1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
80 /* Bit N indicates that an R_ARM_NONE relocation has been output for
81 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
82 emitted only once per section, to save unnecessary bloat. */
83 static unsigned int marked_pr_dependency
= 0;
87 /* Results from operand parsing worker functions. */
91 PARSE_OPERAND_SUCCESS
,
93 PARSE_OPERAND_FAIL_NO_BACKTRACK
94 } parse_operand_result
;
103 /* Types of processor to assemble for. */
105 #if defined __XSCALE__
106 #define CPU_DEFAULT ARM_ARCH_XSCALE
108 #if defined __thumb__
109 #define CPU_DEFAULT ARM_ARCH_V5T
116 # define FPU_DEFAULT FPU_ARCH_FPA
117 # elif defined (TE_NetBSD)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
121 /* Legacy a.out format. */
122 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
124 # elif defined (TE_VXWORKS)
125 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
127 /* For backwards compatibility, default to FPA. */
128 # define FPU_DEFAULT FPU_ARCH_FPA
130 #endif /* ifndef FPU_DEFAULT */
132 #define streq(a, b) (strcmp (a, b) == 0)
134 static arm_feature_set cpu_variant
;
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
149 /* Variables that we set while parsing command-line options. Once all
150 options have been read we re-process these values to set the real
152 static const arm_feature_set
*legacy_cpu
= NULL
;
153 static const arm_feature_set
*legacy_fpu
= NULL
;
155 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
156 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
157 static const arm_feature_set
*march_cpu_opt
= NULL
;
158 static const arm_feature_set
*march_fpu_opt
= NULL
;
159 static const arm_feature_set
*mfpu_opt
= NULL
;
160 static const arm_feature_set
*object_arch
= NULL
;
162 /* Constants for known architecture features. */
163 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
164 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
165 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
166 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
167 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
168 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
169 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
170 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
171 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
174 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
177 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
178 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
179 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
180 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
181 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
182 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
183 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
184 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
185 static const arm_feature_set arm_ext_v4t_5
=
186 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
187 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
188 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
189 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
190 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
191 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
192 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
193 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
194 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
195 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
196 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
197 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
198 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
199 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
200 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
201 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
202 static const arm_feature_set arm_ext_m
=
203 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
205 static const arm_feature_set arm_arch_any
= ARM_ANY
;
206 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
207 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
208 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
210 static const arm_feature_set arm_cext_iwmmxt2
=
211 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
212 static const arm_feature_set arm_cext_iwmmxt
=
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
214 static const arm_feature_set arm_cext_xscale
=
215 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
216 static const arm_feature_set arm_cext_maverick
=
217 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
218 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
219 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
220 static const arm_feature_set fpu_vfp_ext_v1xd
=
221 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
222 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
223 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
224 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
225 static const arm_feature_set fpu_vfp_ext_d32
=
226 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
227 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
228 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
229 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
230 static const arm_feature_set fpu_neon_fp16
= ARM_FEATURE (0, FPU_NEON_FP16
);
232 static int mfloat_abi_opt
= -1;
233 /* Record user cpu selection for object attributes. */
234 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
235 /* Must be long enough to hold any of the names in arm_cpus. */
236 static char selected_cpu_name
[16];
239 static int meabi_flags
= EABI_DEFAULT
;
241 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
244 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
249 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
254 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
255 symbolS
* GOT_symbol
;
258 /* 0: assemble for ARM,
259 1: assemble for Thumb,
260 2: assemble for Thumb even though target CPU does not support thumb
262 static int thumb_mode
= 0;
263 /* A value distinct from the possible values for thumb_mode that we
264 can use to record whether thumb_mode has been copied into the
265 tc_frag_data field of a frag. */
266 #define MODE_RECORDED (1 << 4)
268 /* If unified_syntax is true, we are processing the new unified
269 ARM/Thumb syntax. Important differences from the old ARM mode:
271 - Immediate operands do not require a # prefix.
272 - Conditional affixes always appear at the end of the
273 instruction. (For backward compatibility, those instructions
274 that formerly had them in the middle, continue to accept them
276 - The IT instruction may appear, and if it does is validated
277 against subsequent conditional affixes. It does not generate
280 Important differences from the old Thumb mode:
282 - Immediate operands do not require a # prefix.
283 - Most of the V6T2 instructions are only available in unified mode.
284 - The .N and .W suffixes are recognized and honored (it is an error
285 if they cannot be honored).
286 - All instructions set the flags if and only if they have an 's' affix.
287 - Conditional affixes may be used. They are validated against
288 preceding IT instructions. Unlike ARM mode, you cannot use a
289 conditional affix except in the scope of an IT instruction. */
291 static bfd_boolean unified_syntax
= FALSE
;
306 enum neon_el_type type
;
310 #define NEON_MAX_TYPE_ELS 4
314 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
321 unsigned long instruction
;
325 /* "uncond_value" is set to the value in place of the conditional field in
326 unconditional versions of the instruction, or -1 if nothing is
329 struct neon_type vectype
;
330 /* Set to the opcode if the instruction needs relaxation.
331 Zero if the instruction is not relaxed. */
335 bfd_reloc_code_real_type type
;
344 struct neon_type_el vectype
;
345 unsigned present
: 1; /* Operand present. */
346 unsigned isreg
: 1; /* Operand was a register. */
347 unsigned immisreg
: 1; /* .imm field is a second register. */
348 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
349 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
350 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
351 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
352 instructions. This allows us to disambiguate ARM <-> vector insns. */
353 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
354 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
355 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
356 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
357 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
358 unsigned writeback
: 1; /* Operand has trailing ! */
359 unsigned preind
: 1; /* Preindexed address. */
360 unsigned postind
: 1; /* Postindexed address. */
361 unsigned negative
: 1; /* Index register was negated. */
362 unsigned shifted
: 1; /* Shift applied to operation. */
363 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
367 static struct arm_it inst
;
369 #define NUM_FLOAT_VALS 8
371 const char * fp_const
[] =
373 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
376 /* Number of littlenums required to hold an extended precision number. */
377 #define MAX_LITTLENUMS 6
379 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
389 #define CP_T_X 0x00008000
390 #define CP_T_Y 0x00400000
392 #define CONDS_BIT 0x00100000
393 #define LOAD_BIT 0x00100000
395 #define DOUBLE_LOAD_FLAG 0x00000001
399 const char * template;
403 #define COND_ALWAYS 0xE
407 const char *template;
411 struct asm_barrier_opt
413 const char *template;
417 /* The bit that distinguishes CPSR and SPSR. */
418 #define SPSR_BIT (1 << 22)
420 /* The individual PSR flag bits. */
421 #define PSR_c (1 << 16)
422 #define PSR_x (1 << 17)
423 #define PSR_s (1 << 18)
424 #define PSR_f (1 << 19)
429 bfd_reloc_code_real_type reloc
;
434 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
435 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
440 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
443 /* Bits for DEFINED field in neon_typed_alias. */
444 #define NTA_HASTYPE 1
445 #define NTA_HASINDEX 2
447 struct neon_typed_alias
449 unsigned char defined
;
451 struct neon_type_el eltype
;
454 /* ARM register categories. This includes coprocessor numbers and various
455 architecture extensions' registers. */
481 /* Structure for a hash table entry for a register.
482 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
483 information which states whether a vector type or index is specified (for a
484 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
488 unsigned char number
;
490 unsigned char builtin
;
491 struct neon_typed_alias
*neon
;
494 /* Diagnostics used when we don't get a register of the expected type. */
495 const char *const reg_expected_msgs
[] =
497 N_("ARM register expected"),
498 N_("bad or missing co-processor number"),
499 N_("co-processor register expected"),
500 N_("FPA register expected"),
501 N_("VFP single precision register expected"),
502 N_("VFP/Neon double precision register expected"),
503 N_("Neon quad precision register expected"),
504 N_("VFP single or double precision register expected"),
505 N_("Neon double or quad precision register expected"),
506 N_("VFP single, double or Neon quad precision register expected"),
507 N_("VFP system register expected"),
508 N_("Maverick MVF register expected"),
509 N_("Maverick MVD register expected"),
510 N_("Maverick MVFX register expected"),
511 N_("Maverick MVDX register expected"),
512 N_("Maverick MVAX register expected"),
513 N_("Maverick DSPSC register expected"),
514 N_("iWMMXt data register expected"),
515 N_("iWMMXt control register expected"),
516 N_("iWMMXt scalar register expected"),
517 N_("XScale accumulator register expected"),
520 /* Some well known registers that we refer to directly elsewhere. */
525 /* ARM instructions take 4bytes in the object file, Thumb instructions
531 /* Basic string to match. */
532 const char *template;
534 /* Parameters to instruction. */
535 unsigned char operands
[8];
537 /* Conditional tag - see opcode_lookup. */
538 unsigned int tag
: 4;
540 /* Basic instruction code. */
541 unsigned int avalue
: 28;
543 /* Thumb-format instruction code. */
546 /* Which architecture variant provides this instruction. */
547 const arm_feature_set
*avariant
;
548 const arm_feature_set
*tvariant
;
550 /* Function to call to encode instruction in ARM format. */
551 void (* aencode
) (void);
553 /* Function to call to encode instruction in Thumb format. */
554 void (* tencode
) (void);
557 /* Defines for various bits that we will want to toggle. */
558 #define INST_IMMEDIATE 0x02000000
559 #define OFFSET_REG 0x02000000
560 #define HWOFFSET_IMM 0x00400000
561 #define SHIFT_BY_REG 0x00000010
562 #define PRE_INDEX 0x01000000
563 #define INDEX_UP 0x00800000
564 #define WRITE_BACK 0x00200000
565 #define LDM_TYPE_2_OR_3 0x00400000
566 #define CPSI_MMOD 0x00020000
568 #define LITERAL_MASK 0xf000f000
569 #define OPCODE_MASK 0xfe1fffff
570 #define V4_STR_BIT 0x00000020
572 #define T2_SUBS_PC_LR 0xf3de8f00
574 #define DATA_OP_SHIFT 21
576 #define T2_OPCODE_MASK 0xfe1fffff
577 #define T2_DATA_OP_SHIFT 21
579 /* Codes to distinguish the arithmetic instructions. */
590 #define OPCODE_CMP 10
591 #define OPCODE_CMN 11
592 #define OPCODE_ORR 12
593 #define OPCODE_MOV 13
594 #define OPCODE_BIC 14
595 #define OPCODE_MVN 15
597 #define T2_OPCODE_AND 0
598 #define T2_OPCODE_BIC 1
599 #define T2_OPCODE_ORR 2
600 #define T2_OPCODE_ORN 3
601 #define T2_OPCODE_EOR 4
602 #define T2_OPCODE_ADD 8
603 #define T2_OPCODE_ADC 10
604 #define T2_OPCODE_SBC 11
605 #define T2_OPCODE_SUB 13
606 #define T2_OPCODE_RSB 14
608 #define T_OPCODE_MUL 0x4340
609 #define T_OPCODE_TST 0x4200
610 #define T_OPCODE_CMN 0x42c0
611 #define T_OPCODE_NEG 0x4240
612 #define T_OPCODE_MVN 0x43c0
614 #define T_OPCODE_ADD_R3 0x1800
615 #define T_OPCODE_SUB_R3 0x1a00
616 #define T_OPCODE_ADD_HI 0x4400
617 #define T_OPCODE_ADD_ST 0xb000
618 #define T_OPCODE_SUB_ST 0xb080
619 #define T_OPCODE_ADD_SP 0xa800
620 #define T_OPCODE_ADD_PC 0xa000
621 #define T_OPCODE_ADD_I8 0x3000
622 #define T_OPCODE_SUB_I8 0x3800
623 #define T_OPCODE_ADD_I3 0x1c00
624 #define T_OPCODE_SUB_I3 0x1e00
626 #define T_OPCODE_ASR_R 0x4100
627 #define T_OPCODE_LSL_R 0x4080
628 #define T_OPCODE_LSR_R 0x40c0
629 #define T_OPCODE_ROR_R 0x41c0
630 #define T_OPCODE_ASR_I 0x1000
631 #define T_OPCODE_LSL_I 0x0000
632 #define T_OPCODE_LSR_I 0x0800
634 #define T_OPCODE_MOV_I8 0x2000
635 #define T_OPCODE_CMP_I8 0x2800
636 #define T_OPCODE_CMP_LR 0x4280
637 #define T_OPCODE_MOV_HR 0x4600
638 #define T_OPCODE_CMP_HR 0x4500
640 #define T_OPCODE_LDR_PC 0x4800
641 #define T_OPCODE_LDR_SP 0x9800
642 #define T_OPCODE_STR_SP 0x9000
643 #define T_OPCODE_LDR_IW 0x6800
644 #define T_OPCODE_STR_IW 0x6000
645 #define T_OPCODE_LDR_IH 0x8800
646 #define T_OPCODE_STR_IH 0x8000
647 #define T_OPCODE_LDR_IB 0x7800
648 #define T_OPCODE_STR_IB 0x7000
649 #define T_OPCODE_LDR_RW 0x5800
650 #define T_OPCODE_STR_RW 0x5000
651 #define T_OPCODE_LDR_RH 0x5a00
652 #define T_OPCODE_STR_RH 0x5200
653 #define T_OPCODE_LDR_RB 0x5c00
654 #define T_OPCODE_STR_RB 0x5400
656 #define T_OPCODE_PUSH 0xb400
657 #define T_OPCODE_POP 0xbc00
659 #define T_OPCODE_BRANCH 0xe000
661 #define THUMB_SIZE 2 /* Size of thumb instruction. */
662 #define THUMB_PP_PC_LR 0x0100
663 #define THUMB_LOAD_BIT 0x0800
664 #define THUMB2_LOAD_BIT 0x00100000
666 #define BAD_ARGS _("bad arguments to instruction")
667 #define BAD_SP _("r13 not allowed here")
668 #define BAD_PC _("r15 not allowed here")
669 #define BAD_COND _("instruction cannot be conditional")
670 #define BAD_OVERLAP _("registers may not be the same")
671 #define BAD_HIREG _("lo register required")
672 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
673 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
674 #define BAD_BRANCH _("branch must be last instruction in IT block")
675 #define BAD_NOT_IT _("instruction not allowed in IT block")
676 #define BAD_FPU _("selected FPU does not support instruction")
678 static struct hash_control
*arm_ops_hsh
;
679 static struct hash_control
*arm_cond_hsh
;
680 static struct hash_control
*arm_shift_hsh
;
681 static struct hash_control
*arm_psr_hsh
;
682 static struct hash_control
*arm_v7m_psr_hsh
;
683 static struct hash_control
*arm_reg_hsh
;
684 static struct hash_control
*arm_reloc_hsh
;
685 static struct hash_control
*arm_barrier_opt_hsh
;
687 /* Stuff needed to resolve the label ambiguity
696 symbolS
* last_label_seen
;
697 static int label_is_thumb_function_name
= FALSE
;
699 /* Literal pool structure. Held on a per-section
700 and per-sub-section basis. */
702 #define MAX_LITERAL_POOL_SIZE 1024
703 typedef struct literal_pool
705 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
706 unsigned int next_free_entry
;
711 struct literal_pool
* next
;
714 /* Pointer to a linked list of literal pools. */
715 literal_pool
* list_of_pools
= NULL
;
717 /* State variables for IT block handling. */
718 static bfd_boolean current_it_mask
= 0;
719 static int current_cc
;
723 /* This array holds the chars that always start a comment. If the
724 pre-processor is disabled, these aren't very useful. */
725 const char comment_chars
[] = "@";
727 /* This array holds the chars that only start a comment at the beginning of
728 a line. If the line seems to have the form '# 123 filename'
729 .line and .file directives will appear in the pre-processed output. */
730 /* Note that input_file.c hand checks for '#' at the beginning of the
731 first line of the input file. This is because the compiler outputs
732 #NO_APP at the beginning of its output. */
733 /* Also note that comments like this one will always work. */
734 const char line_comment_chars
[] = "#";
736 const char line_separator_chars
[] = ";";
738 /* Chars that can be used to separate mant
739 from exp in floating point numbers. */
740 const char EXP_CHARS
[] = "eE";
742 /* Chars that mean this number is a floating point constant. */
746 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
748 /* Prefix characters that indicate the start of an immediate
750 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
752 /* Separator character handling. */
754 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
757 skip_past_char (char ** str
, char c
)
767 #define skip_past_comma(str) skip_past_char (str, ',')
769 /* Arithmetic expressions (possibly involving symbols). */
771 /* Return TRUE if anything in the expression is a bignum. */
774 walk_no_bignums (symbolS
* sp
)
776 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
779 if (symbol_get_value_expression (sp
)->X_add_symbol
)
781 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
782 || (symbol_get_value_expression (sp
)->X_op_symbol
783 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
789 static int in_my_get_expression
= 0;
791 /* Third argument to my_get_expression. */
792 #define GE_NO_PREFIX 0
793 #define GE_IMM_PREFIX 1
794 #define GE_OPT_PREFIX 2
795 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
796 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
797 #define GE_OPT_PREFIX_BIG 3
800 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
805 /* In unified syntax, all prefixes are optional. */
807 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
812 case GE_NO_PREFIX
: break;
814 if (!is_immediate_prefix (**str
))
816 inst
.error
= _("immediate expression requires a # prefix");
822 case GE_OPT_PREFIX_BIG
:
823 if (is_immediate_prefix (**str
))
829 memset (ep
, 0, sizeof (expressionS
));
831 save_in
= input_line_pointer
;
832 input_line_pointer
= *str
;
833 in_my_get_expression
= 1;
834 seg
= expression (ep
);
835 in_my_get_expression
= 0;
837 if (ep
->X_op
== O_illegal
)
839 /* We found a bad expression in md_operand(). */
840 *str
= input_line_pointer
;
841 input_line_pointer
= save_in
;
842 if (inst
.error
== NULL
)
843 inst
.error
= _("bad expression");
848 if (seg
!= absolute_section
849 && seg
!= text_section
850 && seg
!= data_section
851 && seg
!= bss_section
852 && seg
!= undefined_section
)
854 inst
.error
= _("bad segment");
855 *str
= input_line_pointer
;
856 input_line_pointer
= save_in
;
861 /* Get rid of any bignums now, so that we don't generate an error for which
862 we can't establish a line number later on. Big numbers are never valid
863 in instructions, which is where this routine is always called. */
864 if (prefix_mode
!= GE_OPT_PREFIX_BIG
865 && (ep
->X_op
== O_big
867 && (walk_no_bignums (ep
->X_add_symbol
)
869 && walk_no_bignums (ep
->X_op_symbol
))))))
871 inst
.error
= _("invalid constant");
872 *str
= input_line_pointer
;
873 input_line_pointer
= save_in
;
877 *str
= input_line_pointer
;
878 input_line_pointer
= save_in
;
882 /* Turn a string in input_line_pointer into a floating point constant
883 of type TYPE, and store the appropriate bytes in *LITP. The number
884 of LITTLENUMS emitted is stored in *SIZEP. An error message is
885 returned, or NULL on OK.
887 Note that fp constants aren't represent in the normal way on the ARM.
888 In big endian mode, things are as expected. However, in little endian
889 mode fp constants are big-endian word-wise, and little-endian byte-wise
890 within the words. For example, (double) 1.1 in big endian mode is
891 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
892 the byte sequence 99 99 f1 3f 9a 99 99 99.
894 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
897 md_atof (int type
, char * litP
, int * sizeP
)
900 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
932 return _("Unrecognized or unsupported floating point constant");
935 t
= atof_ieee (input_line_pointer
, type
, words
);
937 input_line_pointer
= t
;
938 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
940 if (target_big_endian
)
942 for (i
= 0; i
< prec
; i
++)
944 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
945 litP
+= sizeof (LITTLENUM_TYPE
);
950 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
951 for (i
= prec
- 1; i
>= 0; i
--)
953 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
954 litP
+= sizeof (LITTLENUM_TYPE
);
957 /* For a 4 byte float the order of elements in `words' is 1 0.
958 For an 8 byte float the order is 1 0 3 2. */
959 for (i
= 0; i
< prec
; i
+= 2)
961 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
962 sizeof (LITTLENUM_TYPE
));
963 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
964 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
965 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
972 /* We handle all bad expressions here, so that we can report the faulty
973 instruction in the error message. */
975 md_operand (expressionS
* expr
)
977 if (in_my_get_expression
)
978 expr
->X_op
= O_illegal
;
981 /* Immediate values. */
983 /* Generic immediate-value read function for use in directives.
984 Accepts anything that 'expression' can fold to a constant.
985 *val receives the number. */
988 immediate_for_directive (int *val
)
991 exp
.X_op
= O_illegal
;
993 if (is_immediate_prefix (*input_line_pointer
))
995 input_line_pointer
++;
999 if (exp
.X_op
!= O_constant
)
1001 as_bad (_("expected #constant"));
1002 ignore_rest_of_line ();
1005 *val
= exp
.X_add_number
;
1010 /* Register parsing. */
1012 /* Generic register parser. CCP points to what should be the
1013 beginning of a register name. If it is indeed a valid register
1014 name, advance CCP over it and return the reg_entry structure;
1015 otherwise return NULL. Does not issue diagnostics. */
1017 static struct reg_entry
*
1018 arm_reg_parse_multi (char **ccp
)
1022 struct reg_entry
*reg
;
1024 #ifdef REGISTER_PREFIX
1025 if (*start
!= REGISTER_PREFIX
)
1029 #ifdef OPTIONAL_REGISTER_PREFIX
1030 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1035 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1040 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1042 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1052 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1053 enum arm_reg_type type
)
1055 /* Alternative syntaxes are accepted for a few register classes. */
1062 /* Generic coprocessor register names are allowed for these. */
1063 if (reg
&& reg
->type
== REG_TYPE_CN
)
1068 /* For backward compatibility, a bare number is valid here. */
1070 unsigned long processor
= strtoul (start
, ccp
, 10);
1071 if (*ccp
!= start
&& processor
<= 15)
1075 case REG_TYPE_MMXWC
:
1076 /* WC includes WCG. ??? I'm not sure this is true for all
1077 instructions that take WC registers. */
1078 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1089 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1090 return value is the register number or FAIL. */
1093 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1096 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1099 /* Do not allow a scalar (reg+index) to parse as a register. */
1100 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1103 if (reg
&& reg
->type
== type
)
1106 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1113 /* Parse a Neon type specifier. *STR should point at the leading '.'
1114 character. Does no verification at this stage that the type fits the opcode
1121 Can all be legally parsed by this function.
1123 Fills in neon_type struct pointer with parsed information, and updates STR
1124 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1125 type, FAIL if not. */
1128 parse_neon_type (struct neon_type
*type
, char **str
)
1135 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1137 enum neon_el_type thistype
= NT_untyped
;
1138 unsigned thissize
= -1u;
1145 /* Just a size without an explicit type. */
1149 switch (TOLOWER (*ptr
))
1151 case 'i': thistype
= NT_integer
; break;
1152 case 'f': thistype
= NT_float
; break;
1153 case 'p': thistype
= NT_poly
; break;
1154 case 's': thistype
= NT_signed
; break;
1155 case 'u': thistype
= NT_unsigned
; break;
1157 thistype
= NT_float
;
1162 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1168 /* .f is an abbreviation for .f32. */
1169 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1174 thissize
= strtoul (ptr
, &ptr
, 10);
1176 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1179 as_bad (_("bad size %d in type specifier"), thissize
);
1187 type
->el
[type
->elems
].type
= thistype
;
1188 type
->el
[type
->elems
].size
= thissize
;
1193 /* Empty/missing type is not a successful parse. */
1194 if (type
->elems
== 0)
1202 /* Errors may be set multiple times during parsing or bit encoding
1203 (particularly in the Neon bits), but usually the earliest error which is set
1204 will be the most meaningful. Avoid overwriting it with later (cascading)
1205 errors by calling this function. */
1208 first_error (const char *err
)
1214 /* Parse a single type, e.g. ".s32", leading period included. */
1216 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1219 struct neon_type optype
;
1223 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1225 if (optype
.elems
== 1)
1226 *vectype
= optype
.el
[0];
1229 first_error (_("only one type should be specified for operand"));
1235 first_error (_("vector type expected"));
1247 /* Special meanings for indices (which have a range of 0-7), which will fit into
1250 #define NEON_ALL_LANES 15
1251 #define NEON_INTERLEAVE_LANES 14
1253 /* Parse either a register or a scalar, with an optional type. Return the
1254 register number, and optionally fill in the actual type of the register
1255 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1256 type/index information in *TYPEINFO. */
1259 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1260 enum arm_reg_type
*rtype
,
1261 struct neon_typed_alias
*typeinfo
)
1264 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1265 struct neon_typed_alias atype
;
1266 struct neon_type_el parsetype
;
1270 atype
.eltype
.type
= NT_invtype
;
1271 atype
.eltype
.size
= -1;
1273 /* Try alternate syntax for some types of register. Note these are mutually
1274 exclusive with the Neon syntax extensions. */
1277 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1285 /* Undo polymorphism when a set of register types may be accepted. */
1286 if ((type
== REG_TYPE_NDQ
1287 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1288 || (type
== REG_TYPE_VFSD
1289 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1290 || (type
== REG_TYPE_NSDQ
1291 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1292 || reg
->type
== REG_TYPE_NQ
))
1293 || (type
== REG_TYPE_MMXWC
1294 && (reg
->type
== REG_TYPE_MMXWCG
)))
1297 if (type
!= reg
->type
)
1303 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1305 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1307 first_error (_("can't redefine type for operand"));
1310 atype
.defined
|= NTA_HASTYPE
;
1311 atype
.eltype
= parsetype
;
1314 if (skip_past_char (&str
, '[') == SUCCESS
)
1316 if (type
!= REG_TYPE_VFD
)
1318 first_error (_("only D registers may be indexed"));
1322 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1324 first_error (_("can't change index for operand"));
1328 atype
.defined
|= NTA_HASINDEX
;
1330 if (skip_past_char (&str
, ']') == SUCCESS
)
1331 atype
.index
= NEON_ALL_LANES
;
1336 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1338 if (exp
.X_op
!= O_constant
)
1340 first_error (_("constant expression required"));
1344 if (skip_past_char (&str
, ']') == FAIL
)
1347 atype
.index
= exp
.X_add_number
;
1362 /* Like arm_reg_parse, but allow allow the following extra features:
1363 - If RTYPE is non-zero, return the (possibly restricted) type of the
1364 register (e.g. Neon double or quad reg when either has been requested).
1365 - If this is a Neon vector type with additional type information, fill
1366 in the struct pointed to by VECTYPE (if non-NULL).
1367 This function will fault on encountering a scalar. */
1370 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1371 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1373 struct neon_typed_alias atype
;
1375 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1380 /* Do not allow a scalar (reg+index) to parse as a register. */
1381 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1383 first_error (_("register operand expected, but got scalar"));
1388 *vectype
= atype
.eltype
;
1395 #define NEON_SCALAR_REG(X) ((X) >> 4)
1396 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1398 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1399 have enough information to be able to do a good job bounds-checking. So, we
1400 just do easy checks here, and do further checks later. */
1403 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1407 struct neon_typed_alias atype
;
1409 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1411 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1414 if (atype
.index
== NEON_ALL_LANES
)
1416 first_error (_("scalar must have an index"));
1419 else if (atype
.index
>= 64 / elsize
)
1421 first_error (_("scalar index out of range"));
1426 *type
= atype
.eltype
;
1430 return reg
* 16 + atype
.index
;
1433 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1435 parse_reg_list (char ** strp
)
1437 char * str
= * strp
;
1441 /* We come back here if we get ranges concatenated by '+' or '|'. */
1456 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1458 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1468 first_error (_("bad range in register list"));
1472 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1474 if (range
& (1 << i
))
1476 (_("Warning: duplicated register (r%d) in register list"),
1484 if (range
& (1 << reg
))
1485 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1487 else if (reg
<= cur_reg
)
1488 as_tsktsk (_("Warning: register range not in ascending order"));
1493 while (skip_past_comma (&str
) != FAIL
1494 || (in_range
= 1, *str
++ == '-'));
1499 first_error (_("missing `}'"));
1507 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1510 if (expr
.X_op
== O_constant
)
1512 if (expr
.X_add_number
1513 != (expr
.X_add_number
& 0x0000ffff))
1515 inst
.error
= _("invalid register mask");
1519 if ((range
& expr
.X_add_number
) != 0)
1521 int regno
= range
& expr
.X_add_number
;
1524 regno
= (1 << regno
) - 1;
1526 (_("Warning: duplicated register (r%d) in register list"),
1530 range
|= expr
.X_add_number
;
1534 if (inst
.reloc
.type
!= 0)
1536 inst
.error
= _("expression too complex");
1540 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1541 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1542 inst
.reloc
.pc_rel
= 0;
1546 if (*str
== '|' || *str
== '+')
1552 while (another_range
);
1558 /* Types of registers in a list. */
1567 /* Parse a VFP register list. If the string is invalid return FAIL.
1568 Otherwise return the number of registers, and set PBASE to the first
1569 register. Parses registers of type ETYPE.
1570 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1571 - Q registers can be used to specify pairs of D registers
1572 - { } can be omitted from around a singleton register list
1573 FIXME: This is not implemented, as it would require backtracking in
1576 This could be done (the meaning isn't really ambiguous), but doesn't
1577 fit in well with the current parsing framework.
1578 - 32 D registers may be used (also true for VFPv3).
1579 FIXME: Types are ignored in these register lists, which is probably a
1583 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1588 enum arm_reg_type regtype
= 0;
1592 unsigned long mask
= 0;
1597 inst
.error
= _("expecting {");
1606 regtype
= REG_TYPE_VFS
;
1611 regtype
= REG_TYPE_VFD
;
1614 case REGLIST_NEON_D
:
1615 regtype
= REG_TYPE_NDQ
;
1619 if (etype
!= REGLIST_VFP_S
)
1621 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1622 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1626 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1629 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1636 base_reg
= max_regs
;
1640 int setmask
= 1, addregs
= 1;
1642 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1644 if (new_base
== FAIL
)
1646 first_error (_(reg_expected_msgs
[regtype
]));
1650 if (new_base
>= max_regs
)
1652 first_error (_("register out of range in list"));
1656 /* Note: a value of 2 * n is returned for the register Q<n>. */
1657 if (regtype
== REG_TYPE_NQ
)
1663 if (new_base
< base_reg
)
1664 base_reg
= new_base
;
1666 if (mask
& (setmask
<< new_base
))
1668 first_error (_("invalid register list"));
1672 if ((mask
>> new_base
) != 0 && ! warned
)
1674 as_tsktsk (_("register list not in ascending order"));
1678 mask
|= setmask
<< new_base
;
1681 if (*str
== '-') /* We have the start of a range expression */
1687 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1690 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1694 if (high_range
>= max_regs
)
1696 first_error (_("register out of range in list"));
1700 if (regtype
== REG_TYPE_NQ
)
1701 high_range
= high_range
+ 1;
1703 if (high_range
<= new_base
)
1705 inst
.error
= _("register range not in ascending order");
1709 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1711 if (mask
& (setmask
<< new_base
))
1713 inst
.error
= _("invalid register list");
1717 mask
|= setmask
<< new_base
;
1722 while (skip_past_comma (&str
) != FAIL
);
1726 /* Sanity check -- should have raised a parse error above. */
1727 if (count
== 0 || count
> max_regs
)
1732 /* Final test -- the registers must be consecutive. */
1734 for (i
= 0; i
< count
; i
++)
1736 if ((mask
& (1u << i
)) == 0)
1738 inst
.error
= _("non-contiguous register range");
1748 /* True if two alias types are the same. */
1751 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1759 if (a
->defined
!= b
->defined
)
1762 if ((a
->defined
& NTA_HASTYPE
) != 0
1763 && (a
->eltype
.type
!= b
->eltype
.type
1764 || a
->eltype
.size
!= b
->eltype
.size
))
1767 if ((a
->defined
& NTA_HASINDEX
) != 0
1768 && (a
->index
!= b
->index
))
1774 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1775 The base register is put in *PBASE.
1776 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1778 The register stride (minus one) is put in bit 4 of the return value.
1779 Bits [6:5] encode the list length (minus one).
1780 The type of the list elements is put in *ELTYPE, if non-NULL. */
1782 #define NEON_LANE(X) ((X) & 0xf)
1783 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1784 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1787 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1788 struct neon_type_el
*eltype
)
1795 int leading_brace
= 0;
1796 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1798 const char *const incr_error
= "register stride must be 1 or 2";
1799 const char *const type_error
= "mismatched element/structure types in list";
1800 struct neon_typed_alias firsttype
;
1802 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1807 struct neon_typed_alias atype
;
1808 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1812 first_error (_(reg_expected_msgs
[rtype
]));
1819 if (rtype
== REG_TYPE_NQ
)
1826 else if (reg_incr
== -1)
1828 reg_incr
= getreg
- base_reg
;
1829 if (reg_incr
< 1 || reg_incr
> 2)
1831 first_error (_(incr_error
));
1835 else if (getreg
!= base_reg
+ reg_incr
* count
)
1837 first_error (_(incr_error
));
1841 if (!neon_alias_types_same (&atype
, &firsttype
))
1843 first_error (_(type_error
));
1847 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1851 struct neon_typed_alias htype
;
1852 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1854 lane
= NEON_INTERLEAVE_LANES
;
1855 else if (lane
!= NEON_INTERLEAVE_LANES
)
1857 first_error (_(type_error
));
1862 else if (reg_incr
!= 1)
1864 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1868 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1871 first_error (_(reg_expected_msgs
[rtype
]));
1874 if (!neon_alias_types_same (&htype
, &firsttype
))
1876 first_error (_(type_error
));
1879 count
+= hireg
+ dregs
- getreg
;
1883 /* If we're using Q registers, we can't use [] or [n] syntax. */
1884 if (rtype
== REG_TYPE_NQ
)
1890 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1894 else if (lane
!= atype
.index
)
1896 first_error (_(type_error
));
1900 else if (lane
== -1)
1901 lane
= NEON_INTERLEAVE_LANES
;
1902 else if (lane
!= NEON_INTERLEAVE_LANES
)
1904 first_error (_(type_error
));
1909 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1911 /* No lane set by [x]. We must be interleaving structures. */
1913 lane
= NEON_INTERLEAVE_LANES
;
1916 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1917 || (count
> 1 && reg_incr
== -1))
1919 first_error (_("error parsing element/structure list"));
1923 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
1925 first_error (_("expected }"));
1933 *eltype
= firsttype
.eltype
;
1938 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
1941 /* Parse an explicit relocation suffix on an expression. This is
1942 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1943 arm_reloc_hsh contains no entries, so this function can only
1944 succeed if there is no () after the word. Returns -1 on error,
1945 BFD_RELOC_UNUSED if there wasn't any suffix. */
1947 parse_reloc (char **str
)
1949 struct reloc_entry
*r
;
1953 return BFD_RELOC_UNUSED
;
1958 while (*q
&& *q
!= ')' && *q
!= ',')
1963 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1970 /* Directives: register aliases. */
1972 static struct reg_entry
*
1973 insert_reg_alias (char *str
, int number
, int type
)
1975 struct reg_entry
*new;
1978 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1981 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1983 /* Only warn about a redefinition if it's not defined as the
1985 else if (new->number
!= number
|| new->type
!= type
)
1986 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1991 name
= xstrdup (str
);
1992 new = xmalloc (sizeof (struct reg_entry
));
1995 new->number
= number
;
1997 new->builtin
= FALSE
;
2000 if (hash_insert (arm_reg_hsh
, name
, (void *) new))
2007 insert_neon_reg_alias (char *str
, int number
, int type
,
2008 struct neon_typed_alias
*atype
)
2010 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2014 first_error (_("attempt to redefine typed alias"));
2020 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
2021 *reg
->neon
= *atype
;
2025 /* Look for the .req directive. This is of the form:
2027 new_register_name .req existing_register_name
2029 If we find one, or if it looks sufficiently like one that we want to
2030 handle any error here, return TRUE. Otherwise return FALSE. */
2033 create_register_alias (char * newname
, char *p
)
2035 struct reg_entry
*old
;
2036 char *oldname
, *nbuf
;
2039 /* The input scrubber ensures that whitespace after the mnemonic is
2040 collapsed to single spaces. */
2042 if (strncmp (oldname
, " .req ", 6) != 0)
2046 if (*oldname
== '\0')
2049 old
= hash_find (arm_reg_hsh
, oldname
);
2052 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2056 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2057 the desired alias name, and p points to its end. If not, then
2058 the desired alias name is in the global original_case_string. */
2059 #ifdef TC_CASE_SENSITIVE
2062 newname
= original_case_string
;
2063 nlen
= strlen (newname
);
2066 nbuf
= alloca (nlen
+ 1);
2067 memcpy (nbuf
, newname
, nlen
);
2070 /* Create aliases under the new name as stated; an all-lowercase
2071 version of the new name; and an all-uppercase version of the new
2073 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2075 for (p
= nbuf
; *p
; p
++)
2078 if (strncmp (nbuf
, newname
, nlen
))
2080 /* If this attempt to create an additional alias fails, do not bother
2081 trying to create the all-lower case alias. We will fail and issue
2082 a second, duplicate error message. This situation arises when the
2083 programmer does something like:
2086 The second .req creates the "Foo" alias but then fails to create
2087 the artificial FOO alias because it has already been created by the
2089 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2093 for (p
= nbuf
; *p
; p
++)
2096 if (strncmp (nbuf
, newname
, nlen
))
2097 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2103 /* Create a Neon typed/indexed register alias using directives, e.g.:
2108 These typed registers can be used instead of the types specified after the
2109 Neon mnemonic, so long as all operands given have types. Types can also be
2110 specified directly, e.g.:
2111 vadd d0.s32, d1.s32, d2.s32 */
2114 create_neon_reg_alias (char *newname
, char *p
)
2116 enum arm_reg_type basetype
;
2117 struct reg_entry
*basereg
;
2118 struct reg_entry mybasereg
;
2119 struct neon_type ntype
;
2120 struct neon_typed_alias typeinfo
;
2121 char *namebuf
, *nameend
;
2124 typeinfo
.defined
= 0;
2125 typeinfo
.eltype
.type
= NT_invtype
;
2126 typeinfo
.eltype
.size
= -1;
2127 typeinfo
.index
= -1;
2131 if (strncmp (p
, " .dn ", 5) == 0)
2132 basetype
= REG_TYPE_VFD
;
2133 else if (strncmp (p
, " .qn ", 5) == 0)
2134 basetype
= REG_TYPE_NQ
;
2143 basereg
= arm_reg_parse_multi (&p
);
2145 if (basereg
&& basereg
->type
!= basetype
)
2147 as_bad (_("bad type for register"));
2151 if (basereg
== NULL
)
2154 /* Try parsing as an integer. */
2155 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2156 if (exp
.X_op
!= O_constant
)
2158 as_bad (_("expression must be constant"));
2161 basereg
= &mybasereg
;
2162 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2168 typeinfo
= *basereg
->neon
;
2170 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2172 /* We got a type. */
2173 if (typeinfo
.defined
& NTA_HASTYPE
)
2175 as_bad (_("can't redefine the type of a register alias"));
2179 typeinfo
.defined
|= NTA_HASTYPE
;
2180 if (ntype
.elems
!= 1)
2182 as_bad (_("you must specify a single type only"));
2185 typeinfo
.eltype
= ntype
.el
[0];
2188 if (skip_past_char (&p
, '[') == SUCCESS
)
2191 /* We got a scalar index. */
2193 if (typeinfo
.defined
& NTA_HASINDEX
)
2195 as_bad (_("can't redefine the index of a scalar alias"));
2199 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2201 if (exp
.X_op
!= O_constant
)
2203 as_bad (_("scalar index must be constant"));
2207 typeinfo
.defined
|= NTA_HASINDEX
;
2208 typeinfo
.index
= exp
.X_add_number
;
2210 if (skip_past_char (&p
, ']') == FAIL
)
2212 as_bad (_("expecting ]"));
2217 namelen
= nameend
- newname
;
2218 namebuf
= alloca (namelen
+ 1);
2219 strncpy (namebuf
, newname
, namelen
);
2220 namebuf
[namelen
] = '\0';
2222 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2223 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2225 /* Insert name in all uppercase. */
2226 for (p
= namebuf
; *p
; p
++)
2229 if (strncmp (namebuf
, newname
, namelen
))
2230 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2231 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2233 /* Insert name in all lowercase. */
2234 for (p
= namebuf
; *p
; p
++)
2237 if (strncmp (namebuf
, newname
, namelen
))
2238 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2239 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2244 /* Should never be called, as .req goes between the alias and the
2245 register name, not at the beginning of the line. */
2247 s_req (int a ATTRIBUTE_UNUSED
)
2249 as_bad (_("invalid syntax for .req directive"));
2253 s_dn (int a ATTRIBUTE_UNUSED
)
2255 as_bad (_("invalid syntax for .dn directive"));
2259 s_qn (int a ATTRIBUTE_UNUSED
)
2261 as_bad (_("invalid syntax for .qn directive"));
2264 /* The .unreq directive deletes an alias which was previously defined
2265 by .req. For example:
2271 s_unreq (int a ATTRIBUTE_UNUSED
)
2276 name
= input_line_pointer
;
2278 while (*input_line_pointer
!= 0
2279 && *input_line_pointer
!= ' '
2280 && *input_line_pointer
!= '\n')
2281 ++input_line_pointer
;
2283 saved_char
= *input_line_pointer
;
2284 *input_line_pointer
= 0;
2287 as_bad (_("invalid syntax for .unreq directive"));
2290 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2293 as_bad (_("unknown register alias '%s'"), name
);
2294 else if (reg
->builtin
)
2295 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2302 hash_delete (arm_reg_hsh
, name
, FALSE
);
2303 free ((char *) reg
->name
);
2308 /* Also locate the all upper case and all lower case versions.
2309 Do not complain if we cannot find one or the other as it
2310 was probably deleted above. */
2312 nbuf
= strdup (name
);
2313 for (p
= nbuf
; *p
; p
++)
2315 reg
= hash_find (arm_reg_hsh
, nbuf
);
2318 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2319 free ((char *) reg
->name
);
2325 for (p
= nbuf
; *p
; p
++)
2327 reg
= hash_find (arm_reg_hsh
, nbuf
);
2330 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2331 free ((char *) reg
->name
);
2341 *input_line_pointer
= saved_char
;
2342 demand_empty_rest_of_line ();
2345 /* Directives: Instruction set selection. */
2348 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2349 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2350 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2351 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2353 static enum mstate mapstate
= MAP_UNDEFINED
;
2356 mapping_state (enum mstate state
)
2359 const char * symname
;
2362 if (mapstate
== state
)
2363 /* The mapping symbol has already been emitted.
2364 There is nothing else to do. */
2373 type
= BSF_NO_FLAGS
;
2377 type
= BSF_NO_FLAGS
;
2381 type
= BSF_NO_FLAGS
;
2389 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2391 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
2392 symbol_table_insert (symbolP
);
2393 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2398 THUMB_SET_FUNC (symbolP
, 0);
2399 ARM_SET_THUMB (symbolP
, 0);
2400 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2404 THUMB_SET_FUNC (symbolP
, 1);
2405 ARM_SET_THUMB (symbolP
, 1);
2406 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2415 #define mapping_state(x) /* nothing */
2418 /* Find the real, Thumb encoded start of a Thumb function. */
2422 find_real_start (symbolS
* symbolP
)
2425 const char * name
= S_GET_NAME (symbolP
);
2426 symbolS
* new_target
;
2428 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2429 #define STUB_NAME ".real_start_of"
2434 /* The compiler may generate BL instructions to local labels because
2435 it needs to perform a branch to a far away location. These labels
2436 do not have a corresponding ".real_start_of" label. We check
2437 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2438 the ".real_start_of" convention for nonlocal branches. */
2439 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2442 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2443 new_target
= symbol_find (real_start
);
2445 if (new_target
== NULL
)
2447 as_warn (_("Failed to find real start of function: %s\n"), name
);
2448 new_target
= symbolP
;
2456 opcode_select (int width
)
2463 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2464 as_bad (_("selected processor does not support THUMB opcodes"));
2467 /* No need to force the alignment, since we will have been
2468 coming from ARM mode, which is word-aligned. */
2469 record_alignment (now_seg
, 1);
2471 mapping_state (MAP_THUMB
);
2477 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2478 as_bad (_("selected processor does not support ARM opcodes"));
2483 frag_align (2, 0, 0);
2485 record_alignment (now_seg
, 1);
2487 mapping_state (MAP_ARM
);
2491 as_bad (_("invalid instruction size selected (%d)"), width
);
2496 s_arm (int ignore ATTRIBUTE_UNUSED
)
2499 demand_empty_rest_of_line ();
2503 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2506 demand_empty_rest_of_line ();
2510 s_code (int unused ATTRIBUTE_UNUSED
)
2514 temp
= get_absolute_expression ();
2519 opcode_select (temp
);
2523 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2528 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2530 /* If we are not already in thumb mode go into it, EVEN if
2531 the target processor does not support thumb instructions.
2532 This is used by gcc/config/arm/lib1funcs.asm for example
2533 to compile interworking support functions even if the
2534 target processor should not support interworking. */
2538 record_alignment (now_seg
, 1);
2541 demand_empty_rest_of_line ();
2545 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2549 /* The following label is the name/address of the start of a Thumb function.
2550 We need to know this for the interworking support. */
2551 label_is_thumb_function_name
= TRUE
;
2554 /* Perform a .set directive, but also mark the alias as
2555 being a thumb function. */
2558 s_thumb_set (int equiv
)
2560 /* XXX the following is a duplicate of the code for s_set() in read.c
2561 We cannot just call that code as we need to get at the symbol that
2568 /* Especial apologies for the random logic:
2569 This just grew, and could be parsed much more simply!
2571 name
= input_line_pointer
;
2572 delim
= get_symbol_end ();
2573 end_name
= input_line_pointer
;
2576 if (*input_line_pointer
!= ',')
2579 as_bad (_("expected comma after name \"%s\""), name
);
2581 ignore_rest_of_line ();
2585 input_line_pointer
++;
2588 if (name
[0] == '.' && name
[1] == '\0')
2590 /* XXX - this should not happen to .thumb_set. */
2594 if ((symbolP
= symbol_find (name
)) == NULL
2595 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2598 /* When doing symbol listings, play games with dummy fragments living
2599 outside the normal fragment chain to record the file and line info
2601 if (listing
& LISTING_SYMBOLS
)
2603 extern struct list_info_struct
* listing_tail
;
2604 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2606 memset (dummy_frag
, 0, sizeof (fragS
));
2607 dummy_frag
->fr_type
= rs_fill
;
2608 dummy_frag
->line
= listing_tail
;
2609 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2610 dummy_frag
->fr_symbol
= symbolP
;
2614 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2617 /* "set" symbols are local unless otherwise specified. */
2618 SF_SET_LOCAL (symbolP
);
2619 #endif /* OBJ_COFF */
2620 } /* Make a new symbol. */
2622 symbol_table_insert (symbolP
);
2627 && S_IS_DEFINED (symbolP
)
2628 && S_GET_SEGMENT (symbolP
) != reg_section
)
2629 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2631 pseudo_set (symbolP
);
2633 demand_empty_rest_of_line ();
2635 /* XXX Now we come to the Thumb specific bit of code. */
2637 THUMB_SET_FUNC (symbolP
, 1);
2638 ARM_SET_THUMB (symbolP
, 1);
2639 #if defined OBJ_ELF || defined OBJ_COFF
2640 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2644 /* Directives: Mode selection. */
2646 /* .syntax [unified|divided] - choose the new unified syntax
2647 (same for Arm and Thumb encoding, modulo slight differences in what
2648 can be represented) or the old divergent syntax for each mode. */
2650 s_syntax (int unused ATTRIBUTE_UNUSED
)
2654 name
= input_line_pointer
;
2655 delim
= get_symbol_end ();
2657 if (!strcasecmp (name
, "unified"))
2658 unified_syntax
= TRUE
;
2659 else if (!strcasecmp (name
, "divided"))
2660 unified_syntax
= FALSE
;
2663 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2666 *input_line_pointer
= delim
;
2667 demand_empty_rest_of_line ();
2670 /* Directives: sectioning and alignment. */
2672 /* Same as s_align_ptwo but align 0 => align 2. */
2675 s_align (int unused ATTRIBUTE_UNUSED
)
2680 long max_alignment
= 15;
2682 temp
= get_absolute_expression ();
2683 if (temp
> max_alignment
)
2684 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2687 as_bad (_("alignment negative. 0 assumed."));
2691 if (*input_line_pointer
== ',')
2693 input_line_pointer
++;
2694 temp_fill
= get_absolute_expression ();
2706 /* Only make a frag if we HAVE to. */
2707 if (temp
&& !need_pass_2
)
2709 if (!fill_p
&& subseg_text_p (now_seg
))
2710 frag_align_code (temp
, 0);
2712 frag_align (temp
, (int) temp_fill
, 0);
2714 demand_empty_rest_of_line ();
2716 record_alignment (now_seg
, temp
);
2720 s_bss (int ignore ATTRIBUTE_UNUSED
)
2722 /* We don't support putting frags in the BSS segment, we fake it by
2723 marking in_bss, then looking at s_skip for clues. */
2724 subseg_set (bss_section
, 0);
2725 demand_empty_rest_of_line ();
2726 mapping_state (MAP_DATA
);
2730 s_even (int ignore ATTRIBUTE_UNUSED
)
2732 /* Never make frag if expect extra pass. */
2734 frag_align (1, 0, 0);
2736 record_alignment (now_seg
, 1);
2738 demand_empty_rest_of_line ();
2741 /* Directives: Literal pools. */
2743 static literal_pool
*
2744 find_literal_pool (void)
2746 literal_pool
* pool
;
2748 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2750 if (pool
->section
== now_seg
2751 && pool
->sub_section
== now_subseg
)
2758 static literal_pool
*
2759 find_or_make_literal_pool (void)
2761 /* Next literal pool ID number. */
2762 static unsigned int latest_pool_num
= 1;
2763 literal_pool
* pool
;
2765 pool
= find_literal_pool ();
2769 /* Create a new pool. */
2770 pool
= xmalloc (sizeof (* pool
));
2774 pool
->next_free_entry
= 0;
2775 pool
->section
= now_seg
;
2776 pool
->sub_section
= now_subseg
;
2777 pool
->next
= list_of_pools
;
2778 pool
->symbol
= NULL
;
2780 /* Add it to the list. */
2781 list_of_pools
= pool
;
2784 /* New pools, and emptied pools, will have a NULL symbol. */
2785 if (pool
->symbol
== NULL
)
2787 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2788 (valueT
) 0, &zero_address_frag
);
2789 pool
->id
= latest_pool_num
++;
2796 /* Add the literal in the global 'inst'
2797 structure to the relevant literal pool. */
2800 add_to_lit_pool (void)
2802 literal_pool
* pool
;
2805 pool
= find_or_make_literal_pool ();
2807 /* Check if this literal value is already in the pool. */
2808 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2810 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2811 && (inst
.reloc
.exp
.X_op
== O_constant
)
2812 && (pool
->literals
[entry
].X_add_number
2813 == inst
.reloc
.exp
.X_add_number
)
2814 && (pool
->literals
[entry
].X_unsigned
2815 == inst
.reloc
.exp
.X_unsigned
))
2818 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2819 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2820 && (pool
->literals
[entry
].X_add_number
2821 == inst
.reloc
.exp
.X_add_number
)
2822 && (pool
->literals
[entry
].X_add_symbol
2823 == inst
.reloc
.exp
.X_add_symbol
)
2824 && (pool
->literals
[entry
].X_op_symbol
2825 == inst
.reloc
.exp
.X_op_symbol
))
2829 /* Do we need to create a new entry? */
2830 if (entry
== pool
->next_free_entry
)
2832 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2834 inst
.error
= _("literal pool overflow");
2838 pool
->literals
[entry
] = inst
.reloc
.exp
;
2839 pool
->next_free_entry
+= 1;
2842 inst
.reloc
.exp
.X_op
= O_symbol
;
2843 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
2844 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
2849 /* Can't use symbol_new here, so have to create a symbol and then at
2850 a later date assign it a value. Thats what these functions do. */
2853 symbol_locate (symbolS
* symbolP
,
2854 const char * name
, /* It is copied, the caller can modify. */
2855 segT segment
, /* Segment identifier (SEG_<something>). */
2856 valueT valu
, /* Symbol value. */
2857 fragS
* frag
) /* Associated fragment. */
2859 unsigned int name_length
;
2860 char * preserved_copy_of_name
;
2862 name_length
= strlen (name
) + 1; /* +1 for \0. */
2863 obstack_grow (¬es
, name
, name_length
);
2864 preserved_copy_of_name
= obstack_finish (¬es
);
2866 #ifdef tc_canonicalize_symbol_name
2867 preserved_copy_of_name
=
2868 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2871 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2873 S_SET_SEGMENT (symbolP
, segment
);
2874 S_SET_VALUE (symbolP
, valu
);
2875 symbol_clear_list_pointers (symbolP
);
2877 symbol_set_frag (symbolP
, frag
);
2879 /* Link to end of symbol chain. */
2881 extern int symbol_table_frozen
;
2883 if (symbol_table_frozen
)
2887 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
2889 obj_symbol_new_hook (symbolP
);
2891 #ifdef tc_symbol_new_hook
2892 tc_symbol_new_hook (symbolP
);
2896 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2897 #endif /* DEBUG_SYMS */
2902 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2905 literal_pool
* pool
;
2908 pool
= find_literal_pool ();
2910 || pool
->symbol
== NULL
2911 || pool
->next_free_entry
== 0)
2914 mapping_state (MAP_DATA
);
2916 /* Align pool as you have word accesses.
2917 Only make a frag if we have to. */
2919 frag_align (2, 0, 0);
2921 record_alignment (now_seg
, 2);
2923 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2925 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2926 (valueT
) frag_now_fix (), frag_now
);
2927 symbol_table_insert (pool
->symbol
);
2929 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
2931 #if defined OBJ_COFF || defined OBJ_ELF
2932 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
2935 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2936 /* First output the expression in the instruction to the pool. */
2937 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
2939 /* Mark the pool as empty. */
2940 pool
->next_free_entry
= 0;
2941 pool
->symbol
= NULL
;
2945 /* Forward declarations for functions below, in the MD interface
2947 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
2948 static valueT
create_unwind_entry (int);
2949 static void start_unwind_section (const segT
, int);
2950 static void add_unwind_opcode (valueT
, int);
2951 static void flush_pending_unwind (void);
2953 /* Directives: Data. */
2956 s_arm_elf_cons (int nbytes
)
2960 #ifdef md_flush_pending_output
2961 md_flush_pending_output ();
2964 if (is_it_end_of_statement ())
2966 demand_empty_rest_of_line ();
2970 #ifdef md_cons_align
2971 md_cons_align (nbytes
);
2974 mapping_state (MAP_DATA
);
2978 char *base
= input_line_pointer
;
2982 if (exp
.X_op
!= O_symbol
)
2983 emit_expr (&exp
, (unsigned int) nbytes
);
2986 char *before_reloc
= input_line_pointer
;
2987 reloc
= parse_reloc (&input_line_pointer
);
2990 as_bad (_("unrecognized relocation suffix"));
2991 ignore_rest_of_line ();
2994 else if (reloc
== BFD_RELOC_UNUSED
)
2995 emit_expr (&exp
, (unsigned int) nbytes
);
2998 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2999 int size
= bfd_get_reloc_size (howto
);
3001 if (reloc
== BFD_RELOC_ARM_PLT32
)
3003 as_bad (_("(plt) is only valid on branch targets"));
3004 reloc
= BFD_RELOC_UNUSED
;
3009 as_bad (_("%s relocations do not fit in %d bytes"),
3010 howto
->name
, nbytes
);
3013 /* We've parsed an expression stopping at O_symbol.
3014 But there may be more expression left now that we
3015 have parsed the relocation marker. Parse it again.
3016 XXX Surely there is a cleaner way to do this. */
3017 char *p
= input_line_pointer
;
3019 char *save_buf
= alloca (input_line_pointer
- base
);
3020 memcpy (save_buf
, base
, input_line_pointer
- base
);
3021 memmove (base
+ (input_line_pointer
- before_reloc
),
3022 base
, before_reloc
- base
);
3024 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3026 memcpy (base
, save_buf
, p
- base
);
3028 offset
= nbytes
- size
;
3029 p
= frag_more ((int) nbytes
);
3030 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3031 size
, &exp
, 0, reloc
);
3036 while (*input_line_pointer
++ == ',');
3038 /* Put terminator back into stream. */
3039 input_line_pointer
--;
3040 demand_empty_rest_of_line ();
3044 /* Parse a .rel31 directive. */
3047 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3054 if (*input_line_pointer
== '1')
3055 highbit
= 0x80000000;
3056 else if (*input_line_pointer
!= '0')
3057 as_bad (_("expected 0 or 1"));
3059 input_line_pointer
++;
3060 if (*input_line_pointer
!= ',')
3061 as_bad (_("missing comma"));
3062 input_line_pointer
++;
3064 #ifdef md_flush_pending_output
3065 md_flush_pending_output ();
3068 #ifdef md_cons_align
3072 mapping_state (MAP_DATA
);
3077 md_number_to_chars (p
, highbit
, 4);
3078 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3079 BFD_RELOC_ARM_PREL31
);
3081 demand_empty_rest_of_line ();
3084 /* Directives: AEABI stack-unwind tables. */
3086 /* Parse an unwind_fnstart directive. Simply records the current location. */
3089 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3091 demand_empty_rest_of_line ();
3092 /* Mark the start of the function. */
3093 unwind
.proc_start
= expr_build_dot ();
3095 /* Reset the rest of the unwind info. */
3096 unwind
.opcode_count
= 0;
3097 unwind
.table_entry
= NULL
;
3098 unwind
.personality_routine
= NULL
;
3099 unwind
.personality_index
= -1;
3100 unwind
.frame_size
= 0;
3101 unwind
.fp_offset
= 0;
3102 unwind
.fp_reg
= REG_SP
;
3104 unwind
.sp_restored
= 0;
3108 /* Parse a handlerdata directive. Creates the exception handling table entry
3109 for the function. */
3112 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3114 demand_empty_rest_of_line ();
3115 if (unwind
.table_entry
)
3116 as_bad (_("duplicate .handlerdata directive"));
3118 create_unwind_entry (1);
3121 /* Parse an unwind_fnend directive. Generates the index table entry. */
3124 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3130 demand_empty_rest_of_line ();
3132 /* Add eh table entry. */
3133 if (unwind
.table_entry
== NULL
)
3134 val
= create_unwind_entry (0);
3138 /* Add index table entry. This is two words. */
3139 start_unwind_section (unwind
.saved_seg
, 1);
3140 frag_align (2, 0, 0);
3141 record_alignment (now_seg
, 2);
3143 ptr
= frag_more (8);
3144 where
= frag_now_fix () - 8;
3146 /* Self relative offset of the function start. */
3147 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3148 BFD_RELOC_ARM_PREL31
);
3150 /* Indicate dependency on EHABI-defined personality routines to the
3151 linker, if it hasn't been done already. */
3152 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3153 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3155 static const char *const name
[] =
3157 "__aeabi_unwind_cpp_pr0",
3158 "__aeabi_unwind_cpp_pr1",
3159 "__aeabi_unwind_cpp_pr2"
3161 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3162 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3163 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3164 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3165 = marked_pr_dependency
;
3169 /* Inline exception table entry. */
3170 md_number_to_chars (ptr
+ 4, val
, 4);
3172 /* Self relative offset of the table entry. */
3173 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3174 BFD_RELOC_ARM_PREL31
);
3176 /* Restore the original section. */
3177 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3181 /* Parse an unwind_cantunwind directive. */
3184 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3186 demand_empty_rest_of_line ();
3187 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3188 as_bad (_("personality routine specified for cantunwind frame"));
3190 unwind
.personality_index
= -2;
3194 /* Parse a personalityindex directive. */
3197 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3201 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3202 as_bad (_("duplicate .personalityindex directive"));
3206 if (exp
.X_op
!= O_constant
3207 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3209 as_bad (_("bad personality routine number"));
3210 ignore_rest_of_line ();
3214 unwind
.personality_index
= exp
.X_add_number
;
3216 demand_empty_rest_of_line ();
3220 /* Parse a personality directive. */
3223 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3227 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3228 as_bad (_("duplicate .personality directive"));
3230 name
= input_line_pointer
;
3231 c
= get_symbol_end ();
3232 p
= input_line_pointer
;
3233 unwind
.personality_routine
= symbol_find_or_make (name
);
3235 demand_empty_rest_of_line ();
3239 /* Parse a directive saving core registers. */
3242 s_arm_unwind_save_core (void)
3248 range
= parse_reg_list (&input_line_pointer
);
3251 as_bad (_("expected register list"));
3252 ignore_rest_of_line ();
3256 demand_empty_rest_of_line ();
3258 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3259 into .unwind_save {..., sp...}. We aren't bothered about the value of
3260 ip because it is clobbered by calls. */
3261 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3262 && (range
& 0x3000) == 0x1000)
3264 unwind
.opcode_count
--;
3265 unwind
.sp_restored
= 0;
3266 range
= (range
| 0x2000) & ~0x1000;
3267 unwind
.pending_offset
= 0;
3273 /* See if we can use the short opcodes. These pop a block of up to 8
3274 registers starting with r4, plus maybe r14. */
3275 for (n
= 0; n
< 8; n
++)
3277 /* Break at the first non-saved register. */
3278 if ((range
& (1 << (n
+ 4))) == 0)
3281 /* See if there are any other bits set. */
3282 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3284 /* Use the long form. */
3285 op
= 0x8000 | ((range
>> 4) & 0xfff);
3286 add_unwind_opcode (op
, 2);
3290 /* Use the short form. */
3292 op
= 0xa8; /* Pop r14. */
3294 op
= 0xa0; /* Do not pop r14. */
3296 add_unwind_opcode (op
, 1);
3303 op
= 0xb100 | (range
& 0xf);
3304 add_unwind_opcode (op
, 2);
3307 /* Record the number of bytes pushed. */
3308 for (n
= 0; n
< 16; n
++)
3310 if (range
& (1 << n
))
3311 unwind
.frame_size
+= 4;
3316 /* Parse a directive saving FPA registers. */
3319 s_arm_unwind_save_fpa (int reg
)
3325 /* Get Number of registers to transfer. */
3326 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3329 exp
.X_op
= O_illegal
;
3331 if (exp
.X_op
!= O_constant
)
3333 as_bad (_("expected , <constant>"));
3334 ignore_rest_of_line ();
3338 num_regs
= exp
.X_add_number
;
3340 if (num_regs
< 1 || num_regs
> 4)
3342 as_bad (_("number of registers must be in the range [1:4]"));
3343 ignore_rest_of_line ();
3347 demand_empty_rest_of_line ();
3352 op
= 0xb4 | (num_regs
- 1);
3353 add_unwind_opcode (op
, 1);
3358 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3359 add_unwind_opcode (op
, 2);
3361 unwind
.frame_size
+= num_regs
* 12;
3365 /* Parse a directive saving VFP registers for ARMv6 and above. */
3368 s_arm_unwind_save_vfp_armv6 (void)
3373 int num_vfpv3_regs
= 0;
3374 int num_regs_below_16
;
3376 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3379 as_bad (_("expected register list"));
3380 ignore_rest_of_line ();
3384 demand_empty_rest_of_line ();
3386 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3387 than FSTMX/FLDMX-style ones). */
3389 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3391 num_vfpv3_regs
= count
;
3392 else if (start
+ count
> 16)
3393 num_vfpv3_regs
= start
+ count
- 16;
3395 if (num_vfpv3_regs
> 0)
3397 int start_offset
= start
> 16 ? start
- 16 : 0;
3398 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3399 add_unwind_opcode (op
, 2);
3402 /* Generate opcode for registers numbered in the range 0 .. 15. */
3403 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3404 assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3405 if (num_regs_below_16
> 0)
3407 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3408 add_unwind_opcode (op
, 2);
3411 unwind
.frame_size
+= count
* 8;
3415 /* Parse a directive saving VFP registers for pre-ARMv6. */
3418 s_arm_unwind_save_vfp (void)
3424 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3427 as_bad (_("expected register list"));
3428 ignore_rest_of_line ();
3432 demand_empty_rest_of_line ();
3437 op
= 0xb8 | (count
- 1);
3438 add_unwind_opcode (op
, 1);
3443 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3444 add_unwind_opcode (op
, 2);
3446 unwind
.frame_size
+= count
* 8 + 4;
3450 /* Parse a directive saving iWMMXt data registers. */
3453 s_arm_unwind_save_mmxwr (void)
3461 if (*input_line_pointer
== '{')
3462 input_line_pointer
++;
3466 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3470 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3475 as_tsktsk (_("register list not in ascending order"));
3478 if (*input_line_pointer
== '-')
3480 input_line_pointer
++;
3481 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3484 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3487 else if (reg
>= hi_reg
)
3489 as_bad (_("bad register range"));
3492 for (; reg
< hi_reg
; reg
++)
3496 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3498 if (*input_line_pointer
== '}')
3499 input_line_pointer
++;
3501 demand_empty_rest_of_line ();
3503 /* Generate any deferred opcodes because we're going to be looking at
3505 flush_pending_unwind ();
3507 for (i
= 0; i
< 16; i
++)
3509 if (mask
& (1 << i
))
3510 unwind
.frame_size
+= 8;
3513 /* Attempt to combine with a previous opcode. We do this because gcc
3514 likes to output separate unwind directives for a single block of
3516 if (unwind
.opcode_count
> 0)
3518 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3519 if ((i
& 0xf8) == 0xc0)
3522 /* Only merge if the blocks are contiguous. */
3525 if ((mask
& 0xfe00) == (1 << 9))
3527 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3528 unwind
.opcode_count
--;
3531 else if (i
== 6 && unwind
.opcode_count
>= 2)
3533 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3537 op
= 0xffff << (reg
- 1);
3539 && ((mask
& op
) == (1u << (reg
- 1))))
3541 op
= (1 << (reg
+ i
+ 1)) - 1;
3542 op
&= ~((1 << reg
) - 1);
3544 unwind
.opcode_count
-= 2;
3551 /* We want to generate opcodes in the order the registers have been
3552 saved, ie. descending order. */
3553 for (reg
= 15; reg
>= -1; reg
--)
3555 /* Save registers in blocks. */
3557 || !(mask
& (1 << reg
)))
3559 /* We found an unsaved reg. Generate opcodes to save the
3566 op
= 0xc0 | (hi_reg
- 10);
3567 add_unwind_opcode (op
, 1);
3572 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3573 add_unwind_opcode (op
, 2);
3582 ignore_rest_of_line ();
3586 s_arm_unwind_save_mmxwcg (void)
3593 if (*input_line_pointer
== '{')
3594 input_line_pointer
++;
3598 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3602 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3608 as_tsktsk (_("register list not in ascending order"));
3611 if (*input_line_pointer
== '-')
3613 input_line_pointer
++;
3614 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3617 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3620 else if (reg
>= hi_reg
)
3622 as_bad (_("bad register range"));
3625 for (; reg
< hi_reg
; reg
++)
3629 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3631 if (*input_line_pointer
== '}')
3632 input_line_pointer
++;
3634 demand_empty_rest_of_line ();
3636 /* Generate any deferred opcodes because we're going to be looking at
3638 flush_pending_unwind ();
3640 for (reg
= 0; reg
< 16; reg
++)
3642 if (mask
& (1 << reg
))
3643 unwind
.frame_size
+= 4;
3646 add_unwind_opcode (op
, 2);
3649 ignore_rest_of_line ();
3653 /* Parse an unwind_save directive.
3654 If the argument is non-zero, this is a .vsave directive. */
3657 s_arm_unwind_save (int arch_v6
)
3660 struct reg_entry
*reg
;
3661 bfd_boolean had_brace
= FALSE
;
3663 /* Figure out what sort of save we have. */
3664 peek
= input_line_pointer
;
3672 reg
= arm_reg_parse_multi (&peek
);
3676 as_bad (_("register expected"));
3677 ignore_rest_of_line ();
3686 as_bad (_("FPA .unwind_save does not take a register list"));
3687 ignore_rest_of_line ();
3690 input_line_pointer
= peek
;
3691 s_arm_unwind_save_fpa (reg
->number
);
3694 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
3697 s_arm_unwind_save_vfp_armv6 ();
3699 s_arm_unwind_save_vfp ();
3701 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
3702 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
3705 as_bad (_(".unwind_save does not support this kind of register"));
3706 ignore_rest_of_line ();
3711 /* Parse an unwind_movsp directive. */
3714 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
3720 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3723 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
3724 ignore_rest_of_line ();
3728 /* Optional constant. */
3729 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3731 if (immediate_for_directive (&offset
) == FAIL
)
3737 demand_empty_rest_of_line ();
3739 if (reg
== REG_SP
|| reg
== REG_PC
)
3741 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3745 if (unwind
.fp_reg
!= REG_SP
)
3746 as_bad (_("unexpected .unwind_movsp directive"));
3748 /* Generate opcode to restore the value. */
3750 add_unwind_opcode (op
, 1);
3752 /* Record the information for later. */
3753 unwind
.fp_reg
= reg
;
3754 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3755 unwind
.sp_restored
= 1;
3758 /* Parse an unwind_pad directive. */
3761 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
3765 if (immediate_for_directive (&offset
) == FAIL
)
3770 as_bad (_("stack increment must be multiple of 4"));
3771 ignore_rest_of_line ();
3775 /* Don't generate any opcodes, just record the details for later. */
3776 unwind
.frame_size
+= offset
;
3777 unwind
.pending_offset
+= offset
;
3779 demand_empty_rest_of_line ();
3782 /* Parse an unwind_setfp directive. */
3785 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
3791 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3792 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3795 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3797 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
3799 as_bad (_("expected <reg>, <reg>"));
3800 ignore_rest_of_line ();
3804 /* Optional constant. */
3805 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3807 if (immediate_for_directive (&offset
) == FAIL
)
3813 demand_empty_rest_of_line ();
3815 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
3817 as_bad (_("register must be either sp or set by a previous"
3818 "unwind_movsp directive"));
3822 /* Don't generate any opcodes, just record the information for later. */
3823 unwind
.fp_reg
= fp_reg
;
3825 if (sp_reg
== REG_SP
)
3826 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3828 unwind
.fp_offset
-= offset
;
3831 /* Parse an unwind_raw directive. */
3834 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
3837 /* This is an arbitrary limit. */
3838 unsigned char op
[16];
3842 if (exp
.X_op
== O_constant
3843 && skip_past_comma (&input_line_pointer
) != FAIL
)
3845 unwind
.frame_size
+= exp
.X_add_number
;
3849 exp
.X_op
= O_illegal
;
3851 if (exp
.X_op
!= O_constant
)
3853 as_bad (_("expected <offset>, <opcode>"));
3854 ignore_rest_of_line ();
3860 /* Parse the opcode. */
3865 as_bad (_("unwind opcode too long"));
3866 ignore_rest_of_line ();
3868 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
3870 as_bad (_("invalid unwind opcode"));
3871 ignore_rest_of_line ();
3874 op
[count
++] = exp
.X_add_number
;
3876 /* Parse the next byte. */
3877 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3883 /* Add the opcode bytes in reverse order. */
3885 add_unwind_opcode (op
[count
], 1);
3887 demand_empty_rest_of_line ();
3891 /* Parse a .eabi_attribute directive. */
3894 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
3896 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
3898 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
3899 attributes_set_explicitly
[tag
] = 1;
3901 #endif /* OBJ_ELF */
3903 static void s_arm_arch (int);
3904 static void s_arm_object_arch (int);
3905 static void s_arm_cpu (int);
3906 static void s_arm_fpu (int);
3911 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
3918 if (exp
.X_op
== O_symbol
)
3919 exp
.X_op
= O_secrel
;
3921 emit_expr (&exp
, 4);
3923 while (*input_line_pointer
++ == ',');
3925 input_line_pointer
--;
3926 demand_empty_rest_of_line ();
3930 /* This table describes all the machine specific pseudo-ops the assembler
3931 has to support. The fields are:
3932 pseudo-op name without dot
3933 function to call to execute this pseudo-op
3934 Integer arg to pass to the function. */
3936 const pseudo_typeS md_pseudo_table
[] =
3938 /* Never called because '.req' does not start a line. */
3939 { "req", s_req
, 0 },
3940 /* Following two are likewise never called. */
3943 { "unreq", s_unreq
, 0 },
3944 { "bss", s_bss
, 0 },
3945 { "align", s_align
, 0 },
3946 { "arm", s_arm
, 0 },
3947 { "thumb", s_thumb
, 0 },
3948 { "code", s_code
, 0 },
3949 { "force_thumb", s_force_thumb
, 0 },
3950 { "thumb_func", s_thumb_func
, 0 },
3951 { "thumb_set", s_thumb_set
, 0 },
3952 { "even", s_even
, 0 },
3953 { "ltorg", s_ltorg
, 0 },
3954 { "pool", s_ltorg
, 0 },
3955 { "syntax", s_syntax
, 0 },
3956 { "cpu", s_arm_cpu
, 0 },
3957 { "arch", s_arm_arch
, 0 },
3958 { "object_arch", s_arm_object_arch
, 0 },
3959 { "fpu", s_arm_fpu
, 0 },
3961 { "word", s_arm_elf_cons
, 4 },
3962 { "long", s_arm_elf_cons
, 4 },
3963 { "rel31", s_arm_rel31
, 0 },
3964 { "fnstart", s_arm_unwind_fnstart
, 0 },
3965 { "fnend", s_arm_unwind_fnend
, 0 },
3966 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
3967 { "personality", s_arm_unwind_personality
, 0 },
3968 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
3969 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
3970 { "save", s_arm_unwind_save
, 0 },
3971 { "vsave", s_arm_unwind_save
, 1 },
3972 { "movsp", s_arm_unwind_movsp
, 0 },
3973 { "pad", s_arm_unwind_pad
, 0 },
3974 { "setfp", s_arm_unwind_setfp
, 0 },
3975 { "unwind_raw", s_arm_unwind_raw
, 0 },
3976 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
3980 /* These are used for dwarf. */
3984 /* These are used for dwarf2. */
3985 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
3986 { "loc", dwarf2_directive_loc
, 0 },
3987 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
3989 { "extend", float_cons
, 'x' },
3990 { "ldouble", float_cons
, 'x' },
3991 { "packed", float_cons
, 'p' },
3993 {"secrel32", pe_directive_secrel
, 0},
3998 /* Parser functions used exclusively in instruction operands. */
4000 /* Generic immediate-value read function for use in insn parsing.
4001 STR points to the beginning of the immediate (the leading #);
4002 VAL receives the value; if the value is outside [MIN, MAX]
4003 issue an error. PREFIX_OPT is true if the immediate prefix is
4007 parse_immediate (char **str
, int *val
, int min
, int max
,
4008 bfd_boolean prefix_opt
)
4011 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4012 if (exp
.X_op
!= O_constant
)
4014 inst
.error
= _("constant expression required");
4018 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4020 inst
.error
= _("immediate value out of range");
4024 *val
= exp
.X_add_number
;
4028 /* Less-generic immediate-value read function with the possibility of loading a
4029 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4030 instructions. Puts the result directly in inst.operands[i]. */
4033 parse_big_immediate (char **str
, int i
)
4038 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4040 if (exp
.X_op
== O_constant
)
4042 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4043 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4044 O_constant. We have to be careful not to break compilation for
4045 32-bit X_add_number, though. */
4046 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4048 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4049 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4050 inst
.operands
[i
].regisimm
= 1;
4053 else if (exp
.X_op
== O_big
4054 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4055 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4057 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4058 /* Bignums have their least significant bits in
4059 generic_bignum[0]. Make sure we put 32 bits in imm and
4060 32 bits in reg, in a (hopefully) portable way. */
4061 assert (parts
!= 0);
4062 inst
.operands
[i
].imm
= 0;
4063 for (j
= 0; j
< parts
; j
++, idx
++)
4064 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4065 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4066 inst
.operands
[i
].reg
= 0;
4067 for (j
= 0; j
< parts
; j
++, idx
++)
4068 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4069 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4070 inst
.operands
[i
].regisimm
= 1;
4080 /* Returns the pseudo-register number of an FPA immediate constant,
4081 or FAIL if there isn't a valid constant here. */
4084 parse_fpa_immediate (char ** str
)
4086 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4092 /* First try and match exact strings, this is to guarantee
4093 that some formats will work even for cross assembly. */
4095 for (i
= 0; fp_const
[i
]; i
++)
4097 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4101 *str
+= strlen (fp_const
[i
]);
4102 if (is_end_of_line
[(unsigned char) **str
])
4108 /* Just because we didn't get a match doesn't mean that the constant
4109 isn't valid, just that it is in a format that we don't
4110 automatically recognize. Try parsing it with the standard
4111 expression routines. */
4113 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4115 /* Look for a raw floating point number. */
4116 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4117 && is_end_of_line
[(unsigned char) *save_in
])
4119 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4121 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4123 if (words
[j
] != fp_values
[i
][j
])
4127 if (j
== MAX_LITTLENUMS
)
4135 /* Try and parse a more complex expression, this will probably fail
4136 unless the code uses a floating point prefix (eg "0f"). */
4137 save_in
= input_line_pointer
;
4138 input_line_pointer
= *str
;
4139 if (expression (&exp
) == absolute_section
4140 && exp
.X_op
== O_big
4141 && exp
.X_add_number
< 0)
4143 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4145 if (gen_to_words (words
, 5, (long) 15) == 0)
4147 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4149 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4151 if (words
[j
] != fp_values
[i
][j
])
4155 if (j
== MAX_LITTLENUMS
)
4157 *str
= input_line_pointer
;
4158 input_line_pointer
= save_in
;
4165 *str
= input_line_pointer
;
4166 input_line_pointer
= save_in
;
4167 inst
.error
= _("invalid FPA immediate expression");
4171 /* Returns 1 if a number has "quarter-precision" float format
4172 0baBbbbbbc defgh000 00000000 00000000. */
4175 is_quarter_float (unsigned imm
)
4177 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4178 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4181 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4182 0baBbbbbbc defgh000 00000000 00000000.
4183 The zero and minus-zero cases need special handling, since they can't be
4184 encoded in the "quarter-precision" float format, but can nonetheless be
4185 loaded as integer constants. */
4188 parse_qfloat_immediate (char **ccp
, int *immed
)
4192 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4193 int found_fpchar
= 0;
4195 skip_past_char (&str
, '#');
4197 /* We must not accidentally parse an integer as a floating-point number. Make
4198 sure that the value we parse is not an integer by checking for special
4199 characters '.' or 'e'.
4200 FIXME: This is a horrible hack, but doing better is tricky because type
4201 information isn't in a very usable state at parse time. */
4203 skip_whitespace (fpnum
);
4205 if (strncmp (fpnum
, "0x", 2) == 0)
4209 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4210 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4220 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4222 unsigned fpword
= 0;
4225 /* Our FP word must be 32 bits (single-precision FP). */
4226 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4228 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4232 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4245 /* Shift operands. */
4248 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4251 struct asm_shift_name
4254 enum shift_kind kind
;
4257 /* Third argument to parse_shift. */
4258 enum parse_shift_mode
4260 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4261 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4262 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4263 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4264 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4267 /* Parse a <shift> specifier on an ARM data processing instruction.
4268 This has three forms:
4270 (LSL|LSR|ASL|ASR|ROR) Rs
4271 (LSL|LSR|ASL|ASR|ROR) #imm
4274 Note that ASL is assimilated to LSL in the instruction encoding, and
4275 RRX to ROR #0 (which cannot be written as such). */
4278 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4280 const struct asm_shift_name
*shift_name
;
4281 enum shift_kind shift
;
4286 for (p
= *str
; ISALPHA (*p
); p
++)
4291 inst
.error
= _("shift expression expected");
4295 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4297 if (shift_name
== NULL
)
4299 inst
.error
= _("shift expression expected");
4303 shift
= shift_name
->kind
;
4307 case NO_SHIFT_RESTRICT
:
4308 case SHIFT_IMMEDIATE
: break;
4310 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4311 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4313 inst
.error
= _("'LSL' or 'ASR' required");
4318 case SHIFT_LSL_IMMEDIATE
:
4319 if (shift
!= SHIFT_LSL
)
4321 inst
.error
= _("'LSL' required");
4326 case SHIFT_ASR_IMMEDIATE
:
4327 if (shift
!= SHIFT_ASR
)
4329 inst
.error
= _("'ASR' required");
4337 if (shift
!= SHIFT_RRX
)
4339 /* Whitespace can appear here if the next thing is a bare digit. */
4340 skip_whitespace (p
);
4342 if (mode
== NO_SHIFT_RESTRICT
4343 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4345 inst
.operands
[i
].imm
= reg
;
4346 inst
.operands
[i
].immisreg
= 1;
4348 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4351 inst
.operands
[i
].shift_kind
= shift
;
4352 inst
.operands
[i
].shifted
= 1;
4357 /* Parse a <shifter_operand> for an ARM data processing instruction:
4360 #<immediate>, <rotate>
4364 where <shift> is defined by parse_shift above, and <rotate> is a
4365 multiple of 2 between 0 and 30. Validation of immediate operands
4366 is deferred to md_apply_fix. */
4369 parse_shifter_operand (char **str
, int i
)
4374 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4376 inst
.operands
[i
].reg
= value
;
4377 inst
.operands
[i
].isreg
= 1;
4379 /* parse_shift will override this if appropriate */
4380 inst
.reloc
.exp
.X_op
= O_constant
;
4381 inst
.reloc
.exp
.X_add_number
= 0;
4383 if (skip_past_comma (str
) == FAIL
)
4386 /* Shift operation on register. */
4387 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4390 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4393 if (skip_past_comma (str
) == SUCCESS
)
4395 /* #x, y -- ie explicit rotation by Y. */
4396 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4399 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4401 inst
.error
= _("constant expression expected");
4405 value
= expr
.X_add_number
;
4406 if (value
< 0 || value
> 30 || value
% 2 != 0)
4408 inst
.error
= _("invalid rotation");
4411 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4413 inst
.error
= _("invalid constant");
4417 /* Convert to decoded value. md_apply_fix will put it back. */
4418 inst
.reloc
.exp
.X_add_number
4419 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4420 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4423 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4424 inst
.reloc
.pc_rel
= 0;
4428 /* Group relocation information. Each entry in the table contains the
4429 textual name of the relocation as may appear in assembler source
4430 and must end with a colon.
4431 Along with this textual name are the relocation codes to be used if
4432 the corresponding instruction is an ALU instruction (ADD or SUB only),
4433 an LDR, an LDRS, or an LDC. */
4435 struct group_reloc_table_entry
4446 /* Varieties of non-ALU group relocation. */
4453 static struct group_reloc_table_entry group_reloc_table
[] =
4454 { /* Program counter relative: */
4456 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4461 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4462 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4463 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4464 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4466 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4471 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4472 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4473 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4474 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4476 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4477 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4478 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4479 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4480 /* Section base relative */
4482 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4487 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4488 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4489 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4490 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4492 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4497 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4498 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4499 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4500 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4502 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4503 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4504 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4505 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4507 /* Given the address of a pointer pointing to the textual name of a group
4508 relocation as may appear in assembler source, attempt to find its details
4509 in group_reloc_table. The pointer will be updated to the character after
4510 the trailing colon. On failure, FAIL will be returned; SUCCESS
4511 otherwise. On success, *entry will be updated to point at the relevant
4512 group_reloc_table entry. */
4515 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4518 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4520 int length
= strlen (group_reloc_table
[i
].name
);
4522 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4523 && (*str
)[length
] == ':')
4525 *out
= &group_reloc_table
[i
];
4526 *str
+= (length
+ 1);
4534 /* Parse a <shifter_operand> for an ARM data processing instruction
4535 (as for parse_shifter_operand) where group relocations are allowed:
4538 #<immediate>, <rotate>
4539 #:<group_reloc>:<expression>
4543 where <group_reloc> is one of the strings defined in group_reloc_table.
4544 The hashes are optional.
4546 Everything else is as for parse_shifter_operand. */
4548 static parse_operand_result
4549 parse_shifter_operand_group_reloc (char **str
, int i
)
4551 /* Determine if we have the sequence of characters #: or just :
4552 coming next. If we do, then we check for a group relocation.
4553 If we don't, punt the whole lot to parse_shifter_operand. */
4555 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4556 || (*str
)[0] == ':')
4558 struct group_reloc_table_entry
*entry
;
4560 if ((*str
)[0] == '#')
4565 /* Try to parse a group relocation. Anything else is an error. */
4566 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4568 inst
.error
= _("unknown group relocation");
4569 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4572 /* We now have the group relocation table entry corresponding to
4573 the name in the assembler source. Next, we parse the expression. */
4574 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4575 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4577 /* Record the relocation type (always the ALU variant here). */
4578 inst
.reloc
.type
= entry
->alu_code
;
4579 assert (inst
.reloc
.type
!= 0);
4581 return PARSE_OPERAND_SUCCESS
;
4584 return parse_shifter_operand (str
, i
) == SUCCESS
4585 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4587 /* Never reached. */
4590 /* Parse all forms of an ARM address expression. Information is written
4591 to inst.operands[i] and/or inst.reloc.
4593 Preindexed addressing (.preind=1):
4595 [Rn, #offset] .reg=Rn .reloc.exp=offset
4596 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4597 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4598 .shift_kind=shift .reloc.exp=shift_imm
4600 These three may have a trailing ! which causes .writeback to be set also.
4602 Postindexed addressing (.postind=1, .writeback=1):
4604 [Rn], #offset .reg=Rn .reloc.exp=offset
4605 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4606 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4607 .shift_kind=shift .reloc.exp=shift_imm
4609 Unindexed addressing (.preind=0, .postind=0):
4611 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4615 [Rn]{!} shorthand for [Rn,#0]{!}
4616 =immediate .isreg=0 .reloc.exp=immediate
4617 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4619 It is the caller's responsibility to check for addressing modes not
4620 supported by the instruction, and to set inst.reloc.type. */
4622 static parse_operand_result
4623 parse_address_main (char **str
, int i
, int group_relocations
,
4624 group_reloc_type group_type
)
4629 if (skip_past_char (&p
, '[') == FAIL
)
4631 if (skip_past_char (&p
, '=') == FAIL
)
4633 /* bare address - translate to PC-relative offset */
4634 inst
.reloc
.pc_rel
= 1;
4635 inst
.operands
[i
].reg
= REG_PC
;
4636 inst
.operands
[i
].isreg
= 1;
4637 inst
.operands
[i
].preind
= 1;
4639 /* else a load-constant pseudo op, no special treatment needed here */
4641 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4642 return PARSE_OPERAND_FAIL
;
4645 return PARSE_OPERAND_SUCCESS
;
4648 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4650 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4651 return PARSE_OPERAND_FAIL
;
4653 inst
.operands
[i
].reg
= reg
;
4654 inst
.operands
[i
].isreg
= 1;
4656 if (skip_past_comma (&p
) == SUCCESS
)
4658 inst
.operands
[i
].preind
= 1;
4661 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4663 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4665 inst
.operands
[i
].imm
= reg
;
4666 inst
.operands
[i
].immisreg
= 1;
4668 if (skip_past_comma (&p
) == SUCCESS
)
4669 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4670 return PARSE_OPERAND_FAIL
;
4672 else if (skip_past_char (&p
, ':') == SUCCESS
)
4674 /* FIXME: '@' should be used here, but it's filtered out by generic
4675 code before we get to see it here. This may be subject to
4678 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4679 if (exp
.X_op
!= O_constant
)
4681 inst
.error
= _("alignment must be constant");
4682 return PARSE_OPERAND_FAIL
;
4684 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4685 inst
.operands
[i
].immisalign
= 1;
4686 /* Alignments are not pre-indexes. */
4687 inst
.operands
[i
].preind
= 0;
4691 if (inst
.operands
[i
].negative
)
4693 inst
.operands
[i
].negative
= 0;
4697 if (group_relocations
4698 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
4700 struct group_reloc_table_entry
*entry
;
4702 /* Skip over the #: or : sequence. */
4708 /* Try to parse a group relocation. Anything else is an
4710 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
4712 inst
.error
= _("unknown group relocation");
4713 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4716 /* We now have the group relocation table entry corresponding to
4717 the name in the assembler source. Next, we parse the
4719 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4720 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4722 /* Record the relocation type. */
4726 inst
.reloc
.type
= entry
->ldr_code
;
4730 inst
.reloc
.type
= entry
->ldrs_code
;
4734 inst
.reloc
.type
= entry
->ldc_code
;
4741 if (inst
.reloc
.type
== 0)
4743 inst
.error
= _("this group relocation is not allowed on this instruction");
4744 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4748 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4749 return PARSE_OPERAND_FAIL
;
4753 if (skip_past_char (&p
, ']') == FAIL
)
4755 inst
.error
= _("']' expected");
4756 return PARSE_OPERAND_FAIL
;
4759 if (skip_past_char (&p
, '!') == SUCCESS
)
4760 inst
.operands
[i
].writeback
= 1;
4762 else if (skip_past_comma (&p
) == SUCCESS
)
4764 if (skip_past_char (&p
, '{') == SUCCESS
)
4766 /* [Rn], {expr} - unindexed, with option */
4767 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
4768 0, 255, TRUE
) == FAIL
)
4769 return PARSE_OPERAND_FAIL
;
4771 if (skip_past_char (&p
, '}') == FAIL
)
4773 inst
.error
= _("'}' expected at end of 'option' field");
4774 return PARSE_OPERAND_FAIL
;
4776 if (inst
.operands
[i
].preind
)
4778 inst
.error
= _("cannot combine index with option");
4779 return PARSE_OPERAND_FAIL
;
4782 return PARSE_OPERAND_SUCCESS
;
4786 inst
.operands
[i
].postind
= 1;
4787 inst
.operands
[i
].writeback
= 1;
4789 if (inst
.operands
[i
].preind
)
4791 inst
.error
= _("cannot combine pre- and post-indexing");
4792 return PARSE_OPERAND_FAIL
;
4796 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4798 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4800 /* We might be using the immediate for alignment already. If we
4801 are, OR the register number into the low-order bits. */
4802 if (inst
.operands
[i
].immisalign
)
4803 inst
.operands
[i
].imm
|= reg
;
4805 inst
.operands
[i
].imm
= reg
;
4806 inst
.operands
[i
].immisreg
= 1;
4808 if (skip_past_comma (&p
) == SUCCESS
)
4809 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4810 return PARSE_OPERAND_FAIL
;
4814 if (inst
.operands
[i
].negative
)
4816 inst
.operands
[i
].negative
= 0;
4819 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4820 return PARSE_OPERAND_FAIL
;
4825 /* If at this point neither .preind nor .postind is set, we have a
4826 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4827 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
4829 inst
.operands
[i
].preind
= 1;
4830 inst
.reloc
.exp
.X_op
= O_constant
;
4831 inst
.reloc
.exp
.X_add_number
= 0;
4834 return PARSE_OPERAND_SUCCESS
;
4838 parse_address (char **str
, int i
)
4840 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
4844 static parse_operand_result
4845 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
4847 return parse_address_main (str
, i
, 1, type
);
4850 /* Parse an operand for a MOVW or MOVT instruction. */
4852 parse_half (char **str
)
4857 skip_past_char (&p
, '#');
4858 if (strncasecmp (p
, ":lower16:", 9) == 0)
4859 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
4860 else if (strncasecmp (p
, ":upper16:", 9) == 0)
4861 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
4863 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4866 skip_whitespace (p
);
4869 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4872 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4874 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4876 inst
.error
= _("constant expression expected");
4879 if (inst
.reloc
.exp
.X_add_number
< 0
4880 || inst
.reloc
.exp
.X_add_number
> 0xffff)
4882 inst
.error
= _("immediate value out of range");
4890 /* Miscellaneous. */
4892 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4893 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4895 parse_psr (char **str
)
4898 unsigned long psr_field
;
4899 const struct asm_psr
*psr
;
4902 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4903 feature for ease of use and backwards compatibility. */
4905 if (strncasecmp (p
, "SPSR", 4) == 0)
4906 psr_field
= SPSR_BIT
;
4907 else if (strncasecmp (p
, "CPSR", 4) == 0)
4914 while (ISALNUM (*p
) || *p
== '_');
4916 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
4927 /* A suffix follows. */
4933 while (ISALNUM (*p
) || *p
== '_');
4935 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
4939 psr_field
|= psr
->field
;
4944 goto error
; /* Garbage after "[CS]PSR". */
4946 psr_field
|= (PSR_c
| PSR_f
);
4952 inst
.error
= _("flag for {c}psr instruction expected");
4956 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4957 value suitable for splatting into the AIF field of the instruction. */
4960 parse_cps_flags (char **str
)
4969 case '\0': case ',':
4972 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
4973 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
4974 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
4977 inst
.error
= _("unrecognized CPS flag");
4982 if (saw_a_flag
== 0)
4984 inst
.error
= _("missing CPS flags");
4992 /* Parse an endian specifier ("BE" or "LE", case insensitive);
4993 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4996 parse_endian_specifier (char **str
)
5001 if (strncasecmp (s
, "BE", 2))
5003 else if (strncasecmp (s
, "LE", 2))
5007 inst
.error
= _("valid endian specifiers are be or le");
5011 if (ISALNUM (s
[2]) || s
[2] == '_')
5013 inst
.error
= _("valid endian specifiers are be or le");
5018 return little_endian
;
5021 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5022 value suitable for poking into the rotate field of an sxt or sxta
5023 instruction, or FAIL on error. */
5026 parse_ror (char **str
)
5031 if (strncasecmp (s
, "ROR", 3) == 0)
5035 inst
.error
= _("missing rotation field after comma");
5039 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5044 case 0: *str
= s
; return 0x0;
5045 case 8: *str
= s
; return 0x1;
5046 case 16: *str
= s
; return 0x2;
5047 case 24: *str
= s
; return 0x3;
5050 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5055 /* Parse a conditional code (from conds[] below). The value returned is in the
5056 range 0 .. 14, or FAIL. */
5058 parse_cond (char **str
)
5061 const struct asm_cond
*c
;
5063 /* Condition codes are always 2 characters, so matching up to
5064 3 characters is sufficient. */
5069 while (ISALPHA (*q
) && n
< 3)
5071 cond
[n
] = TOLOWER(*q
);
5076 c
= hash_find_n (arm_cond_hsh
, cond
, n
);
5079 inst
.error
= _("condition required");
5087 /* Parse an option for a barrier instruction. Returns the encoding for the
5090 parse_barrier (char **str
)
5093 const struct asm_barrier_opt
*o
;
5096 while (ISALPHA (*q
))
5099 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
5107 /* Parse the operands of a table branch instruction. Similar to a memory
5110 parse_tb (char **str
)
5115 if (skip_past_char (&p
, '[') == FAIL
)
5117 inst
.error
= _("'[' expected");
5121 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5123 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5126 inst
.operands
[0].reg
= reg
;
5128 if (skip_past_comma (&p
) == FAIL
)
5130 inst
.error
= _("',' expected");
5134 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5136 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5139 inst
.operands
[0].imm
= reg
;
5141 if (skip_past_comma (&p
) == SUCCESS
)
5143 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5145 if (inst
.reloc
.exp
.X_add_number
!= 1)
5147 inst
.error
= _("invalid shift");
5150 inst
.operands
[0].shifted
= 1;
5153 if (skip_past_char (&p
, ']') == FAIL
)
5155 inst
.error
= _("']' expected");
5162 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5163 information on the types the operands can take and how they are encoded.
5164 Up to four operands may be read; this function handles setting the
5165 ".present" field for each read operand itself.
5166 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5167 else returns FAIL. */
5170 parse_neon_mov (char **str
, int *which_operand
)
5172 int i
= *which_operand
, val
;
5173 enum arm_reg_type rtype
;
5175 struct neon_type_el optype
;
5177 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5179 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5180 inst
.operands
[i
].reg
= val
;
5181 inst
.operands
[i
].isscalar
= 1;
5182 inst
.operands
[i
].vectype
= optype
;
5183 inst
.operands
[i
++].present
= 1;
5185 if (skip_past_comma (&ptr
) == FAIL
)
5188 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5191 inst
.operands
[i
].reg
= val
;
5192 inst
.operands
[i
].isreg
= 1;
5193 inst
.operands
[i
].present
= 1;
5195 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5198 /* Cases 0, 1, 2, 3, 5 (D only). */
5199 if (skip_past_comma (&ptr
) == FAIL
)
5202 inst
.operands
[i
].reg
= val
;
5203 inst
.operands
[i
].isreg
= 1;
5204 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5205 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5206 inst
.operands
[i
].isvec
= 1;
5207 inst
.operands
[i
].vectype
= optype
;
5208 inst
.operands
[i
++].present
= 1;
5210 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5212 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5213 Case 13: VMOV <Sd>, <Rm> */
5214 inst
.operands
[i
].reg
= val
;
5215 inst
.operands
[i
].isreg
= 1;
5216 inst
.operands
[i
].present
= 1;
5218 if (rtype
== REG_TYPE_NQ
)
5220 first_error (_("can't use Neon quad register here"));
5223 else if (rtype
!= REG_TYPE_VFS
)
5226 if (skip_past_comma (&ptr
) == FAIL
)
5228 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5230 inst
.operands
[i
].reg
= val
;
5231 inst
.operands
[i
].isreg
= 1;
5232 inst
.operands
[i
].present
= 1;
5235 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5238 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5239 Case 1: VMOV<c><q> <Dd>, <Dm>
5240 Case 8: VMOV.F32 <Sd>, <Sm>
5241 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5243 inst
.operands
[i
].reg
= val
;
5244 inst
.operands
[i
].isreg
= 1;
5245 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5246 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5247 inst
.operands
[i
].isvec
= 1;
5248 inst
.operands
[i
].vectype
= optype
;
5249 inst
.operands
[i
].present
= 1;
5251 if (skip_past_comma (&ptr
) == SUCCESS
)
5256 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5259 inst
.operands
[i
].reg
= val
;
5260 inst
.operands
[i
].isreg
= 1;
5261 inst
.operands
[i
++].present
= 1;
5263 if (skip_past_comma (&ptr
) == FAIL
)
5266 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5269 inst
.operands
[i
].reg
= val
;
5270 inst
.operands
[i
].isreg
= 1;
5271 inst
.operands
[i
++].present
= 1;
5274 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5275 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5276 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5277 Case 10: VMOV.F32 <Sd>, #<imm>
5278 Case 11: VMOV.F64 <Dd>, #<imm> */
5279 inst
.operands
[i
].immisfloat
= 1;
5280 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5281 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5282 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5286 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5290 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5293 inst
.operands
[i
].reg
= val
;
5294 inst
.operands
[i
].isreg
= 1;
5295 inst
.operands
[i
++].present
= 1;
5297 if (skip_past_comma (&ptr
) == FAIL
)
5300 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5302 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5303 inst
.operands
[i
].reg
= val
;
5304 inst
.operands
[i
].isscalar
= 1;
5305 inst
.operands
[i
].present
= 1;
5306 inst
.operands
[i
].vectype
= optype
;
5308 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5310 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5311 inst
.operands
[i
].reg
= val
;
5312 inst
.operands
[i
].isreg
= 1;
5313 inst
.operands
[i
++].present
= 1;
5315 if (skip_past_comma (&ptr
) == FAIL
)
5318 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5321 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5325 inst
.operands
[i
].reg
= val
;
5326 inst
.operands
[i
].isreg
= 1;
5327 inst
.operands
[i
].isvec
= 1;
5328 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5329 inst
.operands
[i
].vectype
= optype
;
5330 inst
.operands
[i
].present
= 1;
5332 if (rtype
== REG_TYPE_VFS
)
5336 if (skip_past_comma (&ptr
) == FAIL
)
5338 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5341 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5344 inst
.operands
[i
].reg
= val
;
5345 inst
.operands
[i
].isreg
= 1;
5346 inst
.operands
[i
].isvec
= 1;
5347 inst
.operands
[i
].issingle
= 1;
5348 inst
.operands
[i
].vectype
= optype
;
5349 inst
.operands
[i
].present
= 1;
5352 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5356 inst
.operands
[i
].reg
= val
;
5357 inst
.operands
[i
].isreg
= 1;
5358 inst
.operands
[i
].isvec
= 1;
5359 inst
.operands
[i
].issingle
= 1;
5360 inst
.operands
[i
].vectype
= optype
;
5361 inst
.operands
[i
++].present
= 1;
5366 first_error (_("parse error"));
5370 /* Successfully parsed the operands. Update args. */
5376 first_error (_("expected comma"));
5380 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5384 /* Matcher codes for parse_operands. */
5385 enum operand_parse_code
5387 OP_stop
, /* end of line */
5389 OP_RR
, /* ARM register */
5390 OP_RRnpc
, /* ARM register, not r15 */
5391 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5392 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5393 OP_RCP
, /* Coprocessor number */
5394 OP_RCN
, /* Coprocessor register */
5395 OP_RF
, /* FPA register */
5396 OP_RVS
, /* VFP single precision register */
5397 OP_RVD
, /* VFP double precision register (0..15) */
5398 OP_RND
, /* Neon double precision register (0..31) */
5399 OP_RNQ
, /* Neon quad precision register */
5400 OP_RVSD
, /* VFP single or double precision register */
5401 OP_RNDQ
, /* Neon double or quad precision register */
5402 OP_RNSDQ
, /* Neon single, double or quad precision register */
5403 OP_RNSC
, /* Neon scalar D[X] */
5404 OP_RVC
, /* VFP control register */
5405 OP_RMF
, /* Maverick F register */
5406 OP_RMD
, /* Maverick D register */
5407 OP_RMFX
, /* Maverick FX register */
5408 OP_RMDX
, /* Maverick DX register */
5409 OP_RMAX
, /* Maverick AX register */
5410 OP_RMDS
, /* Maverick DSPSC register */
5411 OP_RIWR
, /* iWMMXt wR register */
5412 OP_RIWC
, /* iWMMXt wC register */
5413 OP_RIWG
, /* iWMMXt wCG register */
5414 OP_RXA
, /* XScale accumulator register */
5416 OP_REGLST
, /* ARM register list */
5417 OP_VRSLST
, /* VFP single-precision register list */
5418 OP_VRDLST
, /* VFP double-precision register list */
5419 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5420 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5421 OP_NSTRLST
, /* Neon element/structure list */
5423 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5424 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5425 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5426 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5427 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5428 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5429 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5430 OP_VMOV
, /* Neon VMOV operands. */
5431 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5432 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5433 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5435 OP_I0
, /* immediate zero */
5436 OP_I7
, /* immediate value 0 .. 7 */
5437 OP_I15
, /* 0 .. 15 */
5438 OP_I16
, /* 1 .. 16 */
5439 OP_I16z
, /* 0 .. 16 */
5440 OP_I31
, /* 0 .. 31 */
5441 OP_I31w
, /* 0 .. 31, optional trailing ! */
5442 OP_I32
, /* 1 .. 32 */
5443 OP_I32z
, /* 0 .. 32 */
5444 OP_I63
, /* 0 .. 63 */
5445 OP_I63s
, /* -64 .. 63 */
5446 OP_I64
, /* 1 .. 64 */
5447 OP_I64z
, /* 0 .. 64 */
5448 OP_I255
, /* 0 .. 255 */
5450 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5451 OP_I7b
, /* 0 .. 7 */
5452 OP_I15b
, /* 0 .. 15 */
5453 OP_I31b
, /* 0 .. 31 */
5455 OP_SH
, /* shifter operand */
5456 OP_SHG
, /* shifter operand with possible group relocation */
5457 OP_ADDR
, /* Memory address expression (any mode) */
5458 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5459 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5460 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5461 OP_EXP
, /* arbitrary expression */
5462 OP_EXPi
, /* same, with optional immediate prefix */
5463 OP_EXPr
, /* same, with optional relocation suffix */
5464 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5466 OP_CPSF
, /* CPS flags */
5467 OP_ENDI
, /* Endianness specifier */
5468 OP_PSR
, /* CPSR/SPSR mask for msr */
5469 OP_COND
, /* conditional code */
5470 OP_TB
, /* Table branch. */
5472 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5473 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5475 OP_RRnpc_I0
, /* ARM register or literal 0 */
5476 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5477 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5478 OP_RF_IF
, /* FPA register or immediate */
5479 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5480 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5482 /* Optional operands. */
5483 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5484 OP_oI31b
, /* 0 .. 31 */
5485 OP_oI32b
, /* 1 .. 32 */
5486 OP_oIffffb
, /* 0 .. 65535 */
5487 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5489 OP_oRR
, /* ARM register */
5490 OP_oRRnpc
, /* ARM register, not the PC */
5491 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5492 OP_oRND
, /* Optional Neon double precision register */
5493 OP_oRNQ
, /* Optional Neon quad precision register */
5494 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5495 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5496 OP_oSHll
, /* LSL immediate */
5497 OP_oSHar
, /* ASR immediate */
5498 OP_oSHllar
, /* LSL or ASR immediate */
5499 OP_oROR
, /* ROR 0/8/16/24 */
5500 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5502 OP_FIRST_OPTIONAL
= OP_oI7b
5505 /* Generic instruction operand parser. This does no encoding and no
5506 semantic validation; it merely squirrels values away in the inst
5507 structure. Returns SUCCESS or FAIL depending on whether the
5508 specified grammar matched. */
5510 parse_operands (char *str
, const unsigned char *pattern
)
5512 unsigned const char *upat
= pattern
;
5513 char *backtrack_pos
= 0;
5514 const char *backtrack_error
= 0;
5515 int i
, val
, backtrack_index
= 0;
5516 enum arm_reg_type rtype
;
5517 parse_operand_result result
;
5519 #define po_char_or_fail(chr) do { \
5520 if (skip_past_char (&str, chr) == FAIL) \
5524 #define po_reg_or_fail(regtype) do { \
5525 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5526 &inst.operands[i].vectype); \
5529 first_error (_(reg_expected_msgs[regtype])); \
5532 inst.operands[i].reg = val; \
5533 inst.operands[i].isreg = 1; \
5534 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5535 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5536 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5537 || rtype == REG_TYPE_VFD \
5538 || rtype == REG_TYPE_NQ); \
5541 #define po_reg_or_goto(regtype, label) do { \
5542 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5543 &inst.operands[i].vectype); \
5547 inst.operands[i].reg = val; \
5548 inst.operands[i].isreg = 1; \
5549 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5550 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5551 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5552 || rtype == REG_TYPE_VFD \
5553 || rtype == REG_TYPE_NQ); \
5556 #define po_imm_or_fail(min, max, popt) do { \
5557 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5559 inst.operands[i].imm = val; \
5562 #define po_scalar_or_goto(elsz, label) do { \
5563 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5566 inst.operands[i].reg = val; \
5567 inst.operands[i].isscalar = 1; \
5570 #define po_misc_or_fail(expr) do { \
5575 #define po_misc_or_fail_no_backtrack(expr) do { \
5577 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5578 backtrack_pos = 0; \
5579 if (result != PARSE_OPERAND_SUCCESS) \
5583 skip_whitespace (str
);
5585 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5587 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5589 /* Remember where we are in case we need to backtrack. */
5590 assert (!backtrack_pos
);
5591 backtrack_pos
= str
;
5592 backtrack_error
= inst
.error
;
5593 backtrack_index
= i
;
5596 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5597 po_char_or_fail (',');
5605 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5606 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5607 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5608 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5609 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5610 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5612 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5614 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
5616 /* Also accept generic coprocessor regs for unknown registers. */
5618 po_reg_or_fail (REG_TYPE_CN
);
5620 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5621 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5622 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5623 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5624 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5625 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5626 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5627 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5628 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5629 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5631 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5633 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5634 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5636 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5638 /* Neon scalar. Using an element size of 8 means that some invalid
5639 scalars are accepted here, so deal with those in later code. */
5640 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5642 /* WARNING: We can expand to two operands here. This has the potential
5643 to totally confuse the backtracking mechanism! It will be OK at
5644 least as long as we don't try to use optional args as well,
5648 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
5649 inst
.operands
[i
].present
= 1;
5651 skip_past_comma (&str
);
5652 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
5655 /* Optional register operand was omitted. Unfortunately, it's in
5656 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5657 here (this is a bit grotty). */
5658 inst
.operands
[i
] = inst
.operands
[i
-1];
5659 inst
.operands
[i
-1].present
= 0;
5662 /* There's a possibility of getting a 64-bit immediate here, so
5663 we need special handling. */
5664 if (parse_big_immediate (&str
, i
) == FAIL
)
5666 inst
.error
= _("immediate value is out of range");
5674 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
5677 po_imm_or_fail (0, 0, TRUE
);
5682 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
5687 po_scalar_or_goto (8, try_rr
);
5690 po_reg_or_fail (REG_TYPE_RN
);
5696 po_scalar_or_goto (8, try_nsdq
);
5699 po_reg_or_fail (REG_TYPE_NSDQ
);
5705 po_scalar_or_goto (8, try_ndq
);
5708 po_reg_or_fail (REG_TYPE_NDQ
);
5714 po_scalar_or_goto (8, try_vfd
);
5717 po_reg_or_fail (REG_TYPE_VFD
);
5722 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5723 not careful then bad things might happen. */
5724 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
5729 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
5732 /* There's a possibility of getting a 64-bit immediate here, so
5733 we need special handling. */
5734 if (parse_big_immediate (&str
, i
) == FAIL
)
5736 inst
.error
= _("immediate value is out of range");
5744 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
5747 po_imm_or_fail (0, 63, TRUE
);
5752 po_char_or_fail ('[');
5753 po_reg_or_fail (REG_TYPE_RN
);
5754 po_char_or_fail (']');
5759 po_reg_or_fail (REG_TYPE_RN
);
5760 if (skip_past_char (&str
, '!') == SUCCESS
)
5761 inst
.operands
[i
].writeback
= 1;
5765 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
5766 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
5767 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
5768 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
5769 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
5770 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
5771 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
5772 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
5773 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
5774 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
5775 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
5776 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
5778 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
5780 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
5781 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
5783 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
5784 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
5785 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
5787 /* Immediate variants */
5789 po_char_or_fail ('{');
5790 po_imm_or_fail (0, 255, TRUE
);
5791 po_char_or_fail ('}');
5795 /* The expression parser chokes on a trailing !, so we have
5796 to find it first and zap it. */
5799 while (*s
&& *s
!= ',')
5804 inst
.operands
[i
].writeback
= 1;
5806 po_imm_or_fail (0, 31, TRUE
);
5814 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5819 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5824 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5826 if (inst
.reloc
.exp
.X_op
== O_symbol
)
5828 val
= parse_reloc (&str
);
5831 inst
.error
= _("unrecognized relocation suffix");
5834 else if (val
!= BFD_RELOC_UNUSED
)
5836 inst
.operands
[i
].imm
= val
;
5837 inst
.operands
[i
].hasreloc
= 1;
5842 /* Operand for MOVW or MOVT. */
5844 po_misc_or_fail (parse_half (&str
));
5847 /* Register or expression */
5848 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
5849 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
5851 /* Register or immediate */
5852 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
5853 I0
: po_imm_or_fail (0, 0, FALSE
); break;
5855 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
5857 if (!is_immediate_prefix (*str
))
5860 val
= parse_fpa_immediate (&str
);
5863 /* FPA immediates are encoded as registers 8-15.
5864 parse_fpa_immediate has already applied the offset. */
5865 inst
.operands
[i
].reg
= val
;
5866 inst
.operands
[i
].isreg
= 1;
5869 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
5870 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
5872 /* Two kinds of register */
5875 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5877 || (rege
->type
!= REG_TYPE_MMXWR
5878 && rege
->type
!= REG_TYPE_MMXWC
5879 && rege
->type
!= REG_TYPE_MMXWCG
))
5881 inst
.error
= _("iWMMXt data or control register expected");
5884 inst
.operands
[i
].reg
= rege
->number
;
5885 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
5891 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5893 || (rege
->type
!= REG_TYPE_MMXWC
5894 && rege
->type
!= REG_TYPE_MMXWCG
))
5896 inst
.error
= _("iWMMXt control register expected");
5899 inst
.operands
[i
].reg
= rege
->number
;
5900 inst
.operands
[i
].isreg
= 1;
5905 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
5906 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
5907 case OP_oROR
: val
= parse_ror (&str
); break;
5908 case OP_PSR
: val
= parse_psr (&str
); break;
5909 case OP_COND
: val
= parse_cond (&str
); break;
5910 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
5913 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
5914 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
5917 val
= parse_psr (&str
);
5921 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
5924 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5926 if (strncasecmp (str
, "APSR_", 5) == 0)
5933 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
5934 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
5935 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
5936 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
5937 default: found
= 16;
5941 inst
.operands
[i
].isvec
= 1;
5948 po_misc_or_fail (parse_tb (&str
));
5951 /* Register lists */
5953 val
= parse_reg_list (&str
);
5956 inst
.operands
[1].writeback
= 1;
5962 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
5966 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
5970 /* Allow Q registers too. */
5971 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5976 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5978 inst
.operands
[i
].issingle
= 1;
5983 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5988 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
5989 &inst
.operands
[i
].vectype
);
5992 /* Addressing modes */
5994 po_misc_or_fail (parse_address (&str
, i
));
5998 po_misc_or_fail_no_backtrack (
5999 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6003 po_misc_or_fail_no_backtrack (
6004 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6008 po_misc_or_fail_no_backtrack (
6009 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6013 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6017 po_misc_or_fail_no_backtrack (
6018 parse_shifter_operand_group_reloc (&str
, i
));
6022 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6026 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6030 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6034 as_fatal (_("unhandled operand code %d"), upat
[i
]);
6037 /* Various value-based sanity checks and shared operations. We
6038 do not signal immediate failures for the register constraints;
6039 this allows a syntax error to take precedence. */
6048 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6049 inst
.error
= BAD_PC
;
6067 inst
.operands
[i
].imm
= val
;
6074 /* If we get here, this operand was successfully parsed. */
6075 inst
.operands
[i
].present
= 1;
6079 inst
.error
= BAD_ARGS
;
6084 /* The parse routine should already have set inst.error, but set a
6085 default here just in case. */
6087 inst
.error
= _("syntax error");
6091 /* Do not backtrack over a trailing optional argument that
6092 absorbed some text. We will only fail again, with the
6093 'garbage following instruction' error message, which is
6094 probably less helpful than the current one. */
6095 if (backtrack_index
== i
&& backtrack_pos
!= str
6096 && upat
[i
+1] == OP_stop
)
6099 inst
.error
= _("syntax error");
6103 /* Try again, skipping the optional argument at backtrack_pos. */
6104 str
= backtrack_pos
;
6105 inst
.error
= backtrack_error
;
6106 inst
.operands
[backtrack_index
].present
= 0;
6107 i
= backtrack_index
;
6111 /* Check that we have parsed all the arguments. */
6112 if (*str
!= '\0' && !inst
.error
)
6113 inst
.error
= _("garbage following instruction");
6115 return inst
.error
? FAIL
: SUCCESS
;
6118 #undef po_char_or_fail
6119 #undef po_reg_or_fail
6120 #undef po_reg_or_goto
6121 #undef po_imm_or_fail
6122 #undef po_scalar_or_fail
6124 /* Shorthand macro for instruction encoding functions issuing errors. */
6125 #define constraint(expr, err) do { \
6133 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6134 instructions are unpredictable if these registers are used. This
6135 is the BadReg predicate in ARM's Thumb-2 documentation. */
6136 #define reject_bad_reg(reg) \
6138 if (reg == REG_SP || reg == REG_PC) \
6140 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6145 /* If REG is R13 (the stack pointer), warn that its use is
6147 #define warn_deprecated_sp(reg) \
6149 if (warn_on_deprecated && reg == REG_SP) \
6150 as_warn (_("use of r13 is deprecated")); \
6153 /* Functions for operand encoding. ARM, then Thumb. */
6155 #define rotate_left(v, n) (v << n | v >> (32 - n))
6157 /* If VAL can be encoded in the immediate field of an ARM instruction,
6158 return the encoded form. Otherwise, return FAIL. */
6161 encode_arm_immediate (unsigned int val
)
6165 for (i
= 0; i
< 32; i
+= 2)
6166 if ((a
= rotate_left (val
, i
)) <= 0xff)
6167 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6172 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6173 return the encoded form. Otherwise, return FAIL. */
6175 encode_thumb32_immediate (unsigned int val
)
6182 for (i
= 1; i
<= 24; i
++)
6185 if ((val
& ~(0xff << i
)) == 0)
6186 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6190 if (val
== ((a
<< 16) | a
))
6192 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6196 if (val
== ((a
<< 16) | a
))
6197 return 0x200 | (a
>> 8);
6201 /* Encode a VFP SP or DP register number into inst.instruction. */
6204 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6206 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6209 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6212 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6215 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6220 first_error (_("D register out of range for selected VFP version"));
6228 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6232 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6236 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6240 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6244 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6248 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6256 /* Encode a <shift> in an ARM-format instruction. The immediate,
6257 if any, is handled by md_apply_fix. */
6259 encode_arm_shift (int i
)
6261 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6262 inst
.instruction
|= SHIFT_ROR
<< 5;
6265 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6266 if (inst
.operands
[i
].immisreg
)
6268 inst
.instruction
|= SHIFT_BY_REG
;
6269 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6272 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6277 encode_arm_shifter_operand (int i
)
6279 if (inst
.operands
[i
].isreg
)
6281 inst
.instruction
|= inst
.operands
[i
].reg
;
6282 encode_arm_shift (i
);
6285 inst
.instruction
|= INST_IMMEDIATE
;
6288 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6290 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6292 assert (inst
.operands
[i
].isreg
);
6293 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6295 if (inst
.operands
[i
].preind
)
6299 inst
.error
= _("instruction does not accept preindexed addressing");
6302 inst
.instruction
|= PRE_INDEX
;
6303 if (inst
.operands
[i
].writeback
)
6304 inst
.instruction
|= WRITE_BACK
;
6307 else if (inst
.operands
[i
].postind
)
6309 assert (inst
.operands
[i
].writeback
);
6311 inst
.instruction
|= WRITE_BACK
;
6313 else /* unindexed - only for coprocessor */
6315 inst
.error
= _("instruction does not accept unindexed addressing");
6319 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6320 && (((inst
.instruction
& 0x000f0000) >> 16)
6321 == ((inst
.instruction
& 0x0000f000) >> 12)))
6322 as_warn ((inst
.instruction
& LOAD_BIT
)
6323 ? _("destination register same as write-back base")
6324 : _("source register same as write-back base"));
6327 /* inst.operands[i] was set up by parse_address. Encode it into an
6328 ARM-format mode 2 load or store instruction. If is_t is true,
6329 reject forms that cannot be used with a T instruction (i.e. not
6332 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6334 encode_arm_addr_mode_common (i
, is_t
);
6336 if (inst
.operands
[i
].immisreg
)
6338 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6339 inst
.instruction
|= inst
.operands
[i
].imm
;
6340 if (!inst
.operands
[i
].negative
)
6341 inst
.instruction
|= INDEX_UP
;
6342 if (inst
.operands
[i
].shifted
)
6344 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6345 inst
.instruction
|= SHIFT_ROR
<< 5;
6348 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6349 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6353 else /* immediate offset in inst.reloc */
6355 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6356 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6360 /* inst.operands[i] was set up by parse_address. Encode it into an
6361 ARM-format mode 3 load or store instruction. Reject forms that
6362 cannot be used with such instructions. If is_t is true, reject
6363 forms that cannot be used with a T instruction (i.e. not
6366 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6368 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6370 inst
.error
= _("instruction does not accept scaled register index");
6374 encode_arm_addr_mode_common (i
, is_t
);
6376 if (inst
.operands
[i
].immisreg
)
6378 inst
.instruction
|= inst
.operands
[i
].imm
;
6379 if (!inst
.operands
[i
].negative
)
6380 inst
.instruction
|= INDEX_UP
;
6382 else /* immediate offset in inst.reloc */
6384 inst
.instruction
|= HWOFFSET_IMM
;
6385 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6386 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6390 /* inst.operands[i] was set up by parse_address. Encode it into an
6391 ARM-format instruction. Reject all forms which cannot be encoded
6392 into a coprocessor load/store instruction. If wb_ok is false,
6393 reject use of writeback; if unind_ok is false, reject use of
6394 unindexed addressing. If reloc_override is not 0, use it instead
6395 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6396 (in which case it is preserved). */
6399 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6401 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6403 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6405 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6407 assert (!inst
.operands
[i
].writeback
);
6410 inst
.error
= _("instruction does not support unindexed addressing");
6413 inst
.instruction
|= inst
.operands
[i
].imm
;
6414 inst
.instruction
|= INDEX_UP
;
6418 if (inst
.operands
[i
].preind
)
6419 inst
.instruction
|= PRE_INDEX
;
6421 if (inst
.operands
[i
].writeback
)
6423 if (inst
.operands
[i
].reg
== REG_PC
)
6425 inst
.error
= _("pc may not be used with write-back");
6430 inst
.error
= _("instruction does not support writeback");
6433 inst
.instruction
|= WRITE_BACK
;
6437 inst
.reloc
.type
= reloc_override
;
6438 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6439 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6440 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6443 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6445 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6451 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6452 Determine whether it can be performed with a move instruction; if
6453 it can, convert inst.instruction to that move instruction and
6454 return 1; if it can't, convert inst.instruction to a literal-pool
6455 load and return 0. If this is not a valid thing to do in the
6456 current context, set inst.error and return 1.
6458 inst.operands[i] describes the destination register. */
6461 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6466 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6470 if ((inst
.instruction
& tbit
) == 0)
6472 inst
.error
= _("invalid pseudo operation");
6475 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6477 inst
.error
= _("constant expression expected");
6480 if (inst
.reloc
.exp
.X_op
== O_constant
)
6484 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6486 /* This can be done with a mov(1) instruction. */
6487 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6488 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6494 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6497 /* This can be done with a mov instruction. */
6498 inst
.instruction
&= LITERAL_MASK
;
6499 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6500 inst
.instruction
|= value
& 0xfff;
6504 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6507 /* This can be done with a mvn instruction. */
6508 inst
.instruction
&= LITERAL_MASK
;
6509 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6510 inst
.instruction
|= value
& 0xfff;
6516 if (add_to_lit_pool () == FAIL
)
6518 inst
.error
= _("literal pool insertion failed");
6521 inst
.operands
[1].reg
= REG_PC
;
6522 inst
.operands
[1].isreg
= 1;
6523 inst
.operands
[1].preind
= 1;
6524 inst
.reloc
.pc_rel
= 1;
6525 inst
.reloc
.type
= (thumb_p
6526 ? BFD_RELOC_ARM_THUMB_OFFSET
6528 ? BFD_RELOC_ARM_HWLITERAL
6529 : BFD_RELOC_ARM_LITERAL
));
6533 /* Functions for instruction encoding, sorted by sub-architecture.
6534 First some generics; their names are taken from the conventional
6535 bit positions for register arguments in ARM format instructions. */
6545 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6551 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6552 inst
.instruction
|= inst
.operands
[1].reg
;
6558 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6559 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6565 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6566 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6572 unsigned Rn
= inst
.operands
[2].reg
;
6573 /* Enforce restrictions on SWP instruction. */
6574 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6575 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6576 _("Rn must not overlap other operands"));
6577 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6578 inst
.instruction
|= inst
.operands
[1].reg
;
6579 inst
.instruction
|= Rn
<< 16;
6585 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6586 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6587 inst
.instruction
|= inst
.operands
[2].reg
;
6593 inst
.instruction
|= inst
.operands
[0].reg
;
6594 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6595 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6601 inst
.instruction
|= inst
.operands
[0].imm
;
6607 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6608 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6611 /* ARM instructions, in alphabetical order by function name (except
6612 that wrapper functions appear immediately after the function they
6615 /* This is a pseudo-op of the form "adr rd, label" to be converted
6616 into a relative address of the form "add rd, pc, #label-.-8". */
6621 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6623 /* Frag hacking will turn this into a sub instruction if the offset turns
6624 out to be negative. */
6625 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6626 inst
.reloc
.pc_rel
= 1;
6627 inst
.reloc
.exp
.X_add_number
-= 8;
6630 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6631 into a relative address of the form:
6632 add rd, pc, #low(label-.-8)"
6633 add rd, rd, #high(label-.-8)" */
6638 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6640 /* Frag hacking will turn this into a sub instruction if the offset turns
6641 out to be negative. */
6642 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6643 inst
.reloc
.pc_rel
= 1;
6644 inst
.size
= INSN_SIZE
* 2;
6645 inst
.reloc
.exp
.X_add_number
-= 8;
6651 if (!inst
.operands
[1].present
)
6652 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6653 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6654 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6655 encode_arm_shifter_operand (2);
6661 if (inst
.operands
[0].present
)
6663 constraint ((inst
.instruction
& 0xf0) != 0x40
6664 && inst
.operands
[0].imm
!= 0xf,
6665 _("bad barrier type"));
6666 inst
.instruction
|= inst
.operands
[0].imm
;
6669 inst
.instruction
|= 0xf;
6675 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6676 constraint (msb
> 32, _("bit-field extends past end of register"));
6677 /* The instruction encoding stores the LSB and MSB,
6678 not the LSB and width. */
6679 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6680 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
6681 inst
.instruction
|= (msb
- 1) << 16;
6689 /* #0 in second position is alternative syntax for bfc, which is
6690 the same instruction but with REG_PC in the Rm field. */
6691 if (!inst
.operands
[1].isreg
)
6692 inst
.operands
[1].reg
= REG_PC
;
6694 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6695 constraint (msb
> 32, _("bit-field extends past end of register"));
6696 /* The instruction encoding stores the LSB and MSB,
6697 not the LSB and width. */
6698 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6699 inst
.instruction
|= inst
.operands
[1].reg
;
6700 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6701 inst
.instruction
|= (msb
- 1) << 16;
6707 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6708 _("bit-field extends past end of register"));
6709 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6710 inst
.instruction
|= inst
.operands
[1].reg
;
6711 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6712 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
6715 /* ARM V5 breakpoint instruction (argument parse)
6716 BKPT <16 bit unsigned immediate>
6717 Instruction is not conditional.
6718 The bit pattern given in insns[] has the COND_ALWAYS condition,
6719 and it is an error if the caller tried to override that. */
6724 /* Top 12 of 16 bits to bits 19:8. */
6725 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
6727 /* Bottom 4 of 16 bits to bits 3:0. */
6728 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
6732 encode_branch (int default_reloc
)
6734 if (inst
.operands
[0].hasreloc
)
6736 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
6737 _("the only suffix valid here is '(plt)'"));
6738 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
6742 inst
.reloc
.type
= default_reloc
;
6744 inst
.reloc
.pc_rel
= 1;
6751 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6752 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6755 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6762 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6764 if (inst
.cond
== COND_ALWAYS
)
6765 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6767 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6771 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6774 /* ARM V5 branch-link-exchange instruction (argument parse)
6775 BLX <target_addr> ie BLX(1)
6776 BLX{<condition>} <Rm> ie BLX(2)
6777 Unfortunately, there are two different opcodes for this mnemonic.
6778 So, the insns[].value is not used, and the code here zaps values
6779 into inst.instruction.
6780 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6785 if (inst
.operands
[0].isreg
)
6787 /* Arg is a register; the opcode provided by insns[] is correct.
6788 It is not illegal to do "blx pc", just useless. */
6789 if (inst
.operands
[0].reg
== REG_PC
)
6790 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6792 inst
.instruction
|= inst
.operands
[0].reg
;
6796 /* Arg is an address; this instruction cannot be executed
6797 conditionally, and the opcode must be adjusted.
6798 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
6799 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
6800 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
6801 inst
.instruction
= 0xfa000000;
6802 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
6809 bfd_boolean want_reloc
;
6811 if (inst
.operands
[0].reg
== REG_PC
)
6812 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6814 inst
.instruction
|= inst
.operands
[0].reg
;
6815 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
6816 it is for ARMv4t or earlier. */
6817 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
6818 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
6822 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
6827 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
6831 /* ARM v5TEJ. Jump to Jazelle code. */
6836 if (inst
.operands
[0].reg
== REG_PC
)
6837 as_tsktsk (_("use of r15 in bxj is not really useful"));
6839 inst
.instruction
|= inst
.operands
[0].reg
;
6842 /* Co-processor data operation:
6843 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6844 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6848 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6849 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
6850 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6851 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6852 inst
.instruction
|= inst
.operands
[4].reg
;
6853 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6859 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6860 encode_arm_shifter_operand (1);
6863 /* Transfer between coprocessor and ARM registers.
6864 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6869 No special properties. */
6876 Rd
= inst
.operands
[2].reg
;
6879 if (inst
.instruction
== 0xee000010
6880 || inst
.instruction
== 0xfe000010)
6882 reject_bad_reg (Rd
);
6885 constraint (Rd
== REG_SP
, BAD_SP
);
6890 if (inst
.instruction
== 0xe000010)
6891 constraint (Rd
== REG_PC
, BAD_PC
);
6895 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6896 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
6897 inst
.instruction
|= Rd
<< 12;
6898 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6899 inst
.instruction
|= inst
.operands
[4].reg
;
6900 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6903 /* Transfer between coprocessor register and pair of ARM registers.
6904 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6909 Two XScale instructions are special cases of these:
6911 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6912 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6914 Result unpredictable if Rd or Rn is R15. */
6921 Rd
= inst
.operands
[2].reg
;
6922 Rn
= inst
.operands
[3].reg
;
6926 reject_bad_reg (Rd
);
6927 reject_bad_reg (Rn
);
6931 constraint (Rd
== REG_PC
, BAD_PC
);
6932 constraint (Rn
== REG_PC
, BAD_PC
);
6935 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6936 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
6937 inst
.instruction
|= Rd
<< 12;
6938 inst
.instruction
|= Rn
<< 16;
6939 inst
.instruction
|= inst
.operands
[4].reg
;
6945 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
6946 if (inst
.operands
[1].present
)
6948 inst
.instruction
|= CPSI_MMOD
;
6949 inst
.instruction
|= inst
.operands
[1].imm
;
6956 inst
.instruction
|= inst
.operands
[0].imm
;
6962 /* There is no IT instruction in ARM mode. We
6963 process it but do not generate code for it. */
6970 int base_reg
= inst
.operands
[0].reg
;
6971 int range
= inst
.operands
[1].imm
;
6973 inst
.instruction
|= base_reg
<< 16;
6974 inst
.instruction
|= range
;
6976 if (inst
.operands
[1].writeback
)
6977 inst
.instruction
|= LDM_TYPE_2_OR_3
;
6979 if (inst
.operands
[0].writeback
)
6981 inst
.instruction
|= WRITE_BACK
;
6982 /* Check for unpredictable uses of writeback. */
6983 if (inst
.instruction
& LOAD_BIT
)
6985 /* Not allowed in LDM type 2. */
6986 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
6987 && ((range
& (1 << REG_PC
)) == 0))
6988 as_warn (_("writeback of base register is UNPREDICTABLE"));
6989 /* Only allowed if base reg not in list for other types. */
6990 else if (range
& (1 << base_reg
))
6991 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6995 /* Not allowed for type 2. */
6996 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
6997 as_warn (_("writeback of base register is UNPREDICTABLE"));
6998 /* Only allowed if base reg not in list, or first in list. */
6999 else if ((range
& (1 << base_reg
))
7000 && (range
& ((1 << base_reg
) - 1)))
7001 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7006 /* ARMv5TE load-consecutive (argument parse)
7015 constraint (inst
.operands
[0].reg
% 2 != 0,
7016 _("first destination register must be even"));
7017 constraint (inst
.operands
[1].present
7018 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7019 _("can only load two consecutive registers"));
7020 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7021 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7023 if (!inst
.operands
[1].present
)
7024 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7026 if (inst
.instruction
& LOAD_BIT
)
7028 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7029 register and the first register written; we have to diagnose
7030 overlap between the base and the second register written here. */
7032 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7033 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7034 as_warn (_("base register written back, and overlaps "
7035 "second destination register"));
7037 /* For an index-register load, the index register must not overlap the
7038 destination (even if not write-back). */
7039 else if (inst
.operands
[2].immisreg
7040 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7041 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7042 as_warn (_("index register overlaps destination register"));
7045 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7046 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7052 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7053 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7054 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7055 || inst
.operands
[1].negative
7056 /* This can arise if the programmer has written
7058 or if they have mistakenly used a register name as the last
7061 It is very difficult to distinguish between these two cases
7062 because "rX" might actually be a label. ie the register
7063 name has been occluded by a symbol of the same name. So we
7064 just generate a general 'bad addressing mode' type error
7065 message and leave it up to the programmer to discover the
7066 true cause and fix their mistake. */
7067 || (inst
.operands
[1].reg
== REG_PC
),
7070 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7071 || inst
.reloc
.exp
.X_add_number
!= 0,
7072 _("offset must be zero in ARM encoding"));
7074 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7075 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7076 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7082 constraint (inst
.operands
[0].reg
% 2 != 0,
7083 _("even register required"));
7084 constraint (inst
.operands
[1].present
7085 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7086 _("can only load two consecutive registers"));
7087 /* If op 1 were present and equal to PC, this function wouldn't
7088 have been called in the first place. */
7089 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7091 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7092 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7098 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7099 if (!inst
.operands
[1].isreg
)
7100 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7102 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7108 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7110 if (inst
.operands
[1].preind
)
7112 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7113 || inst
.reloc
.exp
.X_add_number
!= 0,
7114 _("this instruction requires a post-indexed address"));
7116 inst
.operands
[1].preind
= 0;
7117 inst
.operands
[1].postind
= 1;
7118 inst
.operands
[1].writeback
= 1;
7120 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7121 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7124 /* Halfword and signed-byte load/store operations. */
7129 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7130 if (!inst
.operands
[1].isreg
)
7131 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7133 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7139 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7141 if (inst
.operands
[1].preind
)
7143 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7144 || inst
.reloc
.exp
.X_add_number
!= 0,
7145 _("this instruction requires a post-indexed address"));
7147 inst
.operands
[1].preind
= 0;
7148 inst
.operands
[1].postind
= 1;
7149 inst
.operands
[1].writeback
= 1;
7151 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7152 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7155 /* Co-processor register load/store.
7156 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7160 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7161 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7162 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7168 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7169 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7170 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7171 && !(inst
.instruction
& 0x00400000))
7172 as_tsktsk (_("Rd and Rm should be different in mla"));
7174 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7175 inst
.instruction
|= inst
.operands
[1].reg
;
7176 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7177 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7183 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7184 encode_arm_shifter_operand (1);
7187 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7194 top
= (inst
.instruction
& 0x00400000) != 0;
7195 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7196 _(":lower16: not allowed this instruction"));
7197 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7198 _(":upper16: not allowed instruction"));
7199 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7200 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7202 imm
= inst
.reloc
.exp
.X_add_number
;
7203 /* The value is in two pieces: 0:11, 16:19. */
7204 inst
.instruction
|= (imm
& 0x00000fff);
7205 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7209 static void do_vfp_nsyn_opcode (const char *);
7212 do_vfp_nsyn_mrs (void)
7214 if (inst
.operands
[0].isvec
)
7216 if (inst
.operands
[1].reg
!= 1)
7217 first_error (_("operand 1 must be FPSCR"));
7218 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7219 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7220 do_vfp_nsyn_opcode ("fmstat");
7222 else if (inst
.operands
[1].isvec
)
7223 do_vfp_nsyn_opcode ("fmrx");
7231 do_vfp_nsyn_msr (void)
7233 if (inst
.operands
[0].isvec
)
7234 do_vfp_nsyn_opcode ("fmxr");
7244 if (do_vfp_nsyn_mrs () == SUCCESS
)
7247 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7248 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7250 _("'CPSR' or 'SPSR' expected"));
7251 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7252 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7255 /* Two possible forms:
7256 "{C|S}PSR_<field>, Rm",
7257 "{C|S}PSR_f, #expression". */
7262 if (do_vfp_nsyn_msr () == SUCCESS
)
7265 inst
.instruction
|= inst
.operands
[0].imm
;
7266 if (inst
.operands
[1].isreg
)
7267 inst
.instruction
|= inst
.operands
[1].reg
;
7270 inst
.instruction
|= INST_IMMEDIATE
;
7271 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7272 inst
.reloc
.pc_rel
= 0;
7279 if (!inst
.operands
[2].present
)
7280 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7281 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7282 inst
.instruction
|= inst
.operands
[1].reg
;
7283 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7285 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7286 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7287 as_tsktsk (_("Rd and Rm should be different in mul"));
7290 /* Long Multiply Parser
7291 UMULL RdLo, RdHi, Rm, Rs
7292 SMULL RdLo, RdHi, Rm, Rs
7293 UMLAL RdLo, RdHi, Rm, Rs
7294 SMLAL RdLo, RdHi, Rm, Rs. */
7299 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7300 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7301 inst
.instruction
|= inst
.operands
[2].reg
;
7302 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7304 /* rdhi and rdlo must be different. */
7305 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7306 as_tsktsk (_("rdhi and rdlo must be different"));
7308 /* rdhi, rdlo and rm must all be different before armv6. */
7309 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7310 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7311 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7312 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7318 if (inst
.operands
[0].present
7319 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7321 /* Architectural NOP hints are CPSR sets with no bits selected. */
7322 inst
.instruction
&= 0xf0000000;
7323 inst
.instruction
|= 0x0320f000;
7324 if (inst
.operands
[0].present
)
7325 inst
.instruction
|= inst
.operands
[0].imm
;
7329 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7330 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7331 Condition defaults to COND_ALWAYS.
7332 Error if Rd, Rn or Rm are R15. */
7337 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7338 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7339 inst
.instruction
|= inst
.operands
[2].reg
;
7340 if (inst
.operands
[3].present
)
7341 encode_arm_shift (3);
7344 /* ARM V6 PKHTB (Argument Parse). */
7349 if (!inst
.operands
[3].present
)
7351 /* If the shift specifier is omitted, turn the instruction
7352 into pkhbt rd, rm, rn. */
7353 inst
.instruction
&= 0xfff00010;
7354 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7355 inst
.instruction
|= inst
.operands
[1].reg
;
7356 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7360 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7361 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7362 inst
.instruction
|= inst
.operands
[2].reg
;
7363 encode_arm_shift (3);
7367 /* ARMv5TE: Preload-Cache
7371 Syntactically, like LDR with B=1, W=0, L=1. */
7376 constraint (!inst
.operands
[0].isreg
,
7377 _("'[' expected after PLD mnemonic"));
7378 constraint (inst
.operands
[0].postind
,
7379 _("post-indexed expression used in preload instruction"));
7380 constraint (inst
.operands
[0].writeback
,
7381 _("writeback used in preload instruction"));
7382 constraint (!inst
.operands
[0].preind
,
7383 _("unindexed addressing used in preload instruction"));
7384 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7387 /* ARMv7: PLI <addr_mode> */
7391 constraint (!inst
.operands
[0].isreg
,
7392 _("'[' expected after PLI mnemonic"));
7393 constraint (inst
.operands
[0].postind
,
7394 _("post-indexed expression used in preload instruction"));
7395 constraint (inst
.operands
[0].writeback
,
7396 _("writeback used in preload instruction"));
7397 constraint (!inst
.operands
[0].preind
,
7398 _("unindexed addressing used in preload instruction"));
7399 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7400 inst
.instruction
&= ~PRE_INDEX
;
7406 inst
.operands
[1] = inst
.operands
[0];
7407 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7408 inst
.operands
[0].isreg
= 1;
7409 inst
.operands
[0].writeback
= 1;
7410 inst
.operands
[0].reg
= REG_SP
;
7414 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7415 word at the specified address and the following word
7417 Unconditionally executed.
7418 Error if Rn is R15. */
7423 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7424 if (inst
.operands
[0].writeback
)
7425 inst
.instruction
|= WRITE_BACK
;
7428 /* ARM V6 ssat (argument parse). */
7433 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7434 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7435 inst
.instruction
|= inst
.operands
[2].reg
;
7437 if (inst
.operands
[3].present
)
7438 encode_arm_shift (3);
7441 /* ARM V6 usat (argument parse). */
7446 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7447 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7448 inst
.instruction
|= inst
.operands
[2].reg
;
7450 if (inst
.operands
[3].present
)
7451 encode_arm_shift (3);
7454 /* ARM V6 ssat16 (argument parse). */
7459 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7460 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7461 inst
.instruction
|= inst
.operands
[2].reg
;
7467 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7468 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7469 inst
.instruction
|= inst
.operands
[2].reg
;
7472 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7473 preserving the other bits.
7475 setend <endian_specifier>, where <endian_specifier> is either
7481 if (inst
.operands
[0].imm
)
7482 inst
.instruction
|= 0x200;
7488 unsigned int Rm
= (inst
.operands
[1].present
7489 ? inst
.operands
[1].reg
7490 : inst
.operands
[0].reg
);
7492 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7493 inst
.instruction
|= Rm
;
7494 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7496 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7497 inst
.instruction
|= SHIFT_BY_REG
;
7500 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7506 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7507 inst
.reloc
.pc_rel
= 0;
7513 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7514 inst
.reloc
.pc_rel
= 0;
7517 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7518 SMLAxy{cond} Rd,Rm,Rs,Rn
7519 SMLAWy{cond} Rd,Rm,Rs,Rn
7520 Error if any register is R15. */
7525 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7526 inst
.instruction
|= inst
.operands
[1].reg
;
7527 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7528 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7531 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7532 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7533 Error if any register is R15.
7534 Warning if Rdlo == Rdhi. */
7539 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7540 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7541 inst
.instruction
|= inst
.operands
[2].reg
;
7542 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7544 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7545 as_tsktsk (_("rdhi and rdlo must be different"));
7548 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7549 SMULxy{cond} Rd,Rm,Rs
7550 Error if any register is R15. */
7555 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7556 inst
.instruction
|= inst
.operands
[1].reg
;
7557 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7560 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7561 the same for both ARM and Thumb-2. */
7568 if (inst
.operands
[0].present
)
7570 reg
= inst
.operands
[0].reg
;
7571 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
7576 inst
.instruction
|= reg
<< 16;
7577 inst
.instruction
|= inst
.operands
[1].imm
;
7578 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
7579 inst
.instruction
|= WRITE_BACK
;
7582 /* ARM V6 strex (argument parse). */
7587 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7588 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7589 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7590 || inst
.operands
[2].negative
7591 /* See comment in do_ldrex(). */
7592 || (inst
.operands
[2].reg
== REG_PC
),
7595 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7596 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7598 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7599 || inst
.reloc
.exp
.X_add_number
!= 0,
7600 _("offset must be zero in ARM encoding"));
7602 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7603 inst
.instruction
|= inst
.operands
[1].reg
;
7604 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7605 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7611 constraint (inst
.operands
[1].reg
% 2 != 0,
7612 _("even register required"));
7613 constraint (inst
.operands
[2].present
7614 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7615 _("can only store two consecutive registers"));
7616 /* If op 2 were present and equal to PC, this function wouldn't
7617 have been called in the first place. */
7618 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7620 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7621 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7622 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7625 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7626 inst
.instruction
|= inst
.operands
[1].reg
;
7627 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7630 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7631 extends it to 32-bits, and adds the result to a value in another
7632 register. You can specify a rotation by 0, 8, 16, or 24 bits
7633 before extracting the 16-bit value.
7634 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7635 Condition defaults to COND_ALWAYS.
7636 Error if any register uses R15. */
7641 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7642 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7643 inst
.instruction
|= inst
.operands
[2].reg
;
7644 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
7649 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7650 Condition defaults to COND_ALWAYS.
7651 Error if any register uses R15. */
7656 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7657 inst
.instruction
|= inst
.operands
[1].reg
;
7658 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
7661 /* VFP instructions. In a logical order: SP variant first, monad
7662 before dyad, arithmetic then move then load/store. */
7665 do_vfp_sp_monadic (void)
7667 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7668 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7672 do_vfp_sp_dyadic (void)
7674 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7675 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7676 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7680 do_vfp_sp_compare_z (void)
7682 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7686 do_vfp_dp_sp_cvt (void)
7688 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7689 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7693 do_vfp_sp_dp_cvt (void)
7695 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7696 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7700 do_vfp_reg_from_sp (void)
7702 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7703 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7707 do_vfp_reg2_from_sp2 (void)
7709 constraint (inst
.operands
[2].imm
!= 2,
7710 _("only two consecutive VFP SP registers allowed here"));
7711 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7712 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7713 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7717 do_vfp_sp_from_reg (void)
7719 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
7720 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7724 do_vfp_sp2_from_reg2 (void)
7726 constraint (inst
.operands
[0].imm
!= 2,
7727 _("only two consecutive VFP SP registers allowed here"));
7728 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
7729 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7730 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7734 do_vfp_sp_ldst (void)
7736 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7737 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7741 do_vfp_dp_ldst (void)
7743 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7744 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7749 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
7751 if (inst
.operands
[0].writeback
)
7752 inst
.instruction
|= WRITE_BACK
;
7754 constraint (ldstm_type
!= VFP_LDSTMIA
,
7755 _("this addressing mode requires base-register writeback"));
7756 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7757 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
7758 inst
.instruction
|= inst
.operands
[1].imm
;
7762 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
7766 if (inst
.operands
[0].writeback
)
7767 inst
.instruction
|= WRITE_BACK
;
7769 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
7770 _("this addressing mode requires base-register writeback"));
7772 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7773 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7775 count
= inst
.operands
[1].imm
<< 1;
7776 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
7779 inst
.instruction
|= count
;
7783 do_vfp_sp_ldstmia (void)
7785 vfp_sp_ldstm (VFP_LDSTMIA
);
7789 do_vfp_sp_ldstmdb (void)
7791 vfp_sp_ldstm (VFP_LDSTMDB
);
7795 do_vfp_dp_ldstmia (void)
7797 vfp_dp_ldstm (VFP_LDSTMIA
);
7801 do_vfp_dp_ldstmdb (void)
7803 vfp_dp_ldstm (VFP_LDSTMDB
);
7807 do_vfp_xp_ldstmia (void)
7809 vfp_dp_ldstm (VFP_LDSTMIAX
);
7813 do_vfp_xp_ldstmdb (void)
7815 vfp_dp_ldstm (VFP_LDSTMDBX
);
7819 do_vfp_dp_rd_rm (void)
7821 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7822 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7826 do_vfp_dp_rn_rd (void)
7828 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
7829 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7833 do_vfp_dp_rd_rn (void)
7835 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7836 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7840 do_vfp_dp_rd_rn_rm (void)
7842 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7843 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7844 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
7850 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7854 do_vfp_dp_rm_rd_rn (void)
7856 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
7857 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7858 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
7861 /* VFPv3 instructions. */
7863 do_vfp_sp_const (void)
7865 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7866 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7867 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7871 do_vfp_dp_const (void)
7873 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7874 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7875 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7879 vfp_conv (int srcsize
)
7881 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
7882 inst
.instruction
|= (immbits
& 1) << 5;
7883 inst
.instruction
|= (immbits
>> 1);
7887 do_vfp_sp_conv_16 (void)
7889 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7894 do_vfp_dp_conv_16 (void)
7896 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7901 do_vfp_sp_conv_32 (void)
7903 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7908 do_vfp_dp_conv_32 (void)
7910 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7914 /* FPA instructions. Also in a logical order. */
7919 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7920 inst
.instruction
|= inst
.operands
[1].reg
;
7924 do_fpa_ldmstm (void)
7926 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7927 switch (inst
.operands
[1].imm
)
7929 case 1: inst
.instruction
|= CP_T_X
; break;
7930 case 2: inst
.instruction
|= CP_T_Y
; break;
7931 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
7936 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
7938 /* The instruction specified "ea" or "fd", so we can only accept
7939 [Rn]{!}. The instruction does not really support stacking or
7940 unstacking, so we have to emulate these by setting appropriate
7941 bits and offsets. */
7942 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7943 || inst
.reloc
.exp
.X_add_number
!= 0,
7944 _("this instruction does not support indexing"));
7946 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
7947 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
7949 if (!(inst
.instruction
& INDEX_UP
))
7950 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
7952 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
7954 inst
.operands
[2].preind
= 0;
7955 inst
.operands
[2].postind
= 1;
7959 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7962 /* iWMMXt instructions: strictly in alphabetical order. */
7965 do_iwmmxt_tandorc (void)
7967 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
7971 do_iwmmxt_textrc (void)
7973 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7974 inst
.instruction
|= inst
.operands
[1].imm
;
7978 do_iwmmxt_textrm (void)
7980 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7981 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7982 inst
.instruction
|= inst
.operands
[2].imm
;
7986 do_iwmmxt_tinsr (void)
7988 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7989 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7990 inst
.instruction
|= inst
.operands
[2].imm
;
7994 do_iwmmxt_tmia (void)
7996 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7997 inst
.instruction
|= inst
.operands
[1].reg
;
7998 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8002 do_iwmmxt_waligni (void)
8004 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8005 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8006 inst
.instruction
|= inst
.operands
[2].reg
;
8007 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8011 do_iwmmxt_wmerge (void)
8013 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8014 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8015 inst
.instruction
|= inst
.operands
[2].reg
;
8016 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8020 do_iwmmxt_wmov (void)
8022 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8023 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8024 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8025 inst
.instruction
|= inst
.operands
[1].reg
;
8029 do_iwmmxt_wldstbh (void)
8032 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8034 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8036 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8037 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8041 do_iwmmxt_wldstw (void)
8043 /* RIWR_RIWC clears .isreg for a control register. */
8044 if (!inst
.operands
[0].isreg
)
8046 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8047 inst
.instruction
|= 0xf0000000;
8050 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8051 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8055 do_iwmmxt_wldstd (void)
8057 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8058 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8059 && inst
.operands
[1].immisreg
)
8061 inst
.instruction
&= ~0x1a000ff;
8062 inst
.instruction
|= (0xf << 28);
8063 if (inst
.operands
[1].preind
)
8064 inst
.instruction
|= PRE_INDEX
;
8065 if (!inst
.operands
[1].negative
)
8066 inst
.instruction
|= INDEX_UP
;
8067 if (inst
.operands
[1].writeback
)
8068 inst
.instruction
|= WRITE_BACK
;
8069 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8070 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8071 inst
.instruction
|= inst
.operands
[1].imm
;
8074 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8078 do_iwmmxt_wshufh (void)
8080 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8081 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8082 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8083 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8087 do_iwmmxt_wzero (void)
8089 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8090 inst
.instruction
|= inst
.operands
[0].reg
;
8091 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8092 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8096 do_iwmmxt_wrwrwr_or_imm5 (void)
8098 if (inst
.operands
[2].isreg
)
8101 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8102 _("immediate operand requires iWMMXt2"));
8104 if (inst
.operands
[2].imm
== 0)
8106 switch ((inst
.instruction
>> 20) & 0xf)
8112 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8113 inst
.operands
[2].imm
= 16;
8114 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8120 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8121 inst
.operands
[2].imm
= 32;
8122 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8129 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8131 wrn
= (inst
.instruction
>> 16) & 0xf;
8132 inst
.instruction
&= 0xff0fff0f;
8133 inst
.instruction
|= wrn
;
8134 /* Bail out here; the instruction is now assembled. */
8139 /* Map 32 -> 0, etc. */
8140 inst
.operands
[2].imm
&= 0x1f;
8141 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8145 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8146 operations first, then control, shift, and load/store. */
8148 /* Insns like "foo X,Y,Z". */
8151 do_mav_triple (void)
8153 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8154 inst
.instruction
|= inst
.operands
[1].reg
;
8155 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8158 /* Insns like "foo W,X,Y,Z".
8159 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8164 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8165 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8166 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8167 inst
.instruction
|= inst
.operands
[3].reg
;
8170 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8174 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8177 /* Maverick shift immediate instructions.
8178 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8179 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8184 int imm
= inst
.operands
[2].imm
;
8186 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8187 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8189 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8190 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8191 Bit 4 should be 0. */
8192 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8194 inst
.instruction
|= imm
;
8197 /* XScale instructions. Also sorted arithmetic before move. */
8199 /* Xscale multiply-accumulate (argument parse)
8202 MIAxycc acc0,Rm,Rs. */
8207 inst
.instruction
|= inst
.operands
[1].reg
;
8208 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8211 /* Xscale move-accumulator-register (argument parse)
8213 MARcc acc0,RdLo,RdHi. */
8218 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8219 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8222 /* Xscale move-register-accumulator (argument parse)
8224 MRAcc RdLo,RdHi,acc0. */
8229 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8230 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8231 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8234 /* Encoding functions relevant only to Thumb. */
8236 /* inst.operands[i] is a shifted-register operand; encode
8237 it into inst.instruction in the format used by Thumb32. */
8240 encode_thumb32_shifted_operand (int i
)
8242 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8243 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8245 constraint (inst
.operands
[i
].immisreg
,
8246 _("shift by register not allowed in thumb mode"));
8247 inst
.instruction
|= inst
.operands
[i
].reg
;
8248 if (shift
== SHIFT_RRX
)
8249 inst
.instruction
|= SHIFT_ROR
<< 4;
8252 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8253 _("expression too complex"));
8255 constraint (value
> 32
8256 || (value
== 32 && (shift
== SHIFT_LSL
8257 || shift
== SHIFT_ROR
)),
8258 _("shift expression is too large"));
8262 else if (value
== 32)
8265 inst
.instruction
|= shift
<< 4;
8266 inst
.instruction
|= (value
& 0x1c) << 10;
8267 inst
.instruction
|= (value
& 0x03) << 6;
8272 /* inst.operands[i] was set up by parse_address. Encode it into a
8273 Thumb32 format load or store instruction. Reject forms that cannot
8274 be used with such instructions. If is_t is true, reject forms that
8275 cannot be used with a T instruction; if is_d is true, reject forms
8276 that cannot be used with a D instruction. */
8279 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8281 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8283 constraint (!inst
.operands
[i
].isreg
,
8284 _("Instruction does not support =N addresses"));
8286 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8287 if (inst
.operands
[i
].immisreg
)
8289 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8290 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8291 constraint (inst
.operands
[i
].negative
,
8292 _("Thumb does not support negative register indexing"));
8293 constraint (inst
.operands
[i
].postind
,
8294 _("Thumb does not support register post-indexing"));
8295 constraint (inst
.operands
[i
].writeback
,
8296 _("Thumb does not support register indexing with writeback"));
8297 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8298 _("Thumb supports only LSL in shifted register indexing"));
8300 inst
.instruction
|= inst
.operands
[i
].imm
;
8301 if (inst
.operands
[i
].shifted
)
8303 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8304 _("expression too complex"));
8305 constraint (inst
.reloc
.exp
.X_add_number
< 0
8306 || inst
.reloc
.exp
.X_add_number
> 3,
8307 _("shift out of range"));
8308 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8310 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8312 else if (inst
.operands
[i
].preind
)
8314 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8315 _("cannot use writeback with PC-relative addressing"));
8316 constraint (is_t
&& inst
.operands
[i
].writeback
,
8317 _("cannot use writeback with this instruction"));
8321 inst
.instruction
|= 0x01000000;
8322 if (inst
.operands
[i
].writeback
)
8323 inst
.instruction
|= 0x00200000;
8327 inst
.instruction
|= 0x00000c00;
8328 if (inst
.operands
[i
].writeback
)
8329 inst
.instruction
|= 0x00000100;
8331 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8333 else if (inst
.operands
[i
].postind
)
8335 assert (inst
.operands
[i
].writeback
);
8336 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8337 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8340 inst
.instruction
|= 0x00200000;
8342 inst
.instruction
|= 0x00000900;
8343 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8345 else /* unindexed - only for coprocessor */
8346 inst
.error
= _("instruction does not accept unindexed addressing");
8349 /* Table of Thumb instructions which exist in both 16- and 32-bit
8350 encodings (the latter only in post-V6T2 cores). The index is the
8351 value used in the insns table below. When there is more than one
8352 possible 16-bit encoding for the instruction, this table always
8354 Also contains several pseudo-instructions used during relaxation. */
8355 #define T16_32_TAB \
8356 X(adc, 4140, eb400000), \
8357 X(adcs, 4140, eb500000), \
8358 X(add, 1c00, eb000000), \
8359 X(adds, 1c00, eb100000), \
8360 X(addi, 0000, f1000000), \
8361 X(addis, 0000, f1100000), \
8362 X(add_pc,000f, f20f0000), \
8363 X(add_sp,000d, f10d0000), \
8364 X(adr, 000f, f20f0000), \
8365 X(and, 4000, ea000000), \
8366 X(ands, 4000, ea100000), \
8367 X(asr, 1000, fa40f000), \
8368 X(asrs, 1000, fa50f000), \
8369 X(b, e000, f000b000), \
8370 X(bcond, d000, f0008000), \
8371 X(bic, 4380, ea200000), \
8372 X(bics, 4380, ea300000), \
8373 X(cmn, 42c0, eb100f00), \
8374 X(cmp, 2800, ebb00f00), \
8375 X(cpsie, b660, f3af8400), \
8376 X(cpsid, b670, f3af8600), \
8377 X(cpy, 4600, ea4f0000), \
8378 X(dec_sp,80dd, f1ad0d00), \
8379 X(eor, 4040, ea800000), \
8380 X(eors, 4040, ea900000), \
8381 X(inc_sp,00dd, f10d0d00), \
8382 X(ldmia, c800, e8900000), \
8383 X(ldr, 6800, f8500000), \
8384 X(ldrb, 7800, f8100000), \
8385 X(ldrh, 8800, f8300000), \
8386 X(ldrsb, 5600, f9100000), \
8387 X(ldrsh, 5e00, f9300000), \
8388 X(ldr_pc,4800, f85f0000), \
8389 X(ldr_pc2,4800, f85f0000), \
8390 X(ldr_sp,9800, f85d0000), \
8391 X(lsl, 0000, fa00f000), \
8392 X(lsls, 0000, fa10f000), \
8393 X(lsr, 0800, fa20f000), \
8394 X(lsrs, 0800, fa30f000), \
8395 X(mov, 2000, ea4f0000), \
8396 X(movs, 2000, ea5f0000), \
8397 X(mul, 4340, fb00f000), \
8398 X(muls, 4340, ffffffff), /* no 32b muls */ \
8399 X(mvn, 43c0, ea6f0000), \
8400 X(mvns, 43c0, ea7f0000), \
8401 X(neg, 4240, f1c00000), /* rsb #0 */ \
8402 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8403 X(orr, 4300, ea400000), \
8404 X(orrs, 4300, ea500000), \
8405 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8406 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8407 X(rev, ba00, fa90f080), \
8408 X(rev16, ba40, fa90f090), \
8409 X(revsh, bac0, fa90f0b0), \
8410 X(ror, 41c0, fa60f000), \
8411 X(rors, 41c0, fa70f000), \
8412 X(sbc, 4180, eb600000), \
8413 X(sbcs, 4180, eb700000), \
8414 X(stmia, c000, e8800000), \
8415 X(str, 6000, f8400000), \
8416 X(strb, 7000, f8000000), \
8417 X(strh, 8000, f8200000), \
8418 X(str_sp,9000, f84d0000), \
8419 X(sub, 1e00, eba00000), \
8420 X(subs, 1e00, ebb00000), \
8421 X(subi, 8000, f1a00000), \
8422 X(subis, 8000, f1b00000), \
8423 X(sxtb, b240, fa4ff080), \
8424 X(sxth, b200, fa0ff080), \
8425 X(tst, 4200, ea100f00), \
8426 X(uxtb, b2c0, fa5ff080), \
8427 X(uxth, b280, fa1ff080), \
8428 X(nop, bf00, f3af8000), \
8429 X(yield, bf10, f3af8001), \
8430 X(wfe, bf20, f3af8002), \
8431 X(wfi, bf30, f3af8003), \
8432 X(sev, bf40, f3af9004), /* typo, 8004? */
8434 /* To catch errors in encoding functions, the codes are all offset by
8435 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8436 as 16-bit instructions. */
8437 #define X(a,b,c) T_MNEM_##a
8438 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8441 #define X(a,b,c) 0x##b
8442 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8443 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8446 #define X(a,b,c) 0x##c
8447 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8448 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8449 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8453 /* Thumb instruction encoders, in alphabetical order. */
8457 do_t_add_sub_w (void)
8461 Rd
= inst
.operands
[0].reg
;
8462 Rn
= inst
.operands
[1].reg
;
8464 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this is the
8465 SP-{plus,minute}-immediate form of the instruction. */
8466 reject_bad_reg (Rd
);
8468 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8469 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8472 /* Parse an add or subtract instruction. We get here with inst.instruction
8473 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8480 Rd
= inst
.operands
[0].reg
;
8481 Rs
= (inst
.operands
[1].present
8482 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8483 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8491 flags
= (inst
.instruction
== T_MNEM_adds
8492 || inst
.instruction
== T_MNEM_subs
);
8494 narrow
= (current_it_mask
== 0);
8496 narrow
= (current_it_mask
!= 0);
8497 if (!inst
.operands
[2].isreg
)
8501 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
8503 add
= (inst
.instruction
== T_MNEM_add
8504 || inst
.instruction
== T_MNEM_adds
);
8506 if (inst
.size_req
!= 4)
8508 /* Attempt to use a narrow opcode, with relaxation if
8510 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8511 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8512 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8513 opcode
= T_MNEM_add_sp
;
8514 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8515 opcode
= T_MNEM_add_pc
;
8516 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8519 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8521 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8525 inst
.instruction
= THUMB_OP16(opcode
);
8526 inst
.instruction
|= (Rd
<< 4) | Rs
;
8527 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8528 if (inst
.size_req
!= 2)
8529 inst
.relax
= opcode
;
8532 constraint (inst
.size_req
== 2, BAD_HIREG
);
8534 if (inst
.size_req
== 4
8535 || (inst
.size_req
!= 2 && !opcode
))
8539 constraint (add
, BAD_PC
);
8540 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
8541 _("only SUBS PC, LR, #const allowed"));
8542 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8543 _("expression too complex"));
8544 constraint (inst
.reloc
.exp
.X_add_number
< 0
8545 || inst
.reloc
.exp
.X_add_number
> 0xff,
8546 _("immediate value out of range"));
8547 inst
.instruction
= T2_SUBS_PC_LR
8548 | inst
.reloc
.exp
.X_add_number
;
8549 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8552 else if (Rs
== REG_PC
)
8554 /* Always use addw/subw. */
8555 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8556 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8560 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8561 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8564 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8566 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8568 inst
.instruction
|= Rd
<< 8;
8569 inst
.instruction
|= Rs
<< 16;
8574 Rn
= inst
.operands
[2].reg
;
8575 /* See if we can do this with a 16-bit instruction. */
8576 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8578 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8583 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8584 || inst
.instruction
== T_MNEM_add
)
8587 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8591 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
8593 /* Thumb-1 cores (except v6-M) require at least one high
8594 register in a narrow non flag setting add. */
8595 if (Rd
> 7 || Rn
> 7
8596 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
8597 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
8604 inst
.instruction
= T_OPCODE_ADD_HI
;
8605 inst
.instruction
|= (Rd
& 8) << 4;
8606 inst
.instruction
|= (Rd
& 7);
8607 inst
.instruction
|= Rn
<< 3;
8613 constraint (Rd
== REG_PC
, BAD_PC
);
8614 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
8615 constraint (Rs
== REG_PC
, BAD_PC
);
8616 reject_bad_reg (Rn
);
8618 /* If we get here, it can't be done in 16 bits. */
8619 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8620 _("shift must be constant"));
8621 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8622 inst
.instruction
|= Rd
<< 8;
8623 inst
.instruction
|= Rs
<< 16;
8624 encode_thumb32_shifted_operand (2);
8629 constraint (inst
.instruction
== T_MNEM_adds
8630 || inst
.instruction
== T_MNEM_subs
,
8633 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
8635 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
8636 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
8639 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8641 inst
.instruction
|= (Rd
<< 4) | Rs
;
8642 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8646 Rn
= inst
.operands
[2].reg
;
8647 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
8649 /* We now have Rd, Rs, and Rn set to registers. */
8650 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8652 /* Can't do this for SUB. */
8653 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
8654 inst
.instruction
= T_OPCODE_ADD_HI
;
8655 inst
.instruction
|= (Rd
& 8) << 4;
8656 inst
.instruction
|= (Rd
& 7);
8658 inst
.instruction
|= Rn
<< 3;
8660 inst
.instruction
|= Rs
<< 3;
8662 constraint (1, _("dest must overlap one source register"));
8666 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8667 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
8668 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8678 Rd
= inst
.operands
[0].reg
;
8679 reject_bad_reg (Rd
);
8681 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
8683 /* Defer to section relaxation. */
8684 inst
.relax
= inst
.instruction
;
8685 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8686 inst
.instruction
|= Rd
<< 4;
8688 else if (unified_syntax
&& inst
.size_req
!= 2)
8690 /* Generate a 32-bit opcode. */
8691 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8692 inst
.instruction
|= Rd
<< 8;
8693 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
8694 inst
.reloc
.pc_rel
= 1;
8698 /* Generate a 16-bit opcode. */
8699 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8700 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8701 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
8702 inst
.reloc
.pc_rel
= 1;
8704 inst
.instruction
|= Rd
<< 4;
8708 /* Arithmetic instructions for which there is just one 16-bit
8709 instruction encoding, and it allows only two low registers.
8710 For maximal compatibility with ARM syntax, we allow three register
8711 operands even when Thumb-32 instructions are not available, as long
8712 as the first two are identical. For instance, both "sbc r0,r1" and
8713 "sbc r0,r0,r1" are allowed. */
8719 Rd
= inst
.operands
[0].reg
;
8720 Rs
= (inst
.operands
[1].present
8721 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8722 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8723 Rn
= inst
.operands
[2].reg
;
8725 reject_bad_reg (Rd
);
8726 reject_bad_reg (Rs
);
8727 if (inst
.operands
[2].isreg
)
8728 reject_bad_reg (Rn
);
8732 if (!inst
.operands
[2].isreg
)
8734 /* For an immediate, we always generate a 32-bit opcode;
8735 section relaxation will shrink it later if possible. */
8736 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8737 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8738 inst
.instruction
|= Rd
<< 8;
8739 inst
.instruction
|= Rs
<< 16;
8740 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8746 /* See if we can do this with a 16-bit instruction. */
8747 if (THUMB_SETS_FLAGS (inst
.instruction
))
8748 narrow
= current_it_mask
== 0;
8750 narrow
= current_it_mask
!= 0;
8752 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8754 if (inst
.operands
[2].shifted
)
8756 if (inst
.size_req
== 4)
8762 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8763 inst
.instruction
|= Rd
;
8764 inst
.instruction
|= Rn
<< 3;
8768 /* If we get here, it can't be done in 16 bits. */
8769 constraint (inst
.operands
[2].shifted
8770 && inst
.operands
[2].immisreg
,
8771 _("shift must be constant"));
8772 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8773 inst
.instruction
|= Rd
<< 8;
8774 inst
.instruction
|= Rs
<< 16;
8775 encode_thumb32_shifted_operand (2);
8780 /* On its face this is a lie - the instruction does set the
8781 flags. However, the only supported mnemonic in this mode
8783 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8785 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8786 _("unshifted register required"));
8787 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8788 constraint (Rd
!= Rs
,
8789 _("dest and source1 must be the same register"));
8791 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8792 inst
.instruction
|= Rd
;
8793 inst
.instruction
|= Rn
<< 3;
8797 /* Similarly, but for instructions where the arithmetic operation is
8798 commutative, so we can allow either of them to be different from
8799 the destination operand in a 16-bit instruction. For instance, all
8800 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8807 Rd
= inst
.operands
[0].reg
;
8808 Rs
= (inst
.operands
[1].present
8809 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8810 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8811 Rn
= inst
.operands
[2].reg
;
8813 reject_bad_reg (Rd
);
8814 reject_bad_reg (Rs
);
8815 if (inst
.operands
[2].isreg
)
8816 reject_bad_reg (Rn
);
8820 if (!inst
.operands
[2].isreg
)
8822 /* For an immediate, we always generate a 32-bit opcode;
8823 section relaxation will shrink it later if possible. */
8824 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8825 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8826 inst
.instruction
|= Rd
<< 8;
8827 inst
.instruction
|= Rs
<< 16;
8828 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8834 /* See if we can do this with a 16-bit instruction. */
8835 if (THUMB_SETS_FLAGS (inst
.instruction
))
8836 narrow
= current_it_mask
== 0;
8838 narrow
= current_it_mask
!= 0;
8840 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8842 if (inst
.operands
[2].shifted
)
8844 if (inst
.size_req
== 4)
8851 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8852 inst
.instruction
|= Rd
;
8853 inst
.instruction
|= Rn
<< 3;
8858 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8859 inst
.instruction
|= Rd
;
8860 inst
.instruction
|= Rs
<< 3;
8865 /* If we get here, it can't be done in 16 bits. */
8866 constraint (inst
.operands
[2].shifted
8867 && inst
.operands
[2].immisreg
,
8868 _("shift must be constant"));
8869 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8870 inst
.instruction
|= Rd
<< 8;
8871 inst
.instruction
|= Rs
<< 16;
8872 encode_thumb32_shifted_operand (2);
8877 /* On its face this is a lie - the instruction does set the
8878 flags. However, the only supported mnemonic in this mode
8880 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8882 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8883 _("unshifted register required"));
8884 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8886 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8887 inst
.instruction
|= Rd
;
8890 inst
.instruction
|= Rn
<< 3;
8892 inst
.instruction
|= Rs
<< 3;
8894 constraint (1, _("dest must overlap one source register"));
8901 if (inst
.operands
[0].present
)
8903 constraint ((inst
.instruction
& 0xf0) != 0x40
8904 && inst
.operands
[0].imm
!= 0xf,
8905 _("bad barrier type"));
8906 inst
.instruction
|= inst
.operands
[0].imm
;
8909 inst
.instruction
|= 0xf;
8916 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8917 constraint (msb
> 32, _("bit-field extends past end of register"));
8918 /* The instruction encoding stores the LSB and MSB,
8919 not the LSB and width. */
8920 Rd
= inst
.operands
[0].reg
;
8921 reject_bad_reg (Rd
);
8922 inst
.instruction
|= Rd
<< 8;
8923 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
8924 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
8925 inst
.instruction
|= msb
- 1;
8934 Rd
= inst
.operands
[0].reg
;
8935 reject_bad_reg (Rd
);
8937 /* #0 in second position is alternative syntax for bfc, which is
8938 the same instruction but with REG_PC in the Rm field. */
8939 if (!inst
.operands
[1].isreg
)
8943 Rn
= inst
.operands
[1].reg
;
8944 reject_bad_reg (Rn
);
8947 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8948 constraint (msb
> 32, _("bit-field extends past end of register"));
8949 /* The instruction encoding stores the LSB and MSB,
8950 not the LSB and width. */
8951 inst
.instruction
|= Rd
<< 8;
8952 inst
.instruction
|= Rn
<< 16;
8953 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8954 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8955 inst
.instruction
|= msb
- 1;
8963 Rd
= inst
.operands
[0].reg
;
8964 Rn
= inst
.operands
[1].reg
;
8966 reject_bad_reg (Rd
);
8967 reject_bad_reg (Rn
);
8969 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8970 _("bit-field extends past end of register"));
8971 inst
.instruction
|= Rd
<< 8;
8972 inst
.instruction
|= Rn
<< 16;
8973 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8974 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8975 inst
.instruction
|= inst
.operands
[3].imm
- 1;
8978 /* ARM V5 Thumb BLX (argument parse)
8979 BLX <target_addr> which is BLX(1)
8980 BLX <Rm> which is BLX(2)
8981 Unfortunately, there are two different opcodes for this mnemonic.
8982 So, the insns[].value is not used, and the code here zaps values
8983 into inst.instruction.
8985 ??? How to take advantage of the additional two bits of displacement
8986 available in Thumb32 mode? Need new relocation? */
8991 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8992 if (inst
.operands
[0].isreg
)
8994 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8995 /* We have a register, so this is BLX(2). */
8996 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9000 /* No register. This must be BLX(1). */
9001 inst
.instruction
= 0xf000e800;
9002 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9003 inst
.reloc
.pc_rel
= 1;
9013 if (current_it_mask
)
9015 /* Conditional branches inside IT blocks are encoded as unconditional
9018 /* A branch must be the last instruction in an IT block. */
9019 constraint (current_it_mask
!= 0x10, BAD_BRANCH
);
9024 if (cond
!= COND_ALWAYS
)
9025 opcode
= T_MNEM_bcond
;
9027 opcode
= inst
.instruction
;
9029 if (unified_syntax
&& inst
.size_req
== 4)
9031 inst
.instruction
= THUMB_OP32(opcode
);
9032 if (cond
== COND_ALWAYS
)
9033 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9036 assert (cond
!= 0xF);
9037 inst
.instruction
|= cond
<< 22;
9038 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9043 inst
.instruction
= THUMB_OP16(opcode
);
9044 if (cond
== COND_ALWAYS
)
9045 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9048 inst
.instruction
|= cond
<< 8;
9049 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9051 /* Allow section relaxation. */
9052 if (unified_syntax
&& inst
.size_req
!= 2)
9053 inst
.relax
= opcode
;
9056 inst
.reloc
.pc_rel
= 1;
9062 constraint (inst
.cond
!= COND_ALWAYS
,
9063 _("instruction is always unconditional"));
9064 if (inst
.operands
[0].present
)
9066 constraint (inst
.operands
[0].imm
> 255,
9067 _("immediate value out of range"));
9068 inst
.instruction
|= inst
.operands
[0].imm
;
9073 do_t_branch23 (void)
9075 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
9076 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9077 inst
.reloc
.pc_rel
= 1;
9079 #if defined(OBJ_COFF)
9080 /* If the destination of the branch is a defined symbol which does not have
9081 the THUMB_FUNC attribute, then we must be calling a function which has
9082 the (interfacearm) attribute. We look for the Thumb entry point to that
9083 function and change the branch to refer to that function instead. */
9084 if ( inst
.reloc
.exp
.X_op
== O_symbol
9085 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9086 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9087 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9088 inst
.reloc
.exp
.X_add_symbol
=
9089 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9096 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
9097 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9098 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9099 should cause the alignment to be checked once it is known. This is
9100 because BX PC only works if the instruction is word aligned. */
9108 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
9109 Rm
= inst
.operands
[0].reg
;
9110 reject_bad_reg (Rm
);
9111 inst
.instruction
|= Rm
<< 16;
9120 Rd
= inst
.operands
[0].reg
;
9121 Rm
= inst
.operands
[1].reg
;
9123 reject_bad_reg (Rd
);
9124 reject_bad_reg (Rm
);
9126 inst
.instruction
|= Rd
<< 8;
9127 inst
.instruction
|= Rm
<< 16;
9128 inst
.instruction
|= Rm
;
9134 constraint (current_it_mask
, BAD_NOT_IT
);
9135 inst
.instruction
|= inst
.operands
[0].imm
;
9141 constraint (current_it_mask
, BAD_NOT_IT
);
9143 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9144 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9146 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9147 inst
.instruction
= 0xf3af8000;
9148 inst
.instruction
|= imod
<< 9;
9149 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9150 if (inst
.operands
[1].present
)
9151 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9155 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9156 && (inst
.operands
[0].imm
& 4),
9157 _("selected processor does not support 'A' form "
9158 "of this instruction"));
9159 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9160 _("Thumb does not support the 2-argument "
9161 "form of this instruction"));
9162 inst
.instruction
|= inst
.operands
[0].imm
;
9166 /* THUMB CPY instruction (argument parse). */
9171 if (inst
.size_req
== 4)
9173 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9174 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9175 inst
.instruction
|= inst
.operands
[1].reg
;
9179 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9180 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9181 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9188 constraint (current_it_mask
, BAD_NOT_IT
);
9189 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9190 inst
.instruction
|= inst
.operands
[0].reg
;
9191 inst
.reloc
.pc_rel
= 1;
9192 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9198 inst
.instruction
|= inst
.operands
[0].imm
;
9204 unsigned Rd
, Rn
, Rm
;
9206 Rd
= inst
.operands
[0].reg
;
9207 Rn
= (inst
.operands
[1].present
9208 ? inst
.operands
[1].reg
: Rd
);
9209 Rm
= inst
.operands
[2].reg
;
9211 reject_bad_reg (Rd
);
9212 reject_bad_reg (Rn
);
9213 reject_bad_reg (Rm
);
9215 inst
.instruction
|= Rd
<< 8;
9216 inst
.instruction
|= Rn
<< 16;
9217 inst
.instruction
|= Rm
;
9223 if (unified_syntax
&& inst
.size_req
== 4)
9224 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9226 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9232 unsigned int cond
= inst
.operands
[0].imm
;
9234 constraint (current_it_mask
, BAD_NOT_IT
);
9235 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
9238 /* If the condition is a negative condition, invert the mask. */
9239 if ((cond
& 0x1) == 0x0)
9241 unsigned int mask
= inst
.instruction
& 0x000f;
9243 if ((mask
& 0x7) == 0)
9244 /* no conversion needed */;
9245 else if ((mask
& 0x3) == 0)
9247 else if ((mask
& 0x1) == 0)
9252 inst
.instruction
&= 0xfff0;
9253 inst
.instruction
|= mask
;
9256 inst
.instruction
|= cond
<< 4;
9259 /* Helper function used for both push/pop and ldm/stm. */
9261 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9265 load
= (inst
.instruction
& (1 << 20)) != 0;
9267 if (mask
& (1 << 13))
9268 inst
.error
= _("SP not allowed in register list");
9271 if (mask
& (1 << 14)
9272 && mask
& (1 << 15))
9273 inst
.error
= _("LR and PC should not both be in register list");
9275 if ((mask
& (1 << base
)) != 0
9277 as_warn (_("base register should not be in register list "
9278 "when written back"));
9282 if (mask
& (1 << 15))
9283 inst
.error
= _("PC not allowed in register list");
9285 if (mask
& (1 << base
))
9286 as_warn (_("value stored for r%d is UNPREDICTABLE"), base
);
9289 if ((mask
& (mask
- 1)) == 0)
9291 /* Single register transfers implemented as str/ldr. */
9294 if (inst
.instruction
& (1 << 23))
9295 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9297 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9301 if (inst
.instruction
& (1 << 23))
9302 inst
.instruction
= 0x00800000; /* ia -> [base] */
9304 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9307 inst
.instruction
|= 0xf8400000;
9309 inst
.instruction
|= 0x00100000;
9311 mask
= ffs (mask
) - 1;
9315 inst
.instruction
|= WRITE_BACK
;
9317 inst
.instruction
|= mask
;
9318 inst
.instruction
|= base
<< 16;
9324 /* This really doesn't seem worth it. */
9325 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9326 _("expression too complex"));
9327 constraint (inst
.operands
[1].writeback
,
9328 _("Thumb load/store multiple does not support {reglist}^"));
9336 /* See if we can use a 16-bit instruction. */
9337 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9338 && inst
.size_req
!= 4
9339 && !(inst
.operands
[1].imm
& ~0xff))
9341 mask
= 1 << inst
.operands
[0].reg
;
9343 if (inst
.operands
[0].reg
<= 7
9344 && (inst
.instruction
== T_MNEM_stmia
9345 ? inst
.operands
[0].writeback
9346 : (inst
.operands
[0].writeback
9347 == !(inst
.operands
[1].imm
& mask
))))
9349 if (inst
.instruction
== T_MNEM_stmia
9350 && (inst
.operands
[1].imm
& mask
)
9351 && (inst
.operands
[1].imm
& (mask
- 1)))
9352 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9353 inst
.operands
[0].reg
);
9355 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9356 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9357 inst
.instruction
|= inst
.operands
[1].imm
;
9360 else if (inst
.operands
[0] .reg
== REG_SP
9361 && inst
.operands
[0].writeback
)
9363 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9364 ? T_MNEM_push
: T_MNEM_pop
);
9365 inst
.instruction
|= inst
.operands
[1].imm
;
9372 if (inst
.instruction
< 0xffff)
9373 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9375 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9376 inst
.operands
[0].writeback
);
9381 constraint (inst
.operands
[0].reg
> 7
9382 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9383 constraint (inst
.instruction
!= T_MNEM_ldmia
9384 && inst
.instruction
!= T_MNEM_stmia
,
9385 _("Thumb-2 instruction only valid in unified syntax"));
9386 if (inst
.instruction
== T_MNEM_stmia
)
9388 if (!inst
.operands
[0].writeback
)
9389 as_warn (_("this instruction will write back the base register"));
9390 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9391 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9392 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9393 inst
.operands
[0].reg
);
9397 if (!inst
.operands
[0].writeback
9398 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9399 as_warn (_("this instruction will write back the base register"));
9400 else if (inst
.operands
[0].writeback
9401 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9402 as_warn (_("this instruction will not write back the base register"));
9405 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9406 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9407 inst
.instruction
|= inst
.operands
[1].imm
;
9414 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9415 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9416 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9417 || inst
.operands
[1].negative
,
9420 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9421 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9422 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9428 if (!inst
.operands
[1].present
)
9430 constraint (inst
.operands
[0].reg
== REG_LR
,
9431 _("r14 not allowed as first register "
9432 "when second register is omitted"));
9433 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9435 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9438 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9439 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9440 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9446 unsigned long opcode
;
9449 opcode
= inst
.instruction
;
9452 if (!inst
.operands
[1].isreg
)
9454 if (opcode
<= 0xffff)
9455 inst
.instruction
= THUMB_OP32 (opcode
);
9456 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9459 if (inst
.operands
[1].isreg
9460 && !inst
.operands
[1].writeback
9461 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9462 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9464 && inst
.size_req
!= 4)
9466 /* Insn may have a 16-bit form. */
9467 Rn
= inst
.operands
[1].reg
;
9468 if (inst
.operands
[1].immisreg
)
9470 inst
.instruction
= THUMB_OP16 (opcode
);
9472 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9475 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9476 && opcode
!= T_MNEM_ldrsb
)
9477 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9478 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9485 if (inst
.reloc
.pc_rel
)
9486 opcode
= T_MNEM_ldr_pc2
;
9488 opcode
= T_MNEM_ldr_pc
;
9492 if (opcode
== T_MNEM_ldr
)
9493 opcode
= T_MNEM_ldr_sp
;
9495 opcode
= T_MNEM_str_sp
;
9497 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9501 inst
.instruction
= inst
.operands
[0].reg
;
9502 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9504 inst
.instruction
|= THUMB_OP16 (opcode
);
9505 if (inst
.size_req
== 2)
9506 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9508 inst
.relax
= opcode
;
9512 /* Definitely a 32-bit variant. */
9513 inst
.instruction
= THUMB_OP32 (opcode
);
9514 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9515 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9519 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9521 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9523 /* Only [Rn,Rm] is acceptable. */
9524 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9525 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9526 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9527 || inst
.operands
[1].negative
,
9528 _("Thumb does not support this addressing mode"));
9529 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9533 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9534 if (!inst
.operands
[1].isreg
)
9535 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9538 constraint (!inst
.operands
[1].preind
9539 || inst
.operands
[1].shifted
9540 || inst
.operands
[1].writeback
,
9541 _("Thumb does not support this addressing mode"));
9542 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9544 constraint (inst
.instruction
& 0x0600,
9545 _("byte or halfword not valid for base register"));
9546 constraint (inst
.operands
[1].reg
== REG_PC
9547 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9548 _("r15 based store not allowed"));
9549 constraint (inst
.operands
[1].immisreg
,
9550 _("invalid base register for register offset"));
9552 if (inst
.operands
[1].reg
== REG_PC
)
9553 inst
.instruction
= T_OPCODE_LDR_PC
;
9554 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9555 inst
.instruction
= T_OPCODE_LDR_SP
;
9557 inst
.instruction
= T_OPCODE_STR_SP
;
9559 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9560 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9564 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9565 if (!inst
.operands
[1].immisreg
)
9567 /* Immediate offset. */
9568 inst
.instruction
|= inst
.operands
[0].reg
;
9569 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9570 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9574 /* Register offset. */
9575 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9576 constraint (inst
.operands
[1].negative
,
9577 _("Thumb does not support this addressing mode"));
9580 switch (inst
.instruction
)
9582 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9583 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9584 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9585 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9586 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9587 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9588 case 0x5600 /* ldrsb */:
9589 case 0x5e00 /* ldrsh */: break;
9593 inst
.instruction
|= inst
.operands
[0].reg
;
9594 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9595 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9601 if (!inst
.operands
[1].present
)
9603 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9604 constraint (inst
.operands
[0].reg
== REG_LR
,
9605 _("r14 not allowed here"));
9607 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9608 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9609 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9615 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9616 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
9622 unsigned Rd
, Rn
, Rm
, Ra
;
9624 Rd
= inst
.operands
[0].reg
;
9625 Rn
= inst
.operands
[1].reg
;
9626 Rm
= inst
.operands
[2].reg
;
9627 Ra
= inst
.operands
[3].reg
;
9629 reject_bad_reg (Rd
);
9630 reject_bad_reg (Rn
);
9631 reject_bad_reg (Rm
);
9632 reject_bad_reg (Ra
);
9634 inst
.instruction
|= Rd
<< 8;
9635 inst
.instruction
|= Rn
<< 16;
9636 inst
.instruction
|= Rm
;
9637 inst
.instruction
|= Ra
<< 12;
9643 unsigned RdLo
, RdHi
, Rn
, Rm
;
9645 RdLo
= inst
.operands
[0].reg
;
9646 RdHi
= inst
.operands
[1].reg
;
9647 Rn
= inst
.operands
[2].reg
;
9648 Rm
= inst
.operands
[3].reg
;
9650 reject_bad_reg (RdLo
);
9651 reject_bad_reg (RdHi
);
9652 reject_bad_reg (Rn
);
9653 reject_bad_reg (Rm
);
9655 inst
.instruction
|= RdLo
<< 12;
9656 inst
.instruction
|= RdHi
<< 8;
9657 inst
.instruction
|= Rn
<< 16;
9658 inst
.instruction
|= Rm
;
9666 Rn
= inst
.operands
[0].reg
;
9667 Rm
= inst
.operands
[1].reg
;
9671 int r0off
= (inst
.instruction
== T_MNEM_mov
9672 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
9673 unsigned long opcode
;
9675 bfd_boolean low_regs
;
9677 low_regs
= (Rn
<= 7 && Rm
<= 7);
9678 opcode
= inst
.instruction
;
9679 if (current_it_mask
)
9680 narrow
= opcode
!= T_MNEM_movs
;
9682 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
9683 if (inst
.size_req
== 4
9684 || inst
.operands
[1].shifted
)
9687 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
9688 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
9689 && !inst
.operands
[1].shifted
9693 inst
.instruction
= T2_SUBS_PC_LR
;
9697 if (opcode
== T_MNEM_cmp
)
9699 constraint (Rn
== REG_PC
, BAD_PC
);
9702 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
9704 warn_deprecated_sp (Rm
);
9705 /* R15 was documented as a valid choice for Rm in ARMv6,
9706 but as UNPREDICTABLE in ARMv7. ARM's proprietary
9707 tools reject R15, so we do too. */
9708 constraint (Rm
== REG_PC
, BAD_PC
);
9711 reject_bad_reg (Rm
);
9713 else if (opcode
== T_MNEM_mov
9714 || opcode
== T_MNEM_movs
)
9716 if (inst
.operands
[1].isreg
)
9718 if (opcode
== T_MNEM_movs
)
9720 reject_bad_reg (Rn
);
9721 reject_bad_reg (Rm
);
9723 else if ((Rn
== REG_SP
|| Rn
== REG_PC
)
9724 && (Rm
== REG_SP
|| Rm
== REG_PC
))
9725 reject_bad_reg (Rm
);
9728 reject_bad_reg (Rn
);
9731 if (!inst
.operands
[1].isreg
)
9733 /* Immediate operand. */
9734 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
9736 if (low_regs
&& narrow
)
9738 inst
.instruction
= THUMB_OP16 (opcode
);
9739 inst
.instruction
|= Rn
<< 8;
9740 if (inst
.size_req
== 2)
9741 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9743 inst
.relax
= opcode
;
9747 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9748 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9749 inst
.instruction
|= Rn
<< r0off
;
9750 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9753 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
9754 && (inst
.instruction
== T_MNEM_mov
9755 || inst
.instruction
== T_MNEM_movs
))
9757 /* Register shifts are encoded as separate shift instructions. */
9758 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
9760 if (current_it_mask
)
9765 if (inst
.size_req
== 4)
9768 if (!low_regs
|| inst
.operands
[1].imm
> 7)
9774 switch (inst
.operands
[1].shift_kind
)
9777 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
9780 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
9783 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
9786 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
9792 inst
.instruction
= opcode
;
9795 inst
.instruction
|= Rn
;
9796 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
9801 inst
.instruction
|= CONDS_BIT
;
9803 inst
.instruction
|= Rn
<< 8;
9804 inst
.instruction
|= Rm
<< 16;
9805 inst
.instruction
|= inst
.operands
[1].imm
;
9810 /* Some mov with immediate shift have narrow variants.
9811 Register shifts are handled above. */
9812 if (low_regs
&& inst
.operands
[1].shifted
9813 && (inst
.instruction
== T_MNEM_mov
9814 || inst
.instruction
== T_MNEM_movs
))
9816 if (current_it_mask
)
9817 narrow
= (inst
.instruction
== T_MNEM_mov
);
9819 narrow
= (inst
.instruction
== T_MNEM_movs
);
9824 switch (inst
.operands
[1].shift_kind
)
9826 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9827 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9828 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9829 default: narrow
= FALSE
; break;
9835 inst
.instruction
|= Rn
;
9836 inst
.instruction
|= Rm
<< 3;
9837 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9841 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9842 inst
.instruction
|= Rn
<< r0off
;
9843 encode_thumb32_shifted_operand (1);
9847 switch (inst
.instruction
)
9850 inst
.instruction
= T_OPCODE_MOV_HR
;
9851 inst
.instruction
|= (Rn
& 0x8) << 4;
9852 inst
.instruction
|= (Rn
& 0x7);
9853 inst
.instruction
|= Rm
<< 3;
9857 /* We know we have low registers at this point.
9858 Generate ADD Rd, Rs, #0. */
9859 inst
.instruction
= T_OPCODE_ADD_I3
;
9860 inst
.instruction
|= Rn
;
9861 inst
.instruction
|= Rm
<< 3;
9867 inst
.instruction
= T_OPCODE_CMP_LR
;
9868 inst
.instruction
|= Rn
;
9869 inst
.instruction
|= Rm
<< 3;
9873 inst
.instruction
= T_OPCODE_CMP_HR
;
9874 inst
.instruction
|= (Rn
& 0x8) << 4;
9875 inst
.instruction
|= (Rn
& 0x7);
9876 inst
.instruction
|= Rm
<< 3;
9883 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9884 if (inst
.operands
[1].isreg
)
9886 if (Rn
< 8 && Rm
< 8)
9888 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9889 since a MOV instruction produces unpredictable results. */
9890 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9891 inst
.instruction
= T_OPCODE_ADD_I3
;
9893 inst
.instruction
= T_OPCODE_CMP_LR
;
9895 inst
.instruction
|= Rn
;
9896 inst
.instruction
|= Rm
<< 3;
9900 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9901 inst
.instruction
= T_OPCODE_MOV_HR
;
9903 inst
.instruction
= T_OPCODE_CMP_HR
;
9910 _("only lo regs allowed with immediate"));
9911 inst
.instruction
|= Rn
<< 8;
9912 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9923 top
= (inst
.instruction
& 0x00800000) != 0;
9924 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
9926 constraint (top
, _(":lower16: not allowed this instruction"));
9927 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
9929 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
9931 constraint (!top
, _(":upper16: not allowed this instruction"));
9932 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
9935 Rd
= inst
.operands
[0].reg
;
9936 reject_bad_reg (Rd
);
9938 inst
.instruction
|= Rd
<< 8;
9939 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9941 imm
= inst
.reloc
.exp
.X_add_number
;
9942 inst
.instruction
|= (imm
& 0xf000) << 4;
9943 inst
.instruction
|= (imm
& 0x0800) << 15;
9944 inst
.instruction
|= (imm
& 0x0700) << 4;
9945 inst
.instruction
|= (imm
& 0x00ff);
9954 Rn
= inst
.operands
[0].reg
;
9955 Rm
= inst
.operands
[1].reg
;
9957 if (inst
.instruction
== T_MNEM_cmp
9958 || inst
.instruction
== T_MNEM_cmn
)
9959 constraint (Rn
== REG_PC
, BAD_PC
);
9961 reject_bad_reg (Rn
);
9962 reject_bad_reg (Rm
);
9966 int r0off
= (inst
.instruction
== T_MNEM_mvn
9967 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
9970 if (inst
.size_req
== 4
9971 || inst
.instruction
> 0xffff
9972 || inst
.operands
[1].shifted
9973 || Rn
> 7 || Rm
> 7)
9975 else if (inst
.instruction
== T_MNEM_cmn
)
9977 else if (THUMB_SETS_FLAGS (inst
.instruction
))
9978 narrow
= (current_it_mask
== 0);
9980 narrow
= (current_it_mask
!= 0);
9982 if (!inst
.operands
[1].isreg
)
9984 /* For an immediate, we always generate a 32-bit opcode;
9985 section relaxation will shrink it later if possible. */
9986 if (inst
.instruction
< 0xffff)
9987 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9988 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9989 inst
.instruction
|= Rn
<< r0off
;
9990 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9994 /* See if we can do this with a 16-bit instruction. */
9997 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9998 inst
.instruction
|= Rn
;
9999 inst
.instruction
|= Rm
<< 3;
10003 constraint (inst
.operands
[1].shifted
10004 && inst
.operands
[1].immisreg
,
10005 _("shift must be constant"));
10006 if (inst
.instruction
< 0xffff)
10007 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10008 inst
.instruction
|= Rn
<< r0off
;
10009 encode_thumb32_shifted_operand (1);
10015 constraint (inst
.instruction
> 0xffff
10016 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10017 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10018 _("unshifted register required"));
10019 constraint (Rn
> 7 || Rm
> 7,
10022 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10023 inst
.instruction
|= Rn
;
10024 inst
.instruction
|= Rm
<< 3;
10034 if (do_vfp_nsyn_mrs () == SUCCESS
)
10037 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10040 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10041 _("selected processor does not support "
10042 "requested special purpose register"));
10046 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10047 _("selected processor does not support "
10048 "requested special purpose register"));
10049 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10050 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10051 _("'CPSR' or 'SPSR' expected"));
10054 Rd
= inst
.operands
[0].reg
;
10055 reject_bad_reg (Rd
);
10057 inst
.instruction
|= Rd
<< 8;
10058 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10059 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10068 if (do_vfp_nsyn_msr () == SUCCESS
)
10071 constraint (!inst
.operands
[1].isreg
,
10072 _("Thumb encoding does not support an immediate here"));
10073 flags
= inst
.operands
[0].imm
;
10076 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10077 _("selected processor does not support "
10078 "requested special purpose register"));
10082 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10083 _("selected processor does not support "
10084 "requested special purpose register"));
10088 Rn
= inst
.operands
[1].reg
;
10089 reject_bad_reg (Rn
);
10091 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10092 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
10093 inst
.instruction
|= (flags
& 0xff);
10094 inst
.instruction
|= Rn
<< 16;
10100 bfd_boolean narrow
;
10101 unsigned Rd
, Rn
, Rm
;
10103 if (!inst
.operands
[2].present
)
10104 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10106 Rd
= inst
.operands
[0].reg
;
10107 Rn
= inst
.operands
[1].reg
;
10108 Rm
= inst
.operands
[2].reg
;
10110 if (unified_syntax
)
10112 if (inst
.size_req
== 4
10118 else if (inst
.instruction
== T_MNEM_muls
)
10119 narrow
= (current_it_mask
== 0);
10121 narrow
= (current_it_mask
!= 0);
10125 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10126 constraint (Rn
> 7 || Rm
> 7,
10133 /* 16-bit MULS/Conditional MUL. */
10134 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10135 inst
.instruction
|= Rd
;
10138 inst
.instruction
|= Rm
<< 3;
10140 inst
.instruction
|= Rn
<< 3;
10142 constraint (1, _("dest must overlap one source register"));
10146 constraint(inst
.instruction
!= T_MNEM_mul
,
10147 _("Thumb-2 MUL must not set flags"));
10149 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10150 inst
.instruction
|= Rd
<< 8;
10151 inst
.instruction
|= Rn
<< 16;
10152 inst
.instruction
|= Rm
<< 0;
10154 reject_bad_reg (Rd
);
10155 reject_bad_reg (Rn
);
10156 reject_bad_reg (Rm
);
10163 unsigned RdLo
, RdHi
, Rn
, Rm
;
10165 RdLo
= inst
.operands
[0].reg
;
10166 RdHi
= inst
.operands
[1].reg
;
10167 Rn
= inst
.operands
[2].reg
;
10168 Rm
= inst
.operands
[3].reg
;
10170 reject_bad_reg (RdLo
);
10171 reject_bad_reg (RdHi
);
10172 reject_bad_reg (Rn
);
10173 reject_bad_reg (Rm
);
10175 inst
.instruction
|= RdLo
<< 12;
10176 inst
.instruction
|= RdHi
<< 8;
10177 inst
.instruction
|= Rn
<< 16;
10178 inst
.instruction
|= Rm
;
10181 as_tsktsk (_("rdhi and rdlo must be different"));
10187 if (unified_syntax
)
10189 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10191 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10192 inst
.instruction
|= inst
.operands
[0].imm
;
10196 /* PR9722: Check for Thumb2 availability before
10197 generating a thumb2 nop instruction. */
10198 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
10200 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10201 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10204 inst
.instruction
= 0x46c0;
10209 constraint (inst
.operands
[0].present
,
10210 _("Thumb does not support NOP with hints"));
10211 inst
.instruction
= 0x46c0;
10218 if (unified_syntax
)
10220 bfd_boolean narrow
;
10222 if (THUMB_SETS_FLAGS (inst
.instruction
))
10223 narrow
= (current_it_mask
== 0);
10225 narrow
= (current_it_mask
!= 0);
10226 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10228 if (inst
.size_req
== 4)
10233 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10234 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10235 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10239 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10240 inst
.instruction
|= inst
.operands
[0].reg
;
10241 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10246 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10248 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10250 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10251 inst
.instruction
|= inst
.operands
[0].reg
;
10252 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10261 Rd
= inst
.operands
[0].reg
;
10262 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10264 reject_bad_reg (Rd
);
10265 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10266 reject_bad_reg (Rn
);
10268 inst
.instruction
|= Rd
<< 8;
10269 inst
.instruction
|= Rn
<< 16;
10271 if (!inst
.operands
[2].isreg
)
10273 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10274 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10280 Rm
= inst
.operands
[2].reg
;
10281 reject_bad_reg (Rm
);
10283 constraint (inst
.operands
[2].shifted
10284 && inst
.operands
[2].immisreg
,
10285 _("shift must be constant"));
10286 encode_thumb32_shifted_operand (2);
10293 unsigned Rd
, Rn
, Rm
;
10295 Rd
= inst
.operands
[0].reg
;
10296 Rn
= inst
.operands
[1].reg
;
10297 Rm
= inst
.operands
[2].reg
;
10299 reject_bad_reg (Rd
);
10300 reject_bad_reg (Rn
);
10301 reject_bad_reg (Rm
);
10303 inst
.instruction
|= Rd
<< 8;
10304 inst
.instruction
|= Rn
<< 16;
10305 inst
.instruction
|= Rm
;
10306 if (inst
.operands
[3].present
)
10308 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10309 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10310 _("expression too complex"));
10311 inst
.instruction
|= (val
& 0x1c) << 10;
10312 inst
.instruction
|= (val
& 0x03) << 6;
10319 if (!inst
.operands
[3].present
)
10320 inst
.instruction
&= ~0x00000020;
10327 if (inst
.operands
[0].immisreg
)
10328 reject_bad_reg (inst
.operands
[0].imm
);
10330 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10334 do_t_push_pop (void)
10338 constraint (inst
.operands
[0].writeback
,
10339 _("push/pop do not support {reglist}^"));
10340 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10341 _("expression too complex"));
10343 mask
= inst
.operands
[0].imm
;
10344 if ((mask
& ~0xff) == 0)
10345 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10346 else if ((inst
.instruction
== T_MNEM_push
10347 && (mask
& ~0xff) == 1 << REG_LR
)
10348 || (inst
.instruction
== T_MNEM_pop
10349 && (mask
& ~0xff) == 1 << REG_PC
))
10351 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10352 inst
.instruction
|= THUMB_PP_PC_LR
;
10353 inst
.instruction
|= mask
& 0xff;
10355 else if (unified_syntax
)
10357 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10358 encode_thumb2_ldmstm (13, mask
, TRUE
);
10362 inst
.error
= _("invalid register list to push/pop instruction");
10372 Rd
= inst
.operands
[0].reg
;
10373 Rm
= inst
.operands
[1].reg
;
10375 reject_bad_reg (Rd
);
10376 reject_bad_reg (Rm
);
10378 inst
.instruction
|= Rd
<< 8;
10379 inst
.instruction
|= Rm
<< 16;
10380 inst
.instruction
|= Rm
;
10388 Rd
= inst
.operands
[0].reg
;
10389 Rm
= inst
.operands
[1].reg
;
10391 reject_bad_reg (Rd
);
10392 reject_bad_reg (Rm
);
10394 if (Rd
<= 7 && Rm
<= 7
10395 && inst
.size_req
!= 4)
10397 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10398 inst
.instruction
|= Rd
;
10399 inst
.instruction
|= Rm
<< 3;
10401 else if (unified_syntax
)
10403 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10404 inst
.instruction
|= Rd
<< 8;
10405 inst
.instruction
|= Rm
<< 16;
10406 inst
.instruction
|= Rm
;
10409 inst
.error
= BAD_HIREG
;
10417 Rd
= inst
.operands
[0].reg
;
10418 Rm
= inst
.operands
[1].reg
;
10420 reject_bad_reg (Rd
);
10421 reject_bad_reg (Rm
);
10423 inst
.instruction
|= Rd
<< 8;
10424 inst
.instruction
|= Rm
;
10432 Rd
= inst
.operands
[0].reg
;
10433 Rs
= (inst
.operands
[1].present
10434 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10435 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10437 reject_bad_reg (Rd
);
10438 reject_bad_reg (Rs
);
10439 if (inst
.operands
[2].isreg
)
10440 reject_bad_reg (inst
.operands
[2].reg
);
10442 inst
.instruction
|= Rd
<< 8;
10443 inst
.instruction
|= Rs
<< 16;
10444 if (!inst
.operands
[2].isreg
)
10446 bfd_boolean narrow
;
10448 if ((inst
.instruction
& 0x00100000) != 0)
10449 narrow
= (current_it_mask
== 0);
10451 narrow
= (current_it_mask
!= 0);
10453 if (Rd
> 7 || Rs
> 7)
10456 if (inst
.size_req
== 4 || !unified_syntax
)
10459 if (inst
.reloc
.exp
.X_op
!= O_constant
10460 || inst
.reloc
.exp
.X_add_number
!= 0)
10463 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10464 relaxation, but it doesn't seem worth the hassle. */
10467 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10468 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
10469 inst
.instruction
|= Rs
<< 3;
10470 inst
.instruction
|= Rd
;
10474 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10475 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10479 encode_thumb32_shifted_operand (2);
10485 constraint (current_it_mask
, BAD_NOT_IT
);
10486 if (inst
.operands
[0].imm
)
10487 inst
.instruction
|= 0x8;
10493 if (!inst
.operands
[1].present
)
10494 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
10496 if (unified_syntax
)
10498 bfd_boolean narrow
;
10501 switch (inst
.instruction
)
10504 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
10506 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
10508 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
10510 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
10514 if (THUMB_SETS_FLAGS (inst
.instruction
))
10515 narrow
= (current_it_mask
== 0);
10517 narrow
= (current_it_mask
!= 0);
10518 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10520 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
10522 if (inst
.operands
[2].isreg
10523 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
10524 || inst
.operands
[2].reg
> 7))
10526 if (inst
.size_req
== 4)
10529 reject_bad_reg (inst
.operands
[0].reg
);
10530 reject_bad_reg (inst
.operands
[1].reg
);
10534 if (inst
.operands
[2].isreg
)
10536 reject_bad_reg (inst
.operands
[2].reg
);
10537 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10538 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10539 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10540 inst
.instruction
|= inst
.operands
[2].reg
;
10544 inst
.operands
[1].shifted
= 1;
10545 inst
.operands
[1].shift_kind
= shift_kind
;
10546 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
10547 ? T_MNEM_movs
: T_MNEM_mov
);
10548 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10549 encode_thumb32_shifted_operand (1);
10550 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10551 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10556 if (inst
.operands
[2].isreg
)
10558 switch (shift_kind
)
10560 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10561 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10562 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10563 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10567 inst
.instruction
|= inst
.operands
[0].reg
;
10568 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10572 switch (shift_kind
)
10574 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10575 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10576 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10579 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10580 inst
.instruction
|= inst
.operands
[0].reg
;
10581 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10587 constraint (inst
.operands
[0].reg
> 7
10588 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
10589 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10591 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
10593 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
10594 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
10595 _("source1 and dest must be same register"));
10597 switch (inst
.instruction
)
10599 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10600 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10601 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10602 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10606 inst
.instruction
|= inst
.operands
[0].reg
;
10607 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10611 switch (inst
.instruction
)
10613 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10614 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10615 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10616 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
10619 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10620 inst
.instruction
|= inst
.operands
[0].reg
;
10621 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10629 unsigned Rd
, Rn
, Rm
;
10631 Rd
= inst
.operands
[0].reg
;
10632 Rn
= inst
.operands
[1].reg
;
10633 Rm
= inst
.operands
[2].reg
;
10635 reject_bad_reg (Rd
);
10636 reject_bad_reg (Rn
);
10637 reject_bad_reg (Rm
);
10639 inst
.instruction
|= Rd
<< 8;
10640 inst
.instruction
|= Rn
<< 16;
10641 inst
.instruction
|= Rm
;
10647 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10648 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10649 _("expression too complex"));
10650 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10651 inst
.instruction
|= (value
& 0xf000) >> 12;
10652 inst
.instruction
|= (value
& 0x0ff0);
10653 inst
.instruction
|= (value
& 0x000f) << 16;
10661 Rd
= inst
.operands
[0].reg
;
10662 Rn
= inst
.operands
[2].reg
;
10664 reject_bad_reg (Rd
);
10665 reject_bad_reg (Rn
);
10667 inst
.instruction
|= Rd
<< 8;
10668 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10669 inst
.instruction
|= Rn
<< 16;
10671 if (inst
.operands
[3].present
)
10673 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10674 _("expression too complex"));
10676 if (inst
.reloc
.exp
.X_add_number
!= 0)
10678 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10679 inst
.instruction
|= 0x00200000; /* sh bit */
10680 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10681 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10683 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10692 Rd
= inst
.operands
[0].reg
;
10693 Rn
= inst
.operands
[2].reg
;
10695 reject_bad_reg (Rd
);
10696 reject_bad_reg (Rn
);
10698 inst
.instruction
|= Rd
<< 8;
10699 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10700 inst
.instruction
|= Rn
<< 16;
10706 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10707 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10708 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10709 || inst
.operands
[2].negative
,
10712 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10713 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10714 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10715 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10721 if (!inst
.operands
[2].present
)
10722 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
10724 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10725 || inst
.operands
[0].reg
== inst
.operands
[2].reg
10726 || inst
.operands
[0].reg
== inst
.operands
[3].reg
10727 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
10730 inst
.instruction
|= inst
.operands
[0].reg
;
10731 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10732 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10733 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10739 unsigned Rd
, Rn
, Rm
;
10741 Rd
= inst
.operands
[0].reg
;
10742 Rn
= inst
.operands
[1].reg
;
10743 Rm
= inst
.operands
[2].reg
;
10745 reject_bad_reg (Rd
);
10746 reject_bad_reg (Rn
);
10747 reject_bad_reg (Rm
);
10749 inst
.instruction
|= Rd
<< 8;
10750 inst
.instruction
|= Rn
<< 16;
10751 inst
.instruction
|= Rm
;
10752 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
10760 Rd
= inst
.operands
[0].reg
;
10761 Rm
= inst
.operands
[1].reg
;
10763 reject_bad_reg (Rd
);
10764 reject_bad_reg (Rm
);
10766 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
10767 && Rd
<= 7 && Rm
<= 7
10768 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
10770 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10771 inst
.instruction
|= Rd
;
10772 inst
.instruction
|= Rm
<< 3;
10774 else if (unified_syntax
)
10776 if (inst
.instruction
<= 0xffff)
10777 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10778 inst
.instruction
|= Rd
<< 8;
10779 inst
.instruction
|= Rm
;
10780 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
10784 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
10785 _("Thumb encoding does not support rotation"));
10786 constraint (1, BAD_HIREG
);
10793 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
10802 half
= (inst
.instruction
& 0x10) != 0;
10803 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
10804 constraint (inst
.operands
[0].immisreg
,
10805 _("instruction requires register index"));
10807 Rn
= inst
.operands
[0].reg
;
10808 Rm
= inst
.operands
[0].imm
;
10810 constraint (Rn
== REG_SP
, BAD_SP
);
10811 reject_bad_reg (Rm
);
10813 constraint (!half
&& inst
.operands
[0].shifted
,
10814 _("instruction does not allow shifted index"));
10815 inst
.instruction
|= (Rn
<< 16) | Rm
;
10823 Rd
= inst
.operands
[0].reg
;
10824 Rn
= inst
.operands
[2].reg
;
10826 reject_bad_reg (Rd
);
10827 reject_bad_reg (Rn
);
10829 inst
.instruction
|= Rd
<< 8;
10830 inst
.instruction
|= inst
.operands
[1].imm
;
10831 inst
.instruction
|= Rn
<< 16;
10833 if (inst
.operands
[3].present
)
10835 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10836 _("expression too complex"));
10837 if (inst
.reloc
.exp
.X_add_number
!= 0)
10839 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10840 inst
.instruction
|= 0x00200000; /* sh bit */
10842 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10843 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10845 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10854 Rd
= inst
.operands
[0].reg
;
10855 Rn
= inst
.operands
[2].reg
;
10857 reject_bad_reg (Rd
);
10858 reject_bad_reg (Rn
);
10860 inst
.instruction
|= Rd
<< 8;
10861 inst
.instruction
|= inst
.operands
[1].imm
;
10862 inst
.instruction
|= Rn
<< 16;
10865 /* Neon instruction encoder helpers. */
10867 /* Encodings for the different types for various Neon opcodes. */
10869 /* An "invalid" code for the following tables. */
10872 struct neon_tab_entry
10875 unsigned float_or_poly
;
10876 unsigned scalar_or_imm
;
10879 /* Map overloaded Neon opcodes to their respective encodings. */
10880 #define NEON_ENC_TAB \
10881 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10882 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10883 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10884 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10885 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10886 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10887 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10888 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10889 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10890 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10891 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10892 /* Register variants of the following two instructions are encoded as
10893 vcge / vcgt with the operands reversed. */ \
10894 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
10895 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
10896 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10897 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10898 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10899 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10900 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10901 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10902 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10903 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10904 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10905 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10906 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10907 X(vshl, 0x0000400, N_INV, 0x0800510), \
10908 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10909 X(vand, 0x0000110, N_INV, 0x0800030), \
10910 X(vbic, 0x0100110, N_INV, 0x0800030), \
10911 X(veor, 0x1000110, N_INV, N_INV), \
10912 X(vorn, 0x0300110, N_INV, 0x0800010), \
10913 X(vorr, 0x0200110, N_INV, 0x0800010), \
10914 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10915 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10916 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10917 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10918 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10919 X(vst1, 0x0000000, 0x0800000, N_INV), \
10920 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10921 X(vst2, 0x0000100, 0x0800100, N_INV), \
10922 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10923 X(vst3, 0x0000200, 0x0800200, N_INV), \
10924 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10925 X(vst4, 0x0000300, 0x0800300, N_INV), \
10926 X(vmovn, 0x1b20200, N_INV, N_INV), \
10927 X(vtrn, 0x1b20080, N_INV, N_INV), \
10928 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10929 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10930 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10931 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10932 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10933 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10934 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10935 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10936 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10940 #define X(OPC,I,F,S) N_MNEM_##OPC
10945 static const struct neon_tab_entry neon_enc_tab
[] =
10947 #define X(OPC,I,F,S) { (I), (F), (S) }
10952 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10953 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10954 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10955 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10956 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10957 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10958 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10959 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10960 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10961 #define NEON_ENC_SINGLE(X) \
10962 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10963 #define NEON_ENC_DOUBLE(X) \
10964 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10966 /* Define shapes for instruction operands. The following mnemonic characters
10967 are used in this table:
10969 F - VFP S<n> register
10970 D - Neon D<n> register
10971 Q - Neon Q<n> register
10975 L - D<n> register list
10977 This table is used to generate various data:
10978 - enumerations of the form NS_DDR to be used as arguments to
10980 - a table classifying shapes into single, double, quad, mixed.
10981 - a table used to drive neon_select_shape. */
10983 #define NEON_SHAPE_DEF \
10984 X(3, (D, D, D), DOUBLE), \
10985 X(3, (Q, Q, Q), QUAD), \
10986 X(3, (D, D, I), DOUBLE), \
10987 X(3, (Q, Q, I), QUAD), \
10988 X(3, (D, D, S), DOUBLE), \
10989 X(3, (Q, Q, S), QUAD), \
10990 X(2, (D, D), DOUBLE), \
10991 X(2, (Q, Q), QUAD), \
10992 X(2, (D, S), DOUBLE), \
10993 X(2, (Q, S), QUAD), \
10994 X(2, (D, R), DOUBLE), \
10995 X(2, (Q, R), QUAD), \
10996 X(2, (D, I), DOUBLE), \
10997 X(2, (Q, I), QUAD), \
10998 X(3, (D, L, D), DOUBLE), \
10999 X(2, (D, Q), MIXED), \
11000 X(2, (Q, D), MIXED), \
11001 X(3, (D, Q, I), MIXED), \
11002 X(3, (Q, D, I), MIXED), \
11003 X(3, (Q, D, D), MIXED), \
11004 X(3, (D, Q, Q), MIXED), \
11005 X(3, (Q, Q, D), MIXED), \
11006 X(3, (Q, D, S), MIXED), \
11007 X(3, (D, Q, S), MIXED), \
11008 X(4, (D, D, D, I), DOUBLE), \
11009 X(4, (Q, Q, Q, I), QUAD), \
11010 X(2, (F, F), SINGLE), \
11011 X(3, (F, F, F), SINGLE), \
11012 X(2, (F, I), SINGLE), \
11013 X(2, (F, D), MIXED), \
11014 X(2, (D, F), MIXED), \
11015 X(3, (F, F, I), MIXED), \
11016 X(4, (R, R, F, F), SINGLE), \
11017 X(4, (F, F, R, R), SINGLE), \
11018 X(3, (D, R, R), DOUBLE), \
11019 X(3, (R, R, D), DOUBLE), \
11020 X(2, (S, R), SINGLE), \
11021 X(2, (R, S), SINGLE), \
11022 X(2, (F, R), SINGLE), \
11023 X(2, (R, F), SINGLE)
11025 #define S2(A,B) NS_##A##B
11026 #define S3(A,B,C) NS_##A##B##C
11027 #define S4(A,B,C,D) NS_##A##B##C##D
11029 #define X(N, L, C) S##N L
11042 enum neon_shape_class
11050 #define X(N, L, C) SC_##C
11052 static enum neon_shape_class neon_shape_class
[] =
11070 /* Register widths of above. */
11071 static unsigned neon_shape_el_size
[] =
11082 struct neon_shape_info
11085 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11088 #define S2(A,B) { SE_##A, SE_##B }
11089 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11090 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11092 #define X(N, L, C) { N, S##N L }
11094 static struct neon_shape_info neon_shape_tab
[] =
11104 /* Bit masks used in type checking given instructions.
11105 'N_EQK' means the type must be the same as (or based on in some way) the key
11106 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11107 set, various other bits can be set as well in order to modify the meaning of
11108 the type constraint. */
11110 enum neon_type_mask
11133 N_KEY
= 0x1000000, /* key element (main type specifier). */
11134 N_EQK
= 0x2000000, /* given operand has the same type & size as the key. */
11135 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11136 N_DBL
= 0x0000001, /* if N_EQK, this operand is twice the size. */
11137 N_HLF
= 0x0000002, /* if N_EQK, this operand is half the size. */
11138 N_SGN
= 0x0000004, /* if N_EQK, this operand is forced to be signed. */
11139 N_UNS
= 0x0000008, /* if N_EQK, this operand is forced to be unsigned. */
11140 N_INT
= 0x0000010, /* if N_EQK, this operand is forced to be integer. */
11141 N_FLT
= 0x0000020, /* if N_EQK, this operand is forced to be float. */
11142 N_SIZ
= 0x0000040, /* if N_EQK, this operand is forced to be size-only. */
11144 N_MAX_NONSPECIAL
= N_F64
11147 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11149 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11150 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11151 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11152 #define N_SUF_32 (N_SU_32 | N_F32)
11153 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11154 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11156 /* Pass this as the first type argument to neon_check_type to ignore types
11158 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11160 /* Select a "shape" for the current instruction (describing register types or
11161 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11162 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11163 function of operand parsing, so this function doesn't need to be called.
11164 Shapes should be listed in order of decreasing length. */
11166 static enum neon_shape
11167 neon_select_shape (enum neon_shape shape
, ...)
11170 enum neon_shape first_shape
= shape
;
11172 /* Fix missing optional operands. FIXME: we don't know at this point how
11173 many arguments we should have, so this makes the assumption that we have
11174 > 1. This is true of all current Neon opcodes, I think, but may not be
11175 true in the future. */
11176 if (!inst
.operands
[1].present
)
11177 inst
.operands
[1] = inst
.operands
[0];
11179 va_start (ap
, shape
);
11181 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
11186 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
11188 if (!inst
.operands
[j
].present
)
11194 switch (neon_shape_tab
[shape
].el
[j
])
11197 if (!(inst
.operands
[j
].isreg
11198 && inst
.operands
[j
].isvec
11199 && inst
.operands
[j
].issingle
11200 && !inst
.operands
[j
].isquad
))
11205 if (!(inst
.operands
[j
].isreg
11206 && inst
.operands
[j
].isvec
11207 && !inst
.operands
[j
].isquad
11208 && !inst
.operands
[j
].issingle
))
11213 if (!(inst
.operands
[j
].isreg
11214 && !inst
.operands
[j
].isvec
))
11219 if (!(inst
.operands
[j
].isreg
11220 && inst
.operands
[j
].isvec
11221 && inst
.operands
[j
].isquad
11222 && !inst
.operands
[j
].issingle
))
11227 if (!(!inst
.operands
[j
].isreg
11228 && !inst
.operands
[j
].isscalar
))
11233 if (!(!inst
.operands
[j
].isreg
11234 && inst
.operands
[j
].isscalar
))
11248 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
11249 first_error (_("invalid instruction shape"));
11254 /* True if SHAPE is predominantly a quadword operation (most of the time, this
11255 means the Q bit should be set). */
11258 neon_quad (enum neon_shape shape
)
11260 return neon_shape_class
[shape
] == SC_QUAD
;
11264 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
11267 /* Allow modification to be made to types which are constrained to be
11268 based on the key element, based on bits set alongside N_EQK. */
11269 if ((typebits
& N_EQK
) != 0)
11271 if ((typebits
& N_HLF
) != 0)
11273 else if ((typebits
& N_DBL
) != 0)
11275 if ((typebits
& N_SGN
) != 0)
11276 *g_type
= NT_signed
;
11277 else if ((typebits
& N_UNS
) != 0)
11278 *g_type
= NT_unsigned
;
11279 else if ((typebits
& N_INT
) != 0)
11280 *g_type
= NT_integer
;
11281 else if ((typebits
& N_FLT
) != 0)
11282 *g_type
= NT_float
;
11283 else if ((typebits
& N_SIZ
) != 0)
11284 *g_type
= NT_untyped
;
11288 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
11289 operand type, i.e. the single type specified in a Neon instruction when it
11290 is the only one given. */
11292 static struct neon_type_el
11293 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
11295 struct neon_type_el dest
= *key
;
11297 assert ((thisarg
& N_EQK
) != 0);
11299 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
11304 /* Convert Neon type and size into compact bitmask representation. */
11306 static enum neon_type_mask
11307 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
11314 case 8: return N_8
;
11315 case 16: return N_16
;
11316 case 32: return N_32
;
11317 case 64: return N_64
;
11325 case 8: return N_I8
;
11326 case 16: return N_I16
;
11327 case 32: return N_I32
;
11328 case 64: return N_I64
;
11336 case 16: return N_F16
;
11337 case 32: return N_F32
;
11338 case 64: return N_F64
;
11346 case 8: return N_P8
;
11347 case 16: return N_P16
;
11355 case 8: return N_S8
;
11356 case 16: return N_S16
;
11357 case 32: return N_S32
;
11358 case 64: return N_S64
;
11366 case 8: return N_U8
;
11367 case 16: return N_U16
;
11368 case 32: return N_U32
;
11369 case 64: return N_U64
;
11380 /* Convert compact Neon bitmask type representation to a type and size. Only
11381 handles the case where a single bit is set in the mask. */
11384 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
11385 enum neon_type_mask mask
)
11387 if ((mask
& N_EQK
) != 0)
11390 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
11392 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
11394 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
11396 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
11401 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
11403 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
11404 *type
= NT_unsigned
;
11405 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
11406 *type
= NT_integer
;
11407 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
11408 *type
= NT_untyped
;
11409 else if ((mask
& (N_P8
| N_P16
)) != 0)
11411 else if ((mask
& (N_F32
| N_F64
)) != 0)
11419 /* Modify a bitmask of allowed types. This is only needed for type
11423 modify_types_allowed (unsigned allowed
, unsigned mods
)
11426 enum neon_el_type type
;
11432 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
11434 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
11436 neon_modify_type_size (mods
, &type
, &size
);
11437 destmask
|= type_chk_of_el_type (type
, size
);
11444 /* Check type and return type classification.
11445 The manual states (paraphrase): If one datatype is given, it indicates the
11447 - the second operand, if there is one
11448 - the operand, if there is no second operand
11449 - the result, if there are no operands.
11450 This isn't quite good enough though, so we use a concept of a "key" datatype
11451 which is set on a per-instruction basis, which is the one which matters when
11452 only one data type is written.
11453 Note: this function has side-effects (e.g. filling in missing operands). All
11454 Neon instructions should call it before performing bit encoding. */
11456 static struct neon_type_el
11457 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
11460 unsigned i
, pass
, key_el
= 0;
11461 unsigned types
[NEON_MAX_TYPE_ELS
];
11462 enum neon_el_type k_type
= NT_invtype
;
11463 unsigned k_size
= -1u;
11464 struct neon_type_el badtype
= {NT_invtype
, -1};
11465 unsigned key_allowed
= 0;
11467 /* Optional registers in Neon instructions are always (not) in operand 1.
11468 Fill in the missing operand here, if it was omitted. */
11469 if (els
> 1 && !inst
.operands
[1].present
)
11470 inst
.operands
[1] = inst
.operands
[0];
11472 /* Suck up all the varargs. */
11474 for (i
= 0; i
< els
; i
++)
11476 unsigned thisarg
= va_arg (ap
, unsigned);
11477 if (thisarg
== N_IGNORE_TYPE
)
11482 types
[i
] = thisarg
;
11483 if ((thisarg
& N_KEY
) != 0)
11488 if (inst
.vectype
.elems
> 0)
11489 for (i
= 0; i
< els
; i
++)
11490 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
11492 first_error (_("types specified in both the mnemonic and operands"));
11496 /* Duplicate inst.vectype elements here as necessary.
11497 FIXME: No idea if this is exactly the same as the ARM assembler,
11498 particularly when an insn takes one register and one non-register
11500 if (inst
.vectype
.elems
== 1 && els
> 1)
11503 inst
.vectype
.elems
= els
;
11504 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
11505 for (j
= 0; j
< els
; j
++)
11507 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11510 else if (inst
.vectype
.elems
== 0 && els
> 0)
11513 /* No types were given after the mnemonic, so look for types specified
11514 after each operand. We allow some flexibility here; as long as the
11515 "key" operand has a type, we can infer the others. */
11516 for (j
= 0; j
< els
; j
++)
11517 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
11518 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
11520 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
11522 for (j
= 0; j
< els
; j
++)
11523 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
11524 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11529 first_error (_("operand types can't be inferred"));
11533 else if (inst
.vectype
.elems
!= els
)
11535 first_error (_("type specifier has the wrong number of parts"));
11539 for (pass
= 0; pass
< 2; pass
++)
11541 for (i
= 0; i
< els
; i
++)
11543 unsigned thisarg
= types
[i
];
11544 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
11545 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
11546 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
11547 unsigned g_size
= inst
.vectype
.el
[i
].size
;
11549 /* Decay more-specific signed & unsigned types to sign-insensitive
11550 integer types if sign-specific variants are unavailable. */
11551 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
11552 && (types_allowed
& N_SU_ALL
) == 0)
11553 g_type
= NT_integer
;
11555 /* If only untyped args are allowed, decay any more specific types to
11556 them. Some instructions only care about signs for some element
11557 sizes, so handle that properly. */
11558 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
11559 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
11560 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
11561 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
11562 g_type
= NT_untyped
;
11566 if ((thisarg
& N_KEY
) != 0)
11570 key_allowed
= thisarg
& ~N_KEY
;
11575 if ((thisarg
& N_VFP
) != 0)
11577 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
11578 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
11580 /* In VFP mode, operands must match register widths. If we
11581 have a key operand, use its width, else use the width of
11582 the current operand. */
11588 if (regwidth
!= match
)
11590 first_error (_("operand size must match register width"));
11595 if ((thisarg
& N_EQK
) == 0)
11597 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
11599 if ((given_type
& types_allowed
) == 0)
11601 first_error (_("bad type in Neon instruction"));
11607 enum neon_el_type mod_k_type
= k_type
;
11608 unsigned mod_k_size
= k_size
;
11609 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
11610 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
11612 first_error (_("inconsistent types in Neon instruction"));
11620 return inst
.vectype
.el
[key_el
];
11623 /* Neon-style VFP instruction forwarding. */
11625 /* Thumb VFP instructions have 0xE in the condition field. */
11628 do_vfp_cond_or_thumb (void)
11631 inst
.instruction
|= 0xe0000000;
11633 inst
.instruction
|= inst
.cond
<< 28;
11636 /* Look up and encode a simple mnemonic, for use as a helper function for the
11637 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
11638 etc. It is assumed that operand parsing has already been done, and that the
11639 operands are in the form expected by the given opcode (this isn't necessarily
11640 the same as the form in which they were parsed, hence some massaging must
11641 take place before this function is called).
11642 Checks current arch version against that in the looked-up opcode. */
11645 do_vfp_nsyn_opcode (const char *opname
)
11647 const struct asm_opcode
*opcode
;
11649 opcode
= hash_find (arm_ops_hsh
, opname
);
11654 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
11655 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
11660 inst
.instruction
= opcode
->tvalue
;
11661 opcode
->tencode ();
11665 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
11666 opcode
->aencode ();
11671 do_vfp_nsyn_add_sub (enum neon_shape rs
)
11673 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
11678 do_vfp_nsyn_opcode ("fadds");
11680 do_vfp_nsyn_opcode ("fsubs");
11685 do_vfp_nsyn_opcode ("faddd");
11687 do_vfp_nsyn_opcode ("fsubd");
11691 /* Check operand types to see if this is a VFP instruction, and if so call
11695 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
11697 enum neon_shape rs
;
11698 struct neon_type_el et
;
11703 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11704 et
= neon_check_type (2, rs
,
11705 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11709 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11710 et
= neon_check_type (3, rs
,
11711 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11718 if (et
.type
!= NT_invtype
)
11730 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
11732 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
11737 do_vfp_nsyn_opcode ("fmacs");
11739 do_vfp_nsyn_opcode ("fmscs");
11744 do_vfp_nsyn_opcode ("fmacd");
11746 do_vfp_nsyn_opcode ("fmscd");
11751 do_vfp_nsyn_mul (enum neon_shape rs
)
11754 do_vfp_nsyn_opcode ("fmuls");
11756 do_vfp_nsyn_opcode ("fmuld");
11760 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
11762 int is_neg
= (inst
.instruction
& 0x80) != 0;
11763 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
11768 do_vfp_nsyn_opcode ("fnegs");
11770 do_vfp_nsyn_opcode ("fabss");
11775 do_vfp_nsyn_opcode ("fnegd");
11777 do_vfp_nsyn_opcode ("fabsd");
11781 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
11782 insns belong to Neon, and are handled elsewhere. */
11785 do_vfp_nsyn_ldm_stm (int is_dbmode
)
11787 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
11791 do_vfp_nsyn_opcode ("fldmdbs");
11793 do_vfp_nsyn_opcode ("fldmias");
11798 do_vfp_nsyn_opcode ("fstmdbs");
11800 do_vfp_nsyn_opcode ("fstmias");
11805 do_vfp_nsyn_sqrt (void)
11807 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11808 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11811 do_vfp_nsyn_opcode ("fsqrts");
11813 do_vfp_nsyn_opcode ("fsqrtd");
11817 do_vfp_nsyn_div (void)
11819 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11820 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11821 N_F32
| N_F64
| N_KEY
| N_VFP
);
11824 do_vfp_nsyn_opcode ("fdivs");
11826 do_vfp_nsyn_opcode ("fdivd");
11830 do_vfp_nsyn_nmul (void)
11832 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11833 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11834 N_F32
| N_F64
| N_KEY
| N_VFP
);
11838 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11839 do_vfp_sp_dyadic ();
11843 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11844 do_vfp_dp_rd_rn_rm ();
11846 do_vfp_cond_or_thumb ();
11850 do_vfp_nsyn_cmp (void)
11852 if (inst
.operands
[1].isreg
)
11854 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11855 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11859 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11860 do_vfp_sp_monadic ();
11864 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11865 do_vfp_dp_rd_rm ();
11870 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
11871 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
11873 switch (inst
.instruction
& 0x0fffffff)
11876 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
11879 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
11887 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11888 do_vfp_sp_compare_z ();
11892 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11896 do_vfp_cond_or_thumb ();
11900 nsyn_insert_sp (void)
11902 inst
.operands
[1] = inst
.operands
[0];
11903 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
11904 inst
.operands
[0].reg
= REG_SP
;
11905 inst
.operands
[0].isreg
= 1;
11906 inst
.operands
[0].writeback
= 1;
11907 inst
.operands
[0].present
= 1;
11911 do_vfp_nsyn_push (void)
11914 if (inst
.operands
[1].issingle
)
11915 do_vfp_nsyn_opcode ("fstmdbs");
11917 do_vfp_nsyn_opcode ("fstmdbd");
11921 do_vfp_nsyn_pop (void)
11924 if (inst
.operands
[1].issingle
)
11925 do_vfp_nsyn_opcode ("fldmias");
11927 do_vfp_nsyn_opcode ("fldmiad");
11930 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11931 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11934 neon_dp_fixup (unsigned i
)
11938 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11952 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11956 neon_logbits (unsigned x
)
11958 return ffs (x
) - 4;
11961 #define LOW4(R) ((R) & 0xf)
11962 #define HI1(R) (((R) >> 4) & 1)
11964 /* Encode insns with bit pattern:
11966 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11967 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11969 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11970 different meaning for some instruction. */
11973 neon_three_same (int isquad
, int ubit
, int size
)
11975 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11976 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11977 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11978 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11979 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
11980 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
11981 inst
.instruction
|= (isquad
!= 0) << 6;
11982 inst
.instruction
|= (ubit
!= 0) << 24;
11984 inst
.instruction
|= neon_logbits (size
) << 20;
11986 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11989 /* Encode instructions of the form:
11991 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11992 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11994 Don't write size if SIZE == -1. */
11997 neon_two_same (int qbit
, int ubit
, int size
)
11999 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12000 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12001 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12002 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12003 inst
.instruction
|= (qbit
!= 0) << 6;
12004 inst
.instruction
|= (ubit
!= 0) << 24;
12007 inst
.instruction
|= neon_logbits (size
) << 18;
12009 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12012 /* Neon instruction encoders, in approximate order of appearance. */
12015 do_neon_dyadic_i_su (void)
12017 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12018 struct neon_type_el et
= neon_check_type (3, rs
,
12019 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12020 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12024 do_neon_dyadic_i64_su (void)
12026 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12027 struct neon_type_el et
= neon_check_type (3, rs
,
12028 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12029 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12033 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12036 unsigned size
= et
.size
>> 3;
12037 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12038 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12039 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12040 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12041 inst
.instruction
|= (isquad
!= 0) << 6;
12042 inst
.instruction
|= immbits
<< 16;
12043 inst
.instruction
|= (size
>> 3) << 7;
12044 inst
.instruction
|= (size
& 0x7) << 19;
12046 inst
.instruction
|= (uval
!= 0) << 24;
12048 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12052 do_neon_shl_imm (void)
12054 if (!inst
.operands
[2].isreg
)
12056 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12057 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12058 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12059 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12063 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12064 struct neon_type_el et
= neon_check_type (3, rs
,
12065 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12068 /* VSHL/VQSHL 3-register variants have syntax such as:
12070 whereas other 3-register operations encoded by neon_three_same have
12073 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12075 tmp
= inst
.operands
[2].reg
;
12076 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12077 inst
.operands
[1].reg
= tmp
;
12078 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12079 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12084 do_neon_qshl_imm (void)
12086 if (!inst
.operands
[2].isreg
)
12088 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12089 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12091 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12092 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12093 inst
.operands
[2].imm
);
12097 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12098 struct neon_type_el et
= neon_check_type (3, rs
,
12099 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12102 /* See note in do_neon_shl_imm. */
12103 tmp
= inst
.operands
[2].reg
;
12104 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12105 inst
.operands
[1].reg
= tmp
;
12106 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12107 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12112 do_neon_rshl (void)
12114 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12115 struct neon_type_el et
= neon_check_type (3, rs
,
12116 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12119 tmp
= inst
.operands
[2].reg
;
12120 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12121 inst
.operands
[1].reg
= tmp
;
12122 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12126 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12128 /* Handle .I8 pseudo-instructions. */
12131 /* Unfortunately, this will make everything apart from zero out-of-range.
12132 FIXME is this the intended semantics? There doesn't seem much point in
12133 accepting .I8 if so. */
12134 immediate
|= immediate
<< 8;
12140 if (immediate
== (immediate
& 0x000000ff))
12142 *immbits
= immediate
;
12145 else if (immediate
== (immediate
& 0x0000ff00))
12147 *immbits
= immediate
>> 8;
12150 else if (immediate
== (immediate
& 0x00ff0000))
12152 *immbits
= immediate
>> 16;
12155 else if (immediate
== (immediate
& 0xff000000))
12157 *immbits
= immediate
>> 24;
12160 if ((immediate
& 0xffff) != (immediate
>> 16))
12161 goto bad_immediate
;
12162 immediate
&= 0xffff;
12165 if (immediate
== (immediate
& 0x000000ff))
12167 *immbits
= immediate
;
12170 else if (immediate
== (immediate
& 0x0000ff00))
12172 *immbits
= immediate
>> 8;
12177 first_error (_("immediate value out of range"));
12181 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12185 neon_bits_same_in_bytes (unsigned imm
)
12187 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
12188 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
12189 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
12190 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
12193 /* For immediate of above form, return 0bABCD. */
12196 neon_squash_bits (unsigned imm
)
12198 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
12199 | ((imm
& 0x01000000) >> 21);
12202 /* Compress quarter-float representation to 0b...000 abcdefgh. */
12205 neon_qfloat_bits (unsigned imm
)
12207 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
12210 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12211 the instruction. *OP is passed as the initial value of the op field, and
12212 may be set to a different value depending on the constant (i.e.
12213 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
12214 MVN). If the immediate looks like a repeated pattern then also
12215 try smaller element sizes. */
12218 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
12219 unsigned *immbits
, int *op
, int size
,
12220 enum neon_el_type type
)
12222 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
12224 if (type
== NT_float
&& !float_p
)
12227 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
12229 if (size
!= 32 || *op
== 1)
12231 *immbits
= neon_qfloat_bits (immlo
);
12237 if (neon_bits_same_in_bytes (immhi
)
12238 && neon_bits_same_in_bytes (immlo
))
12242 *immbits
= (neon_squash_bits (immhi
) << 4)
12243 | neon_squash_bits (immlo
);
12248 if (immhi
!= immlo
)
12254 if (immlo
== (immlo
& 0x000000ff))
12259 else if (immlo
== (immlo
& 0x0000ff00))
12261 *immbits
= immlo
>> 8;
12264 else if (immlo
== (immlo
& 0x00ff0000))
12266 *immbits
= immlo
>> 16;
12269 else if (immlo
== (immlo
& 0xff000000))
12271 *immbits
= immlo
>> 24;
12274 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
12276 *immbits
= (immlo
>> 8) & 0xff;
12279 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
12281 *immbits
= (immlo
>> 16) & 0xff;
12285 if ((immlo
& 0xffff) != (immlo
>> 16))
12292 if (immlo
== (immlo
& 0x000000ff))
12297 else if (immlo
== (immlo
& 0x0000ff00))
12299 *immbits
= immlo
>> 8;
12303 if ((immlo
& 0xff) != (immlo
>> 8))
12308 if (immlo
== (immlo
& 0x000000ff))
12310 /* Don't allow MVN with 8-bit immediate. */
12320 /* Write immediate bits [7:0] to the following locations:
12322 |28/24|23 19|18 16|15 4|3 0|
12323 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
12325 This function is used by VMOV/VMVN/VORR/VBIC. */
12328 neon_write_immbits (unsigned immbits
)
12330 inst
.instruction
|= immbits
& 0xf;
12331 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
12332 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
12335 /* Invert low-order SIZE bits of XHI:XLO. */
12338 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
12340 unsigned immlo
= xlo
? *xlo
: 0;
12341 unsigned immhi
= xhi
? *xhi
: 0;
12346 immlo
= (~immlo
) & 0xff;
12350 immlo
= (~immlo
) & 0xffff;
12354 immhi
= (~immhi
) & 0xffffffff;
12355 /* fall through. */
12358 immlo
= (~immlo
) & 0xffffffff;
12373 do_neon_logic (void)
12375 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
12377 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12378 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12379 /* U bit and size field were set as part of the bitmask. */
12380 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12381 neon_three_same (neon_quad (rs
), 0, -1);
12385 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12386 struct neon_type_el et
= neon_check_type (2, rs
,
12387 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12388 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
12392 if (et
.type
== NT_invtype
)
12395 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12397 immbits
= inst
.operands
[1].imm
;
12400 /* .i64 is a pseudo-op, so the immediate must be a repeating
12402 if (immbits
!= (inst
.operands
[1].regisimm
?
12403 inst
.operands
[1].reg
: 0))
12405 /* Set immbits to an invalid constant. */
12406 immbits
= 0xdeadbeef;
12413 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12417 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12421 /* Pseudo-instruction for VBIC. */
12422 neon_invert_size (&immbits
, 0, et
.size
);
12423 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12427 /* Pseudo-instruction for VORR. */
12428 neon_invert_size (&immbits
, 0, et
.size
);
12429 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12439 inst
.instruction
|= neon_quad (rs
) << 6;
12440 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12441 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12442 inst
.instruction
|= cmode
<< 8;
12443 neon_write_immbits (immbits
);
12445 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12450 do_neon_bitfield (void)
12452 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12453 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12454 neon_three_same (neon_quad (rs
), 0, -1);
12458 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
12461 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12462 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
12464 if (et
.type
== NT_float
)
12466 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
12467 neon_three_same (neon_quad (rs
), 0, -1);
12471 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12472 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
12477 do_neon_dyadic_if_su (void)
12479 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12483 do_neon_dyadic_if_su_d (void)
12485 /* This version only allow D registers, but that constraint is enforced during
12486 operand parsing so we don't need to do anything extra here. */
12487 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12491 do_neon_dyadic_if_i_d (void)
12493 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12494 affected if we specify unsigned args. */
12495 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12498 enum vfp_or_neon_is_neon_bits
12501 NEON_CHECK_ARCH
= 2
12504 /* Call this function if an instruction which may have belonged to the VFP or
12505 Neon instruction sets, but turned out to be a Neon instruction (due to the
12506 operand types involved, etc.). We have to check and/or fix-up a couple of
12509 - Make sure the user hasn't attempted to make a Neon instruction
12511 - Alter the value in the condition code field if necessary.
12512 - Make sure that the arch supports Neon instructions.
12514 Which of these operations take place depends on bits from enum
12515 vfp_or_neon_is_neon_bits.
12517 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12518 current instruction's condition is COND_ALWAYS, the condition field is
12519 changed to inst.uncond_value. This is necessary because instructions shared
12520 between VFP and Neon may be conditional for the VFP variants only, and the
12521 unconditional Neon version must have, e.g., 0xF in the condition field. */
12524 vfp_or_neon_is_neon (unsigned check
)
12526 /* Conditions are always legal in Thumb mode (IT blocks). */
12527 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
12529 if (inst
.cond
!= COND_ALWAYS
)
12531 first_error (_(BAD_COND
));
12534 if (inst
.uncond_value
!= -1)
12535 inst
.instruction
|= inst
.uncond_value
<< 28;
12538 if ((check
& NEON_CHECK_ARCH
)
12539 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
12541 first_error (_(BAD_FPU
));
12549 do_neon_addsub_if_i (void)
12551 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
12554 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12557 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12558 affected if we specify unsigned args. */
12559 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
12562 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
12564 V<op> A,B (A is operand 0, B is operand 2)
12569 so handle that case specially. */
12572 neon_exchange_operands (void)
12574 void *scratch
= alloca (sizeof (inst
.operands
[0]));
12575 if (inst
.operands
[1].present
)
12577 /* Swap operands[1] and operands[2]. */
12578 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
12579 inst
.operands
[1] = inst
.operands
[2];
12580 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
12584 inst
.operands
[1] = inst
.operands
[2];
12585 inst
.operands
[2] = inst
.operands
[0];
12590 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
12592 if (inst
.operands
[2].isreg
)
12595 neon_exchange_operands ();
12596 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
12600 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12601 struct neon_type_el et
= neon_check_type (2, rs
,
12602 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
12604 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12605 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12606 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12607 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12608 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12609 inst
.instruction
|= neon_quad (rs
) << 6;
12610 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12611 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12613 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12620 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
12624 do_neon_cmp_inv (void)
12626 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
12632 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
12635 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
12636 scalars, which are encoded in 5 bits, M : Rm.
12637 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
12638 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
12642 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
12644 unsigned regno
= NEON_SCALAR_REG (scalar
);
12645 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
12650 if (regno
> 7 || elno
> 3)
12652 return regno
| (elno
<< 3);
12655 if (regno
> 15 || elno
> 1)
12657 return regno
| (elno
<< 4);
12661 first_error (_("scalar out of range for multiply instruction"));
12667 /* Encode multiply / multiply-accumulate scalar instructions. */
12670 neon_mul_mac (struct neon_type_el et
, int ubit
)
12674 /* Give a more helpful error message if we have an invalid type. */
12675 if (et
.type
== NT_invtype
)
12678 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
12679 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12680 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12681 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12682 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12683 inst
.instruction
|= LOW4 (scalar
);
12684 inst
.instruction
|= HI1 (scalar
) << 5;
12685 inst
.instruction
|= (et
.type
== NT_float
) << 8;
12686 inst
.instruction
|= neon_logbits (et
.size
) << 20;
12687 inst
.instruction
|= (ubit
!= 0) << 24;
12689 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12693 do_neon_mac_maybe_scalar (void)
12695 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
12698 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12701 if (inst
.operands
[2].isscalar
)
12703 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12704 struct neon_type_el et
= neon_check_type (3, rs
,
12705 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
12706 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12707 neon_mul_mac (et
, neon_quad (rs
));
12711 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12712 affected if we specify unsigned args. */
12713 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12720 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12721 struct neon_type_el et
= neon_check_type (3, rs
,
12722 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12723 neon_three_same (neon_quad (rs
), 0, et
.size
);
12726 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
12727 same types as the MAC equivalents. The polynomial type for this instruction
12728 is encoded the same as the integer type. */
12733 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
12736 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12739 if (inst
.operands
[2].isscalar
)
12740 do_neon_mac_maybe_scalar ();
12742 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
12746 do_neon_qdmulh (void)
12748 if (inst
.operands
[2].isscalar
)
12750 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12751 struct neon_type_el et
= neon_check_type (3, rs
,
12752 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12753 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12754 neon_mul_mac (et
, neon_quad (rs
));
12758 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12759 struct neon_type_el et
= neon_check_type (3, rs
,
12760 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12761 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12762 /* The U bit (rounding) comes from bit mask. */
12763 neon_three_same (neon_quad (rs
), 0, et
.size
);
12768 do_neon_fcmp_absolute (void)
12770 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12771 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12772 /* Size field comes from bit mask. */
12773 neon_three_same (neon_quad (rs
), 1, -1);
12777 do_neon_fcmp_absolute_inv (void)
12779 neon_exchange_operands ();
12780 do_neon_fcmp_absolute ();
12784 do_neon_step (void)
12786 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12787 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12788 neon_three_same (neon_quad (rs
), 0, -1);
12792 do_neon_abs_neg (void)
12794 enum neon_shape rs
;
12795 struct neon_type_el et
;
12797 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
12800 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12803 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12804 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
12806 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12807 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12808 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12809 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12810 inst
.instruction
|= neon_quad (rs
) << 6;
12811 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12812 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12814 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12820 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12821 struct neon_type_el et
= neon_check_type (2, rs
,
12822 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12823 int imm
= inst
.operands
[2].imm
;
12824 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12825 _("immediate out of range for insert"));
12826 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12832 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12833 struct neon_type_el et
= neon_check_type (2, rs
,
12834 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12835 int imm
= inst
.operands
[2].imm
;
12836 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12837 _("immediate out of range for insert"));
12838 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
12842 do_neon_qshlu_imm (void)
12844 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12845 struct neon_type_el et
= neon_check_type (2, rs
,
12846 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
12847 int imm
= inst
.operands
[2].imm
;
12848 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12849 _("immediate out of range for shift"));
12850 /* Only encodes the 'U present' variant of the instruction.
12851 In this case, signed types have OP (bit 8) set to 0.
12852 Unsigned types have OP set to 1. */
12853 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
12854 /* The rest of the bits are the same as other immediate shifts. */
12855 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12859 do_neon_qmovn (void)
12861 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12862 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12863 /* Saturating move where operands can be signed or unsigned, and the
12864 destination has the same signedness. */
12865 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12866 if (et
.type
== NT_unsigned
)
12867 inst
.instruction
|= 0xc0;
12869 inst
.instruction
|= 0x80;
12870 neon_two_same (0, 1, et
.size
/ 2);
12874 do_neon_qmovun (void)
12876 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12877 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12878 /* Saturating move with unsigned results. Operands must be signed. */
12879 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12880 neon_two_same (0, 1, et
.size
/ 2);
12884 do_neon_rshift_sat_narrow (void)
12886 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12887 or unsigned. If operands are unsigned, results must also be unsigned. */
12888 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12889 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12890 int imm
= inst
.operands
[2].imm
;
12891 /* This gets the bounds check, size encoding and immediate bits calculation
12895 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12896 VQMOVN.I<size> <Dd>, <Qm>. */
12899 inst
.operands
[2].present
= 0;
12900 inst
.instruction
= N_MNEM_vqmovn
;
12905 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12906 _("immediate out of range"));
12907 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
12911 do_neon_rshift_sat_narrow_u (void)
12913 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12914 or unsigned. If operands are unsigned, results must also be unsigned. */
12915 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12916 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12917 int imm
= inst
.operands
[2].imm
;
12918 /* This gets the bounds check, size encoding and immediate bits calculation
12922 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12923 VQMOVUN.I<size> <Dd>, <Qm>. */
12926 inst
.operands
[2].present
= 0;
12927 inst
.instruction
= N_MNEM_vqmovun
;
12932 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12933 _("immediate out of range"));
12934 /* FIXME: The manual is kind of unclear about what value U should have in
12935 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12937 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
12941 do_neon_movn (void)
12943 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12944 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12945 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12946 neon_two_same (0, 1, et
.size
/ 2);
12950 do_neon_rshift_narrow (void)
12952 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12953 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12954 int imm
= inst
.operands
[2].imm
;
12955 /* This gets the bounds check, size encoding and immediate bits calculation
12959 /* If immediate is zero then we are a pseudo-instruction for
12960 VMOVN.I<size> <Dd>, <Qm> */
12963 inst
.operands
[2].present
= 0;
12964 inst
.instruction
= N_MNEM_vmovn
;
12969 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12970 _("immediate out of range for narrowing operation"));
12971 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
12975 do_neon_shll (void)
12977 /* FIXME: Type checking when lengthening. */
12978 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
12979 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
12980 unsigned imm
= inst
.operands
[2].imm
;
12982 if (imm
== et
.size
)
12984 /* Maximum shift variant. */
12985 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12986 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12987 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12988 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12989 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12990 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12992 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12996 /* A more-specific type check for non-max versions. */
12997 et
= neon_check_type (2, NS_QDI
,
12998 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12999 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13000 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13004 /* Check the various types for the VCVT instruction, and return which version
13005 the current instruction is. */
13008 neon_cvt_flavour (enum neon_shape rs
)
13010 #define CVT_VAR(C,X,Y) \
13011 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13012 if (et.type != NT_invtype) \
13014 inst.error = NULL; \
13017 struct neon_type_el et
;
13018 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13019 || rs
== NS_FF
) ? N_VFP
: 0;
13020 /* The instruction versions which take an immediate take one register
13021 argument, which is extended to the width of the full register. Thus the
13022 "source" and "destination" registers must have the same width. Hack that
13023 here by making the size equal to the key (wider, in this case) operand. */
13024 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13026 CVT_VAR (0, N_S32
, N_F32
);
13027 CVT_VAR (1, N_U32
, N_F32
);
13028 CVT_VAR (2, N_F32
, N_S32
);
13029 CVT_VAR (3, N_F32
, N_U32
);
13030 /* Half-precision conversions. */
13031 CVT_VAR (4, N_F32
, N_F16
);
13032 CVT_VAR (5, N_F16
, N_F32
);
13036 /* VFP instructions. */
13037 CVT_VAR (6, N_F32
, N_F64
);
13038 CVT_VAR (7, N_F64
, N_F32
);
13039 CVT_VAR (8, N_S32
, N_F64
| key
);
13040 CVT_VAR (9, N_U32
, N_F64
| key
);
13041 CVT_VAR (10, N_F64
| key
, N_S32
);
13042 CVT_VAR (11, N_F64
| key
, N_U32
);
13043 /* VFP instructions with bitshift. */
13044 CVT_VAR (12, N_F32
| key
, N_S16
);
13045 CVT_VAR (13, N_F32
| key
, N_U16
);
13046 CVT_VAR (14, N_F64
| key
, N_S16
);
13047 CVT_VAR (15, N_F64
| key
, N_U16
);
13048 CVT_VAR (16, N_S16
, N_F32
| key
);
13049 CVT_VAR (17, N_U16
, N_F32
| key
);
13050 CVT_VAR (18, N_S16
, N_F64
| key
);
13051 CVT_VAR (19, N_U16
, N_F64
| key
);
13057 /* Neon-syntax VFP conversions. */
13060 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13062 const char *opname
= 0;
13064 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13066 /* Conversions with immediate bitshift. */
13067 const char *enc
[] =
13091 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13093 opname
= enc
[flavour
];
13094 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13095 _("operands 0 and 1 must be the same register"));
13096 inst
.operands
[1] = inst
.operands
[2];
13097 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13102 /* Conversions without bitshift. */
13103 const char *enc
[] =
13119 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13120 opname
= enc
[flavour
];
13124 do_vfp_nsyn_opcode (opname
);
13128 do_vfp_nsyn_cvtz (void)
13130 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
13131 int flavour
= neon_cvt_flavour (rs
);
13132 const char *enc
[] =
13146 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
13147 do_vfp_nsyn_opcode (enc
[flavour
]);
13153 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
13154 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
13155 int flavour
= neon_cvt_flavour (rs
);
13157 /* VFP rather than Neon conversions. */
13160 do_vfp_nsyn_cvt (rs
, flavour
);
13170 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13172 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13175 /* Fixed-point conversion with #0 immediate is encoded as an
13176 integer conversion. */
13177 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
13179 immbits
= 32 - inst
.operands
[2].imm
;
13180 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13182 inst
.instruction
|= enctab
[flavour
];
13183 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13184 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13185 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13186 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13187 inst
.instruction
|= neon_quad (rs
) << 6;
13188 inst
.instruction
|= 1 << 21;
13189 inst
.instruction
|= immbits
<< 16;
13191 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13199 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
13201 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13203 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13207 inst
.instruction
|= enctab
[flavour
];
13209 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13210 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13211 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13212 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13213 inst
.instruction
|= neon_quad (rs
) << 6;
13214 inst
.instruction
|= 2 << 18;
13216 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13220 /* Half-precision conversions for Advanced SIMD -- neon. */
13225 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
13227 as_bad (_("operand size must match register width"));
13232 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
13234 as_bad (_("operand size must match register width"));
13239 inst
.instruction
= 0x3b60600;
13241 inst
.instruction
= 0x3b60700;
13243 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13244 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13245 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13246 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13247 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13251 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
13252 do_vfp_nsyn_cvt (rs
, flavour
);
13257 do_neon_cvtb (void)
13259 inst
.instruction
= 0xeb20a40;
13261 /* The sizes are attached to the mnemonic. */
13262 if (inst
.vectype
.el
[0].type
!= NT_invtype
13263 && inst
.vectype
.el
[0].size
== 16)
13264 inst
.instruction
|= 0x00010000;
13266 /* Programmer's syntax: the sizes are attached to the operands. */
13267 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
13268 && inst
.operands
[0].vectype
.size
== 16)
13269 inst
.instruction
|= 0x00010000;
13271 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
13272 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
13273 do_vfp_cond_or_thumb ();
13278 do_neon_cvtt (void)
13281 inst
.instruction
|= 0x80;
13285 neon_move_immediate (void)
13287 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
13288 struct neon_type_el et
= neon_check_type (2, rs
,
13289 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13290 unsigned immlo
, immhi
= 0, immbits
;
13291 int op
, cmode
, float_p
;
13293 constraint (et
.type
== NT_invtype
,
13294 _("operand size must be specified for immediate VMOV"));
13296 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
13297 op
= (inst
.instruction
& (1 << 5)) != 0;
13299 immlo
= inst
.operands
[1].imm
;
13300 if (inst
.operands
[1].regisimm
)
13301 immhi
= inst
.operands
[1].reg
;
13303 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
13304 _("immediate has bits set outside the operand size"));
13306 float_p
= inst
.operands
[1].immisfloat
;
13308 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
13309 et
.size
, et
.type
)) == FAIL
)
13311 /* Invert relevant bits only. */
13312 neon_invert_size (&immlo
, &immhi
, et
.size
);
13313 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
13314 with one or the other; those cases are caught by
13315 neon_cmode_for_move_imm. */
13317 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
13318 &op
, et
.size
, et
.type
)) == FAIL
)
13320 first_error (_("immediate out of range"));
13325 inst
.instruction
&= ~(1 << 5);
13326 inst
.instruction
|= op
<< 5;
13328 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13329 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13330 inst
.instruction
|= neon_quad (rs
) << 6;
13331 inst
.instruction
|= cmode
<< 8;
13333 neon_write_immbits (immbits
);
13339 if (inst
.operands
[1].isreg
)
13341 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13343 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13344 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13345 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13346 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13347 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13348 inst
.instruction
|= neon_quad (rs
) << 6;
13352 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13353 neon_move_immediate ();
13356 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13359 /* Encode instructions of form:
13361 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13362 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
13365 neon_mixed_length (struct neon_type_el et
, unsigned size
)
13367 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13368 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13369 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13370 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13371 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13372 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13373 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
13374 inst
.instruction
|= neon_logbits (size
) << 20;
13376 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13380 do_neon_dyadic_long (void)
13382 /* FIXME: Type checking for lengthening op. */
13383 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13384 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13385 neon_mixed_length (et
, et
.size
);
13389 do_neon_abal (void)
13391 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13392 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13393 neon_mixed_length (et
, et
.size
);
13397 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
13399 if (inst
.operands
[2].isscalar
)
13401 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
13402 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
13403 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13404 neon_mul_mac (et
, et
.type
== NT_unsigned
);
13408 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13409 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
13410 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13411 neon_mixed_length (et
, et
.size
);
13416 do_neon_mac_maybe_scalar_long (void)
13418 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
13422 do_neon_dyadic_wide (void)
13424 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
13425 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13426 neon_mixed_length (et
, et
.size
);
13430 do_neon_dyadic_narrow (void)
13432 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13433 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
13434 /* Operand sign is unimportant, and the U bit is part of the opcode,
13435 so force the operand type to integer. */
13436 et
.type
= NT_integer
;
13437 neon_mixed_length (et
, et
.size
/ 2);
13441 do_neon_mul_sat_scalar_long (void)
13443 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
13447 do_neon_vmull (void)
13449 if (inst
.operands
[2].isscalar
)
13450 do_neon_mac_maybe_scalar_long ();
13453 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13454 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
13455 if (et
.type
== NT_poly
)
13456 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
13458 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13459 /* For polynomial encoding, size field must be 0b00 and the U bit must be
13460 zero. Should be OK as-is. */
13461 neon_mixed_length (et
, et
.size
);
13468 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
13469 struct neon_type_el et
= neon_check_type (3, rs
,
13470 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13471 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
13473 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
13474 _("shift out of range"));
13475 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13476 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13477 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13478 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13479 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13480 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13481 inst
.instruction
|= neon_quad (rs
) << 6;
13482 inst
.instruction
|= imm
<< 8;
13484 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13490 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13491 struct neon_type_el et
= neon_check_type (2, rs
,
13492 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13493 unsigned op
= (inst
.instruction
>> 7) & 3;
13494 /* N (width of reversed regions) is encoded as part of the bitmask. We
13495 extract it here to check the elements to be reversed are smaller.
13496 Otherwise we'd get a reserved instruction. */
13497 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
13498 assert (elsize
!= 0);
13499 constraint (et
.size
>= elsize
,
13500 _("elements must be smaller than reversal region"));
13501 neon_two_same (neon_quad (rs
), 1, et
.size
);
13507 if (inst
.operands
[1].isscalar
)
13509 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
13510 struct neon_type_el et
= neon_check_type (2, rs
,
13511 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13512 unsigned sizebits
= et
.size
>> 3;
13513 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13514 int logsize
= neon_logbits (et
.size
);
13515 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
13517 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
13520 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13521 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13522 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13523 inst
.instruction
|= LOW4 (dm
);
13524 inst
.instruction
|= HI1 (dm
) << 5;
13525 inst
.instruction
|= neon_quad (rs
) << 6;
13526 inst
.instruction
|= x
<< 17;
13527 inst
.instruction
|= sizebits
<< 16;
13529 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13533 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
13534 struct neon_type_el et
= neon_check_type (2, rs
,
13535 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13536 /* Duplicate ARM register to lanes of vector. */
13537 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
13540 case 8: inst
.instruction
|= 0x400000; break;
13541 case 16: inst
.instruction
|= 0x000020; break;
13542 case 32: inst
.instruction
|= 0x000000; break;
13545 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13546 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
13547 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
13548 inst
.instruction
|= neon_quad (rs
) << 21;
13549 /* The encoding for this instruction is identical for the ARM and Thumb
13550 variants, except for the condition field. */
13551 do_vfp_cond_or_thumb ();
13555 /* VMOV has particularly many variations. It can be one of:
13556 0. VMOV<c><q> <Qd>, <Qm>
13557 1. VMOV<c><q> <Dd>, <Dm>
13558 (Register operations, which are VORR with Rm = Rn.)
13559 2. VMOV<c><q>.<dt> <Qd>, #<imm>
13560 3. VMOV<c><q>.<dt> <Dd>, #<imm>
13562 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
13563 (ARM register to scalar.)
13564 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
13565 (Two ARM registers to vector.)
13566 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
13567 (Scalar to ARM register.)
13568 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
13569 (Vector to two ARM registers.)
13570 8. VMOV.F32 <Sd>, <Sm>
13571 9. VMOV.F64 <Dd>, <Dm>
13572 (VFP register moves.)
13573 10. VMOV.F32 <Sd>, #imm
13574 11. VMOV.F64 <Dd>, #imm
13575 (VFP float immediate load.)
13576 12. VMOV <Rd>, <Sm>
13577 (VFP single to ARM reg.)
13578 13. VMOV <Sd>, <Rm>
13579 (ARM reg to VFP single.)
13580 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
13581 (Two ARM regs to two VFP singles.)
13582 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
13583 (Two VFP singles to two ARM regs.)
13585 These cases can be disambiguated using neon_select_shape, except cases 1/9
13586 and 3/11 which depend on the operand type too.
13588 All the encoded bits are hardcoded by this function.
13590 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
13591 Cases 5, 7 may be used with VFPv2 and above.
13593 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
13594 can specify a type where it doesn't make sense to, and is ignored). */
13599 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
13600 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
13602 struct neon_type_el et
;
13603 const char *ldconst
= 0;
13607 case NS_DD
: /* case 1/9. */
13608 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13609 /* It is not an error here if no type is given. */
13611 if (et
.type
== NT_float
&& et
.size
== 64)
13613 do_vfp_nsyn_opcode ("fcpyd");
13616 /* fall through. */
13618 case NS_QQ
: /* case 0/1. */
13620 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13622 /* The architecture manual I have doesn't explicitly state which
13623 value the U bit should have for register->register moves, but
13624 the equivalent VORR instruction has U = 0, so do that. */
13625 inst
.instruction
= 0x0200110;
13626 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13627 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13628 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13629 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13630 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13631 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13632 inst
.instruction
|= neon_quad (rs
) << 6;
13634 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13638 case NS_DI
: /* case 3/11. */
13639 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13641 if (et
.type
== NT_float
&& et
.size
== 64)
13643 /* case 11 (fconstd). */
13644 ldconst
= "fconstd";
13645 goto encode_fconstd
;
13647 /* fall through. */
13649 case NS_QI
: /* case 2/3. */
13650 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13652 inst
.instruction
= 0x0800010;
13653 neon_move_immediate ();
13654 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13657 case NS_SR
: /* case 4. */
13659 unsigned bcdebits
= 0;
13660 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13661 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13662 int logsize
= neon_logbits (et
.size
);
13663 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
13664 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
13666 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13668 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13669 && et
.size
!= 32, _(BAD_FPU
));
13670 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13671 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13675 case 8: bcdebits
= 0x8; break;
13676 case 16: bcdebits
= 0x1; break;
13677 case 32: bcdebits
= 0x0; break;
13681 bcdebits
|= x
<< logsize
;
13683 inst
.instruction
= 0xe000b10;
13684 do_vfp_cond_or_thumb ();
13685 inst
.instruction
|= LOW4 (dn
) << 16;
13686 inst
.instruction
|= HI1 (dn
) << 7;
13687 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13688 inst
.instruction
|= (bcdebits
& 3) << 5;
13689 inst
.instruction
|= (bcdebits
>> 2) << 21;
13693 case NS_DRR
: /* case 5 (fmdrr). */
13694 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13697 inst
.instruction
= 0xc400b10;
13698 do_vfp_cond_or_thumb ();
13699 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
13700 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
13701 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13702 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13705 case NS_RS
: /* case 6. */
13707 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13708 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
13709 unsigned logsize
= neon_logbits (et
.size
);
13710 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13711 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
13712 unsigned abcdebits
= 0;
13714 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13716 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13717 && et
.size
!= 32, _(BAD_FPU
));
13718 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13719 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13723 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
13724 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
13725 case 32: abcdebits
= 0x00; break;
13729 abcdebits
|= x
<< logsize
;
13730 inst
.instruction
= 0xe100b10;
13731 do_vfp_cond_or_thumb ();
13732 inst
.instruction
|= LOW4 (dn
) << 16;
13733 inst
.instruction
|= HI1 (dn
) << 7;
13734 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13735 inst
.instruction
|= (abcdebits
& 3) << 5;
13736 inst
.instruction
|= (abcdebits
>> 2) << 21;
13740 case NS_RRD
: /* case 7 (fmrrd). */
13741 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13744 inst
.instruction
= 0xc500b10;
13745 do_vfp_cond_or_thumb ();
13746 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13747 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13748 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13749 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13752 case NS_FF
: /* case 8 (fcpys). */
13753 do_vfp_nsyn_opcode ("fcpys");
13756 case NS_FI
: /* case 10 (fconsts). */
13757 ldconst
= "fconsts";
13759 if (is_quarter_float (inst
.operands
[1].imm
))
13761 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
13762 do_vfp_nsyn_opcode (ldconst
);
13765 first_error (_("immediate out of range"));
13768 case NS_RF
: /* case 12 (fmrs). */
13769 do_vfp_nsyn_opcode ("fmrs");
13772 case NS_FR
: /* case 13 (fmsr). */
13773 do_vfp_nsyn_opcode ("fmsr");
13776 /* The encoders for the fmrrs and fmsrr instructions expect three operands
13777 (one of which is a list), but we have parsed four. Do some fiddling to
13778 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
13780 case NS_RRFF
: /* case 14 (fmrrs). */
13781 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
13782 _("VFP registers must be adjacent"));
13783 inst
.operands
[2].imm
= 2;
13784 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13785 do_vfp_nsyn_opcode ("fmrrs");
13788 case NS_FFRR
: /* case 15 (fmsrr). */
13789 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
13790 _("VFP registers must be adjacent"));
13791 inst
.operands
[1] = inst
.operands
[2];
13792 inst
.operands
[2] = inst
.operands
[3];
13793 inst
.operands
[0].imm
= 2;
13794 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13795 do_vfp_nsyn_opcode ("fmsrr");
13804 do_neon_rshift_round_imm (void)
13806 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13807 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13808 int imm
= inst
.operands
[2].imm
;
13810 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
13813 inst
.operands
[2].present
= 0;
13818 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13819 _("immediate out of range for shift"));
13820 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13825 do_neon_movl (void)
13827 struct neon_type_el et
= neon_check_type (2, NS_QD
,
13828 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13829 unsigned sizebits
= et
.size
>> 3;
13830 inst
.instruction
|= sizebits
<< 19;
13831 neon_two_same (0, et
.type
== NT_unsigned
, -1);
13837 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13838 struct neon_type_el et
= neon_check_type (2, rs
,
13839 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13840 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13841 neon_two_same (neon_quad (rs
), 1, et
.size
);
13845 do_neon_zip_uzp (void)
13847 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13848 struct neon_type_el et
= neon_check_type (2, rs
,
13849 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13850 if (rs
== NS_DD
&& et
.size
== 32)
13852 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
13853 inst
.instruction
= N_MNEM_vtrn
;
13857 neon_two_same (neon_quad (rs
), 1, et
.size
);
13861 do_neon_sat_abs_neg (void)
13863 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13864 struct neon_type_el et
= neon_check_type (2, rs
,
13865 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13866 neon_two_same (neon_quad (rs
), 1, et
.size
);
13870 do_neon_pair_long (void)
13872 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13873 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
13874 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
13875 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
13876 neon_two_same (neon_quad (rs
), 1, et
.size
);
13880 do_neon_recip_est (void)
13882 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13883 struct neon_type_el et
= neon_check_type (2, rs
,
13884 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
13885 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13886 neon_two_same (neon_quad (rs
), 1, et
.size
);
13892 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13893 struct neon_type_el et
= neon_check_type (2, rs
,
13894 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13895 neon_two_same (neon_quad (rs
), 1, et
.size
);
13901 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13902 struct neon_type_el et
= neon_check_type (2, rs
,
13903 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
13904 neon_two_same (neon_quad (rs
), 1, et
.size
);
13910 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13911 struct neon_type_el et
= neon_check_type (2, rs
,
13912 N_EQK
| N_INT
, N_8
| N_KEY
);
13913 neon_two_same (neon_quad (rs
), 1, et
.size
);
13919 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13920 neon_two_same (neon_quad (rs
), 1, -1);
13924 do_neon_tbl_tbx (void)
13926 unsigned listlenbits
;
13927 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
13929 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
13931 first_error (_("bad list length for table lookup"));
13935 listlenbits
= inst
.operands
[1].imm
- 1;
13936 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13937 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13938 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13939 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13940 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13941 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13942 inst
.instruction
|= listlenbits
<< 8;
13944 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13948 do_neon_ldm_stm (void)
13950 /* P, U and L bits are part of bitmask. */
13951 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
13952 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
13954 if (inst
.operands
[1].issingle
)
13956 do_vfp_nsyn_ldm_stm (is_dbmode
);
13960 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
13961 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13963 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
13964 _("register list must contain at least 1 and at most 16 "
13967 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
13968 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
13969 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13970 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
13972 inst
.instruction
|= offsetbits
;
13974 do_vfp_cond_or_thumb ();
13978 do_neon_ldr_str (void)
13980 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
13982 if (inst
.operands
[0].issingle
)
13985 do_vfp_nsyn_opcode ("flds");
13987 do_vfp_nsyn_opcode ("fsts");
13992 do_vfp_nsyn_opcode ("fldd");
13994 do_vfp_nsyn_opcode ("fstd");
13998 /* "interleave" version also handles non-interleaving register VLD1/VST1
14002 do_neon_ld_st_interleave (void)
14004 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14005 N_8
| N_16
| N_32
| N_64
);
14006 unsigned alignbits
= 0;
14008 /* The bits in this table go:
14009 0: register stride of one (0) or two (1)
14010 1,2: register list length, minus one (1, 2, 3, 4).
14011 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14012 We use -1 for invalid entries. */
14013 const int typetable
[] =
14015 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14016 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14017 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14018 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14022 if (et
.type
== NT_invtype
)
14025 if (inst
.operands
[1].immisalign
)
14026 switch (inst
.operands
[1].imm
>> 8)
14028 case 64: alignbits
= 1; break;
14030 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14031 goto bad_alignment
;
14035 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14036 goto bad_alignment
;
14041 first_error (_("bad alignment"));
14045 inst
.instruction
|= alignbits
<< 4;
14046 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14048 /* Bits [4:6] of the immediate in a list specifier encode register stride
14049 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14050 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14051 up the right value for "type" in a table based on this value and the given
14052 list style, then stick it back. */
14053 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14054 | (((inst
.instruction
>> 8) & 3) << 3);
14056 typebits
= typetable
[idx
];
14058 constraint (typebits
== -1, _("bad list type for instruction"));
14060 inst
.instruction
&= ~0xf00;
14061 inst
.instruction
|= typebits
<< 8;
14064 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14065 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14066 otherwise. The variable arguments are a list of pairs of legal (size, align)
14067 values, terminated with -1. */
14070 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14073 int result
= FAIL
, thissize
, thisalign
;
14075 if (!inst
.operands
[1].immisalign
)
14081 va_start (ap
, do_align
);
14085 thissize
= va_arg (ap
, int);
14086 if (thissize
== -1)
14088 thisalign
= va_arg (ap
, int);
14090 if (size
== thissize
&& align
== thisalign
)
14093 while (result
!= SUCCESS
);
14097 if (result
== SUCCESS
)
14100 first_error (_("unsupported alignment for instruction"));
14106 do_neon_ld_st_lane (void)
14108 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14109 int align_good
, do_align
= 0;
14110 int logsize
= neon_logbits (et
.size
);
14111 int align
= inst
.operands
[1].imm
>> 8;
14112 int n
= (inst
.instruction
>> 8) & 3;
14113 int max_el
= 64 / et
.size
;
14115 if (et
.type
== NT_invtype
)
14118 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
14119 _("bad list length"));
14120 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
14121 _("scalar index out of range"));
14122 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
14124 _("stride of 2 unavailable when element size is 8"));
14128 case 0: /* VLD1 / VST1. */
14129 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
14131 if (align_good
== FAIL
)
14135 unsigned alignbits
= 0;
14138 case 16: alignbits
= 0x1; break;
14139 case 32: alignbits
= 0x3; break;
14142 inst
.instruction
|= alignbits
<< 4;
14146 case 1: /* VLD2 / VST2. */
14147 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
14149 if (align_good
== FAIL
)
14152 inst
.instruction
|= 1 << 4;
14155 case 2: /* VLD3 / VST3. */
14156 constraint (inst
.operands
[1].immisalign
,
14157 _("can't use alignment with this instruction"));
14160 case 3: /* VLD4 / VST4. */
14161 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14162 16, 64, 32, 64, 32, 128, -1);
14163 if (align_good
== FAIL
)
14167 unsigned alignbits
= 0;
14170 case 8: alignbits
= 0x1; break;
14171 case 16: alignbits
= 0x1; break;
14172 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
14175 inst
.instruction
|= alignbits
<< 4;
14182 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
14183 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14184 inst
.instruction
|= 1 << (4 + logsize
);
14186 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
14187 inst
.instruction
|= logsize
<< 10;
14190 /* Encode single n-element structure to all lanes VLD<n> instructions. */
14193 do_neon_ld_dup (void)
14195 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14196 int align_good
, do_align
= 0;
14198 if (et
.type
== NT_invtype
)
14201 switch ((inst
.instruction
>> 8) & 3)
14203 case 0: /* VLD1. */
14204 assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
14205 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14206 &do_align
, 16, 16, 32, 32, -1);
14207 if (align_good
== FAIL
)
14209 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
14212 case 2: inst
.instruction
|= 1 << 5; break;
14213 default: first_error (_("bad list length")); return;
14215 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14218 case 1: /* VLD2. */
14219 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14220 &do_align
, 8, 16, 16, 32, 32, 64, -1);
14221 if (align_good
== FAIL
)
14223 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
14224 _("bad list length"));
14225 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14226 inst
.instruction
|= 1 << 5;
14227 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14230 case 2: /* VLD3. */
14231 constraint (inst
.operands
[1].immisalign
,
14232 _("can't use alignment with this instruction"));
14233 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
14234 _("bad list length"));
14235 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14236 inst
.instruction
|= 1 << 5;
14237 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14240 case 3: /* VLD4. */
14242 int align
= inst
.operands
[1].imm
>> 8;
14243 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14244 16, 64, 32, 64, 32, 128, -1);
14245 if (align_good
== FAIL
)
14247 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
14248 _("bad list length"));
14249 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14250 inst
.instruction
|= 1 << 5;
14251 if (et
.size
== 32 && align
== 128)
14252 inst
.instruction
|= 0x3 << 6;
14254 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14261 inst
.instruction
|= do_align
<< 4;
14264 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
14265 apart from bits [11:4]. */
14268 do_neon_ldx_stx (void)
14270 switch (NEON_LANE (inst
.operands
[0].imm
))
14272 case NEON_INTERLEAVE_LANES
:
14273 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
14274 do_neon_ld_st_interleave ();
14277 case NEON_ALL_LANES
:
14278 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
14283 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
14284 do_neon_ld_st_lane ();
14287 /* L bit comes from bit mask. */
14288 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14289 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14290 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14292 if (inst
.operands
[1].postind
)
14294 int postreg
= inst
.operands
[1].imm
& 0xf;
14295 constraint (!inst
.operands
[1].immisreg
,
14296 _("post-index must be a register"));
14297 constraint (postreg
== 0xd || postreg
== 0xf,
14298 _("bad register for post-index"));
14299 inst
.instruction
|= postreg
;
14301 else if (inst
.operands
[1].writeback
)
14303 inst
.instruction
|= 0xd;
14306 inst
.instruction
|= 0xf;
14309 inst
.instruction
|= 0xf9000000;
14311 inst
.instruction
|= 0xf4000000;
14314 /* Overall per-instruction processing. */
14316 /* We need to be able to fix up arbitrary expressions in some statements.
14317 This is so that we can handle symbols that are an arbitrary distance from
14318 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
14319 which returns part of an address in a form which will be valid for
14320 a data instruction. We do this by pushing the expression into a symbol
14321 in the expr_section, and creating a fix for that. */
14324 fix_new_arm (fragS
* frag
,
14339 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
14343 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
14348 /* Mark whether the fix is to a THUMB instruction, or an ARM
14350 new_fix
->tc_fix_data
= thumb_mode
;
14353 /* Create a frg for an instruction requiring relaxation. */
14355 output_relax_insn (void)
14361 /* The size of the instruction is unknown, so tie the debug info to the
14362 start of the instruction. */
14363 dwarf2_emit_insn (0);
14365 switch (inst
.reloc
.exp
.X_op
)
14368 sym
= inst
.reloc
.exp
.X_add_symbol
;
14369 offset
= inst
.reloc
.exp
.X_add_number
;
14373 offset
= inst
.reloc
.exp
.X_add_number
;
14376 sym
= make_expr_symbol (&inst
.reloc
.exp
);
14380 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
14381 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
14382 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
14385 /* Write a 32-bit thumb instruction to buf. */
14387 put_thumb32_insn (char * buf
, unsigned long insn
)
14389 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
14390 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
14394 output_inst (const char * str
)
14400 as_bad ("%s -- `%s'", inst
.error
, str
);
14405 output_relax_insn ();
14408 if (inst
.size
== 0)
14411 to
= frag_more (inst
.size
);
14412 /* PR 9814: Record the thumb mode into the current frag so that we know
14413 what type of NOP padding to use, if necessary. We override any previous
14414 setting so that if the mode has changed then the NOPS that we use will
14415 match the encoding of the last instruction in the frag. */
14416 frag_now
->tc_frag_data
= thumb_mode
| MODE_RECORDED
;
14418 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
14420 assert (inst
.size
== (2 * THUMB_SIZE
));
14421 put_thumb32_insn (to
, inst
.instruction
);
14423 else if (inst
.size
> INSN_SIZE
)
14425 assert (inst
.size
== (2 * INSN_SIZE
));
14426 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
14427 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
14430 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
14432 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
14433 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
14434 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
14437 dwarf2_emit_insn (inst
.size
);
14440 /* Tag values used in struct asm_opcode's tag field. */
14443 OT_unconditional
, /* Instruction cannot be conditionalized.
14444 The ARM condition field is still 0xE. */
14445 OT_unconditionalF
, /* Instruction cannot be conditionalized
14446 and carries 0xF in its ARM condition field. */
14447 OT_csuffix
, /* Instruction takes a conditional suffix. */
14448 OT_csuffixF
, /* Some forms of the instruction take a conditional
14449 suffix, others place 0xF where the condition field
14451 OT_cinfix3
, /* Instruction takes a conditional infix,
14452 beginning at character index 3. (In
14453 unified mode, it becomes a suffix.) */
14454 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
14455 tsts, cmps, cmns, and teqs. */
14456 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
14457 character index 3, even in unified mode. Used for
14458 legacy instructions where suffix and infix forms
14459 may be ambiguous. */
14460 OT_csuf_or_in3
, /* Instruction takes either a conditional
14461 suffix or an infix at character index 3. */
14462 OT_odd_infix_unc
, /* This is the unconditional variant of an
14463 instruction that takes a conditional infix
14464 at an unusual position. In unified mode,
14465 this variant will accept a suffix. */
14466 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
14467 are the conditional variants of instructions that
14468 take conditional infixes in unusual positions.
14469 The infix appears at character index
14470 (tag - OT_odd_infix_0). These are not accepted
14471 in unified mode. */
14474 /* Subroutine of md_assemble, responsible for looking up the primary
14475 opcode from the mnemonic the user wrote. STR points to the
14476 beginning of the mnemonic.
14478 This is not simply a hash table lookup, because of conditional
14479 variants. Most instructions have conditional variants, which are
14480 expressed with a _conditional affix_ to the mnemonic. If we were
14481 to encode each conditional variant as a literal string in the opcode
14482 table, it would have approximately 20,000 entries.
14484 Most mnemonics take this affix as a suffix, and in unified syntax,
14485 'most' is upgraded to 'all'. However, in the divided syntax, some
14486 instructions take the affix as an infix, notably the s-variants of
14487 the arithmetic instructions. Of those instructions, all but six
14488 have the infix appear after the third character of the mnemonic.
14490 Accordingly, the algorithm for looking up primary opcodes given
14493 1. Look up the identifier in the opcode table.
14494 If we find a match, go to step U.
14496 2. Look up the last two characters of the identifier in the
14497 conditions table. If we find a match, look up the first N-2
14498 characters of the identifier in the opcode table. If we
14499 find a match, go to step CE.
14501 3. Look up the fourth and fifth characters of the identifier in
14502 the conditions table. If we find a match, extract those
14503 characters from the identifier, and look up the remaining
14504 characters in the opcode table. If we find a match, go
14509 U. Examine the tag field of the opcode structure, in case this is
14510 one of the six instructions with its conditional infix in an
14511 unusual place. If it is, the tag tells us where to find the
14512 infix; look it up in the conditions table and set inst.cond
14513 accordingly. Otherwise, this is an unconditional instruction.
14514 Again set inst.cond accordingly. Return the opcode structure.
14516 CE. Examine the tag field to make sure this is an instruction that
14517 should receive a conditional suffix. If it is not, fail.
14518 Otherwise, set inst.cond from the suffix we already looked up,
14519 and return the opcode structure.
14521 CM. Examine the tag field to make sure this is an instruction that
14522 should receive a conditional infix after the third character.
14523 If it is not, fail. Otherwise, undo the edits to the current
14524 line of input and proceed as for case CE. */
14526 static const struct asm_opcode
*
14527 opcode_lookup (char **str
)
14531 const struct asm_opcode
*opcode
;
14532 const struct asm_cond
*cond
;
14534 bfd_boolean neon_supported
;
14536 neon_supported
= ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
);
14538 /* Scan up to the end of the mnemonic, which must end in white space,
14539 '.' (in unified mode, or for Neon instructions), or end of string. */
14540 for (base
= end
= *str
; *end
!= '\0'; end
++)
14541 if (*end
== ' ' || ((unified_syntax
|| neon_supported
) && *end
== '.'))
14547 /* Handle a possible width suffix and/or Neon type suffix. */
14552 /* The .w and .n suffixes are only valid if the unified syntax is in
14554 if (unified_syntax
&& end
[1] == 'w')
14556 else if (unified_syntax
&& end
[1] == 'n')
14561 inst
.vectype
.elems
= 0;
14563 *str
= end
+ offset
;
14565 if (end
[offset
] == '.')
14567 /* See if we have a Neon type suffix (possible in either unified or
14568 non-unified ARM syntax mode). */
14569 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
14572 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
14578 /* Look for unaffixed or special-case affixed mnemonic. */
14579 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
14583 if (opcode
->tag
< OT_odd_infix_0
)
14585 inst
.cond
= COND_ALWAYS
;
14589 if (warn_on_deprecated
&& unified_syntax
)
14590 as_warn (_("conditional infixes are deprecated in unified syntax"));
14591 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
14592 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14595 inst
.cond
= cond
->value
;
14599 /* Cannot have a conditional suffix on a mnemonic of less than two
14601 if (end
- base
< 3)
14604 /* Look for suffixed mnemonic. */
14606 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14607 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
14608 if (opcode
&& cond
)
14611 switch (opcode
->tag
)
14613 case OT_cinfix3_legacy
:
14614 /* Ignore conditional suffixes matched on infix only mnemonics. */
14618 case OT_cinfix3_deprecated
:
14619 case OT_odd_infix_unc
:
14620 if (!unified_syntax
)
14622 /* else fall through */
14626 case OT_csuf_or_in3
:
14627 inst
.cond
= cond
->value
;
14630 case OT_unconditional
:
14631 case OT_unconditionalF
:
14634 inst
.cond
= cond
->value
;
14638 /* delayed diagnostic */
14639 inst
.error
= BAD_COND
;
14640 inst
.cond
= COND_ALWAYS
;
14649 /* Cannot have a usual-position infix on a mnemonic of less than
14650 six characters (five would be a suffix). */
14651 if (end
- base
< 6)
14654 /* Look for infixed mnemonic in the usual position. */
14656 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14660 memcpy (save
, affix
, 2);
14661 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
14662 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
14663 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
14664 memcpy (affix
, save
, 2);
14667 && (opcode
->tag
== OT_cinfix3
14668 || opcode
->tag
== OT_cinfix3_deprecated
14669 || opcode
->tag
== OT_csuf_or_in3
14670 || opcode
->tag
== OT_cinfix3_legacy
))
14673 if (warn_on_deprecated
&& unified_syntax
14674 && (opcode
->tag
== OT_cinfix3
14675 || opcode
->tag
== OT_cinfix3_deprecated
))
14676 as_warn (_("conditional infixes are deprecated in unified syntax"));
14678 inst
.cond
= cond
->value
;
14686 md_assemble (char *str
)
14689 const struct asm_opcode
* opcode
;
14691 /* Align the previous label if needed. */
14692 if (last_label_seen
!= NULL
)
14694 symbol_set_frag (last_label_seen
, frag_now
);
14695 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
14696 S_SET_SEGMENT (last_label_seen
, now_seg
);
14699 memset (&inst
, '\0', sizeof (inst
));
14700 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
14702 opcode
= opcode_lookup (&p
);
14705 /* It wasn't an instruction, but it might be a register alias of
14706 the form alias .req reg, or a Neon .dn/.qn directive. */
14707 if (!create_register_alias (str
, p
)
14708 && !create_neon_reg_alias (str
, p
))
14709 as_bad (_("bad instruction `%s'"), str
);
14714 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
14715 as_warn (_("s suffix on comparison instruction is deprecated"));
14717 /* The value which unconditional instructions should have in place of the
14718 condition field. */
14719 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
14723 arm_feature_set variant
;
14725 variant
= cpu_variant
;
14726 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
14727 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
14728 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
14729 /* Check that this instruction is supported for this CPU. */
14730 if (!opcode
->tvariant
14731 || (thumb_mode
== 1
14732 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
14734 as_bad (_("selected processor does not support `%s'"), str
);
14737 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
14738 && opcode
->tencode
!= do_t_branch
)
14740 as_bad (_("Thumb does not support conditional execution"));
14744 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
) && !inst
.size_req
)
14746 /* Implicit require narrow instructions on Thumb-1. This avoids
14747 relaxation accidentally introducing Thumb-2 instructions. */
14748 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
14749 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
14750 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
14754 /* Check conditional suffixes. */
14755 if (current_it_mask
)
14758 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
14759 current_it_mask
<<= 1;
14760 current_it_mask
&= 0x1f;
14761 /* The BKPT instruction is unconditional even in an IT block. */
14763 && cond
!= inst
.cond
&& opcode
->tencode
!= do_t_bkpt
)
14765 as_bad (_("incorrect condition in IT block"));
14769 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
14771 as_bad (_("thumb conditional instruction not in IT block"));
14775 mapping_state (MAP_THUMB
);
14776 inst
.instruction
= opcode
->tvalue
;
14778 if (!parse_operands (p
, opcode
->operands
))
14779 opcode
->tencode ();
14781 /* Clear current_it_mask at the end of an IT block. */
14782 if (current_it_mask
== 0x10)
14783 current_it_mask
= 0;
14785 if (!(inst
.error
|| inst
.relax
))
14787 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
14788 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
14789 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
14791 as_bad (_("cannot honor width suffix -- `%s'"), str
);
14796 /* Something has gone badly wrong if we try to relax a fixed size
14798 assert (inst
.size_req
== 0 || !inst
.relax
);
14800 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14801 *opcode
->tvariant
);
14802 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
14803 set those bits when Thumb-2 32-bit instructions are seen. ie.
14804 anything other than bl/blx and v6-M instructions.
14805 This is overly pessimistic for relaxable instructions. */
14806 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
14808 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
14809 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
14810 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14813 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
14817 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
14818 is_bx
= (opcode
->aencode
== do_bx
);
14820 /* Check that this instruction is supported for this CPU. */
14821 if (!(is_bx
&& fix_v4bx
)
14822 && !(opcode
->avariant
&&
14823 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
14825 as_bad (_("selected processor does not support `%s'"), str
);
14830 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
14834 mapping_state (MAP_ARM
);
14835 inst
.instruction
= opcode
->avalue
;
14836 if (opcode
->tag
== OT_unconditionalF
)
14837 inst
.instruction
|= 0xF << 28;
14839 inst
.instruction
|= inst
.cond
<< 28;
14840 inst
.size
= INSN_SIZE
;
14841 if (!parse_operands (p
, opcode
->operands
))
14842 opcode
->aencode ();
14843 /* Arm mode bx is marked as both v4T and v5 because it's still required
14844 on a hypothetical non-thumb v5 core. */
14846 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
14848 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
14849 *opcode
->avariant
);
14853 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
14860 /* Various frobbings of labels and their addresses. */
14863 arm_start_line_hook (void)
14865 last_label_seen
= NULL
;
14869 arm_frob_label (symbolS
* sym
)
14871 last_label_seen
= sym
;
14873 ARM_SET_THUMB (sym
, thumb_mode
);
14875 #if defined OBJ_COFF || defined OBJ_ELF
14876 ARM_SET_INTERWORK (sym
, support_interwork
);
14879 /* Note - do not allow local symbols (.Lxxx) to be labelled
14880 as Thumb functions. This is because these labels, whilst
14881 they exist inside Thumb code, are not the entry points for
14882 possible ARM->Thumb calls. Also, these labels can be used
14883 as part of a computed goto or switch statement. eg gcc
14884 can generate code that looks like this:
14886 ldr r2, [pc, .Laaa]
14896 The first instruction loads the address of the jump table.
14897 The second instruction converts a table index into a byte offset.
14898 The third instruction gets the jump address out of the table.
14899 The fourth instruction performs the jump.
14901 If the address stored at .Laaa is that of a symbol which has the
14902 Thumb_Func bit set, then the linker will arrange for this address
14903 to have the bottom bit set, which in turn would mean that the
14904 address computation performed by the third instruction would end
14905 up with the bottom bit set. Since the ARM is capable of unaligned
14906 word loads, the instruction would then load the incorrect address
14907 out of the jump table, and chaos would ensue. */
14908 if (label_is_thumb_function_name
14909 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
14910 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14912 /* When the address of a Thumb function is taken the bottom
14913 bit of that address should be set. This will allow
14914 interworking between Arm and Thumb functions to work
14917 THUMB_SET_FUNC (sym
, 1);
14919 label_is_thumb_function_name
= FALSE
;
14922 dwarf2_emit_label (sym
);
14926 arm_data_in_code (void)
14928 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
14930 *input_line_pointer
= '/';
14931 input_line_pointer
+= 5;
14932 *input_line_pointer
= 0;
14940 arm_canonicalize_symbol_name (char * name
)
14944 if (thumb_mode
&& (len
= strlen (name
)) > 5
14945 && streq (name
+ len
- 5, "/data"))
14946 *(name
+ len
- 5) = 0;
14951 /* Table of all register names defined by default. The user can
14952 define additional names with .req. Note that all register names
14953 should appear in both upper and lowercase variants. Some registers
14954 also have mixed-case names. */
14956 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
14957 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
14958 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
14959 #define REGSET(p,t) \
14960 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
14961 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
14962 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
14963 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
14964 #define REGSETH(p,t) \
14965 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
14966 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14967 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14968 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14969 #define REGSET2(p,t) \
14970 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14971 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14972 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14973 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14975 static const struct reg_entry reg_names
[] =
14977 /* ARM integer registers. */
14978 REGSET(r
, RN
), REGSET(R
, RN
),
14980 /* ATPCS synonyms. */
14981 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
14982 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
14983 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
14985 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
14986 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
14987 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
14989 /* Well-known aliases. */
14990 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
14991 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
14993 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
14994 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
14996 /* Coprocessor numbers. */
14997 REGSET(p
, CP
), REGSET(P
, CP
),
14999 /* Coprocessor register numbers. The "cr" variants are for backward
15001 REGSET(c
, CN
), REGSET(C
, CN
),
15002 REGSET(cr
, CN
), REGSET(CR
, CN
),
15004 /* FPA registers. */
15005 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
15006 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
15008 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
15009 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
15011 /* VFP SP registers. */
15012 REGSET(s
,VFS
), REGSET(S
,VFS
),
15013 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
15015 /* VFP DP Registers. */
15016 REGSET(d
,VFD
), REGSET(D
,VFD
),
15017 /* Extra Neon DP registers. */
15018 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
15020 /* Neon QP registers. */
15021 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
15023 /* VFP control registers. */
15024 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
15025 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
15026 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
15027 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
15028 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
15029 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
15031 /* Maverick DSP coprocessor registers. */
15032 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
15033 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
15035 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
15036 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
15037 REGDEF(dspsc
,0,DSPSC
),
15039 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
15040 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
15041 REGDEF(DSPSC
,0,DSPSC
),
15043 /* iWMMXt data registers - p0, c0-15. */
15044 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
15046 /* iWMMXt control registers - p1, c0-3. */
15047 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
15048 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
15049 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
15050 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
15052 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
15053 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
15054 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
15055 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
15056 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
15058 /* XScale accumulator registers. */
15059 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
15065 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
15066 within psr_required_here. */
15067 static const struct asm_psr psrs
[] =
15069 /* Backward compatibility notation. Note that "all" is no longer
15070 truly all possible PSR bits. */
15071 {"all", PSR_c
| PSR_f
},
15075 /* Individual flags. */
15080 /* Combinations of flags. */
15081 {"fs", PSR_f
| PSR_s
},
15082 {"fx", PSR_f
| PSR_x
},
15083 {"fc", PSR_f
| PSR_c
},
15084 {"sf", PSR_s
| PSR_f
},
15085 {"sx", PSR_s
| PSR_x
},
15086 {"sc", PSR_s
| PSR_c
},
15087 {"xf", PSR_x
| PSR_f
},
15088 {"xs", PSR_x
| PSR_s
},
15089 {"xc", PSR_x
| PSR_c
},
15090 {"cf", PSR_c
| PSR_f
},
15091 {"cs", PSR_c
| PSR_s
},
15092 {"cx", PSR_c
| PSR_x
},
15093 {"fsx", PSR_f
| PSR_s
| PSR_x
},
15094 {"fsc", PSR_f
| PSR_s
| PSR_c
},
15095 {"fxs", PSR_f
| PSR_x
| PSR_s
},
15096 {"fxc", PSR_f
| PSR_x
| PSR_c
},
15097 {"fcs", PSR_f
| PSR_c
| PSR_s
},
15098 {"fcx", PSR_f
| PSR_c
| PSR_x
},
15099 {"sfx", PSR_s
| PSR_f
| PSR_x
},
15100 {"sfc", PSR_s
| PSR_f
| PSR_c
},
15101 {"sxf", PSR_s
| PSR_x
| PSR_f
},
15102 {"sxc", PSR_s
| PSR_x
| PSR_c
},
15103 {"scf", PSR_s
| PSR_c
| PSR_f
},
15104 {"scx", PSR_s
| PSR_c
| PSR_x
},
15105 {"xfs", PSR_x
| PSR_f
| PSR_s
},
15106 {"xfc", PSR_x
| PSR_f
| PSR_c
},
15107 {"xsf", PSR_x
| PSR_s
| PSR_f
},
15108 {"xsc", PSR_x
| PSR_s
| PSR_c
},
15109 {"xcf", PSR_x
| PSR_c
| PSR_f
},
15110 {"xcs", PSR_x
| PSR_c
| PSR_s
},
15111 {"cfs", PSR_c
| PSR_f
| PSR_s
},
15112 {"cfx", PSR_c
| PSR_f
| PSR_x
},
15113 {"csf", PSR_c
| PSR_s
| PSR_f
},
15114 {"csx", PSR_c
| PSR_s
| PSR_x
},
15115 {"cxf", PSR_c
| PSR_x
| PSR_f
},
15116 {"cxs", PSR_c
| PSR_x
| PSR_s
},
15117 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
15118 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
15119 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
15120 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
15121 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
15122 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
15123 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
15124 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
15125 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
15126 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
15127 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
15128 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
15129 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
15130 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
15131 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
15132 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
15133 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
15134 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
15135 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
15136 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
15137 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
15138 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
15139 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
15140 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
15143 /* Table of V7M psr names. */
15144 static const struct asm_psr v7m_psrs
[] =
15146 {"apsr", 0 }, {"APSR", 0 },
15147 {"iapsr", 1 }, {"IAPSR", 1 },
15148 {"eapsr", 2 }, {"EAPSR", 2 },
15149 {"psr", 3 }, {"PSR", 3 },
15150 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
15151 {"ipsr", 5 }, {"IPSR", 5 },
15152 {"epsr", 6 }, {"EPSR", 6 },
15153 {"iepsr", 7 }, {"IEPSR", 7 },
15154 {"msp", 8 }, {"MSP", 8 },
15155 {"psp", 9 }, {"PSP", 9 },
15156 {"primask", 16}, {"PRIMASK", 16},
15157 {"basepri", 17}, {"BASEPRI", 17},
15158 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
15159 {"faultmask", 19}, {"FAULTMASK", 19},
15160 {"control", 20}, {"CONTROL", 20}
15163 /* Table of all shift-in-operand names. */
15164 static const struct asm_shift_name shift_names
[] =
15166 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
15167 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
15168 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
15169 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
15170 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
15171 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
15174 /* Table of all explicit relocation names. */
15176 static struct reloc_entry reloc_names
[] =
15178 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
15179 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
15180 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
15181 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
15182 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
15183 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
15184 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
15185 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
15186 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
15187 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
15188 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
15192 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
15193 static const struct asm_cond conds
[] =
15197 {"cs", 0x2}, {"hs", 0x2},
15198 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
15212 static struct asm_barrier_opt barrier_opt_names
[] =
15220 /* Table of ARM-format instructions. */
15222 /* Macros for gluing together operand strings. N.B. In all cases
15223 other than OPS0, the trailing OP_stop comes from default
15224 zero-initialization of the unspecified elements of the array. */
15225 #define OPS0() { OP_stop, }
15226 #define OPS1(a) { OP_##a, }
15227 #define OPS2(a,b) { OP_##a,OP_##b, }
15228 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
15229 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
15230 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
15231 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
15233 /* These macros abstract out the exact format of the mnemonic table and
15234 save some repeated characters. */
15236 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
15237 #define TxCE(mnem, op, top, nops, ops, ae, te) \
15238 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
15239 THUMB_VARIANT, do_##ae, do_##te }
15241 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
15242 a T_MNEM_xyz enumerator. */
15243 #define TCE(mnem, aop, top, nops, ops, ae, te) \
15244 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
15245 #define tCE(mnem, aop, top, nops, ops, ae, te) \
15246 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
15248 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
15249 infix after the third character. */
15250 #define TxC3(mnem, op, top, nops, ops, ae, te) \
15251 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
15252 THUMB_VARIANT, do_##ae, do_##te }
15253 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
15254 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
15255 THUMB_VARIANT, do_##ae, do_##te }
15256 #define TC3(mnem, aop, top, nops, ops, ae, te) \
15257 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
15258 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
15259 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
15260 #define tC3(mnem, aop, top, nops, ops, ae, te) \
15261 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
15262 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
15263 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
15265 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
15266 appear in the condition table. */
15267 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
15268 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
15269 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
15271 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
15272 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
15273 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
15274 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
15275 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
15276 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
15277 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
15278 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
15279 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
15280 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
15281 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
15282 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
15283 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
15284 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
15285 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
15286 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
15287 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
15288 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
15289 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
15290 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
15292 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
15293 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
15294 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
15295 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
15297 /* Mnemonic that cannot be conditionalized. The ARM condition-code
15298 field is still 0xE. Many of the Thumb variants can be executed
15299 conditionally, so this is checked separately. */
15300 #define TUE(mnem, op, top, nops, ops, ae, te) \
15301 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
15302 THUMB_VARIANT, do_##ae, do_##te }
15304 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
15305 condition code field. */
15306 #define TUF(mnem, op, top, nops, ops, ae, te) \
15307 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
15308 THUMB_VARIANT, do_##ae, do_##te }
15310 /* ARM-only variants of all the above. */
15311 #define CE(mnem, op, nops, ops, ae) \
15312 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
15314 #define C3(mnem, op, nops, ops, ae) \
15315 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
15317 /* Legacy mnemonics that always have conditional infix after the third
15319 #define CL(mnem, op, nops, ops, ae) \
15320 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
15321 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
15323 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
15324 #define cCE(mnem, op, nops, ops, ae) \
15325 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
15327 /* Legacy coprocessor instructions where conditional infix and conditional
15328 suffix are ambiguous. For consistency this includes all FPA instructions,
15329 not just the potentially ambiguous ones. */
15330 #define cCL(mnem, op, nops, ops, ae) \
15331 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
15332 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
15334 /* Coprocessor, takes either a suffix or a position-3 infix
15335 (for an FPA corner case). */
15336 #define C3E(mnem, op, nops, ops, ae) \
15337 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
15338 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
15340 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
15341 { #m1 #m2 #m3, OPS##nops ops, \
15342 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
15343 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
15345 #define CM(m1, m2, op, nops, ops, ae) \
15346 xCM_(m1, , m2, op, nops, ops, ae), \
15347 xCM_(m1, eq, m2, op, nops, ops, ae), \
15348 xCM_(m1, ne, m2, op, nops, ops, ae), \
15349 xCM_(m1, cs, m2, op, nops, ops, ae), \
15350 xCM_(m1, hs, m2, op, nops, ops, ae), \
15351 xCM_(m1, cc, m2, op, nops, ops, ae), \
15352 xCM_(m1, ul, m2, op, nops, ops, ae), \
15353 xCM_(m1, lo, m2, op, nops, ops, ae), \
15354 xCM_(m1, mi, m2, op, nops, ops, ae), \
15355 xCM_(m1, pl, m2, op, nops, ops, ae), \
15356 xCM_(m1, vs, m2, op, nops, ops, ae), \
15357 xCM_(m1, vc, m2, op, nops, ops, ae), \
15358 xCM_(m1, hi, m2, op, nops, ops, ae), \
15359 xCM_(m1, ls, m2, op, nops, ops, ae), \
15360 xCM_(m1, ge, m2, op, nops, ops, ae), \
15361 xCM_(m1, lt, m2, op, nops, ops, ae), \
15362 xCM_(m1, gt, m2, op, nops, ops, ae), \
15363 xCM_(m1, le, m2, op, nops, ops, ae), \
15364 xCM_(m1, al, m2, op, nops, ops, ae)
15366 #define UE(mnem, op, nops, ops, ae) \
15367 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
15369 #define UF(mnem, op, nops, ops, ae) \
15370 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
15372 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
15373 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
15374 use the same encoding function for each. */
15375 #define NUF(mnem, op, nops, ops, enc) \
15376 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
15377 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
15379 /* Neon data processing, version which indirects through neon_enc_tab for
15380 the various overloaded versions of opcodes. */
15381 #define nUF(mnem, op, nops, ops, enc) \
15382 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
15383 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
15385 /* Neon insn with conditional suffix for the ARM version, non-overloaded
15387 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
15388 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
15389 THUMB_VARIANT, do_##enc, do_##enc }
15391 #define NCE(mnem, op, nops, ops, enc) \
15392 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
15394 #define NCEF(mnem, op, nops, ops, enc) \
15395 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
15397 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
15398 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
15399 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
15400 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
15402 #define nCE(mnem, op, nops, ops, enc) \
15403 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
15405 #define nCEF(mnem, op, nops, ops, enc) \
15406 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
15410 /* Thumb-only, unconditional. */
15411 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
15413 static const struct asm_opcode insns
[] =
15415 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
15416 #define THUMB_VARIANT &arm_ext_v4t
15417 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15418 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15419 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15420 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15421 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
15422 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
15423 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
15424 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
15425 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15426 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15427 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15428 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15429 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15430 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15431 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15432 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15434 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
15435 for setting PSR flag bits. They are obsolete in V6 and do not
15436 have Thumb equivalents. */
15437 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15438 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15439 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
15440 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
15441 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
15442 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
15443 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15444 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15445 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
15447 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
15448 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
15449 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
15450 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
15452 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15453 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15454 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15455 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15457 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15458 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15459 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15460 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15461 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15462 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15464 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
15465 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
15466 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
15467 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
15470 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
15471 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
15472 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
15474 /* Thumb-compatibility pseudo ops. */
15475 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15476 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15477 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15478 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15479 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15480 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15481 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15482 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15483 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
15484 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
15485 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
15486 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
15488 /* These may simplify to neg. */
15489 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
15490 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
15492 #undef THUMB_VARIANT
15493 #define THUMB_VARIANT &arm_ext_v6
15494 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
15496 /* V1 instructions with no Thumb analogue prior to V6T2. */
15497 #undef THUMB_VARIANT
15498 #define THUMB_VARIANT &arm_ext_v6t2
15499 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15500 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15501 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
15503 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15504 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15505 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15506 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15508 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15509 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15511 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15512 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15514 /* V1 instructions with no Thumb analogue at all. */
15515 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
15516 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
15518 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
15519 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
15520 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
15521 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
15522 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
15523 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
15524 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
15525 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
15528 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
15529 #undef THUMB_VARIANT
15530 #define THUMB_VARIANT &arm_ext_v4t
15531 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
15532 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
15534 #undef THUMB_VARIANT
15535 #define THUMB_VARIANT &arm_ext_v6t2
15536 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15537 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
15539 /* Generic coprocessor instructions. */
15540 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
15541 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15542 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15543 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15544 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15545 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15546 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15549 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
15550 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15551 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15554 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
15555 #undef THUMB_VARIANT
15556 #define THUMB_VARIANT &arm_ext_msr
15557 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
15558 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
15561 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
15562 #undef THUMB_VARIANT
15563 #define THUMB_VARIANT &arm_ext_v6t2
15564 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15565 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15566 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15567 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15568 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15569 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15570 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15571 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15574 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
15575 #undef THUMB_VARIANT
15576 #define THUMB_VARIANT &arm_ext_v4t
15577 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15578 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15579 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15580 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15581 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15582 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15585 #define ARM_VARIANT &arm_ext_v4t_5
15586 /* ARM Architecture 4T. */
15587 /* Note: bx (and blx) are required on V5, even if the processor does
15588 not support Thumb. */
15589 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
15592 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
15593 #undef THUMB_VARIANT
15594 #define THUMB_VARIANT &arm_ext_v5t
15595 /* Note: blx has 2 variants; the .value coded here is for
15596 BLX(2). Only this variant has conditional execution. */
15597 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
15598 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
15600 #undef THUMB_VARIANT
15601 #define THUMB_VARIANT &arm_ext_v6t2
15602 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
15603 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15604 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15605 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15606 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15607 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
15608 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15609 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15612 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
15613 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15614 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15615 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15616 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15618 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15619 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15621 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15622 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15623 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15624 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15626 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15627 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15628 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15629 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15631 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15632 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15634 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
15635 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
15636 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
15637 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
15640 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
15641 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
15642 TC3(ldrd
, 00000d0
, e8500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15643 TC3(strd
, 00000f0
, e8400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15645 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15646 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15649 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
15650 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
15653 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
15654 #undef THUMB_VARIANT
15655 #define THUMB_VARIANT &arm_ext_v6
15656 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15657 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15658 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15659 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15660 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15661 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15662 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15663 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15664 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15665 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
15667 #undef THUMB_VARIANT
15668 #define THUMB_VARIANT &arm_ext_v6t2
15669 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
15670 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
15671 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15672 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15674 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
15675 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
15677 /* ARM V6 not included in V7M (eg. integer SIMD). */
15678 #undef THUMB_VARIANT
15679 #define THUMB_VARIANT &arm_ext_v6_notm
15680 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
15681 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
15682 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
15683 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15684 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15685 TCE(qasx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15686 /* Old name for QASX. */
15687 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15688 TCE(qsax
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15689 /* Old name for QSAX. */
15690 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15691 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15692 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15693 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15694 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15695 TCE(sasx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15696 /* Old name for SASX. */
15697 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15698 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15699 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15700 TCE(shasx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15701 /* Old name for SHASX. */
15702 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15703 TCE(shsax
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15704 /* Old name for SHSAX. */
15705 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15706 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15707 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15708 TCE(ssax
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15709 /* Old name for SSAX. */
15710 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15711 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15712 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15713 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15714 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15715 TCE(uasx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15716 /* Old name for UASX. */
15717 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15718 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15719 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15720 TCE(uhasx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15721 /* Old name for UHASX. */
15722 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15723 TCE(uhsax
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15724 /* Old name for UHSAX. */
15725 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15726 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15727 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15728 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15729 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15730 TCE(uqasx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15731 /* Old name for UQASX. */
15732 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15733 TCE(uqsax
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15734 /* Old name for UQSAX. */
15735 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15736 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15737 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15738 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15739 TCE(usax
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15740 /* Old name for USAX. */
15741 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15742 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15743 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15744 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
15745 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
15746 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15747 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15748 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
15749 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
15750 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15751 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15752 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15753 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15754 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15755 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15756 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15757 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15758 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15759 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15760 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15761 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15762 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15763 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15764 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15765 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15766 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15767 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15768 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15769 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15770 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15771 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15772 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15773 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15774 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15775 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15776 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15777 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15778 TUF(srsia
, 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
15779 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
15780 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
15781 TUF(srsdb
, 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
15782 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
15783 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
15784 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15785 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15786 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
15789 #define ARM_VARIANT &arm_ext_v6k
15790 #undef THUMB_VARIANT
15791 #define THUMB_VARIANT &arm_ext_v6k
15792 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
15793 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
15794 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
15795 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
15797 #undef THUMB_VARIANT
15798 #define THUMB_VARIANT &arm_ext_v6_notm
15799 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
15800 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
15802 #undef THUMB_VARIANT
15803 #define THUMB_VARIANT &arm_ext_v6t2
15804 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15805 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15806 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15807 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15808 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
15811 #define ARM_VARIANT &arm_ext_v6z
15812 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
15815 #define ARM_VARIANT &arm_ext_v6t2
15816 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
15817 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
15818 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15819 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15821 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15822 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15823 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15824 TCE(rbit
, 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
15826 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15827 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15828 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15829 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15831 UT(cbnz
, b900
, 2, (RR
, EXP
), t_cbz
),
15832 UT(cbz
, b100
, 2, (RR
, EXP
), t_cbz
),
15833 /* ARM does not really have an IT instruction, so always allow it. */
15835 #define ARM_VARIANT &arm_ext_v1
15836 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
15837 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
15838 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
15839 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
15840 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
15841 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
15842 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
15843 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
15844 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
15845 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
15846 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
15847 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
15848 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
15849 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
15850 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
15851 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
15852 TC3(rrx
, 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
15853 TC3(rrxs
, 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
15855 /* Thumb2 only instructions. */
15857 #define ARM_VARIANT NULL
15859 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15860 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15861 TCE(orn
, 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
15862 TCE(orns
, 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
15863 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
15864 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
15866 /* Thumb-2 hardware division instructions (R and M profiles only). */
15867 #undef THUMB_VARIANT
15868 #define THUMB_VARIANT &arm_ext_div
15869 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15870 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15872 /* ARM V6M/V7 instructions. */
15874 #define ARM_VARIANT &arm_ext_barrier
15875 #undef THUMB_VARIANT
15876 #define THUMB_VARIANT &arm_ext_barrier
15877 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
15878 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
15879 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
15881 /* ARM V7 instructions. */
15883 #define ARM_VARIANT &arm_ext_v7
15884 #undef THUMB_VARIANT
15885 #define THUMB_VARIANT &arm_ext_v7
15886 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
15887 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
15890 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
15891 cCE(wfs
, e200110
, 1, (RR
), rd
),
15892 cCE(rfs
, e300110
, 1, (RR
), rd
),
15893 cCE(wfc
, e400110
, 1, (RR
), rd
),
15894 cCE(rfc
, e500110
, 1, (RR
), rd
),
15896 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15897 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15898 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15899 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15901 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15902 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15903 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15904 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15906 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
15907 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
15908 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
15909 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
15910 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
15911 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
15912 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
15913 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
15914 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
15915 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
15916 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
15917 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
15919 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
15920 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
15921 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
15922 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
15923 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
15924 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
15925 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
15926 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
15927 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
15928 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
15929 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
15930 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
15932 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
15933 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
15934 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
15935 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
15936 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
15937 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
15938 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
15939 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
15940 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
15941 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
15942 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
15943 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
15945 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
15946 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
15947 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
15948 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
15949 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
15950 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
15951 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
15952 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
15953 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
15954 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
15955 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
15956 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
15958 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
15959 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
15960 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
15961 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
15962 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
15963 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
15964 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
15965 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
15966 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
15967 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
15968 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
15969 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
15971 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
15972 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
15973 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
15974 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
15975 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
15976 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
15977 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
15978 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
15979 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
15980 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
15981 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
15982 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
15984 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
15985 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
15986 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
15987 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
15988 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
15989 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
15990 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
15991 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
15992 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
15993 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
15994 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
15995 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
15997 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
15998 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
15999 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
16000 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
16001 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
16002 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
16003 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
16004 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
16005 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
16006 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
16007 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
16008 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
16010 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
16011 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
16012 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
16013 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
16014 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
16015 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
16016 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
16017 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
16018 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
16019 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
16020 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
16021 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
16023 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
16024 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
16025 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
16026 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
16027 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
16028 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
16029 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
16030 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
16031 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
16032 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
16033 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
16034 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
16036 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
16037 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
16038 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
16039 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
16040 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
16041 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
16042 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
16043 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
16044 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
16045 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
16046 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
16047 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
16049 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
16050 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
16051 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
16052 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
16053 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
16054 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
16055 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
16056 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
16057 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
16058 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
16059 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
16060 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
16062 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
16063 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
16064 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
16065 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
16066 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
16067 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
16068 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
16069 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
16070 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
16071 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
16072 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
16073 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
16075 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
16076 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
16077 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
16078 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
16079 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
16080 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
16081 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
16082 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
16083 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
16084 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
16085 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
16086 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
16088 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
16089 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
16090 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
16091 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
16092 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
16093 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
16094 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
16095 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
16096 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
16097 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
16098 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
16099 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
16101 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
16102 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
16103 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
16104 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
16105 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
16106 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
16107 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
16108 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
16109 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
16110 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
16111 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
16112 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
16114 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16115 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16116 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16117 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16118 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16119 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16120 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16121 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16122 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16123 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16124 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16125 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16127 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16128 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16129 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16130 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16131 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16132 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16133 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16134 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16135 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16136 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16137 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16138 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16140 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16141 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16142 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16143 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16144 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16145 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16146 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16147 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16148 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16149 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16150 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16151 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16153 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16154 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16155 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16156 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16157 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16158 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16159 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16160 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16161 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16162 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16163 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16164 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16166 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16167 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16168 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16169 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16170 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16171 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16172 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16173 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16174 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16175 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16176 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16177 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16179 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16180 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16181 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16182 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16183 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16184 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16185 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16186 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16187 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16188 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16189 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16190 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16192 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16193 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16194 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16195 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16196 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16197 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16198 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16199 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16200 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16201 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16202 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16203 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16205 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16206 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16207 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16208 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16209 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16210 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16211 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16212 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16213 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16214 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16215 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16216 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16218 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16219 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16220 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16221 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16222 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16223 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16224 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16225 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16226 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16227 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16228 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16229 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16231 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16232 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16233 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16234 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16235 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16236 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16237 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16238 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16239 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16240 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16241 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16242 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16244 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16245 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16246 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16247 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16248 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16249 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16250 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16251 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16252 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16253 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16254 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16255 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16257 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16258 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16259 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16260 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16261 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16262 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16263 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16264 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16265 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16266 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16267 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16268 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16270 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16271 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16272 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16273 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16274 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16275 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16276 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16277 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16278 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16279 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16280 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16281 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16283 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
16284 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
16285 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
16286 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
16288 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
16289 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
16290 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
16291 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
16292 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
16293 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
16294 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
16295 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
16296 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
16297 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
16298 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
16299 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
16301 /* The implementation of the FIX instruction is broken on some
16302 assemblers, in that it accepts a precision specifier as well as a
16303 rounding specifier, despite the fact that this is meaningless.
16304 To be more compatible, we accept it as well, though of course it
16305 does not set any bits. */
16306 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
16307 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
16308 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
16309 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
16310 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
16311 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
16312 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
16313 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
16314 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
16315 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
16316 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
16317 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
16318 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
16320 /* Instructions that were new with the real FPA, call them V2. */
16322 #define ARM_VARIANT &fpu_fpa_ext_v2
16323 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
16324 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
16325 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
16326 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
16327 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
16328 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
16331 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
16332 /* Moves and type conversions. */
16333 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16334 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
16335 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
16336 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
16337 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16338 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16339 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16340 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16341 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16342 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16343 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
16344 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
16346 /* Memory operations. */
16347 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
16348 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
16349 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
16350 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
16351 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
16352 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
16353 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
16354 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
16355 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
16356 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
16357 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
16358 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
16359 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
16360 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
16361 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
16362 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
16363 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
16364 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
16366 /* Monadic operations. */
16367 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16368 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16369 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16371 /* Dyadic operations. */
16372 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16373 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16374 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16375 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16376 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16377 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16378 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16379 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16380 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16383 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16384 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
16385 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16386 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
16389 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
16390 /* Moves and type conversions. */
16391 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16392 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
16393 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
16394 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
16395 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
16396 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
16397 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
16398 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
16399 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
16400 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
16401 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
16402 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
16403 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
16405 /* Memory operations. */
16406 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
16407 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
16408 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
16409 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
16410 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
16411 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
16412 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
16413 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
16414 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
16415 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
16417 /* Monadic operations. */
16418 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16419 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16420 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16422 /* Dyadic operations. */
16423 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16424 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16425 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16426 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16427 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16428 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16429 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16430 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16431 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16434 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16435 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
16436 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16437 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
16440 #define ARM_VARIANT &fpu_vfp_ext_v2
16441 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
16442 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
16443 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
16444 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
16446 /* Instructions which may belong to either the Neon or VFP instruction sets.
16447 Individual encoder functions perform additional architecture checks. */
16449 #define ARM_VARIANT &fpu_vfp_ext_v1xd
16450 #undef THUMB_VARIANT
16451 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
16452 /* These mnemonics are unique to VFP. */
16453 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
16454 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
16455 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
16456 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
16457 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
16458 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
16459 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
16460 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
16461 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
16462 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
16464 /* Mnemonics shared by Neon and VFP. */
16465 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
16466 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
16467 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
16469 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
16470 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
16472 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
16473 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
16475 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16476 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16477 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16478 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16479 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16480 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16481 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
16482 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
16484 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
16485 nCEF(vcvtb
, vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
16486 nCEF(vcvtt
, vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
16489 /* NOTE: All VMOV encoding is special-cased! */
16490 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
16491 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
16493 #undef THUMB_VARIANT
16494 #define THUMB_VARIANT &fpu_neon_ext_v1
16496 #define ARM_VARIANT &fpu_neon_ext_v1
16497 /* Data processing with three registers of the same length. */
16498 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
16499 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
16500 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
16501 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
16502 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
16503 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
16504 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
16505 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
16506 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
16507 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
16508 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
16509 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
16510 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
16511 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
16512 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
16513 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
16514 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
16515 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
16516 /* If not immediate, fall back to neon_dyadic_i64_su.
16517 shl_imm should accept I8 I16 I32 I64,
16518 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
16519 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
16520 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
16521 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
16522 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
16523 /* Logic ops, types optional & ignored. */
16524 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
16525 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
16526 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
16527 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
16528 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
16529 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
16530 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
16531 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
16532 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
16533 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
16534 /* Bitfield ops, untyped. */
16535 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
16536 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
16537 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
16538 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
16539 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
16540 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
16541 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
16542 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
16543 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
16544 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
16545 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
16546 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
16547 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
16548 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
16549 back to neon_dyadic_if_su. */
16550 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
16551 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
16552 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
16553 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
16554 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
16555 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
16556 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
16557 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
16558 /* Comparison. Type I8 I16 I32 F32. */
16559 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
16560 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
16561 /* As above, D registers only. */
16562 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
16563 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
16564 /* Int and float variants, signedness unimportant. */
16565 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
16566 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
16567 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
16568 /* Add/sub take types I8 I16 I32 I64 F32. */
16569 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
16570 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
16571 /* vtst takes sizes 8, 16, 32. */
16572 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
16573 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
16574 /* VMUL takes I8 I16 I32 F32 P8. */
16575 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
16576 /* VQD{R}MULH takes S16 S32. */
16577 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
16578 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
16579 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
16580 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
16581 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
16582 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
16583 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
16584 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
16585 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
16586 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
16587 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
16588 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
16589 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16590 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16591 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16592 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16594 /* Two address, int/float. Types S8 S16 S32 F32. */
16595 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16596 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16598 /* Data processing with two registers and a shift amount. */
16599 /* Right shifts, and variants with rounding.
16600 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
16601 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16602 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16603 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16604 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16605 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16606 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16607 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16608 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16609 /* Shift and insert. Sizes accepted 8 16 32 64. */
16610 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
16611 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
16612 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
16613 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
16614 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
16615 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
16616 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
16617 /* Right shift immediate, saturating & narrowing, with rounding variants.
16618 Types accepted S16 S32 S64 U16 U32 U64. */
16619 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16620 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16621 /* As above, unsigned. Types accepted S16 S32 S64. */
16622 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16623 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16624 /* Right shift narrowing. Types accepted I16 I32 I64. */
16625 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16626 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16627 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
16628 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
16629 /* CVT with optional immediate for fixed-point variant. */
16630 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
16632 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
16633 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
16635 /* Data processing, three registers of different lengths. */
16636 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
16637 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
16638 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16639 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16640 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16641 /* If not scalar, fall back to neon_dyadic_long.
16642 Vector types as above, scalar types S16 S32 U16 U32. */
16643 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16644 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16645 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
16646 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16647 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16648 /* Dyadic, narrowing insns. Types I16 I32 I64. */
16649 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16650 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16651 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16652 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16653 /* Saturating doubling multiplies. Types S16 S32. */
16654 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16655 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16656 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16657 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
16658 S16 S32 U16 U32. */
16659 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
16661 /* Extract. Size 8. */
16662 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
16663 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
16665 /* Two registers, miscellaneous. */
16666 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
16667 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
16668 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
16669 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
16670 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
16671 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
16672 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
16673 /* Vector replicate. Sizes 8 16 32. */
16674 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
16675 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
16676 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
16677 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
16678 /* VMOVN. Types I16 I32 I64. */
16679 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
16680 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
16681 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
16682 /* VQMOVUN. Types S16 S32 S64. */
16683 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
16684 /* VZIP / VUZP. Sizes 8 16 32. */
16685 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16686 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16687 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16688 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16689 /* VQABS / VQNEG. Types S8 S16 S32. */
16690 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16691 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16692 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16693 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16694 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
16695 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16696 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
16697 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16698 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
16699 /* Reciprocal estimates. Types U32 F32. */
16700 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16701 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
16702 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16703 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
16704 /* VCLS. Types S8 S16 S32. */
16705 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
16706 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
16707 /* VCLZ. Types I8 I16 I32. */
16708 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
16709 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
16710 /* VCNT. Size 8. */
16711 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
16712 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
16713 /* Two address, untyped. */
16714 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
16715 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
16716 /* VTRN. Sizes 8 16 32. */
16717 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
16718 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
16720 /* Table lookup. Size 8. */
16721 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16722 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16724 #undef THUMB_VARIANT
16725 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
16727 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
16728 /* Neon element/structure load/store. */
16729 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16730 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16731 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16732 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16733 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16734 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16735 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16736 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16738 #undef THUMB_VARIANT
16739 #define THUMB_VARIANT &fpu_vfp_ext_v3
16741 #define ARM_VARIANT &fpu_vfp_ext_v3
16742 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
16743 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
16744 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16745 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16746 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16747 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16748 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16749 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16750 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16751 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16752 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16753 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16754 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16755 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16756 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16757 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16758 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16759 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16761 #undef THUMB_VARIANT
16763 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
16764 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16765 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16766 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16767 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16768 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16769 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16770 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
16771 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
16774 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
16775 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
16776 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
16777 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
16778 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
16779 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
16780 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
16781 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
16782 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
16783 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
16784 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16785 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16786 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16787 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16788 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16789 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16790 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16791 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16792 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16793 cCE(tmcr
, e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
16794 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
16795 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16796 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16797 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16798 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16799 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16800 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16801 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
16802 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
16803 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
16804 cCE(tmrc
, e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
16805 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
16806 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
16807 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
16808 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
16809 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16810 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16811 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16812 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16813 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16814 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16815 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16816 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16817 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16818 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16819 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16820 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16821 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
16822 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16823 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16824 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16825 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16826 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16827 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16828 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16829 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16830 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16831 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16832 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16833 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16834 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16835 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16836 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16837 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16838 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16839 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16840 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16841 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16842 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16843 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16844 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16845 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16846 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16847 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16848 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16849 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16850 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16851 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16852 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16853 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16854 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16855 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16856 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16857 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16858 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16859 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16860 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16861 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16862 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16863 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
16864 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16865 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16866 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16867 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16868 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16869 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16870 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16871 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16872 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16873 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16874 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16875 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16876 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16877 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16878 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16879 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16880 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16881 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16882 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16883 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16884 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16885 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
16886 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16887 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16888 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16889 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16890 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16891 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16892 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16893 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16894 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16895 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16896 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16897 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16898 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16899 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16900 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16901 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16902 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16903 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16904 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16905 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16906 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16907 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16908 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16909 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16910 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16911 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16912 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16913 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16914 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16915 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16916 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16917 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16918 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16919 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16920 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16921 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16922 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16923 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16924 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16925 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16926 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16927 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16928 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16929 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16930 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16931 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16932 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16933 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16934 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16935 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16936 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
16939 #define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
16940 cCE(torvscb
, e13f190
, 1, (RR
), iwmmxt_tandorc
),
16941 cCE(torvsch
, e53f190
, 1, (RR
), iwmmxt_tandorc
),
16942 cCE(torvscw
, e93f190
, 1, (RR
), iwmmxt_tandorc
),
16943 cCE(wabsb
, e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16944 cCE(wabsh
, e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16945 cCE(wabsw
, ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16946 cCE(wabsdiffb
, e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16947 cCE(wabsdiffh
, e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16948 cCE(wabsdiffw
, e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16949 cCE(waddbhusl
, e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16950 cCE(waddbhusm
, e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16951 cCE(waddhc
, e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16952 cCE(waddwc
, ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16953 cCE(waddsubhx
, ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16954 cCE(wavg4
, e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16955 cCE(wavg4r
, e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16956 cCE(wmaddsn
, ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16957 cCE(wmaddsx
, eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16958 cCE(wmaddun
, ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16959 cCE(wmaddux
, e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16960 cCE(wmerge
, e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
16961 cCE(wmiabb
, e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16962 cCE(wmiabt
, e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16963 cCE(wmiatb
, e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16964 cCE(wmiatt
, e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16965 cCE(wmiabbn
, e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16966 cCE(wmiabtn
, e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16967 cCE(wmiatbn
, e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16968 cCE(wmiattn
, e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16969 cCE(wmiawbb
, e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16970 cCE(wmiawbt
, e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16971 cCE(wmiawtb
, ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16972 cCE(wmiawtt
, eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16973 cCE(wmiawbbn
, ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16974 cCE(wmiawbtn
, ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16975 cCE(wmiawtbn
, ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16976 cCE(wmiawttn
, ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16977 cCE(wmulsmr
, ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16978 cCE(wmulumr
, ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16979 cCE(wmulwumr
, ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16980 cCE(wmulwsmr
, ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16981 cCE(wmulwum
, ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16982 cCE(wmulwsm
, ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16983 cCE(wmulwl
, eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16984 cCE(wqmiabb
, e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16985 cCE(wqmiabt
, e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16986 cCE(wqmiatb
, ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16987 cCE(wqmiatt
, eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16988 cCE(wqmiabbn
, ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16989 cCE(wqmiabtn
, ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16990 cCE(wqmiatbn
, ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16991 cCE(wqmiattn
, ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16992 cCE(wqmulm
, e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16993 cCE(wqmulmr
, e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16994 cCE(wqmulwm
, ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16995 cCE(wqmulwmr
, ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16996 cCE(wsubaddhx
, ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16999 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
17000 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
17001 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
17002 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
17003 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
17004 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
17005 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
17006 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
17007 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
17008 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
17009 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
17010 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
17011 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
17012 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
17013 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
17014 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
17015 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
17016 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
17017 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
17018 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
17019 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
17020 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
17021 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
17022 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
17023 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
17024 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
17025 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
17026 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
17027 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
17028 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
17029 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
17030 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
17031 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
17032 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
17033 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
17034 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
17035 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
17036 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
17037 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
17038 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
17039 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
17040 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
17041 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
17042 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
17043 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
17044 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
17045 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
17046 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
17047 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
17048 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
17049 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
17050 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
17051 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
17052 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
17053 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
17054 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17055 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17056 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17057 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17058 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17059 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17060 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
17061 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
17062 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
17063 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
17064 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17065 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17066 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17067 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17068 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17069 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17070 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17071 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17072 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
17073 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
17074 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
17075 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
17078 #undef THUMB_VARIANT
17105 /* MD interface: bits in the object file. */
17107 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
17108 for use in the a.out file, and stores them in the array pointed to by buf.
17109 This knows about the endian-ness of the target machine and does
17110 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
17111 2 (short) and 4 (long) Floating numbers are put out as a series of
17112 LITTLENUMS (shorts, here at least). */
17115 md_number_to_chars (char * buf
, valueT val
, int n
)
17117 if (target_big_endian
)
17118 number_to_chars_bigendian (buf
, val
, n
);
17120 number_to_chars_littleendian (buf
, val
, n
);
17124 md_chars_to_number (char * buf
, int n
)
17127 unsigned char * where
= (unsigned char *) buf
;
17129 if (target_big_endian
)
17134 result
|= (*where
++ & 255);
17142 result
|= (where
[n
] & 255);
17149 /* MD interface: Sections. */
17151 /* Estimate the size of a frag before relaxing. Assume everything fits in
17155 md_estimate_size_before_relax (fragS
* fragp
,
17156 segT segtype ATTRIBUTE_UNUSED
)
17162 /* Convert a machine dependent frag. */
17165 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
17167 unsigned long insn
;
17168 unsigned long old_op
;
17176 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17178 old_op
= bfd_get_16(abfd
, buf
);
17179 if (fragp
->fr_symbol
)
17181 exp
.X_op
= O_symbol
;
17182 exp
.X_add_symbol
= fragp
->fr_symbol
;
17186 exp
.X_op
= O_constant
;
17188 exp
.X_add_number
= fragp
->fr_offset
;
17189 opcode
= fragp
->fr_subtype
;
17192 case T_MNEM_ldr_pc
:
17193 case T_MNEM_ldr_pc2
:
17194 case T_MNEM_ldr_sp
:
17195 case T_MNEM_str_sp
:
17202 if (fragp
->fr_var
== 4)
17204 insn
= THUMB_OP32 (opcode
);
17205 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
17207 insn
|= (old_op
& 0x700) << 4;
17211 insn
|= (old_op
& 7) << 12;
17212 insn
|= (old_op
& 0x38) << 13;
17214 insn
|= 0x00000c00;
17215 put_thumb32_insn (buf
, insn
);
17216 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
17220 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
17222 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
17225 if (fragp
->fr_var
== 4)
17227 insn
= THUMB_OP32 (opcode
);
17228 insn
|= (old_op
& 0xf0) << 4;
17229 put_thumb32_insn (buf
, insn
);
17230 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
17234 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
17235 exp
.X_add_number
-= 4;
17243 if (fragp
->fr_var
== 4)
17245 int r0off
= (opcode
== T_MNEM_mov
17246 || opcode
== T_MNEM_movs
) ? 0 : 8;
17247 insn
= THUMB_OP32 (opcode
);
17248 insn
= (insn
& 0xe1ffffff) | 0x10000000;
17249 insn
|= (old_op
& 0x700) << r0off
;
17250 put_thumb32_insn (buf
, insn
);
17251 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
17255 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
17260 if (fragp
->fr_var
== 4)
17262 insn
= THUMB_OP32(opcode
);
17263 put_thumb32_insn (buf
, insn
);
17264 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
17267 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
17271 if (fragp
->fr_var
== 4)
17273 insn
= THUMB_OP32(opcode
);
17274 insn
|= (old_op
& 0xf00) << 14;
17275 put_thumb32_insn (buf
, insn
);
17276 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
17279 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
17282 case T_MNEM_add_sp
:
17283 case T_MNEM_add_pc
:
17284 case T_MNEM_inc_sp
:
17285 case T_MNEM_dec_sp
:
17286 if (fragp
->fr_var
== 4)
17288 /* ??? Choose between add and addw. */
17289 insn
= THUMB_OP32 (opcode
);
17290 insn
|= (old_op
& 0xf0) << 4;
17291 put_thumb32_insn (buf
, insn
);
17292 if (opcode
== T_MNEM_add_pc
)
17293 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
17295 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
17298 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
17306 if (fragp
->fr_var
== 4)
17308 insn
= THUMB_OP32 (opcode
);
17309 insn
|= (old_op
& 0xf0) << 4;
17310 insn
|= (old_op
& 0xf) << 16;
17311 put_thumb32_insn (buf
, insn
);
17312 if (insn
& (1 << 20))
17313 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
17315 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
17318 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
17324 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
17326 fixp
->fx_file
= fragp
->fr_file
;
17327 fixp
->fx_line
= fragp
->fr_line
;
17328 fragp
->fr_fix
+= fragp
->fr_var
;
17331 /* Return the size of a relaxable immediate operand instruction.
17332 SHIFT and SIZE specify the form of the allowable immediate. */
17334 relax_immediate (fragS
*fragp
, int size
, int shift
)
17340 /* ??? Should be able to do better than this. */
17341 if (fragp
->fr_symbol
)
17344 low
= (1 << shift
) - 1;
17345 mask
= (1 << (shift
+ size
)) - (1 << shift
);
17346 offset
= fragp
->fr_offset
;
17347 /* Force misaligned offsets to 32-bit variant. */
17350 if (offset
& ~mask
)
17355 /* Get the address of a symbol during relaxation. */
17357 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
17363 sym
= fragp
->fr_symbol
;
17364 sym_frag
= symbol_get_frag (sym
);
17365 know (S_GET_SEGMENT (sym
) != absolute_section
17366 || sym_frag
== &zero_address_frag
);
17367 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
17369 /* If frag has yet to be reached on this pass, assume it will
17370 move by STRETCH just as we did. If this is not so, it will
17371 be because some frag between grows, and that will force
17375 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17379 /* Adjust stretch for any alignment frag. Note that if have
17380 been expanding the earlier code, the symbol may be
17381 defined in what appears to be an earlier frag. FIXME:
17382 This doesn't handle the fr_subtype field, which specifies
17383 a maximum number of bytes to skip when doing an
17385 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17387 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17390 stretch
= - ((- stretch
)
17391 & ~ ((1 << (int) f
->fr_offset
) - 1));
17393 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
17405 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
17408 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
17413 /* Assume worst case for symbols not known to be in the same section. */
17414 if (!S_IS_DEFINED (fragp
->fr_symbol
)
17415 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
17418 val
= relaxed_symbol_addr (fragp
, stretch
);
17419 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17420 addr
= (addr
+ 4) & ~3;
17421 /* Force misaligned targets to 32-bit variant. */
17425 if (val
< 0 || val
> 1020)
17430 /* Return the size of a relaxable add/sub immediate instruction. */
17432 relax_addsub (fragS
*fragp
, asection
*sec
)
17437 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17438 op
= bfd_get_16(sec
->owner
, buf
);
17439 if ((op
& 0xf) == ((op
>> 4) & 0xf))
17440 return relax_immediate (fragp
, 8, 0);
17442 return relax_immediate (fragp
, 3, 0);
17446 /* Return the size of a relaxable branch instruction. BITS is the
17447 size of the offset field in the narrow instruction. */
17450 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
17456 /* Assume worst case for symbols not known to be in the same section. */
17457 if (!S_IS_DEFINED (fragp
->fr_symbol
)
17458 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
17462 if (S_IS_DEFINED (fragp
->fr_symbol
)
17463 && ARM_IS_FUNC (fragp
->fr_symbol
))
17467 val
= relaxed_symbol_addr (fragp
, stretch
);
17468 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17471 /* Offset is a signed value *2 */
17473 if (val
>= limit
|| val
< -limit
)
17479 /* Relax a machine dependent frag. This returns the amount by which
17480 the current size of the frag should change. */
17483 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17488 oldsize
= fragp
->fr_var
;
17489 switch (fragp
->fr_subtype
)
17491 case T_MNEM_ldr_pc2
:
17492 newsize
= relax_adr (fragp
, sec
, stretch
);
17494 case T_MNEM_ldr_pc
:
17495 case T_MNEM_ldr_sp
:
17496 case T_MNEM_str_sp
:
17497 newsize
= relax_immediate (fragp
, 8, 2);
17501 newsize
= relax_immediate (fragp
, 5, 2);
17505 newsize
= relax_immediate (fragp
, 5, 1);
17509 newsize
= relax_immediate (fragp
, 5, 0);
17512 newsize
= relax_adr (fragp
, sec
, stretch
);
17518 newsize
= relax_immediate (fragp
, 8, 0);
17521 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
17524 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
17526 case T_MNEM_add_sp
:
17527 case T_MNEM_add_pc
:
17528 newsize
= relax_immediate (fragp
, 8, 2);
17530 case T_MNEM_inc_sp
:
17531 case T_MNEM_dec_sp
:
17532 newsize
= relax_immediate (fragp
, 7, 2);
17538 newsize
= relax_addsub (fragp
, sec
);
17544 fragp
->fr_var
= newsize
;
17545 /* Freeze wide instructions that are at or before the same location as
17546 in the previous pass. This avoids infinite loops.
17547 Don't freeze them unconditionally because targets may be artificially
17548 misaligned by the expansion of preceding frags. */
17549 if (stretch
<= 0 && newsize
> 2)
17551 md_convert_frag (sec
->owner
, sec
, fragp
);
17555 return newsize
- oldsize
;
17558 /* Round up a section size to the appropriate boundary. */
17561 md_section_align (segT segment ATTRIBUTE_UNUSED
,
17564 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
17565 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
17567 /* For a.out, force the section size to be aligned. If we don't do
17568 this, BFD will align it for us, but it will not write out the
17569 final bytes of the section. This may be a bug in BFD, but it is
17570 easier to fix it here since that is how the other a.out targets
17574 align
= bfd_get_section_alignment (stdoutput
, segment
);
17575 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
17582 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
17583 of an rs_align_code fragment. */
17586 arm_handle_align (fragS
* fragP
)
17588 static char const arm_noop
[2][2][4] =
17591 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
17592 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
17595 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
17596 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
17599 static char const thumb_noop
[2][2][2] =
17602 {0xc0, 0x46}, /* LE */
17603 {0x46, 0xc0}, /* BE */
17606 {0x00, 0xbf}, /* LE */
17607 {0xbf, 0x00} /* BE */
17610 static char const wide_thumb_noop
[2][4] =
17611 { /* Wide Thumb-2 */
17612 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
17613 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
17616 unsigned bytes
, fix
, noop_size
;
17619 const char *narrow_noop
= NULL
;
17621 if (fragP
->fr_type
!= rs_align_code
)
17624 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
17625 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
17628 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17629 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
17631 assert ((fragP
->tc_frag_data
& MODE_RECORDED
) != 0);
17633 if (fragP
->tc_frag_data
& (~ MODE_RECORDED
))
17635 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
17637 narrow_noop
= thumb_noop
[1][target_big_endian
];
17638 noop
= wide_thumb_noop
[target_big_endian
];
17641 noop
= thumb_noop
[0][target_big_endian
];
17646 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
17647 [target_big_endian
];
17651 fragP
->fr_var
= noop_size
;
17653 if (bytes
& (noop_size
- 1))
17655 fix
= bytes
& (noop_size
- 1);
17656 memset (p
, 0, fix
);
17663 if (bytes
& noop_size
)
17665 /* Insert a narrow noop. */
17666 memcpy (p
, narrow_noop
, noop_size
);
17668 bytes
-= noop_size
;
17672 /* Use wide noops for the remainder */
17676 while (bytes
>= noop_size
)
17678 memcpy (p
, noop
, noop_size
);
17680 bytes
-= noop_size
;
17684 fragP
->fr_fix
+= fix
;
17687 /* Called from md_do_align. Used to create an alignment
17688 frag in a code section. */
17691 arm_frag_align_code (int n
, int max
)
17695 /* We assume that there will never be a requirement
17696 to support alignments greater than 32 bytes. */
17697 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17698 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
17700 p
= frag_var (rs_align_code
,
17701 MAX_MEM_FOR_RS_ALIGN_CODE
,
17703 (relax_substateT
) max
,
17710 /* Perform target specific initialisation of a frag.
17711 Note - despite the name this initialisation is not done when the frag
17712 is created, but only when its type is assigned. A frag can be created
17713 and used a long time before its type is set, so beware of assuming that
17714 this initialisationis performed first. */
17717 arm_init_frag (fragS
* fragP
)
17719 /* If the current ARM vs THUMB mode has not already
17720 been recorded into this frag then do so now. */
17721 if ((fragP
->tc_frag_data
& MODE_RECORDED
) == 0)
17722 fragP
->tc_frag_data
= thumb_mode
| MODE_RECORDED
;
17726 /* When we change sections we need to issue a new mapping symbol. */
17729 arm_elf_change_section (void)
17732 segment_info_type
*seginfo
;
17734 /* Link an unlinked unwind index table section to the .text section. */
17735 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
17736 && elf_linked_to_section (now_seg
) == NULL
)
17737 elf_linked_to_section (now_seg
) = text_section
;
17739 if (!SEG_NORMAL (now_seg
))
17742 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
17744 /* We can ignore sections that only contain debug info. */
17745 if ((flags
& SEC_ALLOC
) == 0)
17748 seginfo
= seg_info (now_seg
);
17749 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
17750 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
17754 arm_elf_section_type (const char * str
, size_t len
)
17756 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
17757 return SHT_ARM_EXIDX
;
17762 /* Code to deal with unwinding tables. */
17764 static void add_unwind_adjustsp (offsetT
);
17766 /* Generate any deferred unwind frame offset. */
17769 flush_pending_unwind (void)
17773 offset
= unwind
.pending_offset
;
17774 unwind
.pending_offset
= 0;
17776 add_unwind_adjustsp (offset
);
17779 /* Add an opcode to this list for this function. Two-byte opcodes should
17780 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
17784 add_unwind_opcode (valueT op
, int length
)
17786 /* Add any deferred stack adjustment. */
17787 if (unwind
.pending_offset
)
17788 flush_pending_unwind ();
17790 unwind
.sp_restored
= 0;
17792 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
17794 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
17795 if (unwind
.opcodes
)
17796 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
17797 unwind
.opcode_alloc
);
17799 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
17804 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
17806 unwind
.opcode_count
++;
17810 /* Add unwind opcodes to adjust the stack pointer. */
17813 add_unwind_adjustsp (offsetT offset
)
17817 if (offset
> 0x200)
17819 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
17824 /* Long form: 0xb2, uleb128. */
17825 /* This might not fit in a word so add the individual bytes,
17826 remembering the list is built in reverse order. */
17827 o
= (valueT
) ((offset
- 0x204) >> 2);
17829 add_unwind_opcode (0, 1);
17831 /* Calculate the uleb128 encoding of the offset. */
17835 bytes
[n
] = o
& 0x7f;
17841 /* Add the insn. */
17843 add_unwind_opcode (bytes
[n
- 1], 1);
17844 add_unwind_opcode (0xb2, 1);
17846 else if (offset
> 0x100)
17848 /* Two short opcodes. */
17849 add_unwind_opcode (0x3f, 1);
17850 op
= (offset
- 0x104) >> 2;
17851 add_unwind_opcode (op
, 1);
17853 else if (offset
> 0)
17855 /* Short opcode. */
17856 op
= (offset
- 4) >> 2;
17857 add_unwind_opcode (op
, 1);
17859 else if (offset
< 0)
17862 while (offset
> 0x100)
17864 add_unwind_opcode (0x7f, 1);
17867 op
= ((offset
- 4) >> 2) | 0x40;
17868 add_unwind_opcode (op
, 1);
17872 /* Finish the list of unwind opcodes for this function. */
17874 finish_unwind_opcodes (void)
17878 if (unwind
.fp_used
)
17880 /* Adjust sp as necessary. */
17881 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
17882 flush_pending_unwind ();
17884 /* After restoring sp from the frame pointer. */
17885 op
= 0x90 | unwind
.fp_reg
;
17886 add_unwind_opcode (op
, 1);
17889 flush_pending_unwind ();
17893 /* Start an exception table entry. If idx is nonzero this is an index table
17897 start_unwind_section (const segT text_seg
, int idx
)
17899 const char * text_name
;
17900 const char * prefix
;
17901 const char * prefix_once
;
17902 const char * group_name
;
17906 size_t sec_name_len
;
17913 prefix
= ELF_STRING_ARM_unwind
;
17914 prefix_once
= ELF_STRING_ARM_unwind_once
;
17915 type
= SHT_ARM_EXIDX
;
17919 prefix
= ELF_STRING_ARM_unwind_info
;
17920 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
17921 type
= SHT_PROGBITS
;
17924 text_name
= segment_name (text_seg
);
17925 if (streq (text_name
, ".text"))
17928 if (strncmp (text_name
, ".gnu.linkonce.t.",
17929 strlen (".gnu.linkonce.t.")) == 0)
17931 prefix
= prefix_once
;
17932 text_name
+= strlen (".gnu.linkonce.t.");
17935 prefix_len
= strlen (prefix
);
17936 text_len
= strlen (text_name
);
17937 sec_name_len
= prefix_len
+ text_len
;
17938 sec_name
= xmalloc (sec_name_len
+ 1);
17939 memcpy (sec_name
, prefix
, prefix_len
);
17940 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
17941 sec_name
[prefix_len
+ text_len
] = '\0';
17947 /* Handle COMDAT group. */
17948 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
17950 group_name
= elf_group_name (text_seg
);
17951 if (group_name
== NULL
)
17953 as_bad (_("Group section `%s' has no group signature"),
17954 segment_name (text_seg
));
17955 ignore_rest_of_line ();
17958 flags
|= SHF_GROUP
;
17962 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
17964 /* Set the section link for index tables. */
17966 elf_linked_to_section (now_seg
) = text_seg
;
17970 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
17971 personality routine data. Returns zero, or the index table value for
17972 and inline entry. */
17975 create_unwind_entry (int have_data
)
17980 /* The current word of data. */
17982 /* The number of bytes left in this word. */
17985 finish_unwind_opcodes ();
17987 /* Remember the current text section. */
17988 unwind
.saved_seg
= now_seg
;
17989 unwind
.saved_subseg
= now_subseg
;
17991 start_unwind_section (now_seg
, 0);
17993 if (unwind
.personality_routine
== NULL
)
17995 if (unwind
.personality_index
== -2)
17998 as_bad (_("handlerdata in cantunwind frame"));
17999 return 1; /* EXIDX_CANTUNWIND. */
18002 /* Use a default personality routine if none is specified. */
18003 if (unwind
.personality_index
== -1)
18005 if (unwind
.opcode_count
> 3)
18006 unwind
.personality_index
= 1;
18008 unwind
.personality_index
= 0;
18011 /* Space for the personality routine entry. */
18012 if (unwind
.personality_index
== 0)
18014 if (unwind
.opcode_count
> 3)
18015 as_bad (_("too many unwind opcodes for personality routine 0"));
18019 /* All the data is inline in the index table. */
18022 while (unwind
.opcode_count
> 0)
18024 unwind
.opcode_count
--;
18025 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
18029 /* Pad with "finish" opcodes. */
18031 data
= (data
<< 8) | 0xb0;
18038 /* We get two opcodes "free" in the first word. */
18039 size
= unwind
.opcode_count
- 2;
18042 /* An extra byte is required for the opcode count. */
18043 size
= unwind
.opcode_count
+ 1;
18045 size
= (size
+ 3) >> 2;
18047 as_bad (_("too many unwind opcodes"));
18049 frag_align (2, 0, 0);
18050 record_alignment (now_seg
, 2);
18051 unwind
.table_entry
= expr_build_dot ();
18053 /* Allocate the table entry. */
18054 ptr
= frag_more ((size
<< 2) + 4);
18055 where
= frag_now_fix () - ((size
<< 2) + 4);
18057 switch (unwind
.personality_index
)
18060 /* ??? Should this be a PLT generating relocation? */
18061 /* Custom personality routine. */
18062 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
18063 BFD_RELOC_ARM_PREL31
);
18068 /* Set the first byte to the number of additional words. */
18073 /* ABI defined personality routines. */
18075 /* Three opcodes bytes are packed into the first word. */
18082 /* The size and first two opcode bytes go in the first word. */
18083 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
18088 /* Should never happen. */
18092 /* Pack the opcodes into words (MSB first), reversing the list at the same
18094 while (unwind
.opcode_count
> 0)
18098 md_number_to_chars (ptr
, data
, 4);
18103 unwind
.opcode_count
--;
18105 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
18108 /* Finish off the last word. */
18111 /* Pad with "finish" opcodes. */
18113 data
= (data
<< 8) | 0xb0;
18115 md_number_to_chars (ptr
, data
, 4);
18120 /* Add an empty descriptor if there is no user-specified data. */
18121 ptr
= frag_more (4);
18122 md_number_to_chars (ptr
, 0, 4);
18129 /* Initialize the DWARF-2 unwind information for this procedure. */
18132 tc_arm_frame_initial_instructions (void)
18134 cfi_add_CFA_def_cfa (REG_SP
, 0);
18136 #endif /* OBJ_ELF */
18138 /* Convert REGNAME to a DWARF-2 register number. */
18141 tc_arm_regname_to_dw2regnum (char *regname
)
18143 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
18153 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
18157 expr
.X_op
= O_secrel
;
18158 expr
.X_add_symbol
= symbol
;
18159 expr
.X_add_number
= 0;
18160 emit_expr (&expr
, size
);
18164 /* MD interface: Symbol and relocation handling. */
18166 /* Return the address within the segment that a PC-relative fixup is
18167 relative to. For ARM, PC-relative fixups applied to instructions
18168 are generally relative to the location of the fixup plus 8 bytes.
18169 Thumb branches are offset by 4, and Thumb loads relative to PC
18170 require special handling. */
18173 md_pcrel_from_section (fixS
* fixP
, segT seg
)
18175 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
18177 /* If this is pc-relative and we are going to emit a relocation
18178 then we just want to put out any pipeline compensation that the linker
18179 will need. Otherwise we want to use the calculated base.
18180 For WinCE we skip the bias for externals as well, since this
18181 is how the MS ARM-CE assembler behaves and we want to be compatible. */
18183 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
18184 || (arm_force_relocation (fixP
)
18186 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
18192 switch (fixP
->fx_r_type
)
18194 /* PC relative addressing on the Thumb is slightly odd as the
18195 bottom two bits of the PC are forced to zero for the
18196 calculation. This happens *after* application of the
18197 pipeline offset. However, Thumb adrl already adjusts for
18198 this, so we need not do it again. */
18199 case BFD_RELOC_ARM_THUMB_ADD
:
18202 case BFD_RELOC_ARM_THUMB_OFFSET
:
18203 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
18204 case BFD_RELOC_ARM_T32_ADD_PC12
:
18205 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
18206 return (base
+ 4) & ~3;
18208 /* Thumb branches are simply offset by +4. */
18209 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
18210 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
18211 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
18212 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18213 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18216 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18218 && ARM_IS_FUNC (fixP
->fx_addsy
)
18219 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
18220 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
18223 /* BLX is like branches above, but forces the low two bits of PC to
18225 case BFD_RELOC_THUMB_PCREL_BLX
:
18227 && THUMB_IS_FUNC (fixP
->fx_addsy
)
18228 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
18229 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
18230 return (base
+ 4) & ~3;
18232 /* ARM mode branches are offset by +8. However, the Windows CE
18233 loader expects the relocation not to take this into account. */
18234 case BFD_RELOC_ARM_PCREL_BLX
:
18236 && ARM_IS_FUNC (fixP
->fx_addsy
)
18237 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
18238 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
18241 case BFD_RELOC_ARM_PCREL_CALL
:
18243 && THUMB_IS_FUNC (fixP
->fx_addsy
)
18244 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
18245 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
18248 case BFD_RELOC_ARM_PCREL_BRANCH
:
18249 case BFD_RELOC_ARM_PCREL_JUMP
:
18250 case BFD_RELOC_ARM_PLT32
:
18252 /* When handling fixups immediately, because we have already
18253 discovered the value of a symbol, or the address of the frag involved
18254 we must account for the offset by +8, as the OS loader will never see the reloc.
18255 see fixup_segment() in write.c
18256 The S_IS_EXTERNAL test handles the case of global symbols.
18257 Those need the calculated base, not just the pipe compensation the linker will need. */
18259 && fixP
->fx_addsy
!= NULL
18260 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
18261 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
18269 /* ARM mode loads relative to PC are also offset by +8. Unlike
18270 branches, the Windows CE loader *does* expect the relocation
18271 to take this into account. */
18272 case BFD_RELOC_ARM_OFFSET_IMM
:
18273 case BFD_RELOC_ARM_OFFSET_IMM8
:
18274 case BFD_RELOC_ARM_HWLITERAL
:
18275 case BFD_RELOC_ARM_LITERAL
:
18276 case BFD_RELOC_ARM_CP_OFF_IMM
:
18280 /* Other PC-relative relocations are un-offset. */
18286 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
18287 Otherwise we have no need to default values of symbols. */
18290 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
18293 if (name
[0] == '_' && name
[1] == 'G'
18294 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
18298 if (symbol_find (name
))
18299 as_bad (_("GOT already in the symbol table"));
18301 GOT_symbol
= symbol_new (name
, undefined_section
,
18302 (valueT
) 0, & zero_address_frag
);
18312 /* Subroutine of md_apply_fix. Check to see if an immediate can be
18313 computed as two separate immediate values, added together. We
18314 already know that this value cannot be computed by just one ARM
18317 static unsigned int
18318 validate_immediate_twopart (unsigned int val
,
18319 unsigned int * highpart
)
18324 for (i
= 0; i
< 32; i
+= 2)
18325 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
18331 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
18333 else if (a
& 0xff0000)
18335 if (a
& 0xff000000)
18337 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
18341 assert (a
& 0xff000000);
18342 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
18345 return (a
& 0xff) | (i
<< 7);
18352 validate_offset_imm (unsigned int val
, int hwse
)
18354 if ((hwse
&& val
> 255) || val
> 4095)
18359 /* Subroutine of md_apply_fix. Do those data_ops which can take a
18360 negative immediate constant by altering the instruction. A bit of
18365 by inverting the second operand, and
18368 by negating the second operand. */
18371 negate_data_op (unsigned long * instruction
,
18372 unsigned long value
)
18375 unsigned long negated
, inverted
;
18377 negated
= encode_arm_immediate (-value
);
18378 inverted
= encode_arm_immediate (~value
);
18380 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
18383 /* First negates. */
18384 case OPCODE_SUB
: /* ADD <-> SUB */
18385 new_inst
= OPCODE_ADD
;
18390 new_inst
= OPCODE_SUB
;
18394 case OPCODE_CMP
: /* CMP <-> CMN */
18395 new_inst
= OPCODE_CMN
;
18400 new_inst
= OPCODE_CMP
;
18404 /* Now Inverted ops. */
18405 case OPCODE_MOV
: /* MOV <-> MVN */
18406 new_inst
= OPCODE_MVN
;
18411 new_inst
= OPCODE_MOV
;
18415 case OPCODE_AND
: /* AND <-> BIC */
18416 new_inst
= OPCODE_BIC
;
18421 new_inst
= OPCODE_AND
;
18425 case OPCODE_ADC
: /* ADC <-> SBC */
18426 new_inst
= OPCODE_SBC
;
18431 new_inst
= OPCODE_ADC
;
18435 /* We cannot do anything. */
18440 if (value
== (unsigned) FAIL
)
18443 *instruction
&= OPCODE_MASK
;
18444 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
18448 /* Like negate_data_op, but for Thumb-2. */
18450 static unsigned int
18451 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
18455 unsigned int negated
, inverted
;
18457 negated
= encode_thumb32_immediate (-value
);
18458 inverted
= encode_thumb32_immediate (~value
);
18460 rd
= (*instruction
>> 8) & 0xf;
18461 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
18464 /* ADD <-> SUB. Includes CMP <-> CMN. */
18465 case T2_OPCODE_SUB
:
18466 new_inst
= T2_OPCODE_ADD
;
18470 case T2_OPCODE_ADD
:
18471 new_inst
= T2_OPCODE_SUB
;
18475 /* ORR <-> ORN. Includes MOV <-> MVN. */
18476 case T2_OPCODE_ORR
:
18477 new_inst
= T2_OPCODE_ORN
;
18481 case T2_OPCODE_ORN
:
18482 new_inst
= T2_OPCODE_ORR
;
18486 /* AND <-> BIC. TST has no inverted equivalent. */
18487 case T2_OPCODE_AND
:
18488 new_inst
= T2_OPCODE_BIC
;
18495 case T2_OPCODE_BIC
:
18496 new_inst
= T2_OPCODE_AND
;
18501 case T2_OPCODE_ADC
:
18502 new_inst
= T2_OPCODE_SBC
;
18506 case T2_OPCODE_SBC
:
18507 new_inst
= T2_OPCODE_ADC
;
18511 /* We cannot do anything. */
18516 if (value
== (unsigned int)FAIL
)
18519 *instruction
&= T2_OPCODE_MASK
;
18520 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
18524 /* Read a 32-bit thumb instruction from buf. */
18525 static unsigned long
18526 get_thumb32_insn (char * buf
)
18528 unsigned long insn
;
18529 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
18530 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18536 /* We usually want to set the low bit on the address of thumb function
18537 symbols. In particular .word foo - . should have the low bit set.
18538 Generic code tries to fold the difference of two symbols to
18539 a constant. Prevent this and force a relocation when the first symbols
18540 is a thumb function. */
18542 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
18544 if (op
== O_subtract
18545 && l
->X_op
== O_symbol
18546 && r
->X_op
== O_symbol
18547 && THUMB_IS_FUNC (l
->X_add_symbol
))
18549 l
->X_op
= O_subtract
;
18550 l
->X_op_symbol
= r
->X_add_symbol
;
18551 l
->X_add_number
-= r
->X_add_number
;
18554 /* Process as normal. */
18559 md_apply_fix (fixS
* fixP
,
18563 offsetT value
= * valP
;
18565 unsigned int newimm
;
18566 unsigned long temp
;
18568 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
18570 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
18572 /* Note whether this will delete the relocation. */
18574 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
18577 /* On a 64-bit host, silently truncate 'value' to 32 bits for
18578 consistency with the behaviour on 32-bit hosts. Remember value
18580 value
&= 0xffffffff;
18581 value
^= 0x80000000;
18582 value
-= 0x80000000;
18585 fixP
->fx_addnumber
= value
;
18587 /* Same treatment for fixP->fx_offset. */
18588 fixP
->fx_offset
&= 0xffffffff;
18589 fixP
->fx_offset
^= 0x80000000;
18590 fixP
->fx_offset
-= 0x80000000;
18592 switch (fixP
->fx_r_type
)
18594 case BFD_RELOC_NONE
:
18595 /* This will need to go in the object file. */
18599 case BFD_RELOC_ARM_IMMEDIATE
:
18600 /* We claim that this fixup has been processed here,
18601 even if in fact we generate an error because we do
18602 not have a reloc for it, so tc_gen_reloc will reject it. */
18606 && ! S_IS_DEFINED (fixP
->fx_addsy
))
18608 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18609 _("undefined symbol %s used as an immediate value"),
18610 S_GET_NAME (fixP
->fx_addsy
));
18615 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
18617 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18618 _("symbol %s is in a different section"),
18619 S_GET_NAME (fixP
->fx_addsy
));
18623 newimm
= encode_arm_immediate (value
);
18624 temp
= md_chars_to_number (buf
, INSN_SIZE
);
18626 /* If the instruction will fail, see if we can fix things up by
18627 changing the opcode. */
18628 if (newimm
== (unsigned int) FAIL
18629 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
18631 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18632 _("invalid constant (%lx) after fixup"),
18633 (unsigned long) value
);
18637 newimm
|= (temp
& 0xfffff000);
18638 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
18641 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
18643 unsigned int highpart
= 0;
18644 unsigned int newinsn
= 0xe1a00000; /* nop. */
18647 && ! S_IS_DEFINED (fixP
->fx_addsy
))
18649 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18650 _("undefined symbol %s used as an immediate value"),
18651 S_GET_NAME (fixP
->fx_addsy
));
18656 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
18658 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18659 _("symbol %s is in a different section"),
18660 S_GET_NAME (fixP
->fx_addsy
));
18664 newimm
= encode_arm_immediate (value
);
18665 temp
= md_chars_to_number (buf
, INSN_SIZE
);
18667 /* If the instruction will fail, see if we can fix things up by
18668 changing the opcode. */
18669 if (newimm
== (unsigned int) FAIL
18670 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
18672 /* No ? OK - try using two ADD instructions to generate
18674 newimm
= validate_immediate_twopart (value
, & highpart
);
18676 /* Yes - then make sure that the second instruction is
18678 if (newimm
!= (unsigned int) FAIL
)
18680 /* Still No ? Try using a negated value. */
18681 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
18682 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
18683 /* Otherwise - give up. */
18686 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18687 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
18692 /* Replace the first operand in the 2nd instruction (which
18693 is the PC) with the destination register. We have
18694 already added in the PC in the first instruction and we
18695 do not want to do it again. */
18696 newinsn
&= ~ 0xf0000;
18697 newinsn
|= ((newinsn
& 0x0f000) << 4);
18700 newimm
|= (temp
& 0xfffff000);
18701 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
18703 highpart
|= (newinsn
& 0xfffff000);
18704 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
18708 case BFD_RELOC_ARM_OFFSET_IMM
:
18709 if (!fixP
->fx_done
&& seg
->use_rela_p
)
18712 case BFD_RELOC_ARM_LITERAL
:
18718 if (validate_offset_imm (value
, 0) == FAIL
)
18720 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
18721 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18722 _("invalid literal constant: pool needs to be closer"));
18724 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18725 _("bad immediate value for offset (%ld)"),
18730 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18731 newval
&= 0xff7ff000;
18732 newval
|= value
| (sign
? INDEX_UP
: 0);
18733 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18736 case BFD_RELOC_ARM_OFFSET_IMM8
:
18737 case BFD_RELOC_ARM_HWLITERAL
:
18743 if (validate_offset_imm (value
, 1) == FAIL
)
18745 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
18746 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18747 _("invalid literal constant: pool needs to be closer"));
18749 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
18754 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18755 newval
&= 0xff7ff0f0;
18756 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
18757 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18760 case BFD_RELOC_ARM_T32_OFFSET_U8
:
18761 if (value
< 0 || value
> 1020 || value
% 4 != 0)
18762 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18763 _("bad immediate value for offset (%ld)"), (long) value
);
18766 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
18768 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
18771 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
18772 /* This is a complicated relocation used for all varieties of Thumb32
18773 load/store instruction with immediate offset:
18775 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
18776 *4, optional writeback(W)
18777 (doubleword load/store)
18779 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
18780 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
18781 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
18782 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
18783 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
18785 Uppercase letters indicate bits that are already encoded at
18786 this point. Lowercase letters are our problem. For the
18787 second block of instructions, the secondary opcode nybble
18788 (bits 8..11) is present, and bit 23 is zero, even if this is
18789 a PC-relative operation. */
18790 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18792 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
18794 if ((newval
& 0xf0000000) == 0xe0000000)
18796 /* Doubleword load/store: 8-bit offset, scaled by 4. */
18798 newval
|= (1 << 23);
18801 if (value
% 4 != 0)
18803 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18804 _("offset not a multiple of 4"));
18810 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18811 _("offset out of range"));
18816 else if ((newval
& 0x000f0000) == 0x000f0000)
18818 /* PC-relative, 12-bit offset. */
18820 newval
|= (1 << 23);
18825 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18826 _("offset out of range"));
18831 else if ((newval
& 0x00000100) == 0x00000100)
18833 /* Writeback: 8-bit, +/- offset. */
18835 newval
|= (1 << 9);
18840 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18841 _("offset out of range"));
18846 else if ((newval
& 0x00000f00) == 0x00000e00)
18848 /* T-instruction: positive 8-bit offset. */
18849 if (value
< 0 || value
> 0xff)
18851 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18852 _("offset out of range"));
18860 /* Positive 12-bit or negative 8-bit offset. */
18864 newval
|= (1 << 23);
18874 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18875 _("offset out of range"));
18882 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
18883 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
18886 case BFD_RELOC_ARM_SHIFT_IMM
:
18887 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18888 if (((unsigned long) value
) > 32
18890 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
18892 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18893 _("shift expression is too large"));
18898 /* Shifts of zero must be done as lsl. */
18900 else if (value
== 32)
18902 newval
&= 0xfffff07f;
18903 newval
|= (value
& 0x1f) << 7;
18904 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18907 case BFD_RELOC_ARM_T32_IMMEDIATE
:
18908 case BFD_RELOC_ARM_T32_ADD_IMM
:
18909 case BFD_RELOC_ARM_T32_IMM12
:
18910 case BFD_RELOC_ARM_T32_ADD_PC12
:
18911 /* We claim that this fixup has been processed here,
18912 even if in fact we generate an error because we do
18913 not have a reloc for it, so tc_gen_reloc will reject it. */
18917 && ! S_IS_DEFINED (fixP
->fx_addsy
))
18919 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18920 _("undefined symbol %s used as an immediate value"),
18921 S_GET_NAME (fixP
->fx_addsy
));
18925 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18927 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
18930 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
18931 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18933 newimm
= encode_thumb32_immediate (value
);
18934 if (newimm
== (unsigned int) FAIL
)
18935 newimm
= thumb32_negate_data_op (&newval
, value
);
18937 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
18938 && newimm
== (unsigned int) FAIL
)
18940 /* Turn add/sum into addw/subw. */
18941 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18942 newval
= (newval
& 0xfeffffff) | 0x02000000;
18944 /* 12 bit immediate for addw/subw. */
18948 newval
^= 0x00a00000;
18951 newimm
= (unsigned int) FAIL
;
18956 if (newimm
== (unsigned int)FAIL
)
18958 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18959 _("invalid constant (%lx) after fixup"),
18960 (unsigned long) value
);
18964 newval
|= (newimm
& 0x800) << 15;
18965 newval
|= (newimm
& 0x700) << 4;
18966 newval
|= (newimm
& 0x0ff);
18968 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
18969 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
18972 case BFD_RELOC_ARM_SMC
:
18973 if (((unsigned long) value
) > 0xffff)
18974 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18975 _("invalid smc expression"));
18976 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18977 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
18978 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18981 case BFD_RELOC_ARM_SWI
:
18982 if (fixP
->tc_fix_data
!= 0)
18984 if (((unsigned long) value
) > 0xff)
18985 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18986 _("invalid swi expression"));
18987 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18989 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18993 if (((unsigned long) value
) > 0x00ffffff)
18994 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18995 _("invalid swi expression"));
18996 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18998 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19002 case BFD_RELOC_ARM_MULTI
:
19003 if (((unsigned long) value
) > 0xffff)
19004 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19005 _("invalid expression in load/store multiple"));
19006 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
19007 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19011 case BFD_RELOC_ARM_PCREL_CALL
:
19013 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
19015 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19016 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19017 && THUMB_IS_FUNC (fixP
->fx_addsy
))
19018 /* Flip the bl to blx. This is a simple flip
19019 bit here because we generate PCREL_CALL for
19020 unconditional bls. */
19022 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19023 newval
= newval
| 0x10000000;
19024 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19030 goto arm_branch_common
;
19032 case BFD_RELOC_ARM_PCREL_JUMP
:
19033 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
19035 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19036 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19037 && THUMB_IS_FUNC (fixP
->fx_addsy
))
19039 /* This would map to a bl<cond>, b<cond>,
19040 b<always> to a Thumb function. We
19041 need to force a relocation for this particular
19043 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19047 case BFD_RELOC_ARM_PLT32
:
19049 case BFD_RELOC_ARM_PCREL_BRANCH
:
19051 goto arm_branch_common
;
19053 case BFD_RELOC_ARM_PCREL_BLX
:
19056 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
19058 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19059 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19060 && ARM_IS_FUNC (fixP
->fx_addsy
))
19062 /* Flip the blx to a bl and warn. */
19063 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
19064 newval
= 0xeb000000;
19065 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
19066 _("blx to '%s' an ARM ISA state function changed to bl"),
19068 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19074 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
19075 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
19079 /* We are going to store value (shifted right by two) in the
19080 instruction, in a 24 bit, signed field. Bits 26 through 32 either
19081 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
19082 also be be clear. */
19084 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19085 _("misaligned branch destination"));
19086 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
19087 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
19088 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19089 _("branch out of range"));
19091 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19093 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19094 newval
|= (value
>> 2) & 0x00ffffff;
19095 /* Set the H bit on BLX instructions. */
19099 newval
|= 0x01000000;
19101 newval
&= ~0x01000000;
19103 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19107 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
19108 /* CBZ can only branch forward. */
19110 /* Attempts to use CBZ to branch to the next instruction
19111 (which, strictly speaking, are prohibited) will be turned into
19114 FIXME: It may be better to remove the instruction completely and
19115 perform relaxation. */
19118 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19119 newval
= 0xbf00; /* NOP encoding T1 */
19120 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19125 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19126 _("branch out of range"));
19128 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19130 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19131 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
19132 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19137 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
19138 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
19139 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19140 _("branch out of range"));
19142 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19144 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19145 newval
|= (value
& 0x1ff) >> 1;
19146 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19150 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
19151 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
19152 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19153 _("branch out of range"));
19155 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19157 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19158 newval
|= (value
& 0xfff) >> 1;
19159 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19163 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19165 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19166 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19167 && S_IS_DEFINED (fixP
->fx_addsy
)
19168 && ARM_IS_FUNC (fixP
->fx_addsy
)
19169 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19171 /* Force a relocation for a branch 20 bits wide. */
19174 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
19175 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19176 _("conditional branch out of range"));
19178 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19181 addressT S
, J1
, J2
, lo
, hi
;
19183 S
= (value
& 0x00100000) >> 20;
19184 J2
= (value
& 0x00080000) >> 19;
19185 J1
= (value
& 0x00040000) >> 18;
19186 hi
= (value
& 0x0003f000) >> 12;
19187 lo
= (value
& 0x00000ffe) >> 1;
19189 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19190 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19191 newval
|= (S
<< 10) | hi
;
19192 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
19193 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19194 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19198 case BFD_RELOC_THUMB_PCREL_BLX
:
19200 /* If there is a blx from a thumb state function to
19201 another thumb function flip this to a bl and warn
19205 && S_IS_DEFINED (fixP
->fx_addsy
)
19206 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19207 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19208 && THUMB_IS_FUNC (fixP
->fx_addsy
))
19210 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
19211 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
19212 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
19214 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19215 newval
= newval
| 0x1000;
19216 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
19217 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
19222 goto thumb_bl_common
;
19224 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19226 /* A bl from Thumb state ISA to an internal ARM state function
19227 is converted to a blx. */
19229 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19230 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19231 && S_IS_DEFINED (fixP
->fx_addsy
)
19232 && ARM_IS_FUNC (fixP
->fx_addsy
)
19233 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19235 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19236 newval
= newval
& ~0x1000;
19237 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
19238 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
19245 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
19246 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
19247 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
19250 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
19251 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19252 _("branch out of range"));
19254 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
19255 /* For a BLX instruction, make sure that the relocation is rounded up
19256 to a word boundary. This follows the semantics of the instruction
19257 which specifies that bit 1 of the target address will come from bit
19258 1 of the base address. */
19259 value
= (value
+ 1) & ~ 1;
19261 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19265 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19266 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19267 newval
|= (value
& 0x7fffff) >> 12;
19268 newval2
|= (value
& 0xfff) >> 1;
19269 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19270 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19274 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19275 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
19276 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19277 _("branch out of range"));
19279 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19282 addressT S
, I1
, I2
, lo
, hi
;
19284 S
= (value
& 0x01000000) >> 24;
19285 I1
= (value
& 0x00800000) >> 23;
19286 I2
= (value
& 0x00400000) >> 22;
19287 hi
= (value
& 0x003ff000) >> 12;
19288 lo
= (value
& 0x00000ffe) >> 1;
19293 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19294 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19295 newval
|= (S
<< 10) | hi
;
19296 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
19297 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19298 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19303 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19304 md_number_to_chars (buf
, value
, 1);
19308 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19309 md_number_to_chars (buf
, value
, 2);
19313 case BFD_RELOC_ARM_TLS_GD32
:
19314 case BFD_RELOC_ARM_TLS_LE32
:
19315 case BFD_RELOC_ARM_TLS_IE32
:
19316 case BFD_RELOC_ARM_TLS_LDM32
:
19317 case BFD_RELOC_ARM_TLS_LDO32
:
19318 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
19321 case BFD_RELOC_ARM_GOT32
:
19322 case BFD_RELOC_ARM_GOTOFF
:
19323 case BFD_RELOC_ARM_TARGET2
:
19324 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19325 md_number_to_chars (buf
, 0, 4);
19329 case BFD_RELOC_RVA
:
19331 case BFD_RELOC_ARM_TARGET1
:
19332 case BFD_RELOC_ARM_ROSEGREL32
:
19333 case BFD_RELOC_ARM_SBREL32
:
19334 case BFD_RELOC_32_PCREL
:
19336 case BFD_RELOC_32_SECREL
:
19338 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19340 /* For WinCE we only do this for pcrel fixups. */
19341 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
19343 md_number_to_chars (buf
, value
, 4);
19347 case BFD_RELOC_ARM_PREL31
:
19348 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19350 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
19351 if ((value
^ (value
>> 1)) & 0x40000000)
19353 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19354 _("rel31 relocation overflow"));
19356 newval
|= value
& 0x7fffffff;
19357 md_number_to_chars (buf
, newval
, 4);
19362 case BFD_RELOC_ARM_CP_OFF_IMM
:
19363 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19364 if (value
< -1023 || value
> 1023 || (value
& 3))
19365 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19366 _("co-processor offset out of range"));
19371 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
19372 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
19373 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19375 newval
= get_thumb32_insn (buf
);
19376 newval
&= 0xff7fff00;
19377 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
19378 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
19379 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
19380 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19382 put_thumb32_insn (buf
, newval
);
19385 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
19386 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
19387 if (value
< -255 || value
> 255)
19388 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19389 _("co-processor offset out of range"));
19391 goto cp_off_common
;
19393 case BFD_RELOC_ARM_THUMB_OFFSET
:
19394 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19395 /* Exactly what ranges, and where the offset is inserted depends
19396 on the type of instruction, we can establish this from the
19398 switch (newval
>> 12)
19400 case 4: /* PC load. */
19401 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
19402 forced to zero for these loads; md_pcrel_from has already
19403 compensated for this. */
19405 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19406 _("invalid offset, target not word aligned (0x%08lX)"),
19407 (((unsigned long) fixP
->fx_frag
->fr_address
19408 + (unsigned long) fixP
->fx_where
) & ~3)
19409 + (unsigned long) value
);
19411 if (value
& ~0x3fc)
19412 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19413 _("invalid offset, value too big (0x%08lX)"),
19416 newval
|= value
>> 2;
19419 case 9: /* SP load/store. */
19420 if (value
& ~0x3fc)
19421 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19422 _("invalid offset, value too big (0x%08lX)"),
19424 newval
|= value
>> 2;
19427 case 6: /* Word load/store. */
19429 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19430 _("invalid offset, value too big (0x%08lX)"),
19432 newval
|= value
<< 4; /* 6 - 2. */
19435 case 7: /* Byte load/store. */
19437 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19438 _("invalid offset, value too big (0x%08lX)"),
19440 newval
|= value
<< 6;
19443 case 8: /* Halfword load/store. */
19445 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19446 _("invalid offset, value too big (0x%08lX)"),
19448 newval
|= value
<< 5; /* 6 - 1. */
19452 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19453 "Unable to process relocation for thumb opcode: %lx",
19454 (unsigned long) newval
);
19457 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19460 case BFD_RELOC_ARM_THUMB_ADD
:
19461 /* This is a complicated relocation, since we use it for all of
19462 the following immediate relocations:
19466 9bit ADD/SUB SP word-aligned
19467 10bit ADD PC/SP word-aligned
19469 The type of instruction being processed is encoded in the
19476 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19478 int rd
= (newval
>> 4) & 0xf;
19479 int rs
= newval
& 0xf;
19480 int subtract
= !!(newval
& 0x8000);
19482 /* Check for HI regs, only very restricted cases allowed:
19483 Adjusting SP, and using PC or SP to get an address. */
19484 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
19485 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
19486 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19487 _("invalid Hi register with immediate"));
19489 /* If value is negative, choose the opposite instruction. */
19493 subtract
= !subtract
;
19495 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19496 _("immediate value out of range"));
19501 if (value
& ~0x1fc)
19502 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19503 _("invalid immediate for stack address calculation"));
19504 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
19505 newval
|= value
>> 2;
19507 else if (rs
== REG_PC
|| rs
== REG_SP
)
19509 if (subtract
|| value
& ~0x3fc)
19510 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19511 _("invalid immediate for address calculation (value = 0x%08lX)"),
19512 (unsigned long) value
);
19513 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
19515 newval
|= value
>> 2;
19520 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19521 _("immediate value out of range"));
19522 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
19523 newval
|= (rd
<< 8) | value
;
19528 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19529 _("immediate value out of range"));
19530 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
19531 newval
|= rd
| (rs
<< 3) | (value
<< 6);
19534 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19537 case BFD_RELOC_ARM_THUMB_IMM
:
19538 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19539 if (value
< 0 || value
> 255)
19540 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19541 _("invalid immediate: %ld is out of range"),
19544 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19547 case BFD_RELOC_ARM_THUMB_SHIFT
:
19548 /* 5bit shift value (0..32). LSL cannot take 32. */
19549 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
19550 temp
= newval
& 0xf800;
19551 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
19552 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19553 _("invalid shift value: %ld"), (long) value
);
19554 /* Shifts of zero must be encoded as LSL. */
19556 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
19557 /* Shifts of 32 are encoded as zero. */
19558 else if (value
== 32)
19560 newval
|= value
<< 6;
19561 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19564 case BFD_RELOC_VTABLE_INHERIT
:
19565 case BFD_RELOC_VTABLE_ENTRY
:
19569 case BFD_RELOC_ARM_MOVW
:
19570 case BFD_RELOC_ARM_MOVT
:
19571 case BFD_RELOC_ARM_THUMB_MOVW
:
19572 case BFD_RELOC_ARM_THUMB_MOVT
:
19573 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19575 /* REL format relocations are limited to a 16-bit addend. */
19576 if (!fixP
->fx_done
)
19578 if (value
< -0x8000 || value
> 0x7fff)
19579 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19580 _("offset out of range"));
19582 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
19583 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
19588 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
19589 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
19591 newval
= get_thumb32_insn (buf
);
19592 newval
&= 0xfbf08f00;
19593 newval
|= (value
& 0xf000) << 4;
19594 newval
|= (value
& 0x0800) << 15;
19595 newval
|= (value
& 0x0700) << 4;
19596 newval
|= (value
& 0x00ff);
19597 put_thumb32_insn (buf
, newval
);
19601 newval
= md_chars_to_number (buf
, 4);
19602 newval
&= 0xfff0f000;
19603 newval
|= value
& 0x0fff;
19604 newval
|= (value
& 0xf000) << 4;
19605 md_number_to_chars (buf
, newval
, 4);
19610 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
19611 case BFD_RELOC_ARM_ALU_PC_G0
:
19612 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
19613 case BFD_RELOC_ARM_ALU_PC_G1
:
19614 case BFD_RELOC_ARM_ALU_PC_G2
:
19615 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
19616 case BFD_RELOC_ARM_ALU_SB_G0
:
19617 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
19618 case BFD_RELOC_ARM_ALU_SB_G1
:
19619 case BFD_RELOC_ARM_ALU_SB_G2
:
19620 assert (!fixP
->fx_done
);
19621 if (!seg
->use_rela_p
)
19624 bfd_vma encoded_addend
;
19625 bfd_vma addend_abs
= abs (value
);
19627 /* Check that the absolute value of the addend can be
19628 expressed as an 8-bit constant plus a rotation. */
19629 encoded_addend
= encode_arm_immediate (addend_abs
);
19630 if (encoded_addend
== (unsigned int) FAIL
)
19631 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19632 _("the offset 0x%08lX is not representable"),
19633 (unsigned long) addend_abs
);
19635 /* Extract the instruction. */
19636 insn
= md_chars_to_number (buf
, INSN_SIZE
);
19638 /* If the addend is positive, use an ADD instruction.
19639 Otherwise use a SUB. Take care not to destroy the S bit. */
19640 insn
&= 0xff1fffff;
19646 /* Place the encoded addend into the first 12 bits of the
19648 insn
&= 0xfffff000;
19649 insn
|= encoded_addend
;
19651 /* Update the instruction. */
19652 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19656 case BFD_RELOC_ARM_LDR_PC_G0
:
19657 case BFD_RELOC_ARM_LDR_PC_G1
:
19658 case BFD_RELOC_ARM_LDR_PC_G2
:
19659 case BFD_RELOC_ARM_LDR_SB_G0
:
19660 case BFD_RELOC_ARM_LDR_SB_G1
:
19661 case BFD_RELOC_ARM_LDR_SB_G2
:
19662 assert (!fixP
->fx_done
);
19663 if (!seg
->use_rela_p
)
19666 bfd_vma addend_abs
= abs (value
);
19668 /* Check that the absolute value of the addend can be
19669 encoded in 12 bits. */
19670 if (addend_abs
>= 0x1000)
19671 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19672 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
19673 (unsigned long) addend_abs
);
19675 /* Extract the instruction. */
19676 insn
= md_chars_to_number (buf
, INSN_SIZE
);
19678 /* If the addend is negative, clear bit 23 of the instruction.
19679 Otherwise set it. */
19681 insn
&= ~(1 << 23);
19685 /* Place the absolute value of the addend into the first 12 bits
19686 of the instruction. */
19687 insn
&= 0xfffff000;
19688 insn
|= addend_abs
;
19690 /* Update the instruction. */
19691 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19695 case BFD_RELOC_ARM_LDRS_PC_G0
:
19696 case BFD_RELOC_ARM_LDRS_PC_G1
:
19697 case BFD_RELOC_ARM_LDRS_PC_G2
:
19698 case BFD_RELOC_ARM_LDRS_SB_G0
:
19699 case BFD_RELOC_ARM_LDRS_SB_G1
:
19700 case BFD_RELOC_ARM_LDRS_SB_G2
:
19701 assert (!fixP
->fx_done
);
19702 if (!seg
->use_rela_p
)
19705 bfd_vma addend_abs
= abs (value
);
19707 /* Check that the absolute value of the addend can be
19708 encoded in 8 bits. */
19709 if (addend_abs
>= 0x100)
19710 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19711 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
19712 (unsigned long) addend_abs
);
19714 /* Extract the instruction. */
19715 insn
= md_chars_to_number (buf
, INSN_SIZE
);
19717 /* If the addend is negative, clear bit 23 of the instruction.
19718 Otherwise set it. */
19720 insn
&= ~(1 << 23);
19724 /* Place the first four bits of the absolute value of the addend
19725 into the first 4 bits of the instruction, and the remaining
19726 four into bits 8 .. 11. */
19727 insn
&= 0xfffff0f0;
19728 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
19730 /* Update the instruction. */
19731 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19735 case BFD_RELOC_ARM_LDC_PC_G0
:
19736 case BFD_RELOC_ARM_LDC_PC_G1
:
19737 case BFD_RELOC_ARM_LDC_PC_G2
:
19738 case BFD_RELOC_ARM_LDC_SB_G0
:
19739 case BFD_RELOC_ARM_LDC_SB_G1
:
19740 case BFD_RELOC_ARM_LDC_SB_G2
:
19741 assert (!fixP
->fx_done
);
19742 if (!seg
->use_rela_p
)
19745 bfd_vma addend_abs
= abs (value
);
19747 /* Check that the absolute value of the addend is a multiple of
19748 four and, when divided by four, fits in 8 bits. */
19749 if (addend_abs
& 0x3)
19750 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19751 _("bad offset 0x%08lX (must be word-aligned)"),
19752 (unsigned long) addend_abs
);
19754 if ((addend_abs
>> 2) > 0xff)
19755 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19756 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
19757 (unsigned long) addend_abs
);
19759 /* Extract the instruction. */
19760 insn
= md_chars_to_number (buf
, INSN_SIZE
);
19762 /* If the addend is negative, clear bit 23 of the instruction.
19763 Otherwise set it. */
19765 insn
&= ~(1 << 23);
19769 /* Place the addend (divided by four) into the first eight
19770 bits of the instruction. */
19771 insn
&= 0xfffffff0;
19772 insn
|= addend_abs
>> 2;
19774 /* Update the instruction. */
19775 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19779 case BFD_RELOC_ARM_V4BX
:
19780 /* This will need to go in the object file. */
19784 case BFD_RELOC_UNUSED
:
19786 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19787 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
19791 /* Translate internal representation of relocation info to BFD target
19795 tc_gen_reloc (asection
*section
, fixS
*fixp
)
19798 bfd_reloc_code_real_type code
;
19800 reloc
= xmalloc (sizeof (arelent
));
19802 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
19803 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
19804 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
19806 if (fixp
->fx_pcrel
)
19808 if (section
->use_rela_p
)
19809 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
19811 fixp
->fx_offset
= reloc
->address
;
19813 reloc
->addend
= fixp
->fx_offset
;
19815 switch (fixp
->fx_r_type
)
19818 if (fixp
->fx_pcrel
)
19820 code
= BFD_RELOC_8_PCREL
;
19825 if (fixp
->fx_pcrel
)
19827 code
= BFD_RELOC_16_PCREL
;
19832 if (fixp
->fx_pcrel
)
19834 code
= BFD_RELOC_32_PCREL
;
19838 case BFD_RELOC_ARM_MOVW
:
19839 if (fixp
->fx_pcrel
)
19841 code
= BFD_RELOC_ARM_MOVW_PCREL
;
19845 case BFD_RELOC_ARM_MOVT
:
19846 if (fixp
->fx_pcrel
)
19848 code
= BFD_RELOC_ARM_MOVT_PCREL
;
19852 case BFD_RELOC_ARM_THUMB_MOVW
:
19853 if (fixp
->fx_pcrel
)
19855 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
19859 case BFD_RELOC_ARM_THUMB_MOVT
:
19860 if (fixp
->fx_pcrel
)
19862 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
19866 case BFD_RELOC_NONE
:
19867 case BFD_RELOC_ARM_PCREL_BRANCH
:
19868 case BFD_RELOC_ARM_PCREL_BLX
:
19869 case BFD_RELOC_RVA
:
19870 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19871 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19872 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19873 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19874 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19875 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19876 case BFD_RELOC_VTABLE_ENTRY
:
19877 case BFD_RELOC_VTABLE_INHERIT
:
19879 case BFD_RELOC_32_SECREL
:
19881 code
= fixp
->fx_r_type
;
19884 case BFD_RELOC_THUMB_PCREL_BLX
:
19886 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
19887 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
19890 code
= BFD_RELOC_THUMB_PCREL_BLX
;
19893 case BFD_RELOC_ARM_LITERAL
:
19894 case BFD_RELOC_ARM_HWLITERAL
:
19895 /* If this is called then the a literal has
19896 been referenced across a section boundary. */
19897 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19898 _("literal referenced across section boundary"));
19902 case BFD_RELOC_ARM_GOT32
:
19903 case BFD_RELOC_ARM_GOTOFF
:
19904 case BFD_RELOC_ARM_PLT32
:
19905 case BFD_RELOC_ARM_TARGET1
:
19906 case BFD_RELOC_ARM_ROSEGREL32
:
19907 case BFD_RELOC_ARM_SBREL32
:
19908 case BFD_RELOC_ARM_PREL31
:
19909 case BFD_RELOC_ARM_TARGET2
:
19910 case BFD_RELOC_ARM_TLS_LE32
:
19911 case BFD_RELOC_ARM_TLS_LDO32
:
19912 case BFD_RELOC_ARM_PCREL_CALL
:
19913 case BFD_RELOC_ARM_PCREL_JUMP
:
19914 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
19915 case BFD_RELOC_ARM_ALU_PC_G0
:
19916 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
19917 case BFD_RELOC_ARM_ALU_PC_G1
:
19918 case BFD_RELOC_ARM_ALU_PC_G2
:
19919 case BFD_RELOC_ARM_LDR_PC_G0
:
19920 case BFD_RELOC_ARM_LDR_PC_G1
:
19921 case BFD_RELOC_ARM_LDR_PC_G2
:
19922 case BFD_RELOC_ARM_LDRS_PC_G0
:
19923 case BFD_RELOC_ARM_LDRS_PC_G1
:
19924 case BFD_RELOC_ARM_LDRS_PC_G2
:
19925 case BFD_RELOC_ARM_LDC_PC_G0
:
19926 case BFD_RELOC_ARM_LDC_PC_G1
:
19927 case BFD_RELOC_ARM_LDC_PC_G2
:
19928 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
19929 case BFD_RELOC_ARM_ALU_SB_G0
:
19930 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
19931 case BFD_RELOC_ARM_ALU_SB_G1
:
19932 case BFD_RELOC_ARM_ALU_SB_G2
:
19933 case BFD_RELOC_ARM_LDR_SB_G0
:
19934 case BFD_RELOC_ARM_LDR_SB_G1
:
19935 case BFD_RELOC_ARM_LDR_SB_G2
:
19936 case BFD_RELOC_ARM_LDRS_SB_G0
:
19937 case BFD_RELOC_ARM_LDRS_SB_G1
:
19938 case BFD_RELOC_ARM_LDRS_SB_G2
:
19939 case BFD_RELOC_ARM_LDC_SB_G0
:
19940 case BFD_RELOC_ARM_LDC_SB_G1
:
19941 case BFD_RELOC_ARM_LDC_SB_G2
:
19942 case BFD_RELOC_ARM_V4BX
:
19943 code
= fixp
->fx_r_type
;
19946 case BFD_RELOC_ARM_TLS_GD32
:
19947 case BFD_RELOC_ARM_TLS_IE32
:
19948 case BFD_RELOC_ARM_TLS_LDM32
:
19949 /* BFD will include the symbol's address in the addend.
19950 But we don't want that, so subtract it out again here. */
19951 if (!S_IS_COMMON (fixp
->fx_addsy
))
19952 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
19953 code
= fixp
->fx_r_type
;
19957 case BFD_RELOC_ARM_IMMEDIATE
:
19958 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19959 _("internal relocation (type: IMMEDIATE) not fixed up"));
19962 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19963 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19964 _("ADRL used for a symbol not defined in the same file"));
19967 case BFD_RELOC_ARM_OFFSET_IMM
:
19968 if (section
->use_rela_p
)
19970 code
= fixp
->fx_r_type
;
19974 if (fixp
->fx_addsy
!= NULL
19975 && !S_IS_DEFINED (fixp
->fx_addsy
)
19976 && S_IS_LOCAL (fixp
->fx_addsy
))
19978 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19979 _("undefined local label `%s'"),
19980 S_GET_NAME (fixp
->fx_addsy
));
19984 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19985 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
19992 switch (fixp
->fx_r_type
)
19994 case BFD_RELOC_NONE
: type
= "NONE"; break;
19995 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
19996 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
19997 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
19998 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
19999 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
20000 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
20001 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
20002 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
20003 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
20004 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
20005 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
20006 default: type
= _("<unknown>"); break;
20008 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20009 _("cannot represent %s relocation in this object file format"),
20016 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
20018 && fixp
->fx_addsy
== GOT_symbol
)
20020 code
= BFD_RELOC_ARM_GOTPC
;
20021 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
20025 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
20027 if (reloc
->howto
== NULL
)
20029 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20030 _("cannot represent %s relocation in this object file format"),
20031 bfd_get_reloc_code_name (code
));
20035 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
20036 vtable entry to be used in the relocation's section offset. */
20037 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
20038 reloc
->address
= fixp
->fx_offset
;
20043 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
20046 cons_fix_new_arm (fragS
* frag
,
20051 bfd_reloc_code_real_type type
;
20055 FIXME: @@ Should look at CPU word size. */
20059 type
= BFD_RELOC_8
;
20062 type
= BFD_RELOC_16
;
20066 type
= BFD_RELOC_32
;
20069 type
= BFD_RELOC_64
;
20074 if (exp
->X_op
== O_secrel
)
20076 exp
->X_op
= O_symbol
;
20077 type
= BFD_RELOC_32_SECREL
;
20081 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
20084 #if defined (OBJ_COFF)
20086 arm_validate_fix (fixS
* fixP
)
20088 /* If the destination of the branch is a defined symbol which does not have
20089 the THUMB_FUNC attribute, then we must be calling a function which has
20090 the (interfacearm) attribute. We look for the Thumb entry point to that
20091 function and change the branch to refer to that function instead. */
20092 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
20093 && fixP
->fx_addsy
!= NULL
20094 && S_IS_DEFINED (fixP
->fx_addsy
)
20095 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
20097 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
20104 arm_force_relocation (struct fix
* fixp
)
20106 #if defined (OBJ_COFF) && defined (TE_PE)
20107 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
20111 /* In case we have a call or a branch to a function in ARM ISA mode from
20112 a thumb function or vice-versa force the relocation. These relocations
20113 are cleared off for some cores that might have blx and simple transformations
20117 switch (fixp
->fx_r_type
)
20119 case BFD_RELOC_ARM_PCREL_JUMP
:
20120 case BFD_RELOC_ARM_PCREL_CALL
:
20121 case BFD_RELOC_THUMB_PCREL_BLX
:
20122 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
20126 case BFD_RELOC_ARM_PCREL_BLX
:
20127 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20128 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20129 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20130 if (ARM_IS_FUNC (fixp
->fx_addsy
))
20139 /* Resolve these relocations even if the symbol is extern or weak. */
20140 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
20141 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
20142 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
20143 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
20144 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20145 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
20146 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
20149 /* Always leave these relocations for the linker. */
20150 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
20151 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
20152 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
20155 /* Always generate relocations against function symbols. */
20156 if (fixp
->fx_r_type
== BFD_RELOC_32
20158 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
20161 return generic_force_reloc (fixp
);
20164 #if defined (OBJ_ELF) || defined (OBJ_COFF)
20165 /* Relocations against function names must be left unadjusted,
20166 so that the linker can use this information to generate interworking
20167 stubs. The MIPS version of this function
20168 also prevents relocations that are mips-16 specific, but I do not
20169 know why it does this.
20172 There is one other problem that ought to be addressed here, but
20173 which currently is not: Taking the address of a label (rather
20174 than a function) and then later jumping to that address. Such
20175 addresses also ought to have their bottom bit set (assuming that
20176 they reside in Thumb code), but at the moment they will not. */
20179 arm_fix_adjustable (fixS
* fixP
)
20181 if (fixP
->fx_addsy
== NULL
)
20184 /* Preserve relocations against symbols with function type. */
20185 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
20188 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
20189 && fixP
->fx_subsy
== NULL
)
20192 /* We need the symbol name for the VTABLE entries. */
20193 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
20194 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
20197 /* Don't allow symbols to be discarded on GOT related relocs. */
20198 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
20199 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
20200 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
20201 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
20202 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
20203 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
20204 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
20205 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
20206 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
20209 /* Similarly for group relocations. */
20210 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
20211 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
20212 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
20215 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
20216 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
20217 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
20218 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
20219 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
20220 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20221 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
20222 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
20223 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
20228 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
20233 elf32_arm_target_format (void)
20236 return (target_big_endian
20237 ? "elf32-bigarm-symbian"
20238 : "elf32-littlearm-symbian");
20239 #elif defined (TE_VXWORKS)
20240 return (target_big_endian
20241 ? "elf32-bigarm-vxworks"
20242 : "elf32-littlearm-vxworks");
20244 if (target_big_endian
)
20245 return "elf32-bigarm";
20247 return "elf32-littlearm";
20252 armelf_frob_symbol (symbolS
* symp
,
20255 elf_frob_symbol (symp
, puntp
);
20259 /* MD interface: Finalization. */
20261 /* A good place to do this, although this was probably not intended
20262 for this kind of use. We need to dump the literal pool before
20263 references are made to a null symbol pointer. */
20268 literal_pool
* pool
;
20270 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
20272 /* Put it at the end of the relevant section. */
20273 subseg_set (pool
->section
, pool
->sub_section
);
20275 arm_elf_change_section ();
20281 /* Adjust the symbol table. This marks Thumb symbols as distinct from
20285 arm_adjust_symtab (void)
20290 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
20292 if (ARM_IS_THUMB (sym
))
20294 if (THUMB_IS_FUNC (sym
))
20296 /* Mark the symbol as a Thumb function. */
20297 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
20298 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
20299 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
20301 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
20302 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
20304 as_bad (_("%s: unexpected function type: %d"),
20305 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
20307 else switch (S_GET_STORAGE_CLASS (sym
))
20310 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
20313 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
20316 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
20324 if (ARM_IS_INTERWORK (sym
))
20325 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
20332 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
20334 if (ARM_IS_THUMB (sym
))
20336 elf_symbol_type
* elf_sym
;
20338 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
20339 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
20341 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
20342 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
20344 /* If it's a .thumb_func, declare it as so,
20345 otherwise tag label as .code 16. */
20346 if (THUMB_IS_FUNC (sym
))
20347 elf_sym
->internal_elf_sym
.st_info
=
20348 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
20349 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
20350 elf_sym
->internal_elf_sym
.st_info
=
20351 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
20358 /* MD interface: Initialization. */
20361 set_constant_flonums (void)
20365 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
20366 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
20370 /* Auto-select Thumb mode if it's the only available instruction set for the
20371 given architecture. */
20374 autoselect_thumb_from_cpu_variant (void)
20376 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
20377 opcode_select (16);
20386 if ( (arm_ops_hsh
= hash_new ()) == NULL
20387 || (arm_cond_hsh
= hash_new ()) == NULL
20388 || (arm_shift_hsh
= hash_new ()) == NULL
20389 || (arm_psr_hsh
= hash_new ()) == NULL
20390 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
20391 || (arm_reg_hsh
= hash_new ()) == NULL
20392 || (arm_reloc_hsh
= hash_new ()) == NULL
20393 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
20394 as_fatal (_("virtual memory exhausted"));
20396 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
20397 hash_insert (arm_ops_hsh
, insns
[i
].template, (void *) (insns
+ i
));
20398 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
20399 hash_insert (arm_cond_hsh
, conds
[i
].template, (void *) (conds
+ i
));
20400 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
20401 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
20402 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
20403 hash_insert (arm_psr_hsh
, psrs
[i
].template, (void *) (psrs
+ i
));
20404 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
20405 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (void *) (v7m_psrs
+ i
));
20406 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
20407 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
20409 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
20411 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
20412 (void *) (barrier_opt_names
+ i
));
20414 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
20415 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
20418 set_constant_flonums ();
20420 /* Set the cpu variant based on the command-line options. We prefer
20421 -mcpu= over -march= if both are set (as for GCC); and we prefer
20422 -mfpu= over any other way of setting the floating point unit.
20423 Use of legacy options with new options are faulted. */
20426 if (mcpu_cpu_opt
|| march_cpu_opt
)
20427 as_bad (_("use of old and new-style options to set CPU type"));
20429 mcpu_cpu_opt
= legacy_cpu
;
20431 else if (!mcpu_cpu_opt
)
20432 mcpu_cpu_opt
= march_cpu_opt
;
20437 as_bad (_("use of old and new-style options to set FPU type"));
20439 mfpu_opt
= legacy_fpu
;
20441 else if (!mfpu_opt
)
20443 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
20444 || defined (TE_NetBSD) || defined (TE_VXWORKS))
20445 /* Some environments specify a default FPU. If they don't, infer it
20446 from the processor. */
20448 mfpu_opt
= mcpu_fpu_opt
;
20450 mfpu_opt
= march_fpu_opt
;
20452 mfpu_opt
= &fpu_default
;
20458 if (mcpu_cpu_opt
!= NULL
)
20459 mfpu_opt
= &fpu_default
;
20460 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
20461 mfpu_opt
= &fpu_arch_vfp_v2
;
20463 mfpu_opt
= &fpu_arch_fpa
;
20469 mcpu_cpu_opt
= &cpu_default
;
20470 selected_cpu
= cpu_default
;
20474 selected_cpu
= *mcpu_cpu_opt
;
20476 mcpu_cpu_opt
= &arm_arch_any
;
20479 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20481 autoselect_thumb_from_cpu_variant ();
20483 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
20485 #if defined OBJ_COFF || defined OBJ_ELF
20487 unsigned int flags
= 0;
20489 #if defined OBJ_ELF
20490 flags
= meabi_flags
;
20492 switch (meabi_flags
)
20494 case EF_ARM_EABI_UNKNOWN
:
20496 /* Set the flags in the private structure. */
20497 if (uses_apcs_26
) flags
|= F_APCS26
;
20498 if (support_interwork
) flags
|= F_INTERWORK
;
20499 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
20500 if (pic_code
) flags
|= F_PIC
;
20501 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
20502 flags
|= F_SOFT_FLOAT
;
20504 switch (mfloat_abi_opt
)
20506 case ARM_FLOAT_ABI_SOFT
:
20507 case ARM_FLOAT_ABI_SOFTFP
:
20508 flags
|= F_SOFT_FLOAT
;
20511 case ARM_FLOAT_ABI_HARD
:
20512 if (flags
& F_SOFT_FLOAT
)
20513 as_bad (_("hard-float conflicts with specified fpu"));
20517 /* Using pure-endian doubles (even if soft-float). */
20518 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
20519 flags
|= F_VFP_FLOAT
;
20521 #if defined OBJ_ELF
20522 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
20523 flags
|= EF_ARM_MAVERICK_FLOAT
;
20526 case EF_ARM_EABI_VER4
:
20527 case EF_ARM_EABI_VER5
:
20528 /* No additional flags to set. */
20535 bfd_set_private_flags (stdoutput
, flags
);
20537 /* We have run out flags in the COFF header to encode the
20538 status of ATPCS support, so instead we create a dummy,
20539 empty, debug section called .arm.atpcs. */
20544 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
20548 bfd_set_section_flags
20549 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
20550 bfd_set_section_size (stdoutput
, sec
, 0);
20551 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
20557 /* Record the CPU type as well. */
20558 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
20559 mach
= bfd_mach_arm_iWMMXt2
;
20560 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
20561 mach
= bfd_mach_arm_iWMMXt
;
20562 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
20563 mach
= bfd_mach_arm_XScale
;
20564 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
20565 mach
= bfd_mach_arm_ep9312
;
20566 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
20567 mach
= bfd_mach_arm_5TE
;
20568 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
20570 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
20571 mach
= bfd_mach_arm_5T
;
20573 mach
= bfd_mach_arm_5
;
20575 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
20577 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
20578 mach
= bfd_mach_arm_4T
;
20580 mach
= bfd_mach_arm_4
;
20582 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
20583 mach
= bfd_mach_arm_3M
;
20584 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
20585 mach
= bfd_mach_arm_3
;
20586 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
20587 mach
= bfd_mach_arm_2a
;
20588 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
20589 mach
= bfd_mach_arm_2
;
20591 mach
= bfd_mach_arm_unknown
;
20593 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
20596 /* Command line processing. */
20599 Invocation line includes a switch not recognized by the base assembler.
20600 See if it's a processor-specific option.
20602 This routine is somewhat complicated by the need for backwards
20603 compatibility (since older releases of gcc can't be changed).
20604 The new options try to make the interface as compatible as
20607 New options (supported) are:
20609 -mcpu=<cpu name> Assemble for selected processor
20610 -march=<architecture name> Assemble for selected architecture
20611 -mfpu=<fpu architecture> Assemble for selected FPU.
20612 -EB/-mbig-endian Big-endian
20613 -EL/-mlittle-endian Little-endian
20614 -k Generate PIC code
20615 -mthumb Start in Thumb mode
20616 -mthumb-interwork Code supports ARM/Thumb interworking
20618 -m[no-]warn-deprecated Warn about deprecated features
20620 For now we will also provide support for:
20622 -mapcs-32 32-bit Program counter
20623 -mapcs-26 26-bit Program counter
20624 -macps-float Floats passed in FP registers
20625 -mapcs-reentrant Reentrant code
20627 (sometime these will probably be replaced with -mapcs=<list of options>
20628 and -matpcs=<list of options>)
20630 The remaining options are only supported for back-wards compatibility.
20631 Cpu variants, the arm part is optional:
20632 -m[arm]1 Currently not supported.
20633 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
20634 -m[arm]3 Arm 3 processor
20635 -m[arm]6[xx], Arm 6 processors
20636 -m[arm]7[xx][t][[d]m] Arm 7 processors
20637 -m[arm]8[10] Arm 8 processors
20638 -m[arm]9[20][tdmi] Arm 9 processors
20639 -mstrongarm[110[0]] StrongARM processors
20640 -mxscale XScale processors
20641 -m[arm]v[2345[t[e]]] Arm architectures
20642 -mall All (except the ARM1)
20644 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
20645 -mfpe-old (No float load/store multiples)
20646 -mvfpxd VFP Single precision
20648 -mno-fpu Disable all floating point instructions
20650 The following CPU names are recognized:
20651 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
20652 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
20653 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
20654 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
20655 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
20656 arm10t arm10e, arm1020t, arm1020e, arm10200e,
20657 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
20661 const char * md_shortopts
= "m:k";
20663 #ifdef ARM_BI_ENDIAN
20664 #define OPTION_EB (OPTION_MD_BASE + 0)
20665 #define OPTION_EL (OPTION_MD_BASE + 1)
20667 #if TARGET_BYTES_BIG_ENDIAN
20668 #define OPTION_EB (OPTION_MD_BASE + 0)
20670 #define OPTION_EL (OPTION_MD_BASE + 1)
20673 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
20675 struct option md_longopts
[] =
20678 {"EB", no_argument
, NULL
, OPTION_EB
},
20681 {"EL", no_argument
, NULL
, OPTION_EL
},
20683 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
20684 {NULL
, no_argument
, NULL
, 0}
20687 size_t md_longopts_size
= sizeof (md_longopts
);
20689 struct arm_option_table
20691 char *option
; /* Option name to match. */
20692 char *help
; /* Help information. */
20693 int *var
; /* Variable to change. */
20694 int value
; /* What to change it to. */
20695 char *deprecated
; /* If non-null, print this message. */
20698 struct arm_option_table arm_opts
[] =
20700 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
20701 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
20702 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
20703 &support_interwork
, 1, NULL
},
20704 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
20705 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
20706 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
20708 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
20709 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
20710 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
20711 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
20714 /* These are recognized by the assembler, but have no affect on code. */
20715 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
20716 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
20718 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
20719 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
20720 &warn_on_deprecated
, 0, NULL
},
20721 {NULL
, NULL
, NULL
, 0, NULL
}
20724 struct arm_legacy_option_table
20726 char *option
; /* Option name to match. */
20727 const arm_feature_set
**var
; /* Variable to change. */
20728 const arm_feature_set value
; /* What to change it to. */
20729 char *deprecated
; /* If non-null, print this message. */
20732 const struct arm_legacy_option_table arm_legacy_opts
[] =
20734 /* DON'T add any new processors to this list -- we want the whole list
20735 to go away... Add them to the processors table instead. */
20736 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
20737 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
20738 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
20739 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
20740 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
20741 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
20742 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
20743 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
20744 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
20745 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
20746 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
20747 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
20748 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
20749 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
20750 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
20751 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
20752 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
20753 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
20754 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
20755 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
20756 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
20757 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
20758 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
20759 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
20760 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
20761 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
20762 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
20763 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
20764 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
20765 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
20766 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
20767 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
20768 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
20769 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
20770 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
20771 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
20772 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
20773 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
20774 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
20775 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
20776 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
20777 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
20778 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
20779 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
20780 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
20781 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
20782 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20783 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20784 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20785 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20786 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
20787 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
20788 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
20789 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
20790 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
20791 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
20792 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
20793 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
20794 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
20795 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
20796 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
20797 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
20798 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
20799 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
20800 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
20801 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
20802 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
20803 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
20804 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
20805 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
20806 N_("use -mcpu=strongarm110")},
20807 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
20808 N_("use -mcpu=strongarm1100")},
20809 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
20810 N_("use -mcpu=strongarm1110")},
20811 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
20812 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
20813 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
20815 /* Architecture variants -- don't add any more to this list either. */
20816 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
20817 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
20818 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
20819 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
20820 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
20821 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
20822 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
20823 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
20824 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
20825 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
20826 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
20827 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
20828 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
20829 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
20830 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
20831 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
20832 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
20833 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
20835 /* Floating point variants -- don't add any more to this list either. */
20836 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
20837 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
20838 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
20839 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
20840 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
20842 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
20845 struct arm_cpu_option_table
20848 const arm_feature_set value
;
20849 /* For some CPUs we assume an FPU unless the user explicitly sets
20851 const arm_feature_set default_fpu
;
20852 /* The canonical name of the CPU, or NULL to use NAME converted to upper
20854 const char *canonical_name
;
20857 /* This list should, at a minimum, contain all the cpu names
20858 recognized by GCC. */
20859 static const struct arm_cpu_option_table arm_cpus
[] =
20861 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
20862 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
20863 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
20864 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
20865 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
20866 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20867 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20868 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20869 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20870 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20871 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20872 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20873 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20874 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20875 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20876 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20877 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20878 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20879 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20880 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20881 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20882 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20883 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20884 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20885 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20886 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20887 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20888 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20889 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20890 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20891 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20892 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20893 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20894 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20895 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20896 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20897 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20898 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20899 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20900 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
20901 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20902 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20903 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20904 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20905 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20906 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20907 /* For V5 or later processors we default to using VFP; but the user
20908 should really set the FPU type explicitly. */
20909 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20910 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20911 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20912 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20913 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20914 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20915 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
20916 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20917 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20918 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
20919 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20920 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20921 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20922 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20923 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20924 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
20925 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20926 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20927 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20928 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
20929 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20930 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
20931 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20932 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
20933 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
20934 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
20935 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
20936 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
20937 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
20938 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
20939 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
20940 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
20941 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
20942 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
20943 | FPU_NEON_EXT_V1
),
20945 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
20946 | FPU_NEON_EXT_V1
),
20948 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
20949 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
20950 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
20951 {"cortex-m0", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
20952 /* ??? XSCALE is really an architecture. */
20953 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20954 /* ??? iwmmxt is not a processor. */
20955 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
20956 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
20957 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20959 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
20960 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
20963 struct arm_arch_option_table
20966 const arm_feature_set value
;
20967 const arm_feature_set default_fpu
;
20970 /* This list should, at a minimum, contain all the architecture names
20971 recognized by GCC. */
20972 static const struct arm_arch_option_table arm_archs
[] =
20974 {"all", ARM_ANY
, FPU_ARCH_FPA
},
20975 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
20976 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
20977 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20978 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20979 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
20980 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
20981 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
20982 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
20983 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
20984 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
20985 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
20986 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
20987 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
20988 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
20989 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
20990 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
20991 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20992 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20993 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
20994 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
20995 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
20996 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
20997 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
20998 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
20999 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
21000 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
21001 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
21002 /* The official spelling of the ARMv7 profile variants is the dashed form.
21003 Accept the non-dashed form for compatibility with old toolchains. */
21004 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
21005 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
21006 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
21007 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
21008 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
21009 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
21010 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
21011 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
21012 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
21013 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
21016 /* ISA extensions in the co-processor space. */
21017 struct arm_option_cpu_value_table
21020 const arm_feature_set value
;
21023 static const struct arm_option_cpu_value_table arm_extensions
[] =
21025 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
21026 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
21027 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
21028 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
21029 {NULL
, ARM_ARCH_NONE
}
21032 /* This list should, at a minimum, contain all the fpu names
21033 recognized by GCC. */
21034 static const struct arm_option_cpu_value_table arm_fpus
[] =
21036 {"softfpa", FPU_NONE
},
21037 {"fpe", FPU_ARCH_FPE
},
21038 {"fpe2", FPU_ARCH_FPE
},
21039 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
21040 {"fpa", FPU_ARCH_FPA
},
21041 {"fpa10", FPU_ARCH_FPA
},
21042 {"fpa11", FPU_ARCH_FPA
},
21043 {"arm7500fe", FPU_ARCH_FPA
},
21044 {"softvfp", FPU_ARCH_VFP
},
21045 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
21046 {"vfp", FPU_ARCH_VFP_V2
},
21047 {"vfp9", FPU_ARCH_VFP_V2
},
21048 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
21049 {"vfp10", FPU_ARCH_VFP_V2
},
21050 {"vfp10-r0", FPU_ARCH_VFP_V1
},
21051 {"vfpxd", FPU_ARCH_VFP_V1xD
},
21052 {"vfpv2", FPU_ARCH_VFP_V2
},
21053 {"vfpv3", FPU_ARCH_VFP_V3
},
21054 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
21055 {"arm1020t", FPU_ARCH_VFP_V1
},
21056 {"arm1020e", FPU_ARCH_VFP_V2
},
21057 {"arm1136jfs", FPU_ARCH_VFP_V2
},
21058 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
21059 {"maverick", FPU_ARCH_MAVERICK
},
21060 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
21061 {"neon-fp16", FPU_ARCH_NEON_FP16
},
21062 {NULL
, ARM_ARCH_NONE
}
21065 struct arm_option_value_table
21071 static const struct arm_option_value_table arm_float_abis
[] =
21073 {"hard", ARM_FLOAT_ABI_HARD
},
21074 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
21075 {"soft", ARM_FLOAT_ABI_SOFT
},
21080 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
21081 static const struct arm_option_value_table arm_eabis
[] =
21083 {"gnu", EF_ARM_EABI_UNKNOWN
},
21084 {"4", EF_ARM_EABI_VER4
},
21085 {"5", EF_ARM_EABI_VER5
},
21090 struct arm_long_option_table
21092 char * option
; /* Substring to match. */
21093 char * help
; /* Help information. */
21094 int (* func
) (char * subopt
); /* Function to decode sub-option. */
21095 char * deprecated
; /* If non-null, print this message. */
21099 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
21101 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
21103 /* Copy the feature set, so that we can modify it. */
21104 *ext_set
= **opt_p
;
21107 while (str
!= NULL
&& *str
!= 0)
21109 const struct arm_option_cpu_value_table
* opt
;
21115 as_bad (_("invalid architectural extension"));
21120 ext
= strchr (str
, '+');
21123 optlen
= ext
- str
;
21125 optlen
= strlen (str
);
21129 as_bad (_("missing architectural extension"));
21133 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
21134 if (strncmp (opt
->name
, str
, optlen
) == 0)
21136 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
21140 if (opt
->name
== NULL
)
21142 as_bad (_("unknown architectural extension `%s'"), str
);
21153 arm_parse_cpu (char * str
)
21155 const struct arm_cpu_option_table
* opt
;
21156 char * ext
= strchr (str
, '+');
21160 optlen
= ext
- str
;
21162 optlen
= strlen (str
);
21166 as_bad (_("missing cpu name `%s'"), str
);
21170 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
21171 if (strncmp (opt
->name
, str
, optlen
) == 0)
21173 mcpu_cpu_opt
= &opt
->value
;
21174 mcpu_fpu_opt
= &opt
->default_fpu
;
21175 if (opt
->canonical_name
)
21176 strcpy (selected_cpu_name
, opt
->canonical_name
);
21180 for (i
= 0; i
< optlen
; i
++)
21181 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
21182 selected_cpu_name
[i
] = 0;
21186 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
21191 as_bad (_("unknown cpu `%s'"), str
);
21196 arm_parse_arch (char * str
)
21198 const struct arm_arch_option_table
*opt
;
21199 char *ext
= strchr (str
, '+');
21203 optlen
= ext
- str
;
21205 optlen
= strlen (str
);
21209 as_bad (_("missing architecture name `%s'"), str
);
21213 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
21214 if (streq (opt
->name
, str
))
21216 march_cpu_opt
= &opt
->value
;
21217 march_fpu_opt
= &opt
->default_fpu
;
21218 strcpy (selected_cpu_name
, opt
->name
);
21221 return arm_parse_extension (ext
, &march_cpu_opt
);
21226 as_bad (_("unknown architecture `%s'\n"), str
);
21231 arm_parse_fpu (char * str
)
21233 const struct arm_option_cpu_value_table
* opt
;
21235 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
21236 if (streq (opt
->name
, str
))
21238 mfpu_opt
= &opt
->value
;
21242 as_bad (_("unknown floating point format `%s'\n"), str
);
21247 arm_parse_float_abi (char * str
)
21249 const struct arm_option_value_table
* opt
;
21251 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
21252 if (streq (opt
->name
, str
))
21254 mfloat_abi_opt
= opt
->value
;
21258 as_bad (_("unknown floating point abi `%s'\n"), str
);
21264 arm_parse_eabi (char * str
)
21266 const struct arm_option_value_table
*opt
;
21268 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
21269 if (streq (opt
->name
, str
))
21271 meabi_flags
= opt
->value
;
21274 as_bad (_("unknown EABI `%s'\n"), str
);
21279 struct arm_long_option_table arm_long_opts
[] =
21281 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
21282 arm_parse_cpu
, NULL
},
21283 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
21284 arm_parse_arch
, NULL
},
21285 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
21286 arm_parse_fpu
, NULL
},
21287 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
21288 arm_parse_float_abi
, NULL
},
21290 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
21291 arm_parse_eabi
, NULL
},
21293 {NULL
, NULL
, 0, NULL
}
21297 md_parse_option (int c
, char * arg
)
21299 struct arm_option_table
*opt
;
21300 const struct arm_legacy_option_table
*fopt
;
21301 struct arm_long_option_table
*lopt
;
21307 target_big_endian
= 1;
21313 target_big_endian
= 0;
21317 case OPTION_FIX_V4BX
:
21322 /* Listing option. Just ignore these, we don't support additional
21327 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
21329 if (c
== opt
->option
[0]
21330 && ((arg
== NULL
&& opt
->option
[1] == 0)
21331 || streq (arg
, opt
->option
+ 1)))
21333 /* If the option is deprecated, tell the user. */
21334 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
21335 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
21336 arg
? arg
: "", _(opt
->deprecated
));
21338 if (opt
->var
!= NULL
)
21339 *opt
->var
= opt
->value
;
21345 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
21347 if (c
== fopt
->option
[0]
21348 && ((arg
== NULL
&& fopt
->option
[1] == 0)
21349 || streq (arg
, fopt
->option
+ 1)))
21351 /* If the option is deprecated, tell the user. */
21352 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
21353 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
21354 arg
? arg
: "", _(fopt
->deprecated
));
21356 if (fopt
->var
!= NULL
)
21357 *fopt
->var
= &fopt
->value
;
21363 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
21365 /* These options are expected to have an argument. */
21366 if (c
== lopt
->option
[0]
21368 && strncmp (arg
, lopt
->option
+ 1,
21369 strlen (lopt
->option
+ 1)) == 0)
21371 /* If the option is deprecated, tell the user. */
21372 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
21373 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
21374 _(lopt
->deprecated
));
21376 /* Call the sup-option parser. */
21377 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
21388 md_show_usage (FILE * fp
)
21390 struct arm_option_table
*opt
;
21391 struct arm_long_option_table
*lopt
;
21393 fprintf (fp
, _(" ARM-specific assembler options:\n"));
21395 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
21396 if (opt
->help
!= NULL
)
21397 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
21399 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
21400 if (lopt
->help
!= NULL
)
21401 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
21405 -EB assemble code for a big-endian cpu\n"));
21410 -EL assemble code for a little-endian cpu\n"));
21414 --fix-v4bx Allow BX in ARMv4 code\n"));
21422 arm_feature_set flags
;
21423 } cpu_arch_ver_table
;
21425 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
21426 least features first. */
21427 static const cpu_arch_ver_table cpu_arch_ver
[] =
21433 {4, ARM_ARCH_V5TE
},
21434 {5, ARM_ARCH_V5TEJ
},
21438 {11, ARM_ARCH_V6M
},
21439 {8, ARM_ARCH_V6T2
},
21440 {10, ARM_ARCH_V7A
},
21441 {10, ARM_ARCH_V7R
},
21442 {10, ARM_ARCH_V7M
},
21446 /* Set an attribute if it has not already been set by the user. */
21448 aeabi_set_attribute_int (int tag
, int value
)
21451 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
21452 || !attributes_set_explicitly
[tag
])
21453 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
21457 aeabi_set_attribute_string (int tag
, const char *value
)
21460 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
21461 || !attributes_set_explicitly
[tag
])
21462 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
21465 /* Set the public EABI object attributes. */
21467 aeabi_set_public_attributes (void)
21470 arm_feature_set flags
;
21471 arm_feature_set tmp
;
21472 const cpu_arch_ver_table
*p
;
21474 /* Choose the architecture based on the capabilities of the requested cpu
21475 (if any) and/or the instructions actually used. */
21476 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
21477 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
21478 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
21479 /*Allow the user to override the reported architecture. */
21482 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
21483 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
21488 for (p
= cpu_arch_ver
; p
->val
; p
++)
21490 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
21493 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
21497 /* Tag_CPU_name. */
21498 if (selected_cpu_name
[0])
21502 p
= selected_cpu_name
;
21503 if (strncmp (p
, "armv", 4) == 0)
21508 for (i
= 0; p
[i
]; i
++)
21509 p
[i
] = TOUPPER (p
[i
]);
21511 aeabi_set_attribute_string (Tag_CPU_name
, p
);
21513 /* Tag_CPU_arch. */
21514 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
21515 /* Tag_CPU_arch_profile. */
21516 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
21517 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
21518 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
21519 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
21520 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
21521 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
21522 /* Tag_ARM_ISA_use. */
21523 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
21525 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
21526 /* Tag_THUMB_ISA_use. */
21527 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
21529 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
21530 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
21531 /* Tag_VFP_arch. */
21532 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
21533 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
21534 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3
))
21535 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
21536 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
21537 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
21538 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
21539 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
21540 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
21541 /* Tag_WMMX_arch. */
21542 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
21543 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
21544 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
21545 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
21546 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
21547 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
21548 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
21549 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
21550 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_fp16
))
21551 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
21554 /* Add the default contents for the .ARM.attributes section. */
21558 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21561 aeabi_set_public_attributes ();
21563 #endif /* OBJ_ELF */
21566 /* Parse a .cpu directive. */
21569 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
21571 const struct arm_cpu_option_table
*opt
;
21575 name
= input_line_pointer
;
21576 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
21577 input_line_pointer
++;
21578 saved_char
= *input_line_pointer
;
21579 *input_line_pointer
= 0;
21581 /* Skip the first "all" entry. */
21582 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
21583 if (streq (opt
->name
, name
))
21585 mcpu_cpu_opt
= &opt
->value
;
21586 selected_cpu
= opt
->value
;
21587 if (opt
->canonical_name
)
21588 strcpy (selected_cpu_name
, opt
->canonical_name
);
21592 for (i
= 0; opt
->name
[i
]; i
++)
21593 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
21594 selected_cpu_name
[i
] = 0;
21596 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21597 *input_line_pointer
= saved_char
;
21598 demand_empty_rest_of_line ();
21601 as_bad (_("unknown cpu `%s'"), name
);
21602 *input_line_pointer
= saved_char
;
21603 ignore_rest_of_line ();
21607 /* Parse a .arch directive. */
21610 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
21612 const struct arm_arch_option_table
*opt
;
21616 name
= input_line_pointer
;
21617 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
21618 input_line_pointer
++;
21619 saved_char
= *input_line_pointer
;
21620 *input_line_pointer
= 0;
21622 /* Skip the first "all" entry. */
21623 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
21624 if (streq (opt
->name
, name
))
21626 mcpu_cpu_opt
= &opt
->value
;
21627 selected_cpu
= opt
->value
;
21628 strcpy (selected_cpu_name
, opt
->name
);
21629 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21630 *input_line_pointer
= saved_char
;
21631 demand_empty_rest_of_line ();
21635 as_bad (_("unknown architecture `%s'\n"), name
);
21636 *input_line_pointer
= saved_char
;
21637 ignore_rest_of_line ();
21641 /* Parse a .object_arch directive. */
21644 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
21646 const struct arm_arch_option_table
*opt
;
21650 name
= input_line_pointer
;
21651 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
21652 input_line_pointer
++;
21653 saved_char
= *input_line_pointer
;
21654 *input_line_pointer
= 0;
21656 /* Skip the first "all" entry. */
21657 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
21658 if (streq (opt
->name
, name
))
21660 object_arch
= &opt
->value
;
21661 *input_line_pointer
= saved_char
;
21662 demand_empty_rest_of_line ();
21666 as_bad (_("unknown architecture `%s'\n"), name
);
21667 *input_line_pointer
= saved_char
;
21668 ignore_rest_of_line ();
21671 /* Parse a .fpu directive. */
21674 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
21676 const struct arm_option_cpu_value_table
*opt
;
21680 name
= input_line_pointer
;
21681 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
21682 input_line_pointer
++;
21683 saved_char
= *input_line_pointer
;
21684 *input_line_pointer
= 0;
21686 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
21687 if (streq (opt
->name
, name
))
21689 mfpu_opt
= &opt
->value
;
21690 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21691 *input_line_pointer
= saved_char
;
21692 demand_empty_rest_of_line ();
21696 as_bad (_("unknown floating point format `%s'\n"), name
);
21697 *input_line_pointer
= saved_char
;
21698 ignore_rest_of_line ();
21701 /* Copy symbol information. */
21704 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
21706 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
21710 /* Given a symbolic attribute NAME, return the proper integer value.
21711 Returns -1 if the attribute is not known. */
21714 arm_convert_symbolic_attribute (const char *name
)
21716 static const struct
21721 attribute_table
[] =
21723 /* When you modify this table you should
21724 also modify the list in doc/c-arm.texi. */
21725 #define T(tag) {#tag, tag}
21726 T (Tag_CPU_raw_name
),
21729 T (Tag_CPU_arch_profile
),
21730 T (Tag_ARM_ISA_use
),
21731 T (Tag_THUMB_ISA_use
),
21734 T (Tag_Advanced_SIMD_arch
),
21735 T (Tag_PCS_config
),
21736 T (Tag_ABI_PCS_R9_use
),
21737 T (Tag_ABI_PCS_RW_data
),
21738 T (Tag_ABI_PCS_RO_data
),
21739 T (Tag_ABI_PCS_GOT_use
),
21740 T (Tag_ABI_PCS_wchar_t
),
21741 T (Tag_ABI_FP_rounding
),
21742 T (Tag_ABI_FP_denormal
),
21743 T (Tag_ABI_FP_exceptions
),
21744 T (Tag_ABI_FP_user_exceptions
),
21745 T (Tag_ABI_FP_number_model
),
21746 T (Tag_ABI_align8_needed
),
21747 T (Tag_ABI_align8_preserved
),
21748 T (Tag_ABI_enum_size
),
21749 T (Tag_ABI_HardFP_use
),
21750 T (Tag_ABI_VFP_args
),
21751 T (Tag_ABI_WMMX_args
),
21752 T (Tag_ABI_optimization_goals
),
21753 T (Tag_ABI_FP_optimization_goals
),
21754 T (Tag_compatibility
),
21755 T (Tag_CPU_unaligned_access
),
21756 T (Tag_VFP_HP_extension
),
21757 T (Tag_ABI_FP_16bit_format
),
21758 T (Tag_nodefaults
),
21759 T (Tag_also_compatible_with
),
21760 T (Tag_conformance
),
21762 T (Tag_Virtualization_use
),
21763 T (Tag_MPextension_use
)
21771 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
21772 if (strcmp (name
, attribute_table
[i
].name
) == 0)
21773 return attribute_table
[i
].tag
;
21779 /* Apply sym value for relocations only in the case that
21780 they are for local symbols and you have the respective
21781 architectural feature for blx and simple switches. */
21783 arm_apply_sym_value (struct fix
* fixP
)
21786 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
21787 && !S_IS_EXTERNAL (fixP
->fx_addsy
))
21789 switch (fixP
->fx_r_type
)
21791 case BFD_RELOC_ARM_PCREL_BLX
:
21792 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21793 if (ARM_IS_FUNC (fixP
->fx_addsy
))
21797 case BFD_RELOC_ARM_PCREL_CALL
:
21798 case BFD_RELOC_THUMB_PCREL_BLX
:
21799 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
21810 #endif /* OBJ_ELF */