1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2018 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 static const arm_feature_set arm_ext_v6_notm
=
208 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
209 static const arm_feature_set arm_ext_v6_dsp
=
210 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
211 static const arm_feature_set arm_ext_barrier
=
212 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
213 static const arm_feature_set arm_ext_msr
=
214 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
215 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
216 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
217 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
218 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
220 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
222 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
223 static const arm_feature_set arm_ext_m
=
224 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
225 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
226 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
227 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
228 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
229 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
230 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
231 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
232 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
233 static const arm_feature_set arm_ext_v8m_main
=
234 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
235 /* Instructions in ARMv8-M only found in M profile architectures. */
236 static const arm_feature_set arm_ext_v8m_m_only
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v6t2_v8m
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
240 /* Instructions shared between ARMv8-A and ARMv8-M. */
241 static const arm_feature_set arm_ext_atomics
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
244 /* DSP instructions Tag_DSP_extension refers to. */
245 static const arm_feature_set arm_ext_dsp
=
246 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
248 static const arm_feature_set arm_ext_ras
=
249 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
250 /* FP16 instructions. */
251 static const arm_feature_set arm_ext_fp16
=
252 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
253 static const arm_feature_set arm_ext_fp16_fml
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
255 static const arm_feature_set arm_ext_v8_2
=
256 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
257 static const arm_feature_set arm_ext_v8_3
=
258 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
260 static const arm_feature_set arm_arch_any
= ARM_ANY
;
262 static const arm_feature_set fpu_any
= FPU_ANY
;
264 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
265 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
266 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
268 static const arm_feature_set arm_cext_iwmmxt2
=
269 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
270 static const arm_feature_set arm_cext_iwmmxt
=
271 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
272 static const arm_feature_set arm_cext_xscale
=
273 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
274 static const arm_feature_set arm_cext_maverick
=
275 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
276 static const arm_feature_set fpu_fpa_ext_v1
=
277 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
278 static const arm_feature_set fpu_fpa_ext_v2
=
279 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
280 static const arm_feature_set fpu_vfp_ext_v1xd
=
281 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
282 static const arm_feature_set fpu_vfp_ext_v1
=
283 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
284 static const arm_feature_set fpu_vfp_ext_v2
=
285 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
286 static const arm_feature_set fpu_vfp_ext_v3xd
=
287 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
288 static const arm_feature_set fpu_vfp_ext_v3
=
289 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
290 static const arm_feature_set fpu_vfp_ext_d32
=
291 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
292 static const arm_feature_set fpu_neon_ext_v1
=
293 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
294 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
295 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
297 static const arm_feature_set fpu_vfp_fp16
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
299 static const arm_feature_set fpu_neon_ext_fma
=
300 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
302 static const arm_feature_set fpu_vfp_ext_fma
=
303 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
304 static const arm_feature_set fpu_vfp_ext_armv8
=
305 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
306 static const arm_feature_set fpu_vfp_ext_armv8xd
=
307 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
308 static const arm_feature_set fpu_neon_ext_armv8
=
309 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
310 static const arm_feature_set fpu_crypto_ext_armv8
=
311 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
312 static const arm_feature_set crc_ext_armv8
=
313 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
314 static const arm_feature_set fpu_neon_ext_v8_1
=
315 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
316 static const arm_feature_set fpu_neon_ext_dotprod
=
317 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
319 static int mfloat_abi_opt
= -1;
320 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
322 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
323 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
325 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
326 /* Feature bits selected by the last -mcpu/-march or by the combination of the
327 last .cpu/.arch directive .arch_extension directives since that
329 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
330 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
331 static arm_feature_set selected_fpu
= FPU_NONE
;
332 /* Feature bits selected by the last .object_arch directive. */
333 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
334 /* Must be long enough to hold any of the names in arm_cpus. */
335 static char selected_cpu_name
[20];
337 extern FLONUM_TYPE generic_floating_point_number
;
339 /* Return if no cpu was selected on command-line. */
341 no_cpu_selected (void)
343 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
348 static int meabi_flags
= EABI_DEFAULT
;
350 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
353 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
358 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
363 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
364 symbolS
* GOT_symbol
;
367 /* 0: assemble for ARM,
368 1: assemble for Thumb,
369 2: assemble for Thumb even though target CPU does not support thumb
371 static int thumb_mode
= 0;
372 /* A value distinct from the possible values for thumb_mode that we
373 can use to record whether thumb_mode has been copied into the
374 tc_frag_data field of a frag. */
375 #define MODE_RECORDED (1 << 4)
377 /* Specifies the intrinsic IT insn behavior mode. */
378 enum implicit_it_mode
380 IMPLICIT_IT_MODE_NEVER
= 0x00,
381 IMPLICIT_IT_MODE_ARM
= 0x01,
382 IMPLICIT_IT_MODE_THUMB
= 0x02,
383 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
385 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
387 /* If unified_syntax is true, we are processing the new unified
388 ARM/Thumb syntax. Important differences from the old ARM mode:
390 - Immediate operands do not require a # prefix.
391 - Conditional affixes always appear at the end of the
392 instruction. (For backward compatibility, those instructions
393 that formerly had them in the middle, continue to accept them
395 - The IT instruction may appear, and if it does is validated
396 against subsequent conditional affixes. It does not generate
399 Important differences from the old Thumb mode:
401 - Immediate operands do not require a # prefix.
402 - Most of the V6T2 instructions are only available in unified mode.
403 - The .N and .W suffixes are recognized and honored (it is an error
404 if they cannot be honored).
405 - All instructions set the flags if and only if they have an 's' affix.
406 - Conditional affixes may be used. They are validated against
407 preceding IT instructions. Unlike ARM mode, you cannot use a
408 conditional affix except in the scope of an IT instruction. */
410 static bfd_boolean unified_syntax
= FALSE
;
412 /* An immediate operand can start with #, and ld*, st*, pld operands
413 can contain [ and ]. We need to tell APP not to elide whitespace
414 before a [, which can appear as the first operand for pld.
415 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
416 const char arm_symbol_chars
[] = "#[]{}";
431 enum neon_el_type type
;
435 #define NEON_MAX_TYPE_ELS 4
439 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
443 enum it_instruction_type
448 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
449 if inside, should be the last one. */
450 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
451 i.e. BKPT and NOP. */
452 IT_INSN
/* The IT insn has been parsed. */
455 /* The maximum number of operands we need. */
456 #define ARM_IT_MAX_OPERANDS 6
461 unsigned long instruction
;
465 /* "uncond_value" is set to the value in place of the conditional field in
466 unconditional versions of the instruction, or -1 if nothing is
469 struct neon_type vectype
;
470 /* This does not indicate an actual NEON instruction, only that
471 the mnemonic accepts neon-style type suffixes. */
473 /* Set to the opcode if the instruction needs relaxation.
474 Zero if the instruction is not relaxed. */
478 bfd_reloc_code_real_type type
;
483 enum it_instruction_type it_insn_type
;
489 struct neon_type_el vectype
;
490 unsigned present
: 1; /* Operand present. */
491 unsigned isreg
: 1; /* Operand was a register. */
492 unsigned immisreg
: 1; /* .imm field is a second register. */
493 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
494 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
495 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
496 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
497 instructions. This allows us to disambiguate ARM <-> vector insns. */
498 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
499 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
500 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
501 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
502 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
503 unsigned writeback
: 1; /* Operand has trailing ! */
504 unsigned preind
: 1; /* Preindexed address. */
505 unsigned postind
: 1; /* Postindexed address. */
506 unsigned negative
: 1; /* Index register was negated. */
507 unsigned shifted
: 1; /* Shift applied to operation. */
508 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
509 } operands
[ARM_IT_MAX_OPERANDS
];
512 static struct arm_it inst
;
514 #define NUM_FLOAT_VALS 8
516 const char * fp_const
[] =
518 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
521 /* Number of littlenums required to hold an extended precision number. */
522 #define MAX_LITTLENUMS 6
524 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
534 #define CP_T_X 0x00008000
535 #define CP_T_Y 0x00400000
537 #define CONDS_BIT 0x00100000
538 #define LOAD_BIT 0x00100000
540 #define DOUBLE_LOAD_FLAG 0x00000001
544 const char * template_name
;
548 #define COND_ALWAYS 0xE
552 const char * template_name
;
556 struct asm_barrier_opt
558 const char * template_name
;
560 const arm_feature_set arch
;
563 /* The bit that distinguishes CPSR and SPSR. */
564 #define SPSR_BIT (1 << 22)
566 /* The individual PSR flag bits. */
567 #define PSR_c (1 << 16)
568 #define PSR_x (1 << 17)
569 #define PSR_s (1 << 18)
570 #define PSR_f (1 << 19)
575 bfd_reloc_code_real_type reloc
;
580 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
581 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
586 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
589 /* Bits for DEFINED field in neon_typed_alias. */
590 #define NTA_HASTYPE 1
591 #define NTA_HASINDEX 2
593 struct neon_typed_alias
595 unsigned char defined
;
597 struct neon_type_el eltype
;
600 /* ARM register categories. This includes coprocessor numbers and various
601 architecture extensions' registers. Each entry should have an error message
602 in reg_expected_msgs below. */
630 /* Structure for a hash table entry for a register.
631 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
632 information which states whether a vector type or index is specified (for a
633 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
639 unsigned char builtin
;
640 struct neon_typed_alias
* neon
;
643 /* Diagnostics used when we don't get a register of the expected type. */
644 const char * const reg_expected_msgs
[] =
646 [REG_TYPE_RN
] = N_("ARM register expected"),
647 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
648 [REG_TYPE_CN
] = N_("co-processor register expected"),
649 [REG_TYPE_FN
] = N_("FPA register expected"),
650 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
651 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
652 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
653 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
654 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
655 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
656 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
658 [REG_TYPE_VFC
] = N_("VFP system register expected"),
659 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
660 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
661 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
662 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
663 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
664 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
665 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
666 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
667 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
668 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
669 [REG_TYPE_RNB
] = N_("")
672 /* Some well known registers that we refer to directly elsewhere. */
678 /* ARM instructions take 4bytes in the object file, Thumb instructions
684 /* Basic string to match. */
685 const char * template_name
;
687 /* Parameters to instruction. */
688 unsigned int operands
[8];
690 /* Conditional tag - see opcode_lookup. */
691 unsigned int tag
: 4;
693 /* Basic instruction code. */
694 unsigned int avalue
: 28;
696 /* Thumb-format instruction code. */
699 /* Which architecture variant provides this instruction. */
700 const arm_feature_set
* avariant
;
701 const arm_feature_set
* tvariant
;
703 /* Function to call to encode instruction in ARM format. */
704 void (* aencode
) (void);
706 /* Function to call to encode instruction in Thumb format. */
707 void (* tencode
) (void);
710 /* Defines for various bits that we will want to toggle. */
711 #define INST_IMMEDIATE 0x02000000
712 #define OFFSET_REG 0x02000000
713 #define HWOFFSET_IMM 0x00400000
714 #define SHIFT_BY_REG 0x00000010
715 #define PRE_INDEX 0x01000000
716 #define INDEX_UP 0x00800000
717 #define WRITE_BACK 0x00200000
718 #define LDM_TYPE_2_OR_3 0x00400000
719 #define CPSI_MMOD 0x00020000
721 #define LITERAL_MASK 0xf000f000
722 #define OPCODE_MASK 0xfe1fffff
723 #define V4_STR_BIT 0x00000020
724 #define VLDR_VMOV_SAME 0x0040f000
726 #define T2_SUBS_PC_LR 0xf3de8f00
728 #define DATA_OP_SHIFT 21
729 #define SBIT_SHIFT 20
731 #define T2_OPCODE_MASK 0xfe1fffff
732 #define T2_DATA_OP_SHIFT 21
733 #define T2_SBIT_SHIFT 20
735 #define A_COND_MASK 0xf0000000
736 #define A_PUSH_POP_OP_MASK 0x0fff0000
738 /* Opcodes for pushing/poping registers to/from the stack. */
739 #define A1_OPCODE_PUSH 0x092d0000
740 #define A2_OPCODE_PUSH 0x052d0004
741 #define A2_OPCODE_POP 0x049d0004
743 /* Codes to distinguish the arithmetic instructions. */
754 #define OPCODE_CMP 10
755 #define OPCODE_CMN 11
756 #define OPCODE_ORR 12
757 #define OPCODE_MOV 13
758 #define OPCODE_BIC 14
759 #define OPCODE_MVN 15
761 #define T2_OPCODE_AND 0
762 #define T2_OPCODE_BIC 1
763 #define T2_OPCODE_ORR 2
764 #define T2_OPCODE_ORN 3
765 #define T2_OPCODE_EOR 4
766 #define T2_OPCODE_ADD 8
767 #define T2_OPCODE_ADC 10
768 #define T2_OPCODE_SBC 11
769 #define T2_OPCODE_SUB 13
770 #define T2_OPCODE_RSB 14
772 #define T_OPCODE_MUL 0x4340
773 #define T_OPCODE_TST 0x4200
774 #define T_OPCODE_CMN 0x42c0
775 #define T_OPCODE_NEG 0x4240
776 #define T_OPCODE_MVN 0x43c0
778 #define T_OPCODE_ADD_R3 0x1800
779 #define T_OPCODE_SUB_R3 0x1a00
780 #define T_OPCODE_ADD_HI 0x4400
781 #define T_OPCODE_ADD_ST 0xb000
782 #define T_OPCODE_SUB_ST 0xb080
783 #define T_OPCODE_ADD_SP 0xa800
784 #define T_OPCODE_ADD_PC 0xa000
785 #define T_OPCODE_ADD_I8 0x3000
786 #define T_OPCODE_SUB_I8 0x3800
787 #define T_OPCODE_ADD_I3 0x1c00
788 #define T_OPCODE_SUB_I3 0x1e00
790 #define T_OPCODE_ASR_R 0x4100
791 #define T_OPCODE_LSL_R 0x4080
792 #define T_OPCODE_LSR_R 0x40c0
793 #define T_OPCODE_ROR_R 0x41c0
794 #define T_OPCODE_ASR_I 0x1000
795 #define T_OPCODE_LSL_I 0x0000
796 #define T_OPCODE_LSR_I 0x0800
798 #define T_OPCODE_MOV_I8 0x2000
799 #define T_OPCODE_CMP_I8 0x2800
800 #define T_OPCODE_CMP_LR 0x4280
801 #define T_OPCODE_MOV_HR 0x4600
802 #define T_OPCODE_CMP_HR 0x4500
804 #define T_OPCODE_LDR_PC 0x4800
805 #define T_OPCODE_LDR_SP 0x9800
806 #define T_OPCODE_STR_SP 0x9000
807 #define T_OPCODE_LDR_IW 0x6800
808 #define T_OPCODE_STR_IW 0x6000
809 #define T_OPCODE_LDR_IH 0x8800
810 #define T_OPCODE_STR_IH 0x8000
811 #define T_OPCODE_LDR_IB 0x7800
812 #define T_OPCODE_STR_IB 0x7000
813 #define T_OPCODE_LDR_RW 0x5800
814 #define T_OPCODE_STR_RW 0x5000
815 #define T_OPCODE_LDR_RH 0x5a00
816 #define T_OPCODE_STR_RH 0x5200
817 #define T_OPCODE_LDR_RB 0x5c00
818 #define T_OPCODE_STR_RB 0x5400
820 #define T_OPCODE_PUSH 0xb400
821 #define T_OPCODE_POP 0xbc00
823 #define T_OPCODE_BRANCH 0xe000
825 #define THUMB_SIZE 2 /* Size of thumb instruction. */
826 #define THUMB_PP_PC_LR 0x0100
827 #define THUMB_LOAD_BIT 0x0800
828 #define THUMB2_LOAD_BIT 0x00100000
830 #define BAD_ARGS _("bad arguments to instruction")
831 #define BAD_SP _("r13 not allowed here")
832 #define BAD_PC _("r15 not allowed here")
833 #define BAD_COND _("instruction cannot be conditional")
834 #define BAD_OVERLAP _("registers may not be the same")
835 #define BAD_HIREG _("lo register required")
836 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
837 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
838 #define BAD_BRANCH _("branch must be last instruction in IT block")
839 #define BAD_NOT_IT _("instruction not allowed in IT block")
840 #define BAD_FPU _("selected FPU does not support instruction")
841 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
842 #define BAD_IT_COND _("incorrect condition in IT block")
843 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
844 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
845 #define BAD_PC_ADDRESSING \
846 _("cannot use register index with PC-relative addressing")
847 #define BAD_PC_WRITEBACK \
848 _("cannot use writeback with PC-relative addressing")
849 #define BAD_RANGE _("branch out of range")
850 #define BAD_FP16 _("selected processor does not support fp16 instruction")
851 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
852 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
854 static struct hash_control
* arm_ops_hsh
;
855 static struct hash_control
* arm_cond_hsh
;
856 static struct hash_control
* arm_shift_hsh
;
857 static struct hash_control
* arm_psr_hsh
;
858 static struct hash_control
* arm_v7m_psr_hsh
;
859 static struct hash_control
* arm_reg_hsh
;
860 static struct hash_control
* arm_reloc_hsh
;
861 static struct hash_control
* arm_barrier_opt_hsh
;
863 /* Stuff needed to resolve the label ambiguity
872 symbolS
* last_label_seen
;
873 static int label_is_thumb_function_name
= FALSE
;
875 /* Literal pool structure. Held on a per-section
876 and per-sub-section basis. */
878 #define MAX_LITERAL_POOL_SIZE 1024
879 typedef struct literal_pool
881 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
882 unsigned int next_free_entry
;
888 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
890 struct literal_pool
* next
;
891 unsigned int alignment
;
894 /* Pointer to a linked list of literal pools. */
895 literal_pool
* list_of_pools
= NULL
;
897 typedef enum asmfunc_states
900 WAITING_ASMFUNC_NAME
,
904 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
907 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
909 static struct current_it now_it
;
913 now_it_compatible (int cond
)
915 return (cond
& ~1) == (now_it
.cc
& ~1);
919 conditional_insn (void)
921 return inst
.cond
!= COND_ALWAYS
;
924 static int in_it_block (void);
926 static int handle_it_state (void);
928 static void force_automatic_it_block_close (void);
930 static void it_fsm_post_encode (void);
932 #define set_it_insn_type(type) \
935 inst.it_insn_type = type; \
936 if (handle_it_state () == FAIL) \
941 #define set_it_insn_type_nonvoid(type, failret) \
944 inst.it_insn_type = type; \
945 if (handle_it_state () == FAIL) \
950 #define set_it_insn_type_last() \
953 if (inst.cond == COND_ALWAYS) \
954 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
956 set_it_insn_type (INSIDE_IT_LAST_INSN); \
962 /* This array holds the chars that always start a comment. If the
963 pre-processor is disabled, these aren't very useful. */
964 char arm_comment_chars
[] = "@";
966 /* This array holds the chars that only start a comment at the beginning of
967 a line. If the line seems to have the form '# 123 filename'
968 .line and .file directives will appear in the pre-processed output. */
969 /* Note that input_file.c hand checks for '#' at the beginning of the
970 first line of the input file. This is because the compiler outputs
971 #NO_APP at the beginning of its output. */
972 /* Also note that comments like this one will always work. */
973 const char line_comment_chars
[] = "#";
975 char arm_line_separator_chars
[] = ";";
977 /* Chars that can be used to separate mant
978 from exp in floating point numbers. */
979 const char EXP_CHARS
[] = "eE";
981 /* Chars that mean this number is a floating point constant. */
985 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
987 /* Prefix characters that indicate the start of an immediate
989 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
991 /* Separator character handling. */
993 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
996 skip_past_char (char ** str
, char c
)
998 /* PR gas/14987: Allow for whitespace before the expected character. */
999 skip_whitespace (*str
);
1010 #define skip_past_comma(str) skip_past_char (str, ',')
1012 /* Arithmetic expressions (possibly involving symbols). */
1014 /* Return TRUE if anything in the expression is a bignum. */
1017 walk_no_bignums (symbolS
* sp
)
1019 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1022 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1024 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1025 || (symbol_get_value_expression (sp
)->X_op_symbol
1026 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1032 static bfd_boolean in_my_get_expression
= FALSE
;
1034 /* Third argument to my_get_expression. */
1035 #define GE_NO_PREFIX 0
1036 #define GE_IMM_PREFIX 1
1037 #define GE_OPT_PREFIX 2
1038 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1039 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1040 #define GE_OPT_PREFIX_BIG 3
1043 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1047 /* In unified syntax, all prefixes are optional. */
1049 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1052 switch (prefix_mode
)
1054 case GE_NO_PREFIX
: break;
1056 if (!is_immediate_prefix (**str
))
1058 inst
.error
= _("immediate expression requires a # prefix");
1064 case GE_OPT_PREFIX_BIG
:
1065 if (is_immediate_prefix (**str
))
1072 memset (ep
, 0, sizeof (expressionS
));
1074 save_in
= input_line_pointer
;
1075 input_line_pointer
= *str
;
1076 in_my_get_expression
= TRUE
;
1078 in_my_get_expression
= FALSE
;
1080 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1082 /* We found a bad or missing expression in md_operand(). */
1083 *str
= input_line_pointer
;
1084 input_line_pointer
= save_in
;
1085 if (inst
.error
== NULL
)
1086 inst
.error
= (ep
->X_op
== O_absent
1087 ? _("missing expression") :_("bad expression"));
1091 /* Get rid of any bignums now, so that we don't generate an error for which
1092 we can't establish a line number later on. Big numbers are never valid
1093 in instructions, which is where this routine is always called. */
1094 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1095 && (ep
->X_op
== O_big
1096 || (ep
->X_add_symbol
1097 && (walk_no_bignums (ep
->X_add_symbol
)
1099 && walk_no_bignums (ep
->X_op_symbol
))))))
1101 inst
.error
= _("invalid constant");
1102 *str
= input_line_pointer
;
1103 input_line_pointer
= save_in
;
1107 *str
= input_line_pointer
;
1108 input_line_pointer
= save_in
;
1112 /* Turn a string in input_line_pointer into a floating point constant
1113 of type TYPE, and store the appropriate bytes in *LITP. The number
1114 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1115 returned, or NULL on OK.
1117 Note that fp constants aren't represent in the normal way on the ARM.
1118 In big endian mode, things are as expected. However, in little endian
1119 mode fp constants are big-endian word-wise, and little-endian byte-wise
1120 within the words. For example, (double) 1.1 in big endian mode is
1121 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1122 the byte sequence 99 99 f1 3f 9a 99 99 99.
1124 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1127 md_atof (int type
, char * litP
, int * sizeP
)
1130 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1162 return _("Unrecognized or unsupported floating point constant");
1165 t
= atof_ieee (input_line_pointer
, type
, words
);
1167 input_line_pointer
= t
;
1168 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1170 if (target_big_endian
)
1172 for (i
= 0; i
< prec
; i
++)
1174 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1175 litP
+= sizeof (LITTLENUM_TYPE
);
1180 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1181 for (i
= prec
- 1; i
>= 0; i
--)
1183 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1184 litP
+= sizeof (LITTLENUM_TYPE
);
1187 /* For a 4 byte float the order of elements in `words' is 1 0.
1188 For an 8 byte float the order is 1 0 3 2. */
1189 for (i
= 0; i
< prec
; i
+= 2)
1191 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1192 sizeof (LITTLENUM_TYPE
));
1193 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1194 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1195 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1202 /* We handle all bad expressions here, so that we can report the faulty
1203 instruction in the error message. */
1206 md_operand (expressionS
* exp
)
1208 if (in_my_get_expression
)
1209 exp
->X_op
= O_illegal
;
1212 /* Immediate values. */
1215 /* Generic immediate-value read function for use in directives.
1216 Accepts anything that 'expression' can fold to a constant.
1217 *val receives the number. */
1220 immediate_for_directive (int *val
)
1223 exp
.X_op
= O_illegal
;
1225 if (is_immediate_prefix (*input_line_pointer
))
1227 input_line_pointer
++;
1231 if (exp
.X_op
!= O_constant
)
1233 as_bad (_("expected #constant"));
1234 ignore_rest_of_line ();
1237 *val
= exp
.X_add_number
;
1242 /* Register parsing. */
1244 /* Generic register parser. CCP points to what should be the
1245 beginning of a register name. If it is indeed a valid register
1246 name, advance CCP over it and return the reg_entry structure;
1247 otherwise return NULL. Does not issue diagnostics. */
1249 static struct reg_entry
*
1250 arm_reg_parse_multi (char **ccp
)
1254 struct reg_entry
*reg
;
1256 skip_whitespace (start
);
1258 #ifdef REGISTER_PREFIX
1259 if (*start
!= REGISTER_PREFIX
)
1263 #ifdef OPTIONAL_REGISTER_PREFIX
1264 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1269 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1274 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1276 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1286 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1287 enum arm_reg_type type
)
1289 /* Alternative syntaxes are accepted for a few register classes. */
1296 /* Generic coprocessor register names are allowed for these. */
1297 if (reg
&& reg
->type
== REG_TYPE_CN
)
1302 /* For backward compatibility, a bare number is valid here. */
1304 unsigned long processor
= strtoul (start
, ccp
, 10);
1305 if (*ccp
!= start
&& processor
<= 15)
1310 case REG_TYPE_MMXWC
:
1311 /* WC includes WCG. ??? I'm not sure this is true for all
1312 instructions that take WC registers. */
1313 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1324 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1325 return value is the register number or FAIL. */
1328 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1331 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1334 /* Do not allow a scalar (reg+index) to parse as a register. */
1335 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1338 if (reg
&& reg
->type
== type
)
1341 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1348 /* Parse a Neon type specifier. *STR should point at the leading '.'
1349 character. Does no verification at this stage that the type fits the opcode
1356 Can all be legally parsed by this function.
1358 Fills in neon_type struct pointer with parsed information, and updates STR
1359 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1360 type, FAIL if not. */
1363 parse_neon_type (struct neon_type
*type
, char **str
)
1370 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1372 enum neon_el_type thistype
= NT_untyped
;
1373 unsigned thissize
= -1u;
1380 /* Just a size without an explicit type. */
1384 switch (TOLOWER (*ptr
))
1386 case 'i': thistype
= NT_integer
; break;
1387 case 'f': thistype
= NT_float
; break;
1388 case 'p': thistype
= NT_poly
; break;
1389 case 's': thistype
= NT_signed
; break;
1390 case 'u': thistype
= NT_unsigned
; break;
1392 thistype
= NT_float
;
1397 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1403 /* .f is an abbreviation for .f32. */
1404 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1409 thissize
= strtoul (ptr
, &ptr
, 10);
1411 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1414 as_bad (_("bad size %d in type specifier"), thissize
);
1422 type
->el
[type
->elems
].type
= thistype
;
1423 type
->el
[type
->elems
].size
= thissize
;
1428 /* Empty/missing type is not a successful parse. */
1429 if (type
->elems
== 0)
1437 /* Errors may be set multiple times during parsing or bit encoding
1438 (particularly in the Neon bits), but usually the earliest error which is set
1439 will be the most meaningful. Avoid overwriting it with later (cascading)
1440 errors by calling this function. */
1443 first_error (const char *err
)
1449 /* Parse a single type, e.g. ".s32", leading period included. */
1451 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1454 struct neon_type optype
;
1458 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1460 if (optype
.elems
== 1)
1461 *vectype
= optype
.el
[0];
1464 first_error (_("only one type should be specified for operand"));
1470 first_error (_("vector type expected"));
1482 /* Special meanings for indices (which have a range of 0-7), which will fit into
1485 #define NEON_ALL_LANES 15
1486 #define NEON_INTERLEAVE_LANES 14
1488 /* Parse either a register or a scalar, with an optional type. Return the
1489 register number, and optionally fill in the actual type of the register
1490 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1491 type/index information in *TYPEINFO. */
1494 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1495 enum arm_reg_type
*rtype
,
1496 struct neon_typed_alias
*typeinfo
)
1499 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1500 struct neon_typed_alias atype
;
1501 struct neon_type_el parsetype
;
1505 atype
.eltype
.type
= NT_invtype
;
1506 atype
.eltype
.size
= -1;
1508 /* Try alternate syntax for some types of register. Note these are mutually
1509 exclusive with the Neon syntax extensions. */
1512 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1520 /* Undo polymorphism when a set of register types may be accepted. */
1521 if ((type
== REG_TYPE_NDQ
1522 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1523 || (type
== REG_TYPE_VFSD
1524 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1525 || (type
== REG_TYPE_NSDQ
1526 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1527 || reg
->type
== REG_TYPE_NQ
))
1528 || (type
== REG_TYPE_NSD
1529 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1530 || (type
== REG_TYPE_MMXWC
1531 && (reg
->type
== REG_TYPE_MMXWCG
)))
1532 type
= (enum arm_reg_type
) reg
->type
;
1534 if (type
!= reg
->type
)
1540 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1542 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1544 first_error (_("can't redefine type for operand"));
1547 atype
.defined
|= NTA_HASTYPE
;
1548 atype
.eltype
= parsetype
;
1551 if (skip_past_char (&str
, '[') == SUCCESS
)
1553 if (type
!= REG_TYPE_VFD
1554 && !(type
== REG_TYPE_VFS
1555 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
)))
1557 first_error (_("only D registers may be indexed"));
1561 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1563 first_error (_("can't change index for operand"));
1567 atype
.defined
|= NTA_HASINDEX
;
1569 if (skip_past_char (&str
, ']') == SUCCESS
)
1570 atype
.index
= NEON_ALL_LANES
;
1575 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1577 if (exp
.X_op
!= O_constant
)
1579 first_error (_("constant expression required"));
1583 if (skip_past_char (&str
, ']') == FAIL
)
1586 atype
.index
= exp
.X_add_number
;
1601 /* Like arm_reg_parse, but allow allow the following extra features:
1602 - If RTYPE is non-zero, return the (possibly restricted) type of the
1603 register (e.g. Neon double or quad reg when either has been requested).
1604 - If this is a Neon vector type with additional type information, fill
1605 in the struct pointed to by VECTYPE (if non-NULL).
1606 This function will fault on encountering a scalar. */
1609 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1610 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1612 struct neon_typed_alias atype
;
1614 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1619 /* Do not allow regname(... to parse as a register. */
1623 /* Do not allow a scalar (reg+index) to parse as a register. */
1624 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1626 first_error (_("register operand expected, but got scalar"));
1631 *vectype
= atype
.eltype
;
1638 #define NEON_SCALAR_REG(X) ((X) >> 4)
1639 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1641 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1642 have enough information to be able to do a good job bounds-checking. So, we
1643 just do easy checks here, and do further checks later. */
1646 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1650 struct neon_typed_alias atype
;
1651 enum arm_reg_type reg_type
= REG_TYPE_VFD
;
1654 reg_type
= REG_TYPE_VFS
;
1656 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1658 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1661 if (atype
.index
== NEON_ALL_LANES
)
1663 first_error (_("scalar must have an index"));
1666 else if (atype
.index
>= 64 / elsize
)
1668 first_error (_("scalar index out of range"));
1673 *type
= atype
.eltype
;
1677 return reg
* 16 + atype
.index
;
1680 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1683 parse_reg_list (char ** strp
)
1685 char * str
= * strp
;
1689 /* We come back here if we get ranges concatenated by '+' or '|'. */
1692 skip_whitespace (str
);
1706 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1708 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1718 first_error (_("bad range in register list"));
1722 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1724 if (range
& (1 << i
))
1726 (_("Warning: duplicated register (r%d) in register list"),
1734 if (range
& (1 << reg
))
1735 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1737 else if (reg
<= cur_reg
)
1738 as_tsktsk (_("Warning: register range not in ascending order"));
1743 while (skip_past_comma (&str
) != FAIL
1744 || (in_range
= 1, *str
++ == '-'));
1747 if (skip_past_char (&str
, '}') == FAIL
)
1749 first_error (_("missing `}'"));
1757 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1760 if (exp
.X_op
== O_constant
)
1762 if (exp
.X_add_number
1763 != (exp
.X_add_number
& 0x0000ffff))
1765 inst
.error
= _("invalid register mask");
1769 if ((range
& exp
.X_add_number
) != 0)
1771 int regno
= range
& exp
.X_add_number
;
1774 regno
= (1 << regno
) - 1;
1776 (_("Warning: duplicated register (r%d) in register list"),
1780 range
|= exp
.X_add_number
;
1784 if (inst
.reloc
.type
!= 0)
1786 inst
.error
= _("expression too complex");
1790 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1791 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1792 inst
.reloc
.pc_rel
= 0;
1796 if (*str
== '|' || *str
== '+')
1802 while (another_range
);
1808 /* Types of registers in a list. */
1817 /* Parse a VFP register list. If the string is invalid return FAIL.
1818 Otherwise return the number of registers, and set PBASE to the first
1819 register. Parses registers of type ETYPE.
1820 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1821 - Q registers can be used to specify pairs of D registers
1822 - { } can be omitted from around a singleton register list
1823 FIXME: This is not implemented, as it would require backtracking in
1826 This could be done (the meaning isn't really ambiguous), but doesn't
1827 fit in well with the current parsing framework.
1828 - 32 D registers may be used (also true for VFPv3).
1829 FIXME: Types are ignored in these register lists, which is probably a
1833 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1838 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1842 unsigned long mask
= 0;
1845 if (skip_past_char (&str
, '{') == FAIL
)
1847 inst
.error
= _("expecting {");
1854 regtype
= REG_TYPE_VFS
;
1859 regtype
= REG_TYPE_VFD
;
1862 case REGLIST_NEON_D
:
1863 regtype
= REG_TYPE_NDQ
;
1867 if (etype
!= REGLIST_VFP_S
)
1869 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1870 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1874 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1877 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1884 base_reg
= max_regs
;
1888 int setmask
= 1, addregs
= 1;
1890 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1892 if (new_base
== FAIL
)
1894 first_error (_(reg_expected_msgs
[regtype
]));
1898 if (new_base
>= max_regs
)
1900 first_error (_("register out of range in list"));
1904 /* Note: a value of 2 * n is returned for the register Q<n>. */
1905 if (regtype
== REG_TYPE_NQ
)
1911 if (new_base
< base_reg
)
1912 base_reg
= new_base
;
1914 if (mask
& (setmask
<< new_base
))
1916 first_error (_("invalid register list"));
1920 if ((mask
>> new_base
) != 0 && ! warned
)
1922 as_tsktsk (_("register list not in ascending order"));
1926 mask
|= setmask
<< new_base
;
1929 if (*str
== '-') /* We have the start of a range expression */
1935 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1938 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1942 if (high_range
>= max_regs
)
1944 first_error (_("register out of range in list"));
1948 if (regtype
== REG_TYPE_NQ
)
1949 high_range
= high_range
+ 1;
1951 if (high_range
<= new_base
)
1953 inst
.error
= _("register range not in ascending order");
1957 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1959 if (mask
& (setmask
<< new_base
))
1961 inst
.error
= _("invalid register list");
1965 mask
|= setmask
<< new_base
;
1970 while (skip_past_comma (&str
) != FAIL
);
1974 /* Sanity check -- should have raised a parse error above. */
1975 if (count
== 0 || count
> max_regs
)
1980 /* Final test -- the registers must be consecutive. */
1982 for (i
= 0; i
< count
; i
++)
1984 if ((mask
& (1u << i
)) == 0)
1986 inst
.error
= _("non-contiguous register range");
1996 /* True if two alias types are the same. */
1999 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2007 if (a
->defined
!= b
->defined
)
2010 if ((a
->defined
& NTA_HASTYPE
) != 0
2011 && (a
->eltype
.type
!= b
->eltype
.type
2012 || a
->eltype
.size
!= b
->eltype
.size
))
2015 if ((a
->defined
& NTA_HASINDEX
) != 0
2016 && (a
->index
!= b
->index
))
2022 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2023 The base register is put in *PBASE.
2024 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2026 The register stride (minus one) is put in bit 4 of the return value.
2027 Bits [6:5] encode the list length (minus one).
2028 The type of the list elements is put in *ELTYPE, if non-NULL. */
2030 #define NEON_LANE(X) ((X) & 0xf)
2031 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2032 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2035 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2036 struct neon_type_el
*eltype
)
2043 int leading_brace
= 0;
2044 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2045 const char *const incr_error
= _("register stride must be 1 or 2");
2046 const char *const type_error
= _("mismatched element/structure types in list");
2047 struct neon_typed_alias firsttype
;
2048 firsttype
.defined
= 0;
2049 firsttype
.eltype
.type
= NT_invtype
;
2050 firsttype
.eltype
.size
= -1;
2051 firsttype
.index
= -1;
2053 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2058 struct neon_typed_alias atype
;
2059 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2063 first_error (_(reg_expected_msgs
[rtype
]));
2070 if (rtype
== REG_TYPE_NQ
)
2076 else if (reg_incr
== -1)
2078 reg_incr
= getreg
- base_reg
;
2079 if (reg_incr
< 1 || reg_incr
> 2)
2081 first_error (_(incr_error
));
2085 else if (getreg
!= base_reg
+ reg_incr
* count
)
2087 first_error (_(incr_error
));
2091 if (! neon_alias_types_same (&atype
, &firsttype
))
2093 first_error (_(type_error
));
2097 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2101 struct neon_typed_alias htype
;
2102 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2104 lane
= NEON_INTERLEAVE_LANES
;
2105 else if (lane
!= NEON_INTERLEAVE_LANES
)
2107 first_error (_(type_error
));
2112 else if (reg_incr
!= 1)
2114 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2118 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2121 first_error (_(reg_expected_msgs
[rtype
]));
2124 if (! neon_alias_types_same (&htype
, &firsttype
))
2126 first_error (_(type_error
));
2129 count
+= hireg
+ dregs
- getreg
;
2133 /* If we're using Q registers, we can't use [] or [n] syntax. */
2134 if (rtype
== REG_TYPE_NQ
)
2140 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2144 else if (lane
!= atype
.index
)
2146 first_error (_(type_error
));
2150 else if (lane
== -1)
2151 lane
= NEON_INTERLEAVE_LANES
;
2152 else if (lane
!= NEON_INTERLEAVE_LANES
)
2154 first_error (_(type_error
));
2159 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2161 /* No lane set by [x]. We must be interleaving structures. */
2163 lane
= NEON_INTERLEAVE_LANES
;
2166 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2167 || (count
> 1 && reg_incr
== -1))
2169 first_error (_("error parsing element/structure list"));
2173 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2175 first_error (_("expected }"));
2183 *eltype
= firsttype
.eltype
;
2188 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2191 /* Parse an explicit relocation suffix on an expression. This is
2192 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2193 arm_reloc_hsh contains no entries, so this function can only
2194 succeed if there is no () after the word. Returns -1 on error,
2195 BFD_RELOC_UNUSED if there wasn't any suffix. */
2198 parse_reloc (char **str
)
2200 struct reloc_entry
*r
;
2204 return BFD_RELOC_UNUSED
;
2209 while (*q
&& *q
!= ')' && *q
!= ',')
2214 if ((r
= (struct reloc_entry
*)
2215 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2222 /* Directives: register aliases. */
2224 static struct reg_entry
*
2225 insert_reg_alias (char *str
, unsigned number
, int type
)
2227 struct reg_entry
*new_reg
;
2230 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2232 if (new_reg
->builtin
)
2233 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2235 /* Only warn about a redefinition if it's not defined as the
2237 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2238 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2243 name
= xstrdup (str
);
2244 new_reg
= XNEW (struct reg_entry
);
2246 new_reg
->name
= name
;
2247 new_reg
->number
= number
;
2248 new_reg
->type
= type
;
2249 new_reg
->builtin
= FALSE
;
2250 new_reg
->neon
= NULL
;
2252 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2259 insert_neon_reg_alias (char *str
, int number
, int type
,
2260 struct neon_typed_alias
*atype
)
2262 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2266 first_error (_("attempt to redefine typed alias"));
2272 reg
->neon
= XNEW (struct neon_typed_alias
);
2273 *reg
->neon
= *atype
;
2277 /* Look for the .req directive. This is of the form:
2279 new_register_name .req existing_register_name
2281 If we find one, or if it looks sufficiently like one that we want to
2282 handle any error here, return TRUE. Otherwise return FALSE. */
2285 create_register_alias (char * newname
, char *p
)
2287 struct reg_entry
*old
;
2288 char *oldname
, *nbuf
;
2291 /* The input scrubber ensures that whitespace after the mnemonic is
2292 collapsed to single spaces. */
2294 if (strncmp (oldname
, " .req ", 6) != 0)
2298 if (*oldname
== '\0')
2301 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2304 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2308 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2309 the desired alias name, and p points to its end. If not, then
2310 the desired alias name is in the global original_case_string. */
2311 #ifdef TC_CASE_SENSITIVE
2314 newname
= original_case_string
;
2315 nlen
= strlen (newname
);
2318 nbuf
= xmemdup0 (newname
, nlen
);
2320 /* Create aliases under the new name as stated; an all-lowercase
2321 version of the new name; and an all-uppercase version of the new
2323 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2325 for (p
= nbuf
; *p
; p
++)
2328 if (strncmp (nbuf
, newname
, nlen
))
2330 /* If this attempt to create an additional alias fails, do not bother
2331 trying to create the all-lower case alias. We will fail and issue
2332 a second, duplicate error message. This situation arises when the
2333 programmer does something like:
2336 The second .req creates the "Foo" alias but then fails to create
2337 the artificial FOO alias because it has already been created by the
2339 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2346 for (p
= nbuf
; *p
; p
++)
2349 if (strncmp (nbuf
, newname
, nlen
))
2350 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2357 /* Create a Neon typed/indexed register alias using directives, e.g.:
2362 These typed registers can be used instead of the types specified after the
2363 Neon mnemonic, so long as all operands given have types. Types can also be
2364 specified directly, e.g.:
2365 vadd d0.s32, d1.s32, d2.s32 */
2368 create_neon_reg_alias (char *newname
, char *p
)
2370 enum arm_reg_type basetype
;
2371 struct reg_entry
*basereg
;
2372 struct reg_entry mybasereg
;
2373 struct neon_type ntype
;
2374 struct neon_typed_alias typeinfo
;
2375 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2378 typeinfo
.defined
= 0;
2379 typeinfo
.eltype
.type
= NT_invtype
;
2380 typeinfo
.eltype
.size
= -1;
2381 typeinfo
.index
= -1;
2385 if (strncmp (p
, " .dn ", 5) == 0)
2386 basetype
= REG_TYPE_VFD
;
2387 else if (strncmp (p
, " .qn ", 5) == 0)
2388 basetype
= REG_TYPE_NQ
;
2397 basereg
= arm_reg_parse_multi (&p
);
2399 if (basereg
&& basereg
->type
!= basetype
)
2401 as_bad (_("bad type for register"));
2405 if (basereg
== NULL
)
2408 /* Try parsing as an integer. */
2409 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2410 if (exp
.X_op
!= O_constant
)
2412 as_bad (_("expression must be constant"));
2415 basereg
= &mybasereg
;
2416 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2422 typeinfo
= *basereg
->neon
;
2424 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2426 /* We got a type. */
2427 if (typeinfo
.defined
& NTA_HASTYPE
)
2429 as_bad (_("can't redefine the type of a register alias"));
2433 typeinfo
.defined
|= NTA_HASTYPE
;
2434 if (ntype
.elems
!= 1)
2436 as_bad (_("you must specify a single type only"));
2439 typeinfo
.eltype
= ntype
.el
[0];
2442 if (skip_past_char (&p
, '[') == SUCCESS
)
2445 /* We got a scalar index. */
2447 if (typeinfo
.defined
& NTA_HASINDEX
)
2449 as_bad (_("can't redefine the index of a scalar alias"));
2453 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2455 if (exp
.X_op
!= O_constant
)
2457 as_bad (_("scalar index must be constant"));
2461 typeinfo
.defined
|= NTA_HASINDEX
;
2462 typeinfo
.index
= exp
.X_add_number
;
2464 if (skip_past_char (&p
, ']') == FAIL
)
2466 as_bad (_("expecting ]"));
2471 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2472 the desired alias name, and p points to its end. If not, then
2473 the desired alias name is in the global original_case_string. */
2474 #ifdef TC_CASE_SENSITIVE
2475 namelen
= nameend
- newname
;
2477 newname
= original_case_string
;
2478 namelen
= strlen (newname
);
2481 namebuf
= xmemdup0 (newname
, namelen
);
2483 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2484 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2486 /* Insert name in all uppercase. */
2487 for (p
= namebuf
; *p
; p
++)
2490 if (strncmp (namebuf
, newname
, namelen
))
2491 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2492 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2494 /* Insert name in all lowercase. */
2495 for (p
= namebuf
; *p
; p
++)
2498 if (strncmp (namebuf
, newname
, namelen
))
2499 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2500 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2506 /* Should never be called, as .req goes between the alias and the
2507 register name, not at the beginning of the line. */
2510 s_req (int a ATTRIBUTE_UNUSED
)
2512 as_bad (_("invalid syntax for .req directive"));
2516 s_dn (int a ATTRIBUTE_UNUSED
)
2518 as_bad (_("invalid syntax for .dn directive"));
2522 s_qn (int a ATTRIBUTE_UNUSED
)
2524 as_bad (_("invalid syntax for .qn directive"));
2527 /* The .unreq directive deletes an alias which was previously defined
2528 by .req. For example:
2534 s_unreq (int a ATTRIBUTE_UNUSED
)
2539 name
= input_line_pointer
;
2541 while (*input_line_pointer
!= 0
2542 && *input_line_pointer
!= ' '
2543 && *input_line_pointer
!= '\n')
2544 ++input_line_pointer
;
2546 saved_char
= *input_line_pointer
;
2547 *input_line_pointer
= 0;
2550 as_bad (_("invalid syntax for .unreq directive"));
2553 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2557 as_bad (_("unknown register alias '%s'"), name
);
2558 else if (reg
->builtin
)
2559 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2566 hash_delete (arm_reg_hsh
, name
, FALSE
);
2567 free ((char *) reg
->name
);
2572 /* Also locate the all upper case and all lower case versions.
2573 Do not complain if we cannot find one or the other as it
2574 was probably deleted above. */
2576 nbuf
= strdup (name
);
2577 for (p
= nbuf
; *p
; p
++)
2579 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2582 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2583 free ((char *) reg
->name
);
2589 for (p
= nbuf
; *p
; p
++)
2591 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2594 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2595 free ((char *) reg
->name
);
2605 *input_line_pointer
= saved_char
;
2606 demand_empty_rest_of_line ();
2609 /* Directives: Instruction set selection. */
2612 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2613 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2614 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2615 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2617 /* Create a new mapping symbol for the transition to STATE. */
2620 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2623 const char * symname
;
2630 type
= BSF_NO_FLAGS
;
2634 type
= BSF_NO_FLAGS
;
2638 type
= BSF_NO_FLAGS
;
2644 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2645 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2650 THUMB_SET_FUNC (symbolP
, 0);
2651 ARM_SET_THUMB (symbolP
, 0);
2652 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2656 THUMB_SET_FUNC (symbolP
, 1);
2657 ARM_SET_THUMB (symbolP
, 1);
2658 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2666 /* Save the mapping symbols for future reference. Also check that
2667 we do not place two mapping symbols at the same offset within a
2668 frag. We'll handle overlap between frags in
2669 check_mapping_symbols.
2671 If .fill or other data filling directive generates zero sized data,
2672 the mapping symbol for the following code will have the same value
2673 as the one generated for the data filling directive. In this case,
2674 we replace the old symbol with the new one at the same address. */
2677 if (frag
->tc_frag_data
.first_map
!= NULL
)
2679 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2680 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2682 frag
->tc_frag_data
.first_map
= symbolP
;
2684 if (frag
->tc_frag_data
.last_map
!= NULL
)
2686 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2687 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2688 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2690 frag
->tc_frag_data
.last_map
= symbolP
;
2693 /* We must sometimes convert a region marked as code to data during
2694 code alignment, if an odd number of bytes have to be padded. The
2695 code mapping symbol is pushed to an aligned address. */
2698 insert_data_mapping_symbol (enum mstate state
,
2699 valueT value
, fragS
*frag
, offsetT bytes
)
2701 /* If there was already a mapping symbol, remove it. */
2702 if (frag
->tc_frag_data
.last_map
!= NULL
2703 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2705 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2709 know (frag
->tc_frag_data
.first_map
== symp
);
2710 frag
->tc_frag_data
.first_map
= NULL
;
2712 frag
->tc_frag_data
.last_map
= NULL
;
2713 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2716 make_mapping_symbol (MAP_DATA
, value
, frag
);
2717 make_mapping_symbol (state
, value
+ bytes
, frag
);
2720 static void mapping_state_2 (enum mstate state
, int max_chars
);
2722 /* Set the mapping state to STATE. Only call this when about to
2723 emit some STATE bytes to the file. */
2725 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2727 mapping_state (enum mstate state
)
2729 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2731 if (mapstate
== state
)
2732 /* The mapping symbol has already been emitted.
2733 There is nothing else to do. */
2736 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2738 All ARM instructions require 4-byte alignment.
2739 (Almost) all Thumb instructions require 2-byte alignment.
2741 When emitting instructions into any section, mark the section
2744 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2745 but themselves require 2-byte alignment; this applies to some
2746 PC- relative forms. However, these cases will involve implicit
2747 literal pool generation or an explicit .align >=2, both of
2748 which will cause the section to me marked with sufficient
2749 alignment. Thus, we don't handle those cases here. */
2750 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2752 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2753 /* This case will be evaluated later. */
2756 mapping_state_2 (state
, 0);
2759 /* Same as mapping_state, but MAX_CHARS bytes have already been
2760 allocated. Put the mapping symbol that far back. */
2763 mapping_state_2 (enum mstate state
, int max_chars
)
2765 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2767 if (!SEG_NORMAL (now_seg
))
2770 if (mapstate
== state
)
2771 /* The mapping symbol has already been emitted.
2772 There is nothing else to do. */
2775 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2776 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2778 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2779 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2782 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2785 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2786 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2790 #define mapping_state(x) ((void)0)
2791 #define mapping_state_2(x, y) ((void)0)
2794 /* Find the real, Thumb encoded start of a Thumb function. */
2798 find_real_start (symbolS
* symbolP
)
2801 const char * name
= S_GET_NAME (symbolP
);
2802 symbolS
* new_target
;
2804 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2805 #define STUB_NAME ".real_start_of"
2810 /* The compiler may generate BL instructions to local labels because
2811 it needs to perform a branch to a far away location. These labels
2812 do not have a corresponding ".real_start_of" label. We check
2813 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2814 the ".real_start_of" convention for nonlocal branches. */
2815 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2818 real_start
= concat (STUB_NAME
, name
, NULL
);
2819 new_target
= symbol_find (real_start
);
2822 if (new_target
== NULL
)
2824 as_warn (_("Failed to find real start of function: %s\n"), name
);
2825 new_target
= symbolP
;
2833 opcode_select (int width
)
2840 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2841 as_bad (_("selected processor does not support THUMB opcodes"));
2844 /* No need to force the alignment, since we will have been
2845 coming from ARM mode, which is word-aligned. */
2846 record_alignment (now_seg
, 1);
2853 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2854 as_bad (_("selected processor does not support ARM opcodes"));
2859 frag_align (2, 0, 0);
2861 record_alignment (now_seg
, 1);
2866 as_bad (_("invalid instruction size selected (%d)"), width
);
2871 s_arm (int ignore ATTRIBUTE_UNUSED
)
2874 demand_empty_rest_of_line ();
2878 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2881 demand_empty_rest_of_line ();
2885 s_code (int unused ATTRIBUTE_UNUSED
)
2889 temp
= get_absolute_expression ();
2894 opcode_select (temp
);
2898 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2903 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2905 /* If we are not already in thumb mode go into it, EVEN if
2906 the target processor does not support thumb instructions.
2907 This is used by gcc/config/arm/lib1funcs.asm for example
2908 to compile interworking support functions even if the
2909 target processor should not support interworking. */
2913 record_alignment (now_seg
, 1);
2916 demand_empty_rest_of_line ();
2920 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2924 /* The following label is the name/address of the start of a Thumb function.
2925 We need to know this for the interworking support. */
2926 label_is_thumb_function_name
= TRUE
;
2929 /* Perform a .set directive, but also mark the alias as
2930 being a thumb function. */
2933 s_thumb_set (int equiv
)
2935 /* XXX the following is a duplicate of the code for s_set() in read.c
2936 We cannot just call that code as we need to get at the symbol that
2943 /* Especial apologies for the random logic:
2944 This just grew, and could be parsed much more simply!
2946 delim
= get_symbol_name (& name
);
2947 end_name
= input_line_pointer
;
2948 (void) restore_line_pointer (delim
);
2950 if (*input_line_pointer
!= ',')
2953 as_bad (_("expected comma after name \"%s\""), name
);
2955 ignore_rest_of_line ();
2959 input_line_pointer
++;
2962 if (name
[0] == '.' && name
[1] == '\0')
2964 /* XXX - this should not happen to .thumb_set. */
2968 if ((symbolP
= symbol_find (name
)) == NULL
2969 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2972 /* When doing symbol listings, play games with dummy fragments living
2973 outside the normal fragment chain to record the file and line info
2975 if (listing
& LISTING_SYMBOLS
)
2977 extern struct list_info_struct
* listing_tail
;
2978 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2980 memset (dummy_frag
, 0, sizeof (fragS
));
2981 dummy_frag
->fr_type
= rs_fill
;
2982 dummy_frag
->line
= listing_tail
;
2983 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2984 dummy_frag
->fr_symbol
= symbolP
;
2988 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2991 /* "set" symbols are local unless otherwise specified. */
2992 SF_SET_LOCAL (symbolP
);
2993 #endif /* OBJ_COFF */
2994 } /* Make a new symbol. */
2996 symbol_table_insert (symbolP
);
3001 && S_IS_DEFINED (symbolP
)
3002 && S_GET_SEGMENT (symbolP
) != reg_section
)
3003 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3005 pseudo_set (symbolP
);
3007 demand_empty_rest_of_line ();
3009 /* XXX Now we come to the Thumb specific bit of code. */
3011 THUMB_SET_FUNC (symbolP
, 1);
3012 ARM_SET_THUMB (symbolP
, 1);
3013 #if defined OBJ_ELF || defined OBJ_COFF
3014 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3018 /* Directives: Mode selection. */
3020 /* .syntax [unified|divided] - choose the new unified syntax
3021 (same for Arm and Thumb encoding, modulo slight differences in what
3022 can be represented) or the old divergent syntax for each mode. */
3024 s_syntax (int unused ATTRIBUTE_UNUSED
)
3028 delim
= get_symbol_name (& name
);
3030 if (!strcasecmp (name
, "unified"))
3031 unified_syntax
= TRUE
;
3032 else if (!strcasecmp (name
, "divided"))
3033 unified_syntax
= FALSE
;
3036 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3039 (void) restore_line_pointer (delim
);
3040 demand_empty_rest_of_line ();
3043 /* Directives: sectioning and alignment. */
3046 s_bss (int ignore ATTRIBUTE_UNUSED
)
3048 /* We don't support putting frags in the BSS segment, we fake it by
3049 marking in_bss, then looking at s_skip for clues. */
3050 subseg_set (bss_section
, 0);
3051 demand_empty_rest_of_line ();
3053 #ifdef md_elf_section_change_hook
3054 md_elf_section_change_hook ();
3059 s_even (int ignore ATTRIBUTE_UNUSED
)
3061 /* Never make frag if expect extra pass. */
3063 frag_align (1, 0, 0);
3065 record_alignment (now_seg
, 1);
3067 demand_empty_rest_of_line ();
3070 /* Directives: CodeComposer Studio. */
3072 /* .ref (for CodeComposer Studio syntax only). */
3074 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3076 if (codecomposer_syntax
)
3077 ignore_rest_of_line ();
3079 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3082 /* If name is not NULL, then it is used for marking the beginning of a
3083 function, whereas if it is NULL then it means the function end. */
3085 asmfunc_debug (const char * name
)
3087 static const char * last_name
= NULL
;
3091 gas_assert (last_name
== NULL
);
3094 if (debug_type
== DEBUG_STABS
)
3095 stabs_generate_asm_func (name
, name
);
3099 gas_assert (last_name
!= NULL
);
3101 if (debug_type
== DEBUG_STABS
)
3102 stabs_generate_asm_endfunc (last_name
, last_name
);
3109 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3111 if (codecomposer_syntax
)
3113 switch (asmfunc_state
)
3115 case OUTSIDE_ASMFUNC
:
3116 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3119 case WAITING_ASMFUNC_NAME
:
3120 as_bad (_(".asmfunc repeated."));
3123 case WAITING_ENDASMFUNC
:
3124 as_bad (_(".asmfunc without function."));
3127 demand_empty_rest_of_line ();
3130 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3134 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3136 if (codecomposer_syntax
)
3138 switch (asmfunc_state
)
3140 case OUTSIDE_ASMFUNC
:
3141 as_bad (_(".endasmfunc without a .asmfunc."));
3144 case WAITING_ASMFUNC_NAME
:
3145 as_bad (_(".endasmfunc without function."));
3148 case WAITING_ENDASMFUNC
:
3149 asmfunc_state
= OUTSIDE_ASMFUNC
;
3150 asmfunc_debug (NULL
);
3153 demand_empty_rest_of_line ();
3156 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3160 s_ccs_def (int name
)
3162 if (codecomposer_syntax
)
3165 as_bad (_(".def pseudo-op only available with -mccs flag."));
3168 /* Directives: Literal pools. */
3170 static literal_pool
*
3171 find_literal_pool (void)
3173 literal_pool
* pool
;
3175 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3177 if (pool
->section
== now_seg
3178 && pool
->sub_section
== now_subseg
)
3185 static literal_pool
*
3186 find_or_make_literal_pool (void)
3188 /* Next literal pool ID number. */
3189 static unsigned int latest_pool_num
= 1;
3190 literal_pool
* pool
;
3192 pool
= find_literal_pool ();
3196 /* Create a new pool. */
3197 pool
= XNEW (literal_pool
);
3201 pool
->next_free_entry
= 0;
3202 pool
->section
= now_seg
;
3203 pool
->sub_section
= now_subseg
;
3204 pool
->next
= list_of_pools
;
3205 pool
->symbol
= NULL
;
3206 pool
->alignment
= 2;
3208 /* Add it to the list. */
3209 list_of_pools
= pool
;
3212 /* New pools, and emptied pools, will have a NULL symbol. */
3213 if (pool
->symbol
== NULL
)
3215 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3216 (valueT
) 0, &zero_address_frag
);
3217 pool
->id
= latest_pool_num
++;
3224 /* Add the literal in the global 'inst'
3225 structure to the relevant literal pool. */
3228 add_to_lit_pool (unsigned int nbytes
)
3230 #define PADDING_SLOT 0x1
3231 #define LIT_ENTRY_SIZE_MASK 0xFF
3232 literal_pool
* pool
;
3233 unsigned int entry
, pool_size
= 0;
3234 bfd_boolean padding_slot_p
= FALSE
;
3240 imm1
= inst
.operands
[1].imm
;
3241 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3242 : inst
.reloc
.exp
.X_unsigned
? 0
3243 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3244 if (target_big_endian
)
3247 imm2
= inst
.operands
[1].imm
;
3251 pool
= find_or_make_literal_pool ();
3253 /* Check if this literal value is already in the pool. */
3254 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3258 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3259 && (inst
.reloc
.exp
.X_op
== O_constant
)
3260 && (pool
->literals
[entry
].X_add_number
3261 == inst
.reloc
.exp
.X_add_number
)
3262 && (pool
->literals
[entry
].X_md
== nbytes
)
3263 && (pool
->literals
[entry
].X_unsigned
3264 == inst
.reloc
.exp
.X_unsigned
))
3267 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3268 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3269 && (pool
->literals
[entry
].X_add_number
3270 == inst
.reloc
.exp
.X_add_number
)
3271 && (pool
->literals
[entry
].X_add_symbol
3272 == inst
.reloc
.exp
.X_add_symbol
)
3273 && (pool
->literals
[entry
].X_op_symbol
3274 == inst
.reloc
.exp
.X_op_symbol
)
3275 && (pool
->literals
[entry
].X_md
== nbytes
))
3278 else if ((nbytes
== 8)
3279 && !(pool_size
& 0x7)
3280 && ((entry
+ 1) != pool
->next_free_entry
)
3281 && (pool
->literals
[entry
].X_op
== O_constant
)
3282 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3283 && (pool
->literals
[entry
].X_unsigned
3284 == inst
.reloc
.exp
.X_unsigned
)
3285 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3286 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3287 && (pool
->literals
[entry
+ 1].X_unsigned
3288 == inst
.reloc
.exp
.X_unsigned
))
3291 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3292 if (padding_slot_p
&& (nbytes
== 4))
3298 /* Do we need to create a new entry? */
3299 if (entry
== pool
->next_free_entry
)
3301 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3303 inst
.error
= _("literal pool overflow");
3309 /* For 8-byte entries, we align to an 8-byte boundary,
3310 and split it into two 4-byte entries, because on 32-bit
3311 host, 8-byte constants are treated as big num, thus
3312 saved in "generic_bignum" which will be overwritten
3313 by later assignments.
3315 We also need to make sure there is enough space for
3318 We also check to make sure the literal operand is a
3320 if (!(inst
.reloc
.exp
.X_op
== O_constant
3321 || inst
.reloc
.exp
.X_op
== O_big
))
3323 inst
.error
= _("invalid type for literal pool");
3326 else if (pool_size
& 0x7)
3328 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3330 inst
.error
= _("literal pool overflow");
3334 pool
->literals
[entry
] = inst
.reloc
.exp
;
3335 pool
->literals
[entry
].X_op
= O_constant
;
3336 pool
->literals
[entry
].X_add_number
= 0;
3337 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3338 pool
->next_free_entry
+= 1;
3341 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3343 inst
.error
= _("literal pool overflow");
3347 pool
->literals
[entry
] = inst
.reloc
.exp
;
3348 pool
->literals
[entry
].X_op
= O_constant
;
3349 pool
->literals
[entry
].X_add_number
= imm1
;
3350 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3351 pool
->literals
[entry
++].X_md
= 4;
3352 pool
->literals
[entry
] = inst
.reloc
.exp
;
3353 pool
->literals
[entry
].X_op
= O_constant
;
3354 pool
->literals
[entry
].X_add_number
= imm2
;
3355 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3356 pool
->literals
[entry
].X_md
= 4;
3357 pool
->alignment
= 3;
3358 pool
->next_free_entry
+= 1;
3362 pool
->literals
[entry
] = inst
.reloc
.exp
;
3363 pool
->literals
[entry
].X_md
= 4;
3367 /* PR ld/12974: Record the location of the first source line to reference
3368 this entry in the literal pool. If it turns out during linking that the
3369 symbol does not exist we will be able to give an accurate line number for
3370 the (first use of the) missing reference. */
3371 if (debug_type
== DEBUG_DWARF2
)
3372 dwarf2_where (pool
->locs
+ entry
);
3374 pool
->next_free_entry
+= 1;
3376 else if (padding_slot_p
)
3378 pool
->literals
[entry
] = inst
.reloc
.exp
;
3379 pool
->literals
[entry
].X_md
= nbytes
;
3382 inst
.reloc
.exp
.X_op
= O_symbol
;
3383 inst
.reloc
.exp
.X_add_number
= pool_size
;
3384 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3390 tc_start_label_without_colon (void)
3392 bfd_boolean ret
= TRUE
;
3394 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3396 const char *label
= input_line_pointer
;
3398 while (!is_end_of_line
[(int) label
[-1]])
3403 as_bad (_("Invalid label '%s'"), label
);
3407 asmfunc_debug (label
);
3409 asmfunc_state
= WAITING_ENDASMFUNC
;
3415 /* Can't use symbol_new here, so have to create a symbol and then at
3416 a later date assign it a value. That's what these functions do. */
3419 symbol_locate (symbolS
* symbolP
,
3420 const char * name
, /* It is copied, the caller can modify. */
3421 segT segment
, /* Segment identifier (SEG_<something>). */
3422 valueT valu
, /* Symbol value. */
3423 fragS
* frag
) /* Associated fragment. */
3426 char * preserved_copy_of_name
;
3428 name_length
= strlen (name
) + 1; /* +1 for \0. */
3429 obstack_grow (¬es
, name
, name_length
);
3430 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3432 #ifdef tc_canonicalize_symbol_name
3433 preserved_copy_of_name
=
3434 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3437 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3439 S_SET_SEGMENT (symbolP
, segment
);
3440 S_SET_VALUE (symbolP
, valu
);
3441 symbol_clear_list_pointers (symbolP
);
3443 symbol_set_frag (symbolP
, frag
);
3445 /* Link to end of symbol chain. */
3447 extern int symbol_table_frozen
;
3449 if (symbol_table_frozen
)
3453 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3455 obj_symbol_new_hook (symbolP
);
3457 #ifdef tc_symbol_new_hook
3458 tc_symbol_new_hook (symbolP
);
3462 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3463 #endif /* DEBUG_SYMS */
3467 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3470 literal_pool
* pool
;
3473 pool
= find_literal_pool ();
3475 || pool
->symbol
== NULL
3476 || pool
->next_free_entry
== 0)
3479 /* Align pool as you have word accesses.
3480 Only make a frag if we have to. */
3482 frag_align (pool
->alignment
, 0, 0);
3484 record_alignment (now_seg
, 2);
3487 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3488 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3490 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3492 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3493 (valueT
) frag_now_fix (), frag_now
);
3494 symbol_table_insert (pool
->symbol
);
3496 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3498 #if defined OBJ_COFF || defined OBJ_ELF
3499 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3502 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3505 if (debug_type
== DEBUG_DWARF2
)
3506 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3508 /* First output the expression in the instruction to the pool. */
3509 emit_expr (&(pool
->literals
[entry
]),
3510 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3513 /* Mark the pool as empty. */
3514 pool
->next_free_entry
= 0;
3515 pool
->symbol
= NULL
;
3519 /* Forward declarations for functions below, in the MD interface
3521 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3522 static valueT
create_unwind_entry (int);
3523 static void start_unwind_section (const segT
, int);
3524 static void add_unwind_opcode (valueT
, int);
3525 static void flush_pending_unwind (void);
3527 /* Directives: Data. */
3530 s_arm_elf_cons (int nbytes
)
3534 #ifdef md_flush_pending_output
3535 md_flush_pending_output ();
3538 if (is_it_end_of_statement ())
3540 demand_empty_rest_of_line ();
3544 #ifdef md_cons_align
3545 md_cons_align (nbytes
);
3548 mapping_state (MAP_DATA
);
3552 char *base
= input_line_pointer
;
3556 if (exp
.X_op
!= O_symbol
)
3557 emit_expr (&exp
, (unsigned int) nbytes
);
3560 char *before_reloc
= input_line_pointer
;
3561 reloc
= parse_reloc (&input_line_pointer
);
3564 as_bad (_("unrecognized relocation suffix"));
3565 ignore_rest_of_line ();
3568 else if (reloc
== BFD_RELOC_UNUSED
)
3569 emit_expr (&exp
, (unsigned int) nbytes
);
3572 reloc_howto_type
*howto
= (reloc_howto_type
*)
3573 bfd_reloc_type_lookup (stdoutput
,
3574 (bfd_reloc_code_real_type
) reloc
);
3575 int size
= bfd_get_reloc_size (howto
);
3577 if (reloc
== BFD_RELOC_ARM_PLT32
)
3579 as_bad (_("(plt) is only valid on branch targets"));
3580 reloc
= BFD_RELOC_UNUSED
;
3585 as_bad (ngettext ("%s relocations do not fit in %d byte",
3586 "%s relocations do not fit in %d bytes",
3588 howto
->name
, nbytes
);
3591 /* We've parsed an expression stopping at O_symbol.
3592 But there may be more expression left now that we
3593 have parsed the relocation marker. Parse it again.
3594 XXX Surely there is a cleaner way to do this. */
3595 char *p
= input_line_pointer
;
3597 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3599 memcpy (save_buf
, base
, input_line_pointer
- base
);
3600 memmove (base
+ (input_line_pointer
- before_reloc
),
3601 base
, before_reloc
- base
);
3603 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3605 memcpy (base
, save_buf
, p
- base
);
3607 offset
= nbytes
- size
;
3608 p
= frag_more (nbytes
);
3609 memset (p
, 0, nbytes
);
3610 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3611 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3617 while (*input_line_pointer
++ == ',');
3619 /* Put terminator back into stream. */
3620 input_line_pointer
--;
3621 demand_empty_rest_of_line ();
3624 /* Emit an expression containing a 32-bit thumb instruction.
3625 Implementation based on put_thumb32_insn. */
3628 emit_thumb32_expr (expressionS
* exp
)
3630 expressionS exp_high
= *exp
;
3632 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3633 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3634 exp
->X_add_number
&= 0xffff;
3635 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3638 /* Guess the instruction size based on the opcode. */
3641 thumb_insn_size (int opcode
)
3643 if ((unsigned int) opcode
< 0xe800u
)
3645 else if ((unsigned int) opcode
>= 0xe8000000u
)
3652 emit_insn (expressionS
*exp
, int nbytes
)
3656 if (exp
->X_op
== O_constant
)
3661 size
= thumb_insn_size (exp
->X_add_number
);
3665 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3667 as_bad (_(".inst.n operand too big. "\
3668 "Use .inst.w instead"));
3673 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3674 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3676 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3678 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3679 emit_thumb32_expr (exp
);
3681 emit_expr (exp
, (unsigned int) size
);
3683 it_fsm_post_encode ();
3687 as_bad (_("cannot determine Thumb instruction size. " \
3688 "Use .inst.n/.inst.w instead"));
3691 as_bad (_("constant expression required"));
3696 /* Like s_arm_elf_cons but do not use md_cons_align and
3697 set the mapping state to MAP_ARM/MAP_THUMB. */
3700 s_arm_elf_inst (int nbytes
)
3702 if (is_it_end_of_statement ())
3704 demand_empty_rest_of_line ();
3708 /* Calling mapping_state () here will not change ARM/THUMB,
3709 but will ensure not to be in DATA state. */
3712 mapping_state (MAP_THUMB
);
3717 as_bad (_("width suffixes are invalid in ARM mode"));
3718 ignore_rest_of_line ();
3724 mapping_state (MAP_ARM
);
3733 if (! emit_insn (& exp
, nbytes
))
3735 ignore_rest_of_line ();
3739 while (*input_line_pointer
++ == ',');
3741 /* Put terminator back into stream. */
3742 input_line_pointer
--;
3743 demand_empty_rest_of_line ();
3746 /* Parse a .rel31 directive. */
3749 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3756 if (*input_line_pointer
== '1')
3757 highbit
= 0x80000000;
3758 else if (*input_line_pointer
!= '0')
3759 as_bad (_("expected 0 or 1"));
3761 input_line_pointer
++;
3762 if (*input_line_pointer
!= ',')
3763 as_bad (_("missing comma"));
3764 input_line_pointer
++;
3766 #ifdef md_flush_pending_output
3767 md_flush_pending_output ();
3770 #ifdef md_cons_align
3774 mapping_state (MAP_DATA
);
3779 md_number_to_chars (p
, highbit
, 4);
3780 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3781 BFD_RELOC_ARM_PREL31
);
3783 demand_empty_rest_of_line ();
3786 /* Directives: AEABI stack-unwind tables. */
3788 /* Parse an unwind_fnstart directive. Simply records the current location. */
3791 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3793 demand_empty_rest_of_line ();
3794 if (unwind
.proc_start
)
3796 as_bad (_("duplicate .fnstart directive"));
3800 /* Mark the start of the function. */
3801 unwind
.proc_start
= expr_build_dot ();
3803 /* Reset the rest of the unwind info. */
3804 unwind
.opcode_count
= 0;
3805 unwind
.table_entry
= NULL
;
3806 unwind
.personality_routine
= NULL
;
3807 unwind
.personality_index
= -1;
3808 unwind
.frame_size
= 0;
3809 unwind
.fp_offset
= 0;
3810 unwind
.fp_reg
= REG_SP
;
3812 unwind
.sp_restored
= 0;
3816 /* Parse a handlerdata directive. Creates the exception handling table entry
3817 for the function. */
3820 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3822 demand_empty_rest_of_line ();
3823 if (!unwind
.proc_start
)
3824 as_bad (MISSING_FNSTART
);
3826 if (unwind
.table_entry
)
3827 as_bad (_("duplicate .handlerdata directive"));
3829 create_unwind_entry (1);
3832 /* Parse an unwind_fnend directive. Generates the index table entry. */
3835 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3840 unsigned int marked_pr_dependency
;
3842 demand_empty_rest_of_line ();
3844 if (!unwind
.proc_start
)
3846 as_bad (_(".fnend directive without .fnstart"));
3850 /* Add eh table entry. */
3851 if (unwind
.table_entry
== NULL
)
3852 val
= create_unwind_entry (0);
3856 /* Add index table entry. This is two words. */
3857 start_unwind_section (unwind
.saved_seg
, 1);
3858 frag_align (2, 0, 0);
3859 record_alignment (now_seg
, 2);
3861 ptr
= frag_more (8);
3863 where
= frag_now_fix () - 8;
3865 /* Self relative offset of the function start. */
3866 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3867 BFD_RELOC_ARM_PREL31
);
3869 /* Indicate dependency on EHABI-defined personality routines to the
3870 linker, if it hasn't been done already. */
3871 marked_pr_dependency
3872 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3873 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3874 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3876 static const char *const name
[] =
3878 "__aeabi_unwind_cpp_pr0",
3879 "__aeabi_unwind_cpp_pr1",
3880 "__aeabi_unwind_cpp_pr2"
3882 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3883 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3884 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3885 |= 1 << unwind
.personality_index
;
3889 /* Inline exception table entry. */
3890 md_number_to_chars (ptr
+ 4, val
, 4);
3892 /* Self relative offset of the table entry. */
3893 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3894 BFD_RELOC_ARM_PREL31
);
3896 /* Restore the original section. */
3897 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3899 unwind
.proc_start
= NULL
;
3903 /* Parse an unwind_cantunwind directive. */
3906 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3908 demand_empty_rest_of_line ();
3909 if (!unwind
.proc_start
)
3910 as_bad (MISSING_FNSTART
);
3912 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3913 as_bad (_("personality routine specified for cantunwind frame"));
3915 unwind
.personality_index
= -2;
3919 /* Parse a personalityindex directive. */
3922 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3926 if (!unwind
.proc_start
)
3927 as_bad (MISSING_FNSTART
);
3929 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3930 as_bad (_("duplicate .personalityindex directive"));
3934 if (exp
.X_op
!= O_constant
3935 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3937 as_bad (_("bad personality routine number"));
3938 ignore_rest_of_line ();
3942 unwind
.personality_index
= exp
.X_add_number
;
3944 demand_empty_rest_of_line ();
3948 /* Parse a personality directive. */
3951 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3955 if (!unwind
.proc_start
)
3956 as_bad (MISSING_FNSTART
);
3958 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3959 as_bad (_("duplicate .personality directive"));
3961 c
= get_symbol_name (& name
);
3962 p
= input_line_pointer
;
3964 ++ input_line_pointer
;
3965 unwind
.personality_routine
= symbol_find_or_make (name
);
3967 demand_empty_rest_of_line ();
3971 /* Parse a directive saving core registers. */
3974 s_arm_unwind_save_core (void)
3980 range
= parse_reg_list (&input_line_pointer
);
3983 as_bad (_("expected register list"));
3984 ignore_rest_of_line ();
3988 demand_empty_rest_of_line ();
3990 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3991 into .unwind_save {..., sp...}. We aren't bothered about the value of
3992 ip because it is clobbered by calls. */
3993 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3994 && (range
& 0x3000) == 0x1000)
3996 unwind
.opcode_count
--;
3997 unwind
.sp_restored
= 0;
3998 range
= (range
| 0x2000) & ~0x1000;
3999 unwind
.pending_offset
= 0;
4005 /* See if we can use the short opcodes. These pop a block of up to 8
4006 registers starting with r4, plus maybe r14. */
4007 for (n
= 0; n
< 8; n
++)
4009 /* Break at the first non-saved register. */
4010 if ((range
& (1 << (n
+ 4))) == 0)
4013 /* See if there are any other bits set. */
4014 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4016 /* Use the long form. */
4017 op
= 0x8000 | ((range
>> 4) & 0xfff);
4018 add_unwind_opcode (op
, 2);
4022 /* Use the short form. */
4024 op
= 0xa8; /* Pop r14. */
4026 op
= 0xa0; /* Do not pop r14. */
4028 add_unwind_opcode (op
, 1);
4035 op
= 0xb100 | (range
& 0xf);
4036 add_unwind_opcode (op
, 2);
4039 /* Record the number of bytes pushed. */
4040 for (n
= 0; n
< 16; n
++)
4042 if (range
& (1 << n
))
4043 unwind
.frame_size
+= 4;
4048 /* Parse a directive saving FPA registers. */
4051 s_arm_unwind_save_fpa (int reg
)
4057 /* Get Number of registers to transfer. */
4058 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4061 exp
.X_op
= O_illegal
;
4063 if (exp
.X_op
!= O_constant
)
4065 as_bad (_("expected , <constant>"));
4066 ignore_rest_of_line ();
4070 num_regs
= exp
.X_add_number
;
4072 if (num_regs
< 1 || num_regs
> 4)
4074 as_bad (_("number of registers must be in the range [1:4]"));
4075 ignore_rest_of_line ();
4079 demand_empty_rest_of_line ();
4084 op
= 0xb4 | (num_regs
- 1);
4085 add_unwind_opcode (op
, 1);
4090 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4091 add_unwind_opcode (op
, 2);
4093 unwind
.frame_size
+= num_regs
* 12;
4097 /* Parse a directive saving VFP registers for ARMv6 and above. */
4100 s_arm_unwind_save_vfp_armv6 (void)
4105 int num_vfpv3_regs
= 0;
4106 int num_regs_below_16
;
4108 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4111 as_bad (_("expected register list"));
4112 ignore_rest_of_line ();
4116 demand_empty_rest_of_line ();
4118 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4119 than FSTMX/FLDMX-style ones). */
4121 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4123 num_vfpv3_regs
= count
;
4124 else if (start
+ count
> 16)
4125 num_vfpv3_regs
= start
+ count
- 16;
4127 if (num_vfpv3_regs
> 0)
4129 int start_offset
= start
> 16 ? start
- 16 : 0;
4130 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4131 add_unwind_opcode (op
, 2);
4134 /* Generate opcode for registers numbered in the range 0 .. 15. */
4135 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4136 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4137 if (num_regs_below_16
> 0)
4139 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4140 add_unwind_opcode (op
, 2);
4143 unwind
.frame_size
+= count
* 8;
4147 /* Parse a directive saving VFP registers for pre-ARMv6. */
4150 s_arm_unwind_save_vfp (void)
4156 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4159 as_bad (_("expected register list"));
4160 ignore_rest_of_line ();
4164 demand_empty_rest_of_line ();
4169 op
= 0xb8 | (count
- 1);
4170 add_unwind_opcode (op
, 1);
4175 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4176 add_unwind_opcode (op
, 2);
4178 unwind
.frame_size
+= count
* 8 + 4;
4182 /* Parse a directive saving iWMMXt data registers. */
4185 s_arm_unwind_save_mmxwr (void)
4193 if (*input_line_pointer
== '{')
4194 input_line_pointer
++;
4198 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4202 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4207 as_tsktsk (_("register list not in ascending order"));
4210 if (*input_line_pointer
== '-')
4212 input_line_pointer
++;
4213 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4216 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4219 else if (reg
>= hi_reg
)
4221 as_bad (_("bad register range"));
4224 for (; reg
< hi_reg
; reg
++)
4228 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4230 skip_past_char (&input_line_pointer
, '}');
4232 demand_empty_rest_of_line ();
4234 /* Generate any deferred opcodes because we're going to be looking at
4236 flush_pending_unwind ();
4238 for (i
= 0; i
< 16; i
++)
4240 if (mask
& (1 << i
))
4241 unwind
.frame_size
+= 8;
4244 /* Attempt to combine with a previous opcode. We do this because gcc
4245 likes to output separate unwind directives for a single block of
4247 if (unwind
.opcode_count
> 0)
4249 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4250 if ((i
& 0xf8) == 0xc0)
4253 /* Only merge if the blocks are contiguous. */
4256 if ((mask
& 0xfe00) == (1 << 9))
4258 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4259 unwind
.opcode_count
--;
4262 else if (i
== 6 && unwind
.opcode_count
>= 2)
4264 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4268 op
= 0xffff << (reg
- 1);
4270 && ((mask
& op
) == (1u << (reg
- 1))))
4272 op
= (1 << (reg
+ i
+ 1)) - 1;
4273 op
&= ~((1 << reg
) - 1);
4275 unwind
.opcode_count
-= 2;
4282 /* We want to generate opcodes in the order the registers have been
4283 saved, ie. descending order. */
4284 for (reg
= 15; reg
>= -1; reg
--)
4286 /* Save registers in blocks. */
4288 || !(mask
& (1 << reg
)))
4290 /* We found an unsaved reg. Generate opcodes to save the
4297 op
= 0xc0 | (hi_reg
- 10);
4298 add_unwind_opcode (op
, 1);
4303 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4304 add_unwind_opcode (op
, 2);
4313 ignore_rest_of_line ();
4317 s_arm_unwind_save_mmxwcg (void)
4324 if (*input_line_pointer
== '{')
4325 input_line_pointer
++;
4327 skip_whitespace (input_line_pointer
);
4331 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4335 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4341 as_tsktsk (_("register list not in ascending order"));
4344 if (*input_line_pointer
== '-')
4346 input_line_pointer
++;
4347 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4350 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4353 else if (reg
>= hi_reg
)
4355 as_bad (_("bad register range"));
4358 for (; reg
< hi_reg
; reg
++)
4362 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4364 skip_past_char (&input_line_pointer
, '}');
4366 demand_empty_rest_of_line ();
4368 /* Generate any deferred opcodes because we're going to be looking at
4370 flush_pending_unwind ();
4372 for (reg
= 0; reg
< 16; reg
++)
4374 if (mask
& (1 << reg
))
4375 unwind
.frame_size
+= 4;
4378 add_unwind_opcode (op
, 2);
4381 ignore_rest_of_line ();
4385 /* Parse an unwind_save directive.
4386 If the argument is non-zero, this is a .vsave directive. */
4389 s_arm_unwind_save (int arch_v6
)
4392 struct reg_entry
*reg
;
4393 bfd_boolean had_brace
= FALSE
;
4395 if (!unwind
.proc_start
)
4396 as_bad (MISSING_FNSTART
);
4398 /* Figure out what sort of save we have. */
4399 peek
= input_line_pointer
;
4407 reg
= arm_reg_parse_multi (&peek
);
4411 as_bad (_("register expected"));
4412 ignore_rest_of_line ();
4421 as_bad (_("FPA .unwind_save does not take a register list"));
4422 ignore_rest_of_line ();
4425 input_line_pointer
= peek
;
4426 s_arm_unwind_save_fpa (reg
->number
);
4430 s_arm_unwind_save_core ();
4435 s_arm_unwind_save_vfp_armv6 ();
4437 s_arm_unwind_save_vfp ();
4440 case REG_TYPE_MMXWR
:
4441 s_arm_unwind_save_mmxwr ();
4444 case REG_TYPE_MMXWCG
:
4445 s_arm_unwind_save_mmxwcg ();
4449 as_bad (_(".unwind_save does not support this kind of register"));
4450 ignore_rest_of_line ();
4455 /* Parse an unwind_movsp directive. */
4458 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4464 if (!unwind
.proc_start
)
4465 as_bad (MISSING_FNSTART
);
4467 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4470 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4471 ignore_rest_of_line ();
4475 /* Optional constant. */
4476 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4478 if (immediate_for_directive (&offset
) == FAIL
)
4484 demand_empty_rest_of_line ();
4486 if (reg
== REG_SP
|| reg
== REG_PC
)
4488 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4492 if (unwind
.fp_reg
!= REG_SP
)
4493 as_bad (_("unexpected .unwind_movsp directive"));
4495 /* Generate opcode to restore the value. */
4497 add_unwind_opcode (op
, 1);
4499 /* Record the information for later. */
4500 unwind
.fp_reg
= reg
;
4501 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4502 unwind
.sp_restored
= 1;
4505 /* Parse an unwind_pad directive. */
4508 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4512 if (!unwind
.proc_start
)
4513 as_bad (MISSING_FNSTART
);
4515 if (immediate_for_directive (&offset
) == FAIL
)
4520 as_bad (_("stack increment must be multiple of 4"));
4521 ignore_rest_of_line ();
4525 /* Don't generate any opcodes, just record the details for later. */
4526 unwind
.frame_size
+= offset
;
4527 unwind
.pending_offset
+= offset
;
4529 demand_empty_rest_of_line ();
4532 /* Parse an unwind_setfp directive. */
4535 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4541 if (!unwind
.proc_start
)
4542 as_bad (MISSING_FNSTART
);
4544 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4545 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4548 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4550 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4552 as_bad (_("expected <reg>, <reg>"));
4553 ignore_rest_of_line ();
4557 /* Optional constant. */
4558 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4560 if (immediate_for_directive (&offset
) == FAIL
)
4566 demand_empty_rest_of_line ();
4568 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4570 as_bad (_("register must be either sp or set by a previous"
4571 "unwind_movsp directive"));
4575 /* Don't generate any opcodes, just record the information for later. */
4576 unwind
.fp_reg
= fp_reg
;
4578 if (sp_reg
== REG_SP
)
4579 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4581 unwind
.fp_offset
-= offset
;
4584 /* Parse an unwind_raw directive. */
4587 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4590 /* This is an arbitrary limit. */
4591 unsigned char op
[16];
4594 if (!unwind
.proc_start
)
4595 as_bad (MISSING_FNSTART
);
4598 if (exp
.X_op
== O_constant
4599 && skip_past_comma (&input_line_pointer
) != FAIL
)
4601 unwind
.frame_size
+= exp
.X_add_number
;
4605 exp
.X_op
= O_illegal
;
4607 if (exp
.X_op
!= O_constant
)
4609 as_bad (_("expected <offset>, <opcode>"));
4610 ignore_rest_of_line ();
4616 /* Parse the opcode. */
4621 as_bad (_("unwind opcode too long"));
4622 ignore_rest_of_line ();
4624 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4626 as_bad (_("invalid unwind opcode"));
4627 ignore_rest_of_line ();
4630 op
[count
++] = exp
.X_add_number
;
4632 /* Parse the next byte. */
4633 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4639 /* Add the opcode bytes in reverse order. */
4641 add_unwind_opcode (op
[count
], 1);
4643 demand_empty_rest_of_line ();
4647 /* Parse a .eabi_attribute directive. */
4650 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4652 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4654 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4655 attributes_set_explicitly
[tag
] = 1;
4658 /* Emit a tls fix for the symbol. */
4661 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4665 #ifdef md_flush_pending_output
4666 md_flush_pending_output ();
4669 #ifdef md_cons_align
4673 /* Since we're just labelling the code, there's no need to define a
4676 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4677 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4678 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4679 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4681 #endif /* OBJ_ELF */
4683 static void s_arm_arch (int);
4684 static void s_arm_object_arch (int);
4685 static void s_arm_cpu (int);
4686 static void s_arm_fpu (int);
4687 static void s_arm_arch_extension (int);
4692 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4699 if (exp
.X_op
== O_symbol
)
4700 exp
.X_op
= O_secrel
;
4702 emit_expr (&exp
, 4);
4704 while (*input_line_pointer
++ == ',');
4706 input_line_pointer
--;
4707 demand_empty_rest_of_line ();
4711 /* This table describes all the machine specific pseudo-ops the assembler
4712 has to support. The fields are:
4713 pseudo-op name without dot
4714 function to call to execute this pseudo-op
4715 Integer arg to pass to the function. */
4717 const pseudo_typeS md_pseudo_table
[] =
4719 /* Never called because '.req' does not start a line. */
4720 { "req", s_req
, 0 },
4721 /* Following two are likewise never called. */
4724 { "unreq", s_unreq
, 0 },
4725 { "bss", s_bss
, 0 },
4726 { "align", s_align_ptwo
, 2 },
4727 { "arm", s_arm
, 0 },
4728 { "thumb", s_thumb
, 0 },
4729 { "code", s_code
, 0 },
4730 { "force_thumb", s_force_thumb
, 0 },
4731 { "thumb_func", s_thumb_func
, 0 },
4732 { "thumb_set", s_thumb_set
, 0 },
4733 { "even", s_even
, 0 },
4734 { "ltorg", s_ltorg
, 0 },
4735 { "pool", s_ltorg
, 0 },
4736 { "syntax", s_syntax
, 0 },
4737 { "cpu", s_arm_cpu
, 0 },
4738 { "arch", s_arm_arch
, 0 },
4739 { "object_arch", s_arm_object_arch
, 0 },
4740 { "fpu", s_arm_fpu
, 0 },
4741 { "arch_extension", s_arm_arch_extension
, 0 },
4743 { "word", s_arm_elf_cons
, 4 },
4744 { "long", s_arm_elf_cons
, 4 },
4745 { "inst.n", s_arm_elf_inst
, 2 },
4746 { "inst.w", s_arm_elf_inst
, 4 },
4747 { "inst", s_arm_elf_inst
, 0 },
4748 { "rel31", s_arm_rel31
, 0 },
4749 { "fnstart", s_arm_unwind_fnstart
, 0 },
4750 { "fnend", s_arm_unwind_fnend
, 0 },
4751 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4752 { "personality", s_arm_unwind_personality
, 0 },
4753 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4754 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4755 { "save", s_arm_unwind_save
, 0 },
4756 { "vsave", s_arm_unwind_save
, 1 },
4757 { "movsp", s_arm_unwind_movsp
, 0 },
4758 { "pad", s_arm_unwind_pad
, 0 },
4759 { "setfp", s_arm_unwind_setfp
, 0 },
4760 { "unwind_raw", s_arm_unwind_raw
, 0 },
4761 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4762 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4766 /* These are used for dwarf. */
4770 /* These are used for dwarf2. */
4771 { "file", dwarf2_directive_file
, 0 },
4772 { "loc", dwarf2_directive_loc
, 0 },
4773 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4775 { "extend", float_cons
, 'x' },
4776 { "ldouble", float_cons
, 'x' },
4777 { "packed", float_cons
, 'p' },
4779 {"secrel32", pe_directive_secrel
, 0},
4782 /* These are for compatibility with CodeComposer Studio. */
4783 {"ref", s_ccs_ref
, 0},
4784 {"def", s_ccs_def
, 0},
4785 {"asmfunc", s_ccs_asmfunc
, 0},
4786 {"endasmfunc", s_ccs_endasmfunc
, 0},
4791 /* Parser functions used exclusively in instruction operands. */
4793 /* Generic immediate-value read function for use in insn parsing.
4794 STR points to the beginning of the immediate (the leading #);
4795 VAL receives the value; if the value is outside [MIN, MAX]
4796 issue an error. PREFIX_OPT is true if the immediate prefix is
4800 parse_immediate (char **str
, int *val
, int min
, int max
,
4801 bfd_boolean prefix_opt
)
4805 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4806 if (exp
.X_op
!= O_constant
)
4808 inst
.error
= _("constant expression required");
4812 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4814 inst
.error
= _("immediate value out of range");
4818 *val
= exp
.X_add_number
;
4822 /* Less-generic immediate-value read function with the possibility of loading a
4823 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4824 instructions. Puts the result directly in inst.operands[i]. */
4827 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4828 bfd_boolean allow_symbol_p
)
4831 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4834 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4836 if (exp_p
->X_op
== O_constant
)
4838 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4839 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4840 O_constant. We have to be careful not to break compilation for
4841 32-bit X_add_number, though. */
4842 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4844 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4845 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4847 inst
.operands
[i
].regisimm
= 1;
4850 else if (exp_p
->X_op
== O_big
4851 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4853 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4855 /* Bignums have their least significant bits in
4856 generic_bignum[0]. Make sure we put 32 bits in imm and
4857 32 bits in reg, in a (hopefully) portable way. */
4858 gas_assert (parts
!= 0);
4860 /* Make sure that the number is not too big.
4861 PR 11972: Bignums can now be sign-extended to the
4862 size of a .octa so check that the out of range bits
4863 are all zero or all one. */
4864 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4866 LITTLENUM_TYPE m
= -1;
4868 if (generic_bignum
[parts
* 2] != 0
4869 && generic_bignum
[parts
* 2] != m
)
4872 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4873 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4877 inst
.operands
[i
].imm
= 0;
4878 for (j
= 0; j
< parts
; j
++, idx
++)
4879 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4880 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4881 inst
.operands
[i
].reg
= 0;
4882 for (j
= 0; j
< parts
; j
++, idx
++)
4883 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4884 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4885 inst
.operands
[i
].regisimm
= 1;
4887 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4895 /* Returns the pseudo-register number of an FPA immediate constant,
4896 or FAIL if there isn't a valid constant here. */
4899 parse_fpa_immediate (char ** str
)
4901 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4907 /* First try and match exact strings, this is to guarantee
4908 that some formats will work even for cross assembly. */
4910 for (i
= 0; fp_const
[i
]; i
++)
4912 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4916 *str
+= strlen (fp_const
[i
]);
4917 if (is_end_of_line
[(unsigned char) **str
])
4923 /* Just because we didn't get a match doesn't mean that the constant
4924 isn't valid, just that it is in a format that we don't
4925 automatically recognize. Try parsing it with the standard
4926 expression routines. */
4928 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4930 /* Look for a raw floating point number. */
4931 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4932 && is_end_of_line
[(unsigned char) *save_in
])
4934 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4936 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4938 if (words
[j
] != fp_values
[i
][j
])
4942 if (j
== MAX_LITTLENUMS
)
4950 /* Try and parse a more complex expression, this will probably fail
4951 unless the code uses a floating point prefix (eg "0f"). */
4952 save_in
= input_line_pointer
;
4953 input_line_pointer
= *str
;
4954 if (expression (&exp
) == absolute_section
4955 && exp
.X_op
== O_big
4956 && exp
.X_add_number
< 0)
4958 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4960 #define X_PRECISION 5
4961 #define E_PRECISION 15L
4962 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4964 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4966 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4968 if (words
[j
] != fp_values
[i
][j
])
4972 if (j
== MAX_LITTLENUMS
)
4974 *str
= input_line_pointer
;
4975 input_line_pointer
= save_in
;
4982 *str
= input_line_pointer
;
4983 input_line_pointer
= save_in
;
4984 inst
.error
= _("invalid FPA immediate expression");
4988 /* Returns 1 if a number has "quarter-precision" float format
4989 0baBbbbbbc defgh000 00000000 00000000. */
4992 is_quarter_float (unsigned imm
)
4994 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4995 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4999 /* Detect the presence of a floating point or integer zero constant,
5003 parse_ifimm_zero (char **in
)
5007 if (!is_immediate_prefix (**in
))
5009 /* In unified syntax, all prefixes are optional. */
5010 if (!unified_syntax
)
5016 /* Accept #0x0 as a synonym for #0. */
5017 if (strncmp (*in
, "0x", 2) == 0)
5020 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5025 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5026 &generic_floating_point_number
);
5029 && generic_floating_point_number
.sign
== '+'
5030 && (generic_floating_point_number
.low
5031 > generic_floating_point_number
.leader
))
5037 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5038 0baBbbbbbc defgh000 00000000 00000000.
5039 The zero and minus-zero cases need special handling, since they can't be
5040 encoded in the "quarter-precision" float format, but can nonetheless be
5041 loaded as integer constants. */
5044 parse_qfloat_immediate (char **ccp
, int *immed
)
5048 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5049 int found_fpchar
= 0;
5051 skip_past_char (&str
, '#');
5053 /* We must not accidentally parse an integer as a floating-point number. Make
5054 sure that the value we parse is not an integer by checking for special
5055 characters '.' or 'e'.
5056 FIXME: This is a horrible hack, but doing better is tricky because type
5057 information isn't in a very usable state at parse time. */
5059 skip_whitespace (fpnum
);
5061 if (strncmp (fpnum
, "0x", 2) == 0)
5065 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5066 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5076 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5078 unsigned fpword
= 0;
5081 /* Our FP word must be 32 bits (single-precision FP). */
5082 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5084 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5088 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5101 /* Shift operands. */
5104 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5107 struct asm_shift_name
5110 enum shift_kind kind
;
5113 /* Third argument to parse_shift. */
5114 enum parse_shift_mode
5116 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5117 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5118 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5119 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5120 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5123 /* Parse a <shift> specifier on an ARM data processing instruction.
5124 This has three forms:
5126 (LSL|LSR|ASL|ASR|ROR) Rs
5127 (LSL|LSR|ASL|ASR|ROR) #imm
5130 Note that ASL is assimilated to LSL in the instruction encoding, and
5131 RRX to ROR #0 (which cannot be written as such). */
5134 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5136 const struct asm_shift_name
*shift_name
;
5137 enum shift_kind shift
;
5142 for (p
= *str
; ISALPHA (*p
); p
++)
5147 inst
.error
= _("shift expression expected");
5151 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5154 if (shift_name
== NULL
)
5156 inst
.error
= _("shift expression expected");
5160 shift
= shift_name
->kind
;
5164 case NO_SHIFT_RESTRICT
:
5165 case SHIFT_IMMEDIATE
: break;
5167 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5168 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5170 inst
.error
= _("'LSL' or 'ASR' required");
5175 case SHIFT_LSL_IMMEDIATE
:
5176 if (shift
!= SHIFT_LSL
)
5178 inst
.error
= _("'LSL' required");
5183 case SHIFT_ASR_IMMEDIATE
:
5184 if (shift
!= SHIFT_ASR
)
5186 inst
.error
= _("'ASR' required");
5194 if (shift
!= SHIFT_RRX
)
5196 /* Whitespace can appear here if the next thing is a bare digit. */
5197 skip_whitespace (p
);
5199 if (mode
== NO_SHIFT_RESTRICT
5200 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5202 inst
.operands
[i
].imm
= reg
;
5203 inst
.operands
[i
].immisreg
= 1;
5205 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5208 inst
.operands
[i
].shift_kind
= shift
;
5209 inst
.operands
[i
].shifted
= 1;
5214 /* Parse a <shifter_operand> for an ARM data processing instruction:
5217 #<immediate>, <rotate>
5221 where <shift> is defined by parse_shift above, and <rotate> is a
5222 multiple of 2 between 0 and 30. Validation of immediate operands
5223 is deferred to md_apply_fix. */
5226 parse_shifter_operand (char **str
, int i
)
5231 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5233 inst
.operands
[i
].reg
= value
;
5234 inst
.operands
[i
].isreg
= 1;
5236 /* parse_shift will override this if appropriate */
5237 inst
.reloc
.exp
.X_op
= O_constant
;
5238 inst
.reloc
.exp
.X_add_number
= 0;
5240 if (skip_past_comma (str
) == FAIL
)
5243 /* Shift operation on register. */
5244 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5247 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5250 if (skip_past_comma (str
) == SUCCESS
)
5252 /* #x, y -- ie explicit rotation by Y. */
5253 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5256 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5258 inst
.error
= _("constant expression expected");
5262 value
= exp
.X_add_number
;
5263 if (value
< 0 || value
> 30 || value
% 2 != 0)
5265 inst
.error
= _("invalid rotation");
5268 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5270 inst
.error
= _("invalid constant");
5274 /* Encode as specified. */
5275 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5279 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5280 inst
.reloc
.pc_rel
= 0;
5284 /* Group relocation information. Each entry in the table contains the
5285 textual name of the relocation as may appear in assembler source
5286 and must end with a colon.
5287 Along with this textual name are the relocation codes to be used if
5288 the corresponding instruction is an ALU instruction (ADD or SUB only),
5289 an LDR, an LDRS, or an LDC. */
5291 struct group_reloc_table_entry
5302 /* Varieties of non-ALU group relocation. */
5309 static struct group_reloc_table_entry group_reloc_table
[] =
5310 { /* Program counter relative: */
5312 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5317 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5318 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5319 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5320 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5322 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5327 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5328 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5329 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5330 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5332 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5333 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5334 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5335 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5336 /* Section base relative */
5338 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5343 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5344 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5345 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5346 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5348 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5353 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5354 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5355 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5356 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5358 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5359 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5360 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5361 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5362 /* Absolute thumb alu relocations. */
5364 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5369 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5374 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5379 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5384 /* Given the address of a pointer pointing to the textual name of a group
5385 relocation as may appear in assembler source, attempt to find its details
5386 in group_reloc_table. The pointer will be updated to the character after
5387 the trailing colon. On failure, FAIL will be returned; SUCCESS
5388 otherwise. On success, *entry will be updated to point at the relevant
5389 group_reloc_table entry. */
5392 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5395 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5397 int length
= strlen (group_reloc_table
[i
].name
);
5399 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5400 && (*str
)[length
] == ':')
5402 *out
= &group_reloc_table
[i
];
5403 *str
+= (length
+ 1);
5411 /* Parse a <shifter_operand> for an ARM data processing instruction
5412 (as for parse_shifter_operand) where group relocations are allowed:
5415 #<immediate>, <rotate>
5416 #:<group_reloc>:<expression>
5420 where <group_reloc> is one of the strings defined in group_reloc_table.
5421 The hashes are optional.
5423 Everything else is as for parse_shifter_operand. */
5425 static parse_operand_result
5426 parse_shifter_operand_group_reloc (char **str
, int i
)
5428 /* Determine if we have the sequence of characters #: or just :
5429 coming next. If we do, then we check for a group relocation.
5430 If we don't, punt the whole lot to parse_shifter_operand. */
5432 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5433 || (*str
)[0] == ':')
5435 struct group_reloc_table_entry
*entry
;
5437 if ((*str
)[0] == '#')
5442 /* Try to parse a group relocation. Anything else is an error. */
5443 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5445 inst
.error
= _("unknown group relocation");
5446 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5449 /* We now have the group relocation table entry corresponding to
5450 the name in the assembler source. Next, we parse the expression. */
5451 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5452 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5454 /* Record the relocation type (always the ALU variant here). */
5455 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5456 gas_assert (inst
.reloc
.type
!= 0);
5458 return PARSE_OPERAND_SUCCESS
;
5461 return parse_shifter_operand (str
, i
) == SUCCESS
5462 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5464 /* Never reached. */
5467 /* Parse a Neon alignment expression. Information is written to
5468 inst.operands[i]. We assume the initial ':' has been skipped.
5470 align .imm = align << 8, .immisalign=1, .preind=0 */
5471 static parse_operand_result
5472 parse_neon_alignment (char **str
, int i
)
5477 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5479 if (exp
.X_op
!= O_constant
)
5481 inst
.error
= _("alignment must be constant");
5482 return PARSE_OPERAND_FAIL
;
5485 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5486 inst
.operands
[i
].immisalign
= 1;
5487 /* Alignments are not pre-indexes. */
5488 inst
.operands
[i
].preind
= 0;
5491 return PARSE_OPERAND_SUCCESS
;
5494 /* Parse all forms of an ARM address expression. Information is written
5495 to inst.operands[i] and/or inst.reloc.
5497 Preindexed addressing (.preind=1):
5499 [Rn, #offset] .reg=Rn .reloc.exp=offset
5500 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5501 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5502 .shift_kind=shift .reloc.exp=shift_imm
5504 These three may have a trailing ! which causes .writeback to be set also.
5506 Postindexed addressing (.postind=1, .writeback=1):
5508 [Rn], #offset .reg=Rn .reloc.exp=offset
5509 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5510 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5511 .shift_kind=shift .reloc.exp=shift_imm
5513 Unindexed addressing (.preind=0, .postind=0):
5515 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5519 [Rn]{!} shorthand for [Rn,#0]{!}
5520 =immediate .isreg=0 .reloc.exp=immediate
5521 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5523 It is the caller's responsibility to check for addressing modes not
5524 supported by the instruction, and to set inst.reloc.type. */
5526 static parse_operand_result
5527 parse_address_main (char **str
, int i
, int group_relocations
,
5528 group_reloc_type group_type
)
5533 if (skip_past_char (&p
, '[') == FAIL
)
5535 if (skip_past_char (&p
, '=') == FAIL
)
5537 /* Bare address - translate to PC-relative offset. */
5538 inst
.reloc
.pc_rel
= 1;
5539 inst
.operands
[i
].reg
= REG_PC
;
5540 inst
.operands
[i
].isreg
= 1;
5541 inst
.operands
[i
].preind
= 1;
5543 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5544 return PARSE_OPERAND_FAIL
;
5546 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5547 /*allow_symbol_p=*/TRUE
))
5548 return PARSE_OPERAND_FAIL
;
5551 return PARSE_OPERAND_SUCCESS
;
5554 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5555 skip_whitespace (p
);
5557 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5559 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5560 return PARSE_OPERAND_FAIL
;
5562 inst
.operands
[i
].reg
= reg
;
5563 inst
.operands
[i
].isreg
= 1;
5565 if (skip_past_comma (&p
) == SUCCESS
)
5567 inst
.operands
[i
].preind
= 1;
5570 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5572 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5574 inst
.operands
[i
].imm
= reg
;
5575 inst
.operands
[i
].immisreg
= 1;
5577 if (skip_past_comma (&p
) == SUCCESS
)
5578 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5579 return PARSE_OPERAND_FAIL
;
5581 else if (skip_past_char (&p
, ':') == SUCCESS
)
5583 /* FIXME: '@' should be used here, but it's filtered out by generic
5584 code before we get to see it here. This may be subject to
5586 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5588 if (result
!= PARSE_OPERAND_SUCCESS
)
5593 if (inst
.operands
[i
].negative
)
5595 inst
.operands
[i
].negative
= 0;
5599 if (group_relocations
5600 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5602 struct group_reloc_table_entry
*entry
;
5604 /* Skip over the #: or : sequence. */
5610 /* Try to parse a group relocation. Anything else is an
5612 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5614 inst
.error
= _("unknown group relocation");
5615 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5618 /* We now have the group relocation table entry corresponding to
5619 the name in the assembler source. Next, we parse the
5621 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5622 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5624 /* Record the relocation type. */
5628 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5632 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5636 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5643 if (inst
.reloc
.type
== 0)
5645 inst
.error
= _("this group relocation is not allowed on this instruction");
5646 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5653 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5654 return PARSE_OPERAND_FAIL
;
5655 /* If the offset is 0, find out if it's a +0 or -0. */
5656 if (inst
.reloc
.exp
.X_op
== O_constant
5657 && inst
.reloc
.exp
.X_add_number
== 0)
5659 skip_whitespace (q
);
5663 skip_whitespace (q
);
5666 inst
.operands
[i
].negative
= 1;
5671 else if (skip_past_char (&p
, ':') == SUCCESS
)
5673 /* FIXME: '@' should be used here, but it's filtered out by generic code
5674 before we get to see it here. This may be subject to change. */
5675 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5677 if (result
!= PARSE_OPERAND_SUCCESS
)
5681 if (skip_past_char (&p
, ']') == FAIL
)
5683 inst
.error
= _("']' expected");
5684 return PARSE_OPERAND_FAIL
;
5687 if (skip_past_char (&p
, '!') == SUCCESS
)
5688 inst
.operands
[i
].writeback
= 1;
5690 else if (skip_past_comma (&p
) == SUCCESS
)
5692 if (skip_past_char (&p
, '{') == SUCCESS
)
5694 /* [Rn], {expr} - unindexed, with option */
5695 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5696 0, 255, TRUE
) == FAIL
)
5697 return PARSE_OPERAND_FAIL
;
5699 if (skip_past_char (&p
, '}') == FAIL
)
5701 inst
.error
= _("'}' expected at end of 'option' field");
5702 return PARSE_OPERAND_FAIL
;
5704 if (inst
.operands
[i
].preind
)
5706 inst
.error
= _("cannot combine index with option");
5707 return PARSE_OPERAND_FAIL
;
5710 return PARSE_OPERAND_SUCCESS
;
5714 inst
.operands
[i
].postind
= 1;
5715 inst
.operands
[i
].writeback
= 1;
5717 if (inst
.operands
[i
].preind
)
5719 inst
.error
= _("cannot combine pre- and post-indexing");
5720 return PARSE_OPERAND_FAIL
;
5724 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5726 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5728 /* We might be using the immediate for alignment already. If we
5729 are, OR the register number into the low-order bits. */
5730 if (inst
.operands
[i
].immisalign
)
5731 inst
.operands
[i
].imm
|= reg
;
5733 inst
.operands
[i
].imm
= reg
;
5734 inst
.operands
[i
].immisreg
= 1;
5736 if (skip_past_comma (&p
) == SUCCESS
)
5737 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5738 return PARSE_OPERAND_FAIL
;
5744 if (inst
.operands
[i
].negative
)
5746 inst
.operands
[i
].negative
= 0;
5749 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5750 return PARSE_OPERAND_FAIL
;
5751 /* If the offset is 0, find out if it's a +0 or -0. */
5752 if (inst
.reloc
.exp
.X_op
== O_constant
5753 && inst
.reloc
.exp
.X_add_number
== 0)
5755 skip_whitespace (q
);
5759 skip_whitespace (q
);
5762 inst
.operands
[i
].negative
= 1;
5768 /* If at this point neither .preind nor .postind is set, we have a
5769 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5770 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5772 inst
.operands
[i
].preind
= 1;
5773 inst
.reloc
.exp
.X_op
= O_constant
;
5774 inst
.reloc
.exp
.X_add_number
= 0;
5777 return PARSE_OPERAND_SUCCESS
;
5781 parse_address (char **str
, int i
)
5783 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5787 static parse_operand_result
5788 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5790 return parse_address_main (str
, i
, 1, type
);
5793 /* Parse an operand for a MOVW or MOVT instruction. */
5795 parse_half (char **str
)
5800 skip_past_char (&p
, '#');
5801 if (strncasecmp (p
, ":lower16:", 9) == 0)
5802 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5803 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5804 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5806 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5809 skip_whitespace (p
);
5812 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5815 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5817 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5819 inst
.error
= _("constant expression expected");
5822 if (inst
.reloc
.exp
.X_add_number
< 0
5823 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5825 inst
.error
= _("immediate value out of range");
5833 /* Miscellaneous. */
5835 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5836 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5838 parse_psr (char **str
, bfd_boolean lhs
)
5841 unsigned long psr_field
;
5842 const struct asm_psr
*psr
;
5844 bfd_boolean is_apsr
= FALSE
;
5845 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5847 /* PR gas/12698: If the user has specified -march=all then m_profile will
5848 be TRUE, but we want to ignore it in this case as we are building for any
5849 CPU type, including non-m variants. */
5850 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5853 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5854 feature for ease of use and backwards compatibility. */
5856 if (strncasecmp (p
, "SPSR", 4) == 0)
5859 goto unsupported_psr
;
5861 psr_field
= SPSR_BIT
;
5863 else if (strncasecmp (p
, "CPSR", 4) == 0)
5866 goto unsupported_psr
;
5870 else if (strncasecmp (p
, "APSR", 4) == 0)
5872 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5873 and ARMv7-R architecture CPUs. */
5882 while (ISALNUM (*p
) || *p
== '_');
5884 if (strncasecmp (start
, "iapsr", 5) == 0
5885 || strncasecmp (start
, "eapsr", 5) == 0
5886 || strncasecmp (start
, "xpsr", 4) == 0
5887 || strncasecmp (start
, "psr", 3) == 0)
5888 p
= start
+ strcspn (start
, "rR") + 1;
5890 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5896 /* If APSR is being written, a bitfield may be specified. Note that
5897 APSR itself is handled above. */
5898 if (psr
->field
<= 3)
5900 psr_field
= psr
->field
;
5906 /* M-profile MSR instructions have the mask field set to "10", except
5907 *PSR variants which modify APSR, which may use a different mask (and
5908 have been handled already). Do that by setting the PSR_f field
5910 return psr
->field
| (lhs
? PSR_f
: 0);
5913 goto unsupported_psr
;
5919 /* A suffix follows. */
5925 while (ISALNUM (*p
) || *p
== '_');
5929 /* APSR uses a notation for bits, rather than fields. */
5930 unsigned int nzcvq_bits
= 0;
5931 unsigned int g_bit
= 0;
5934 for (bit
= start
; bit
!= p
; bit
++)
5936 switch (TOLOWER (*bit
))
5939 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5943 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5947 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5951 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5955 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5959 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5963 inst
.error
= _("unexpected bit specified after APSR");
5968 if (nzcvq_bits
== 0x1f)
5973 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5975 inst
.error
= _("selected processor does not "
5976 "support DSP extension");
5983 if ((nzcvq_bits
& 0x20) != 0
5984 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5985 || (g_bit
& 0x2) != 0)
5987 inst
.error
= _("bad bitmask specified after APSR");
5993 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5998 psr_field
|= psr
->field
;
6004 goto error
; /* Garbage after "[CS]PSR". */
6006 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6007 is deprecated, but allow it anyway. */
6011 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6014 else if (!m_profile
)
6015 /* These bits are never right for M-profile devices: don't set them
6016 (only code paths which read/write APSR reach here). */
6017 psr_field
|= (PSR_c
| PSR_f
);
6023 inst
.error
= _("selected processor does not support requested special "
6024 "purpose register");
6028 inst
.error
= _("flag for {c}psr instruction expected");
6032 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6033 value suitable for splatting into the AIF field of the instruction. */
6036 parse_cps_flags (char **str
)
6045 case '\0': case ',':
6048 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6049 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6050 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6053 inst
.error
= _("unrecognized CPS flag");
6058 if (saw_a_flag
== 0)
6060 inst
.error
= _("missing CPS flags");
6068 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6069 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6072 parse_endian_specifier (char **str
)
6077 if (strncasecmp (s
, "BE", 2))
6079 else if (strncasecmp (s
, "LE", 2))
6083 inst
.error
= _("valid endian specifiers are be or le");
6087 if (ISALNUM (s
[2]) || s
[2] == '_')
6089 inst
.error
= _("valid endian specifiers are be or le");
6094 return little_endian
;
6097 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6098 value suitable for poking into the rotate field of an sxt or sxta
6099 instruction, or FAIL on error. */
6102 parse_ror (char **str
)
6107 if (strncasecmp (s
, "ROR", 3) == 0)
6111 inst
.error
= _("missing rotation field after comma");
6115 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6120 case 0: *str
= s
; return 0x0;
6121 case 8: *str
= s
; return 0x1;
6122 case 16: *str
= s
; return 0x2;
6123 case 24: *str
= s
; return 0x3;
6126 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6131 /* Parse a conditional code (from conds[] below). The value returned is in the
6132 range 0 .. 14, or FAIL. */
6134 parse_cond (char **str
)
6137 const struct asm_cond
*c
;
6139 /* Condition codes are always 2 characters, so matching up to
6140 3 characters is sufficient. */
6145 while (ISALPHA (*q
) && n
< 3)
6147 cond
[n
] = TOLOWER (*q
);
6152 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6155 inst
.error
= _("condition required");
6163 /* Record a use of the given feature. */
6165 record_feature_use (const arm_feature_set
*feature
)
6168 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6170 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6173 /* If the given feature is currently allowed, mark it as used and return TRUE.
6174 Return FALSE otherwise. */
6176 mark_feature_used (const arm_feature_set
*feature
)
6178 /* Ensure the option is currently allowed. */
6179 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6182 /* Add the appropriate architecture feature for the barrier option used. */
6183 record_feature_use (feature
);
6188 /* Parse an option for a barrier instruction. Returns the encoding for the
6191 parse_barrier (char **str
)
6194 const struct asm_barrier_opt
*o
;
6197 while (ISALPHA (*q
))
6200 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6205 if (!mark_feature_used (&o
->arch
))
6212 /* Parse the operands of a table branch instruction. Similar to a memory
6215 parse_tb (char **str
)
6220 if (skip_past_char (&p
, '[') == FAIL
)
6222 inst
.error
= _("'[' expected");
6226 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6228 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6231 inst
.operands
[0].reg
= reg
;
6233 if (skip_past_comma (&p
) == FAIL
)
6235 inst
.error
= _("',' expected");
6239 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6241 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6244 inst
.operands
[0].imm
= reg
;
6246 if (skip_past_comma (&p
) == SUCCESS
)
6248 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6250 if (inst
.reloc
.exp
.X_add_number
!= 1)
6252 inst
.error
= _("invalid shift");
6255 inst
.operands
[0].shifted
= 1;
6258 if (skip_past_char (&p
, ']') == FAIL
)
6260 inst
.error
= _("']' expected");
6267 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6268 information on the types the operands can take and how they are encoded.
6269 Up to four operands may be read; this function handles setting the
6270 ".present" field for each read operand itself.
6271 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6272 else returns FAIL. */
6275 parse_neon_mov (char **str
, int *which_operand
)
6277 int i
= *which_operand
, val
;
6278 enum arm_reg_type rtype
;
6280 struct neon_type_el optype
;
6282 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6284 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6285 inst
.operands
[i
].reg
= val
;
6286 inst
.operands
[i
].isscalar
= 1;
6287 inst
.operands
[i
].vectype
= optype
;
6288 inst
.operands
[i
++].present
= 1;
6290 if (skip_past_comma (&ptr
) == FAIL
)
6293 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6296 inst
.operands
[i
].reg
= val
;
6297 inst
.operands
[i
].isreg
= 1;
6298 inst
.operands
[i
].present
= 1;
6300 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6303 /* Cases 0, 1, 2, 3, 5 (D only). */
6304 if (skip_past_comma (&ptr
) == FAIL
)
6307 inst
.operands
[i
].reg
= val
;
6308 inst
.operands
[i
].isreg
= 1;
6309 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6310 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6311 inst
.operands
[i
].isvec
= 1;
6312 inst
.operands
[i
].vectype
= optype
;
6313 inst
.operands
[i
++].present
= 1;
6315 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6317 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6318 Case 13: VMOV <Sd>, <Rm> */
6319 inst
.operands
[i
].reg
= val
;
6320 inst
.operands
[i
].isreg
= 1;
6321 inst
.operands
[i
].present
= 1;
6323 if (rtype
== REG_TYPE_NQ
)
6325 first_error (_("can't use Neon quad register here"));
6328 else if (rtype
!= REG_TYPE_VFS
)
6331 if (skip_past_comma (&ptr
) == FAIL
)
6333 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6335 inst
.operands
[i
].reg
= val
;
6336 inst
.operands
[i
].isreg
= 1;
6337 inst
.operands
[i
].present
= 1;
6340 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6343 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6344 Case 1: VMOV<c><q> <Dd>, <Dm>
6345 Case 8: VMOV.F32 <Sd>, <Sm>
6346 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6348 inst
.operands
[i
].reg
= val
;
6349 inst
.operands
[i
].isreg
= 1;
6350 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6351 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6352 inst
.operands
[i
].isvec
= 1;
6353 inst
.operands
[i
].vectype
= optype
;
6354 inst
.operands
[i
].present
= 1;
6356 if (skip_past_comma (&ptr
) == SUCCESS
)
6361 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6364 inst
.operands
[i
].reg
= val
;
6365 inst
.operands
[i
].isreg
= 1;
6366 inst
.operands
[i
++].present
= 1;
6368 if (skip_past_comma (&ptr
) == FAIL
)
6371 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6374 inst
.operands
[i
].reg
= val
;
6375 inst
.operands
[i
].isreg
= 1;
6376 inst
.operands
[i
].present
= 1;
6379 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6380 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6381 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6382 Case 10: VMOV.F32 <Sd>, #<imm>
6383 Case 11: VMOV.F64 <Dd>, #<imm> */
6384 inst
.operands
[i
].immisfloat
= 1;
6385 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6387 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6388 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6392 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6396 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6399 inst
.operands
[i
].reg
= val
;
6400 inst
.operands
[i
].isreg
= 1;
6401 inst
.operands
[i
++].present
= 1;
6403 if (skip_past_comma (&ptr
) == FAIL
)
6406 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6408 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6409 inst
.operands
[i
].reg
= val
;
6410 inst
.operands
[i
].isscalar
= 1;
6411 inst
.operands
[i
].present
= 1;
6412 inst
.operands
[i
].vectype
= optype
;
6414 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6416 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6417 inst
.operands
[i
].reg
= val
;
6418 inst
.operands
[i
].isreg
= 1;
6419 inst
.operands
[i
++].present
= 1;
6421 if (skip_past_comma (&ptr
) == FAIL
)
6424 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6427 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6431 inst
.operands
[i
].reg
= val
;
6432 inst
.operands
[i
].isreg
= 1;
6433 inst
.operands
[i
].isvec
= 1;
6434 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6435 inst
.operands
[i
].vectype
= optype
;
6436 inst
.operands
[i
].present
= 1;
6438 if (rtype
== REG_TYPE_VFS
)
6442 if (skip_past_comma (&ptr
) == FAIL
)
6444 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6447 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6450 inst
.operands
[i
].reg
= val
;
6451 inst
.operands
[i
].isreg
= 1;
6452 inst
.operands
[i
].isvec
= 1;
6453 inst
.operands
[i
].issingle
= 1;
6454 inst
.operands
[i
].vectype
= optype
;
6455 inst
.operands
[i
].present
= 1;
6458 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6462 inst
.operands
[i
].reg
= val
;
6463 inst
.operands
[i
].isreg
= 1;
6464 inst
.operands
[i
].isvec
= 1;
6465 inst
.operands
[i
].issingle
= 1;
6466 inst
.operands
[i
].vectype
= optype
;
6467 inst
.operands
[i
].present
= 1;
6472 first_error (_("parse error"));
6476 /* Successfully parsed the operands. Update args. */
6482 first_error (_("expected comma"));
6486 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6490 /* Use this macro when the operand constraints are different
6491 for ARM and THUMB (e.g. ldrd). */
6492 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6493 ((arm_operand) | ((thumb_operand) << 16))
6495 /* Matcher codes for parse_operands. */
6496 enum operand_parse_code
6498 OP_stop
, /* end of line */
6500 OP_RR
, /* ARM register */
6501 OP_RRnpc
, /* ARM register, not r15 */
6502 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6503 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6504 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6505 optional trailing ! */
6506 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6507 OP_RCP
, /* Coprocessor number */
6508 OP_RCN
, /* Coprocessor register */
6509 OP_RF
, /* FPA register */
6510 OP_RVS
, /* VFP single precision register */
6511 OP_RVD
, /* VFP double precision register (0..15) */
6512 OP_RND
, /* Neon double precision register (0..31) */
6513 OP_RNQ
, /* Neon quad precision register */
6514 OP_RVSD
, /* VFP single or double precision register */
6515 OP_RNSD
, /* Neon single or double precision register */
6516 OP_RNDQ
, /* Neon double or quad precision register */
6517 OP_RNSDQ
, /* Neon single, double or quad precision register */
6518 OP_RNSC
, /* Neon scalar D[X] */
6519 OP_RVC
, /* VFP control register */
6520 OP_RMF
, /* Maverick F register */
6521 OP_RMD
, /* Maverick D register */
6522 OP_RMFX
, /* Maverick FX register */
6523 OP_RMDX
, /* Maverick DX register */
6524 OP_RMAX
, /* Maverick AX register */
6525 OP_RMDS
, /* Maverick DSPSC register */
6526 OP_RIWR
, /* iWMMXt wR register */
6527 OP_RIWC
, /* iWMMXt wC register */
6528 OP_RIWG
, /* iWMMXt wCG register */
6529 OP_RXA
, /* XScale accumulator register */
6531 OP_REGLST
, /* ARM register list */
6532 OP_VRSLST
, /* VFP single-precision register list */
6533 OP_VRDLST
, /* VFP double-precision register list */
6534 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6535 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6536 OP_NSTRLST
, /* Neon element/structure list */
6538 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6539 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6540 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6541 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6542 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6543 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6544 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6545 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6546 OP_VMOV
, /* Neon VMOV operands. */
6547 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6548 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6549 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6551 OP_I0
, /* immediate zero */
6552 OP_I7
, /* immediate value 0 .. 7 */
6553 OP_I15
, /* 0 .. 15 */
6554 OP_I16
, /* 1 .. 16 */
6555 OP_I16z
, /* 0 .. 16 */
6556 OP_I31
, /* 0 .. 31 */
6557 OP_I31w
, /* 0 .. 31, optional trailing ! */
6558 OP_I32
, /* 1 .. 32 */
6559 OP_I32z
, /* 0 .. 32 */
6560 OP_I63
, /* 0 .. 63 */
6561 OP_I63s
, /* -64 .. 63 */
6562 OP_I64
, /* 1 .. 64 */
6563 OP_I64z
, /* 0 .. 64 */
6564 OP_I255
, /* 0 .. 255 */
6566 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6567 OP_I7b
, /* 0 .. 7 */
6568 OP_I15b
, /* 0 .. 15 */
6569 OP_I31b
, /* 0 .. 31 */
6571 OP_SH
, /* shifter operand */
6572 OP_SHG
, /* shifter operand with possible group relocation */
6573 OP_ADDR
, /* Memory address expression (any mode) */
6574 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6575 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6576 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6577 OP_EXP
, /* arbitrary expression */
6578 OP_EXPi
, /* same, with optional immediate prefix */
6579 OP_EXPr
, /* same, with optional relocation suffix */
6580 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6581 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6582 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6584 OP_CPSF
, /* CPS flags */
6585 OP_ENDI
, /* Endianness specifier */
6586 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6587 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6588 OP_COND
, /* conditional code */
6589 OP_TB
, /* Table branch. */
6591 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6593 OP_RRnpc_I0
, /* ARM register or literal 0 */
6594 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
6595 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6596 OP_RF_IF
, /* FPA register or immediate */
6597 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6598 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6600 /* Optional operands. */
6601 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6602 OP_oI31b
, /* 0 .. 31 */
6603 OP_oI32b
, /* 1 .. 32 */
6604 OP_oI32z
, /* 0 .. 32 */
6605 OP_oIffffb
, /* 0 .. 65535 */
6606 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6608 OP_oRR
, /* ARM register */
6609 OP_oRRnpc
, /* ARM register, not the PC */
6610 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6611 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6612 OP_oRND
, /* Optional Neon double precision register */
6613 OP_oRNQ
, /* Optional Neon quad precision register */
6614 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6615 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6616 OP_oSHll
, /* LSL immediate */
6617 OP_oSHar
, /* ASR immediate */
6618 OP_oSHllar
, /* LSL or ASR immediate */
6619 OP_oROR
, /* ROR 0/8/16/24 */
6620 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6622 /* Some pre-defined mixed (ARM/THUMB) operands. */
6623 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6624 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6625 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6627 OP_FIRST_OPTIONAL
= OP_oI7b
6630 /* Generic instruction operand parser. This does no encoding and no
6631 semantic validation; it merely squirrels values away in the inst
6632 structure. Returns SUCCESS or FAIL depending on whether the
6633 specified grammar matched. */
6635 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6637 unsigned const int *upat
= pattern
;
6638 char *backtrack_pos
= 0;
6639 const char *backtrack_error
= 0;
6640 int i
, val
= 0, backtrack_index
= 0;
6641 enum arm_reg_type rtype
;
6642 parse_operand_result result
;
6643 unsigned int op_parse_code
;
6645 #define po_char_or_fail(chr) \
6648 if (skip_past_char (&str, chr) == FAIL) \
6653 #define po_reg_or_fail(regtype) \
6656 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6657 & inst.operands[i].vectype); \
6660 first_error (_(reg_expected_msgs[regtype])); \
6663 inst.operands[i].reg = val; \
6664 inst.operands[i].isreg = 1; \
6665 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6666 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6667 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6668 || rtype == REG_TYPE_VFD \
6669 || rtype == REG_TYPE_NQ); \
6673 #define po_reg_or_goto(regtype, label) \
6676 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6677 & inst.operands[i].vectype); \
6681 inst.operands[i].reg = val; \
6682 inst.operands[i].isreg = 1; \
6683 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6684 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6685 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6686 || rtype == REG_TYPE_VFD \
6687 || rtype == REG_TYPE_NQ); \
6691 #define po_imm_or_fail(min, max, popt) \
6694 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6696 inst.operands[i].imm = val; \
6700 #define po_scalar_or_goto(elsz, label) \
6703 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6706 inst.operands[i].reg = val; \
6707 inst.operands[i].isscalar = 1; \
6711 #define po_misc_or_fail(expr) \
6719 #define po_misc_or_fail_no_backtrack(expr) \
6723 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6724 backtrack_pos = 0; \
6725 if (result != PARSE_OPERAND_SUCCESS) \
6730 #define po_barrier_or_imm(str) \
6733 val = parse_barrier (&str); \
6734 if (val == FAIL && ! ISALPHA (*str)) \
6737 /* ISB can only take SY as an option. */ \
6738 || ((inst.instruction & 0xf0) == 0x60 \
6741 inst.error = _("invalid barrier type"); \
6742 backtrack_pos = 0; \
6748 skip_whitespace (str
);
6750 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6752 op_parse_code
= upat
[i
];
6753 if (op_parse_code
>= 1<<16)
6754 op_parse_code
= thumb
? (op_parse_code
>> 16)
6755 : (op_parse_code
& ((1<<16)-1));
6757 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6759 /* Remember where we are in case we need to backtrack. */
6760 gas_assert (!backtrack_pos
);
6761 backtrack_pos
= str
;
6762 backtrack_error
= inst
.error
;
6763 backtrack_index
= i
;
6766 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6767 po_char_or_fail (',');
6769 switch (op_parse_code
)
6777 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6778 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6779 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6780 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6781 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6782 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6784 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6786 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6788 /* Also accept generic coprocessor regs for unknown registers. */
6790 po_reg_or_fail (REG_TYPE_CN
);
6792 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6793 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6794 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6795 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6796 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6797 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6798 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6799 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6800 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6801 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6803 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6804 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
6806 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6807 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6809 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6811 /* Neon scalar. Using an element size of 8 means that some invalid
6812 scalars are accepted here, so deal with those in later code. */
6813 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6817 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6820 po_imm_or_fail (0, 0, TRUE
);
6825 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6830 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6833 if (parse_ifimm_zero (&str
))
6834 inst
.operands
[i
].imm
= 0;
6838 = _("only floating point zero is allowed as immediate value");
6846 po_scalar_or_goto (8, try_rr
);
6849 po_reg_or_fail (REG_TYPE_RN
);
6855 po_scalar_or_goto (8, try_nsdq
);
6858 po_reg_or_fail (REG_TYPE_NSDQ
);
6864 po_scalar_or_goto (8, try_s_scalar
);
6867 po_scalar_or_goto (4, try_nsd
);
6870 po_reg_or_fail (REG_TYPE_NSD
);
6876 po_scalar_or_goto (8, try_ndq
);
6879 po_reg_or_fail (REG_TYPE_NDQ
);
6885 po_scalar_or_goto (8, try_vfd
);
6888 po_reg_or_fail (REG_TYPE_VFD
);
6893 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6894 not careful then bad things might happen. */
6895 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6900 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6903 /* There's a possibility of getting a 64-bit immediate here, so
6904 we need special handling. */
6905 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6908 inst
.error
= _("immediate value is out of range");
6916 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6919 po_imm_or_fail (0, 63, TRUE
);
6924 po_char_or_fail ('[');
6925 po_reg_or_fail (REG_TYPE_RN
);
6926 po_char_or_fail (']');
6932 po_reg_or_fail (REG_TYPE_RN
);
6933 if (skip_past_char (&str
, '!') == SUCCESS
)
6934 inst
.operands
[i
].writeback
= 1;
6938 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6939 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6940 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6941 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6942 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6943 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6944 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6945 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6946 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6947 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6948 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6949 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6951 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6953 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6954 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6956 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6957 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6958 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6959 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6961 /* Immediate variants */
6963 po_char_or_fail ('{');
6964 po_imm_or_fail (0, 255, TRUE
);
6965 po_char_or_fail ('}');
6969 /* The expression parser chokes on a trailing !, so we have
6970 to find it first and zap it. */
6973 while (*s
&& *s
!= ',')
6978 inst
.operands
[i
].writeback
= 1;
6980 po_imm_or_fail (0, 31, TRUE
);
6988 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6993 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6998 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
7000 if (inst
.reloc
.exp
.X_op
== O_symbol
)
7002 val
= parse_reloc (&str
);
7005 inst
.error
= _("unrecognized relocation suffix");
7008 else if (val
!= BFD_RELOC_UNUSED
)
7010 inst
.operands
[i
].imm
= val
;
7011 inst
.operands
[i
].hasreloc
= 1;
7016 /* Operand for MOVW or MOVT. */
7018 po_misc_or_fail (parse_half (&str
));
7021 /* Register or expression. */
7022 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7023 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7025 /* Register or immediate. */
7026 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7027 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7029 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7031 if (!is_immediate_prefix (*str
))
7034 val
= parse_fpa_immediate (&str
);
7037 /* FPA immediates are encoded as registers 8-15.
7038 parse_fpa_immediate has already applied the offset. */
7039 inst
.operands
[i
].reg
= val
;
7040 inst
.operands
[i
].isreg
= 1;
7043 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7044 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7046 /* Two kinds of register. */
7049 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7051 || (rege
->type
!= REG_TYPE_MMXWR
7052 && rege
->type
!= REG_TYPE_MMXWC
7053 && rege
->type
!= REG_TYPE_MMXWCG
))
7055 inst
.error
= _("iWMMXt data or control register expected");
7058 inst
.operands
[i
].reg
= rege
->number
;
7059 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7065 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7067 || (rege
->type
!= REG_TYPE_MMXWC
7068 && rege
->type
!= REG_TYPE_MMXWCG
))
7070 inst
.error
= _("iWMMXt control register expected");
7073 inst
.operands
[i
].reg
= rege
->number
;
7074 inst
.operands
[i
].isreg
= 1;
7079 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7080 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7081 case OP_oROR
: val
= parse_ror (&str
); break;
7082 case OP_COND
: val
= parse_cond (&str
); break;
7083 case OP_oBARRIER_I15
:
7084 po_barrier_or_imm (str
); break;
7086 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7092 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7093 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7095 inst
.error
= _("Banked registers are not available with this "
7101 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7105 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7108 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7110 if (strncasecmp (str
, "APSR_", 5) == 0)
7117 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7118 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7119 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7120 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7121 default: found
= 16;
7125 inst
.operands
[i
].isvec
= 1;
7126 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7127 inst
.operands
[i
].reg
= REG_PC
;
7134 po_misc_or_fail (parse_tb (&str
));
7137 /* Register lists. */
7139 val
= parse_reg_list (&str
);
7142 inst
.operands
[i
].writeback
= 1;
7148 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7152 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7156 /* Allow Q registers too. */
7157 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7162 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7164 inst
.operands
[i
].issingle
= 1;
7169 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7174 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7175 &inst
.operands
[i
].vectype
);
7178 /* Addressing modes */
7180 po_misc_or_fail (parse_address (&str
, i
));
7184 po_misc_or_fail_no_backtrack (
7185 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7189 po_misc_or_fail_no_backtrack (
7190 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7194 po_misc_or_fail_no_backtrack (
7195 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7199 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7203 po_misc_or_fail_no_backtrack (
7204 parse_shifter_operand_group_reloc (&str
, i
));
7208 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7212 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7216 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7220 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7223 /* Various value-based sanity checks and shared operations. We
7224 do not signal immediate failures for the register constraints;
7225 this allows a syntax error to take precedence. */
7226 switch (op_parse_code
)
7234 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7235 inst
.error
= BAD_PC
;
7240 if (inst
.operands
[i
].isreg
)
7242 if (inst
.operands
[i
].reg
== REG_PC
)
7243 inst
.error
= BAD_PC
;
7244 else if (inst
.operands
[i
].reg
== REG_SP
7245 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7246 relaxed since ARMv8-A. */
7247 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7250 inst
.error
= BAD_SP
;
7256 if (inst
.operands
[i
].isreg
7257 && inst
.operands
[i
].reg
== REG_PC
7258 && (inst
.operands
[i
].writeback
|| thumb
))
7259 inst
.error
= BAD_PC
;
7268 case OP_oBARRIER_I15
:
7277 inst
.operands
[i
].imm
= val
;
7284 /* If we get here, this operand was successfully parsed. */
7285 inst
.operands
[i
].present
= 1;
7289 inst
.error
= BAD_ARGS
;
7294 /* The parse routine should already have set inst.error, but set a
7295 default here just in case. */
7297 inst
.error
= _("syntax error");
7301 /* Do not backtrack over a trailing optional argument that
7302 absorbed some text. We will only fail again, with the
7303 'garbage following instruction' error message, which is
7304 probably less helpful than the current one. */
7305 if (backtrack_index
== i
&& backtrack_pos
!= str
7306 && upat
[i
+1] == OP_stop
)
7309 inst
.error
= _("syntax error");
7313 /* Try again, skipping the optional argument at backtrack_pos. */
7314 str
= backtrack_pos
;
7315 inst
.error
= backtrack_error
;
7316 inst
.operands
[backtrack_index
].present
= 0;
7317 i
= backtrack_index
;
7321 /* Check that we have parsed all the arguments. */
7322 if (*str
!= '\0' && !inst
.error
)
7323 inst
.error
= _("garbage following instruction");
7325 return inst
.error
? FAIL
: SUCCESS
;
7328 #undef po_char_or_fail
7329 #undef po_reg_or_fail
7330 #undef po_reg_or_goto
7331 #undef po_imm_or_fail
7332 #undef po_scalar_or_fail
7333 #undef po_barrier_or_imm
7335 /* Shorthand macro for instruction encoding functions issuing errors. */
7336 #define constraint(expr, err) \
7347 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7348 instructions are unpredictable if these registers are used. This
7349 is the BadReg predicate in ARM's Thumb-2 documentation.
7351 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7352 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7353 #define reject_bad_reg(reg) \
7355 if (reg == REG_PC) \
7357 inst.error = BAD_PC; \
7360 else if (reg == REG_SP \
7361 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7363 inst.error = BAD_SP; \
7368 /* If REG is R13 (the stack pointer), warn that its use is
7370 #define warn_deprecated_sp(reg) \
7372 if (warn_on_deprecated && reg == REG_SP) \
7373 as_tsktsk (_("use of r13 is deprecated")); \
7376 /* Functions for operand encoding. ARM, then Thumb. */
7378 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7380 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7382 The only binary encoding difference is the Coprocessor number. Coprocessor
7383 9 is used for half-precision calculations or conversions. The format of the
7384 instruction is the same as the equivalent Coprocessor 10 instruction that
7385 exists for Single-Precision operation. */
7388 do_scalar_fp16_v82_encode (void)
7390 if (inst
.cond
!= COND_ALWAYS
)
7391 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7392 " the behaviour is UNPREDICTABLE"));
7393 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7396 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7397 mark_feature_used (&arm_ext_fp16
);
7400 /* If VAL can be encoded in the immediate field of an ARM instruction,
7401 return the encoded form. Otherwise, return FAIL. */
7404 encode_arm_immediate (unsigned int val
)
7411 for (i
= 2; i
< 32; i
+= 2)
7412 if ((a
= rotate_left (val
, i
)) <= 0xff)
7413 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7418 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7419 return the encoded form. Otherwise, return FAIL. */
7421 encode_thumb32_immediate (unsigned int val
)
7428 for (i
= 1; i
<= 24; i
++)
7431 if ((val
& ~(0xff << i
)) == 0)
7432 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7436 if (val
== ((a
<< 16) | a
))
7438 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7442 if (val
== ((a
<< 16) | a
))
7443 return 0x200 | (a
>> 8);
7447 /* Encode a VFP SP or DP register number into inst.instruction. */
7450 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7452 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7455 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7458 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7461 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7466 first_error (_("D register out of range for selected VFP version"));
7474 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7478 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7482 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7486 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7490 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7494 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7502 /* Encode a <shift> in an ARM-format instruction. The immediate,
7503 if any, is handled by md_apply_fix. */
7505 encode_arm_shift (int i
)
7507 /* register-shifted register. */
7508 if (inst
.operands
[i
].immisreg
)
7511 for (op_index
= 0; op_index
<= i
; ++op_index
)
7513 /* Check the operand only when it's presented. In pre-UAL syntax,
7514 if the destination register is the same as the first operand, two
7515 register form of the instruction can be used. */
7516 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
7517 && inst
.operands
[op_index
].reg
== REG_PC
)
7518 as_warn (UNPRED_REG ("r15"));
7521 if (inst
.operands
[i
].imm
== REG_PC
)
7522 as_warn (UNPRED_REG ("r15"));
7525 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7526 inst
.instruction
|= SHIFT_ROR
<< 5;
7529 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7530 if (inst
.operands
[i
].immisreg
)
7532 inst
.instruction
|= SHIFT_BY_REG
;
7533 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7536 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7541 encode_arm_shifter_operand (int i
)
7543 if (inst
.operands
[i
].isreg
)
7545 inst
.instruction
|= inst
.operands
[i
].reg
;
7546 encode_arm_shift (i
);
7550 inst
.instruction
|= INST_IMMEDIATE
;
7551 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7552 inst
.instruction
|= inst
.operands
[i
].imm
;
7556 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7558 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7561 Generate an error if the operand is not a register. */
7562 constraint (!inst
.operands
[i
].isreg
,
7563 _("Instruction does not support =N addresses"));
7565 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7567 if (inst
.operands
[i
].preind
)
7571 inst
.error
= _("instruction does not accept preindexed addressing");
7574 inst
.instruction
|= PRE_INDEX
;
7575 if (inst
.operands
[i
].writeback
)
7576 inst
.instruction
|= WRITE_BACK
;
7579 else if (inst
.operands
[i
].postind
)
7581 gas_assert (inst
.operands
[i
].writeback
);
7583 inst
.instruction
|= WRITE_BACK
;
7585 else /* unindexed - only for coprocessor */
7587 inst
.error
= _("instruction does not accept unindexed addressing");
7591 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7592 && (((inst
.instruction
& 0x000f0000) >> 16)
7593 == ((inst
.instruction
& 0x0000f000) >> 12)))
7594 as_warn ((inst
.instruction
& LOAD_BIT
)
7595 ? _("destination register same as write-back base")
7596 : _("source register same as write-back base"));
7599 /* inst.operands[i] was set up by parse_address. Encode it into an
7600 ARM-format mode 2 load or store instruction. If is_t is true,
7601 reject forms that cannot be used with a T instruction (i.e. not
7604 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7606 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7608 encode_arm_addr_mode_common (i
, is_t
);
7610 if (inst
.operands
[i
].immisreg
)
7612 constraint ((inst
.operands
[i
].imm
== REG_PC
7613 || (is_pc
&& inst
.operands
[i
].writeback
)),
7615 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7616 inst
.instruction
|= inst
.operands
[i
].imm
;
7617 if (!inst
.operands
[i
].negative
)
7618 inst
.instruction
|= INDEX_UP
;
7619 if (inst
.operands
[i
].shifted
)
7621 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7622 inst
.instruction
|= SHIFT_ROR
<< 5;
7625 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7626 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7630 else /* immediate offset in inst.reloc */
7632 if (is_pc
&& !inst
.reloc
.pc_rel
)
7634 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7636 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7637 cannot use PC in addressing.
7638 PC cannot be used in writeback addressing, either. */
7639 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7642 /* Use of PC in str is deprecated for ARMv7. */
7643 if (warn_on_deprecated
7645 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7646 as_tsktsk (_("use of PC in this instruction is deprecated"));
7649 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7651 /* Prefer + for zero encoded value. */
7652 if (!inst
.operands
[i
].negative
)
7653 inst
.instruction
|= INDEX_UP
;
7654 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7659 /* inst.operands[i] was set up by parse_address. Encode it into an
7660 ARM-format mode 3 load or store instruction. Reject forms that
7661 cannot be used with such instructions. If is_t is true, reject
7662 forms that cannot be used with a T instruction (i.e. not
7665 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7667 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7669 inst
.error
= _("instruction does not accept scaled register index");
7673 encode_arm_addr_mode_common (i
, is_t
);
7675 if (inst
.operands
[i
].immisreg
)
7677 constraint ((inst
.operands
[i
].imm
== REG_PC
7678 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7680 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7682 inst
.instruction
|= inst
.operands
[i
].imm
;
7683 if (!inst
.operands
[i
].negative
)
7684 inst
.instruction
|= INDEX_UP
;
7686 else /* immediate offset in inst.reloc */
7688 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7689 && inst
.operands
[i
].writeback
),
7691 inst
.instruction
|= HWOFFSET_IMM
;
7692 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7694 /* Prefer + for zero encoded value. */
7695 if (!inst
.operands
[i
].negative
)
7696 inst
.instruction
|= INDEX_UP
;
7698 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7703 /* Write immediate bits [7:0] to the following locations:
7705 |28/24|23 19|18 16|15 4|3 0|
7706 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7708 This function is used by VMOV/VMVN/VORR/VBIC. */
7711 neon_write_immbits (unsigned immbits
)
7713 inst
.instruction
|= immbits
& 0xf;
7714 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7715 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7718 /* Invert low-order SIZE bits of XHI:XLO. */
7721 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7723 unsigned immlo
= xlo
? *xlo
: 0;
7724 unsigned immhi
= xhi
? *xhi
: 0;
7729 immlo
= (~immlo
) & 0xff;
7733 immlo
= (~immlo
) & 0xffff;
7737 immhi
= (~immhi
) & 0xffffffff;
7741 immlo
= (~immlo
) & 0xffffffff;
7755 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7759 neon_bits_same_in_bytes (unsigned imm
)
7761 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7762 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7763 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7764 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7767 /* For immediate of above form, return 0bABCD. */
7770 neon_squash_bits (unsigned imm
)
7772 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7773 | ((imm
& 0x01000000) >> 21);
7776 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7779 neon_qfloat_bits (unsigned imm
)
7781 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7784 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7785 the instruction. *OP is passed as the initial value of the op field, and
7786 may be set to a different value depending on the constant (i.e.
7787 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7788 MVN). If the immediate looks like a repeated pattern then also
7789 try smaller element sizes. */
7792 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7793 unsigned *immbits
, int *op
, int size
,
7794 enum neon_el_type type
)
7796 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7798 if (type
== NT_float
&& !float_p
)
7801 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7803 if (size
!= 32 || *op
== 1)
7805 *immbits
= neon_qfloat_bits (immlo
);
7811 if (neon_bits_same_in_bytes (immhi
)
7812 && neon_bits_same_in_bytes (immlo
))
7816 *immbits
= (neon_squash_bits (immhi
) << 4)
7817 | neon_squash_bits (immlo
);
7828 if (immlo
== (immlo
& 0x000000ff))
7833 else if (immlo
== (immlo
& 0x0000ff00))
7835 *immbits
= immlo
>> 8;
7838 else if (immlo
== (immlo
& 0x00ff0000))
7840 *immbits
= immlo
>> 16;
7843 else if (immlo
== (immlo
& 0xff000000))
7845 *immbits
= immlo
>> 24;
7848 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7850 *immbits
= (immlo
>> 8) & 0xff;
7853 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7855 *immbits
= (immlo
>> 16) & 0xff;
7859 if ((immlo
& 0xffff) != (immlo
>> 16))
7866 if (immlo
== (immlo
& 0x000000ff))
7871 else if (immlo
== (immlo
& 0x0000ff00))
7873 *immbits
= immlo
>> 8;
7877 if ((immlo
& 0xff) != (immlo
>> 8))
7882 if (immlo
== (immlo
& 0x000000ff))
7884 /* Don't allow MVN with 8-bit immediate. */
7894 #if defined BFD_HOST_64_BIT
7895 /* Returns TRUE if double precision value V may be cast
7896 to single precision without loss of accuracy. */
7899 is_double_a_single (bfd_int64_t v
)
7901 int exp
= (int)((v
>> 52) & 0x7FF);
7902 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7904 return (exp
== 0 || exp
== 0x7FF
7905 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7906 && (mantissa
& 0x1FFFFFFFl
) == 0;
7909 /* Returns a double precision value casted to single precision
7910 (ignoring the least significant bits in exponent and mantissa). */
7913 double_to_single (bfd_int64_t v
)
7915 int sign
= (int) ((v
>> 63) & 1l);
7916 int exp
= (int) ((v
>> 52) & 0x7FF);
7917 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7923 exp
= exp
- 1023 + 127;
7932 /* No denormalized numbers. */
7938 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7940 #endif /* BFD_HOST_64_BIT */
7949 static void do_vfp_nsyn_opcode (const char *);
7951 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7952 Determine whether it can be performed with a move instruction; if
7953 it can, convert inst.instruction to that move instruction and
7954 return TRUE; if it can't, convert inst.instruction to a literal-pool
7955 load and return FALSE. If this is not a valid thing to do in the
7956 current context, set inst.error and return TRUE.
7958 inst.operands[i] describes the destination register. */
7961 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7964 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7965 bfd_boolean arm_p
= (t
== CONST_ARM
);
7968 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7972 if ((inst
.instruction
& tbit
) == 0)
7974 inst
.error
= _("invalid pseudo operation");
7978 if (inst
.reloc
.exp
.X_op
!= O_constant
7979 && inst
.reloc
.exp
.X_op
!= O_symbol
7980 && inst
.reloc
.exp
.X_op
!= O_big
)
7982 inst
.error
= _("constant expression expected");
7986 if (inst
.reloc
.exp
.X_op
== O_constant
7987 || inst
.reloc
.exp
.X_op
== O_big
)
7989 #if defined BFD_HOST_64_BIT
7994 if (inst
.reloc
.exp
.X_op
== O_big
)
7996 LITTLENUM_TYPE w
[X_PRECISION
];
7999 if (inst
.reloc
.exp
.X_add_number
== -1)
8001 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8003 /* FIXME: Should we check words w[2..5] ? */
8008 #if defined BFD_HOST_64_BIT
8010 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8011 << LITTLENUM_NUMBER_OF_BITS
)
8012 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8013 << LITTLENUM_NUMBER_OF_BITS
)
8014 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8015 << LITTLENUM_NUMBER_OF_BITS
)
8016 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8018 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8019 | (l
[0] & LITTLENUM_MASK
);
8023 v
= inst
.reloc
.exp
.X_add_number
;
8025 if (!inst
.operands
[i
].issingle
)
8029 /* LDR should not use lead in a flag-setting instruction being
8030 chosen so we do not check whether movs can be used. */
8032 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8033 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8034 && inst
.operands
[i
].reg
!= 13
8035 && inst
.operands
[i
].reg
!= 15)
8037 /* Check if on thumb2 it can be done with a mov.w, mvn or
8038 movw instruction. */
8039 unsigned int newimm
;
8040 bfd_boolean isNegated
;
8042 newimm
= encode_thumb32_immediate (v
);
8043 if (newimm
!= (unsigned int) FAIL
)
8047 newimm
= encode_thumb32_immediate (~v
);
8048 if (newimm
!= (unsigned int) FAIL
)
8052 /* The number can be loaded with a mov.w or mvn
8054 if (newimm
!= (unsigned int) FAIL
8055 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8057 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8058 | (inst
.operands
[i
].reg
<< 8));
8059 /* Change to MOVN. */
8060 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8061 inst
.instruction
|= (newimm
& 0x800) << 15;
8062 inst
.instruction
|= (newimm
& 0x700) << 4;
8063 inst
.instruction
|= (newimm
& 0x0ff);
8066 /* The number can be loaded with a movw instruction. */
8067 else if ((v
& ~0xFFFF) == 0
8068 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8070 int imm
= v
& 0xFFFF;
8072 inst
.instruction
= 0xf2400000; /* MOVW. */
8073 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8074 inst
.instruction
|= (imm
& 0xf000) << 4;
8075 inst
.instruction
|= (imm
& 0x0800) << 15;
8076 inst
.instruction
|= (imm
& 0x0700) << 4;
8077 inst
.instruction
|= (imm
& 0x00ff);
8084 int value
= encode_arm_immediate (v
);
8088 /* This can be done with a mov instruction. */
8089 inst
.instruction
&= LITERAL_MASK
;
8090 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8091 inst
.instruction
|= value
& 0xfff;
8095 value
= encode_arm_immediate (~ v
);
8098 /* This can be done with a mvn instruction. */
8099 inst
.instruction
&= LITERAL_MASK
;
8100 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8101 inst
.instruction
|= value
& 0xfff;
8105 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8108 unsigned immbits
= 0;
8109 unsigned immlo
= inst
.operands
[1].imm
;
8110 unsigned immhi
= inst
.operands
[1].regisimm
8111 ? inst
.operands
[1].reg
8112 : inst
.reloc
.exp
.X_unsigned
8114 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8115 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8116 &op
, 64, NT_invtype
);
8120 neon_invert_size (&immlo
, &immhi
, 64);
8122 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8123 &op
, 64, NT_invtype
);
8128 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8134 /* Fill other bits in vmov encoding for both thumb and arm. */
8136 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8138 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8139 neon_write_immbits (immbits
);
8147 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8148 if (inst
.operands
[i
].issingle
8149 && is_quarter_float (inst
.operands
[1].imm
)
8150 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8152 inst
.operands
[1].imm
=
8153 neon_qfloat_bits (v
);
8154 do_vfp_nsyn_opcode ("fconsts");
8158 /* If our host does not support a 64-bit type then we cannot perform
8159 the following optimization. This mean that there will be a
8160 discrepancy between the output produced by an assembler built for
8161 a 32-bit-only host and the output produced from a 64-bit host, but
8162 this cannot be helped. */
8163 #if defined BFD_HOST_64_BIT
8164 else if (!inst
.operands
[1].issingle
8165 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8167 if (is_double_a_single (v
)
8168 && is_quarter_float (double_to_single (v
)))
8170 inst
.operands
[1].imm
=
8171 neon_qfloat_bits (double_to_single (v
));
8172 do_vfp_nsyn_opcode ("fconstd");
8180 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8181 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8184 inst
.operands
[1].reg
= REG_PC
;
8185 inst
.operands
[1].isreg
= 1;
8186 inst
.operands
[1].preind
= 1;
8187 inst
.reloc
.pc_rel
= 1;
8188 inst
.reloc
.type
= (thumb_p
8189 ? BFD_RELOC_ARM_THUMB_OFFSET
8191 ? BFD_RELOC_ARM_HWLITERAL
8192 : BFD_RELOC_ARM_LITERAL
));
8196 /* inst.operands[i] was set up by parse_address. Encode it into an
8197 ARM-format instruction. Reject all forms which cannot be encoded
8198 into a coprocessor load/store instruction. If wb_ok is false,
8199 reject use of writeback; if unind_ok is false, reject use of
8200 unindexed addressing. If reloc_override is not 0, use it instead
8201 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8202 (in which case it is preserved). */
8205 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8207 if (!inst
.operands
[i
].isreg
)
8210 if (! inst
.operands
[0].isvec
)
8212 inst
.error
= _("invalid co-processor operand");
8215 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8219 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8221 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8223 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8225 gas_assert (!inst
.operands
[i
].writeback
);
8228 inst
.error
= _("instruction does not support unindexed addressing");
8231 inst
.instruction
|= inst
.operands
[i
].imm
;
8232 inst
.instruction
|= INDEX_UP
;
8236 if (inst
.operands
[i
].preind
)
8237 inst
.instruction
|= PRE_INDEX
;
8239 if (inst
.operands
[i
].writeback
)
8241 if (inst
.operands
[i
].reg
== REG_PC
)
8243 inst
.error
= _("pc may not be used with write-back");
8248 inst
.error
= _("instruction does not support writeback");
8251 inst
.instruction
|= WRITE_BACK
;
8255 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8256 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8257 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8258 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8261 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8263 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8266 /* Prefer + for zero encoded value. */
8267 if (!inst
.operands
[i
].negative
)
8268 inst
.instruction
|= INDEX_UP
;
8273 /* Functions for instruction encoding, sorted by sub-architecture.
8274 First some generics; their names are taken from the conventional
8275 bit positions for register arguments in ARM format instructions. */
8285 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8291 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8297 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8298 inst
.instruction
|= inst
.operands
[1].reg
;
8304 inst
.instruction
|= inst
.operands
[0].reg
;
8305 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8311 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8312 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8318 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8319 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8325 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8326 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8330 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8332 if (ARM_CPU_IS_ANY (cpu_variant
))
8334 as_tsktsk ("%s", msg
);
8337 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8349 unsigned Rn
= inst
.operands
[2].reg
;
8350 /* Enforce restrictions on SWP instruction. */
8351 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8353 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8354 _("Rn must not overlap other operands"));
8356 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8358 if (!check_obsolete (&arm_ext_v8
,
8359 _("swp{b} use is obsoleted for ARMv8 and later"))
8360 && warn_on_deprecated
8361 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8362 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8365 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8366 inst
.instruction
|= inst
.operands
[1].reg
;
8367 inst
.instruction
|= Rn
<< 16;
8373 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8374 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8375 inst
.instruction
|= inst
.operands
[2].reg
;
8381 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8382 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8383 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8384 || inst
.reloc
.exp
.X_add_number
!= 0),
8386 inst
.instruction
|= inst
.operands
[0].reg
;
8387 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8388 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8394 inst
.instruction
|= inst
.operands
[0].imm
;
8400 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8401 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8404 /* ARM instructions, in alphabetical order by function name (except
8405 that wrapper functions appear immediately after the function they
8408 /* This is a pseudo-op of the form "adr rd, label" to be converted
8409 into a relative address of the form "add rd, pc, #label-.-8". */
8414 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8416 /* Frag hacking will turn this into a sub instruction if the offset turns
8417 out to be negative. */
8418 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8419 inst
.reloc
.pc_rel
= 1;
8420 inst
.reloc
.exp
.X_add_number
-= 8;
8422 if (support_interwork
8423 && inst
.reloc
.exp
.X_op
== O_symbol
8424 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8425 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8426 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8427 inst
.reloc
.exp
.X_add_number
|= 1;
8430 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8431 into a relative address of the form:
8432 add rd, pc, #low(label-.-8)"
8433 add rd, rd, #high(label-.-8)" */
8438 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8440 /* Frag hacking will turn this into a sub instruction if the offset turns
8441 out to be negative. */
8442 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8443 inst
.reloc
.pc_rel
= 1;
8444 inst
.size
= INSN_SIZE
* 2;
8445 inst
.reloc
.exp
.X_add_number
-= 8;
8447 if (support_interwork
8448 && inst
.reloc
.exp
.X_op
== O_symbol
8449 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8450 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8451 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8452 inst
.reloc
.exp
.X_add_number
|= 1;
8458 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8459 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8461 if (!inst
.operands
[1].present
)
8462 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8463 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8464 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8465 encode_arm_shifter_operand (2);
8471 if (inst
.operands
[0].present
)
8472 inst
.instruction
|= inst
.operands
[0].imm
;
8474 inst
.instruction
|= 0xf;
8480 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8481 constraint (msb
> 32, _("bit-field extends past end of register"));
8482 /* The instruction encoding stores the LSB and MSB,
8483 not the LSB and width. */
8484 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8485 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8486 inst
.instruction
|= (msb
- 1) << 16;
8494 /* #0 in second position is alternative syntax for bfc, which is
8495 the same instruction but with REG_PC in the Rm field. */
8496 if (!inst
.operands
[1].isreg
)
8497 inst
.operands
[1].reg
= REG_PC
;
8499 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8500 constraint (msb
> 32, _("bit-field extends past end of register"));
8501 /* The instruction encoding stores the LSB and MSB,
8502 not the LSB and width. */
8503 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8504 inst
.instruction
|= inst
.operands
[1].reg
;
8505 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8506 inst
.instruction
|= (msb
- 1) << 16;
8512 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8513 _("bit-field extends past end of register"));
8514 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8515 inst
.instruction
|= inst
.operands
[1].reg
;
8516 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8517 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8520 /* ARM V5 breakpoint instruction (argument parse)
8521 BKPT <16 bit unsigned immediate>
8522 Instruction is not conditional.
8523 The bit pattern given in insns[] has the COND_ALWAYS condition,
8524 and it is an error if the caller tried to override that. */
8529 /* Top 12 of 16 bits to bits 19:8. */
8530 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8532 /* Bottom 4 of 16 bits to bits 3:0. */
8533 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8537 encode_branch (int default_reloc
)
8539 if (inst
.operands
[0].hasreloc
)
8541 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8542 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8543 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8544 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8545 ? BFD_RELOC_ARM_PLT32
8546 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8549 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8550 inst
.reloc
.pc_rel
= 1;
8557 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8558 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8561 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8568 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8570 if (inst
.cond
== COND_ALWAYS
)
8571 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8573 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8577 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8580 /* ARM V5 branch-link-exchange instruction (argument parse)
8581 BLX <target_addr> ie BLX(1)
8582 BLX{<condition>} <Rm> ie BLX(2)
8583 Unfortunately, there are two different opcodes for this mnemonic.
8584 So, the insns[].value is not used, and the code here zaps values
8585 into inst.instruction.
8586 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8591 if (inst
.operands
[0].isreg
)
8593 /* Arg is a register; the opcode provided by insns[] is correct.
8594 It is not illegal to do "blx pc", just useless. */
8595 if (inst
.operands
[0].reg
== REG_PC
)
8596 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8598 inst
.instruction
|= inst
.operands
[0].reg
;
8602 /* Arg is an address; this instruction cannot be executed
8603 conditionally, and the opcode must be adjusted.
8604 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8605 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8606 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8607 inst
.instruction
= 0xfa000000;
8608 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8615 bfd_boolean want_reloc
;
8617 if (inst
.operands
[0].reg
== REG_PC
)
8618 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8620 inst
.instruction
|= inst
.operands
[0].reg
;
8621 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8622 it is for ARMv4t or earlier. */
8623 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8624 if (!ARM_FEATURE_ZERO (selected_object_arch
)
8625 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
8629 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8634 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8638 /* ARM v5TEJ. Jump to Jazelle code. */
8643 if (inst
.operands
[0].reg
== REG_PC
)
8644 as_tsktsk (_("use of r15 in bxj is not really useful"));
8646 inst
.instruction
|= inst
.operands
[0].reg
;
8649 /* Co-processor data operation:
8650 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8651 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8655 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8656 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8657 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8658 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8659 inst
.instruction
|= inst
.operands
[4].reg
;
8660 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8666 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8667 encode_arm_shifter_operand (1);
8670 /* Transfer between coprocessor and ARM registers.
8671 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8676 No special properties. */
8678 struct deprecated_coproc_regs_s
8685 arm_feature_set deprecated
;
8686 arm_feature_set obsoleted
;
8687 const char *dep_msg
;
8688 const char *obs_msg
;
8691 #define DEPR_ACCESS_V8 \
8692 N_("This coprocessor register access is deprecated in ARMv8")
8694 /* Table of all deprecated coprocessor registers. */
8695 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8697 {15, 0, 7, 10, 5, /* CP15DMB. */
8698 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8699 DEPR_ACCESS_V8
, NULL
},
8700 {15, 0, 7, 10, 4, /* CP15DSB. */
8701 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8702 DEPR_ACCESS_V8
, NULL
},
8703 {15, 0, 7, 5, 4, /* CP15ISB. */
8704 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8705 DEPR_ACCESS_V8
, NULL
},
8706 {14, 6, 1, 0, 0, /* TEEHBR. */
8707 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8708 DEPR_ACCESS_V8
, NULL
},
8709 {14, 6, 0, 0, 0, /* TEECR. */
8710 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8711 DEPR_ACCESS_V8
, NULL
},
8714 #undef DEPR_ACCESS_V8
8716 static const size_t deprecated_coproc_reg_count
=
8717 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8725 Rd
= inst
.operands
[2].reg
;
8728 if (inst
.instruction
== 0xee000010
8729 || inst
.instruction
== 0xfe000010)
8731 reject_bad_reg (Rd
);
8732 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8734 constraint (Rd
== REG_SP
, BAD_SP
);
8739 if (inst
.instruction
== 0xe000010)
8740 constraint (Rd
== REG_PC
, BAD_PC
);
8743 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8745 const struct deprecated_coproc_regs_s
*r
=
8746 deprecated_coproc_regs
+ i
;
8748 if (inst
.operands
[0].reg
== r
->cp
8749 && inst
.operands
[1].imm
== r
->opc1
8750 && inst
.operands
[3].reg
== r
->crn
8751 && inst
.operands
[4].reg
== r
->crm
8752 && inst
.operands
[5].imm
== r
->opc2
)
8754 if (! ARM_CPU_IS_ANY (cpu_variant
)
8755 && warn_on_deprecated
8756 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8757 as_tsktsk ("%s", r
->dep_msg
);
8761 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8762 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8763 inst
.instruction
|= Rd
<< 12;
8764 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8765 inst
.instruction
|= inst
.operands
[4].reg
;
8766 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8769 /* Transfer between coprocessor register and pair of ARM registers.
8770 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8775 Two XScale instructions are special cases of these:
8777 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8778 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8780 Result unpredictable if Rd or Rn is R15. */
8787 Rd
= inst
.operands
[2].reg
;
8788 Rn
= inst
.operands
[3].reg
;
8792 reject_bad_reg (Rd
);
8793 reject_bad_reg (Rn
);
8797 constraint (Rd
== REG_PC
, BAD_PC
);
8798 constraint (Rn
== REG_PC
, BAD_PC
);
8801 /* Only check the MRRC{2} variants. */
8802 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8804 /* If Rd == Rn, error that the operation is
8805 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8806 constraint (Rd
== Rn
, BAD_OVERLAP
);
8809 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8810 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8811 inst
.instruction
|= Rd
<< 12;
8812 inst
.instruction
|= Rn
<< 16;
8813 inst
.instruction
|= inst
.operands
[4].reg
;
8819 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8820 if (inst
.operands
[1].present
)
8822 inst
.instruction
|= CPSI_MMOD
;
8823 inst
.instruction
|= inst
.operands
[1].imm
;
8830 inst
.instruction
|= inst
.operands
[0].imm
;
8836 unsigned Rd
, Rn
, Rm
;
8838 Rd
= inst
.operands
[0].reg
;
8839 Rn
= (inst
.operands
[1].present
8840 ? inst
.operands
[1].reg
: Rd
);
8841 Rm
= inst
.operands
[2].reg
;
8843 constraint ((Rd
== REG_PC
), BAD_PC
);
8844 constraint ((Rn
== REG_PC
), BAD_PC
);
8845 constraint ((Rm
== REG_PC
), BAD_PC
);
8847 inst
.instruction
|= Rd
<< 16;
8848 inst
.instruction
|= Rn
<< 0;
8849 inst
.instruction
|= Rm
<< 8;
8855 /* There is no IT instruction in ARM mode. We
8856 process it to do the validation as if in
8857 thumb mode, just in case the code gets
8858 assembled for thumb using the unified syntax. */
8863 set_it_insn_type (IT_INSN
);
8864 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8865 now_it
.cc
= inst
.operands
[0].imm
;
8869 /* If there is only one register in the register list,
8870 then return its register number. Otherwise return -1. */
8872 only_one_reg_in_list (int range
)
8874 int i
= ffs (range
) - 1;
8875 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8879 encode_ldmstm(int from_push_pop_mnem
)
8881 int base_reg
= inst
.operands
[0].reg
;
8882 int range
= inst
.operands
[1].imm
;
8885 inst
.instruction
|= base_reg
<< 16;
8886 inst
.instruction
|= range
;
8888 if (inst
.operands
[1].writeback
)
8889 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8891 if (inst
.operands
[0].writeback
)
8893 inst
.instruction
|= WRITE_BACK
;
8894 /* Check for unpredictable uses of writeback. */
8895 if (inst
.instruction
& LOAD_BIT
)
8897 /* Not allowed in LDM type 2. */
8898 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8899 && ((range
& (1 << REG_PC
)) == 0))
8900 as_warn (_("writeback of base register is UNPREDICTABLE"));
8901 /* Only allowed if base reg not in list for other types. */
8902 else if (range
& (1 << base_reg
))
8903 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8907 /* Not allowed for type 2. */
8908 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8909 as_warn (_("writeback of base register is UNPREDICTABLE"));
8910 /* Only allowed if base reg not in list, or first in list. */
8911 else if ((range
& (1 << base_reg
))
8912 && (range
& ((1 << base_reg
) - 1)))
8913 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8917 /* If PUSH/POP has only one register, then use the A2 encoding. */
8918 one_reg
= only_one_reg_in_list (range
);
8919 if (from_push_pop_mnem
&& one_reg
>= 0)
8921 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8923 if (is_push
&& one_reg
== 13 /* SP */)
8924 /* PR 22483: The A2 encoding cannot be used when
8925 pushing the stack pointer as this is UNPREDICTABLE. */
8928 inst
.instruction
&= A_COND_MASK
;
8929 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8930 inst
.instruction
|= one_reg
<< 12;
8937 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8940 /* ARMv5TE load-consecutive (argument parse)
8949 constraint (inst
.operands
[0].reg
% 2 != 0,
8950 _("first transfer register must be even"));
8951 constraint (inst
.operands
[1].present
8952 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8953 _("can only transfer two consecutive registers"));
8954 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8955 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8957 if (!inst
.operands
[1].present
)
8958 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8960 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8961 register and the first register written; we have to diagnose
8962 overlap between the base and the second register written here. */
8964 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8965 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8966 as_warn (_("base register written back, and overlaps "
8967 "second transfer register"));
8969 if (!(inst
.instruction
& V4_STR_BIT
))
8971 /* For an index-register load, the index register must not overlap the
8972 destination (even if not write-back). */
8973 if (inst
.operands
[2].immisreg
8974 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8975 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8976 as_warn (_("index register overlaps transfer register"));
8978 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8979 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8985 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8986 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8987 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8988 || inst
.operands
[1].negative
8989 /* This can arise if the programmer has written
8991 or if they have mistakenly used a register name as the last
8994 It is very difficult to distinguish between these two cases
8995 because "rX" might actually be a label. ie the register
8996 name has been occluded by a symbol of the same name. So we
8997 just generate a general 'bad addressing mode' type error
8998 message and leave it up to the programmer to discover the
8999 true cause and fix their mistake. */
9000 || (inst
.operands
[1].reg
== REG_PC
),
9003 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9004 || inst
.reloc
.exp
.X_add_number
!= 0,
9005 _("offset must be zero in ARM encoding"));
9007 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9009 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9010 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9011 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9017 constraint (inst
.operands
[0].reg
% 2 != 0,
9018 _("even register required"));
9019 constraint (inst
.operands
[1].present
9020 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9021 _("can only load two consecutive registers"));
9022 /* If op 1 were present and equal to PC, this function wouldn't
9023 have been called in the first place. */
9024 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9026 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9027 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9030 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9031 which is not a multiple of four is UNPREDICTABLE. */
9033 check_ldr_r15_aligned (void)
9035 constraint (!(inst
.operands
[1].immisreg
)
9036 && (inst
.operands
[0].reg
== REG_PC
9037 && inst
.operands
[1].reg
== REG_PC
9038 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
9039 _("ldr to register 15 must be 4-byte aligned"));
9045 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9046 if (!inst
.operands
[1].isreg
)
9047 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9049 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9050 check_ldr_r15_aligned ();
9056 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9058 if (inst
.operands
[1].preind
)
9060 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9061 || inst
.reloc
.exp
.X_add_number
!= 0,
9062 _("this instruction requires a post-indexed address"));
9064 inst
.operands
[1].preind
= 0;
9065 inst
.operands
[1].postind
= 1;
9066 inst
.operands
[1].writeback
= 1;
9068 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9069 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9072 /* Halfword and signed-byte load/store operations. */
9077 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9078 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9079 if (!inst
.operands
[1].isreg
)
9080 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9082 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9088 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9090 if (inst
.operands
[1].preind
)
9092 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9093 || inst
.reloc
.exp
.X_add_number
!= 0,
9094 _("this instruction requires a post-indexed address"));
9096 inst
.operands
[1].preind
= 0;
9097 inst
.operands
[1].postind
= 1;
9098 inst
.operands
[1].writeback
= 1;
9100 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9101 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9104 /* Co-processor register load/store.
9105 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9109 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9110 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9111 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9117 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9118 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9119 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9120 && !(inst
.instruction
& 0x00400000))
9121 as_tsktsk (_("Rd and Rm should be different in mla"));
9123 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9124 inst
.instruction
|= inst
.operands
[1].reg
;
9125 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9126 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9132 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9133 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9135 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9136 encode_arm_shifter_operand (1);
9139 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9146 top
= (inst
.instruction
& 0x00400000) != 0;
9147 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9148 _(":lower16: not allowed in this instruction"));
9149 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9150 _(":upper16: not allowed in this instruction"));
9151 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9152 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9154 imm
= inst
.reloc
.exp
.X_add_number
;
9155 /* The value is in two pieces: 0:11, 16:19. */
9156 inst
.instruction
|= (imm
& 0x00000fff);
9157 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9162 do_vfp_nsyn_mrs (void)
9164 if (inst
.operands
[0].isvec
)
9166 if (inst
.operands
[1].reg
!= 1)
9167 first_error (_("operand 1 must be FPSCR"));
9168 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9169 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9170 do_vfp_nsyn_opcode ("fmstat");
9172 else if (inst
.operands
[1].isvec
)
9173 do_vfp_nsyn_opcode ("fmrx");
9181 do_vfp_nsyn_msr (void)
9183 if (inst
.operands
[0].isvec
)
9184 do_vfp_nsyn_opcode ("fmxr");
9194 unsigned Rt
= inst
.operands
[0].reg
;
9196 if (thumb_mode
&& Rt
== REG_SP
)
9198 inst
.error
= BAD_SP
;
9202 /* MVFR2 is only valid at ARMv8-A. */
9203 if (inst
.operands
[1].reg
== 5)
9204 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9207 /* APSR_ sets isvec. All other refs to PC are illegal. */
9208 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9210 inst
.error
= BAD_PC
;
9214 /* If we get through parsing the register name, we just insert the number
9215 generated into the instruction without further validation. */
9216 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9217 inst
.instruction
|= (Rt
<< 12);
9223 unsigned Rt
= inst
.operands
[1].reg
;
9226 reject_bad_reg (Rt
);
9227 else if (Rt
== REG_PC
)
9229 inst
.error
= BAD_PC
;
9233 /* MVFR2 is only valid for ARMv8-A. */
9234 if (inst
.operands
[0].reg
== 5)
9235 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9238 /* If we get through parsing the register name, we just insert the number
9239 generated into the instruction without further validation. */
9240 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9241 inst
.instruction
|= (Rt
<< 12);
9249 if (do_vfp_nsyn_mrs () == SUCCESS
)
9252 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9253 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9255 if (inst
.operands
[1].isreg
)
9257 br
= inst
.operands
[1].reg
;
9258 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9259 as_bad (_("bad register for mrs"));
9263 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9264 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9266 _("'APSR', 'CPSR' or 'SPSR' expected"));
9267 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9270 inst
.instruction
|= br
;
9273 /* Two possible forms:
9274 "{C|S}PSR_<field>, Rm",
9275 "{C|S}PSR_f, #expression". */
9280 if (do_vfp_nsyn_msr () == SUCCESS
)
9283 inst
.instruction
|= inst
.operands
[0].imm
;
9284 if (inst
.operands
[1].isreg
)
9285 inst
.instruction
|= inst
.operands
[1].reg
;
9288 inst
.instruction
|= INST_IMMEDIATE
;
9289 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9290 inst
.reloc
.pc_rel
= 0;
9297 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9299 if (!inst
.operands
[2].present
)
9300 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9301 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9302 inst
.instruction
|= inst
.operands
[1].reg
;
9303 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9305 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9306 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9307 as_tsktsk (_("Rd and Rm should be different in mul"));
9310 /* Long Multiply Parser
9311 UMULL RdLo, RdHi, Rm, Rs
9312 SMULL RdLo, RdHi, Rm, Rs
9313 UMLAL RdLo, RdHi, Rm, Rs
9314 SMLAL RdLo, RdHi, Rm, Rs. */
9319 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9320 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9321 inst
.instruction
|= inst
.operands
[2].reg
;
9322 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9324 /* rdhi and rdlo must be different. */
9325 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9326 as_tsktsk (_("rdhi and rdlo must be different"));
9328 /* rdhi, rdlo and rm must all be different before armv6. */
9329 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9330 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9331 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9332 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9338 if (inst
.operands
[0].present
9339 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9341 /* Architectural NOP hints are CPSR sets with no bits selected. */
9342 inst
.instruction
&= 0xf0000000;
9343 inst
.instruction
|= 0x0320f000;
9344 if (inst
.operands
[0].present
)
9345 inst
.instruction
|= inst
.operands
[0].imm
;
9349 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9350 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9351 Condition defaults to COND_ALWAYS.
9352 Error if Rd, Rn or Rm are R15. */
9357 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9358 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9359 inst
.instruction
|= inst
.operands
[2].reg
;
9360 if (inst
.operands
[3].present
)
9361 encode_arm_shift (3);
9364 /* ARM V6 PKHTB (Argument Parse). */
9369 if (!inst
.operands
[3].present
)
9371 /* If the shift specifier is omitted, turn the instruction
9372 into pkhbt rd, rm, rn. */
9373 inst
.instruction
&= 0xfff00010;
9374 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9375 inst
.instruction
|= inst
.operands
[1].reg
;
9376 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9380 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9381 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9382 inst
.instruction
|= inst
.operands
[2].reg
;
9383 encode_arm_shift (3);
9387 /* ARMv5TE: Preload-Cache
9388 MP Extensions: Preload for write
9392 Syntactically, like LDR with B=1, W=0, L=1. */
9397 constraint (!inst
.operands
[0].isreg
,
9398 _("'[' expected after PLD mnemonic"));
9399 constraint (inst
.operands
[0].postind
,
9400 _("post-indexed expression used in preload instruction"));
9401 constraint (inst
.operands
[0].writeback
,
9402 _("writeback used in preload instruction"));
9403 constraint (!inst
.operands
[0].preind
,
9404 _("unindexed addressing used in preload instruction"));
9405 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9408 /* ARMv7: PLI <addr_mode> */
9412 constraint (!inst
.operands
[0].isreg
,
9413 _("'[' expected after PLI mnemonic"));
9414 constraint (inst
.operands
[0].postind
,
9415 _("post-indexed expression used in preload instruction"));
9416 constraint (inst
.operands
[0].writeback
,
9417 _("writeback used in preload instruction"));
9418 constraint (!inst
.operands
[0].preind
,
9419 _("unindexed addressing used in preload instruction"));
9420 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9421 inst
.instruction
&= ~PRE_INDEX
;
9427 constraint (inst
.operands
[0].writeback
,
9428 _("push/pop do not support {reglist}^"));
9429 inst
.operands
[1] = inst
.operands
[0];
9430 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9431 inst
.operands
[0].isreg
= 1;
9432 inst
.operands
[0].writeback
= 1;
9433 inst
.operands
[0].reg
= REG_SP
;
9434 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9437 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9438 word at the specified address and the following word
9440 Unconditionally executed.
9441 Error if Rn is R15. */
9446 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9447 if (inst
.operands
[0].writeback
)
9448 inst
.instruction
|= WRITE_BACK
;
9451 /* ARM V6 ssat (argument parse). */
9456 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9457 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9458 inst
.instruction
|= inst
.operands
[2].reg
;
9460 if (inst
.operands
[3].present
)
9461 encode_arm_shift (3);
9464 /* ARM V6 usat (argument parse). */
9469 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9470 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9471 inst
.instruction
|= inst
.operands
[2].reg
;
9473 if (inst
.operands
[3].present
)
9474 encode_arm_shift (3);
9477 /* ARM V6 ssat16 (argument parse). */
9482 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9483 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9484 inst
.instruction
|= inst
.operands
[2].reg
;
9490 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9491 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9492 inst
.instruction
|= inst
.operands
[2].reg
;
9495 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9496 preserving the other bits.
9498 setend <endian_specifier>, where <endian_specifier> is either
9504 if (warn_on_deprecated
9505 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9506 as_tsktsk (_("setend use is deprecated for ARMv8"));
9508 if (inst
.operands
[0].imm
)
9509 inst
.instruction
|= 0x200;
9515 unsigned int Rm
= (inst
.operands
[1].present
9516 ? inst
.operands
[1].reg
9517 : inst
.operands
[0].reg
);
9519 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9520 inst
.instruction
|= Rm
;
9521 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9523 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9524 inst
.instruction
|= SHIFT_BY_REG
;
9525 /* PR 12854: Error on extraneous shifts. */
9526 constraint (inst
.operands
[2].shifted
,
9527 _("extraneous shift as part of operand to shift insn"));
9530 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9536 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9537 inst
.reloc
.pc_rel
= 0;
9543 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9544 inst
.reloc
.pc_rel
= 0;
9550 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9551 inst
.reloc
.pc_rel
= 0;
9557 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9558 _("selected processor does not support SETPAN instruction"));
9560 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9566 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9567 _("selected processor does not support SETPAN instruction"));
9569 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9572 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9573 SMLAxy{cond} Rd,Rm,Rs,Rn
9574 SMLAWy{cond} Rd,Rm,Rs,Rn
9575 Error if any register is R15. */
9580 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9581 inst
.instruction
|= inst
.operands
[1].reg
;
9582 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9583 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9586 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9587 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9588 Error if any register is R15.
9589 Warning if Rdlo == Rdhi. */
9594 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9595 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9596 inst
.instruction
|= inst
.operands
[2].reg
;
9597 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9599 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9600 as_tsktsk (_("rdhi and rdlo must be different"));
9603 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9604 SMULxy{cond} Rd,Rm,Rs
9605 Error if any register is R15. */
9610 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9611 inst
.instruction
|= inst
.operands
[1].reg
;
9612 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9615 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9616 the same for both ARM and Thumb-2. */
9623 if (inst
.operands
[0].present
)
9625 reg
= inst
.operands
[0].reg
;
9626 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9631 inst
.instruction
|= reg
<< 16;
9632 inst
.instruction
|= inst
.operands
[1].imm
;
9633 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9634 inst
.instruction
|= WRITE_BACK
;
9637 /* ARM V6 strex (argument parse). */
9642 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9643 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9644 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9645 || inst
.operands
[2].negative
9646 /* See comment in do_ldrex(). */
9647 || (inst
.operands
[2].reg
== REG_PC
),
9650 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9651 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9653 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9654 || inst
.reloc
.exp
.X_add_number
!= 0,
9655 _("offset must be zero in ARM encoding"));
9657 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9658 inst
.instruction
|= inst
.operands
[1].reg
;
9659 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9660 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9666 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9667 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9668 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9669 || inst
.operands
[2].negative
,
9672 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9673 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9681 constraint (inst
.operands
[1].reg
% 2 != 0,
9682 _("even register required"));
9683 constraint (inst
.operands
[2].present
9684 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9685 _("can only store two consecutive registers"));
9686 /* If op 2 were present and equal to PC, this function wouldn't
9687 have been called in the first place. */
9688 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9690 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9691 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9692 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9695 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9696 inst
.instruction
|= inst
.operands
[1].reg
;
9697 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9704 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9705 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9713 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9714 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9719 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9720 extends it to 32-bits, and adds the result to a value in another
9721 register. You can specify a rotation by 0, 8, 16, or 24 bits
9722 before extracting the 16-bit value.
9723 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9724 Condition defaults to COND_ALWAYS.
9725 Error if any register uses R15. */
9730 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9731 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9732 inst
.instruction
|= inst
.operands
[2].reg
;
9733 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9738 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9739 Condition defaults to COND_ALWAYS.
9740 Error if any register uses R15. */
9745 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9746 inst
.instruction
|= inst
.operands
[1].reg
;
9747 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9750 /* VFP instructions. In a logical order: SP variant first, monad
9751 before dyad, arithmetic then move then load/store. */
9754 do_vfp_sp_monadic (void)
9756 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9757 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9761 do_vfp_sp_dyadic (void)
9763 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9764 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9765 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9769 do_vfp_sp_compare_z (void)
9771 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9775 do_vfp_dp_sp_cvt (void)
9777 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9778 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9782 do_vfp_sp_dp_cvt (void)
9784 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9785 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9789 do_vfp_reg_from_sp (void)
9791 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9792 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9796 do_vfp_reg2_from_sp2 (void)
9798 constraint (inst
.operands
[2].imm
!= 2,
9799 _("only two consecutive VFP SP registers allowed here"));
9800 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9801 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9802 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9806 do_vfp_sp_from_reg (void)
9808 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9809 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9813 do_vfp_sp2_from_reg2 (void)
9815 constraint (inst
.operands
[0].imm
!= 2,
9816 _("only two consecutive VFP SP registers allowed here"));
9817 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9818 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9819 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9823 do_vfp_sp_ldst (void)
9825 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9826 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9830 do_vfp_dp_ldst (void)
9832 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9833 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9838 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9840 if (inst
.operands
[0].writeback
)
9841 inst
.instruction
|= WRITE_BACK
;
9843 constraint (ldstm_type
!= VFP_LDSTMIA
,
9844 _("this addressing mode requires base-register writeback"));
9845 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9846 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9847 inst
.instruction
|= inst
.operands
[1].imm
;
9851 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9855 if (inst
.operands
[0].writeback
)
9856 inst
.instruction
|= WRITE_BACK
;
9858 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9859 _("this addressing mode requires base-register writeback"));
9861 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9862 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9864 count
= inst
.operands
[1].imm
<< 1;
9865 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9868 inst
.instruction
|= count
;
9872 do_vfp_sp_ldstmia (void)
9874 vfp_sp_ldstm (VFP_LDSTMIA
);
9878 do_vfp_sp_ldstmdb (void)
9880 vfp_sp_ldstm (VFP_LDSTMDB
);
9884 do_vfp_dp_ldstmia (void)
9886 vfp_dp_ldstm (VFP_LDSTMIA
);
9890 do_vfp_dp_ldstmdb (void)
9892 vfp_dp_ldstm (VFP_LDSTMDB
);
9896 do_vfp_xp_ldstmia (void)
9898 vfp_dp_ldstm (VFP_LDSTMIAX
);
9902 do_vfp_xp_ldstmdb (void)
9904 vfp_dp_ldstm (VFP_LDSTMDBX
);
9908 do_vfp_dp_rd_rm (void)
9910 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9911 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9915 do_vfp_dp_rn_rd (void)
9917 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9918 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9922 do_vfp_dp_rd_rn (void)
9924 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9925 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9929 do_vfp_dp_rd_rn_rm (void)
9931 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9932 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9933 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9939 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9943 do_vfp_dp_rm_rd_rn (void)
9945 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9946 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9947 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9950 /* VFPv3 instructions. */
9952 do_vfp_sp_const (void)
9954 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9955 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9956 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9960 do_vfp_dp_const (void)
9962 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9963 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9964 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9968 vfp_conv (int srcsize
)
9970 int immbits
= srcsize
- inst
.operands
[1].imm
;
9972 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9974 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9975 i.e. immbits must be in range 0 - 16. */
9976 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9979 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9981 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9982 i.e. immbits must be in range 0 - 31. */
9983 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9987 inst
.instruction
|= (immbits
& 1) << 5;
9988 inst
.instruction
|= (immbits
>> 1);
9992 do_vfp_sp_conv_16 (void)
9994 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9999 do_vfp_dp_conv_16 (void)
10001 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10006 do_vfp_sp_conv_32 (void)
10008 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10013 do_vfp_dp_conv_32 (void)
10015 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10019 /* FPA instructions. Also in a logical order. */
10024 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10025 inst
.instruction
|= inst
.operands
[1].reg
;
10029 do_fpa_ldmstm (void)
10031 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10032 switch (inst
.operands
[1].imm
)
10034 case 1: inst
.instruction
|= CP_T_X
; break;
10035 case 2: inst
.instruction
|= CP_T_Y
; break;
10036 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10041 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10043 /* The instruction specified "ea" or "fd", so we can only accept
10044 [Rn]{!}. The instruction does not really support stacking or
10045 unstacking, so we have to emulate these by setting appropriate
10046 bits and offsets. */
10047 constraint (inst
.reloc
.exp
.X_op
!= O_constant
10048 || inst
.reloc
.exp
.X_add_number
!= 0,
10049 _("this instruction does not support indexing"));
10051 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10052 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10054 if (!(inst
.instruction
& INDEX_UP
))
10055 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
10057 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10059 inst
.operands
[2].preind
= 0;
10060 inst
.operands
[2].postind
= 1;
10064 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10067 /* iWMMXt instructions: strictly in alphabetical order. */
10070 do_iwmmxt_tandorc (void)
10072 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10076 do_iwmmxt_textrc (void)
10078 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10079 inst
.instruction
|= inst
.operands
[1].imm
;
10083 do_iwmmxt_textrm (void)
10085 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10086 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10087 inst
.instruction
|= inst
.operands
[2].imm
;
10091 do_iwmmxt_tinsr (void)
10093 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10094 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10095 inst
.instruction
|= inst
.operands
[2].imm
;
10099 do_iwmmxt_tmia (void)
10101 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10102 inst
.instruction
|= inst
.operands
[1].reg
;
10103 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10107 do_iwmmxt_waligni (void)
10109 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10110 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10111 inst
.instruction
|= inst
.operands
[2].reg
;
10112 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10116 do_iwmmxt_wmerge (void)
10118 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10119 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10120 inst
.instruction
|= inst
.operands
[2].reg
;
10121 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10125 do_iwmmxt_wmov (void)
10127 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10128 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10129 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10130 inst
.instruction
|= inst
.operands
[1].reg
;
10134 do_iwmmxt_wldstbh (void)
10137 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10139 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10141 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10142 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10146 do_iwmmxt_wldstw (void)
10148 /* RIWR_RIWC clears .isreg for a control register. */
10149 if (!inst
.operands
[0].isreg
)
10151 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10152 inst
.instruction
|= 0xf0000000;
10155 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10156 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10160 do_iwmmxt_wldstd (void)
10162 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10163 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10164 && inst
.operands
[1].immisreg
)
10166 inst
.instruction
&= ~0x1a000ff;
10167 inst
.instruction
|= (0xfU
<< 28);
10168 if (inst
.operands
[1].preind
)
10169 inst
.instruction
|= PRE_INDEX
;
10170 if (!inst
.operands
[1].negative
)
10171 inst
.instruction
|= INDEX_UP
;
10172 if (inst
.operands
[1].writeback
)
10173 inst
.instruction
|= WRITE_BACK
;
10174 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10175 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10176 inst
.instruction
|= inst
.operands
[1].imm
;
10179 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10183 do_iwmmxt_wshufh (void)
10185 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10186 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10187 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10188 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10192 do_iwmmxt_wzero (void)
10194 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10195 inst
.instruction
|= inst
.operands
[0].reg
;
10196 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10197 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10201 do_iwmmxt_wrwrwr_or_imm5 (void)
10203 if (inst
.operands
[2].isreg
)
10206 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10207 _("immediate operand requires iWMMXt2"));
10209 if (inst
.operands
[2].imm
== 0)
10211 switch ((inst
.instruction
>> 20) & 0xf)
10217 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10218 inst
.operands
[2].imm
= 16;
10219 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10225 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10226 inst
.operands
[2].imm
= 32;
10227 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10234 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10236 wrn
= (inst
.instruction
>> 16) & 0xf;
10237 inst
.instruction
&= 0xff0fff0f;
10238 inst
.instruction
|= wrn
;
10239 /* Bail out here; the instruction is now assembled. */
10244 /* Map 32 -> 0, etc. */
10245 inst
.operands
[2].imm
&= 0x1f;
10246 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10250 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10251 operations first, then control, shift, and load/store. */
10253 /* Insns like "foo X,Y,Z". */
10256 do_mav_triple (void)
10258 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10259 inst
.instruction
|= inst
.operands
[1].reg
;
10260 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10263 /* Insns like "foo W,X,Y,Z".
10264 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10269 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10270 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10271 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10272 inst
.instruction
|= inst
.operands
[3].reg
;
10275 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10277 do_mav_dspsc (void)
10279 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10282 /* Maverick shift immediate instructions.
10283 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10284 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10287 do_mav_shift (void)
10289 int imm
= inst
.operands
[2].imm
;
10291 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10292 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10294 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10295 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10296 Bit 4 should be 0. */
10297 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10299 inst
.instruction
|= imm
;
10302 /* XScale instructions. Also sorted arithmetic before move. */
10304 /* Xscale multiply-accumulate (argument parse)
10307 MIAxycc acc0,Rm,Rs. */
10312 inst
.instruction
|= inst
.operands
[1].reg
;
10313 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10316 /* Xscale move-accumulator-register (argument parse)
10318 MARcc acc0,RdLo,RdHi. */
10323 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10324 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10327 /* Xscale move-register-accumulator (argument parse)
10329 MRAcc RdLo,RdHi,acc0. */
10334 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10335 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10336 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10339 /* Encoding functions relevant only to Thumb. */
10341 /* inst.operands[i] is a shifted-register operand; encode
10342 it into inst.instruction in the format used by Thumb32. */
10345 encode_thumb32_shifted_operand (int i
)
10347 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10348 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10350 constraint (inst
.operands
[i
].immisreg
,
10351 _("shift by register not allowed in thumb mode"));
10352 inst
.instruction
|= inst
.operands
[i
].reg
;
10353 if (shift
== SHIFT_RRX
)
10354 inst
.instruction
|= SHIFT_ROR
<< 4;
10357 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10358 _("expression too complex"));
10360 constraint (value
> 32
10361 || (value
== 32 && (shift
== SHIFT_LSL
10362 || shift
== SHIFT_ROR
)),
10363 _("shift expression is too large"));
10367 else if (value
== 32)
10370 inst
.instruction
|= shift
<< 4;
10371 inst
.instruction
|= (value
& 0x1c) << 10;
10372 inst
.instruction
|= (value
& 0x03) << 6;
10377 /* inst.operands[i] was set up by parse_address. Encode it into a
10378 Thumb32 format load or store instruction. Reject forms that cannot
10379 be used with such instructions. If is_t is true, reject forms that
10380 cannot be used with a T instruction; if is_d is true, reject forms
10381 that cannot be used with a D instruction. If it is a store insn,
10382 reject PC in Rn. */
10385 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10387 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10389 constraint (!inst
.operands
[i
].isreg
,
10390 _("Instruction does not support =N addresses"));
10392 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10393 if (inst
.operands
[i
].immisreg
)
10395 constraint (is_pc
, BAD_PC_ADDRESSING
);
10396 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10397 constraint (inst
.operands
[i
].negative
,
10398 _("Thumb does not support negative register indexing"));
10399 constraint (inst
.operands
[i
].postind
,
10400 _("Thumb does not support register post-indexing"));
10401 constraint (inst
.operands
[i
].writeback
,
10402 _("Thumb does not support register indexing with writeback"));
10403 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10404 _("Thumb supports only LSL in shifted register indexing"));
10406 inst
.instruction
|= inst
.operands
[i
].imm
;
10407 if (inst
.operands
[i
].shifted
)
10409 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10410 _("expression too complex"));
10411 constraint (inst
.reloc
.exp
.X_add_number
< 0
10412 || inst
.reloc
.exp
.X_add_number
> 3,
10413 _("shift out of range"));
10414 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10416 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10418 else if (inst
.operands
[i
].preind
)
10420 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10421 constraint (is_t
&& inst
.operands
[i
].writeback
,
10422 _("cannot use writeback with this instruction"));
10423 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10424 BAD_PC_ADDRESSING
);
10428 inst
.instruction
|= 0x01000000;
10429 if (inst
.operands
[i
].writeback
)
10430 inst
.instruction
|= 0x00200000;
10434 inst
.instruction
|= 0x00000c00;
10435 if (inst
.operands
[i
].writeback
)
10436 inst
.instruction
|= 0x00000100;
10438 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10440 else if (inst
.operands
[i
].postind
)
10442 gas_assert (inst
.operands
[i
].writeback
);
10443 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10444 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10447 inst
.instruction
|= 0x00200000;
10449 inst
.instruction
|= 0x00000900;
10450 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10452 else /* unindexed - only for coprocessor */
10453 inst
.error
= _("instruction does not accept unindexed addressing");
10456 /* Table of Thumb instructions which exist in both 16- and 32-bit
10457 encodings (the latter only in post-V6T2 cores). The index is the
10458 value used in the insns table below. When there is more than one
10459 possible 16-bit encoding for the instruction, this table always
10461 Also contains several pseudo-instructions used during relaxation. */
10462 #define T16_32_TAB \
10463 X(_adc, 4140, eb400000), \
10464 X(_adcs, 4140, eb500000), \
10465 X(_add, 1c00, eb000000), \
10466 X(_adds, 1c00, eb100000), \
10467 X(_addi, 0000, f1000000), \
10468 X(_addis, 0000, f1100000), \
10469 X(_add_pc,000f, f20f0000), \
10470 X(_add_sp,000d, f10d0000), \
10471 X(_adr, 000f, f20f0000), \
10472 X(_and, 4000, ea000000), \
10473 X(_ands, 4000, ea100000), \
10474 X(_asr, 1000, fa40f000), \
10475 X(_asrs, 1000, fa50f000), \
10476 X(_b, e000, f000b000), \
10477 X(_bcond, d000, f0008000), \
10478 X(_bic, 4380, ea200000), \
10479 X(_bics, 4380, ea300000), \
10480 X(_cmn, 42c0, eb100f00), \
10481 X(_cmp, 2800, ebb00f00), \
10482 X(_cpsie, b660, f3af8400), \
10483 X(_cpsid, b670, f3af8600), \
10484 X(_cpy, 4600, ea4f0000), \
10485 X(_dec_sp,80dd, f1ad0d00), \
10486 X(_eor, 4040, ea800000), \
10487 X(_eors, 4040, ea900000), \
10488 X(_inc_sp,00dd, f10d0d00), \
10489 X(_ldmia, c800, e8900000), \
10490 X(_ldr, 6800, f8500000), \
10491 X(_ldrb, 7800, f8100000), \
10492 X(_ldrh, 8800, f8300000), \
10493 X(_ldrsb, 5600, f9100000), \
10494 X(_ldrsh, 5e00, f9300000), \
10495 X(_ldr_pc,4800, f85f0000), \
10496 X(_ldr_pc2,4800, f85f0000), \
10497 X(_ldr_sp,9800, f85d0000), \
10498 X(_lsl, 0000, fa00f000), \
10499 X(_lsls, 0000, fa10f000), \
10500 X(_lsr, 0800, fa20f000), \
10501 X(_lsrs, 0800, fa30f000), \
10502 X(_mov, 2000, ea4f0000), \
10503 X(_movs, 2000, ea5f0000), \
10504 X(_mul, 4340, fb00f000), \
10505 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10506 X(_mvn, 43c0, ea6f0000), \
10507 X(_mvns, 43c0, ea7f0000), \
10508 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10509 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10510 X(_orr, 4300, ea400000), \
10511 X(_orrs, 4300, ea500000), \
10512 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10513 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10514 X(_rev, ba00, fa90f080), \
10515 X(_rev16, ba40, fa90f090), \
10516 X(_revsh, bac0, fa90f0b0), \
10517 X(_ror, 41c0, fa60f000), \
10518 X(_rors, 41c0, fa70f000), \
10519 X(_sbc, 4180, eb600000), \
10520 X(_sbcs, 4180, eb700000), \
10521 X(_stmia, c000, e8800000), \
10522 X(_str, 6000, f8400000), \
10523 X(_strb, 7000, f8000000), \
10524 X(_strh, 8000, f8200000), \
10525 X(_str_sp,9000, f84d0000), \
10526 X(_sub, 1e00, eba00000), \
10527 X(_subs, 1e00, ebb00000), \
10528 X(_subi, 8000, f1a00000), \
10529 X(_subis, 8000, f1b00000), \
10530 X(_sxtb, b240, fa4ff080), \
10531 X(_sxth, b200, fa0ff080), \
10532 X(_tst, 4200, ea100f00), \
10533 X(_uxtb, b2c0, fa5ff080), \
10534 X(_uxth, b280, fa1ff080), \
10535 X(_nop, bf00, f3af8000), \
10536 X(_yield, bf10, f3af8001), \
10537 X(_wfe, bf20, f3af8002), \
10538 X(_wfi, bf30, f3af8003), \
10539 X(_sev, bf40, f3af8004), \
10540 X(_sevl, bf50, f3af8005), \
10541 X(_udf, de00, f7f0a000)
10543 /* To catch errors in encoding functions, the codes are all offset by
10544 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10545 as 16-bit instructions. */
10546 #define X(a,b,c) T_MNEM##a
10547 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10550 #define X(a,b,c) 0x##b
10551 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10552 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10555 #define X(a,b,c) 0x##c
10556 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10557 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10558 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10562 /* Thumb instruction encoders, in alphabetical order. */
10564 /* ADDW or SUBW. */
10567 do_t_add_sub_w (void)
10571 Rd
= inst
.operands
[0].reg
;
10572 Rn
= inst
.operands
[1].reg
;
10574 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10575 is the SP-{plus,minus}-immediate form of the instruction. */
10577 constraint (Rd
== REG_PC
, BAD_PC
);
10579 reject_bad_reg (Rd
);
10581 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10582 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10585 /* Parse an add or subtract instruction. We get here with inst.instruction
10586 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
10589 do_t_add_sub (void)
10593 Rd
= inst
.operands
[0].reg
;
10594 Rs
= (inst
.operands
[1].present
10595 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10596 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10599 set_it_insn_type_last ();
10601 if (unified_syntax
)
10604 bfd_boolean narrow
;
10607 flags
= (inst
.instruction
== T_MNEM_adds
10608 || inst
.instruction
== T_MNEM_subs
);
10610 narrow
= !in_it_block ();
10612 narrow
= in_it_block ();
10613 if (!inst
.operands
[2].isreg
)
10617 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10618 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10620 add
= (inst
.instruction
== T_MNEM_add
10621 || inst
.instruction
== T_MNEM_adds
);
10623 if (inst
.size_req
!= 4)
10625 /* Attempt to use a narrow opcode, with relaxation if
10627 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10628 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10629 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10630 opcode
= T_MNEM_add_sp
;
10631 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10632 opcode
= T_MNEM_add_pc
;
10633 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10636 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10638 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10642 inst
.instruction
= THUMB_OP16(opcode
);
10643 inst
.instruction
|= (Rd
<< 4) | Rs
;
10644 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10645 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10647 if (inst
.size_req
== 2)
10648 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10650 inst
.relax
= opcode
;
10654 constraint (inst
.size_req
== 2, BAD_HIREG
);
10656 if (inst
.size_req
== 4
10657 || (inst
.size_req
!= 2 && !opcode
))
10659 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10660 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10661 THUMB1_RELOC_ONLY
);
10664 constraint (add
, BAD_PC
);
10665 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10666 _("only SUBS PC, LR, #const allowed"));
10667 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10668 _("expression too complex"));
10669 constraint (inst
.reloc
.exp
.X_add_number
< 0
10670 || inst
.reloc
.exp
.X_add_number
> 0xff,
10671 _("immediate value out of range"));
10672 inst
.instruction
= T2_SUBS_PC_LR
10673 | inst
.reloc
.exp
.X_add_number
;
10674 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10677 else if (Rs
== REG_PC
)
10679 /* Always use addw/subw. */
10680 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10681 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10685 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10686 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10689 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10691 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10693 inst
.instruction
|= Rd
<< 8;
10694 inst
.instruction
|= Rs
<< 16;
10699 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10700 unsigned int shift
= inst
.operands
[2].shift_kind
;
10702 Rn
= inst
.operands
[2].reg
;
10703 /* See if we can do this with a 16-bit instruction. */
10704 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10706 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10711 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10712 || inst
.instruction
== T_MNEM_add
)
10714 : T_OPCODE_SUB_R3
);
10715 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10719 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10721 /* Thumb-1 cores (except v6-M) require at least one high
10722 register in a narrow non flag setting add. */
10723 if (Rd
> 7 || Rn
> 7
10724 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10725 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10732 inst
.instruction
= T_OPCODE_ADD_HI
;
10733 inst
.instruction
|= (Rd
& 8) << 4;
10734 inst
.instruction
|= (Rd
& 7);
10735 inst
.instruction
|= Rn
<< 3;
10741 constraint (Rd
== REG_PC
, BAD_PC
);
10742 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10743 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10744 constraint (Rs
== REG_PC
, BAD_PC
);
10745 reject_bad_reg (Rn
);
10747 /* If we get here, it can't be done in 16 bits. */
10748 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10749 _("shift must be constant"));
10750 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10751 inst
.instruction
|= Rd
<< 8;
10752 inst
.instruction
|= Rs
<< 16;
10753 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10754 _("shift value over 3 not allowed in thumb mode"));
10755 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10756 _("only LSL shift allowed in thumb mode"));
10757 encode_thumb32_shifted_operand (2);
10762 constraint (inst
.instruction
== T_MNEM_adds
10763 || inst
.instruction
== T_MNEM_subs
,
10766 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10768 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10769 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10772 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10773 ? 0x0000 : 0x8000);
10774 inst
.instruction
|= (Rd
<< 4) | Rs
;
10775 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10779 Rn
= inst
.operands
[2].reg
;
10780 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10782 /* We now have Rd, Rs, and Rn set to registers. */
10783 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10785 /* Can't do this for SUB. */
10786 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10787 inst
.instruction
= T_OPCODE_ADD_HI
;
10788 inst
.instruction
|= (Rd
& 8) << 4;
10789 inst
.instruction
|= (Rd
& 7);
10791 inst
.instruction
|= Rn
<< 3;
10793 inst
.instruction
|= Rs
<< 3;
10795 constraint (1, _("dest must overlap one source register"));
10799 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10800 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10801 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10811 Rd
= inst
.operands
[0].reg
;
10812 reject_bad_reg (Rd
);
10814 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10816 /* Defer to section relaxation. */
10817 inst
.relax
= inst
.instruction
;
10818 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10819 inst
.instruction
|= Rd
<< 4;
10821 else if (unified_syntax
&& inst
.size_req
!= 2)
10823 /* Generate a 32-bit opcode. */
10824 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10825 inst
.instruction
|= Rd
<< 8;
10826 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10827 inst
.reloc
.pc_rel
= 1;
10831 /* Generate a 16-bit opcode. */
10832 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10833 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10834 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10835 inst
.reloc
.pc_rel
= 1;
10836 inst
.instruction
|= Rd
<< 4;
10839 if (inst
.reloc
.exp
.X_op
== O_symbol
10840 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10841 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10842 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10843 inst
.reloc
.exp
.X_add_number
+= 1;
10846 /* Arithmetic instructions for which there is just one 16-bit
10847 instruction encoding, and it allows only two low registers.
10848 For maximal compatibility with ARM syntax, we allow three register
10849 operands even when Thumb-32 instructions are not available, as long
10850 as the first two are identical. For instance, both "sbc r0,r1" and
10851 "sbc r0,r0,r1" are allowed. */
10857 Rd
= inst
.operands
[0].reg
;
10858 Rs
= (inst
.operands
[1].present
10859 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10860 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10861 Rn
= inst
.operands
[2].reg
;
10863 reject_bad_reg (Rd
);
10864 reject_bad_reg (Rs
);
10865 if (inst
.operands
[2].isreg
)
10866 reject_bad_reg (Rn
);
10868 if (unified_syntax
)
10870 if (!inst
.operands
[2].isreg
)
10872 /* For an immediate, we always generate a 32-bit opcode;
10873 section relaxation will shrink it later if possible. */
10874 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10875 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10876 inst
.instruction
|= Rd
<< 8;
10877 inst
.instruction
|= Rs
<< 16;
10878 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10882 bfd_boolean narrow
;
10884 /* See if we can do this with a 16-bit instruction. */
10885 if (THUMB_SETS_FLAGS (inst
.instruction
))
10886 narrow
= !in_it_block ();
10888 narrow
= in_it_block ();
10890 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10892 if (inst
.operands
[2].shifted
)
10894 if (inst
.size_req
== 4)
10900 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10901 inst
.instruction
|= Rd
;
10902 inst
.instruction
|= Rn
<< 3;
10906 /* If we get here, it can't be done in 16 bits. */
10907 constraint (inst
.operands
[2].shifted
10908 && inst
.operands
[2].immisreg
,
10909 _("shift must be constant"));
10910 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10911 inst
.instruction
|= Rd
<< 8;
10912 inst
.instruction
|= Rs
<< 16;
10913 encode_thumb32_shifted_operand (2);
10918 /* On its face this is a lie - the instruction does set the
10919 flags. However, the only supported mnemonic in this mode
10920 says it doesn't. */
10921 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10923 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10924 _("unshifted register required"));
10925 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10926 constraint (Rd
!= Rs
,
10927 _("dest and source1 must be the same register"));
10929 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10930 inst
.instruction
|= Rd
;
10931 inst
.instruction
|= Rn
<< 3;
10935 /* Similarly, but for instructions where the arithmetic operation is
10936 commutative, so we can allow either of them to be different from
10937 the destination operand in a 16-bit instruction. For instance, all
10938 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10945 Rd
= inst
.operands
[0].reg
;
10946 Rs
= (inst
.operands
[1].present
10947 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10948 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10949 Rn
= inst
.operands
[2].reg
;
10951 reject_bad_reg (Rd
);
10952 reject_bad_reg (Rs
);
10953 if (inst
.operands
[2].isreg
)
10954 reject_bad_reg (Rn
);
10956 if (unified_syntax
)
10958 if (!inst
.operands
[2].isreg
)
10960 /* For an immediate, we always generate a 32-bit opcode;
10961 section relaxation will shrink it later if possible. */
10962 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10963 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10964 inst
.instruction
|= Rd
<< 8;
10965 inst
.instruction
|= Rs
<< 16;
10966 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10970 bfd_boolean narrow
;
10972 /* See if we can do this with a 16-bit instruction. */
10973 if (THUMB_SETS_FLAGS (inst
.instruction
))
10974 narrow
= !in_it_block ();
10976 narrow
= in_it_block ();
10978 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10980 if (inst
.operands
[2].shifted
)
10982 if (inst
.size_req
== 4)
10989 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10990 inst
.instruction
|= Rd
;
10991 inst
.instruction
|= Rn
<< 3;
10996 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10997 inst
.instruction
|= Rd
;
10998 inst
.instruction
|= Rs
<< 3;
11003 /* If we get here, it can't be done in 16 bits. */
11004 constraint (inst
.operands
[2].shifted
11005 && inst
.operands
[2].immisreg
,
11006 _("shift must be constant"));
11007 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11008 inst
.instruction
|= Rd
<< 8;
11009 inst
.instruction
|= Rs
<< 16;
11010 encode_thumb32_shifted_operand (2);
11015 /* On its face this is a lie - the instruction does set the
11016 flags. However, the only supported mnemonic in this mode
11017 says it doesn't. */
11018 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11020 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11021 _("unshifted register required"));
11022 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11024 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11025 inst
.instruction
|= Rd
;
11028 inst
.instruction
|= Rn
<< 3;
11030 inst
.instruction
|= Rs
<< 3;
11032 constraint (1, _("dest must overlap one source register"));
11040 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11041 constraint (msb
> 32, _("bit-field extends past end of register"));
11042 /* The instruction encoding stores the LSB and MSB,
11043 not the LSB and width. */
11044 Rd
= inst
.operands
[0].reg
;
11045 reject_bad_reg (Rd
);
11046 inst
.instruction
|= Rd
<< 8;
11047 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11048 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11049 inst
.instruction
|= msb
- 1;
11058 Rd
= inst
.operands
[0].reg
;
11059 reject_bad_reg (Rd
);
11061 /* #0 in second position is alternative syntax for bfc, which is
11062 the same instruction but with REG_PC in the Rm field. */
11063 if (!inst
.operands
[1].isreg
)
11067 Rn
= inst
.operands
[1].reg
;
11068 reject_bad_reg (Rn
);
11071 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11072 constraint (msb
> 32, _("bit-field extends past end of register"));
11073 /* The instruction encoding stores the LSB and MSB,
11074 not the LSB and width. */
11075 inst
.instruction
|= Rd
<< 8;
11076 inst
.instruction
|= Rn
<< 16;
11077 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11078 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11079 inst
.instruction
|= msb
- 1;
11087 Rd
= inst
.operands
[0].reg
;
11088 Rn
= inst
.operands
[1].reg
;
11090 reject_bad_reg (Rd
);
11091 reject_bad_reg (Rn
);
11093 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11094 _("bit-field extends past end of register"));
11095 inst
.instruction
|= Rd
<< 8;
11096 inst
.instruction
|= Rn
<< 16;
11097 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11098 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11099 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11102 /* ARM V5 Thumb BLX (argument parse)
11103 BLX <target_addr> which is BLX(1)
11104 BLX <Rm> which is BLX(2)
11105 Unfortunately, there are two different opcodes for this mnemonic.
11106 So, the insns[].value is not used, and the code here zaps values
11107 into inst.instruction.
11109 ??? How to take advantage of the additional two bits of displacement
11110 available in Thumb32 mode? Need new relocation? */
11115 set_it_insn_type_last ();
11117 if (inst
.operands
[0].isreg
)
11119 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11120 /* We have a register, so this is BLX(2). */
11121 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11125 /* No register. This must be BLX(1). */
11126 inst
.instruction
= 0xf000e800;
11127 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11136 bfd_reloc_code_real_type reloc
;
11139 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11141 if (in_it_block ())
11143 /* Conditional branches inside IT blocks are encoded as unconditional
11145 cond
= COND_ALWAYS
;
11150 if (cond
!= COND_ALWAYS
)
11151 opcode
= T_MNEM_bcond
;
11153 opcode
= inst
.instruction
;
11156 && (inst
.size_req
== 4
11157 || (inst
.size_req
!= 2
11158 && (inst
.operands
[0].hasreloc
11159 || inst
.reloc
.exp
.X_op
== O_constant
))))
11161 inst
.instruction
= THUMB_OP32(opcode
);
11162 if (cond
== COND_ALWAYS
)
11163 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11166 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11167 _("selected architecture does not support "
11168 "wide conditional branch instruction"));
11170 gas_assert (cond
!= 0xF);
11171 inst
.instruction
|= cond
<< 22;
11172 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11177 inst
.instruction
= THUMB_OP16(opcode
);
11178 if (cond
== COND_ALWAYS
)
11179 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11182 inst
.instruction
|= cond
<< 8;
11183 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11185 /* Allow section relaxation. */
11186 if (unified_syntax
&& inst
.size_req
!= 2)
11187 inst
.relax
= opcode
;
11189 inst
.reloc
.type
= reloc
;
11190 inst
.reloc
.pc_rel
= 1;
11193 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11194 between the two is the maximum immediate allowed - which is passed in
11197 do_t_bkpt_hlt1 (int range
)
11199 constraint (inst
.cond
!= COND_ALWAYS
,
11200 _("instruction is always unconditional"));
11201 if (inst
.operands
[0].present
)
11203 constraint (inst
.operands
[0].imm
> range
,
11204 _("immediate value out of range"));
11205 inst
.instruction
|= inst
.operands
[0].imm
;
11208 set_it_insn_type (NEUTRAL_IT_INSN
);
11214 do_t_bkpt_hlt1 (63);
11220 do_t_bkpt_hlt1 (255);
11224 do_t_branch23 (void)
11226 set_it_insn_type_last ();
11227 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11229 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11230 this file. We used to simply ignore the PLT reloc type here --
11231 the branch encoding is now needed to deal with TLSCALL relocs.
11232 So if we see a PLT reloc now, put it back to how it used to be to
11233 keep the preexisting behaviour. */
11234 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11235 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11237 #if defined(OBJ_COFF)
11238 /* If the destination of the branch is a defined symbol which does not have
11239 the THUMB_FUNC attribute, then we must be calling a function which has
11240 the (interfacearm) attribute. We look for the Thumb entry point to that
11241 function and change the branch to refer to that function instead. */
11242 if ( inst
.reloc
.exp
.X_op
== O_symbol
11243 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11244 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11245 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11246 inst
.reloc
.exp
.X_add_symbol
=
11247 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11254 set_it_insn_type_last ();
11255 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11256 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11257 should cause the alignment to be checked once it is known. This is
11258 because BX PC only works if the instruction is word aligned. */
11266 set_it_insn_type_last ();
11267 Rm
= inst
.operands
[0].reg
;
11268 reject_bad_reg (Rm
);
11269 inst
.instruction
|= Rm
<< 16;
11278 Rd
= inst
.operands
[0].reg
;
11279 Rm
= inst
.operands
[1].reg
;
11281 reject_bad_reg (Rd
);
11282 reject_bad_reg (Rm
);
11284 inst
.instruction
|= Rd
<< 8;
11285 inst
.instruction
|= Rm
<< 16;
11286 inst
.instruction
|= Rm
;
11292 set_it_insn_type (OUTSIDE_IT_INSN
);
11298 set_it_insn_type (OUTSIDE_IT_INSN
);
11299 inst
.instruction
|= inst
.operands
[0].imm
;
11305 set_it_insn_type (OUTSIDE_IT_INSN
);
11307 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11308 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11310 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11311 inst
.instruction
= 0xf3af8000;
11312 inst
.instruction
|= imod
<< 9;
11313 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11314 if (inst
.operands
[1].present
)
11315 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11319 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11320 && (inst
.operands
[0].imm
& 4),
11321 _("selected processor does not support 'A' form "
11322 "of this instruction"));
11323 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11324 _("Thumb does not support the 2-argument "
11325 "form of this instruction"));
11326 inst
.instruction
|= inst
.operands
[0].imm
;
11330 /* THUMB CPY instruction (argument parse). */
11335 if (inst
.size_req
== 4)
11337 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11338 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11339 inst
.instruction
|= inst
.operands
[1].reg
;
11343 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11344 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11345 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11352 set_it_insn_type (OUTSIDE_IT_INSN
);
11353 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11354 inst
.instruction
|= inst
.operands
[0].reg
;
11355 inst
.reloc
.pc_rel
= 1;
11356 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11362 inst
.instruction
|= inst
.operands
[0].imm
;
11368 unsigned Rd
, Rn
, Rm
;
11370 Rd
= inst
.operands
[0].reg
;
11371 Rn
= (inst
.operands
[1].present
11372 ? inst
.operands
[1].reg
: Rd
);
11373 Rm
= inst
.operands
[2].reg
;
11375 reject_bad_reg (Rd
);
11376 reject_bad_reg (Rn
);
11377 reject_bad_reg (Rm
);
11379 inst
.instruction
|= Rd
<< 8;
11380 inst
.instruction
|= Rn
<< 16;
11381 inst
.instruction
|= Rm
;
11387 if (unified_syntax
&& inst
.size_req
== 4)
11388 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11390 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11396 unsigned int cond
= inst
.operands
[0].imm
;
11398 set_it_insn_type (IT_INSN
);
11399 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11401 now_it
.warn_deprecated
= FALSE
;
11403 /* If the condition is a negative condition, invert the mask. */
11404 if ((cond
& 0x1) == 0x0)
11406 unsigned int mask
= inst
.instruction
& 0x000f;
11408 if ((mask
& 0x7) == 0)
11410 /* No conversion needed. */
11411 now_it
.block_length
= 1;
11413 else if ((mask
& 0x3) == 0)
11416 now_it
.block_length
= 2;
11418 else if ((mask
& 0x1) == 0)
11421 now_it
.block_length
= 3;
11426 now_it
.block_length
= 4;
11429 inst
.instruction
&= 0xfff0;
11430 inst
.instruction
|= mask
;
11433 inst
.instruction
|= cond
<< 4;
11436 /* Helper function used for both push/pop and ldm/stm. */
11438 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11442 load
= (inst
.instruction
& (1 << 20)) != 0;
11444 if (mask
& (1 << 13))
11445 inst
.error
= _("SP not allowed in register list");
11447 if ((mask
& (1 << base
)) != 0
11449 inst
.error
= _("having the base register in the register list when "
11450 "using write back is UNPREDICTABLE");
11454 if (mask
& (1 << 15))
11456 if (mask
& (1 << 14))
11457 inst
.error
= _("LR and PC should not both be in register list");
11459 set_it_insn_type_last ();
11464 if (mask
& (1 << 15))
11465 inst
.error
= _("PC not allowed in register list");
11468 if ((mask
& (mask
- 1)) == 0)
11470 /* Single register transfers implemented as str/ldr. */
11473 if (inst
.instruction
& (1 << 23))
11474 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11476 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11480 if (inst
.instruction
& (1 << 23))
11481 inst
.instruction
= 0x00800000; /* ia -> [base] */
11483 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11486 inst
.instruction
|= 0xf8400000;
11488 inst
.instruction
|= 0x00100000;
11490 mask
= ffs (mask
) - 1;
11493 else if (writeback
)
11494 inst
.instruction
|= WRITE_BACK
;
11496 inst
.instruction
|= mask
;
11497 inst
.instruction
|= base
<< 16;
11503 /* This really doesn't seem worth it. */
11504 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11505 _("expression too complex"));
11506 constraint (inst
.operands
[1].writeback
,
11507 _("Thumb load/store multiple does not support {reglist}^"));
11509 if (unified_syntax
)
11511 bfd_boolean narrow
;
11515 /* See if we can use a 16-bit instruction. */
11516 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11517 && inst
.size_req
!= 4
11518 && !(inst
.operands
[1].imm
& ~0xff))
11520 mask
= 1 << inst
.operands
[0].reg
;
11522 if (inst
.operands
[0].reg
<= 7)
11524 if (inst
.instruction
== T_MNEM_stmia
11525 ? inst
.operands
[0].writeback
11526 : (inst
.operands
[0].writeback
11527 == !(inst
.operands
[1].imm
& mask
)))
11529 if (inst
.instruction
== T_MNEM_stmia
11530 && (inst
.operands
[1].imm
& mask
)
11531 && (inst
.operands
[1].imm
& (mask
- 1)))
11532 as_warn (_("value stored for r%d is UNKNOWN"),
11533 inst
.operands
[0].reg
);
11535 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11536 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11537 inst
.instruction
|= inst
.operands
[1].imm
;
11540 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11542 /* This means 1 register in reg list one of 3 situations:
11543 1. Instruction is stmia, but without writeback.
11544 2. lmdia without writeback, but with Rn not in
11546 3. ldmia with writeback, but with Rn in reglist.
11547 Case 3 is UNPREDICTABLE behaviour, so we handle
11548 case 1 and 2 which can be converted into a 16-bit
11549 str or ldr. The SP cases are handled below. */
11550 unsigned long opcode
;
11551 /* First, record an error for Case 3. */
11552 if (inst
.operands
[1].imm
& mask
11553 && inst
.operands
[0].writeback
)
11555 _("having the base register in the register list when "
11556 "using write back is UNPREDICTABLE");
11558 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11560 inst
.instruction
= THUMB_OP16 (opcode
);
11561 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11562 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11566 else if (inst
.operands
[0] .reg
== REG_SP
)
11568 if (inst
.operands
[0].writeback
)
11571 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11572 ? T_MNEM_push
: T_MNEM_pop
);
11573 inst
.instruction
|= inst
.operands
[1].imm
;
11576 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11579 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11580 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11581 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11589 if (inst
.instruction
< 0xffff)
11590 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11592 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11593 inst
.operands
[0].writeback
);
11598 constraint (inst
.operands
[0].reg
> 7
11599 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11600 constraint (inst
.instruction
!= T_MNEM_ldmia
11601 && inst
.instruction
!= T_MNEM_stmia
,
11602 _("Thumb-2 instruction only valid in unified syntax"));
11603 if (inst
.instruction
== T_MNEM_stmia
)
11605 if (!inst
.operands
[0].writeback
)
11606 as_warn (_("this instruction will write back the base register"));
11607 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11608 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11609 as_warn (_("value stored for r%d is UNKNOWN"),
11610 inst
.operands
[0].reg
);
11614 if (!inst
.operands
[0].writeback
11615 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11616 as_warn (_("this instruction will write back the base register"));
11617 else if (inst
.operands
[0].writeback
11618 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11619 as_warn (_("this instruction will not write back the base register"));
11622 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11623 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11624 inst
.instruction
|= inst
.operands
[1].imm
;
11631 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11632 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11633 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11634 || inst
.operands
[1].negative
,
11637 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11639 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11640 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11641 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11647 if (!inst
.operands
[1].present
)
11649 constraint (inst
.operands
[0].reg
== REG_LR
,
11650 _("r14 not allowed as first register "
11651 "when second register is omitted"));
11652 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11654 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11657 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11658 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11659 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11665 unsigned long opcode
;
11668 if (inst
.operands
[0].isreg
11669 && !inst
.operands
[0].preind
11670 && inst
.operands
[0].reg
== REG_PC
)
11671 set_it_insn_type_last ();
11673 opcode
= inst
.instruction
;
11674 if (unified_syntax
)
11676 if (!inst
.operands
[1].isreg
)
11678 if (opcode
<= 0xffff)
11679 inst
.instruction
= THUMB_OP32 (opcode
);
11680 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11683 if (inst
.operands
[1].isreg
11684 && !inst
.operands
[1].writeback
11685 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11686 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11687 && opcode
<= 0xffff
11688 && inst
.size_req
!= 4)
11690 /* Insn may have a 16-bit form. */
11691 Rn
= inst
.operands
[1].reg
;
11692 if (inst
.operands
[1].immisreg
)
11694 inst
.instruction
= THUMB_OP16 (opcode
);
11696 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11698 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11699 reject_bad_reg (inst
.operands
[1].imm
);
11701 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11702 && opcode
!= T_MNEM_ldrsb
)
11703 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11704 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11711 if (inst
.reloc
.pc_rel
)
11712 opcode
= T_MNEM_ldr_pc2
;
11714 opcode
= T_MNEM_ldr_pc
;
11718 if (opcode
== T_MNEM_ldr
)
11719 opcode
= T_MNEM_ldr_sp
;
11721 opcode
= T_MNEM_str_sp
;
11723 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11727 inst
.instruction
= inst
.operands
[0].reg
;
11728 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11730 inst
.instruction
|= THUMB_OP16 (opcode
);
11731 if (inst
.size_req
== 2)
11732 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11734 inst
.relax
= opcode
;
11738 /* Definitely a 32-bit variant. */
11740 /* Warning for Erratum 752419. */
11741 if (opcode
== T_MNEM_ldr
11742 && inst
.operands
[0].reg
== REG_SP
11743 && inst
.operands
[1].writeback
== 1
11744 && !inst
.operands
[1].immisreg
)
11746 if (no_cpu_selected ()
11747 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11748 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11749 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11750 as_warn (_("This instruction may be unpredictable "
11751 "if executed on M-profile cores "
11752 "with interrupts enabled."));
11755 /* Do some validations regarding addressing modes. */
11756 if (inst
.operands
[1].immisreg
)
11757 reject_bad_reg (inst
.operands
[1].imm
);
11759 constraint (inst
.operands
[1].writeback
== 1
11760 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11763 inst
.instruction
= THUMB_OP32 (opcode
);
11764 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11765 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11766 check_ldr_r15_aligned ();
11770 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11772 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11774 /* Only [Rn,Rm] is acceptable. */
11775 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11776 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11777 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11778 || inst
.operands
[1].negative
,
11779 _("Thumb does not support this addressing mode"));
11780 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11784 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11785 if (!inst
.operands
[1].isreg
)
11786 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11789 constraint (!inst
.operands
[1].preind
11790 || inst
.operands
[1].shifted
11791 || inst
.operands
[1].writeback
,
11792 _("Thumb does not support this addressing mode"));
11793 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11795 constraint (inst
.instruction
& 0x0600,
11796 _("byte or halfword not valid for base register"));
11797 constraint (inst
.operands
[1].reg
== REG_PC
11798 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11799 _("r15 based store not allowed"));
11800 constraint (inst
.operands
[1].immisreg
,
11801 _("invalid base register for register offset"));
11803 if (inst
.operands
[1].reg
== REG_PC
)
11804 inst
.instruction
= T_OPCODE_LDR_PC
;
11805 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11806 inst
.instruction
= T_OPCODE_LDR_SP
;
11808 inst
.instruction
= T_OPCODE_STR_SP
;
11810 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11811 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11815 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11816 if (!inst
.operands
[1].immisreg
)
11818 /* Immediate offset. */
11819 inst
.instruction
|= inst
.operands
[0].reg
;
11820 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11821 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11825 /* Register offset. */
11826 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11827 constraint (inst
.operands
[1].negative
,
11828 _("Thumb does not support this addressing mode"));
11831 switch (inst
.instruction
)
11833 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11834 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11835 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11836 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11837 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11838 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11839 case 0x5600 /* ldrsb */:
11840 case 0x5e00 /* ldrsh */: break;
11844 inst
.instruction
|= inst
.operands
[0].reg
;
11845 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11846 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11852 if (!inst
.operands
[1].present
)
11854 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11855 constraint (inst
.operands
[0].reg
== REG_LR
,
11856 _("r14 not allowed here"));
11857 constraint (inst
.operands
[0].reg
== REG_R12
,
11858 _("r12 not allowed here"));
11861 if (inst
.operands
[2].writeback
11862 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11863 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11864 as_warn (_("base register written back, and overlaps "
11865 "one of transfer registers"));
11867 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11868 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11869 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11875 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11876 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11882 unsigned Rd
, Rn
, Rm
, Ra
;
11884 Rd
= inst
.operands
[0].reg
;
11885 Rn
= inst
.operands
[1].reg
;
11886 Rm
= inst
.operands
[2].reg
;
11887 Ra
= inst
.operands
[3].reg
;
11889 reject_bad_reg (Rd
);
11890 reject_bad_reg (Rn
);
11891 reject_bad_reg (Rm
);
11892 reject_bad_reg (Ra
);
11894 inst
.instruction
|= Rd
<< 8;
11895 inst
.instruction
|= Rn
<< 16;
11896 inst
.instruction
|= Rm
;
11897 inst
.instruction
|= Ra
<< 12;
11903 unsigned RdLo
, RdHi
, Rn
, Rm
;
11905 RdLo
= inst
.operands
[0].reg
;
11906 RdHi
= inst
.operands
[1].reg
;
11907 Rn
= inst
.operands
[2].reg
;
11908 Rm
= inst
.operands
[3].reg
;
11910 reject_bad_reg (RdLo
);
11911 reject_bad_reg (RdHi
);
11912 reject_bad_reg (Rn
);
11913 reject_bad_reg (Rm
);
11915 inst
.instruction
|= RdLo
<< 12;
11916 inst
.instruction
|= RdHi
<< 8;
11917 inst
.instruction
|= Rn
<< 16;
11918 inst
.instruction
|= Rm
;
11922 do_t_mov_cmp (void)
11926 Rn
= inst
.operands
[0].reg
;
11927 Rm
= inst
.operands
[1].reg
;
11930 set_it_insn_type_last ();
11932 if (unified_syntax
)
11934 int r0off
= (inst
.instruction
== T_MNEM_mov
11935 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11936 unsigned long opcode
;
11937 bfd_boolean narrow
;
11938 bfd_boolean low_regs
;
11940 low_regs
= (Rn
<= 7 && Rm
<= 7);
11941 opcode
= inst
.instruction
;
11942 if (in_it_block ())
11943 narrow
= opcode
!= T_MNEM_movs
;
11945 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11946 if (inst
.size_req
== 4
11947 || inst
.operands
[1].shifted
)
11950 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11951 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11952 && !inst
.operands
[1].shifted
11956 inst
.instruction
= T2_SUBS_PC_LR
;
11960 if (opcode
== T_MNEM_cmp
)
11962 constraint (Rn
== REG_PC
, BAD_PC
);
11965 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11967 warn_deprecated_sp (Rm
);
11968 /* R15 was documented as a valid choice for Rm in ARMv6,
11969 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11970 tools reject R15, so we do too. */
11971 constraint (Rm
== REG_PC
, BAD_PC
);
11974 reject_bad_reg (Rm
);
11976 else if (opcode
== T_MNEM_mov
11977 || opcode
== T_MNEM_movs
)
11979 if (inst
.operands
[1].isreg
)
11981 if (opcode
== T_MNEM_movs
)
11983 reject_bad_reg (Rn
);
11984 reject_bad_reg (Rm
);
11988 /* This is mov.n. */
11989 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11990 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11992 as_tsktsk (_("Use of r%u as a source register is "
11993 "deprecated when r%u is the destination "
11994 "register."), Rm
, Rn
);
11999 /* This is mov.w. */
12000 constraint (Rn
== REG_PC
, BAD_PC
);
12001 constraint (Rm
== REG_PC
, BAD_PC
);
12002 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12003 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12007 reject_bad_reg (Rn
);
12010 if (!inst
.operands
[1].isreg
)
12012 /* Immediate operand. */
12013 if (!in_it_block () && opcode
== T_MNEM_mov
)
12015 if (low_regs
&& narrow
)
12017 inst
.instruction
= THUMB_OP16 (opcode
);
12018 inst
.instruction
|= Rn
<< 8;
12019 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12020 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12022 if (inst
.size_req
== 2)
12023 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12025 inst
.relax
= opcode
;
12030 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12031 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
12032 THUMB1_RELOC_ONLY
);
12034 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12035 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12036 inst
.instruction
|= Rn
<< r0off
;
12037 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12040 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12041 && (inst
.instruction
== T_MNEM_mov
12042 || inst
.instruction
== T_MNEM_movs
))
12044 /* Register shifts are encoded as separate shift instructions. */
12045 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12047 if (in_it_block ())
12052 if (inst
.size_req
== 4)
12055 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12061 switch (inst
.operands
[1].shift_kind
)
12064 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12067 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12070 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12073 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12079 inst
.instruction
= opcode
;
12082 inst
.instruction
|= Rn
;
12083 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12088 inst
.instruction
|= CONDS_BIT
;
12090 inst
.instruction
|= Rn
<< 8;
12091 inst
.instruction
|= Rm
<< 16;
12092 inst
.instruction
|= inst
.operands
[1].imm
;
12097 /* Some mov with immediate shift have narrow variants.
12098 Register shifts are handled above. */
12099 if (low_regs
&& inst
.operands
[1].shifted
12100 && (inst
.instruction
== T_MNEM_mov
12101 || inst
.instruction
== T_MNEM_movs
))
12103 if (in_it_block ())
12104 narrow
= (inst
.instruction
== T_MNEM_mov
);
12106 narrow
= (inst
.instruction
== T_MNEM_movs
);
12111 switch (inst
.operands
[1].shift_kind
)
12113 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12114 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12115 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12116 default: narrow
= FALSE
; break;
12122 inst
.instruction
|= Rn
;
12123 inst
.instruction
|= Rm
<< 3;
12124 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12128 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12129 inst
.instruction
|= Rn
<< r0off
;
12130 encode_thumb32_shifted_operand (1);
12134 switch (inst
.instruction
)
12137 /* In v4t or v5t a move of two lowregs produces unpredictable
12138 results. Don't allow this. */
12141 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12142 "MOV Rd, Rs with two low registers is not "
12143 "permitted on this architecture");
12144 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12148 inst
.instruction
= T_OPCODE_MOV_HR
;
12149 inst
.instruction
|= (Rn
& 0x8) << 4;
12150 inst
.instruction
|= (Rn
& 0x7);
12151 inst
.instruction
|= Rm
<< 3;
12155 /* We know we have low registers at this point.
12156 Generate LSLS Rd, Rs, #0. */
12157 inst
.instruction
= T_OPCODE_LSL_I
;
12158 inst
.instruction
|= Rn
;
12159 inst
.instruction
|= Rm
<< 3;
12165 inst
.instruction
= T_OPCODE_CMP_LR
;
12166 inst
.instruction
|= Rn
;
12167 inst
.instruction
|= Rm
<< 3;
12171 inst
.instruction
= T_OPCODE_CMP_HR
;
12172 inst
.instruction
|= (Rn
& 0x8) << 4;
12173 inst
.instruction
|= (Rn
& 0x7);
12174 inst
.instruction
|= Rm
<< 3;
12181 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12183 /* PR 10443: Do not silently ignore shifted operands. */
12184 constraint (inst
.operands
[1].shifted
,
12185 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12187 if (inst
.operands
[1].isreg
)
12189 if (Rn
< 8 && Rm
< 8)
12191 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12192 since a MOV instruction produces unpredictable results. */
12193 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12194 inst
.instruction
= T_OPCODE_ADD_I3
;
12196 inst
.instruction
= T_OPCODE_CMP_LR
;
12198 inst
.instruction
|= Rn
;
12199 inst
.instruction
|= Rm
<< 3;
12203 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12204 inst
.instruction
= T_OPCODE_MOV_HR
;
12206 inst
.instruction
= T_OPCODE_CMP_HR
;
12212 constraint (Rn
> 7,
12213 _("only lo regs allowed with immediate"));
12214 inst
.instruction
|= Rn
<< 8;
12215 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12226 top
= (inst
.instruction
& 0x00800000) != 0;
12227 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12229 constraint (top
, _(":lower16: not allowed in this instruction"));
12230 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12232 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12234 constraint (!top
, _(":upper16: not allowed in this instruction"));
12235 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12238 Rd
= inst
.operands
[0].reg
;
12239 reject_bad_reg (Rd
);
12241 inst
.instruction
|= Rd
<< 8;
12242 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12244 imm
= inst
.reloc
.exp
.X_add_number
;
12245 inst
.instruction
|= (imm
& 0xf000) << 4;
12246 inst
.instruction
|= (imm
& 0x0800) << 15;
12247 inst
.instruction
|= (imm
& 0x0700) << 4;
12248 inst
.instruction
|= (imm
& 0x00ff);
12253 do_t_mvn_tst (void)
12257 Rn
= inst
.operands
[0].reg
;
12258 Rm
= inst
.operands
[1].reg
;
12260 if (inst
.instruction
== T_MNEM_cmp
12261 || inst
.instruction
== T_MNEM_cmn
)
12262 constraint (Rn
== REG_PC
, BAD_PC
);
12264 reject_bad_reg (Rn
);
12265 reject_bad_reg (Rm
);
12267 if (unified_syntax
)
12269 int r0off
= (inst
.instruction
== T_MNEM_mvn
12270 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12271 bfd_boolean narrow
;
12273 if (inst
.size_req
== 4
12274 || inst
.instruction
> 0xffff
12275 || inst
.operands
[1].shifted
12276 || Rn
> 7 || Rm
> 7)
12278 else if (inst
.instruction
== T_MNEM_cmn
12279 || inst
.instruction
== T_MNEM_tst
)
12281 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12282 narrow
= !in_it_block ();
12284 narrow
= in_it_block ();
12286 if (!inst
.operands
[1].isreg
)
12288 /* For an immediate, we always generate a 32-bit opcode;
12289 section relaxation will shrink it later if possible. */
12290 if (inst
.instruction
< 0xffff)
12291 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12292 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12293 inst
.instruction
|= Rn
<< r0off
;
12294 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12298 /* See if we can do this with a 16-bit instruction. */
12301 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12302 inst
.instruction
|= Rn
;
12303 inst
.instruction
|= Rm
<< 3;
12307 constraint (inst
.operands
[1].shifted
12308 && inst
.operands
[1].immisreg
,
12309 _("shift must be constant"));
12310 if (inst
.instruction
< 0xffff)
12311 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12312 inst
.instruction
|= Rn
<< r0off
;
12313 encode_thumb32_shifted_operand (1);
12319 constraint (inst
.instruction
> 0xffff
12320 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12321 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12322 _("unshifted register required"));
12323 constraint (Rn
> 7 || Rm
> 7,
12326 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12327 inst
.instruction
|= Rn
;
12328 inst
.instruction
|= Rm
<< 3;
12337 if (do_vfp_nsyn_mrs () == SUCCESS
)
12340 Rd
= inst
.operands
[0].reg
;
12341 reject_bad_reg (Rd
);
12342 inst
.instruction
|= Rd
<< 8;
12344 if (inst
.operands
[1].isreg
)
12346 unsigned br
= inst
.operands
[1].reg
;
12347 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12348 as_bad (_("bad register for mrs"));
12350 inst
.instruction
|= br
& (0xf << 16);
12351 inst
.instruction
|= (br
& 0x300) >> 4;
12352 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12356 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12358 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12360 /* PR gas/12698: The constraint is only applied for m_profile.
12361 If the user has specified -march=all, we want to ignore it as
12362 we are building for any CPU type, including non-m variants. */
12363 bfd_boolean m_profile
=
12364 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12365 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12366 "not support requested special purpose register"));
12369 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12371 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12372 _("'APSR', 'CPSR' or 'SPSR' expected"));
12374 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12375 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12376 inst
.instruction
|= 0xf0000;
12386 if (do_vfp_nsyn_msr () == SUCCESS
)
12389 constraint (!inst
.operands
[1].isreg
,
12390 _("Thumb encoding does not support an immediate here"));
12392 if (inst
.operands
[0].isreg
)
12393 flags
= (int)(inst
.operands
[0].reg
);
12395 flags
= inst
.operands
[0].imm
;
12397 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12399 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12401 /* PR gas/12698: The constraint is only applied for m_profile.
12402 If the user has specified -march=all, we want to ignore it as
12403 we are building for any CPU type, including non-m variants. */
12404 bfd_boolean m_profile
=
12405 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12406 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12407 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12408 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12409 && bits
!= PSR_f
)) && m_profile
,
12410 _("selected processor does not support requested special "
12411 "purpose register"));
12414 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12415 "requested special purpose register"));
12417 Rn
= inst
.operands
[1].reg
;
12418 reject_bad_reg (Rn
);
12420 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12421 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12422 inst
.instruction
|= (flags
& 0x300) >> 4;
12423 inst
.instruction
|= (flags
& 0xff);
12424 inst
.instruction
|= Rn
<< 16;
12430 bfd_boolean narrow
;
12431 unsigned Rd
, Rn
, Rm
;
12433 if (!inst
.operands
[2].present
)
12434 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12436 Rd
= inst
.operands
[0].reg
;
12437 Rn
= inst
.operands
[1].reg
;
12438 Rm
= inst
.operands
[2].reg
;
12440 if (unified_syntax
)
12442 if (inst
.size_req
== 4
12448 else if (inst
.instruction
== T_MNEM_muls
)
12449 narrow
= !in_it_block ();
12451 narrow
= in_it_block ();
12455 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12456 constraint (Rn
> 7 || Rm
> 7,
12463 /* 16-bit MULS/Conditional MUL. */
12464 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12465 inst
.instruction
|= Rd
;
12468 inst
.instruction
|= Rm
<< 3;
12470 inst
.instruction
|= Rn
<< 3;
12472 constraint (1, _("dest must overlap one source register"));
12476 constraint (inst
.instruction
!= T_MNEM_mul
,
12477 _("Thumb-2 MUL must not set flags"));
12479 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12480 inst
.instruction
|= Rd
<< 8;
12481 inst
.instruction
|= Rn
<< 16;
12482 inst
.instruction
|= Rm
<< 0;
12484 reject_bad_reg (Rd
);
12485 reject_bad_reg (Rn
);
12486 reject_bad_reg (Rm
);
12493 unsigned RdLo
, RdHi
, Rn
, Rm
;
12495 RdLo
= inst
.operands
[0].reg
;
12496 RdHi
= inst
.operands
[1].reg
;
12497 Rn
= inst
.operands
[2].reg
;
12498 Rm
= inst
.operands
[3].reg
;
12500 reject_bad_reg (RdLo
);
12501 reject_bad_reg (RdHi
);
12502 reject_bad_reg (Rn
);
12503 reject_bad_reg (Rm
);
12505 inst
.instruction
|= RdLo
<< 12;
12506 inst
.instruction
|= RdHi
<< 8;
12507 inst
.instruction
|= Rn
<< 16;
12508 inst
.instruction
|= Rm
;
12511 as_tsktsk (_("rdhi and rdlo must be different"));
12517 set_it_insn_type (NEUTRAL_IT_INSN
);
12519 if (unified_syntax
)
12521 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12523 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12524 inst
.instruction
|= inst
.operands
[0].imm
;
12528 /* PR9722: Check for Thumb2 availability before
12529 generating a thumb2 nop instruction. */
12530 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12532 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12533 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12536 inst
.instruction
= 0x46c0;
12541 constraint (inst
.operands
[0].present
,
12542 _("Thumb does not support NOP with hints"));
12543 inst
.instruction
= 0x46c0;
12550 if (unified_syntax
)
12552 bfd_boolean narrow
;
12554 if (THUMB_SETS_FLAGS (inst
.instruction
))
12555 narrow
= !in_it_block ();
12557 narrow
= in_it_block ();
12558 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12560 if (inst
.size_req
== 4)
12565 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12566 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12567 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12571 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12572 inst
.instruction
|= inst
.operands
[0].reg
;
12573 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12578 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12580 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12582 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12583 inst
.instruction
|= inst
.operands
[0].reg
;
12584 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12593 Rd
= inst
.operands
[0].reg
;
12594 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12596 reject_bad_reg (Rd
);
12597 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12598 reject_bad_reg (Rn
);
12600 inst
.instruction
|= Rd
<< 8;
12601 inst
.instruction
|= Rn
<< 16;
12603 if (!inst
.operands
[2].isreg
)
12605 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12606 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12612 Rm
= inst
.operands
[2].reg
;
12613 reject_bad_reg (Rm
);
12615 constraint (inst
.operands
[2].shifted
12616 && inst
.operands
[2].immisreg
,
12617 _("shift must be constant"));
12618 encode_thumb32_shifted_operand (2);
12625 unsigned Rd
, Rn
, Rm
;
12627 Rd
= inst
.operands
[0].reg
;
12628 Rn
= inst
.operands
[1].reg
;
12629 Rm
= inst
.operands
[2].reg
;
12631 reject_bad_reg (Rd
);
12632 reject_bad_reg (Rn
);
12633 reject_bad_reg (Rm
);
12635 inst
.instruction
|= Rd
<< 8;
12636 inst
.instruction
|= Rn
<< 16;
12637 inst
.instruction
|= Rm
;
12638 if (inst
.operands
[3].present
)
12640 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12641 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12642 _("expression too complex"));
12643 inst
.instruction
|= (val
& 0x1c) << 10;
12644 inst
.instruction
|= (val
& 0x03) << 6;
12651 if (!inst
.operands
[3].present
)
12655 inst
.instruction
&= ~0x00000020;
12657 /* PR 10168. Swap the Rm and Rn registers. */
12658 Rtmp
= inst
.operands
[1].reg
;
12659 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12660 inst
.operands
[2].reg
= Rtmp
;
12668 if (inst
.operands
[0].immisreg
)
12669 reject_bad_reg (inst
.operands
[0].imm
);
12671 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12675 do_t_push_pop (void)
12679 constraint (inst
.operands
[0].writeback
,
12680 _("push/pop do not support {reglist}^"));
12681 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12682 _("expression too complex"));
12684 mask
= inst
.operands
[0].imm
;
12685 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12686 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12687 else if (inst
.size_req
!= 4
12688 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12689 ? REG_LR
: REG_PC
)))
12691 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12692 inst
.instruction
|= THUMB_PP_PC_LR
;
12693 inst
.instruction
|= mask
& 0xff;
12695 else if (unified_syntax
)
12697 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12698 encode_thumb2_ldmstm (13, mask
, TRUE
);
12702 inst
.error
= _("invalid register list to push/pop instruction");
12712 Rd
= inst
.operands
[0].reg
;
12713 Rm
= inst
.operands
[1].reg
;
12715 reject_bad_reg (Rd
);
12716 reject_bad_reg (Rm
);
12718 inst
.instruction
|= Rd
<< 8;
12719 inst
.instruction
|= Rm
<< 16;
12720 inst
.instruction
|= Rm
;
12728 Rd
= inst
.operands
[0].reg
;
12729 Rm
= inst
.operands
[1].reg
;
12731 reject_bad_reg (Rd
);
12732 reject_bad_reg (Rm
);
12734 if (Rd
<= 7 && Rm
<= 7
12735 && inst
.size_req
!= 4)
12737 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12738 inst
.instruction
|= Rd
;
12739 inst
.instruction
|= Rm
<< 3;
12741 else if (unified_syntax
)
12743 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12744 inst
.instruction
|= Rd
<< 8;
12745 inst
.instruction
|= Rm
<< 16;
12746 inst
.instruction
|= Rm
;
12749 inst
.error
= BAD_HIREG
;
12757 Rd
= inst
.operands
[0].reg
;
12758 Rm
= inst
.operands
[1].reg
;
12760 reject_bad_reg (Rd
);
12761 reject_bad_reg (Rm
);
12763 inst
.instruction
|= Rd
<< 8;
12764 inst
.instruction
|= Rm
;
12772 Rd
= inst
.operands
[0].reg
;
12773 Rs
= (inst
.operands
[1].present
12774 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12775 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12777 reject_bad_reg (Rd
);
12778 reject_bad_reg (Rs
);
12779 if (inst
.operands
[2].isreg
)
12780 reject_bad_reg (inst
.operands
[2].reg
);
12782 inst
.instruction
|= Rd
<< 8;
12783 inst
.instruction
|= Rs
<< 16;
12784 if (!inst
.operands
[2].isreg
)
12786 bfd_boolean narrow
;
12788 if ((inst
.instruction
& 0x00100000) != 0)
12789 narrow
= !in_it_block ();
12791 narrow
= in_it_block ();
12793 if (Rd
> 7 || Rs
> 7)
12796 if (inst
.size_req
== 4 || !unified_syntax
)
12799 if (inst
.reloc
.exp
.X_op
!= O_constant
12800 || inst
.reloc
.exp
.X_add_number
!= 0)
12803 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12804 relaxation, but it doesn't seem worth the hassle. */
12807 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12808 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12809 inst
.instruction
|= Rs
<< 3;
12810 inst
.instruction
|= Rd
;
12814 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12815 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12819 encode_thumb32_shifted_operand (2);
12825 if (warn_on_deprecated
12826 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12827 as_tsktsk (_("setend use is deprecated for ARMv8"));
12829 set_it_insn_type (OUTSIDE_IT_INSN
);
12830 if (inst
.operands
[0].imm
)
12831 inst
.instruction
|= 0x8;
12837 if (!inst
.operands
[1].present
)
12838 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12840 if (unified_syntax
)
12842 bfd_boolean narrow
;
12845 switch (inst
.instruction
)
12848 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12850 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12852 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12854 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12858 if (THUMB_SETS_FLAGS (inst
.instruction
))
12859 narrow
= !in_it_block ();
12861 narrow
= in_it_block ();
12862 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12864 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12866 if (inst
.operands
[2].isreg
12867 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12868 || inst
.operands
[2].reg
> 7))
12870 if (inst
.size_req
== 4)
12873 reject_bad_reg (inst
.operands
[0].reg
);
12874 reject_bad_reg (inst
.operands
[1].reg
);
12878 if (inst
.operands
[2].isreg
)
12880 reject_bad_reg (inst
.operands
[2].reg
);
12881 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12882 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12883 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12884 inst
.instruction
|= inst
.operands
[2].reg
;
12886 /* PR 12854: Error on extraneous shifts. */
12887 constraint (inst
.operands
[2].shifted
,
12888 _("extraneous shift as part of operand to shift insn"));
12892 inst
.operands
[1].shifted
= 1;
12893 inst
.operands
[1].shift_kind
= shift_kind
;
12894 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12895 ? T_MNEM_movs
: T_MNEM_mov
);
12896 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12897 encode_thumb32_shifted_operand (1);
12898 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12899 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12904 if (inst
.operands
[2].isreg
)
12906 switch (shift_kind
)
12908 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12909 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12910 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12911 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12915 inst
.instruction
|= inst
.operands
[0].reg
;
12916 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12918 /* PR 12854: Error on extraneous shifts. */
12919 constraint (inst
.operands
[2].shifted
,
12920 _("extraneous shift as part of operand to shift insn"));
12924 switch (shift_kind
)
12926 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12927 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12928 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12931 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12932 inst
.instruction
|= inst
.operands
[0].reg
;
12933 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12939 constraint (inst
.operands
[0].reg
> 7
12940 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12941 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12943 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12945 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12946 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12947 _("source1 and dest must be same register"));
12949 switch (inst
.instruction
)
12951 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12952 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12953 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12954 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12958 inst
.instruction
|= inst
.operands
[0].reg
;
12959 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12961 /* PR 12854: Error on extraneous shifts. */
12962 constraint (inst
.operands
[2].shifted
,
12963 _("extraneous shift as part of operand to shift insn"));
12967 switch (inst
.instruction
)
12969 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12970 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12971 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12972 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12975 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12976 inst
.instruction
|= inst
.operands
[0].reg
;
12977 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12985 unsigned Rd
, Rn
, Rm
;
12987 Rd
= inst
.operands
[0].reg
;
12988 Rn
= inst
.operands
[1].reg
;
12989 Rm
= inst
.operands
[2].reg
;
12991 reject_bad_reg (Rd
);
12992 reject_bad_reg (Rn
);
12993 reject_bad_reg (Rm
);
12995 inst
.instruction
|= Rd
<< 8;
12996 inst
.instruction
|= Rn
<< 16;
12997 inst
.instruction
|= Rm
;
13003 unsigned Rd
, Rn
, Rm
;
13005 Rd
= inst
.operands
[0].reg
;
13006 Rm
= inst
.operands
[1].reg
;
13007 Rn
= inst
.operands
[2].reg
;
13009 reject_bad_reg (Rd
);
13010 reject_bad_reg (Rn
);
13011 reject_bad_reg (Rm
);
13013 inst
.instruction
|= Rd
<< 8;
13014 inst
.instruction
|= Rn
<< 16;
13015 inst
.instruction
|= Rm
;
13021 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
13022 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13023 _("SMC is not permitted on this architecture"));
13024 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
13025 _("expression too complex"));
13026 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13027 inst
.instruction
|= (value
& 0xf000) >> 12;
13028 inst
.instruction
|= (value
& 0x0ff0);
13029 inst
.instruction
|= (value
& 0x000f) << 16;
13030 /* PR gas/15623: SMC instructions must be last in an IT block. */
13031 set_it_insn_type_last ();
13037 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
13039 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13040 inst
.instruction
|= (value
& 0x0fff);
13041 inst
.instruction
|= (value
& 0xf000) << 4;
13045 do_t_ssat_usat (int bias
)
13049 Rd
= inst
.operands
[0].reg
;
13050 Rn
= inst
.operands
[2].reg
;
13052 reject_bad_reg (Rd
);
13053 reject_bad_reg (Rn
);
13055 inst
.instruction
|= Rd
<< 8;
13056 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13057 inst
.instruction
|= Rn
<< 16;
13059 if (inst
.operands
[3].present
)
13061 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
13063 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13065 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
13066 _("expression too complex"));
13068 if (shift_amount
!= 0)
13070 constraint (shift_amount
> 31,
13071 _("shift expression is too large"));
13073 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13074 inst
.instruction
|= 0x00200000; /* sh bit. */
13076 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13077 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13085 do_t_ssat_usat (1);
13093 Rd
= inst
.operands
[0].reg
;
13094 Rn
= inst
.operands
[2].reg
;
13096 reject_bad_reg (Rd
);
13097 reject_bad_reg (Rn
);
13099 inst
.instruction
|= Rd
<< 8;
13100 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13101 inst
.instruction
|= Rn
<< 16;
13107 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13108 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13109 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13110 || inst
.operands
[2].negative
,
13113 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13115 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13116 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13117 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13118 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13124 if (!inst
.operands
[2].present
)
13125 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13127 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13128 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13129 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13132 inst
.instruction
|= inst
.operands
[0].reg
;
13133 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13134 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13135 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13141 unsigned Rd
, Rn
, Rm
;
13143 Rd
= inst
.operands
[0].reg
;
13144 Rn
= inst
.operands
[1].reg
;
13145 Rm
= inst
.operands
[2].reg
;
13147 reject_bad_reg (Rd
);
13148 reject_bad_reg (Rn
);
13149 reject_bad_reg (Rm
);
13151 inst
.instruction
|= Rd
<< 8;
13152 inst
.instruction
|= Rn
<< 16;
13153 inst
.instruction
|= Rm
;
13154 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13162 Rd
= inst
.operands
[0].reg
;
13163 Rm
= inst
.operands
[1].reg
;
13165 reject_bad_reg (Rd
);
13166 reject_bad_reg (Rm
);
13168 if (inst
.instruction
<= 0xffff
13169 && inst
.size_req
!= 4
13170 && Rd
<= 7 && Rm
<= 7
13171 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13173 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13174 inst
.instruction
|= Rd
;
13175 inst
.instruction
|= Rm
<< 3;
13177 else if (unified_syntax
)
13179 if (inst
.instruction
<= 0xffff)
13180 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13181 inst
.instruction
|= Rd
<< 8;
13182 inst
.instruction
|= Rm
;
13183 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13187 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13188 _("Thumb encoding does not support rotation"));
13189 constraint (1, BAD_HIREG
);
13196 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13205 half
= (inst
.instruction
& 0x10) != 0;
13206 set_it_insn_type_last ();
13207 constraint (inst
.operands
[0].immisreg
,
13208 _("instruction requires register index"));
13210 Rn
= inst
.operands
[0].reg
;
13211 Rm
= inst
.operands
[0].imm
;
13213 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13214 constraint (Rn
== REG_SP
, BAD_SP
);
13215 reject_bad_reg (Rm
);
13217 constraint (!half
&& inst
.operands
[0].shifted
,
13218 _("instruction does not allow shifted index"));
13219 inst
.instruction
|= (Rn
<< 16) | Rm
;
13225 if (!inst
.operands
[0].present
)
13226 inst
.operands
[0].imm
= 0;
13228 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13230 constraint (inst
.size_req
== 2,
13231 _("immediate value out of range"));
13232 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13233 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13234 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13238 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13239 inst
.instruction
|= inst
.operands
[0].imm
;
13242 set_it_insn_type (NEUTRAL_IT_INSN
);
13249 do_t_ssat_usat (0);
13257 Rd
= inst
.operands
[0].reg
;
13258 Rn
= inst
.operands
[2].reg
;
13260 reject_bad_reg (Rd
);
13261 reject_bad_reg (Rn
);
13263 inst
.instruction
|= Rd
<< 8;
13264 inst
.instruction
|= inst
.operands
[1].imm
;
13265 inst
.instruction
|= Rn
<< 16;
13268 /* Neon instruction encoder helpers. */
13270 /* Encodings for the different types for various Neon opcodes. */
13272 /* An "invalid" code for the following tables. */
13275 struct neon_tab_entry
13278 unsigned float_or_poly
;
13279 unsigned scalar_or_imm
;
13282 /* Map overloaded Neon opcodes to their respective encodings. */
13283 #define NEON_ENC_TAB \
13284 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13285 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13286 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13287 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13288 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13289 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13290 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13291 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13292 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13293 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13294 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13295 /* Register variants of the following two instructions are encoded as
13296 vcge / vcgt with the operands reversed. */ \
13297 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13298 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13299 X(vfma, N_INV, 0x0000c10, N_INV), \
13300 X(vfms, N_INV, 0x0200c10, N_INV), \
13301 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13302 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13303 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13304 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13305 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13306 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13307 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13308 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13309 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13310 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13311 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13312 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13313 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13314 X(vshl, 0x0000400, N_INV, 0x0800510), \
13315 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13316 X(vand, 0x0000110, N_INV, 0x0800030), \
13317 X(vbic, 0x0100110, N_INV, 0x0800030), \
13318 X(veor, 0x1000110, N_INV, N_INV), \
13319 X(vorn, 0x0300110, N_INV, 0x0800010), \
13320 X(vorr, 0x0200110, N_INV, 0x0800010), \
13321 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13322 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13323 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13324 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13325 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13326 X(vst1, 0x0000000, 0x0800000, N_INV), \
13327 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13328 X(vst2, 0x0000100, 0x0800100, N_INV), \
13329 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13330 X(vst3, 0x0000200, 0x0800200, N_INV), \
13331 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13332 X(vst4, 0x0000300, 0x0800300, N_INV), \
13333 X(vmovn, 0x1b20200, N_INV, N_INV), \
13334 X(vtrn, 0x1b20080, N_INV, N_INV), \
13335 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13336 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13337 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13338 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13339 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13340 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13341 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13342 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13343 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13344 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13345 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13346 X(vseleq, 0xe000a00, N_INV, N_INV), \
13347 X(vselvs, 0xe100a00, N_INV, N_INV), \
13348 X(vselge, 0xe200a00, N_INV, N_INV), \
13349 X(vselgt, 0xe300a00, N_INV, N_INV), \
13350 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13351 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13352 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13353 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13354 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13355 X(aes, 0x3b00300, N_INV, N_INV), \
13356 X(sha3op, 0x2000c00, N_INV, N_INV), \
13357 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13358 X(sha2op, 0x3ba0380, N_INV, N_INV)
13362 #define X(OPC,I,F,S) N_MNEM_##OPC
13367 static const struct neon_tab_entry neon_enc_tab
[] =
13369 #define X(OPC,I,F,S) { (I), (F), (S) }
13374 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13375 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13376 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13377 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13378 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13379 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13380 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13381 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13382 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13383 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13384 #define NEON_ENC_SINGLE_(X) \
13385 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13386 #define NEON_ENC_DOUBLE_(X) \
13387 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13388 #define NEON_ENC_FPV8_(X) \
13389 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13391 #define NEON_ENCODE(type, inst) \
13394 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13395 inst.is_neon = 1; \
13399 #define check_neon_suffixes \
13402 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13404 as_bad (_("invalid neon suffix for non neon instruction")); \
13410 /* Define shapes for instruction operands. The following mnemonic characters
13411 are used in this table:
13413 F - VFP S<n> register
13414 D - Neon D<n> register
13415 Q - Neon Q<n> register
13419 L - D<n> register list
13421 This table is used to generate various data:
13422 - enumerations of the form NS_DDR to be used as arguments to
13424 - a table classifying shapes into single, double, quad, mixed.
13425 - a table used to drive neon_select_shape. */
13427 #define NEON_SHAPE_DEF \
13428 X(3, (D, D, D), DOUBLE), \
13429 X(3, (Q, Q, Q), QUAD), \
13430 X(3, (D, D, I), DOUBLE), \
13431 X(3, (Q, Q, I), QUAD), \
13432 X(3, (D, D, S), DOUBLE), \
13433 X(3, (Q, Q, S), QUAD), \
13434 X(2, (D, D), DOUBLE), \
13435 X(2, (Q, Q), QUAD), \
13436 X(2, (D, S), DOUBLE), \
13437 X(2, (Q, S), QUAD), \
13438 X(2, (D, R), DOUBLE), \
13439 X(2, (Q, R), QUAD), \
13440 X(2, (D, I), DOUBLE), \
13441 X(2, (Q, I), QUAD), \
13442 X(3, (D, L, D), DOUBLE), \
13443 X(2, (D, Q), MIXED), \
13444 X(2, (Q, D), MIXED), \
13445 X(3, (D, Q, I), MIXED), \
13446 X(3, (Q, D, I), MIXED), \
13447 X(3, (Q, D, D), MIXED), \
13448 X(3, (D, Q, Q), MIXED), \
13449 X(3, (Q, Q, D), MIXED), \
13450 X(3, (Q, D, S), MIXED), \
13451 X(3, (D, Q, S), MIXED), \
13452 X(4, (D, D, D, I), DOUBLE), \
13453 X(4, (Q, Q, Q, I), QUAD), \
13454 X(4, (D, D, S, I), DOUBLE), \
13455 X(4, (Q, Q, S, I), QUAD), \
13456 X(2, (F, F), SINGLE), \
13457 X(3, (F, F, F), SINGLE), \
13458 X(2, (F, I), SINGLE), \
13459 X(2, (F, D), MIXED), \
13460 X(2, (D, F), MIXED), \
13461 X(3, (F, F, I), MIXED), \
13462 X(4, (R, R, F, F), SINGLE), \
13463 X(4, (F, F, R, R), SINGLE), \
13464 X(3, (D, R, R), DOUBLE), \
13465 X(3, (R, R, D), DOUBLE), \
13466 X(2, (S, R), SINGLE), \
13467 X(2, (R, S), SINGLE), \
13468 X(2, (F, R), SINGLE), \
13469 X(2, (R, F), SINGLE), \
13470 /* Half float shape supported so far. */\
13471 X (2, (H, D), MIXED), \
13472 X (2, (D, H), MIXED), \
13473 X (2, (H, F), MIXED), \
13474 X (2, (F, H), MIXED), \
13475 X (2, (H, H), HALF), \
13476 X (2, (H, R), HALF), \
13477 X (2, (R, H), HALF), \
13478 X (2, (H, I), HALF), \
13479 X (3, (H, H, H), HALF), \
13480 X (3, (H, F, I), MIXED), \
13481 X (3, (F, H, I), MIXED), \
13482 X (3, (D, H, H), MIXED), \
13483 X (3, (D, H, S), MIXED)
13485 #define S2(A,B) NS_##A##B
13486 #define S3(A,B,C) NS_##A##B##C
13487 #define S4(A,B,C,D) NS_##A##B##C##D
13489 #define X(N, L, C) S##N L
13502 enum neon_shape_class
13511 #define X(N, L, C) SC_##C
13513 static enum neon_shape_class neon_shape_class
[] =
13532 /* Register widths of above. */
13533 static unsigned neon_shape_el_size
[] =
13545 struct neon_shape_info
13548 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13551 #define S2(A,B) { SE_##A, SE_##B }
13552 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13553 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13555 #define X(N, L, C) { N, S##N L }
13557 static struct neon_shape_info neon_shape_tab
[] =
13567 /* Bit masks used in type checking given instructions.
13568 'N_EQK' means the type must be the same as (or based on in some way) the key
13569 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13570 set, various other bits can be set as well in order to modify the meaning of
13571 the type constraint. */
13573 enum neon_type_mask
13597 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13598 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13599 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13600 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13601 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13602 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13603 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13604 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13605 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13606 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13607 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13609 N_MAX_NONSPECIAL
= N_P64
13612 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13614 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13615 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13616 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13617 #define N_S_32 (N_S8 | N_S16 | N_S32)
13618 #define N_F_16_32 (N_F16 | N_F32)
13619 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13620 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13621 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13622 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13624 /* Pass this as the first type argument to neon_check_type to ignore types
13626 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13628 /* Select a "shape" for the current instruction (describing register types or
13629 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13630 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13631 function of operand parsing, so this function doesn't need to be called.
13632 Shapes should be listed in order of decreasing length. */
13634 static enum neon_shape
13635 neon_select_shape (enum neon_shape shape
, ...)
13638 enum neon_shape first_shape
= shape
;
13640 /* Fix missing optional operands. FIXME: we don't know at this point how
13641 many arguments we should have, so this makes the assumption that we have
13642 > 1. This is true of all current Neon opcodes, I think, but may not be
13643 true in the future. */
13644 if (!inst
.operands
[1].present
)
13645 inst
.operands
[1] = inst
.operands
[0];
13647 va_start (ap
, shape
);
13649 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13654 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13656 if (!inst
.operands
[j
].present
)
13662 switch (neon_shape_tab
[shape
].el
[j
])
13664 /* If a .f16, .16, .u16, .s16 type specifier is given over
13665 a VFP single precision register operand, it's essentially
13666 means only half of the register is used.
13668 If the type specifier is given after the mnemonics, the
13669 information is stored in inst.vectype. If the type specifier
13670 is given after register operand, the information is stored
13671 in inst.operands[].vectype.
13673 When there is only one type specifier, and all the register
13674 operands are the same type of hardware register, the type
13675 specifier applies to all register operands.
13677 If no type specifier is given, the shape is inferred from
13678 operand information.
13681 vadd.f16 s0, s1, s2: NS_HHH
13682 vabs.f16 s0, s1: NS_HH
13683 vmov.f16 s0, r1: NS_HR
13684 vmov.f16 r0, s1: NS_RH
13685 vcvt.f16 r0, s1: NS_RH
13686 vcvt.f16.s32 s2, s2, #29: NS_HFI
13687 vcvt.f16.s32 s2, s2: NS_HF
13690 if (!(inst
.operands
[j
].isreg
13691 && inst
.operands
[j
].isvec
13692 && inst
.operands
[j
].issingle
13693 && !inst
.operands
[j
].isquad
13694 && ((inst
.vectype
.elems
== 1
13695 && inst
.vectype
.el
[0].size
== 16)
13696 || (inst
.vectype
.elems
> 1
13697 && inst
.vectype
.el
[j
].size
== 16)
13698 || (inst
.vectype
.elems
== 0
13699 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13700 && inst
.operands
[j
].vectype
.size
== 16))))
13705 if (!(inst
.operands
[j
].isreg
13706 && inst
.operands
[j
].isvec
13707 && inst
.operands
[j
].issingle
13708 && !inst
.operands
[j
].isquad
13709 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13710 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13711 || (inst
.vectype
.elems
== 0
13712 && (inst
.operands
[j
].vectype
.size
== 32
13713 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13718 if (!(inst
.operands
[j
].isreg
13719 && inst
.operands
[j
].isvec
13720 && !inst
.operands
[j
].isquad
13721 && !inst
.operands
[j
].issingle
))
13726 if (!(inst
.operands
[j
].isreg
13727 && !inst
.operands
[j
].isvec
))
13732 if (!(inst
.operands
[j
].isreg
13733 && inst
.operands
[j
].isvec
13734 && inst
.operands
[j
].isquad
13735 && !inst
.operands
[j
].issingle
))
13740 if (!(!inst
.operands
[j
].isreg
13741 && !inst
.operands
[j
].isscalar
))
13746 if (!(!inst
.operands
[j
].isreg
13747 && inst
.operands
[j
].isscalar
))
13757 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13758 /* We've matched all the entries in the shape table, and we don't
13759 have any left over operands which have not been matched. */
13765 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13766 first_error (_("invalid instruction shape"));
13771 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13772 means the Q bit should be set). */
13775 neon_quad (enum neon_shape shape
)
13777 return neon_shape_class
[shape
] == SC_QUAD
;
13781 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13784 /* Allow modification to be made to types which are constrained to be
13785 based on the key element, based on bits set alongside N_EQK. */
13786 if ((typebits
& N_EQK
) != 0)
13788 if ((typebits
& N_HLF
) != 0)
13790 else if ((typebits
& N_DBL
) != 0)
13792 if ((typebits
& N_SGN
) != 0)
13793 *g_type
= NT_signed
;
13794 else if ((typebits
& N_UNS
) != 0)
13795 *g_type
= NT_unsigned
;
13796 else if ((typebits
& N_INT
) != 0)
13797 *g_type
= NT_integer
;
13798 else if ((typebits
& N_FLT
) != 0)
13799 *g_type
= NT_float
;
13800 else if ((typebits
& N_SIZ
) != 0)
13801 *g_type
= NT_untyped
;
13805 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13806 operand type, i.e. the single type specified in a Neon instruction when it
13807 is the only one given. */
13809 static struct neon_type_el
13810 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13812 struct neon_type_el dest
= *key
;
13814 gas_assert ((thisarg
& N_EQK
) != 0);
13816 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13821 /* Convert Neon type and size into compact bitmask representation. */
13823 static enum neon_type_mask
13824 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13831 case 8: return N_8
;
13832 case 16: return N_16
;
13833 case 32: return N_32
;
13834 case 64: return N_64
;
13842 case 8: return N_I8
;
13843 case 16: return N_I16
;
13844 case 32: return N_I32
;
13845 case 64: return N_I64
;
13853 case 16: return N_F16
;
13854 case 32: return N_F32
;
13855 case 64: return N_F64
;
13863 case 8: return N_P8
;
13864 case 16: return N_P16
;
13865 case 64: return N_P64
;
13873 case 8: return N_S8
;
13874 case 16: return N_S16
;
13875 case 32: return N_S32
;
13876 case 64: return N_S64
;
13884 case 8: return N_U8
;
13885 case 16: return N_U16
;
13886 case 32: return N_U32
;
13887 case 64: return N_U64
;
13898 /* Convert compact Neon bitmask type representation to a type and size. Only
13899 handles the case where a single bit is set in the mask. */
13902 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13903 enum neon_type_mask mask
)
13905 if ((mask
& N_EQK
) != 0)
13908 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13910 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13912 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13914 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13919 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13921 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13922 *type
= NT_unsigned
;
13923 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13924 *type
= NT_integer
;
13925 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13926 *type
= NT_untyped
;
13927 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13929 else if ((mask
& (N_F_ALL
)) != 0)
13937 /* Modify a bitmask of allowed types. This is only needed for type
13941 modify_types_allowed (unsigned allowed
, unsigned mods
)
13944 enum neon_el_type type
;
13950 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13952 if (el_type_of_type_chk (&type
, &size
,
13953 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13955 neon_modify_type_size (mods
, &type
, &size
);
13956 destmask
|= type_chk_of_el_type (type
, size
);
13963 /* Check type and return type classification.
13964 The manual states (paraphrase): If one datatype is given, it indicates the
13966 - the second operand, if there is one
13967 - the operand, if there is no second operand
13968 - the result, if there are no operands.
13969 This isn't quite good enough though, so we use a concept of a "key" datatype
13970 which is set on a per-instruction basis, which is the one which matters when
13971 only one data type is written.
13972 Note: this function has side-effects (e.g. filling in missing operands). All
13973 Neon instructions should call it before performing bit encoding. */
13975 static struct neon_type_el
13976 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13979 unsigned i
, pass
, key_el
= 0;
13980 unsigned types
[NEON_MAX_TYPE_ELS
];
13981 enum neon_el_type k_type
= NT_invtype
;
13982 unsigned k_size
= -1u;
13983 struct neon_type_el badtype
= {NT_invtype
, -1};
13984 unsigned key_allowed
= 0;
13986 /* Optional registers in Neon instructions are always (not) in operand 1.
13987 Fill in the missing operand here, if it was omitted. */
13988 if (els
> 1 && !inst
.operands
[1].present
)
13989 inst
.operands
[1] = inst
.operands
[0];
13991 /* Suck up all the varargs. */
13993 for (i
= 0; i
< els
; i
++)
13995 unsigned thisarg
= va_arg (ap
, unsigned);
13996 if (thisarg
== N_IGNORE_TYPE
)
14001 types
[i
] = thisarg
;
14002 if ((thisarg
& N_KEY
) != 0)
14007 if (inst
.vectype
.elems
> 0)
14008 for (i
= 0; i
< els
; i
++)
14009 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
14011 first_error (_("types specified in both the mnemonic and operands"));
14015 /* Duplicate inst.vectype elements here as necessary.
14016 FIXME: No idea if this is exactly the same as the ARM assembler,
14017 particularly when an insn takes one register and one non-register
14019 if (inst
.vectype
.elems
== 1 && els
> 1)
14022 inst
.vectype
.elems
= els
;
14023 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
14024 for (j
= 0; j
< els
; j
++)
14026 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14029 else if (inst
.vectype
.elems
== 0 && els
> 0)
14032 /* No types were given after the mnemonic, so look for types specified
14033 after each operand. We allow some flexibility here; as long as the
14034 "key" operand has a type, we can infer the others. */
14035 for (j
= 0; j
< els
; j
++)
14036 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
14037 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
14039 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
14041 for (j
= 0; j
< els
; j
++)
14042 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
14043 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14048 first_error (_("operand types can't be inferred"));
14052 else if (inst
.vectype
.elems
!= els
)
14054 first_error (_("type specifier has the wrong number of parts"));
14058 for (pass
= 0; pass
< 2; pass
++)
14060 for (i
= 0; i
< els
; i
++)
14062 unsigned thisarg
= types
[i
];
14063 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
14064 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
14065 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
14066 unsigned g_size
= inst
.vectype
.el
[i
].size
;
14068 /* Decay more-specific signed & unsigned types to sign-insensitive
14069 integer types if sign-specific variants are unavailable. */
14070 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
14071 && (types_allowed
& N_SU_ALL
) == 0)
14072 g_type
= NT_integer
;
14074 /* If only untyped args are allowed, decay any more specific types to
14075 them. Some instructions only care about signs for some element
14076 sizes, so handle that properly. */
14077 if (((types_allowed
& N_UNT
) == 0)
14078 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14079 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14080 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
14081 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
14082 g_type
= NT_untyped
;
14086 if ((thisarg
& N_KEY
) != 0)
14090 key_allowed
= thisarg
& ~N_KEY
;
14092 /* Check architecture constraint on FP16 extension. */
14094 && k_type
== NT_float
14095 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14097 inst
.error
= _(BAD_FP16
);
14104 if ((thisarg
& N_VFP
) != 0)
14106 enum neon_shape_el regshape
;
14107 unsigned regwidth
, match
;
14109 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14112 first_error (_("invalid instruction shape"));
14115 regshape
= neon_shape_tab
[ns
].el
[i
];
14116 regwidth
= neon_shape_el_size
[regshape
];
14118 /* In VFP mode, operands must match register widths. If we
14119 have a key operand, use its width, else use the width of
14120 the current operand. */
14126 /* FP16 will use a single precision register. */
14127 if (regwidth
== 32 && match
== 16)
14129 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14133 inst
.error
= _(BAD_FP16
);
14138 if (regwidth
!= match
)
14140 first_error (_("operand size must match register width"));
14145 if ((thisarg
& N_EQK
) == 0)
14147 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14149 if ((given_type
& types_allowed
) == 0)
14151 first_error (_("bad type in Neon instruction"));
14157 enum neon_el_type mod_k_type
= k_type
;
14158 unsigned mod_k_size
= k_size
;
14159 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14160 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14162 first_error (_("inconsistent types in Neon instruction"));
14170 return inst
.vectype
.el
[key_el
];
14173 /* Neon-style VFP instruction forwarding. */
14175 /* Thumb VFP instructions have 0xE in the condition field. */
14178 do_vfp_cond_or_thumb (void)
14183 inst
.instruction
|= 0xe0000000;
14185 inst
.instruction
|= inst
.cond
<< 28;
14188 /* Look up and encode a simple mnemonic, for use as a helper function for the
14189 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14190 etc. It is assumed that operand parsing has already been done, and that the
14191 operands are in the form expected by the given opcode (this isn't necessarily
14192 the same as the form in which they were parsed, hence some massaging must
14193 take place before this function is called).
14194 Checks current arch version against that in the looked-up opcode. */
14197 do_vfp_nsyn_opcode (const char *opname
)
14199 const struct asm_opcode
*opcode
;
14201 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14206 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14207 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14214 inst
.instruction
= opcode
->tvalue
;
14215 opcode
->tencode ();
14219 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14220 opcode
->aencode ();
14225 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14227 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14229 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14232 do_vfp_nsyn_opcode ("fadds");
14234 do_vfp_nsyn_opcode ("fsubs");
14236 /* ARMv8.2 fp16 instruction. */
14238 do_scalar_fp16_v82_encode ();
14243 do_vfp_nsyn_opcode ("faddd");
14245 do_vfp_nsyn_opcode ("fsubd");
14249 /* Check operand types to see if this is a VFP instruction, and if so call
14253 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14255 enum neon_shape rs
;
14256 struct neon_type_el et
;
14261 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14262 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14266 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14267 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14268 N_F_ALL
| N_KEY
| N_VFP
);
14275 if (et
.type
!= NT_invtype
)
14286 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14288 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14290 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14293 do_vfp_nsyn_opcode ("fmacs");
14295 do_vfp_nsyn_opcode ("fnmacs");
14297 /* ARMv8.2 fp16 instruction. */
14299 do_scalar_fp16_v82_encode ();
14304 do_vfp_nsyn_opcode ("fmacd");
14306 do_vfp_nsyn_opcode ("fnmacd");
14311 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14313 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14315 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14318 do_vfp_nsyn_opcode ("ffmas");
14320 do_vfp_nsyn_opcode ("ffnmas");
14322 /* ARMv8.2 fp16 instruction. */
14324 do_scalar_fp16_v82_encode ();
14329 do_vfp_nsyn_opcode ("ffmad");
14331 do_vfp_nsyn_opcode ("ffnmad");
14336 do_vfp_nsyn_mul (enum neon_shape rs
)
14338 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14340 do_vfp_nsyn_opcode ("fmuls");
14342 /* ARMv8.2 fp16 instruction. */
14344 do_scalar_fp16_v82_encode ();
14347 do_vfp_nsyn_opcode ("fmuld");
14351 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14353 int is_neg
= (inst
.instruction
& 0x80) != 0;
14354 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14356 if (rs
== NS_FF
|| rs
== NS_HH
)
14359 do_vfp_nsyn_opcode ("fnegs");
14361 do_vfp_nsyn_opcode ("fabss");
14363 /* ARMv8.2 fp16 instruction. */
14365 do_scalar_fp16_v82_encode ();
14370 do_vfp_nsyn_opcode ("fnegd");
14372 do_vfp_nsyn_opcode ("fabsd");
14376 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14377 insns belong to Neon, and are handled elsewhere. */
14380 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14382 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14386 do_vfp_nsyn_opcode ("fldmdbs");
14388 do_vfp_nsyn_opcode ("fldmias");
14393 do_vfp_nsyn_opcode ("fstmdbs");
14395 do_vfp_nsyn_opcode ("fstmias");
14400 do_vfp_nsyn_sqrt (void)
14402 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14403 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14405 if (rs
== NS_FF
|| rs
== NS_HH
)
14407 do_vfp_nsyn_opcode ("fsqrts");
14409 /* ARMv8.2 fp16 instruction. */
14411 do_scalar_fp16_v82_encode ();
14414 do_vfp_nsyn_opcode ("fsqrtd");
14418 do_vfp_nsyn_div (void)
14420 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14421 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14422 N_F_ALL
| N_KEY
| N_VFP
);
14424 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14426 do_vfp_nsyn_opcode ("fdivs");
14428 /* ARMv8.2 fp16 instruction. */
14430 do_scalar_fp16_v82_encode ();
14433 do_vfp_nsyn_opcode ("fdivd");
14437 do_vfp_nsyn_nmul (void)
14439 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14440 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14441 N_F_ALL
| N_KEY
| N_VFP
);
14443 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14445 NEON_ENCODE (SINGLE
, inst
);
14446 do_vfp_sp_dyadic ();
14448 /* ARMv8.2 fp16 instruction. */
14450 do_scalar_fp16_v82_encode ();
14454 NEON_ENCODE (DOUBLE
, inst
);
14455 do_vfp_dp_rd_rn_rm ();
14457 do_vfp_cond_or_thumb ();
14462 do_vfp_nsyn_cmp (void)
14464 enum neon_shape rs
;
14465 if (inst
.operands
[1].isreg
)
14467 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14468 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14470 if (rs
== NS_FF
|| rs
== NS_HH
)
14472 NEON_ENCODE (SINGLE
, inst
);
14473 do_vfp_sp_monadic ();
14477 NEON_ENCODE (DOUBLE
, inst
);
14478 do_vfp_dp_rd_rm ();
14483 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14484 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14486 switch (inst
.instruction
& 0x0fffffff)
14489 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14492 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14498 if (rs
== NS_FI
|| rs
== NS_HI
)
14500 NEON_ENCODE (SINGLE
, inst
);
14501 do_vfp_sp_compare_z ();
14505 NEON_ENCODE (DOUBLE
, inst
);
14509 do_vfp_cond_or_thumb ();
14511 /* ARMv8.2 fp16 instruction. */
14512 if (rs
== NS_HI
|| rs
== NS_HH
)
14513 do_scalar_fp16_v82_encode ();
14517 nsyn_insert_sp (void)
14519 inst
.operands
[1] = inst
.operands
[0];
14520 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14521 inst
.operands
[0].reg
= REG_SP
;
14522 inst
.operands
[0].isreg
= 1;
14523 inst
.operands
[0].writeback
= 1;
14524 inst
.operands
[0].present
= 1;
14528 do_vfp_nsyn_push (void)
14532 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14533 _("register list must contain at least 1 and at most 16 "
14536 if (inst
.operands
[1].issingle
)
14537 do_vfp_nsyn_opcode ("fstmdbs");
14539 do_vfp_nsyn_opcode ("fstmdbd");
14543 do_vfp_nsyn_pop (void)
14547 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14548 _("register list must contain at least 1 and at most 16 "
14551 if (inst
.operands
[1].issingle
)
14552 do_vfp_nsyn_opcode ("fldmias");
14554 do_vfp_nsyn_opcode ("fldmiad");
14557 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14558 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14561 neon_dp_fixup (struct arm_it
* insn
)
14563 unsigned int i
= insn
->instruction
;
14568 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14579 insn
->instruction
= i
;
14582 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14586 neon_logbits (unsigned x
)
14588 return ffs (x
) - 4;
14591 #define LOW4(R) ((R) & 0xf)
14592 #define HI1(R) (((R) >> 4) & 1)
14594 /* Encode insns with bit pattern:
14596 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14597 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14599 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14600 different meaning for some instruction. */
14603 neon_three_same (int isquad
, int ubit
, int size
)
14605 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14606 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14607 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14608 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14609 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14610 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14611 inst
.instruction
|= (isquad
!= 0) << 6;
14612 inst
.instruction
|= (ubit
!= 0) << 24;
14614 inst
.instruction
|= neon_logbits (size
) << 20;
14616 neon_dp_fixup (&inst
);
14619 /* Encode instructions of the form:
14621 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14622 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14624 Don't write size if SIZE == -1. */
14627 neon_two_same (int qbit
, int ubit
, int size
)
14629 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14630 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14631 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14632 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14633 inst
.instruction
|= (qbit
!= 0) << 6;
14634 inst
.instruction
|= (ubit
!= 0) << 24;
14637 inst
.instruction
|= neon_logbits (size
) << 18;
14639 neon_dp_fixup (&inst
);
14642 /* Neon instruction encoders, in approximate order of appearance. */
14645 do_neon_dyadic_i_su (void)
14647 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14648 struct neon_type_el et
= neon_check_type (3, rs
,
14649 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14650 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14654 do_neon_dyadic_i64_su (void)
14656 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14657 struct neon_type_el et
= neon_check_type (3, rs
,
14658 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14659 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14663 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14666 unsigned size
= et
.size
>> 3;
14667 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14668 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14669 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14670 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14671 inst
.instruction
|= (isquad
!= 0) << 6;
14672 inst
.instruction
|= immbits
<< 16;
14673 inst
.instruction
|= (size
>> 3) << 7;
14674 inst
.instruction
|= (size
& 0x7) << 19;
14676 inst
.instruction
|= (uval
!= 0) << 24;
14678 neon_dp_fixup (&inst
);
14682 do_neon_shl_imm (void)
14684 if (!inst
.operands
[2].isreg
)
14686 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14687 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14688 int imm
= inst
.operands
[2].imm
;
14690 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14691 _("immediate out of range for shift"));
14692 NEON_ENCODE (IMMED
, inst
);
14693 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14697 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14698 struct neon_type_el et
= neon_check_type (3, rs
,
14699 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14702 /* VSHL/VQSHL 3-register variants have syntax such as:
14704 whereas other 3-register operations encoded by neon_three_same have
14707 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14709 tmp
= inst
.operands
[2].reg
;
14710 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14711 inst
.operands
[1].reg
= tmp
;
14712 NEON_ENCODE (INTEGER
, inst
);
14713 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14718 do_neon_qshl_imm (void)
14720 if (!inst
.operands
[2].isreg
)
14722 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14723 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14724 int imm
= inst
.operands
[2].imm
;
14726 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14727 _("immediate out of range for shift"));
14728 NEON_ENCODE (IMMED
, inst
);
14729 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14733 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14734 struct neon_type_el et
= neon_check_type (3, rs
,
14735 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14738 /* See note in do_neon_shl_imm. */
14739 tmp
= inst
.operands
[2].reg
;
14740 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14741 inst
.operands
[1].reg
= tmp
;
14742 NEON_ENCODE (INTEGER
, inst
);
14743 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14748 do_neon_rshl (void)
14750 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14751 struct neon_type_el et
= neon_check_type (3, rs
,
14752 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14755 tmp
= inst
.operands
[2].reg
;
14756 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14757 inst
.operands
[1].reg
= tmp
;
14758 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14762 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14764 /* Handle .I8 pseudo-instructions. */
14767 /* Unfortunately, this will make everything apart from zero out-of-range.
14768 FIXME is this the intended semantics? There doesn't seem much point in
14769 accepting .I8 if so. */
14770 immediate
|= immediate
<< 8;
14776 if (immediate
== (immediate
& 0x000000ff))
14778 *immbits
= immediate
;
14781 else if (immediate
== (immediate
& 0x0000ff00))
14783 *immbits
= immediate
>> 8;
14786 else if (immediate
== (immediate
& 0x00ff0000))
14788 *immbits
= immediate
>> 16;
14791 else if (immediate
== (immediate
& 0xff000000))
14793 *immbits
= immediate
>> 24;
14796 if ((immediate
& 0xffff) != (immediate
>> 16))
14797 goto bad_immediate
;
14798 immediate
&= 0xffff;
14801 if (immediate
== (immediate
& 0x000000ff))
14803 *immbits
= immediate
;
14806 else if (immediate
== (immediate
& 0x0000ff00))
14808 *immbits
= immediate
>> 8;
14813 first_error (_("immediate value out of range"));
14818 do_neon_logic (void)
14820 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14822 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14823 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14824 /* U bit and size field were set as part of the bitmask. */
14825 NEON_ENCODE (INTEGER
, inst
);
14826 neon_three_same (neon_quad (rs
), 0, -1);
14830 const int three_ops_form
= (inst
.operands
[2].present
14831 && !inst
.operands
[2].isreg
);
14832 const int immoperand
= (three_ops_form
? 2 : 1);
14833 enum neon_shape rs
= (three_ops_form
14834 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14835 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14836 struct neon_type_el et
= neon_check_type (2, rs
,
14837 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14838 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14842 if (et
.type
== NT_invtype
)
14845 if (three_ops_form
)
14846 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14847 _("first and second operands shall be the same register"));
14849 NEON_ENCODE (IMMED
, inst
);
14851 immbits
= inst
.operands
[immoperand
].imm
;
14854 /* .i64 is a pseudo-op, so the immediate must be a repeating
14856 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14857 inst
.operands
[immoperand
].reg
: 0))
14859 /* Set immbits to an invalid constant. */
14860 immbits
= 0xdeadbeef;
14867 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14871 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14875 /* Pseudo-instruction for VBIC. */
14876 neon_invert_size (&immbits
, 0, et
.size
);
14877 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14881 /* Pseudo-instruction for VORR. */
14882 neon_invert_size (&immbits
, 0, et
.size
);
14883 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14893 inst
.instruction
|= neon_quad (rs
) << 6;
14894 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14895 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14896 inst
.instruction
|= cmode
<< 8;
14897 neon_write_immbits (immbits
);
14899 neon_dp_fixup (&inst
);
14904 do_neon_bitfield (void)
14906 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14907 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14908 neon_three_same (neon_quad (rs
), 0, -1);
14912 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14915 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14916 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14918 if (et
.type
== NT_float
)
14920 NEON_ENCODE (FLOAT
, inst
);
14921 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14925 NEON_ENCODE (INTEGER
, inst
);
14926 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14931 do_neon_dyadic_if_su (void)
14933 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14937 do_neon_dyadic_if_su_d (void)
14939 /* This version only allow D registers, but that constraint is enforced during
14940 operand parsing so we don't need to do anything extra here. */
14941 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14945 do_neon_dyadic_if_i_d (void)
14947 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14948 affected if we specify unsigned args. */
14949 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14952 enum vfp_or_neon_is_neon_bits
14955 NEON_CHECK_ARCH
= 2,
14956 NEON_CHECK_ARCH8
= 4
14959 /* Call this function if an instruction which may have belonged to the VFP or
14960 Neon instruction sets, but turned out to be a Neon instruction (due to the
14961 operand types involved, etc.). We have to check and/or fix-up a couple of
14964 - Make sure the user hasn't attempted to make a Neon instruction
14966 - Alter the value in the condition code field if necessary.
14967 - Make sure that the arch supports Neon instructions.
14969 Which of these operations take place depends on bits from enum
14970 vfp_or_neon_is_neon_bits.
14972 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14973 current instruction's condition is COND_ALWAYS, the condition field is
14974 changed to inst.uncond_value. This is necessary because instructions shared
14975 between VFP and Neon may be conditional for the VFP variants only, and the
14976 unconditional Neon version must have, e.g., 0xF in the condition field. */
14979 vfp_or_neon_is_neon (unsigned check
)
14981 /* Conditions are always legal in Thumb mode (IT blocks). */
14982 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14984 if (inst
.cond
!= COND_ALWAYS
)
14986 first_error (_(BAD_COND
));
14989 if (inst
.uncond_value
!= -1)
14990 inst
.instruction
|= inst
.uncond_value
<< 28;
14993 if ((check
& NEON_CHECK_ARCH
)
14994 && !mark_feature_used (&fpu_neon_ext_v1
))
14996 first_error (_(BAD_FPU
));
15000 if ((check
& NEON_CHECK_ARCH8
)
15001 && !mark_feature_used (&fpu_neon_ext_armv8
))
15003 first_error (_(BAD_FPU
));
15011 do_neon_addsub_if_i (void)
15013 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
15016 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15019 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15020 affected if we specify unsigned args. */
15021 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
15024 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
15026 V<op> A,B (A is operand 0, B is operand 2)
15031 so handle that case specially. */
15034 neon_exchange_operands (void)
15036 if (inst
.operands
[1].present
)
15038 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
15040 /* Swap operands[1] and operands[2]. */
15041 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
15042 inst
.operands
[1] = inst
.operands
[2];
15043 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
15048 inst
.operands
[1] = inst
.operands
[2];
15049 inst
.operands
[2] = inst
.operands
[0];
15054 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
15056 if (inst
.operands
[2].isreg
)
15059 neon_exchange_operands ();
15060 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
15064 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15065 struct neon_type_el et
= neon_check_type (2, rs
,
15066 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
15068 NEON_ENCODE (IMMED
, inst
);
15069 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15070 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15071 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15072 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15073 inst
.instruction
|= neon_quad (rs
) << 6;
15074 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15075 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15077 neon_dp_fixup (&inst
);
15084 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
15088 do_neon_cmp_inv (void)
15090 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
15096 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
15099 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
15100 scalars, which are encoded in 5 bits, M : Rm.
15101 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
15102 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
15105 Dot Product instructions are similar to multiply instructions except elsize
15106 should always be 32.
15108 This function translates SCALAR, which is GAS's internal encoding of indexed
15109 scalar register, to raw encoding. There is also register and index range
15110 check based on ELSIZE. */
15113 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
15115 unsigned regno
= NEON_SCALAR_REG (scalar
);
15116 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15121 if (regno
> 7 || elno
> 3)
15123 return regno
| (elno
<< 3);
15126 if (regno
> 15 || elno
> 1)
15128 return regno
| (elno
<< 4);
15132 first_error (_("scalar out of range for multiply instruction"));
15138 /* Encode multiply / multiply-accumulate scalar instructions. */
15141 neon_mul_mac (struct neon_type_el et
, int ubit
)
15145 /* Give a more helpful error message if we have an invalid type. */
15146 if (et
.type
== NT_invtype
)
15149 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15150 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15151 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15152 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15153 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15154 inst
.instruction
|= LOW4 (scalar
);
15155 inst
.instruction
|= HI1 (scalar
) << 5;
15156 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15157 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15158 inst
.instruction
|= (ubit
!= 0) << 24;
15160 neon_dp_fixup (&inst
);
15164 do_neon_mac_maybe_scalar (void)
15166 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15169 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15172 if (inst
.operands
[2].isscalar
)
15174 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15175 struct neon_type_el et
= neon_check_type (3, rs
,
15176 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15177 NEON_ENCODE (SCALAR
, inst
);
15178 neon_mul_mac (et
, neon_quad (rs
));
15182 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15183 affected if we specify unsigned args. */
15184 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15189 do_neon_fmac (void)
15191 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15194 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15197 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15203 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15204 struct neon_type_el et
= neon_check_type (3, rs
,
15205 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15206 neon_three_same (neon_quad (rs
), 0, et
.size
);
15209 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15210 same types as the MAC equivalents. The polynomial type for this instruction
15211 is encoded the same as the integer type. */
15216 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15219 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15222 if (inst
.operands
[2].isscalar
)
15223 do_neon_mac_maybe_scalar ();
15225 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15229 do_neon_qdmulh (void)
15231 if (inst
.operands
[2].isscalar
)
15233 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15234 struct neon_type_el et
= neon_check_type (3, rs
,
15235 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15236 NEON_ENCODE (SCALAR
, inst
);
15237 neon_mul_mac (et
, neon_quad (rs
));
15241 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15242 struct neon_type_el et
= neon_check_type (3, rs
,
15243 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15244 NEON_ENCODE (INTEGER
, inst
);
15245 /* The U bit (rounding) comes from bit mask. */
15246 neon_three_same (neon_quad (rs
), 0, et
.size
);
15251 do_neon_qrdmlah (void)
15253 /* Check we're on the correct architecture. */
15254 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15256 _("instruction form not available on this architecture.");
15257 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15259 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15260 record_feature_use (&fpu_neon_ext_v8_1
);
15263 if (inst
.operands
[2].isscalar
)
15265 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15266 struct neon_type_el et
= neon_check_type (3, rs
,
15267 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15268 NEON_ENCODE (SCALAR
, inst
);
15269 neon_mul_mac (et
, neon_quad (rs
));
15273 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15274 struct neon_type_el et
= neon_check_type (3, rs
,
15275 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15276 NEON_ENCODE (INTEGER
, inst
);
15277 /* The U bit (rounding) comes from bit mask. */
15278 neon_three_same (neon_quad (rs
), 0, et
.size
);
15283 do_neon_fcmp_absolute (void)
15285 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15286 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15287 N_F_16_32
| N_KEY
);
15288 /* Size field comes from bit mask. */
15289 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15293 do_neon_fcmp_absolute_inv (void)
15295 neon_exchange_operands ();
15296 do_neon_fcmp_absolute ();
15300 do_neon_step (void)
15302 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15303 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15304 N_F_16_32
| N_KEY
);
15305 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15309 do_neon_abs_neg (void)
15311 enum neon_shape rs
;
15312 struct neon_type_el et
;
15314 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15317 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15320 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15321 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15323 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15324 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15325 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15326 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15327 inst
.instruction
|= neon_quad (rs
) << 6;
15328 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15329 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15331 neon_dp_fixup (&inst
);
15337 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15338 struct neon_type_el et
= neon_check_type (2, rs
,
15339 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15340 int imm
= inst
.operands
[2].imm
;
15341 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15342 _("immediate out of range for insert"));
15343 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15349 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15350 struct neon_type_el et
= neon_check_type (2, rs
,
15351 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15352 int imm
= inst
.operands
[2].imm
;
15353 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15354 _("immediate out of range for insert"));
15355 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15359 do_neon_qshlu_imm (void)
15361 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15362 struct neon_type_el et
= neon_check_type (2, rs
,
15363 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15364 int imm
= inst
.operands
[2].imm
;
15365 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15366 _("immediate out of range for shift"));
15367 /* Only encodes the 'U present' variant of the instruction.
15368 In this case, signed types have OP (bit 8) set to 0.
15369 Unsigned types have OP set to 1. */
15370 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15371 /* The rest of the bits are the same as other immediate shifts. */
15372 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15376 do_neon_qmovn (void)
15378 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15379 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15380 /* Saturating move where operands can be signed or unsigned, and the
15381 destination has the same signedness. */
15382 NEON_ENCODE (INTEGER
, inst
);
15383 if (et
.type
== NT_unsigned
)
15384 inst
.instruction
|= 0xc0;
15386 inst
.instruction
|= 0x80;
15387 neon_two_same (0, 1, et
.size
/ 2);
15391 do_neon_qmovun (void)
15393 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15394 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15395 /* Saturating move with unsigned results. Operands must be signed. */
15396 NEON_ENCODE (INTEGER
, inst
);
15397 neon_two_same (0, 1, et
.size
/ 2);
15401 do_neon_rshift_sat_narrow (void)
15403 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15404 or unsigned. If operands are unsigned, results must also be unsigned. */
15405 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15406 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15407 int imm
= inst
.operands
[2].imm
;
15408 /* This gets the bounds check, size encoding and immediate bits calculation
15412 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15413 VQMOVN.I<size> <Dd>, <Qm>. */
15416 inst
.operands
[2].present
= 0;
15417 inst
.instruction
= N_MNEM_vqmovn
;
15422 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15423 _("immediate out of range"));
15424 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15428 do_neon_rshift_sat_narrow_u (void)
15430 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15431 or unsigned. If operands are unsigned, results must also be unsigned. */
15432 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15433 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15434 int imm
= inst
.operands
[2].imm
;
15435 /* This gets the bounds check, size encoding and immediate bits calculation
15439 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15440 VQMOVUN.I<size> <Dd>, <Qm>. */
15443 inst
.operands
[2].present
= 0;
15444 inst
.instruction
= N_MNEM_vqmovun
;
15449 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15450 _("immediate out of range"));
15451 /* FIXME: The manual is kind of unclear about what value U should have in
15452 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15454 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15458 do_neon_movn (void)
15460 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15461 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15462 NEON_ENCODE (INTEGER
, inst
);
15463 neon_two_same (0, 1, et
.size
/ 2);
15467 do_neon_rshift_narrow (void)
15469 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15470 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15471 int imm
= inst
.operands
[2].imm
;
15472 /* This gets the bounds check, size encoding and immediate bits calculation
15476 /* If immediate is zero then we are a pseudo-instruction for
15477 VMOVN.I<size> <Dd>, <Qm> */
15480 inst
.operands
[2].present
= 0;
15481 inst
.instruction
= N_MNEM_vmovn
;
15486 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15487 _("immediate out of range for narrowing operation"));
15488 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15492 do_neon_shll (void)
15494 /* FIXME: Type checking when lengthening. */
15495 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15496 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15497 unsigned imm
= inst
.operands
[2].imm
;
15499 if (imm
== et
.size
)
15501 /* Maximum shift variant. */
15502 NEON_ENCODE (INTEGER
, inst
);
15503 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15504 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15505 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15506 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15507 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15509 neon_dp_fixup (&inst
);
15513 /* A more-specific type check for non-max versions. */
15514 et
= neon_check_type (2, NS_QDI
,
15515 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15516 NEON_ENCODE (IMMED
, inst
);
15517 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15521 /* Check the various types for the VCVT instruction, and return which version
15522 the current instruction is. */
15524 #define CVT_FLAVOUR_VAR \
15525 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15526 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15527 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15528 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15529 /* Half-precision conversions. */ \
15530 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15531 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15532 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15533 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15534 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15535 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15536 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15537 Compared with single/double precision variants, only the co-processor \
15538 field is different, so the encoding flow is reused here. */ \
15539 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15540 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15541 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15542 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15543 /* VFP instructions. */ \
15544 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15545 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15546 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15547 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15548 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15549 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15550 /* VFP instructions with bitshift. */ \
15551 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15552 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15553 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15554 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15555 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15556 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15557 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15558 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15560 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15561 neon_cvt_flavour_##C,
15563 /* The different types of conversions we can do. */
15564 enum neon_cvt_flavour
15567 neon_cvt_flavour_invalid
,
15568 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15573 static enum neon_cvt_flavour
15574 get_neon_cvt_flavour (enum neon_shape rs
)
15576 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15577 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15578 if (et.type != NT_invtype) \
15580 inst.error = NULL; \
15581 return (neon_cvt_flavour_##C); \
15584 struct neon_type_el et
;
15585 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15586 || rs
== NS_FF
) ? N_VFP
: 0;
15587 /* The instruction versions which take an immediate take one register
15588 argument, which is extended to the width of the full register. Thus the
15589 "source" and "destination" registers must have the same width. Hack that
15590 here by making the size equal to the key (wider, in this case) operand. */
15591 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15595 return neon_cvt_flavour_invalid
;
15610 /* Neon-syntax VFP conversions. */
15613 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15615 const char *opname
= 0;
15617 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15618 || rs
== NS_FHI
|| rs
== NS_HFI
)
15620 /* Conversions with immediate bitshift. */
15621 const char *enc
[] =
15623 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15629 if (flavour
< (int) ARRAY_SIZE (enc
))
15631 opname
= enc
[flavour
];
15632 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15633 _("operands 0 and 1 must be the same register"));
15634 inst
.operands
[1] = inst
.operands
[2];
15635 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15640 /* Conversions without bitshift. */
15641 const char *enc
[] =
15643 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15649 if (flavour
< (int) ARRAY_SIZE (enc
))
15650 opname
= enc
[flavour
];
15654 do_vfp_nsyn_opcode (opname
);
15656 /* ARMv8.2 fp16 VCVT instruction. */
15657 if (flavour
== neon_cvt_flavour_s32_f16
15658 || flavour
== neon_cvt_flavour_u32_f16
15659 || flavour
== neon_cvt_flavour_f16_u32
15660 || flavour
== neon_cvt_flavour_f16_s32
)
15661 do_scalar_fp16_v82_encode ();
15665 do_vfp_nsyn_cvtz (void)
15667 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15668 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15669 const char *enc
[] =
15671 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15677 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15678 do_vfp_nsyn_opcode (enc
[flavour
]);
15682 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15683 enum neon_cvt_mode mode
)
15688 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15689 D register operands. */
15690 if (flavour
== neon_cvt_flavour_s32_f64
15691 || flavour
== neon_cvt_flavour_u32_f64
)
15692 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15695 if (flavour
== neon_cvt_flavour_s32_f16
15696 || flavour
== neon_cvt_flavour_u32_f16
)
15697 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15700 set_it_insn_type (OUTSIDE_IT_INSN
);
15704 case neon_cvt_flavour_s32_f64
:
15708 case neon_cvt_flavour_s32_f32
:
15712 case neon_cvt_flavour_s32_f16
:
15716 case neon_cvt_flavour_u32_f64
:
15720 case neon_cvt_flavour_u32_f32
:
15724 case neon_cvt_flavour_u32_f16
:
15729 first_error (_("invalid instruction shape"));
15735 case neon_cvt_mode_a
: rm
= 0; break;
15736 case neon_cvt_mode_n
: rm
= 1; break;
15737 case neon_cvt_mode_p
: rm
= 2; break;
15738 case neon_cvt_mode_m
: rm
= 3; break;
15739 default: first_error (_("invalid rounding mode")); return;
15742 NEON_ENCODE (FPV8
, inst
);
15743 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15744 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15745 inst
.instruction
|= sz
<< 8;
15747 /* ARMv8.2 fp16 VCVT instruction. */
15748 if (flavour
== neon_cvt_flavour_s32_f16
15749 ||flavour
== neon_cvt_flavour_u32_f16
)
15750 do_scalar_fp16_v82_encode ();
15751 inst
.instruction
|= op
<< 7;
15752 inst
.instruction
|= rm
<< 16;
15753 inst
.instruction
|= 0xf0000000;
15754 inst
.is_neon
= TRUE
;
15758 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15760 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15761 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15762 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15764 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15766 if (flavour
== neon_cvt_flavour_invalid
)
15769 /* PR11109: Handle round-to-zero for VCVT conversions. */
15770 if (mode
== neon_cvt_mode_z
15771 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15772 && (flavour
== neon_cvt_flavour_s16_f16
15773 || flavour
== neon_cvt_flavour_u16_f16
15774 || flavour
== neon_cvt_flavour_s32_f32
15775 || flavour
== neon_cvt_flavour_u32_f32
15776 || flavour
== neon_cvt_flavour_s32_f64
15777 || flavour
== neon_cvt_flavour_u32_f64
)
15778 && (rs
== NS_FD
|| rs
== NS_FF
))
15780 do_vfp_nsyn_cvtz ();
15784 /* ARMv8.2 fp16 VCVT conversions. */
15785 if (mode
== neon_cvt_mode_z
15786 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15787 && (flavour
== neon_cvt_flavour_s32_f16
15788 || flavour
== neon_cvt_flavour_u32_f16
)
15791 do_vfp_nsyn_cvtz ();
15792 do_scalar_fp16_v82_encode ();
15796 /* VFP rather than Neon conversions. */
15797 if (flavour
>= neon_cvt_flavour_first_fp
)
15799 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15800 do_vfp_nsyn_cvt (rs
, flavour
);
15802 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15813 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15814 0x0000100, 0x1000100, 0x0, 0x1000000};
15816 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15819 /* Fixed-point conversion with #0 immediate is encoded as an
15820 integer conversion. */
15821 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15823 NEON_ENCODE (IMMED
, inst
);
15824 if (flavour
!= neon_cvt_flavour_invalid
)
15825 inst
.instruction
|= enctab
[flavour
];
15826 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15827 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15828 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15829 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15830 inst
.instruction
|= neon_quad (rs
) << 6;
15831 inst
.instruction
|= 1 << 21;
15832 if (flavour
< neon_cvt_flavour_s16_f16
)
15834 inst
.instruction
|= 1 << 21;
15835 immbits
= 32 - inst
.operands
[2].imm
;
15836 inst
.instruction
|= immbits
<< 16;
15840 inst
.instruction
|= 3 << 20;
15841 immbits
= 16 - inst
.operands
[2].imm
;
15842 inst
.instruction
|= immbits
<< 16;
15843 inst
.instruction
&= ~(1 << 9);
15846 neon_dp_fixup (&inst
);
15852 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15854 NEON_ENCODE (FLOAT
, inst
);
15855 set_it_insn_type (OUTSIDE_IT_INSN
);
15857 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15860 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15861 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15862 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15863 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15864 inst
.instruction
|= neon_quad (rs
) << 6;
15865 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15866 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15867 inst
.instruction
|= mode
<< 8;
15868 if (flavour
== neon_cvt_flavour_u16_f16
15869 || flavour
== neon_cvt_flavour_s16_f16
)
15870 /* Mask off the original size bits and reencode them. */
15871 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15874 inst
.instruction
|= 0xfc000000;
15876 inst
.instruction
|= 0xf0000000;
15882 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15883 0x100, 0x180, 0x0, 0x080};
15885 NEON_ENCODE (INTEGER
, inst
);
15887 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15890 if (flavour
!= neon_cvt_flavour_invalid
)
15891 inst
.instruction
|= enctab
[flavour
];
15893 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15894 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15895 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15896 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15897 inst
.instruction
|= neon_quad (rs
) << 6;
15898 if (flavour
>= neon_cvt_flavour_s16_f16
15899 && flavour
<= neon_cvt_flavour_f16_u16
)
15900 /* Half precision. */
15901 inst
.instruction
|= 1 << 18;
15903 inst
.instruction
|= 2 << 18;
15905 neon_dp_fixup (&inst
);
15910 /* Half-precision conversions for Advanced SIMD -- neon. */
15915 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15917 as_bad (_("operand size must match register width"));
15922 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15924 as_bad (_("operand size must match register width"));
15929 inst
.instruction
= 0x3b60600;
15931 inst
.instruction
= 0x3b60700;
15933 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15934 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15935 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15936 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15937 neon_dp_fixup (&inst
);
15941 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15942 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15943 do_vfp_nsyn_cvt (rs
, flavour
);
15945 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15950 do_neon_cvtr (void)
15952 do_neon_cvt_1 (neon_cvt_mode_x
);
15958 do_neon_cvt_1 (neon_cvt_mode_z
);
15962 do_neon_cvta (void)
15964 do_neon_cvt_1 (neon_cvt_mode_a
);
15968 do_neon_cvtn (void)
15970 do_neon_cvt_1 (neon_cvt_mode_n
);
15974 do_neon_cvtp (void)
15976 do_neon_cvt_1 (neon_cvt_mode_p
);
15980 do_neon_cvtm (void)
15982 do_neon_cvt_1 (neon_cvt_mode_m
);
15986 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15989 mark_feature_used (&fpu_vfp_ext_armv8
);
15991 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15992 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15993 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15994 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15995 inst
.instruction
|= to
? 0x10000 : 0;
15996 inst
.instruction
|= t
? 0x80 : 0;
15997 inst
.instruction
|= is_double
? 0x100 : 0;
15998 do_vfp_cond_or_thumb ();
16002 do_neon_cvttb_1 (bfd_boolean t
)
16004 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
16005 NS_DF
, NS_DH
, NS_NULL
);
16009 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
16012 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
16014 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
16017 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
16019 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
16021 /* The VCVTB and VCVTT instructions with D-register operands
16022 don't work for SP only targets. */
16023 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16027 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
16029 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
16031 /* The VCVTB and VCVTT instructions with D-register operands
16032 don't work for SP only targets. */
16033 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16037 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
16044 do_neon_cvtb (void)
16046 do_neon_cvttb_1 (FALSE
);
16051 do_neon_cvtt (void)
16053 do_neon_cvttb_1 (TRUE
);
16057 neon_move_immediate (void)
16059 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
16060 struct neon_type_el et
= neon_check_type (2, rs
,
16061 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
16062 unsigned immlo
, immhi
= 0, immbits
;
16063 int op
, cmode
, float_p
;
16065 constraint (et
.type
== NT_invtype
,
16066 _("operand size must be specified for immediate VMOV"));
16068 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
16069 op
= (inst
.instruction
& (1 << 5)) != 0;
16071 immlo
= inst
.operands
[1].imm
;
16072 if (inst
.operands
[1].regisimm
)
16073 immhi
= inst
.operands
[1].reg
;
16075 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
16076 _("immediate has bits set outside the operand size"));
16078 float_p
= inst
.operands
[1].immisfloat
;
16080 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
16081 et
.size
, et
.type
)) == FAIL
)
16083 /* Invert relevant bits only. */
16084 neon_invert_size (&immlo
, &immhi
, et
.size
);
16085 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
16086 with one or the other; those cases are caught by
16087 neon_cmode_for_move_imm. */
16089 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
16090 &op
, et
.size
, et
.type
)) == FAIL
)
16092 first_error (_("immediate out of range"));
16097 inst
.instruction
&= ~(1 << 5);
16098 inst
.instruction
|= op
<< 5;
16100 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16101 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16102 inst
.instruction
|= neon_quad (rs
) << 6;
16103 inst
.instruction
|= cmode
<< 8;
16105 neon_write_immbits (immbits
);
16111 if (inst
.operands
[1].isreg
)
16113 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16115 NEON_ENCODE (INTEGER
, inst
);
16116 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16117 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16118 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16119 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16120 inst
.instruction
|= neon_quad (rs
) << 6;
16124 NEON_ENCODE (IMMED
, inst
);
16125 neon_move_immediate ();
16128 neon_dp_fixup (&inst
);
16131 /* Encode instructions of form:
16133 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16134 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16137 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16139 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16140 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16141 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16142 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16143 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16144 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16145 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16146 inst
.instruction
|= neon_logbits (size
) << 20;
16148 neon_dp_fixup (&inst
);
16152 do_neon_dyadic_long (void)
16154 /* FIXME: Type checking for lengthening op. */
16155 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16156 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16157 neon_mixed_length (et
, et
.size
);
16161 do_neon_abal (void)
16163 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16164 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16165 neon_mixed_length (et
, et
.size
);
16169 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16171 if (inst
.operands
[2].isscalar
)
16173 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16174 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16175 NEON_ENCODE (SCALAR
, inst
);
16176 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16180 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16181 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16182 NEON_ENCODE (INTEGER
, inst
);
16183 neon_mixed_length (et
, et
.size
);
16188 do_neon_mac_maybe_scalar_long (void)
16190 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16193 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
16194 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
16197 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
16199 unsigned regno
= NEON_SCALAR_REG (scalar
);
16200 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
16204 if (regno
> 7 || elno
> 3)
16207 return ((regno
& 0x7)
16208 | ((elno
& 0x1) << 3)
16209 | (((elno
>> 1) & 0x1) << 5));
16213 if (regno
> 15 || elno
> 1)
16216 return (((regno
& 0x1) << 5)
16217 | ((regno
>> 1) & 0x7)
16218 | ((elno
& 0x1) << 3));
16222 first_error (_("scalar out of range for multiply instruction"));
16227 do_neon_fmac_maybe_scalar_long (int subtype
)
16229 enum neon_shape rs
;
16231 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
16232 field (bits[21:20]) has different meaning. For scalar index variant, it's
16233 used to differentiate add and subtract, otherwise it's with fixed value
16237 if (inst
.cond
!= COND_ALWAYS
)
16238 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
16239 "behaviour is UNPREDICTABLE"));
16241 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
16244 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
16247 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
16248 be a scalar index register. */
16249 if (inst
.operands
[2].isscalar
)
16251 high8
= 0xfe000000;
16254 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
16258 high8
= 0xfc000000;
16261 inst
.instruction
|= (0x1 << 23);
16262 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
16265 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
16267 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
16268 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
16269 so we simply pass -1 as size. */
16270 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
16271 neon_three_same (quad_p
, 0, size
);
16273 /* Undo neon_dp_fixup. Redo the high eight bits. */
16274 inst
.instruction
&= 0x00ffffff;
16275 inst
.instruction
|= high8
;
16277 #define LOW1(R) ((R) & 0x1)
16278 #define HI4(R) (((R) >> 1) & 0xf)
16279 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
16280 whether the instruction is in Q form and whether Vm is a scalar indexed
16282 if (inst
.operands
[2].isscalar
)
16285 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
16286 inst
.instruction
&= 0xffffffd0;
16287 inst
.instruction
|= rm
;
16291 /* Redo Rn as well. */
16292 inst
.instruction
&= 0xfff0ff7f;
16293 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16294 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16299 /* Redo Rn and Rm. */
16300 inst
.instruction
&= 0xfff0ff50;
16301 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16302 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16303 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
16304 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
16309 do_neon_vfmal (void)
16311 return do_neon_fmac_maybe_scalar_long (0);
16315 do_neon_vfmsl (void)
16317 return do_neon_fmac_maybe_scalar_long (1);
16321 do_neon_dyadic_wide (void)
16323 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16324 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16325 neon_mixed_length (et
, et
.size
);
16329 do_neon_dyadic_narrow (void)
16331 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16332 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16333 /* Operand sign is unimportant, and the U bit is part of the opcode,
16334 so force the operand type to integer. */
16335 et
.type
= NT_integer
;
16336 neon_mixed_length (et
, et
.size
/ 2);
16340 do_neon_mul_sat_scalar_long (void)
16342 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16346 do_neon_vmull (void)
16348 if (inst
.operands
[2].isscalar
)
16349 do_neon_mac_maybe_scalar_long ();
16352 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16353 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16355 if (et
.type
== NT_poly
)
16356 NEON_ENCODE (POLY
, inst
);
16358 NEON_ENCODE (INTEGER
, inst
);
16360 /* For polynomial encoding the U bit must be zero, and the size must
16361 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16362 obviously, as 0b10). */
16365 /* Check we're on the correct architecture. */
16366 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16368 _("Instruction form not available on this architecture.");
16373 neon_mixed_length (et
, et
.size
);
16380 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16381 struct neon_type_el et
= neon_check_type (3, rs
,
16382 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16383 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16385 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16386 _("shift out of range"));
16387 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16388 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16389 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16390 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16391 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16392 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16393 inst
.instruction
|= neon_quad (rs
) << 6;
16394 inst
.instruction
|= imm
<< 8;
16396 neon_dp_fixup (&inst
);
16402 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16403 struct neon_type_el et
= neon_check_type (2, rs
,
16404 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16405 unsigned op
= (inst
.instruction
>> 7) & 3;
16406 /* N (width of reversed regions) is encoded as part of the bitmask. We
16407 extract it here to check the elements to be reversed are smaller.
16408 Otherwise we'd get a reserved instruction. */
16409 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16410 gas_assert (elsize
!= 0);
16411 constraint (et
.size
>= elsize
,
16412 _("elements must be smaller than reversal region"));
16413 neon_two_same (neon_quad (rs
), 1, et
.size
);
16419 if (inst
.operands
[1].isscalar
)
16421 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16422 struct neon_type_el et
= neon_check_type (2, rs
,
16423 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16424 unsigned sizebits
= et
.size
>> 3;
16425 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16426 int logsize
= neon_logbits (et
.size
);
16427 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16429 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16432 NEON_ENCODE (SCALAR
, inst
);
16433 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16434 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16435 inst
.instruction
|= LOW4 (dm
);
16436 inst
.instruction
|= HI1 (dm
) << 5;
16437 inst
.instruction
|= neon_quad (rs
) << 6;
16438 inst
.instruction
|= x
<< 17;
16439 inst
.instruction
|= sizebits
<< 16;
16441 neon_dp_fixup (&inst
);
16445 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16446 struct neon_type_el et
= neon_check_type (2, rs
,
16447 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16448 /* Duplicate ARM register to lanes of vector. */
16449 NEON_ENCODE (ARMREG
, inst
);
16452 case 8: inst
.instruction
|= 0x400000; break;
16453 case 16: inst
.instruction
|= 0x000020; break;
16454 case 32: inst
.instruction
|= 0x000000; break;
16457 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16458 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16459 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16460 inst
.instruction
|= neon_quad (rs
) << 21;
16461 /* The encoding for this instruction is identical for the ARM and Thumb
16462 variants, except for the condition field. */
16463 do_vfp_cond_or_thumb ();
16467 /* VMOV has particularly many variations. It can be one of:
16468 0. VMOV<c><q> <Qd>, <Qm>
16469 1. VMOV<c><q> <Dd>, <Dm>
16470 (Register operations, which are VORR with Rm = Rn.)
16471 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16472 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16474 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16475 (ARM register to scalar.)
16476 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16477 (Two ARM registers to vector.)
16478 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16479 (Scalar to ARM register.)
16480 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16481 (Vector to two ARM registers.)
16482 8. VMOV.F32 <Sd>, <Sm>
16483 9. VMOV.F64 <Dd>, <Dm>
16484 (VFP register moves.)
16485 10. VMOV.F32 <Sd>, #imm
16486 11. VMOV.F64 <Dd>, #imm
16487 (VFP float immediate load.)
16488 12. VMOV <Rd>, <Sm>
16489 (VFP single to ARM reg.)
16490 13. VMOV <Sd>, <Rm>
16491 (ARM reg to VFP single.)
16492 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16493 (Two ARM regs to two VFP singles.)
16494 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16495 (Two VFP singles to two ARM regs.)
16497 These cases can be disambiguated using neon_select_shape, except cases 1/9
16498 and 3/11 which depend on the operand type too.
16500 All the encoded bits are hardcoded by this function.
16502 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16503 Cases 5, 7 may be used with VFPv2 and above.
16505 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16506 can specify a type where it doesn't make sense to, and is ignored). */
16511 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16512 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16513 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16514 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16515 struct neon_type_el et
;
16516 const char *ldconst
= 0;
16520 case NS_DD
: /* case 1/9. */
16521 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16522 /* It is not an error here if no type is given. */
16524 if (et
.type
== NT_float
&& et
.size
== 64)
16526 do_vfp_nsyn_opcode ("fcpyd");
16529 /* fall through. */
16531 case NS_QQ
: /* case 0/1. */
16533 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16535 /* The architecture manual I have doesn't explicitly state which
16536 value the U bit should have for register->register moves, but
16537 the equivalent VORR instruction has U = 0, so do that. */
16538 inst
.instruction
= 0x0200110;
16539 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16540 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16541 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16542 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16543 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16544 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16545 inst
.instruction
|= neon_quad (rs
) << 6;
16547 neon_dp_fixup (&inst
);
16551 case NS_DI
: /* case 3/11. */
16552 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16554 if (et
.type
== NT_float
&& et
.size
== 64)
16556 /* case 11 (fconstd). */
16557 ldconst
= "fconstd";
16558 goto encode_fconstd
;
16560 /* fall through. */
16562 case NS_QI
: /* case 2/3. */
16563 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16565 inst
.instruction
= 0x0800010;
16566 neon_move_immediate ();
16567 neon_dp_fixup (&inst
);
16570 case NS_SR
: /* case 4. */
16572 unsigned bcdebits
= 0;
16574 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16575 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16577 /* .<size> is optional here, defaulting to .32. */
16578 if (inst
.vectype
.elems
== 0
16579 && inst
.operands
[0].vectype
.type
== NT_invtype
16580 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16582 inst
.vectype
.el
[0].type
= NT_untyped
;
16583 inst
.vectype
.el
[0].size
= 32;
16584 inst
.vectype
.elems
= 1;
16587 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16588 logsize
= neon_logbits (et
.size
);
16590 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16592 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16593 && et
.size
!= 32, _(BAD_FPU
));
16594 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16595 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16599 case 8: bcdebits
= 0x8; break;
16600 case 16: bcdebits
= 0x1; break;
16601 case 32: bcdebits
= 0x0; break;
16605 bcdebits
|= x
<< logsize
;
16607 inst
.instruction
= 0xe000b10;
16608 do_vfp_cond_or_thumb ();
16609 inst
.instruction
|= LOW4 (dn
) << 16;
16610 inst
.instruction
|= HI1 (dn
) << 7;
16611 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16612 inst
.instruction
|= (bcdebits
& 3) << 5;
16613 inst
.instruction
|= (bcdebits
>> 2) << 21;
16617 case NS_DRR
: /* case 5 (fmdrr). */
16618 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16621 inst
.instruction
= 0xc400b10;
16622 do_vfp_cond_or_thumb ();
16623 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16624 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16625 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16626 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16629 case NS_RS
: /* case 6. */
16632 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16633 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16634 unsigned abcdebits
= 0;
16636 /* .<dt> is optional here, defaulting to .32. */
16637 if (inst
.vectype
.elems
== 0
16638 && inst
.operands
[0].vectype
.type
== NT_invtype
16639 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16641 inst
.vectype
.el
[0].type
= NT_untyped
;
16642 inst
.vectype
.el
[0].size
= 32;
16643 inst
.vectype
.elems
= 1;
16646 et
= neon_check_type (2, NS_NULL
,
16647 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16648 logsize
= neon_logbits (et
.size
);
16650 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16652 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16653 && et
.size
!= 32, _(BAD_FPU
));
16654 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16655 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16659 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16660 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16661 case 32: abcdebits
= 0x00; break;
16665 abcdebits
|= x
<< logsize
;
16666 inst
.instruction
= 0xe100b10;
16667 do_vfp_cond_or_thumb ();
16668 inst
.instruction
|= LOW4 (dn
) << 16;
16669 inst
.instruction
|= HI1 (dn
) << 7;
16670 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16671 inst
.instruction
|= (abcdebits
& 3) << 5;
16672 inst
.instruction
|= (abcdebits
>> 2) << 21;
16676 case NS_RRD
: /* case 7 (fmrrd). */
16677 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16680 inst
.instruction
= 0xc500b10;
16681 do_vfp_cond_or_thumb ();
16682 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16683 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16684 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16685 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16688 case NS_FF
: /* case 8 (fcpys). */
16689 do_vfp_nsyn_opcode ("fcpys");
16693 case NS_FI
: /* case 10 (fconsts). */
16694 ldconst
= "fconsts";
16696 if (!inst
.operands
[1].immisfloat
)
16699 /* Immediate has to fit in 8 bits so float is enough. */
16700 float imm
= (float) inst
.operands
[1].imm
;
16701 memcpy (&new_imm
, &imm
, sizeof (float));
16702 /* But the assembly may have been written to provide an integer
16703 bit pattern that equates to a float, so check that the
16704 conversion has worked. */
16705 if (is_quarter_float (new_imm
))
16707 if (is_quarter_float (inst
.operands
[1].imm
))
16708 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
16710 inst
.operands
[1].imm
= new_imm
;
16711 inst
.operands
[1].immisfloat
= 1;
16715 if (is_quarter_float (inst
.operands
[1].imm
))
16717 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16718 do_vfp_nsyn_opcode (ldconst
);
16720 /* ARMv8.2 fp16 vmov.f16 instruction. */
16722 do_scalar_fp16_v82_encode ();
16725 first_error (_("immediate out of range"));
16729 case NS_RF
: /* case 12 (fmrs). */
16730 do_vfp_nsyn_opcode ("fmrs");
16731 /* ARMv8.2 fp16 vmov.f16 instruction. */
16733 do_scalar_fp16_v82_encode ();
16737 case NS_FR
: /* case 13 (fmsr). */
16738 do_vfp_nsyn_opcode ("fmsr");
16739 /* ARMv8.2 fp16 vmov.f16 instruction. */
16741 do_scalar_fp16_v82_encode ();
16744 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16745 (one of which is a list), but we have parsed four. Do some fiddling to
16746 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16748 case NS_RRFF
: /* case 14 (fmrrs). */
16749 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16750 _("VFP registers must be adjacent"));
16751 inst
.operands
[2].imm
= 2;
16752 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16753 do_vfp_nsyn_opcode ("fmrrs");
16756 case NS_FFRR
: /* case 15 (fmsrr). */
16757 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16758 _("VFP registers must be adjacent"));
16759 inst
.operands
[1] = inst
.operands
[2];
16760 inst
.operands
[2] = inst
.operands
[3];
16761 inst
.operands
[0].imm
= 2;
16762 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16763 do_vfp_nsyn_opcode ("fmsrr");
16767 /* neon_select_shape has determined that the instruction
16768 shape is wrong and has already set the error message. */
16777 do_neon_rshift_round_imm (void)
16779 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16780 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16781 int imm
= inst
.operands
[2].imm
;
16783 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16786 inst
.operands
[2].present
= 0;
16791 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16792 _("immediate out of range for shift"));
16793 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16798 do_neon_movhf (void)
16800 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16801 constraint (rs
!= NS_HH
, _("invalid suffix"));
16803 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16806 if (inst
.cond
!= COND_ALWAYS
)
16810 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
16811 " the behaviour is UNPREDICTABLE"));
16815 inst
.error
= BAD_COND
;
16820 do_vfp_sp_monadic ();
16823 inst
.instruction
|= 0xf0000000;
16827 do_neon_movl (void)
16829 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16830 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16831 unsigned sizebits
= et
.size
>> 3;
16832 inst
.instruction
|= sizebits
<< 19;
16833 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16839 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16840 struct neon_type_el et
= neon_check_type (2, rs
,
16841 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16842 NEON_ENCODE (INTEGER
, inst
);
16843 neon_two_same (neon_quad (rs
), 1, et
.size
);
16847 do_neon_zip_uzp (void)
16849 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16850 struct neon_type_el et
= neon_check_type (2, rs
,
16851 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16852 if (rs
== NS_DD
&& et
.size
== 32)
16854 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16855 inst
.instruction
= N_MNEM_vtrn
;
16859 neon_two_same (neon_quad (rs
), 1, et
.size
);
16863 do_neon_sat_abs_neg (void)
16865 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16866 struct neon_type_el et
= neon_check_type (2, rs
,
16867 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16868 neon_two_same (neon_quad (rs
), 1, et
.size
);
16872 do_neon_pair_long (void)
16874 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16875 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16876 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16877 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16878 neon_two_same (neon_quad (rs
), 1, et
.size
);
16882 do_neon_recip_est (void)
16884 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16885 struct neon_type_el et
= neon_check_type (2, rs
,
16886 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16887 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16888 neon_two_same (neon_quad (rs
), 1, et
.size
);
16894 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16895 struct neon_type_el et
= neon_check_type (2, rs
,
16896 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16897 neon_two_same (neon_quad (rs
), 1, et
.size
);
16903 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16904 struct neon_type_el et
= neon_check_type (2, rs
,
16905 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16906 neon_two_same (neon_quad (rs
), 1, et
.size
);
16912 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16913 struct neon_type_el et
= neon_check_type (2, rs
,
16914 N_EQK
| N_INT
, N_8
| N_KEY
);
16915 neon_two_same (neon_quad (rs
), 1, et
.size
);
16921 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16922 neon_two_same (neon_quad (rs
), 1, -1);
16926 do_neon_tbl_tbx (void)
16928 unsigned listlenbits
;
16929 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16931 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16933 first_error (_("bad list length for table lookup"));
16937 listlenbits
= inst
.operands
[1].imm
- 1;
16938 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16939 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16940 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16941 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16942 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16943 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16944 inst
.instruction
|= listlenbits
<< 8;
16946 neon_dp_fixup (&inst
);
16950 do_neon_ldm_stm (void)
16952 /* P, U and L bits are part of bitmask. */
16953 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16954 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16956 if (inst
.operands
[1].issingle
)
16958 do_vfp_nsyn_ldm_stm (is_dbmode
);
16962 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16963 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16965 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16966 _("register list must contain at least 1 and at most 16 "
16969 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16970 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16971 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16972 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16974 inst
.instruction
|= offsetbits
;
16976 do_vfp_cond_or_thumb ();
16980 do_neon_ldr_str (void)
16982 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16984 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16985 And is UNPREDICTABLE in thumb mode. */
16987 && inst
.operands
[1].reg
== REG_PC
16988 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16991 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16992 else if (warn_on_deprecated
)
16993 as_tsktsk (_("Use of PC here is deprecated"));
16996 if (inst
.operands
[0].issingle
)
16999 do_vfp_nsyn_opcode ("flds");
17001 do_vfp_nsyn_opcode ("fsts");
17003 /* ARMv8.2 vldr.16/vstr.16 instruction. */
17004 if (inst
.vectype
.el
[0].size
== 16)
17005 do_scalar_fp16_v82_encode ();
17010 do_vfp_nsyn_opcode ("fldd");
17012 do_vfp_nsyn_opcode ("fstd");
17016 /* "interleave" version also handles non-interleaving register VLD1/VST1
17020 do_neon_ld_st_interleave (void)
17022 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
17023 N_8
| N_16
| N_32
| N_64
);
17024 unsigned alignbits
= 0;
17026 /* The bits in this table go:
17027 0: register stride of one (0) or two (1)
17028 1,2: register list length, minus one (1, 2, 3, 4).
17029 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
17030 We use -1 for invalid entries. */
17031 const int typetable
[] =
17033 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
17034 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
17035 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
17036 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
17040 if (et
.type
== NT_invtype
)
17043 if (inst
.operands
[1].immisalign
)
17044 switch (inst
.operands
[1].imm
>> 8)
17046 case 64: alignbits
= 1; break;
17048 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
17049 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
17050 goto bad_alignment
;
17054 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
17055 goto bad_alignment
;
17060 first_error (_("bad alignment"));
17064 inst
.instruction
|= alignbits
<< 4;
17065 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17067 /* Bits [4:6] of the immediate in a list specifier encode register stride
17068 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
17069 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
17070 up the right value for "type" in a table based on this value and the given
17071 list style, then stick it back. */
17072 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
17073 | (((inst
.instruction
>> 8) & 3) << 3);
17075 typebits
= typetable
[idx
];
17077 constraint (typebits
== -1, _("bad list type for instruction"));
17078 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
17079 _("bad element type for instruction"));
17081 inst
.instruction
&= ~0xf00;
17082 inst
.instruction
|= typebits
<< 8;
17085 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
17086 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
17087 otherwise. The variable arguments are a list of pairs of legal (size, align)
17088 values, terminated with -1. */
17091 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
17094 int result
= FAIL
, thissize
, thisalign
;
17096 if (!inst
.operands
[1].immisalign
)
17102 va_start (ap
, do_alignment
);
17106 thissize
= va_arg (ap
, int);
17107 if (thissize
== -1)
17109 thisalign
= va_arg (ap
, int);
17111 if (size
== thissize
&& align
== thisalign
)
17114 while (result
!= SUCCESS
);
17118 if (result
== SUCCESS
)
17121 first_error (_("unsupported alignment for instruction"));
17127 do_neon_ld_st_lane (void)
17129 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17130 int align_good
, do_alignment
= 0;
17131 int logsize
= neon_logbits (et
.size
);
17132 int align
= inst
.operands
[1].imm
>> 8;
17133 int n
= (inst
.instruction
>> 8) & 3;
17134 int max_el
= 64 / et
.size
;
17136 if (et
.type
== NT_invtype
)
17139 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
17140 _("bad list length"));
17141 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
17142 _("scalar index out of range"));
17143 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
17145 _("stride of 2 unavailable when element size is 8"));
17149 case 0: /* VLD1 / VST1. */
17150 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
17152 if (align_good
== FAIL
)
17156 unsigned alignbits
= 0;
17159 case 16: alignbits
= 0x1; break;
17160 case 32: alignbits
= 0x3; break;
17163 inst
.instruction
|= alignbits
<< 4;
17167 case 1: /* VLD2 / VST2. */
17168 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
17169 16, 32, 32, 64, -1);
17170 if (align_good
== FAIL
)
17173 inst
.instruction
|= 1 << 4;
17176 case 2: /* VLD3 / VST3. */
17177 constraint (inst
.operands
[1].immisalign
,
17178 _("can't use alignment with this instruction"));
17181 case 3: /* VLD4 / VST4. */
17182 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17183 16, 64, 32, 64, 32, 128, -1);
17184 if (align_good
== FAIL
)
17188 unsigned alignbits
= 0;
17191 case 8: alignbits
= 0x1; break;
17192 case 16: alignbits
= 0x1; break;
17193 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
17196 inst
.instruction
|= alignbits
<< 4;
17203 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
17204 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17205 inst
.instruction
|= 1 << (4 + logsize
);
17207 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
17208 inst
.instruction
|= logsize
<< 10;
17211 /* Encode single n-element structure to all lanes VLD<n> instructions. */
17214 do_neon_ld_dup (void)
17216 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17217 int align_good
, do_alignment
= 0;
17219 if (et
.type
== NT_invtype
)
17222 switch ((inst
.instruction
>> 8) & 3)
17224 case 0: /* VLD1. */
17225 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
17226 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17227 &do_alignment
, 16, 16, 32, 32, -1);
17228 if (align_good
== FAIL
)
17230 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
17233 case 2: inst
.instruction
|= 1 << 5; break;
17234 default: first_error (_("bad list length")); return;
17236 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17239 case 1: /* VLD2. */
17240 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17241 &do_alignment
, 8, 16, 16, 32, 32, 64,
17243 if (align_good
== FAIL
)
17245 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
17246 _("bad list length"));
17247 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17248 inst
.instruction
|= 1 << 5;
17249 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17252 case 2: /* VLD3. */
17253 constraint (inst
.operands
[1].immisalign
,
17254 _("can't use alignment with this instruction"));
17255 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
17256 _("bad list length"));
17257 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17258 inst
.instruction
|= 1 << 5;
17259 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17262 case 3: /* VLD4. */
17264 int align
= inst
.operands
[1].imm
>> 8;
17265 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17266 16, 64, 32, 64, 32, 128, -1);
17267 if (align_good
== FAIL
)
17269 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
17270 _("bad list length"));
17271 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17272 inst
.instruction
|= 1 << 5;
17273 if (et
.size
== 32 && align
== 128)
17274 inst
.instruction
|= 0x3 << 6;
17276 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17283 inst
.instruction
|= do_alignment
<< 4;
17286 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17287 apart from bits [11:4]. */
17290 do_neon_ldx_stx (void)
17292 if (inst
.operands
[1].isreg
)
17293 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17295 switch (NEON_LANE (inst
.operands
[0].imm
))
17297 case NEON_INTERLEAVE_LANES
:
17298 NEON_ENCODE (INTERLV
, inst
);
17299 do_neon_ld_st_interleave ();
17302 case NEON_ALL_LANES
:
17303 NEON_ENCODE (DUP
, inst
);
17304 if (inst
.instruction
== N_INV
)
17306 first_error ("only loads support such operands");
17313 NEON_ENCODE (LANE
, inst
);
17314 do_neon_ld_st_lane ();
17317 /* L bit comes from bit mask. */
17318 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17319 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17320 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17322 if (inst
.operands
[1].postind
)
17324 int postreg
= inst
.operands
[1].imm
& 0xf;
17325 constraint (!inst
.operands
[1].immisreg
,
17326 _("post-index must be a register"));
17327 constraint (postreg
== 0xd || postreg
== 0xf,
17328 _("bad register for post-index"));
17329 inst
.instruction
|= postreg
;
17333 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17334 constraint (inst
.reloc
.exp
.X_op
!= O_constant
17335 || inst
.reloc
.exp
.X_add_number
!= 0,
17338 if (inst
.operands
[1].writeback
)
17340 inst
.instruction
|= 0xd;
17343 inst
.instruction
|= 0xf;
17347 inst
.instruction
|= 0xf9000000;
17349 inst
.instruction
|= 0xf4000000;
17354 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17356 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17357 D register operands. */
17358 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17359 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17362 NEON_ENCODE (FPV8
, inst
);
17364 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17366 do_vfp_sp_dyadic ();
17368 /* ARMv8.2 fp16 instruction. */
17370 do_scalar_fp16_v82_encode ();
17373 do_vfp_dp_rd_rn_rm ();
17376 inst
.instruction
|= 0x100;
17378 inst
.instruction
|= 0xf0000000;
17384 set_it_insn_type (OUTSIDE_IT_INSN
);
17386 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17387 first_error (_("invalid instruction shape"));
17393 set_it_insn_type (OUTSIDE_IT_INSN
);
17395 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17398 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17401 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17405 do_vrint_1 (enum neon_cvt_mode mode
)
17407 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17408 struct neon_type_el et
;
17413 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17414 D register operands. */
17415 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17416 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17419 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17421 if (et
.type
!= NT_invtype
)
17423 /* VFP encodings. */
17424 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17425 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17426 set_it_insn_type (OUTSIDE_IT_INSN
);
17428 NEON_ENCODE (FPV8
, inst
);
17429 if (rs
== NS_FF
|| rs
== NS_HH
)
17430 do_vfp_sp_monadic ();
17432 do_vfp_dp_rd_rm ();
17436 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17437 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17438 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17439 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17440 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17441 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17442 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17446 inst
.instruction
|= (rs
== NS_DD
) << 8;
17447 do_vfp_cond_or_thumb ();
17449 /* ARMv8.2 fp16 vrint instruction. */
17451 do_scalar_fp16_v82_encode ();
17455 /* Neon encodings (or something broken...). */
17457 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17459 if (et
.type
== NT_invtype
)
17462 set_it_insn_type (OUTSIDE_IT_INSN
);
17463 NEON_ENCODE (FLOAT
, inst
);
17465 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17468 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17469 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17470 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17471 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17472 inst
.instruction
|= neon_quad (rs
) << 6;
17473 /* Mask off the original size bits and reencode them. */
17474 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17475 | neon_logbits (et
.size
) << 18);
17479 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17480 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17481 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17482 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17483 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17484 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17485 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17490 inst
.instruction
|= 0xfc000000;
17492 inst
.instruction
|= 0xf0000000;
17499 do_vrint_1 (neon_cvt_mode_x
);
17505 do_vrint_1 (neon_cvt_mode_z
);
17511 do_vrint_1 (neon_cvt_mode_r
);
17517 do_vrint_1 (neon_cvt_mode_a
);
17523 do_vrint_1 (neon_cvt_mode_n
);
17529 do_vrint_1 (neon_cvt_mode_p
);
17535 do_vrint_1 (neon_cvt_mode_m
);
17539 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
17541 unsigned regno
= NEON_SCALAR_REG (opnd
);
17542 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
17544 if (elsize
== 16 && elno
< 2 && regno
< 16)
17545 return regno
| (elno
<< 4);
17546 else if (elsize
== 32 && elno
== 0)
17549 first_error (_("scalar out of range"));
17556 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17558 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17559 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17560 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
17561 _("immediate out of range"));
17563 if (inst
.operands
[2].isscalar
)
17565 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
17566 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17567 N_KEY
| N_F16
| N_F32
).size
;
17568 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
17570 inst
.instruction
= 0xfe000800;
17571 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17572 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17573 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17574 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17575 inst
.instruction
|= LOW4 (m
);
17576 inst
.instruction
|= HI1 (m
) << 5;
17577 inst
.instruction
|= neon_quad (rs
) << 6;
17578 inst
.instruction
|= rot
<< 20;
17579 inst
.instruction
|= (size
== 32) << 23;
17583 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17584 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17585 N_KEY
| N_F16
| N_F32
).size
;
17586 neon_three_same (neon_quad (rs
), 0, -1);
17587 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17588 inst
.instruction
|= 0xfc200800;
17589 inst
.instruction
|= rot
<< 23;
17590 inst
.instruction
|= (size
== 32) << 20;
17597 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17599 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17600 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17601 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17602 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17603 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17604 N_KEY
| N_F16
| N_F32
).size
;
17605 neon_three_same (neon_quad (rs
), 0, -1);
17606 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17607 inst
.instruction
|= 0xfc800800;
17608 inst
.instruction
|= (rot
== 270) << 24;
17609 inst
.instruction
|= (size
== 32) << 20;
17612 /* Dot Product instructions encoding support. */
17615 do_neon_dotproduct (int unsigned_p
)
17617 enum neon_shape rs
;
17618 unsigned scalar_oprd2
= 0;
17621 if (inst
.cond
!= COND_ALWAYS
)
17622 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
17623 "is UNPREDICTABLE"));
17625 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17628 /* Dot Product instructions are in three-same D/Q register format or the third
17629 operand can be a scalar index register. */
17630 if (inst
.operands
[2].isscalar
)
17632 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
17633 high8
= 0xfe000000;
17634 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17638 high8
= 0xfc000000;
17639 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17643 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
17645 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
17647 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
17648 Product instruction, so we pass 0 as the "ubit" parameter. And the
17649 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
17650 neon_three_same (neon_quad (rs
), 0, 32);
17652 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
17653 different NEON three-same encoding. */
17654 inst
.instruction
&= 0x00ffffff;
17655 inst
.instruction
|= high8
;
17656 /* Encode 'U' bit which indicates signedness. */
17657 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
17658 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
17659 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
17660 the instruction encoding. */
17661 if (inst
.operands
[2].isscalar
)
17663 inst
.instruction
&= 0xffffffd0;
17664 inst
.instruction
|= LOW4 (scalar_oprd2
);
17665 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
17669 /* Dot Product instructions for signed integer. */
17672 do_neon_dotproduct_s (void)
17674 return do_neon_dotproduct (0);
17677 /* Dot Product instructions for unsigned integer. */
17680 do_neon_dotproduct_u (void)
17682 return do_neon_dotproduct (1);
17685 /* Crypto v1 instructions. */
17687 do_crypto_2op_1 (unsigned elttype
, int op
)
17689 set_it_insn_type (OUTSIDE_IT_INSN
);
17691 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17697 NEON_ENCODE (INTEGER
, inst
);
17698 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17699 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17700 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17701 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17703 inst
.instruction
|= op
<< 6;
17706 inst
.instruction
|= 0xfc000000;
17708 inst
.instruction
|= 0xf0000000;
17712 do_crypto_3op_1 (int u
, int op
)
17714 set_it_insn_type (OUTSIDE_IT_INSN
);
17716 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17717 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17722 NEON_ENCODE (INTEGER
, inst
);
17723 neon_three_same (1, u
, 8 << op
);
17729 do_crypto_2op_1 (N_8
, 0);
17735 do_crypto_2op_1 (N_8
, 1);
17741 do_crypto_2op_1 (N_8
, 2);
17747 do_crypto_2op_1 (N_8
, 3);
17753 do_crypto_3op_1 (0, 0);
17759 do_crypto_3op_1 (0, 1);
17765 do_crypto_3op_1 (0, 2);
17771 do_crypto_3op_1 (0, 3);
17777 do_crypto_3op_1 (1, 0);
17783 do_crypto_3op_1 (1, 1);
17787 do_sha256su1 (void)
17789 do_crypto_3op_1 (1, 2);
17795 do_crypto_2op_1 (N_32
, -1);
17801 do_crypto_2op_1 (N_32
, 0);
17805 do_sha256su0 (void)
17807 do_crypto_2op_1 (N_32
, 1);
17811 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17813 unsigned int Rd
= inst
.operands
[0].reg
;
17814 unsigned int Rn
= inst
.operands
[1].reg
;
17815 unsigned int Rm
= inst
.operands
[2].reg
;
17817 set_it_insn_type (OUTSIDE_IT_INSN
);
17818 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17819 inst
.instruction
|= LOW4 (Rn
) << 16;
17820 inst
.instruction
|= LOW4 (Rm
);
17821 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17822 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17824 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17825 as_warn (UNPRED_REG ("r15"));
17867 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17869 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
17870 do_vfp_sp_dp_cvt ();
17871 do_vfp_cond_or_thumb ();
17875 /* Overall per-instruction processing. */
17877 /* We need to be able to fix up arbitrary expressions in some statements.
17878 This is so that we can handle symbols that are an arbitrary distance from
17879 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17880 which returns part of an address in a form which will be valid for
17881 a data instruction. We do this by pushing the expression into a symbol
17882 in the expr_section, and creating a fix for that. */
17885 fix_new_arm (fragS
* frag
,
17899 /* Create an absolute valued symbol, so we have something to
17900 refer to in the object file. Unfortunately for us, gas's
17901 generic expression parsing will already have folded out
17902 any use of .set foo/.type foo %function that may have
17903 been used to set type information of the target location,
17904 that's being specified symbolically. We have to presume
17905 the user knows what they are doing. */
17909 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17911 symbol
= symbol_find_or_make (name
);
17912 S_SET_SEGMENT (symbol
, absolute_section
);
17913 symbol_set_frag (symbol
, &zero_address_frag
);
17914 S_SET_VALUE (symbol
, exp
->X_add_number
);
17915 exp
->X_op
= O_symbol
;
17916 exp
->X_add_symbol
= symbol
;
17917 exp
->X_add_number
= 0;
17923 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17924 (enum bfd_reloc_code_real
) reloc
);
17928 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17929 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17933 /* Mark whether the fix is to a THUMB instruction, or an ARM
17935 new_fix
->tc_fix_data
= thumb_mode
;
17938 /* Create a frg for an instruction requiring relaxation. */
17940 output_relax_insn (void)
17946 /* The size of the instruction is unknown, so tie the debug info to the
17947 start of the instruction. */
17948 dwarf2_emit_insn (0);
17950 switch (inst
.reloc
.exp
.X_op
)
17953 sym
= inst
.reloc
.exp
.X_add_symbol
;
17954 offset
= inst
.reloc
.exp
.X_add_number
;
17958 offset
= inst
.reloc
.exp
.X_add_number
;
17961 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17965 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17966 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17967 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17970 /* Write a 32-bit thumb instruction to buf. */
17972 put_thumb32_insn (char * buf
, unsigned long insn
)
17974 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17975 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17979 output_inst (const char * str
)
17985 as_bad ("%s -- `%s'", inst
.error
, str
);
17990 output_relax_insn ();
17993 if (inst
.size
== 0)
17996 to
= frag_more (inst
.size
);
17997 /* PR 9814: Record the thumb mode into the current frag so that we know
17998 what type of NOP padding to use, if necessary. We override any previous
17999 setting so that if the mode has changed then the NOPS that we use will
18000 match the encoding of the last instruction in the frag. */
18001 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18003 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
18005 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
18006 put_thumb32_insn (to
, inst
.instruction
);
18008 else if (inst
.size
> INSN_SIZE
)
18010 gas_assert (inst
.size
== (2 * INSN_SIZE
));
18011 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
18012 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
18015 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
18017 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
18018 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
18019 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
18022 dwarf2_emit_insn (inst
.size
);
18026 output_it_inst (int cond
, int mask
, char * to
)
18028 unsigned long instruction
= 0xbf00;
18031 instruction
|= mask
;
18032 instruction
|= cond
<< 4;
18036 to
= frag_more (2);
18038 dwarf2_emit_insn (2);
18042 md_number_to_chars (to
, instruction
, 2);
18047 /* Tag values used in struct asm_opcode's tag field. */
18050 OT_unconditional
, /* Instruction cannot be conditionalized.
18051 The ARM condition field is still 0xE. */
18052 OT_unconditionalF
, /* Instruction cannot be conditionalized
18053 and carries 0xF in its ARM condition field. */
18054 OT_csuffix
, /* Instruction takes a conditional suffix. */
18055 OT_csuffixF
, /* Some forms of the instruction take a conditional
18056 suffix, others place 0xF where the condition field
18058 OT_cinfix3
, /* Instruction takes a conditional infix,
18059 beginning at character index 3. (In
18060 unified mode, it becomes a suffix.) */
18061 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
18062 tsts, cmps, cmns, and teqs. */
18063 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
18064 character index 3, even in unified mode. Used for
18065 legacy instructions where suffix and infix forms
18066 may be ambiguous. */
18067 OT_csuf_or_in3
, /* Instruction takes either a conditional
18068 suffix or an infix at character index 3. */
18069 OT_odd_infix_unc
, /* This is the unconditional variant of an
18070 instruction that takes a conditional infix
18071 at an unusual position. In unified mode,
18072 this variant will accept a suffix. */
18073 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
18074 are the conditional variants of instructions that
18075 take conditional infixes in unusual positions.
18076 The infix appears at character index
18077 (tag - OT_odd_infix_0). These are not accepted
18078 in unified mode. */
18081 /* Subroutine of md_assemble, responsible for looking up the primary
18082 opcode from the mnemonic the user wrote. STR points to the
18083 beginning of the mnemonic.
18085 This is not simply a hash table lookup, because of conditional
18086 variants. Most instructions have conditional variants, which are
18087 expressed with a _conditional affix_ to the mnemonic. If we were
18088 to encode each conditional variant as a literal string in the opcode
18089 table, it would have approximately 20,000 entries.
18091 Most mnemonics take this affix as a suffix, and in unified syntax,
18092 'most' is upgraded to 'all'. However, in the divided syntax, some
18093 instructions take the affix as an infix, notably the s-variants of
18094 the arithmetic instructions. Of those instructions, all but six
18095 have the infix appear after the third character of the mnemonic.
18097 Accordingly, the algorithm for looking up primary opcodes given
18100 1. Look up the identifier in the opcode table.
18101 If we find a match, go to step U.
18103 2. Look up the last two characters of the identifier in the
18104 conditions table. If we find a match, look up the first N-2
18105 characters of the identifier in the opcode table. If we
18106 find a match, go to step CE.
18108 3. Look up the fourth and fifth characters of the identifier in
18109 the conditions table. If we find a match, extract those
18110 characters from the identifier, and look up the remaining
18111 characters in the opcode table. If we find a match, go
18116 U. Examine the tag field of the opcode structure, in case this is
18117 one of the six instructions with its conditional infix in an
18118 unusual place. If it is, the tag tells us where to find the
18119 infix; look it up in the conditions table and set inst.cond
18120 accordingly. Otherwise, this is an unconditional instruction.
18121 Again set inst.cond accordingly. Return the opcode structure.
18123 CE. Examine the tag field to make sure this is an instruction that
18124 should receive a conditional suffix. If it is not, fail.
18125 Otherwise, set inst.cond from the suffix we already looked up,
18126 and return the opcode structure.
18128 CM. Examine the tag field to make sure this is an instruction that
18129 should receive a conditional infix after the third character.
18130 If it is not, fail. Otherwise, undo the edits to the current
18131 line of input and proceed as for case CE. */
18133 static const struct asm_opcode
*
18134 opcode_lookup (char **str
)
18138 const struct asm_opcode
*opcode
;
18139 const struct asm_cond
*cond
;
18142 /* Scan up to the end of the mnemonic, which must end in white space,
18143 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
18144 for (base
= end
= *str
; *end
!= '\0'; end
++)
18145 if (*end
== ' ' || *end
== '.')
18151 /* Handle a possible width suffix and/or Neon type suffix. */
18156 /* The .w and .n suffixes are only valid if the unified syntax is in
18158 if (unified_syntax
&& end
[1] == 'w')
18160 else if (unified_syntax
&& end
[1] == 'n')
18165 inst
.vectype
.elems
= 0;
18167 *str
= end
+ offset
;
18169 if (end
[offset
] == '.')
18171 /* See if we have a Neon type suffix (possible in either unified or
18172 non-unified ARM syntax mode). */
18173 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
18176 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
18182 /* Look for unaffixed or special-case affixed mnemonic. */
18183 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18188 if (opcode
->tag
< OT_odd_infix_0
)
18190 inst
.cond
= COND_ALWAYS
;
18194 if (warn_on_deprecated
&& unified_syntax
)
18195 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18196 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
18197 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18200 inst
.cond
= cond
->value
;
18204 /* Cannot have a conditional suffix on a mnemonic of less than two
18206 if (end
- base
< 3)
18209 /* Look for suffixed mnemonic. */
18211 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18212 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18214 if (opcode
&& cond
)
18217 switch (opcode
->tag
)
18219 case OT_cinfix3_legacy
:
18220 /* Ignore conditional suffixes matched on infix only mnemonics. */
18224 case OT_cinfix3_deprecated
:
18225 case OT_odd_infix_unc
:
18226 if (!unified_syntax
)
18228 /* Fall through. */
18232 case OT_csuf_or_in3
:
18233 inst
.cond
= cond
->value
;
18236 case OT_unconditional
:
18237 case OT_unconditionalF
:
18239 inst
.cond
= cond
->value
;
18242 /* Delayed diagnostic. */
18243 inst
.error
= BAD_COND
;
18244 inst
.cond
= COND_ALWAYS
;
18253 /* Cannot have a usual-position infix on a mnemonic of less than
18254 six characters (five would be a suffix). */
18255 if (end
- base
< 6)
18258 /* Look for infixed mnemonic in the usual position. */
18260 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18264 memcpy (save
, affix
, 2);
18265 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
18266 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18268 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
18269 memcpy (affix
, save
, 2);
18272 && (opcode
->tag
== OT_cinfix3
18273 || opcode
->tag
== OT_cinfix3_deprecated
18274 || opcode
->tag
== OT_csuf_or_in3
18275 || opcode
->tag
== OT_cinfix3_legacy
))
18278 if (warn_on_deprecated
&& unified_syntax
18279 && (opcode
->tag
== OT_cinfix3
18280 || opcode
->tag
== OT_cinfix3_deprecated
))
18281 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18283 inst
.cond
= cond
->value
;
18290 /* This function generates an initial IT instruction, leaving its block
18291 virtually open for the new instructions. Eventually,
18292 the mask will be updated by now_it_add_mask () each time
18293 a new instruction needs to be included in the IT block.
18294 Finally, the block is closed with close_automatic_it_block ().
18295 The block closure can be requested either from md_assemble (),
18296 a tencode (), or due to a label hook. */
18299 new_automatic_it_block (int cond
)
18301 now_it
.state
= AUTOMATIC_IT_BLOCK
;
18302 now_it
.mask
= 0x18;
18304 now_it
.block_length
= 1;
18305 mapping_state (MAP_THUMB
);
18306 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
18307 now_it
.warn_deprecated
= FALSE
;
18308 now_it
.insn_cond
= TRUE
;
18311 /* Close an automatic IT block.
18312 See comments in new_automatic_it_block (). */
18315 close_automatic_it_block (void)
18317 now_it
.mask
= 0x10;
18318 now_it
.block_length
= 0;
18321 /* Update the mask of the current automatically-generated IT
18322 instruction. See comments in new_automatic_it_block (). */
18325 now_it_add_mask (int cond
)
18327 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
18328 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
18329 | ((bitvalue) << (nbit)))
18330 const int resulting_bit
= (cond
& 1);
18332 now_it
.mask
&= 0xf;
18333 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18335 (5 - now_it
.block_length
));
18336 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18338 ((5 - now_it
.block_length
) - 1) );
18339 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
18342 #undef SET_BIT_VALUE
18345 /* The IT blocks handling machinery is accessed through the these functions:
18346 it_fsm_pre_encode () from md_assemble ()
18347 set_it_insn_type () optional, from the tencode functions
18348 set_it_insn_type_last () ditto
18349 in_it_block () ditto
18350 it_fsm_post_encode () from md_assemble ()
18351 force_automatic_it_block_close () from label handling functions
18354 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
18355 initializing the IT insn type with a generic initial value depending
18356 on the inst.condition.
18357 2) During the tencode function, two things may happen:
18358 a) The tencode function overrides the IT insn type by
18359 calling either set_it_insn_type (type) or set_it_insn_type_last ().
18360 b) The tencode function queries the IT block state by
18361 calling in_it_block () (i.e. to determine narrow/not narrow mode).
18363 Both set_it_insn_type and in_it_block run the internal FSM state
18364 handling function (handle_it_state), because: a) setting the IT insn
18365 type may incur in an invalid state (exiting the function),
18366 and b) querying the state requires the FSM to be updated.
18367 Specifically we want to avoid creating an IT block for conditional
18368 branches, so it_fsm_pre_encode is actually a guess and we can't
18369 determine whether an IT block is required until the tencode () routine
18370 has decided what type of instruction this actually it.
18371 Because of this, if set_it_insn_type and in_it_block have to be used,
18372 set_it_insn_type has to be called first.
18374 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
18375 determines the insn IT type depending on the inst.cond code.
18376 When a tencode () routine encodes an instruction that can be
18377 either outside an IT block, or, in the case of being inside, has to be
18378 the last one, set_it_insn_type_last () will determine the proper
18379 IT instruction type based on the inst.cond code. Otherwise,
18380 set_it_insn_type can be called for overriding that logic or
18381 for covering other cases.
18383 Calling handle_it_state () may not transition the IT block state to
18384 OUTSIDE_IT_BLOCK immediately, since the (current) state could be
18385 still queried. Instead, if the FSM determines that the state should
18386 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
18387 after the tencode () function: that's what it_fsm_post_encode () does.
18389 Since in_it_block () calls the state handling function to get an
18390 updated state, an error may occur (due to invalid insns combination).
18391 In that case, inst.error is set.
18392 Therefore, inst.error has to be checked after the execution of
18393 the tencode () routine.
18395 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
18396 any pending state change (if any) that didn't take place in
18397 handle_it_state () as explained above. */
18400 it_fsm_pre_encode (void)
18402 if (inst
.cond
!= COND_ALWAYS
)
18403 inst
.it_insn_type
= INSIDE_IT_INSN
;
18405 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
18407 now_it
.state_handled
= 0;
18410 /* IT state FSM handling function. */
18413 handle_it_state (void)
18415 now_it
.state_handled
= 1;
18416 now_it
.insn_cond
= FALSE
;
18418 switch (now_it
.state
)
18420 case OUTSIDE_IT_BLOCK
:
18421 switch (inst
.it_insn_type
)
18423 case OUTSIDE_IT_INSN
:
18426 case INSIDE_IT_INSN
:
18427 case INSIDE_IT_LAST_INSN
:
18428 if (thumb_mode
== 0)
18431 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
18432 as_tsktsk (_("Warning: conditional outside an IT block"\
18437 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
18438 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
18440 /* Automatically generate the IT instruction. */
18441 new_automatic_it_block (inst
.cond
);
18442 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
18443 close_automatic_it_block ();
18447 inst
.error
= BAD_OUT_IT
;
18453 case IF_INSIDE_IT_LAST_INSN
:
18454 case NEUTRAL_IT_INSN
:
18458 now_it
.state
= MANUAL_IT_BLOCK
;
18459 now_it
.block_length
= 0;
18464 case AUTOMATIC_IT_BLOCK
:
18465 /* Three things may happen now:
18466 a) We should increment current it block size;
18467 b) We should close current it block (closing insn or 4 insns);
18468 c) We should close current it block and start a new one (due
18469 to incompatible conditions or
18470 4 insns-length block reached). */
18472 switch (inst
.it_insn_type
)
18474 case OUTSIDE_IT_INSN
:
18475 /* The closure of the block shall happen immediately,
18476 so any in_it_block () call reports the block as closed. */
18477 force_automatic_it_block_close ();
18480 case INSIDE_IT_INSN
:
18481 case INSIDE_IT_LAST_INSN
:
18482 case IF_INSIDE_IT_LAST_INSN
:
18483 now_it
.block_length
++;
18485 if (now_it
.block_length
> 4
18486 || !now_it_compatible (inst
.cond
))
18488 force_automatic_it_block_close ();
18489 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18490 new_automatic_it_block (inst
.cond
);
18494 now_it
.insn_cond
= TRUE
;
18495 now_it_add_mask (inst
.cond
);
18498 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18499 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18500 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18501 close_automatic_it_block ();
18504 case NEUTRAL_IT_INSN
:
18505 now_it
.block_length
++;
18506 now_it
.insn_cond
= TRUE
;
18508 if (now_it
.block_length
> 4)
18509 force_automatic_it_block_close ();
18511 now_it_add_mask (now_it
.cc
& 1);
18515 close_automatic_it_block ();
18516 now_it
.state
= MANUAL_IT_BLOCK
;
18521 case MANUAL_IT_BLOCK
:
18523 /* Check conditional suffixes. */
18524 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18527 now_it
.mask
&= 0x1f;
18528 is_last
= (now_it
.mask
== 0x10);
18529 now_it
.insn_cond
= TRUE
;
18531 switch (inst
.it_insn_type
)
18533 case OUTSIDE_IT_INSN
:
18534 inst
.error
= BAD_NOT_IT
;
18537 case INSIDE_IT_INSN
:
18538 if (cond
!= inst
.cond
)
18540 inst
.error
= BAD_IT_COND
;
18545 case INSIDE_IT_LAST_INSN
:
18546 case IF_INSIDE_IT_LAST_INSN
:
18547 if (cond
!= inst
.cond
)
18549 inst
.error
= BAD_IT_COND
;
18554 inst
.error
= BAD_BRANCH
;
18559 case NEUTRAL_IT_INSN
:
18560 /* The BKPT instruction is unconditional even in an IT block. */
18564 inst
.error
= BAD_IT_IT
;
18574 struct depr_insn_mask
18576 unsigned long pattern
;
18577 unsigned long mask
;
18578 const char* description
;
18581 /* List of 16-bit instruction patterns deprecated in an IT block in
18583 static const struct depr_insn_mask depr_it_insns
[] = {
18584 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18585 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18586 { 0xa000, 0xb800, N_("ADR") },
18587 { 0x4800, 0xf800, N_("Literal loads") },
18588 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18589 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18590 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18591 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18592 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18597 it_fsm_post_encode (void)
18601 if (!now_it
.state_handled
)
18602 handle_it_state ();
18604 if (now_it
.insn_cond
18605 && !now_it
.warn_deprecated
18606 && warn_on_deprecated
18607 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
18608 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
18610 if (inst
.instruction
>= 0x10000)
18612 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18613 "performance deprecated in ARMv8-A and ARMv8-R"));
18614 now_it
.warn_deprecated
= TRUE
;
18618 const struct depr_insn_mask
*p
= depr_it_insns
;
18620 while (p
->mask
!= 0)
18622 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18624 as_tsktsk (_("IT blocks containing 16-bit Thumb "
18625 "instructions of the following class are "
18626 "performance deprecated in ARMv8-A and "
18627 "ARMv8-R: %s"), p
->description
);
18628 now_it
.warn_deprecated
= TRUE
;
18636 if (now_it
.block_length
> 1)
18638 as_tsktsk (_("IT blocks containing more than one conditional "
18639 "instruction are performance deprecated in ARMv8-A and "
18641 now_it
.warn_deprecated
= TRUE
;
18645 is_last
= (now_it
.mask
== 0x10);
18648 now_it
.state
= OUTSIDE_IT_BLOCK
;
18654 force_automatic_it_block_close (void)
18656 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18658 close_automatic_it_block ();
18659 now_it
.state
= OUTSIDE_IT_BLOCK
;
18667 if (!now_it
.state_handled
)
18668 handle_it_state ();
18670 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18673 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18674 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18675 here, hence the "known" in the function name. */
18678 known_t32_only_insn (const struct asm_opcode
*opcode
)
18680 /* Original Thumb-1 wide instruction. */
18681 if (opcode
->tencode
== do_t_blx
18682 || opcode
->tencode
== do_t_branch23
18683 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18684 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18687 /* Wide-only instruction added to ARMv8-M Baseline. */
18688 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18689 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18690 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18691 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18697 /* Whether wide instruction variant can be used if available for a valid OPCODE
18701 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18703 if (known_t32_only_insn (opcode
))
18706 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18707 of variant T3 of B.W is checked in do_t_branch. */
18708 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18709 && opcode
->tencode
== do_t_branch
)
18712 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
18713 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18714 && opcode
->tencode
== do_t_mov_cmp
18715 /* Make sure CMP instruction is not affected. */
18716 && opcode
->aencode
== do_mov
)
18719 /* Wide instruction variants of all instructions with narrow *and* wide
18720 variants become available with ARMv6t2. Other opcodes are either
18721 narrow-only or wide-only and are thus available if OPCODE is valid. */
18722 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18725 /* OPCODE with narrow only instruction variant or wide variant not
18731 md_assemble (char *str
)
18734 const struct asm_opcode
* opcode
;
18736 /* Align the previous label if needed. */
18737 if (last_label_seen
!= NULL
)
18739 symbol_set_frag (last_label_seen
, frag_now
);
18740 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18741 S_SET_SEGMENT (last_label_seen
, now_seg
);
18744 memset (&inst
, '\0', sizeof (inst
));
18745 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18747 opcode
= opcode_lookup (&p
);
18750 /* It wasn't an instruction, but it might be a register alias of
18751 the form alias .req reg, or a Neon .dn/.qn directive. */
18752 if (! create_register_alias (str
, p
)
18753 && ! create_neon_reg_alias (str
, p
))
18754 as_bad (_("bad instruction `%s'"), str
);
18759 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18760 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18762 /* The value which unconditional instructions should have in place of the
18763 condition field. */
18764 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18768 arm_feature_set variant
;
18770 variant
= cpu_variant
;
18771 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18772 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18773 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18774 /* Check that this instruction is supported for this CPU. */
18775 if (!opcode
->tvariant
18776 || (thumb_mode
== 1
18777 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18779 if (opcode
->tencode
== do_t_swi
)
18780 as_bad (_("SVC is not permitted on this architecture"));
18782 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18785 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18786 && opcode
->tencode
!= do_t_branch
)
18788 as_bad (_("Thumb does not support conditional execution"));
18792 /* Two things are addressed here:
18793 1) Implicit require narrow instructions on Thumb-1.
18794 This avoids relaxation accidentally introducing Thumb-2
18796 2) Reject wide instructions in non Thumb-2 cores.
18798 Only instructions with narrow and wide variants need to be handled
18799 but selecting all non wide-only instructions is easier. */
18800 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18801 && !t32_insn_ok (variant
, opcode
))
18803 if (inst
.size_req
== 0)
18805 else if (inst
.size_req
== 4)
18807 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18808 as_bad (_("selected processor does not support 32bit wide "
18809 "variant of instruction `%s'"), str
);
18811 as_bad (_("selected processor does not support `%s' in "
18812 "Thumb-2 mode"), str
);
18817 inst
.instruction
= opcode
->tvalue
;
18819 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18821 /* Prepare the it_insn_type for those encodings that don't set
18823 it_fsm_pre_encode ();
18825 opcode
->tencode ();
18827 it_fsm_post_encode ();
18830 if (!(inst
.error
|| inst
.relax
))
18832 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18833 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18834 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18836 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18841 /* Something has gone badly wrong if we try to relax a fixed size
18843 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18845 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18846 *opcode
->tvariant
);
18847 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18848 set those bits when Thumb-2 32-bit instructions are seen. The impact
18849 of relaxable instructions will be considered later after we finish all
18851 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18852 variant
= arm_arch_none
;
18854 variant
= cpu_variant
;
18855 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18856 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18859 check_neon_suffixes
;
18863 mapping_state (MAP_THUMB
);
18866 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18870 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18871 is_bx
= (opcode
->aencode
== do_bx
);
18873 /* Check that this instruction is supported for this CPU. */
18874 if (!(is_bx
&& fix_v4bx
)
18875 && !(opcode
->avariant
&&
18876 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18878 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18883 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18887 inst
.instruction
= opcode
->avalue
;
18888 if (opcode
->tag
== OT_unconditionalF
)
18889 inst
.instruction
|= 0xFU
<< 28;
18891 inst
.instruction
|= inst
.cond
<< 28;
18892 inst
.size
= INSN_SIZE
;
18893 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18895 it_fsm_pre_encode ();
18896 opcode
->aencode ();
18897 it_fsm_post_encode ();
18899 /* Arm mode bx is marked as both v4T and v5 because it's still required
18900 on a hypothetical non-thumb v5 core. */
18902 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18904 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18905 *opcode
->avariant
);
18907 check_neon_suffixes
;
18911 mapping_state (MAP_ARM
);
18916 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18924 check_it_blocks_finished (void)
18929 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18930 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18931 == MANUAL_IT_BLOCK
)
18933 as_warn (_("section '%s' finished with an open IT block."),
18937 if (now_it
.state
== MANUAL_IT_BLOCK
)
18938 as_warn (_("file finished with an open IT block."));
18942 /* Various frobbings of labels and their addresses. */
18945 arm_start_line_hook (void)
18947 last_label_seen
= NULL
;
18951 arm_frob_label (symbolS
* sym
)
18953 last_label_seen
= sym
;
18955 ARM_SET_THUMB (sym
, thumb_mode
);
18957 #if defined OBJ_COFF || defined OBJ_ELF
18958 ARM_SET_INTERWORK (sym
, support_interwork
);
18961 force_automatic_it_block_close ();
18963 /* Note - do not allow local symbols (.Lxxx) to be labelled
18964 as Thumb functions. This is because these labels, whilst
18965 they exist inside Thumb code, are not the entry points for
18966 possible ARM->Thumb calls. Also, these labels can be used
18967 as part of a computed goto or switch statement. eg gcc
18968 can generate code that looks like this:
18970 ldr r2, [pc, .Laaa]
18980 The first instruction loads the address of the jump table.
18981 The second instruction converts a table index into a byte offset.
18982 The third instruction gets the jump address out of the table.
18983 The fourth instruction performs the jump.
18985 If the address stored at .Laaa is that of a symbol which has the
18986 Thumb_Func bit set, then the linker will arrange for this address
18987 to have the bottom bit set, which in turn would mean that the
18988 address computation performed by the third instruction would end
18989 up with the bottom bit set. Since the ARM is capable of unaligned
18990 word loads, the instruction would then load the incorrect address
18991 out of the jump table, and chaos would ensue. */
18992 if (label_is_thumb_function_name
18993 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18994 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18996 /* When the address of a Thumb function is taken the bottom
18997 bit of that address should be set. This will allow
18998 interworking between Arm and Thumb functions to work
19001 THUMB_SET_FUNC (sym
, 1);
19003 label_is_thumb_function_name
= FALSE
;
19006 dwarf2_emit_label (sym
);
19010 arm_data_in_code (void)
19012 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
19014 *input_line_pointer
= '/';
19015 input_line_pointer
+= 5;
19016 *input_line_pointer
= 0;
19024 arm_canonicalize_symbol_name (char * name
)
19028 if (thumb_mode
&& (len
= strlen (name
)) > 5
19029 && streq (name
+ len
- 5, "/data"))
19030 *(name
+ len
- 5) = 0;
19035 /* Table of all register names defined by default. The user can
19036 define additional names with .req. Note that all register names
19037 should appear in both upper and lowercase variants. Some registers
19038 also have mixed-case names. */
19040 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
19041 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
19042 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
19043 #define REGSET(p,t) \
19044 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
19045 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
19046 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
19047 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
19048 #define REGSETH(p,t) \
19049 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
19050 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
19051 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
19052 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
19053 #define REGSET2(p,t) \
19054 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
19055 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
19056 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
19057 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
19058 #define SPLRBANK(base,bank,t) \
19059 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
19060 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
19061 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
19062 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
19063 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
19064 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
19066 static const struct reg_entry reg_names
[] =
19068 /* ARM integer registers. */
19069 REGSET(r
, RN
), REGSET(R
, RN
),
19071 /* ATPCS synonyms. */
19072 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
19073 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
19074 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
19076 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
19077 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
19078 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
19080 /* Well-known aliases. */
19081 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
19082 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
19084 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
19085 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
19087 /* Coprocessor numbers. */
19088 REGSET(p
, CP
), REGSET(P
, CP
),
19090 /* Coprocessor register numbers. The "cr" variants are for backward
19092 REGSET(c
, CN
), REGSET(C
, CN
),
19093 REGSET(cr
, CN
), REGSET(CR
, CN
),
19095 /* ARM banked registers. */
19096 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
19097 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
19098 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
19099 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
19100 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
19101 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
19102 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
19104 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
19105 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
19106 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
19107 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
19108 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
19109 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
19110 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
19111 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
19113 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
19114 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
19115 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
19116 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
19117 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
19118 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
19119 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
19120 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19121 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19123 /* FPA registers. */
19124 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
19125 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
19127 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
19128 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
19130 /* VFP SP registers. */
19131 REGSET(s
,VFS
), REGSET(S
,VFS
),
19132 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
19134 /* VFP DP Registers. */
19135 REGSET(d
,VFD
), REGSET(D
,VFD
),
19136 /* Extra Neon DP registers. */
19137 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
19139 /* Neon QP registers. */
19140 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
19142 /* VFP control registers. */
19143 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
19144 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
19145 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
19146 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
19147 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
19148 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
19149 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
19151 /* Maverick DSP coprocessor registers. */
19152 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
19153 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
19155 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
19156 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
19157 REGDEF(dspsc
,0,DSPSC
),
19159 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
19160 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
19161 REGDEF(DSPSC
,0,DSPSC
),
19163 /* iWMMXt data registers - p0, c0-15. */
19164 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
19166 /* iWMMXt control registers - p1, c0-3. */
19167 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
19168 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
19169 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
19170 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
19172 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
19173 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
19174 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
19175 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
19176 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
19178 /* XScale accumulator registers. */
19179 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
19185 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
19186 within psr_required_here. */
19187 static const struct asm_psr psrs
[] =
19189 /* Backward compatibility notation. Note that "all" is no longer
19190 truly all possible PSR bits. */
19191 {"all", PSR_c
| PSR_f
},
19195 /* Individual flags. */
19201 /* Combinations of flags. */
19202 {"fs", PSR_f
| PSR_s
},
19203 {"fx", PSR_f
| PSR_x
},
19204 {"fc", PSR_f
| PSR_c
},
19205 {"sf", PSR_s
| PSR_f
},
19206 {"sx", PSR_s
| PSR_x
},
19207 {"sc", PSR_s
| PSR_c
},
19208 {"xf", PSR_x
| PSR_f
},
19209 {"xs", PSR_x
| PSR_s
},
19210 {"xc", PSR_x
| PSR_c
},
19211 {"cf", PSR_c
| PSR_f
},
19212 {"cs", PSR_c
| PSR_s
},
19213 {"cx", PSR_c
| PSR_x
},
19214 {"fsx", PSR_f
| PSR_s
| PSR_x
},
19215 {"fsc", PSR_f
| PSR_s
| PSR_c
},
19216 {"fxs", PSR_f
| PSR_x
| PSR_s
},
19217 {"fxc", PSR_f
| PSR_x
| PSR_c
},
19218 {"fcs", PSR_f
| PSR_c
| PSR_s
},
19219 {"fcx", PSR_f
| PSR_c
| PSR_x
},
19220 {"sfx", PSR_s
| PSR_f
| PSR_x
},
19221 {"sfc", PSR_s
| PSR_f
| PSR_c
},
19222 {"sxf", PSR_s
| PSR_x
| PSR_f
},
19223 {"sxc", PSR_s
| PSR_x
| PSR_c
},
19224 {"scf", PSR_s
| PSR_c
| PSR_f
},
19225 {"scx", PSR_s
| PSR_c
| PSR_x
},
19226 {"xfs", PSR_x
| PSR_f
| PSR_s
},
19227 {"xfc", PSR_x
| PSR_f
| PSR_c
},
19228 {"xsf", PSR_x
| PSR_s
| PSR_f
},
19229 {"xsc", PSR_x
| PSR_s
| PSR_c
},
19230 {"xcf", PSR_x
| PSR_c
| PSR_f
},
19231 {"xcs", PSR_x
| PSR_c
| PSR_s
},
19232 {"cfs", PSR_c
| PSR_f
| PSR_s
},
19233 {"cfx", PSR_c
| PSR_f
| PSR_x
},
19234 {"csf", PSR_c
| PSR_s
| PSR_f
},
19235 {"csx", PSR_c
| PSR_s
| PSR_x
},
19236 {"cxf", PSR_c
| PSR_x
| PSR_f
},
19237 {"cxs", PSR_c
| PSR_x
| PSR_s
},
19238 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
19239 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
19240 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
19241 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
19242 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
19243 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
19244 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
19245 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
19246 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
19247 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
19248 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
19249 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
19250 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
19251 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
19252 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
19253 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
19254 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
19255 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
19256 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
19257 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
19258 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
19259 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
19260 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
19261 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
19264 /* Table of V7M psr names. */
19265 static const struct asm_psr v7m_psrs
[] =
19267 {"apsr", 0x0 }, {"APSR", 0x0 },
19268 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
19269 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
19270 {"psr", 0x3 }, {"PSR", 0x3 },
19271 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
19272 {"ipsr", 0x5 }, {"IPSR", 0x5 },
19273 {"epsr", 0x6 }, {"EPSR", 0x6 },
19274 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
19275 {"msp", 0x8 }, {"MSP", 0x8 },
19276 {"psp", 0x9 }, {"PSP", 0x9 },
19277 {"msplim", 0xa }, {"MSPLIM", 0xa },
19278 {"psplim", 0xb }, {"PSPLIM", 0xb },
19279 {"primask", 0x10}, {"PRIMASK", 0x10},
19280 {"basepri", 0x11}, {"BASEPRI", 0x11},
19281 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
19282 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
19283 {"control", 0x14}, {"CONTROL", 0x14},
19284 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
19285 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
19286 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
19287 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
19288 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
19289 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
19290 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
19291 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
19292 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
19295 /* Table of all shift-in-operand names. */
19296 static const struct asm_shift_name shift_names
[] =
19298 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
19299 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
19300 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
19301 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
19302 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
19303 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
19306 /* Table of all explicit relocation names. */
19308 static struct reloc_entry reloc_names
[] =
19310 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
19311 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
19312 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
19313 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
19314 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
19315 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
19316 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
19317 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
19318 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
19319 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
19320 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
19321 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
19322 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
19323 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
19324 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
19325 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
19326 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
19327 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
19328 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
19329 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
19330 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
19331 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
19332 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
19333 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
19334 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
19335 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
19336 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
19340 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
19341 static const struct asm_cond conds
[] =
19345 {"cs", 0x2}, {"hs", 0x2},
19346 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
19360 #define UL_BARRIER(L,U,CODE,FEAT) \
19361 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
19362 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
19364 static struct asm_barrier_opt barrier_opt_names
[] =
19366 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
19367 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
19368 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
19369 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
19370 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
19371 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
19372 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
19373 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
19374 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
19375 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
19376 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
19377 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
19378 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
19379 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
19380 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
19381 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
19386 /* Table of ARM-format instructions. */
19388 /* Macros for gluing together operand strings. N.B. In all cases
19389 other than OPS0, the trailing OP_stop comes from default
19390 zero-initialization of the unspecified elements of the array. */
19391 #define OPS0() { OP_stop, }
19392 #define OPS1(a) { OP_##a, }
19393 #define OPS2(a,b) { OP_##a,OP_##b, }
19394 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
19395 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
19396 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
19397 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
19399 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
19400 This is useful when mixing operands for ARM and THUMB, i.e. using the
19401 MIX_ARM_THUMB_OPERANDS macro.
19402 In order to use these macros, prefix the number of operands with _
19404 #define OPS_1(a) { a, }
19405 #define OPS_2(a,b) { a,b, }
19406 #define OPS_3(a,b,c) { a,b,c, }
19407 #define OPS_4(a,b,c,d) { a,b,c,d, }
19408 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
19409 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
19411 /* These macros abstract out the exact format of the mnemonic table and
19412 save some repeated characters. */
19414 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
19415 #define TxCE(mnem, op, top, nops, ops, ae, te) \
19416 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
19417 THUMB_VARIANT, do_##ae, do_##te }
19419 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
19420 a T_MNEM_xyz enumerator. */
19421 #define TCE(mnem, aop, top, nops, ops, ae, te) \
19422 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
19423 #define tCE(mnem, aop, top, nops, ops, ae, te) \
19424 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19426 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
19427 infix after the third character. */
19428 #define TxC3(mnem, op, top, nops, ops, ae, te) \
19429 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
19430 THUMB_VARIANT, do_##ae, do_##te }
19431 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
19432 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
19433 THUMB_VARIANT, do_##ae, do_##te }
19434 #define TC3(mnem, aop, top, nops, ops, ae, te) \
19435 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
19436 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
19437 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
19438 #define tC3(mnem, aop, top, nops, ops, ae, te) \
19439 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19440 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
19441 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19443 /* Mnemonic that cannot be conditionalized. The ARM condition-code
19444 field is still 0xE. Many of the Thumb variants can be executed
19445 conditionally, so this is checked separately. */
19446 #define TUE(mnem, op, top, nops, ops, ae, te) \
19447 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19448 THUMB_VARIANT, do_##ae, do_##te }
19450 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
19451 Used by mnemonics that have very minimal differences in the encoding for
19452 ARM and Thumb variants and can be handled in a common function. */
19453 #define TUEc(mnem, op, top, nops, ops, en) \
19454 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19455 THUMB_VARIANT, do_##en, do_##en }
19457 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
19458 condition code field. */
19459 #define TUF(mnem, op, top, nops, ops, ae, te) \
19460 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19461 THUMB_VARIANT, do_##ae, do_##te }
19463 /* ARM-only variants of all the above. */
19464 #define CE(mnem, op, nops, ops, ae) \
19465 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19467 #define C3(mnem, op, nops, ops, ae) \
19468 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19470 /* Thumb-only variants of TCE and TUE. */
19471 #define ToC(mnem, top, nops, ops, te) \
19472 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
19475 #define ToU(mnem, top, nops, ops, te) \
19476 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
19479 /* Legacy mnemonics that always have conditional infix after the third
19481 #define CL(mnem, op, nops, ops, ae) \
19482 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19483 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19485 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19486 #define cCE(mnem, op, nops, ops, ae) \
19487 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19489 /* Legacy coprocessor instructions where conditional infix and conditional
19490 suffix are ambiguous. For consistency this includes all FPA instructions,
19491 not just the potentially ambiguous ones. */
19492 #define cCL(mnem, op, nops, ops, ae) \
19493 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19494 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19496 /* Coprocessor, takes either a suffix or a position-3 infix
19497 (for an FPA corner case). */
19498 #define C3E(mnem, op, nops, ops, ae) \
19499 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19500 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19502 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19503 { m1 #m2 m3, OPS##nops ops, \
19504 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19505 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19507 #define CM(m1, m2, op, nops, ops, ae) \
19508 xCM_ (m1, , m2, op, nops, ops, ae), \
19509 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19510 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19511 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19512 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19513 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19514 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19515 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19516 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19517 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19518 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19519 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19520 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19521 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19522 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19523 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19524 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19525 xCM_ (m1, le, m2, op, nops, ops, ae), \
19526 xCM_ (m1, al, m2, op, nops, ops, ae)
19528 #define UE(mnem, op, nops, ops, ae) \
19529 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19531 #define UF(mnem, op, nops, ops, ae) \
19532 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19534 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19535 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19536 use the same encoding function for each. */
19537 #define NUF(mnem, op, nops, ops, enc) \
19538 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19539 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19541 /* Neon data processing, version which indirects through neon_enc_tab for
19542 the various overloaded versions of opcodes. */
19543 #define nUF(mnem, op, nops, ops, enc) \
19544 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19545 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19547 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19549 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19550 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19551 THUMB_VARIANT, do_##enc, do_##enc }
19553 #define NCE(mnem, op, nops, ops, enc) \
19554 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19556 #define NCEF(mnem, op, nops, ops, enc) \
19557 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19559 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19560 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19561 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19562 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19564 #define nCE(mnem, op, nops, ops, enc) \
19565 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19567 #define nCEF(mnem, op, nops, ops, enc) \
19568 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19572 static const struct asm_opcode insns
[] =
19574 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19575 #define THUMB_VARIANT & arm_ext_v4t
19576 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19577 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19578 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19579 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19580 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19581 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19582 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19583 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19584 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19585 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19586 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19587 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19588 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19589 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19590 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19591 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19593 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19594 for setting PSR flag bits. They are obsolete in V6 and do not
19595 have Thumb equivalents. */
19596 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19597 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19598 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19599 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19600 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19601 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19602 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19603 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19604 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19606 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19607 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19608 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19609 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19611 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19612 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19613 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19615 OP_ADDRGLDR
),ldst
, t_ldst
),
19616 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19618 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19619 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19620 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19621 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19622 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19623 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19625 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19626 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19629 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19630 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19631 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19632 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19634 /* Thumb-compatibility pseudo ops. */
19635 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19636 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19637 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19638 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19639 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19640 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19641 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19642 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19643 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19644 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19645 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19646 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19648 /* These may simplify to neg. */
19649 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19650 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19652 #undef THUMB_VARIANT
19653 #define THUMB_VARIANT & arm_ext_os
19655 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19656 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19658 #undef THUMB_VARIANT
19659 #define THUMB_VARIANT & arm_ext_v6
19661 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19663 /* V1 instructions with no Thumb analogue prior to V6T2. */
19664 #undef THUMB_VARIANT
19665 #define THUMB_VARIANT & arm_ext_v6t2
19667 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19668 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19669 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19671 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19672 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19673 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19674 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19676 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19677 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19679 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19680 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19682 /* V1 instructions with no Thumb analogue at all. */
19683 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19684 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19686 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19687 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19688 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19689 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19690 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19691 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19692 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19693 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19696 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19697 #undef THUMB_VARIANT
19698 #define THUMB_VARIANT & arm_ext_v4t
19700 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19701 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19703 #undef THUMB_VARIANT
19704 #define THUMB_VARIANT & arm_ext_v6t2
19706 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19707 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19709 /* Generic coprocessor instructions. */
19710 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19711 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19712 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19713 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19714 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19715 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19716 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19719 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19721 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19722 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19725 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19726 #undef THUMB_VARIANT
19727 #define THUMB_VARIANT & arm_ext_msr
19729 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19730 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19733 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19734 #undef THUMB_VARIANT
19735 #define THUMB_VARIANT & arm_ext_v6t2
19737 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19738 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19739 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19740 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19741 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19742 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19743 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19744 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19747 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19748 #undef THUMB_VARIANT
19749 #define THUMB_VARIANT & arm_ext_v4t
19751 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19752 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19753 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19754 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19755 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19756 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19759 #define ARM_VARIANT & arm_ext_v4t_5
19761 /* ARM Architecture 4T. */
19762 /* Note: bx (and blx) are required on V5, even if the processor does
19763 not support Thumb. */
19764 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19767 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19768 #undef THUMB_VARIANT
19769 #define THUMB_VARIANT & arm_ext_v5t
19771 /* Note: blx has 2 variants; the .value coded here is for
19772 BLX(2). Only this variant has conditional execution. */
19773 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19774 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19776 #undef THUMB_VARIANT
19777 #define THUMB_VARIANT & arm_ext_v6t2
19779 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19780 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19781 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19782 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19783 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19784 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19785 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19786 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19789 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19790 #undef THUMB_VARIANT
19791 #define THUMB_VARIANT & arm_ext_v5exp
19793 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19794 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19795 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19796 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19798 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19799 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19801 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19802 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19803 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19804 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19806 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19807 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19808 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19809 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19811 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19812 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19814 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19815 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19816 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19817 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19820 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19821 #undef THUMB_VARIANT
19822 #define THUMB_VARIANT & arm_ext_v6t2
19824 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19825 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19827 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19828 ADDRGLDRS
), ldrd
, t_ldstd
),
19830 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19831 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19834 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19836 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19839 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19840 #undef THUMB_VARIANT
19841 #define THUMB_VARIANT & arm_ext_v6
19843 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19844 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19845 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19846 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19847 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19848 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19849 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19850 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19851 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19852 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19854 #undef THUMB_VARIANT
19855 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19857 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19858 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19860 #undef THUMB_VARIANT
19861 #define THUMB_VARIANT & arm_ext_v6t2
19863 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19864 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19866 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19867 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19869 /* ARM V6 not included in V7M. */
19870 #undef THUMB_VARIANT
19871 #define THUMB_VARIANT & arm_ext_v6_notm
19872 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19873 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19874 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19875 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19876 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19877 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19878 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19879 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19880 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19881 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19882 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19883 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19884 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19885 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19886 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19887 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19888 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19889 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19890 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19892 /* ARM V6 not included in V7M (eg. integer SIMD). */
19893 #undef THUMB_VARIANT
19894 #define THUMB_VARIANT & arm_ext_v6_dsp
19895 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19896 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19897 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19898 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19899 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19900 /* Old name for QASX. */
19901 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19902 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19903 /* Old name for QSAX. */
19904 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19905 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19906 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19907 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19908 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19909 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19910 /* Old name for SASX. */
19911 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19912 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19913 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19914 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19915 /* Old name for SHASX. */
19916 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19917 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19918 /* Old name for SHSAX. */
19919 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19920 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19921 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19922 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19923 /* Old name for SSAX. */
19924 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19925 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19926 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19927 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19928 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19929 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19930 /* Old name for UASX. */
19931 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19932 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19933 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19934 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19935 /* Old name for UHASX. */
19936 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19937 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19938 /* Old name for UHSAX. */
19939 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19940 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19941 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19942 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19943 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19944 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19945 /* Old name for UQASX. */
19946 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19947 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19948 /* Old name for UQSAX. */
19949 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19950 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19951 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19952 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19953 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19954 /* Old name for USAX. */
19955 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19956 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19957 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19958 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19959 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19960 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19961 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19962 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19963 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19964 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19965 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19966 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19967 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19968 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19969 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19970 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19971 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19972 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19973 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19974 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19975 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19976 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19977 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19978 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19979 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19980 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19981 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19982 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19983 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19984 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19985 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19986 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19987 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19988 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19991 #define ARM_VARIANT & arm_ext_v6k
19992 #undef THUMB_VARIANT
19993 #define THUMB_VARIANT & arm_ext_v6k
19995 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19996 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19997 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19998 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
20000 #undef THUMB_VARIANT
20001 #define THUMB_VARIANT & arm_ext_v6_notm
20002 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
20004 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
20005 RRnpcb
), strexd
, t_strexd
),
20007 #undef THUMB_VARIANT
20008 #define THUMB_VARIANT & arm_ext_v6t2_v8m
20009 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
20011 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
20013 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
20015 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
20017 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
20020 #define ARM_VARIANT & arm_ext_sec
20021 #undef THUMB_VARIANT
20022 #define THUMB_VARIANT & arm_ext_sec
20024 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
20027 #define ARM_VARIANT & arm_ext_virt
20028 #undef THUMB_VARIANT
20029 #define THUMB_VARIANT & arm_ext_virt
20031 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
20032 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
20035 #define ARM_VARIANT & arm_ext_pan
20036 #undef THUMB_VARIANT
20037 #define THUMB_VARIANT & arm_ext_pan
20039 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
20042 #define ARM_VARIANT & arm_ext_v6t2
20043 #undef THUMB_VARIANT
20044 #define THUMB_VARIANT & arm_ext_v6t2
20046 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
20047 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
20048 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
20049 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
20051 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
20052 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
20054 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20055 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20056 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20057 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20060 #define ARM_VARIANT & arm_ext_v3
20061 #undef THUMB_VARIANT
20062 #define THUMB_VARIANT & arm_ext_v6t2
20064 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
20065 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
20066 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
20069 #define ARM_VARIANT & arm_ext_v6t2
20070 #undef THUMB_VARIANT
20071 #define THUMB_VARIANT & arm_ext_v6t2_v8m
20072 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
20073 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
20075 /* Thumb-only instructions. */
20077 #define ARM_VARIANT NULL
20078 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
20079 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
20081 /* ARM does not really have an IT instruction, so always allow it.
20082 The opcode is copied from Thumb in order to allow warnings in
20083 -mimplicit-it=[never | arm] modes. */
20085 #define ARM_VARIANT & arm_ext_v1
20086 #undef THUMB_VARIANT
20087 #define THUMB_VARIANT & arm_ext_v6t2
20089 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
20090 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
20091 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
20092 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
20093 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
20094 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
20095 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
20096 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
20097 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
20098 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
20099 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
20100 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
20101 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
20102 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
20103 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
20104 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
20105 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20106 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20108 /* Thumb2 only instructions. */
20110 #define ARM_VARIANT NULL
20112 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20113 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20114 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20115 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20116 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
20117 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
20119 /* Hardware division instructions. */
20121 #define ARM_VARIANT & arm_ext_adiv
20122 #undef THUMB_VARIANT
20123 #define THUMB_VARIANT & arm_ext_div
20125 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20126 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20128 /* ARM V6M/V7 instructions. */
20130 #define ARM_VARIANT & arm_ext_barrier
20131 #undef THUMB_VARIANT
20132 #define THUMB_VARIANT & arm_ext_barrier
20134 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
20135 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
20136 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
20138 /* ARM V7 instructions. */
20140 #define ARM_VARIANT & arm_ext_v7
20141 #undef THUMB_VARIANT
20142 #define THUMB_VARIANT & arm_ext_v7
20144 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
20145 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
20148 #define ARM_VARIANT & arm_ext_mp
20149 #undef THUMB_VARIANT
20150 #define THUMB_VARIANT & arm_ext_mp
20152 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
20154 /* AArchv8 instructions. */
20156 #define ARM_VARIANT & arm_ext_v8
20158 /* Instructions shared between armv8-a and armv8-m. */
20159 #undef THUMB_VARIANT
20160 #define THUMB_VARIANT & arm_ext_atomics
20162 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20163 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20164 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20165 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20166 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20167 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20168 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20169 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
20170 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20171 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20173 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20175 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20177 #undef THUMB_VARIANT
20178 #define THUMB_VARIANT & arm_ext_v8
20180 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
20181 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
20182 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
20184 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
20186 /* ARMv8 T32 only. */
20188 #define ARM_VARIANT NULL
20189 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
20190 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
20191 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
20193 /* FP for ARMv8. */
20195 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
20196 #undef THUMB_VARIANT
20197 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
20199 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20200 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20201 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20202 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20203 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20204 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20205 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
20206 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
20207 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
20208 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
20209 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
20210 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
20211 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
20212 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
20213 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
20214 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
20215 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
20217 /* Crypto v1 extensions. */
20219 #define ARM_VARIANT & fpu_crypto_ext_armv8
20220 #undef THUMB_VARIANT
20221 #define THUMB_VARIANT & fpu_crypto_ext_armv8
20223 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
20224 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
20225 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
20226 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
20227 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
20228 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
20229 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
20230 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
20231 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
20232 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
20233 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
20234 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
20235 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
20236 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
20239 #define ARM_VARIANT & crc_ext_armv8
20240 #undef THUMB_VARIANT
20241 #define THUMB_VARIANT & crc_ext_armv8
20242 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
20243 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
20244 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
20245 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
20246 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
20247 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
20249 /* ARMv8.2 RAS extension. */
20251 #define ARM_VARIANT & arm_ext_ras
20252 #undef THUMB_VARIANT
20253 #define THUMB_VARIANT & arm_ext_ras
20254 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
20257 #define ARM_VARIANT & arm_ext_v8_3
20258 #undef THUMB_VARIANT
20259 #define THUMB_VARIANT & arm_ext_v8_3
20260 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
20261 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
20262 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
20265 #define ARM_VARIANT & fpu_neon_ext_dotprod
20266 #undef THUMB_VARIANT
20267 #define THUMB_VARIANT & fpu_neon_ext_dotprod
20268 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
20269 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
20272 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
20273 #undef THUMB_VARIANT
20274 #define THUMB_VARIANT NULL
20276 cCE("wfs", e200110
, 1, (RR
), rd
),
20277 cCE("rfs", e300110
, 1, (RR
), rd
),
20278 cCE("wfc", e400110
, 1, (RR
), rd
),
20279 cCE("rfc", e500110
, 1, (RR
), rd
),
20281 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20282 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20283 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20284 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20286 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20287 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20288 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20289 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20291 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
20292 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
20293 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
20294 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
20295 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
20296 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
20297 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
20298 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
20299 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
20300 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
20301 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
20302 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
20304 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
20305 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
20306 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
20307 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
20308 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
20309 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
20310 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
20311 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
20312 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
20313 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
20314 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
20315 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
20317 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
20318 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
20319 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
20320 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
20321 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
20322 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
20323 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
20324 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
20325 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
20326 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
20327 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
20328 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
20330 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
20331 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
20332 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
20333 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
20334 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
20335 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
20336 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
20337 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
20338 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
20339 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
20340 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
20341 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
20343 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
20344 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
20345 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
20346 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
20347 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
20348 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
20349 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
20350 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
20351 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
20352 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
20353 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
20354 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
20356 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
20357 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
20358 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
20359 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
20360 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
20361 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
20362 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
20363 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
20364 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
20365 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
20366 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
20367 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
20369 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
20370 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
20371 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
20372 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
20373 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
20374 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
20375 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
20376 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
20377 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
20378 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
20379 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
20380 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
20382 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
20383 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
20384 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
20385 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
20386 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
20387 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
20388 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
20389 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
20390 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
20391 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
20392 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
20393 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
20395 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
20396 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
20397 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
20398 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
20399 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
20400 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
20401 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
20402 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
20403 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
20404 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
20405 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
20406 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
20408 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
20409 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
20410 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
20411 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
20412 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
20413 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
20414 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
20415 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
20416 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
20417 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
20418 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
20419 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
20421 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
20422 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
20423 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
20424 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
20425 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
20426 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
20427 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
20428 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
20429 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
20430 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
20431 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
20432 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
20434 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
20435 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
20436 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
20437 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
20438 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
20439 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
20440 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
20441 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
20442 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
20443 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
20444 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
20445 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
20447 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
20448 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
20449 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
20450 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
20451 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
20452 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
20453 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
20454 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
20455 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
20456 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
20457 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
20458 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
20460 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
20461 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
20462 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
20463 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
20464 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
20465 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
20466 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
20467 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
20468 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
20469 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
20470 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
20471 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
20473 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
20474 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
20475 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
20476 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
20477 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
20478 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
20479 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
20480 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
20481 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
20482 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
20483 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
20484 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
20486 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
20487 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
20488 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
20489 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
20490 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
20491 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
20492 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
20493 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
20494 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
20495 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
20496 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
20497 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
20499 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20500 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20501 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20502 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20503 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20504 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20505 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20506 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20507 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20508 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20509 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20510 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20512 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20513 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20514 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20515 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20516 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20517 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20518 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20519 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20520 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20521 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20522 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20523 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20525 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20526 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20527 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20528 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20529 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20530 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20531 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20532 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20533 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20534 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20535 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20536 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20538 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20539 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20540 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20541 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20542 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20543 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20544 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20545 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20546 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20547 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20548 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20549 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20551 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20552 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20553 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20554 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20555 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20556 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20557 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20558 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20559 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20560 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20561 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20562 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20564 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20565 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20566 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20567 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20568 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20569 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20570 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20571 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20572 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20573 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20574 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20575 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20577 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20578 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20579 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20580 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20581 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20582 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20583 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20584 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20585 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20586 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20587 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20588 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20590 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20591 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20592 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20593 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20594 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20595 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20596 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20597 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20598 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20599 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20600 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20601 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20603 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20604 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20605 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20606 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20607 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20608 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20609 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20610 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20611 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20612 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20613 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20614 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20616 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20617 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20618 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20619 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20620 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20621 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20622 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20623 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20624 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20625 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20626 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20627 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20629 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20630 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20631 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20632 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20633 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20634 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20635 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20636 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20637 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20638 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20639 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20640 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20642 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20643 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20644 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20645 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20646 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20647 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20648 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20649 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20650 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20651 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20652 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20653 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20655 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20656 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20657 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20658 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20659 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20660 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20661 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20662 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20663 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20664 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20665 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20666 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20668 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20669 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20670 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20671 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20673 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20674 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20675 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20676 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20677 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20678 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20679 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20680 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20681 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20682 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20683 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20684 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20686 /* The implementation of the FIX instruction is broken on some
20687 assemblers, in that it accepts a precision specifier as well as a
20688 rounding specifier, despite the fact that this is meaningless.
20689 To be more compatible, we accept it as well, though of course it
20690 does not set any bits. */
20691 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20692 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20693 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20694 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20695 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20696 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20697 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20698 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20699 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20700 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20701 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20702 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20703 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20705 /* Instructions that were new with the real FPA, call them V2. */
20707 #define ARM_VARIANT & fpu_fpa_ext_v2
20709 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20710 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20711 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20712 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20713 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20714 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20717 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20719 /* Moves and type conversions. */
20720 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20721 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20722 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20723 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20724 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20725 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20726 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20727 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20728 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20729 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20730 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20731 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20732 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20733 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20735 /* Memory operations. */
20736 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20737 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20738 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20739 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20740 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20741 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20742 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20743 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20744 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20745 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20746 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20747 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20748 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20749 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20750 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20751 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20752 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20753 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20755 /* Monadic operations. */
20756 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20757 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20758 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20760 /* Dyadic operations. */
20761 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20762 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20763 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20764 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20765 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20766 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20767 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20768 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20769 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20772 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20773 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20774 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20775 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20777 /* Double precision load/store are still present on single precision
20778 implementations. */
20779 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20780 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20781 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20782 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20783 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20784 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20785 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20786 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20787 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20788 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20791 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20793 /* Moves and type conversions. */
20794 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20795 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20796 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20797 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20798 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20799 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20800 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20801 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20802 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20803 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20804 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20805 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20806 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20808 /* Monadic operations. */
20809 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20810 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20811 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20813 /* Dyadic operations. */
20814 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20815 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20816 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20817 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20818 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20819 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20820 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20821 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20822 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20825 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20826 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20827 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20828 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20831 #define ARM_VARIANT & fpu_vfp_ext_v2
20833 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20834 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20835 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20836 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20838 /* Instructions which may belong to either the Neon or VFP instruction sets.
20839 Individual encoder functions perform additional architecture checks. */
20841 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20842 #undef THUMB_VARIANT
20843 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20845 /* These mnemonics are unique to VFP. */
20846 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20847 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20848 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20849 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20850 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20851 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20852 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20853 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20854 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20855 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20857 /* Mnemonics shared by Neon and VFP. */
20858 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20859 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20860 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20862 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20863 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20865 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20866 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20868 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20869 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20870 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20871 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20872 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20873 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20874 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20875 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20877 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20878 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20879 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20880 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20883 /* NOTE: All VMOV encoding is special-cased! */
20884 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20885 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20888 #define ARM_VARIANT & arm_ext_fp16
20889 #undef THUMB_VARIANT
20890 #define THUMB_VARIANT & arm_ext_fp16
20891 /* New instructions added from v8.2, allowing the extraction and insertion of
20892 the upper 16 bits of a 32-bit vector register. */
20893 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20894 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20896 /* New backported fma/fms instructions optional in v8.2. */
20897 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
20898 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
20900 #undef THUMB_VARIANT
20901 #define THUMB_VARIANT & fpu_neon_ext_v1
20903 #define ARM_VARIANT & fpu_neon_ext_v1
20905 /* Data processing with three registers of the same length. */
20906 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20907 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20908 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20909 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20910 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20911 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20912 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20913 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20914 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20915 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20916 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20917 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20918 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20919 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20920 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20921 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20922 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20923 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20924 /* If not immediate, fall back to neon_dyadic_i64_su.
20925 shl_imm should accept I8 I16 I32 I64,
20926 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20927 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20928 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20929 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20930 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20931 /* Logic ops, types optional & ignored. */
20932 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20933 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20934 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20935 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20936 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20937 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20938 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20939 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20940 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20941 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20942 /* Bitfield ops, untyped. */
20943 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20944 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20945 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20946 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20947 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20948 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20949 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20950 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20951 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20952 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20953 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20954 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20955 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20956 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20957 back to neon_dyadic_if_su. */
20958 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20959 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20960 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20961 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20962 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20963 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20964 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20965 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20966 /* Comparison. Type I8 I16 I32 F32. */
20967 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20968 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20969 /* As above, D registers only. */
20970 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20971 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20972 /* Int and float variants, signedness unimportant. */
20973 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20974 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20975 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20976 /* Add/sub take types I8 I16 I32 I64 F32. */
20977 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20978 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20979 /* vtst takes sizes 8, 16, 32. */
20980 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20981 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20982 /* VMUL takes I8 I16 I32 F32 P8. */
20983 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20984 /* VQD{R}MULH takes S16 S32. */
20985 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20986 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20987 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20988 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20989 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20990 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20991 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20992 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20993 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20994 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20995 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20996 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20997 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20998 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20999 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
21000 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
21001 /* ARM v8.1 extension. */
21002 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
21003 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
21004 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
21005 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
21007 /* Two address, int/float. Types S8 S16 S32 F32. */
21008 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
21009 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
21011 /* Data processing with two registers and a shift amount. */
21012 /* Right shifts, and variants with rounding.
21013 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
21014 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
21015 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
21016 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
21017 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
21018 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
21019 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
21020 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
21021 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
21022 /* Shift and insert. Sizes accepted 8 16 32 64. */
21023 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
21024 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
21025 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
21026 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
21027 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
21028 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
21029 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
21030 /* Right shift immediate, saturating & narrowing, with rounding variants.
21031 Types accepted S16 S32 S64 U16 U32 U64. */
21032 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
21033 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
21034 /* As above, unsigned. Types accepted S16 S32 S64. */
21035 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
21036 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
21037 /* Right shift narrowing. Types accepted I16 I32 I64. */
21038 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
21039 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
21040 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
21041 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
21042 /* CVT with optional immediate for fixed-point variant. */
21043 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
21045 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
21046 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
21048 /* Data processing, three registers of different lengths. */
21049 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
21050 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
21051 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21052 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21053 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21054 /* If not scalar, fall back to neon_dyadic_long.
21055 Vector types as above, scalar types S16 S32 U16 U32. */
21056 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
21057 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
21058 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
21059 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
21060 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
21061 /* Dyadic, narrowing insns. Types I16 I32 I64. */
21062 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21063 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21064 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21065 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21066 /* Saturating doubling multiplies. Types S16 S32. */
21067 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21068 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21069 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21070 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
21071 S16 S32 U16 U32. */
21072 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
21074 /* Extract. Size 8. */
21075 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
21076 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
21078 /* Two registers, miscellaneous. */
21079 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
21080 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
21081 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
21082 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
21083 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
21084 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
21085 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
21086 /* Vector replicate. Sizes 8 16 32. */
21087 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
21088 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
21089 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
21090 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
21091 /* VMOVN. Types I16 I32 I64. */
21092 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
21093 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
21094 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
21095 /* VQMOVUN. Types S16 S32 S64. */
21096 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
21097 /* VZIP / VUZP. Sizes 8 16 32. */
21098 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21099 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21100 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21101 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21102 /* VQABS / VQNEG. Types S8 S16 S32. */
21103 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21104 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21105 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21106 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21107 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
21108 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21109 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
21110 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21111 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
21112 /* Reciprocal estimates. Types U32 F16 F32. */
21113 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21114 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
21115 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21116 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
21117 /* VCLS. Types S8 S16 S32. */
21118 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
21119 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
21120 /* VCLZ. Types I8 I16 I32. */
21121 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
21122 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
21123 /* VCNT. Size 8. */
21124 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
21125 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
21126 /* Two address, untyped. */
21127 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
21128 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
21129 /* VTRN. Sizes 8 16 32. */
21130 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
21131 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
21133 /* Table lookup. Size 8. */
21134 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21135 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21137 #undef THUMB_VARIANT
21138 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
21140 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
21142 /* Neon element/structure load/store. */
21143 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21144 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21145 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21146 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21147 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21148 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21149 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21150 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21152 #undef THUMB_VARIANT
21153 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
21155 #define ARM_VARIANT & fpu_vfp_ext_v3xd
21156 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
21157 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21158 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21159 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21160 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21161 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21162 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21163 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21164 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21166 #undef THUMB_VARIANT
21167 #define THUMB_VARIANT & fpu_vfp_ext_v3
21169 #define ARM_VARIANT & fpu_vfp_ext_v3
21171 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
21172 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21173 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21174 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21175 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21176 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21177 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21178 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21179 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21182 #define ARM_VARIANT & fpu_vfp_ext_fma
21183 #undef THUMB_VARIANT
21184 #define THUMB_VARIANT & fpu_vfp_ext_fma
21185 /* Mnemonics shared by Neon and VFP. These are included in the
21186 VFP FMA variant; NEON and VFP FMA always includes the NEON
21187 FMA instructions. */
21188 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21189 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21190 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
21191 the v form should always be used. */
21192 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21193 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21194 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21195 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21196 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21197 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21199 #undef THUMB_VARIANT
21201 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
21203 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21204 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21205 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21206 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21207 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21208 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21209 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
21210 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
21213 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
21215 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
21216 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
21217 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
21218 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
21219 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
21220 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
21221 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
21222 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
21223 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
21224 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21225 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21226 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21227 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21228 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21229 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21230 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21231 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21232 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21233 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
21234 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
21235 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21236 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21237 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21238 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21239 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21240 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21241 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
21242 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
21243 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
21244 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
21245 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
21246 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
21247 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
21248 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
21249 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21250 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21251 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21252 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21253 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21254 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21255 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21256 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21257 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21258 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21259 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21260 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21261 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
21262 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21263 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21264 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21265 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21266 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21267 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21268 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21269 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21270 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21271 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21272 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21273 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21274 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21275 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21276 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21277 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21278 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21279 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21280 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21281 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21282 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21283 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21284 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21285 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21286 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21287 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21288 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21289 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21290 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21291 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21292 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21293 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21294 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21295 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21296 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21297 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21298 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21299 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21300 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21301 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21302 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21303 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
21304 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21305 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21306 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21307 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21308 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21309 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21310 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21311 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21312 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21313 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21314 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21315 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21316 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21317 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21318 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21319 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21320 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21321 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21322 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21323 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21324 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21325 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
21326 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21327 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21328 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21329 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21330 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21331 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21332 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21333 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21334 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21335 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21336 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21337 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21338 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21339 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21340 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21341 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21342 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21343 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21344 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21345 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21346 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21347 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21348 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21349 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21350 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21351 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21352 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21353 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21354 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21355 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21356 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21357 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21358 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21359 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21360 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21361 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21362 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21363 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21364 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21365 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21366 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21367 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21368 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21369 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21370 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21371 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21372 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21373 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21374 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21375 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21376 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
21379 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
21381 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
21382 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
21383 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
21384 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21385 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21386 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21387 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21388 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21389 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21390 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21391 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21392 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21393 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21394 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21395 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21396 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21397 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21398 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21399 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21400 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21401 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
21402 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21403 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21404 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21405 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21406 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21407 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21408 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21409 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21410 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21411 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21412 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21413 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21414 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21415 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21416 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21417 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21418 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21419 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21420 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21421 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21422 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21423 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21424 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21425 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21426 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21427 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21428 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21429 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21430 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21431 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21432 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21433 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21434 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21435 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21436 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21437 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21440 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
21442 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21443 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21444 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21445 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21446 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21447 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21448 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21449 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21450 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
21451 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
21452 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
21453 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
21454 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
21455 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
21456 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
21457 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
21458 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
21459 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
21460 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
21461 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
21462 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
21463 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
21464 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
21465 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
21466 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
21467 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
21468 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
21469 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
21470 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
21471 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
21472 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
21473 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
21474 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
21475 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
21476 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
21477 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
21478 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
21479 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
21480 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
21481 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
21482 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
21483 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
21484 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
21485 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
21486 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
21487 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
21488 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
21489 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
21490 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
21491 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
21492 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
21493 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
21494 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
21495 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
21496 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21497 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21498 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21499 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21500 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21501 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21502 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
21503 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
21504 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
21505 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
21506 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21507 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21508 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21509 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21510 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21511 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21512 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21513 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21514 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21515 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21516 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21517 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21519 /* ARMv8-M instructions. */
21521 #define ARM_VARIANT NULL
21522 #undef THUMB_VARIANT
21523 #define THUMB_VARIANT & arm_ext_v8m
21524 ToU("sg", e97fe97f
, 0, (), noargs
),
21525 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
21526 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
21527 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
21528 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
21529 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
21530 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
21532 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21533 instructions behave as nop if no VFP is present. */
21534 #undef THUMB_VARIANT
21535 #define THUMB_VARIANT & arm_ext_v8m_main
21536 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
21537 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
21540 #undef THUMB_VARIANT
21566 /* MD interface: bits in the object file. */
21568 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21569 for use in the a.out file, and stores them in the array pointed to by buf.
21570 This knows about the endian-ness of the target machine and does
21571 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21572 2 (short) and 4 (long) Floating numbers are put out as a series of
21573 LITTLENUMS (shorts, here at least). */
21576 md_number_to_chars (char * buf
, valueT val
, int n
)
21578 if (target_big_endian
)
21579 number_to_chars_bigendian (buf
, val
, n
);
21581 number_to_chars_littleendian (buf
, val
, n
);
21585 md_chars_to_number (char * buf
, int n
)
21588 unsigned char * where
= (unsigned char *) buf
;
21590 if (target_big_endian
)
21595 result
|= (*where
++ & 255);
21603 result
|= (where
[n
] & 255);
21610 /* MD interface: Sections. */
21612 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21613 that an rs_machine_dependent frag may reach. */
21616 arm_frag_max_var (fragS
*fragp
)
21618 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21619 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21621 Note that we generate relaxable instructions even for cases that don't
21622 really need it, like an immediate that's a trivial constant. So we're
21623 overestimating the instruction size for some of those cases. Rather
21624 than putting more intelligence here, it would probably be better to
21625 avoid generating a relaxation frag in the first place when it can be
21626 determined up front that a short instruction will suffice. */
21628 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21632 /* Estimate the size of a frag before relaxing. Assume everything fits in
21636 md_estimate_size_before_relax (fragS
* fragp
,
21637 segT segtype ATTRIBUTE_UNUSED
)
21643 /* Convert a machine dependent frag. */
21646 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21648 unsigned long insn
;
21649 unsigned long old_op
;
21657 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21659 old_op
= bfd_get_16(abfd
, buf
);
21660 if (fragp
->fr_symbol
)
21662 exp
.X_op
= O_symbol
;
21663 exp
.X_add_symbol
= fragp
->fr_symbol
;
21667 exp
.X_op
= O_constant
;
21669 exp
.X_add_number
= fragp
->fr_offset
;
21670 opcode
= fragp
->fr_subtype
;
21673 case T_MNEM_ldr_pc
:
21674 case T_MNEM_ldr_pc2
:
21675 case T_MNEM_ldr_sp
:
21676 case T_MNEM_str_sp
:
21683 if (fragp
->fr_var
== 4)
21685 insn
= THUMB_OP32 (opcode
);
21686 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21688 insn
|= (old_op
& 0x700) << 4;
21692 insn
|= (old_op
& 7) << 12;
21693 insn
|= (old_op
& 0x38) << 13;
21695 insn
|= 0x00000c00;
21696 put_thumb32_insn (buf
, insn
);
21697 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21701 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21703 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21706 if (fragp
->fr_var
== 4)
21708 insn
= THUMB_OP32 (opcode
);
21709 insn
|= (old_op
& 0xf0) << 4;
21710 put_thumb32_insn (buf
, insn
);
21711 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21715 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21716 exp
.X_add_number
-= 4;
21724 if (fragp
->fr_var
== 4)
21726 int r0off
= (opcode
== T_MNEM_mov
21727 || opcode
== T_MNEM_movs
) ? 0 : 8;
21728 insn
= THUMB_OP32 (opcode
);
21729 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21730 insn
|= (old_op
& 0x700) << r0off
;
21731 put_thumb32_insn (buf
, insn
);
21732 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21736 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21741 if (fragp
->fr_var
== 4)
21743 insn
= THUMB_OP32(opcode
);
21744 put_thumb32_insn (buf
, insn
);
21745 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21748 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21752 if (fragp
->fr_var
== 4)
21754 insn
= THUMB_OP32(opcode
);
21755 insn
|= (old_op
& 0xf00) << 14;
21756 put_thumb32_insn (buf
, insn
);
21757 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21760 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21763 case T_MNEM_add_sp
:
21764 case T_MNEM_add_pc
:
21765 case T_MNEM_inc_sp
:
21766 case T_MNEM_dec_sp
:
21767 if (fragp
->fr_var
== 4)
21769 /* ??? Choose between add and addw. */
21770 insn
= THUMB_OP32 (opcode
);
21771 insn
|= (old_op
& 0xf0) << 4;
21772 put_thumb32_insn (buf
, insn
);
21773 if (opcode
== T_MNEM_add_pc
)
21774 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21776 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21779 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21787 if (fragp
->fr_var
== 4)
21789 insn
= THUMB_OP32 (opcode
);
21790 insn
|= (old_op
& 0xf0) << 4;
21791 insn
|= (old_op
& 0xf) << 16;
21792 put_thumb32_insn (buf
, insn
);
21793 if (insn
& (1 << 20))
21794 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21796 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21799 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21805 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21806 (enum bfd_reloc_code_real
) reloc_type
);
21807 fixp
->fx_file
= fragp
->fr_file
;
21808 fixp
->fx_line
= fragp
->fr_line
;
21809 fragp
->fr_fix
+= fragp
->fr_var
;
21811 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21812 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21813 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21814 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21817 /* Return the size of a relaxable immediate operand instruction.
21818 SHIFT and SIZE specify the form of the allowable immediate. */
21820 relax_immediate (fragS
*fragp
, int size
, int shift
)
21826 /* ??? Should be able to do better than this. */
21827 if (fragp
->fr_symbol
)
21830 low
= (1 << shift
) - 1;
21831 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21832 offset
= fragp
->fr_offset
;
21833 /* Force misaligned offsets to 32-bit variant. */
21836 if (offset
& ~mask
)
21841 /* Get the address of a symbol during relaxation. */
21843 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21849 sym
= fragp
->fr_symbol
;
21850 sym_frag
= symbol_get_frag (sym
);
21851 know (S_GET_SEGMENT (sym
) != absolute_section
21852 || sym_frag
== &zero_address_frag
);
21853 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21855 /* If frag has yet to be reached on this pass, assume it will
21856 move by STRETCH just as we did. If this is not so, it will
21857 be because some frag between grows, and that will force
21861 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21865 /* Adjust stretch for any alignment frag. Note that if have
21866 been expanding the earlier code, the symbol may be
21867 defined in what appears to be an earlier frag. FIXME:
21868 This doesn't handle the fr_subtype field, which specifies
21869 a maximum number of bytes to skip when doing an
21871 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21873 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21876 stretch
= - ((- stretch
)
21877 & ~ ((1 << (int) f
->fr_offset
) - 1));
21879 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21891 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21894 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21899 /* Assume worst case for symbols not known to be in the same section. */
21900 if (fragp
->fr_symbol
== NULL
21901 || !S_IS_DEFINED (fragp
->fr_symbol
)
21902 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21903 || S_IS_WEAK (fragp
->fr_symbol
))
21906 val
= relaxed_symbol_addr (fragp
, stretch
);
21907 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21908 addr
= (addr
+ 4) & ~3;
21909 /* Force misaligned targets to 32-bit variant. */
21913 if (val
< 0 || val
> 1020)
21918 /* Return the size of a relaxable add/sub immediate instruction. */
21920 relax_addsub (fragS
*fragp
, asection
*sec
)
21925 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21926 op
= bfd_get_16(sec
->owner
, buf
);
21927 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21928 return relax_immediate (fragp
, 8, 0);
21930 return relax_immediate (fragp
, 3, 0);
21933 /* Return TRUE iff the definition of symbol S could be pre-empted
21934 (overridden) at link or load time. */
21936 symbol_preemptible (symbolS
*s
)
21938 /* Weak symbols can always be pre-empted. */
21942 /* Non-global symbols cannot be pre-empted. */
21943 if (! S_IS_EXTERNAL (s
))
21947 /* In ELF, a global symbol can be marked protected, or private. In that
21948 case it can't be pre-empted (other definitions in the same link unit
21949 would violate the ODR). */
21950 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21954 /* Other global symbols might be pre-empted. */
21958 /* Return the size of a relaxable branch instruction. BITS is the
21959 size of the offset field in the narrow instruction. */
21962 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21968 /* Assume worst case for symbols not known to be in the same section. */
21969 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21970 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21971 || S_IS_WEAK (fragp
->fr_symbol
))
21975 /* A branch to a function in ARM state will require interworking. */
21976 if (S_IS_DEFINED (fragp
->fr_symbol
)
21977 && ARM_IS_FUNC (fragp
->fr_symbol
))
21981 if (symbol_preemptible (fragp
->fr_symbol
))
21984 val
= relaxed_symbol_addr (fragp
, stretch
);
21985 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21988 /* Offset is a signed value *2 */
21990 if (val
>= limit
|| val
< -limit
)
21996 /* Relax a machine dependent frag. This returns the amount by which
21997 the current size of the frag should change. */
22000 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
22005 oldsize
= fragp
->fr_var
;
22006 switch (fragp
->fr_subtype
)
22008 case T_MNEM_ldr_pc2
:
22009 newsize
= relax_adr (fragp
, sec
, stretch
);
22011 case T_MNEM_ldr_pc
:
22012 case T_MNEM_ldr_sp
:
22013 case T_MNEM_str_sp
:
22014 newsize
= relax_immediate (fragp
, 8, 2);
22018 newsize
= relax_immediate (fragp
, 5, 2);
22022 newsize
= relax_immediate (fragp
, 5, 1);
22026 newsize
= relax_immediate (fragp
, 5, 0);
22029 newsize
= relax_adr (fragp
, sec
, stretch
);
22035 newsize
= relax_immediate (fragp
, 8, 0);
22038 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
22041 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
22043 case T_MNEM_add_sp
:
22044 case T_MNEM_add_pc
:
22045 newsize
= relax_immediate (fragp
, 8, 2);
22047 case T_MNEM_inc_sp
:
22048 case T_MNEM_dec_sp
:
22049 newsize
= relax_immediate (fragp
, 7, 2);
22055 newsize
= relax_addsub (fragp
, sec
);
22061 fragp
->fr_var
= newsize
;
22062 /* Freeze wide instructions that are at or before the same location as
22063 in the previous pass. This avoids infinite loops.
22064 Don't freeze them unconditionally because targets may be artificially
22065 misaligned by the expansion of preceding frags. */
22066 if (stretch
<= 0 && newsize
> 2)
22068 md_convert_frag (sec
->owner
, sec
, fragp
);
22072 return newsize
- oldsize
;
22075 /* Round up a section size to the appropriate boundary. */
22078 md_section_align (segT segment ATTRIBUTE_UNUSED
,
22084 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
22085 of an rs_align_code fragment. */
22088 arm_handle_align (fragS
* fragP
)
22090 static unsigned char const arm_noop
[2][2][4] =
22093 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
22094 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
22097 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
22098 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
22101 static unsigned char const thumb_noop
[2][2][2] =
22104 {0xc0, 0x46}, /* LE */
22105 {0x46, 0xc0}, /* BE */
22108 {0x00, 0xbf}, /* LE */
22109 {0xbf, 0x00} /* BE */
22112 static unsigned char const wide_thumb_noop
[2][4] =
22113 { /* Wide Thumb-2 */
22114 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
22115 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
22118 unsigned bytes
, fix
, noop_size
;
22120 const unsigned char * noop
;
22121 const unsigned char *narrow_noop
= NULL
;
22126 if (fragP
->fr_type
!= rs_align_code
)
22129 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
22130 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
22133 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22134 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
22136 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
22138 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
22140 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22141 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
22143 narrow_noop
= thumb_noop
[1][target_big_endian
];
22144 noop
= wide_thumb_noop
[target_big_endian
];
22147 noop
= thumb_noop
[0][target_big_endian
];
22155 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22156 ? selected_cpu
: arm_arch_none
,
22158 [target_big_endian
];
22165 fragP
->fr_var
= noop_size
;
22167 if (bytes
& (noop_size
- 1))
22169 fix
= bytes
& (noop_size
- 1);
22171 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
22173 memset (p
, 0, fix
);
22180 if (bytes
& noop_size
)
22182 /* Insert a narrow noop. */
22183 memcpy (p
, narrow_noop
, noop_size
);
22185 bytes
-= noop_size
;
22189 /* Use wide noops for the remainder */
22193 while (bytes
>= noop_size
)
22195 memcpy (p
, noop
, noop_size
);
22197 bytes
-= noop_size
;
22201 fragP
->fr_fix
+= fix
;
22204 /* Called from md_do_align. Used to create an alignment
22205 frag in a code section. */
22208 arm_frag_align_code (int n
, int max
)
22212 /* We assume that there will never be a requirement
22213 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
22214 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22219 _("alignments greater than %d bytes not supported in .text sections."),
22220 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
22221 as_fatal ("%s", err_msg
);
22224 p
= frag_var (rs_align_code
,
22225 MAX_MEM_FOR_RS_ALIGN_CODE
,
22227 (relax_substateT
) max
,
22234 /* Perform target specific initialisation of a frag.
22235 Note - despite the name this initialisation is not done when the frag
22236 is created, but only when its type is assigned. A frag can be created
22237 and used a long time before its type is set, so beware of assuming that
22238 this initialisation is performed first. */
22242 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
22244 /* Record whether this frag is in an ARM or a THUMB area. */
22245 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22248 #else /* OBJ_ELF is defined. */
22250 arm_init_frag (fragS
* fragP
, int max_chars
)
22252 bfd_boolean frag_thumb_mode
;
22254 /* If the current ARM vs THUMB mode has not already
22255 been recorded into this frag then do so now. */
22256 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
22257 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22259 /* PR 21809: Do not set a mapping state for debug sections
22260 - it just confuses other tools. */
22261 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
22264 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
22266 /* Record a mapping symbol for alignment frags. We will delete this
22267 later if the alignment ends up empty. */
22268 switch (fragP
->fr_type
)
22271 case rs_align_test
:
22273 mapping_state_2 (MAP_DATA
, max_chars
);
22275 case rs_align_code
:
22276 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
22283 /* When we change sections we need to issue a new mapping symbol. */
22286 arm_elf_change_section (void)
22288 /* Link an unlinked unwind index table section to the .text section. */
22289 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
22290 && elf_linked_to_section (now_seg
) == NULL
)
22291 elf_linked_to_section (now_seg
) = text_section
;
22295 arm_elf_section_type (const char * str
, size_t len
)
22297 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
22298 return SHT_ARM_EXIDX
;
22303 /* Code to deal with unwinding tables. */
22305 static void add_unwind_adjustsp (offsetT
);
22307 /* Generate any deferred unwind frame offset. */
22310 flush_pending_unwind (void)
22314 offset
= unwind
.pending_offset
;
22315 unwind
.pending_offset
= 0;
22317 add_unwind_adjustsp (offset
);
22320 /* Add an opcode to this list for this function. Two-byte opcodes should
22321 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
22325 add_unwind_opcode (valueT op
, int length
)
22327 /* Add any deferred stack adjustment. */
22328 if (unwind
.pending_offset
)
22329 flush_pending_unwind ();
22331 unwind
.sp_restored
= 0;
22333 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
22335 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
22336 if (unwind
.opcodes
)
22337 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
22338 unwind
.opcode_alloc
);
22340 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
22345 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
22347 unwind
.opcode_count
++;
22351 /* Add unwind opcodes to adjust the stack pointer. */
22354 add_unwind_adjustsp (offsetT offset
)
22358 if (offset
> 0x200)
22360 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
22365 /* Long form: 0xb2, uleb128. */
22366 /* This might not fit in a word so add the individual bytes,
22367 remembering the list is built in reverse order. */
22368 o
= (valueT
) ((offset
- 0x204) >> 2);
22370 add_unwind_opcode (0, 1);
22372 /* Calculate the uleb128 encoding of the offset. */
22376 bytes
[n
] = o
& 0x7f;
22382 /* Add the insn. */
22384 add_unwind_opcode (bytes
[n
- 1], 1);
22385 add_unwind_opcode (0xb2, 1);
22387 else if (offset
> 0x100)
22389 /* Two short opcodes. */
22390 add_unwind_opcode (0x3f, 1);
22391 op
= (offset
- 0x104) >> 2;
22392 add_unwind_opcode (op
, 1);
22394 else if (offset
> 0)
22396 /* Short opcode. */
22397 op
= (offset
- 4) >> 2;
22398 add_unwind_opcode (op
, 1);
22400 else if (offset
< 0)
22403 while (offset
> 0x100)
22405 add_unwind_opcode (0x7f, 1);
22408 op
= ((offset
- 4) >> 2) | 0x40;
22409 add_unwind_opcode (op
, 1);
22413 /* Finish the list of unwind opcodes for this function. */
22416 finish_unwind_opcodes (void)
22420 if (unwind
.fp_used
)
22422 /* Adjust sp as necessary. */
22423 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
22424 flush_pending_unwind ();
22426 /* After restoring sp from the frame pointer. */
22427 op
= 0x90 | unwind
.fp_reg
;
22428 add_unwind_opcode (op
, 1);
22431 flush_pending_unwind ();
22435 /* Start an exception table entry. If idx is nonzero this is an index table
22439 start_unwind_section (const segT text_seg
, int idx
)
22441 const char * text_name
;
22442 const char * prefix
;
22443 const char * prefix_once
;
22444 const char * group_name
;
22452 prefix
= ELF_STRING_ARM_unwind
;
22453 prefix_once
= ELF_STRING_ARM_unwind_once
;
22454 type
= SHT_ARM_EXIDX
;
22458 prefix
= ELF_STRING_ARM_unwind_info
;
22459 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
22460 type
= SHT_PROGBITS
;
22463 text_name
= segment_name (text_seg
);
22464 if (streq (text_name
, ".text"))
22467 if (strncmp (text_name
, ".gnu.linkonce.t.",
22468 strlen (".gnu.linkonce.t.")) == 0)
22470 prefix
= prefix_once
;
22471 text_name
+= strlen (".gnu.linkonce.t.");
22474 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
22480 /* Handle COMDAT group. */
22481 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
22483 group_name
= elf_group_name (text_seg
);
22484 if (group_name
== NULL
)
22486 as_bad (_("Group section `%s' has no group signature"),
22487 segment_name (text_seg
));
22488 ignore_rest_of_line ();
22491 flags
|= SHF_GROUP
;
22495 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
22498 /* Set the section link for index tables. */
22500 elf_linked_to_section (now_seg
) = text_seg
;
22504 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22505 personality routine data. Returns zero, or the index table value for
22506 an inline entry. */
22509 create_unwind_entry (int have_data
)
22514 /* The current word of data. */
22516 /* The number of bytes left in this word. */
22519 finish_unwind_opcodes ();
22521 /* Remember the current text section. */
22522 unwind
.saved_seg
= now_seg
;
22523 unwind
.saved_subseg
= now_subseg
;
22525 start_unwind_section (now_seg
, 0);
22527 if (unwind
.personality_routine
== NULL
)
22529 if (unwind
.personality_index
== -2)
22532 as_bad (_("handlerdata in cantunwind frame"));
22533 return 1; /* EXIDX_CANTUNWIND. */
22536 /* Use a default personality routine if none is specified. */
22537 if (unwind
.personality_index
== -1)
22539 if (unwind
.opcode_count
> 3)
22540 unwind
.personality_index
= 1;
22542 unwind
.personality_index
= 0;
22545 /* Space for the personality routine entry. */
22546 if (unwind
.personality_index
== 0)
22548 if (unwind
.opcode_count
> 3)
22549 as_bad (_("too many unwind opcodes for personality routine 0"));
22553 /* All the data is inline in the index table. */
22556 while (unwind
.opcode_count
> 0)
22558 unwind
.opcode_count
--;
22559 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22563 /* Pad with "finish" opcodes. */
22565 data
= (data
<< 8) | 0xb0;
22572 /* We get two opcodes "free" in the first word. */
22573 size
= unwind
.opcode_count
- 2;
22577 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22578 if (unwind
.personality_index
!= -1)
22580 as_bad (_("attempt to recreate an unwind entry"));
22584 /* An extra byte is required for the opcode count. */
22585 size
= unwind
.opcode_count
+ 1;
22588 size
= (size
+ 3) >> 2;
22590 as_bad (_("too many unwind opcodes"));
22592 frag_align (2, 0, 0);
22593 record_alignment (now_seg
, 2);
22594 unwind
.table_entry
= expr_build_dot ();
22596 /* Allocate the table entry. */
22597 ptr
= frag_more ((size
<< 2) + 4);
22598 /* PR 13449: Zero the table entries in case some of them are not used. */
22599 memset (ptr
, 0, (size
<< 2) + 4);
22600 where
= frag_now_fix () - ((size
<< 2) + 4);
22602 switch (unwind
.personality_index
)
22605 /* ??? Should this be a PLT generating relocation? */
22606 /* Custom personality routine. */
22607 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22608 BFD_RELOC_ARM_PREL31
);
22613 /* Set the first byte to the number of additional words. */
22614 data
= size
> 0 ? size
- 1 : 0;
22618 /* ABI defined personality routines. */
22620 /* Three opcodes bytes are packed into the first word. */
22627 /* The size and first two opcode bytes go in the first word. */
22628 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22633 /* Should never happen. */
22637 /* Pack the opcodes into words (MSB first), reversing the list at the same
22639 while (unwind
.opcode_count
> 0)
22643 md_number_to_chars (ptr
, data
, 4);
22648 unwind
.opcode_count
--;
22650 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22653 /* Finish off the last word. */
22656 /* Pad with "finish" opcodes. */
22658 data
= (data
<< 8) | 0xb0;
22660 md_number_to_chars (ptr
, data
, 4);
22665 /* Add an empty descriptor if there is no user-specified data. */
22666 ptr
= frag_more (4);
22667 md_number_to_chars (ptr
, 0, 4);
22674 /* Initialize the DWARF-2 unwind information for this procedure. */
22677 tc_arm_frame_initial_instructions (void)
22679 cfi_add_CFA_def_cfa (REG_SP
, 0);
22681 #endif /* OBJ_ELF */
22683 /* Convert REGNAME to a DWARF-2 register number. */
22686 tc_arm_regname_to_dw2regnum (char *regname
)
22688 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22692 /* PR 16694: Allow VFP registers as well. */
22693 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22697 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22706 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22710 exp
.X_op
= O_secrel
;
22711 exp
.X_add_symbol
= symbol
;
22712 exp
.X_add_number
= 0;
22713 emit_expr (&exp
, size
);
22717 /* MD interface: Symbol and relocation handling. */
22719 /* Return the address within the segment that a PC-relative fixup is
22720 relative to. For ARM, PC-relative fixups applied to instructions
22721 are generally relative to the location of the fixup plus 8 bytes.
22722 Thumb branches are offset by 4, and Thumb loads relative to PC
22723 require special handling. */
22726 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22728 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22730 /* If this is pc-relative and we are going to emit a relocation
22731 then we just want to put out any pipeline compensation that the linker
22732 will need. Otherwise we want to use the calculated base.
22733 For WinCE we skip the bias for externals as well, since this
22734 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22736 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22737 || (arm_force_relocation (fixP
)
22739 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22745 switch (fixP
->fx_r_type
)
22747 /* PC relative addressing on the Thumb is slightly odd as the
22748 bottom two bits of the PC are forced to zero for the
22749 calculation. This happens *after* application of the
22750 pipeline offset. However, Thumb adrl already adjusts for
22751 this, so we need not do it again. */
22752 case BFD_RELOC_ARM_THUMB_ADD
:
22755 case BFD_RELOC_ARM_THUMB_OFFSET
:
22756 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22757 case BFD_RELOC_ARM_T32_ADD_PC12
:
22758 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22759 return (base
+ 4) & ~3;
22761 /* Thumb branches are simply offset by +4. */
22762 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22763 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22764 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22765 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22766 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22769 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22771 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22772 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22773 && ARM_IS_FUNC (fixP
->fx_addsy
)
22774 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22775 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22778 /* BLX is like branches above, but forces the low two bits of PC to
22780 case BFD_RELOC_THUMB_PCREL_BLX
:
22782 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22783 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22784 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22785 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22786 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22787 return (base
+ 4) & ~3;
22789 /* ARM mode branches are offset by +8. However, the Windows CE
22790 loader expects the relocation not to take this into account. */
22791 case BFD_RELOC_ARM_PCREL_BLX
:
22793 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22794 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22795 && ARM_IS_FUNC (fixP
->fx_addsy
)
22796 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22797 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22800 case BFD_RELOC_ARM_PCREL_CALL
:
22802 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22803 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22804 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22805 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22806 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22809 case BFD_RELOC_ARM_PCREL_BRANCH
:
22810 case BFD_RELOC_ARM_PCREL_JUMP
:
22811 case BFD_RELOC_ARM_PLT32
:
22813 /* When handling fixups immediately, because we have already
22814 discovered the value of a symbol, or the address of the frag involved
22815 we must account for the offset by +8, as the OS loader will never see the reloc.
22816 see fixup_segment() in write.c
22817 The S_IS_EXTERNAL test handles the case of global symbols.
22818 Those need the calculated base, not just the pipe compensation the linker will need. */
22820 && fixP
->fx_addsy
!= NULL
22821 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22822 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22830 /* ARM mode loads relative to PC are also offset by +8. Unlike
22831 branches, the Windows CE loader *does* expect the relocation
22832 to take this into account. */
22833 case BFD_RELOC_ARM_OFFSET_IMM
:
22834 case BFD_RELOC_ARM_OFFSET_IMM8
:
22835 case BFD_RELOC_ARM_HWLITERAL
:
22836 case BFD_RELOC_ARM_LITERAL
:
22837 case BFD_RELOC_ARM_CP_OFF_IMM
:
22841 /* Other PC-relative relocations are un-offset. */
22847 static bfd_boolean flag_warn_syms
= TRUE
;
22850 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22852 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22853 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22854 does mean that the resulting code might be very confusing to the reader.
22855 Also this warning can be triggered if the user omits an operand before
22856 an immediate address, eg:
22860 GAS treats this as an assignment of the value of the symbol foo to a
22861 symbol LDR, and so (without this code) it will not issue any kind of
22862 warning or error message.
22864 Note - ARM instructions are case-insensitive but the strings in the hash
22865 table are all stored in lower case, so we must first ensure that name is
22867 if (flag_warn_syms
&& arm_ops_hsh
)
22869 char * nbuf
= strdup (name
);
22872 for (p
= nbuf
; *p
; p
++)
22874 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22876 static struct hash_control
* already_warned
= NULL
;
22878 if (already_warned
== NULL
)
22879 already_warned
= hash_new ();
22880 /* Only warn about the symbol once. To keep the code
22881 simple we let hash_insert do the lookup for us. */
22882 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22883 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22892 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22893 Otherwise we have no need to default values of symbols. */
22896 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22899 if (name
[0] == '_' && name
[1] == 'G'
22900 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22904 if (symbol_find (name
))
22905 as_bad (_("GOT already in the symbol table"));
22907 GOT_symbol
= symbol_new (name
, undefined_section
,
22908 (valueT
) 0, & zero_address_frag
);
22918 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22919 computed as two separate immediate values, added together. We
22920 already know that this value cannot be computed by just one ARM
22923 static unsigned int
22924 validate_immediate_twopart (unsigned int val
,
22925 unsigned int * highpart
)
22930 for (i
= 0; i
< 32; i
+= 2)
22931 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22937 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22939 else if (a
& 0xff0000)
22941 if (a
& 0xff000000)
22943 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22947 gas_assert (a
& 0xff000000);
22948 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22951 return (a
& 0xff) | (i
<< 7);
22958 validate_offset_imm (unsigned int val
, int hwse
)
22960 if ((hwse
&& val
> 255) || val
> 4095)
22965 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22966 negative immediate constant by altering the instruction. A bit of
22971 by inverting the second operand, and
22974 by negating the second operand. */
22977 negate_data_op (unsigned long * instruction
,
22978 unsigned long value
)
22981 unsigned long negated
, inverted
;
22983 negated
= encode_arm_immediate (-value
);
22984 inverted
= encode_arm_immediate (~value
);
22986 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22989 /* First negates. */
22990 case OPCODE_SUB
: /* ADD <-> SUB */
22991 new_inst
= OPCODE_ADD
;
22996 new_inst
= OPCODE_SUB
;
23000 case OPCODE_CMP
: /* CMP <-> CMN */
23001 new_inst
= OPCODE_CMN
;
23006 new_inst
= OPCODE_CMP
;
23010 /* Now Inverted ops. */
23011 case OPCODE_MOV
: /* MOV <-> MVN */
23012 new_inst
= OPCODE_MVN
;
23017 new_inst
= OPCODE_MOV
;
23021 case OPCODE_AND
: /* AND <-> BIC */
23022 new_inst
= OPCODE_BIC
;
23027 new_inst
= OPCODE_AND
;
23031 case OPCODE_ADC
: /* ADC <-> SBC */
23032 new_inst
= OPCODE_SBC
;
23037 new_inst
= OPCODE_ADC
;
23041 /* We cannot do anything. */
23046 if (value
== (unsigned) FAIL
)
23049 *instruction
&= OPCODE_MASK
;
23050 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
23054 /* Like negate_data_op, but for Thumb-2. */
23056 static unsigned int
23057 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
23061 unsigned int negated
, inverted
;
23063 negated
= encode_thumb32_immediate (-value
);
23064 inverted
= encode_thumb32_immediate (~value
);
23066 rd
= (*instruction
>> 8) & 0xf;
23067 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
23070 /* ADD <-> SUB. Includes CMP <-> CMN. */
23071 case T2_OPCODE_SUB
:
23072 new_inst
= T2_OPCODE_ADD
;
23076 case T2_OPCODE_ADD
:
23077 new_inst
= T2_OPCODE_SUB
;
23081 /* ORR <-> ORN. Includes MOV <-> MVN. */
23082 case T2_OPCODE_ORR
:
23083 new_inst
= T2_OPCODE_ORN
;
23087 case T2_OPCODE_ORN
:
23088 new_inst
= T2_OPCODE_ORR
;
23092 /* AND <-> BIC. TST has no inverted equivalent. */
23093 case T2_OPCODE_AND
:
23094 new_inst
= T2_OPCODE_BIC
;
23101 case T2_OPCODE_BIC
:
23102 new_inst
= T2_OPCODE_AND
;
23107 case T2_OPCODE_ADC
:
23108 new_inst
= T2_OPCODE_SBC
;
23112 case T2_OPCODE_SBC
:
23113 new_inst
= T2_OPCODE_ADC
;
23117 /* We cannot do anything. */
23122 if (value
== (unsigned int)FAIL
)
23125 *instruction
&= T2_OPCODE_MASK
;
23126 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
23130 /* Read a 32-bit thumb instruction from buf. */
23132 static unsigned long
23133 get_thumb32_insn (char * buf
)
23135 unsigned long insn
;
23136 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
23137 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23142 /* We usually want to set the low bit on the address of thumb function
23143 symbols. In particular .word foo - . should have the low bit set.
23144 Generic code tries to fold the difference of two symbols to
23145 a constant. Prevent this and force a relocation when the first symbols
23146 is a thumb function. */
23149 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
23151 if (op
== O_subtract
23152 && l
->X_op
== O_symbol
23153 && r
->X_op
== O_symbol
23154 && THUMB_IS_FUNC (l
->X_add_symbol
))
23156 l
->X_op
= O_subtract
;
23157 l
->X_op_symbol
= r
->X_add_symbol
;
23158 l
->X_add_number
-= r
->X_add_number
;
23162 /* Process as normal. */
23166 /* Encode Thumb2 unconditional branches and calls. The encoding
23167 for the 2 are identical for the immediate values. */
23170 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
23172 #define T2I1I2MASK ((1 << 13) | (1 << 11))
23175 addressT S
, I1
, I2
, lo
, hi
;
23177 S
= (value
>> 24) & 0x01;
23178 I1
= (value
>> 23) & 0x01;
23179 I2
= (value
>> 22) & 0x01;
23180 hi
= (value
>> 12) & 0x3ff;
23181 lo
= (value
>> 1) & 0x7ff;
23182 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23183 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23184 newval
|= (S
<< 10) | hi
;
23185 newval2
&= ~T2I1I2MASK
;
23186 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
23187 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23188 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23192 md_apply_fix (fixS
* fixP
,
23196 offsetT value
= * valP
;
23198 unsigned int newimm
;
23199 unsigned long temp
;
23201 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
23203 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
23205 /* Note whether this will delete the relocation. */
23207 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
23210 /* On a 64-bit host, silently truncate 'value' to 32 bits for
23211 consistency with the behaviour on 32-bit hosts. Remember value
23213 value
&= 0xffffffff;
23214 value
^= 0x80000000;
23215 value
-= 0x80000000;
23218 fixP
->fx_addnumber
= value
;
23220 /* Same treatment for fixP->fx_offset. */
23221 fixP
->fx_offset
&= 0xffffffff;
23222 fixP
->fx_offset
^= 0x80000000;
23223 fixP
->fx_offset
-= 0x80000000;
23225 switch (fixP
->fx_r_type
)
23227 case BFD_RELOC_NONE
:
23228 /* This will need to go in the object file. */
23232 case BFD_RELOC_ARM_IMMEDIATE
:
23233 /* We claim that this fixup has been processed here,
23234 even if in fact we generate an error because we do
23235 not have a reloc for it, so tc_gen_reloc will reject it. */
23238 if (fixP
->fx_addsy
)
23240 const char *msg
= 0;
23242 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23243 msg
= _("undefined symbol %s used as an immediate value");
23244 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23245 msg
= _("symbol %s is in a different section");
23246 else if (S_IS_WEAK (fixP
->fx_addsy
))
23247 msg
= _("symbol %s is weak and may be overridden later");
23251 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23252 msg
, S_GET_NAME (fixP
->fx_addsy
));
23257 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23259 /* If the offset is negative, we should use encoding A2 for ADR. */
23260 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
23261 newimm
= negate_data_op (&temp
, value
);
23264 newimm
= encode_arm_immediate (value
);
23266 /* If the instruction will fail, see if we can fix things up by
23267 changing the opcode. */
23268 if (newimm
== (unsigned int) FAIL
)
23269 newimm
= negate_data_op (&temp
, value
);
23270 /* MOV accepts both ARM modified immediate (A1 encoding) and
23271 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
23272 When disassembling, MOV is preferred when there is no encoding
23274 if (newimm
== (unsigned int) FAIL
23275 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
23276 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
23277 && !((temp
>> SBIT_SHIFT
) & 0x1)
23278 && value
>= 0 && value
<= 0xffff)
23280 /* Clear bits[23:20] to change encoding from A1 to A2. */
23281 temp
&= 0xff0fffff;
23282 /* Encoding high 4bits imm. Code below will encode the remaining
23284 temp
|= (value
& 0x0000f000) << 4;
23285 newimm
= value
& 0x00000fff;
23289 if (newimm
== (unsigned int) FAIL
)
23291 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23292 _("invalid constant (%lx) after fixup"),
23293 (unsigned long) value
);
23297 newimm
|= (temp
& 0xfffff000);
23298 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23301 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23303 unsigned int highpart
= 0;
23304 unsigned int newinsn
= 0xe1a00000; /* nop. */
23306 if (fixP
->fx_addsy
)
23308 const char *msg
= 0;
23310 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23311 msg
= _("undefined symbol %s used as an immediate value");
23312 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23313 msg
= _("symbol %s is in a different section");
23314 else if (S_IS_WEAK (fixP
->fx_addsy
))
23315 msg
= _("symbol %s is weak and may be overridden later");
23319 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23320 msg
, S_GET_NAME (fixP
->fx_addsy
));
23325 newimm
= encode_arm_immediate (value
);
23326 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23328 /* If the instruction will fail, see if we can fix things up by
23329 changing the opcode. */
23330 if (newimm
== (unsigned int) FAIL
23331 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
23333 /* No ? OK - try using two ADD instructions to generate
23335 newimm
= validate_immediate_twopart (value
, & highpart
);
23337 /* Yes - then make sure that the second instruction is
23339 if (newimm
!= (unsigned int) FAIL
)
23341 /* Still No ? Try using a negated value. */
23342 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
23343 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
23344 /* Otherwise - give up. */
23347 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23348 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
23353 /* Replace the first operand in the 2nd instruction (which
23354 is the PC) with the destination register. We have
23355 already added in the PC in the first instruction and we
23356 do not want to do it again. */
23357 newinsn
&= ~ 0xf0000;
23358 newinsn
|= ((newinsn
& 0x0f000) << 4);
23361 newimm
|= (temp
& 0xfffff000);
23362 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23364 highpart
|= (newinsn
& 0xfffff000);
23365 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
23369 case BFD_RELOC_ARM_OFFSET_IMM
:
23370 if (!fixP
->fx_done
&& seg
->use_rela_p
)
23372 /* Fall through. */
23374 case BFD_RELOC_ARM_LITERAL
:
23380 if (validate_offset_imm (value
, 0) == FAIL
)
23382 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
23383 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23384 _("invalid literal constant: pool needs to be closer"));
23386 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23387 _("bad immediate value for offset (%ld)"),
23392 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23394 newval
&= 0xfffff000;
23397 newval
&= 0xff7ff000;
23398 newval
|= value
| (sign
? INDEX_UP
: 0);
23400 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23403 case BFD_RELOC_ARM_OFFSET_IMM8
:
23404 case BFD_RELOC_ARM_HWLITERAL
:
23410 if (validate_offset_imm (value
, 1) == FAIL
)
23412 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
23413 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23414 _("invalid literal constant: pool needs to be closer"));
23416 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23417 _("bad immediate value for 8-bit offset (%ld)"),
23422 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23424 newval
&= 0xfffff0f0;
23427 newval
&= 0xff7ff0f0;
23428 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
23430 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23433 case BFD_RELOC_ARM_T32_OFFSET_U8
:
23434 if (value
< 0 || value
> 1020 || value
% 4 != 0)
23435 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23436 _("bad immediate value for offset (%ld)"), (long) value
);
23439 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
23441 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
23444 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23445 /* This is a complicated relocation used for all varieties of Thumb32
23446 load/store instruction with immediate offset:
23448 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
23449 *4, optional writeback(W)
23450 (doubleword load/store)
23452 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
23453 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
23454 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
23455 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
23456 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
23458 Uppercase letters indicate bits that are already encoded at
23459 this point. Lowercase letters are our problem. For the
23460 second block of instructions, the secondary opcode nybble
23461 (bits 8..11) is present, and bit 23 is zero, even if this is
23462 a PC-relative operation. */
23463 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23465 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
23467 if ((newval
& 0xf0000000) == 0xe0000000)
23469 /* Doubleword load/store: 8-bit offset, scaled by 4. */
23471 newval
|= (1 << 23);
23474 if (value
% 4 != 0)
23476 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23477 _("offset not a multiple of 4"));
23483 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23484 _("offset out of range"));
23489 else if ((newval
& 0x000f0000) == 0x000f0000)
23491 /* PC-relative, 12-bit offset. */
23493 newval
|= (1 << 23);
23498 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23499 _("offset out of range"));
23504 else if ((newval
& 0x00000100) == 0x00000100)
23506 /* Writeback: 8-bit, +/- offset. */
23508 newval
|= (1 << 9);
23513 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23514 _("offset out of range"));
23519 else if ((newval
& 0x00000f00) == 0x00000e00)
23521 /* T-instruction: positive 8-bit offset. */
23522 if (value
< 0 || value
> 0xff)
23524 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23525 _("offset out of range"));
23533 /* Positive 12-bit or negative 8-bit offset. */
23537 newval
|= (1 << 23);
23547 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23548 _("offset out of range"));
23555 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23556 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23559 case BFD_RELOC_ARM_SHIFT_IMM
:
23560 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23561 if (((unsigned long) value
) > 32
23563 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23565 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23566 _("shift expression is too large"));
23571 /* Shifts of zero must be done as lsl. */
23573 else if (value
== 32)
23575 newval
&= 0xfffff07f;
23576 newval
|= (value
& 0x1f) << 7;
23577 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23580 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23581 case BFD_RELOC_ARM_T32_ADD_IMM
:
23582 case BFD_RELOC_ARM_T32_IMM12
:
23583 case BFD_RELOC_ARM_T32_ADD_PC12
:
23584 /* We claim that this fixup has been processed here,
23585 even if in fact we generate an error because we do
23586 not have a reloc for it, so tc_gen_reloc will reject it. */
23590 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23592 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23593 _("undefined symbol %s used as an immediate value"),
23594 S_GET_NAME (fixP
->fx_addsy
));
23598 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23600 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23603 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23604 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
23605 Thumb2 modified immediate encoding (T2). */
23606 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
23607 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23609 newimm
= encode_thumb32_immediate (value
);
23610 if (newimm
== (unsigned int) FAIL
)
23611 newimm
= thumb32_negate_data_op (&newval
, value
);
23613 if (newimm
== (unsigned int) FAIL
)
23615 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
23617 /* Turn add/sum into addw/subw. */
23618 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23619 newval
= (newval
& 0xfeffffff) | 0x02000000;
23620 /* No flat 12-bit imm encoding for addsw/subsw. */
23621 if ((newval
& 0x00100000) == 0)
23623 /* 12 bit immediate for addw/subw. */
23627 newval
^= 0x00a00000;
23630 newimm
= (unsigned int) FAIL
;
23637 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
23638 UINT16 (T3 encoding), MOVW only accepts UINT16. When
23639 disassembling, MOV is preferred when there is no encoding
23641 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
23642 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
23643 but with the Rn field [19:16] set to 1111. */
23644 && (((newval
>> 16) & 0xf) == 0xf)
23645 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
23646 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
23647 && value
>= 0 && value
<= 0xffff)
23649 /* Toggle bit[25] to change encoding from T2 to T3. */
23651 /* Clear bits[19:16]. */
23652 newval
&= 0xfff0ffff;
23653 /* Encoding high 4bits imm. Code below will encode the
23654 remaining low 12bits. */
23655 newval
|= (value
& 0x0000f000) << 4;
23656 newimm
= value
& 0x00000fff;
23661 if (newimm
== (unsigned int)FAIL
)
23663 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23664 _("invalid constant (%lx) after fixup"),
23665 (unsigned long) value
);
23669 newval
|= (newimm
& 0x800) << 15;
23670 newval
|= (newimm
& 0x700) << 4;
23671 newval
|= (newimm
& 0x0ff);
23673 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23674 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23677 case BFD_RELOC_ARM_SMC
:
23678 if (((unsigned long) value
) > 0xffff)
23679 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23680 _("invalid smc expression"));
23681 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23682 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23683 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23686 case BFD_RELOC_ARM_HVC
:
23687 if (((unsigned long) value
) > 0xffff)
23688 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23689 _("invalid hvc expression"));
23690 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23691 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23692 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23695 case BFD_RELOC_ARM_SWI
:
23696 if (fixP
->tc_fix_data
!= 0)
23698 if (((unsigned long) value
) > 0xff)
23699 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23700 _("invalid swi expression"));
23701 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23703 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23707 if (((unsigned long) value
) > 0x00ffffff)
23708 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23709 _("invalid swi expression"));
23710 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23712 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23716 case BFD_RELOC_ARM_MULTI
:
23717 if (((unsigned long) value
) > 0xffff)
23718 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23719 _("invalid expression in load/store multiple"));
23720 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23721 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23725 case BFD_RELOC_ARM_PCREL_CALL
:
23727 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23729 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23730 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23731 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23732 /* Flip the bl to blx. This is a simple flip
23733 bit here because we generate PCREL_CALL for
23734 unconditional bls. */
23736 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23737 newval
= newval
| 0x10000000;
23738 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23744 goto arm_branch_common
;
23746 case BFD_RELOC_ARM_PCREL_JUMP
:
23747 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23749 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23750 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23751 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23753 /* This would map to a bl<cond>, b<cond>,
23754 b<always> to a Thumb function. We
23755 need to force a relocation for this particular
23757 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23760 /* Fall through. */
23762 case BFD_RELOC_ARM_PLT32
:
23764 case BFD_RELOC_ARM_PCREL_BRANCH
:
23766 goto arm_branch_common
;
23768 case BFD_RELOC_ARM_PCREL_BLX
:
23771 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23773 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23774 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23775 && ARM_IS_FUNC (fixP
->fx_addsy
))
23777 /* Flip the blx to a bl and warn. */
23778 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23779 newval
= 0xeb000000;
23780 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23781 _("blx to '%s' an ARM ISA state function changed to bl"),
23783 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23789 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23790 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23794 /* We are going to store value (shifted right by two) in the
23795 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23796 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23799 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23800 _("misaligned branch destination"));
23801 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23802 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23803 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23805 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23807 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23808 newval
|= (value
>> 2) & 0x00ffffff;
23809 /* Set the H bit on BLX instructions. */
23813 newval
|= 0x01000000;
23815 newval
&= ~0x01000000;
23817 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23821 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23822 /* CBZ can only branch forward. */
23824 /* Attempts to use CBZ to branch to the next instruction
23825 (which, strictly speaking, are prohibited) will be turned into
23828 FIXME: It may be better to remove the instruction completely and
23829 perform relaxation. */
23832 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23833 newval
= 0xbf00; /* NOP encoding T1 */
23834 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23839 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23841 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23843 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23844 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23845 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23850 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23851 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23852 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23854 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23856 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23857 newval
|= (value
& 0x1ff) >> 1;
23858 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23862 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23863 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23864 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23866 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23868 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23869 newval
|= (value
& 0xfff) >> 1;
23870 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23874 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23876 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23877 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23878 && ARM_IS_FUNC (fixP
->fx_addsy
)
23879 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23881 /* Force a relocation for a branch 20 bits wide. */
23884 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23885 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23886 _("conditional branch out of range"));
23888 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23891 addressT S
, J1
, J2
, lo
, hi
;
23893 S
= (value
& 0x00100000) >> 20;
23894 J2
= (value
& 0x00080000) >> 19;
23895 J1
= (value
& 0x00040000) >> 18;
23896 hi
= (value
& 0x0003f000) >> 12;
23897 lo
= (value
& 0x00000ffe) >> 1;
23899 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23900 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23901 newval
|= (S
<< 10) | hi
;
23902 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23903 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23904 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23908 case BFD_RELOC_THUMB_PCREL_BLX
:
23909 /* If there is a blx from a thumb state function to
23910 another thumb function flip this to a bl and warn
23914 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23915 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23916 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23918 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23919 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23920 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23922 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23923 newval
= newval
| 0x1000;
23924 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23925 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23930 goto thumb_bl_common
;
23932 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23933 /* A bl from Thumb state ISA to an internal ARM state function
23934 is converted to a blx. */
23936 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23937 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23938 && ARM_IS_FUNC (fixP
->fx_addsy
)
23939 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23941 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23942 newval
= newval
& ~0x1000;
23943 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23944 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23950 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23951 /* For a BLX instruction, make sure that the relocation is rounded up
23952 to a word boundary. This follows the semantics of the instruction
23953 which specifies that bit 1 of the target address will come from bit
23954 1 of the base address. */
23955 value
= (value
+ 3) & ~ 3;
23958 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23959 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23960 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23963 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23965 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23966 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23967 else if ((value
& ~0x1ffffff)
23968 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23969 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23970 _("Thumb2 branch out of range"));
23973 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23974 encode_thumb2_b_bl_offset (buf
, value
);
23978 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23979 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23980 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23982 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23983 encode_thumb2_b_bl_offset (buf
, value
);
23988 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23993 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23994 md_number_to_chars (buf
, value
, 2);
23998 case BFD_RELOC_ARM_TLS_CALL
:
23999 case BFD_RELOC_ARM_THM_TLS_CALL
:
24000 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24001 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24002 case BFD_RELOC_ARM_TLS_GOTDESC
:
24003 case BFD_RELOC_ARM_TLS_GD32
:
24004 case BFD_RELOC_ARM_TLS_LE32
:
24005 case BFD_RELOC_ARM_TLS_IE32
:
24006 case BFD_RELOC_ARM_TLS_LDM32
:
24007 case BFD_RELOC_ARM_TLS_LDO32
:
24008 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
24011 /* Same handling as above, but with the arm_fdpic guard. */
24012 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
24013 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
24014 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
24017 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
24021 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24022 _("Relocation supported only in FDPIC mode"));
24026 case BFD_RELOC_ARM_GOT32
:
24027 case BFD_RELOC_ARM_GOTOFF
:
24030 case BFD_RELOC_ARM_GOT_PREL
:
24031 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24032 md_number_to_chars (buf
, value
, 4);
24035 case BFD_RELOC_ARM_TARGET2
:
24036 /* TARGET2 is not partial-inplace, so we need to write the
24037 addend here for REL targets, because it won't be written out
24038 during reloc processing later. */
24039 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24040 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
24043 /* Relocations for FDPIC. */
24044 case BFD_RELOC_ARM_GOTFUNCDESC
:
24045 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
24046 case BFD_RELOC_ARM_FUNCDESC
:
24049 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24050 md_number_to_chars (buf
, 0, 4);
24054 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24055 _("Relocation supported only in FDPIC mode"));
24060 case BFD_RELOC_RVA
:
24062 case BFD_RELOC_ARM_TARGET1
:
24063 case BFD_RELOC_ARM_ROSEGREL32
:
24064 case BFD_RELOC_ARM_SBREL32
:
24065 case BFD_RELOC_32_PCREL
:
24067 case BFD_RELOC_32_SECREL
:
24069 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24071 /* For WinCE we only do this for pcrel fixups. */
24072 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
24074 md_number_to_chars (buf
, value
, 4);
24078 case BFD_RELOC_ARM_PREL31
:
24079 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24081 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
24082 if ((value
^ (value
>> 1)) & 0x40000000)
24084 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24085 _("rel31 relocation overflow"));
24087 newval
|= value
& 0x7fffffff;
24088 md_number_to_chars (buf
, newval
, 4);
24093 case BFD_RELOC_ARM_CP_OFF_IMM
:
24094 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
24095 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
24096 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24098 newval
= get_thumb32_insn (buf
);
24099 if ((newval
& 0x0f200f00) == 0x0d000900)
24101 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
24102 has permitted values that are multiples of 2, in the range 0
24104 if (value
< -510 || value
> 510 || (value
& 1))
24105 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24106 _("co-processor offset out of range"));
24108 else if (value
< -1023 || value
> 1023 || (value
& 3))
24109 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24110 _("co-processor offset out of range"));
24115 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24116 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24117 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24119 newval
= get_thumb32_insn (buf
);
24121 newval
&= 0xffffff00;
24124 newval
&= 0xff7fff00;
24125 if ((newval
& 0x0f200f00) == 0x0d000900)
24127 /* This is a fp16 vstr/vldr.
24129 It requires the immediate offset in the instruction is shifted
24130 left by 1 to be a half-word offset.
24132 Here, left shift by 1 first, and later right shift by 2
24133 should get the right offset. */
24136 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
24138 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24139 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24140 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24142 put_thumb32_insn (buf
, newval
);
24145 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
24146 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
24147 if (value
< -255 || value
> 255)
24148 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24149 _("co-processor offset out of range"));
24151 goto cp_off_common
;
24153 case BFD_RELOC_ARM_THUMB_OFFSET
:
24154 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24155 /* Exactly what ranges, and where the offset is inserted depends
24156 on the type of instruction, we can establish this from the
24158 switch (newval
>> 12)
24160 case 4: /* PC load. */
24161 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
24162 forced to zero for these loads; md_pcrel_from has already
24163 compensated for this. */
24165 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24166 _("invalid offset, target not word aligned (0x%08lX)"),
24167 (((unsigned long) fixP
->fx_frag
->fr_address
24168 + (unsigned long) fixP
->fx_where
) & ~3)
24169 + (unsigned long) value
);
24171 if (value
& ~0x3fc)
24172 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24173 _("invalid offset, value too big (0x%08lX)"),
24176 newval
|= value
>> 2;
24179 case 9: /* SP load/store. */
24180 if (value
& ~0x3fc)
24181 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24182 _("invalid offset, value too big (0x%08lX)"),
24184 newval
|= value
>> 2;
24187 case 6: /* Word load/store. */
24189 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24190 _("invalid offset, value too big (0x%08lX)"),
24192 newval
|= value
<< 4; /* 6 - 2. */
24195 case 7: /* Byte load/store. */
24197 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24198 _("invalid offset, value too big (0x%08lX)"),
24200 newval
|= value
<< 6;
24203 case 8: /* Halfword load/store. */
24205 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24206 _("invalid offset, value too big (0x%08lX)"),
24208 newval
|= value
<< 5; /* 6 - 1. */
24212 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24213 "Unable to process relocation for thumb opcode: %lx",
24214 (unsigned long) newval
);
24217 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24220 case BFD_RELOC_ARM_THUMB_ADD
:
24221 /* This is a complicated relocation, since we use it for all of
24222 the following immediate relocations:
24226 9bit ADD/SUB SP word-aligned
24227 10bit ADD PC/SP word-aligned
24229 The type of instruction being processed is encoded in the
24236 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24238 int rd
= (newval
>> 4) & 0xf;
24239 int rs
= newval
& 0xf;
24240 int subtract
= !!(newval
& 0x8000);
24242 /* Check for HI regs, only very restricted cases allowed:
24243 Adjusting SP, and using PC or SP to get an address. */
24244 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
24245 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
24246 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24247 _("invalid Hi register with immediate"));
24249 /* If value is negative, choose the opposite instruction. */
24253 subtract
= !subtract
;
24255 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24256 _("immediate value out of range"));
24261 if (value
& ~0x1fc)
24262 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24263 _("invalid immediate for stack address calculation"));
24264 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
24265 newval
|= value
>> 2;
24267 else if (rs
== REG_PC
|| rs
== REG_SP
)
24269 /* PR gas/18541. If the addition is for a defined symbol
24270 within range of an ADR instruction then accept it. */
24273 && fixP
->fx_addsy
!= NULL
)
24277 if (! S_IS_DEFINED (fixP
->fx_addsy
)
24278 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
24279 || S_IS_WEAK (fixP
->fx_addsy
))
24281 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24282 _("address calculation needs a strongly defined nearby symbol"));
24286 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
24288 /* Round up to the next 4-byte boundary. */
24293 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
24297 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24298 _("symbol too far away"));
24308 if (subtract
|| value
& ~0x3fc)
24309 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24310 _("invalid immediate for address calculation (value = 0x%08lX)"),
24311 (unsigned long) (subtract
? - value
: value
));
24312 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
24314 newval
|= value
>> 2;
24319 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24320 _("immediate value out of range"));
24321 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
24322 newval
|= (rd
<< 8) | value
;
24327 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24328 _("immediate value out of range"));
24329 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
24330 newval
|= rd
| (rs
<< 3) | (value
<< 6);
24333 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24336 case BFD_RELOC_ARM_THUMB_IMM
:
24337 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24338 if (value
< 0 || value
> 255)
24339 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24340 _("invalid immediate: %ld is out of range"),
24343 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24346 case BFD_RELOC_ARM_THUMB_SHIFT
:
24347 /* 5bit shift value (0..32). LSL cannot take 32. */
24348 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
24349 temp
= newval
& 0xf800;
24350 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
24351 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24352 _("invalid shift value: %ld"), (long) value
);
24353 /* Shifts of zero must be encoded as LSL. */
24355 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
24356 /* Shifts of 32 are encoded as zero. */
24357 else if (value
== 32)
24359 newval
|= value
<< 6;
24360 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24363 case BFD_RELOC_VTABLE_INHERIT
:
24364 case BFD_RELOC_VTABLE_ENTRY
:
24368 case BFD_RELOC_ARM_MOVW
:
24369 case BFD_RELOC_ARM_MOVT
:
24370 case BFD_RELOC_ARM_THUMB_MOVW
:
24371 case BFD_RELOC_ARM_THUMB_MOVT
:
24372 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24374 /* REL format relocations are limited to a 16-bit addend. */
24375 if (!fixP
->fx_done
)
24377 if (value
< -0x8000 || value
> 0x7fff)
24378 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24379 _("offset out of range"));
24381 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24382 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24387 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24388 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24390 newval
= get_thumb32_insn (buf
);
24391 newval
&= 0xfbf08f00;
24392 newval
|= (value
& 0xf000) << 4;
24393 newval
|= (value
& 0x0800) << 15;
24394 newval
|= (value
& 0x0700) << 4;
24395 newval
|= (value
& 0x00ff);
24396 put_thumb32_insn (buf
, newval
);
24400 newval
= md_chars_to_number (buf
, 4);
24401 newval
&= 0xfff0f000;
24402 newval
|= value
& 0x0fff;
24403 newval
|= (value
& 0xf000) << 4;
24404 md_number_to_chars (buf
, newval
, 4);
24409 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24410 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24411 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24412 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24413 gas_assert (!fixP
->fx_done
);
24416 bfd_boolean is_mov
;
24417 bfd_vma encoded_addend
= value
;
24419 /* Check that addend can be encoded in instruction. */
24420 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
24421 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24422 _("the offset 0x%08lX is not representable"),
24423 (unsigned long) encoded_addend
);
24425 /* Extract the instruction. */
24426 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
24427 is_mov
= (insn
& 0xf800) == 0x2000;
24432 if (!seg
->use_rela_p
)
24433 insn
|= encoded_addend
;
24439 /* Extract the instruction. */
24440 /* Encoding is the following
24445 /* The following conditions must be true :
24450 rd
= (insn
>> 4) & 0xf;
24452 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
24453 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24454 _("Unable to process relocation for thumb opcode: %lx"),
24455 (unsigned long) insn
);
24457 /* Encode as ADD immediate8 thumb 1 code. */
24458 insn
= 0x3000 | (rd
<< 8);
24460 /* Place the encoded addend into the first 8 bits of the
24462 if (!seg
->use_rela_p
)
24463 insn
|= encoded_addend
;
24466 /* Update the instruction. */
24467 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
24471 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24472 case BFD_RELOC_ARM_ALU_PC_G0
:
24473 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24474 case BFD_RELOC_ARM_ALU_PC_G1
:
24475 case BFD_RELOC_ARM_ALU_PC_G2
:
24476 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24477 case BFD_RELOC_ARM_ALU_SB_G0
:
24478 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24479 case BFD_RELOC_ARM_ALU_SB_G1
:
24480 case BFD_RELOC_ARM_ALU_SB_G2
:
24481 gas_assert (!fixP
->fx_done
);
24482 if (!seg
->use_rela_p
)
24485 bfd_vma encoded_addend
;
24486 bfd_vma addend_abs
= abs (value
);
24488 /* Check that the absolute value of the addend can be
24489 expressed as an 8-bit constant plus a rotation. */
24490 encoded_addend
= encode_arm_immediate (addend_abs
);
24491 if (encoded_addend
== (unsigned int) FAIL
)
24492 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24493 _("the offset 0x%08lX is not representable"),
24494 (unsigned long) addend_abs
);
24496 /* Extract the instruction. */
24497 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24499 /* If the addend is positive, use an ADD instruction.
24500 Otherwise use a SUB. Take care not to destroy the S bit. */
24501 insn
&= 0xff1fffff;
24507 /* Place the encoded addend into the first 12 bits of the
24509 insn
&= 0xfffff000;
24510 insn
|= encoded_addend
;
24512 /* Update the instruction. */
24513 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24517 case BFD_RELOC_ARM_LDR_PC_G0
:
24518 case BFD_RELOC_ARM_LDR_PC_G1
:
24519 case BFD_RELOC_ARM_LDR_PC_G2
:
24520 case BFD_RELOC_ARM_LDR_SB_G0
:
24521 case BFD_RELOC_ARM_LDR_SB_G1
:
24522 case BFD_RELOC_ARM_LDR_SB_G2
:
24523 gas_assert (!fixP
->fx_done
);
24524 if (!seg
->use_rela_p
)
24527 bfd_vma addend_abs
= abs (value
);
24529 /* Check that the absolute value of the addend can be
24530 encoded in 12 bits. */
24531 if (addend_abs
>= 0x1000)
24532 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24533 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
24534 (unsigned long) addend_abs
);
24536 /* Extract the instruction. */
24537 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24539 /* If the addend is negative, clear bit 23 of the instruction.
24540 Otherwise set it. */
24542 insn
&= ~(1 << 23);
24546 /* Place the absolute value of the addend into the first 12 bits
24547 of the instruction. */
24548 insn
&= 0xfffff000;
24549 insn
|= addend_abs
;
24551 /* Update the instruction. */
24552 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24556 case BFD_RELOC_ARM_LDRS_PC_G0
:
24557 case BFD_RELOC_ARM_LDRS_PC_G1
:
24558 case BFD_RELOC_ARM_LDRS_PC_G2
:
24559 case BFD_RELOC_ARM_LDRS_SB_G0
:
24560 case BFD_RELOC_ARM_LDRS_SB_G1
:
24561 case BFD_RELOC_ARM_LDRS_SB_G2
:
24562 gas_assert (!fixP
->fx_done
);
24563 if (!seg
->use_rela_p
)
24566 bfd_vma addend_abs
= abs (value
);
24568 /* Check that the absolute value of the addend can be
24569 encoded in 8 bits. */
24570 if (addend_abs
>= 0x100)
24571 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24572 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
24573 (unsigned long) addend_abs
);
24575 /* Extract the instruction. */
24576 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24578 /* If the addend is negative, clear bit 23 of the instruction.
24579 Otherwise set it. */
24581 insn
&= ~(1 << 23);
24585 /* Place the first four bits of the absolute value of the addend
24586 into the first 4 bits of the instruction, and the remaining
24587 four into bits 8 .. 11. */
24588 insn
&= 0xfffff0f0;
24589 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
24591 /* Update the instruction. */
24592 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24596 case BFD_RELOC_ARM_LDC_PC_G0
:
24597 case BFD_RELOC_ARM_LDC_PC_G1
:
24598 case BFD_RELOC_ARM_LDC_PC_G2
:
24599 case BFD_RELOC_ARM_LDC_SB_G0
:
24600 case BFD_RELOC_ARM_LDC_SB_G1
:
24601 case BFD_RELOC_ARM_LDC_SB_G2
:
24602 gas_assert (!fixP
->fx_done
);
24603 if (!seg
->use_rela_p
)
24606 bfd_vma addend_abs
= abs (value
);
24608 /* Check that the absolute value of the addend is a multiple of
24609 four and, when divided by four, fits in 8 bits. */
24610 if (addend_abs
& 0x3)
24611 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24612 _("bad offset 0x%08lX (must be word-aligned)"),
24613 (unsigned long) addend_abs
);
24615 if ((addend_abs
>> 2) > 0xff)
24616 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24617 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24618 (unsigned long) addend_abs
);
24620 /* Extract the instruction. */
24621 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24623 /* If the addend is negative, clear bit 23 of the instruction.
24624 Otherwise set it. */
24626 insn
&= ~(1 << 23);
24630 /* Place the addend (divided by four) into the first eight
24631 bits of the instruction. */
24632 insn
&= 0xfffffff0;
24633 insn
|= addend_abs
>> 2;
24635 /* Update the instruction. */
24636 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24640 case BFD_RELOC_ARM_V4BX
:
24641 /* This will need to go in the object file. */
24645 case BFD_RELOC_UNUSED
:
24647 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24648 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24652 /* Translate internal representation of relocation info to BFD target
24656 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24659 bfd_reloc_code_real_type code
;
24661 reloc
= XNEW (arelent
);
24663 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24664 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24665 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24667 if (fixp
->fx_pcrel
)
24669 if (section
->use_rela_p
)
24670 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24672 fixp
->fx_offset
= reloc
->address
;
24674 reloc
->addend
= fixp
->fx_offset
;
24676 switch (fixp
->fx_r_type
)
24679 if (fixp
->fx_pcrel
)
24681 code
= BFD_RELOC_8_PCREL
;
24684 /* Fall through. */
24687 if (fixp
->fx_pcrel
)
24689 code
= BFD_RELOC_16_PCREL
;
24692 /* Fall through. */
24695 if (fixp
->fx_pcrel
)
24697 code
= BFD_RELOC_32_PCREL
;
24700 /* Fall through. */
24702 case BFD_RELOC_ARM_MOVW
:
24703 if (fixp
->fx_pcrel
)
24705 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24708 /* Fall through. */
24710 case BFD_RELOC_ARM_MOVT
:
24711 if (fixp
->fx_pcrel
)
24713 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24716 /* Fall through. */
24718 case BFD_RELOC_ARM_THUMB_MOVW
:
24719 if (fixp
->fx_pcrel
)
24721 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24724 /* Fall through. */
24726 case BFD_RELOC_ARM_THUMB_MOVT
:
24727 if (fixp
->fx_pcrel
)
24729 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24732 /* Fall through. */
24734 case BFD_RELOC_NONE
:
24735 case BFD_RELOC_ARM_PCREL_BRANCH
:
24736 case BFD_RELOC_ARM_PCREL_BLX
:
24737 case BFD_RELOC_RVA
:
24738 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24739 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24740 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24741 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24742 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24743 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24744 case BFD_RELOC_VTABLE_ENTRY
:
24745 case BFD_RELOC_VTABLE_INHERIT
:
24747 case BFD_RELOC_32_SECREL
:
24749 code
= fixp
->fx_r_type
;
24752 case BFD_RELOC_THUMB_PCREL_BLX
:
24754 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24755 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24758 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24761 case BFD_RELOC_ARM_LITERAL
:
24762 case BFD_RELOC_ARM_HWLITERAL
:
24763 /* If this is called then the a literal has
24764 been referenced across a section boundary. */
24765 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24766 _("literal referenced across section boundary"));
24770 case BFD_RELOC_ARM_TLS_CALL
:
24771 case BFD_RELOC_ARM_THM_TLS_CALL
:
24772 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24773 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24774 case BFD_RELOC_ARM_GOT32
:
24775 case BFD_RELOC_ARM_GOTOFF
:
24776 case BFD_RELOC_ARM_GOT_PREL
:
24777 case BFD_RELOC_ARM_PLT32
:
24778 case BFD_RELOC_ARM_TARGET1
:
24779 case BFD_RELOC_ARM_ROSEGREL32
:
24780 case BFD_RELOC_ARM_SBREL32
:
24781 case BFD_RELOC_ARM_PREL31
:
24782 case BFD_RELOC_ARM_TARGET2
:
24783 case BFD_RELOC_ARM_TLS_LDO32
:
24784 case BFD_RELOC_ARM_PCREL_CALL
:
24785 case BFD_RELOC_ARM_PCREL_JUMP
:
24786 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24787 case BFD_RELOC_ARM_ALU_PC_G0
:
24788 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24789 case BFD_RELOC_ARM_ALU_PC_G1
:
24790 case BFD_RELOC_ARM_ALU_PC_G2
:
24791 case BFD_RELOC_ARM_LDR_PC_G0
:
24792 case BFD_RELOC_ARM_LDR_PC_G1
:
24793 case BFD_RELOC_ARM_LDR_PC_G2
:
24794 case BFD_RELOC_ARM_LDRS_PC_G0
:
24795 case BFD_RELOC_ARM_LDRS_PC_G1
:
24796 case BFD_RELOC_ARM_LDRS_PC_G2
:
24797 case BFD_RELOC_ARM_LDC_PC_G0
:
24798 case BFD_RELOC_ARM_LDC_PC_G1
:
24799 case BFD_RELOC_ARM_LDC_PC_G2
:
24800 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24801 case BFD_RELOC_ARM_ALU_SB_G0
:
24802 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24803 case BFD_RELOC_ARM_ALU_SB_G1
:
24804 case BFD_RELOC_ARM_ALU_SB_G2
:
24805 case BFD_RELOC_ARM_LDR_SB_G0
:
24806 case BFD_RELOC_ARM_LDR_SB_G1
:
24807 case BFD_RELOC_ARM_LDR_SB_G2
:
24808 case BFD_RELOC_ARM_LDRS_SB_G0
:
24809 case BFD_RELOC_ARM_LDRS_SB_G1
:
24810 case BFD_RELOC_ARM_LDRS_SB_G2
:
24811 case BFD_RELOC_ARM_LDC_SB_G0
:
24812 case BFD_RELOC_ARM_LDC_SB_G1
:
24813 case BFD_RELOC_ARM_LDC_SB_G2
:
24814 case BFD_RELOC_ARM_V4BX
:
24815 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24816 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24817 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24818 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24819 case BFD_RELOC_ARM_GOTFUNCDESC
:
24820 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
24821 case BFD_RELOC_ARM_FUNCDESC
:
24822 code
= fixp
->fx_r_type
;
24825 case BFD_RELOC_ARM_TLS_GOTDESC
:
24826 case BFD_RELOC_ARM_TLS_GD32
:
24827 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
24828 case BFD_RELOC_ARM_TLS_LE32
:
24829 case BFD_RELOC_ARM_TLS_IE32
:
24830 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
24831 case BFD_RELOC_ARM_TLS_LDM32
:
24832 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
24833 /* BFD will include the symbol's address in the addend.
24834 But we don't want that, so subtract it out again here. */
24835 if (!S_IS_COMMON (fixp
->fx_addsy
))
24836 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24837 code
= fixp
->fx_r_type
;
24841 case BFD_RELOC_ARM_IMMEDIATE
:
24842 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24843 _("internal relocation (type: IMMEDIATE) not fixed up"));
24846 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24847 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24848 _("ADRL used for a symbol not defined in the same file"));
24851 case BFD_RELOC_ARM_OFFSET_IMM
:
24852 if (section
->use_rela_p
)
24854 code
= fixp
->fx_r_type
;
24858 if (fixp
->fx_addsy
!= NULL
24859 && !S_IS_DEFINED (fixp
->fx_addsy
)
24860 && S_IS_LOCAL (fixp
->fx_addsy
))
24862 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24863 _("undefined local label `%s'"),
24864 S_GET_NAME (fixp
->fx_addsy
));
24868 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24869 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24876 switch (fixp
->fx_r_type
)
24878 case BFD_RELOC_NONE
: type
= "NONE"; break;
24879 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24880 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24881 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24882 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24883 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24884 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24885 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24886 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24887 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24888 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24889 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24890 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24891 default: type
= _("<unknown>"); break;
24893 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24894 _("cannot represent %s relocation in this object file format"),
24901 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24903 && fixp
->fx_addsy
== GOT_symbol
)
24905 code
= BFD_RELOC_ARM_GOTPC
;
24906 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24910 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24912 if (reloc
->howto
== NULL
)
24914 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24915 _("cannot represent %s relocation in this object file format"),
24916 bfd_get_reloc_code_name (code
));
24920 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24921 vtable entry to be used in the relocation's section offset. */
24922 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24923 reloc
->address
= fixp
->fx_offset
;
24928 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24931 cons_fix_new_arm (fragS
* frag
,
24935 bfd_reloc_code_real_type reloc
)
24940 FIXME: @@ Should look at CPU word size. */
24944 reloc
= BFD_RELOC_8
;
24947 reloc
= BFD_RELOC_16
;
24951 reloc
= BFD_RELOC_32
;
24954 reloc
= BFD_RELOC_64
;
24959 if (exp
->X_op
== O_secrel
)
24961 exp
->X_op
= O_symbol
;
24962 reloc
= BFD_RELOC_32_SECREL
;
24966 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24969 #if defined (OBJ_COFF)
24971 arm_validate_fix (fixS
* fixP
)
24973 /* If the destination of the branch is a defined symbol which does not have
24974 the THUMB_FUNC attribute, then we must be calling a function which has
24975 the (interfacearm) attribute. We look for the Thumb entry point to that
24976 function and change the branch to refer to that function instead. */
24977 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24978 && fixP
->fx_addsy
!= NULL
24979 && S_IS_DEFINED (fixP
->fx_addsy
)
24980 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24982 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24989 arm_force_relocation (struct fix
* fixp
)
24991 #if defined (OBJ_COFF) && defined (TE_PE)
24992 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24996 /* In case we have a call or a branch to a function in ARM ISA mode from
24997 a thumb function or vice-versa force the relocation. These relocations
24998 are cleared off for some cores that might have blx and simple transformations
25002 switch (fixp
->fx_r_type
)
25004 case BFD_RELOC_ARM_PCREL_JUMP
:
25005 case BFD_RELOC_ARM_PCREL_CALL
:
25006 case BFD_RELOC_THUMB_PCREL_BLX
:
25007 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
25011 case BFD_RELOC_ARM_PCREL_BLX
:
25012 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
25013 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
25014 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25015 if (ARM_IS_FUNC (fixp
->fx_addsy
))
25024 /* Resolve these relocations even if the symbol is extern or weak.
25025 Technically this is probably wrong due to symbol preemption.
25026 In practice these relocations do not have enough range to be useful
25027 at dynamic link time, and some code (e.g. in the Linux kernel)
25028 expects these references to be resolved. */
25029 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
25030 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
25031 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
25032 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
25033 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
25034 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
25035 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
25036 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
25037 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
25038 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
25039 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
25040 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
25041 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
25042 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
25045 /* Always leave these relocations for the linker. */
25046 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
25047 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
25048 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
25051 /* Always generate relocations against function symbols. */
25052 if (fixp
->fx_r_type
== BFD_RELOC_32
25054 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
25057 return generic_force_reloc (fixp
);
25060 #if defined (OBJ_ELF) || defined (OBJ_COFF)
25061 /* Relocations against function names must be left unadjusted,
25062 so that the linker can use this information to generate interworking
25063 stubs. The MIPS version of this function
25064 also prevents relocations that are mips-16 specific, but I do not
25065 know why it does this.
25068 There is one other problem that ought to be addressed here, but
25069 which currently is not: Taking the address of a label (rather
25070 than a function) and then later jumping to that address. Such
25071 addresses also ought to have their bottom bit set (assuming that
25072 they reside in Thumb code), but at the moment they will not. */
25075 arm_fix_adjustable (fixS
* fixP
)
25077 if (fixP
->fx_addsy
== NULL
)
25080 /* Preserve relocations against symbols with function type. */
25081 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
25084 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
25085 && fixP
->fx_subsy
== NULL
)
25088 /* We need the symbol name for the VTABLE entries. */
25089 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
25090 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
25093 /* Don't allow symbols to be discarded on GOT related relocs. */
25094 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
25095 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
25096 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
25097 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
25098 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
25099 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
25100 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
25101 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
25102 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
25103 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
25104 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
25105 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
25106 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
25107 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
25108 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
25109 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
25110 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
25113 /* Similarly for group relocations. */
25114 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
25115 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
25116 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
25119 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
25120 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
25121 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
25122 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
25123 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
25124 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
25125 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
25126 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
25127 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
25130 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
25131 offsets, so keep these symbols. */
25132 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
25133 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
25138 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
25142 elf32_arm_target_format (void)
25145 return (target_big_endian
25146 ? "elf32-bigarm-symbian"
25147 : "elf32-littlearm-symbian");
25148 #elif defined (TE_VXWORKS)
25149 return (target_big_endian
25150 ? "elf32-bigarm-vxworks"
25151 : "elf32-littlearm-vxworks");
25152 #elif defined (TE_NACL)
25153 return (target_big_endian
25154 ? "elf32-bigarm-nacl"
25155 : "elf32-littlearm-nacl");
25159 if (target_big_endian
)
25160 return "elf32-bigarm-fdpic";
25162 return "elf32-littlearm-fdpic";
25166 if (target_big_endian
)
25167 return "elf32-bigarm";
25169 return "elf32-littlearm";
25175 armelf_frob_symbol (symbolS
* symp
,
25178 elf_frob_symbol (symp
, puntp
);
25182 /* MD interface: Finalization. */
25187 literal_pool
* pool
;
25189 /* Ensure that all the IT blocks are properly closed. */
25190 check_it_blocks_finished ();
25192 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
25194 /* Put it at the end of the relevant section. */
25195 subseg_set (pool
->section
, pool
->sub_section
);
25197 arm_elf_change_section ();
25204 /* Remove any excess mapping symbols generated for alignment frags in
25205 SEC. We may have created a mapping symbol before a zero byte
25206 alignment; remove it if there's a mapping symbol after the
25209 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
25210 void *dummy ATTRIBUTE_UNUSED
)
25212 segment_info_type
*seginfo
= seg_info (sec
);
25215 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
25218 for (fragp
= seginfo
->frchainP
->frch_root
;
25220 fragp
= fragp
->fr_next
)
25222 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
25223 fragS
*next
= fragp
->fr_next
;
25225 /* Variable-sized frags have been converted to fixed size by
25226 this point. But if this was variable-sized to start with,
25227 there will be a fixed-size frag after it. So don't handle
25229 if (sym
== NULL
|| next
== NULL
)
25232 if (S_GET_VALUE (sym
) < next
->fr_address
)
25233 /* Not at the end of this frag. */
25235 know (S_GET_VALUE (sym
) == next
->fr_address
);
25239 if (next
->tc_frag_data
.first_map
!= NULL
)
25241 /* Next frag starts with a mapping symbol. Discard this
25243 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25247 if (next
->fr_next
== NULL
)
25249 /* This mapping symbol is at the end of the section. Discard
25251 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
25252 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25256 /* As long as we have empty frags without any mapping symbols,
25258 /* If the next frag is non-empty and does not start with a
25259 mapping symbol, then this mapping symbol is required. */
25260 if (next
->fr_address
!= next
->fr_next
->fr_address
)
25263 next
= next
->fr_next
;
25265 while (next
!= NULL
);
25270 /* Adjust the symbol table. This marks Thumb symbols as distinct from
25274 arm_adjust_symtab (void)
25279 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25281 if (ARM_IS_THUMB (sym
))
25283 if (THUMB_IS_FUNC (sym
))
25285 /* Mark the symbol as a Thumb function. */
25286 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
25287 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
25288 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
25290 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
25291 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
25293 as_bad (_("%s: unexpected function type: %d"),
25294 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
25296 else switch (S_GET_STORAGE_CLASS (sym
))
25299 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
25302 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
25305 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
25313 if (ARM_IS_INTERWORK (sym
))
25314 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
25321 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25323 if (ARM_IS_THUMB (sym
))
25325 elf_symbol_type
* elf_sym
;
25327 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
25328 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
25330 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
25331 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
25333 /* If it's a .thumb_func, declare it as so,
25334 otherwise tag label as .code 16. */
25335 if (THUMB_IS_FUNC (sym
))
25336 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
25337 ST_BRANCH_TO_THUMB
);
25338 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25339 elf_sym
->internal_elf_sym
.st_info
=
25340 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
25345 /* Remove any overlapping mapping symbols generated by alignment frags. */
25346 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
25347 /* Now do generic ELF adjustments. */
25348 elf_adjust_symtab ();
25352 /* MD interface: Initialization. */
25355 set_constant_flonums (void)
25359 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
25360 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
25364 /* Auto-select Thumb mode if it's the only available instruction set for the
25365 given architecture. */
25368 autoselect_thumb_from_cpu_variant (void)
25370 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
25371 opcode_select (16);
25380 if ( (arm_ops_hsh
= hash_new ()) == NULL
25381 || (arm_cond_hsh
= hash_new ()) == NULL
25382 || (arm_shift_hsh
= hash_new ()) == NULL
25383 || (arm_psr_hsh
= hash_new ()) == NULL
25384 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
25385 || (arm_reg_hsh
= hash_new ()) == NULL
25386 || (arm_reloc_hsh
= hash_new ()) == NULL
25387 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
25388 as_fatal (_("virtual memory exhausted"));
25390 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
25391 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
25392 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
25393 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
25394 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
25395 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
25396 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
25397 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
25398 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
25399 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
25400 (void *) (v7m_psrs
+ i
));
25401 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
25402 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
25404 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
25406 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
25407 (void *) (barrier_opt_names
+ i
));
25409 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
25411 struct reloc_entry
* entry
= reloc_names
+ i
;
25413 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
25414 /* This makes encode_branch() use the EABI versions of this relocation. */
25415 entry
->reloc
= BFD_RELOC_UNUSED
;
25417 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
25421 set_constant_flonums ();
25423 /* Set the cpu variant based on the command-line options. We prefer
25424 -mcpu= over -march= if both are set (as for GCC); and we prefer
25425 -mfpu= over any other way of setting the floating point unit.
25426 Use of legacy options with new options are faulted. */
25429 if (mcpu_cpu_opt
|| march_cpu_opt
)
25430 as_bad (_("use of old and new-style options to set CPU type"));
25432 selected_arch
= *legacy_cpu
;
25434 else if (mcpu_cpu_opt
)
25436 selected_arch
= *mcpu_cpu_opt
;
25437 selected_ext
= *mcpu_ext_opt
;
25439 else if (march_cpu_opt
)
25441 selected_arch
= *march_cpu_opt
;
25442 selected_ext
= *march_ext_opt
;
25444 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
25449 as_bad (_("use of old and new-style options to set FPU type"));
25451 selected_fpu
= *legacy_fpu
;
25454 selected_fpu
= *mfpu_opt
;
25457 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
25458 || defined (TE_NetBSD) || defined (TE_VXWORKS))
25459 /* Some environments specify a default FPU. If they don't, infer it
25460 from the processor. */
25462 selected_fpu
= *mcpu_fpu_opt
;
25463 else if (march_fpu_opt
)
25464 selected_fpu
= *march_fpu_opt
;
25466 selected_fpu
= fpu_default
;
25470 if (ARM_FEATURE_ZERO (selected_fpu
))
25472 if (!no_cpu_selected ())
25473 selected_fpu
= fpu_default
;
25475 selected_fpu
= fpu_arch_fpa
;
25479 if (ARM_FEATURE_ZERO (selected_arch
))
25481 selected_arch
= cpu_default
;
25482 selected_cpu
= selected_arch
;
25484 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
25486 /* Autodection of feature mode: allow all features in cpu_variant but leave
25487 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
25488 after all instruction have been processed and we can decide what CPU
25489 should be selected. */
25490 if (ARM_FEATURE_ZERO (selected_arch
))
25491 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
25493 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
25496 autoselect_thumb_from_cpu_variant ();
25498 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
25500 #if defined OBJ_COFF || defined OBJ_ELF
25502 unsigned int flags
= 0;
25504 #if defined OBJ_ELF
25505 flags
= meabi_flags
;
25507 switch (meabi_flags
)
25509 case EF_ARM_EABI_UNKNOWN
:
25511 /* Set the flags in the private structure. */
25512 if (uses_apcs_26
) flags
|= F_APCS26
;
25513 if (support_interwork
) flags
|= F_INTERWORK
;
25514 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
25515 if (pic_code
) flags
|= F_PIC
;
25516 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
25517 flags
|= F_SOFT_FLOAT
;
25519 switch (mfloat_abi_opt
)
25521 case ARM_FLOAT_ABI_SOFT
:
25522 case ARM_FLOAT_ABI_SOFTFP
:
25523 flags
|= F_SOFT_FLOAT
;
25526 case ARM_FLOAT_ABI_HARD
:
25527 if (flags
& F_SOFT_FLOAT
)
25528 as_bad (_("hard-float conflicts with specified fpu"));
25532 /* Using pure-endian doubles (even if soft-float). */
25533 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
25534 flags
|= F_VFP_FLOAT
;
25536 #if defined OBJ_ELF
25537 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
25538 flags
|= EF_ARM_MAVERICK_FLOAT
;
25541 case EF_ARM_EABI_VER4
:
25542 case EF_ARM_EABI_VER5
:
25543 /* No additional flags to set. */
25550 bfd_set_private_flags (stdoutput
, flags
);
25552 /* We have run out flags in the COFF header to encode the
25553 status of ATPCS support, so instead we create a dummy,
25554 empty, debug section called .arm.atpcs. */
25559 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
25563 bfd_set_section_flags
25564 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
25565 bfd_set_section_size (stdoutput
, sec
, 0);
25566 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
25572 /* Record the CPU type as well. */
25573 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
25574 mach
= bfd_mach_arm_iWMMXt2
;
25575 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
25576 mach
= bfd_mach_arm_iWMMXt
;
25577 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
25578 mach
= bfd_mach_arm_XScale
;
25579 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
25580 mach
= bfd_mach_arm_ep9312
;
25581 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
25582 mach
= bfd_mach_arm_5TE
;
25583 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
25585 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25586 mach
= bfd_mach_arm_5T
;
25588 mach
= bfd_mach_arm_5
;
25590 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
25592 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25593 mach
= bfd_mach_arm_4T
;
25595 mach
= bfd_mach_arm_4
;
25597 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
25598 mach
= bfd_mach_arm_3M
;
25599 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
25600 mach
= bfd_mach_arm_3
;
25601 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
25602 mach
= bfd_mach_arm_2a
;
25603 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
25604 mach
= bfd_mach_arm_2
;
25606 mach
= bfd_mach_arm_unknown
;
25608 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
25611 /* Command line processing. */
25614 Invocation line includes a switch not recognized by the base assembler.
25615 See if it's a processor-specific option.
25617 This routine is somewhat complicated by the need for backwards
25618 compatibility (since older releases of gcc can't be changed).
25619 The new options try to make the interface as compatible as
25622 New options (supported) are:
25624 -mcpu=<cpu name> Assemble for selected processor
25625 -march=<architecture name> Assemble for selected architecture
25626 -mfpu=<fpu architecture> Assemble for selected FPU.
25627 -EB/-mbig-endian Big-endian
25628 -EL/-mlittle-endian Little-endian
25629 -k Generate PIC code
25630 -mthumb Start in Thumb mode
25631 -mthumb-interwork Code supports ARM/Thumb interworking
25633 -m[no-]warn-deprecated Warn about deprecated features
25634 -m[no-]warn-syms Warn when symbols match instructions
25636 For now we will also provide support for:
25638 -mapcs-32 32-bit Program counter
25639 -mapcs-26 26-bit Program counter
25640 -macps-float Floats passed in FP registers
25641 -mapcs-reentrant Reentrant code
25643 (sometime these will probably be replaced with -mapcs=<list of options>
25644 and -matpcs=<list of options>)
25646 The remaining options are only supported for back-wards compatibility.
25647 Cpu variants, the arm part is optional:
25648 -m[arm]1 Currently not supported.
25649 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25650 -m[arm]3 Arm 3 processor
25651 -m[arm]6[xx], Arm 6 processors
25652 -m[arm]7[xx][t][[d]m] Arm 7 processors
25653 -m[arm]8[10] Arm 8 processors
25654 -m[arm]9[20][tdmi] Arm 9 processors
25655 -mstrongarm[110[0]] StrongARM processors
25656 -mxscale XScale processors
25657 -m[arm]v[2345[t[e]]] Arm architectures
25658 -mall All (except the ARM1)
25660 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25661 -mfpe-old (No float load/store multiples)
25662 -mvfpxd VFP Single precision
25664 -mno-fpu Disable all floating point instructions
25666 The following CPU names are recognized:
25667 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25668 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25669 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25670 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25671 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25672 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25673 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25677 const char * md_shortopts
= "m:k";
25679 #ifdef ARM_BI_ENDIAN
25680 #define OPTION_EB (OPTION_MD_BASE + 0)
25681 #define OPTION_EL (OPTION_MD_BASE + 1)
25683 #if TARGET_BYTES_BIG_ENDIAN
25684 #define OPTION_EB (OPTION_MD_BASE + 0)
25686 #define OPTION_EL (OPTION_MD_BASE + 1)
25689 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25690 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
25692 struct option md_longopts
[] =
25695 {"EB", no_argument
, NULL
, OPTION_EB
},
25698 {"EL", no_argument
, NULL
, OPTION_EL
},
25700 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25702 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
25704 {NULL
, no_argument
, NULL
, 0}
25707 size_t md_longopts_size
= sizeof (md_longopts
);
25709 struct arm_option_table
25711 const char * option
; /* Option name to match. */
25712 const char * help
; /* Help information. */
25713 int * var
; /* Variable to change. */
25714 int value
; /* What to change it to. */
25715 const char * deprecated
; /* If non-null, print this message. */
25718 struct arm_option_table arm_opts
[] =
25720 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25721 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25722 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25723 &support_interwork
, 1, NULL
},
25724 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25725 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25726 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25728 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25729 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25730 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25731 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25734 /* These are recognized by the assembler, but have no affect on code. */
25735 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25736 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25738 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25739 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25740 &warn_on_deprecated
, 0, NULL
},
25741 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25742 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25743 {NULL
, NULL
, NULL
, 0, NULL
}
25746 struct arm_legacy_option_table
25748 const char * option
; /* Option name to match. */
25749 const arm_feature_set
** var
; /* Variable to change. */
25750 const arm_feature_set value
; /* What to change it to. */
25751 const char * deprecated
; /* If non-null, print this message. */
25754 const struct arm_legacy_option_table arm_legacy_opts
[] =
25756 /* DON'T add any new processors to this list -- we want the whole list
25757 to go away... Add them to the processors table instead. */
25758 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25759 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25760 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25761 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25762 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25763 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25764 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25765 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25766 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25767 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25768 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25769 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25770 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25771 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25772 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25773 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25774 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25775 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25776 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25777 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25778 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25779 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25780 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25781 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25782 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25783 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25784 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25785 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25786 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25787 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25788 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25789 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25790 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25791 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25792 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25793 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25794 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25795 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25796 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25797 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25798 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25799 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25800 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25801 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25802 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25803 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25804 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25805 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25806 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25807 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25808 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25809 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25810 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25811 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25812 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25813 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25814 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25815 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25816 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25817 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25818 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25819 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25820 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25821 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25822 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25823 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25824 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25825 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25826 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25827 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25828 N_("use -mcpu=strongarm110")},
25829 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25830 N_("use -mcpu=strongarm1100")},
25831 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25832 N_("use -mcpu=strongarm1110")},
25833 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25834 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25835 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25837 /* Architecture variants -- don't add any more to this list either. */
25838 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25839 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25840 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25841 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25842 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25843 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25844 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25845 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25846 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25847 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25848 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25849 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25850 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25851 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25852 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25853 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25854 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25855 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25857 /* Floating point variants -- don't add any more to this list either. */
25858 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25859 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25860 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25861 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25862 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25864 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25867 struct arm_cpu_option_table
25871 const arm_feature_set value
;
25872 const arm_feature_set ext
;
25873 /* For some CPUs we assume an FPU unless the user explicitly sets
25875 const arm_feature_set default_fpu
;
25876 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25878 const char * canonical_name
;
25881 /* This list should, at a minimum, contain all the cpu names
25882 recognized by GCC. */
25883 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
25885 static const struct arm_cpu_option_table arm_cpus
[] =
25887 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
25890 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
25893 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
25896 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
25899 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
25902 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
25905 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
25908 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
25911 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
25914 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
25917 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
25920 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
25923 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
25926 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
25929 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
25932 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
25935 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
25938 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
25941 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
25944 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
25947 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
25950 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
25953 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
25956 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
25959 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
25962 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
25965 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
25968 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
25971 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
25974 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
25977 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
25980 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
25983 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
25986 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
25989 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
25992 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
25995 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
25998 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
26001 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
26004 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
26007 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
26010 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
26013 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
26016 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
26019 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
26022 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
26026 /* For V5 or later processors we default to using VFP; but the user
26027 should really set the FPU type explicitly. */
26028 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
26031 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
26034 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
26037 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
26040 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
26043 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
26046 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
26049 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
26052 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
26055 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
26058 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
26061 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
26064 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
26067 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
26070 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
26073 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
26076 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
26079 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
26082 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
26085 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
26088 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
26091 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
26094 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
26097 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
26100 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
26103 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
26106 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
26109 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
26112 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
26115 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
26118 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
26121 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
26124 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
26127 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
26130 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
26133 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
26136 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
26137 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26139 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
26141 FPU_ARCH_NEON_VFP_V4
),
26142 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
26143 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26144 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26145 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
26146 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26147 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26148 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
26150 FPU_ARCH_NEON_VFP_V4
),
26151 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
26153 FPU_ARCH_NEON_VFP_V4
),
26154 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
26156 FPU_ARCH_NEON_VFP_V4
),
26157 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
26158 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26159 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26160 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
26161 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26162 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26163 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
26164 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26165 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26166 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
26167 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26168 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26169 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
26170 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26171 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26172 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
26173 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26174 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26175 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
26176 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26177 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26178 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
26179 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26180 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26181 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
26182 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26183 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26184 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
26187 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
26189 FPU_ARCH_VFP_V3D16
),
26190 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
26191 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26193 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
26194 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26195 FPU_ARCH_VFP_V3D16
),
26196 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
26197 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26198 FPU_ARCH_VFP_V3D16
),
26199 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
26200 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26201 FPU_ARCH_NEON_VFP_ARMV8
),
26202 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
26203 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26205 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
26208 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
26211 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
26214 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
26217 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
26220 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
26223 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
26226 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
26227 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26228 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26230 /* ??? XSCALE is really an architecture. */
26231 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
26235 /* ??? iwmmxt is not a processor. */
26236 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
26239 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
26242 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
26247 ARM_CPU_OPT ("ep9312", "ARM920T",
26248 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
26249 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
26251 /* Marvell processors. */
26252 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
26253 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26254 FPU_ARCH_VFP_V3D16
),
26255 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
26256 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26257 FPU_ARCH_NEON_VFP_V4
),
26259 /* APM X-Gene family. */
26260 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
26262 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26263 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
26264 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26265 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26267 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
26271 struct arm_arch_option_table
26275 const arm_feature_set value
;
26276 const arm_feature_set default_fpu
;
26279 /* This list should, at a minimum, contain all the architecture names
26280 recognized by GCC. */
26281 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
26283 static const struct arm_arch_option_table arm_archs
[] =
26285 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
26286 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
26287 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
26288 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
26289 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
26290 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
26291 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
26292 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
26293 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
26294 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
26295 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
26296 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
26297 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
26298 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
26299 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
26300 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
26301 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
26302 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
26303 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
26304 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
26305 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
26306 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
26307 kept to preserve existing behaviour. */
26308 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
26309 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
26310 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
26311 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
26312 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
26313 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
26314 kept to preserve existing behaviour. */
26315 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
26316 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
26317 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
26318 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
26319 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
26320 /* The official spelling of the ARMv7 profile variants is the dashed form.
26321 Accept the non-dashed form for compatibility with old toolchains. */
26322 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
26323 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
26324 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
26325 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26326 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
26327 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
26328 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26329 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
26330 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
26331 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
26332 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
26333 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
26334 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
26335 ARM_ARCH_OPT ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
),
26336 ARM_ARCH_OPT ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
),
26337 ARM_ARCH_OPT ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
),
26338 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
26339 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
26340 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
26341 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26343 #undef ARM_ARCH_OPT
26345 /* ISA extensions in the co-processor and main instruction set space. */
26347 struct arm_option_extension_value_table
26351 const arm_feature_set merge_value
;
26352 const arm_feature_set clear_value
;
26353 /* List of architectures for which an extension is available. ARM_ARCH_NONE
26354 indicates that an extension is available for all architectures while
26355 ARM_ANY marks an empty entry. */
26356 const arm_feature_set allowed_archs
[2];
26359 /* The following table must be in alphabetical order with a NULL last entry. */
26361 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
26362 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
26364 static const struct arm_option_extension_value_table arm_extensions
[] =
26366 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26367 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26368 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
26369 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
26370 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26371 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
26372 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
26374 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26375 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26376 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
26377 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
26378 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26379 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26380 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26382 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
26383 | ARM_EXT2_FP16_FML
),
26384 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
26385 | ARM_EXT2_FP16_FML
),
26387 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26388 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26389 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
26390 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
26391 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
26392 Thumb divide instruction. Due to this having the same name as the
26393 previous entry, this will be ignored when doing command-line parsing and
26394 only considered by build attribute selection code. */
26395 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
26396 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
26397 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
26398 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
26399 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
26400 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
26401 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
26402 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
26403 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
26404 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
26405 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
26406 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
26407 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
26408 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
26409 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
26410 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
26411 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
26412 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
26413 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26414 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
26415 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
26416 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26417 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
26418 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
26419 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26420 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26421 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26422 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
26423 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26424 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
26425 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
26426 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26427 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
26429 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
26430 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26431 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
26432 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
26433 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
26437 /* ISA floating-point and Advanced SIMD extensions. */
26438 struct arm_option_fpu_value_table
26441 const arm_feature_set value
;
26444 /* This list should, at a minimum, contain all the fpu names
26445 recognized by GCC. */
26446 static const struct arm_option_fpu_value_table arm_fpus
[] =
26448 {"softfpa", FPU_NONE
},
26449 {"fpe", FPU_ARCH_FPE
},
26450 {"fpe2", FPU_ARCH_FPE
},
26451 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
26452 {"fpa", FPU_ARCH_FPA
},
26453 {"fpa10", FPU_ARCH_FPA
},
26454 {"fpa11", FPU_ARCH_FPA
},
26455 {"arm7500fe", FPU_ARCH_FPA
},
26456 {"softvfp", FPU_ARCH_VFP
},
26457 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
26458 {"vfp", FPU_ARCH_VFP_V2
},
26459 {"vfp9", FPU_ARCH_VFP_V2
},
26460 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
26461 {"vfp10", FPU_ARCH_VFP_V2
},
26462 {"vfp10-r0", FPU_ARCH_VFP_V1
},
26463 {"vfpxd", FPU_ARCH_VFP_V1xD
},
26464 {"vfpv2", FPU_ARCH_VFP_V2
},
26465 {"vfpv3", FPU_ARCH_VFP_V3
},
26466 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
26467 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
26468 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
26469 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
26470 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
26471 {"arm1020t", FPU_ARCH_VFP_V1
},
26472 {"arm1020e", FPU_ARCH_VFP_V2
},
26473 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
26474 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
26475 {"maverick", FPU_ARCH_MAVERICK
},
26476 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26477 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26478 {"neon-fp16", FPU_ARCH_NEON_FP16
},
26479 {"vfpv4", FPU_ARCH_VFP_V4
},
26480 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
26481 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
26482 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
26483 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
26484 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
26485 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
26486 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
26487 {"crypto-neon-fp-armv8",
26488 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
26489 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
26490 {"crypto-neon-fp-armv8.1",
26491 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
26492 {NULL
, ARM_ARCH_NONE
}
26495 struct arm_option_value_table
26501 static const struct arm_option_value_table arm_float_abis
[] =
26503 {"hard", ARM_FLOAT_ABI_HARD
},
26504 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
26505 {"soft", ARM_FLOAT_ABI_SOFT
},
26510 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
26511 static const struct arm_option_value_table arm_eabis
[] =
26513 {"gnu", EF_ARM_EABI_UNKNOWN
},
26514 {"4", EF_ARM_EABI_VER4
},
26515 {"5", EF_ARM_EABI_VER5
},
26520 struct arm_long_option_table
26522 const char * option
; /* Substring to match. */
26523 const char * help
; /* Help information. */
26524 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
26525 const char * deprecated
; /* If non-null, print this message. */
26529 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
26530 arm_feature_set
*ext_set
)
26532 /* We insist on extensions being specified in alphabetical order, and with
26533 extensions being added before being removed. We achieve this by having
26534 the global ARM_EXTENSIONS table in alphabetical order, and using the
26535 ADDING_VALUE variable to indicate whether we are adding an extension (1)
26536 or removing it (0) and only allowing it to change in the order
26538 const struct arm_option_extension_value_table
* opt
= NULL
;
26539 const arm_feature_set arm_any
= ARM_ANY
;
26540 int adding_value
= -1;
26542 while (str
!= NULL
&& *str
!= 0)
26549 as_bad (_("invalid architectural extension"));
26554 ext
= strchr (str
, '+');
26559 len
= strlen (str
);
26561 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
26563 if (adding_value
!= 0)
26566 opt
= arm_extensions
;
26574 if (adding_value
== -1)
26577 opt
= arm_extensions
;
26579 else if (adding_value
!= 1)
26581 as_bad (_("must specify extensions to add before specifying "
26582 "those to remove"));
26589 as_bad (_("missing architectural extension"));
26593 gas_assert (adding_value
!= -1);
26594 gas_assert (opt
!= NULL
);
26596 /* Scan over the options table trying to find an exact match. */
26597 for (; opt
->name
!= NULL
; opt
++)
26598 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26600 int i
, nb_allowed_archs
=
26601 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
26602 /* Check we can apply the extension to this architecture. */
26603 for (i
= 0; i
< nb_allowed_archs
; i
++)
26606 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26608 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
26611 if (i
== nb_allowed_archs
)
26613 as_bad (_("extension does not apply to the base architecture"));
26617 /* Add or remove the extension. */
26619 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
26621 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
26623 /* Allowing Thumb division instructions for ARMv7 in autodetection
26624 rely on this break so that duplicate extensions (extensions
26625 with the same name as a previous extension in the list) are not
26626 considered for command-line parsing. */
26630 if (opt
->name
== NULL
)
26632 /* Did we fail to find an extension because it wasn't specified in
26633 alphabetical order, or because it does not exist? */
26635 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26636 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26639 if (opt
->name
== NULL
)
26640 as_bad (_("unknown architectural extension `%s'"), str
);
26642 as_bad (_("architectural extensions must be specified in "
26643 "alphabetical order"));
26649 /* We should skip the extension we've just matched the next time
26661 arm_parse_cpu (const char *str
)
26663 const struct arm_cpu_option_table
*opt
;
26664 const char *ext
= strchr (str
, '+');
26670 len
= strlen (str
);
26674 as_bad (_("missing cpu name `%s'"), str
);
26678 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
26679 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26681 mcpu_cpu_opt
= &opt
->value
;
26682 if (mcpu_ext_opt
== NULL
)
26683 mcpu_ext_opt
= XNEW (arm_feature_set
);
26684 *mcpu_ext_opt
= opt
->ext
;
26685 mcpu_fpu_opt
= &opt
->default_fpu
;
26686 if (opt
->canonical_name
)
26688 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
26689 strcpy (selected_cpu_name
, opt
->canonical_name
);
26695 if (len
>= sizeof selected_cpu_name
)
26696 len
= (sizeof selected_cpu_name
) - 1;
26698 for (i
= 0; i
< len
; i
++)
26699 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26700 selected_cpu_name
[i
] = 0;
26704 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
);
26709 as_bad (_("unknown cpu `%s'"), str
);
26714 arm_parse_arch (const char *str
)
26716 const struct arm_arch_option_table
*opt
;
26717 const char *ext
= strchr (str
, '+');
26723 len
= strlen (str
);
26727 as_bad (_("missing architecture name `%s'"), str
);
26731 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
26732 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26734 march_cpu_opt
= &opt
->value
;
26735 if (march_ext_opt
== NULL
)
26736 march_ext_opt
= XNEW (arm_feature_set
);
26737 *march_ext_opt
= arm_arch_none
;
26738 march_fpu_opt
= &opt
->default_fpu
;
26739 strcpy (selected_cpu_name
, opt
->name
);
26742 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
);
26747 as_bad (_("unknown architecture `%s'\n"), str
);
26752 arm_parse_fpu (const char * str
)
26754 const struct arm_option_fpu_value_table
* opt
;
26756 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26757 if (streq (opt
->name
, str
))
26759 mfpu_opt
= &opt
->value
;
26763 as_bad (_("unknown floating point format `%s'\n"), str
);
26768 arm_parse_float_abi (const char * str
)
26770 const struct arm_option_value_table
* opt
;
26772 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
26773 if (streq (opt
->name
, str
))
26775 mfloat_abi_opt
= opt
->value
;
26779 as_bad (_("unknown floating point abi `%s'\n"), str
);
26785 arm_parse_eabi (const char * str
)
26787 const struct arm_option_value_table
*opt
;
26789 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
26790 if (streq (opt
->name
, str
))
26792 meabi_flags
= opt
->value
;
26795 as_bad (_("unknown EABI `%s'\n"), str
);
26801 arm_parse_it_mode (const char * str
)
26803 bfd_boolean ret
= TRUE
;
26805 if (streq ("arm", str
))
26806 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
26807 else if (streq ("thumb", str
))
26808 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
26809 else if (streq ("always", str
))
26810 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
26811 else if (streq ("never", str
))
26812 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
26815 as_bad (_("unknown implicit IT mode `%s', should be "\
26816 "arm, thumb, always, or never."), str
);
26824 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
26826 codecomposer_syntax
= TRUE
;
26827 arm_comment_chars
[0] = ';';
26828 arm_line_separator_chars
[0] = 0;
26832 struct arm_long_option_table arm_long_opts
[] =
26834 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
26835 arm_parse_cpu
, NULL
},
26836 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
26837 arm_parse_arch
, NULL
},
26838 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
26839 arm_parse_fpu
, NULL
},
26840 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
26841 arm_parse_float_abi
, NULL
},
26843 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
26844 arm_parse_eabi
, NULL
},
26846 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
26847 arm_parse_it_mode
, NULL
},
26848 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
26849 arm_ccs_mode
, NULL
},
26850 {NULL
, NULL
, 0, NULL
}
26854 md_parse_option (int c
, const char * arg
)
26856 struct arm_option_table
*opt
;
26857 const struct arm_legacy_option_table
*fopt
;
26858 struct arm_long_option_table
*lopt
;
26864 target_big_endian
= 1;
26870 target_big_endian
= 0;
26874 case OPTION_FIX_V4BX
:
26882 #endif /* OBJ_ELF */
26885 /* Listing option. Just ignore these, we don't support additional
26890 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26892 if (c
== opt
->option
[0]
26893 && ((arg
== NULL
&& opt
->option
[1] == 0)
26894 || streq (arg
, opt
->option
+ 1)))
26896 /* If the option is deprecated, tell the user. */
26897 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
26898 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26899 arg
? arg
: "", _(opt
->deprecated
));
26901 if (opt
->var
!= NULL
)
26902 *opt
->var
= opt
->value
;
26908 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
26910 if (c
== fopt
->option
[0]
26911 && ((arg
== NULL
&& fopt
->option
[1] == 0)
26912 || streq (arg
, fopt
->option
+ 1)))
26914 /* If the option is deprecated, tell the user. */
26915 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
26916 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26917 arg
? arg
: "", _(fopt
->deprecated
));
26919 if (fopt
->var
!= NULL
)
26920 *fopt
->var
= &fopt
->value
;
26926 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26928 /* These options are expected to have an argument. */
26929 if (c
== lopt
->option
[0]
26931 && strncmp (arg
, lopt
->option
+ 1,
26932 strlen (lopt
->option
+ 1)) == 0)
26934 /* If the option is deprecated, tell the user. */
26935 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
26936 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
26937 _(lopt
->deprecated
));
26939 /* Call the sup-option parser. */
26940 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
26951 md_show_usage (FILE * fp
)
26953 struct arm_option_table
*opt
;
26954 struct arm_long_option_table
*lopt
;
26956 fprintf (fp
, _(" ARM-specific assembler options:\n"));
26958 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26959 if (opt
->help
!= NULL
)
26960 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
26962 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26963 if (lopt
->help
!= NULL
)
26964 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
26968 -EB assemble code for a big-endian cpu\n"));
26973 -EL assemble code for a little-endian cpu\n"));
26977 --fix-v4bx Allow BX in ARMv4 code\n"));
26981 --fdpic generate an FDPIC object file\n"));
26982 #endif /* OBJ_ELF */
26990 arm_feature_set flags
;
26991 } cpu_arch_ver_table
;
26993 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
26994 chronologically for architectures, with an exception for ARMv6-M and
26995 ARMv6S-M due to legacy reasons. No new architecture should have a
26996 special case. This allows for build attribute selection results to be
26997 stable when new architectures are added. */
26998 static const cpu_arch_ver_table cpu_arch_ver
[] =
27000 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
27001 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
27002 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
27003 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
27004 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
27005 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
27006 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
27007 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
27008 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
27009 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
27010 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
27011 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
27012 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
27013 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
27014 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
27015 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
27016 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
27017 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
27018 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
27019 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
27020 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
27021 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
27022 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
27023 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
27025 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
27026 always selected build attributes to match those of ARMv6-M
27027 (resp. ARMv6S-M). However, due to these architectures being a strict
27028 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
27029 would be selected when fully respecting chronology of architectures.
27030 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
27031 move them before ARMv7 architectures. */
27032 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
27033 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
27035 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
27036 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
27037 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
27038 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
27039 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
27040 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
27041 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
27042 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
27043 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
27044 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
27045 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
27046 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
27047 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
27048 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
27049 {-1, ARM_ARCH_NONE
}
27052 /* Set an attribute if it has not already been set by the user. */
27055 aeabi_set_attribute_int (int tag
, int value
)
27058 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
27059 || !attributes_set_explicitly
[tag
])
27060 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
27064 aeabi_set_attribute_string (int tag
, const char *value
)
27067 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
27068 || !attributes_set_explicitly
[tag
])
27069 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
27072 /* Return whether features in the *NEEDED feature set are available via
27073 extensions for the architecture whose feature set is *ARCH_FSET. */
27076 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
27077 const arm_feature_set
*needed
)
27079 int i
, nb_allowed_archs
;
27080 arm_feature_set ext_fset
;
27081 const struct arm_option_extension_value_table
*opt
;
27083 ext_fset
= arm_arch_none
;
27084 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27086 /* Extension does not provide any feature we need. */
27087 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
27091 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
27092 for (i
= 0; i
< nb_allowed_archs
; i
++)
27095 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
27098 /* Extension is available, add it. */
27099 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
27100 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
27104 /* Can we enable all features in *needed? */
27105 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
27108 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
27109 a given architecture feature set *ARCH_EXT_FSET including extension feature
27110 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
27111 - if true, check for an exact match of the architecture modulo extensions;
27112 - otherwise, select build attribute value of the first superset
27113 architecture released so that results remains stable when new architectures
27115 For -march/-mcpu=all the build attribute value of the most featureful
27116 architecture is returned. Tag_CPU_arch_profile result is returned in
27120 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
27121 const arm_feature_set
*ext_fset
,
27122 char *profile
, int exact_match
)
27124 arm_feature_set arch_fset
;
27125 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
27127 /* Select most featureful architecture with all its extensions if building
27128 for -march=all as the feature sets used to set build attributes. */
27129 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
27131 /* Force revisiting of decision for each new architecture. */
27132 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8M_MAIN
);
27134 return TAG_CPU_ARCH_V8
;
27137 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
27139 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
27141 arm_feature_set known_arch_fset
;
27143 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
27146 /* Base architecture match user-specified architecture and
27147 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
27148 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
27153 /* Base architecture match user-specified architecture only
27154 (eg. ARMv6-M in the same case as above). Record it in case we
27155 find a match with above condition. */
27156 else if (p_ver_ret
== NULL
27157 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
27163 /* Architecture has all features wanted. */
27164 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
27166 arm_feature_set added_fset
;
27168 /* Compute features added by this architecture over the one
27169 recorded in p_ver_ret. */
27170 if (p_ver_ret
!= NULL
)
27171 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
27173 /* First architecture that match incl. with extensions, or the
27174 only difference in features over the recorded match is
27175 features that were optional and are now mandatory. */
27176 if (p_ver_ret
== NULL
27177 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
27183 else if (p_ver_ret
== NULL
)
27185 arm_feature_set needed_ext_fset
;
27187 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
27189 /* Architecture has all features needed when using some
27190 extensions. Record it and continue searching in case there
27191 exist an architecture providing all needed features without
27192 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
27194 if (have_ext_for_needed_feat_p (&known_arch_fset
,
27201 if (p_ver_ret
== NULL
)
27205 /* Tag_CPU_arch_profile. */
27206 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
27207 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
27208 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
27209 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
27211 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
27213 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
27217 return p_ver_ret
->val
;
27220 /* Set the public EABI object attributes. */
27223 aeabi_set_public_attributes (void)
27225 char profile
= '\0';
27228 int fp16_optional
= 0;
27229 int skip_exact_match
= 0;
27230 arm_feature_set flags
, flags_arch
, flags_ext
;
27232 /* Autodetection mode, choose the architecture based the instructions
27234 if (no_cpu_selected ())
27236 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
27238 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
27239 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
27241 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
27242 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
27244 /* Code run during relaxation relies on selected_cpu being set. */
27245 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
27246 flags_ext
= arm_arch_none
;
27247 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
27248 selected_ext
= flags_ext
;
27249 selected_cpu
= flags
;
27251 /* Otherwise, choose the architecture based on the capabilities of the
27255 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
27256 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
27257 flags_ext
= selected_ext
;
27258 flags
= selected_cpu
;
27260 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
27262 /* Allow the user to override the reported architecture. */
27263 if (!ARM_FEATURE_ZERO (selected_object_arch
))
27265 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
27266 flags_ext
= arm_arch_none
;
27269 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
27271 /* When this function is run again after relaxation has happened there is no
27272 way to determine whether an architecture or CPU was specified by the user:
27273 - selected_cpu is set above for relaxation to work;
27274 - march_cpu_opt is not set if only -mcpu or .cpu is used;
27275 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
27276 Therefore, if not in -march=all case we first try an exact match and fall
27277 back to autodetection. */
27278 if (!skip_exact_match
)
27279 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
27281 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
27283 as_bad (_("no architecture contains all the instructions used\n"));
27285 /* Tag_CPU_name. */
27286 if (selected_cpu_name
[0])
27290 q
= selected_cpu_name
;
27291 if (strncmp (q
, "armv", 4) == 0)
27296 for (i
= 0; q
[i
]; i
++)
27297 q
[i
] = TOUPPER (q
[i
]);
27299 aeabi_set_attribute_string (Tag_CPU_name
, q
);
27302 /* Tag_CPU_arch. */
27303 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
27305 /* Tag_CPU_arch_profile. */
27306 if (profile
!= '\0')
27307 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
27309 /* Tag_DSP_extension. */
27310 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
27311 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
27313 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
27314 /* Tag_ARM_ISA_use. */
27315 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
27316 || ARM_FEATURE_ZERO (flags_arch
))
27317 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
27319 /* Tag_THUMB_ISA_use. */
27320 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
27321 || ARM_FEATURE_ZERO (flags_arch
))
27325 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
27326 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
27328 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
27332 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
27335 /* Tag_VFP_arch. */
27336 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
27337 aeabi_set_attribute_int (Tag_VFP_arch
,
27338 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
27340 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
27341 aeabi_set_attribute_int (Tag_VFP_arch
,
27342 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
27344 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
27347 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
27349 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
27351 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
27354 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
27355 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
27356 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
27357 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
27358 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
27360 /* Tag_ABI_HardFP_use. */
27361 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
27362 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
27363 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
27365 /* Tag_WMMX_arch. */
27366 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
27367 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
27368 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
27369 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
27371 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
27372 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
27373 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
27374 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
27375 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
27376 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
27378 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
27380 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
27384 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
27389 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
27390 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
27391 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
27395 We set Tag_DIV_use to two when integer divide instructions have been used
27396 in ARM state, or when Thumb integer divide instructions have been used,
27397 but we have no architecture profile set, nor have we any ARM instructions.
27399 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
27400 by the base architecture.
27402 For new architectures we will have to check these tests. */
27403 gas_assert (arch
<= TAG_CPU_ARCH_V8M_MAIN
);
27404 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
27405 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
27406 aeabi_set_attribute_int (Tag_DIV_use
, 0);
27407 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
27408 || (profile
== '\0'
27409 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
27410 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
27411 aeabi_set_attribute_int (Tag_DIV_use
, 2);
27413 /* Tag_MP_extension_use. */
27414 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
27415 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
27417 /* Tag Virtualization_use. */
27418 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
27420 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
27423 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
27426 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
27427 finished and free extension feature bits which will not be used anymore. */
27430 arm_md_post_relax (void)
27432 aeabi_set_public_attributes ();
27433 XDELETE (mcpu_ext_opt
);
27434 mcpu_ext_opt
= NULL
;
27435 XDELETE (march_ext_opt
);
27436 march_ext_opt
= NULL
;
27439 /* Add the default contents for the .ARM.attributes section. */
27444 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
27447 aeabi_set_public_attributes ();
27449 #endif /* OBJ_ELF */
27451 /* Parse a .cpu directive. */
27454 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
27456 const struct arm_cpu_option_table
*opt
;
27460 name
= input_line_pointer
;
27461 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27462 input_line_pointer
++;
27463 saved_char
= *input_line_pointer
;
27464 *input_line_pointer
= 0;
27466 /* Skip the first "all" entry. */
27467 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
27468 if (streq (opt
->name
, name
))
27470 selected_arch
= opt
->value
;
27471 selected_ext
= opt
->ext
;
27472 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
27473 if (opt
->canonical_name
)
27474 strcpy (selected_cpu_name
, opt
->canonical_name
);
27478 for (i
= 0; opt
->name
[i
]; i
++)
27479 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
27481 selected_cpu_name
[i
] = 0;
27483 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
27485 *input_line_pointer
= saved_char
;
27486 demand_empty_rest_of_line ();
27489 as_bad (_("unknown cpu `%s'"), name
);
27490 *input_line_pointer
= saved_char
;
27491 ignore_rest_of_line ();
27494 /* Parse a .arch directive. */
27497 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
27499 const struct arm_arch_option_table
*opt
;
27503 name
= input_line_pointer
;
27504 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27505 input_line_pointer
++;
27506 saved_char
= *input_line_pointer
;
27507 *input_line_pointer
= 0;
27509 /* Skip the first "all" entry. */
27510 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27511 if (streq (opt
->name
, name
))
27513 selected_arch
= opt
->value
;
27514 selected_ext
= arm_arch_none
;
27515 selected_cpu
= selected_arch
;
27516 strcpy (selected_cpu_name
, opt
->name
);
27517 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
27518 *input_line_pointer
= saved_char
;
27519 demand_empty_rest_of_line ();
27523 as_bad (_("unknown architecture `%s'\n"), name
);
27524 *input_line_pointer
= saved_char
;
27525 ignore_rest_of_line ();
27528 /* Parse a .object_arch directive. */
27531 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
27533 const struct arm_arch_option_table
*opt
;
27537 name
= input_line_pointer
;
27538 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27539 input_line_pointer
++;
27540 saved_char
= *input_line_pointer
;
27541 *input_line_pointer
= 0;
27543 /* Skip the first "all" entry. */
27544 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27545 if (streq (opt
->name
, name
))
27547 selected_object_arch
= opt
->value
;
27548 *input_line_pointer
= saved_char
;
27549 demand_empty_rest_of_line ();
27553 as_bad (_("unknown architecture `%s'\n"), name
);
27554 *input_line_pointer
= saved_char
;
27555 ignore_rest_of_line ();
27558 /* Parse a .arch_extension directive. */
27561 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
27563 const struct arm_option_extension_value_table
*opt
;
27566 int adding_value
= 1;
27568 name
= input_line_pointer
;
27569 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27570 input_line_pointer
++;
27571 saved_char
= *input_line_pointer
;
27572 *input_line_pointer
= 0;
27574 if (strlen (name
) >= 2
27575 && strncmp (name
, "no", 2) == 0)
27581 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27582 if (streq (opt
->name
, name
))
27584 int i
, nb_allowed_archs
=
27585 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
27586 for (i
= 0; i
< nb_allowed_archs
; i
++)
27589 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
27591 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
27595 if (i
== nb_allowed_archs
)
27597 as_bad (_("architectural extension `%s' is not allowed for the "
27598 "current base architecture"), name
);
27603 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
27606 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
27608 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
27609 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
27610 *input_line_pointer
= saved_char
;
27611 demand_empty_rest_of_line ();
27612 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
27613 on this return so that duplicate extensions (extensions with the
27614 same name as a previous extension in the list) are not considered
27615 for command-line parsing. */
27619 if (opt
->name
== NULL
)
27620 as_bad (_("unknown architecture extension `%s'\n"), name
);
27622 *input_line_pointer
= saved_char
;
27623 ignore_rest_of_line ();
27626 /* Parse a .fpu directive. */
27629 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
27631 const struct arm_option_fpu_value_table
*opt
;
27635 name
= input_line_pointer
;
27636 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27637 input_line_pointer
++;
27638 saved_char
= *input_line_pointer
;
27639 *input_line_pointer
= 0;
27641 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
27642 if (streq (opt
->name
, name
))
27644 selected_fpu
= opt
->value
;
27645 #ifndef CPU_DEFAULT
27646 if (no_cpu_selected ())
27647 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
27650 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
27651 *input_line_pointer
= saved_char
;
27652 demand_empty_rest_of_line ();
27656 as_bad (_("unknown floating point format `%s'\n"), name
);
27657 *input_line_pointer
= saved_char
;
27658 ignore_rest_of_line ();
27661 /* Copy symbol information. */
27664 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
27666 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
27670 /* Given a symbolic attribute NAME, return the proper integer value.
27671 Returns -1 if the attribute is not known. */
27674 arm_convert_symbolic_attribute (const char *name
)
27676 static const struct
27681 attribute_table
[] =
27683 /* When you modify this table you should
27684 also modify the list in doc/c-arm.texi. */
27685 #define T(tag) {#tag, tag}
27686 T (Tag_CPU_raw_name
),
27689 T (Tag_CPU_arch_profile
),
27690 T (Tag_ARM_ISA_use
),
27691 T (Tag_THUMB_ISA_use
),
27695 T (Tag_Advanced_SIMD_arch
),
27696 T (Tag_PCS_config
),
27697 T (Tag_ABI_PCS_R9_use
),
27698 T (Tag_ABI_PCS_RW_data
),
27699 T (Tag_ABI_PCS_RO_data
),
27700 T (Tag_ABI_PCS_GOT_use
),
27701 T (Tag_ABI_PCS_wchar_t
),
27702 T (Tag_ABI_FP_rounding
),
27703 T (Tag_ABI_FP_denormal
),
27704 T (Tag_ABI_FP_exceptions
),
27705 T (Tag_ABI_FP_user_exceptions
),
27706 T (Tag_ABI_FP_number_model
),
27707 T (Tag_ABI_align_needed
),
27708 T (Tag_ABI_align8_needed
),
27709 T (Tag_ABI_align_preserved
),
27710 T (Tag_ABI_align8_preserved
),
27711 T (Tag_ABI_enum_size
),
27712 T (Tag_ABI_HardFP_use
),
27713 T (Tag_ABI_VFP_args
),
27714 T (Tag_ABI_WMMX_args
),
27715 T (Tag_ABI_optimization_goals
),
27716 T (Tag_ABI_FP_optimization_goals
),
27717 T (Tag_compatibility
),
27718 T (Tag_CPU_unaligned_access
),
27719 T (Tag_FP_HP_extension
),
27720 T (Tag_VFP_HP_extension
),
27721 T (Tag_ABI_FP_16bit_format
),
27722 T (Tag_MPextension_use
),
27724 T (Tag_nodefaults
),
27725 T (Tag_also_compatible_with
),
27726 T (Tag_conformance
),
27728 T (Tag_Virtualization_use
),
27729 T (Tag_DSP_extension
),
27730 /* We deliberately do not include Tag_MPextension_use_legacy. */
27738 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
27739 if (streq (name
, attribute_table
[i
].name
))
27740 return attribute_table
[i
].tag
;
27745 /* Apply sym value for relocations only in the case that they are for
27746 local symbols in the same segment as the fixup and you have the
27747 respective architectural feature for blx and simple switches. */
27750 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
27753 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27754 /* PR 17444: If the local symbol is in a different section then a reloc
27755 will always be generated for it, so applying the symbol value now
27756 will result in a double offset being stored in the relocation. */
27757 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
27758 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
27760 switch (fixP
->fx_r_type
)
27762 case BFD_RELOC_ARM_PCREL_BLX
:
27763 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27764 if (ARM_IS_FUNC (fixP
->fx_addsy
))
27768 case BFD_RELOC_ARM_PCREL_CALL
:
27769 case BFD_RELOC_THUMB_PCREL_BLX
:
27770 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
27781 #endif /* OBJ_ELF */