1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
188 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_m
=
199 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
201 static const arm_feature_set arm_arch_any
= ARM_ANY
;
202 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
203 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
204 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
206 static const arm_feature_set arm_cext_iwmmxt2
=
207 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
208 static const arm_feature_set arm_cext_iwmmxt
=
209 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
210 static const arm_feature_set arm_cext_xscale
=
211 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
212 static const arm_feature_set arm_cext_maverick
=
213 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
214 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
215 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
216 static const arm_feature_set fpu_vfp_ext_v1xd
=
217 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
218 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
219 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
220 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
221 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
222 static const arm_feature_set fpu_vfp_ext_d32
=
223 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
224 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
225 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
226 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
227 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
228 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
229 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
231 static int mfloat_abi_opt
= -1;
232 /* Record user cpu selection for object attributes. */
233 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
234 /* Must be long enough to hold any of the names in arm_cpus. */
235 static char selected_cpu_name
[16];
238 static int meabi_flags
= EABI_DEFAULT
;
240 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
243 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
248 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
253 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
254 symbolS
* GOT_symbol
;
257 /* 0: assemble for ARM,
258 1: assemble for Thumb,
259 2: assemble for Thumb even though target CPU does not support thumb
261 static int thumb_mode
= 0;
262 /* A value distinct from the possible values for thumb_mode that we
263 can use to record whether thumb_mode has been copied into the
264 tc_frag_data field of a frag. */
265 #define MODE_RECORDED (1 << 4)
267 /* Specifies the intrinsic IT insn behavior mode. */
268 enum implicit_it_mode
270 IMPLICIT_IT_MODE_NEVER
= 0x00,
271 IMPLICIT_IT_MODE_ARM
= 0x01,
272 IMPLICIT_IT_MODE_THUMB
= 0x02,
273 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
275 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
277 /* If unified_syntax is true, we are processing the new unified
278 ARM/Thumb syntax. Important differences from the old ARM mode:
280 - Immediate operands do not require a # prefix.
281 - Conditional affixes always appear at the end of the
282 instruction. (For backward compatibility, those instructions
283 that formerly had them in the middle, continue to accept them
285 - The IT instruction may appear, and if it does is validated
286 against subsequent conditional affixes. It does not generate
289 Important differences from the old Thumb mode:
291 - Immediate operands do not require a # prefix.
292 - Most of the V6T2 instructions are only available in unified mode.
293 - The .N and .W suffixes are recognized and honored (it is an error
294 if they cannot be honored).
295 - All instructions set the flags if and only if they have an 's' affix.
296 - Conditional affixes may be used. They are validated against
297 preceding IT instructions. Unlike ARM mode, you cannot use a
298 conditional affix except in the scope of an IT instruction. */
300 static bfd_boolean unified_syntax
= FALSE
;
315 enum neon_el_type type
;
319 #define NEON_MAX_TYPE_ELS 4
323 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
327 enum it_instruction_type
332 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
333 if inside, should be the last one. */
334 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
335 i.e. BKPT and NOP. */
336 IT_INSN
/* The IT insn has been parsed. */
342 unsigned long instruction
;
346 /* "uncond_value" is set to the value in place of the conditional field in
347 unconditional versions of the instruction, or -1 if nothing is
350 struct neon_type vectype
;
351 /* This does not indicate an actual NEON instruction, only that
352 the mnemonic accepts neon-style type suffixes. */
354 /* Set to the opcode if the instruction needs relaxation.
355 Zero if the instruction is not relaxed. */
359 bfd_reloc_code_real_type type
;
364 enum it_instruction_type it_insn_type
;
370 struct neon_type_el vectype
;
371 unsigned present
: 1; /* Operand present. */
372 unsigned isreg
: 1; /* Operand was a register. */
373 unsigned immisreg
: 1; /* .imm field is a second register. */
374 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
375 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
376 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
377 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
378 instructions. This allows us to disambiguate ARM <-> vector insns. */
379 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
380 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
381 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
382 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
383 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
384 unsigned writeback
: 1; /* Operand has trailing ! */
385 unsigned preind
: 1; /* Preindexed address. */
386 unsigned postind
: 1; /* Postindexed address. */
387 unsigned negative
: 1; /* Index register was negated. */
388 unsigned shifted
: 1; /* Shift applied to operation. */
389 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
393 static struct arm_it inst
;
395 #define NUM_FLOAT_VALS 8
397 const char * fp_const
[] =
399 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
402 /* Number of littlenums required to hold an extended precision number. */
403 #define MAX_LITTLENUMS 6
405 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
415 #define CP_T_X 0x00008000
416 #define CP_T_Y 0x00400000
418 #define CONDS_BIT 0x00100000
419 #define LOAD_BIT 0x00100000
421 #define DOUBLE_LOAD_FLAG 0x00000001
425 const char * template_name
;
429 #define COND_ALWAYS 0xE
433 const char * template_name
;
437 struct asm_barrier_opt
439 const char * template_name
;
443 /* The bit that distinguishes CPSR and SPSR. */
444 #define SPSR_BIT (1 << 22)
446 /* The individual PSR flag bits. */
447 #define PSR_c (1 << 16)
448 #define PSR_x (1 << 17)
449 #define PSR_s (1 << 18)
450 #define PSR_f (1 << 19)
455 bfd_reloc_code_real_type reloc
;
460 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
461 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
466 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
469 /* Bits for DEFINED field in neon_typed_alias. */
470 #define NTA_HASTYPE 1
471 #define NTA_HASINDEX 2
473 struct neon_typed_alias
475 unsigned char defined
;
477 struct neon_type_el eltype
;
480 /* ARM register categories. This includes coprocessor numbers and various
481 architecture extensions' registers. */
507 /* Structure for a hash table entry for a register.
508 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
509 information which states whether a vector type or index is specified (for a
510 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
514 unsigned char number
;
516 unsigned char builtin
;
517 struct neon_typed_alias
* neon
;
520 /* Diagnostics used when we don't get a register of the expected type. */
521 const char * const reg_expected_msgs
[] =
523 N_("ARM register expected"),
524 N_("bad or missing co-processor number"),
525 N_("co-processor register expected"),
526 N_("FPA register expected"),
527 N_("VFP single precision register expected"),
528 N_("VFP/Neon double precision register expected"),
529 N_("Neon quad precision register expected"),
530 N_("VFP single or double precision register expected"),
531 N_("Neon double or quad precision register expected"),
532 N_("VFP single, double or Neon quad precision register expected"),
533 N_("VFP system register expected"),
534 N_("Maverick MVF register expected"),
535 N_("Maverick MVD register expected"),
536 N_("Maverick MVFX register expected"),
537 N_("Maverick MVDX register expected"),
538 N_("Maverick MVAX register expected"),
539 N_("Maverick DSPSC register expected"),
540 N_("iWMMXt data register expected"),
541 N_("iWMMXt control register expected"),
542 N_("iWMMXt scalar register expected"),
543 N_("XScale accumulator register expected"),
546 /* Some well known registers that we refer to directly elsewhere. */
551 /* ARM instructions take 4bytes in the object file, Thumb instructions
557 /* Basic string to match. */
558 const char * template_name
;
560 /* Parameters to instruction. */
561 unsigned int operands
[8];
563 /* Conditional tag - see opcode_lookup. */
564 unsigned int tag
: 4;
566 /* Basic instruction code. */
567 unsigned int avalue
: 28;
569 /* Thumb-format instruction code. */
572 /* Which architecture variant provides this instruction. */
573 const arm_feature_set
* avariant
;
574 const arm_feature_set
* tvariant
;
576 /* Function to call to encode instruction in ARM format. */
577 void (* aencode
) (void);
579 /* Function to call to encode instruction in Thumb format. */
580 void (* tencode
) (void);
583 /* Defines for various bits that we will want to toggle. */
584 #define INST_IMMEDIATE 0x02000000
585 #define OFFSET_REG 0x02000000
586 #define HWOFFSET_IMM 0x00400000
587 #define SHIFT_BY_REG 0x00000010
588 #define PRE_INDEX 0x01000000
589 #define INDEX_UP 0x00800000
590 #define WRITE_BACK 0x00200000
591 #define LDM_TYPE_2_OR_3 0x00400000
592 #define CPSI_MMOD 0x00020000
594 #define LITERAL_MASK 0xf000f000
595 #define OPCODE_MASK 0xfe1fffff
596 #define V4_STR_BIT 0x00000020
598 #define T2_SUBS_PC_LR 0xf3de8f00
600 #define DATA_OP_SHIFT 21
602 #define T2_OPCODE_MASK 0xfe1fffff
603 #define T2_DATA_OP_SHIFT 21
605 /* Codes to distinguish the arithmetic instructions. */
616 #define OPCODE_CMP 10
617 #define OPCODE_CMN 11
618 #define OPCODE_ORR 12
619 #define OPCODE_MOV 13
620 #define OPCODE_BIC 14
621 #define OPCODE_MVN 15
623 #define T2_OPCODE_AND 0
624 #define T2_OPCODE_BIC 1
625 #define T2_OPCODE_ORR 2
626 #define T2_OPCODE_ORN 3
627 #define T2_OPCODE_EOR 4
628 #define T2_OPCODE_ADD 8
629 #define T2_OPCODE_ADC 10
630 #define T2_OPCODE_SBC 11
631 #define T2_OPCODE_SUB 13
632 #define T2_OPCODE_RSB 14
634 #define T_OPCODE_MUL 0x4340
635 #define T_OPCODE_TST 0x4200
636 #define T_OPCODE_CMN 0x42c0
637 #define T_OPCODE_NEG 0x4240
638 #define T_OPCODE_MVN 0x43c0
640 #define T_OPCODE_ADD_R3 0x1800
641 #define T_OPCODE_SUB_R3 0x1a00
642 #define T_OPCODE_ADD_HI 0x4400
643 #define T_OPCODE_ADD_ST 0xb000
644 #define T_OPCODE_SUB_ST 0xb080
645 #define T_OPCODE_ADD_SP 0xa800
646 #define T_OPCODE_ADD_PC 0xa000
647 #define T_OPCODE_ADD_I8 0x3000
648 #define T_OPCODE_SUB_I8 0x3800
649 #define T_OPCODE_ADD_I3 0x1c00
650 #define T_OPCODE_SUB_I3 0x1e00
652 #define T_OPCODE_ASR_R 0x4100
653 #define T_OPCODE_LSL_R 0x4080
654 #define T_OPCODE_LSR_R 0x40c0
655 #define T_OPCODE_ROR_R 0x41c0
656 #define T_OPCODE_ASR_I 0x1000
657 #define T_OPCODE_LSL_I 0x0000
658 #define T_OPCODE_LSR_I 0x0800
660 #define T_OPCODE_MOV_I8 0x2000
661 #define T_OPCODE_CMP_I8 0x2800
662 #define T_OPCODE_CMP_LR 0x4280
663 #define T_OPCODE_MOV_HR 0x4600
664 #define T_OPCODE_CMP_HR 0x4500
666 #define T_OPCODE_LDR_PC 0x4800
667 #define T_OPCODE_LDR_SP 0x9800
668 #define T_OPCODE_STR_SP 0x9000
669 #define T_OPCODE_LDR_IW 0x6800
670 #define T_OPCODE_STR_IW 0x6000
671 #define T_OPCODE_LDR_IH 0x8800
672 #define T_OPCODE_STR_IH 0x8000
673 #define T_OPCODE_LDR_IB 0x7800
674 #define T_OPCODE_STR_IB 0x7000
675 #define T_OPCODE_LDR_RW 0x5800
676 #define T_OPCODE_STR_RW 0x5000
677 #define T_OPCODE_LDR_RH 0x5a00
678 #define T_OPCODE_STR_RH 0x5200
679 #define T_OPCODE_LDR_RB 0x5c00
680 #define T_OPCODE_STR_RB 0x5400
682 #define T_OPCODE_PUSH 0xb400
683 #define T_OPCODE_POP 0xbc00
685 #define T_OPCODE_BRANCH 0xe000
687 #define THUMB_SIZE 2 /* Size of thumb instruction. */
688 #define THUMB_PP_PC_LR 0x0100
689 #define THUMB_LOAD_BIT 0x0800
690 #define THUMB2_LOAD_BIT 0x00100000
692 #define BAD_ARGS _("bad arguments to instruction")
693 #define BAD_SP _("r13 not allowed here")
694 #define BAD_PC _("r15 not allowed here")
695 #define BAD_COND _("instruction cannot be conditional")
696 #define BAD_OVERLAP _("registers may not be the same")
697 #define BAD_HIREG _("lo register required")
698 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
699 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
700 #define BAD_BRANCH _("branch must be last instruction in IT block")
701 #define BAD_NOT_IT _("instruction not allowed in IT block")
702 #define BAD_FPU _("selected FPU does not support instruction")
703 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
704 #define BAD_IT_COND _("incorrect condition in IT block")
705 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
706 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
707 #define BAD_PC_ADDRESSING \
708 _("cannot use register index with PC-relative addressing")
709 #define BAD_PC_WRITEBACK \
710 _("cannot use writeback with PC-relative addressing")
712 static struct hash_control
* arm_ops_hsh
;
713 static struct hash_control
* arm_cond_hsh
;
714 static struct hash_control
* arm_shift_hsh
;
715 static struct hash_control
* arm_psr_hsh
;
716 static struct hash_control
* arm_v7m_psr_hsh
;
717 static struct hash_control
* arm_reg_hsh
;
718 static struct hash_control
* arm_reloc_hsh
;
719 static struct hash_control
* arm_barrier_opt_hsh
;
721 /* Stuff needed to resolve the label ambiguity
730 symbolS
* last_label_seen
;
731 static int label_is_thumb_function_name
= FALSE
;
733 /* Literal pool structure. Held on a per-section
734 and per-sub-section basis. */
736 #define MAX_LITERAL_POOL_SIZE 1024
737 typedef struct literal_pool
739 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
740 unsigned int next_free_entry
;
745 struct literal_pool
* next
;
748 /* Pointer to a linked list of literal pools. */
749 literal_pool
* list_of_pools
= NULL
;
752 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
754 static struct current_it now_it
;
758 now_it_compatible (int cond
)
760 return (cond
& ~1) == (now_it
.cc
& ~1);
764 conditional_insn (void)
766 return inst
.cond
!= COND_ALWAYS
;
769 static int in_it_block (void);
771 static int handle_it_state (void);
773 static void force_automatic_it_block_close (void);
775 static void it_fsm_post_encode (void);
777 #define set_it_insn_type(type) \
780 inst.it_insn_type = type; \
781 if (handle_it_state () == FAIL) \
786 #define set_it_insn_type_nonvoid(type, failret) \
789 inst.it_insn_type = type; \
790 if (handle_it_state () == FAIL) \
795 #define set_it_insn_type_last() \
798 if (inst.cond == COND_ALWAYS) \
799 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
801 set_it_insn_type (INSIDE_IT_LAST_INSN); \
807 /* This array holds the chars that always start a comment. If the
808 pre-processor is disabled, these aren't very useful. */
809 const char comment_chars
[] = "@";
811 /* This array holds the chars that only start a comment at the beginning of
812 a line. If the line seems to have the form '# 123 filename'
813 .line and .file directives will appear in the pre-processed output. */
814 /* Note that input_file.c hand checks for '#' at the beginning of the
815 first line of the input file. This is because the compiler outputs
816 #NO_APP at the beginning of its output. */
817 /* Also note that comments like this one will always work. */
818 const char line_comment_chars
[] = "#";
820 const char line_separator_chars
[] = ";";
822 /* Chars that can be used to separate mant
823 from exp in floating point numbers. */
824 const char EXP_CHARS
[] = "eE";
826 /* Chars that mean this number is a floating point constant. */
830 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
832 /* Prefix characters that indicate the start of an immediate
834 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
836 /* Separator character handling. */
838 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
841 skip_past_char (char ** str
, char c
)
852 #define skip_past_comma(str) skip_past_char (str, ',')
854 /* Arithmetic expressions (possibly involving symbols). */
856 /* Return TRUE if anything in the expression is a bignum. */
859 walk_no_bignums (symbolS
* sp
)
861 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
864 if (symbol_get_value_expression (sp
)->X_add_symbol
)
866 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
867 || (symbol_get_value_expression (sp
)->X_op_symbol
868 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
874 static int in_my_get_expression
= 0;
876 /* Third argument to my_get_expression. */
877 #define GE_NO_PREFIX 0
878 #define GE_IMM_PREFIX 1
879 #define GE_OPT_PREFIX 2
880 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
881 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
882 #define GE_OPT_PREFIX_BIG 3
885 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
890 /* In unified syntax, all prefixes are optional. */
892 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
897 case GE_NO_PREFIX
: break;
899 if (!is_immediate_prefix (**str
))
901 inst
.error
= _("immediate expression requires a # prefix");
907 case GE_OPT_PREFIX_BIG
:
908 if (is_immediate_prefix (**str
))
914 memset (ep
, 0, sizeof (expressionS
));
916 save_in
= input_line_pointer
;
917 input_line_pointer
= *str
;
918 in_my_get_expression
= 1;
919 seg
= expression (ep
);
920 in_my_get_expression
= 0;
922 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
924 /* We found a bad or missing expression in md_operand(). */
925 *str
= input_line_pointer
;
926 input_line_pointer
= save_in
;
927 if (inst
.error
== NULL
)
928 inst
.error
= (ep
->X_op
== O_absent
929 ? _("missing expression") :_("bad expression"));
934 if (seg
!= absolute_section
935 && seg
!= text_section
936 && seg
!= data_section
937 && seg
!= bss_section
938 && seg
!= undefined_section
)
940 inst
.error
= _("bad segment");
941 *str
= input_line_pointer
;
942 input_line_pointer
= save_in
;
949 /* Get rid of any bignums now, so that we don't generate an error for which
950 we can't establish a line number later on. Big numbers are never valid
951 in instructions, which is where this routine is always called. */
952 if (prefix_mode
!= GE_OPT_PREFIX_BIG
953 && (ep
->X_op
== O_big
955 && (walk_no_bignums (ep
->X_add_symbol
)
957 && walk_no_bignums (ep
->X_op_symbol
))))))
959 inst
.error
= _("invalid constant");
960 *str
= input_line_pointer
;
961 input_line_pointer
= save_in
;
965 *str
= input_line_pointer
;
966 input_line_pointer
= save_in
;
970 /* Turn a string in input_line_pointer into a floating point constant
971 of type TYPE, and store the appropriate bytes in *LITP. The number
972 of LITTLENUMS emitted is stored in *SIZEP. An error message is
973 returned, or NULL on OK.
975 Note that fp constants aren't represent in the normal way on the ARM.
976 In big endian mode, things are as expected. However, in little endian
977 mode fp constants are big-endian word-wise, and little-endian byte-wise
978 within the words. For example, (double) 1.1 in big endian mode is
979 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
980 the byte sequence 99 99 f1 3f 9a 99 99 99.
982 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
985 md_atof (int type
, char * litP
, int * sizeP
)
988 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1020 return _("Unrecognized or unsupported floating point constant");
1023 t
= atof_ieee (input_line_pointer
, type
, words
);
1025 input_line_pointer
= t
;
1026 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1028 if (target_big_endian
)
1030 for (i
= 0; i
< prec
; i
++)
1032 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1033 litP
+= sizeof (LITTLENUM_TYPE
);
1038 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1039 for (i
= prec
- 1; i
>= 0; i
--)
1041 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1042 litP
+= sizeof (LITTLENUM_TYPE
);
1045 /* For a 4 byte float the order of elements in `words' is 1 0.
1046 For an 8 byte float the order is 1 0 3 2. */
1047 for (i
= 0; i
< prec
; i
+= 2)
1049 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1050 sizeof (LITTLENUM_TYPE
));
1051 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1052 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1053 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1060 /* We handle all bad expressions here, so that we can report the faulty
1061 instruction in the error message. */
1063 md_operand (expressionS
* exp
)
1065 if (in_my_get_expression
)
1066 exp
->X_op
= O_illegal
;
1069 /* Immediate values. */
1071 /* Generic immediate-value read function for use in directives.
1072 Accepts anything that 'expression' can fold to a constant.
1073 *val receives the number. */
1076 immediate_for_directive (int *val
)
1079 exp
.X_op
= O_illegal
;
1081 if (is_immediate_prefix (*input_line_pointer
))
1083 input_line_pointer
++;
1087 if (exp
.X_op
!= O_constant
)
1089 as_bad (_("expected #constant"));
1090 ignore_rest_of_line ();
1093 *val
= exp
.X_add_number
;
1098 /* Register parsing. */
1100 /* Generic register parser. CCP points to what should be the
1101 beginning of a register name. If it is indeed a valid register
1102 name, advance CCP over it and return the reg_entry structure;
1103 otherwise return NULL. Does not issue diagnostics. */
1105 static struct reg_entry
*
1106 arm_reg_parse_multi (char **ccp
)
1110 struct reg_entry
*reg
;
1112 #ifdef REGISTER_PREFIX
1113 if (*start
!= REGISTER_PREFIX
)
1117 #ifdef OPTIONAL_REGISTER_PREFIX
1118 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1123 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1128 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1130 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1140 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1141 enum arm_reg_type type
)
1143 /* Alternative syntaxes are accepted for a few register classes. */
1150 /* Generic coprocessor register names are allowed for these. */
1151 if (reg
&& reg
->type
== REG_TYPE_CN
)
1156 /* For backward compatibility, a bare number is valid here. */
1158 unsigned long processor
= strtoul (start
, ccp
, 10);
1159 if (*ccp
!= start
&& processor
<= 15)
1163 case REG_TYPE_MMXWC
:
1164 /* WC includes WCG. ??? I'm not sure this is true for all
1165 instructions that take WC registers. */
1166 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1177 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1178 return value is the register number or FAIL. */
1181 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1184 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1187 /* Do not allow a scalar (reg+index) to parse as a register. */
1188 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1191 if (reg
&& reg
->type
== type
)
1194 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1201 /* Parse a Neon type specifier. *STR should point at the leading '.'
1202 character. Does no verification at this stage that the type fits the opcode
1209 Can all be legally parsed by this function.
1211 Fills in neon_type struct pointer with parsed information, and updates STR
1212 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1213 type, FAIL if not. */
1216 parse_neon_type (struct neon_type
*type
, char **str
)
1223 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1225 enum neon_el_type thistype
= NT_untyped
;
1226 unsigned thissize
= -1u;
1233 /* Just a size without an explicit type. */
1237 switch (TOLOWER (*ptr
))
1239 case 'i': thistype
= NT_integer
; break;
1240 case 'f': thistype
= NT_float
; break;
1241 case 'p': thistype
= NT_poly
; break;
1242 case 's': thistype
= NT_signed
; break;
1243 case 'u': thistype
= NT_unsigned
; break;
1245 thistype
= NT_float
;
1250 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1256 /* .f is an abbreviation for .f32. */
1257 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1262 thissize
= strtoul (ptr
, &ptr
, 10);
1264 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1267 as_bad (_("bad size %d in type specifier"), thissize
);
1275 type
->el
[type
->elems
].type
= thistype
;
1276 type
->el
[type
->elems
].size
= thissize
;
1281 /* Empty/missing type is not a successful parse. */
1282 if (type
->elems
== 0)
1290 /* Errors may be set multiple times during parsing or bit encoding
1291 (particularly in the Neon bits), but usually the earliest error which is set
1292 will be the most meaningful. Avoid overwriting it with later (cascading)
1293 errors by calling this function. */
1296 first_error (const char *err
)
1302 /* Parse a single type, e.g. ".s32", leading period included. */
1304 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1307 struct neon_type optype
;
1311 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1313 if (optype
.elems
== 1)
1314 *vectype
= optype
.el
[0];
1317 first_error (_("only one type should be specified for operand"));
1323 first_error (_("vector type expected"));
1335 /* Special meanings for indices (which have a range of 0-7), which will fit into
1338 #define NEON_ALL_LANES 15
1339 #define NEON_INTERLEAVE_LANES 14
1341 /* Parse either a register or a scalar, with an optional type. Return the
1342 register number, and optionally fill in the actual type of the register
1343 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1344 type/index information in *TYPEINFO. */
1347 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1348 enum arm_reg_type
*rtype
,
1349 struct neon_typed_alias
*typeinfo
)
1352 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1353 struct neon_typed_alias atype
;
1354 struct neon_type_el parsetype
;
1358 atype
.eltype
.type
= NT_invtype
;
1359 atype
.eltype
.size
= -1;
1361 /* Try alternate syntax for some types of register. Note these are mutually
1362 exclusive with the Neon syntax extensions. */
1365 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1373 /* Undo polymorphism when a set of register types may be accepted. */
1374 if ((type
== REG_TYPE_NDQ
1375 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1376 || (type
== REG_TYPE_VFSD
1377 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1378 || (type
== REG_TYPE_NSDQ
1379 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1380 || reg
->type
== REG_TYPE_NQ
))
1381 || (type
== REG_TYPE_MMXWC
1382 && (reg
->type
== REG_TYPE_MMXWCG
)))
1383 type
= (enum arm_reg_type
) reg
->type
;
1385 if (type
!= reg
->type
)
1391 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1393 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1395 first_error (_("can't redefine type for operand"));
1398 atype
.defined
|= NTA_HASTYPE
;
1399 atype
.eltype
= parsetype
;
1402 if (skip_past_char (&str
, '[') == SUCCESS
)
1404 if (type
!= REG_TYPE_VFD
)
1406 first_error (_("only D registers may be indexed"));
1410 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1412 first_error (_("can't change index for operand"));
1416 atype
.defined
|= NTA_HASINDEX
;
1418 if (skip_past_char (&str
, ']') == SUCCESS
)
1419 atype
.index
= NEON_ALL_LANES
;
1424 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1426 if (exp
.X_op
!= O_constant
)
1428 first_error (_("constant expression required"));
1432 if (skip_past_char (&str
, ']') == FAIL
)
1435 atype
.index
= exp
.X_add_number
;
1450 /* Like arm_reg_parse, but allow allow the following extra features:
1451 - If RTYPE is non-zero, return the (possibly restricted) type of the
1452 register (e.g. Neon double or quad reg when either has been requested).
1453 - If this is a Neon vector type with additional type information, fill
1454 in the struct pointed to by VECTYPE (if non-NULL).
1455 This function will fault on encountering a scalar. */
1458 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1459 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1461 struct neon_typed_alias atype
;
1463 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1468 /* Do not allow a scalar (reg+index) to parse as a register. */
1469 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1471 first_error (_("register operand expected, but got scalar"));
1476 *vectype
= atype
.eltype
;
1483 #define NEON_SCALAR_REG(X) ((X) >> 4)
1484 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1486 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1487 have enough information to be able to do a good job bounds-checking. So, we
1488 just do easy checks here, and do further checks later. */
1491 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1495 struct neon_typed_alias atype
;
1497 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1499 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1502 if (atype
.index
== NEON_ALL_LANES
)
1504 first_error (_("scalar must have an index"));
1507 else if (atype
.index
>= 64 / elsize
)
1509 first_error (_("scalar index out of range"));
1514 *type
= atype
.eltype
;
1518 return reg
* 16 + atype
.index
;
1521 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1524 parse_reg_list (char ** strp
)
1526 char * str
= * strp
;
1530 /* We come back here if we get ranges concatenated by '+' or '|'. */
1545 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1547 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1557 first_error (_("bad range in register list"));
1561 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1563 if (range
& (1 << i
))
1565 (_("Warning: duplicated register (r%d) in register list"),
1573 if (range
& (1 << reg
))
1574 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1576 else if (reg
<= cur_reg
)
1577 as_tsktsk (_("Warning: register range not in ascending order"));
1582 while (skip_past_comma (&str
) != FAIL
1583 || (in_range
= 1, *str
++ == '-'));
1588 first_error (_("missing `}'"));
1596 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1599 if (exp
.X_op
== O_constant
)
1601 if (exp
.X_add_number
1602 != (exp
.X_add_number
& 0x0000ffff))
1604 inst
.error
= _("invalid register mask");
1608 if ((range
& exp
.X_add_number
) != 0)
1610 int regno
= range
& exp
.X_add_number
;
1613 regno
= (1 << regno
) - 1;
1615 (_("Warning: duplicated register (r%d) in register list"),
1619 range
|= exp
.X_add_number
;
1623 if (inst
.reloc
.type
!= 0)
1625 inst
.error
= _("expression too complex");
1629 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1630 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1631 inst
.reloc
.pc_rel
= 0;
1635 if (*str
== '|' || *str
== '+')
1641 while (another_range
);
1647 /* Types of registers in a list. */
1656 /* Parse a VFP register list. If the string is invalid return FAIL.
1657 Otherwise return the number of registers, and set PBASE to the first
1658 register. Parses registers of type ETYPE.
1659 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1660 - Q registers can be used to specify pairs of D registers
1661 - { } can be omitted from around a singleton register list
1662 FIXME: This is not implemented, as it would require backtracking in
1665 This could be done (the meaning isn't really ambiguous), but doesn't
1666 fit in well with the current parsing framework.
1667 - 32 D registers may be used (also true for VFPv3).
1668 FIXME: Types are ignored in these register lists, which is probably a
1672 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1677 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1681 unsigned long mask
= 0;
1686 inst
.error
= _("expecting {");
1695 regtype
= REG_TYPE_VFS
;
1700 regtype
= REG_TYPE_VFD
;
1703 case REGLIST_NEON_D
:
1704 regtype
= REG_TYPE_NDQ
;
1708 if (etype
!= REGLIST_VFP_S
)
1710 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1711 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1715 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1718 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1725 base_reg
= max_regs
;
1729 int setmask
= 1, addregs
= 1;
1731 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1733 if (new_base
== FAIL
)
1735 first_error (_(reg_expected_msgs
[regtype
]));
1739 if (new_base
>= max_regs
)
1741 first_error (_("register out of range in list"));
1745 /* Note: a value of 2 * n is returned for the register Q<n>. */
1746 if (regtype
== REG_TYPE_NQ
)
1752 if (new_base
< base_reg
)
1753 base_reg
= new_base
;
1755 if (mask
& (setmask
<< new_base
))
1757 first_error (_("invalid register list"));
1761 if ((mask
>> new_base
) != 0 && ! warned
)
1763 as_tsktsk (_("register list not in ascending order"));
1767 mask
|= setmask
<< new_base
;
1770 if (*str
== '-') /* We have the start of a range expression */
1776 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1779 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1783 if (high_range
>= max_regs
)
1785 first_error (_("register out of range in list"));
1789 if (regtype
== REG_TYPE_NQ
)
1790 high_range
= high_range
+ 1;
1792 if (high_range
<= new_base
)
1794 inst
.error
= _("register range not in ascending order");
1798 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1800 if (mask
& (setmask
<< new_base
))
1802 inst
.error
= _("invalid register list");
1806 mask
|= setmask
<< new_base
;
1811 while (skip_past_comma (&str
) != FAIL
);
1815 /* Sanity check -- should have raised a parse error above. */
1816 if (count
== 0 || count
> max_regs
)
1821 /* Final test -- the registers must be consecutive. */
1823 for (i
= 0; i
< count
; i
++)
1825 if ((mask
& (1u << i
)) == 0)
1827 inst
.error
= _("non-contiguous register range");
1837 /* True if two alias types are the same. */
1840 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1848 if (a
->defined
!= b
->defined
)
1851 if ((a
->defined
& NTA_HASTYPE
) != 0
1852 && (a
->eltype
.type
!= b
->eltype
.type
1853 || a
->eltype
.size
!= b
->eltype
.size
))
1856 if ((a
->defined
& NTA_HASINDEX
) != 0
1857 && (a
->index
!= b
->index
))
1863 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1864 The base register is put in *PBASE.
1865 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1867 The register stride (minus one) is put in bit 4 of the return value.
1868 Bits [6:5] encode the list length (minus one).
1869 The type of the list elements is put in *ELTYPE, if non-NULL. */
1871 #define NEON_LANE(X) ((X) & 0xf)
1872 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1873 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1876 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1877 struct neon_type_el
*eltype
)
1884 int leading_brace
= 0;
1885 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1886 const char *const incr_error
= _("register stride must be 1 or 2");
1887 const char *const type_error
= _("mismatched element/structure types in list");
1888 struct neon_typed_alias firsttype
;
1890 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1895 struct neon_typed_alias atype
;
1896 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1900 first_error (_(reg_expected_msgs
[rtype
]));
1907 if (rtype
== REG_TYPE_NQ
)
1913 else if (reg_incr
== -1)
1915 reg_incr
= getreg
- base_reg
;
1916 if (reg_incr
< 1 || reg_incr
> 2)
1918 first_error (_(incr_error
));
1922 else if (getreg
!= base_reg
+ reg_incr
* count
)
1924 first_error (_(incr_error
));
1928 if (! neon_alias_types_same (&atype
, &firsttype
))
1930 first_error (_(type_error
));
1934 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1938 struct neon_typed_alias htype
;
1939 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1941 lane
= NEON_INTERLEAVE_LANES
;
1942 else if (lane
!= NEON_INTERLEAVE_LANES
)
1944 first_error (_(type_error
));
1949 else if (reg_incr
!= 1)
1951 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1955 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1958 first_error (_(reg_expected_msgs
[rtype
]));
1961 if (! neon_alias_types_same (&htype
, &firsttype
))
1963 first_error (_(type_error
));
1966 count
+= hireg
+ dregs
- getreg
;
1970 /* If we're using Q registers, we can't use [] or [n] syntax. */
1971 if (rtype
== REG_TYPE_NQ
)
1977 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1981 else if (lane
!= atype
.index
)
1983 first_error (_(type_error
));
1987 else if (lane
== -1)
1988 lane
= NEON_INTERLEAVE_LANES
;
1989 else if (lane
!= NEON_INTERLEAVE_LANES
)
1991 first_error (_(type_error
));
1996 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1998 /* No lane set by [x]. We must be interleaving structures. */
2000 lane
= NEON_INTERLEAVE_LANES
;
2003 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2004 || (count
> 1 && reg_incr
== -1))
2006 first_error (_("error parsing element/structure list"));
2010 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2012 first_error (_("expected }"));
2020 *eltype
= firsttype
.eltype
;
2025 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2028 /* Parse an explicit relocation suffix on an expression. This is
2029 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2030 arm_reloc_hsh contains no entries, so this function can only
2031 succeed if there is no () after the word. Returns -1 on error,
2032 BFD_RELOC_UNUSED if there wasn't any suffix. */
2034 parse_reloc (char **str
)
2036 struct reloc_entry
*r
;
2040 return BFD_RELOC_UNUSED
;
2045 while (*q
&& *q
!= ')' && *q
!= ',')
2050 if ((r
= (struct reloc_entry
*)
2051 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2058 /* Directives: register aliases. */
2060 static struct reg_entry
*
2061 insert_reg_alias (char *str
, int number
, int type
)
2063 struct reg_entry
*new_reg
;
2066 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2068 if (new_reg
->builtin
)
2069 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2071 /* Only warn about a redefinition if it's not defined as the
2073 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2074 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2079 name
= xstrdup (str
);
2080 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2082 new_reg
->name
= name
;
2083 new_reg
->number
= number
;
2084 new_reg
->type
= type
;
2085 new_reg
->builtin
= FALSE
;
2086 new_reg
->neon
= NULL
;
2088 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2095 insert_neon_reg_alias (char *str
, int number
, int type
,
2096 struct neon_typed_alias
*atype
)
2098 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2102 first_error (_("attempt to redefine typed alias"));
2108 reg
->neon
= (struct neon_typed_alias
*)
2109 xmalloc (sizeof (struct neon_typed_alias
));
2110 *reg
->neon
= *atype
;
2114 /* Look for the .req directive. This is of the form:
2116 new_register_name .req existing_register_name
2118 If we find one, or if it looks sufficiently like one that we want to
2119 handle any error here, return TRUE. Otherwise return FALSE. */
2122 create_register_alias (char * newname
, char *p
)
2124 struct reg_entry
*old
;
2125 char *oldname
, *nbuf
;
2128 /* The input scrubber ensures that whitespace after the mnemonic is
2129 collapsed to single spaces. */
2131 if (strncmp (oldname
, " .req ", 6) != 0)
2135 if (*oldname
== '\0')
2138 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2141 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2145 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2146 the desired alias name, and p points to its end. If not, then
2147 the desired alias name is in the global original_case_string. */
2148 #ifdef TC_CASE_SENSITIVE
2151 newname
= original_case_string
;
2152 nlen
= strlen (newname
);
2155 nbuf
= (char *) alloca (nlen
+ 1);
2156 memcpy (nbuf
, newname
, nlen
);
2159 /* Create aliases under the new name as stated; an all-lowercase
2160 version of the new name; and an all-uppercase version of the new
2162 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2164 for (p
= nbuf
; *p
; p
++)
2167 if (strncmp (nbuf
, newname
, nlen
))
2169 /* If this attempt to create an additional alias fails, do not bother
2170 trying to create the all-lower case alias. We will fail and issue
2171 a second, duplicate error message. This situation arises when the
2172 programmer does something like:
2175 The second .req creates the "Foo" alias but then fails to create
2176 the artificial FOO alias because it has already been created by the
2178 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2182 for (p
= nbuf
; *p
; p
++)
2185 if (strncmp (nbuf
, newname
, nlen
))
2186 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2192 /* Create a Neon typed/indexed register alias using directives, e.g.:
2197 These typed registers can be used instead of the types specified after the
2198 Neon mnemonic, so long as all operands given have types. Types can also be
2199 specified directly, e.g.:
2200 vadd d0.s32, d1.s32, d2.s32 */
2203 create_neon_reg_alias (char *newname
, char *p
)
2205 enum arm_reg_type basetype
;
2206 struct reg_entry
*basereg
;
2207 struct reg_entry mybasereg
;
2208 struct neon_type ntype
;
2209 struct neon_typed_alias typeinfo
;
2210 char *namebuf
, *nameend
;
2213 typeinfo
.defined
= 0;
2214 typeinfo
.eltype
.type
= NT_invtype
;
2215 typeinfo
.eltype
.size
= -1;
2216 typeinfo
.index
= -1;
2220 if (strncmp (p
, " .dn ", 5) == 0)
2221 basetype
= REG_TYPE_VFD
;
2222 else if (strncmp (p
, " .qn ", 5) == 0)
2223 basetype
= REG_TYPE_NQ
;
2232 basereg
= arm_reg_parse_multi (&p
);
2234 if (basereg
&& basereg
->type
!= basetype
)
2236 as_bad (_("bad type for register"));
2240 if (basereg
== NULL
)
2243 /* Try parsing as an integer. */
2244 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2245 if (exp
.X_op
!= O_constant
)
2247 as_bad (_("expression must be constant"));
2250 basereg
= &mybasereg
;
2251 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2257 typeinfo
= *basereg
->neon
;
2259 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2261 /* We got a type. */
2262 if (typeinfo
.defined
& NTA_HASTYPE
)
2264 as_bad (_("can't redefine the type of a register alias"));
2268 typeinfo
.defined
|= NTA_HASTYPE
;
2269 if (ntype
.elems
!= 1)
2271 as_bad (_("you must specify a single type only"));
2274 typeinfo
.eltype
= ntype
.el
[0];
2277 if (skip_past_char (&p
, '[') == SUCCESS
)
2280 /* We got a scalar index. */
2282 if (typeinfo
.defined
& NTA_HASINDEX
)
2284 as_bad (_("can't redefine the index of a scalar alias"));
2288 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2290 if (exp
.X_op
!= O_constant
)
2292 as_bad (_("scalar index must be constant"));
2296 typeinfo
.defined
|= NTA_HASINDEX
;
2297 typeinfo
.index
= exp
.X_add_number
;
2299 if (skip_past_char (&p
, ']') == FAIL
)
2301 as_bad (_("expecting ]"));
2306 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2307 the desired alias name, and p points to its end. If not, then
2308 the desired alias name is in the global original_case_string. */
2309 #ifdef TC_CASE_SENSITIVE
2310 namelen
= nameend
- newname
;
2312 newname
= original_case_string
;
2313 namelen
= strlen (newname
);
2316 namebuf
= (char *) alloca (namelen
+ 1);
2317 strncpy (namebuf
, newname
, namelen
);
2318 namebuf
[namelen
] = '\0';
2320 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2321 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2323 /* Insert name in all uppercase. */
2324 for (p
= namebuf
; *p
; p
++)
2327 if (strncmp (namebuf
, newname
, namelen
))
2328 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2329 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2331 /* Insert name in all lowercase. */
2332 for (p
= namebuf
; *p
; p
++)
2335 if (strncmp (namebuf
, newname
, namelen
))
2336 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2337 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2342 /* Should never be called, as .req goes between the alias and the
2343 register name, not at the beginning of the line. */
2346 s_req (int a ATTRIBUTE_UNUSED
)
2348 as_bad (_("invalid syntax for .req directive"));
2352 s_dn (int a ATTRIBUTE_UNUSED
)
2354 as_bad (_("invalid syntax for .dn directive"));
2358 s_qn (int a ATTRIBUTE_UNUSED
)
2360 as_bad (_("invalid syntax for .qn directive"));
2363 /* The .unreq directive deletes an alias which was previously defined
2364 by .req. For example:
2370 s_unreq (int a ATTRIBUTE_UNUSED
)
2375 name
= input_line_pointer
;
2377 while (*input_line_pointer
!= 0
2378 && *input_line_pointer
!= ' '
2379 && *input_line_pointer
!= '\n')
2380 ++input_line_pointer
;
2382 saved_char
= *input_line_pointer
;
2383 *input_line_pointer
= 0;
2386 as_bad (_("invalid syntax for .unreq directive"));
2389 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2393 as_bad (_("unknown register alias '%s'"), name
);
2394 else if (reg
->builtin
)
2395 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2402 hash_delete (arm_reg_hsh
, name
, FALSE
);
2403 free ((char *) reg
->name
);
2408 /* Also locate the all upper case and all lower case versions.
2409 Do not complain if we cannot find one or the other as it
2410 was probably deleted above. */
2412 nbuf
= strdup (name
);
2413 for (p
= nbuf
; *p
; p
++)
2415 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2418 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2419 free ((char *) reg
->name
);
2425 for (p
= nbuf
; *p
; p
++)
2427 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2430 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2431 free ((char *) reg
->name
);
2441 *input_line_pointer
= saved_char
;
2442 demand_empty_rest_of_line ();
2445 /* Directives: Instruction set selection. */
2448 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2449 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2450 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2451 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2453 /* Create a new mapping symbol for the transition to STATE. */
2456 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2459 const char * symname
;
2466 type
= BSF_NO_FLAGS
;
2470 type
= BSF_NO_FLAGS
;
2474 type
= BSF_NO_FLAGS
;
2480 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2481 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2486 THUMB_SET_FUNC (symbolP
, 0);
2487 ARM_SET_THUMB (symbolP
, 0);
2488 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2492 THUMB_SET_FUNC (symbolP
, 1);
2493 ARM_SET_THUMB (symbolP
, 1);
2494 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2502 /* Save the mapping symbols for future reference. Also check that
2503 we do not place two mapping symbols at the same offset within a
2504 frag. We'll handle overlap between frags in
2505 check_mapping_symbols.
2507 If .fill or other data filling directive generates zero sized data,
2508 the mapping symbol for the following code will have the same value
2509 as the one generated for the data filling directive. In this case,
2510 we replace the old symbol with the new one at the same address. */
2513 if (frag
->tc_frag_data
.first_map
!= NULL
)
2515 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2516 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2518 frag
->tc_frag_data
.first_map
= symbolP
;
2520 if (frag
->tc_frag_data
.last_map
!= NULL
)
2522 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2523 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2524 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2526 frag
->tc_frag_data
.last_map
= symbolP
;
2529 /* We must sometimes convert a region marked as code to data during
2530 code alignment, if an odd number of bytes have to be padded. The
2531 code mapping symbol is pushed to an aligned address. */
2534 insert_data_mapping_symbol (enum mstate state
,
2535 valueT value
, fragS
*frag
, offsetT bytes
)
2537 /* If there was already a mapping symbol, remove it. */
2538 if (frag
->tc_frag_data
.last_map
!= NULL
2539 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2541 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2545 know (frag
->tc_frag_data
.first_map
== symp
);
2546 frag
->tc_frag_data
.first_map
= NULL
;
2548 frag
->tc_frag_data
.last_map
= NULL
;
2549 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2552 make_mapping_symbol (MAP_DATA
, value
, frag
);
2553 make_mapping_symbol (state
, value
+ bytes
, frag
);
2556 static void mapping_state_2 (enum mstate state
, int max_chars
);
2558 /* Set the mapping state to STATE. Only call this when about to
2559 emit some STATE bytes to the file. */
2562 mapping_state (enum mstate state
)
2564 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2566 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2568 if (mapstate
== state
)
2569 /* The mapping symbol has already been emitted.
2570 There is nothing else to do. */
2572 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2573 /* This case will be evaluated later in the next else. */
2575 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2576 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2578 /* Only add the symbol if the offset is > 0:
2579 if we're at the first frag, check it's size > 0;
2580 if we're not at the first frag, then for sure
2581 the offset is > 0. */
2582 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2583 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2586 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2589 mapping_state_2 (state
, 0);
2593 /* Same as mapping_state, but MAX_CHARS bytes have already been
2594 allocated. Put the mapping symbol that far back. */
2597 mapping_state_2 (enum mstate state
, int max_chars
)
2599 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2601 if (!SEG_NORMAL (now_seg
))
2604 if (mapstate
== state
)
2605 /* The mapping symbol has already been emitted.
2606 There is nothing else to do. */
2609 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2610 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2613 #define mapping_state(x) ((void)0)
2614 #define mapping_state_2(x, y) ((void)0)
2617 /* Find the real, Thumb encoded start of a Thumb function. */
2621 find_real_start (symbolS
* symbolP
)
2624 const char * name
= S_GET_NAME (symbolP
);
2625 symbolS
* new_target
;
2627 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2628 #define STUB_NAME ".real_start_of"
2633 /* The compiler may generate BL instructions to local labels because
2634 it needs to perform a branch to a far away location. These labels
2635 do not have a corresponding ".real_start_of" label. We check
2636 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2637 the ".real_start_of" convention for nonlocal branches. */
2638 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2641 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2642 new_target
= symbol_find (real_start
);
2644 if (new_target
== NULL
)
2646 as_warn (_("Failed to find real start of function: %s\n"), name
);
2647 new_target
= symbolP
;
2655 opcode_select (int width
)
2662 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2663 as_bad (_("selected processor does not support THUMB opcodes"));
2666 /* No need to force the alignment, since we will have been
2667 coming from ARM mode, which is word-aligned. */
2668 record_alignment (now_seg
, 1);
2675 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2676 as_bad (_("selected processor does not support ARM opcodes"));
2681 frag_align (2, 0, 0);
2683 record_alignment (now_seg
, 1);
2688 as_bad (_("invalid instruction size selected (%d)"), width
);
2693 s_arm (int ignore ATTRIBUTE_UNUSED
)
2696 demand_empty_rest_of_line ();
2700 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2703 demand_empty_rest_of_line ();
2707 s_code (int unused ATTRIBUTE_UNUSED
)
2711 temp
= get_absolute_expression ();
2716 opcode_select (temp
);
2720 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2725 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2727 /* If we are not already in thumb mode go into it, EVEN if
2728 the target processor does not support thumb instructions.
2729 This is used by gcc/config/arm/lib1funcs.asm for example
2730 to compile interworking support functions even if the
2731 target processor should not support interworking. */
2735 record_alignment (now_seg
, 1);
2738 demand_empty_rest_of_line ();
2742 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2746 /* The following label is the name/address of the start of a Thumb function.
2747 We need to know this for the interworking support. */
2748 label_is_thumb_function_name
= TRUE
;
2751 /* Perform a .set directive, but also mark the alias as
2752 being a thumb function. */
2755 s_thumb_set (int equiv
)
2757 /* XXX the following is a duplicate of the code for s_set() in read.c
2758 We cannot just call that code as we need to get at the symbol that
2765 /* Especial apologies for the random logic:
2766 This just grew, and could be parsed much more simply!
2768 name
= input_line_pointer
;
2769 delim
= get_symbol_end ();
2770 end_name
= input_line_pointer
;
2773 if (*input_line_pointer
!= ',')
2776 as_bad (_("expected comma after name \"%s\""), name
);
2778 ignore_rest_of_line ();
2782 input_line_pointer
++;
2785 if (name
[0] == '.' && name
[1] == '\0')
2787 /* XXX - this should not happen to .thumb_set. */
2791 if ((symbolP
= symbol_find (name
)) == NULL
2792 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2795 /* When doing symbol listings, play games with dummy fragments living
2796 outside the normal fragment chain to record the file and line info
2798 if (listing
& LISTING_SYMBOLS
)
2800 extern struct list_info_struct
* listing_tail
;
2801 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2803 memset (dummy_frag
, 0, sizeof (fragS
));
2804 dummy_frag
->fr_type
= rs_fill
;
2805 dummy_frag
->line
= listing_tail
;
2806 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2807 dummy_frag
->fr_symbol
= symbolP
;
2811 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2814 /* "set" symbols are local unless otherwise specified. */
2815 SF_SET_LOCAL (symbolP
);
2816 #endif /* OBJ_COFF */
2817 } /* Make a new symbol. */
2819 symbol_table_insert (symbolP
);
2824 && S_IS_DEFINED (symbolP
)
2825 && S_GET_SEGMENT (symbolP
) != reg_section
)
2826 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2828 pseudo_set (symbolP
);
2830 demand_empty_rest_of_line ();
2832 /* XXX Now we come to the Thumb specific bit of code. */
2834 THUMB_SET_FUNC (symbolP
, 1);
2835 ARM_SET_THUMB (symbolP
, 1);
2836 #if defined OBJ_ELF || defined OBJ_COFF
2837 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2841 /* Directives: Mode selection. */
2843 /* .syntax [unified|divided] - choose the new unified syntax
2844 (same for Arm and Thumb encoding, modulo slight differences in what
2845 can be represented) or the old divergent syntax for each mode. */
2847 s_syntax (int unused ATTRIBUTE_UNUSED
)
2851 name
= input_line_pointer
;
2852 delim
= get_symbol_end ();
2854 if (!strcasecmp (name
, "unified"))
2855 unified_syntax
= TRUE
;
2856 else if (!strcasecmp (name
, "divided"))
2857 unified_syntax
= FALSE
;
2860 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2863 *input_line_pointer
= delim
;
2864 demand_empty_rest_of_line ();
2867 /* Directives: sectioning and alignment. */
2869 /* Same as s_align_ptwo but align 0 => align 2. */
2872 s_align (int unused ATTRIBUTE_UNUSED
)
2877 long max_alignment
= 15;
2879 temp
= get_absolute_expression ();
2880 if (temp
> max_alignment
)
2881 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2884 as_bad (_("alignment negative. 0 assumed."));
2888 if (*input_line_pointer
== ',')
2890 input_line_pointer
++;
2891 temp_fill
= get_absolute_expression ();
2903 /* Only make a frag if we HAVE to. */
2904 if (temp
&& !need_pass_2
)
2906 if (!fill_p
&& subseg_text_p (now_seg
))
2907 frag_align_code (temp
, 0);
2909 frag_align (temp
, (int) temp_fill
, 0);
2911 demand_empty_rest_of_line ();
2913 record_alignment (now_seg
, temp
);
2917 s_bss (int ignore ATTRIBUTE_UNUSED
)
2919 /* We don't support putting frags in the BSS segment, we fake it by
2920 marking in_bss, then looking at s_skip for clues. */
2921 subseg_set (bss_section
, 0);
2922 demand_empty_rest_of_line ();
2924 #ifdef md_elf_section_change_hook
2925 md_elf_section_change_hook ();
2930 s_even (int ignore ATTRIBUTE_UNUSED
)
2932 /* Never make frag if expect extra pass. */
2934 frag_align (1, 0, 0);
2936 record_alignment (now_seg
, 1);
2938 demand_empty_rest_of_line ();
2941 /* Directives: Literal pools. */
2943 static literal_pool
*
2944 find_literal_pool (void)
2946 literal_pool
* pool
;
2948 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2950 if (pool
->section
== now_seg
2951 && pool
->sub_section
== now_subseg
)
2958 static literal_pool
*
2959 find_or_make_literal_pool (void)
2961 /* Next literal pool ID number. */
2962 static unsigned int latest_pool_num
= 1;
2963 literal_pool
* pool
;
2965 pool
= find_literal_pool ();
2969 /* Create a new pool. */
2970 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2974 pool
->next_free_entry
= 0;
2975 pool
->section
= now_seg
;
2976 pool
->sub_section
= now_subseg
;
2977 pool
->next
= list_of_pools
;
2978 pool
->symbol
= NULL
;
2980 /* Add it to the list. */
2981 list_of_pools
= pool
;
2984 /* New pools, and emptied pools, will have a NULL symbol. */
2985 if (pool
->symbol
== NULL
)
2987 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2988 (valueT
) 0, &zero_address_frag
);
2989 pool
->id
= latest_pool_num
++;
2996 /* Add the literal in the global 'inst'
2997 structure to the relevant literal pool. */
3000 add_to_lit_pool (void)
3002 literal_pool
* pool
;
3005 pool
= find_or_make_literal_pool ();
3007 /* Check if this literal value is already in the pool. */
3008 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3010 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3011 && (inst
.reloc
.exp
.X_op
== O_constant
)
3012 && (pool
->literals
[entry
].X_add_number
3013 == inst
.reloc
.exp
.X_add_number
)
3014 && (pool
->literals
[entry
].X_unsigned
3015 == inst
.reloc
.exp
.X_unsigned
))
3018 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3019 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3020 && (pool
->literals
[entry
].X_add_number
3021 == inst
.reloc
.exp
.X_add_number
)
3022 && (pool
->literals
[entry
].X_add_symbol
3023 == inst
.reloc
.exp
.X_add_symbol
)
3024 && (pool
->literals
[entry
].X_op_symbol
3025 == inst
.reloc
.exp
.X_op_symbol
))
3029 /* Do we need to create a new entry? */
3030 if (entry
== pool
->next_free_entry
)
3032 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3034 inst
.error
= _("literal pool overflow");
3038 pool
->literals
[entry
] = inst
.reloc
.exp
;
3039 pool
->next_free_entry
+= 1;
3042 inst
.reloc
.exp
.X_op
= O_symbol
;
3043 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3044 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3049 /* Can't use symbol_new here, so have to create a symbol and then at
3050 a later date assign it a value. Thats what these functions do. */
3053 symbol_locate (symbolS
* symbolP
,
3054 const char * name
, /* It is copied, the caller can modify. */
3055 segT segment
, /* Segment identifier (SEG_<something>). */
3056 valueT valu
, /* Symbol value. */
3057 fragS
* frag
) /* Associated fragment. */
3059 unsigned int name_length
;
3060 char * preserved_copy_of_name
;
3062 name_length
= strlen (name
) + 1; /* +1 for \0. */
3063 obstack_grow (¬es
, name
, name_length
);
3064 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3066 #ifdef tc_canonicalize_symbol_name
3067 preserved_copy_of_name
=
3068 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3071 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3073 S_SET_SEGMENT (symbolP
, segment
);
3074 S_SET_VALUE (symbolP
, valu
);
3075 symbol_clear_list_pointers (symbolP
);
3077 symbol_set_frag (symbolP
, frag
);
3079 /* Link to end of symbol chain. */
3081 extern int symbol_table_frozen
;
3083 if (symbol_table_frozen
)
3087 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3089 obj_symbol_new_hook (symbolP
);
3091 #ifdef tc_symbol_new_hook
3092 tc_symbol_new_hook (symbolP
);
3096 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3097 #endif /* DEBUG_SYMS */
3102 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3105 literal_pool
* pool
;
3108 pool
= find_literal_pool ();
3110 || pool
->symbol
== NULL
3111 || pool
->next_free_entry
== 0)
3114 mapping_state (MAP_DATA
);
3116 /* Align pool as you have word accesses.
3117 Only make a frag if we have to. */
3119 frag_align (2, 0, 0);
3121 record_alignment (now_seg
, 2);
3123 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3125 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3126 (valueT
) frag_now_fix (), frag_now
);
3127 symbol_table_insert (pool
->symbol
);
3129 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3131 #if defined OBJ_COFF || defined OBJ_ELF
3132 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3135 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3136 /* First output the expression in the instruction to the pool. */
3137 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3139 /* Mark the pool as empty. */
3140 pool
->next_free_entry
= 0;
3141 pool
->symbol
= NULL
;
3145 /* Forward declarations for functions below, in the MD interface
3147 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3148 static valueT
create_unwind_entry (int);
3149 static void start_unwind_section (const segT
, int);
3150 static void add_unwind_opcode (valueT
, int);
3151 static void flush_pending_unwind (void);
3153 /* Directives: Data. */
3156 s_arm_elf_cons (int nbytes
)
3160 #ifdef md_flush_pending_output
3161 md_flush_pending_output ();
3164 if (is_it_end_of_statement ())
3166 demand_empty_rest_of_line ();
3170 #ifdef md_cons_align
3171 md_cons_align (nbytes
);
3174 mapping_state (MAP_DATA
);
3178 char *base
= input_line_pointer
;
3182 if (exp
.X_op
!= O_symbol
)
3183 emit_expr (&exp
, (unsigned int) nbytes
);
3186 char *before_reloc
= input_line_pointer
;
3187 reloc
= parse_reloc (&input_line_pointer
);
3190 as_bad (_("unrecognized relocation suffix"));
3191 ignore_rest_of_line ();
3194 else if (reloc
== BFD_RELOC_UNUSED
)
3195 emit_expr (&exp
, (unsigned int) nbytes
);
3198 reloc_howto_type
*howto
= (reloc_howto_type
*)
3199 bfd_reloc_type_lookup (stdoutput
,
3200 (bfd_reloc_code_real_type
) reloc
);
3201 int size
= bfd_get_reloc_size (howto
);
3203 if (reloc
== BFD_RELOC_ARM_PLT32
)
3205 as_bad (_("(plt) is only valid on branch targets"));
3206 reloc
= BFD_RELOC_UNUSED
;
3211 as_bad (_("%s relocations do not fit in %d bytes"),
3212 howto
->name
, nbytes
);
3215 /* We've parsed an expression stopping at O_symbol.
3216 But there may be more expression left now that we
3217 have parsed the relocation marker. Parse it again.
3218 XXX Surely there is a cleaner way to do this. */
3219 char *p
= input_line_pointer
;
3221 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3222 memcpy (save_buf
, base
, input_line_pointer
- base
);
3223 memmove (base
+ (input_line_pointer
- before_reloc
),
3224 base
, before_reloc
- base
);
3226 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3228 memcpy (base
, save_buf
, p
- base
);
3230 offset
= nbytes
- size
;
3231 p
= frag_more ((int) nbytes
);
3232 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3233 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3238 while (*input_line_pointer
++ == ',');
3240 /* Put terminator back into stream. */
3241 input_line_pointer
--;
3242 demand_empty_rest_of_line ();
3245 /* Emit an expression containing a 32-bit thumb instruction.
3246 Implementation based on put_thumb32_insn. */
3249 emit_thumb32_expr (expressionS
* exp
)
3251 expressionS exp_high
= *exp
;
3253 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3254 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3255 exp
->X_add_number
&= 0xffff;
3256 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3259 /* Guess the instruction size based on the opcode. */
3262 thumb_insn_size (int opcode
)
3264 if ((unsigned int) opcode
< 0xe800u
)
3266 else if ((unsigned int) opcode
>= 0xe8000000u
)
3273 emit_insn (expressionS
*exp
, int nbytes
)
3277 if (exp
->X_op
== O_constant
)
3282 size
= thumb_insn_size (exp
->X_add_number
);
3286 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3288 as_bad (_(".inst.n operand too big. "\
3289 "Use .inst.w instead"));
3294 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3295 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3297 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3299 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3300 emit_thumb32_expr (exp
);
3302 emit_expr (exp
, (unsigned int) size
);
3304 it_fsm_post_encode ();
3308 as_bad (_("cannot determine Thumb instruction size. " \
3309 "Use .inst.n/.inst.w instead"));
3312 as_bad (_("constant expression required"));
3317 /* Like s_arm_elf_cons but do not use md_cons_align and
3318 set the mapping state to MAP_ARM/MAP_THUMB. */
3321 s_arm_elf_inst (int nbytes
)
3323 if (is_it_end_of_statement ())
3325 demand_empty_rest_of_line ();
3329 /* Calling mapping_state () here will not change ARM/THUMB,
3330 but will ensure not to be in DATA state. */
3333 mapping_state (MAP_THUMB
);
3338 as_bad (_("width suffixes are invalid in ARM mode"));
3339 ignore_rest_of_line ();
3345 mapping_state (MAP_ARM
);
3354 if (! emit_insn (& exp
, nbytes
))
3356 ignore_rest_of_line ();
3360 while (*input_line_pointer
++ == ',');
3362 /* Put terminator back into stream. */
3363 input_line_pointer
--;
3364 demand_empty_rest_of_line ();
3367 /* Parse a .rel31 directive. */
3370 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3377 if (*input_line_pointer
== '1')
3378 highbit
= 0x80000000;
3379 else if (*input_line_pointer
!= '0')
3380 as_bad (_("expected 0 or 1"));
3382 input_line_pointer
++;
3383 if (*input_line_pointer
!= ',')
3384 as_bad (_("missing comma"));
3385 input_line_pointer
++;
3387 #ifdef md_flush_pending_output
3388 md_flush_pending_output ();
3391 #ifdef md_cons_align
3395 mapping_state (MAP_DATA
);
3400 md_number_to_chars (p
, highbit
, 4);
3401 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3402 BFD_RELOC_ARM_PREL31
);
3404 demand_empty_rest_of_line ();
3407 /* Directives: AEABI stack-unwind tables. */
3409 /* Parse an unwind_fnstart directive. Simply records the current location. */
3412 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3414 demand_empty_rest_of_line ();
3415 if (unwind
.proc_start
)
3417 as_bad (_("duplicate .fnstart directive"));
3421 /* Mark the start of the function. */
3422 unwind
.proc_start
= expr_build_dot ();
3424 /* Reset the rest of the unwind info. */
3425 unwind
.opcode_count
= 0;
3426 unwind
.table_entry
= NULL
;
3427 unwind
.personality_routine
= NULL
;
3428 unwind
.personality_index
= -1;
3429 unwind
.frame_size
= 0;
3430 unwind
.fp_offset
= 0;
3431 unwind
.fp_reg
= REG_SP
;
3433 unwind
.sp_restored
= 0;
3437 /* Parse a handlerdata directive. Creates the exception handling table entry
3438 for the function. */
3441 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3443 demand_empty_rest_of_line ();
3444 if (!unwind
.proc_start
)
3445 as_bad (MISSING_FNSTART
);
3447 if (unwind
.table_entry
)
3448 as_bad (_("duplicate .handlerdata directive"));
3450 create_unwind_entry (1);
3453 /* Parse an unwind_fnend directive. Generates the index table entry. */
3456 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3461 unsigned int marked_pr_dependency
;
3463 demand_empty_rest_of_line ();
3465 if (!unwind
.proc_start
)
3467 as_bad (_(".fnend directive without .fnstart"));
3471 /* Add eh table entry. */
3472 if (unwind
.table_entry
== NULL
)
3473 val
= create_unwind_entry (0);
3477 /* Add index table entry. This is two words. */
3478 start_unwind_section (unwind
.saved_seg
, 1);
3479 frag_align (2, 0, 0);
3480 record_alignment (now_seg
, 2);
3482 ptr
= frag_more (8);
3483 where
= frag_now_fix () - 8;
3485 /* Self relative offset of the function start. */
3486 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3487 BFD_RELOC_ARM_PREL31
);
3489 /* Indicate dependency on EHABI-defined personality routines to the
3490 linker, if it hasn't been done already. */
3491 marked_pr_dependency
3492 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3493 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3494 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3496 static const char *const name
[] =
3498 "__aeabi_unwind_cpp_pr0",
3499 "__aeabi_unwind_cpp_pr1",
3500 "__aeabi_unwind_cpp_pr2"
3502 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3503 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3504 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3505 |= 1 << unwind
.personality_index
;
3509 /* Inline exception table entry. */
3510 md_number_to_chars (ptr
+ 4, val
, 4);
3512 /* Self relative offset of the table entry. */
3513 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3514 BFD_RELOC_ARM_PREL31
);
3516 /* Restore the original section. */
3517 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3519 unwind
.proc_start
= NULL
;
3523 /* Parse an unwind_cantunwind directive. */
3526 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3528 demand_empty_rest_of_line ();
3529 if (!unwind
.proc_start
)
3530 as_bad (MISSING_FNSTART
);
3532 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3533 as_bad (_("personality routine specified for cantunwind frame"));
3535 unwind
.personality_index
= -2;
3539 /* Parse a personalityindex directive. */
3542 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3546 if (!unwind
.proc_start
)
3547 as_bad (MISSING_FNSTART
);
3549 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3550 as_bad (_("duplicate .personalityindex directive"));
3554 if (exp
.X_op
!= O_constant
3555 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3557 as_bad (_("bad personality routine number"));
3558 ignore_rest_of_line ();
3562 unwind
.personality_index
= exp
.X_add_number
;
3564 demand_empty_rest_of_line ();
3568 /* Parse a personality directive. */
3571 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3575 if (!unwind
.proc_start
)
3576 as_bad (MISSING_FNSTART
);
3578 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3579 as_bad (_("duplicate .personality directive"));
3581 name
= input_line_pointer
;
3582 c
= get_symbol_end ();
3583 p
= input_line_pointer
;
3584 unwind
.personality_routine
= symbol_find_or_make (name
);
3586 demand_empty_rest_of_line ();
3590 /* Parse a directive saving core registers. */
3593 s_arm_unwind_save_core (void)
3599 range
= parse_reg_list (&input_line_pointer
);
3602 as_bad (_("expected register list"));
3603 ignore_rest_of_line ();
3607 demand_empty_rest_of_line ();
3609 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3610 into .unwind_save {..., sp...}. We aren't bothered about the value of
3611 ip because it is clobbered by calls. */
3612 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3613 && (range
& 0x3000) == 0x1000)
3615 unwind
.opcode_count
--;
3616 unwind
.sp_restored
= 0;
3617 range
= (range
| 0x2000) & ~0x1000;
3618 unwind
.pending_offset
= 0;
3624 /* See if we can use the short opcodes. These pop a block of up to 8
3625 registers starting with r4, plus maybe r14. */
3626 for (n
= 0; n
< 8; n
++)
3628 /* Break at the first non-saved register. */
3629 if ((range
& (1 << (n
+ 4))) == 0)
3632 /* See if there are any other bits set. */
3633 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3635 /* Use the long form. */
3636 op
= 0x8000 | ((range
>> 4) & 0xfff);
3637 add_unwind_opcode (op
, 2);
3641 /* Use the short form. */
3643 op
= 0xa8; /* Pop r14. */
3645 op
= 0xa0; /* Do not pop r14. */
3647 add_unwind_opcode (op
, 1);
3654 op
= 0xb100 | (range
& 0xf);
3655 add_unwind_opcode (op
, 2);
3658 /* Record the number of bytes pushed. */
3659 for (n
= 0; n
< 16; n
++)
3661 if (range
& (1 << n
))
3662 unwind
.frame_size
+= 4;
3667 /* Parse a directive saving FPA registers. */
3670 s_arm_unwind_save_fpa (int reg
)
3676 /* Get Number of registers to transfer. */
3677 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3680 exp
.X_op
= O_illegal
;
3682 if (exp
.X_op
!= O_constant
)
3684 as_bad (_("expected , <constant>"));
3685 ignore_rest_of_line ();
3689 num_regs
= exp
.X_add_number
;
3691 if (num_regs
< 1 || num_regs
> 4)
3693 as_bad (_("number of registers must be in the range [1:4]"));
3694 ignore_rest_of_line ();
3698 demand_empty_rest_of_line ();
3703 op
= 0xb4 | (num_regs
- 1);
3704 add_unwind_opcode (op
, 1);
3709 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3710 add_unwind_opcode (op
, 2);
3712 unwind
.frame_size
+= num_regs
* 12;
3716 /* Parse a directive saving VFP registers for ARMv6 and above. */
3719 s_arm_unwind_save_vfp_armv6 (void)
3724 int num_vfpv3_regs
= 0;
3725 int num_regs_below_16
;
3727 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3730 as_bad (_("expected register list"));
3731 ignore_rest_of_line ();
3735 demand_empty_rest_of_line ();
3737 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3738 than FSTMX/FLDMX-style ones). */
3740 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3742 num_vfpv3_regs
= count
;
3743 else if (start
+ count
> 16)
3744 num_vfpv3_regs
= start
+ count
- 16;
3746 if (num_vfpv3_regs
> 0)
3748 int start_offset
= start
> 16 ? start
- 16 : 0;
3749 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3750 add_unwind_opcode (op
, 2);
3753 /* Generate opcode for registers numbered in the range 0 .. 15. */
3754 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3755 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3756 if (num_regs_below_16
> 0)
3758 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3759 add_unwind_opcode (op
, 2);
3762 unwind
.frame_size
+= count
* 8;
3766 /* Parse a directive saving VFP registers for pre-ARMv6. */
3769 s_arm_unwind_save_vfp (void)
3775 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3778 as_bad (_("expected register list"));
3779 ignore_rest_of_line ();
3783 demand_empty_rest_of_line ();
3788 op
= 0xb8 | (count
- 1);
3789 add_unwind_opcode (op
, 1);
3794 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3795 add_unwind_opcode (op
, 2);
3797 unwind
.frame_size
+= count
* 8 + 4;
3801 /* Parse a directive saving iWMMXt data registers. */
3804 s_arm_unwind_save_mmxwr (void)
3812 if (*input_line_pointer
== '{')
3813 input_line_pointer
++;
3817 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3821 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3826 as_tsktsk (_("register list not in ascending order"));
3829 if (*input_line_pointer
== '-')
3831 input_line_pointer
++;
3832 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3835 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3838 else if (reg
>= hi_reg
)
3840 as_bad (_("bad register range"));
3843 for (; reg
< hi_reg
; reg
++)
3847 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3849 if (*input_line_pointer
== '}')
3850 input_line_pointer
++;
3852 demand_empty_rest_of_line ();
3854 /* Generate any deferred opcodes because we're going to be looking at
3856 flush_pending_unwind ();
3858 for (i
= 0; i
< 16; i
++)
3860 if (mask
& (1 << i
))
3861 unwind
.frame_size
+= 8;
3864 /* Attempt to combine with a previous opcode. We do this because gcc
3865 likes to output separate unwind directives for a single block of
3867 if (unwind
.opcode_count
> 0)
3869 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3870 if ((i
& 0xf8) == 0xc0)
3873 /* Only merge if the blocks are contiguous. */
3876 if ((mask
& 0xfe00) == (1 << 9))
3878 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3879 unwind
.opcode_count
--;
3882 else if (i
== 6 && unwind
.opcode_count
>= 2)
3884 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3888 op
= 0xffff << (reg
- 1);
3890 && ((mask
& op
) == (1u << (reg
- 1))))
3892 op
= (1 << (reg
+ i
+ 1)) - 1;
3893 op
&= ~((1 << reg
) - 1);
3895 unwind
.opcode_count
-= 2;
3902 /* We want to generate opcodes in the order the registers have been
3903 saved, ie. descending order. */
3904 for (reg
= 15; reg
>= -1; reg
--)
3906 /* Save registers in blocks. */
3908 || !(mask
& (1 << reg
)))
3910 /* We found an unsaved reg. Generate opcodes to save the
3917 op
= 0xc0 | (hi_reg
- 10);
3918 add_unwind_opcode (op
, 1);
3923 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3924 add_unwind_opcode (op
, 2);
3933 ignore_rest_of_line ();
3937 s_arm_unwind_save_mmxwcg (void)
3944 if (*input_line_pointer
== '{')
3945 input_line_pointer
++;
3949 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3953 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3959 as_tsktsk (_("register list not in ascending order"));
3962 if (*input_line_pointer
== '-')
3964 input_line_pointer
++;
3965 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3968 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3971 else if (reg
>= hi_reg
)
3973 as_bad (_("bad register range"));
3976 for (; reg
< hi_reg
; reg
++)
3980 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3982 if (*input_line_pointer
== '}')
3983 input_line_pointer
++;
3985 demand_empty_rest_of_line ();
3987 /* Generate any deferred opcodes because we're going to be looking at
3989 flush_pending_unwind ();
3991 for (reg
= 0; reg
< 16; reg
++)
3993 if (mask
& (1 << reg
))
3994 unwind
.frame_size
+= 4;
3997 add_unwind_opcode (op
, 2);
4000 ignore_rest_of_line ();
4004 /* Parse an unwind_save directive.
4005 If the argument is non-zero, this is a .vsave directive. */
4008 s_arm_unwind_save (int arch_v6
)
4011 struct reg_entry
*reg
;
4012 bfd_boolean had_brace
= FALSE
;
4014 if (!unwind
.proc_start
)
4015 as_bad (MISSING_FNSTART
);
4017 /* Figure out what sort of save we have. */
4018 peek
= input_line_pointer
;
4026 reg
= arm_reg_parse_multi (&peek
);
4030 as_bad (_("register expected"));
4031 ignore_rest_of_line ();
4040 as_bad (_("FPA .unwind_save does not take a register list"));
4041 ignore_rest_of_line ();
4044 input_line_pointer
= peek
;
4045 s_arm_unwind_save_fpa (reg
->number
);
4048 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4051 s_arm_unwind_save_vfp_armv6 ();
4053 s_arm_unwind_save_vfp ();
4055 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4056 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4059 as_bad (_(".unwind_save does not support this kind of register"));
4060 ignore_rest_of_line ();
4065 /* Parse an unwind_movsp directive. */
4068 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4074 if (!unwind
.proc_start
)
4075 as_bad (MISSING_FNSTART
);
4077 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4080 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4081 ignore_rest_of_line ();
4085 /* Optional constant. */
4086 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4088 if (immediate_for_directive (&offset
) == FAIL
)
4094 demand_empty_rest_of_line ();
4096 if (reg
== REG_SP
|| reg
== REG_PC
)
4098 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4102 if (unwind
.fp_reg
!= REG_SP
)
4103 as_bad (_("unexpected .unwind_movsp directive"));
4105 /* Generate opcode to restore the value. */
4107 add_unwind_opcode (op
, 1);
4109 /* Record the information for later. */
4110 unwind
.fp_reg
= reg
;
4111 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4112 unwind
.sp_restored
= 1;
4115 /* Parse an unwind_pad directive. */
4118 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4122 if (!unwind
.proc_start
)
4123 as_bad (MISSING_FNSTART
);
4125 if (immediate_for_directive (&offset
) == FAIL
)
4130 as_bad (_("stack increment must be multiple of 4"));
4131 ignore_rest_of_line ();
4135 /* Don't generate any opcodes, just record the details for later. */
4136 unwind
.frame_size
+= offset
;
4137 unwind
.pending_offset
+= offset
;
4139 demand_empty_rest_of_line ();
4142 /* Parse an unwind_setfp directive. */
4145 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4151 if (!unwind
.proc_start
)
4152 as_bad (MISSING_FNSTART
);
4154 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4155 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4158 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4160 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4162 as_bad (_("expected <reg>, <reg>"));
4163 ignore_rest_of_line ();
4167 /* Optional constant. */
4168 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4170 if (immediate_for_directive (&offset
) == FAIL
)
4176 demand_empty_rest_of_line ();
4178 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4180 as_bad (_("register must be either sp or set by a previous"
4181 "unwind_movsp directive"));
4185 /* Don't generate any opcodes, just record the information for later. */
4186 unwind
.fp_reg
= fp_reg
;
4188 if (sp_reg
== REG_SP
)
4189 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4191 unwind
.fp_offset
-= offset
;
4194 /* Parse an unwind_raw directive. */
4197 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4200 /* This is an arbitrary limit. */
4201 unsigned char op
[16];
4204 if (!unwind
.proc_start
)
4205 as_bad (MISSING_FNSTART
);
4208 if (exp
.X_op
== O_constant
4209 && skip_past_comma (&input_line_pointer
) != FAIL
)
4211 unwind
.frame_size
+= exp
.X_add_number
;
4215 exp
.X_op
= O_illegal
;
4217 if (exp
.X_op
!= O_constant
)
4219 as_bad (_("expected <offset>, <opcode>"));
4220 ignore_rest_of_line ();
4226 /* Parse the opcode. */
4231 as_bad (_("unwind opcode too long"));
4232 ignore_rest_of_line ();
4234 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4236 as_bad (_("invalid unwind opcode"));
4237 ignore_rest_of_line ();
4240 op
[count
++] = exp
.X_add_number
;
4242 /* Parse the next byte. */
4243 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4249 /* Add the opcode bytes in reverse order. */
4251 add_unwind_opcode (op
[count
], 1);
4253 demand_empty_rest_of_line ();
4257 /* Parse a .eabi_attribute directive. */
4260 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4262 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4264 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4265 attributes_set_explicitly
[tag
] = 1;
4267 #endif /* OBJ_ELF */
4269 static void s_arm_arch (int);
4270 static void s_arm_object_arch (int);
4271 static void s_arm_cpu (int);
4272 static void s_arm_fpu (int);
4277 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4284 if (exp
.X_op
== O_symbol
)
4285 exp
.X_op
= O_secrel
;
4287 emit_expr (&exp
, 4);
4289 while (*input_line_pointer
++ == ',');
4291 input_line_pointer
--;
4292 demand_empty_rest_of_line ();
4296 /* This table describes all the machine specific pseudo-ops the assembler
4297 has to support. The fields are:
4298 pseudo-op name without dot
4299 function to call to execute this pseudo-op
4300 Integer arg to pass to the function. */
4302 const pseudo_typeS md_pseudo_table
[] =
4304 /* Never called because '.req' does not start a line. */
4305 { "req", s_req
, 0 },
4306 /* Following two are likewise never called. */
4309 { "unreq", s_unreq
, 0 },
4310 { "bss", s_bss
, 0 },
4311 { "align", s_align
, 0 },
4312 { "arm", s_arm
, 0 },
4313 { "thumb", s_thumb
, 0 },
4314 { "code", s_code
, 0 },
4315 { "force_thumb", s_force_thumb
, 0 },
4316 { "thumb_func", s_thumb_func
, 0 },
4317 { "thumb_set", s_thumb_set
, 0 },
4318 { "even", s_even
, 0 },
4319 { "ltorg", s_ltorg
, 0 },
4320 { "pool", s_ltorg
, 0 },
4321 { "syntax", s_syntax
, 0 },
4322 { "cpu", s_arm_cpu
, 0 },
4323 { "arch", s_arm_arch
, 0 },
4324 { "object_arch", s_arm_object_arch
, 0 },
4325 { "fpu", s_arm_fpu
, 0 },
4327 { "word", s_arm_elf_cons
, 4 },
4328 { "long", s_arm_elf_cons
, 4 },
4329 { "inst.n", s_arm_elf_inst
, 2 },
4330 { "inst.w", s_arm_elf_inst
, 4 },
4331 { "inst", s_arm_elf_inst
, 0 },
4332 { "rel31", s_arm_rel31
, 0 },
4333 { "fnstart", s_arm_unwind_fnstart
, 0 },
4334 { "fnend", s_arm_unwind_fnend
, 0 },
4335 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4336 { "personality", s_arm_unwind_personality
, 0 },
4337 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4338 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4339 { "save", s_arm_unwind_save
, 0 },
4340 { "vsave", s_arm_unwind_save
, 1 },
4341 { "movsp", s_arm_unwind_movsp
, 0 },
4342 { "pad", s_arm_unwind_pad
, 0 },
4343 { "setfp", s_arm_unwind_setfp
, 0 },
4344 { "unwind_raw", s_arm_unwind_raw
, 0 },
4345 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4349 /* These are used for dwarf. */
4353 /* These are used for dwarf2. */
4354 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4355 { "loc", dwarf2_directive_loc
, 0 },
4356 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4358 { "extend", float_cons
, 'x' },
4359 { "ldouble", float_cons
, 'x' },
4360 { "packed", float_cons
, 'p' },
4362 {"secrel32", pe_directive_secrel
, 0},
4367 /* Parser functions used exclusively in instruction operands. */
4369 /* Generic immediate-value read function for use in insn parsing.
4370 STR points to the beginning of the immediate (the leading #);
4371 VAL receives the value; if the value is outside [MIN, MAX]
4372 issue an error. PREFIX_OPT is true if the immediate prefix is
4376 parse_immediate (char **str
, int *val
, int min
, int max
,
4377 bfd_boolean prefix_opt
)
4380 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4381 if (exp
.X_op
!= O_constant
)
4383 inst
.error
= _("constant expression required");
4387 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4389 inst
.error
= _("immediate value out of range");
4393 *val
= exp
.X_add_number
;
4397 /* Less-generic immediate-value read function with the possibility of loading a
4398 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4399 instructions. Puts the result directly in inst.operands[i]. */
4402 parse_big_immediate (char **str
, int i
)
4407 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4409 if (exp
.X_op
== O_constant
)
4411 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4412 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4413 O_constant. We have to be careful not to break compilation for
4414 32-bit X_add_number, though. */
4415 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4417 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4418 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4419 inst
.operands
[i
].regisimm
= 1;
4422 else if (exp
.X_op
== O_big
4423 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32)
4425 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4427 /* Bignums have their least significant bits in
4428 generic_bignum[0]. Make sure we put 32 bits in imm and
4429 32 bits in reg, in a (hopefully) portable way. */
4430 gas_assert (parts
!= 0);
4432 /* Make sure that the number is not too big.
4433 PR 11972: Bignums can now be sign-extended to the
4434 size of a .octa so check that the out of range bits
4435 are all zero or all one. */
4436 if (LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 64)
4438 LITTLENUM_TYPE m
= -1;
4440 if (generic_bignum
[parts
* 2] != 0
4441 && generic_bignum
[parts
* 2] != m
)
4444 for (j
= parts
* 2 + 1; j
< (unsigned) exp
.X_add_number
; j
++)
4445 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4449 inst
.operands
[i
].imm
= 0;
4450 for (j
= 0; j
< parts
; j
++, idx
++)
4451 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4452 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4453 inst
.operands
[i
].reg
= 0;
4454 for (j
= 0; j
< parts
; j
++, idx
++)
4455 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4456 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4457 inst
.operands
[i
].regisimm
= 1;
4467 /* Returns the pseudo-register number of an FPA immediate constant,
4468 or FAIL if there isn't a valid constant here. */
4471 parse_fpa_immediate (char ** str
)
4473 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4479 /* First try and match exact strings, this is to guarantee
4480 that some formats will work even for cross assembly. */
4482 for (i
= 0; fp_const
[i
]; i
++)
4484 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4488 *str
+= strlen (fp_const
[i
]);
4489 if (is_end_of_line
[(unsigned char) **str
])
4495 /* Just because we didn't get a match doesn't mean that the constant
4496 isn't valid, just that it is in a format that we don't
4497 automatically recognize. Try parsing it with the standard
4498 expression routines. */
4500 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4502 /* Look for a raw floating point number. */
4503 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4504 && is_end_of_line
[(unsigned char) *save_in
])
4506 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4508 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4510 if (words
[j
] != fp_values
[i
][j
])
4514 if (j
== MAX_LITTLENUMS
)
4522 /* Try and parse a more complex expression, this will probably fail
4523 unless the code uses a floating point prefix (eg "0f"). */
4524 save_in
= input_line_pointer
;
4525 input_line_pointer
= *str
;
4526 if (expression (&exp
) == absolute_section
4527 && exp
.X_op
== O_big
4528 && exp
.X_add_number
< 0)
4530 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4532 if (gen_to_words (words
, 5, (long) 15) == 0)
4534 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4536 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4538 if (words
[j
] != fp_values
[i
][j
])
4542 if (j
== MAX_LITTLENUMS
)
4544 *str
= input_line_pointer
;
4545 input_line_pointer
= save_in
;
4552 *str
= input_line_pointer
;
4553 input_line_pointer
= save_in
;
4554 inst
.error
= _("invalid FPA immediate expression");
4558 /* Returns 1 if a number has "quarter-precision" float format
4559 0baBbbbbbc defgh000 00000000 00000000. */
4562 is_quarter_float (unsigned imm
)
4564 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4565 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4568 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4569 0baBbbbbbc defgh000 00000000 00000000.
4570 The zero and minus-zero cases need special handling, since they can't be
4571 encoded in the "quarter-precision" float format, but can nonetheless be
4572 loaded as integer constants. */
4575 parse_qfloat_immediate (char **ccp
, int *immed
)
4579 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4580 int found_fpchar
= 0;
4582 skip_past_char (&str
, '#');
4584 /* We must not accidentally parse an integer as a floating-point number. Make
4585 sure that the value we parse is not an integer by checking for special
4586 characters '.' or 'e'.
4587 FIXME: This is a horrible hack, but doing better is tricky because type
4588 information isn't in a very usable state at parse time. */
4590 skip_whitespace (fpnum
);
4592 if (strncmp (fpnum
, "0x", 2) == 0)
4596 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4597 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4607 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4609 unsigned fpword
= 0;
4612 /* Our FP word must be 32 bits (single-precision FP). */
4613 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4615 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4619 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4632 /* Shift operands. */
4635 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4638 struct asm_shift_name
4641 enum shift_kind kind
;
4644 /* Third argument to parse_shift. */
4645 enum parse_shift_mode
4647 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4648 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4649 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4650 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4651 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4654 /* Parse a <shift> specifier on an ARM data processing instruction.
4655 This has three forms:
4657 (LSL|LSR|ASL|ASR|ROR) Rs
4658 (LSL|LSR|ASL|ASR|ROR) #imm
4661 Note that ASL is assimilated to LSL in the instruction encoding, and
4662 RRX to ROR #0 (which cannot be written as such). */
4665 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4667 const struct asm_shift_name
*shift_name
;
4668 enum shift_kind shift
;
4673 for (p
= *str
; ISALPHA (*p
); p
++)
4678 inst
.error
= _("shift expression expected");
4682 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4685 if (shift_name
== NULL
)
4687 inst
.error
= _("shift expression expected");
4691 shift
= shift_name
->kind
;
4695 case NO_SHIFT_RESTRICT
:
4696 case SHIFT_IMMEDIATE
: break;
4698 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4699 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4701 inst
.error
= _("'LSL' or 'ASR' required");
4706 case SHIFT_LSL_IMMEDIATE
:
4707 if (shift
!= SHIFT_LSL
)
4709 inst
.error
= _("'LSL' required");
4714 case SHIFT_ASR_IMMEDIATE
:
4715 if (shift
!= SHIFT_ASR
)
4717 inst
.error
= _("'ASR' required");
4725 if (shift
!= SHIFT_RRX
)
4727 /* Whitespace can appear here if the next thing is a bare digit. */
4728 skip_whitespace (p
);
4730 if (mode
== NO_SHIFT_RESTRICT
4731 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4733 inst
.operands
[i
].imm
= reg
;
4734 inst
.operands
[i
].immisreg
= 1;
4736 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4739 inst
.operands
[i
].shift_kind
= shift
;
4740 inst
.operands
[i
].shifted
= 1;
4745 /* Parse a <shifter_operand> for an ARM data processing instruction:
4748 #<immediate>, <rotate>
4752 where <shift> is defined by parse_shift above, and <rotate> is a
4753 multiple of 2 between 0 and 30. Validation of immediate operands
4754 is deferred to md_apply_fix. */
4757 parse_shifter_operand (char **str
, int i
)
4762 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4764 inst
.operands
[i
].reg
= value
;
4765 inst
.operands
[i
].isreg
= 1;
4767 /* parse_shift will override this if appropriate */
4768 inst
.reloc
.exp
.X_op
= O_constant
;
4769 inst
.reloc
.exp
.X_add_number
= 0;
4771 if (skip_past_comma (str
) == FAIL
)
4774 /* Shift operation on register. */
4775 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4778 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4781 if (skip_past_comma (str
) == SUCCESS
)
4783 /* #x, y -- ie explicit rotation by Y. */
4784 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4787 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4789 inst
.error
= _("constant expression expected");
4793 value
= exp
.X_add_number
;
4794 if (value
< 0 || value
> 30 || value
% 2 != 0)
4796 inst
.error
= _("invalid rotation");
4799 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4801 inst
.error
= _("invalid constant");
4805 /* Convert to decoded value. md_apply_fix will put it back. */
4806 inst
.reloc
.exp
.X_add_number
4807 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4808 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4811 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4812 inst
.reloc
.pc_rel
= 0;
4816 /* Group relocation information. Each entry in the table contains the
4817 textual name of the relocation as may appear in assembler source
4818 and must end with a colon.
4819 Along with this textual name are the relocation codes to be used if
4820 the corresponding instruction is an ALU instruction (ADD or SUB only),
4821 an LDR, an LDRS, or an LDC. */
4823 struct group_reloc_table_entry
4834 /* Varieties of non-ALU group relocation. */
4841 static struct group_reloc_table_entry group_reloc_table
[] =
4842 { /* Program counter relative: */
4844 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4849 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4850 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4851 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4852 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4854 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4859 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4860 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4861 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4862 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4864 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4865 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4866 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4867 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4868 /* Section base relative */
4870 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4875 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4876 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4877 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4878 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4880 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4885 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4886 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4887 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4888 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4890 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4891 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4892 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4893 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4895 /* Given the address of a pointer pointing to the textual name of a group
4896 relocation as may appear in assembler source, attempt to find its details
4897 in group_reloc_table. The pointer will be updated to the character after
4898 the trailing colon. On failure, FAIL will be returned; SUCCESS
4899 otherwise. On success, *entry will be updated to point at the relevant
4900 group_reloc_table entry. */
4903 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4906 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4908 int length
= strlen (group_reloc_table
[i
].name
);
4910 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4911 && (*str
)[length
] == ':')
4913 *out
= &group_reloc_table
[i
];
4914 *str
+= (length
+ 1);
4922 /* Parse a <shifter_operand> for an ARM data processing instruction
4923 (as for parse_shifter_operand) where group relocations are allowed:
4926 #<immediate>, <rotate>
4927 #:<group_reloc>:<expression>
4931 where <group_reloc> is one of the strings defined in group_reloc_table.
4932 The hashes are optional.
4934 Everything else is as for parse_shifter_operand. */
4936 static parse_operand_result
4937 parse_shifter_operand_group_reloc (char **str
, int i
)
4939 /* Determine if we have the sequence of characters #: or just :
4940 coming next. If we do, then we check for a group relocation.
4941 If we don't, punt the whole lot to parse_shifter_operand. */
4943 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4944 || (*str
)[0] == ':')
4946 struct group_reloc_table_entry
*entry
;
4948 if ((*str
)[0] == '#')
4953 /* Try to parse a group relocation. Anything else is an error. */
4954 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4956 inst
.error
= _("unknown group relocation");
4957 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4960 /* We now have the group relocation table entry corresponding to
4961 the name in the assembler source. Next, we parse the expression. */
4962 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4963 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4965 /* Record the relocation type (always the ALU variant here). */
4966 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
4967 gas_assert (inst
.reloc
.type
!= 0);
4969 return PARSE_OPERAND_SUCCESS
;
4972 return parse_shifter_operand (str
, i
) == SUCCESS
4973 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4975 /* Never reached. */
4978 /* Parse a Neon alignment expression. Information is written to
4979 inst.operands[i]. We assume the initial ':' has been skipped.
4981 align .imm = align << 8, .immisalign=1, .preind=0 */
4982 static parse_operand_result
4983 parse_neon_alignment (char **str
, int i
)
4988 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4990 if (exp
.X_op
!= O_constant
)
4992 inst
.error
= _("alignment must be constant");
4993 return PARSE_OPERAND_FAIL
;
4996 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4997 inst
.operands
[i
].immisalign
= 1;
4998 /* Alignments are not pre-indexes. */
4999 inst
.operands
[i
].preind
= 0;
5002 return PARSE_OPERAND_SUCCESS
;
5005 /* Parse all forms of an ARM address expression. Information is written
5006 to inst.operands[i] and/or inst.reloc.
5008 Preindexed addressing (.preind=1):
5010 [Rn, #offset] .reg=Rn .reloc.exp=offset
5011 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5012 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5013 .shift_kind=shift .reloc.exp=shift_imm
5015 These three may have a trailing ! which causes .writeback to be set also.
5017 Postindexed addressing (.postind=1, .writeback=1):
5019 [Rn], #offset .reg=Rn .reloc.exp=offset
5020 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5021 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5022 .shift_kind=shift .reloc.exp=shift_imm
5024 Unindexed addressing (.preind=0, .postind=0):
5026 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5030 [Rn]{!} shorthand for [Rn,#0]{!}
5031 =immediate .isreg=0 .reloc.exp=immediate
5032 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5034 It is the caller's responsibility to check for addressing modes not
5035 supported by the instruction, and to set inst.reloc.type. */
5037 static parse_operand_result
5038 parse_address_main (char **str
, int i
, int group_relocations
,
5039 group_reloc_type group_type
)
5044 if (skip_past_char (&p
, '[') == FAIL
)
5046 if (skip_past_char (&p
, '=') == FAIL
)
5048 /* Bare address - translate to PC-relative offset. */
5049 inst
.reloc
.pc_rel
= 1;
5050 inst
.operands
[i
].reg
= REG_PC
;
5051 inst
.operands
[i
].isreg
= 1;
5052 inst
.operands
[i
].preind
= 1;
5054 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5056 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5057 return PARSE_OPERAND_FAIL
;
5060 return PARSE_OPERAND_SUCCESS
;
5063 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5065 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5066 return PARSE_OPERAND_FAIL
;
5068 inst
.operands
[i
].reg
= reg
;
5069 inst
.operands
[i
].isreg
= 1;
5071 if (skip_past_comma (&p
) == SUCCESS
)
5073 inst
.operands
[i
].preind
= 1;
5076 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5078 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5080 inst
.operands
[i
].imm
= reg
;
5081 inst
.operands
[i
].immisreg
= 1;
5083 if (skip_past_comma (&p
) == SUCCESS
)
5084 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5085 return PARSE_OPERAND_FAIL
;
5087 else if (skip_past_char (&p
, ':') == SUCCESS
)
5089 /* FIXME: '@' should be used here, but it's filtered out by generic
5090 code before we get to see it here. This may be subject to
5092 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5094 if (result
!= PARSE_OPERAND_SUCCESS
)
5099 if (inst
.operands
[i
].negative
)
5101 inst
.operands
[i
].negative
= 0;
5105 if (group_relocations
5106 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5108 struct group_reloc_table_entry
*entry
;
5110 /* Skip over the #: or : sequence. */
5116 /* Try to parse a group relocation. Anything else is an
5118 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5120 inst
.error
= _("unknown group relocation");
5121 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5124 /* We now have the group relocation table entry corresponding to
5125 the name in the assembler source. Next, we parse the
5127 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5128 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5130 /* Record the relocation type. */
5134 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5138 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5142 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5149 if (inst
.reloc
.type
== 0)
5151 inst
.error
= _("this group relocation is not allowed on this instruction");
5152 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5156 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5157 return PARSE_OPERAND_FAIL
;
5160 else if (skip_past_char (&p
, ':') == SUCCESS
)
5162 /* FIXME: '@' should be used here, but it's filtered out by generic code
5163 before we get to see it here. This may be subject to change. */
5164 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5166 if (result
!= PARSE_OPERAND_SUCCESS
)
5170 if (skip_past_char (&p
, ']') == FAIL
)
5172 inst
.error
= _("']' expected");
5173 return PARSE_OPERAND_FAIL
;
5176 if (skip_past_char (&p
, '!') == SUCCESS
)
5177 inst
.operands
[i
].writeback
= 1;
5179 else if (skip_past_comma (&p
) == SUCCESS
)
5181 if (skip_past_char (&p
, '{') == SUCCESS
)
5183 /* [Rn], {expr} - unindexed, with option */
5184 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5185 0, 255, TRUE
) == FAIL
)
5186 return PARSE_OPERAND_FAIL
;
5188 if (skip_past_char (&p
, '}') == FAIL
)
5190 inst
.error
= _("'}' expected at end of 'option' field");
5191 return PARSE_OPERAND_FAIL
;
5193 if (inst
.operands
[i
].preind
)
5195 inst
.error
= _("cannot combine index with option");
5196 return PARSE_OPERAND_FAIL
;
5199 return PARSE_OPERAND_SUCCESS
;
5203 inst
.operands
[i
].postind
= 1;
5204 inst
.operands
[i
].writeback
= 1;
5206 if (inst
.operands
[i
].preind
)
5208 inst
.error
= _("cannot combine pre- and post-indexing");
5209 return PARSE_OPERAND_FAIL
;
5213 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5215 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5217 /* We might be using the immediate for alignment already. If we
5218 are, OR the register number into the low-order bits. */
5219 if (inst
.operands
[i
].immisalign
)
5220 inst
.operands
[i
].imm
|= reg
;
5222 inst
.operands
[i
].imm
= reg
;
5223 inst
.operands
[i
].immisreg
= 1;
5225 if (skip_past_comma (&p
) == SUCCESS
)
5226 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5227 return PARSE_OPERAND_FAIL
;
5231 if (inst
.operands
[i
].negative
)
5233 inst
.operands
[i
].negative
= 0;
5236 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5237 return PARSE_OPERAND_FAIL
;
5242 /* If at this point neither .preind nor .postind is set, we have a
5243 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5244 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5246 inst
.operands
[i
].preind
= 1;
5247 inst
.reloc
.exp
.X_op
= O_constant
;
5248 inst
.reloc
.exp
.X_add_number
= 0;
5251 return PARSE_OPERAND_SUCCESS
;
5255 parse_address (char **str
, int i
)
5257 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5261 static parse_operand_result
5262 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5264 return parse_address_main (str
, i
, 1, type
);
5267 /* Parse an operand for a MOVW or MOVT instruction. */
5269 parse_half (char **str
)
5274 skip_past_char (&p
, '#');
5275 if (strncasecmp (p
, ":lower16:", 9) == 0)
5276 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5277 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5278 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5280 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5283 skip_whitespace (p
);
5286 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5289 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5291 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5293 inst
.error
= _("constant expression expected");
5296 if (inst
.reloc
.exp
.X_add_number
< 0
5297 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5299 inst
.error
= _("immediate value out of range");
5307 /* Miscellaneous. */
5309 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5310 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5312 parse_psr (char **str
)
5315 unsigned long psr_field
;
5316 const struct asm_psr
*psr
;
5319 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5320 feature for ease of use and backwards compatibility. */
5322 if (strncasecmp (p
, "SPSR", 4) == 0)
5323 psr_field
= SPSR_BIT
;
5324 else if (strncasecmp (p
, "CPSR", 4) == 0
5325 || (strncasecmp (p
, "APSR", 4) == 0
5326 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
)))
5333 while (ISALNUM (*p
) || *p
== '_');
5335 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5347 /* A suffix follows. */
5353 while (ISALNUM (*p
) || *p
== '_');
5355 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5360 psr_field
|= psr
->field
;
5365 goto error
; /* Garbage after "[CS]PSR". */
5367 psr_field
|= (PSR_c
| PSR_f
);
5373 inst
.error
= _("flag for {c}psr instruction expected");
5377 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5378 value suitable for splatting into the AIF field of the instruction. */
5381 parse_cps_flags (char **str
)
5390 case '\0': case ',':
5393 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5394 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5395 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5398 inst
.error
= _("unrecognized CPS flag");
5403 if (saw_a_flag
== 0)
5405 inst
.error
= _("missing CPS flags");
5413 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5414 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5417 parse_endian_specifier (char **str
)
5422 if (strncasecmp (s
, "BE", 2))
5424 else if (strncasecmp (s
, "LE", 2))
5428 inst
.error
= _("valid endian specifiers are be or le");
5432 if (ISALNUM (s
[2]) || s
[2] == '_')
5434 inst
.error
= _("valid endian specifiers are be or le");
5439 return little_endian
;
5442 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5443 value suitable for poking into the rotate field of an sxt or sxta
5444 instruction, or FAIL on error. */
5447 parse_ror (char **str
)
5452 if (strncasecmp (s
, "ROR", 3) == 0)
5456 inst
.error
= _("missing rotation field after comma");
5460 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5465 case 0: *str
= s
; return 0x0;
5466 case 8: *str
= s
; return 0x1;
5467 case 16: *str
= s
; return 0x2;
5468 case 24: *str
= s
; return 0x3;
5471 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5476 /* Parse a conditional code (from conds[] below). The value returned is in the
5477 range 0 .. 14, or FAIL. */
5479 parse_cond (char **str
)
5482 const struct asm_cond
*c
;
5484 /* Condition codes are always 2 characters, so matching up to
5485 3 characters is sufficient. */
5490 while (ISALPHA (*q
) && n
< 3)
5492 cond
[n
] = TOLOWER (*q
);
5497 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5500 inst
.error
= _("condition required");
5508 /* Parse an option for a barrier instruction. Returns the encoding for the
5511 parse_barrier (char **str
)
5514 const struct asm_barrier_opt
*o
;
5517 while (ISALPHA (*q
))
5520 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5529 /* Parse the operands of a table branch instruction. Similar to a memory
5532 parse_tb (char **str
)
5537 if (skip_past_char (&p
, '[') == FAIL
)
5539 inst
.error
= _("'[' expected");
5543 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5545 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5548 inst
.operands
[0].reg
= reg
;
5550 if (skip_past_comma (&p
) == FAIL
)
5552 inst
.error
= _("',' expected");
5556 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5558 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5561 inst
.operands
[0].imm
= reg
;
5563 if (skip_past_comma (&p
) == SUCCESS
)
5565 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5567 if (inst
.reloc
.exp
.X_add_number
!= 1)
5569 inst
.error
= _("invalid shift");
5572 inst
.operands
[0].shifted
= 1;
5575 if (skip_past_char (&p
, ']') == FAIL
)
5577 inst
.error
= _("']' expected");
5584 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5585 information on the types the operands can take and how they are encoded.
5586 Up to four operands may be read; this function handles setting the
5587 ".present" field for each read operand itself.
5588 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5589 else returns FAIL. */
5592 parse_neon_mov (char **str
, int *which_operand
)
5594 int i
= *which_operand
, val
;
5595 enum arm_reg_type rtype
;
5597 struct neon_type_el optype
;
5599 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5601 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5602 inst
.operands
[i
].reg
= val
;
5603 inst
.operands
[i
].isscalar
= 1;
5604 inst
.operands
[i
].vectype
= optype
;
5605 inst
.operands
[i
++].present
= 1;
5607 if (skip_past_comma (&ptr
) == FAIL
)
5610 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5613 inst
.operands
[i
].reg
= val
;
5614 inst
.operands
[i
].isreg
= 1;
5615 inst
.operands
[i
].present
= 1;
5617 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5620 /* Cases 0, 1, 2, 3, 5 (D only). */
5621 if (skip_past_comma (&ptr
) == FAIL
)
5624 inst
.operands
[i
].reg
= val
;
5625 inst
.operands
[i
].isreg
= 1;
5626 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5627 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5628 inst
.operands
[i
].isvec
= 1;
5629 inst
.operands
[i
].vectype
= optype
;
5630 inst
.operands
[i
++].present
= 1;
5632 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5634 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5635 Case 13: VMOV <Sd>, <Rm> */
5636 inst
.operands
[i
].reg
= val
;
5637 inst
.operands
[i
].isreg
= 1;
5638 inst
.operands
[i
].present
= 1;
5640 if (rtype
== REG_TYPE_NQ
)
5642 first_error (_("can't use Neon quad register here"));
5645 else if (rtype
!= REG_TYPE_VFS
)
5648 if (skip_past_comma (&ptr
) == FAIL
)
5650 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5652 inst
.operands
[i
].reg
= val
;
5653 inst
.operands
[i
].isreg
= 1;
5654 inst
.operands
[i
].present
= 1;
5657 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5660 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5661 Case 1: VMOV<c><q> <Dd>, <Dm>
5662 Case 8: VMOV.F32 <Sd>, <Sm>
5663 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5665 inst
.operands
[i
].reg
= val
;
5666 inst
.operands
[i
].isreg
= 1;
5667 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5668 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5669 inst
.operands
[i
].isvec
= 1;
5670 inst
.operands
[i
].vectype
= optype
;
5671 inst
.operands
[i
].present
= 1;
5673 if (skip_past_comma (&ptr
) == SUCCESS
)
5678 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5681 inst
.operands
[i
].reg
= val
;
5682 inst
.operands
[i
].isreg
= 1;
5683 inst
.operands
[i
++].present
= 1;
5685 if (skip_past_comma (&ptr
) == FAIL
)
5688 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5691 inst
.operands
[i
].reg
= val
;
5692 inst
.operands
[i
].isreg
= 1;
5693 inst
.operands
[i
++].present
= 1;
5696 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5697 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5698 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5699 Case 10: VMOV.F32 <Sd>, #<imm>
5700 Case 11: VMOV.F64 <Dd>, #<imm> */
5701 inst
.operands
[i
].immisfloat
= 1;
5702 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5703 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5704 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5708 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5712 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5715 inst
.operands
[i
].reg
= val
;
5716 inst
.operands
[i
].isreg
= 1;
5717 inst
.operands
[i
++].present
= 1;
5719 if (skip_past_comma (&ptr
) == FAIL
)
5722 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5724 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5725 inst
.operands
[i
].reg
= val
;
5726 inst
.operands
[i
].isscalar
= 1;
5727 inst
.operands
[i
].present
= 1;
5728 inst
.operands
[i
].vectype
= optype
;
5730 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5732 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5733 inst
.operands
[i
].reg
= val
;
5734 inst
.operands
[i
].isreg
= 1;
5735 inst
.operands
[i
++].present
= 1;
5737 if (skip_past_comma (&ptr
) == FAIL
)
5740 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5743 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5747 inst
.operands
[i
].reg
= val
;
5748 inst
.operands
[i
].isreg
= 1;
5749 inst
.operands
[i
].isvec
= 1;
5750 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5751 inst
.operands
[i
].vectype
= optype
;
5752 inst
.operands
[i
].present
= 1;
5754 if (rtype
== REG_TYPE_VFS
)
5758 if (skip_past_comma (&ptr
) == FAIL
)
5760 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5763 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5766 inst
.operands
[i
].reg
= val
;
5767 inst
.operands
[i
].isreg
= 1;
5768 inst
.operands
[i
].isvec
= 1;
5769 inst
.operands
[i
].issingle
= 1;
5770 inst
.operands
[i
].vectype
= optype
;
5771 inst
.operands
[i
].present
= 1;
5774 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5778 inst
.operands
[i
].reg
= val
;
5779 inst
.operands
[i
].isreg
= 1;
5780 inst
.operands
[i
].isvec
= 1;
5781 inst
.operands
[i
].issingle
= 1;
5782 inst
.operands
[i
].vectype
= optype
;
5783 inst
.operands
[i
++].present
= 1;
5788 first_error (_("parse error"));
5792 /* Successfully parsed the operands. Update args. */
5798 first_error (_("expected comma"));
5802 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5806 /* Use this macro when the operand constraints are different
5807 for ARM and THUMB (e.g. ldrd). */
5808 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
5809 ((arm_operand) | ((thumb_operand) << 16))
5811 /* Matcher codes for parse_operands. */
5812 enum operand_parse_code
5814 OP_stop
, /* end of line */
5816 OP_RR
, /* ARM register */
5817 OP_RRnpc
, /* ARM register, not r15 */
5818 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
5819 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5820 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
5821 optional trailing ! */
5822 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5823 OP_RCP
, /* Coprocessor number */
5824 OP_RCN
, /* Coprocessor register */
5825 OP_RF
, /* FPA register */
5826 OP_RVS
, /* VFP single precision register */
5827 OP_RVD
, /* VFP double precision register (0..15) */
5828 OP_RND
, /* Neon double precision register (0..31) */
5829 OP_RNQ
, /* Neon quad precision register */
5830 OP_RVSD
, /* VFP single or double precision register */
5831 OP_RNDQ
, /* Neon double or quad precision register */
5832 OP_RNSDQ
, /* Neon single, double or quad precision register */
5833 OP_RNSC
, /* Neon scalar D[X] */
5834 OP_RVC
, /* VFP control register */
5835 OP_RMF
, /* Maverick F register */
5836 OP_RMD
, /* Maverick D register */
5837 OP_RMFX
, /* Maverick FX register */
5838 OP_RMDX
, /* Maverick DX register */
5839 OP_RMAX
, /* Maverick AX register */
5840 OP_RMDS
, /* Maverick DSPSC register */
5841 OP_RIWR
, /* iWMMXt wR register */
5842 OP_RIWC
, /* iWMMXt wC register */
5843 OP_RIWG
, /* iWMMXt wCG register */
5844 OP_RXA
, /* XScale accumulator register */
5846 OP_REGLST
, /* ARM register list */
5847 OP_VRSLST
, /* VFP single-precision register list */
5848 OP_VRDLST
, /* VFP double-precision register list */
5849 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5850 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5851 OP_NSTRLST
, /* Neon element/structure list */
5853 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5854 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5855 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5856 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5857 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5858 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5859 OP_VMOV
, /* Neon VMOV operands. */
5860 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
5861 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5862 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5864 OP_I0
, /* immediate zero */
5865 OP_I7
, /* immediate value 0 .. 7 */
5866 OP_I15
, /* 0 .. 15 */
5867 OP_I16
, /* 1 .. 16 */
5868 OP_I16z
, /* 0 .. 16 */
5869 OP_I31
, /* 0 .. 31 */
5870 OP_I31w
, /* 0 .. 31, optional trailing ! */
5871 OP_I32
, /* 1 .. 32 */
5872 OP_I32z
, /* 0 .. 32 */
5873 OP_I63
, /* 0 .. 63 */
5874 OP_I63s
, /* -64 .. 63 */
5875 OP_I64
, /* 1 .. 64 */
5876 OP_I64z
, /* 0 .. 64 */
5877 OP_I255
, /* 0 .. 255 */
5879 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5880 OP_I7b
, /* 0 .. 7 */
5881 OP_I15b
, /* 0 .. 15 */
5882 OP_I31b
, /* 0 .. 31 */
5884 OP_SH
, /* shifter operand */
5885 OP_SHG
, /* shifter operand with possible group relocation */
5886 OP_ADDR
, /* Memory address expression (any mode) */
5887 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5888 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5889 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5890 OP_EXP
, /* arbitrary expression */
5891 OP_EXPi
, /* same, with optional immediate prefix */
5892 OP_EXPr
, /* same, with optional relocation suffix */
5893 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5895 OP_CPSF
, /* CPS flags */
5896 OP_ENDI
, /* Endianness specifier */
5897 OP_PSR
, /* CPSR/SPSR mask for msr */
5898 OP_COND
, /* conditional code */
5899 OP_TB
, /* Table branch. */
5901 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5902 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5904 OP_RRnpc_I0
, /* ARM register or literal 0 */
5905 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5906 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5907 OP_RF_IF
, /* FPA register or immediate */
5908 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5909 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5911 /* Optional operands. */
5912 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5913 OP_oI31b
, /* 0 .. 31 */
5914 OP_oI32b
, /* 1 .. 32 */
5915 OP_oIffffb
, /* 0 .. 65535 */
5916 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5918 OP_oRR
, /* ARM register */
5919 OP_oRRnpc
, /* ARM register, not the PC */
5920 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
5921 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5922 OP_oRND
, /* Optional Neon double precision register */
5923 OP_oRNQ
, /* Optional Neon quad precision register */
5924 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5925 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5926 OP_oSHll
, /* LSL immediate */
5927 OP_oSHar
, /* ASR immediate */
5928 OP_oSHllar
, /* LSL or ASR immediate */
5929 OP_oROR
, /* ROR 0/8/16/24 */
5930 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
5932 /* Some pre-defined mixed (ARM/THUMB) operands. */
5933 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
5934 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
5935 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
5937 OP_FIRST_OPTIONAL
= OP_oI7b
5940 /* Generic instruction operand parser. This does no encoding and no
5941 semantic validation; it merely squirrels values away in the inst
5942 structure. Returns SUCCESS or FAIL depending on whether the
5943 specified grammar matched. */
5945 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
5947 unsigned const int *upat
= pattern
;
5948 char *backtrack_pos
= 0;
5949 const char *backtrack_error
= 0;
5950 int i
, val
, backtrack_index
= 0;
5951 enum arm_reg_type rtype
;
5952 parse_operand_result result
;
5953 unsigned int op_parse_code
;
5955 #define po_char_or_fail(chr) \
5958 if (skip_past_char (&str, chr) == FAIL) \
5963 #define po_reg_or_fail(regtype) \
5966 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5967 & inst.operands[i].vectype); \
5970 first_error (_(reg_expected_msgs[regtype])); \
5973 inst.operands[i].reg = val; \
5974 inst.operands[i].isreg = 1; \
5975 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5976 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5977 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5978 || rtype == REG_TYPE_VFD \
5979 || rtype == REG_TYPE_NQ); \
5983 #define po_reg_or_goto(regtype, label) \
5986 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5987 & inst.operands[i].vectype); \
5991 inst.operands[i].reg = val; \
5992 inst.operands[i].isreg = 1; \
5993 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5994 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5995 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5996 || rtype == REG_TYPE_VFD \
5997 || rtype == REG_TYPE_NQ); \
6001 #define po_imm_or_fail(min, max, popt) \
6004 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6006 inst.operands[i].imm = val; \
6010 #define po_scalar_or_goto(elsz, label) \
6013 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6016 inst.operands[i].reg = val; \
6017 inst.operands[i].isscalar = 1; \
6021 #define po_misc_or_fail(expr) \
6029 #define po_misc_or_fail_no_backtrack(expr) \
6033 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6034 backtrack_pos = 0; \
6035 if (result != PARSE_OPERAND_SUCCESS) \
6040 #define po_barrier_or_imm(str) \
6043 val = parse_barrier (&str); \
6046 if (ISALPHA (*str)) \
6053 if ((inst.instruction & 0xf0) == 0x60 \
6056 /* ISB can only take SY as an option. */ \
6057 inst.error = _("invalid barrier type"); \
6064 skip_whitespace (str
);
6066 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6068 op_parse_code
= upat
[i
];
6069 if (op_parse_code
>= 1<<16)
6070 op_parse_code
= thumb
? (op_parse_code
>> 16)
6071 : (op_parse_code
& ((1<<16)-1));
6073 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6075 /* Remember where we are in case we need to backtrack. */
6076 gas_assert (!backtrack_pos
);
6077 backtrack_pos
= str
;
6078 backtrack_error
= inst
.error
;
6079 backtrack_index
= i
;
6082 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6083 po_char_or_fail (',');
6085 switch (op_parse_code
)
6093 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6094 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6095 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6096 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6097 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6098 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6100 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6102 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6104 /* Also accept generic coprocessor regs for unknown registers. */
6106 po_reg_or_fail (REG_TYPE_CN
);
6108 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6109 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6110 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6111 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6112 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6113 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6114 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6115 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6116 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6117 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6119 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6121 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6122 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6124 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6126 /* Neon scalar. Using an element size of 8 means that some invalid
6127 scalars are accepted here, so deal with those in later code. */
6128 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6132 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6135 po_imm_or_fail (0, 0, TRUE
);
6140 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6145 po_scalar_or_goto (8, try_rr
);
6148 po_reg_or_fail (REG_TYPE_RN
);
6154 po_scalar_or_goto (8, try_nsdq
);
6157 po_reg_or_fail (REG_TYPE_NSDQ
);
6163 po_scalar_or_goto (8, try_ndq
);
6166 po_reg_or_fail (REG_TYPE_NDQ
);
6172 po_scalar_or_goto (8, try_vfd
);
6175 po_reg_or_fail (REG_TYPE_VFD
);
6180 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6181 not careful then bad things might happen. */
6182 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6187 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6190 /* There's a possibility of getting a 64-bit immediate here, so
6191 we need special handling. */
6192 if (parse_big_immediate (&str
, i
) == FAIL
)
6194 inst
.error
= _("immediate value is out of range");
6202 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6205 po_imm_or_fail (0, 63, TRUE
);
6210 po_char_or_fail ('[');
6211 po_reg_or_fail (REG_TYPE_RN
);
6212 po_char_or_fail (']');
6218 po_reg_or_fail (REG_TYPE_RN
);
6219 if (skip_past_char (&str
, '!') == SUCCESS
)
6220 inst
.operands
[i
].writeback
= 1;
6224 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6225 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6226 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6227 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6228 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6229 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6230 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6231 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6232 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6233 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6234 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6235 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6237 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6239 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6240 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6242 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6243 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6244 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6246 /* Immediate variants */
6248 po_char_or_fail ('{');
6249 po_imm_or_fail (0, 255, TRUE
);
6250 po_char_or_fail ('}');
6254 /* The expression parser chokes on a trailing !, so we have
6255 to find it first and zap it. */
6258 while (*s
&& *s
!= ',')
6263 inst
.operands
[i
].writeback
= 1;
6265 po_imm_or_fail (0, 31, TRUE
);
6273 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6278 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6283 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6285 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6287 val
= parse_reloc (&str
);
6290 inst
.error
= _("unrecognized relocation suffix");
6293 else if (val
!= BFD_RELOC_UNUSED
)
6295 inst
.operands
[i
].imm
= val
;
6296 inst
.operands
[i
].hasreloc
= 1;
6301 /* Operand for MOVW or MOVT. */
6303 po_misc_or_fail (parse_half (&str
));
6306 /* Register or expression. */
6307 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6308 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6310 /* Register or immediate. */
6311 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6312 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6314 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6316 if (!is_immediate_prefix (*str
))
6319 val
= parse_fpa_immediate (&str
);
6322 /* FPA immediates are encoded as registers 8-15.
6323 parse_fpa_immediate has already applied the offset. */
6324 inst
.operands
[i
].reg
= val
;
6325 inst
.operands
[i
].isreg
= 1;
6328 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6329 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6331 /* Two kinds of register. */
6334 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6336 || (rege
->type
!= REG_TYPE_MMXWR
6337 && rege
->type
!= REG_TYPE_MMXWC
6338 && rege
->type
!= REG_TYPE_MMXWCG
))
6340 inst
.error
= _("iWMMXt data or control register expected");
6343 inst
.operands
[i
].reg
= rege
->number
;
6344 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6350 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6352 || (rege
->type
!= REG_TYPE_MMXWC
6353 && rege
->type
!= REG_TYPE_MMXWCG
))
6355 inst
.error
= _("iWMMXt control register expected");
6358 inst
.operands
[i
].reg
= rege
->number
;
6359 inst
.operands
[i
].isreg
= 1;
6364 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6365 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6366 case OP_oROR
: val
= parse_ror (&str
); break;
6367 case OP_PSR
: val
= parse_psr (&str
); break;
6368 case OP_COND
: val
= parse_cond (&str
); break;
6369 case OP_oBARRIER_I15
:
6370 po_barrier_or_imm (str
); break;
6372 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6377 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
6378 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
6381 val
= parse_psr (&str
);
6385 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6388 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6390 if (strncasecmp (str
, "APSR_", 5) == 0)
6397 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6398 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6399 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6400 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6401 default: found
= 16;
6405 inst
.operands
[i
].isvec
= 1;
6406 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6407 inst
.operands
[i
].reg
= REG_PC
;
6414 po_misc_or_fail (parse_tb (&str
));
6417 /* Register lists. */
6419 val
= parse_reg_list (&str
);
6422 inst
.operands
[1].writeback
= 1;
6428 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6432 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6436 /* Allow Q registers too. */
6437 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6442 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6444 inst
.operands
[i
].issingle
= 1;
6449 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6454 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6455 &inst
.operands
[i
].vectype
);
6458 /* Addressing modes */
6460 po_misc_or_fail (parse_address (&str
, i
));
6464 po_misc_or_fail_no_backtrack (
6465 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6469 po_misc_or_fail_no_backtrack (
6470 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6474 po_misc_or_fail_no_backtrack (
6475 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6479 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6483 po_misc_or_fail_no_backtrack (
6484 parse_shifter_operand_group_reloc (&str
, i
));
6488 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6492 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6496 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6500 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6503 /* Various value-based sanity checks and shared operations. We
6504 do not signal immediate failures for the register constraints;
6505 this allows a syntax error to take precedence. */
6506 switch (op_parse_code
)
6514 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6515 inst
.error
= BAD_PC
;
6520 if (inst
.operands
[i
].isreg
)
6522 if (inst
.operands
[i
].reg
== REG_PC
)
6523 inst
.error
= BAD_PC
;
6524 else if (inst
.operands
[i
].reg
== REG_SP
)
6525 inst
.error
= BAD_SP
;
6530 if (inst
.operands
[i
].isreg
6531 && inst
.operands
[i
].reg
== REG_PC
6532 && (inst
.operands
[i
].writeback
|| thumb
))
6533 inst
.error
= BAD_PC
;
6542 case OP_oBARRIER_I15
:
6551 inst
.operands
[i
].imm
= val
;
6558 /* If we get here, this operand was successfully parsed. */
6559 inst
.operands
[i
].present
= 1;
6563 inst
.error
= BAD_ARGS
;
6568 /* The parse routine should already have set inst.error, but set a
6569 default here just in case. */
6571 inst
.error
= _("syntax error");
6575 /* Do not backtrack over a trailing optional argument that
6576 absorbed some text. We will only fail again, with the
6577 'garbage following instruction' error message, which is
6578 probably less helpful than the current one. */
6579 if (backtrack_index
== i
&& backtrack_pos
!= str
6580 && upat
[i
+1] == OP_stop
)
6583 inst
.error
= _("syntax error");
6587 /* Try again, skipping the optional argument at backtrack_pos. */
6588 str
= backtrack_pos
;
6589 inst
.error
= backtrack_error
;
6590 inst
.operands
[backtrack_index
].present
= 0;
6591 i
= backtrack_index
;
6595 /* Check that we have parsed all the arguments. */
6596 if (*str
!= '\0' && !inst
.error
)
6597 inst
.error
= _("garbage following instruction");
6599 return inst
.error
? FAIL
: SUCCESS
;
6602 #undef po_char_or_fail
6603 #undef po_reg_or_fail
6604 #undef po_reg_or_goto
6605 #undef po_imm_or_fail
6606 #undef po_scalar_or_fail
6607 #undef po_barrier_or_imm
6609 /* Shorthand macro for instruction encoding functions issuing errors. */
6610 #define constraint(expr, err) \
6621 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6622 instructions are unpredictable if these registers are used. This
6623 is the BadReg predicate in ARM's Thumb-2 documentation. */
6624 #define reject_bad_reg(reg) \
6626 if (reg == REG_SP || reg == REG_PC) \
6628 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6633 /* If REG is R13 (the stack pointer), warn that its use is
6635 #define warn_deprecated_sp(reg) \
6637 if (warn_on_deprecated && reg == REG_SP) \
6638 as_warn (_("use of r13 is deprecated")); \
6641 /* Functions for operand encoding. ARM, then Thumb. */
6643 #define rotate_left(v, n) (v << n | v >> (32 - n))
6645 /* If VAL can be encoded in the immediate field of an ARM instruction,
6646 return the encoded form. Otherwise, return FAIL. */
6649 encode_arm_immediate (unsigned int val
)
6653 for (i
= 0; i
< 32; i
+= 2)
6654 if ((a
= rotate_left (val
, i
)) <= 0xff)
6655 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6660 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6661 return the encoded form. Otherwise, return FAIL. */
6663 encode_thumb32_immediate (unsigned int val
)
6670 for (i
= 1; i
<= 24; i
++)
6673 if ((val
& ~(0xff << i
)) == 0)
6674 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6678 if (val
== ((a
<< 16) | a
))
6680 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6684 if (val
== ((a
<< 16) | a
))
6685 return 0x200 | (a
>> 8);
6689 /* Encode a VFP SP or DP register number into inst.instruction. */
6692 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6694 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6697 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6700 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6703 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6708 first_error (_("D register out of range for selected VFP version"));
6716 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6720 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6724 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6728 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6732 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6736 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6744 /* Encode a <shift> in an ARM-format instruction. The immediate,
6745 if any, is handled by md_apply_fix. */
6747 encode_arm_shift (int i
)
6749 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6750 inst
.instruction
|= SHIFT_ROR
<< 5;
6753 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6754 if (inst
.operands
[i
].immisreg
)
6756 inst
.instruction
|= SHIFT_BY_REG
;
6757 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6760 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6765 encode_arm_shifter_operand (int i
)
6767 if (inst
.operands
[i
].isreg
)
6769 inst
.instruction
|= inst
.operands
[i
].reg
;
6770 encode_arm_shift (i
);
6773 inst
.instruction
|= INST_IMMEDIATE
;
6776 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6778 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6780 gas_assert (inst
.operands
[i
].isreg
);
6781 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6783 if (inst
.operands
[i
].preind
)
6787 inst
.error
= _("instruction does not accept preindexed addressing");
6790 inst
.instruction
|= PRE_INDEX
;
6791 if (inst
.operands
[i
].writeback
)
6792 inst
.instruction
|= WRITE_BACK
;
6795 else if (inst
.operands
[i
].postind
)
6797 gas_assert (inst
.operands
[i
].writeback
);
6799 inst
.instruction
|= WRITE_BACK
;
6801 else /* unindexed - only for coprocessor */
6803 inst
.error
= _("instruction does not accept unindexed addressing");
6807 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6808 && (((inst
.instruction
& 0x000f0000) >> 16)
6809 == ((inst
.instruction
& 0x0000f000) >> 12)))
6810 as_warn ((inst
.instruction
& LOAD_BIT
)
6811 ? _("destination register same as write-back base")
6812 : _("source register same as write-back base"));
6815 /* inst.operands[i] was set up by parse_address. Encode it into an
6816 ARM-format mode 2 load or store instruction. If is_t is true,
6817 reject forms that cannot be used with a T instruction (i.e. not
6820 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6822 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
6824 encode_arm_addr_mode_common (i
, is_t
);
6826 if (inst
.operands
[i
].immisreg
)
6828 constraint ((inst
.operands
[i
].imm
== REG_PC
6829 || (is_pc
&& inst
.operands
[i
].writeback
)),
6831 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6832 inst
.instruction
|= inst
.operands
[i
].imm
;
6833 if (!inst
.operands
[i
].negative
)
6834 inst
.instruction
|= INDEX_UP
;
6835 if (inst
.operands
[i
].shifted
)
6837 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6838 inst
.instruction
|= SHIFT_ROR
<< 5;
6841 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6842 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6846 else /* immediate offset in inst.reloc */
6848 if (is_pc
&& !inst
.reloc
.pc_rel
)
6850 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
6852 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
6853 cannot use PC in addressing.
6854 PC cannot be used in writeback addressing, either. */
6855 constraint ((is_t
|| inst
.operands
[i
].writeback
),
6858 /* Use of PC in str is deprecated for ARMv7. */
6859 if (warn_on_deprecated
6861 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
6862 as_warn (_("use of PC in this instruction is deprecated"));
6865 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6866 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6870 /* inst.operands[i] was set up by parse_address. Encode it into an
6871 ARM-format mode 3 load or store instruction. Reject forms that
6872 cannot be used with such instructions. If is_t is true, reject
6873 forms that cannot be used with a T instruction (i.e. not
6876 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6878 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6880 inst
.error
= _("instruction does not accept scaled register index");
6884 encode_arm_addr_mode_common (i
, is_t
);
6886 if (inst
.operands
[i
].immisreg
)
6888 constraint ((inst
.operands
[i
].imm
== REG_PC
6889 || inst
.operands
[i
].reg
== REG_PC
),
6891 inst
.instruction
|= inst
.operands
[i
].imm
;
6892 if (!inst
.operands
[i
].negative
)
6893 inst
.instruction
|= INDEX_UP
;
6895 else /* immediate offset in inst.reloc */
6897 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
6898 && inst
.operands
[i
].writeback
),
6900 inst
.instruction
|= HWOFFSET_IMM
;
6901 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6902 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6906 /* inst.operands[i] was set up by parse_address. Encode it into an
6907 ARM-format instruction. Reject all forms which cannot be encoded
6908 into a coprocessor load/store instruction. If wb_ok is false,
6909 reject use of writeback; if unind_ok is false, reject use of
6910 unindexed addressing. If reloc_override is not 0, use it instead
6911 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6912 (in which case it is preserved). */
6915 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6917 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6919 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6921 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6923 gas_assert (!inst
.operands
[i
].writeback
);
6926 inst
.error
= _("instruction does not support unindexed addressing");
6929 inst
.instruction
|= inst
.operands
[i
].imm
;
6930 inst
.instruction
|= INDEX_UP
;
6934 if (inst
.operands
[i
].preind
)
6935 inst
.instruction
|= PRE_INDEX
;
6937 if (inst
.operands
[i
].writeback
)
6939 if (inst
.operands
[i
].reg
== REG_PC
)
6941 inst
.error
= _("pc may not be used with write-back");
6946 inst
.error
= _("instruction does not support writeback");
6949 inst
.instruction
|= WRITE_BACK
;
6953 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
6954 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6955 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6956 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6959 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6961 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6967 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6968 Determine whether it can be performed with a move instruction; if
6969 it can, convert inst.instruction to that move instruction and
6970 return TRUE; if it can't, convert inst.instruction to a literal-pool
6971 load and return FALSE. If this is not a valid thing to do in the
6972 current context, set inst.error and return TRUE.
6974 inst.operands[i] describes the destination register. */
6977 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6982 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6986 if ((inst
.instruction
& tbit
) == 0)
6988 inst
.error
= _("invalid pseudo operation");
6991 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6993 inst
.error
= _("constant expression expected");
6996 if (inst
.reloc
.exp
.X_op
== O_constant
)
7000 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7002 /* This can be done with a mov(1) instruction. */
7003 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7004 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7010 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7013 /* This can be done with a mov instruction. */
7014 inst
.instruction
&= LITERAL_MASK
;
7015 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7016 inst
.instruction
|= value
& 0xfff;
7020 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7023 /* This can be done with a mvn instruction. */
7024 inst
.instruction
&= LITERAL_MASK
;
7025 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7026 inst
.instruction
|= value
& 0xfff;
7032 if (add_to_lit_pool () == FAIL
)
7034 inst
.error
= _("literal pool insertion failed");
7037 inst
.operands
[1].reg
= REG_PC
;
7038 inst
.operands
[1].isreg
= 1;
7039 inst
.operands
[1].preind
= 1;
7040 inst
.reloc
.pc_rel
= 1;
7041 inst
.reloc
.type
= (thumb_p
7042 ? BFD_RELOC_ARM_THUMB_OFFSET
7044 ? BFD_RELOC_ARM_HWLITERAL
7045 : BFD_RELOC_ARM_LITERAL
));
7049 /* Functions for instruction encoding, sorted by sub-architecture.
7050 First some generics; their names are taken from the conventional
7051 bit positions for register arguments in ARM format instructions. */
7061 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7067 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7068 inst
.instruction
|= inst
.operands
[1].reg
;
7074 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7075 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7081 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7082 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7088 unsigned Rn
= inst
.operands
[2].reg
;
7089 /* Enforce restrictions on SWP instruction. */
7090 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7092 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7093 _("Rn must not overlap other operands"));
7095 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7096 if (warn_on_deprecated
7097 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7098 as_warn (_("swp{b} use is deprecated for this architecture"));
7101 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7102 inst
.instruction
|= inst
.operands
[1].reg
;
7103 inst
.instruction
|= Rn
<< 16;
7109 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7110 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7111 inst
.instruction
|= inst
.operands
[2].reg
;
7117 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7118 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7119 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7120 || inst
.reloc
.exp
.X_add_number
!= 0),
7122 inst
.instruction
|= inst
.operands
[0].reg
;
7123 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7124 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7130 inst
.instruction
|= inst
.operands
[0].imm
;
7136 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7137 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7140 /* ARM instructions, in alphabetical order by function name (except
7141 that wrapper functions appear immediately after the function they
7144 /* This is a pseudo-op of the form "adr rd, label" to be converted
7145 into a relative address of the form "add rd, pc, #label-.-8". */
7150 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7152 /* Frag hacking will turn this into a sub instruction if the offset turns
7153 out to be negative. */
7154 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7155 inst
.reloc
.pc_rel
= 1;
7156 inst
.reloc
.exp
.X_add_number
-= 8;
7159 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7160 into a relative address of the form:
7161 add rd, pc, #low(label-.-8)"
7162 add rd, rd, #high(label-.-8)" */
7167 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7169 /* Frag hacking will turn this into a sub instruction if the offset turns
7170 out to be negative. */
7171 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7172 inst
.reloc
.pc_rel
= 1;
7173 inst
.size
= INSN_SIZE
* 2;
7174 inst
.reloc
.exp
.X_add_number
-= 8;
7180 if (!inst
.operands
[1].present
)
7181 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7182 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7183 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7184 encode_arm_shifter_operand (2);
7190 if (inst
.operands
[0].present
)
7192 constraint ((inst
.instruction
& 0xf0) != 0x40
7193 && inst
.operands
[0].imm
> 0xf
7194 && inst
.operands
[0].imm
< 0x0,
7195 _("bad barrier type"));
7196 inst
.instruction
|= inst
.operands
[0].imm
;
7199 inst
.instruction
|= 0xf;
7205 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7206 constraint (msb
> 32, _("bit-field extends past end of register"));
7207 /* The instruction encoding stores the LSB and MSB,
7208 not the LSB and width. */
7209 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7210 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7211 inst
.instruction
|= (msb
- 1) << 16;
7219 /* #0 in second position is alternative syntax for bfc, which is
7220 the same instruction but with REG_PC in the Rm field. */
7221 if (!inst
.operands
[1].isreg
)
7222 inst
.operands
[1].reg
= REG_PC
;
7224 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7225 constraint (msb
> 32, _("bit-field extends past end of register"));
7226 /* The instruction encoding stores the LSB and MSB,
7227 not the LSB and width. */
7228 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7229 inst
.instruction
|= inst
.operands
[1].reg
;
7230 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7231 inst
.instruction
|= (msb
- 1) << 16;
7237 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7238 _("bit-field extends past end of register"));
7239 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7240 inst
.instruction
|= inst
.operands
[1].reg
;
7241 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7242 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7245 /* ARM V5 breakpoint instruction (argument parse)
7246 BKPT <16 bit unsigned immediate>
7247 Instruction is not conditional.
7248 The bit pattern given in insns[] has the COND_ALWAYS condition,
7249 and it is an error if the caller tried to override that. */
7254 /* Top 12 of 16 bits to bits 19:8. */
7255 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7257 /* Bottom 4 of 16 bits to bits 3:0. */
7258 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7262 encode_branch (int default_reloc
)
7264 if (inst
.operands
[0].hasreloc
)
7266 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
7267 _("the only suffix valid here is '(plt)'"));
7268 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
7272 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7274 inst
.reloc
.pc_rel
= 1;
7281 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7282 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7285 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7292 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7294 if (inst
.cond
== COND_ALWAYS
)
7295 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7297 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7301 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7304 /* ARM V5 branch-link-exchange instruction (argument parse)
7305 BLX <target_addr> ie BLX(1)
7306 BLX{<condition>} <Rm> ie BLX(2)
7307 Unfortunately, there are two different opcodes for this mnemonic.
7308 So, the insns[].value is not used, and the code here zaps values
7309 into inst.instruction.
7310 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7315 if (inst
.operands
[0].isreg
)
7317 /* Arg is a register; the opcode provided by insns[] is correct.
7318 It is not illegal to do "blx pc", just useless. */
7319 if (inst
.operands
[0].reg
== REG_PC
)
7320 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7322 inst
.instruction
|= inst
.operands
[0].reg
;
7326 /* Arg is an address; this instruction cannot be executed
7327 conditionally, and the opcode must be adjusted.
7328 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7329 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7330 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7331 inst
.instruction
= 0xfa000000;
7332 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7339 bfd_boolean want_reloc
;
7341 if (inst
.operands
[0].reg
== REG_PC
)
7342 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7344 inst
.instruction
|= inst
.operands
[0].reg
;
7345 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7346 it is for ARMv4t or earlier. */
7347 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7348 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7352 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7357 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7361 /* ARM v5TEJ. Jump to Jazelle code. */
7366 if (inst
.operands
[0].reg
== REG_PC
)
7367 as_tsktsk (_("use of r15 in bxj is not really useful"));
7369 inst
.instruction
|= inst
.operands
[0].reg
;
7372 /* Co-processor data operation:
7373 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7374 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7378 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7379 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7380 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7381 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7382 inst
.instruction
|= inst
.operands
[4].reg
;
7383 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7389 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7390 encode_arm_shifter_operand (1);
7393 /* Transfer between coprocessor and ARM registers.
7394 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7399 No special properties. */
7406 Rd
= inst
.operands
[2].reg
;
7409 if (inst
.instruction
== 0xee000010
7410 || inst
.instruction
== 0xfe000010)
7412 reject_bad_reg (Rd
);
7415 constraint (Rd
== REG_SP
, BAD_SP
);
7420 if (inst
.instruction
== 0xe000010)
7421 constraint (Rd
== REG_PC
, BAD_PC
);
7425 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7426 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7427 inst
.instruction
|= Rd
<< 12;
7428 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7429 inst
.instruction
|= inst
.operands
[4].reg
;
7430 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7433 /* Transfer between coprocessor register and pair of ARM registers.
7434 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7439 Two XScale instructions are special cases of these:
7441 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7442 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7444 Result unpredictable if Rd or Rn is R15. */
7451 Rd
= inst
.operands
[2].reg
;
7452 Rn
= inst
.operands
[3].reg
;
7456 reject_bad_reg (Rd
);
7457 reject_bad_reg (Rn
);
7461 constraint (Rd
== REG_PC
, BAD_PC
);
7462 constraint (Rn
== REG_PC
, BAD_PC
);
7465 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7466 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7467 inst
.instruction
|= Rd
<< 12;
7468 inst
.instruction
|= Rn
<< 16;
7469 inst
.instruction
|= inst
.operands
[4].reg
;
7475 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7476 if (inst
.operands
[1].present
)
7478 inst
.instruction
|= CPSI_MMOD
;
7479 inst
.instruction
|= inst
.operands
[1].imm
;
7486 inst
.instruction
|= inst
.operands
[0].imm
;
7492 /* There is no IT instruction in ARM mode. We
7493 process it to do the validation as if in
7494 thumb mode, just in case the code gets
7495 assembled for thumb using the unified syntax. */
7500 set_it_insn_type (IT_INSN
);
7501 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7502 now_it
.cc
= inst
.operands
[0].imm
;
7509 int base_reg
= inst
.operands
[0].reg
;
7510 int range
= inst
.operands
[1].imm
;
7512 inst
.instruction
|= base_reg
<< 16;
7513 inst
.instruction
|= range
;
7515 if (inst
.operands
[1].writeback
)
7516 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7518 if (inst
.operands
[0].writeback
)
7520 inst
.instruction
|= WRITE_BACK
;
7521 /* Check for unpredictable uses of writeback. */
7522 if (inst
.instruction
& LOAD_BIT
)
7524 /* Not allowed in LDM type 2. */
7525 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7526 && ((range
& (1 << REG_PC
)) == 0))
7527 as_warn (_("writeback of base register is UNPREDICTABLE"));
7528 /* Only allowed if base reg not in list for other types. */
7529 else if (range
& (1 << base_reg
))
7530 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7534 /* Not allowed for type 2. */
7535 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7536 as_warn (_("writeback of base register is UNPREDICTABLE"));
7537 /* Only allowed if base reg not in list, or first in list. */
7538 else if ((range
& (1 << base_reg
))
7539 && (range
& ((1 << base_reg
) - 1)))
7540 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7545 /* ARMv5TE load-consecutive (argument parse)
7554 constraint (inst
.operands
[0].reg
% 2 != 0,
7555 _("first destination register must be even"));
7556 constraint (inst
.operands
[1].present
7557 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7558 _("can only load two consecutive registers"));
7559 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7560 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7562 if (!inst
.operands
[1].present
)
7563 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7565 if (inst
.instruction
& LOAD_BIT
)
7567 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7568 register and the first register written; we have to diagnose
7569 overlap between the base and the second register written here. */
7571 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7572 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7573 as_warn (_("base register written back, and overlaps "
7574 "second destination register"));
7576 /* For an index-register load, the index register must not overlap the
7577 destination (even if not write-back). */
7578 else if (inst
.operands
[2].immisreg
7579 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7580 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7581 as_warn (_("index register overlaps destination register"));
7584 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7585 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7591 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7592 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7593 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7594 || inst
.operands
[1].negative
7595 /* This can arise if the programmer has written
7597 or if they have mistakenly used a register name as the last
7600 It is very difficult to distinguish between these two cases
7601 because "rX" might actually be a label. ie the register
7602 name has been occluded by a symbol of the same name. So we
7603 just generate a general 'bad addressing mode' type error
7604 message and leave it up to the programmer to discover the
7605 true cause and fix their mistake. */
7606 || (inst
.operands
[1].reg
== REG_PC
),
7609 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7610 || inst
.reloc
.exp
.X_add_number
!= 0,
7611 _("offset must be zero in ARM encoding"));
7613 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
7615 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7616 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7617 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7623 constraint (inst
.operands
[0].reg
% 2 != 0,
7624 _("even register required"));
7625 constraint (inst
.operands
[1].present
7626 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7627 _("can only load two consecutive registers"));
7628 /* If op 1 were present and equal to PC, this function wouldn't
7629 have been called in the first place. */
7630 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7632 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7633 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7639 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7640 if (!inst
.operands
[1].isreg
)
7641 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7643 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7649 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7651 if (inst
.operands
[1].preind
)
7653 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7654 || inst
.reloc
.exp
.X_add_number
!= 0,
7655 _("this instruction requires a post-indexed address"));
7657 inst
.operands
[1].preind
= 0;
7658 inst
.operands
[1].postind
= 1;
7659 inst
.operands
[1].writeback
= 1;
7661 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7662 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7665 /* Halfword and signed-byte load/store operations. */
7670 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7671 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7672 if (!inst
.operands
[1].isreg
)
7673 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7675 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7681 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7683 if (inst
.operands
[1].preind
)
7685 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7686 || inst
.reloc
.exp
.X_add_number
!= 0,
7687 _("this instruction requires a post-indexed address"));
7689 inst
.operands
[1].preind
= 0;
7690 inst
.operands
[1].postind
= 1;
7691 inst
.operands
[1].writeback
= 1;
7693 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7694 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7697 /* Co-processor register load/store.
7698 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7702 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7703 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7704 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7710 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7711 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7712 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7713 && !(inst
.instruction
& 0x00400000))
7714 as_tsktsk (_("Rd and Rm should be different in mla"));
7716 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7717 inst
.instruction
|= inst
.operands
[1].reg
;
7718 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7719 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7725 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7726 encode_arm_shifter_operand (1);
7729 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7736 top
= (inst
.instruction
& 0x00400000) != 0;
7737 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7738 _(":lower16: not allowed this instruction"));
7739 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7740 _(":upper16: not allowed instruction"));
7741 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7742 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7744 imm
= inst
.reloc
.exp
.X_add_number
;
7745 /* The value is in two pieces: 0:11, 16:19. */
7746 inst
.instruction
|= (imm
& 0x00000fff);
7747 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7751 static void do_vfp_nsyn_opcode (const char *);
7754 do_vfp_nsyn_mrs (void)
7756 if (inst
.operands
[0].isvec
)
7758 if (inst
.operands
[1].reg
!= 1)
7759 first_error (_("operand 1 must be FPSCR"));
7760 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7761 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7762 do_vfp_nsyn_opcode ("fmstat");
7764 else if (inst
.operands
[1].isvec
)
7765 do_vfp_nsyn_opcode ("fmrx");
7773 do_vfp_nsyn_msr (void)
7775 if (inst
.operands
[0].isvec
)
7776 do_vfp_nsyn_opcode ("fmxr");
7786 unsigned Rt
= inst
.operands
[0].reg
;
7788 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
7790 inst
.error
= BAD_SP
;
7794 /* APSR_ sets isvec. All other refs to PC are illegal. */
7795 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
7797 inst
.error
= BAD_PC
;
7801 if (inst
.operands
[1].reg
!= 1)
7802 first_error (_("operand 1 must be FPSCR"));
7804 inst
.instruction
|= (Rt
<< 12);
7810 unsigned Rt
= inst
.operands
[1].reg
;
7813 reject_bad_reg (Rt
);
7814 else if (Rt
== REG_PC
)
7816 inst
.error
= BAD_PC
;
7820 if (inst
.operands
[0].reg
!= 1)
7821 first_error (_("operand 0 must be FPSCR"));
7823 inst
.instruction
|= (Rt
<< 12);
7829 if (do_vfp_nsyn_mrs () == SUCCESS
)
7832 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7833 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7835 _("'CPSR' or 'SPSR' expected"));
7836 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7837 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7838 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7841 /* Two possible forms:
7842 "{C|S}PSR_<field>, Rm",
7843 "{C|S}PSR_f, #expression". */
7848 if (do_vfp_nsyn_msr () == SUCCESS
)
7851 inst
.instruction
|= inst
.operands
[0].imm
;
7852 if (inst
.operands
[1].isreg
)
7853 inst
.instruction
|= inst
.operands
[1].reg
;
7856 inst
.instruction
|= INST_IMMEDIATE
;
7857 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7858 inst
.reloc
.pc_rel
= 0;
7865 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
7867 if (!inst
.operands
[2].present
)
7868 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7869 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7870 inst
.instruction
|= inst
.operands
[1].reg
;
7871 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7873 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7874 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7875 as_tsktsk (_("Rd and Rm should be different in mul"));
7878 /* Long Multiply Parser
7879 UMULL RdLo, RdHi, Rm, Rs
7880 SMULL RdLo, RdHi, Rm, Rs
7881 UMLAL RdLo, RdHi, Rm, Rs
7882 SMLAL RdLo, RdHi, Rm, Rs. */
7887 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7888 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7889 inst
.instruction
|= inst
.operands
[2].reg
;
7890 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7892 /* rdhi and rdlo must be different. */
7893 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7894 as_tsktsk (_("rdhi and rdlo must be different"));
7896 /* rdhi, rdlo and rm must all be different before armv6. */
7897 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7898 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7899 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7900 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7906 if (inst
.operands
[0].present
7907 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7909 /* Architectural NOP hints are CPSR sets with no bits selected. */
7910 inst
.instruction
&= 0xf0000000;
7911 inst
.instruction
|= 0x0320f000;
7912 if (inst
.operands
[0].present
)
7913 inst
.instruction
|= inst
.operands
[0].imm
;
7917 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7918 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7919 Condition defaults to COND_ALWAYS.
7920 Error if Rd, Rn or Rm are R15. */
7925 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7926 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7927 inst
.instruction
|= inst
.operands
[2].reg
;
7928 if (inst
.operands
[3].present
)
7929 encode_arm_shift (3);
7932 /* ARM V6 PKHTB (Argument Parse). */
7937 if (!inst
.operands
[3].present
)
7939 /* If the shift specifier is omitted, turn the instruction
7940 into pkhbt rd, rm, rn. */
7941 inst
.instruction
&= 0xfff00010;
7942 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7943 inst
.instruction
|= inst
.operands
[1].reg
;
7944 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7948 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7949 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7950 inst
.instruction
|= inst
.operands
[2].reg
;
7951 encode_arm_shift (3);
7955 /* ARMv5TE: Preload-Cache
7959 Syntactically, like LDR with B=1, W=0, L=1. */
7964 constraint (!inst
.operands
[0].isreg
,
7965 _("'[' expected after PLD mnemonic"));
7966 constraint (inst
.operands
[0].postind
,
7967 _("post-indexed expression used in preload instruction"));
7968 constraint (inst
.operands
[0].writeback
,
7969 _("writeback used in preload instruction"));
7970 constraint (!inst
.operands
[0].preind
,
7971 _("unindexed addressing used in preload instruction"));
7972 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7975 /* ARMv7: PLI <addr_mode> */
7979 constraint (!inst
.operands
[0].isreg
,
7980 _("'[' expected after PLI mnemonic"));
7981 constraint (inst
.operands
[0].postind
,
7982 _("post-indexed expression used in preload instruction"));
7983 constraint (inst
.operands
[0].writeback
,
7984 _("writeback used in preload instruction"));
7985 constraint (!inst
.operands
[0].preind
,
7986 _("unindexed addressing used in preload instruction"));
7987 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7988 inst
.instruction
&= ~PRE_INDEX
;
7994 inst
.operands
[1] = inst
.operands
[0];
7995 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7996 inst
.operands
[0].isreg
= 1;
7997 inst
.operands
[0].writeback
= 1;
7998 inst
.operands
[0].reg
= REG_SP
;
8002 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8003 word at the specified address and the following word
8005 Unconditionally executed.
8006 Error if Rn is R15. */
8011 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8012 if (inst
.operands
[0].writeback
)
8013 inst
.instruction
|= WRITE_BACK
;
8016 /* ARM V6 ssat (argument parse). */
8021 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8022 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
8023 inst
.instruction
|= inst
.operands
[2].reg
;
8025 if (inst
.operands
[3].present
)
8026 encode_arm_shift (3);
8029 /* ARM V6 usat (argument parse). */
8034 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8035 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8036 inst
.instruction
|= inst
.operands
[2].reg
;
8038 if (inst
.operands
[3].present
)
8039 encode_arm_shift (3);
8042 /* ARM V6 ssat16 (argument parse). */
8047 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8048 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
8049 inst
.instruction
|= inst
.operands
[2].reg
;
8055 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8056 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8057 inst
.instruction
|= inst
.operands
[2].reg
;
8060 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8061 preserving the other bits.
8063 setend <endian_specifier>, where <endian_specifier> is either
8069 if (inst
.operands
[0].imm
)
8070 inst
.instruction
|= 0x200;
8076 unsigned int Rm
= (inst
.operands
[1].present
8077 ? inst
.operands
[1].reg
8078 : inst
.operands
[0].reg
);
8080 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8081 inst
.instruction
|= Rm
;
8082 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8084 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8085 inst
.instruction
|= SHIFT_BY_REG
;
8088 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8094 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8095 inst
.reloc
.pc_rel
= 0;
8101 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8102 inst
.reloc
.pc_rel
= 0;
8105 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8106 SMLAxy{cond} Rd,Rm,Rs,Rn
8107 SMLAWy{cond} Rd,Rm,Rs,Rn
8108 Error if any register is R15. */
8113 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8114 inst
.instruction
|= inst
.operands
[1].reg
;
8115 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8116 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8119 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8120 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8121 Error if any register is R15.
8122 Warning if Rdlo == Rdhi. */
8127 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8128 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8129 inst
.instruction
|= inst
.operands
[2].reg
;
8130 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8132 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8133 as_tsktsk (_("rdhi and rdlo must be different"));
8136 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8137 SMULxy{cond} Rd,Rm,Rs
8138 Error if any register is R15. */
8143 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8144 inst
.instruction
|= inst
.operands
[1].reg
;
8145 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8148 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8149 the same for both ARM and Thumb-2. */
8156 if (inst
.operands
[0].present
)
8158 reg
= inst
.operands
[0].reg
;
8159 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8164 inst
.instruction
|= reg
<< 16;
8165 inst
.instruction
|= inst
.operands
[1].imm
;
8166 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8167 inst
.instruction
|= WRITE_BACK
;
8170 /* ARM V6 strex (argument parse). */
8175 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8176 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8177 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8178 || inst
.operands
[2].negative
8179 /* See comment in do_ldrex(). */
8180 || (inst
.operands
[2].reg
== REG_PC
),
8183 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8184 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8186 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8187 || inst
.reloc
.exp
.X_add_number
!= 0,
8188 _("offset must be zero in ARM encoding"));
8190 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8191 inst
.instruction
|= inst
.operands
[1].reg
;
8192 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8193 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8199 constraint (inst
.operands
[1].reg
% 2 != 0,
8200 _("even register required"));
8201 constraint (inst
.operands
[2].present
8202 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8203 _("can only store two consecutive registers"));
8204 /* If op 2 were present and equal to PC, this function wouldn't
8205 have been called in the first place. */
8206 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8208 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8209 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8210 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8213 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8214 inst
.instruction
|= inst
.operands
[1].reg
;
8215 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8218 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8219 extends it to 32-bits, and adds the result to a value in another
8220 register. You can specify a rotation by 0, 8, 16, or 24 bits
8221 before extracting the 16-bit value.
8222 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8223 Condition defaults to COND_ALWAYS.
8224 Error if any register uses R15. */
8229 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8230 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8231 inst
.instruction
|= inst
.operands
[2].reg
;
8232 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8237 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8238 Condition defaults to COND_ALWAYS.
8239 Error if any register uses R15. */
8244 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8245 inst
.instruction
|= inst
.operands
[1].reg
;
8246 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8249 /* VFP instructions. In a logical order: SP variant first, monad
8250 before dyad, arithmetic then move then load/store. */
8253 do_vfp_sp_monadic (void)
8255 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8256 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8260 do_vfp_sp_dyadic (void)
8262 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8263 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8264 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8268 do_vfp_sp_compare_z (void)
8270 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8274 do_vfp_dp_sp_cvt (void)
8276 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8277 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8281 do_vfp_sp_dp_cvt (void)
8283 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8284 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8288 do_vfp_reg_from_sp (void)
8290 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8291 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8295 do_vfp_reg2_from_sp2 (void)
8297 constraint (inst
.operands
[2].imm
!= 2,
8298 _("only two consecutive VFP SP registers allowed here"));
8299 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8300 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8301 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8305 do_vfp_sp_from_reg (void)
8307 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8308 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8312 do_vfp_sp2_from_reg2 (void)
8314 constraint (inst
.operands
[0].imm
!= 2,
8315 _("only two consecutive VFP SP registers allowed here"));
8316 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8317 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8318 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8322 do_vfp_sp_ldst (void)
8324 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8325 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8329 do_vfp_dp_ldst (void)
8331 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8332 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8337 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8339 if (inst
.operands
[0].writeback
)
8340 inst
.instruction
|= WRITE_BACK
;
8342 constraint (ldstm_type
!= VFP_LDSTMIA
,
8343 _("this addressing mode requires base-register writeback"));
8344 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8345 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8346 inst
.instruction
|= inst
.operands
[1].imm
;
8350 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8354 if (inst
.operands
[0].writeback
)
8355 inst
.instruction
|= WRITE_BACK
;
8357 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8358 _("this addressing mode requires base-register writeback"));
8360 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8361 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8363 count
= inst
.operands
[1].imm
<< 1;
8364 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8367 inst
.instruction
|= count
;
8371 do_vfp_sp_ldstmia (void)
8373 vfp_sp_ldstm (VFP_LDSTMIA
);
8377 do_vfp_sp_ldstmdb (void)
8379 vfp_sp_ldstm (VFP_LDSTMDB
);
8383 do_vfp_dp_ldstmia (void)
8385 vfp_dp_ldstm (VFP_LDSTMIA
);
8389 do_vfp_dp_ldstmdb (void)
8391 vfp_dp_ldstm (VFP_LDSTMDB
);
8395 do_vfp_xp_ldstmia (void)
8397 vfp_dp_ldstm (VFP_LDSTMIAX
);
8401 do_vfp_xp_ldstmdb (void)
8403 vfp_dp_ldstm (VFP_LDSTMDBX
);
8407 do_vfp_dp_rd_rm (void)
8409 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8410 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8414 do_vfp_dp_rn_rd (void)
8416 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8417 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8421 do_vfp_dp_rd_rn (void)
8423 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8424 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8428 do_vfp_dp_rd_rn_rm (void)
8430 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8431 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8432 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8438 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8442 do_vfp_dp_rm_rd_rn (void)
8444 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8445 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8446 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8449 /* VFPv3 instructions. */
8451 do_vfp_sp_const (void)
8453 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8454 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8455 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8459 do_vfp_dp_const (void)
8461 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8462 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8463 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8467 vfp_conv (int srcsize
)
8469 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8470 inst
.instruction
|= (immbits
& 1) << 5;
8471 inst
.instruction
|= (immbits
>> 1);
8475 do_vfp_sp_conv_16 (void)
8477 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8482 do_vfp_dp_conv_16 (void)
8484 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8489 do_vfp_sp_conv_32 (void)
8491 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8496 do_vfp_dp_conv_32 (void)
8498 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8502 /* FPA instructions. Also in a logical order. */
8507 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8508 inst
.instruction
|= inst
.operands
[1].reg
;
8512 do_fpa_ldmstm (void)
8514 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8515 switch (inst
.operands
[1].imm
)
8517 case 1: inst
.instruction
|= CP_T_X
; break;
8518 case 2: inst
.instruction
|= CP_T_Y
; break;
8519 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8524 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8526 /* The instruction specified "ea" or "fd", so we can only accept
8527 [Rn]{!}. The instruction does not really support stacking or
8528 unstacking, so we have to emulate these by setting appropriate
8529 bits and offsets. */
8530 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8531 || inst
.reloc
.exp
.X_add_number
!= 0,
8532 _("this instruction does not support indexing"));
8534 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8535 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8537 if (!(inst
.instruction
& INDEX_UP
))
8538 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8540 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8542 inst
.operands
[2].preind
= 0;
8543 inst
.operands
[2].postind
= 1;
8547 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8550 /* iWMMXt instructions: strictly in alphabetical order. */
8553 do_iwmmxt_tandorc (void)
8555 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8559 do_iwmmxt_textrc (void)
8561 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8562 inst
.instruction
|= inst
.operands
[1].imm
;
8566 do_iwmmxt_textrm (void)
8568 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8569 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8570 inst
.instruction
|= inst
.operands
[2].imm
;
8574 do_iwmmxt_tinsr (void)
8576 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8577 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8578 inst
.instruction
|= inst
.operands
[2].imm
;
8582 do_iwmmxt_tmia (void)
8584 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8585 inst
.instruction
|= inst
.operands
[1].reg
;
8586 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8590 do_iwmmxt_waligni (void)
8592 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8593 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8594 inst
.instruction
|= inst
.operands
[2].reg
;
8595 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8599 do_iwmmxt_wmerge (void)
8601 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8602 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8603 inst
.instruction
|= inst
.operands
[2].reg
;
8604 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8608 do_iwmmxt_wmov (void)
8610 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8611 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8612 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8613 inst
.instruction
|= inst
.operands
[1].reg
;
8617 do_iwmmxt_wldstbh (void)
8620 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8622 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8624 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8625 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8629 do_iwmmxt_wldstw (void)
8631 /* RIWR_RIWC clears .isreg for a control register. */
8632 if (!inst
.operands
[0].isreg
)
8634 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8635 inst
.instruction
|= 0xf0000000;
8638 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8639 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8643 do_iwmmxt_wldstd (void)
8645 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8646 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8647 && inst
.operands
[1].immisreg
)
8649 inst
.instruction
&= ~0x1a000ff;
8650 inst
.instruction
|= (0xf << 28);
8651 if (inst
.operands
[1].preind
)
8652 inst
.instruction
|= PRE_INDEX
;
8653 if (!inst
.operands
[1].negative
)
8654 inst
.instruction
|= INDEX_UP
;
8655 if (inst
.operands
[1].writeback
)
8656 inst
.instruction
|= WRITE_BACK
;
8657 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8658 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8659 inst
.instruction
|= inst
.operands
[1].imm
;
8662 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8666 do_iwmmxt_wshufh (void)
8668 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8669 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8670 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8671 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8675 do_iwmmxt_wzero (void)
8677 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8678 inst
.instruction
|= inst
.operands
[0].reg
;
8679 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8680 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8684 do_iwmmxt_wrwrwr_or_imm5 (void)
8686 if (inst
.operands
[2].isreg
)
8689 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8690 _("immediate operand requires iWMMXt2"));
8692 if (inst
.operands
[2].imm
== 0)
8694 switch ((inst
.instruction
>> 20) & 0xf)
8700 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8701 inst
.operands
[2].imm
= 16;
8702 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8708 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8709 inst
.operands
[2].imm
= 32;
8710 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8717 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8719 wrn
= (inst
.instruction
>> 16) & 0xf;
8720 inst
.instruction
&= 0xff0fff0f;
8721 inst
.instruction
|= wrn
;
8722 /* Bail out here; the instruction is now assembled. */
8727 /* Map 32 -> 0, etc. */
8728 inst
.operands
[2].imm
&= 0x1f;
8729 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8733 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8734 operations first, then control, shift, and load/store. */
8736 /* Insns like "foo X,Y,Z". */
8739 do_mav_triple (void)
8741 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8742 inst
.instruction
|= inst
.operands
[1].reg
;
8743 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8746 /* Insns like "foo W,X,Y,Z".
8747 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8752 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8753 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8754 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8755 inst
.instruction
|= inst
.operands
[3].reg
;
8758 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8762 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8765 /* Maverick shift immediate instructions.
8766 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8767 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8772 int imm
= inst
.operands
[2].imm
;
8774 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8775 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8777 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8778 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8779 Bit 4 should be 0. */
8780 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8782 inst
.instruction
|= imm
;
8785 /* XScale instructions. Also sorted arithmetic before move. */
8787 /* Xscale multiply-accumulate (argument parse)
8790 MIAxycc acc0,Rm,Rs. */
8795 inst
.instruction
|= inst
.operands
[1].reg
;
8796 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8799 /* Xscale move-accumulator-register (argument parse)
8801 MARcc acc0,RdLo,RdHi. */
8806 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8807 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8810 /* Xscale move-register-accumulator (argument parse)
8812 MRAcc RdLo,RdHi,acc0. */
8817 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8818 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8819 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8822 /* Encoding functions relevant only to Thumb. */
8824 /* inst.operands[i] is a shifted-register operand; encode
8825 it into inst.instruction in the format used by Thumb32. */
8828 encode_thumb32_shifted_operand (int i
)
8830 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8831 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8833 constraint (inst
.operands
[i
].immisreg
,
8834 _("shift by register not allowed in thumb mode"));
8835 inst
.instruction
|= inst
.operands
[i
].reg
;
8836 if (shift
== SHIFT_RRX
)
8837 inst
.instruction
|= SHIFT_ROR
<< 4;
8840 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8841 _("expression too complex"));
8843 constraint (value
> 32
8844 || (value
== 32 && (shift
== SHIFT_LSL
8845 || shift
== SHIFT_ROR
)),
8846 _("shift expression is too large"));
8850 else if (value
== 32)
8853 inst
.instruction
|= shift
<< 4;
8854 inst
.instruction
|= (value
& 0x1c) << 10;
8855 inst
.instruction
|= (value
& 0x03) << 6;
8860 /* inst.operands[i] was set up by parse_address. Encode it into a
8861 Thumb32 format load or store instruction. Reject forms that cannot
8862 be used with such instructions. If is_t is true, reject forms that
8863 cannot be used with a T instruction; if is_d is true, reject forms
8864 that cannot be used with a D instruction. If it is a store insn,
8868 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8870 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8872 constraint (!inst
.operands
[i
].isreg
,
8873 _("Instruction does not support =N addresses"));
8875 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8876 if (inst
.operands
[i
].immisreg
)
8878 constraint (is_pc
, BAD_PC_ADDRESSING
);
8879 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8880 constraint (inst
.operands
[i
].negative
,
8881 _("Thumb does not support negative register indexing"));
8882 constraint (inst
.operands
[i
].postind
,
8883 _("Thumb does not support register post-indexing"));
8884 constraint (inst
.operands
[i
].writeback
,
8885 _("Thumb does not support register indexing with writeback"));
8886 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8887 _("Thumb supports only LSL in shifted register indexing"));
8889 inst
.instruction
|= inst
.operands
[i
].imm
;
8890 if (inst
.operands
[i
].shifted
)
8892 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8893 _("expression too complex"));
8894 constraint (inst
.reloc
.exp
.X_add_number
< 0
8895 || inst
.reloc
.exp
.X_add_number
> 3,
8896 _("shift out of range"));
8897 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8899 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8901 else if (inst
.operands
[i
].preind
)
8903 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
8904 constraint (is_t
&& inst
.operands
[i
].writeback
,
8905 _("cannot use writeback with this instruction"));
8906 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
8907 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
8911 inst
.instruction
|= 0x01000000;
8912 if (inst
.operands
[i
].writeback
)
8913 inst
.instruction
|= 0x00200000;
8917 inst
.instruction
|= 0x00000c00;
8918 if (inst
.operands
[i
].writeback
)
8919 inst
.instruction
|= 0x00000100;
8921 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8923 else if (inst
.operands
[i
].postind
)
8925 gas_assert (inst
.operands
[i
].writeback
);
8926 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8927 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8930 inst
.instruction
|= 0x00200000;
8932 inst
.instruction
|= 0x00000900;
8933 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8935 else /* unindexed - only for coprocessor */
8936 inst
.error
= _("instruction does not accept unindexed addressing");
8939 /* Table of Thumb instructions which exist in both 16- and 32-bit
8940 encodings (the latter only in post-V6T2 cores). The index is the
8941 value used in the insns table below. When there is more than one
8942 possible 16-bit encoding for the instruction, this table always
8944 Also contains several pseudo-instructions used during relaxation. */
8945 #define T16_32_TAB \
8946 X(_adc, 4140, eb400000), \
8947 X(_adcs, 4140, eb500000), \
8948 X(_add, 1c00, eb000000), \
8949 X(_adds, 1c00, eb100000), \
8950 X(_addi, 0000, f1000000), \
8951 X(_addis, 0000, f1100000), \
8952 X(_add_pc,000f, f20f0000), \
8953 X(_add_sp,000d, f10d0000), \
8954 X(_adr, 000f, f20f0000), \
8955 X(_and, 4000, ea000000), \
8956 X(_ands, 4000, ea100000), \
8957 X(_asr, 1000, fa40f000), \
8958 X(_asrs, 1000, fa50f000), \
8959 X(_b, e000, f000b000), \
8960 X(_bcond, d000, f0008000), \
8961 X(_bic, 4380, ea200000), \
8962 X(_bics, 4380, ea300000), \
8963 X(_cmn, 42c0, eb100f00), \
8964 X(_cmp, 2800, ebb00f00), \
8965 X(_cpsie, b660, f3af8400), \
8966 X(_cpsid, b670, f3af8600), \
8967 X(_cpy, 4600, ea4f0000), \
8968 X(_dec_sp,80dd, f1ad0d00), \
8969 X(_eor, 4040, ea800000), \
8970 X(_eors, 4040, ea900000), \
8971 X(_inc_sp,00dd, f10d0d00), \
8972 X(_ldmia, c800, e8900000), \
8973 X(_ldr, 6800, f8500000), \
8974 X(_ldrb, 7800, f8100000), \
8975 X(_ldrh, 8800, f8300000), \
8976 X(_ldrsb, 5600, f9100000), \
8977 X(_ldrsh, 5e00, f9300000), \
8978 X(_ldr_pc,4800, f85f0000), \
8979 X(_ldr_pc2,4800, f85f0000), \
8980 X(_ldr_sp,9800, f85d0000), \
8981 X(_lsl, 0000, fa00f000), \
8982 X(_lsls, 0000, fa10f000), \
8983 X(_lsr, 0800, fa20f000), \
8984 X(_lsrs, 0800, fa30f000), \
8985 X(_mov, 2000, ea4f0000), \
8986 X(_movs, 2000, ea5f0000), \
8987 X(_mul, 4340, fb00f000), \
8988 X(_muls, 4340, ffffffff), /* no 32b muls */ \
8989 X(_mvn, 43c0, ea6f0000), \
8990 X(_mvns, 43c0, ea7f0000), \
8991 X(_neg, 4240, f1c00000), /* rsb #0 */ \
8992 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
8993 X(_orr, 4300, ea400000), \
8994 X(_orrs, 4300, ea500000), \
8995 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8996 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
8997 X(_rev, ba00, fa90f080), \
8998 X(_rev16, ba40, fa90f090), \
8999 X(_revsh, bac0, fa90f0b0), \
9000 X(_ror, 41c0, fa60f000), \
9001 X(_rors, 41c0, fa70f000), \
9002 X(_sbc, 4180, eb600000), \
9003 X(_sbcs, 4180, eb700000), \
9004 X(_stmia, c000, e8800000), \
9005 X(_str, 6000, f8400000), \
9006 X(_strb, 7000, f8000000), \
9007 X(_strh, 8000, f8200000), \
9008 X(_str_sp,9000, f84d0000), \
9009 X(_sub, 1e00, eba00000), \
9010 X(_subs, 1e00, ebb00000), \
9011 X(_subi, 8000, f1a00000), \
9012 X(_subis, 8000, f1b00000), \
9013 X(_sxtb, b240, fa4ff080), \
9014 X(_sxth, b200, fa0ff080), \
9015 X(_tst, 4200, ea100f00), \
9016 X(_uxtb, b2c0, fa5ff080), \
9017 X(_uxth, b280, fa1ff080), \
9018 X(_nop, bf00, f3af8000), \
9019 X(_yield, bf10, f3af8001), \
9020 X(_wfe, bf20, f3af8002), \
9021 X(_wfi, bf30, f3af8003), \
9022 X(_sev, bf40, f3af8004),
9024 /* To catch errors in encoding functions, the codes are all offset by
9025 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9026 as 16-bit instructions. */
9027 #define X(a,b,c) T_MNEM##a
9028 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
9031 #define X(a,b,c) 0x##b
9032 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
9033 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9036 #define X(a,b,c) 0x##c
9037 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
9038 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9039 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9043 /* Thumb instruction encoders, in alphabetical order. */
9048 do_t_add_sub_w (void)
9052 Rd
= inst
.operands
[0].reg
;
9053 Rn
= inst
.operands
[1].reg
;
9055 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9056 is the SP-{plus,minus}-immediate form of the instruction. */
9058 constraint (Rd
== REG_PC
, BAD_PC
);
9060 reject_bad_reg (Rd
);
9062 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
9063 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9066 /* Parse an add or subtract instruction. We get here with inst.instruction
9067 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9074 Rd
= inst
.operands
[0].reg
;
9075 Rs
= (inst
.operands
[1].present
9076 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9077 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9080 set_it_insn_type_last ();
9088 flags
= (inst
.instruction
== T_MNEM_adds
9089 || inst
.instruction
== T_MNEM_subs
);
9091 narrow
= !in_it_block ();
9093 narrow
= in_it_block ();
9094 if (!inst
.operands
[2].isreg
)
9098 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9100 add
= (inst
.instruction
== T_MNEM_add
9101 || inst
.instruction
== T_MNEM_adds
);
9103 if (inst
.size_req
!= 4)
9105 /* Attempt to use a narrow opcode, with relaxation if
9107 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9108 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9109 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9110 opcode
= T_MNEM_add_sp
;
9111 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9112 opcode
= T_MNEM_add_pc
;
9113 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9116 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9118 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9122 inst
.instruction
= THUMB_OP16(opcode
);
9123 inst
.instruction
|= (Rd
<< 4) | Rs
;
9124 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9125 if (inst
.size_req
!= 2)
9126 inst
.relax
= opcode
;
9129 constraint (inst
.size_req
== 2, BAD_HIREG
);
9131 if (inst
.size_req
== 4
9132 || (inst
.size_req
!= 2 && !opcode
))
9136 constraint (add
, BAD_PC
);
9137 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9138 _("only SUBS PC, LR, #const allowed"));
9139 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9140 _("expression too complex"));
9141 constraint (inst
.reloc
.exp
.X_add_number
< 0
9142 || inst
.reloc
.exp
.X_add_number
> 0xff,
9143 _("immediate value out of range"));
9144 inst
.instruction
= T2_SUBS_PC_LR
9145 | inst
.reloc
.exp
.X_add_number
;
9146 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9149 else if (Rs
== REG_PC
)
9151 /* Always use addw/subw. */
9152 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9153 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9157 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9158 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9161 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9163 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9165 inst
.instruction
|= Rd
<< 8;
9166 inst
.instruction
|= Rs
<< 16;
9171 Rn
= inst
.operands
[2].reg
;
9172 /* See if we can do this with a 16-bit instruction. */
9173 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9175 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9180 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9181 || inst
.instruction
== T_MNEM_add
)
9184 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9188 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9190 /* Thumb-1 cores (except v6-M) require at least one high
9191 register in a narrow non flag setting add. */
9192 if (Rd
> 7 || Rn
> 7
9193 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9194 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9201 inst
.instruction
= T_OPCODE_ADD_HI
;
9202 inst
.instruction
|= (Rd
& 8) << 4;
9203 inst
.instruction
|= (Rd
& 7);
9204 inst
.instruction
|= Rn
<< 3;
9210 constraint (Rd
== REG_PC
, BAD_PC
);
9211 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9212 constraint (Rs
== REG_PC
, BAD_PC
);
9213 reject_bad_reg (Rn
);
9215 /* If we get here, it can't be done in 16 bits. */
9216 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9217 _("shift must be constant"));
9218 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9219 inst
.instruction
|= Rd
<< 8;
9220 inst
.instruction
|= Rs
<< 16;
9221 encode_thumb32_shifted_operand (2);
9226 constraint (inst
.instruction
== T_MNEM_adds
9227 || inst
.instruction
== T_MNEM_subs
,
9230 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9232 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9233 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9236 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9238 inst
.instruction
|= (Rd
<< 4) | Rs
;
9239 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9243 Rn
= inst
.operands
[2].reg
;
9244 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9246 /* We now have Rd, Rs, and Rn set to registers. */
9247 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9249 /* Can't do this for SUB. */
9250 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9251 inst
.instruction
= T_OPCODE_ADD_HI
;
9252 inst
.instruction
|= (Rd
& 8) << 4;
9253 inst
.instruction
|= (Rd
& 7);
9255 inst
.instruction
|= Rn
<< 3;
9257 inst
.instruction
|= Rs
<< 3;
9259 constraint (1, _("dest must overlap one source register"));
9263 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9264 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9265 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9275 Rd
= inst
.operands
[0].reg
;
9276 reject_bad_reg (Rd
);
9278 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9280 /* Defer to section relaxation. */
9281 inst
.relax
= inst
.instruction
;
9282 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9283 inst
.instruction
|= Rd
<< 4;
9285 else if (unified_syntax
&& inst
.size_req
!= 2)
9287 /* Generate a 32-bit opcode. */
9288 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9289 inst
.instruction
|= Rd
<< 8;
9290 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9291 inst
.reloc
.pc_rel
= 1;
9295 /* Generate a 16-bit opcode. */
9296 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9297 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9298 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9299 inst
.reloc
.pc_rel
= 1;
9301 inst
.instruction
|= Rd
<< 4;
9305 /* Arithmetic instructions for which there is just one 16-bit
9306 instruction encoding, and it allows only two low registers.
9307 For maximal compatibility with ARM syntax, we allow three register
9308 operands even when Thumb-32 instructions are not available, as long
9309 as the first two are identical. For instance, both "sbc r0,r1" and
9310 "sbc r0,r0,r1" are allowed. */
9316 Rd
= inst
.operands
[0].reg
;
9317 Rs
= (inst
.operands
[1].present
9318 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9319 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9320 Rn
= inst
.operands
[2].reg
;
9322 reject_bad_reg (Rd
);
9323 reject_bad_reg (Rs
);
9324 if (inst
.operands
[2].isreg
)
9325 reject_bad_reg (Rn
);
9329 if (!inst
.operands
[2].isreg
)
9331 /* For an immediate, we always generate a 32-bit opcode;
9332 section relaxation will shrink it later if possible. */
9333 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9334 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9335 inst
.instruction
|= Rd
<< 8;
9336 inst
.instruction
|= Rs
<< 16;
9337 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9343 /* See if we can do this with a 16-bit instruction. */
9344 if (THUMB_SETS_FLAGS (inst
.instruction
))
9345 narrow
= !in_it_block ();
9347 narrow
= in_it_block ();
9349 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9351 if (inst
.operands
[2].shifted
)
9353 if (inst
.size_req
== 4)
9359 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9360 inst
.instruction
|= Rd
;
9361 inst
.instruction
|= Rn
<< 3;
9365 /* If we get here, it can't be done in 16 bits. */
9366 constraint (inst
.operands
[2].shifted
9367 && inst
.operands
[2].immisreg
,
9368 _("shift must be constant"));
9369 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9370 inst
.instruction
|= Rd
<< 8;
9371 inst
.instruction
|= Rs
<< 16;
9372 encode_thumb32_shifted_operand (2);
9377 /* On its face this is a lie - the instruction does set the
9378 flags. However, the only supported mnemonic in this mode
9380 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9382 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9383 _("unshifted register required"));
9384 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9385 constraint (Rd
!= Rs
,
9386 _("dest and source1 must be the same register"));
9388 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9389 inst
.instruction
|= Rd
;
9390 inst
.instruction
|= Rn
<< 3;
9394 /* Similarly, but for instructions where the arithmetic operation is
9395 commutative, so we can allow either of them to be different from
9396 the destination operand in a 16-bit instruction. For instance, all
9397 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9404 Rd
= inst
.operands
[0].reg
;
9405 Rs
= (inst
.operands
[1].present
9406 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9407 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9408 Rn
= inst
.operands
[2].reg
;
9410 reject_bad_reg (Rd
);
9411 reject_bad_reg (Rs
);
9412 if (inst
.operands
[2].isreg
)
9413 reject_bad_reg (Rn
);
9417 if (!inst
.operands
[2].isreg
)
9419 /* For an immediate, we always generate a 32-bit opcode;
9420 section relaxation will shrink it later if possible. */
9421 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9422 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9423 inst
.instruction
|= Rd
<< 8;
9424 inst
.instruction
|= Rs
<< 16;
9425 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9431 /* See if we can do this with a 16-bit instruction. */
9432 if (THUMB_SETS_FLAGS (inst
.instruction
))
9433 narrow
= !in_it_block ();
9435 narrow
= in_it_block ();
9437 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9439 if (inst
.operands
[2].shifted
)
9441 if (inst
.size_req
== 4)
9448 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9449 inst
.instruction
|= Rd
;
9450 inst
.instruction
|= Rn
<< 3;
9455 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9456 inst
.instruction
|= Rd
;
9457 inst
.instruction
|= Rs
<< 3;
9462 /* If we get here, it can't be done in 16 bits. */
9463 constraint (inst
.operands
[2].shifted
9464 && inst
.operands
[2].immisreg
,
9465 _("shift must be constant"));
9466 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9467 inst
.instruction
|= Rd
<< 8;
9468 inst
.instruction
|= Rs
<< 16;
9469 encode_thumb32_shifted_operand (2);
9474 /* On its face this is a lie - the instruction does set the
9475 flags. However, the only supported mnemonic in this mode
9477 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9479 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9480 _("unshifted register required"));
9481 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9483 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9484 inst
.instruction
|= Rd
;
9487 inst
.instruction
|= Rn
<< 3;
9489 inst
.instruction
|= Rs
<< 3;
9491 constraint (1, _("dest must overlap one source register"));
9498 if (inst
.operands
[0].present
)
9500 constraint ((inst
.instruction
& 0xf0) != 0x40
9501 && inst
.operands
[0].imm
> 0xf
9502 && inst
.operands
[0].imm
< 0x0,
9503 _("bad barrier type"));
9504 inst
.instruction
|= inst
.operands
[0].imm
;
9507 inst
.instruction
|= 0xf;
9514 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9515 constraint (msb
> 32, _("bit-field extends past end of register"));
9516 /* The instruction encoding stores the LSB and MSB,
9517 not the LSB and width. */
9518 Rd
= inst
.operands
[0].reg
;
9519 reject_bad_reg (Rd
);
9520 inst
.instruction
|= Rd
<< 8;
9521 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9522 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9523 inst
.instruction
|= msb
- 1;
9532 Rd
= inst
.operands
[0].reg
;
9533 reject_bad_reg (Rd
);
9535 /* #0 in second position is alternative syntax for bfc, which is
9536 the same instruction but with REG_PC in the Rm field. */
9537 if (!inst
.operands
[1].isreg
)
9541 Rn
= inst
.operands
[1].reg
;
9542 reject_bad_reg (Rn
);
9545 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9546 constraint (msb
> 32, _("bit-field extends past end of register"));
9547 /* The instruction encoding stores the LSB and MSB,
9548 not the LSB and width. */
9549 inst
.instruction
|= Rd
<< 8;
9550 inst
.instruction
|= Rn
<< 16;
9551 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9552 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9553 inst
.instruction
|= msb
- 1;
9561 Rd
= inst
.operands
[0].reg
;
9562 Rn
= inst
.operands
[1].reg
;
9564 reject_bad_reg (Rd
);
9565 reject_bad_reg (Rn
);
9567 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9568 _("bit-field extends past end of register"));
9569 inst
.instruction
|= Rd
<< 8;
9570 inst
.instruction
|= Rn
<< 16;
9571 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9572 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9573 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9576 /* ARM V5 Thumb BLX (argument parse)
9577 BLX <target_addr> which is BLX(1)
9578 BLX <Rm> which is BLX(2)
9579 Unfortunately, there are two different opcodes for this mnemonic.
9580 So, the insns[].value is not used, and the code here zaps values
9581 into inst.instruction.
9583 ??? How to take advantage of the additional two bits of displacement
9584 available in Thumb32 mode? Need new relocation? */
9589 set_it_insn_type_last ();
9591 if (inst
.operands
[0].isreg
)
9593 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9594 /* We have a register, so this is BLX(2). */
9595 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9599 /* No register. This must be BLX(1). */
9600 inst
.instruction
= 0xf000e800;
9601 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9602 inst
.reloc
.pc_rel
= 1;
9613 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9617 /* Conditional branches inside IT blocks are encoded as unconditional
9624 if (cond
!= COND_ALWAYS
)
9625 opcode
= T_MNEM_bcond
;
9627 opcode
= inst
.instruction
;
9629 if (unified_syntax
&& inst
.size_req
== 4)
9631 inst
.instruction
= THUMB_OP32(opcode
);
9632 if (cond
== COND_ALWAYS
)
9633 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9636 gas_assert (cond
!= 0xF);
9637 inst
.instruction
|= cond
<< 22;
9638 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9643 inst
.instruction
= THUMB_OP16(opcode
);
9644 if (cond
== COND_ALWAYS
)
9645 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9648 inst
.instruction
|= cond
<< 8;
9649 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9651 /* Allow section relaxation. */
9652 if (unified_syntax
&& inst
.size_req
!= 2)
9653 inst
.relax
= opcode
;
9656 inst
.reloc
.pc_rel
= 1;
9662 constraint (inst
.cond
!= COND_ALWAYS
,
9663 _("instruction is always unconditional"));
9664 if (inst
.operands
[0].present
)
9666 constraint (inst
.operands
[0].imm
> 255,
9667 _("immediate value out of range"));
9668 inst
.instruction
|= inst
.operands
[0].imm
;
9669 set_it_insn_type (NEUTRAL_IT_INSN
);
9674 do_t_branch23 (void)
9676 set_it_insn_type_last ();
9677 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9678 inst
.reloc
.pc_rel
= 1;
9680 #if defined(OBJ_COFF)
9681 /* If the destination of the branch is a defined symbol which does not have
9682 the THUMB_FUNC attribute, then we must be calling a function which has
9683 the (interfacearm) attribute. We look for the Thumb entry point to that
9684 function and change the branch to refer to that function instead. */
9685 if ( inst
.reloc
.exp
.X_op
== O_symbol
9686 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9687 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9688 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9689 inst
.reloc
.exp
.X_add_symbol
=
9690 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9697 set_it_insn_type_last ();
9698 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9699 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9700 should cause the alignment to be checked once it is known. This is
9701 because BX PC only works if the instruction is word aligned. */
9709 set_it_insn_type_last ();
9710 Rm
= inst
.operands
[0].reg
;
9711 reject_bad_reg (Rm
);
9712 inst
.instruction
|= Rm
<< 16;
9721 Rd
= inst
.operands
[0].reg
;
9722 Rm
= inst
.operands
[1].reg
;
9724 reject_bad_reg (Rd
);
9725 reject_bad_reg (Rm
);
9727 inst
.instruction
|= Rd
<< 8;
9728 inst
.instruction
|= Rm
<< 16;
9729 inst
.instruction
|= Rm
;
9735 set_it_insn_type (OUTSIDE_IT_INSN
);
9736 inst
.instruction
|= inst
.operands
[0].imm
;
9742 set_it_insn_type (OUTSIDE_IT_INSN
);
9744 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9745 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9747 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9748 inst
.instruction
= 0xf3af8000;
9749 inst
.instruction
|= imod
<< 9;
9750 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9751 if (inst
.operands
[1].present
)
9752 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9756 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9757 && (inst
.operands
[0].imm
& 4),
9758 _("selected processor does not support 'A' form "
9759 "of this instruction"));
9760 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9761 _("Thumb does not support the 2-argument "
9762 "form of this instruction"));
9763 inst
.instruction
|= inst
.operands
[0].imm
;
9767 /* THUMB CPY instruction (argument parse). */
9772 if (inst
.size_req
== 4)
9774 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9775 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9776 inst
.instruction
|= inst
.operands
[1].reg
;
9780 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9781 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9782 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9789 set_it_insn_type (OUTSIDE_IT_INSN
);
9790 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9791 inst
.instruction
|= inst
.operands
[0].reg
;
9792 inst
.reloc
.pc_rel
= 1;
9793 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9799 inst
.instruction
|= inst
.operands
[0].imm
;
9805 unsigned Rd
, Rn
, Rm
;
9807 Rd
= inst
.operands
[0].reg
;
9808 Rn
= (inst
.operands
[1].present
9809 ? inst
.operands
[1].reg
: Rd
);
9810 Rm
= inst
.operands
[2].reg
;
9812 reject_bad_reg (Rd
);
9813 reject_bad_reg (Rn
);
9814 reject_bad_reg (Rm
);
9816 inst
.instruction
|= Rd
<< 8;
9817 inst
.instruction
|= Rn
<< 16;
9818 inst
.instruction
|= Rm
;
9824 if (unified_syntax
&& inst
.size_req
== 4)
9825 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9827 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9833 unsigned int cond
= inst
.operands
[0].imm
;
9835 set_it_insn_type (IT_INSN
);
9836 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
9839 /* If the condition is a negative condition, invert the mask. */
9840 if ((cond
& 0x1) == 0x0)
9842 unsigned int mask
= inst
.instruction
& 0x000f;
9844 if ((mask
& 0x7) == 0)
9845 /* no conversion needed */;
9846 else if ((mask
& 0x3) == 0)
9848 else if ((mask
& 0x1) == 0)
9853 inst
.instruction
&= 0xfff0;
9854 inst
.instruction
|= mask
;
9857 inst
.instruction
|= cond
<< 4;
9860 /* Helper function used for both push/pop and ldm/stm. */
9862 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9866 load
= (inst
.instruction
& (1 << 20)) != 0;
9868 if (mask
& (1 << 13))
9869 inst
.error
= _("SP not allowed in register list");
9871 if ((mask
& (1 << base
)) != 0
9873 inst
.error
= _("having the base register in the register list when "
9874 "using write back is UNPREDICTABLE");
9878 if (mask
& (1 << 15))
9880 if (mask
& (1 << 14))
9881 inst
.error
= _("LR and PC should not both be in register list");
9883 set_it_insn_type_last ();
9888 if (mask
& (1 << 15))
9889 inst
.error
= _("PC not allowed in register list");
9892 if ((mask
& (mask
- 1)) == 0)
9894 /* Single register transfers implemented as str/ldr. */
9897 if (inst
.instruction
& (1 << 23))
9898 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9900 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9904 if (inst
.instruction
& (1 << 23))
9905 inst
.instruction
= 0x00800000; /* ia -> [base] */
9907 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9910 inst
.instruction
|= 0xf8400000;
9912 inst
.instruction
|= 0x00100000;
9914 mask
= ffs (mask
) - 1;
9918 inst
.instruction
|= WRITE_BACK
;
9920 inst
.instruction
|= mask
;
9921 inst
.instruction
|= base
<< 16;
9927 /* This really doesn't seem worth it. */
9928 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9929 _("expression too complex"));
9930 constraint (inst
.operands
[1].writeback
,
9931 _("Thumb load/store multiple does not support {reglist}^"));
9939 /* See if we can use a 16-bit instruction. */
9940 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9941 && inst
.size_req
!= 4
9942 && !(inst
.operands
[1].imm
& ~0xff))
9944 mask
= 1 << inst
.operands
[0].reg
;
9946 if (inst
.operands
[0].reg
<= 7)
9948 if (inst
.instruction
== T_MNEM_stmia
9949 ? inst
.operands
[0].writeback
9950 : (inst
.operands
[0].writeback
9951 == !(inst
.operands
[1].imm
& mask
)))
9953 if (inst
.instruction
== T_MNEM_stmia
9954 && (inst
.operands
[1].imm
& mask
)
9955 && (inst
.operands
[1].imm
& (mask
- 1)))
9956 as_warn (_("value stored for r%d is UNKNOWN"),
9957 inst
.operands
[0].reg
);
9959 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9960 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9961 inst
.instruction
|= inst
.operands
[1].imm
;
9964 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
9966 /* This means 1 register in reg list one of 3 situations:
9967 1. Instruction is stmia, but without writeback.
9968 2. lmdia without writeback, but with Rn not in
9970 3. ldmia with writeback, but with Rn in reglist.
9971 Case 3 is UNPREDICTABLE behaviour, so we handle
9972 case 1 and 2 which can be converted into a 16-bit
9973 str or ldr. The SP cases are handled below. */
9974 unsigned long opcode
;
9975 /* First, record an error for Case 3. */
9976 if (inst
.operands
[1].imm
& mask
9977 && inst
.operands
[0].writeback
)
9979 _("having the base register in the register list when "
9980 "using write back is UNPREDICTABLE");
9982 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
9984 inst
.instruction
= THUMB_OP16 (opcode
);
9985 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9986 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
9990 else if (inst
.operands
[0] .reg
== REG_SP
)
9992 if (inst
.operands
[0].writeback
)
9995 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9996 ? T_MNEM_push
: T_MNEM_pop
);
9997 inst
.instruction
|= inst
.operands
[1].imm
;
10000 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10003 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10004 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
10005 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
10013 if (inst
.instruction
< 0xffff)
10014 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10016 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
10017 inst
.operands
[0].writeback
);
10022 constraint (inst
.operands
[0].reg
> 7
10023 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
10024 constraint (inst
.instruction
!= T_MNEM_ldmia
10025 && inst
.instruction
!= T_MNEM_stmia
,
10026 _("Thumb-2 instruction only valid in unified syntax"));
10027 if (inst
.instruction
== T_MNEM_stmia
)
10029 if (!inst
.operands
[0].writeback
)
10030 as_warn (_("this instruction will write back the base register"));
10031 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
10032 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
10033 as_warn (_("value stored for r%d is UNKNOWN"),
10034 inst
.operands
[0].reg
);
10038 if (!inst
.operands
[0].writeback
10039 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10040 as_warn (_("this instruction will write back the base register"));
10041 else if (inst
.operands
[0].writeback
10042 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10043 as_warn (_("this instruction will not write back the base register"));
10046 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10047 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10048 inst
.instruction
|= inst
.operands
[1].imm
;
10055 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
10056 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
10057 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
10058 || inst
.operands
[1].negative
,
10061 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
10063 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10064 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10065 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10071 if (!inst
.operands
[1].present
)
10073 constraint (inst
.operands
[0].reg
== REG_LR
,
10074 _("r14 not allowed as first register "
10075 "when second register is omitted"));
10076 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10078 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10081 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10082 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10083 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10089 unsigned long opcode
;
10092 if (inst
.operands
[0].isreg
10093 && !inst
.operands
[0].preind
10094 && inst
.operands
[0].reg
== REG_PC
)
10095 set_it_insn_type_last ();
10097 opcode
= inst
.instruction
;
10098 if (unified_syntax
)
10100 if (!inst
.operands
[1].isreg
)
10102 if (opcode
<= 0xffff)
10103 inst
.instruction
= THUMB_OP32 (opcode
);
10104 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10107 if (inst
.operands
[1].isreg
10108 && !inst
.operands
[1].writeback
10109 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10110 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10111 && opcode
<= 0xffff
10112 && inst
.size_req
!= 4)
10114 /* Insn may have a 16-bit form. */
10115 Rn
= inst
.operands
[1].reg
;
10116 if (inst
.operands
[1].immisreg
)
10118 inst
.instruction
= THUMB_OP16 (opcode
);
10120 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10122 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10123 reject_bad_reg (inst
.operands
[1].imm
);
10125 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10126 && opcode
!= T_MNEM_ldrsb
)
10127 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10128 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10135 if (inst
.reloc
.pc_rel
)
10136 opcode
= T_MNEM_ldr_pc2
;
10138 opcode
= T_MNEM_ldr_pc
;
10142 if (opcode
== T_MNEM_ldr
)
10143 opcode
= T_MNEM_ldr_sp
;
10145 opcode
= T_MNEM_str_sp
;
10147 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10151 inst
.instruction
= inst
.operands
[0].reg
;
10152 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10154 inst
.instruction
|= THUMB_OP16 (opcode
);
10155 if (inst
.size_req
== 2)
10156 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10158 inst
.relax
= opcode
;
10162 /* Definitely a 32-bit variant. */
10164 /* Do some validations regarding addressing modes. */
10165 if (inst
.operands
[1].immisreg
&& opcode
!= T_MNEM_ldr
10166 && opcode
!= T_MNEM_str
)
10167 reject_bad_reg (inst
.operands
[1].imm
);
10169 inst
.instruction
= THUMB_OP32 (opcode
);
10170 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10171 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10175 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10177 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10179 /* Only [Rn,Rm] is acceptable. */
10180 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10181 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10182 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10183 || inst
.operands
[1].negative
,
10184 _("Thumb does not support this addressing mode"));
10185 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10189 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10190 if (!inst
.operands
[1].isreg
)
10191 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10194 constraint (!inst
.operands
[1].preind
10195 || inst
.operands
[1].shifted
10196 || inst
.operands
[1].writeback
,
10197 _("Thumb does not support this addressing mode"));
10198 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10200 constraint (inst
.instruction
& 0x0600,
10201 _("byte or halfword not valid for base register"));
10202 constraint (inst
.operands
[1].reg
== REG_PC
10203 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10204 _("r15 based store not allowed"));
10205 constraint (inst
.operands
[1].immisreg
,
10206 _("invalid base register for register offset"));
10208 if (inst
.operands
[1].reg
== REG_PC
)
10209 inst
.instruction
= T_OPCODE_LDR_PC
;
10210 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10211 inst
.instruction
= T_OPCODE_LDR_SP
;
10213 inst
.instruction
= T_OPCODE_STR_SP
;
10215 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10216 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10220 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10221 if (!inst
.operands
[1].immisreg
)
10223 /* Immediate offset. */
10224 inst
.instruction
|= inst
.operands
[0].reg
;
10225 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10226 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10230 /* Register offset. */
10231 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10232 constraint (inst
.operands
[1].negative
,
10233 _("Thumb does not support this addressing mode"));
10236 switch (inst
.instruction
)
10238 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10239 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10240 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10241 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10242 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10243 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10244 case 0x5600 /* ldrsb */:
10245 case 0x5e00 /* ldrsh */: break;
10249 inst
.instruction
|= inst
.operands
[0].reg
;
10250 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10251 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10257 if (!inst
.operands
[1].present
)
10259 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10260 constraint (inst
.operands
[0].reg
== REG_LR
,
10261 _("r14 not allowed here"));
10263 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10264 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10265 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10271 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10272 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10278 unsigned Rd
, Rn
, Rm
, Ra
;
10280 Rd
= inst
.operands
[0].reg
;
10281 Rn
= inst
.operands
[1].reg
;
10282 Rm
= inst
.operands
[2].reg
;
10283 Ra
= inst
.operands
[3].reg
;
10285 reject_bad_reg (Rd
);
10286 reject_bad_reg (Rn
);
10287 reject_bad_reg (Rm
);
10288 reject_bad_reg (Ra
);
10290 inst
.instruction
|= Rd
<< 8;
10291 inst
.instruction
|= Rn
<< 16;
10292 inst
.instruction
|= Rm
;
10293 inst
.instruction
|= Ra
<< 12;
10299 unsigned RdLo
, RdHi
, Rn
, Rm
;
10301 RdLo
= inst
.operands
[0].reg
;
10302 RdHi
= inst
.operands
[1].reg
;
10303 Rn
= inst
.operands
[2].reg
;
10304 Rm
= inst
.operands
[3].reg
;
10306 reject_bad_reg (RdLo
);
10307 reject_bad_reg (RdHi
);
10308 reject_bad_reg (Rn
);
10309 reject_bad_reg (Rm
);
10311 inst
.instruction
|= RdLo
<< 12;
10312 inst
.instruction
|= RdHi
<< 8;
10313 inst
.instruction
|= Rn
<< 16;
10314 inst
.instruction
|= Rm
;
10318 do_t_mov_cmp (void)
10322 Rn
= inst
.operands
[0].reg
;
10323 Rm
= inst
.operands
[1].reg
;
10326 set_it_insn_type_last ();
10328 if (unified_syntax
)
10330 int r0off
= (inst
.instruction
== T_MNEM_mov
10331 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10332 unsigned long opcode
;
10333 bfd_boolean narrow
;
10334 bfd_boolean low_regs
;
10336 low_regs
= (Rn
<= 7 && Rm
<= 7);
10337 opcode
= inst
.instruction
;
10338 if (in_it_block ())
10339 narrow
= opcode
!= T_MNEM_movs
;
10341 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10342 if (inst
.size_req
== 4
10343 || inst
.operands
[1].shifted
)
10346 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10347 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10348 && !inst
.operands
[1].shifted
10352 inst
.instruction
= T2_SUBS_PC_LR
;
10356 if (opcode
== T_MNEM_cmp
)
10358 constraint (Rn
== REG_PC
, BAD_PC
);
10361 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10363 warn_deprecated_sp (Rm
);
10364 /* R15 was documented as a valid choice for Rm in ARMv6,
10365 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10366 tools reject R15, so we do too. */
10367 constraint (Rm
== REG_PC
, BAD_PC
);
10370 reject_bad_reg (Rm
);
10372 else if (opcode
== T_MNEM_mov
10373 || opcode
== T_MNEM_movs
)
10375 if (inst
.operands
[1].isreg
)
10377 if (opcode
== T_MNEM_movs
)
10379 reject_bad_reg (Rn
);
10380 reject_bad_reg (Rm
);
10384 /* This is mov.n. */
10385 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10386 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10388 as_warn (_("Use of r%u as a source register is "
10389 "deprecated when r%u is the destination "
10390 "register."), Rm
, Rn
);
10395 /* This is mov.w. */
10396 constraint (Rn
== REG_PC
, BAD_PC
);
10397 constraint (Rm
== REG_PC
, BAD_PC
);
10398 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
10402 reject_bad_reg (Rn
);
10405 if (!inst
.operands
[1].isreg
)
10407 /* Immediate operand. */
10408 if (!in_it_block () && opcode
== T_MNEM_mov
)
10410 if (low_regs
&& narrow
)
10412 inst
.instruction
= THUMB_OP16 (opcode
);
10413 inst
.instruction
|= Rn
<< 8;
10414 if (inst
.size_req
== 2)
10415 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10417 inst
.relax
= opcode
;
10421 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10422 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10423 inst
.instruction
|= Rn
<< r0off
;
10424 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10427 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10428 && (inst
.instruction
== T_MNEM_mov
10429 || inst
.instruction
== T_MNEM_movs
))
10431 /* Register shifts are encoded as separate shift instructions. */
10432 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10434 if (in_it_block ())
10439 if (inst
.size_req
== 4)
10442 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10448 switch (inst
.operands
[1].shift_kind
)
10451 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10454 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10457 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10460 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10466 inst
.instruction
= opcode
;
10469 inst
.instruction
|= Rn
;
10470 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10475 inst
.instruction
|= CONDS_BIT
;
10477 inst
.instruction
|= Rn
<< 8;
10478 inst
.instruction
|= Rm
<< 16;
10479 inst
.instruction
|= inst
.operands
[1].imm
;
10484 /* Some mov with immediate shift have narrow variants.
10485 Register shifts are handled above. */
10486 if (low_regs
&& inst
.operands
[1].shifted
10487 && (inst
.instruction
== T_MNEM_mov
10488 || inst
.instruction
== T_MNEM_movs
))
10490 if (in_it_block ())
10491 narrow
= (inst
.instruction
== T_MNEM_mov
);
10493 narrow
= (inst
.instruction
== T_MNEM_movs
);
10498 switch (inst
.operands
[1].shift_kind
)
10500 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10501 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10502 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10503 default: narrow
= FALSE
; break;
10509 inst
.instruction
|= Rn
;
10510 inst
.instruction
|= Rm
<< 3;
10511 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10515 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10516 inst
.instruction
|= Rn
<< r0off
;
10517 encode_thumb32_shifted_operand (1);
10521 switch (inst
.instruction
)
10524 inst
.instruction
= T_OPCODE_MOV_HR
;
10525 inst
.instruction
|= (Rn
& 0x8) << 4;
10526 inst
.instruction
|= (Rn
& 0x7);
10527 inst
.instruction
|= Rm
<< 3;
10531 /* We know we have low registers at this point.
10532 Generate LSLS Rd, Rs, #0. */
10533 inst
.instruction
= T_OPCODE_LSL_I
;
10534 inst
.instruction
|= Rn
;
10535 inst
.instruction
|= Rm
<< 3;
10541 inst
.instruction
= T_OPCODE_CMP_LR
;
10542 inst
.instruction
|= Rn
;
10543 inst
.instruction
|= Rm
<< 3;
10547 inst
.instruction
= T_OPCODE_CMP_HR
;
10548 inst
.instruction
|= (Rn
& 0x8) << 4;
10549 inst
.instruction
|= (Rn
& 0x7);
10550 inst
.instruction
|= Rm
<< 3;
10557 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10559 /* PR 10443: Do not silently ignore shifted operands. */
10560 constraint (inst
.operands
[1].shifted
,
10561 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10563 if (inst
.operands
[1].isreg
)
10565 if (Rn
< 8 && Rm
< 8)
10567 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10568 since a MOV instruction produces unpredictable results. */
10569 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10570 inst
.instruction
= T_OPCODE_ADD_I3
;
10572 inst
.instruction
= T_OPCODE_CMP_LR
;
10574 inst
.instruction
|= Rn
;
10575 inst
.instruction
|= Rm
<< 3;
10579 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10580 inst
.instruction
= T_OPCODE_MOV_HR
;
10582 inst
.instruction
= T_OPCODE_CMP_HR
;
10588 constraint (Rn
> 7,
10589 _("only lo regs allowed with immediate"));
10590 inst
.instruction
|= Rn
<< 8;
10591 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10602 top
= (inst
.instruction
& 0x00800000) != 0;
10603 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10605 constraint (top
, _(":lower16: not allowed this instruction"));
10606 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10608 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10610 constraint (!top
, _(":upper16: not allowed this instruction"));
10611 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10614 Rd
= inst
.operands
[0].reg
;
10615 reject_bad_reg (Rd
);
10617 inst
.instruction
|= Rd
<< 8;
10618 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10620 imm
= inst
.reloc
.exp
.X_add_number
;
10621 inst
.instruction
|= (imm
& 0xf000) << 4;
10622 inst
.instruction
|= (imm
& 0x0800) << 15;
10623 inst
.instruction
|= (imm
& 0x0700) << 4;
10624 inst
.instruction
|= (imm
& 0x00ff);
10629 do_t_mvn_tst (void)
10633 Rn
= inst
.operands
[0].reg
;
10634 Rm
= inst
.operands
[1].reg
;
10636 if (inst
.instruction
== T_MNEM_cmp
10637 || inst
.instruction
== T_MNEM_cmn
)
10638 constraint (Rn
== REG_PC
, BAD_PC
);
10640 reject_bad_reg (Rn
);
10641 reject_bad_reg (Rm
);
10643 if (unified_syntax
)
10645 int r0off
= (inst
.instruction
== T_MNEM_mvn
10646 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10647 bfd_boolean narrow
;
10649 if (inst
.size_req
== 4
10650 || inst
.instruction
> 0xffff
10651 || inst
.operands
[1].shifted
10652 || Rn
> 7 || Rm
> 7)
10654 else if (inst
.instruction
== T_MNEM_cmn
)
10656 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10657 narrow
= !in_it_block ();
10659 narrow
= in_it_block ();
10661 if (!inst
.operands
[1].isreg
)
10663 /* For an immediate, we always generate a 32-bit opcode;
10664 section relaxation will shrink it later if possible. */
10665 if (inst
.instruction
< 0xffff)
10666 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10667 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10668 inst
.instruction
|= Rn
<< r0off
;
10669 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10673 /* See if we can do this with a 16-bit instruction. */
10676 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10677 inst
.instruction
|= Rn
;
10678 inst
.instruction
|= Rm
<< 3;
10682 constraint (inst
.operands
[1].shifted
10683 && inst
.operands
[1].immisreg
,
10684 _("shift must be constant"));
10685 if (inst
.instruction
< 0xffff)
10686 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10687 inst
.instruction
|= Rn
<< r0off
;
10688 encode_thumb32_shifted_operand (1);
10694 constraint (inst
.instruction
> 0xffff
10695 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10696 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10697 _("unshifted register required"));
10698 constraint (Rn
> 7 || Rm
> 7,
10701 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10702 inst
.instruction
|= Rn
;
10703 inst
.instruction
|= Rm
<< 3;
10713 if (do_vfp_nsyn_mrs () == SUCCESS
)
10716 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10719 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10720 _("selected processor does not support "
10721 "requested special purpose register"));
10725 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10726 _("selected processor does not support "
10727 "requested special purpose register"));
10728 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10729 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10730 _("'CPSR' or 'SPSR' expected"));
10733 Rd
= inst
.operands
[0].reg
;
10734 reject_bad_reg (Rd
);
10736 inst
.instruction
|= Rd
<< 8;
10737 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10738 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10747 if (do_vfp_nsyn_msr () == SUCCESS
)
10750 constraint (!inst
.operands
[1].isreg
,
10751 _("Thumb encoding does not support an immediate here"));
10752 flags
= inst
.operands
[0].imm
;
10755 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10756 _("selected processor does not support "
10757 "requested special purpose register"));
10761 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10762 _("selected processor does not support "
10763 "requested special purpose register"));
10767 Rn
= inst
.operands
[1].reg
;
10768 reject_bad_reg (Rn
);
10770 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10771 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
10772 inst
.instruction
|= (flags
& 0xff);
10773 inst
.instruction
|= Rn
<< 16;
10779 bfd_boolean narrow
;
10780 unsigned Rd
, Rn
, Rm
;
10782 if (!inst
.operands
[2].present
)
10783 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10785 Rd
= inst
.operands
[0].reg
;
10786 Rn
= inst
.operands
[1].reg
;
10787 Rm
= inst
.operands
[2].reg
;
10789 if (unified_syntax
)
10791 if (inst
.size_req
== 4
10797 else if (inst
.instruction
== T_MNEM_muls
)
10798 narrow
= !in_it_block ();
10800 narrow
= in_it_block ();
10804 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10805 constraint (Rn
> 7 || Rm
> 7,
10812 /* 16-bit MULS/Conditional MUL. */
10813 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10814 inst
.instruction
|= Rd
;
10817 inst
.instruction
|= Rm
<< 3;
10819 inst
.instruction
|= Rn
<< 3;
10821 constraint (1, _("dest must overlap one source register"));
10825 constraint (inst
.instruction
!= T_MNEM_mul
,
10826 _("Thumb-2 MUL must not set flags"));
10828 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10829 inst
.instruction
|= Rd
<< 8;
10830 inst
.instruction
|= Rn
<< 16;
10831 inst
.instruction
|= Rm
<< 0;
10833 reject_bad_reg (Rd
);
10834 reject_bad_reg (Rn
);
10835 reject_bad_reg (Rm
);
10842 unsigned RdLo
, RdHi
, Rn
, Rm
;
10844 RdLo
= inst
.operands
[0].reg
;
10845 RdHi
= inst
.operands
[1].reg
;
10846 Rn
= inst
.operands
[2].reg
;
10847 Rm
= inst
.operands
[3].reg
;
10849 reject_bad_reg (RdLo
);
10850 reject_bad_reg (RdHi
);
10851 reject_bad_reg (Rn
);
10852 reject_bad_reg (Rm
);
10854 inst
.instruction
|= RdLo
<< 12;
10855 inst
.instruction
|= RdHi
<< 8;
10856 inst
.instruction
|= Rn
<< 16;
10857 inst
.instruction
|= Rm
;
10860 as_tsktsk (_("rdhi and rdlo must be different"));
10866 set_it_insn_type (NEUTRAL_IT_INSN
);
10868 if (unified_syntax
)
10870 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10872 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10873 inst
.instruction
|= inst
.operands
[0].imm
;
10877 /* PR9722: Check for Thumb2 availability before
10878 generating a thumb2 nop instruction. */
10879 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
10881 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10882 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10885 inst
.instruction
= 0x46c0;
10890 constraint (inst
.operands
[0].present
,
10891 _("Thumb does not support NOP with hints"));
10892 inst
.instruction
= 0x46c0;
10899 if (unified_syntax
)
10901 bfd_boolean narrow
;
10903 if (THUMB_SETS_FLAGS (inst
.instruction
))
10904 narrow
= !in_it_block ();
10906 narrow
= in_it_block ();
10907 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10909 if (inst
.size_req
== 4)
10914 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10915 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10916 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10920 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10921 inst
.instruction
|= inst
.operands
[0].reg
;
10922 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10927 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10929 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10931 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10932 inst
.instruction
|= inst
.operands
[0].reg
;
10933 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10942 Rd
= inst
.operands
[0].reg
;
10943 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10945 reject_bad_reg (Rd
);
10946 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10947 reject_bad_reg (Rn
);
10949 inst
.instruction
|= Rd
<< 8;
10950 inst
.instruction
|= Rn
<< 16;
10952 if (!inst
.operands
[2].isreg
)
10954 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10955 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10961 Rm
= inst
.operands
[2].reg
;
10962 reject_bad_reg (Rm
);
10964 constraint (inst
.operands
[2].shifted
10965 && inst
.operands
[2].immisreg
,
10966 _("shift must be constant"));
10967 encode_thumb32_shifted_operand (2);
10974 unsigned Rd
, Rn
, Rm
;
10976 Rd
= inst
.operands
[0].reg
;
10977 Rn
= inst
.operands
[1].reg
;
10978 Rm
= inst
.operands
[2].reg
;
10980 reject_bad_reg (Rd
);
10981 reject_bad_reg (Rn
);
10982 reject_bad_reg (Rm
);
10984 inst
.instruction
|= Rd
<< 8;
10985 inst
.instruction
|= Rn
<< 16;
10986 inst
.instruction
|= Rm
;
10987 if (inst
.operands
[3].present
)
10989 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10990 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10991 _("expression too complex"));
10992 inst
.instruction
|= (val
& 0x1c) << 10;
10993 inst
.instruction
|= (val
& 0x03) << 6;
11000 if (!inst
.operands
[3].present
)
11004 inst
.instruction
&= ~0x00000020;
11006 /* PR 10168. Swap the Rm and Rn registers. */
11007 Rtmp
= inst
.operands
[1].reg
;
11008 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
11009 inst
.operands
[2].reg
= Rtmp
;
11017 if (inst
.operands
[0].immisreg
)
11018 reject_bad_reg (inst
.operands
[0].imm
);
11020 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11024 do_t_push_pop (void)
11028 constraint (inst
.operands
[0].writeback
,
11029 _("push/pop do not support {reglist}^"));
11030 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11031 _("expression too complex"));
11033 mask
= inst
.operands
[0].imm
;
11034 if ((mask
& ~0xff) == 0)
11035 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
11036 else if ((inst
.instruction
== T_MNEM_push
11037 && (mask
& ~0xff) == 1 << REG_LR
)
11038 || (inst
.instruction
== T_MNEM_pop
11039 && (mask
& ~0xff) == 1 << REG_PC
))
11041 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11042 inst
.instruction
|= THUMB_PP_PC_LR
;
11043 inst
.instruction
|= mask
& 0xff;
11045 else if (unified_syntax
)
11047 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11048 encode_thumb2_ldmstm (13, mask
, TRUE
);
11052 inst
.error
= _("invalid register list to push/pop instruction");
11062 Rd
= inst
.operands
[0].reg
;
11063 Rm
= inst
.operands
[1].reg
;
11065 reject_bad_reg (Rd
);
11066 reject_bad_reg (Rm
);
11068 inst
.instruction
|= Rd
<< 8;
11069 inst
.instruction
|= Rm
<< 16;
11070 inst
.instruction
|= Rm
;
11078 Rd
= inst
.operands
[0].reg
;
11079 Rm
= inst
.operands
[1].reg
;
11081 reject_bad_reg (Rd
);
11082 reject_bad_reg (Rm
);
11084 if (Rd
<= 7 && Rm
<= 7
11085 && inst
.size_req
!= 4)
11087 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11088 inst
.instruction
|= Rd
;
11089 inst
.instruction
|= Rm
<< 3;
11091 else if (unified_syntax
)
11093 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11094 inst
.instruction
|= Rd
<< 8;
11095 inst
.instruction
|= Rm
<< 16;
11096 inst
.instruction
|= Rm
;
11099 inst
.error
= BAD_HIREG
;
11107 Rd
= inst
.operands
[0].reg
;
11108 Rm
= inst
.operands
[1].reg
;
11110 reject_bad_reg (Rd
);
11111 reject_bad_reg (Rm
);
11113 inst
.instruction
|= Rd
<< 8;
11114 inst
.instruction
|= Rm
;
11122 Rd
= inst
.operands
[0].reg
;
11123 Rs
= (inst
.operands
[1].present
11124 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11125 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11127 reject_bad_reg (Rd
);
11128 reject_bad_reg (Rs
);
11129 if (inst
.operands
[2].isreg
)
11130 reject_bad_reg (inst
.operands
[2].reg
);
11132 inst
.instruction
|= Rd
<< 8;
11133 inst
.instruction
|= Rs
<< 16;
11134 if (!inst
.operands
[2].isreg
)
11136 bfd_boolean narrow
;
11138 if ((inst
.instruction
& 0x00100000) != 0)
11139 narrow
= !in_it_block ();
11141 narrow
= in_it_block ();
11143 if (Rd
> 7 || Rs
> 7)
11146 if (inst
.size_req
== 4 || !unified_syntax
)
11149 if (inst
.reloc
.exp
.X_op
!= O_constant
11150 || inst
.reloc
.exp
.X_add_number
!= 0)
11153 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11154 relaxation, but it doesn't seem worth the hassle. */
11157 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11158 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11159 inst
.instruction
|= Rs
<< 3;
11160 inst
.instruction
|= Rd
;
11164 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11165 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11169 encode_thumb32_shifted_operand (2);
11175 set_it_insn_type (OUTSIDE_IT_INSN
);
11176 if (inst
.operands
[0].imm
)
11177 inst
.instruction
|= 0x8;
11183 if (!inst
.operands
[1].present
)
11184 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11186 if (unified_syntax
)
11188 bfd_boolean narrow
;
11191 switch (inst
.instruction
)
11194 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11196 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11198 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11200 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11204 if (THUMB_SETS_FLAGS (inst
.instruction
))
11205 narrow
= !in_it_block ();
11207 narrow
= in_it_block ();
11208 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11210 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11212 if (inst
.operands
[2].isreg
11213 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11214 || inst
.operands
[2].reg
> 7))
11216 if (inst
.size_req
== 4)
11219 reject_bad_reg (inst
.operands
[0].reg
);
11220 reject_bad_reg (inst
.operands
[1].reg
);
11224 if (inst
.operands
[2].isreg
)
11226 reject_bad_reg (inst
.operands
[2].reg
);
11227 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11228 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11229 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11230 inst
.instruction
|= inst
.operands
[2].reg
;
11234 inst
.operands
[1].shifted
= 1;
11235 inst
.operands
[1].shift_kind
= shift_kind
;
11236 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11237 ? T_MNEM_movs
: T_MNEM_mov
);
11238 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11239 encode_thumb32_shifted_operand (1);
11240 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11241 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11246 if (inst
.operands
[2].isreg
)
11248 switch (shift_kind
)
11250 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11251 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11252 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11253 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11257 inst
.instruction
|= inst
.operands
[0].reg
;
11258 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11262 switch (shift_kind
)
11264 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11265 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11266 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11269 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11270 inst
.instruction
|= inst
.operands
[0].reg
;
11271 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11277 constraint (inst
.operands
[0].reg
> 7
11278 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11279 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11281 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11283 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11284 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11285 _("source1 and dest must be same register"));
11287 switch (inst
.instruction
)
11289 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11290 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11291 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11292 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11296 inst
.instruction
|= inst
.operands
[0].reg
;
11297 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11301 switch (inst
.instruction
)
11303 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11304 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11305 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11306 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11309 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11310 inst
.instruction
|= inst
.operands
[0].reg
;
11311 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11319 unsigned Rd
, Rn
, Rm
;
11321 Rd
= inst
.operands
[0].reg
;
11322 Rn
= inst
.operands
[1].reg
;
11323 Rm
= inst
.operands
[2].reg
;
11325 reject_bad_reg (Rd
);
11326 reject_bad_reg (Rn
);
11327 reject_bad_reg (Rm
);
11329 inst
.instruction
|= Rd
<< 8;
11330 inst
.instruction
|= Rn
<< 16;
11331 inst
.instruction
|= Rm
;
11337 unsigned Rd
, Rn
, Rm
;
11339 Rd
= inst
.operands
[0].reg
;
11340 Rm
= inst
.operands
[1].reg
;
11341 Rn
= inst
.operands
[2].reg
;
11343 reject_bad_reg (Rd
);
11344 reject_bad_reg (Rn
);
11345 reject_bad_reg (Rm
);
11347 inst
.instruction
|= Rd
<< 8;
11348 inst
.instruction
|= Rn
<< 16;
11349 inst
.instruction
|= Rm
;
11355 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11356 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11357 _("expression too complex"));
11358 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11359 inst
.instruction
|= (value
& 0xf000) >> 12;
11360 inst
.instruction
|= (value
& 0x0ff0);
11361 inst
.instruction
|= (value
& 0x000f) << 16;
11365 do_t_ssat_usat (int bias
)
11369 Rd
= inst
.operands
[0].reg
;
11370 Rn
= inst
.operands
[2].reg
;
11372 reject_bad_reg (Rd
);
11373 reject_bad_reg (Rn
);
11375 inst
.instruction
|= Rd
<< 8;
11376 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11377 inst
.instruction
|= Rn
<< 16;
11379 if (inst
.operands
[3].present
)
11381 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11383 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11385 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11386 _("expression too complex"));
11388 if (shift_amount
!= 0)
11390 constraint (shift_amount
> 31,
11391 _("shift expression is too large"));
11393 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11394 inst
.instruction
|= 0x00200000; /* sh bit. */
11396 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11397 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11405 do_t_ssat_usat (1);
11413 Rd
= inst
.operands
[0].reg
;
11414 Rn
= inst
.operands
[2].reg
;
11416 reject_bad_reg (Rd
);
11417 reject_bad_reg (Rn
);
11419 inst
.instruction
|= Rd
<< 8;
11420 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11421 inst
.instruction
|= Rn
<< 16;
11427 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11428 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11429 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11430 || inst
.operands
[2].negative
,
11433 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
11435 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11436 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11437 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11438 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11444 if (!inst
.operands
[2].present
)
11445 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11447 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11448 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11449 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
11452 inst
.instruction
|= inst
.operands
[0].reg
;
11453 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11454 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11455 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11461 unsigned Rd
, Rn
, Rm
;
11463 Rd
= inst
.operands
[0].reg
;
11464 Rn
= inst
.operands
[1].reg
;
11465 Rm
= inst
.operands
[2].reg
;
11467 reject_bad_reg (Rd
);
11468 reject_bad_reg (Rn
);
11469 reject_bad_reg (Rm
);
11471 inst
.instruction
|= Rd
<< 8;
11472 inst
.instruction
|= Rn
<< 16;
11473 inst
.instruction
|= Rm
;
11474 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11482 Rd
= inst
.operands
[0].reg
;
11483 Rm
= inst
.operands
[1].reg
;
11485 reject_bad_reg (Rd
);
11486 reject_bad_reg (Rm
);
11488 if (inst
.instruction
<= 0xffff
11489 && inst
.size_req
!= 4
11490 && Rd
<= 7 && Rm
<= 7
11491 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11493 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11494 inst
.instruction
|= Rd
;
11495 inst
.instruction
|= Rm
<< 3;
11497 else if (unified_syntax
)
11499 if (inst
.instruction
<= 0xffff)
11500 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11501 inst
.instruction
|= Rd
<< 8;
11502 inst
.instruction
|= Rm
;
11503 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11507 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11508 _("Thumb encoding does not support rotation"));
11509 constraint (1, BAD_HIREG
);
11516 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11525 half
= (inst
.instruction
& 0x10) != 0;
11526 set_it_insn_type_last ();
11527 constraint (inst
.operands
[0].immisreg
,
11528 _("instruction requires register index"));
11530 Rn
= inst
.operands
[0].reg
;
11531 Rm
= inst
.operands
[0].imm
;
11533 constraint (Rn
== REG_SP
, BAD_SP
);
11534 reject_bad_reg (Rm
);
11536 constraint (!half
&& inst
.operands
[0].shifted
,
11537 _("instruction does not allow shifted index"));
11538 inst
.instruction
|= (Rn
<< 16) | Rm
;
11544 do_t_ssat_usat (0);
11552 Rd
= inst
.operands
[0].reg
;
11553 Rn
= inst
.operands
[2].reg
;
11555 reject_bad_reg (Rd
);
11556 reject_bad_reg (Rn
);
11558 inst
.instruction
|= Rd
<< 8;
11559 inst
.instruction
|= inst
.operands
[1].imm
;
11560 inst
.instruction
|= Rn
<< 16;
11563 /* Neon instruction encoder helpers. */
11565 /* Encodings for the different types for various Neon opcodes. */
11567 /* An "invalid" code for the following tables. */
11570 struct neon_tab_entry
11573 unsigned float_or_poly
;
11574 unsigned scalar_or_imm
;
11577 /* Map overloaded Neon opcodes to their respective encodings. */
11578 #define NEON_ENC_TAB \
11579 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11580 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11581 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11582 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11583 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11584 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11585 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11586 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11587 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11588 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11589 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11590 /* Register variants of the following two instructions are encoded as
11591 vcge / vcgt with the operands reversed. */ \
11592 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11593 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11594 X(vfma, N_INV, 0x0000c10, N_INV), \
11595 X(vfms, N_INV, 0x0200c10, N_INV), \
11596 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11597 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11598 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11599 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11600 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11601 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11602 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11603 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11604 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11605 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11606 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11607 X(vshl, 0x0000400, N_INV, 0x0800510), \
11608 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11609 X(vand, 0x0000110, N_INV, 0x0800030), \
11610 X(vbic, 0x0100110, N_INV, 0x0800030), \
11611 X(veor, 0x1000110, N_INV, N_INV), \
11612 X(vorn, 0x0300110, N_INV, 0x0800010), \
11613 X(vorr, 0x0200110, N_INV, 0x0800010), \
11614 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11615 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11616 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11617 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11618 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11619 X(vst1, 0x0000000, 0x0800000, N_INV), \
11620 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11621 X(vst2, 0x0000100, 0x0800100, N_INV), \
11622 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11623 X(vst3, 0x0000200, 0x0800200, N_INV), \
11624 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11625 X(vst4, 0x0000300, 0x0800300, N_INV), \
11626 X(vmovn, 0x1b20200, N_INV, N_INV), \
11627 X(vtrn, 0x1b20080, N_INV, N_INV), \
11628 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11629 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11630 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11631 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11632 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11633 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11634 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11635 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11636 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11637 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11638 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11642 #define X(OPC,I,F,S) N_MNEM_##OPC
11647 static const struct neon_tab_entry neon_enc_tab
[] =
11649 #define X(OPC,I,F,S) { (I), (F), (S) }
11654 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
11655 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11656 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11657 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11658 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11659 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11660 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11661 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11662 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11663 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11664 #define NEON_ENC_SINGLE_(X) \
11665 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11666 #define NEON_ENC_DOUBLE_(X) \
11667 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11669 #define NEON_ENCODE(type, inst) \
11672 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
11673 inst.is_neon = 1; \
11677 #define check_neon_suffixes \
11680 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
11682 as_bad (_("invalid neon suffix for non neon instruction")); \
11688 /* Define shapes for instruction operands. The following mnemonic characters
11689 are used in this table:
11691 F - VFP S<n> register
11692 D - Neon D<n> register
11693 Q - Neon Q<n> register
11697 L - D<n> register list
11699 This table is used to generate various data:
11700 - enumerations of the form NS_DDR to be used as arguments to
11702 - a table classifying shapes into single, double, quad, mixed.
11703 - a table used to drive neon_select_shape. */
11705 #define NEON_SHAPE_DEF \
11706 X(3, (D, D, D), DOUBLE), \
11707 X(3, (Q, Q, Q), QUAD), \
11708 X(3, (D, D, I), DOUBLE), \
11709 X(3, (Q, Q, I), QUAD), \
11710 X(3, (D, D, S), DOUBLE), \
11711 X(3, (Q, Q, S), QUAD), \
11712 X(2, (D, D), DOUBLE), \
11713 X(2, (Q, Q), QUAD), \
11714 X(2, (D, S), DOUBLE), \
11715 X(2, (Q, S), QUAD), \
11716 X(2, (D, R), DOUBLE), \
11717 X(2, (Q, R), QUAD), \
11718 X(2, (D, I), DOUBLE), \
11719 X(2, (Q, I), QUAD), \
11720 X(3, (D, L, D), DOUBLE), \
11721 X(2, (D, Q), MIXED), \
11722 X(2, (Q, D), MIXED), \
11723 X(3, (D, Q, I), MIXED), \
11724 X(3, (Q, D, I), MIXED), \
11725 X(3, (Q, D, D), MIXED), \
11726 X(3, (D, Q, Q), MIXED), \
11727 X(3, (Q, Q, D), MIXED), \
11728 X(3, (Q, D, S), MIXED), \
11729 X(3, (D, Q, S), MIXED), \
11730 X(4, (D, D, D, I), DOUBLE), \
11731 X(4, (Q, Q, Q, I), QUAD), \
11732 X(2, (F, F), SINGLE), \
11733 X(3, (F, F, F), SINGLE), \
11734 X(2, (F, I), SINGLE), \
11735 X(2, (F, D), MIXED), \
11736 X(2, (D, F), MIXED), \
11737 X(3, (F, F, I), MIXED), \
11738 X(4, (R, R, F, F), SINGLE), \
11739 X(4, (F, F, R, R), SINGLE), \
11740 X(3, (D, R, R), DOUBLE), \
11741 X(3, (R, R, D), DOUBLE), \
11742 X(2, (S, R), SINGLE), \
11743 X(2, (R, S), SINGLE), \
11744 X(2, (F, R), SINGLE), \
11745 X(2, (R, F), SINGLE)
11747 #define S2(A,B) NS_##A##B
11748 #define S3(A,B,C) NS_##A##B##C
11749 #define S4(A,B,C,D) NS_##A##B##C##D
11751 #define X(N, L, C) S##N L
11764 enum neon_shape_class
11772 #define X(N, L, C) SC_##C
11774 static enum neon_shape_class neon_shape_class
[] =
11792 /* Register widths of above. */
11793 static unsigned neon_shape_el_size
[] =
11804 struct neon_shape_info
11807 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11810 #define S2(A,B) { SE_##A, SE_##B }
11811 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11812 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11814 #define X(N, L, C) { N, S##N L }
11816 static struct neon_shape_info neon_shape_tab
[] =
11826 /* Bit masks used in type checking given instructions.
11827 'N_EQK' means the type must be the same as (or based on in some way) the key
11828 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11829 set, various other bits can be set as well in order to modify the meaning of
11830 the type constraint. */
11832 enum neon_type_mask
11855 N_KEY
= 0x1000000, /* Key element (main type specifier). */
11856 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
11857 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11858 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
11859 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
11860 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
11861 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
11862 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
11863 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
11864 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
11866 N_MAX_NONSPECIAL
= N_F64
11869 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11871 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11872 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11873 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11874 #define N_SUF_32 (N_SU_32 | N_F32)
11875 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11876 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11878 /* Pass this as the first type argument to neon_check_type to ignore types
11880 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11882 /* Select a "shape" for the current instruction (describing register types or
11883 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11884 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11885 function of operand parsing, so this function doesn't need to be called.
11886 Shapes should be listed in order of decreasing length. */
11888 static enum neon_shape
11889 neon_select_shape (enum neon_shape shape
, ...)
11892 enum neon_shape first_shape
= shape
;
11894 /* Fix missing optional operands. FIXME: we don't know at this point how
11895 many arguments we should have, so this makes the assumption that we have
11896 > 1. This is true of all current Neon opcodes, I think, but may not be
11897 true in the future. */
11898 if (!inst
.operands
[1].present
)
11899 inst
.operands
[1] = inst
.operands
[0];
11901 va_start (ap
, shape
);
11903 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
11908 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
11910 if (!inst
.operands
[j
].present
)
11916 switch (neon_shape_tab
[shape
].el
[j
])
11919 if (!(inst
.operands
[j
].isreg
11920 && inst
.operands
[j
].isvec
11921 && inst
.operands
[j
].issingle
11922 && !inst
.operands
[j
].isquad
))
11927 if (!(inst
.operands
[j
].isreg
11928 && inst
.operands
[j
].isvec
11929 && !inst
.operands
[j
].isquad
11930 && !inst
.operands
[j
].issingle
))
11935 if (!(inst
.operands
[j
].isreg
11936 && !inst
.operands
[j
].isvec
))
11941 if (!(inst
.operands
[j
].isreg
11942 && inst
.operands
[j
].isvec
11943 && inst
.operands
[j
].isquad
11944 && !inst
.operands
[j
].issingle
))
11949 if (!(!inst
.operands
[j
].isreg
11950 && !inst
.operands
[j
].isscalar
))
11955 if (!(!inst
.operands
[j
].isreg
11956 && inst
.operands
[j
].isscalar
))
11972 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
11973 first_error (_("invalid instruction shape"));
11978 /* True if SHAPE is predominantly a quadword operation (most of the time, this
11979 means the Q bit should be set). */
11982 neon_quad (enum neon_shape shape
)
11984 return neon_shape_class
[shape
] == SC_QUAD
;
11988 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
11991 /* Allow modification to be made to types which are constrained to be
11992 based on the key element, based on bits set alongside N_EQK. */
11993 if ((typebits
& N_EQK
) != 0)
11995 if ((typebits
& N_HLF
) != 0)
11997 else if ((typebits
& N_DBL
) != 0)
11999 if ((typebits
& N_SGN
) != 0)
12000 *g_type
= NT_signed
;
12001 else if ((typebits
& N_UNS
) != 0)
12002 *g_type
= NT_unsigned
;
12003 else if ((typebits
& N_INT
) != 0)
12004 *g_type
= NT_integer
;
12005 else if ((typebits
& N_FLT
) != 0)
12006 *g_type
= NT_float
;
12007 else if ((typebits
& N_SIZ
) != 0)
12008 *g_type
= NT_untyped
;
12012 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12013 operand type, i.e. the single type specified in a Neon instruction when it
12014 is the only one given. */
12016 static struct neon_type_el
12017 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
12019 struct neon_type_el dest
= *key
;
12021 gas_assert ((thisarg
& N_EQK
) != 0);
12023 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
12028 /* Convert Neon type and size into compact bitmask representation. */
12030 static enum neon_type_mask
12031 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
12038 case 8: return N_8
;
12039 case 16: return N_16
;
12040 case 32: return N_32
;
12041 case 64: return N_64
;
12049 case 8: return N_I8
;
12050 case 16: return N_I16
;
12051 case 32: return N_I32
;
12052 case 64: return N_I64
;
12060 case 16: return N_F16
;
12061 case 32: return N_F32
;
12062 case 64: return N_F64
;
12070 case 8: return N_P8
;
12071 case 16: return N_P16
;
12079 case 8: return N_S8
;
12080 case 16: return N_S16
;
12081 case 32: return N_S32
;
12082 case 64: return N_S64
;
12090 case 8: return N_U8
;
12091 case 16: return N_U16
;
12092 case 32: return N_U32
;
12093 case 64: return N_U64
;
12104 /* Convert compact Neon bitmask type representation to a type and size. Only
12105 handles the case where a single bit is set in the mask. */
12108 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12109 enum neon_type_mask mask
)
12111 if ((mask
& N_EQK
) != 0)
12114 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12116 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
12118 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12120 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
12125 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
12127 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
12128 *type
= NT_unsigned
;
12129 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
12130 *type
= NT_integer
;
12131 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
12132 *type
= NT_untyped
;
12133 else if ((mask
& (N_P8
| N_P16
)) != 0)
12135 else if ((mask
& (N_F32
| N_F64
)) != 0)
12143 /* Modify a bitmask of allowed types. This is only needed for type
12147 modify_types_allowed (unsigned allowed
, unsigned mods
)
12150 enum neon_el_type type
;
12156 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
12158 if (el_type_of_type_chk (&type
, &size
,
12159 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
12161 neon_modify_type_size (mods
, &type
, &size
);
12162 destmask
|= type_chk_of_el_type (type
, size
);
12169 /* Check type and return type classification.
12170 The manual states (paraphrase): If one datatype is given, it indicates the
12172 - the second operand, if there is one
12173 - the operand, if there is no second operand
12174 - the result, if there are no operands.
12175 This isn't quite good enough though, so we use a concept of a "key" datatype
12176 which is set on a per-instruction basis, which is the one which matters when
12177 only one data type is written.
12178 Note: this function has side-effects (e.g. filling in missing operands). All
12179 Neon instructions should call it before performing bit encoding. */
12181 static struct neon_type_el
12182 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12185 unsigned i
, pass
, key_el
= 0;
12186 unsigned types
[NEON_MAX_TYPE_ELS
];
12187 enum neon_el_type k_type
= NT_invtype
;
12188 unsigned k_size
= -1u;
12189 struct neon_type_el badtype
= {NT_invtype
, -1};
12190 unsigned key_allowed
= 0;
12192 /* Optional registers in Neon instructions are always (not) in operand 1.
12193 Fill in the missing operand here, if it was omitted. */
12194 if (els
> 1 && !inst
.operands
[1].present
)
12195 inst
.operands
[1] = inst
.operands
[0];
12197 /* Suck up all the varargs. */
12199 for (i
= 0; i
< els
; i
++)
12201 unsigned thisarg
= va_arg (ap
, unsigned);
12202 if (thisarg
== N_IGNORE_TYPE
)
12207 types
[i
] = thisarg
;
12208 if ((thisarg
& N_KEY
) != 0)
12213 if (inst
.vectype
.elems
> 0)
12214 for (i
= 0; i
< els
; i
++)
12215 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12217 first_error (_("types specified in both the mnemonic and operands"));
12221 /* Duplicate inst.vectype elements here as necessary.
12222 FIXME: No idea if this is exactly the same as the ARM assembler,
12223 particularly when an insn takes one register and one non-register
12225 if (inst
.vectype
.elems
== 1 && els
> 1)
12228 inst
.vectype
.elems
= els
;
12229 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12230 for (j
= 0; j
< els
; j
++)
12232 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12235 else if (inst
.vectype
.elems
== 0 && els
> 0)
12238 /* No types were given after the mnemonic, so look for types specified
12239 after each operand. We allow some flexibility here; as long as the
12240 "key" operand has a type, we can infer the others. */
12241 for (j
= 0; j
< els
; j
++)
12242 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12243 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12245 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12247 for (j
= 0; j
< els
; j
++)
12248 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12249 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12254 first_error (_("operand types can't be inferred"));
12258 else if (inst
.vectype
.elems
!= els
)
12260 first_error (_("type specifier has the wrong number of parts"));
12264 for (pass
= 0; pass
< 2; pass
++)
12266 for (i
= 0; i
< els
; i
++)
12268 unsigned thisarg
= types
[i
];
12269 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12270 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12271 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12272 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12274 /* Decay more-specific signed & unsigned types to sign-insensitive
12275 integer types if sign-specific variants are unavailable. */
12276 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12277 && (types_allowed
& N_SU_ALL
) == 0)
12278 g_type
= NT_integer
;
12280 /* If only untyped args are allowed, decay any more specific types to
12281 them. Some instructions only care about signs for some element
12282 sizes, so handle that properly. */
12283 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12284 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12285 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12286 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12287 g_type
= NT_untyped
;
12291 if ((thisarg
& N_KEY
) != 0)
12295 key_allowed
= thisarg
& ~N_KEY
;
12300 if ((thisarg
& N_VFP
) != 0)
12302 enum neon_shape_el regshape
;
12303 unsigned regwidth
, match
;
12305 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12308 first_error (_("invalid instruction shape"));
12311 regshape
= neon_shape_tab
[ns
].el
[i
];
12312 regwidth
= neon_shape_el_size
[regshape
];
12314 /* In VFP mode, operands must match register widths. If we
12315 have a key operand, use its width, else use the width of
12316 the current operand. */
12322 if (regwidth
!= match
)
12324 first_error (_("operand size must match register width"));
12329 if ((thisarg
& N_EQK
) == 0)
12331 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12333 if ((given_type
& types_allowed
) == 0)
12335 first_error (_("bad type in Neon instruction"));
12341 enum neon_el_type mod_k_type
= k_type
;
12342 unsigned mod_k_size
= k_size
;
12343 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12344 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12346 first_error (_("inconsistent types in Neon instruction"));
12354 return inst
.vectype
.el
[key_el
];
12357 /* Neon-style VFP instruction forwarding. */
12359 /* Thumb VFP instructions have 0xE in the condition field. */
12362 do_vfp_cond_or_thumb (void)
12367 inst
.instruction
|= 0xe0000000;
12369 inst
.instruction
|= inst
.cond
<< 28;
12372 /* Look up and encode a simple mnemonic, for use as a helper function for the
12373 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12374 etc. It is assumed that operand parsing has already been done, and that the
12375 operands are in the form expected by the given opcode (this isn't necessarily
12376 the same as the form in which they were parsed, hence some massaging must
12377 take place before this function is called).
12378 Checks current arch version against that in the looked-up opcode. */
12381 do_vfp_nsyn_opcode (const char *opname
)
12383 const struct asm_opcode
*opcode
;
12385 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12390 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12391 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12398 inst
.instruction
= opcode
->tvalue
;
12399 opcode
->tencode ();
12403 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12404 opcode
->aencode ();
12409 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12411 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12416 do_vfp_nsyn_opcode ("fadds");
12418 do_vfp_nsyn_opcode ("fsubs");
12423 do_vfp_nsyn_opcode ("faddd");
12425 do_vfp_nsyn_opcode ("fsubd");
12429 /* Check operand types to see if this is a VFP instruction, and if so call
12433 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12435 enum neon_shape rs
;
12436 struct neon_type_el et
;
12441 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12442 et
= neon_check_type (2, rs
,
12443 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12447 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12448 et
= neon_check_type (3, rs
,
12449 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12456 if (et
.type
!= NT_invtype
)
12467 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12469 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12474 do_vfp_nsyn_opcode ("fmacs");
12476 do_vfp_nsyn_opcode ("fnmacs");
12481 do_vfp_nsyn_opcode ("fmacd");
12483 do_vfp_nsyn_opcode ("fnmacd");
12488 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12490 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12495 do_vfp_nsyn_opcode ("ffmas");
12497 do_vfp_nsyn_opcode ("ffnmas");
12502 do_vfp_nsyn_opcode ("ffmad");
12504 do_vfp_nsyn_opcode ("ffnmad");
12509 do_vfp_nsyn_mul (enum neon_shape rs
)
12512 do_vfp_nsyn_opcode ("fmuls");
12514 do_vfp_nsyn_opcode ("fmuld");
12518 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12520 int is_neg
= (inst
.instruction
& 0x80) != 0;
12521 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12526 do_vfp_nsyn_opcode ("fnegs");
12528 do_vfp_nsyn_opcode ("fabss");
12533 do_vfp_nsyn_opcode ("fnegd");
12535 do_vfp_nsyn_opcode ("fabsd");
12539 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12540 insns belong to Neon, and are handled elsewhere. */
12543 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12545 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12549 do_vfp_nsyn_opcode ("fldmdbs");
12551 do_vfp_nsyn_opcode ("fldmias");
12556 do_vfp_nsyn_opcode ("fstmdbs");
12558 do_vfp_nsyn_opcode ("fstmias");
12563 do_vfp_nsyn_sqrt (void)
12565 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12566 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12569 do_vfp_nsyn_opcode ("fsqrts");
12571 do_vfp_nsyn_opcode ("fsqrtd");
12575 do_vfp_nsyn_div (void)
12577 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12578 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12579 N_F32
| N_F64
| N_KEY
| N_VFP
);
12582 do_vfp_nsyn_opcode ("fdivs");
12584 do_vfp_nsyn_opcode ("fdivd");
12588 do_vfp_nsyn_nmul (void)
12590 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12591 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12592 N_F32
| N_F64
| N_KEY
| N_VFP
);
12596 NEON_ENCODE (SINGLE
, inst
);
12597 do_vfp_sp_dyadic ();
12601 NEON_ENCODE (DOUBLE
, inst
);
12602 do_vfp_dp_rd_rn_rm ();
12604 do_vfp_cond_or_thumb ();
12608 do_vfp_nsyn_cmp (void)
12610 if (inst
.operands
[1].isreg
)
12612 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12613 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12617 NEON_ENCODE (SINGLE
, inst
);
12618 do_vfp_sp_monadic ();
12622 NEON_ENCODE (DOUBLE
, inst
);
12623 do_vfp_dp_rd_rm ();
12628 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12629 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12631 switch (inst
.instruction
& 0x0fffffff)
12634 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12637 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12645 NEON_ENCODE (SINGLE
, inst
);
12646 do_vfp_sp_compare_z ();
12650 NEON_ENCODE (DOUBLE
, inst
);
12654 do_vfp_cond_or_thumb ();
12658 nsyn_insert_sp (void)
12660 inst
.operands
[1] = inst
.operands
[0];
12661 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12662 inst
.operands
[0].reg
= REG_SP
;
12663 inst
.operands
[0].isreg
= 1;
12664 inst
.operands
[0].writeback
= 1;
12665 inst
.operands
[0].present
= 1;
12669 do_vfp_nsyn_push (void)
12672 if (inst
.operands
[1].issingle
)
12673 do_vfp_nsyn_opcode ("fstmdbs");
12675 do_vfp_nsyn_opcode ("fstmdbd");
12679 do_vfp_nsyn_pop (void)
12682 if (inst
.operands
[1].issingle
)
12683 do_vfp_nsyn_opcode ("fldmias");
12685 do_vfp_nsyn_opcode ("fldmiad");
12688 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12689 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12692 neon_dp_fixup (struct arm_it
* insn
)
12694 unsigned int i
= insn
->instruction
;
12699 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12710 insn
->instruction
= i
;
12713 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12717 neon_logbits (unsigned x
)
12719 return ffs (x
) - 4;
12722 #define LOW4(R) ((R) & 0xf)
12723 #define HI1(R) (((R) >> 4) & 1)
12725 /* Encode insns with bit pattern:
12727 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12728 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
12730 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12731 different meaning for some instruction. */
12734 neon_three_same (int isquad
, int ubit
, int size
)
12736 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12737 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12738 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12739 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12740 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12741 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12742 inst
.instruction
|= (isquad
!= 0) << 6;
12743 inst
.instruction
|= (ubit
!= 0) << 24;
12745 inst
.instruction
|= neon_logbits (size
) << 20;
12747 neon_dp_fixup (&inst
);
12750 /* Encode instructions of the form:
12752 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
12753 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
12755 Don't write size if SIZE == -1. */
12758 neon_two_same (int qbit
, int ubit
, int size
)
12760 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12761 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12762 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12763 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12764 inst
.instruction
|= (qbit
!= 0) << 6;
12765 inst
.instruction
|= (ubit
!= 0) << 24;
12768 inst
.instruction
|= neon_logbits (size
) << 18;
12770 neon_dp_fixup (&inst
);
12773 /* Neon instruction encoders, in approximate order of appearance. */
12776 do_neon_dyadic_i_su (void)
12778 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12779 struct neon_type_el et
= neon_check_type (3, rs
,
12780 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12781 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12785 do_neon_dyadic_i64_su (void)
12787 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12788 struct neon_type_el et
= neon_check_type (3, rs
,
12789 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12790 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12794 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12797 unsigned size
= et
.size
>> 3;
12798 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12799 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12800 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12801 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12802 inst
.instruction
|= (isquad
!= 0) << 6;
12803 inst
.instruction
|= immbits
<< 16;
12804 inst
.instruction
|= (size
>> 3) << 7;
12805 inst
.instruction
|= (size
& 0x7) << 19;
12807 inst
.instruction
|= (uval
!= 0) << 24;
12809 neon_dp_fixup (&inst
);
12813 do_neon_shl_imm (void)
12815 if (!inst
.operands
[2].isreg
)
12817 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12818 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12819 NEON_ENCODE (IMMED
, inst
);
12820 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12824 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12825 struct neon_type_el et
= neon_check_type (3, rs
,
12826 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12829 /* VSHL/VQSHL 3-register variants have syntax such as:
12831 whereas other 3-register operations encoded by neon_three_same have
12834 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12836 tmp
= inst
.operands
[2].reg
;
12837 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12838 inst
.operands
[1].reg
= tmp
;
12839 NEON_ENCODE (INTEGER
, inst
);
12840 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12845 do_neon_qshl_imm (void)
12847 if (!inst
.operands
[2].isreg
)
12849 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12850 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12852 NEON_ENCODE (IMMED
, inst
);
12853 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12854 inst
.operands
[2].imm
);
12858 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12859 struct neon_type_el et
= neon_check_type (3, rs
,
12860 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12863 /* See note in do_neon_shl_imm. */
12864 tmp
= inst
.operands
[2].reg
;
12865 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12866 inst
.operands
[1].reg
= tmp
;
12867 NEON_ENCODE (INTEGER
, inst
);
12868 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12873 do_neon_rshl (void)
12875 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12876 struct neon_type_el et
= neon_check_type (3, rs
,
12877 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12880 tmp
= inst
.operands
[2].reg
;
12881 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12882 inst
.operands
[1].reg
= tmp
;
12883 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12887 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12889 /* Handle .I8 pseudo-instructions. */
12892 /* Unfortunately, this will make everything apart from zero out-of-range.
12893 FIXME is this the intended semantics? There doesn't seem much point in
12894 accepting .I8 if so. */
12895 immediate
|= immediate
<< 8;
12901 if (immediate
== (immediate
& 0x000000ff))
12903 *immbits
= immediate
;
12906 else if (immediate
== (immediate
& 0x0000ff00))
12908 *immbits
= immediate
>> 8;
12911 else if (immediate
== (immediate
& 0x00ff0000))
12913 *immbits
= immediate
>> 16;
12916 else if (immediate
== (immediate
& 0xff000000))
12918 *immbits
= immediate
>> 24;
12921 if ((immediate
& 0xffff) != (immediate
>> 16))
12922 goto bad_immediate
;
12923 immediate
&= 0xffff;
12926 if (immediate
== (immediate
& 0x000000ff))
12928 *immbits
= immediate
;
12931 else if (immediate
== (immediate
& 0x0000ff00))
12933 *immbits
= immediate
>> 8;
12938 first_error (_("immediate value out of range"));
12942 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12946 neon_bits_same_in_bytes (unsigned imm
)
12948 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
12949 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
12950 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
12951 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
12954 /* For immediate of above form, return 0bABCD. */
12957 neon_squash_bits (unsigned imm
)
12959 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
12960 | ((imm
& 0x01000000) >> 21);
12963 /* Compress quarter-float representation to 0b...000 abcdefgh. */
12966 neon_qfloat_bits (unsigned imm
)
12968 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
12971 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12972 the instruction. *OP is passed as the initial value of the op field, and
12973 may be set to a different value depending on the constant (i.e.
12974 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
12975 MVN). If the immediate looks like a repeated pattern then also
12976 try smaller element sizes. */
12979 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
12980 unsigned *immbits
, int *op
, int size
,
12981 enum neon_el_type type
)
12983 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
12985 if (type
== NT_float
&& !float_p
)
12988 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
12990 if (size
!= 32 || *op
== 1)
12992 *immbits
= neon_qfloat_bits (immlo
);
12998 if (neon_bits_same_in_bytes (immhi
)
12999 && neon_bits_same_in_bytes (immlo
))
13003 *immbits
= (neon_squash_bits (immhi
) << 4)
13004 | neon_squash_bits (immlo
);
13009 if (immhi
!= immlo
)
13015 if (immlo
== (immlo
& 0x000000ff))
13020 else if (immlo
== (immlo
& 0x0000ff00))
13022 *immbits
= immlo
>> 8;
13025 else if (immlo
== (immlo
& 0x00ff0000))
13027 *immbits
= immlo
>> 16;
13030 else if (immlo
== (immlo
& 0xff000000))
13032 *immbits
= immlo
>> 24;
13035 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
13037 *immbits
= (immlo
>> 8) & 0xff;
13040 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
13042 *immbits
= (immlo
>> 16) & 0xff;
13046 if ((immlo
& 0xffff) != (immlo
>> 16))
13053 if (immlo
== (immlo
& 0x000000ff))
13058 else if (immlo
== (immlo
& 0x0000ff00))
13060 *immbits
= immlo
>> 8;
13064 if ((immlo
& 0xff) != (immlo
>> 8))
13069 if (immlo
== (immlo
& 0x000000ff))
13071 /* Don't allow MVN with 8-bit immediate. */
13081 /* Write immediate bits [7:0] to the following locations:
13083 |28/24|23 19|18 16|15 4|3 0|
13084 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13086 This function is used by VMOV/VMVN/VORR/VBIC. */
13089 neon_write_immbits (unsigned immbits
)
13091 inst
.instruction
|= immbits
& 0xf;
13092 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
13093 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
13096 /* Invert low-order SIZE bits of XHI:XLO. */
13099 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
13101 unsigned immlo
= xlo
? *xlo
: 0;
13102 unsigned immhi
= xhi
? *xhi
: 0;
13107 immlo
= (~immlo
) & 0xff;
13111 immlo
= (~immlo
) & 0xffff;
13115 immhi
= (~immhi
) & 0xffffffff;
13116 /* fall through. */
13119 immlo
= (~immlo
) & 0xffffffff;
13134 do_neon_logic (void)
13136 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
13138 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13139 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13140 /* U bit and size field were set as part of the bitmask. */
13141 NEON_ENCODE (INTEGER
, inst
);
13142 neon_three_same (neon_quad (rs
), 0, -1);
13146 const int three_ops_form
= (inst
.operands
[2].present
13147 && !inst
.operands
[2].isreg
);
13148 const int immoperand
= (three_ops_form
? 2 : 1);
13149 enum neon_shape rs
= (three_ops_form
13150 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
13151 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
13152 struct neon_type_el et
= neon_check_type (2, rs
,
13153 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13154 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
13158 if (et
.type
== NT_invtype
)
13161 if (three_ops_form
)
13162 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13163 _("first and second operands shall be the same register"));
13165 NEON_ENCODE (IMMED
, inst
);
13167 immbits
= inst
.operands
[immoperand
].imm
;
13170 /* .i64 is a pseudo-op, so the immediate must be a repeating
13172 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
13173 inst
.operands
[immoperand
].reg
: 0))
13175 /* Set immbits to an invalid constant. */
13176 immbits
= 0xdeadbeef;
13183 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13187 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13191 /* Pseudo-instruction for VBIC. */
13192 neon_invert_size (&immbits
, 0, et
.size
);
13193 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13197 /* Pseudo-instruction for VORR. */
13198 neon_invert_size (&immbits
, 0, et
.size
);
13199 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13209 inst
.instruction
|= neon_quad (rs
) << 6;
13210 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13211 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13212 inst
.instruction
|= cmode
<< 8;
13213 neon_write_immbits (immbits
);
13215 neon_dp_fixup (&inst
);
13220 do_neon_bitfield (void)
13222 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13223 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13224 neon_three_same (neon_quad (rs
), 0, -1);
13228 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13231 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13232 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13234 if (et
.type
== NT_float
)
13236 NEON_ENCODE (FLOAT
, inst
);
13237 neon_three_same (neon_quad (rs
), 0, -1);
13241 NEON_ENCODE (INTEGER
, inst
);
13242 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13247 do_neon_dyadic_if_su (void)
13249 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13253 do_neon_dyadic_if_su_d (void)
13255 /* This version only allow D registers, but that constraint is enforced during
13256 operand parsing so we don't need to do anything extra here. */
13257 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13261 do_neon_dyadic_if_i_d (void)
13263 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13264 affected if we specify unsigned args. */
13265 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13268 enum vfp_or_neon_is_neon_bits
13271 NEON_CHECK_ARCH
= 2
13274 /* Call this function if an instruction which may have belonged to the VFP or
13275 Neon instruction sets, but turned out to be a Neon instruction (due to the
13276 operand types involved, etc.). We have to check and/or fix-up a couple of
13279 - Make sure the user hasn't attempted to make a Neon instruction
13281 - Alter the value in the condition code field if necessary.
13282 - Make sure that the arch supports Neon instructions.
13284 Which of these operations take place depends on bits from enum
13285 vfp_or_neon_is_neon_bits.
13287 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13288 current instruction's condition is COND_ALWAYS, the condition field is
13289 changed to inst.uncond_value. This is necessary because instructions shared
13290 between VFP and Neon may be conditional for the VFP variants only, and the
13291 unconditional Neon version must have, e.g., 0xF in the condition field. */
13294 vfp_or_neon_is_neon (unsigned check
)
13296 /* Conditions are always legal in Thumb mode (IT blocks). */
13297 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13299 if (inst
.cond
!= COND_ALWAYS
)
13301 first_error (_(BAD_COND
));
13304 if (inst
.uncond_value
!= -1)
13305 inst
.instruction
|= inst
.uncond_value
<< 28;
13308 if ((check
& NEON_CHECK_ARCH
)
13309 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13311 first_error (_(BAD_FPU
));
13319 do_neon_addsub_if_i (void)
13321 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13324 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13327 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13328 affected if we specify unsigned args. */
13329 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13332 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13334 V<op> A,B (A is operand 0, B is operand 2)
13339 so handle that case specially. */
13342 neon_exchange_operands (void)
13344 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13345 if (inst
.operands
[1].present
)
13347 /* Swap operands[1] and operands[2]. */
13348 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13349 inst
.operands
[1] = inst
.operands
[2];
13350 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13354 inst
.operands
[1] = inst
.operands
[2];
13355 inst
.operands
[2] = inst
.operands
[0];
13360 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13362 if (inst
.operands
[2].isreg
)
13365 neon_exchange_operands ();
13366 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13370 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13371 struct neon_type_el et
= neon_check_type (2, rs
,
13372 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13374 NEON_ENCODE (IMMED
, inst
);
13375 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13376 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13377 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13378 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13379 inst
.instruction
|= neon_quad (rs
) << 6;
13380 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13381 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13383 neon_dp_fixup (&inst
);
13390 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13394 do_neon_cmp_inv (void)
13396 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13402 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13405 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13406 scalars, which are encoded in 5 bits, M : Rm.
13407 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13408 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13412 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13414 unsigned regno
= NEON_SCALAR_REG (scalar
);
13415 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13420 if (regno
> 7 || elno
> 3)
13422 return regno
| (elno
<< 3);
13425 if (regno
> 15 || elno
> 1)
13427 return regno
| (elno
<< 4);
13431 first_error (_("scalar out of range for multiply instruction"));
13437 /* Encode multiply / multiply-accumulate scalar instructions. */
13440 neon_mul_mac (struct neon_type_el et
, int ubit
)
13444 /* Give a more helpful error message if we have an invalid type. */
13445 if (et
.type
== NT_invtype
)
13448 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13449 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13450 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13451 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13452 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13453 inst
.instruction
|= LOW4 (scalar
);
13454 inst
.instruction
|= HI1 (scalar
) << 5;
13455 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13456 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13457 inst
.instruction
|= (ubit
!= 0) << 24;
13459 neon_dp_fixup (&inst
);
13463 do_neon_mac_maybe_scalar (void)
13465 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13468 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13471 if (inst
.operands
[2].isscalar
)
13473 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13474 struct neon_type_el et
= neon_check_type (3, rs
,
13475 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13476 NEON_ENCODE (SCALAR
, inst
);
13477 neon_mul_mac (et
, neon_quad (rs
));
13481 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13482 affected if we specify unsigned args. */
13483 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13488 do_neon_fmac (void)
13490 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13493 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13496 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13502 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13503 struct neon_type_el et
= neon_check_type (3, rs
,
13504 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13505 neon_three_same (neon_quad (rs
), 0, et
.size
);
13508 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13509 same types as the MAC equivalents. The polynomial type for this instruction
13510 is encoded the same as the integer type. */
13515 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13518 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13521 if (inst
.operands
[2].isscalar
)
13522 do_neon_mac_maybe_scalar ();
13524 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13528 do_neon_qdmulh (void)
13530 if (inst
.operands
[2].isscalar
)
13532 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13533 struct neon_type_el et
= neon_check_type (3, rs
,
13534 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13535 NEON_ENCODE (SCALAR
, inst
);
13536 neon_mul_mac (et
, neon_quad (rs
));
13540 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13541 struct neon_type_el et
= neon_check_type (3, rs
,
13542 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13543 NEON_ENCODE (INTEGER
, inst
);
13544 /* The U bit (rounding) comes from bit mask. */
13545 neon_three_same (neon_quad (rs
), 0, et
.size
);
13550 do_neon_fcmp_absolute (void)
13552 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13553 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13554 /* Size field comes from bit mask. */
13555 neon_three_same (neon_quad (rs
), 1, -1);
13559 do_neon_fcmp_absolute_inv (void)
13561 neon_exchange_operands ();
13562 do_neon_fcmp_absolute ();
13566 do_neon_step (void)
13568 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13569 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13570 neon_three_same (neon_quad (rs
), 0, -1);
13574 do_neon_abs_neg (void)
13576 enum neon_shape rs
;
13577 struct neon_type_el et
;
13579 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13582 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13585 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13586 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13588 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13589 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13590 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13591 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13592 inst
.instruction
|= neon_quad (rs
) << 6;
13593 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13594 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13596 neon_dp_fixup (&inst
);
13602 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13603 struct neon_type_el et
= neon_check_type (2, rs
,
13604 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13605 int imm
= inst
.operands
[2].imm
;
13606 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13607 _("immediate out of range for insert"));
13608 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13614 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13615 struct neon_type_el et
= neon_check_type (2, rs
,
13616 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13617 int imm
= inst
.operands
[2].imm
;
13618 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13619 _("immediate out of range for insert"));
13620 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13624 do_neon_qshlu_imm (void)
13626 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13627 struct neon_type_el et
= neon_check_type (2, rs
,
13628 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13629 int imm
= inst
.operands
[2].imm
;
13630 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13631 _("immediate out of range for shift"));
13632 /* Only encodes the 'U present' variant of the instruction.
13633 In this case, signed types have OP (bit 8) set to 0.
13634 Unsigned types have OP set to 1. */
13635 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13636 /* The rest of the bits are the same as other immediate shifts. */
13637 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13641 do_neon_qmovn (void)
13643 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13644 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13645 /* Saturating move where operands can be signed or unsigned, and the
13646 destination has the same signedness. */
13647 NEON_ENCODE (INTEGER
, inst
);
13648 if (et
.type
== NT_unsigned
)
13649 inst
.instruction
|= 0xc0;
13651 inst
.instruction
|= 0x80;
13652 neon_two_same (0, 1, et
.size
/ 2);
13656 do_neon_qmovun (void)
13658 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13659 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13660 /* Saturating move with unsigned results. Operands must be signed. */
13661 NEON_ENCODE (INTEGER
, inst
);
13662 neon_two_same (0, 1, et
.size
/ 2);
13666 do_neon_rshift_sat_narrow (void)
13668 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13669 or unsigned. If operands are unsigned, results must also be unsigned. */
13670 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13671 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13672 int imm
= inst
.operands
[2].imm
;
13673 /* This gets the bounds check, size encoding and immediate bits calculation
13677 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13678 VQMOVN.I<size> <Dd>, <Qm>. */
13681 inst
.operands
[2].present
= 0;
13682 inst
.instruction
= N_MNEM_vqmovn
;
13687 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13688 _("immediate out of range"));
13689 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13693 do_neon_rshift_sat_narrow_u (void)
13695 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13696 or unsigned. If operands are unsigned, results must also be unsigned. */
13697 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13698 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13699 int imm
= inst
.operands
[2].imm
;
13700 /* This gets the bounds check, size encoding and immediate bits calculation
13704 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13705 VQMOVUN.I<size> <Dd>, <Qm>. */
13708 inst
.operands
[2].present
= 0;
13709 inst
.instruction
= N_MNEM_vqmovun
;
13714 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13715 _("immediate out of range"));
13716 /* FIXME: The manual is kind of unclear about what value U should have in
13717 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13719 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
13723 do_neon_movn (void)
13725 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13726 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13727 NEON_ENCODE (INTEGER
, inst
);
13728 neon_two_same (0, 1, et
.size
/ 2);
13732 do_neon_rshift_narrow (void)
13734 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13735 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13736 int imm
= inst
.operands
[2].imm
;
13737 /* This gets the bounds check, size encoding and immediate bits calculation
13741 /* If immediate is zero then we are a pseudo-instruction for
13742 VMOVN.I<size> <Dd>, <Qm> */
13745 inst
.operands
[2].present
= 0;
13746 inst
.instruction
= N_MNEM_vmovn
;
13751 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13752 _("immediate out of range for narrowing operation"));
13753 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
13757 do_neon_shll (void)
13759 /* FIXME: Type checking when lengthening. */
13760 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
13761 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
13762 unsigned imm
= inst
.operands
[2].imm
;
13764 if (imm
== et
.size
)
13766 /* Maximum shift variant. */
13767 NEON_ENCODE (INTEGER
, inst
);
13768 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13769 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13770 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13771 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13772 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13774 neon_dp_fixup (&inst
);
13778 /* A more-specific type check for non-max versions. */
13779 et
= neon_check_type (2, NS_QDI
,
13780 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13781 NEON_ENCODE (IMMED
, inst
);
13782 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13786 /* Check the various types for the VCVT instruction, and return which version
13787 the current instruction is. */
13790 neon_cvt_flavour (enum neon_shape rs
)
13792 #define CVT_VAR(C,X,Y) \
13793 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13794 if (et.type != NT_invtype) \
13796 inst.error = NULL; \
13799 struct neon_type_el et
;
13800 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13801 || rs
== NS_FF
) ? N_VFP
: 0;
13802 /* The instruction versions which take an immediate take one register
13803 argument, which is extended to the width of the full register. Thus the
13804 "source" and "destination" registers must have the same width. Hack that
13805 here by making the size equal to the key (wider, in this case) operand. */
13806 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13808 CVT_VAR (0, N_S32
, N_F32
);
13809 CVT_VAR (1, N_U32
, N_F32
);
13810 CVT_VAR (2, N_F32
, N_S32
);
13811 CVT_VAR (3, N_F32
, N_U32
);
13812 /* Half-precision conversions. */
13813 CVT_VAR (4, N_F32
, N_F16
);
13814 CVT_VAR (5, N_F16
, N_F32
);
13818 /* VFP instructions. */
13819 CVT_VAR (6, N_F32
, N_F64
);
13820 CVT_VAR (7, N_F64
, N_F32
);
13821 CVT_VAR (8, N_S32
, N_F64
| key
);
13822 CVT_VAR (9, N_U32
, N_F64
| key
);
13823 CVT_VAR (10, N_F64
| key
, N_S32
);
13824 CVT_VAR (11, N_F64
| key
, N_U32
);
13825 /* VFP instructions with bitshift. */
13826 CVT_VAR (12, N_F32
| key
, N_S16
);
13827 CVT_VAR (13, N_F32
| key
, N_U16
);
13828 CVT_VAR (14, N_F64
| key
, N_S16
);
13829 CVT_VAR (15, N_F64
| key
, N_U16
);
13830 CVT_VAR (16, N_S16
, N_F32
| key
);
13831 CVT_VAR (17, N_U16
, N_F32
| key
);
13832 CVT_VAR (18, N_S16
, N_F64
| key
);
13833 CVT_VAR (19, N_U16
, N_F64
| key
);
13839 /* Neon-syntax VFP conversions. */
13842 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13844 const char *opname
= 0;
13846 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13848 /* Conversions with immediate bitshift. */
13849 const char *enc
[] =
13873 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13875 opname
= enc
[flavour
];
13876 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13877 _("operands 0 and 1 must be the same register"));
13878 inst
.operands
[1] = inst
.operands
[2];
13879 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13884 /* Conversions without bitshift. */
13885 const char *enc
[] =
13901 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13902 opname
= enc
[flavour
];
13906 do_vfp_nsyn_opcode (opname
);
13910 do_vfp_nsyn_cvtz (void)
13912 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
13913 int flavour
= neon_cvt_flavour (rs
);
13914 const char *enc
[] =
13928 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
13929 do_vfp_nsyn_opcode (enc
[flavour
]);
13933 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
13935 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
13936 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
13937 int flavour
= neon_cvt_flavour (rs
);
13939 /* PR11109: Handle round-to-zero for VCVT conversions. */
13941 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
13942 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
13943 && (rs
== NS_FD
|| rs
== NS_FF
))
13945 do_vfp_nsyn_cvtz ();
13949 /* VFP rather than Neon conversions. */
13952 do_vfp_nsyn_cvt (rs
, flavour
);
13962 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13964 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13967 /* Fixed-point conversion with #0 immediate is encoded as an
13968 integer conversion. */
13969 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
13971 immbits
= 32 - inst
.operands
[2].imm
;
13972 NEON_ENCODE (IMMED
, inst
);
13974 inst
.instruction
|= enctab
[flavour
];
13975 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13976 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13977 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13978 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13979 inst
.instruction
|= neon_quad (rs
) << 6;
13980 inst
.instruction
|= 1 << 21;
13981 inst
.instruction
|= immbits
<< 16;
13983 neon_dp_fixup (&inst
);
13991 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
13993 NEON_ENCODE (INTEGER
, inst
);
13995 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13999 inst
.instruction
|= enctab
[flavour
];
14001 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14002 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14003 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14004 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14005 inst
.instruction
|= neon_quad (rs
) << 6;
14006 inst
.instruction
|= 2 << 18;
14008 neon_dp_fixup (&inst
);
14012 /* Half-precision conversions for Advanced SIMD -- neon. */
14017 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
14019 as_bad (_("operand size must match register width"));
14024 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
14026 as_bad (_("operand size must match register width"));
14031 inst
.instruction
= 0x3b60600;
14033 inst
.instruction
= 0x3b60700;
14035 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14036 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14037 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14038 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14039 neon_dp_fixup (&inst
);
14043 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14044 do_vfp_nsyn_cvt (rs
, flavour
);
14049 do_neon_cvtr (void)
14051 do_neon_cvt_1 (FALSE
);
14057 do_neon_cvt_1 (TRUE
);
14061 do_neon_cvtb (void)
14063 inst
.instruction
= 0xeb20a40;
14065 /* The sizes are attached to the mnemonic. */
14066 if (inst
.vectype
.el
[0].type
!= NT_invtype
14067 && inst
.vectype
.el
[0].size
== 16)
14068 inst
.instruction
|= 0x00010000;
14070 /* Programmer's syntax: the sizes are attached to the operands. */
14071 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
14072 && inst
.operands
[0].vectype
.size
== 16)
14073 inst
.instruction
|= 0x00010000;
14075 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
14076 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
14077 do_vfp_cond_or_thumb ();
14082 do_neon_cvtt (void)
14085 inst
.instruction
|= 0x80;
14089 neon_move_immediate (void)
14091 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
14092 struct neon_type_el et
= neon_check_type (2, rs
,
14093 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14094 unsigned immlo
, immhi
= 0, immbits
;
14095 int op
, cmode
, float_p
;
14097 constraint (et
.type
== NT_invtype
,
14098 _("operand size must be specified for immediate VMOV"));
14100 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14101 op
= (inst
.instruction
& (1 << 5)) != 0;
14103 immlo
= inst
.operands
[1].imm
;
14104 if (inst
.operands
[1].regisimm
)
14105 immhi
= inst
.operands
[1].reg
;
14107 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
14108 _("immediate has bits set outside the operand size"));
14110 float_p
= inst
.operands
[1].immisfloat
;
14112 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
14113 et
.size
, et
.type
)) == FAIL
)
14115 /* Invert relevant bits only. */
14116 neon_invert_size (&immlo
, &immhi
, et
.size
);
14117 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14118 with one or the other; those cases are caught by
14119 neon_cmode_for_move_imm. */
14121 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
14122 &op
, et
.size
, et
.type
)) == FAIL
)
14124 first_error (_("immediate out of range"));
14129 inst
.instruction
&= ~(1 << 5);
14130 inst
.instruction
|= op
<< 5;
14132 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14133 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14134 inst
.instruction
|= neon_quad (rs
) << 6;
14135 inst
.instruction
|= cmode
<< 8;
14137 neon_write_immbits (immbits
);
14143 if (inst
.operands
[1].isreg
)
14145 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14147 NEON_ENCODE (INTEGER
, inst
);
14148 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14149 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14150 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14151 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14152 inst
.instruction
|= neon_quad (rs
) << 6;
14156 NEON_ENCODE (IMMED
, inst
);
14157 neon_move_immediate ();
14160 neon_dp_fixup (&inst
);
14163 /* Encode instructions of form:
14165 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14166 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14169 neon_mixed_length (struct neon_type_el et
, unsigned size
)
14171 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14172 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14173 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14174 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14175 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14176 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14177 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
14178 inst
.instruction
|= neon_logbits (size
) << 20;
14180 neon_dp_fixup (&inst
);
14184 do_neon_dyadic_long (void)
14186 /* FIXME: Type checking for lengthening op. */
14187 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14188 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14189 neon_mixed_length (et
, et
.size
);
14193 do_neon_abal (void)
14195 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14196 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14197 neon_mixed_length (et
, et
.size
);
14201 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
14203 if (inst
.operands
[2].isscalar
)
14205 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
14206 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
14207 NEON_ENCODE (SCALAR
, inst
);
14208 neon_mul_mac (et
, et
.type
== NT_unsigned
);
14212 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14213 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
14214 NEON_ENCODE (INTEGER
, inst
);
14215 neon_mixed_length (et
, et
.size
);
14220 do_neon_mac_maybe_scalar_long (void)
14222 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
14226 do_neon_dyadic_wide (void)
14228 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
14229 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14230 neon_mixed_length (et
, et
.size
);
14234 do_neon_dyadic_narrow (void)
14236 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14237 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
14238 /* Operand sign is unimportant, and the U bit is part of the opcode,
14239 so force the operand type to integer. */
14240 et
.type
= NT_integer
;
14241 neon_mixed_length (et
, et
.size
/ 2);
14245 do_neon_mul_sat_scalar_long (void)
14247 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
14251 do_neon_vmull (void)
14253 if (inst
.operands
[2].isscalar
)
14254 do_neon_mac_maybe_scalar_long ();
14257 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14258 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
14259 if (et
.type
== NT_poly
)
14260 NEON_ENCODE (POLY
, inst
);
14262 NEON_ENCODE (INTEGER
, inst
);
14263 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14264 zero. Should be OK as-is. */
14265 neon_mixed_length (et
, et
.size
);
14272 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14273 struct neon_type_el et
= neon_check_type (3, rs
,
14274 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14275 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14277 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14278 _("shift out of range"));
14279 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14280 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14281 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14282 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14283 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14284 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14285 inst
.instruction
|= neon_quad (rs
) << 6;
14286 inst
.instruction
|= imm
<< 8;
14288 neon_dp_fixup (&inst
);
14294 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14295 struct neon_type_el et
= neon_check_type (2, rs
,
14296 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14297 unsigned op
= (inst
.instruction
>> 7) & 3;
14298 /* N (width of reversed regions) is encoded as part of the bitmask. We
14299 extract it here to check the elements to be reversed are smaller.
14300 Otherwise we'd get a reserved instruction. */
14301 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14302 gas_assert (elsize
!= 0);
14303 constraint (et
.size
>= elsize
,
14304 _("elements must be smaller than reversal region"));
14305 neon_two_same (neon_quad (rs
), 1, et
.size
);
14311 if (inst
.operands
[1].isscalar
)
14313 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14314 struct neon_type_el et
= neon_check_type (2, rs
,
14315 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14316 unsigned sizebits
= et
.size
>> 3;
14317 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14318 int logsize
= neon_logbits (et
.size
);
14319 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14321 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14324 NEON_ENCODE (SCALAR
, inst
);
14325 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14326 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14327 inst
.instruction
|= LOW4 (dm
);
14328 inst
.instruction
|= HI1 (dm
) << 5;
14329 inst
.instruction
|= neon_quad (rs
) << 6;
14330 inst
.instruction
|= x
<< 17;
14331 inst
.instruction
|= sizebits
<< 16;
14333 neon_dp_fixup (&inst
);
14337 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14338 struct neon_type_el et
= neon_check_type (2, rs
,
14339 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14340 /* Duplicate ARM register to lanes of vector. */
14341 NEON_ENCODE (ARMREG
, inst
);
14344 case 8: inst
.instruction
|= 0x400000; break;
14345 case 16: inst
.instruction
|= 0x000020; break;
14346 case 32: inst
.instruction
|= 0x000000; break;
14349 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14350 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14351 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14352 inst
.instruction
|= neon_quad (rs
) << 21;
14353 /* The encoding for this instruction is identical for the ARM and Thumb
14354 variants, except for the condition field. */
14355 do_vfp_cond_or_thumb ();
14359 /* VMOV has particularly many variations. It can be one of:
14360 0. VMOV<c><q> <Qd>, <Qm>
14361 1. VMOV<c><q> <Dd>, <Dm>
14362 (Register operations, which are VORR with Rm = Rn.)
14363 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14364 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14366 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14367 (ARM register to scalar.)
14368 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14369 (Two ARM registers to vector.)
14370 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14371 (Scalar to ARM register.)
14372 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14373 (Vector to two ARM registers.)
14374 8. VMOV.F32 <Sd>, <Sm>
14375 9. VMOV.F64 <Dd>, <Dm>
14376 (VFP register moves.)
14377 10. VMOV.F32 <Sd>, #imm
14378 11. VMOV.F64 <Dd>, #imm
14379 (VFP float immediate load.)
14380 12. VMOV <Rd>, <Sm>
14381 (VFP single to ARM reg.)
14382 13. VMOV <Sd>, <Rm>
14383 (ARM reg to VFP single.)
14384 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14385 (Two ARM regs to two VFP singles.)
14386 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14387 (Two VFP singles to two ARM regs.)
14389 These cases can be disambiguated using neon_select_shape, except cases 1/9
14390 and 3/11 which depend on the operand type too.
14392 All the encoded bits are hardcoded by this function.
14394 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14395 Cases 5, 7 may be used with VFPv2 and above.
14397 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14398 can specify a type where it doesn't make sense to, and is ignored). */
14403 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14404 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14406 struct neon_type_el et
;
14407 const char *ldconst
= 0;
14411 case NS_DD
: /* case 1/9. */
14412 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14413 /* It is not an error here if no type is given. */
14415 if (et
.type
== NT_float
&& et
.size
== 64)
14417 do_vfp_nsyn_opcode ("fcpyd");
14420 /* fall through. */
14422 case NS_QQ
: /* case 0/1. */
14424 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14426 /* The architecture manual I have doesn't explicitly state which
14427 value the U bit should have for register->register moves, but
14428 the equivalent VORR instruction has U = 0, so do that. */
14429 inst
.instruction
= 0x0200110;
14430 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14431 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14432 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14433 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14434 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14435 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14436 inst
.instruction
|= neon_quad (rs
) << 6;
14438 neon_dp_fixup (&inst
);
14442 case NS_DI
: /* case 3/11. */
14443 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14445 if (et
.type
== NT_float
&& et
.size
== 64)
14447 /* case 11 (fconstd). */
14448 ldconst
= "fconstd";
14449 goto encode_fconstd
;
14451 /* fall through. */
14453 case NS_QI
: /* case 2/3. */
14454 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14456 inst
.instruction
= 0x0800010;
14457 neon_move_immediate ();
14458 neon_dp_fixup (&inst
);
14461 case NS_SR
: /* case 4. */
14463 unsigned bcdebits
= 0;
14465 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14466 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14468 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14469 logsize
= neon_logbits (et
.size
);
14471 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14473 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14474 && et
.size
!= 32, _(BAD_FPU
));
14475 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14476 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14480 case 8: bcdebits
= 0x8; break;
14481 case 16: bcdebits
= 0x1; break;
14482 case 32: bcdebits
= 0x0; break;
14486 bcdebits
|= x
<< logsize
;
14488 inst
.instruction
= 0xe000b10;
14489 do_vfp_cond_or_thumb ();
14490 inst
.instruction
|= LOW4 (dn
) << 16;
14491 inst
.instruction
|= HI1 (dn
) << 7;
14492 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14493 inst
.instruction
|= (bcdebits
& 3) << 5;
14494 inst
.instruction
|= (bcdebits
>> 2) << 21;
14498 case NS_DRR
: /* case 5 (fmdrr). */
14499 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14502 inst
.instruction
= 0xc400b10;
14503 do_vfp_cond_or_thumb ();
14504 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14505 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14506 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14507 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14510 case NS_RS
: /* case 6. */
14513 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14514 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14515 unsigned abcdebits
= 0;
14517 et
= neon_check_type (2, NS_NULL
,
14518 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14519 logsize
= neon_logbits (et
.size
);
14521 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14523 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14524 && et
.size
!= 32, _(BAD_FPU
));
14525 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14526 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14530 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14531 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14532 case 32: abcdebits
= 0x00; break;
14536 abcdebits
|= x
<< logsize
;
14537 inst
.instruction
= 0xe100b10;
14538 do_vfp_cond_or_thumb ();
14539 inst
.instruction
|= LOW4 (dn
) << 16;
14540 inst
.instruction
|= HI1 (dn
) << 7;
14541 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14542 inst
.instruction
|= (abcdebits
& 3) << 5;
14543 inst
.instruction
|= (abcdebits
>> 2) << 21;
14547 case NS_RRD
: /* case 7 (fmrrd). */
14548 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14551 inst
.instruction
= 0xc500b10;
14552 do_vfp_cond_or_thumb ();
14553 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14554 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14555 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14556 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14559 case NS_FF
: /* case 8 (fcpys). */
14560 do_vfp_nsyn_opcode ("fcpys");
14563 case NS_FI
: /* case 10 (fconsts). */
14564 ldconst
= "fconsts";
14566 if (is_quarter_float (inst
.operands
[1].imm
))
14568 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14569 do_vfp_nsyn_opcode (ldconst
);
14572 first_error (_("immediate out of range"));
14575 case NS_RF
: /* case 12 (fmrs). */
14576 do_vfp_nsyn_opcode ("fmrs");
14579 case NS_FR
: /* case 13 (fmsr). */
14580 do_vfp_nsyn_opcode ("fmsr");
14583 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14584 (one of which is a list), but we have parsed four. Do some fiddling to
14585 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14587 case NS_RRFF
: /* case 14 (fmrrs). */
14588 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14589 _("VFP registers must be adjacent"));
14590 inst
.operands
[2].imm
= 2;
14591 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14592 do_vfp_nsyn_opcode ("fmrrs");
14595 case NS_FFRR
: /* case 15 (fmsrr). */
14596 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14597 _("VFP registers must be adjacent"));
14598 inst
.operands
[1] = inst
.operands
[2];
14599 inst
.operands
[2] = inst
.operands
[3];
14600 inst
.operands
[0].imm
= 2;
14601 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14602 do_vfp_nsyn_opcode ("fmsrr");
14611 do_neon_rshift_round_imm (void)
14613 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14614 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14615 int imm
= inst
.operands
[2].imm
;
14617 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14620 inst
.operands
[2].present
= 0;
14625 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14626 _("immediate out of range for shift"));
14627 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14632 do_neon_movl (void)
14634 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14635 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14636 unsigned sizebits
= et
.size
>> 3;
14637 inst
.instruction
|= sizebits
<< 19;
14638 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14644 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14645 struct neon_type_el et
= neon_check_type (2, rs
,
14646 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14647 NEON_ENCODE (INTEGER
, inst
);
14648 neon_two_same (neon_quad (rs
), 1, et
.size
);
14652 do_neon_zip_uzp (void)
14654 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14655 struct neon_type_el et
= neon_check_type (2, rs
,
14656 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14657 if (rs
== NS_DD
&& et
.size
== 32)
14659 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14660 inst
.instruction
= N_MNEM_vtrn
;
14664 neon_two_same (neon_quad (rs
), 1, et
.size
);
14668 do_neon_sat_abs_neg (void)
14670 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14671 struct neon_type_el et
= neon_check_type (2, rs
,
14672 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14673 neon_two_same (neon_quad (rs
), 1, et
.size
);
14677 do_neon_pair_long (void)
14679 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14680 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14681 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14682 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14683 neon_two_same (neon_quad (rs
), 1, et
.size
);
14687 do_neon_recip_est (void)
14689 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14690 struct neon_type_el et
= neon_check_type (2, rs
,
14691 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14692 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14693 neon_two_same (neon_quad (rs
), 1, et
.size
);
14699 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14700 struct neon_type_el et
= neon_check_type (2, rs
,
14701 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14702 neon_two_same (neon_quad (rs
), 1, et
.size
);
14708 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14709 struct neon_type_el et
= neon_check_type (2, rs
,
14710 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14711 neon_two_same (neon_quad (rs
), 1, et
.size
);
14717 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14718 struct neon_type_el et
= neon_check_type (2, rs
,
14719 N_EQK
| N_INT
, N_8
| N_KEY
);
14720 neon_two_same (neon_quad (rs
), 1, et
.size
);
14726 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14727 neon_two_same (neon_quad (rs
), 1, -1);
14731 do_neon_tbl_tbx (void)
14733 unsigned listlenbits
;
14734 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
14736 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
14738 first_error (_("bad list length for table lookup"));
14742 listlenbits
= inst
.operands
[1].imm
- 1;
14743 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14744 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14745 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14746 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14747 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14748 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14749 inst
.instruction
|= listlenbits
<< 8;
14751 neon_dp_fixup (&inst
);
14755 do_neon_ldm_stm (void)
14757 /* P, U and L bits are part of bitmask. */
14758 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
14759 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
14761 if (inst
.operands
[1].issingle
)
14763 do_vfp_nsyn_ldm_stm (is_dbmode
);
14767 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
14768 _("writeback (!) must be used for VLDMDB and VSTMDB"));
14770 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14771 _("register list must contain at least 1 and at most 16 "
14774 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14775 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
14776 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14777 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
14779 inst
.instruction
|= offsetbits
;
14781 do_vfp_cond_or_thumb ();
14785 do_neon_ldr_str (void)
14787 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
14789 if (inst
.operands
[0].issingle
)
14792 do_vfp_nsyn_opcode ("flds");
14794 do_vfp_nsyn_opcode ("fsts");
14799 do_vfp_nsyn_opcode ("fldd");
14801 do_vfp_nsyn_opcode ("fstd");
14805 /* "interleave" version also handles non-interleaving register VLD1/VST1
14809 do_neon_ld_st_interleave (void)
14811 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14812 N_8
| N_16
| N_32
| N_64
);
14813 unsigned alignbits
= 0;
14815 /* The bits in this table go:
14816 0: register stride of one (0) or two (1)
14817 1,2: register list length, minus one (1, 2, 3, 4).
14818 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14819 We use -1 for invalid entries. */
14820 const int typetable
[] =
14822 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14823 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14824 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14825 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14829 if (et
.type
== NT_invtype
)
14832 if (inst
.operands
[1].immisalign
)
14833 switch (inst
.operands
[1].imm
>> 8)
14835 case 64: alignbits
= 1; break;
14837 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
14838 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14839 goto bad_alignment
;
14843 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14844 goto bad_alignment
;
14849 first_error (_("bad alignment"));
14853 inst
.instruction
|= alignbits
<< 4;
14854 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14856 /* Bits [4:6] of the immediate in a list specifier encode register stride
14857 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14858 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14859 up the right value for "type" in a table based on this value and the given
14860 list style, then stick it back. */
14861 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14862 | (((inst
.instruction
>> 8) & 3) << 3);
14864 typebits
= typetable
[idx
];
14866 constraint (typebits
== -1, _("bad list type for instruction"));
14868 inst
.instruction
&= ~0xf00;
14869 inst
.instruction
|= typebits
<< 8;
14872 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14873 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14874 otherwise. The variable arguments are a list of pairs of legal (size, align)
14875 values, terminated with -1. */
14878 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14881 int result
= FAIL
, thissize
, thisalign
;
14883 if (!inst
.operands
[1].immisalign
)
14889 va_start (ap
, do_align
);
14893 thissize
= va_arg (ap
, int);
14894 if (thissize
== -1)
14896 thisalign
= va_arg (ap
, int);
14898 if (size
== thissize
&& align
== thisalign
)
14901 while (result
!= SUCCESS
);
14905 if (result
== SUCCESS
)
14908 first_error (_("unsupported alignment for instruction"));
14914 do_neon_ld_st_lane (void)
14916 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14917 int align_good
, do_align
= 0;
14918 int logsize
= neon_logbits (et
.size
);
14919 int align
= inst
.operands
[1].imm
>> 8;
14920 int n
= (inst
.instruction
>> 8) & 3;
14921 int max_el
= 64 / et
.size
;
14923 if (et
.type
== NT_invtype
)
14926 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
14927 _("bad list length"));
14928 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
14929 _("scalar index out of range"));
14930 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
14932 _("stride of 2 unavailable when element size is 8"));
14936 case 0: /* VLD1 / VST1. */
14937 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
14939 if (align_good
== FAIL
)
14943 unsigned alignbits
= 0;
14946 case 16: alignbits
= 0x1; break;
14947 case 32: alignbits
= 0x3; break;
14950 inst
.instruction
|= alignbits
<< 4;
14954 case 1: /* VLD2 / VST2. */
14955 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
14957 if (align_good
== FAIL
)
14960 inst
.instruction
|= 1 << 4;
14963 case 2: /* VLD3 / VST3. */
14964 constraint (inst
.operands
[1].immisalign
,
14965 _("can't use alignment with this instruction"));
14968 case 3: /* VLD4 / VST4. */
14969 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14970 16, 64, 32, 64, 32, 128, -1);
14971 if (align_good
== FAIL
)
14975 unsigned alignbits
= 0;
14978 case 8: alignbits
= 0x1; break;
14979 case 16: alignbits
= 0x1; break;
14980 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
14983 inst
.instruction
|= alignbits
<< 4;
14990 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
14991 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14992 inst
.instruction
|= 1 << (4 + logsize
);
14994 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
14995 inst
.instruction
|= logsize
<< 10;
14998 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15001 do_neon_ld_dup (void)
15003 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15004 int align_good
, do_align
= 0;
15006 if (et
.type
== NT_invtype
)
15009 switch ((inst
.instruction
>> 8) & 3)
15011 case 0: /* VLD1. */
15012 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
15013 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15014 &do_align
, 16, 16, 32, 32, -1);
15015 if (align_good
== FAIL
)
15017 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
15020 case 2: inst
.instruction
|= 1 << 5; break;
15021 default: first_error (_("bad list length")); return;
15023 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15026 case 1: /* VLD2. */
15027 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15028 &do_align
, 8, 16, 16, 32, 32, 64, -1);
15029 if (align_good
== FAIL
)
15031 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
15032 _("bad list length"));
15033 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15034 inst
.instruction
|= 1 << 5;
15035 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15038 case 2: /* VLD3. */
15039 constraint (inst
.operands
[1].immisalign
,
15040 _("can't use alignment with this instruction"));
15041 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
15042 _("bad list length"));
15043 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15044 inst
.instruction
|= 1 << 5;
15045 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15048 case 3: /* VLD4. */
15050 int align
= inst
.operands
[1].imm
>> 8;
15051 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15052 16, 64, 32, 64, 32, 128, -1);
15053 if (align_good
== FAIL
)
15055 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
15056 _("bad list length"));
15057 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15058 inst
.instruction
|= 1 << 5;
15059 if (et
.size
== 32 && align
== 128)
15060 inst
.instruction
|= 0x3 << 6;
15062 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15069 inst
.instruction
|= do_align
<< 4;
15072 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15073 apart from bits [11:4]. */
15076 do_neon_ldx_stx (void)
15078 if (inst
.operands
[1].isreg
)
15079 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
15081 switch (NEON_LANE (inst
.operands
[0].imm
))
15083 case NEON_INTERLEAVE_LANES
:
15084 NEON_ENCODE (INTERLV
, inst
);
15085 do_neon_ld_st_interleave ();
15088 case NEON_ALL_LANES
:
15089 NEON_ENCODE (DUP
, inst
);
15094 NEON_ENCODE (LANE
, inst
);
15095 do_neon_ld_st_lane ();
15098 /* L bit comes from bit mask. */
15099 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15100 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15101 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15103 if (inst
.operands
[1].postind
)
15105 int postreg
= inst
.operands
[1].imm
& 0xf;
15106 constraint (!inst
.operands
[1].immisreg
,
15107 _("post-index must be a register"));
15108 constraint (postreg
== 0xd || postreg
== 0xf,
15109 _("bad register for post-index"));
15110 inst
.instruction
|= postreg
;
15112 else if (inst
.operands
[1].writeback
)
15114 inst
.instruction
|= 0xd;
15117 inst
.instruction
|= 0xf;
15120 inst
.instruction
|= 0xf9000000;
15122 inst
.instruction
|= 0xf4000000;
15125 /* Overall per-instruction processing. */
15127 /* We need to be able to fix up arbitrary expressions in some statements.
15128 This is so that we can handle symbols that are an arbitrary distance from
15129 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15130 which returns part of an address in a form which will be valid for
15131 a data instruction. We do this by pushing the expression into a symbol
15132 in the expr_section, and creating a fix for that. */
15135 fix_new_arm (fragS
* frag
,
15150 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
15151 (enum bfd_reloc_code_real
) reloc
);
15155 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
15156 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
15160 /* Mark whether the fix is to a THUMB instruction, or an ARM
15162 new_fix
->tc_fix_data
= thumb_mode
;
15165 /* Create a frg for an instruction requiring relaxation. */
15167 output_relax_insn (void)
15173 /* The size of the instruction is unknown, so tie the debug info to the
15174 start of the instruction. */
15175 dwarf2_emit_insn (0);
15177 switch (inst
.reloc
.exp
.X_op
)
15180 sym
= inst
.reloc
.exp
.X_add_symbol
;
15181 offset
= inst
.reloc
.exp
.X_add_number
;
15185 offset
= inst
.reloc
.exp
.X_add_number
;
15188 sym
= make_expr_symbol (&inst
.reloc
.exp
);
15192 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
15193 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
15194 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
15197 /* Write a 32-bit thumb instruction to buf. */
15199 put_thumb32_insn (char * buf
, unsigned long insn
)
15201 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
15202 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
15206 output_inst (const char * str
)
15212 as_bad ("%s -- `%s'", inst
.error
, str
);
15217 output_relax_insn ();
15220 if (inst
.size
== 0)
15223 to
= frag_more (inst
.size
);
15224 /* PR 9814: Record the thumb mode into the current frag so that we know
15225 what type of NOP padding to use, if necessary. We override any previous
15226 setting so that if the mode has changed then the NOPS that we use will
15227 match the encoding of the last instruction in the frag. */
15228 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
15230 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
15232 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
15233 put_thumb32_insn (to
, inst
.instruction
);
15235 else if (inst
.size
> INSN_SIZE
)
15237 gas_assert (inst
.size
== (2 * INSN_SIZE
));
15238 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
15239 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
15242 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
15244 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
15245 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
15246 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
15249 dwarf2_emit_insn (inst
.size
);
15253 output_it_inst (int cond
, int mask
, char * to
)
15255 unsigned long instruction
= 0xbf00;
15258 instruction
|= mask
;
15259 instruction
|= cond
<< 4;
15263 to
= frag_more (2);
15265 dwarf2_emit_insn (2);
15269 md_number_to_chars (to
, instruction
, 2);
15274 /* Tag values used in struct asm_opcode's tag field. */
15277 OT_unconditional
, /* Instruction cannot be conditionalized.
15278 The ARM condition field is still 0xE. */
15279 OT_unconditionalF
, /* Instruction cannot be conditionalized
15280 and carries 0xF in its ARM condition field. */
15281 OT_csuffix
, /* Instruction takes a conditional suffix. */
15282 OT_csuffixF
, /* Some forms of the instruction take a conditional
15283 suffix, others place 0xF where the condition field
15285 OT_cinfix3
, /* Instruction takes a conditional infix,
15286 beginning at character index 3. (In
15287 unified mode, it becomes a suffix.) */
15288 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15289 tsts, cmps, cmns, and teqs. */
15290 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15291 character index 3, even in unified mode. Used for
15292 legacy instructions where suffix and infix forms
15293 may be ambiguous. */
15294 OT_csuf_or_in3
, /* Instruction takes either a conditional
15295 suffix or an infix at character index 3. */
15296 OT_odd_infix_unc
, /* This is the unconditional variant of an
15297 instruction that takes a conditional infix
15298 at an unusual position. In unified mode,
15299 this variant will accept a suffix. */
15300 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15301 are the conditional variants of instructions that
15302 take conditional infixes in unusual positions.
15303 The infix appears at character index
15304 (tag - OT_odd_infix_0). These are not accepted
15305 in unified mode. */
15308 /* Subroutine of md_assemble, responsible for looking up the primary
15309 opcode from the mnemonic the user wrote. STR points to the
15310 beginning of the mnemonic.
15312 This is not simply a hash table lookup, because of conditional
15313 variants. Most instructions have conditional variants, which are
15314 expressed with a _conditional affix_ to the mnemonic. If we were
15315 to encode each conditional variant as a literal string in the opcode
15316 table, it would have approximately 20,000 entries.
15318 Most mnemonics take this affix as a suffix, and in unified syntax,
15319 'most' is upgraded to 'all'. However, in the divided syntax, some
15320 instructions take the affix as an infix, notably the s-variants of
15321 the arithmetic instructions. Of those instructions, all but six
15322 have the infix appear after the third character of the mnemonic.
15324 Accordingly, the algorithm for looking up primary opcodes given
15327 1. Look up the identifier in the opcode table.
15328 If we find a match, go to step U.
15330 2. Look up the last two characters of the identifier in the
15331 conditions table. If we find a match, look up the first N-2
15332 characters of the identifier in the opcode table. If we
15333 find a match, go to step CE.
15335 3. Look up the fourth and fifth characters of the identifier in
15336 the conditions table. If we find a match, extract those
15337 characters from the identifier, and look up the remaining
15338 characters in the opcode table. If we find a match, go
15343 U. Examine the tag field of the opcode structure, in case this is
15344 one of the six instructions with its conditional infix in an
15345 unusual place. If it is, the tag tells us where to find the
15346 infix; look it up in the conditions table and set inst.cond
15347 accordingly. Otherwise, this is an unconditional instruction.
15348 Again set inst.cond accordingly. Return the opcode structure.
15350 CE. Examine the tag field to make sure this is an instruction that
15351 should receive a conditional suffix. If it is not, fail.
15352 Otherwise, set inst.cond from the suffix we already looked up,
15353 and return the opcode structure.
15355 CM. Examine the tag field to make sure this is an instruction that
15356 should receive a conditional infix after the third character.
15357 If it is not, fail. Otherwise, undo the edits to the current
15358 line of input and proceed as for case CE. */
15360 static const struct asm_opcode
*
15361 opcode_lookup (char **str
)
15365 const struct asm_opcode
*opcode
;
15366 const struct asm_cond
*cond
;
15369 /* Scan up to the end of the mnemonic, which must end in white space,
15370 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15371 for (base
= end
= *str
; *end
!= '\0'; end
++)
15372 if (*end
== ' ' || *end
== '.')
15378 /* Handle a possible width suffix and/or Neon type suffix. */
15383 /* The .w and .n suffixes are only valid if the unified syntax is in
15385 if (unified_syntax
&& end
[1] == 'w')
15387 else if (unified_syntax
&& end
[1] == 'n')
15392 inst
.vectype
.elems
= 0;
15394 *str
= end
+ offset
;
15396 if (end
[offset
] == '.')
15398 /* See if we have a Neon type suffix (possible in either unified or
15399 non-unified ARM syntax mode). */
15400 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15403 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15409 /* Look for unaffixed or special-case affixed mnemonic. */
15410 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15415 if (opcode
->tag
< OT_odd_infix_0
)
15417 inst
.cond
= COND_ALWAYS
;
15421 if (warn_on_deprecated
&& unified_syntax
)
15422 as_warn (_("conditional infixes are deprecated in unified syntax"));
15423 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15424 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15427 inst
.cond
= cond
->value
;
15431 /* Cannot have a conditional suffix on a mnemonic of less than two
15433 if (end
- base
< 3)
15436 /* Look for suffixed mnemonic. */
15438 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15439 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15441 if (opcode
&& cond
)
15444 switch (opcode
->tag
)
15446 case OT_cinfix3_legacy
:
15447 /* Ignore conditional suffixes matched on infix only mnemonics. */
15451 case OT_cinfix3_deprecated
:
15452 case OT_odd_infix_unc
:
15453 if (!unified_syntax
)
15455 /* else fall through */
15459 case OT_csuf_or_in3
:
15460 inst
.cond
= cond
->value
;
15463 case OT_unconditional
:
15464 case OT_unconditionalF
:
15466 inst
.cond
= cond
->value
;
15469 /* Delayed diagnostic. */
15470 inst
.error
= BAD_COND
;
15471 inst
.cond
= COND_ALWAYS
;
15480 /* Cannot have a usual-position infix on a mnemonic of less than
15481 six characters (five would be a suffix). */
15482 if (end
- base
< 6)
15485 /* Look for infixed mnemonic in the usual position. */
15487 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15491 memcpy (save
, affix
, 2);
15492 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15493 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15495 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15496 memcpy (affix
, save
, 2);
15499 && (opcode
->tag
== OT_cinfix3
15500 || opcode
->tag
== OT_cinfix3_deprecated
15501 || opcode
->tag
== OT_csuf_or_in3
15502 || opcode
->tag
== OT_cinfix3_legacy
))
15505 if (warn_on_deprecated
&& unified_syntax
15506 && (opcode
->tag
== OT_cinfix3
15507 || opcode
->tag
== OT_cinfix3_deprecated
))
15508 as_warn (_("conditional infixes are deprecated in unified syntax"));
15510 inst
.cond
= cond
->value
;
15517 /* This function generates an initial IT instruction, leaving its block
15518 virtually open for the new instructions. Eventually,
15519 the mask will be updated by now_it_add_mask () each time
15520 a new instruction needs to be included in the IT block.
15521 Finally, the block is closed with close_automatic_it_block ().
15522 The block closure can be requested either from md_assemble (),
15523 a tencode (), or due to a label hook. */
15526 new_automatic_it_block (int cond
)
15528 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15529 now_it
.mask
= 0x18;
15531 now_it
.block_length
= 1;
15532 mapping_state (MAP_THUMB
);
15533 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15536 /* Close an automatic IT block.
15537 See comments in new_automatic_it_block (). */
15540 close_automatic_it_block (void)
15542 now_it
.mask
= 0x10;
15543 now_it
.block_length
= 0;
15546 /* Update the mask of the current automatically-generated IT
15547 instruction. See comments in new_automatic_it_block (). */
15550 now_it_add_mask (int cond
)
15552 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15553 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15554 | ((bitvalue) << (nbit)))
15555 const int resulting_bit
= (cond
& 1);
15557 now_it
.mask
&= 0xf;
15558 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15560 (5 - now_it
.block_length
));
15561 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15563 ((5 - now_it
.block_length
) - 1) );
15564 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15567 #undef SET_BIT_VALUE
15570 /* The IT blocks handling machinery is accessed through the these functions:
15571 it_fsm_pre_encode () from md_assemble ()
15572 set_it_insn_type () optional, from the tencode functions
15573 set_it_insn_type_last () ditto
15574 in_it_block () ditto
15575 it_fsm_post_encode () from md_assemble ()
15576 force_automatic_it_block_close () from label habdling functions
15579 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15580 initializing the IT insn type with a generic initial value depending
15581 on the inst.condition.
15582 2) During the tencode function, two things may happen:
15583 a) The tencode function overrides the IT insn type by
15584 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15585 b) The tencode function queries the IT block state by
15586 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15588 Both set_it_insn_type and in_it_block run the internal FSM state
15589 handling function (handle_it_state), because: a) setting the IT insn
15590 type may incur in an invalid state (exiting the function),
15591 and b) querying the state requires the FSM to be updated.
15592 Specifically we want to avoid creating an IT block for conditional
15593 branches, so it_fsm_pre_encode is actually a guess and we can't
15594 determine whether an IT block is required until the tencode () routine
15595 has decided what type of instruction this actually it.
15596 Because of this, if set_it_insn_type and in_it_block have to be used,
15597 set_it_insn_type has to be called first.
15599 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15600 determines the insn IT type depending on the inst.cond code.
15601 When a tencode () routine encodes an instruction that can be
15602 either outside an IT block, or, in the case of being inside, has to be
15603 the last one, set_it_insn_type_last () will determine the proper
15604 IT instruction type based on the inst.cond code. Otherwise,
15605 set_it_insn_type can be called for overriding that logic or
15606 for covering other cases.
15608 Calling handle_it_state () may not transition the IT block state to
15609 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15610 still queried. Instead, if the FSM determines that the state should
15611 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15612 after the tencode () function: that's what it_fsm_post_encode () does.
15614 Since in_it_block () calls the state handling function to get an
15615 updated state, an error may occur (due to invalid insns combination).
15616 In that case, inst.error is set.
15617 Therefore, inst.error has to be checked after the execution of
15618 the tencode () routine.
15620 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15621 any pending state change (if any) that didn't take place in
15622 handle_it_state () as explained above. */
15625 it_fsm_pre_encode (void)
15627 if (inst
.cond
!= COND_ALWAYS
)
15628 inst
.it_insn_type
= INSIDE_IT_INSN
;
15630 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15632 now_it
.state_handled
= 0;
15635 /* IT state FSM handling function. */
15638 handle_it_state (void)
15640 now_it
.state_handled
= 1;
15642 switch (now_it
.state
)
15644 case OUTSIDE_IT_BLOCK
:
15645 switch (inst
.it_insn_type
)
15647 case OUTSIDE_IT_INSN
:
15650 case INSIDE_IT_INSN
:
15651 case INSIDE_IT_LAST_INSN
:
15652 if (thumb_mode
== 0)
15655 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15656 as_tsktsk (_("Warning: conditional outside an IT block"\
15661 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15662 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15664 /* Automatically generate the IT instruction. */
15665 new_automatic_it_block (inst
.cond
);
15666 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15667 close_automatic_it_block ();
15671 inst
.error
= BAD_OUT_IT
;
15677 case IF_INSIDE_IT_LAST_INSN
:
15678 case NEUTRAL_IT_INSN
:
15682 now_it
.state
= MANUAL_IT_BLOCK
;
15683 now_it
.block_length
= 0;
15688 case AUTOMATIC_IT_BLOCK
:
15689 /* Three things may happen now:
15690 a) We should increment current it block size;
15691 b) We should close current it block (closing insn or 4 insns);
15692 c) We should close current it block and start a new one (due
15693 to incompatible conditions or
15694 4 insns-length block reached). */
15696 switch (inst
.it_insn_type
)
15698 case OUTSIDE_IT_INSN
:
15699 /* The closure of the block shall happen immediatelly,
15700 so any in_it_block () call reports the block as closed. */
15701 force_automatic_it_block_close ();
15704 case INSIDE_IT_INSN
:
15705 case INSIDE_IT_LAST_INSN
:
15706 case IF_INSIDE_IT_LAST_INSN
:
15707 now_it
.block_length
++;
15709 if (now_it
.block_length
> 4
15710 || !now_it_compatible (inst
.cond
))
15712 force_automatic_it_block_close ();
15713 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
15714 new_automatic_it_block (inst
.cond
);
15718 now_it_add_mask (inst
.cond
);
15721 if (now_it
.state
== AUTOMATIC_IT_BLOCK
15722 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
15723 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
15724 close_automatic_it_block ();
15727 case NEUTRAL_IT_INSN
:
15728 now_it
.block_length
++;
15730 if (now_it
.block_length
> 4)
15731 force_automatic_it_block_close ();
15733 now_it_add_mask (now_it
.cc
& 1);
15737 close_automatic_it_block ();
15738 now_it
.state
= MANUAL_IT_BLOCK
;
15743 case MANUAL_IT_BLOCK
:
15745 /* Check conditional suffixes. */
15746 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
15749 now_it
.mask
&= 0x1f;
15750 is_last
= (now_it
.mask
== 0x10);
15752 switch (inst
.it_insn_type
)
15754 case OUTSIDE_IT_INSN
:
15755 inst
.error
= BAD_NOT_IT
;
15758 case INSIDE_IT_INSN
:
15759 if (cond
!= inst
.cond
)
15761 inst
.error
= BAD_IT_COND
;
15766 case INSIDE_IT_LAST_INSN
:
15767 case IF_INSIDE_IT_LAST_INSN
:
15768 if (cond
!= inst
.cond
)
15770 inst
.error
= BAD_IT_COND
;
15775 inst
.error
= BAD_BRANCH
;
15780 case NEUTRAL_IT_INSN
:
15781 /* The BKPT instruction is unconditional even in an IT block. */
15785 inst
.error
= BAD_IT_IT
;
15796 it_fsm_post_encode (void)
15800 if (!now_it
.state_handled
)
15801 handle_it_state ();
15803 is_last
= (now_it
.mask
== 0x10);
15806 now_it
.state
= OUTSIDE_IT_BLOCK
;
15812 force_automatic_it_block_close (void)
15814 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
15816 close_automatic_it_block ();
15817 now_it
.state
= OUTSIDE_IT_BLOCK
;
15825 if (!now_it
.state_handled
)
15826 handle_it_state ();
15828 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
15832 md_assemble (char *str
)
15835 const struct asm_opcode
* opcode
;
15837 /* Align the previous label if needed. */
15838 if (last_label_seen
!= NULL
)
15840 symbol_set_frag (last_label_seen
, frag_now
);
15841 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
15842 S_SET_SEGMENT (last_label_seen
, now_seg
);
15845 memset (&inst
, '\0', sizeof (inst
));
15846 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
15848 opcode
= opcode_lookup (&p
);
15851 /* It wasn't an instruction, but it might be a register alias of
15852 the form alias .req reg, or a Neon .dn/.qn directive. */
15853 if (! create_register_alias (str
, p
)
15854 && ! create_neon_reg_alias (str
, p
))
15855 as_bad (_("bad instruction `%s'"), str
);
15860 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
15861 as_warn (_("s suffix on comparison instruction is deprecated"));
15863 /* The value which unconditional instructions should have in place of the
15864 condition field. */
15865 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
15869 arm_feature_set variant
;
15871 variant
= cpu_variant
;
15872 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
15873 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
15874 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
15875 /* Check that this instruction is supported for this CPU. */
15876 if (!opcode
->tvariant
15877 || (thumb_mode
== 1
15878 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
15880 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
15883 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
15884 && opcode
->tencode
!= do_t_branch
)
15886 as_bad (_("Thumb does not support conditional execution"));
15890 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
15892 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
15893 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
15894 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
15896 /* Two things are addressed here.
15897 1) Implicit require narrow instructions on Thumb-1.
15898 This avoids relaxation accidentally introducing Thumb-2
15900 2) Reject wide instructions in non Thumb-2 cores. */
15901 if (inst
.size_req
== 0)
15903 else if (inst
.size_req
== 4)
15905 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
15911 inst
.instruction
= opcode
->tvalue
;
15913 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
15915 /* Prepare the it_insn_type for those encodings that don't set
15917 it_fsm_pre_encode ();
15919 opcode
->tencode ();
15921 it_fsm_post_encode ();
15924 if (!(inst
.error
|| inst
.relax
))
15926 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
15927 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
15928 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
15930 as_bad (_("cannot honor width suffix -- `%s'"), str
);
15935 /* Something has gone badly wrong if we try to relax a fixed size
15937 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
15939 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15940 *opcode
->tvariant
);
15941 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
15942 set those bits when Thumb-2 32-bit instructions are seen. ie.
15943 anything other than bl/blx and v6-M instructions.
15944 This is overly pessimistic for relaxable instructions. */
15945 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
15947 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
15948 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
15949 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15952 check_neon_suffixes
;
15956 mapping_state (MAP_THUMB
);
15959 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
15963 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
15964 is_bx
= (opcode
->aencode
== do_bx
);
15966 /* Check that this instruction is supported for this CPU. */
15967 if (!(is_bx
&& fix_v4bx
)
15968 && !(opcode
->avariant
&&
15969 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
15971 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
15976 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
15980 inst
.instruction
= opcode
->avalue
;
15981 if (opcode
->tag
== OT_unconditionalF
)
15982 inst
.instruction
|= 0xF << 28;
15984 inst
.instruction
|= inst
.cond
<< 28;
15985 inst
.size
= INSN_SIZE
;
15986 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
15988 it_fsm_pre_encode ();
15989 opcode
->aencode ();
15990 it_fsm_post_encode ();
15992 /* Arm mode bx is marked as both v4T and v5 because it's still required
15993 on a hypothetical non-thumb v5 core. */
15995 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
15997 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
15998 *opcode
->avariant
);
16000 check_neon_suffixes
;
16004 mapping_state (MAP_ARM
);
16009 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16017 check_it_blocks_finished (void)
16022 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
16023 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
16024 == MANUAL_IT_BLOCK
)
16026 as_warn (_("section '%s' finished with an open IT block."),
16030 if (now_it
.state
== MANUAL_IT_BLOCK
)
16031 as_warn (_("file finished with an open IT block."));
16035 /* Various frobbings of labels and their addresses. */
16038 arm_start_line_hook (void)
16040 last_label_seen
= NULL
;
16044 arm_frob_label (symbolS
* sym
)
16046 last_label_seen
= sym
;
16048 ARM_SET_THUMB (sym
, thumb_mode
);
16050 #if defined OBJ_COFF || defined OBJ_ELF
16051 ARM_SET_INTERWORK (sym
, support_interwork
);
16054 force_automatic_it_block_close ();
16056 /* Note - do not allow local symbols (.Lxxx) to be labelled
16057 as Thumb functions. This is because these labels, whilst
16058 they exist inside Thumb code, are not the entry points for
16059 possible ARM->Thumb calls. Also, these labels can be used
16060 as part of a computed goto or switch statement. eg gcc
16061 can generate code that looks like this:
16063 ldr r2, [pc, .Laaa]
16073 The first instruction loads the address of the jump table.
16074 The second instruction converts a table index into a byte offset.
16075 The third instruction gets the jump address out of the table.
16076 The fourth instruction performs the jump.
16078 If the address stored at .Laaa is that of a symbol which has the
16079 Thumb_Func bit set, then the linker will arrange for this address
16080 to have the bottom bit set, which in turn would mean that the
16081 address computation performed by the third instruction would end
16082 up with the bottom bit set. Since the ARM is capable of unaligned
16083 word loads, the instruction would then load the incorrect address
16084 out of the jump table, and chaos would ensue. */
16085 if (label_is_thumb_function_name
16086 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
16087 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
16089 /* When the address of a Thumb function is taken the bottom
16090 bit of that address should be set. This will allow
16091 interworking between Arm and Thumb functions to work
16094 THUMB_SET_FUNC (sym
, 1);
16096 label_is_thumb_function_name
= FALSE
;
16099 dwarf2_emit_label (sym
);
16103 arm_data_in_code (void)
16105 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
16107 *input_line_pointer
= '/';
16108 input_line_pointer
+= 5;
16109 *input_line_pointer
= 0;
16117 arm_canonicalize_symbol_name (char * name
)
16121 if (thumb_mode
&& (len
= strlen (name
)) > 5
16122 && streq (name
+ len
- 5, "/data"))
16123 *(name
+ len
- 5) = 0;
16128 /* Table of all register names defined by default. The user can
16129 define additional names with .req. Note that all register names
16130 should appear in both upper and lowercase variants. Some registers
16131 also have mixed-case names. */
16133 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16134 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16135 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16136 #define REGSET(p,t) \
16137 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16138 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16139 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16140 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16141 #define REGSETH(p,t) \
16142 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16143 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16144 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16145 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16146 #define REGSET2(p,t) \
16147 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16148 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16149 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16150 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16152 static const struct reg_entry reg_names
[] =
16154 /* ARM integer registers. */
16155 REGSET(r
, RN
), REGSET(R
, RN
),
16157 /* ATPCS synonyms. */
16158 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
16159 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
16160 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
16162 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
16163 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
16164 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
16166 /* Well-known aliases. */
16167 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
16168 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
16170 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
16171 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
16173 /* Coprocessor numbers. */
16174 REGSET(p
, CP
), REGSET(P
, CP
),
16176 /* Coprocessor register numbers. The "cr" variants are for backward
16178 REGSET(c
, CN
), REGSET(C
, CN
),
16179 REGSET(cr
, CN
), REGSET(CR
, CN
),
16181 /* FPA registers. */
16182 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
16183 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
16185 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
16186 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
16188 /* VFP SP registers. */
16189 REGSET(s
,VFS
), REGSET(S
,VFS
),
16190 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
16192 /* VFP DP Registers. */
16193 REGSET(d
,VFD
), REGSET(D
,VFD
),
16194 /* Extra Neon DP registers. */
16195 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
16197 /* Neon QP registers. */
16198 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
16200 /* VFP control registers. */
16201 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
16202 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
16203 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
16204 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
16205 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
16206 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
16208 /* Maverick DSP coprocessor registers. */
16209 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
16210 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
16212 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
16213 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
16214 REGDEF(dspsc
,0,DSPSC
),
16216 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
16217 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
16218 REGDEF(DSPSC
,0,DSPSC
),
16220 /* iWMMXt data registers - p0, c0-15. */
16221 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
16223 /* iWMMXt control registers - p1, c0-3. */
16224 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
16225 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
16226 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
16227 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
16229 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16230 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
16231 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
16232 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
16233 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
16235 /* XScale accumulator registers. */
16236 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
16242 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16243 within psr_required_here. */
16244 static const struct asm_psr psrs
[] =
16246 /* Backward compatibility notation. Note that "all" is no longer
16247 truly all possible PSR bits. */
16248 {"all", PSR_c
| PSR_f
},
16252 /* Individual flags. */
16259 /* Combinations of flags. */
16260 {"fs", PSR_f
| PSR_s
},
16261 {"fx", PSR_f
| PSR_x
},
16262 {"fc", PSR_f
| PSR_c
},
16263 {"sf", PSR_s
| PSR_f
},
16264 {"sx", PSR_s
| PSR_x
},
16265 {"sc", PSR_s
| PSR_c
},
16266 {"xf", PSR_x
| PSR_f
},
16267 {"xs", PSR_x
| PSR_s
},
16268 {"xc", PSR_x
| PSR_c
},
16269 {"cf", PSR_c
| PSR_f
},
16270 {"cs", PSR_c
| PSR_s
},
16271 {"cx", PSR_c
| PSR_x
},
16272 {"fsx", PSR_f
| PSR_s
| PSR_x
},
16273 {"fsc", PSR_f
| PSR_s
| PSR_c
},
16274 {"fxs", PSR_f
| PSR_x
| PSR_s
},
16275 {"fxc", PSR_f
| PSR_x
| PSR_c
},
16276 {"fcs", PSR_f
| PSR_c
| PSR_s
},
16277 {"fcx", PSR_f
| PSR_c
| PSR_x
},
16278 {"sfx", PSR_s
| PSR_f
| PSR_x
},
16279 {"sfc", PSR_s
| PSR_f
| PSR_c
},
16280 {"sxf", PSR_s
| PSR_x
| PSR_f
},
16281 {"sxc", PSR_s
| PSR_x
| PSR_c
},
16282 {"scf", PSR_s
| PSR_c
| PSR_f
},
16283 {"scx", PSR_s
| PSR_c
| PSR_x
},
16284 {"xfs", PSR_x
| PSR_f
| PSR_s
},
16285 {"xfc", PSR_x
| PSR_f
| PSR_c
},
16286 {"xsf", PSR_x
| PSR_s
| PSR_f
},
16287 {"xsc", PSR_x
| PSR_s
| PSR_c
},
16288 {"xcf", PSR_x
| PSR_c
| PSR_f
},
16289 {"xcs", PSR_x
| PSR_c
| PSR_s
},
16290 {"cfs", PSR_c
| PSR_f
| PSR_s
},
16291 {"cfx", PSR_c
| PSR_f
| PSR_x
},
16292 {"csf", PSR_c
| PSR_s
| PSR_f
},
16293 {"csx", PSR_c
| PSR_s
| PSR_x
},
16294 {"cxf", PSR_c
| PSR_x
| PSR_f
},
16295 {"cxs", PSR_c
| PSR_x
| PSR_s
},
16296 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
16297 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
16298 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
16299 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
16300 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
16301 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
16302 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
16303 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
16304 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16305 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16306 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16307 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16308 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16309 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16310 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16311 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16312 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16313 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16314 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16315 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16316 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16317 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16318 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16319 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16323 {"nzcvqg", PSR_s
| PSR_f
}
16326 /* Table of V7M psr names. */
16327 static const struct asm_psr v7m_psrs
[] =
16329 {"apsr", 0 }, {"APSR", 0 },
16330 {"iapsr", 1 }, {"IAPSR", 1 },
16331 {"eapsr", 2 }, {"EAPSR", 2 },
16332 {"psr", 3 }, {"PSR", 3 },
16333 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16334 {"ipsr", 5 }, {"IPSR", 5 },
16335 {"epsr", 6 }, {"EPSR", 6 },
16336 {"iepsr", 7 }, {"IEPSR", 7 },
16337 {"msp", 8 }, {"MSP", 8 },
16338 {"psp", 9 }, {"PSP", 9 },
16339 {"primask", 16}, {"PRIMASK", 16},
16340 {"basepri", 17}, {"BASEPRI", 17},
16341 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16342 {"faultmask", 19}, {"FAULTMASK", 19},
16343 {"control", 20}, {"CONTROL", 20}
16346 /* Table of all shift-in-operand names. */
16347 static const struct asm_shift_name shift_names
[] =
16349 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16350 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16351 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16352 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16353 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16354 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16357 /* Table of all explicit relocation names. */
16359 static struct reloc_entry reloc_names
[] =
16361 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16362 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16363 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16364 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16365 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16366 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16367 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16368 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16369 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16370 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16371 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
16372 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
}
16376 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16377 static const struct asm_cond conds
[] =
16381 {"cs", 0x2}, {"hs", 0x2},
16382 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16396 static struct asm_barrier_opt barrier_opt_names
[] =
16398 { "sy", 0xf }, { "SY", 0xf },
16399 { "un", 0x7 }, { "UN", 0x7 },
16400 { "st", 0xe }, { "ST", 0xe },
16401 { "unst", 0x6 }, { "UNST", 0x6 },
16402 { "ish", 0xb }, { "ISH", 0xb },
16403 { "sh", 0xb }, { "SH", 0xb },
16404 { "ishst", 0xa }, { "ISHST", 0xa },
16405 { "shst", 0xa }, { "SHST", 0xa },
16406 { "nsh", 0x7 }, { "NSH", 0x7 },
16407 { "nshst", 0x6 }, { "NSHST", 0x6 },
16408 { "osh", 0x3 }, { "OSH", 0x3 },
16409 { "oshst", 0x2 }, { "OSHST", 0x2 }
16412 /* Table of ARM-format instructions. */
16414 /* Macros for gluing together operand strings. N.B. In all cases
16415 other than OPS0, the trailing OP_stop comes from default
16416 zero-initialization of the unspecified elements of the array. */
16417 #define OPS0() { OP_stop, }
16418 #define OPS1(a) { OP_##a, }
16419 #define OPS2(a,b) { OP_##a,OP_##b, }
16420 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16421 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16422 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16423 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16425 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16426 This is useful when mixing operands for ARM and THUMB, i.e. using the
16427 MIX_ARM_THUMB_OPERANDS macro.
16428 In order to use these macros, prefix the number of operands with _
16430 #define OPS_1(a) { a, }
16431 #define OPS_2(a,b) { a,b, }
16432 #define OPS_3(a,b,c) { a,b,c, }
16433 #define OPS_4(a,b,c,d) { a,b,c,d, }
16434 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16435 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16437 /* These macros abstract out the exact format of the mnemonic table and
16438 save some repeated characters. */
16440 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16441 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16442 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16443 THUMB_VARIANT, do_##ae, do_##te }
16445 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16446 a T_MNEM_xyz enumerator. */
16447 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16448 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16449 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16450 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16452 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16453 infix after the third character. */
16454 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16455 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16456 THUMB_VARIANT, do_##ae, do_##te }
16457 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16458 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16459 THUMB_VARIANT, do_##ae, do_##te }
16460 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16461 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16462 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16463 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16464 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16465 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16466 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16467 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16469 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16470 appear in the condition table. */
16471 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16472 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16473 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16475 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16476 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16477 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16478 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16479 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16480 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16481 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16482 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16483 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16484 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16485 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16486 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16487 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16488 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16489 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16490 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16491 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16492 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16493 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16494 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16496 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16497 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16498 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16499 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16501 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16502 field is still 0xE. Many of the Thumb variants can be executed
16503 conditionally, so this is checked separately. */
16504 #define TUE(mnem, op, top, nops, ops, ae, te) \
16505 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16506 THUMB_VARIANT, do_##ae, do_##te }
16508 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16509 condition code field. */
16510 #define TUF(mnem, op, top, nops, ops, ae, te) \
16511 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16512 THUMB_VARIANT, do_##ae, do_##te }
16514 /* ARM-only variants of all the above. */
16515 #define CE(mnem, op, nops, ops, ae) \
16516 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16518 #define C3(mnem, op, nops, ops, ae) \
16519 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16521 /* Legacy mnemonics that always have conditional infix after the third
16523 #define CL(mnem, op, nops, ops, ae) \
16524 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16525 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16527 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16528 #define cCE(mnem, op, nops, ops, ae) \
16529 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16531 /* Legacy coprocessor instructions where conditional infix and conditional
16532 suffix are ambiguous. For consistency this includes all FPA instructions,
16533 not just the potentially ambiguous ones. */
16534 #define cCL(mnem, op, nops, ops, ae) \
16535 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16536 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16538 /* Coprocessor, takes either a suffix or a position-3 infix
16539 (for an FPA corner case). */
16540 #define C3E(mnem, op, nops, ops, ae) \
16541 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16542 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16544 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16545 { m1 #m2 m3, OPS##nops ops, \
16546 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16547 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16549 #define CM(m1, m2, op, nops, ops, ae) \
16550 xCM_ (m1, , m2, op, nops, ops, ae), \
16551 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16552 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16553 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16554 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16555 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16556 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16557 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16558 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16559 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16560 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16561 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16562 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16563 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16564 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16565 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16566 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16567 xCM_ (m1, le, m2, op, nops, ops, ae), \
16568 xCM_ (m1, al, m2, op, nops, ops, ae)
16570 #define UE(mnem, op, nops, ops, ae) \
16571 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16573 #define UF(mnem, op, nops, ops, ae) \
16574 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16576 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16577 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16578 use the same encoding function for each. */
16579 #define NUF(mnem, op, nops, ops, enc) \
16580 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16581 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16583 /* Neon data processing, version which indirects through neon_enc_tab for
16584 the various overloaded versions of opcodes. */
16585 #define nUF(mnem, op, nops, ops, enc) \
16586 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16587 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16589 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16591 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16592 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16593 THUMB_VARIANT, do_##enc, do_##enc }
16595 #define NCE(mnem, op, nops, ops, enc) \
16596 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16598 #define NCEF(mnem, op, nops, ops, enc) \
16599 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16601 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16602 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16603 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
16604 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16606 #define nCE(mnem, op, nops, ops, enc) \
16607 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16609 #define nCEF(mnem, op, nops, ops, enc) \
16610 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16614 static const struct asm_opcode insns
[] =
16616 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16617 #define THUMB_VARIANT &arm_ext_v4t
16618 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16619 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16620 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16621 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16622 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16623 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16624 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16625 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16626 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16627 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16628 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16629 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16630 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16631 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16632 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16633 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16635 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16636 for setting PSR flag bits. They are obsolete in V6 and do not
16637 have Thumb equivalents. */
16638 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16639 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16640 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
16641 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16642 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16643 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
16644 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16645 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16646 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
16648 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16649 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16650 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16651 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16653 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16654 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16655 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
16657 OP_ADDRGLDR
),ldst
, t_ldst
),
16658 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16660 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16661 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16662 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16663 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16664 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16665 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16667 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16668 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16669 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
16670 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
16673 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
16674 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
16675 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
16677 /* Thumb-compatibility pseudo ops. */
16678 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16679 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16680 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16681 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16682 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16683 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16684 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16685 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16686 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
16687 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
16688 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
16689 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
16691 /* These may simplify to neg. */
16692 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16693 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16695 #undef THUMB_VARIANT
16696 #define THUMB_VARIANT & arm_ext_v6
16698 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
16700 /* V1 instructions with no Thumb analogue prior to V6T2. */
16701 #undef THUMB_VARIANT
16702 #define THUMB_VARIANT & arm_ext_v6t2
16704 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16705 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16706 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
16708 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16709 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16710 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
16711 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16713 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16714 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16716 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16717 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16719 /* V1 instructions with no Thumb analogue at all. */
16720 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
16721 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
16723 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16724 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16725 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16726 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16727 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16728 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16729 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16730 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16733 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
16734 #undef THUMB_VARIANT
16735 #define THUMB_VARIANT & arm_ext_v4t
16737 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16738 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16740 #undef THUMB_VARIANT
16741 #define THUMB_VARIANT & arm_ext_v6t2
16743 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16744 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
16746 /* Generic coprocessor instructions. */
16747 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16748 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16749 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16750 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16751 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16752 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16753 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16756 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
16758 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16759 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16762 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
16763 #undef THUMB_VARIANT
16764 #define THUMB_VARIANT & arm_ext_msr
16766 TCE("mrs", 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
16767 TCE("msr", 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
16770 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
16771 #undef THUMB_VARIANT
16772 #define THUMB_VARIANT & arm_ext_v6t2
16774 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16775 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16776 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16777 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16778 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16779 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16780 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16781 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16784 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
16785 #undef THUMB_VARIANT
16786 #define THUMB_VARIANT & arm_ext_v4t
16788 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16789 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16790 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16791 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16792 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16793 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16796 #define ARM_VARIANT & arm_ext_v4t_5
16798 /* ARM Architecture 4T. */
16799 /* Note: bx (and blx) are required on V5, even if the processor does
16800 not support Thumb. */
16801 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
16804 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
16805 #undef THUMB_VARIANT
16806 #define THUMB_VARIANT & arm_ext_v5t
16808 /* Note: blx has 2 variants; the .value coded here is for
16809 BLX(2). Only this variant has conditional execution. */
16810 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
16811 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
16813 #undef THUMB_VARIANT
16814 #define THUMB_VARIANT & arm_ext_v6t2
16816 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
16817 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16818 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16819 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16820 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16821 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16822 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16823 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16826 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
16827 #undef THUMB_VARIANT
16828 #define THUMB_VARIANT &arm_ext_v5exp
16830 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16831 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16832 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16833 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16835 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16836 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16838 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16839 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16840 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16841 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16843 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16844 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16845 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16846 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16848 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16849 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16851 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16852 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16853 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16854 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16857 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
16858 #undef THUMB_VARIANT
16859 #define THUMB_VARIANT &arm_ext_v6t2
16861 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
16862 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
16864 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
16865 ADDRGLDRS
), ldrd
, t_ldstd
),
16867 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16868 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16871 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
16873 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
16876 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
16877 #undef THUMB_VARIANT
16878 #define THUMB_VARIANT & arm_ext_v6
16880 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16881 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16882 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16883 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16884 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16885 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16886 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16887 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16888 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16889 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
16891 #undef THUMB_VARIANT
16892 #define THUMB_VARIANT & arm_ext_v6t2
16894 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
16895 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16897 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16898 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16900 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
16901 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
16903 /* ARM V6 not included in V7M. */
16904 #undef THUMB_VARIANT
16905 #define THUMB_VARIANT & arm_ext_v6_notm
16906 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16907 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
16908 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
16909 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16910 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16911 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
16912 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
16913 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16914 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
16915 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
16916 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
16917 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
16919 /* ARM V6 not included in V7M (eg. integer SIMD). */
16920 #undef THUMB_VARIANT
16921 #define THUMB_VARIANT & arm_ext_v6_dsp
16922 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
16923 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
16924 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
16925 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16926 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16927 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16928 /* Old name for QASX. */
16929 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16930 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16931 /* Old name for QSAX. */
16932 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16933 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16934 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16935 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16936 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16937 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16938 /* Old name for SASX. */
16939 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16940 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16941 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16942 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16943 /* Old name for SHASX. */
16944 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16945 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16946 /* Old name for SHSAX. */
16947 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16948 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16949 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16950 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16951 /* Old name for SSAX. */
16952 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16953 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16954 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16955 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16956 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16957 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16958 /* Old name for UASX. */
16959 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16960 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16961 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16962 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16963 /* Old name for UHASX. */
16964 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16965 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16966 /* Old name for UHSAX. */
16967 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16968 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16969 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16970 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16971 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16972 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16973 /* Old name for UQASX. */
16974 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16975 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16976 /* Old name for UQSAX. */
16977 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16978 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16979 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16980 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16981 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16982 /* Old name for USAX. */
16983 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16984 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16985 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16986 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16987 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16988 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16989 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16990 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16991 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16992 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16993 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16994 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16995 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16996 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16997 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16998 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16999 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17000 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17001 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17002 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17003 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17004 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17005 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17006 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17007 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17008 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17009 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17010 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17011 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17012 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
17013 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
17014 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17015 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17016 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
17019 #define ARM_VARIANT & arm_ext_v6k
17020 #undef THUMB_VARIANT
17021 #define THUMB_VARIANT & arm_ext_v6k
17023 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
17024 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
17025 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
17026 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
17028 #undef THUMB_VARIANT
17029 #define THUMB_VARIANT & arm_ext_v6_notm
17030 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
17032 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
17033 RRnpcb
), strexd
, t_strexd
),
17035 #undef THUMB_VARIANT
17036 #define THUMB_VARIANT & arm_ext_v6t2
17037 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
17039 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
17041 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17043 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17045 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
17048 #define ARM_VARIANT & arm_ext_v6z
17050 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
17053 #define ARM_VARIANT & arm_ext_v6t2
17055 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
17056 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
17057 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17058 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17060 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17061 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17062 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17063 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
17065 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17066 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17067 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17068 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17070 /* Thumb-only instructions. */
17072 #define ARM_VARIANT NULL
17073 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
17074 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
17076 /* ARM does not really have an IT instruction, so always allow it.
17077 The opcode is copied from Thumb in order to allow warnings in
17078 -mimplicit-it=[never | arm] modes. */
17080 #define ARM_VARIANT & arm_ext_v1
17082 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
17083 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
17084 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
17085 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
17086 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
17087 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
17088 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
17089 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
17090 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
17091 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
17092 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
17093 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
17094 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
17095 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
17096 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
17097 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17098 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17099 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17101 /* Thumb2 only instructions. */
17103 #define ARM_VARIANT NULL
17105 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17106 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17107 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17108 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17109 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
17110 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
17112 /* Thumb-2 hardware division instructions (R and M profiles only). */
17113 #undef THUMB_VARIANT
17114 #define THUMB_VARIANT & arm_ext_div
17116 TCE("sdiv", 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
17117 TCE("udiv", 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
17119 /* ARM V6M/V7 instructions. */
17121 #define ARM_VARIANT & arm_ext_barrier
17122 #undef THUMB_VARIANT
17123 #define THUMB_VARIANT & arm_ext_barrier
17125 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17126 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17127 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17129 /* ARM V7 instructions. */
17131 #define ARM_VARIANT & arm_ext_v7
17132 #undef THUMB_VARIANT
17133 #define THUMB_VARIANT & arm_ext_v7
17135 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
17136 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
17139 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17141 cCE("wfs", e200110
, 1, (RR
), rd
),
17142 cCE("rfs", e300110
, 1, (RR
), rd
),
17143 cCE("wfc", e400110
, 1, (RR
), rd
),
17144 cCE("rfc", e500110
, 1, (RR
), rd
),
17146 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17147 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17148 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17149 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17151 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17152 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17153 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17154 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17156 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
17157 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
17158 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
17159 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
17160 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
17161 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
17162 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
17163 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
17164 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
17165 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
17166 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
17167 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
17169 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
17170 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
17171 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
17172 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
17173 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
17174 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
17175 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
17176 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
17177 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
17178 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
17179 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
17180 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
17182 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
17183 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
17184 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
17185 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
17186 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
17187 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
17188 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
17189 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
17190 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
17191 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
17192 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
17193 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
17195 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
17196 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
17197 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
17198 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
17199 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
17200 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
17201 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
17202 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
17203 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
17204 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
17205 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
17206 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
17208 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
17209 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
17210 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
17211 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
17212 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
17213 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
17214 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
17215 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
17216 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
17217 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
17218 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
17219 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
17221 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
17222 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
17223 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
17224 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
17225 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
17226 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
17227 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
17228 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
17229 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
17230 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
17231 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
17232 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
17234 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
17235 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
17236 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
17237 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
17238 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
17239 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
17240 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
17241 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
17242 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
17243 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
17244 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
17245 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
17247 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
17248 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
17249 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
17250 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
17251 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
17252 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
17253 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
17254 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
17255 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
17256 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
17257 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
17258 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
17260 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
17261 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
17262 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
17263 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
17264 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
17265 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
17266 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
17267 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
17268 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
17269 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
17270 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
17271 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
17273 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
17274 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
17275 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
17276 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
17277 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
17278 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
17279 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
17280 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
17281 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
17282 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
17283 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
17284 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
17286 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
17287 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
17288 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
17289 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
17290 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
17291 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
17292 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
17293 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
17294 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
17295 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
17296 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
17297 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
17299 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
17300 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
17301 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
17302 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
17303 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
17304 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
17305 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
17306 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
17307 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
17308 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
17309 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
17310 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
17312 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
17313 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
17314 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
17315 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
17316 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
17317 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
17318 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
17319 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
17320 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
17321 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
17322 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
17323 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
17325 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
17326 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
17327 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
17328 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
17329 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
17330 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
17331 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
17332 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
17333 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
17334 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
17335 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
17336 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
17338 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17339 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17340 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17341 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17342 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17343 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17344 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17345 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17346 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17347 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17348 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17349 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17351 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17352 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17353 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17354 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17355 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17356 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17357 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17358 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17359 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17360 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17361 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17362 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17364 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17365 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17366 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17367 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17368 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17369 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17370 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17371 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17372 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17373 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17374 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17375 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17377 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17378 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17379 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17380 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17381 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17382 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17383 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17384 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17385 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17386 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17387 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17388 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17390 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17391 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17392 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17393 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17394 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17395 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17396 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17397 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17398 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17399 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17400 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17401 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17403 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17404 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17405 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17406 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17407 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17408 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17409 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17410 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17411 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17412 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17413 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17414 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17416 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17417 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17418 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17419 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17420 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17421 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17422 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17423 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17424 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17425 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17426 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17427 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17429 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17430 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17431 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17432 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17433 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17434 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17435 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17436 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17437 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17438 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17439 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17440 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17442 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17443 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17444 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17445 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17446 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17447 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17448 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17449 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17450 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17451 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17452 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17453 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17455 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17456 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17457 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17458 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17459 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17460 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17461 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17462 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17463 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17464 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17465 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17466 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17468 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17469 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17470 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17471 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17472 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17473 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17474 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17475 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17476 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17477 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17478 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17479 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17481 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17482 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17483 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17484 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17485 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17486 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17487 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17488 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17489 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17490 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17491 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17492 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17494 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17495 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17496 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17497 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17498 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17499 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17500 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17501 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17502 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17503 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17504 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17505 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17507 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17508 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17509 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17510 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17511 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17512 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17513 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17514 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17515 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17516 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17517 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17518 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17520 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17521 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17522 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17523 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17524 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17525 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17526 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17527 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17528 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17529 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17530 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17531 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17533 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17534 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17535 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17536 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17538 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17539 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17540 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17541 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17542 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17543 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17544 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17545 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17546 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17547 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17548 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17549 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17551 /* The implementation of the FIX instruction is broken on some
17552 assemblers, in that it accepts a precision specifier as well as a
17553 rounding specifier, despite the fact that this is meaningless.
17554 To be more compatible, we accept it as well, though of course it
17555 does not set any bits. */
17556 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17557 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17558 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17559 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17560 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17561 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
17562 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
17563 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
17564 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
17565 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
17566 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
17567 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
17568 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
17570 /* Instructions that were new with the real FPA, call them V2. */
17572 #define ARM_VARIANT & fpu_fpa_ext_v2
17574 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17575 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17576 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17577 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17578 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17579 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17582 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17584 /* Moves and type conversions. */
17585 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17586 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17587 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17588 cCE("fmstat", ef1fa10
, 0, (), noargs
),
17589 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
17590 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
17591 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17592 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17593 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17594 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17595 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17596 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17597 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
17598 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
17600 /* Memory operations. */
17601 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17602 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17603 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17604 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17605 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17606 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17607 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17608 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17609 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17610 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17611 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17612 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17613 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17614 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17615 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17616 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17617 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17618 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17620 /* Monadic operations. */
17621 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17622 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17623 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17625 /* Dyadic operations. */
17626 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17627 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17628 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17629 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17630 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17631 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17632 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17633 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17634 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17637 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17638 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17639 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17640 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17642 /* Double precision load/store are still present on single precision
17643 implementations. */
17644 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17645 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17646 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17647 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17648 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17649 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17650 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17651 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17652 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17653 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17656 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17658 /* Moves and type conversions. */
17659 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17660 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17661 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17662 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17663 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17664 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17665 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17666 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17667 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17668 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17669 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17670 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17671 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17673 /* Monadic operations. */
17674 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17675 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17676 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17678 /* Dyadic operations. */
17679 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17680 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17681 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17682 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17683 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17684 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17685 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17686 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17687 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17690 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17691 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
17692 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17693 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
17696 #define ARM_VARIANT & fpu_vfp_ext_v2
17698 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
17699 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
17700 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
17701 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
17703 /* Instructions which may belong to either the Neon or VFP instruction sets.
17704 Individual encoder functions perform additional architecture checks. */
17706 #define ARM_VARIANT & fpu_vfp_ext_v1xd
17707 #undef THUMB_VARIANT
17708 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
17710 /* These mnemonics are unique to VFP. */
17711 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
17712 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
17713 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17714 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17715 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17716 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17717 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17718 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
17719 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
17720 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
17722 /* Mnemonics shared by Neon and VFP. */
17723 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
17724 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17725 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17727 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17728 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17730 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17731 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17733 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17734 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17735 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17736 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17737 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17738 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17739 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17740 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17742 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
17743 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
17744 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
17745 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
17748 /* NOTE: All VMOV encoding is special-cased! */
17749 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
17750 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
17752 #undef THUMB_VARIANT
17753 #define THUMB_VARIANT & fpu_neon_ext_v1
17755 #define ARM_VARIANT & fpu_neon_ext_v1
17757 /* Data processing with three registers of the same length. */
17758 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
17759 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
17760 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
17761 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17762 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17763 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17764 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17765 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17766 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17767 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
17768 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17769 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17770 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17771 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17772 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17773 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17774 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17775 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17776 /* If not immediate, fall back to neon_dyadic_i64_su.
17777 shl_imm should accept I8 I16 I32 I64,
17778 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
17779 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
17780 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
17781 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
17782 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
17783 /* Logic ops, types optional & ignored. */
17784 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17785 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17786 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17787 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17788 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17789 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17790 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17791 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17792 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
17793 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
17794 /* Bitfield ops, untyped. */
17795 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17796 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17797 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17798 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17799 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17800 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17801 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
17802 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17803 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17804 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17805 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17806 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17807 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17808 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
17809 back to neon_dyadic_if_su. */
17810 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17811 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17812 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17813 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17814 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17815 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17816 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17817 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17818 /* Comparison. Type I8 I16 I32 F32. */
17819 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
17820 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
17821 /* As above, D registers only. */
17822 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17823 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17824 /* Int and float variants, signedness unimportant. */
17825 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17826 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17827 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
17828 /* Add/sub take types I8 I16 I32 I64 F32. */
17829 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17830 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17831 /* vtst takes sizes 8, 16, 32. */
17832 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
17833 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
17834 /* VMUL takes I8 I16 I32 F32 P8. */
17835 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
17836 /* VQD{R}MULH takes S16 S32. */
17837 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17838 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17839 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17840 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17841 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17842 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17843 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17844 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17845 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17846 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17847 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17848 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17849 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17850 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17851 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17852 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17854 /* Two address, int/float. Types S8 S16 S32 F32. */
17855 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17856 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17858 /* Data processing with two registers and a shift amount. */
17859 /* Right shifts, and variants with rounding.
17860 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
17861 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17862 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17863 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17864 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17865 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17866 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17867 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17868 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17869 /* Shift and insert. Sizes accepted 8 16 32 64. */
17870 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
17871 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
17872 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
17873 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
17874 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
17875 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
17876 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
17877 /* Right shift immediate, saturating & narrowing, with rounding variants.
17878 Types accepted S16 S32 S64 U16 U32 U64. */
17879 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17880 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17881 /* As above, unsigned. Types accepted S16 S32 S64. */
17882 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17883 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17884 /* Right shift narrowing. Types accepted I16 I32 I64. */
17885 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17886 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17887 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
17888 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
17889 /* CVT with optional immediate for fixed-point variant. */
17890 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
17892 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
17893 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
17895 /* Data processing, three registers of different lengths. */
17896 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
17897 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
17898 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17899 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17900 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17901 /* If not scalar, fall back to neon_dyadic_long.
17902 Vector types as above, scalar types S16 S32 U16 U32. */
17903 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17904 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17905 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
17906 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17907 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17908 /* Dyadic, narrowing insns. Types I16 I32 I64. */
17909 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17910 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17911 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17912 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17913 /* Saturating doubling multiplies. Types S16 S32. */
17914 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17915 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17916 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17917 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
17918 S16 S32 U16 U32. */
17919 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
17921 /* Extract. Size 8. */
17922 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
17923 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
17925 /* Two registers, miscellaneous. */
17926 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
17927 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
17928 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
17929 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
17930 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
17931 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
17932 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
17933 /* Vector replicate. Sizes 8 16 32. */
17934 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
17935 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
17936 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
17937 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
17938 /* VMOVN. Types I16 I32 I64. */
17939 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
17940 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
17941 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
17942 /* VQMOVUN. Types S16 S32 S64. */
17943 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
17944 /* VZIP / VUZP. Sizes 8 16 32. */
17945 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17946 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17947 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17948 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17949 /* VQABS / VQNEG. Types S8 S16 S32. */
17950 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17951 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17952 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17953 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17954 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
17955 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17956 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
17957 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17958 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
17959 /* Reciprocal estimates. Types U32 F32. */
17960 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17961 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
17962 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17963 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
17964 /* VCLS. Types S8 S16 S32. */
17965 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
17966 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
17967 /* VCLZ. Types I8 I16 I32. */
17968 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
17969 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
17970 /* VCNT. Size 8. */
17971 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
17972 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
17973 /* Two address, untyped. */
17974 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
17975 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
17976 /* VTRN. Sizes 8 16 32. */
17977 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
17978 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
17980 /* Table lookup. Size 8. */
17981 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17982 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17984 #undef THUMB_VARIANT
17985 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
17987 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
17989 /* Neon element/structure load/store. */
17990 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17991 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17992 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17993 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17994 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17995 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17996 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17997 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17999 #undef THUMB_VARIANT
18000 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18002 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18003 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
18004 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18005 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18006 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18007 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18008 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18009 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18010 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18011 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18013 #undef THUMB_VARIANT
18014 #define THUMB_VARIANT & fpu_vfp_ext_v3
18016 #define ARM_VARIANT & fpu_vfp_ext_v3
18018 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
18019 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18020 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18021 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18022 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18023 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18024 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18025 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18026 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18029 #define ARM_VARIANT &fpu_vfp_ext_fma
18030 #undef THUMB_VARIANT
18031 #define THUMB_VARIANT &fpu_vfp_ext_fma
18032 /* Mnemonics shared by Neon and VFP. These are included in the
18033 VFP FMA variant; NEON and VFP FMA always includes the NEON
18034 FMA instructions. */
18035 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18036 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18037 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18038 the v form should always be used. */
18039 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18040 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18041 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18042 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18043 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18044 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18046 #undef THUMB_VARIANT
18048 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18050 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18051 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18052 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18053 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18054 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18055 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18056 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
18057 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
18060 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18062 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
18063 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
18064 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
18065 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
18066 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
18067 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
18068 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
18069 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
18070 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
18071 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18072 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18073 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18074 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18075 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18076 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18077 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18078 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18079 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18080 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
18081 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
18082 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18083 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18084 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18085 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18086 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18087 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18088 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
18089 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
18090 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
18091 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
18092 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
18093 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
18094 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
18095 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
18096 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18097 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18098 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18099 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18100 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18101 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18102 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18103 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18104 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18105 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18106 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18107 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18108 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
18109 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18110 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18111 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18112 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18113 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18114 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18115 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18116 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18117 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18118 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18119 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18120 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18121 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18122 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18123 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18124 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18125 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18126 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18127 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18128 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18129 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18130 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18131 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18132 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18133 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18134 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18135 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18136 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18137 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18138 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18139 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18140 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18141 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18142 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18143 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18144 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18145 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18146 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18147 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18148 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18149 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18150 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
18151 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18152 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18153 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18154 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18155 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18156 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18157 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18158 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18159 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18160 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18161 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18162 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18163 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18164 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18165 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18166 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18167 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18168 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18169 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18170 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18171 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18172 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
18173 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18174 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18175 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18176 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18177 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18178 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18179 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18180 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18181 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18182 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18183 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18184 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18185 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18186 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18187 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18188 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18189 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18190 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18191 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18192 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18193 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18194 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18195 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18196 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18197 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18198 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18199 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18200 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18201 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18202 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18203 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18204 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18205 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18206 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18207 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18208 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18209 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18210 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18211 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18212 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18213 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18214 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18215 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18216 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18217 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18218 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18219 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18220 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18221 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18222 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18223 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
18226 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18228 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
18229 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
18230 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
18231 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18232 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18233 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18234 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18235 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18236 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18237 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18238 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18239 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18240 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18241 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18242 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18243 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18244 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18245 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18246 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18247 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18248 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
18249 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18250 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18251 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18252 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18253 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18254 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18255 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18256 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18257 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18258 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18259 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18260 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18261 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18262 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18263 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18264 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18265 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18266 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18267 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18268 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18269 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18270 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18271 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18272 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18273 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18274 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18275 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18276 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18277 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18278 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18279 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18280 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18281 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18282 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18283 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18284 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18287 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18289 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18290 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18291 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18292 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18293 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18294 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18295 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18296 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18297 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
18298 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
18299 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
18300 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
18301 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
18302 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
18303 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
18304 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
18305 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
18306 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
18307 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
18308 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
18309 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
18310 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
18311 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
18312 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
18313 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
18314 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
18315 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
18316 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
18317 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
18318 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
18319 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
18320 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
18321 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
18322 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
18323 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
18324 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
18325 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
18326 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
18327 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
18328 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
18329 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
18330 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
18331 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
18332 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
18333 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
18334 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
18335 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
18336 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
18337 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
18338 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
18339 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18340 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18341 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18342 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18343 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18344 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18345 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18346 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18347 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18348 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18349 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18350 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18351 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18352 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18353 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18354 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18355 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18356 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18357 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18358 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18359 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18360 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18361 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18362 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18363 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18364 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18367 #undef THUMB_VARIANT
18394 /* MD interface: bits in the object file. */
18396 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18397 for use in the a.out file, and stores them in the array pointed to by buf.
18398 This knows about the endian-ness of the target machine and does
18399 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18400 2 (short) and 4 (long) Floating numbers are put out as a series of
18401 LITTLENUMS (shorts, here at least). */
18404 md_number_to_chars (char * buf
, valueT val
, int n
)
18406 if (target_big_endian
)
18407 number_to_chars_bigendian (buf
, val
, n
);
18409 number_to_chars_littleendian (buf
, val
, n
);
18413 md_chars_to_number (char * buf
, int n
)
18416 unsigned char * where
= (unsigned char *) buf
;
18418 if (target_big_endian
)
18423 result
|= (*where
++ & 255);
18431 result
|= (where
[n
] & 255);
18438 /* MD interface: Sections. */
18440 /* Estimate the size of a frag before relaxing. Assume everything fits in
18444 md_estimate_size_before_relax (fragS
* fragp
,
18445 segT segtype ATTRIBUTE_UNUSED
)
18451 /* Convert a machine dependent frag. */
18454 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18456 unsigned long insn
;
18457 unsigned long old_op
;
18465 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18467 old_op
= bfd_get_16(abfd
, buf
);
18468 if (fragp
->fr_symbol
)
18470 exp
.X_op
= O_symbol
;
18471 exp
.X_add_symbol
= fragp
->fr_symbol
;
18475 exp
.X_op
= O_constant
;
18477 exp
.X_add_number
= fragp
->fr_offset
;
18478 opcode
= fragp
->fr_subtype
;
18481 case T_MNEM_ldr_pc
:
18482 case T_MNEM_ldr_pc2
:
18483 case T_MNEM_ldr_sp
:
18484 case T_MNEM_str_sp
:
18491 if (fragp
->fr_var
== 4)
18493 insn
= THUMB_OP32 (opcode
);
18494 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18496 insn
|= (old_op
& 0x700) << 4;
18500 insn
|= (old_op
& 7) << 12;
18501 insn
|= (old_op
& 0x38) << 13;
18503 insn
|= 0x00000c00;
18504 put_thumb32_insn (buf
, insn
);
18505 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18509 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18511 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18514 if (fragp
->fr_var
== 4)
18516 insn
= THUMB_OP32 (opcode
);
18517 insn
|= (old_op
& 0xf0) << 4;
18518 put_thumb32_insn (buf
, insn
);
18519 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18523 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18524 exp
.X_add_number
-= 4;
18532 if (fragp
->fr_var
== 4)
18534 int r0off
= (opcode
== T_MNEM_mov
18535 || opcode
== T_MNEM_movs
) ? 0 : 8;
18536 insn
= THUMB_OP32 (opcode
);
18537 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18538 insn
|= (old_op
& 0x700) << r0off
;
18539 put_thumb32_insn (buf
, insn
);
18540 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18544 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18549 if (fragp
->fr_var
== 4)
18551 insn
= THUMB_OP32(opcode
);
18552 put_thumb32_insn (buf
, insn
);
18553 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18556 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18560 if (fragp
->fr_var
== 4)
18562 insn
= THUMB_OP32(opcode
);
18563 insn
|= (old_op
& 0xf00) << 14;
18564 put_thumb32_insn (buf
, insn
);
18565 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18568 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18571 case T_MNEM_add_sp
:
18572 case T_MNEM_add_pc
:
18573 case T_MNEM_inc_sp
:
18574 case T_MNEM_dec_sp
:
18575 if (fragp
->fr_var
== 4)
18577 /* ??? Choose between add and addw. */
18578 insn
= THUMB_OP32 (opcode
);
18579 insn
|= (old_op
& 0xf0) << 4;
18580 put_thumb32_insn (buf
, insn
);
18581 if (opcode
== T_MNEM_add_pc
)
18582 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18584 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18587 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18595 if (fragp
->fr_var
== 4)
18597 insn
= THUMB_OP32 (opcode
);
18598 insn
|= (old_op
& 0xf0) << 4;
18599 insn
|= (old_op
& 0xf) << 16;
18600 put_thumb32_insn (buf
, insn
);
18601 if (insn
& (1 << 20))
18602 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18604 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18607 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18613 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18614 (enum bfd_reloc_code_real
) reloc_type
);
18615 fixp
->fx_file
= fragp
->fr_file
;
18616 fixp
->fx_line
= fragp
->fr_line
;
18617 fragp
->fr_fix
+= fragp
->fr_var
;
18620 /* Return the size of a relaxable immediate operand instruction.
18621 SHIFT and SIZE specify the form of the allowable immediate. */
18623 relax_immediate (fragS
*fragp
, int size
, int shift
)
18629 /* ??? Should be able to do better than this. */
18630 if (fragp
->fr_symbol
)
18633 low
= (1 << shift
) - 1;
18634 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18635 offset
= fragp
->fr_offset
;
18636 /* Force misaligned offsets to 32-bit variant. */
18639 if (offset
& ~mask
)
18644 /* Get the address of a symbol during relaxation. */
18646 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
18652 sym
= fragp
->fr_symbol
;
18653 sym_frag
= symbol_get_frag (sym
);
18654 know (S_GET_SEGMENT (sym
) != absolute_section
18655 || sym_frag
== &zero_address_frag
);
18656 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
18658 /* If frag has yet to be reached on this pass, assume it will
18659 move by STRETCH just as we did. If this is not so, it will
18660 be because some frag between grows, and that will force
18664 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
18668 /* Adjust stretch for any alignment frag. Note that if have
18669 been expanding the earlier code, the symbol may be
18670 defined in what appears to be an earlier frag. FIXME:
18671 This doesn't handle the fr_subtype field, which specifies
18672 a maximum number of bytes to skip when doing an
18674 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
18676 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
18679 stretch
= - ((- stretch
)
18680 & ~ ((1 << (int) f
->fr_offset
) - 1));
18682 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
18694 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
18697 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
18702 /* Assume worst case for symbols not known to be in the same section. */
18703 if (fragp
->fr_symbol
== NULL
18704 || !S_IS_DEFINED (fragp
->fr_symbol
)
18705 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18706 || S_IS_WEAK (fragp
->fr_symbol
))
18709 val
= relaxed_symbol_addr (fragp
, stretch
);
18710 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18711 addr
= (addr
+ 4) & ~3;
18712 /* Force misaligned targets to 32-bit variant. */
18716 if (val
< 0 || val
> 1020)
18721 /* Return the size of a relaxable add/sub immediate instruction. */
18723 relax_addsub (fragS
*fragp
, asection
*sec
)
18728 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18729 op
= bfd_get_16(sec
->owner
, buf
);
18730 if ((op
& 0xf) == ((op
>> 4) & 0xf))
18731 return relax_immediate (fragp
, 8, 0);
18733 return relax_immediate (fragp
, 3, 0);
18737 /* Return the size of a relaxable branch instruction. BITS is the
18738 size of the offset field in the narrow instruction. */
18741 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
18747 /* Assume worst case for symbols not known to be in the same section. */
18748 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18749 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18750 || S_IS_WEAK (fragp
->fr_symbol
))
18754 if (S_IS_DEFINED (fragp
->fr_symbol
)
18755 && ARM_IS_FUNC (fragp
->fr_symbol
))
18759 val
= relaxed_symbol_addr (fragp
, stretch
);
18760 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18763 /* Offset is a signed value *2 */
18765 if (val
>= limit
|| val
< -limit
)
18771 /* Relax a machine dependent frag. This returns the amount by which
18772 the current size of the frag should change. */
18775 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18780 oldsize
= fragp
->fr_var
;
18781 switch (fragp
->fr_subtype
)
18783 case T_MNEM_ldr_pc2
:
18784 newsize
= relax_adr (fragp
, sec
, stretch
);
18786 case T_MNEM_ldr_pc
:
18787 case T_MNEM_ldr_sp
:
18788 case T_MNEM_str_sp
:
18789 newsize
= relax_immediate (fragp
, 8, 2);
18793 newsize
= relax_immediate (fragp
, 5, 2);
18797 newsize
= relax_immediate (fragp
, 5, 1);
18801 newsize
= relax_immediate (fragp
, 5, 0);
18804 newsize
= relax_adr (fragp
, sec
, stretch
);
18810 newsize
= relax_immediate (fragp
, 8, 0);
18813 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
18816 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
18818 case T_MNEM_add_sp
:
18819 case T_MNEM_add_pc
:
18820 newsize
= relax_immediate (fragp
, 8, 2);
18822 case T_MNEM_inc_sp
:
18823 case T_MNEM_dec_sp
:
18824 newsize
= relax_immediate (fragp
, 7, 2);
18830 newsize
= relax_addsub (fragp
, sec
);
18836 fragp
->fr_var
= newsize
;
18837 /* Freeze wide instructions that are at or before the same location as
18838 in the previous pass. This avoids infinite loops.
18839 Don't freeze them unconditionally because targets may be artificially
18840 misaligned by the expansion of preceding frags. */
18841 if (stretch
<= 0 && newsize
> 2)
18843 md_convert_frag (sec
->owner
, sec
, fragp
);
18847 return newsize
- oldsize
;
18850 /* Round up a section size to the appropriate boundary. */
18853 md_section_align (segT segment ATTRIBUTE_UNUSED
,
18856 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
18857 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
18859 /* For a.out, force the section size to be aligned. If we don't do
18860 this, BFD will align it for us, but it will not write out the
18861 final bytes of the section. This may be a bug in BFD, but it is
18862 easier to fix it here since that is how the other a.out targets
18866 align
= bfd_get_section_alignment (stdoutput
, segment
);
18867 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
18874 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
18875 of an rs_align_code fragment. */
18878 arm_handle_align (fragS
* fragP
)
18880 static char const arm_noop
[2][2][4] =
18883 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
18884 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
18887 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
18888 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
18891 static char const thumb_noop
[2][2][2] =
18894 {0xc0, 0x46}, /* LE */
18895 {0x46, 0xc0}, /* BE */
18898 {0x00, 0xbf}, /* LE */
18899 {0xbf, 0x00} /* BE */
18902 static char const wide_thumb_noop
[2][4] =
18903 { /* Wide Thumb-2 */
18904 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
18905 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
18908 unsigned bytes
, fix
, noop_size
;
18911 const char *narrow_noop
= NULL
;
18916 if (fragP
->fr_type
!= rs_align_code
)
18919 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
18920 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
18923 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18924 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
18926 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
18928 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
18930 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
18932 narrow_noop
= thumb_noop
[1][target_big_endian
];
18933 noop
= wide_thumb_noop
[target_big_endian
];
18936 noop
= thumb_noop
[0][target_big_endian
];
18944 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
18945 [target_big_endian
];
18952 fragP
->fr_var
= noop_size
;
18954 if (bytes
& (noop_size
- 1))
18956 fix
= bytes
& (noop_size
- 1);
18958 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
18960 memset (p
, 0, fix
);
18967 if (bytes
& noop_size
)
18969 /* Insert a narrow noop. */
18970 memcpy (p
, narrow_noop
, noop_size
);
18972 bytes
-= noop_size
;
18976 /* Use wide noops for the remainder */
18980 while (bytes
>= noop_size
)
18982 memcpy (p
, noop
, noop_size
);
18984 bytes
-= noop_size
;
18988 fragP
->fr_fix
+= fix
;
18991 /* Called from md_do_align. Used to create an alignment
18992 frag in a code section. */
18995 arm_frag_align_code (int n
, int max
)
18999 /* We assume that there will never be a requirement
19000 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19001 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19006 _("alignments greater than %d bytes not supported in .text sections."),
19007 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
19008 as_fatal ("%s", err_msg
);
19011 p
= frag_var (rs_align_code
,
19012 MAX_MEM_FOR_RS_ALIGN_CODE
,
19014 (relax_substateT
) max
,
19021 /* Perform target specific initialisation of a frag.
19022 Note - despite the name this initialisation is not done when the frag
19023 is created, but only when its type is assigned. A frag can be created
19024 and used a long time before its type is set, so beware of assuming that
19025 this initialisationis performed first. */
19029 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
19031 /* Record whether this frag is in an ARM or a THUMB area. */
19032 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19035 #else /* OBJ_ELF is defined. */
19037 arm_init_frag (fragS
* fragP
, int max_chars
)
19039 /* If the current ARM vs THUMB mode has not already
19040 been recorded into this frag then do so now. */
19041 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
19043 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19045 /* Record a mapping symbol for alignment frags. We will delete this
19046 later if the alignment ends up empty. */
19047 switch (fragP
->fr_type
)
19050 case rs_align_test
:
19052 mapping_state_2 (MAP_DATA
, max_chars
);
19054 case rs_align_code
:
19055 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
19063 /* When we change sections we need to issue a new mapping symbol. */
19066 arm_elf_change_section (void)
19068 /* Link an unlinked unwind index table section to the .text section. */
19069 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
19070 && elf_linked_to_section (now_seg
) == NULL
)
19071 elf_linked_to_section (now_seg
) = text_section
;
19075 arm_elf_section_type (const char * str
, size_t len
)
19077 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
19078 return SHT_ARM_EXIDX
;
19083 /* Code to deal with unwinding tables. */
19085 static void add_unwind_adjustsp (offsetT
);
19087 /* Generate any deferred unwind frame offset. */
19090 flush_pending_unwind (void)
19094 offset
= unwind
.pending_offset
;
19095 unwind
.pending_offset
= 0;
19097 add_unwind_adjustsp (offset
);
19100 /* Add an opcode to this list for this function. Two-byte opcodes should
19101 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19105 add_unwind_opcode (valueT op
, int length
)
19107 /* Add any deferred stack adjustment. */
19108 if (unwind
.pending_offset
)
19109 flush_pending_unwind ();
19111 unwind
.sp_restored
= 0;
19113 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
19115 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
19116 if (unwind
.opcodes
)
19117 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
19118 unwind
.opcode_alloc
);
19120 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
19125 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
19127 unwind
.opcode_count
++;
19131 /* Add unwind opcodes to adjust the stack pointer. */
19134 add_unwind_adjustsp (offsetT offset
)
19138 if (offset
> 0x200)
19140 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19145 /* Long form: 0xb2, uleb128. */
19146 /* This might not fit in a word so add the individual bytes,
19147 remembering the list is built in reverse order. */
19148 o
= (valueT
) ((offset
- 0x204) >> 2);
19150 add_unwind_opcode (0, 1);
19152 /* Calculate the uleb128 encoding of the offset. */
19156 bytes
[n
] = o
& 0x7f;
19162 /* Add the insn. */
19164 add_unwind_opcode (bytes
[n
- 1], 1);
19165 add_unwind_opcode (0xb2, 1);
19167 else if (offset
> 0x100)
19169 /* Two short opcodes. */
19170 add_unwind_opcode (0x3f, 1);
19171 op
= (offset
- 0x104) >> 2;
19172 add_unwind_opcode (op
, 1);
19174 else if (offset
> 0)
19176 /* Short opcode. */
19177 op
= (offset
- 4) >> 2;
19178 add_unwind_opcode (op
, 1);
19180 else if (offset
< 0)
19183 while (offset
> 0x100)
19185 add_unwind_opcode (0x7f, 1);
19188 op
= ((offset
- 4) >> 2) | 0x40;
19189 add_unwind_opcode (op
, 1);
19193 /* Finish the list of unwind opcodes for this function. */
19195 finish_unwind_opcodes (void)
19199 if (unwind
.fp_used
)
19201 /* Adjust sp as necessary. */
19202 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
19203 flush_pending_unwind ();
19205 /* After restoring sp from the frame pointer. */
19206 op
= 0x90 | unwind
.fp_reg
;
19207 add_unwind_opcode (op
, 1);
19210 flush_pending_unwind ();
19214 /* Start an exception table entry. If idx is nonzero this is an index table
19218 start_unwind_section (const segT text_seg
, int idx
)
19220 const char * text_name
;
19221 const char * prefix
;
19222 const char * prefix_once
;
19223 const char * group_name
;
19227 size_t sec_name_len
;
19234 prefix
= ELF_STRING_ARM_unwind
;
19235 prefix_once
= ELF_STRING_ARM_unwind_once
;
19236 type
= SHT_ARM_EXIDX
;
19240 prefix
= ELF_STRING_ARM_unwind_info
;
19241 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
19242 type
= SHT_PROGBITS
;
19245 text_name
= segment_name (text_seg
);
19246 if (streq (text_name
, ".text"))
19249 if (strncmp (text_name
, ".gnu.linkonce.t.",
19250 strlen (".gnu.linkonce.t.")) == 0)
19252 prefix
= prefix_once
;
19253 text_name
+= strlen (".gnu.linkonce.t.");
19256 prefix_len
= strlen (prefix
);
19257 text_len
= strlen (text_name
);
19258 sec_name_len
= prefix_len
+ text_len
;
19259 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
19260 memcpy (sec_name
, prefix
, prefix_len
);
19261 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
19262 sec_name
[prefix_len
+ text_len
] = '\0';
19268 /* Handle COMDAT group. */
19269 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
19271 group_name
= elf_group_name (text_seg
);
19272 if (group_name
== NULL
)
19274 as_bad (_("Group section `%s' has no group signature"),
19275 segment_name (text_seg
));
19276 ignore_rest_of_line ();
19279 flags
|= SHF_GROUP
;
19283 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
19285 /* Set the section link for index tables. */
19287 elf_linked_to_section (now_seg
) = text_seg
;
19291 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19292 personality routine data. Returns zero, or the index table value for
19293 and inline entry. */
19296 create_unwind_entry (int have_data
)
19301 /* The current word of data. */
19303 /* The number of bytes left in this word. */
19306 finish_unwind_opcodes ();
19308 /* Remember the current text section. */
19309 unwind
.saved_seg
= now_seg
;
19310 unwind
.saved_subseg
= now_subseg
;
19312 start_unwind_section (now_seg
, 0);
19314 if (unwind
.personality_routine
== NULL
)
19316 if (unwind
.personality_index
== -2)
19319 as_bad (_("handlerdata in cantunwind frame"));
19320 return 1; /* EXIDX_CANTUNWIND. */
19323 /* Use a default personality routine if none is specified. */
19324 if (unwind
.personality_index
== -1)
19326 if (unwind
.opcode_count
> 3)
19327 unwind
.personality_index
= 1;
19329 unwind
.personality_index
= 0;
19332 /* Space for the personality routine entry. */
19333 if (unwind
.personality_index
== 0)
19335 if (unwind
.opcode_count
> 3)
19336 as_bad (_("too many unwind opcodes for personality routine 0"));
19340 /* All the data is inline in the index table. */
19343 while (unwind
.opcode_count
> 0)
19345 unwind
.opcode_count
--;
19346 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19350 /* Pad with "finish" opcodes. */
19352 data
= (data
<< 8) | 0xb0;
19359 /* We get two opcodes "free" in the first word. */
19360 size
= unwind
.opcode_count
- 2;
19363 /* An extra byte is required for the opcode count. */
19364 size
= unwind
.opcode_count
+ 1;
19366 size
= (size
+ 3) >> 2;
19368 as_bad (_("too many unwind opcodes"));
19370 frag_align (2, 0, 0);
19371 record_alignment (now_seg
, 2);
19372 unwind
.table_entry
= expr_build_dot ();
19374 /* Allocate the table entry. */
19375 ptr
= frag_more ((size
<< 2) + 4);
19376 where
= frag_now_fix () - ((size
<< 2) + 4);
19378 switch (unwind
.personality_index
)
19381 /* ??? Should this be a PLT generating relocation? */
19382 /* Custom personality routine. */
19383 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19384 BFD_RELOC_ARM_PREL31
);
19389 /* Set the first byte to the number of additional words. */
19394 /* ABI defined personality routines. */
19396 /* Three opcodes bytes are packed into the first word. */
19403 /* The size and first two opcode bytes go in the first word. */
19404 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19409 /* Should never happen. */
19413 /* Pack the opcodes into words (MSB first), reversing the list at the same
19415 while (unwind
.opcode_count
> 0)
19419 md_number_to_chars (ptr
, data
, 4);
19424 unwind
.opcode_count
--;
19426 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19429 /* Finish off the last word. */
19432 /* Pad with "finish" opcodes. */
19434 data
= (data
<< 8) | 0xb0;
19436 md_number_to_chars (ptr
, data
, 4);
19441 /* Add an empty descriptor if there is no user-specified data. */
19442 ptr
= frag_more (4);
19443 md_number_to_chars (ptr
, 0, 4);
19450 /* Initialize the DWARF-2 unwind information for this procedure. */
19453 tc_arm_frame_initial_instructions (void)
19455 cfi_add_CFA_def_cfa (REG_SP
, 0);
19457 #endif /* OBJ_ELF */
19459 /* Convert REGNAME to a DWARF-2 register number. */
19462 tc_arm_regname_to_dw2regnum (char *regname
)
19464 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19474 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19478 exp
.X_op
= O_secrel
;
19479 exp
.X_add_symbol
= symbol
;
19480 exp
.X_add_number
= 0;
19481 emit_expr (&exp
, size
);
19485 /* MD interface: Symbol and relocation handling. */
19487 /* Return the address within the segment that a PC-relative fixup is
19488 relative to. For ARM, PC-relative fixups applied to instructions
19489 are generally relative to the location of the fixup plus 8 bytes.
19490 Thumb branches are offset by 4, and Thumb loads relative to PC
19491 require special handling. */
19494 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19496 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19498 /* If this is pc-relative and we are going to emit a relocation
19499 then we just want to put out any pipeline compensation that the linker
19500 will need. Otherwise we want to use the calculated base.
19501 For WinCE we skip the bias for externals as well, since this
19502 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19504 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19505 || (arm_force_relocation (fixP
)
19507 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19513 switch (fixP
->fx_r_type
)
19515 /* PC relative addressing on the Thumb is slightly odd as the
19516 bottom two bits of the PC are forced to zero for the
19517 calculation. This happens *after* application of the
19518 pipeline offset. However, Thumb adrl already adjusts for
19519 this, so we need not do it again. */
19520 case BFD_RELOC_ARM_THUMB_ADD
:
19523 case BFD_RELOC_ARM_THUMB_OFFSET
:
19524 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19525 case BFD_RELOC_ARM_T32_ADD_PC12
:
19526 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19527 return (base
+ 4) & ~3;
19529 /* Thumb branches are simply offset by +4. */
19530 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19531 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19532 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19533 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19534 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19537 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19539 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19540 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19541 && ARM_IS_FUNC (fixP
->fx_addsy
)
19542 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19543 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19546 /* BLX is like branches above, but forces the low two bits of PC to
19548 case BFD_RELOC_THUMB_PCREL_BLX
:
19550 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19551 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19552 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19553 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19554 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19555 return (base
+ 4) & ~3;
19557 /* ARM mode branches are offset by +8. However, the Windows CE
19558 loader expects the relocation not to take this into account. */
19559 case BFD_RELOC_ARM_PCREL_BLX
:
19561 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19562 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19563 && ARM_IS_FUNC (fixP
->fx_addsy
)
19564 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19565 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19568 case BFD_RELOC_ARM_PCREL_CALL
:
19570 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19571 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19572 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19573 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19574 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19577 case BFD_RELOC_ARM_PCREL_BRANCH
:
19578 case BFD_RELOC_ARM_PCREL_JUMP
:
19579 case BFD_RELOC_ARM_PLT32
:
19581 /* When handling fixups immediately, because we have already
19582 discovered the value of a symbol, or the address of the frag involved
19583 we must account for the offset by +8, as the OS loader will never see the reloc.
19584 see fixup_segment() in write.c
19585 The S_IS_EXTERNAL test handles the case of global symbols.
19586 Those need the calculated base, not just the pipe compensation the linker will need. */
19588 && fixP
->fx_addsy
!= NULL
19589 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19590 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19598 /* ARM mode loads relative to PC are also offset by +8. Unlike
19599 branches, the Windows CE loader *does* expect the relocation
19600 to take this into account. */
19601 case BFD_RELOC_ARM_OFFSET_IMM
:
19602 case BFD_RELOC_ARM_OFFSET_IMM8
:
19603 case BFD_RELOC_ARM_HWLITERAL
:
19604 case BFD_RELOC_ARM_LITERAL
:
19605 case BFD_RELOC_ARM_CP_OFF_IMM
:
19609 /* Other PC-relative relocations are un-offset. */
19615 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19616 Otherwise we have no need to default values of symbols. */
19619 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
19622 if (name
[0] == '_' && name
[1] == 'G'
19623 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
19627 if (symbol_find (name
))
19628 as_bad (_("GOT already in the symbol table"));
19630 GOT_symbol
= symbol_new (name
, undefined_section
,
19631 (valueT
) 0, & zero_address_frag
);
19641 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19642 computed as two separate immediate values, added together. We
19643 already know that this value cannot be computed by just one ARM
19646 static unsigned int
19647 validate_immediate_twopart (unsigned int val
,
19648 unsigned int * highpart
)
19653 for (i
= 0; i
< 32; i
+= 2)
19654 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
19660 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
19662 else if (a
& 0xff0000)
19664 if (a
& 0xff000000)
19666 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
19670 gas_assert (a
& 0xff000000);
19671 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
19674 return (a
& 0xff) | (i
<< 7);
19681 validate_offset_imm (unsigned int val
, int hwse
)
19683 if ((hwse
&& val
> 255) || val
> 4095)
19688 /* Subroutine of md_apply_fix. Do those data_ops which can take a
19689 negative immediate constant by altering the instruction. A bit of
19694 by inverting the second operand, and
19697 by negating the second operand. */
19700 negate_data_op (unsigned long * instruction
,
19701 unsigned long value
)
19704 unsigned long negated
, inverted
;
19706 negated
= encode_arm_immediate (-value
);
19707 inverted
= encode_arm_immediate (~value
);
19709 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
19712 /* First negates. */
19713 case OPCODE_SUB
: /* ADD <-> SUB */
19714 new_inst
= OPCODE_ADD
;
19719 new_inst
= OPCODE_SUB
;
19723 case OPCODE_CMP
: /* CMP <-> CMN */
19724 new_inst
= OPCODE_CMN
;
19729 new_inst
= OPCODE_CMP
;
19733 /* Now Inverted ops. */
19734 case OPCODE_MOV
: /* MOV <-> MVN */
19735 new_inst
= OPCODE_MVN
;
19740 new_inst
= OPCODE_MOV
;
19744 case OPCODE_AND
: /* AND <-> BIC */
19745 new_inst
= OPCODE_BIC
;
19750 new_inst
= OPCODE_AND
;
19754 case OPCODE_ADC
: /* ADC <-> SBC */
19755 new_inst
= OPCODE_SBC
;
19760 new_inst
= OPCODE_ADC
;
19764 /* We cannot do anything. */
19769 if (value
== (unsigned) FAIL
)
19772 *instruction
&= OPCODE_MASK
;
19773 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
19777 /* Like negate_data_op, but for Thumb-2. */
19779 static unsigned int
19780 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
19784 unsigned int negated
, inverted
;
19786 negated
= encode_thumb32_immediate (-value
);
19787 inverted
= encode_thumb32_immediate (~value
);
19789 rd
= (*instruction
>> 8) & 0xf;
19790 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
19793 /* ADD <-> SUB. Includes CMP <-> CMN. */
19794 case T2_OPCODE_SUB
:
19795 new_inst
= T2_OPCODE_ADD
;
19799 case T2_OPCODE_ADD
:
19800 new_inst
= T2_OPCODE_SUB
;
19804 /* ORR <-> ORN. Includes MOV <-> MVN. */
19805 case T2_OPCODE_ORR
:
19806 new_inst
= T2_OPCODE_ORN
;
19810 case T2_OPCODE_ORN
:
19811 new_inst
= T2_OPCODE_ORR
;
19815 /* AND <-> BIC. TST has no inverted equivalent. */
19816 case T2_OPCODE_AND
:
19817 new_inst
= T2_OPCODE_BIC
;
19824 case T2_OPCODE_BIC
:
19825 new_inst
= T2_OPCODE_AND
;
19830 case T2_OPCODE_ADC
:
19831 new_inst
= T2_OPCODE_SBC
;
19835 case T2_OPCODE_SBC
:
19836 new_inst
= T2_OPCODE_ADC
;
19840 /* We cannot do anything. */
19845 if (value
== (unsigned int)FAIL
)
19848 *instruction
&= T2_OPCODE_MASK
;
19849 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
19853 /* Read a 32-bit thumb instruction from buf. */
19854 static unsigned long
19855 get_thumb32_insn (char * buf
)
19857 unsigned long insn
;
19858 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
19859 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19865 /* We usually want to set the low bit on the address of thumb function
19866 symbols. In particular .word foo - . should have the low bit set.
19867 Generic code tries to fold the difference of two symbols to
19868 a constant. Prevent this and force a relocation when the first symbols
19869 is a thumb function. */
19872 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
19874 if (op
== O_subtract
19875 && l
->X_op
== O_symbol
19876 && r
->X_op
== O_symbol
19877 && THUMB_IS_FUNC (l
->X_add_symbol
))
19879 l
->X_op
= O_subtract
;
19880 l
->X_op_symbol
= r
->X_add_symbol
;
19881 l
->X_add_number
-= r
->X_add_number
;
19885 /* Process as normal. */
19889 /* Encode Thumb2 unconditional branches and calls. The encoding
19890 for the 2 are identical for the immediate values. */
19893 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
19895 #define T2I1I2MASK ((1 << 13) | (1 << 11))
19898 addressT S
, I1
, I2
, lo
, hi
;
19900 S
= (value
>> 24) & 0x01;
19901 I1
= (value
>> 23) & 0x01;
19902 I2
= (value
>> 22) & 0x01;
19903 hi
= (value
>> 12) & 0x3ff;
19904 lo
= (value
>> 1) & 0x7ff;
19905 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19906 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19907 newval
|= (S
<< 10) | hi
;
19908 newval2
&= ~T2I1I2MASK
;
19909 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
19910 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19911 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19915 md_apply_fix (fixS
* fixP
,
19919 offsetT value
= * valP
;
19921 unsigned int newimm
;
19922 unsigned long temp
;
19924 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
19926 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
19928 /* Note whether this will delete the relocation. */
19930 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
19933 /* On a 64-bit host, silently truncate 'value' to 32 bits for
19934 consistency with the behaviour on 32-bit hosts. Remember value
19936 value
&= 0xffffffff;
19937 value
^= 0x80000000;
19938 value
-= 0x80000000;
19941 fixP
->fx_addnumber
= value
;
19943 /* Same treatment for fixP->fx_offset. */
19944 fixP
->fx_offset
&= 0xffffffff;
19945 fixP
->fx_offset
^= 0x80000000;
19946 fixP
->fx_offset
-= 0x80000000;
19948 switch (fixP
->fx_r_type
)
19950 case BFD_RELOC_NONE
:
19951 /* This will need to go in the object file. */
19955 case BFD_RELOC_ARM_IMMEDIATE
:
19956 /* We claim that this fixup has been processed here,
19957 even if in fact we generate an error because we do
19958 not have a reloc for it, so tc_gen_reloc will reject it. */
19961 if (fixP
->fx_addsy
)
19963 const char *msg
= 0;
19965 if (! S_IS_DEFINED (fixP
->fx_addsy
))
19966 msg
= _("undefined symbol %s used as an immediate value");
19967 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19968 msg
= _("symbol %s is in a different section");
19969 else if (S_IS_WEAK (fixP
->fx_addsy
))
19970 msg
= _("symbol %s is weak and may be overridden later");
19974 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19975 msg
, S_GET_NAME (fixP
->fx_addsy
));
19980 newimm
= encode_arm_immediate (value
);
19981 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19983 /* If the instruction will fail, see if we can fix things up by
19984 changing the opcode. */
19985 if (newimm
== (unsigned int) FAIL
19986 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
19988 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19989 _("invalid constant (%lx) after fixup"),
19990 (unsigned long) value
);
19994 newimm
|= (temp
& 0xfffff000);
19995 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19998 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
20000 unsigned int highpart
= 0;
20001 unsigned int newinsn
= 0xe1a00000; /* nop. */
20003 if (fixP
->fx_addsy
)
20005 const char *msg
= 0;
20007 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20008 msg
= _("undefined symbol %s used as an immediate value");
20009 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20010 msg
= _("symbol %s is in a different section");
20011 else if (S_IS_WEAK (fixP
->fx_addsy
))
20012 msg
= _("symbol %s is weak and may be overridden later");
20016 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20017 msg
, S_GET_NAME (fixP
->fx_addsy
));
20022 newimm
= encode_arm_immediate (value
);
20023 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20025 /* If the instruction will fail, see if we can fix things up by
20026 changing the opcode. */
20027 if (newimm
== (unsigned int) FAIL
20028 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
20030 /* No ? OK - try using two ADD instructions to generate
20032 newimm
= validate_immediate_twopart (value
, & highpart
);
20034 /* Yes - then make sure that the second instruction is
20036 if (newimm
!= (unsigned int) FAIL
)
20038 /* Still No ? Try using a negated value. */
20039 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
20040 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
20041 /* Otherwise - give up. */
20044 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20045 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20050 /* Replace the first operand in the 2nd instruction (which
20051 is the PC) with the destination register. We have
20052 already added in the PC in the first instruction and we
20053 do not want to do it again. */
20054 newinsn
&= ~ 0xf0000;
20055 newinsn
|= ((newinsn
& 0x0f000) << 4);
20058 newimm
|= (temp
& 0xfffff000);
20059 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20061 highpart
|= (newinsn
& 0xfffff000);
20062 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
20066 case BFD_RELOC_ARM_OFFSET_IMM
:
20067 if (!fixP
->fx_done
&& seg
->use_rela_p
)
20070 case BFD_RELOC_ARM_LITERAL
:
20076 if (validate_offset_imm (value
, 0) == FAIL
)
20078 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
20079 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20080 _("invalid literal constant: pool needs to be closer"));
20082 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20083 _("bad immediate value for offset (%ld)"),
20088 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20089 newval
&= 0xff7ff000;
20090 newval
|= value
| (sign
? INDEX_UP
: 0);
20091 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20094 case BFD_RELOC_ARM_OFFSET_IMM8
:
20095 case BFD_RELOC_ARM_HWLITERAL
:
20101 if (validate_offset_imm (value
, 1) == FAIL
)
20103 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
20104 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20105 _("invalid literal constant: pool needs to be closer"));
20107 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20112 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20113 newval
&= 0xff7ff0f0;
20114 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
20115 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20118 case BFD_RELOC_ARM_T32_OFFSET_U8
:
20119 if (value
< 0 || value
> 1020 || value
% 4 != 0)
20120 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20121 _("bad immediate value for offset (%ld)"), (long) value
);
20124 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
20126 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
20129 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20130 /* This is a complicated relocation used for all varieties of Thumb32
20131 load/store instruction with immediate offset:
20133 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20134 *4, optional writeback(W)
20135 (doubleword load/store)
20137 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20138 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20139 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20140 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20141 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20143 Uppercase letters indicate bits that are already encoded at
20144 this point. Lowercase letters are our problem. For the
20145 second block of instructions, the secondary opcode nybble
20146 (bits 8..11) is present, and bit 23 is zero, even if this is
20147 a PC-relative operation. */
20148 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20150 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
20152 if ((newval
& 0xf0000000) == 0xe0000000)
20154 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20156 newval
|= (1 << 23);
20159 if (value
% 4 != 0)
20161 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20162 _("offset not a multiple of 4"));
20168 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20169 _("offset out of range"));
20174 else if ((newval
& 0x000f0000) == 0x000f0000)
20176 /* PC-relative, 12-bit offset. */
20178 newval
|= (1 << 23);
20183 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20184 _("offset out of range"));
20189 else if ((newval
& 0x00000100) == 0x00000100)
20191 /* Writeback: 8-bit, +/- offset. */
20193 newval
|= (1 << 9);
20198 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20199 _("offset out of range"));
20204 else if ((newval
& 0x00000f00) == 0x00000e00)
20206 /* T-instruction: positive 8-bit offset. */
20207 if (value
< 0 || value
> 0xff)
20209 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20210 _("offset out of range"));
20218 /* Positive 12-bit or negative 8-bit offset. */
20222 newval
|= (1 << 23);
20232 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20233 _("offset out of range"));
20240 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
20241 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
20244 case BFD_RELOC_ARM_SHIFT_IMM
:
20245 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20246 if (((unsigned long) value
) > 32
20248 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
20250 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20251 _("shift expression is too large"));
20256 /* Shifts of zero must be done as lsl. */
20258 else if (value
== 32)
20260 newval
&= 0xfffff07f;
20261 newval
|= (value
& 0x1f) << 7;
20262 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20265 case BFD_RELOC_ARM_T32_IMMEDIATE
:
20266 case BFD_RELOC_ARM_T32_ADD_IMM
:
20267 case BFD_RELOC_ARM_T32_IMM12
:
20268 case BFD_RELOC_ARM_T32_ADD_PC12
:
20269 /* We claim that this fixup has been processed here,
20270 even if in fact we generate an error because we do
20271 not have a reloc for it, so tc_gen_reloc will reject it. */
20275 && ! S_IS_DEFINED (fixP
->fx_addsy
))
20277 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20278 _("undefined symbol %s used as an immediate value"),
20279 S_GET_NAME (fixP
->fx_addsy
));
20283 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20285 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
20288 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20289 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20291 newimm
= encode_thumb32_immediate (value
);
20292 if (newimm
== (unsigned int) FAIL
)
20293 newimm
= thumb32_negate_data_op (&newval
, value
);
20295 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
20296 && newimm
== (unsigned int) FAIL
)
20298 /* Turn add/sum into addw/subw. */
20299 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20300 newval
= (newval
& 0xfeffffff) | 0x02000000;
20301 /* No flat 12-bit imm encoding for addsw/subsw. */
20302 if ((newval
& 0x00100000) == 0)
20304 /* 12 bit immediate for addw/subw. */
20308 newval
^= 0x00a00000;
20311 newimm
= (unsigned int) FAIL
;
20317 if (newimm
== (unsigned int)FAIL
)
20319 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20320 _("invalid constant (%lx) after fixup"),
20321 (unsigned long) value
);
20325 newval
|= (newimm
& 0x800) << 15;
20326 newval
|= (newimm
& 0x700) << 4;
20327 newval
|= (newimm
& 0x0ff);
20329 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
20330 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
20333 case BFD_RELOC_ARM_SMC
:
20334 if (((unsigned long) value
) > 0xffff)
20335 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20336 _("invalid smc expression"));
20337 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20338 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20339 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20342 case BFD_RELOC_ARM_SWI
:
20343 if (fixP
->tc_fix_data
!= 0)
20345 if (((unsigned long) value
) > 0xff)
20346 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20347 _("invalid swi expression"));
20348 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20350 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20354 if (((unsigned long) value
) > 0x00ffffff)
20355 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20356 _("invalid swi expression"));
20357 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20359 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20363 case BFD_RELOC_ARM_MULTI
:
20364 if (((unsigned long) value
) > 0xffff)
20365 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20366 _("invalid expression in load/store multiple"));
20367 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20368 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20372 case BFD_RELOC_ARM_PCREL_CALL
:
20374 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20376 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20377 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20378 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20379 /* Flip the bl to blx. This is a simple flip
20380 bit here because we generate PCREL_CALL for
20381 unconditional bls. */
20383 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20384 newval
= newval
| 0x10000000;
20385 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20391 goto arm_branch_common
;
20393 case BFD_RELOC_ARM_PCREL_JUMP
:
20394 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20396 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20397 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20398 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20400 /* This would map to a bl<cond>, b<cond>,
20401 b<always> to a Thumb function. We
20402 need to force a relocation for this particular
20404 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20408 case BFD_RELOC_ARM_PLT32
:
20410 case BFD_RELOC_ARM_PCREL_BRANCH
:
20412 goto arm_branch_common
;
20414 case BFD_RELOC_ARM_PCREL_BLX
:
20417 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20419 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20420 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20421 && ARM_IS_FUNC (fixP
->fx_addsy
))
20423 /* Flip the blx to a bl and warn. */
20424 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20425 newval
= 0xeb000000;
20426 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20427 _("blx to '%s' an ARM ISA state function changed to bl"),
20429 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20435 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20436 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20440 /* We are going to store value (shifted right by two) in the
20441 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20442 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20443 also be be clear. */
20445 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20446 _("misaligned branch destination"));
20447 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20448 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20449 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20450 _("branch out of range"));
20452 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20454 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20455 newval
|= (value
>> 2) & 0x00ffffff;
20456 /* Set the H bit on BLX instructions. */
20460 newval
|= 0x01000000;
20462 newval
&= ~0x01000000;
20464 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20468 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20469 /* CBZ can only branch forward. */
20471 /* Attempts to use CBZ to branch to the next instruction
20472 (which, strictly speaking, are prohibited) will be turned into
20475 FIXME: It may be better to remove the instruction completely and
20476 perform relaxation. */
20479 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20480 newval
= 0xbf00; /* NOP encoding T1 */
20481 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20486 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20487 _("branch out of range"));
20489 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20491 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20492 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20493 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20498 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20499 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20500 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20501 _("branch out of range"));
20503 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20505 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20506 newval
|= (value
& 0x1ff) >> 1;
20507 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20511 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20512 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20513 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20514 _("branch out of range"));
20516 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20518 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20519 newval
|= (value
& 0xfff) >> 1;
20520 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20524 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20526 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20527 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20528 && S_IS_DEFINED (fixP
->fx_addsy
)
20529 && ARM_IS_FUNC (fixP
->fx_addsy
)
20530 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20532 /* Force a relocation for a branch 20 bits wide. */
20535 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20536 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20537 _("conditional branch out of range"));
20539 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20542 addressT S
, J1
, J2
, lo
, hi
;
20544 S
= (value
& 0x00100000) >> 20;
20545 J2
= (value
& 0x00080000) >> 19;
20546 J1
= (value
& 0x00040000) >> 18;
20547 hi
= (value
& 0x0003f000) >> 12;
20548 lo
= (value
& 0x00000ffe) >> 1;
20550 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20551 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20552 newval
|= (S
<< 10) | hi
;
20553 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20554 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20555 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20559 case BFD_RELOC_THUMB_PCREL_BLX
:
20561 /* If there is a blx from a thumb state function to
20562 another thumb function flip this to a bl and warn
20566 && S_IS_DEFINED (fixP
->fx_addsy
)
20567 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20568 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20569 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20571 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20572 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20573 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20575 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20576 newval
= newval
| 0x1000;
20577 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20578 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20583 goto thumb_bl_common
;
20585 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20587 /* A bl from Thumb state ISA to an internal ARM state function
20588 is converted to a blx. */
20590 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20591 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20592 && S_IS_DEFINED (fixP
->fx_addsy
)
20593 && ARM_IS_FUNC (fixP
->fx_addsy
)
20594 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20596 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20597 newval
= newval
& ~0x1000;
20598 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20599 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20606 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20607 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20608 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20611 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20612 /* For a BLX instruction, make sure that the relocation is rounded up
20613 to a word boundary. This follows the semantics of the instruction
20614 which specifies that bit 1 of the target address will come from bit
20615 1 of the base address. */
20616 value
= (value
+ 1) & ~ 1;
20619 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
20621 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
20623 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20624 _("branch out of range"));
20626 else if ((value
& ~0x1ffffff)
20627 && ((value
& ~0x1ffffff) != ~0x1ffffff))
20629 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20630 _("Thumb2 branch out of range"));
20634 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20635 encode_thumb2_b_bl_offset (buf
, value
);
20639 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20640 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
20641 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20642 _("branch out of range"));
20644 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20645 encode_thumb2_b_bl_offset (buf
, value
);
20650 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20651 md_number_to_chars (buf
, value
, 1);
20655 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20656 md_number_to_chars (buf
, value
, 2);
20660 case BFD_RELOC_ARM_TLS_GD32
:
20661 case BFD_RELOC_ARM_TLS_LE32
:
20662 case BFD_RELOC_ARM_TLS_IE32
:
20663 case BFD_RELOC_ARM_TLS_LDM32
:
20664 case BFD_RELOC_ARM_TLS_LDO32
:
20665 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
20668 case BFD_RELOC_ARM_GOT32
:
20669 case BFD_RELOC_ARM_GOTOFF
:
20670 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20671 md_number_to_chars (buf
, 0, 4);
20674 case BFD_RELOC_ARM_GOT_PREL
:
20675 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20676 md_number_to_chars (buf
, value
, 4);
20679 case BFD_RELOC_ARM_TARGET2
:
20680 /* TARGET2 is not partial-inplace, so we need to write the
20681 addend here for REL targets, because it won't be written out
20682 during reloc processing later. */
20683 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20684 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
20688 case BFD_RELOC_RVA
:
20690 case BFD_RELOC_ARM_TARGET1
:
20691 case BFD_RELOC_ARM_ROSEGREL32
:
20692 case BFD_RELOC_ARM_SBREL32
:
20693 case BFD_RELOC_32_PCREL
:
20695 case BFD_RELOC_32_SECREL
:
20697 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20699 /* For WinCE we only do this for pcrel fixups. */
20700 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
20702 md_number_to_chars (buf
, value
, 4);
20706 case BFD_RELOC_ARM_PREL31
:
20707 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20709 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
20710 if ((value
^ (value
>> 1)) & 0x40000000)
20712 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20713 _("rel31 relocation overflow"));
20715 newval
|= value
& 0x7fffffff;
20716 md_number_to_chars (buf
, newval
, 4);
20721 case BFD_RELOC_ARM_CP_OFF_IMM
:
20722 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20723 if (value
< -1023 || value
> 1023 || (value
& 3))
20724 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20725 _("co-processor offset out of range"));
20730 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20731 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20732 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20734 newval
= get_thumb32_insn (buf
);
20735 newval
&= 0xff7fff00;
20736 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
20737 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20738 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20739 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20741 put_thumb32_insn (buf
, newval
);
20744 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
20745 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
20746 if (value
< -255 || value
> 255)
20747 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20748 _("co-processor offset out of range"));
20750 goto cp_off_common
;
20752 case BFD_RELOC_ARM_THUMB_OFFSET
:
20753 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20754 /* Exactly what ranges, and where the offset is inserted depends
20755 on the type of instruction, we can establish this from the
20757 switch (newval
>> 12)
20759 case 4: /* PC load. */
20760 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
20761 forced to zero for these loads; md_pcrel_from has already
20762 compensated for this. */
20764 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20765 _("invalid offset, target not word aligned (0x%08lX)"),
20766 (((unsigned long) fixP
->fx_frag
->fr_address
20767 + (unsigned long) fixP
->fx_where
) & ~3)
20768 + (unsigned long) value
);
20770 if (value
& ~0x3fc)
20771 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20772 _("invalid offset, value too big (0x%08lX)"),
20775 newval
|= value
>> 2;
20778 case 9: /* SP load/store. */
20779 if (value
& ~0x3fc)
20780 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20781 _("invalid offset, value too big (0x%08lX)"),
20783 newval
|= value
>> 2;
20786 case 6: /* Word load/store. */
20788 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20789 _("invalid offset, value too big (0x%08lX)"),
20791 newval
|= value
<< 4; /* 6 - 2. */
20794 case 7: /* Byte load/store. */
20796 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20797 _("invalid offset, value too big (0x%08lX)"),
20799 newval
|= value
<< 6;
20802 case 8: /* Halfword load/store. */
20804 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20805 _("invalid offset, value too big (0x%08lX)"),
20807 newval
|= value
<< 5; /* 6 - 1. */
20811 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20812 "Unable to process relocation for thumb opcode: %lx",
20813 (unsigned long) newval
);
20816 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20819 case BFD_RELOC_ARM_THUMB_ADD
:
20820 /* This is a complicated relocation, since we use it for all of
20821 the following immediate relocations:
20825 9bit ADD/SUB SP word-aligned
20826 10bit ADD PC/SP word-aligned
20828 The type of instruction being processed is encoded in the
20835 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20837 int rd
= (newval
>> 4) & 0xf;
20838 int rs
= newval
& 0xf;
20839 int subtract
= !!(newval
& 0x8000);
20841 /* Check for HI regs, only very restricted cases allowed:
20842 Adjusting SP, and using PC or SP to get an address. */
20843 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
20844 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
20845 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20846 _("invalid Hi register with immediate"));
20848 /* If value is negative, choose the opposite instruction. */
20852 subtract
= !subtract
;
20854 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20855 _("immediate value out of range"));
20860 if (value
& ~0x1fc)
20861 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20862 _("invalid immediate for stack address calculation"));
20863 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
20864 newval
|= value
>> 2;
20866 else if (rs
== REG_PC
|| rs
== REG_SP
)
20868 if (subtract
|| value
& ~0x3fc)
20869 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20870 _("invalid immediate for address calculation (value = 0x%08lX)"),
20871 (unsigned long) value
);
20872 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
20874 newval
|= value
>> 2;
20879 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20880 _("immediate value out of range"));
20881 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
20882 newval
|= (rd
<< 8) | value
;
20887 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20888 _("immediate value out of range"));
20889 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
20890 newval
|= rd
| (rs
<< 3) | (value
<< 6);
20893 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20896 case BFD_RELOC_ARM_THUMB_IMM
:
20897 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20898 if (value
< 0 || value
> 255)
20899 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20900 _("invalid immediate: %ld is out of range"),
20903 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20906 case BFD_RELOC_ARM_THUMB_SHIFT
:
20907 /* 5bit shift value (0..32). LSL cannot take 32. */
20908 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
20909 temp
= newval
& 0xf800;
20910 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
20911 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20912 _("invalid shift value: %ld"), (long) value
);
20913 /* Shifts of zero must be encoded as LSL. */
20915 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
20916 /* Shifts of 32 are encoded as zero. */
20917 else if (value
== 32)
20919 newval
|= value
<< 6;
20920 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20923 case BFD_RELOC_VTABLE_INHERIT
:
20924 case BFD_RELOC_VTABLE_ENTRY
:
20928 case BFD_RELOC_ARM_MOVW
:
20929 case BFD_RELOC_ARM_MOVT
:
20930 case BFD_RELOC_ARM_THUMB_MOVW
:
20931 case BFD_RELOC_ARM_THUMB_MOVT
:
20932 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20934 /* REL format relocations are limited to a 16-bit addend. */
20935 if (!fixP
->fx_done
)
20937 if (value
< -0x8000 || value
> 0x7fff)
20938 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20939 _("offset out of range"));
20941 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
20942 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20947 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20948 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20950 newval
= get_thumb32_insn (buf
);
20951 newval
&= 0xfbf08f00;
20952 newval
|= (value
& 0xf000) << 4;
20953 newval
|= (value
& 0x0800) << 15;
20954 newval
|= (value
& 0x0700) << 4;
20955 newval
|= (value
& 0x00ff);
20956 put_thumb32_insn (buf
, newval
);
20960 newval
= md_chars_to_number (buf
, 4);
20961 newval
&= 0xfff0f000;
20962 newval
|= value
& 0x0fff;
20963 newval
|= (value
& 0xf000) << 4;
20964 md_number_to_chars (buf
, newval
, 4);
20969 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20970 case BFD_RELOC_ARM_ALU_PC_G0
:
20971 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20972 case BFD_RELOC_ARM_ALU_PC_G1
:
20973 case BFD_RELOC_ARM_ALU_PC_G2
:
20974 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20975 case BFD_RELOC_ARM_ALU_SB_G0
:
20976 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20977 case BFD_RELOC_ARM_ALU_SB_G1
:
20978 case BFD_RELOC_ARM_ALU_SB_G2
:
20979 gas_assert (!fixP
->fx_done
);
20980 if (!seg
->use_rela_p
)
20983 bfd_vma encoded_addend
;
20984 bfd_vma addend_abs
= abs (value
);
20986 /* Check that the absolute value of the addend can be
20987 expressed as an 8-bit constant plus a rotation. */
20988 encoded_addend
= encode_arm_immediate (addend_abs
);
20989 if (encoded_addend
== (unsigned int) FAIL
)
20990 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20991 _("the offset 0x%08lX is not representable"),
20992 (unsigned long) addend_abs
);
20994 /* Extract the instruction. */
20995 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20997 /* If the addend is positive, use an ADD instruction.
20998 Otherwise use a SUB. Take care not to destroy the S bit. */
20999 insn
&= 0xff1fffff;
21005 /* Place the encoded addend into the first 12 bits of the
21007 insn
&= 0xfffff000;
21008 insn
|= encoded_addend
;
21010 /* Update the instruction. */
21011 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21015 case BFD_RELOC_ARM_LDR_PC_G0
:
21016 case BFD_RELOC_ARM_LDR_PC_G1
:
21017 case BFD_RELOC_ARM_LDR_PC_G2
:
21018 case BFD_RELOC_ARM_LDR_SB_G0
:
21019 case BFD_RELOC_ARM_LDR_SB_G1
:
21020 case BFD_RELOC_ARM_LDR_SB_G2
:
21021 gas_assert (!fixP
->fx_done
);
21022 if (!seg
->use_rela_p
)
21025 bfd_vma addend_abs
= abs (value
);
21027 /* Check that the absolute value of the addend can be
21028 encoded in 12 bits. */
21029 if (addend_abs
>= 0x1000)
21030 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21031 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21032 (unsigned long) addend_abs
);
21034 /* Extract the instruction. */
21035 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21037 /* If the addend is negative, clear bit 23 of the instruction.
21038 Otherwise set it. */
21040 insn
&= ~(1 << 23);
21044 /* Place the absolute value of the addend into the first 12 bits
21045 of the instruction. */
21046 insn
&= 0xfffff000;
21047 insn
|= addend_abs
;
21049 /* Update the instruction. */
21050 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21054 case BFD_RELOC_ARM_LDRS_PC_G0
:
21055 case BFD_RELOC_ARM_LDRS_PC_G1
:
21056 case BFD_RELOC_ARM_LDRS_PC_G2
:
21057 case BFD_RELOC_ARM_LDRS_SB_G0
:
21058 case BFD_RELOC_ARM_LDRS_SB_G1
:
21059 case BFD_RELOC_ARM_LDRS_SB_G2
:
21060 gas_assert (!fixP
->fx_done
);
21061 if (!seg
->use_rela_p
)
21064 bfd_vma addend_abs
= abs (value
);
21066 /* Check that the absolute value of the addend can be
21067 encoded in 8 bits. */
21068 if (addend_abs
>= 0x100)
21069 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21070 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21071 (unsigned long) addend_abs
);
21073 /* Extract the instruction. */
21074 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21076 /* If the addend is negative, clear bit 23 of the instruction.
21077 Otherwise set it. */
21079 insn
&= ~(1 << 23);
21083 /* Place the first four bits of the absolute value of the addend
21084 into the first 4 bits of the instruction, and the remaining
21085 four into bits 8 .. 11. */
21086 insn
&= 0xfffff0f0;
21087 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
21089 /* Update the instruction. */
21090 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21094 case BFD_RELOC_ARM_LDC_PC_G0
:
21095 case BFD_RELOC_ARM_LDC_PC_G1
:
21096 case BFD_RELOC_ARM_LDC_PC_G2
:
21097 case BFD_RELOC_ARM_LDC_SB_G0
:
21098 case BFD_RELOC_ARM_LDC_SB_G1
:
21099 case BFD_RELOC_ARM_LDC_SB_G2
:
21100 gas_assert (!fixP
->fx_done
);
21101 if (!seg
->use_rela_p
)
21104 bfd_vma addend_abs
= abs (value
);
21106 /* Check that the absolute value of the addend is a multiple of
21107 four and, when divided by four, fits in 8 bits. */
21108 if (addend_abs
& 0x3)
21109 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21110 _("bad offset 0x%08lX (must be word-aligned)"),
21111 (unsigned long) addend_abs
);
21113 if ((addend_abs
>> 2) > 0xff)
21114 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21115 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21116 (unsigned long) addend_abs
);
21118 /* Extract the instruction. */
21119 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21121 /* If the addend is negative, clear bit 23 of the instruction.
21122 Otherwise set it. */
21124 insn
&= ~(1 << 23);
21128 /* Place the addend (divided by four) into the first eight
21129 bits of the instruction. */
21130 insn
&= 0xfffffff0;
21131 insn
|= addend_abs
>> 2;
21133 /* Update the instruction. */
21134 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21138 case BFD_RELOC_ARM_V4BX
:
21139 /* This will need to go in the object file. */
21143 case BFD_RELOC_UNUSED
:
21145 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21146 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
21150 /* Translate internal representation of relocation info to BFD target
21154 tc_gen_reloc (asection
*section
, fixS
*fixp
)
21157 bfd_reloc_code_real_type code
;
21159 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
21161 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
21162 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
21163 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
21165 if (fixp
->fx_pcrel
)
21167 if (section
->use_rela_p
)
21168 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
21170 fixp
->fx_offset
= reloc
->address
;
21172 reloc
->addend
= fixp
->fx_offset
;
21174 switch (fixp
->fx_r_type
)
21177 if (fixp
->fx_pcrel
)
21179 code
= BFD_RELOC_8_PCREL
;
21184 if (fixp
->fx_pcrel
)
21186 code
= BFD_RELOC_16_PCREL
;
21191 if (fixp
->fx_pcrel
)
21193 code
= BFD_RELOC_32_PCREL
;
21197 case BFD_RELOC_ARM_MOVW
:
21198 if (fixp
->fx_pcrel
)
21200 code
= BFD_RELOC_ARM_MOVW_PCREL
;
21204 case BFD_RELOC_ARM_MOVT
:
21205 if (fixp
->fx_pcrel
)
21207 code
= BFD_RELOC_ARM_MOVT_PCREL
;
21211 case BFD_RELOC_ARM_THUMB_MOVW
:
21212 if (fixp
->fx_pcrel
)
21214 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
21218 case BFD_RELOC_ARM_THUMB_MOVT
:
21219 if (fixp
->fx_pcrel
)
21221 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
21225 case BFD_RELOC_NONE
:
21226 case BFD_RELOC_ARM_PCREL_BRANCH
:
21227 case BFD_RELOC_ARM_PCREL_BLX
:
21228 case BFD_RELOC_RVA
:
21229 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21230 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21231 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21232 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21233 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21234 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21235 case BFD_RELOC_VTABLE_ENTRY
:
21236 case BFD_RELOC_VTABLE_INHERIT
:
21238 case BFD_RELOC_32_SECREL
:
21240 code
= fixp
->fx_r_type
;
21243 case BFD_RELOC_THUMB_PCREL_BLX
:
21245 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21246 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21249 code
= BFD_RELOC_THUMB_PCREL_BLX
;
21252 case BFD_RELOC_ARM_LITERAL
:
21253 case BFD_RELOC_ARM_HWLITERAL
:
21254 /* If this is called then the a literal has
21255 been referenced across a section boundary. */
21256 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21257 _("literal referenced across section boundary"));
21261 case BFD_RELOC_ARM_GOT32
:
21262 case BFD_RELOC_ARM_GOTOFF
:
21263 case BFD_RELOC_ARM_GOT_PREL
:
21264 case BFD_RELOC_ARM_PLT32
:
21265 case BFD_RELOC_ARM_TARGET1
:
21266 case BFD_RELOC_ARM_ROSEGREL32
:
21267 case BFD_RELOC_ARM_SBREL32
:
21268 case BFD_RELOC_ARM_PREL31
:
21269 case BFD_RELOC_ARM_TARGET2
:
21270 case BFD_RELOC_ARM_TLS_LE32
:
21271 case BFD_RELOC_ARM_TLS_LDO32
:
21272 case BFD_RELOC_ARM_PCREL_CALL
:
21273 case BFD_RELOC_ARM_PCREL_JUMP
:
21274 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21275 case BFD_RELOC_ARM_ALU_PC_G0
:
21276 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21277 case BFD_RELOC_ARM_ALU_PC_G1
:
21278 case BFD_RELOC_ARM_ALU_PC_G2
:
21279 case BFD_RELOC_ARM_LDR_PC_G0
:
21280 case BFD_RELOC_ARM_LDR_PC_G1
:
21281 case BFD_RELOC_ARM_LDR_PC_G2
:
21282 case BFD_RELOC_ARM_LDRS_PC_G0
:
21283 case BFD_RELOC_ARM_LDRS_PC_G1
:
21284 case BFD_RELOC_ARM_LDRS_PC_G2
:
21285 case BFD_RELOC_ARM_LDC_PC_G0
:
21286 case BFD_RELOC_ARM_LDC_PC_G1
:
21287 case BFD_RELOC_ARM_LDC_PC_G2
:
21288 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21289 case BFD_RELOC_ARM_ALU_SB_G0
:
21290 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21291 case BFD_RELOC_ARM_ALU_SB_G1
:
21292 case BFD_RELOC_ARM_ALU_SB_G2
:
21293 case BFD_RELOC_ARM_LDR_SB_G0
:
21294 case BFD_RELOC_ARM_LDR_SB_G1
:
21295 case BFD_RELOC_ARM_LDR_SB_G2
:
21296 case BFD_RELOC_ARM_LDRS_SB_G0
:
21297 case BFD_RELOC_ARM_LDRS_SB_G1
:
21298 case BFD_RELOC_ARM_LDRS_SB_G2
:
21299 case BFD_RELOC_ARM_LDC_SB_G0
:
21300 case BFD_RELOC_ARM_LDC_SB_G1
:
21301 case BFD_RELOC_ARM_LDC_SB_G2
:
21302 case BFD_RELOC_ARM_V4BX
:
21303 code
= fixp
->fx_r_type
;
21306 case BFD_RELOC_ARM_TLS_GD32
:
21307 case BFD_RELOC_ARM_TLS_IE32
:
21308 case BFD_RELOC_ARM_TLS_LDM32
:
21309 /* BFD will include the symbol's address in the addend.
21310 But we don't want that, so subtract it out again here. */
21311 if (!S_IS_COMMON (fixp
->fx_addsy
))
21312 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
21313 code
= fixp
->fx_r_type
;
21317 case BFD_RELOC_ARM_IMMEDIATE
:
21318 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21319 _("internal relocation (type: IMMEDIATE) not fixed up"));
21322 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21323 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21324 _("ADRL used for a symbol not defined in the same file"));
21327 case BFD_RELOC_ARM_OFFSET_IMM
:
21328 if (section
->use_rela_p
)
21330 code
= fixp
->fx_r_type
;
21334 if (fixp
->fx_addsy
!= NULL
21335 && !S_IS_DEFINED (fixp
->fx_addsy
)
21336 && S_IS_LOCAL (fixp
->fx_addsy
))
21338 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21339 _("undefined local label `%s'"),
21340 S_GET_NAME (fixp
->fx_addsy
));
21344 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21345 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21352 switch (fixp
->fx_r_type
)
21354 case BFD_RELOC_NONE
: type
= "NONE"; break;
21355 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
21356 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
21357 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
21358 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
21359 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
21360 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21361 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
21362 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21363 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21364 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21365 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21366 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21367 default: type
= _("<unknown>"); break;
21369 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21370 _("cannot represent %s relocation in this object file format"),
21377 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21379 && fixp
->fx_addsy
== GOT_symbol
)
21381 code
= BFD_RELOC_ARM_GOTPC
;
21382 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21386 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21388 if (reloc
->howto
== NULL
)
21390 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21391 _("cannot represent %s relocation in this object file format"),
21392 bfd_get_reloc_code_name (code
));
21396 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21397 vtable entry to be used in the relocation's section offset. */
21398 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21399 reloc
->address
= fixp
->fx_offset
;
21404 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21407 cons_fix_new_arm (fragS
* frag
,
21412 bfd_reloc_code_real_type type
;
21416 FIXME: @@ Should look at CPU word size. */
21420 type
= BFD_RELOC_8
;
21423 type
= BFD_RELOC_16
;
21427 type
= BFD_RELOC_32
;
21430 type
= BFD_RELOC_64
;
21435 if (exp
->X_op
== O_secrel
)
21437 exp
->X_op
= O_symbol
;
21438 type
= BFD_RELOC_32_SECREL
;
21442 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21445 #if defined (OBJ_COFF)
21447 arm_validate_fix (fixS
* fixP
)
21449 /* If the destination of the branch is a defined symbol which does not have
21450 the THUMB_FUNC attribute, then we must be calling a function which has
21451 the (interfacearm) attribute. We look for the Thumb entry point to that
21452 function and change the branch to refer to that function instead. */
21453 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21454 && fixP
->fx_addsy
!= NULL
21455 && S_IS_DEFINED (fixP
->fx_addsy
)
21456 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21458 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21465 arm_force_relocation (struct fix
* fixp
)
21467 #if defined (OBJ_COFF) && defined (TE_PE)
21468 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21472 /* In case we have a call or a branch to a function in ARM ISA mode from
21473 a thumb function or vice-versa force the relocation. These relocations
21474 are cleared off for some cores that might have blx and simple transformations
21478 switch (fixp
->fx_r_type
)
21480 case BFD_RELOC_ARM_PCREL_JUMP
:
21481 case BFD_RELOC_ARM_PCREL_CALL
:
21482 case BFD_RELOC_THUMB_PCREL_BLX
:
21483 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21487 case BFD_RELOC_ARM_PCREL_BLX
:
21488 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21489 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21490 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21491 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21500 /* Resolve these relocations even if the symbol is extern or weak. */
21501 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
21502 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
21503 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
21504 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
21505 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21506 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
21507 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
21510 /* Always leave these relocations for the linker. */
21511 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21512 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21513 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21516 /* Always generate relocations against function symbols. */
21517 if (fixp
->fx_r_type
== BFD_RELOC_32
21519 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
21522 return generic_force_reloc (fixp
);
21525 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21526 /* Relocations against function names must be left unadjusted,
21527 so that the linker can use this information to generate interworking
21528 stubs. The MIPS version of this function
21529 also prevents relocations that are mips-16 specific, but I do not
21530 know why it does this.
21533 There is one other problem that ought to be addressed here, but
21534 which currently is not: Taking the address of a label (rather
21535 than a function) and then later jumping to that address. Such
21536 addresses also ought to have their bottom bit set (assuming that
21537 they reside in Thumb code), but at the moment they will not. */
21540 arm_fix_adjustable (fixS
* fixP
)
21542 if (fixP
->fx_addsy
== NULL
)
21545 /* Preserve relocations against symbols with function type. */
21546 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21549 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21550 && fixP
->fx_subsy
== NULL
)
21553 /* We need the symbol name for the VTABLE entries. */
21554 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21555 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21558 /* Don't allow symbols to be discarded on GOT related relocs. */
21559 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21560 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21561 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21562 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21563 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21564 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21565 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21566 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21567 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21570 /* Similarly for group relocations. */
21571 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21572 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21573 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21576 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21577 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21578 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21579 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21580 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21581 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21582 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21583 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21584 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
21589 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21594 elf32_arm_target_format (void)
21597 return (target_big_endian
21598 ? "elf32-bigarm-symbian"
21599 : "elf32-littlearm-symbian");
21600 #elif defined (TE_VXWORKS)
21601 return (target_big_endian
21602 ? "elf32-bigarm-vxworks"
21603 : "elf32-littlearm-vxworks");
21605 if (target_big_endian
)
21606 return "elf32-bigarm";
21608 return "elf32-littlearm";
21613 armelf_frob_symbol (symbolS
* symp
,
21616 elf_frob_symbol (symp
, puntp
);
21620 /* MD interface: Finalization. */
21625 literal_pool
* pool
;
21627 /* Ensure that all the IT blocks are properly closed. */
21628 check_it_blocks_finished ();
21630 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
21632 /* Put it at the end of the relevant section. */
21633 subseg_set (pool
->section
, pool
->sub_section
);
21635 arm_elf_change_section ();
21642 /* Remove any excess mapping symbols generated for alignment frags in
21643 SEC. We may have created a mapping symbol before a zero byte
21644 alignment; remove it if there's a mapping symbol after the
21647 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
21648 void *dummy ATTRIBUTE_UNUSED
)
21650 segment_info_type
*seginfo
= seg_info (sec
);
21653 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
21656 for (fragp
= seginfo
->frchainP
->frch_root
;
21658 fragp
= fragp
->fr_next
)
21660 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
21661 fragS
*next
= fragp
->fr_next
;
21663 /* Variable-sized frags have been converted to fixed size by
21664 this point. But if this was variable-sized to start with,
21665 there will be a fixed-size frag after it. So don't handle
21667 if (sym
== NULL
|| next
== NULL
)
21670 if (S_GET_VALUE (sym
) < next
->fr_address
)
21671 /* Not at the end of this frag. */
21673 know (S_GET_VALUE (sym
) == next
->fr_address
);
21677 if (next
->tc_frag_data
.first_map
!= NULL
)
21679 /* Next frag starts with a mapping symbol. Discard this
21681 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21685 if (next
->fr_next
== NULL
)
21687 /* This mapping symbol is at the end of the section. Discard
21689 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
21690 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21694 /* As long as we have empty frags without any mapping symbols,
21696 /* If the next frag is non-empty and does not start with a
21697 mapping symbol, then this mapping symbol is required. */
21698 if (next
->fr_address
!= next
->fr_next
->fr_address
)
21701 next
= next
->fr_next
;
21703 while (next
!= NULL
);
21708 /* Adjust the symbol table. This marks Thumb symbols as distinct from
21712 arm_adjust_symtab (void)
21717 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21719 if (ARM_IS_THUMB (sym
))
21721 if (THUMB_IS_FUNC (sym
))
21723 /* Mark the symbol as a Thumb function. */
21724 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
21725 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
21726 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
21728 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
21729 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
21731 as_bad (_("%s: unexpected function type: %d"),
21732 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
21734 else switch (S_GET_STORAGE_CLASS (sym
))
21737 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
21740 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
21743 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
21751 if (ARM_IS_INTERWORK (sym
))
21752 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
21759 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21761 if (ARM_IS_THUMB (sym
))
21763 elf_symbol_type
* elf_sym
;
21765 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
21766 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
21768 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
21769 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
21771 /* If it's a .thumb_func, declare it as so,
21772 otherwise tag label as .code 16. */
21773 if (THUMB_IS_FUNC (sym
))
21774 elf_sym
->internal_elf_sym
.st_info
=
21775 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
21776 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21777 elf_sym
->internal_elf_sym
.st_info
=
21778 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
21783 /* Remove any overlapping mapping symbols generated by alignment frags. */
21784 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
21788 /* MD interface: Initialization. */
21791 set_constant_flonums (void)
21795 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
21796 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
21800 /* Auto-select Thumb mode if it's the only available instruction set for the
21801 given architecture. */
21804 autoselect_thumb_from_cpu_variant (void)
21806 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21807 opcode_select (16);
21816 if ( (arm_ops_hsh
= hash_new ()) == NULL
21817 || (arm_cond_hsh
= hash_new ()) == NULL
21818 || (arm_shift_hsh
= hash_new ()) == NULL
21819 || (arm_psr_hsh
= hash_new ()) == NULL
21820 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
21821 || (arm_reg_hsh
= hash_new ()) == NULL
21822 || (arm_reloc_hsh
= hash_new ()) == NULL
21823 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
21824 as_fatal (_("virtual memory exhausted"));
21826 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
21827 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
21828 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
21829 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
21830 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
21831 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
21832 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
21833 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
21834 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
21835 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
21836 (void *) (v7m_psrs
+ i
));
21837 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
21838 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
21840 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
21842 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
21843 (void *) (barrier_opt_names
+ i
));
21845 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
21846 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
21849 set_constant_flonums ();
21851 /* Set the cpu variant based on the command-line options. We prefer
21852 -mcpu= over -march= if both are set (as for GCC); and we prefer
21853 -mfpu= over any other way of setting the floating point unit.
21854 Use of legacy options with new options are faulted. */
21857 if (mcpu_cpu_opt
|| march_cpu_opt
)
21858 as_bad (_("use of old and new-style options to set CPU type"));
21860 mcpu_cpu_opt
= legacy_cpu
;
21862 else if (!mcpu_cpu_opt
)
21863 mcpu_cpu_opt
= march_cpu_opt
;
21868 as_bad (_("use of old and new-style options to set FPU type"));
21870 mfpu_opt
= legacy_fpu
;
21872 else if (!mfpu_opt
)
21874 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
21875 || defined (TE_NetBSD) || defined (TE_VXWORKS))
21876 /* Some environments specify a default FPU. If they don't, infer it
21877 from the processor. */
21879 mfpu_opt
= mcpu_fpu_opt
;
21881 mfpu_opt
= march_fpu_opt
;
21883 mfpu_opt
= &fpu_default
;
21889 if (mcpu_cpu_opt
!= NULL
)
21890 mfpu_opt
= &fpu_default
;
21891 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
21892 mfpu_opt
= &fpu_arch_vfp_v2
;
21894 mfpu_opt
= &fpu_arch_fpa
;
21900 mcpu_cpu_opt
= &cpu_default
;
21901 selected_cpu
= cpu_default
;
21905 selected_cpu
= *mcpu_cpu_opt
;
21907 mcpu_cpu_opt
= &arm_arch_any
;
21910 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21912 autoselect_thumb_from_cpu_variant ();
21914 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
21916 #if defined OBJ_COFF || defined OBJ_ELF
21918 unsigned int flags
= 0;
21920 #if defined OBJ_ELF
21921 flags
= meabi_flags
;
21923 switch (meabi_flags
)
21925 case EF_ARM_EABI_UNKNOWN
:
21927 /* Set the flags in the private structure. */
21928 if (uses_apcs_26
) flags
|= F_APCS26
;
21929 if (support_interwork
) flags
|= F_INTERWORK
;
21930 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
21931 if (pic_code
) flags
|= F_PIC
;
21932 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
21933 flags
|= F_SOFT_FLOAT
;
21935 switch (mfloat_abi_opt
)
21937 case ARM_FLOAT_ABI_SOFT
:
21938 case ARM_FLOAT_ABI_SOFTFP
:
21939 flags
|= F_SOFT_FLOAT
;
21942 case ARM_FLOAT_ABI_HARD
:
21943 if (flags
& F_SOFT_FLOAT
)
21944 as_bad (_("hard-float conflicts with specified fpu"));
21948 /* Using pure-endian doubles (even if soft-float). */
21949 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
21950 flags
|= F_VFP_FLOAT
;
21952 #if defined OBJ_ELF
21953 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
21954 flags
|= EF_ARM_MAVERICK_FLOAT
;
21957 case EF_ARM_EABI_VER4
:
21958 case EF_ARM_EABI_VER5
:
21959 /* No additional flags to set. */
21966 bfd_set_private_flags (stdoutput
, flags
);
21968 /* We have run out flags in the COFF header to encode the
21969 status of ATPCS support, so instead we create a dummy,
21970 empty, debug section called .arm.atpcs. */
21975 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
21979 bfd_set_section_flags
21980 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
21981 bfd_set_section_size (stdoutput
, sec
, 0);
21982 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
21988 /* Record the CPU type as well. */
21989 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
21990 mach
= bfd_mach_arm_iWMMXt2
;
21991 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
21992 mach
= bfd_mach_arm_iWMMXt
;
21993 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
21994 mach
= bfd_mach_arm_XScale
;
21995 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
21996 mach
= bfd_mach_arm_ep9312
;
21997 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
21998 mach
= bfd_mach_arm_5TE
;
21999 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
22001 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22002 mach
= bfd_mach_arm_5T
;
22004 mach
= bfd_mach_arm_5
;
22006 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
22008 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22009 mach
= bfd_mach_arm_4T
;
22011 mach
= bfd_mach_arm_4
;
22013 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
22014 mach
= bfd_mach_arm_3M
;
22015 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
22016 mach
= bfd_mach_arm_3
;
22017 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
22018 mach
= bfd_mach_arm_2a
;
22019 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
22020 mach
= bfd_mach_arm_2
;
22022 mach
= bfd_mach_arm_unknown
;
22024 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
22027 /* Command line processing. */
22030 Invocation line includes a switch not recognized by the base assembler.
22031 See if it's a processor-specific option.
22033 This routine is somewhat complicated by the need for backwards
22034 compatibility (since older releases of gcc can't be changed).
22035 The new options try to make the interface as compatible as
22038 New options (supported) are:
22040 -mcpu=<cpu name> Assemble for selected processor
22041 -march=<architecture name> Assemble for selected architecture
22042 -mfpu=<fpu architecture> Assemble for selected FPU.
22043 -EB/-mbig-endian Big-endian
22044 -EL/-mlittle-endian Little-endian
22045 -k Generate PIC code
22046 -mthumb Start in Thumb mode
22047 -mthumb-interwork Code supports ARM/Thumb interworking
22049 -m[no-]warn-deprecated Warn about deprecated features
22051 For now we will also provide support for:
22053 -mapcs-32 32-bit Program counter
22054 -mapcs-26 26-bit Program counter
22055 -macps-float Floats passed in FP registers
22056 -mapcs-reentrant Reentrant code
22058 (sometime these will probably be replaced with -mapcs=<list of options>
22059 and -matpcs=<list of options>)
22061 The remaining options are only supported for back-wards compatibility.
22062 Cpu variants, the arm part is optional:
22063 -m[arm]1 Currently not supported.
22064 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22065 -m[arm]3 Arm 3 processor
22066 -m[arm]6[xx], Arm 6 processors
22067 -m[arm]7[xx][t][[d]m] Arm 7 processors
22068 -m[arm]8[10] Arm 8 processors
22069 -m[arm]9[20][tdmi] Arm 9 processors
22070 -mstrongarm[110[0]] StrongARM processors
22071 -mxscale XScale processors
22072 -m[arm]v[2345[t[e]]] Arm architectures
22073 -mall All (except the ARM1)
22075 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22076 -mfpe-old (No float load/store multiples)
22077 -mvfpxd VFP Single precision
22079 -mno-fpu Disable all floating point instructions
22081 The following CPU names are recognized:
22082 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22083 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22084 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22085 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22086 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22087 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22088 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22092 const char * md_shortopts
= "m:k";
22094 #ifdef ARM_BI_ENDIAN
22095 #define OPTION_EB (OPTION_MD_BASE + 0)
22096 #define OPTION_EL (OPTION_MD_BASE + 1)
22098 #if TARGET_BYTES_BIG_ENDIAN
22099 #define OPTION_EB (OPTION_MD_BASE + 0)
22101 #define OPTION_EL (OPTION_MD_BASE + 1)
22104 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22106 struct option md_longopts
[] =
22109 {"EB", no_argument
, NULL
, OPTION_EB
},
22112 {"EL", no_argument
, NULL
, OPTION_EL
},
22114 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
22115 {NULL
, no_argument
, NULL
, 0}
22118 size_t md_longopts_size
= sizeof (md_longopts
);
22120 struct arm_option_table
22122 char *option
; /* Option name to match. */
22123 char *help
; /* Help information. */
22124 int *var
; /* Variable to change. */
22125 int value
; /* What to change it to. */
22126 char *deprecated
; /* If non-null, print this message. */
22129 struct arm_option_table arm_opts
[] =
22131 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
22132 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
22133 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22134 &support_interwork
, 1, NULL
},
22135 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
22136 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
22137 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
22139 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
22140 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
22141 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
22142 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
22145 /* These are recognized by the assembler, but have no affect on code. */
22146 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
22147 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
22149 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
22150 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22151 &warn_on_deprecated
, 0, NULL
},
22152 {NULL
, NULL
, NULL
, 0, NULL
}
22155 struct arm_legacy_option_table
22157 char *option
; /* Option name to match. */
22158 const arm_feature_set
**var
; /* Variable to change. */
22159 const arm_feature_set value
; /* What to change it to. */
22160 char *deprecated
; /* If non-null, print this message. */
22163 const struct arm_legacy_option_table arm_legacy_opts
[] =
22165 /* DON'T add any new processors to this list -- we want the whole list
22166 to go away... Add them to the processors table instead. */
22167 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22168 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22169 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22170 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22171 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22172 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22173 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22174 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22175 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22176 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22177 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22178 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22179 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22180 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22181 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22182 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22183 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22184 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22185 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22186 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22187 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22188 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22189 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22190 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22191 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22192 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22193 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22194 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22195 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22196 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22197 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22198 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22199 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22200 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22201 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22202 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22203 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22204 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22205 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22206 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22207 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22208 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22209 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22210 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22211 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22212 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22213 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22214 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22215 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22216 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22217 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22218 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22219 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22220 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22221 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22222 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22223 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22224 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22225 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22226 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22227 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22228 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22229 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22230 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22231 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22232 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22233 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22234 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22235 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
22236 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
22237 N_("use -mcpu=strongarm110")},
22238 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
22239 N_("use -mcpu=strongarm1100")},
22240 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
22241 N_("use -mcpu=strongarm1110")},
22242 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
22243 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
22244 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
22246 /* Architecture variants -- don't add any more to this list either. */
22247 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22248 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22249 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22250 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22251 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22252 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22253 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22254 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22255 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22256 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22257 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22258 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22259 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22260 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22261 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22262 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22263 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22264 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22266 /* Floating point variants -- don't add any more to this list either. */
22267 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
22268 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
22269 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
22270 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
22271 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22273 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
22276 struct arm_cpu_option_table
22279 const arm_feature_set value
;
22280 /* For some CPUs we assume an FPU unless the user explicitly sets
22282 const arm_feature_set default_fpu
;
22283 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22285 const char *canonical_name
;
22288 /* This list should, at a minimum, contain all the cpu names
22289 recognized by GCC. */
22290 static const struct arm_cpu_option_table arm_cpus
[] =
22292 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
22293 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
22294 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
22295 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22296 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22297 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22298 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22299 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22300 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22301 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22302 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22303 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22304 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22305 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22306 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22307 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22308 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22309 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22310 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22311 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22312 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22313 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22314 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22315 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22316 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22317 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22318 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22319 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22320 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22321 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22322 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22323 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22324 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22325 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22326 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22327 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22328 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22329 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22330 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22331 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
22332 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22333 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22334 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22335 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22336 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22337 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22338 /* For V5 or later processors we default to using VFP; but the user
22339 should really set the FPU type explicitly. */
22340 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22341 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22342 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22343 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22344 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22345 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22346 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
22347 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22348 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22349 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
22350 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22351 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22352 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22353 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22354 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22355 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
22356 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22357 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22358 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22359 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
22360 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22361 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
22362 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22363 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
22364 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
22365 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
22366 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
22367 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"},
22368 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"},
22369 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
22370 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
22371 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
22372 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
22373 {"cortex-a5", ARM_ARCH_V7A
, FPU_NONE
, "Cortex-A5"},
22374 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22375 | FPU_NEON_EXT_V1
),
22377 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22378 | FPU_NEON_EXT_V1
),
22380 {"cortex-a15", ARM_ARCH_V7A
, FPU_ARCH_NEON_VFP_V4
,
22382 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"},
22383 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
22385 {"cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"},
22386 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"},
22387 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, "Cortex-M1"},
22388 {"cortex-m0", ARM_ARCH_V6M
, FPU_NONE
, "Cortex-M0"},
22389 /* ??? XSCALE is really an architecture. */
22390 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22391 /* ??? iwmmxt is not a processor. */
22392 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22393 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22394 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22396 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22397 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22400 struct arm_arch_option_table
22403 const arm_feature_set value
;
22404 const arm_feature_set default_fpu
;
22407 /* This list should, at a minimum, contain all the architecture names
22408 recognized by GCC. */
22409 static const struct arm_arch_option_table arm_archs
[] =
22411 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22412 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22413 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22414 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22415 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22416 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22417 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22418 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22419 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22420 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22421 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22422 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22423 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22424 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22425 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22426 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22427 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22428 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22429 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22430 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22431 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22432 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22433 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22434 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22435 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22436 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22437 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22438 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22439 /* The official spelling of the ARMv7 profile variants is the dashed form.
22440 Accept the non-dashed form for compatibility with old toolchains. */
22441 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22442 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22443 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22444 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22445 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22446 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22447 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22448 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22449 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22450 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22451 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22454 /* ISA extensions in the co-processor space. */
22455 struct arm_option_cpu_value_table
22458 const arm_feature_set value
;
22461 static const struct arm_option_cpu_value_table arm_extensions
[] =
22463 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
22464 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
22465 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
22466 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
22467 {NULL
, ARM_ARCH_NONE
}
22470 /* This list should, at a minimum, contain all the fpu names
22471 recognized by GCC. */
22472 static const struct arm_option_cpu_value_table arm_fpus
[] =
22474 {"softfpa", FPU_NONE
},
22475 {"fpe", FPU_ARCH_FPE
},
22476 {"fpe2", FPU_ARCH_FPE
},
22477 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
22478 {"fpa", FPU_ARCH_FPA
},
22479 {"fpa10", FPU_ARCH_FPA
},
22480 {"fpa11", FPU_ARCH_FPA
},
22481 {"arm7500fe", FPU_ARCH_FPA
},
22482 {"softvfp", FPU_ARCH_VFP
},
22483 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
22484 {"vfp", FPU_ARCH_VFP_V2
},
22485 {"vfp9", FPU_ARCH_VFP_V2
},
22486 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
22487 {"vfp10", FPU_ARCH_VFP_V2
},
22488 {"vfp10-r0", FPU_ARCH_VFP_V1
},
22489 {"vfpxd", FPU_ARCH_VFP_V1xD
},
22490 {"vfpv2", FPU_ARCH_VFP_V2
},
22491 {"vfpv3", FPU_ARCH_VFP_V3
},
22492 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
22493 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
22494 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
22495 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
22496 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
22497 {"arm1020t", FPU_ARCH_VFP_V1
},
22498 {"arm1020e", FPU_ARCH_VFP_V2
},
22499 {"arm1136jfs", FPU_ARCH_VFP_V2
},
22500 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
22501 {"maverick", FPU_ARCH_MAVERICK
},
22502 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
22503 {"neon-fp16", FPU_ARCH_NEON_FP16
},
22504 {"vfpv4", FPU_ARCH_VFP_V4
},
22505 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
22506 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
22507 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
22508 {NULL
, ARM_ARCH_NONE
}
22511 struct arm_option_value_table
22517 static const struct arm_option_value_table arm_float_abis
[] =
22519 {"hard", ARM_FLOAT_ABI_HARD
},
22520 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
22521 {"soft", ARM_FLOAT_ABI_SOFT
},
22526 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
22527 static const struct arm_option_value_table arm_eabis
[] =
22529 {"gnu", EF_ARM_EABI_UNKNOWN
},
22530 {"4", EF_ARM_EABI_VER4
},
22531 {"5", EF_ARM_EABI_VER5
},
22536 struct arm_long_option_table
22538 char * option
; /* Substring to match. */
22539 char * help
; /* Help information. */
22540 int (* func
) (char * subopt
); /* Function to decode sub-option. */
22541 char * deprecated
; /* If non-null, print this message. */
22545 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
22547 arm_feature_set
*ext_set
= (arm_feature_set
*)
22548 xmalloc (sizeof (arm_feature_set
));
22550 /* Copy the feature set, so that we can modify it. */
22551 *ext_set
= **opt_p
;
22554 while (str
!= NULL
&& *str
!= 0)
22556 const struct arm_option_cpu_value_table
* opt
;
22562 as_bad (_("invalid architectural extension"));
22567 ext
= strchr (str
, '+');
22570 optlen
= ext
- str
;
22572 optlen
= strlen (str
);
22576 as_bad (_("missing architectural extension"));
22580 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
22581 if (strncmp (opt
->name
, str
, optlen
) == 0)
22583 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
22587 if (opt
->name
== NULL
)
22589 as_bad (_("unknown architectural extension `%s'"), str
);
22600 arm_parse_cpu (char * str
)
22602 const struct arm_cpu_option_table
* opt
;
22603 char * ext
= strchr (str
, '+');
22607 optlen
= ext
- str
;
22609 optlen
= strlen (str
);
22613 as_bad (_("missing cpu name `%s'"), str
);
22617 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
22618 if (strncmp (opt
->name
, str
, optlen
) == 0)
22620 mcpu_cpu_opt
= &opt
->value
;
22621 mcpu_fpu_opt
= &opt
->default_fpu
;
22622 if (opt
->canonical_name
)
22623 strcpy (selected_cpu_name
, opt
->canonical_name
);
22628 for (i
= 0; i
< optlen
; i
++)
22629 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22630 selected_cpu_name
[i
] = 0;
22634 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
22639 as_bad (_("unknown cpu `%s'"), str
);
22644 arm_parse_arch (char * str
)
22646 const struct arm_arch_option_table
*opt
;
22647 char *ext
= strchr (str
, '+');
22651 optlen
= ext
- str
;
22653 optlen
= strlen (str
);
22657 as_bad (_("missing architecture name `%s'"), str
);
22661 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
22662 if (streq (opt
->name
, str
))
22664 march_cpu_opt
= &opt
->value
;
22665 march_fpu_opt
= &opt
->default_fpu
;
22666 strcpy (selected_cpu_name
, opt
->name
);
22669 return arm_parse_extension (ext
, &march_cpu_opt
);
22674 as_bad (_("unknown architecture `%s'\n"), str
);
22679 arm_parse_fpu (char * str
)
22681 const struct arm_option_cpu_value_table
* opt
;
22683 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22684 if (streq (opt
->name
, str
))
22686 mfpu_opt
= &opt
->value
;
22690 as_bad (_("unknown floating point format `%s'\n"), str
);
22695 arm_parse_float_abi (char * str
)
22697 const struct arm_option_value_table
* opt
;
22699 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
22700 if (streq (opt
->name
, str
))
22702 mfloat_abi_opt
= opt
->value
;
22706 as_bad (_("unknown floating point abi `%s'\n"), str
);
22712 arm_parse_eabi (char * str
)
22714 const struct arm_option_value_table
*opt
;
22716 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
22717 if (streq (opt
->name
, str
))
22719 meabi_flags
= opt
->value
;
22722 as_bad (_("unknown EABI `%s'\n"), str
);
22728 arm_parse_it_mode (char * str
)
22730 bfd_boolean ret
= TRUE
;
22732 if (streq ("arm", str
))
22733 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
22734 else if (streq ("thumb", str
))
22735 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
22736 else if (streq ("always", str
))
22737 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
22738 else if (streq ("never", str
))
22739 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
22742 as_bad (_("unknown implicit IT mode `%s', should be "\
22743 "arm, thumb, always, or never."), str
);
22750 struct arm_long_option_table arm_long_opts
[] =
22752 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
22753 arm_parse_cpu
, NULL
},
22754 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
22755 arm_parse_arch
, NULL
},
22756 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
22757 arm_parse_fpu
, NULL
},
22758 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
22759 arm_parse_float_abi
, NULL
},
22761 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
22762 arm_parse_eabi
, NULL
},
22764 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
22765 arm_parse_it_mode
, NULL
},
22766 {NULL
, NULL
, 0, NULL
}
22770 md_parse_option (int c
, char * arg
)
22772 struct arm_option_table
*opt
;
22773 const struct arm_legacy_option_table
*fopt
;
22774 struct arm_long_option_table
*lopt
;
22780 target_big_endian
= 1;
22786 target_big_endian
= 0;
22790 case OPTION_FIX_V4BX
:
22795 /* Listing option. Just ignore these, we don't support additional
22800 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22802 if (c
== opt
->option
[0]
22803 && ((arg
== NULL
&& opt
->option
[1] == 0)
22804 || streq (arg
, opt
->option
+ 1)))
22806 /* If the option is deprecated, tell the user. */
22807 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
22808 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22809 arg
? arg
: "", _(opt
->deprecated
));
22811 if (opt
->var
!= NULL
)
22812 *opt
->var
= opt
->value
;
22818 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
22820 if (c
== fopt
->option
[0]
22821 && ((arg
== NULL
&& fopt
->option
[1] == 0)
22822 || streq (arg
, fopt
->option
+ 1)))
22824 /* If the option is deprecated, tell the user. */
22825 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
22826 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22827 arg
? arg
: "", _(fopt
->deprecated
));
22829 if (fopt
->var
!= NULL
)
22830 *fopt
->var
= &fopt
->value
;
22836 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22838 /* These options are expected to have an argument. */
22839 if (c
== lopt
->option
[0]
22841 && strncmp (arg
, lopt
->option
+ 1,
22842 strlen (lopt
->option
+ 1)) == 0)
22844 /* If the option is deprecated, tell the user. */
22845 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
22846 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
22847 _(lopt
->deprecated
));
22849 /* Call the sup-option parser. */
22850 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
22861 md_show_usage (FILE * fp
)
22863 struct arm_option_table
*opt
;
22864 struct arm_long_option_table
*lopt
;
22866 fprintf (fp
, _(" ARM-specific assembler options:\n"));
22868 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22869 if (opt
->help
!= NULL
)
22870 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
22872 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22873 if (lopt
->help
!= NULL
)
22874 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
22878 -EB assemble code for a big-endian cpu\n"));
22883 -EL assemble code for a little-endian cpu\n"));
22887 --fix-v4bx Allow BX in ARMv4 code\n"));
22895 arm_feature_set flags
;
22896 } cpu_arch_ver_table
;
22898 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
22899 least features first. */
22900 static const cpu_arch_ver_table cpu_arch_ver
[] =
22906 {4, ARM_ARCH_V5TE
},
22907 {5, ARM_ARCH_V5TEJ
},
22911 {11, ARM_ARCH_V6M
},
22912 {8, ARM_ARCH_V6T2
},
22913 {10, ARM_ARCH_V7A
},
22914 {10, ARM_ARCH_V7R
},
22915 {10, ARM_ARCH_V7M
},
22919 /* Set an attribute if it has not already been set by the user. */
22921 aeabi_set_attribute_int (int tag
, int value
)
22924 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22925 || !attributes_set_explicitly
[tag
])
22926 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
22930 aeabi_set_attribute_string (int tag
, const char *value
)
22933 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22934 || !attributes_set_explicitly
[tag
])
22935 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
22938 /* Set the public EABI object attributes. */
22940 aeabi_set_public_attributes (void)
22943 arm_feature_set flags
;
22944 arm_feature_set tmp
;
22945 const cpu_arch_ver_table
*p
;
22947 /* Choose the architecture based on the capabilities of the requested cpu
22948 (if any) and/or the instructions actually used. */
22949 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
22950 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
22951 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
22952 /*Allow the user to override the reported architecture. */
22955 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
22956 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
22961 for (p
= cpu_arch_ver
; p
->val
; p
++)
22963 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
22966 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
22970 /* The table lookup above finds the last architecture to contribute
22971 a new feature. Unfortunately, Tag13 is a subset of the union of
22972 v6T2 and v7-M, so it is never seen as contributing a new feature.
22973 We can not search for the last entry which is entirely used,
22974 because if no CPU is specified we build up only those flags
22975 actually used. Perhaps we should separate out the specified
22976 and implicit cases. Avoid taking this path for -march=all by
22977 checking for contradictory v7-A / v7-M features. */
22979 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
22980 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
22981 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
22984 /* Tag_CPU_name. */
22985 if (selected_cpu_name
[0])
22989 q
= selected_cpu_name
;
22990 if (strncmp (q
, "armv", 4) == 0)
22995 for (i
= 0; q
[i
]; i
++)
22996 q
[i
] = TOUPPER (q
[i
]);
22998 aeabi_set_attribute_string (Tag_CPU_name
, q
);
23001 /* Tag_CPU_arch. */
23002 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
23004 /* Tag_CPU_arch_profile. */
23005 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
23006 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
23007 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
23008 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
23009 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
23010 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
23012 /* Tag_ARM_ISA_use. */
23013 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
23015 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
23017 /* Tag_THUMB_ISA_use. */
23018 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
23020 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
23021 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
23023 /* Tag_VFP_arch. */
23024 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
23025 aeabi_set_attribute_int (Tag_VFP_arch
,
23026 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
23028 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
23029 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
23030 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
23031 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
23032 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
23033 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
23034 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
23035 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
23036 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
23038 /* Tag_ABI_HardFP_use. */
23039 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
23040 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
23041 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
23043 /* Tag_WMMX_arch. */
23044 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
23045 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
23046 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
23047 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
23049 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23050 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
23051 aeabi_set_attribute_int
23052 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
23055 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23056 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
23057 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
23060 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
))
23061 aeabi_set_attribute_int (Tag_DIV_use
, 0);
23062 /* Fill this in when gas supports v7a sdiv/udiv.
23063 else if (... v7a with div extension used ...)
23064 aeabi_set_attribute_int (Tag_DIV_use, 2); */
23066 aeabi_set_attribute_int (Tag_DIV_use
, 1);
23069 /* Add the default contents for the .ARM.attributes section. */
23073 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23076 aeabi_set_public_attributes ();
23078 #endif /* OBJ_ELF */
23081 /* Parse a .cpu directive. */
23084 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
23086 const struct arm_cpu_option_table
*opt
;
23090 name
= input_line_pointer
;
23091 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23092 input_line_pointer
++;
23093 saved_char
= *input_line_pointer
;
23094 *input_line_pointer
= 0;
23096 /* Skip the first "all" entry. */
23097 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
23098 if (streq (opt
->name
, name
))
23100 mcpu_cpu_opt
= &opt
->value
;
23101 selected_cpu
= opt
->value
;
23102 if (opt
->canonical_name
)
23103 strcpy (selected_cpu_name
, opt
->canonical_name
);
23107 for (i
= 0; opt
->name
[i
]; i
++)
23108 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23109 selected_cpu_name
[i
] = 0;
23111 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23112 *input_line_pointer
= saved_char
;
23113 demand_empty_rest_of_line ();
23116 as_bad (_("unknown cpu `%s'"), name
);
23117 *input_line_pointer
= saved_char
;
23118 ignore_rest_of_line ();
23122 /* Parse a .arch directive. */
23125 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
23127 const struct arm_arch_option_table
*opt
;
23131 name
= input_line_pointer
;
23132 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23133 input_line_pointer
++;
23134 saved_char
= *input_line_pointer
;
23135 *input_line_pointer
= 0;
23137 /* Skip the first "all" entry. */
23138 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23139 if (streq (opt
->name
, name
))
23141 mcpu_cpu_opt
= &opt
->value
;
23142 selected_cpu
= opt
->value
;
23143 strcpy (selected_cpu_name
, opt
->name
);
23144 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23145 *input_line_pointer
= saved_char
;
23146 demand_empty_rest_of_line ();
23150 as_bad (_("unknown architecture `%s'\n"), name
);
23151 *input_line_pointer
= saved_char
;
23152 ignore_rest_of_line ();
23156 /* Parse a .object_arch directive. */
23159 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
23161 const struct arm_arch_option_table
*opt
;
23165 name
= input_line_pointer
;
23166 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23167 input_line_pointer
++;
23168 saved_char
= *input_line_pointer
;
23169 *input_line_pointer
= 0;
23171 /* Skip the first "all" entry. */
23172 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23173 if (streq (opt
->name
, name
))
23175 object_arch
= &opt
->value
;
23176 *input_line_pointer
= saved_char
;
23177 demand_empty_rest_of_line ();
23181 as_bad (_("unknown architecture `%s'\n"), name
);
23182 *input_line_pointer
= saved_char
;
23183 ignore_rest_of_line ();
23186 /* Parse a .fpu directive. */
23189 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
23191 const struct arm_option_cpu_value_table
*opt
;
23195 name
= input_line_pointer
;
23196 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23197 input_line_pointer
++;
23198 saved_char
= *input_line_pointer
;
23199 *input_line_pointer
= 0;
23201 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23202 if (streq (opt
->name
, name
))
23204 mfpu_opt
= &opt
->value
;
23205 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23206 *input_line_pointer
= saved_char
;
23207 demand_empty_rest_of_line ();
23211 as_bad (_("unknown floating point format `%s'\n"), name
);
23212 *input_line_pointer
= saved_char
;
23213 ignore_rest_of_line ();
23216 /* Copy symbol information. */
23219 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
23221 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
23225 /* Given a symbolic attribute NAME, return the proper integer value.
23226 Returns -1 if the attribute is not known. */
23229 arm_convert_symbolic_attribute (const char *name
)
23231 static const struct
23236 attribute_table
[] =
23238 /* When you modify this table you should
23239 also modify the list in doc/c-arm.texi. */
23240 #define T(tag) {#tag, tag}
23241 T (Tag_CPU_raw_name
),
23244 T (Tag_CPU_arch_profile
),
23245 T (Tag_ARM_ISA_use
),
23246 T (Tag_THUMB_ISA_use
),
23250 T (Tag_Advanced_SIMD_arch
),
23251 T (Tag_PCS_config
),
23252 T (Tag_ABI_PCS_R9_use
),
23253 T (Tag_ABI_PCS_RW_data
),
23254 T (Tag_ABI_PCS_RO_data
),
23255 T (Tag_ABI_PCS_GOT_use
),
23256 T (Tag_ABI_PCS_wchar_t
),
23257 T (Tag_ABI_FP_rounding
),
23258 T (Tag_ABI_FP_denormal
),
23259 T (Tag_ABI_FP_exceptions
),
23260 T (Tag_ABI_FP_user_exceptions
),
23261 T (Tag_ABI_FP_number_model
),
23262 T (Tag_ABI_align_needed
),
23263 T (Tag_ABI_align8_needed
),
23264 T (Tag_ABI_align_preserved
),
23265 T (Tag_ABI_align8_preserved
),
23266 T (Tag_ABI_enum_size
),
23267 T (Tag_ABI_HardFP_use
),
23268 T (Tag_ABI_VFP_args
),
23269 T (Tag_ABI_WMMX_args
),
23270 T (Tag_ABI_optimization_goals
),
23271 T (Tag_ABI_FP_optimization_goals
),
23272 T (Tag_compatibility
),
23273 T (Tag_CPU_unaligned_access
),
23274 T (Tag_FP_HP_extension
),
23275 T (Tag_VFP_HP_extension
),
23276 T (Tag_ABI_FP_16bit_format
),
23277 T (Tag_MPextension_use
),
23279 T (Tag_nodefaults
),
23280 T (Tag_also_compatible_with
),
23281 T (Tag_conformance
),
23283 T (Tag_Virtualization_use
),
23284 /* We deliberately do not include Tag_MPextension_use_legacy. */
23292 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
23293 if (streq (name
, attribute_table
[i
].name
))
23294 return attribute_table
[i
].tag
;
23300 /* Apply sym value for relocations only in the case that
23301 they are for local symbols and you have the respective
23302 architectural feature for blx and simple switches. */
23304 arm_apply_sym_value (struct fix
* fixP
)
23307 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23308 && !S_IS_EXTERNAL (fixP
->fx_addsy
))
23310 switch (fixP
->fx_r_type
)
23312 case BFD_RELOC_ARM_PCREL_BLX
:
23313 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23314 if (ARM_IS_FUNC (fixP
->fx_addsy
))
23318 case BFD_RELOC_ARM_PCREL_CALL
:
23319 case BFD_RELOC_THUMB_PCREL_BLX
:
23320 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
23331 #endif /* OBJ_ELF */