1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
305 static const arm_feature_set mve_ext
=
306 ARM_FEATURE_COPROC (FPU_MVE
);
307 static const arm_feature_set mve_fp_ext
=
308 ARM_FEATURE_COPROC (FPU_MVE_FP
);
310 static const arm_feature_set fpu_vfp_fp16
=
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
312 static const arm_feature_set fpu_neon_ext_fma
=
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
315 static const arm_feature_set fpu_vfp_ext_fma
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
317 static const arm_feature_set fpu_vfp_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
319 static const arm_feature_set fpu_vfp_ext_armv8xd
=
320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
321 static const arm_feature_set fpu_neon_ext_armv8
=
322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
323 static const arm_feature_set fpu_crypto_ext_armv8
=
324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
325 static const arm_feature_set crc_ext_armv8
=
326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
327 static const arm_feature_set fpu_neon_ext_v8_1
=
328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
329 static const arm_feature_set fpu_neon_ext_dotprod
=
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
332 static int mfloat_abi_opt
= -1;
333 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
335 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
336 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
338 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
339 /* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
342 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
343 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
344 static arm_feature_set selected_fpu
= FPU_NONE
;
345 /* Feature bits selected by the last .object_arch directive. */
346 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
347 /* Must be long enough to hold any of the names in arm_cpus. */
348 static char selected_cpu_name
[20];
350 extern FLONUM_TYPE generic_floating_point_number
;
352 /* Return if no cpu was selected on command-line. */
354 no_cpu_selected (void)
356 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
361 static int meabi_flags
= EABI_DEFAULT
;
363 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
366 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
371 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
376 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
377 symbolS
* GOT_symbol
;
380 /* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
384 static int thumb_mode
= 0;
385 /* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388 #define MODE_RECORDED (1 << 4)
390 /* Specifies the intrinsic IT insn behavior mode. */
391 enum implicit_it_mode
393 IMPLICIT_IT_MODE_NEVER
= 0x00,
394 IMPLICIT_IT_MODE_ARM
= 0x01,
395 IMPLICIT_IT_MODE_THUMB
= 0x02,
396 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
398 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
400 /* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
412 Important differences from the old Thumb mode:
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
423 static bfd_boolean unified_syntax
= FALSE
;
425 /* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429 const char arm_symbol_chars
[] = "#[]{}";
444 enum neon_el_type type
;
448 #define NEON_MAX_TYPE_ELS 4
452 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
456 enum pred_instruction_type
462 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
463 if inside, should be the last one. */
464 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
465 i.e. BKPT and NOP. */
466 IT_INSN
, /* The IT insn has been parsed. */
467 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
468 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
469 a predication code. */
470 MVE_UNPREDICABLE_INSN
/* MVE instruction that is non-predicable. */
473 /* The maximum number of operands we need. */
474 #define ARM_IT_MAX_OPERANDS 6
475 #define ARM_IT_MAX_RELOCS 3
480 unsigned long instruction
;
484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
488 struct neon_type vectype
;
489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
497 bfd_reloc_code_real_type type
;
500 } relocs
[ARM_IT_MAX_RELOCS
];
502 enum pred_instruction_type pred_insn_type
;
508 struct neon_type_el vectype
;
509 unsigned present
: 1; /* Operand present. */
510 unsigned isreg
: 1; /* Operand was a register. */
511 unsigned immisreg
: 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
513 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
517 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
518 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
522 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
523 unsigned isquad
: 1; /* Operand is SIMD quad register. */
524 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
525 unsigned iszr
: 1; /* Operand is ZR register. */
526 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
527 unsigned writeback
: 1; /* Operand has trailing ! */
528 unsigned preind
: 1; /* Preindexed address. */
529 unsigned postind
: 1; /* Postindexed address. */
530 unsigned negative
: 1; /* Index register was negated. */
531 unsigned shifted
: 1; /* Shift applied to operation. */
532 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
533 } operands
[ARM_IT_MAX_OPERANDS
];
536 static struct arm_it inst
;
538 #define NUM_FLOAT_VALS 8
540 const char * fp_const
[] =
542 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
545 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
555 #define CP_T_X 0x00008000
556 #define CP_T_Y 0x00400000
558 #define CONDS_BIT 0x00100000
559 #define LOAD_BIT 0x00100000
561 #define DOUBLE_LOAD_FLAG 0x00000001
565 const char * template_name
;
569 #define COND_ALWAYS 0xE
573 const char * template_name
;
577 struct asm_barrier_opt
579 const char * template_name
;
581 const arm_feature_set arch
;
584 /* The bit that distinguishes CPSR and SPSR. */
585 #define SPSR_BIT (1 << 22)
587 /* The individual PSR flag bits. */
588 #define PSR_c (1 << 16)
589 #define PSR_x (1 << 17)
590 #define PSR_s (1 << 18)
591 #define PSR_f (1 << 19)
596 bfd_reloc_code_real_type reloc
;
601 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
602 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
607 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
610 /* Bits for DEFINED field in neon_typed_alias. */
611 #define NTA_HASTYPE 1
612 #define NTA_HASINDEX 2
614 struct neon_typed_alias
616 unsigned char defined
;
618 struct neon_type_el eltype
;
621 /* ARM register categories. This includes coprocessor numbers and various
622 architecture extensions' registers. Each entry should have an error message
623 in reg_expected_msgs below. */
653 /* Structure for a hash table entry for a register.
654 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
655 information which states whether a vector type or index is specified (for a
656 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
662 unsigned char builtin
;
663 struct neon_typed_alias
* neon
;
666 /* Diagnostics used when we don't get a register of the expected type. */
667 const char * const reg_expected_msgs
[] =
669 [REG_TYPE_RN
] = N_("ARM register expected"),
670 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
671 [REG_TYPE_CN
] = N_("co-processor register expected"),
672 [REG_TYPE_FN
] = N_("FPA register expected"),
673 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
674 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
675 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
676 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
677 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
678 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
679 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
681 [REG_TYPE_VFC
] = N_("VFP system register expected"),
682 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
683 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
684 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
685 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
686 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
687 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
688 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
689 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
690 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
691 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
692 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
693 [REG_TYPE_RNB
] = N_("")
696 /* Some well known registers that we refer to directly elsewhere. */
702 /* ARM instructions take 4bytes in the object file, Thumb instructions
708 /* Basic string to match. */
709 const char * template_name
;
711 /* Parameters to instruction. */
712 unsigned int operands
[8];
714 /* Conditional tag - see opcode_lookup. */
715 unsigned int tag
: 4;
717 /* Basic instruction code. */
720 /* Thumb-format instruction code. */
723 /* Which architecture variant provides this instruction. */
724 const arm_feature_set
* avariant
;
725 const arm_feature_set
* tvariant
;
727 /* Function to call to encode instruction in ARM format. */
728 void (* aencode
) (void);
730 /* Function to call to encode instruction in Thumb format. */
731 void (* tencode
) (void);
733 /* Indicates whether this instruction may be vector predicated. */
734 unsigned int mayBeVecPred
: 1;
737 /* Defines for various bits that we will want to toggle. */
738 #define INST_IMMEDIATE 0x02000000
739 #define OFFSET_REG 0x02000000
740 #define HWOFFSET_IMM 0x00400000
741 #define SHIFT_BY_REG 0x00000010
742 #define PRE_INDEX 0x01000000
743 #define INDEX_UP 0x00800000
744 #define WRITE_BACK 0x00200000
745 #define LDM_TYPE_2_OR_3 0x00400000
746 #define CPSI_MMOD 0x00020000
748 #define LITERAL_MASK 0xf000f000
749 #define OPCODE_MASK 0xfe1fffff
750 #define V4_STR_BIT 0x00000020
751 #define VLDR_VMOV_SAME 0x0040f000
753 #define T2_SUBS_PC_LR 0xf3de8f00
755 #define DATA_OP_SHIFT 21
756 #define SBIT_SHIFT 20
758 #define T2_OPCODE_MASK 0xfe1fffff
759 #define T2_DATA_OP_SHIFT 21
760 #define T2_SBIT_SHIFT 20
762 #define A_COND_MASK 0xf0000000
763 #define A_PUSH_POP_OP_MASK 0x0fff0000
765 /* Opcodes for pushing/poping registers to/from the stack. */
766 #define A1_OPCODE_PUSH 0x092d0000
767 #define A2_OPCODE_PUSH 0x052d0004
768 #define A2_OPCODE_POP 0x049d0004
770 /* Codes to distinguish the arithmetic instructions. */
781 #define OPCODE_CMP 10
782 #define OPCODE_CMN 11
783 #define OPCODE_ORR 12
784 #define OPCODE_MOV 13
785 #define OPCODE_BIC 14
786 #define OPCODE_MVN 15
788 #define T2_OPCODE_AND 0
789 #define T2_OPCODE_BIC 1
790 #define T2_OPCODE_ORR 2
791 #define T2_OPCODE_ORN 3
792 #define T2_OPCODE_EOR 4
793 #define T2_OPCODE_ADD 8
794 #define T2_OPCODE_ADC 10
795 #define T2_OPCODE_SBC 11
796 #define T2_OPCODE_SUB 13
797 #define T2_OPCODE_RSB 14
799 #define T_OPCODE_MUL 0x4340
800 #define T_OPCODE_TST 0x4200
801 #define T_OPCODE_CMN 0x42c0
802 #define T_OPCODE_NEG 0x4240
803 #define T_OPCODE_MVN 0x43c0
805 #define T_OPCODE_ADD_R3 0x1800
806 #define T_OPCODE_SUB_R3 0x1a00
807 #define T_OPCODE_ADD_HI 0x4400
808 #define T_OPCODE_ADD_ST 0xb000
809 #define T_OPCODE_SUB_ST 0xb080
810 #define T_OPCODE_ADD_SP 0xa800
811 #define T_OPCODE_ADD_PC 0xa000
812 #define T_OPCODE_ADD_I8 0x3000
813 #define T_OPCODE_SUB_I8 0x3800
814 #define T_OPCODE_ADD_I3 0x1c00
815 #define T_OPCODE_SUB_I3 0x1e00
817 #define T_OPCODE_ASR_R 0x4100
818 #define T_OPCODE_LSL_R 0x4080
819 #define T_OPCODE_LSR_R 0x40c0
820 #define T_OPCODE_ROR_R 0x41c0
821 #define T_OPCODE_ASR_I 0x1000
822 #define T_OPCODE_LSL_I 0x0000
823 #define T_OPCODE_LSR_I 0x0800
825 #define T_OPCODE_MOV_I8 0x2000
826 #define T_OPCODE_CMP_I8 0x2800
827 #define T_OPCODE_CMP_LR 0x4280
828 #define T_OPCODE_MOV_HR 0x4600
829 #define T_OPCODE_CMP_HR 0x4500
831 #define T_OPCODE_LDR_PC 0x4800
832 #define T_OPCODE_LDR_SP 0x9800
833 #define T_OPCODE_STR_SP 0x9000
834 #define T_OPCODE_LDR_IW 0x6800
835 #define T_OPCODE_STR_IW 0x6000
836 #define T_OPCODE_LDR_IH 0x8800
837 #define T_OPCODE_STR_IH 0x8000
838 #define T_OPCODE_LDR_IB 0x7800
839 #define T_OPCODE_STR_IB 0x7000
840 #define T_OPCODE_LDR_RW 0x5800
841 #define T_OPCODE_STR_RW 0x5000
842 #define T_OPCODE_LDR_RH 0x5a00
843 #define T_OPCODE_STR_RH 0x5200
844 #define T_OPCODE_LDR_RB 0x5c00
845 #define T_OPCODE_STR_RB 0x5400
847 #define T_OPCODE_PUSH 0xb400
848 #define T_OPCODE_POP 0xbc00
850 #define T_OPCODE_BRANCH 0xe000
852 #define THUMB_SIZE 2 /* Size of thumb instruction. */
853 #define THUMB_PP_PC_LR 0x0100
854 #define THUMB_LOAD_BIT 0x0800
855 #define THUMB2_LOAD_BIT 0x00100000
857 #define BAD_SYNTAX _("syntax error")
858 #define BAD_ARGS _("bad arguments to instruction")
859 #define BAD_SP _("r13 not allowed here")
860 #define BAD_PC _("r15 not allowed here")
861 #define BAD_ODD _("Odd register not allowed here")
862 #define BAD_EVEN _("Even register not allowed here")
863 #define BAD_COND _("instruction cannot be conditional")
864 #define BAD_OVERLAP _("registers may not be the same")
865 #define BAD_HIREG _("lo register required")
866 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
867 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
868 #define BAD_BRANCH _("branch must be last instruction in IT block")
869 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
870 #define BAD_NOT_IT _("instruction not allowed in IT block")
871 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
872 #define BAD_FPU _("selected FPU does not support instruction")
873 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
874 #define BAD_OUT_VPT \
875 _("vector predicated instruction should be in VPT/VPST block")
876 #define BAD_IT_COND _("incorrect condition in IT block")
877 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
878 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
879 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
880 #define BAD_PC_ADDRESSING \
881 _("cannot use register index with PC-relative addressing")
882 #define BAD_PC_WRITEBACK \
883 _("cannot use writeback with PC-relative addressing")
884 #define BAD_RANGE _("branch out of range")
885 #define BAD_FP16 _("selected processor does not support fp16 instruction")
886 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
887 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
888 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
890 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
892 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
894 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
896 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
897 #define BAD_MVE_AUTO \
898 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
899 " use a valid -march or -mcpu option.")
900 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
901 "and source operands makes instruction UNPREDICTABLE")
902 #define BAD_EL_TYPE _("bad element type for instruction")
903 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
905 static struct hash_control
* arm_ops_hsh
;
906 static struct hash_control
* arm_cond_hsh
;
907 static struct hash_control
* arm_vcond_hsh
;
908 static struct hash_control
* arm_shift_hsh
;
909 static struct hash_control
* arm_psr_hsh
;
910 static struct hash_control
* arm_v7m_psr_hsh
;
911 static struct hash_control
* arm_reg_hsh
;
912 static struct hash_control
* arm_reloc_hsh
;
913 static struct hash_control
* arm_barrier_opt_hsh
;
915 /* Stuff needed to resolve the label ambiguity
924 symbolS
* last_label_seen
;
925 static int label_is_thumb_function_name
= FALSE
;
927 /* Literal pool structure. Held on a per-section
928 and per-sub-section basis. */
930 #define MAX_LITERAL_POOL_SIZE 1024
931 typedef struct literal_pool
933 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
934 unsigned int next_free_entry
;
940 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
942 struct literal_pool
* next
;
943 unsigned int alignment
;
946 /* Pointer to a linked list of literal pools. */
947 literal_pool
* list_of_pools
= NULL
;
949 typedef enum asmfunc_states
952 WAITING_ASMFUNC_NAME
,
956 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
959 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
961 static struct current_pred now_pred
;
965 now_pred_compatible (int cond
)
967 return (cond
& ~1) == (now_pred
.cc
& ~1);
971 conditional_insn (void)
973 return inst
.cond
!= COND_ALWAYS
;
976 static int in_pred_block (void);
978 static int handle_pred_state (void);
980 static void force_automatic_it_block_close (void);
982 static void it_fsm_post_encode (void);
984 #define set_pred_insn_type(type) \
987 inst.pred_insn_type = type; \
988 if (handle_pred_state () == FAIL) \
993 #define set_pred_insn_type_nonvoid(type, failret) \
996 inst.pred_insn_type = type; \
997 if (handle_pred_state () == FAIL) \
1002 #define set_pred_insn_type_last() \
1005 if (inst.cond == COND_ALWAYS) \
1006 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1008 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1014 /* This array holds the chars that always start a comment. If the
1015 pre-processor is disabled, these aren't very useful. */
1016 char arm_comment_chars
[] = "@";
1018 /* This array holds the chars that only start a comment at the beginning of
1019 a line. If the line seems to have the form '# 123 filename'
1020 .line and .file directives will appear in the pre-processed output. */
1021 /* Note that input_file.c hand checks for '#' at the beginning of the
1022 first line of the input file. This is because the compiler outputs
1023 #NO_APP at the beginning of its output. */
1024 /* Also note that comments like this one will always work. */
1025 const char line_comment_chars
[] = "#";
1027 char arm_line_separator_chars
[] = ";";
1029 /* Chars that can be used to separate mant
1030 from exp in floating point numbers. */
1031 const char EXP_CHARS
[] = "eE";
1033 /* Chars that mean this number is a floating point constant. */
1034 /* As in 0f12.456 */
1035 /* or 0d1.2345e12 */
1037 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
1039 /* Prefix characters that indicate the start of an immediate
1041 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1043 /* Separator character handling. */
1045 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1048 skip_past_char (char ** str
, char c
)
1050 /* PR gas/14987: Allow for whitespace before the expected character. */
1051 skip_whitespace (*str
);
1062 #define skip_past_comma(str) skip_past_char (str, ',')
1064 /* Arithmetic expressions (possibly involving symbols). */
1066 /* Return TRUE if anything in the expression is a bignum. */
1069 walk_no_bignums (symbolS
* sp
)
1071 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1074 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1076 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1077 || (symbol_get_value_expression (sp
)->X_op_symbol
1078 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1084 static bfd_boolean in_my_get_expression
= FALSE
;
1086 /* Third argument to my_get_expression. */
1087 #define GE_NO_PREFIX 0
1088 #define GE_IMM_PREFIX 1
1089 #define GE_OPT_PREFIX 2
1090 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1091 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1092 #define GE_OPT_PREFIX_BIG 3
1095 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1099 /* In unified syntax, all prefixes are optional. */
1101 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1104 switch (prefix_mode
)
1106 case GE_NO_PREFIX
: break;
1108 if (!is_immediate_prefix (**str
))
1110 inst
.error
= _("immediate expression requires a # prefix");
1116 case GE_OPT_PREFIX_BIG
:
1117 if (is_immediate_prefix (**str
))
1124 memset (ep
, 0, sizeof (expressionS
));
1126 save_in
= input_line_pointer
;
1127 input_line_pointer
= *str
;
1128 in_my_get_expression
= TRUE
;
1130 in_my_get_expression
= FALSE
;
1132 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1134 /* We found a bad or missing expression in md_operand(). */
1135 *str
= input_line_pointer
;
1136 input_line_pointer
= save_in
;
1137 if (inst
.error
== NULL
)
1138 inst
.error
= (ep
->X_op
== O_absent
1139 ? _("missing expression") :_("bad expression"));
1143 /* Get rid of any bignums now, so that we don't generate an error for which
1144 we can't establish a line number later on. Big numbers are never valid
1145 in instructions, which is where this routine is always called. */
1146 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1147 && (ep
->X_op
== O_big
1148 || (ep
->X_add_symbol
1149 && (walk_no_bignums (ep
->X_add_symbol
)
1151 && walk_no_bignums (ep
->X_op_symbol
))))))
1153 inst
.error
= _("invalid constant");
1154 *str
= input_line_pointer
;
1155 input_line_pointer
= save_in
;
1159 *str
= input_line_pointer
;
1160 input_line_pointer
= save_in
;
1164 /* Turn a string in input_line_pointer into a floating point constant
1165 of type TYPE, and store the appropriate bytes in *LITP. The number
1166 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1167 returned, or NULL on OK.
1169 Note that fp constants aren't represent in the normal way on the ARM.
1170 In big endian mode, things are as expected. However, in little endian
1171 mode fp constants are big-endian word-wise, and little-endian byte-wise
1172 within the words. For example, (double) 1.1 in big endian mode is
1173 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1174 the byte sequence 99 99 f1 3f 9a 99 99 99.
1176 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1179 md_atof (int type
, char * litP
, int * sizeP
)
1182 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1214 return _("Unrecognized or unsupported floating point constant");
1217 t
= atof_ieee (input_line_pointer
, type
, words
);
1219 input_line_pointer
= t
;
1220 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1222 if (target_big_endian
)
1224 for (i
= 0; i
< prec
; i
++)
1226 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1227 litP
+= sizeof (LITTLENUM_TYPE
);
1232 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1233 for (i
= prec
- 1; i
>= 0; i
--)
1235 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1236 litP
+= sizeof (LITTLENUM_TYPE
);
1239 /* For a 4 byte float the order of elements in `words' is 1 0.
1240 For an 8 byte float the order is 1 0 3 2. */
1241 for (i
= 0; i
< prec
; i
+= 2)
1243 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1244 sizeof (LITTLENUM_TYPE
));
1245 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1246 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1247 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1254 /* We handle all bad expressions here, so that we can report the faulty
1255 instruction in the error message. */
1258 md_operand (expressionS
* exp
)
1260 if (in_my_get_expression
)
1261 exp
->X_op
= O_illegal
;
1264 /* Immediate values. */
1267 /* Generic immediate-value read function for use in directives.
1268 Accepts anything that 'expression' can fold to a constant.
1269 *val receives the number. */
1272 immediate_for_directive (int *val
)
1275 exp
.X_op
= O_illegal
;
1277 if (is_immediate_prefix (*input_line_pointer
))
1279 input_line_pointer
++;
1283 if (exp
.X_op
!= O_constant
)
1285 as_bad (_("expected #constant"));
1286 ignore_rest_of_line ();
1289 *val
= exp
.X_add_number
;
1294 /* Register parsing. */
1296 /* Generic register parser. CCP points to what should be the
1297 beginning of a register name. If it is indeed a valid register
1298 name, advance CCP over it and return the reg_entry structure;
1299 otherwise return NULL. Does not issue diagnostics. */
1301 static struct reg_entry
*
1302 arm_reg_parse_multi (char **ccp
)
1306 struct reg_entry
*reg
;
1308 skip_whitespace (start
);
1310 #ifdef REGISTER_PREFIX
1311 if (*start
!= REGISTER_PREFIX
)
1315 #ifdef OPTIONAL_REGISTER_PREFIX
1316 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1321 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1326 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1328 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1338 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1339 enum arm_reg_type type
)
1341 /* Alternative syntaxes are accepted for a few register classes. */
1348 /* Generic coprocessor register names are allowed for these. */
1349 if (reg
&& reg
->type
== REG_TYPE_CN
)
1354 /* For backward compatibility, a bare number is valid here. */
1356 unsigned long processor
= strtoul (start
, ccp
, 10);
1357 if (*ccp
!= start
&& processor
<= 15)
1362 case REG_TYPE_MMXWC
:
1363 /* WC includes WCG. ??? I'm not sure this is true for all
1364 instructions that take WC registers. */
1365 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1376 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1377 return value is the register number or FAIL. */
1380 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1383 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1386 /* Do not allow a scalar (reg+index) to parse as a register. */
1387 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1390 if (reg
&& reg
->type
== type
)
1393 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1400 /* Parse a Neon type specifier. *STR should point at the leading '.'
1401 character. Does no verification at this stage that the type fits the opcode
1408 Can all be legally parsed by this function.
1410 Fills in neon_type struct pointer with parsed information, and updates STR
1411 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1412 type, FAIL if not. */
1415 parse_neon_type (struct neon_type
*type
, char **str
)
1422 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1424 enum neon_el_type thistype
= NT_untyped
;
1425 unsigned thissize
= -1u;
1432 /* Just a size without an explicit type. */
1436 switch (TOLOWER (*ptr
))
1438 case 'i': thistype
= NT_integer
; break;
1439 case 'f': thistype
= NT_float
; break;
1440 case 'p': thistype
= NT_poly
; break;
1441 case 's': thistype
= NT_signed
; break;
1442 case 'u': thistype
= NT_unsigned
; break;
1444 thistype
= NT_float
;
1449 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1455 /* .f is an abbreviation for .f32. */
1456 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1461 thissize
= strtoul (ptr
, &ptr
, 10);
1463 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1466 as_bad (_("bad size %d in type specifier"), thissize
);
1474 type
->el
[type
->elems
].type
= thistype
;
1475 type
->el
[type
->elems
].size
= thissize
;
1480 /* Empty/missing type is not a successful parse. */
1481 if (type
->elems
== 0)
1489 /* Errors may be set multiple times during parsing or bit encoding
1490 (particularly in the Neon bits), but usually the earliest error which is set
1491 will be the most meaningful. Avoid overwriting it with later (cascading)
1492 errors by calling this function. */
1495 first_error (const char *err
)
1501 /* Parse a single type, e.g. ".s32", leading period included. */
1503 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1506 struct neon_type optype
;
1510 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1512 if (optype
.elems
== 1)
1513 *vectype
= optype
.el
[0];
1516 first_error (_("only one type should be specified for operand"));
1522 first_error (_("vector type expected"));
1534 /* Special meanings for indices (which have a range of 0-7), which will fit into
1537 #define NEON_ALL_LANES 15
1538 #define NEON_INTERLEAVE_LANES 14
1540 /* Record a use of the given feature. */
1542 record_feature_use (const arm_feature_set
*feature
)
1545 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1547 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1550 /* If the given feature available in the selected CPU, mark it as used.
1551 Returns TRUE iff feature is available. */
1553 mark_feature_used (const arm_feature_set
*feature
)
1556 /* Do not support the use of MVE only instructions when in auto-detection or
1558 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1559 && ARM_CPU_IS_ANY (cpu_variant
))
1561 first_error (BAD_MVE_AUTO
);
1564 /* Ensure the option is valid on the current architecture. */
1565 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1568 /* Add the appropriate architecture feature for the barrier option used.
1570 record_feature_use (feature
);
1575 /* Parse either a register or a scalar, with an optional type. Return the
1576 register number, and optionally fill in the actual type of the register
1577 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1578 type/index information in *TYPEINFO. */
1581 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1582 enum arm_reg_type
*rtype
,
1583 struct neon_typed_alias
*typeinfo
)
1586 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1587 struct neon_typed_alias atype
;
1588 struct neon_type_el parsetype
;
1592 atype
.eltype
.type
= NT_invtype
;
1593 atype
.eltype
.size
= -1;
1595 /* Try alternate syntax for some types of register. Note these are mutually
1596 exclusive with the Neon syntax extensions. */
1599 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1607 /* Undo polymorphism when a set of register types may be accepted. */
1608 if ((type
== REG_TYPE_NDQ
1609 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1610 || (type
== REG_TYPE_VFSD
1611 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1612 || (type
== REG_TYPE_NSDQ
1613 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1614 || reg
->type
== REG_TYPE_NQ
))
1615 || (type
== REG_TYPE_NSD
1616 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1617 || (type
== REG_TYPE_MMXWC
1618 && (reg
->type
== REG_TYPE_MMXWCG
)))
1619 type
= (enum arm_reg_type
) reg
->type
;
1621 if (type
== REG_TYPE_MQ
)
1623 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1626 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1629 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1631 first_error (_("expected MVE register [q0..q7]"));
1636 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1637 && (type
== REG_TYPE_NQ
))
1641 if (type
!= reg
->type
)
1647 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1649 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1651 first_error (_("can't redefine type for operand"));
1654 atype
.defined
|= NTA_HASTYPE
;
1655 atype
.eltype
= parsetype
;
1658 if (skip_past_char (&str
, '[') == SUCCESS
)
1660 if (type
!= REG_TYPE_VFD
1661 && !(type
== REG_TYPE_VFS
1662 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1663 && !(type
== REG_TYPE_NQ
1664 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1666 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1667 first_error (_("only D and Q registers may be indexed"));
1669 first_error (_("only D registers may be indexed"));
1673 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1675 first_error (_("can't change index for operand"));
1679 atype
.defined
|= NTA_HASINDEX
;
1681 if (skip_past_char (&str
, ']') == SUCCESS
)
1682 atype
.index
= NEON_ALL_LANES
;
1687 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1689 if (exp
.X_op
!= O_constant
)
1691 first_error (_("constant expression required"));
1695 if (skip_past_char (&str
, ']') == FAIL
)
1698 atype
.index
= exp
.X_add_number
;
1713 /* Like arm_reg_parse, but also allow the following extra features:
1714 - If RTYPE is non-zero, return the (possibly restricted) type of the
1715 register (e.g. Neon double or quad reg when either has been requested).
1716 - If this is a Neon vector type with additional type information, fill
1717 in the struct pointed to by VECTYPE (if non-NULL).
1718 This function will fault on encountering a scalar. */
1721 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1722 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1724 struct neon_typed_alias atype
;
1726 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1731 /* Do not allow regname(... to parse as a register. */
1735 /* Do not allow a scalar (reg+index) to parse as a register. */
1736 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1738 first_error (_("register operand expected, but got scalar"));
1743 *vectype
= atype
.eltype
;
1750 #define NEON_SCALAR_REG(X) ((X) >> 4)
1751 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1753 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1754 have enough information to be able to do a good job bounds-checking. So, we
1755 just do easy checks here, and do further checks later. */
1758 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1759 arm_reg_type reg_type
)
1763 struct neon_typed_alias atype
;
1766 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1784 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1787 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1789 first_error (_("scalar must have an index"));
1792 else if (atype
.index
>= reg_size
/ elsize
)
1794 first_error (_("scalar index out of range"));
1799 *type
= atype
.eltype
;
1803 return reg
* 16 + atype
.index
;
1806 /* Types of registers in a list. */
1819 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1822 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1828 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1830 /* We come back here if we get ranges concatenated by '+' or '|'. */
1833 skip_whitespace (str
);
1846 const char apsr_str
[] = "apsr";
1847 int apsr_str_len
= strlen (apsr_str
);
1849 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1850 if (etype
== REGLIST_CLRM
)
1852 if (reg
== REG_SP
|| reg
== REG_PC
)
1854 else if (reg
== FAIL
1855 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1856 && !ISALPHA (*(str
+ apsr_str_len
)))
1859 str
+= apsr_str_len
;
1864 first_error (_("r0-r12, lr or APSR expected"));
1868 else /* etype == REGLIST_RN. */
1872 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1883 first_error (_("bad range in register list"));
1887 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1889 if (range
& (1 << i
))
1891 (_("Warning: duplicated register (r%d) in register list"),
1899 if (range
& (1 << reg
))
1900 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1902 else if (reg
<= cur_reg
)
1903 as_tsktsk (_("Warning: register range not in ascending order"));
1908 while (skip_past_comma (&str
) != FAIL
1909 || (in_range
= 1, *str
++ == '-'));
1912 if (skip_past_char (&str
, '}') == FAIL
)
1914 first_error (_("missing `}'"));
1918 else if (etype
== REGLIST_RN
)
1922 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1925 if (exp
.X_op
== O_constant
)
1927 if (exp
.X_add_number
1928 != (exp
.X_add_number
& 0x0000ffff))
1930 inst
.error
= _("invalid register mask");
1934 if ((range
& exp
.X_add_number
) != 0)
1936 int regno
= range
& exp
.X_add_number
;
1939 regno
= (1 << regno
) - 1;
1941 (_("Warning: duplicated register (r%d) in register list"),
1945 range
|= exp
.X_add_number
;
1949 if (inst
.relocs
[0].type
!= 0)
1951 inst
.error
= _("expression too complex");
1955 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1956 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1957 inst
.relocs
[0].pc_rel
= 0;
1961 if (*str
== '|' || *str
== '+')
1967 while (another_range
);
1973 /* Parse a VFP register list. If the string is invalid return FAIL.
1974 Otherwise return the number of registers, and set PBASE to the first
1975 register. Parses registers of type ETYPE.
1976 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1977 - Q registers can be used to specify pairs of D registers
1978 - { } can be omitted from around a singleton register list
1979 FIXME: This is not implemented, as it would require backtracking in
1982 This could be done (the meaning isn't really ambiguous), but doesn't
1983 fit in well with the current parsing framework.
1984 - 32 D registers may be used (also true for VFPv3).
1985 FIXME: Types are ignored in these register lists, which is probably a
1989 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
1990 bfd_boolean
*partial_match
)
1995 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1999 unsigned long mask
= 0;
2001 bfd_boolean vpr_seen
= FALSE
;
2002 bfd_boolean expect_vpr
=
2003 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2005 if (skip_past_char (&str
, '{') == FAIL
)
2007 inst
.error
= _("expecting {");
2014 case REGLIST_VFP_S_VPR
:
2015 regtype
= REG_TYPE_VFS
;
2020 case REGLIST_VFP_D_VPR
:
2021 regtype
= REG_TYPE_VFD
;
2024 case REGLIST_NEON_D
:
2025 regtype
= REG_TYPE_NDQ
;
2032 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2034 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2035 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2039 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2042 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2049 base_reg
= max_regs
;
2050 *partial_match
= FALSE
;
2054 int setmask
= 1, addregs
= 1;
2055 const char vpr_str
[] = "vpr";
2056 int vpr_str_len
= strlen (vpr_str
);
2058 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2062 if (new_base
== FAIL
2063 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2064 && !ISALPHA (*(str
+ vpr_str_len
))
2070 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2074 first_error (_("VPR expected last"));
2077 else if (new_base
== FAIL
)
2079 if (regtype
== REG_TYPE_VFS
)
2080 first_error (_("VFP single precision register or VPR "
2082 else /* regtype == REG_TYPE_VFD. */
2083 first_error (_("VFP/Neon double precision register or VPR "
2088 else if (new_base
== FAIL
)
2090 first_error (_(reg_expected_msgs
[regtype
]));
2094 *partial_match
= TRUE
;
2098 if (new_base
>= max_regs
)
2100 first_error (_("register out of range in list"));
2104 /* Note: a value of 2 * n is returned for the register Q<n>. */
2105 if (regtype
== REG_TYPE_NQ
)
2111 if (new_base
< base_reg
)
2112 base_reg
= new_base
;
2114 if (mask
& (setmask
<< new_base
))
2116 first_error (_("invalid register list"));
2120 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2122 as_tsktsk (_("register list not in ascending order"));
2126 mask
|= setmask
<< new_base
;
2129 if (*str
== '-') /* We have the start of a range expression */
2135 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2138 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2142 if (high_range
>= max_regs
)
2144 first_error (_("register out of range in list"));
2148 if (regtype
== REG_TYPE_NQ
)
2149 high_range
= high_range
+ 1;
2151 if (high_range
<= new_base
)
2153 inst
.error
= _("register range not in ascending order");
2157 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2159 if (mask
& (setmask
<< new_base
))
2161 inst
.error
= _("invalid register list");
2165 mask
|= setmask
<< new_base
;
2170 while (skip_past_comma (&str
) != FAIL
);
2174 /* Sanity check -- should have raised a parse error above. */
2175 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2180 if (expect_vpr
&& !vpr_seen
)
2182 first_error (_("VPR expected last"));
2186 /* Final test -- the registers must be consecutive. */
2188 for (i
= 0; i
< count
; i
++)
2190 if ((mask
& (1u << i
)) == 0)
2192 inst
.error
= _("non-contiguous register range");
2202 /* True if two alias types are the same. */
2205 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2213 if (a
->defined
!= b
->defined
)
2216 if ((a
->defined
& NTA_HASTYPE
) != 0
2217 && (a
->eltype
.type
!= b
->eltype
.type
2218 || a
->eltype
.size
!= b
->eltype
.size
))
2221 if ((a
->defined
& NTA_HASINDEX
) != 0
2222 && (a
->index
!= b
->index
))
2228 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2229 The base register is put in *PBASE.
2230 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2232 The register stride (minus one) is put in bit 4 of the return value.
2233 Bits [6:5] encode the list length (minus one).
2234 The type of the list elements is put in *ELTYPE, if non-NULL. */
2236 #define NEON_LANE(X) ((X) & 0xf)
2237 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2238 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2241 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2243 struct neon_type_el
*eltype
)
2250 int leading_brace
= 0;
2251 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2252 const char *const incr_error
= mve
? _("register stride must be 1") :
2253 _("register stride must be 1 or 2");
2254 const char *const type_error
= _("mismatched element/structure types in list");
2255 struct neon_typed_alias firsttype
;
2256 firsttype
.defined
= 0;
2257 firsttype
.eltype
.type
= NT_invtype
;
2258 firsttype
.eltype
.size
= -1;
2259 firsttype
.index
= -1;
2261 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2266 struct neon_typed_alias atype
;
2268 rtype
= REG_TYPE_MQ
;
2269 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2273 first_error (_(reg_expected_msgs
[rtype
]));
2280 if (rtype
== REG_TYPE_NQ
)
2286 else if (reg_incr
== -1)
2288 reg_incr
= getreg
- base_reg
;
2289 if (reg_incr
< 1 || reg_incr
> 2)
2291 first_error (_(incr_error
));
2295 else if (getreg
!= base_reg
+ reg_incr
* count
)
2297 first_error (_(incr_error
));
2301 if (! neon_alias_types_same (&atype
, &firsttype
))
2303 first_error (_(type_error
));
2307 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2311 struct neon_typed_alias htype
;
2312 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2314 lane
= NEON_INTERLEAVE_LANES
;
2315 else if (lane
!= NEON_INTERLEAVE_LANES
)
2317 first_error (_(type_error
));
2322 else if (reg_incr
!= 1)
2324 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2328 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2331 first_error (_(reg_expected_msgs
[rtype
]));
2334 if (! neon_alias_types_same (&htype
, &firsttype
))
2336 first_error (_(type_error
));
2339 count
+= hireg
+ dregs
- getreg
;
2343 /* If we're using Q registers, we can't use [] or [n] syntax. */
2344 if (rtype
== REG_TYPE_NQ
)
2350 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2354 else if (lane
!= atype
.index
)
2356 first_error (_(type_error
));
2360 else if (lane
== -1)
2361 lane
= NEON_INTERLEAVE_LANES
;
2362 else if (lane
!= NEON_INTERLEAVE_LANES
)
2364 first_error (_(type_error
));
2369 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2371 /* No lane set by [x]. We must be interleaving structures. */
2373 lane
= NEON_INTERLEAVE_LANES
;
2376 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2377 || (count
> 1 && reg_incr
== -1))
2379 first_error (_("error parsing element/structure list"));
2383 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2385 first_error (_("expected }"));
2393 *eltype
= firsttype
.eltype
;
2398 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2401 /* Parse an explicit relocation suffix on an expression. This is
2402 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2403 arm_reloc_hsh contains no entries, so this function can only
2404 succeed if there is no () after the word. Returns -1 on error,
2405 BFD_RELOC_UNUSED if there wasn't any suffix. */
2408 parse_reloc (char **str
)
2410 struct reloc_entry
*r
;
2414 return BFD_RELOC_UNUSED
;
2419 while (*q
&& *q
!= ')' && *q
!= ',')
2424 if ((r
= (struct reloc_entry
*)
2425 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2432 /* Directives: register aliases. */
2434 static struct reg_entry
*
2435 insert_reg_alias (char *str
, unsigned number
, int type
)
2437 struct reg_entry
*new_reg
;
2440 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2442 if (new_reg
->builtin
)
2443 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2445 /* Only warn about a redefinition if it's not defined as the
2447 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2448 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2453 name
= xstrdup (str
);
2454 new_reg
= XNEW (struct reg_entry
);
2456 new_reg
->name
= name
;
2457 new_reg
->number
= number
;
2458 new_reg
->type
= type
;
2459 new_reg
->builtin
= FALSE
;
2460 new_reg
->neon
= NULL
;
2462 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2469 insert_neon_reg_alias (char *str
, int number
, int type
,
2470 struct neon_typed_alias
*atype
)
2472 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2476 first_error (_("attempt to redefine typed alias"));
2482 reg
->neon
= XNEW (struct neon_typed_alias
);
2483 *reg
->neon
= *atype
;
2487 /* Look for the .req directive. This is of the form:
2489 new_register_name .req existing_register_name
2491 If we find one, or if it looks sufficiently like one that we want to
2492 handle any error here, return TRUE. Otherwise return FALSE. */
2495 create_register_alias (char * newname
, char *p
)
2497 struct reg_entry
*old
;
2498 char *oldname
, *nbuf
;
2501 /* The input scrubber ensures that whitespace after the mnemonic is
2502 collapsed to single spaces. */
2504 if (strncmp (oldname
, " .req ", 6) != 0)
2508 if (*oldname
== '\0')
2511 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2514 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2518 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2519 the desired alias name, and p points to its end. If not, then
2520 the desired alias name is in the global original_case_string. */
2521 #ifdef TC_CASE_SENSITIVE
2524 newname
= original_case_string
;
2525 nlen
= strlen (newname
);
2528 nbuf
= xmemdup0 (newname
, nlen
);
2530 /* Create aliases under the new name as stated; an all-lowercase
2531 version of the new name; and an all-uppercase version of the new
2533 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2535 for (p
= nbuf
; *p
; p
++)
2538 if (strncmp (nbuf
, newname
, nlen
))
2540 /* If this attempt to create an additional alias fails, do not bother
2541 trying to create the all-lower case alias. We will fail and issue
2542 a second, duplicate error message. This situation arises when the
2543 programmer does something like:
2546 The second .req creates the "Foo" alias but then fails to create
2547 the artificial FOO alias because it has already been created by the
2549 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2556 for (p
= nbuf
; *p
; p
++)
2559 if (strncmp (nbuf
, newname
, nlen
))
2560 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2567 /* Create a Neon typed/indexed register alias using directives, e.g.:
2572 These typed registers can be used instead of the types specified after the
2573 Neon mnemonic, so long as all operands given have types. Types can also be
2574 specified directly, e.g.:
2575 vadd d0.s32, d1.s32, d2.s32 */
2578 create_neon_reg_alias (char *newname
, char *p
)
2580 enum arm_reg_type basetype
;
2581 struct reg_entry
*basereg
;
2582 struct reg_entry mybasereg
;
2583 struct neon_type ntype
;
2584 struct neon_typed_alias typeinfo
;
2585 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2588 typeinfo
.defined
= 0;
2589 typeinfo
.eltype
.type
= NT_invtype
;
2590 typeinfo
.eltype
.size
= -1;
2591 typeinfo
.index
= -1;
2595 if (strncmp (p
, " .dn ", 5) == 0)
2596 basetype
= REG_TYPE_VFD
;
2597 else if (strncmp (p
, " .qn ", 5) == 0)
2598 basetype
= REG_TYPE_NQ
;
2607 basereg
= arm_reg_parse_multi (&p
);
2609 if (basereg
&& basereg
->type
!= basetype
)
2611 as_bad (_("bad type for register"));
2615 if (basereg
== NULL
)
2618 /* Try parsing as an integer. */
2619 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2620 if (exp
.X_op
!= O_constant
)
2622 as_bad (_("expression must be constant"));
2625 basereg
= &mybasereg
;
2626 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2632 typeinfo
= *basereg
->neon
;
2634 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2636 /* We got a type. */
2637 if (typeinfo
.defined
& NTA_HASTYPE
)
2639 as_bad (_("can't redefine the type of a register alias"));
2643 typeinfo
.defined
|= NTA_HASTYPE
;
2644 if (ntype
.elems
!= 1)
2646 as_bad (_("you must specify a single type only"));
2649 typeinfo
.eltype
= ntype
.el
[0];
2652 if (skip_past_char (&p
, '[') == SUCCESS
)
2655 /* We got a scalar index. */
2657 if (typeinfo
.defined
& NTA_HASINDEX
)
2659 as_bad (_("can't redefine the index of a scalar alias"));
2663 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2665 if (exp
.X_op
!= O_constant
)
2667 as_bad (_("scalar index must be constant"));
2671 typeinfo
.defined
|= NTA_HASINDEX
;
2672 typeinfo
.index
= exp
.X_add_number
;
2674 if (skip_past_char (&p
, ']') == FAIL
)
2676 as_bad (_("expecting ]"));
2681 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2682 the desired alias name, and p points to its end. If not, then
2683 the desired alias name is in the global original_case_string. */
2684 #ifdef TC_CASE_SENSITIVE
2685 namelen
= nameend
- newname
;
2687 newname
= original_case_string
;
2688 namelen
= strlen (newname
);
2691 namebuf
= xmemdup0 (newname
, namelen
);
2693 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2694 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2696 /* Insert name in all uppercase. */
2697 for (p
= namebuf
; *p
; p
++)
2700 if (strncmp (namebuf
, newname
, namelen
))
2701 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2702 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2704 /* Insert name in all lowercase. */
2705 for (p
= namebuf
; *p
; p
++)
2708 if (strncmp (namebuf
, newname
, namelen
))
2709 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2710 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2716 /* Should never be called, as .req goes between the alias and the
2717 register name, not at the beginning of the line. */
2720 s_req (int a ATTRIBUTE_UNUSED
)
2722 as_bad (_("invalid syntax for .req directive"));
2726 s_dn (int a ATTRIBUTE_UNUSED
)
2728 as_bad (_("invalid syntax for .dn directive"));
2732 s_qn (int a ATTRIBUTE_UNUSED
)
2734 as_bad (_("invalid syntax for .qn directive"));
2737 /* The .unreq directive deletes an alias which was previously defined
2738 by .req. For example:
2744 s_unreq (int a ATTRIBUTE_UNUSED
)
2749 name
= input_line_pointer
;
2751 while (*input_line_pointer
!= 0
2752 && *input_line_pointer
!= ' '
2753 && *input_line_pointer
!= '\n')
2754 ++input_line_pointer
;
2756 saved_char
= *input_line_pointer
;
2757 *input_line_pointer
= 0;
2760 as_bad (_("invalid syntax for .unreq directive"));
2763 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2767 as_bad (_("unknown register alias '%s'"), name
);
2768 else if (reg
->builtin
)
2769 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2776 hash_delete (arm_reg_hsh
, name
, FALSE
);
2777 free ((char *) reg
->name
);
2782 /* Also locate the all upper case and all lower case versions.
2783 Do not complain if we cannot find one or the other as it
2784 was probably deleted above. */
2786 nbuf
= strdup (name
);
2787 for (p
= nbuf
; *p
; p
++)
2789 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2792 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2793 free ((char *) reg
->name
);
2799 for (p
= nbuf
; *p
; p
++)
2801 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2804 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2805 free ((char *) reg
->name
);
2815 *input_line_pointer
= saved_char
;
2816 demand_empty_rest_of_line ();
2819 /* Directives: Instruction set selection. */
2822 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2823 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2824 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2825 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2827 /* Create a new mapping symbol for the transition to STATE. */
2830 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2833 const char * symname
;
2840 type
= BSF_NO_FLAGS
;
2844 type
= BSF_NO_FLAGS
;
2848 type
= BSF_NO_FLAGS
;
2854 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2855 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2860 THUMB_SET_FUNC (symbolP
, 0);
2861 ARM_SET_THUMB (symbolP
, 0);
2862 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2866 THUMB_SET_FUNC (symbolP
, 1);
2867 ARM_SET_THUMB (symbolP
, 1);
2868 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2876 /* Save the mapping symbols for future reference. Also check that
2877 we do not place two mapping symbols at the same offset within a
2878 frag. We'll handle overlap between frags in
2879 check_mapping_symbols.
2881 If .fill or other data filling directive generates zero sized data,
2882 the mapping symbol for the following code will have the same value
2883 as the one generated for the data filling directive. In this case,
2884 we replace the old symbol with the new one at the same address. */
2887 if (frag
->tc_frag_data
.first_map
!= NULL
)
2889 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2890 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2892 frag
->tc_frag_data
.first_map
= symbolP
;
2894 if (frag
->tc_frag_data
.last_map
!= NULL
)
2896 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2897 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2898 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2900 frag
->tc_frag_data
.last_map
= symbolP
;
2903 /* We must sometimes convert a region marked as code to data during
2904 code alignment, if an odd number of bytes have to be padded. The
2905 code mapping symbol is pushed to an aligned address. */
2908 insert_data_mapping_symbol (enum mstate state
,
2909 valueT value
, fragS
*frag
, offsetT bytes
)
2911 /* If there was already a mapping symbol, remove it. */
2912 if (frag
->tc_frag_data
.last_map
!= NULL
2913 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2915 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2919 know (frag
->tc_frag_data
.first_map
== symp
);
2920 frag
->tc_frag_data
.first_map
= NULL
;
2922 frag
->tc_frag_data
.last_map
= NULL
;
2923 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2926 make_mapping_symbol (MAP_DATA
, value
, frag
);
2927 make_mapping_symbol (state
, value
+ bytes
, frag
);
2930 static void mapping_state_2 (enum mstate state
, int max_chars
);
2932 /* Set the mapping state to STATE. Only call this when about to
2933 emit some STATE bytes to the file. */
2935 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2937 mapping_state (enum mstate state
)
2939 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2941 if (mapstate
== state
)
2942 /* The mapping symbol has already been emitted.
2943 There is nothing else to do. */
2946 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2948 All ARM instructions require 4-byte alignment.
2949 (Almost) all Thumb instructions require 2-byte alignment.
2951 When emitting instructions into any section, mark the section
2954 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2955 but themselves require 2-byte alignment; this applies to some
2956 PC- relative forms. However, these cases will involve implicit
2957 literal pool generation or an explicit .align >=2, both of
2958 which will cause the section to me marked with sufficient
2959 alignment. Thus, we don't handle those cases here. */
2960 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2962 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2963 /* This case will be evaluated later. */
2966 mapping_state_2 (state
, 0);
2969 /* Same as mapping_state, but MAX_CHARS bytes have already been
2970 allocated. Put the mapping symbol that far back. */
2973 mapping_state_2 (enum mstate state
, int max_chars
)
2975 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2977 if (!SEG_NORMAL (now_seg
))
2980 if (mapstate
== state
)
2981 /* The mapping symbol has already been emitted.
2982 There is nothing else to do. */
2985 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2986 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2988 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2989 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2992 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2995 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2996 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3000 #define mapping_state(x) ((void)0)
3001 #define mapping_state_2(x, y) ((void)0)
3004 /* Find the real, Thumb encoded start of a Thumb function. */
3008 find_real_start (symbolS
* symbolP
)
3011 const char * name
= S_GET_NAME (symbolP
);
3012 symbolS
* new_target
;
3014 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3015 #define STUB_NAME ".real_start_of"
3020 /* The compiler may generate BL instructions to local labels because
3021 it needs to perform a branch to a far away location. These labels
3022 do not have a corresponding ".real_start_of" label. We check
3023 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3024 the ".real_start_of" convention for nonlocal branches. */
3025 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3028 real_start
= concat (STUB_NAME
, name
, NULL
);
3029 new_target
= symbol_find (real_start
);
3032 if (new_target
== NULL
)
3034 as_warn (_("Failed to find real start of function: %s\n"), name
);
3035 new_target
= symbolP
;
3043 opcode_select (int width
)
3050 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3051 as_bad (_("selected processor does not support THUMB opcodes"));
3054 /* No need to force the alignment, since we will have been
3055 coming from ARM mode, which is word-aligned. */
3056 record_alignment (now_seg
, 1);
3063 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3064 as_bad (_("selected processor does not support ARM opcodes"));
3069 frag_align (2, 0, 0);
3071 record_alignment (now_seg
, 1);
3076 as_bad (_("invalid instruction size selected (%d)"), width
);
3081 s_arm (int ignore ATTRIBUTE_UNUSED
)
3084 demand_empty_rest_of_line ();
3088 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3091 demand_empty_rest_of_line ();
3095 s_code (int unused ATTRIBUTE_UNUSED
)
3099 temp
= get_absolute_expression ();
3104 opcode_select (temp
);
3108 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3113 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3115 /* If we are not already in thumb mode go into it, EVEN if
3116 the target processor does not support thumb instructions.
3117 This is used by gcc/config/arm/lib1funcs.asm for example
3118 to compile interworking support functions even if the
3119 target processor should not support interworking. */
3123 record_alignment (now_seg
, 1);
3126 demand_empty_rest_of_line ();
3130 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3134 /* The following label is the name/address of the start of a Thumb function.
3135 We need to know this for the interworking support. */
3136 label_is_thumb_function_name
= TRUE
;
3139 /* Perform a .set directive, but also mark the alias as
3140 being a thumb function. */
3143 s_thumb_set (int equiv
)
3145 /* XXX the following is a duplicate of the code for s_set() in read.c
3146 We cannot just call that code as we need to get at the symbol that
3153 /* Especial apologies for the random logic:
3154 This just grew, and could be parsed much more simply!
3156 delim
= get_symbol_name (& name
);
3157 end_name
= input_line_pointer
;
3158 (void) restore_line_pointer (delim
);
3160 if (*input_line_pointer
!= ',')
3163 as_bad (_("expected comma after name \"%s\""), name
);
3165 ignore_rest_of_line ();
3169 input_line_pointer
++;
3172 if (name
[0] == '.' && name
[1] == '\0')
3174 /* XXX - this should not happen to .thumb_set. */
3178 if ((symbolP
= symbol_find (name
)) == NULL
3179 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3182 /* When doing symbol listings, play games with dummy fragments living
3183 outside the normal fragment chain to record the file and line info
3185 if (listing
& LISTING_SYMBOLS
)
3187 extern struct list_info_struct
* listing_tail
;
3188 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3190 memset (dummy_frag
, 0, sizeof (fragS
));
3191 dummy_frag
->fr_type
= rs_fill
;
3192 dummy_frag
->line
= listing_tail
;
3193 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3194 dummy_frag
->fr_symbol
= symbolP
;
3198 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3201 /* "set" symbols are local unless otherwise specified. */
3202 SF_SET_LOCAL (symbolP
);
3203 #endif /* OBJ_COFF */
3204 } /* Make a new symbol. */
3206 symbol_table_insert (symbolP
);
3211 && S_IS_DEFINED (symbolP
)
3212 && S_GET_SEGMENT (symbolP
) != reg_section
)
3213 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3215 pseudo_set (symbolP
);
3217 demand_empty_rest_of_line ();
3219 /* XXX Now we come to the Thumb specific bit of code. */
3221 THUMB_SET_FUNC (symbolP
, 1);
3222 ARM_SET_THUMB (symbolP
, 1);
3223 #if defined OBJ_ELF || defined OBJ_COFF
3224 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3228 /* Directives: Mode selection. */
3230 /* .syntax [unified|divided] - choose the new unified syntax
3231 (same for Arm and Thumb encoding, modulo slight differences in what
3232 can be represented) or the old divergent syntax for each mode. */
3234 s_syntax (int unused ATTRIBUTE_UNUSED
)
3238 delim
= get_symbol_name (& name
);
3240 if (!strcasecmp (name
, "unified"))
3241 unified_syntax
= TRUE
;
3242 else if (!strcasecmp (name
, "divided"))
3243 unified_syntax
= FALSE
;
3246 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3249 (void) restore_line_pointer (delim
);
3250 demand_empty_rest_of_line ();
3253 /* Directives: sectioning and alignment. */
3256 s_bss (int ignore ATTRIBUTE_UNUSED
)
3258 /* We don't support putting frags in the BSS segment, we fake it by
3259 marking in_bss, then looking at s_skip for clues. */
3260 subseg_set (bss_section
, 0);
3261 demand_empty_rest_of_line ();
3263 #ifdef md_elf_section_change_hook
3264 md_elf_section_change_hook ();
3269 s_even (int ignore ATTRIBUTE_UNUSED
)
3271 /* Never make frag if expect extra pass. */
3273 frag_align (1, 0, 0);
3275 record_alignment (now_seg
, 1);
3277 demand_empty_rest_of_line ();
3280 /* Directives: CodeComposer Studio. */
3282 /* .ref (for CodeComposer Studio syntax only). */
3284 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3286 if (codecomposer_syntax
)
3287 ignore_rest_of_line ();
3289 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3292 /* If name is not NULL, then it is used for marking the beginning of a
3293 function, whereas if it is NULL then it means the function end. */
3295 asmfunc_debug (const char * name
)
3297 static const char * last_name
= NULL
;
3301 gas_assert (last_name
== NULL
);
3304 if (debug_type
== DEBUG_STABS
)
3305 stabs_generate_asm_func (name
, name
);
3309 gas_assert (last_name
!= NULL
);
3311 if (debug_type
== DEBUG_STABS
)
3312 stabs_generate_asm_endfunc (last_name
, last_name
);
3319 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3321 if (codecomposer_syntax
)
3323 switch (asmfunc_state
)
3325 case OUTSIDE_ASMFUNC
:
3326 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3329 case WAITING_ASMFUNC_NAME
:
3330 as_bad (_(".asmfunc repeated."));
3333 case WAITING_ENDASMFUNC
:
3334 as_bad (_(".asmfunc without function."));
3337 demand_empty_rest_of_line ();
3340 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3344 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3346 if (codecomposer_syntax
)
3348 switch (asmfunc_state
)
3350 case OUTSIDE_ASMFUNC
:
3351 as_bad (_(".endasmfunc without a .asmfunc."));
3354 case WAITING_ASMFUNC_NAME
:
3355 as_bad (_(".endasmfunc without function."));
3358 case WAITING_ENDASMFUNC
:
3359 asmfunc_state
= OUTSIDE_ASMFUNC
;
3360 asmfunc_debug (NULL
);
3363 demand_empty_rest_of_line ();
3366 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3370 s_ccs_def (int name
)
3372 if (codecomposer_syntax
)
3375 as_bad (_(".def pseudo-op only available with -mccs flag."));
3378 /* Directives: Literal pools. */
3380 static literal_pool
*
3381 find_literal_pool (void)
3383 literal_pool
* pool
;
3385 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3387 if (pool
->section
== now_seg
3388 && pool
->sub_section
== now_subseg
)
3395 static literal_pool
*
3396 find_or_make_literal_pool (void)
3398 /* Next literal pool ID number. */
3399 static unsigned int latest_pool_num
= 1;
3400 literal_pool
* pool
;
3402 pool
= find_literal_pool ();
3406 /* Create a new pool. */
3407 pool
= XNEW (literal_pool
);
3411 pool
->next_free_entry
= 0;
3412 pool
->section
= now_seg
;
3413 pool
->sub_section
= now_subseg
;
3414 pool
->next
= list_of_pools
;
3415 pool
->symbol
= NULL
;
3416 pool
->alignment
= 2;
3418 /* Add it to the list. */
3419 list_of_pools
= pool
;
3422 /* New pools, and emptied pools, will have a NULL symbol. */
3423 if (pool
->symbol
== NULL
)
3425 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3426 (valueT
) 0, &zero_address_frag
);
3427 pool
->id
= latest_pool_num
++;
3434 /* Add the literal in the global 'inst'
3435 structure to the relevant literal pool. */
3438 add_to_lit_pool (unsigned int nbytes
)
3440 #define PADDING_SLOT 0x1
3441 #define LIT_ENTRY_SIZE_MASK 0xFF
3442 literal_pool
* pool
;
3443 unsigned int entry
, pool_size
= 0;
3444 bfd_boolean padding_slot_p
= FALSE
;
3450 imm1
= inst
.operands
[1].imm
;
3451 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3452 : inst
.relocs
[0].exp
.X_unsigned
? 0
3453 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3454 if (target_big_endian
)
3457 imm2
= inst
.operands
[1].imm
;
3461 pool
= find_or_make_literal_pool ();
3463 /* Check if this literal value is already in the pool. */
3464 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3468 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3469 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3470 && (pool
->literals
[entry
].X_add_number
3471 == inst
.relocs
[0].exp
.X_add_number
)
3472 && (pool
->literals
[entry
].X_md
== nbytes
)
3473 && (pool
->literals
[entry
].X_unsigned
3474 == inst
.relocs
[0].exp
.X_unsigned
))
3477 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3478 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3479 && (pool
->literals
[entry
].X_add_number
3480 == inst
.relocs
[0].exp
.X_add_number
)
3481 && (pool
->literals
[entry
].X_add_symbol
3482 == inst
.relocs
[0].exp
.X_add_symbol
)
3483 && (pool
->literals
[entry
].X_op_symbol
3484 == inst
.relocs
[0].exp
.X_op_symbol
)
3485 && (pool
->literals
[entry
].X_md
== nbytes
))
3488 else if ((nbytes
== 8)
3489 && !(pool_size
& 0x7)
3490 && ((entry
+ 1) != pool
->next_free_entry
)
3491 && (pool
->literals
[entry
].X_op
== O_constant
)
3492 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3493 && (pool
->literals
[entry
].X_unsigned
3494 == inst
.relocs
[0].exp
.X_unsigned
)
3495 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3496 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3497 && (pool
->literals
[entry
+ 1].X_unsigned
3498 == inst
.relocs
[0].exp
.X_unsigned
))
3501 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3502 if (padding_slot_p
&& (nbytes
== 4))
3508 /* Do we need to create a new entry? */
3509 if (entry
== pool
->next_free_entry
)
3511 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3513 inst
.error
= _("literal pool overflow");
3519 /* For 8-byte entries, we align to an 8-byte boundary,
3520 and split it into two 4-byte entries, because on 32-bit
3521 host, 8-byte constants are treated as big num, thus
3522 saved in "generic_bignum" which will be overwritten
3523 by later assignments.
3525 We also need to make sure there is enough space for
3528 We also check to make sure the literal operand is a
3530 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3531 || inst
.relocs
[0].exp
.X_op
== O_big
))
3533 inst
.error
= _("invalid type for literal pool");
3536 else if (pool_size
& 0x7)
3538 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3540 inst
.error
= _("literal pool overflow");
3544 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3545 pool
->literals
[entry
].X_op
= O_constant
;
3546 pool
->literals
[entry
].X_add_number
= 0;
3547 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3548 pool
->next_free_entry
+= 1;
3551 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3553 inst
.error
= _("literal pool overflow");
3557 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3558 pool
->literals
[entry
].X_op
= O_constant
;
3559 pool
->literals
[entry
].X_add_number
= imm1
;
3560 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3561 pool
->literals
[entry
++].X_md
= 4;
3562 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3563 pool
->literals
[entry
].X_op
= O_constant
;
3564 pool
->literals
[entry
].X_add_number
= imm2
;
3565 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3566 pool
->literals
[entry
].X_md
= 4;
3567 pool
->alignment
= 3;
3568 pool
->next_free_entry
+= 1;
3572 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3573 pool
->literals
[entry
].X_md
= 4;
3577 /* PR ld/12974: Record the location of the first source line to reference
3578 this entry in the literal pool. If it turns out during linking that the
3579 symbol does not exist we will be able to give an accurate line number for
3580 the (first use of the) missing reference. */
3581 if (debug_type
== DEBUG_DWARF2
)
3582 dwarf2_where (pool
->locs
+ entry
);
3584 pool
->next_free_entry
+= 1;
3586 else if (padding_slot_p
)
3588 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3589 pool
->literals
[entry
].X_md
= nbytes
;
3592 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3593 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3594 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3600 tc_start_label_without_colon (void)
3602 bfd_boolean ret
= TRUE
;
3604 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3606 const char *label
= input_line_pointer
;
3608 while (!is_end_of_line
[(int) label
[-1]])
3613 as_bad (_("Invalid label '%s'"), label
);
3617 asmfunc_debug (label
);
3619 asmfunc_state
= WAITING_ENDASMFUNC
;
3625 /* Can't use symbol_new here, so have to create a symbol and then at
3626 a later date assign it a value. That's what these functions do. */
3629 symbol_locate (symbolS
* symbolP
,
3630 const char * name
, /* It is copied, the caller can modify. */
3631 segT segment
, /* Segment identifier (SEG_<something>). */
3632 valueT valu
, /* Symbol value. */
3633 fragS
* frag
) /* Associated fragment. */
3636 char * preserved_copy_of_name
;
3638 name_length
= strlen (name
) + 1; /* +1 for \0. */
3639 obstack_grow (¬es
, name
, name_length
);
3640 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3642 #ifdef tc_canonicalize_symbol_name
3643 preserved_copy_of_name
=
3644 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3647 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3649 S_SET_SEGMENT (symbolP
, segment
);
3650 S_SET_VALUE (symbolP
, valu
);
3651 symbol_clear_list_pointers (symbolP
);
3653 symbol_set_frag (symbolP
, frag
);
3655 /* Link to end of symbol chain. */
3657 extern int symbol_table_frozen
;
3659 if (symbol_table_frozen
)
3663 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3665 obj_symbol_new_hook (symbolP
);
3667 #ifdef tc_symbol_new_hook
3668 tc_symbol_new_hook (symbolP
);
3672 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3673 #endif /* DEBUG_SYMS */
3677 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3680 literal_pool
* pool
;
3683 pool
= find_literal_pool ();
3685 || pool
->symbol
== NULL
3686 || pool
->next_free_entry
== 0)
3689 /* Align pool as you have word accesses.
3690 Only make a frag if we have to. */
3692 frag_align (pool
->alignment
, 0, 0);
3694 record_alignment (now_seg
, 2);
3697 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3698 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3700 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3702 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3703 (valueT
) frag_now_fix (), frag_now
);
3704 symbol_table_insert (pool
->symbol
);
3706 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3708 #if defined OBJ_COFF || defined OBJ_ELF
3709 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3712 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3715 if (debug_type
== DEBUG_DWARF2
)
3716 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3718 /* First output the expression in the instruction to the pool. */
3719 emit_expr (&(pool
->literals
[entry
]),
3720 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3723 /* Mark the pool as empty. */
3724 pool
->next_free_entry
= 0;
3725 pool
->symbol
= NULL
;
3729 /* Forward declarations for functions below, in the MD interface
3731 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3732 static valueT
create_unwind_entry (int);
3733 static void start_unwind_section (const segT
, int);
3734 static void add_unwind_opcode (valueT
, int);
3735 static void flush_pending_unwind (void);
3737 /* Directives: Data. */
3740 s_arm_elf_cons (int nbytes
)
3744 #ifdef md_flush_pending_output
3745 md_flush_pending_output ();
3748 if (is_it_end_of_statement ())
3750 demand_empty_rest_of_line ();
3754 #ifdef md_cons_align
3755 md_cons_align (nbytes
);
3758 mapping_state (MAP_DATA
);
3762 char *base
= input_line_pointer
;
3766 if (exp
.X_op
!= O_symbol
)
3767 emit_expr (&exp
, (unsigned int) nbytes
);
3770 char *before_reloc
= input_line_pointer
;
3771 reloc
= parse_reloc (&input_line_pointer
);
3774 as_bad (_("unrecognized relocation suffix"));
3775 ignore_rest_of_line ();
3778 else if (reloc
== BFD_RELOC_UNUSED
)
3779 emit_expr (&exp
, (unsigned int) nbytes
);
3782 reloc_howto_type
*howto
= (reloc_howto_type
*)
3783 bfd_reloc_type_lookup (stdoutput
,
3784 (bfd_reloc_code_real_type
) reloc
);
3785 int size
= bfd_get_reloc_size (howto
);
3787 if (reloc
== BFD_RELOC_ARM_PLT32
)
3789 as_bad (_("(plt) is only valid on branch targets"));
3790 reloc
= BFD_RELOC_UNUSED
;
3795 as_bad (ngettext ("%s relocations do not fit in %d byte",
3796 "%s relocations do not fit in %d bytes",
3798 howto
->name
, nbytes
);
3801 /* We've parsed an expression stopping at O_symbol.
3802 But there may be more expression left now that we
3803 have parsed the relocation marker. Parse it again.
3804 XXX Surely there is a cleaner way to do this. */
3805 char *p
= input_line_pointer
;
3807 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3809 memcpy (save_buf
, base
, input_line_pointer
- base
);
3810 memmove (base
+ (input_line_pointer
- before_reloc
),
3811 base
, before_reloc
- base
);
3813 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3815 memcpy (base
, save_buf
, p
- base
);
3817 offset
= nbytes
- size
;
3818 p
= frag_more (nbytes
);
3819 memset (p
, 0, nbytes
);
3820 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3821 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3827 while (*input_line_pointer
++ == ',');
3829 /* Put terminator back into stream. */
3830 input_line_pointer
--;
3831 demand_empty_rest_of_line ();
3834 /* Emit an expression containing a 32-bit thumb instruction.
3835 Implementation based on put_thumb32_insn. */
3838 emit_thumb32_expr (expressionS
* exp
)
3840 expressionS exp_high
= *exp
;
3842 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3843 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3844 exp
->X_add_number
&= 0xffff;
3845 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3848 /* Guess the instruction size based on the opcode. */
3851 thumb_insn_size (int opcode
)
3853 if ((unsigned int) opcode
< 0xe800u
)
3855 else if ((unsigned int) opcode
>= 0xe8000000u
)
3862 emit_insn (expressionS
*exp
, int nbytes
)
3866 if (exp
->X_op
== O_constant
)
3871 size
= thumb_insn_size (exp
->X_add_number
);
3875 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3877 as_bad (_(".inst.n operand too big. "\
3878 "Use .inst.w instead"));
3883 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3884 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3886 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3888 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3889 emit_thumb32_expr (exp
);
3891 emit_expr (exp
, (unsigned int) size
);
3893 it_fsm_post_encode ();
3897 as_bad (_("cannot determine Thumb instruction size. " \
3898 "Use .inst.n/.inst.w instead"));
3901 as_bad (_("constant expression required"));
3906 /* Like s_arm_elf_cons but do not use md_cons_align and
3907 set the mapping state to MAP_ARM/MAP_THUMB. */
3910 s_arm_elf_inst (int nbytes
)
3912 if (is_it_end_of_statement ())
3914 demand_empty_rest_of_line ();
3918 /* Calling mapping_state () here will not change ARM/THUMB,
3919 but will ensure not to be in DATA state. */
3922 mapping_state (MAP_THUMB
);
3927 as_bad (_("width suffixes are invalid in ARM mode"));
3928 ignore_rest_of_line ();
3934 mapping_state (MAP_ARM
);
3943 if (! emit_insn (& exp
, nbytes
))
3945 ignore_rest_of_line ();
3949 while (*input_line_pointer
++ == ',');
3951 /* Put terminator back into stream. */
3952 input_line_pointer
--;
3953 demand_empty_rest_of_line ();
3956 /* Parse a .rel31 directive. */
3959 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3966 if (*input_line_pointer
== '1')
3967 highbit
= 0x80000000;
3968 else if (*input_line_pointer
!= '0')
3969 as_bad (_("expected 0 or 1"));
3971 input_line_pointer
++;
3972 if (*input_line_pointer
!= ',')
3973 as_bad (_("missing comma"));
3974 input_line_pointer
++;
3976 #ifdef md_flush_pending_output
3977 md_flush_pending_output ();
3980 #ifdef md_cons_align
3984 mapping_state (MAP_DATA
);
3989 md_number_to_chars (p
, highbit
, 4);
3990 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3991 BFD_RELOC_ARM_PREL31
);
3993 demand_empty_rest_of_line ();
3996 /* Directives: AEABI stack-unwind tables. */
3998 /* Parse an unwind_fnstart directive. Simply records the current location. */
4001 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4003 demand_empty_rest_of_line ();
4004 if (unwind
.proc_start
)
4006 as_bad (_("duplicate .fnstart directive"));
4010 /* Mark the start of the function. */
4011 unwind
.proc_start
= expr_build_dot ();
4013 /* Reset the rest of the unwind info. */
4014 unwind
.opcode_count
= 0;
4015 unwind
.table_entry
= NULL
;
4016 unwind
.personality_routine
= NULL
;
4017 unwind
.personality_index
= -1;
4018 unwind
.frame_size
= 0;
4019 unwind
.fp_offset
= 0;
4020 unwind
.fp_reg
= REG_SP
;
4022 unwind
.sp_restored
= 0;
4026 /* Parse a handlerdata directive. Creates the exception handling table entry
4027 for the function. */
4030 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4032 demand_empty_rest_of_line ();
4033 if (!unwind
.proc_start
)
4034 as_bad (MISSING_FNSTART
);
4036 if (unwind
.table_entry
)
4037 as_bad (_("duplicate .handlerdata directive"));
4039 create_unwind_entry (1);
4042 /* Parse an unwind_fnend directive. Generates the index table entry. */
4045 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4050 unsigned int marked_pr_dependency
;
4052 demand_empty_rest_of_line ();
4054 if (!unwind
.proc_start
)
4056 as_bad (_(".fnend directive without .fnstart"));
4060 /* Add eh table entry. */
4061 if (unwind
.table_entry
== NULL
)
4062 val
= create_unwind_entry (0);
4066 /* Add index table entry. This is two words. */
4067 start_unwind_section (unwind
.saved_seg
, 1);
4068 frag_align (2, 0, 0);
4069 record_alignment (now_seg
, 2);
4071 ptr
= frag_more (8);
4073 where
= frag_now_fix () - 8;
4075 /* Self relative offset of the function start. */
4076 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4077 BFD_RELOC_ARM_PREL31
);
4079 /* Indicate dependency on EHABI-defined personality routines to the
4080 linker, if it hasn't been done already. */
4081 marked_pr_dependency
4082 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4083 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4084 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4086 static const char *const name
[] =
4088 "__aeabi_unwind_cpp_pr0",
4089 "__aeabi_unwind_cpp_pr1",
4090 "__aeabi_unwind_cpp_pr2"
4092 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4093 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4094 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4095 |= 1 << unwind
.personality_index
;
4099 /* Inline exception table entry. */
4100 md_number_to_chars (ptr
+ 4, val
, 4);
4102 /* Self relative offset of the table entry. */
4103 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4104 BFD_RELOC_ARM_PREL31
);
4106 /* Restore the original section. */
4107 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4109 unwind
.proc_start
= NULL
;
4113 /* Parse an unwind_cantunwind directive. */
4116 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4118 demand_empty_rest_of_line ();
4119 if (!unwind
.proc_start
)
4120 as_bad (MISSING_FNSTART
);
4122 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4123 as_bad (_("personality routine specified for cantunwind frame"));
4125 unwind
.personality_index
= -2;
4129 /* Parse a personalityindex directive. */
4132 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4136 if (!unwind
.proc_start
)
4137 as_bad (MISSING_FNSTART
);
4139 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4140 as_bad (_("duplicate .personalityindex directive"));
4144 if (exp
.X_op
!= O_constant
4145 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4147 as_bad (_("bad personality routine number"));
4148 ignore_rest_of_line ();
4152 unwind
.personality_index
= exp
.X_add_number
;
4154 demand_empty_rest_of_line ();
4158 /* Parse a personality directive. */
4161 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4165 if (!unwind
.proc_start
)
4166 as_bad (MISSING_FNSTART
);
4168 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4169 as_bad (_("duplicate .personality directive"));
4171 c
= get_symbol_name (& name
);
4172 p
= input_line_pointer
;
4174 ++ input_line_pointer
;
4175 unwind
.personality_routine
= symbol_find_or_make (name
);
4177 demand_empty_rest_of_line ();
4181 /* Parse a directive saving core registers. */
4184 s_arm_unwind_save_core (void)
4190 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4193 as_bad (_("expected register list"));
4194 ignore_rest_of_line ();
4198 demand_empty_rest_of_line ();
4200 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4201 into .unwind_save {..., sp...}. We aren't bothered about the value of
4202 ip because it is clobbered by calls. */
4203 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4204 && (range
& 0x3000) == 0x1000)
4206 unwind
.opcode_count
--;
4207 unwind
.sp_restored
= 0;
4208 range
= (range
| 0x2000) & ~0x1000;
4209 unwind
.pending_offset
= 0;
4215 /* See if we can use the short opcodes. These pop a block of up to 8
4216 registers starting with r4, plus maybe r14. */
4217 for (n
= 0; n
< 8; n
++)
4219 /* Break at the first non-saved register. */
4220 if ((range
& (1 << (n
+ 4))) == 0)
4223 /* See if there are any other bits set. */
4224 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4226 /* Use the long form. */
4227 op
= 0x8000 | ((range
>> 4) & 0xfff);
4228 add_unwind_opcode (op
, 2);
4232 /* Use the short form. */
4234 op
= 0xa8; /* Pop r14. */
4236 op
= 0xa0; /* Do not pop r14. */
4238 add_unwind_opcode (op
, 1);
4245 op
= 0xb100 | (range
& 0xf);
4246 add_unwind_opcode (op
, 2);
4249 /* Record the number of bytes pushed. */
4250 for (n
= 0; n
< 16; n
++)
4252 if (range
& (1 << n
))
4253 unwind
.frame_size
+= 4;
4258 /* Parse a directive saving FPA registers. */
4261 s_arm_unwind_save_fpa (int reg
)
4267 /* Get Number of registers to transfer. */
4268 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4271 exp
.X_op
= O_illegal
;
4273 if (exp
.X_op
!= O_constant
)
4275 as_bad (_("expected , <constant>"));
4276 ignore_rest_of_line ();
4280 num_regs
= exp
.X_add_number
;
4282 if (num_regs
< 1 || num_regs
> 4)
4284 as_bad (_("number of registers must be in the range [1:4]"));
4285 ignore_rest_of_line ();
4289 demand_empty_rest_of_line ();
4294 op
= 0xb4 | (num_regs
- 1);
4295 add_unwind_opcode (op
, 1);
4300 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4301 add_unwind_opcode (op
, 2);
4303 unwind
.frame_size
+= num_regs
* 12;
4307 /* Parse a directive saving VFP registers for ARMv6 and above. */
4310 s_arm_unwind_save_vfp_armv6 (void)
4315 int num_vfpv3_regs
= 0;
4316 int num_regs_below_16
;
4317 bfd_boolean partial_match
;
4319 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4323 as_bad (_("expected register list"));
4324 ignore_rest_of_line ();
4328 demand_empty_rest_of_line ();
4330 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4331 than FSTMX/FLDMX-style ones). */
4333 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4335 num_vfpv3_regs
= count
;
4336 else if (start
+ count
> 16)
4337 num_vfpv3_regs
= start
+ count
- 16;
4339 if (num_vfpv3_regs
> 0)
4341 int start_offset
= start
> 16 ? start
- 16 : 0;
4342 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4343 add_unwind_opcode (op
, 2);
4346 /* Generate opcode for registers numbered in the range 0 .. 15. */
4347 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4348 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4349 if (num_regs_below_16
> 0)
4351 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4352 add_unwind_opcode (op
, 2);
4355 unwind
.frame_size
+= count
* 8;
4359 /* Parse a directive saving VFP registers for pre-ARMv6. */
4362 s_arm_unwind_save_vfp (void)
4367 bfd_boolean partial_match
;
4369 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4373 as_bad (_("expected register list"));
4374 ignore_rest_of_line ();
4378 demand_empty_rest_of_line ();
4383 op
= 0xb8 | (count
- 1);
4384 add_unwind_opcode (op
, 1);
4389 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4390 add_unwind_opcode (op
, 2);
4392 unwind
.frame_size
+= count
* 8 + 4;
4396 /* Parse a directive saving iWMMXt data registers. */
4399 s_arm_unwind_save_mmxwr (void)
4407 if (*input_line_pointer
== '{')
4408 input_line_pointer
++;
4412 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4416 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4421 as_tsktsk (_("register list not in ascending order"));
4424 if (*input_line_pointer
== '-')
4426 input_line_pointer
++;
4427 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4430 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4433 else if (reg
>= hi_reg
)
4435 as_bad (_("bad register range"));
4438 for (; reg
< hi_reg
; reg
++)
4442 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4444 skip_past_char (&input_line_pointer
, '}');
4446 demand_empty_rest_of_line ();
4448 /* Generate any deferred opcodes because we're going to be looking at
4450 flush_pending_unwind ();
4452 for (i
= 0; i
< 16; i
++)
4454 if (mask
& (1 << i
))
4455 unwind
.frame_size
+= 8;
4458 /* Attempt to combine with a previous opcode. We do this because gcc
4459 likes to output separate unwind directives for a single block of
4461 if (unwind
.opcode_count
> 0)
4463 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4464 if ((i
& 0xf8) == 0xc0)
4467 /* Only merge if the blocks are contiguous. */
4470 if ((mask
& 0xfe00) == (1 << 9))
4472 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4473 unwind
.opcode_count
--;
4476 else if (i
== 6 && unwind
.opcode_count
>= 2)
4478 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4482 op
= 0xffff << (reg
- 1);
4484 && ((mask
& op
) == (1u << (reg
- 1))))
4486 op
= (1 << (reg
+ i
+ 1)) - 1;
4487 op
&= ~((1 << reg
) - 1);
4489 unwind
.opcode_count
-= 2;
4496 /* We want to generate opcodes in the order the registers have been
4497 saved, ie. descending order. */
4498 for (reg
= 15; reg
>= -1; reg
--)
4500 /* Save registers in blocks. */
4502 || !(mask
& (1 << reg
)))
4504 /* We found an unsaved reg. Generate opcodes to save the
4511 op
= 0xc0 | (hi_reg
- 10);
4512 add_unwind_opcode (op
, 1);
4517 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4518 add_unwind_opcode (op
, 2);
4527 ignore_rest_of_line ();
4531 s_arm_unwind_save_mmxwcg (void)
4538 if (*input_line_pointer
== '{')
4539 input_line_pointer
++;
4541 skip_whitespace (input_line_pointer
);
4545 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4549 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4555 as_tsktsk (_("register list not in ascending order"));
4558 if (*input_line_pointer
== '-')
4560 input_line_pointer
++;
4561 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4564 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4567 else if (reg
>= hi_reg
)
4569 as_bad (_("bad register range"));
4572 for (; reg
< hi_reg
; reg
++)
4576 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4578 skip_past_char (&input_line_pointer
, '}');
4580 demand_empty_rest_of_line ();
4582 /* Generate any deferred opcodes because we're going to be looking at
4584 flush_pending_unwind ();
4586 for (reg
= 0; reg
< 16; reg
++)
4588 if (mask
& (1 << reg
))
4589 unwind
.frame_size
+= 4;
4592 add_unwind_opcode (op
, 2);
4595 ignore_rest_of_line ();
4599 /* Parse an unwind_save directive.
4600 If the argument is non-zero, this is a .vsave directive. */
4603 s_arm_unwind_save (int arch_v6
)
4606 struct reg_entry
*reg
;
4607 bfd_boolean had_brace
= FALSE
;
4609 if (!unwind
.proc_start
)
4610 as_bad (MISSING_FNSTART
);
4612 /* Figure out what sort of save we have. */
4613 peek
= input_line_pointer
;
4621 reg
= arm_reg_parse_multi (&peek
);
4625 as_bad (_("register expected"));
4626 ignore_rest_of_line ();
4635 as_bad (_("FPA .unwind_save does not take a register list"));
4636 ignore_rest_of_line ();
4639 input_line_pointer
= peek
;
4640 s_arm_unwind_save_fpa (reg
->number
);
4644 s_arm_unwind_save_core ();
4649 s_arm_unwind_save_vfp_armv6 ();
4651 s_arm_unwind_save_vfp ();
4654 case REG_TYPE_MMXWR
:
4655 s_arm_unwind_save_mmxwr ();
4658 case REG_TYPE_MMXWCG
:
4659 s_arm_unwind_save_mmxwcg ();
4663 as_bad (_(".unwind_save does not support this kind of register"));
4664 ignore_rest_of_line ();
4669 /* Parse an unwind_movsp directive. */
4672 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4678 if (!unwind
.proc_start
)
4679 as_bad (MISSING_FNSTART
);
4681 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4684 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4685 ignore_rest_of_line ();
4689 /* Optional constant. */
4690 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4692 if (immediate_for_directive (&offset
) == FAIL
)
4698 demand_empty_rest_of_line ();
4700 if (reg
== REG_SP
|| reg
== REG_PC
)
4702 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4706 if (unwind
.fp_reg
!= REG_SP
)
4707 as_bad (_("unexpected .unwind_movsp directive"));
4709 /* Generate opcode to restore the value. */
4711 add_unwind_opcode (op
, 1);
4713 /* Record the information for later. */
4714 unwind
.fp_reg
= reg
;
4715 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4716 unwind
.sp_restored
= 1;
4719 /* Parse an unwind_pad directive. */
4722 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4726 if (!unwind
.proc_start
)
4727 as_bad (MISSING_FNSTART
);
4729 if (immediate_for_directive (&offset
) == FAIL
)
4734 as_bad (_("stack increment must be multiple of 4"));
4735 ignore_rest_of_line ();
4739 /* Don't generate any opcodes, just record the details for later. */
4740 unwind
.frame_size
+= offset
;
4741 unwind
.pending_offset
+= offset
;
4743 demand_empty_rest_of_line ();
4746 /* Parse an unwind_setfp directive. */
4749 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4755 if (!unwind
.proc_start
)
4756 as_bad (MISSING_FNSTART
);
4758 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4759 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4762 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4764 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4766 as_bad (_("expected <reg>, <reg>"));
4767 ignore_rest_of_line ();
4771 /* Optional constant. */
4772 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4774 if (immediate_for_directive (&offset
) == FAIL
)
4780 demand_empty_rest_of_line ();
4782 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4784 as_bad (_("register must be either sp or set by a previous"
4785 "unwind_movsp directive"));
4789 /* Don't generate any opcodes, just record the information for later. */
4790 unwind
.fp_reg
= fp_reg
;
4792 if (sp_reg
== REG_SP
)
4793 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4795 unwind
.fp_offset
-= offset
;
4798 /* Parse an unwind_raw directive. */
4801 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4804 /* This is an arbitrary limit. */
4805 unsigned char op
[16];
4808 if (!unwind
.proc_start
)
4809 as_bad (MISSING_FNSTART
);
4812 if (exp
.X_op
== O_constant
4813 && skip_past_comma (&input_line_pointer
) != FAIL
)
4815 unwind
.frame_size
+= exp
.X_add_number
;
4819 exp
.X_op
= O_illegal
;
4821 if (exp
.X_op
!= O_constant
)
4823 as_bad (_("expected <offset>, <opcode>"));
4824 ignore_rest_of_line ();
4830 /* Parse the opcode. */
4835 as_bad (_("unwind opcode too long"));
4836 ignore_rest_of_line ();
4838 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4840 as_bad (_("invalid unwind opcode"));
4841 ignore_rest_of_line ();
4844 op
[count
++] = exp
.X_add_number
;
4846 /* Parse the next byte. */
4847 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4853 /* Add the opcode bytes in reverse order. */
4855 add_unwind_opcode (op
[count
], 1);
4857 demand_empty_rest_of_line ();
4861 /* Parse a .eabi_attribute directive. */
4864 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4866 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4868 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4869 attributes_set_explicitly
[tag
] = 1;
4872 /* Emit a tls fix for the symbol. */
4875 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4879 #ifdef md_flush_pending_output
4880 md_flush_pending_output ();
4883 #ifdef md_cons_align
4887 /* Since we're just labelling the code, there's no need to define a
4890 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4891 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4892 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4893 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4895 #endif /* OBJ_ELF */
4897 static void s_arm_arch (int);
4898 static void s_arm_object_arch (int);
4899 static void s_arm_cpu (int);
4900 static void s_arm_fpu (int);
4901 static void s_arm_arch_extension (int);
4906 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4913 if (exp
.X_op
== O_symbol
)
4914 exp
.X_op
= O_secrel
;
4916 emit_expr (&exp
, 4);
4918 while (*input_line_pointer
++ == ',');
4920 input_line_pointer
--;
4921 demand_empty_rest_of_line ();
4925 /* This table describes all the machine specific pseudo-ops the assembler
4926 has to support. The fields are:
4927 pseudo-op name without dot
4928 function to call to execute this pseudo-op
4929 Integer arg to pass to the function. */
4931 const pseudo_typeS md_pseudo_table
[] =
4933 /* Never called because '.req' does not start a line. */
4934 { "req", s_req
, 0 },
4935 /* Following two are likewise never called. */
4938 { "unreq", s_unreq
, 0 },
4939 { "bss", s_bss
, 0 },
4940 { "align", s_align_ptwo
, 2 },
4941 { "arm", s_arm
, 0 },
4942 { "thumb", s_thumb
, 0 },
4943 { "code", s_code
, 0 },
4944 { "force_thumb", s_force_thumb
, 0 },
4945 { "thumb_func", s_thumb_func
, 0 },
4946 { "thumb_set", s_thumb_set
, 0 },
4947 { "even", s_even
, 0 },
4948 { "ltorg", s_ltorg
, 0 },
4949 { "pool", s_ltorg
, 0 },
4950 { "syntax", s_syntax
, 0 },
4951 { "cpu", s_arm_cpu
, 0 },
4952 { "arch", s_arm_arch
, 0 },
4953 { "object_arch", s_arm_object_arch
, 0 },
4954 { "fpu", s_arm_fpu
, 0 },
4955 { "arch_extension", s_arm_arch_extension
, 0 },
4957 { "word", s_arm_elf_cons
, 4 },
4958 { "long", s_arm_elf_cons
, 4 },
4959 { "inst.n", s_arm_elf_inst
, 2 },
4960 { "inst.w", s_arm_elf_inst
, 4 },
4961 { "inst", s_arm_elf_inst
, 0 },
4962 { "rel31", s_arm_rel31
, 0 },
4963 { "fnstart", s_arm_unwind_fnstart
, 0 },
4964 { "fnend", s_arm_unwind_fnend
, 0 },
4965 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4966 { "personality", s_arm_unwind_personality
, 0 },
4967 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4968 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4969 { "save", s_arm_unwind_save
, 0 },
4970 { "vsave", s_arm_unwind_save
, 1 },
4971 { "movsp", s_arm_unwind_movsp
, 0 },
4972 { "pad", s_arm_unwind_pad
, 0 },
4973 { "setfp", s_arm_unwind_setfp
, 0 },
4974 { "unwind_raw", s_arm_unwind_raw
, 0 },
4975 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4976 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4980 /* These are used for dwarf. */
4984 /* These are used for dwarf2. */
4985 { "file", dwarf2_directive_file
, 0 },
4986 { "loc", dwarf2_directive_loc
, 0 },
4987 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4989 { "extend", float_cons
, 'x' },
4990 { "ldouble", float_cons
, 'x' },
4991 { "packed", float_cons
, 'p' },
4993 {"secrel32", pe_directive_secrel
, 0},
4996 /* These are for compatibility with CodeComposer Studio. */
4997 {"ref", s_ccs_ref
, 0},
4998 {"def", s_ccs_def
, 0},
4999 {"asmfunc", s_ccs_asmfunc
, 0},
5000 {"endasmfunc", s_ccs_endasmfunc
, 0},
5005 /* Parser functions used exclusively in instruction operands. */
5007 /* Generic immediate-value read function for use in insn parsing.
5008 STR points to the beginning of the immediate (the leading #);
5009 VAL receives the value; if the value is outside [MIN, MAX]
5010 issue an error. PREFIX_OPT is true if the immediate prefix is
5014 parse_immediate (char **str
, int *val
, int min
, int max
,
5015 bfd_boolean prefix_opt
)
5019 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5020 if (exp
.X_op
!= O_constant
)
5022 inst
.error
= _("constant expression required");
5026 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5028 inst
.error
= _("immediate value out of range");
5032 *val
= exp
.X_add_number
;
5036 /* Less-generic immediate-value read function with the possibility of loading a
5037 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5038 instructions. Puts the result directly in inst.operands[i]. */
5041 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5042 bfd_boolean allow_symbol_p
)
5045 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5048 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5050 if (exp_p
->X_op
== O_constant
)
5052 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5053 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5054 O_constant. We have to be careful not to break compilation for
5055 32-bit X_add_number, though. */
5056 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5058 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5059 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5061 inst
.operands
[i
].regisimm
= 1;
5064 else if (exp_p
->X_op
== O_big
5065 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5067 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5069 /* Bignums have their least significant bits in
5070 generic_bignum[0]. Make sure we put 32 bits in imm and
5071 32 bits in reg, in a (hopefully) portable way. */
5072 gas_assert (parts
!= 0);
5074 /* Make sure that the number is not too big.
5075 PR 11972: Bignums can now be sign-extended to the
5076 size of a .octa so check that the out of range bits
5077 are all zero or all one. */
5078 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5080 LITTLENUM_TYPE m
= -1;
5082 if (generic_bignum
[parts
* 2] != 0
5083 && generic_bignum
[parts
* 2] != m
)
5086 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5087 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5091 inst
.operands
[i
].imm
= 0;
5092 for (j
= 0; j
< parts
; j
++, idx
++)
5093 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5094 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5095 inst
.operands
[i
].reg
= 0;
5096 for (j
= 0; j
< parts
; j
++, idx
++)
5097 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5098 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5099 inst
.operands
[i
].regisimm
= 1;
5101 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5109 /* Returns the pseudo-register number of an FPA immediate constant,
5110 or FAIL if there isn't a valid constant here. */
5113 parse_fpa_immediate (char ** str
)
5115 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5121 /* First try and match exact strings, this is to guarantee
5122 that some formats will work even for cross assembly. */
5124 for (i
= 0; fp_const
[i
]; i
++)
5126 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5130 *str
+= strlen (fp_const
[i
]);
5131 if (is_end_of_line
[(unsigned char) **str
])
5137 /* Just because we didn't get a match doesn't mean that the constant
5138 isn't valid, just that it is in a format that we don't
5139 automatically recognize. Try parsing it with the standard
5140 expression routines. */
5142 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5144 /* Look for a raw floating point number. */
5145 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5146 && is_end_of_line
[(unsigned char) *save_in
])
5148 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5150 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5152 if (words
[j
] != fp_values
[i
][j
])
5156 if (j
== MAX_LITTLENUMS
)
5164 /* Try and parse a more complex expression, this will probably fail
5165 unless the code uses a floating point prefix (eg "0f"). */
5166 save_in
= input_line_pointer
;
5167 input_line_pointer
= *str
;
5168 if (expression (&exp
) == absolute_section
5169 && exp
.X_op
== O_big
5170 && exp
.X_add_number
< 0)
5172 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5174 #define X_PRECISION 5
5175 #define E_PRECISION 15L
5176 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5178 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5180 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5182 if (words
[j
] != fp_values
[i
][j
])
5186 if (j
== MAX_LITTLENUMS
)
5188 *str
= input_line_pointer
;
5189 input_line_pointer
= save_in
;
5196 *str
= input_line_pointer
;
5197 input_line_pointer
= save_in
;
5198 inst
.error
= _("invalid FPA immediate expression");
5202 /* Returns 1 if a number has "quarter-precision" float format
5203 0baBbbbbbc defgh000 00000000 00000000. */
5206 is_quarter_float (unsigned imm
)
5208 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5209 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5213 /* Detect the presence of a floating point or integer zero constant,
5217 parse_ifimm_zero (char **in
)
5221 if (!is_immediate_prefix (**in
))
5223 /* In unified syntax, all prefixes are optional. */
5224 if (!unified_syntax
)
5230 /* Accept #0x0 as a synonym for #0. */
5231 if (strncmp (*in
, "0x", 2) == 0)
5234 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5239 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5240 &generic_floating_point_number
);
5243 && generic_floating_point_number
.sign
== '+'
5244 && (generic_floating_point_number
.low
5245 > generic_floating_point_number
.leader
))
5251 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5252 0baBbbbbbc defgh000 00000000 00000000.
5253 The zero and minus-zero cases need special handling, since they can't be
5254 encoded in the "quarter-precision" float format, but can nonetheless be
5255 loaded as integer constants. */
5258 parse_qfloat_immediate (char **ccp
, int *immed
)
5262 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5263 int found_fpchar
= 0;
5265 skip_past_char (&str
, '#');
5267 /* We must not accidentally parse an integer as a floating-point number. Make
5268 sure that the value we parse is not an integer by checking for special
5269 characters '.' or 'e'.
5270 FIXME: This is a horrible hack, but doing better is tricky because type
5271 information isn't in a very usable state at parse time. */
5273 skip_whitespace (fpnum
);
5275 if (strncmp (fpnum
, "0x", 2) == 0)
5279 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5280 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5290 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5292 unsigned fpword
= 0;
5295 /* Our FP word must be 32 bits (single-precision FP). */
5296 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5298 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5302 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5315 /* Shift operands. */
5318 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5321 struct asm_shift_name
5324 enum shift_kind kind
;
5327 /* Third argument to parse_shift. */
5328 enum parse_shift_mode
5330 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5331 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5332 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5333 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5334 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5335 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5338 /* Parse a <shift> specifier on an ARM data processing instruction.
5339 This has three forms:
5341 (LSL|LSR|ASL|ASR|ROR) Rs
5342 (LSL|LSR|ASL|ASR|ROR) #imm
5345 Note that ASL is assimilated to LSL in the instruction encoding, and
5346 RRX to ROR #0 (which cannot be written as such). */
5349 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5351 const struct asm_shift_name
*shift_name
;
5352 enum shift_kind shift
;
5357 for (p
= *str
; ISALPHA (*p
); p
++)
5362 inst
.error
= _("shift expression expected");
5366 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5369 if (shift_name
== NULL
)
5371 inst
.error
= _("shift expression expected");
5375 shift
= shift_name
->kind
;
5379 case NO_SHIFT_RESTRICT
:
5380 case SHIFT_IMMEDIATE
:
5381 if (shift
== SHIFT_UXTW
)
5383 inst
.error
= _("'UXTW' not allowed here");
5388 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5389 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5391 inst
.error
= _("'LSL' or 'ASR' required");
5396 case SHIFT_LSL_IMMEDIATE
:
5397 if (shift
!= SHIFT_LSL
)
5399 inst
.error
= _("'LSL' required");
5404 case SHIFT_ASR_IMMEDIATE
:
5405 if (shift
!= SHIFT_ASR
)
5407 inst
.error
= _("'ASR' required");
5411 case SHIFT_UXTW_IMMEDIATE
:
5412 if (shift
!= SHIFT_UXTW
)
5414 inst
.error
= _("'UXTW' required");
5422 if (shift
!= SHIFT_RRX
)
5424 /* Whitespace can appear here if the next thing is a bare digit. */
5425 skip_whitespace (p
);
5427 if (mode
== NO_SHIFT_RESTRICT
5428 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5430 inst
.operands
[i
].imm
= reg
;
5431 inst
.operands
[i
].immisreg
= 1;
5433 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5436 inst
.operands
[i
].shift_kind
= shift
;
5437 inst
.operands
[i
].shifted
= 1;
5442 /* Parse a <shifter_operand> for an ARM data processing instruction:
5445 #<immediate>, <rotate>
5449 where <shift> is defined by parse_shift above, and <rotate> is a
5450 multiple of 2 between 0 and 30. Validation of immediate operands
5451 is deferred to md_apply_fix. */
5454 parse_shifter_operand (char **str
, int i
)
5459 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5461 inst
.operands
[i
].reg
= value
;
5462 inst
.operands
[i
].isreg
= 1;
5464 /* parse_shift will override this if appropriate */
5465 inst
.relocs
[0].exp
.X_op
= O_constant
;
5466 inst
.relocs
[0].exp
.X_add_number
= 0;
5468 if (skip_past_comma (str
) == FAIL
)
5471 /* Shift operation on register. */
5472 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5475 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5478 if (skip_past_comma (str
) == SUCCESS
)
5480 /* #x, y -- ie explicit rotation by Y. */
5481 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5484 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5486 inst
.error
= _("constant expression expected");
5490 value
= exp
.X_add_number
;
5491 if (value
< 0 || value
> 30 || value
% 2 != 0)
5493 inst
.error
= _("invalid rotation");
5496 if (inst
.relocs
[0].exp
.X_add_number
< 0
5497 || inst
.relocs
[0].exp
.X_add_number
> 255)
5499 inst
.error
= _("invalid constant");
5503 /* Encode as specified. */
5504 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5508 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5509 inst
.relocs
[0].pc_rel
= 0;
5513 /* Group relocation information. Each entry in the table contains the
5514 textual name of the relocation as may appear in assembler source
5515 and must end with a colon.
5516 Along with this textual name are the relocation codes to be used if
5517 the corresponding instruction is an ALU instruction (ADD or SUB only),
5518 an LDR, an LDRS, or an LDC. */
5520 struct group_reloc_table_entry
5531 /* Varieties of non-ALU group relocation. */
5539 static struct group_reloc_table_entry group_reloc_table
[] =
5540 { /* Program counter relative: */
5542 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5547 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5548 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5549 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5550 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5552 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5557 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5558 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5559 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5560 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5562 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5563 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5564 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5565 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5566 /* Section base relative */
5568 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5573 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5574 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5575 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5576 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5578 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5583 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5584 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5585 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5586 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5588 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5589 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5590 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5591 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5592 /* Absolute thumb alu relocations. */
5594 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5599 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5604 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5609 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5614 /* Given the address of a pointer pointing to the textual name of a group
5615 relocation as may appear in assembler source, attempt to find its details
5616 in group_reloc_table. The pointer will be updated to the character after
5617 the trailing colon. On failure, FAIL will be returned; SUCCESS
5618 otherwise. On success, *entry will be updated to point at the relevant
5619 group_reloc_table entry. */
5622 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5625 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5627 int length
= strlen (group_reloc_table
[i
].name
);
5629 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5630 && (*str
)[length
] == ':')
5632 *out
= &group_reloc_table
[i
];
5633 *str
+= (length
+ 1);
5641 /* Parse a <shifter_operand> for an ARM data processing instruction
5642 (as for parse_shifter_operand) where group relocations are allowed:
5645 #<immediate>, <rotate>
5646 #:<group_reloc>:<expression>
5650 where <group_reloc> is one of the strings defined in group_reloc_table.
5651 The hashes are optional.
5653 Everything else is as for parse_shifter_operand. */
5655 static parse_operand_result
5656 parse_shifter_operand_group_reloc (char **str
, int i
)
5658 /* Determine if we have the sequence of characters #: or just :
5659 coming next. If we do, then we check for a group relocation.
5660 If we don't, punt the whole lot to parse_shifter_operand. */
5662 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5663 || (*str
)[0] == ':')
5665 struct group_reloc_table_entry
*entry
;
5667 if ((*str
)[0] == '#')
5672 /* Try to parse a group relocation. Anything else is an error. */
5673 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5675 inst
.error
= _("unknown group relocation");
5676 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5679 /* We now have the group relocation table entry corresponding to
5680 the name in the assembler source. Next, we parse the expression. */
5681 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5682 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5684 /* Record the relocation type (always the ALU variant here). */
5685 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5686 gas_assert (inst
.relocs
[0].type
!= 0);
5688 return PARSE_OPERAND_SUCCESS
;
5691 return parse_shifter_operand (str
, i
) == SUCCESS
5692 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5694 /* Never reached. */
5697 /* Parse a Neon alignment expression. Information is written to
5698 inst.operands[i]. We assume the initial ':' has been skipped.
5700 align .imm = align << 8, .immisalign=1, .preind=0 */
5701 static parse_operand_result
5702 parse_neon_alignment (char **str
, int i
)
5707 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5709 if (exp
.X_op
!= O_constant
)
5711 inst
.error
= _("alignment must be constant");
5712 return PARSE_OPERAND_FAIL
;
5715 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5716 inst
.operands
[i
].immisalign
= 1;
5717 /* Alignments are not pre-indexes. */
5718 inst
.operands
[i
].preind
= 0;
5721 return PARSE_OPERAND_SUCCESS
;
5724 /* Parse all forms of an ARM address expression. Information is written
5725 to inst.operands[i] and/or inst.relocs[0].
5727 Preindexed addressing (.preind=1):
5729 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5730 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5731 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5732 .shift_kind=shift .relocs[0].exp=shift_imm
5734 These three may have a trailing ! which causes .writeback to be set also.
5736 Postindexed addressing (.postind=1, .writeback=1):
5738 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5739 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5740 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5741 .shift_kind=shift .relocs[0].exp=shift_imm
5743 Unindexed addressing (.preind=0, .postind=0):
5745 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5749 [Rn]{!} shorthand for [Rn,#0]{!}
5750 =immediate .isreg=0 .relocs[0].exp=immediate
5751 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5753 It is the caller's responsibility to check for addressing modes not
5754 supported by the instruction, and to set inst.relocs[0].type. */
5756 static parse_operand_result
5757 parse_address_main (char **str
, int i
, int group_relocations
,
5758 group_reloc_type group_type
)
5763 if (skip_past_char (&p
, '[') == FAIL
)
5765 if (skip_past_char (&p
, '=') == FAIL
)
5767 /* Bare address - translate to PC-relative offset. */
5768 inst
.relocs
[0].pc_rel
= 1;
5769 inst
.operands
[i
].reg
= REG_PC
;
5770 inst
.operands
[i
].isreg
= 1;
5771 inst
.operands
[i
].preind
= 1;
5773 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5774 return PARSE_OPERAND_FAIL
;
5776 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5777 /*allow_symbol_p=*/TRUE
))
5778 return PARSE_OPERAND_FAIL
;
5781 return PARSE_OPERAND_SUCCESS
;
5784 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5785 skip_whitespace (p
);
5787 if (group_type
== GROUP_MVE
)
5789 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5790 struct neon_type_el et
;
5791 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5793 inst
.operands
[i
].isquad
= 1;
5795 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5797 inst
.error
= BAD_ADDR_MODE
;
5798 return PARSE_OPERAND_FAIL
;
5801 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5803 if (group_type
== GROUP_MVE
)
5804 inst
.error
= BAD_ADDR_MODE
;
5806 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5807 return PARSE_OPERAND_FAIL
;
5809 inst
.operands
[i
].reg
= reg
;
5810 inst
.operands
[i
].isreg
= 1;
5812 if (skip_past_comma (&p
) == SUCCESS
)
5814 inst
.operands
[i
].preind
= 1;
5817 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5819 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5820 struct neon_type_el et
;
5821 if (group_type
== GROUP_MVE
5822 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5824 inst
.operands
[i
].immisreg
= 2;
5825 inst
.operands
[i
].imm
= reg
;
5827 if (skip_past_comma (&p
) == SUCCESS
)
5829 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
5831 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
5832 inst
.relocs
[0].exp
.X_add_number
= 0;
5835 return PARSE_OPERAND_FAIL
;
5838 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5840 inst
.operands
[i
].imm
= reg
;
5841 inst
.operands
[i
].immisreg
= 1;
5843 if (skip_past_comma (&p
) == SUCCESS
)
5844 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5845 return PARSE_OPERAND_FAIL
;
5847 else if (skip_past_char (&p
, ':') == SUCCESS
)
5849 /* FIXME: '@' should be used here, but it's filtered out by generic
5850 code before we get to see it here. This may be subject to
5852 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5854 if (result
!= PARSE_OPERAND_SUCCESS
)
5859 if (inst
.operands
[i
].negative
)
5861 inst
.operands
[i
].negative
= 0;
5865 if (group_relocations
5866 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5868 struct group_reloc_table_entry
*entry
;
5870 /* Skip over the #: or : sequence. */
5876 /* Try to parse a group relocation. Anything else is an
5878 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5880 inst
.error
= _("unknown group relocation");
5881 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5884 /* We now have the group relocation table entry corresponding to
5885 the name in the assembler source. Next, we parse the
5887 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5888 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5890 /* Record the relocation type. */
5895 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5900 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5905 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5912 if (inst
.relocs
[0].type
== 0)
5914 inst
.error
= _("this group relocation is not allowed on this instruction");
5915 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5922 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5923 return PARSE_OPERAND_FAIL
;
5924 /* If the offset is 0, find out if it's a +0 or -0. */
5925 if (inst
.relocs
[0].exp
.X_op
== O_constant
5926 && inst
.relocs
[0].exp
.X_add_number
== 0)
5928 skip_whitespace (q
);
5932 skip_whitespace (q
);
5935 inst
.operands
[i
].negative
= 1;
5940 else if (skip_past_char (&p
, ':') == SUCCESS
)
5942 /* FIXME: '@' should be used here, but it's filtered out by generic code
5943 before we get to see it here. This may be subject to change. */
5944 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5946 if (result
!= PARSE_OPERAND_SUCCESS
)
5950 if (skip_past_char (&p
, ']') == FAIL
)
5952 inst
.error
= _("']' expected");
5953 return PARSE_OPERAND_FAIL
;
5956 if (skip_past_char (&p
, '!') == SUCCESS
)
5957 inst
.operands
[i
].writeback
= 1;
5959 else if (skip_past_comma (&p
) == SUCCESS
)
5961 if (skip_past_char (&p
, '{') == SUCCESS
)
5963 /* [Rn], {expr} - unindexed, with option */
5964 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5965 0, 255, TRUE
) == FAIL
)
5966 return PARSE_OPERAND_FAIL
;
5968 if (skip_past_char (&p
, '}') == FAIL
)
5970 inst
.error
= _("'}' expected at end of 'option' field");
5971 return PARSE_OPERAND_FAIL
;
5973 if (inst
.operands
[i
].preind
)
5975 inst
.error
= _("cannot combine index with option");
5976 return PARSE_OPERAND_FAIL
;
5979 return PARSE_OPERAND_SUCCESS
;
5983 inst
.operands
[i
].postind
= 1;
5984 inst
.operands
[i
].writeback
= 1;
5986 if (inst
.operands
[i
].preind
)
5988 inst
.error
= _("cannot combine pre- and post-indexing");
5989 return PARSE_OPERAND_FAIL
;
5993 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5995 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5996 struct neon_type_el et
;
5997 if (group_type
== GROUP_MVE
5998 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6000 inst
.operands
[i
].immisreg
= 2;
6001 inst
.operands
[i
].imm
= reg
;
6003 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6005 /* We might be using the immediate for alignment already. If we
6006 are, OR the register number into the low-order bits. */
6007 if (inst
.operands
[i
].immisalign
)
6008 inst
.operands
[i
].imm
|= reg
;
6010 inst
.operands
[i
].imm
= reg
;
6011 inst
.operands
[i
].immisreg
= 1;
6013 if (skip_past_comma (&p
) == SUCCESS
)
6014 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6015 return PARSE_OPERAND_FAIL
;
6021 if (inst
.operands
[i
].negative
)
6023 inst
.operands
[i
].negative
= 0;
6026 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6027 return PARSE_OPERAND_FAIL
;
6028 /* If the offset is 0, find out if it's a +0 or -0. */
6029 if (inst
.relocs
[0].exp
.X_op
== O_constant
6030 && inst
.relocs
[0].exp
.X_add_number
== 0)
6032 skip_whitespace (q
);
6036 skip_whitespace (q
);
6039 inst
.operands
[i
].negative
= 1;
6045 /* If at this point neither .preind nor .postind is set, we have a
6046 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6047 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6049 inst
.operands
[i
].preind
= 1;
6050 inst
.relocs
[0].exp
.X_op
= O_constant
;
6051 inst
.relocs
[0].exp
.X_add_number
= 0;
6054 return PARSE_OPERAND_SUCCESS
;
6058 parse_address (char **str
, int i
)
6060 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6064 static parse_operand_result
6065 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6067 return parse_address_main (str
, i
, 1, type
);
6070 /* Parse an operand for a MOVW or MOVT instruction. */
6072 parse_half (char **str
)
6077 skip_past_char (&p
, '#');
6078 if (strncasecmp (p
, ":lower16:", 9) == 0)
6079 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6080 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6081 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6083 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6086 skip_whitespace (p
);
6089 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6092 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6094 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6096 inst
.error
= _("constant expression expected");
6099 if (inst
.relocs
[0].exp
.X_add_number
< 0
6100 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6102 inst
.error
= _("immediate value out of range");
6110 /* Miscellaneous. */
6112 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6113 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6115 parse_psr (char **str
, bfd_boolean lhs
)
6118 unsigned long psr_field
;
6119 const struct asm_psr
*psr
;
6121 bfd_boolean is_apsr
= FALSE
;
6122 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6124 /* PR gas/12698: If the user has specified -march=all then m_profile will
6125 be TRUE, but we want to ignore it in this case as we are building for any
6126 CPU type, including non-m variants. */
6127 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6130 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6131 feature for ease of use and backwards compatibility. */
6133 if (strncasecmp (p
, "SPSR", 4) == 0)
6136 goto unsupported_psr
;
6138 psr_field
= SPSR_BIT
;
6140 else if (strncasecmp (p
, "CPSR", 4) == 0)
6143 goto unsupported_psr
;
6147 else if (strncasecmp (p
, "APSR", 4) == 0)
6149 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6150 and ARMv7-R architecture CPUs. */
6159 while (ISALNUM (*p
) || *p
== '_');
6161 if (strncasecmp (start
, "iapsr", 5) == 0
6162 || strncasecmp (start
, "eapsr", 5) == 0
6163 || strncasecmp (start
, "xpsr", 4) == 0
6164 || strncasecmp (start
, "psr", 3) == 0)
6165 p
= start
+ strcspn (start
, "rR") + 1;
6167 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6173 /* If APSR is being written, a bitfield may be specified. Note that
6174 APSR itself is handled above. */
6175 if (psr
->field
<= 3)
6177 psr_field
= psr
->field
;
6183 /* M-profile MSR instructions have the mask field set to "10", except
6184 *PSR variants which modify APSR, which may use a different mask (and
6185 have been handled already). Do that by setting the PSR_f field
6187 return psr
->field
| (lhs
? PSR_f
: 0);
6190 goto unsupported_psr
;
6196 /* A suffix follows. */
6202 while (ISALNUM (*p
) || *p
== '_');
6206 /* APSR uses a notation for bits, rather than fields. */
6207 unsigned int nzcvq_bits
= 0;
6208 unsigned int g_bit
= 0;
6211 for (bit
= start
; bit
!= p
; bit
++)
6213 switch (TOLOWER (*bit
))
6216 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6220 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6224 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6228 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6232 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6236 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6240 inst
.error
= _("unexpected bit specified after APSR");
6245 if (nzcvq_bits
== 0x1f)
6250 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6252 inst
.error
= _("selected processor does not "
6253 "support DSP extension");
6260 if ((nzcvq_bits
& 0x20) != 0
6261 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6262 || (g_bit
& 0x2) != 0)
6264 inst
.error
= _("bad bitmask specified after APSR");
6270 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6275 psr_field
|= psr
->field
;
6281 goto error
; /* Garbage after "[CS]PSR". */
6283 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6284 is deprecated, but allow it anyway. */
6288 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6291 else if (!m_profile
)
6292 /* These bits are never right for M-profile devices: don't set them
6293 (only code paths which read/write APSR reach here). */
6294 psr_field
|= (PSR_c
| PSR_f
);
6300 inst
.error
= _("selected processor does not support requested special "
6301 "purpose register");
6305 inst
.error
= _("flag for {c}psr instruction expected");
6310 parse_sys_vldr_vstr (char **str
)
6319 {"FPSCR", 0x1, 0x0},
6320 {"FPSCR_nzcvqc", 0x2, 0x0},
6323 {"FPCXTNS", 0x6, 0x1},
6324 {"FPCXTS", 0x7, 0x1}
6326 char *op_end
= strchr (*str
, ',');
6327 size_t op_strlen
= op_end
- *str
;
6329 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6331 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6333 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6342 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6343 value suitable for splatting into the AIF field of the instruction. */
6346 parse_cps_flags (char **str
)
6355 case '\0': case ',':
6358 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6359 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6360 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6363 inst
.error
= _("unrecognized CPS flag");
6368 if (saw_a_flag
== 0)
6370 inst
.error
= _("missing CPS flags");
6378 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6379 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6382 parse_endian_specifier (char **str
)
6387 if (strncasecmp (s
, "BE", 2))
6389 else if (strncasecmp (s
, "LE", 2))
6393 inst
.error
= _("valid endian specifiers are be or le");
6397 if (ISALNUM (s
[2]) || s
[2] == '_')
6399 inst
.error
= _("valid endian specifiers are be or le");
6404 return little_endian
;
6407 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6408 value suitable for poking into the rotate field of an sxt or sxta
6409 instruction, or FAIL on error. */
6412 parse_ror (char **str
)
6417 if (strncasecmp (s
, "ROR", 3) == 0)
6421 inst
.error
= _("missing rotation field after comma");
6425 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6430 case 0: *str
= s
; return 0x0;
6431 case 8: *str
= s
; return 0x1;
6432 case 16: *str
= s
; return 0x2;
6433 case 24: *str
= s
; return 0x3;
6436 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6441 /* Parse a conditional code (from conds[] below). The value returned is in the
6442 range 0 .. 14, or FAIL. */
6444 parse_cond (char **str
)
6447 const struct asm_cond
*c
;
6449 /* Condition codes are always 2 characters, so matching up to
6450 3 characters is sufficient. */
6455 while (ISALPHA (*q
) && n
< 3)
6457 cond
[n
] = TOLOWER (*q
);
6462 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6465 inst
.error
= _("condition required");
6473 /* Parse an option for a barrier instruction. Returns the encoding for the
6476 parse_barrier (char **str
)
6479 const struct asm_barrier_opt
*o
;
6482 while (ISALPHA (*q
))
6485 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6490 if (!mark_feature_used (&o
->arch
))
6497 /* Parse the operands of a table branch instruction. Similar to a memory
6500 parse_tb (char **str
)
6505 if (skip_past_char (&p
, '[') == FAIL
)
6507 inst
.error
= _("'[' expected");
6511 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6513 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6516 inst
.operands
[0].reg
= reg
;
6518 if (skip_past_comma (&p
) == FAIL
)
6520 inst
.error
= _("',' expected");
6524 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6526 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6529 inst
.operands
[0].imm
= reg
;
6531 if (skip_past_comma (&p
) == SUCCESS
)
6533 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6535 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6537 inst
.error
= _("invalid shift");
6540 inst
.operands
[0].shifted
= 1;
6543 if (skip_past_char (&p
, ']') == FAIL
)
6545 inst
.error
= _("']' expected");
6552 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6553 information on the types the operands can take and how they are encoded.
6554 Up to four operands may be read; this function handles setting the
6555 ".present" field for each read operand itself.
6556 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6557 else returns FAIL. */
6560 parse_neon_mov (char **str
, int *which_operand
)
6562 int i
= *which_operand
, val
;
6563 enum arm_reg_type rtype
;
6565 struct neon_type_el optype
;
6567 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6569 /* Cases 17 or 19. */
6570 inst
.operands
[i
].reg
= val
;
6571 inst
.operands
[i
].isvec
= 1;
6572 inst
.operands
[i
].isscalar
= 2;
6573 inst
.operands
[i
].vectype
= optype
;
6574 inst
.operands
[i
++].present
= 1;
6576 if (skip_past_comma (&ptr
) == FAIL
)
6579 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6581 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6582 inst
.operands
[i
].reg
= val
;
6583 inst
.operands
[i
].isreg
= 1;
6584 inst
.operands
[i
].present
= 1;
6586 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6588 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6589 inst
.operands
[i
].reg
= val
;
6590 inst
.operands
[i
].isvec
= 1;
6591 inst
.operands
[i
].isscalar
= 2;
6592 inst
.operands
[i
].vectype
= optype
;
6593 inst
.operands
[i
++].present
= 1;
6595 if (skip_past_comma (&ptr
) == FAIL
)
6598 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6601 inst
.operands
[i
].reg
= val
;
6602 inst
.operands
[i
].isreg
= 1;
6603 inst
.operands
[i
++].present
= 1;
6605 if (skip_past_comma (&ptr
) == FAIL
)
6608 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6611 inst
.operands
[i
].reg
= val
;
6612 inst
.operands
[i
].isreg
= 1;
6613 inst
.operands
[i
].present
= 1;
6617 first_error (_("expected ARM or MVE vector register"));
6621 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6623 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6624 inst
.operands
[i
].reg
= val
;
6625 inst
.operands
[i
].isscalar
= 1;
6626 inst
.operands
[i
].vectype
= optype
;
6627 inst
.operands
[i
++].present
= 1;
6629 if (skip_past_comma (&ptr
) == FAIL
)
6632 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6635 inst
.operands
[i
].reg
= val
;
6636 inst
.operands
[i
].isreg
= 1;
6637 inst
.operands
[i
].present
= 1;
6639 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6641 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6644 /* Cases 0, 1, 2, 3, 5 (D only). */
6645 if (skip_past_comma (&ptr
) == FAIL
)
6648 inst
.operands
[i
].reg
= val
;
6649 inst
.operands
[i
].isreg
= 1;
6650 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6651 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6652 inst
.operands
[i
].isvec
= 1;
6653 inst
.operands
[i
].vectype
= optype
;
6654 inst
.operands
[i
++].present
= 1;
6656 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6658 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6659 Case 13: VMOV <Sd>, <Rm> */
6660 inst
.operands
[i
].reg
= val
;
6661 inst
.operands
[i
].isreg
= 1;
6662 inst
.operands
[i
].present
= 1;
6664 if (rtype
== REG_TYPE_NQ
)
6666 first_error (_("can't use Neon quad register here"));
6669 else if (rtype
!= REG_TYPE_VFS
)
6672 if (skip_past_comma (&ptr
) == FAIL
)
6674 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6676 inst
.operands
[i
].reg
= val
;
6677 inst
.operands
[i
].isreg
= 1;
6678 inst
.operands
[i
].present
= 1;
6681 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6684 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6685 Case 1: VMOV<c><q> <Dd>, <Dm>
6686 Case 8: VMOV.F32 <Sd>, <Sm>
6687 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6689 inst
.operands
[i
].reg
= val
;
6690 inst
.operands
[i
].isreg
= 1;
6691 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6692 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6693 inst
.operands
[i
].isvec
= 1;
6694 inst
.operands
[i
].vectype
= optype
;
6695 inst
.operands
[i
].present
= 1;
6697 if (skip_past_comma (&ptr
) == SUCCESS
)
6702 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6705 inst
.operands
[i
].reg
= val
;
6706 inst
.operands
[i
].isreg
= 1;
6707 inst
.operands
[i
++].present
= 1;
6709 if (skip_past_comma (&ptr
) == FAIL
)
6712 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6715 inst
.operands
[i
].reg
= val
;
6716 inst
.operands
[i
].isreg
= 1;
6717 inst
.operands
[i
].present
= 1;
6720 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6721 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6722 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6723 Case 10: VMOV.F32 <Sd>, #<imm>
6724 Case 11: VMOV.F64 <Dd>, #<imm> */
6725 inst
.operands
[i
].immisfloat
= 1;
6726 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6728 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6729 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6733 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6737 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6739 /* Cases 6, 7, 16, 18. */
6740 inst
.operands
[i
].reg
= val
;
6741 inst
.operands
[i
].isreg
= 1;
6742 inst
.operands
[i
++].present
= 1;
6744 if (skip_past_comma (&ptr
) == FAIL
)
6747 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6749 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6750 inst
.operands
[i
].reg
= val
;
6751 inst
.operands
[i
].isscalar
= 2;
6752 inst
.operands
[i
].present
= 1;
6753 inst
.operands
[i
].vectype
= optype
;
6755 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6757 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6758 inst
.operands
[i
].reg
= val
;
6759 inst
.operands
[i
].isscalar
= 1;
6760 inst
.operands
[i
].present
= 1;
6761 inst
.operands
[i
].vectype
= optype
;
6763 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6765 inst
.operands
[i
].reg
= val
;
6766 inst
.operands
[i
].isreg
= 1;
6767 inst
.operands
[i
++].present
= 1;
6769 if (skip_past_comma (&ptr
) == FAIL
)
6772 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6775 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6777 inst
.operands
[i
].reg
= val
;
6778 inst
.operands
[i
].isreg
= 1;
6779 inst
.operands
[i
].isvec
= 1;
6780 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6781 inst
.operands
[i
].vectype
= optype
;
6782 inst
.operands
[i
].present
= 1;
6784 if (rtype
== REG_TYPE_VFS
)
6788 if (skip_past_comma (&ptr
) == FAIL
)
6790 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6793 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6796 inst
.operands
[i
].reg
= val
;
6797 inst
.operands
[i
].isreg
= 1;
6798 inst
.operands
[i
].isvec
= 1;
6799 inst
.operands
[i
].issingle
= 1;
6800 inst
.operands
[i
].vectype
= optype
;
6801 inst
.operands
[i
].present
= 1;
6806 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6809 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6810 inst
.operands
[i
].reg
= val
;
6811 inst
.operands
[i
].isvec
= 1;
6812 inst
.operands
[i
].isscalar
= 2;
6813 inst
.operands
[i
].vectype
= optype
;
6814 inst
.operands
[i
++].present
= 1;
6816 if (skip_past_comma (&ptr
) == FAIL
)
6819 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6822 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
6825 inst
.operands
[i
].reg
= val
;
6826 inst
.operands
[i
].isvec
= 1;
6827 inst
.operands
[i
].isscalar
= 2;
6828 inst
.operands
[i
].vectype
= optype
;
6829 inst
.operands
[i
].present
= 1;
6833 first_error (_("VFP single, double or MVE vector register"
6839 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6843 inst
.operands
[i
].reg
= val
;
6844 inst
.operands
[i
].isreg
= 1;
6845 inst
.operands
[i
].isvec
= 1;
6846 inst
.operands
[i
].issingle
= 1;
6847 inst
.operands
[i
].vectype
= optype
;
6848 inst
.operands
[i
].present
= 1;
6853 first_error (_("parse error"));
6857 /* Successfully parsed the operands. Update args. */
6863 first_error (_("expected comma"));
6867 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6871 /* Use this macro when the operand constraints are different
6872 for ARM and THUMB (e.g. ldrd). */
6873 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6874 ((arm_operand) | ((thumb_operand) << 16))
6876 /* Matcher codes for parse_operands. */
6877 enum operand_parse_code
6879 OP_stop
, /* end of line */
6881 OP_RR
, /* ARM register */
6882 OP_RRnpc
, /* ARM register, not r15 */
6883 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6884 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6885 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6886 optional trailing ! */
6887 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6888 OP_RCP
, /* Coprocessor number */
6889 OP_RCN
, /* Coprocessor register */
6890 OP_RF
, /* FPA register */
6891 OP_RVS
, /* VFP single precision register */
6892 OP_RVD
, /* VFP double precision register (0..15) */
6893 OP_RND
, /* Neon double precision register (0..31) */
6894 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
6895 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
6897 OP_RNQ
, /* Neon quad precision register */
6898 OP_RNQMQ
, /* Neon quad or MVE vector register. */
6899 OP_RVSD
, /* VFP single or double precision register */
6900 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
6901 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
6902 OP_RNSD
, /* Neon single or double precision register */
6903 OP_RNDQ
, /* Neon double or quad precision register */
6904 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
6905 OP_RNSDQ
, /* Neon single, double or quad precision register */
6906 OP_RNSC
, /* Neon scalar D[X] */
6907 OP_RVC
, /* VFP control register */
6908 OP_RMF
, /* Maverick F register */
6909 OP_RMD
, /* Maverick D register */
6910 OP_RMFX
, /* Maverick FX register */
6911 OP_RMDX
, /* Maverick DX register */
6912 OP_RMAX
, /* Maverick AX register */
6913 OP_RMDS
, /* Maverick DSPSC register */
6914 OP_RIWR
, /* iWMMXt wR register */
6915 OP_RIWC
, /* iWMMXt wC register */
6916 OP_RIWG
, /* iWMMXt wCG register */
6917 OP_RXA
, /* XScale accumulator register */
6919 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
6921 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
6923 OP_RMQ
, /* MVE vector register. */
6924 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
6926 /* New operands for Armv8.1-M Mainline. */
6927 OP_LR
, /* ARM LR register */
6928 OP_RRe
, /* ARM register, only even numbered. */
6929 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
6930 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
6932 OP_REGLST
, /* ARM register list */
6933 OP_CLRMLST
, /* CLRM register list */
6934 OP_VRSLST
, /* VFP single-precision register list */
6935 OP_VRDLST
, /* VFP double-precision register list */
6936 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6937 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6938 OP_NSTRLST
, /* Neon element/structure list */
6939 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
6940 OP_MSTRLST2
, /* MVE vector list with two elements. */
6941 OP_MSTRLST4
, /* MVE vector list with four elements. */
6943 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6944 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6945 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6946 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
6948 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6949 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6950 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6951 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
6953 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6954 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
6955 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6956 OP_VMOV
, /* Neon VMOV operands. */
6957 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6958 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
6960 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6961 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6962 OP_VLDR
, /* VLDR operand. */
6964 OP_I0
, /* immediate zero */
6965 OP_I7
, /* immediate value 0 .. 7 */
6966 OP_I15
, /* 0 .. 15 */
6967 OP_I16
, /* 1 .. 16 */
6968 OP_I16z
, /* 0 .. 16 */
6969 OP_I31
, /* 0 .. 31 */
6970 OP_I31w
, /* 0 .. 31, optional trailing ! */
6971 OP_I32
, /* 1 .. 32 */
6972 OP_I32z
, /* 0 .. 32 */
6973 OP_I63
, /* 0 .. 63 */
6974 OP_I63s
, /* -64 .. 63 */
6975 OP_I64
, /* 1 .. 64 */
6976 OP_I64z
, /* 0 .. 64 */
6977 OP_I255
, /* 0 .. 255 */
6979 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6980 OP_I7b
, /* 0 .. 7 */
6981 OP_I15b
, /* 0 .. 15 */
6982 OP_I31b
, /* 0 .. 31 */
6984 OP_SH
, /* shifter operand */
6985 OP_SHG
, /* shifter operand with possible group relocation */
6986 OP_ADDR
, /* Memory address expression (any mode) */
6987 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
6988 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6989 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6990 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6991 OP_EXP
, /* arbitrary expression */
6992 OP_EXPi
, /* same, with optional immediate prefix */
6993 OP_EXPr
, /* same, with optional relocation suffix */
6994 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
6995 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6996 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6997 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6999 OP_CPSF
, /* CPS flags */
7000 OP_ENDI
, /* Endianness specifier */
7001 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7002 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7003 OP_COND
, /* conditional code */
7004 OP_TB
, /* Table branch. */
7006 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7008 OP_RRnpc_I0
, /* ARM register or literal 0 */
7009 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7010 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7011 OP_RF_IF
, /* FPA register or immediate */
7012 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7013 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7015 /* Optional operands. */
7016 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7017 OP_oI31b
, /* 0 .. 31 */
7018 OP_oI32b
, /* 1 .. 32 */
7019 OP_oI32z
, /* 0 .. 32 */
7020 OP_oIffffb
, /* 0 .. 65535 */
7021 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7023 OP_oRR
, /* ARM register */
7024 OP_oLR
, /* ARM LR register */
7025 OP_oRRnpc
, /* ARM register, not the PC */
7026 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7027 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7028 OP_oRND
, /* Optional Neon double precision register */
7029 OP_oRNQ
, /* Optional Neon quad precision register */
7030 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7031 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7032 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7033 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7035 OP_oSHll
, /* LSL immediate */
7036 OP_oSHar
, /* ASR immediate */
7037 OP_oSHllar
, /* LSL or ASR immediate */
7038 OP_oROR
, /* ROR 0/8/16/24 */
7039 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7041 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7043 /* Some pre-defined mixed (ARM/THUMB) operands. */
7044 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7045 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7046 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7048 OP_FIRST_OPTIONAL
= OP_oI7b
7051 /* Generic instruction operand parser. This does no encoding and no
7052 semantic validation; it merely squirrels values away in the inst
7053 structure. Returns SUCCESS or FAIL depending on whether the
7054 specified grammar matched. */
7056 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7058 unsigned const int *upat
= pattern
;
7059 char *backtrack_pos
= 0;
7060 const char *backtrack_error
= 0;
7061 int i
, val
= 0, backtrack_index
= 0;
7062 enum arm_reg_type rtype
;
7063 parse_operand_result result
;
7064 unsigned int op_parse_code
;
7065 bfd_boolean partial_match
;
7067 #define po_char_or_fail(chr) \
7070 if (skip_past_char (&str, chr) == FAIL) \
7075 #define po_reg_or_fail(regtype) \
7078 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7079 & inst.operands[i].vectype); \
7082 first_error (_(reg_expected_msgs[regtype])); \
7085 inst.operands[i].reg = val; \
7086 inst.operands[i].isreg = 1; \
7087 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7088 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7089 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7090 || rtype == REG_TYPE_VFD \
7091 || rtype == REG_TYPE_NQ); \
7092 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7096 #define po_reg_or_goto(regtype, label) \
7099 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7100 & inst.operands[i].vectype); \
7104 inst.operands[i].reg = val; \
7105 inst.operands[i].isreg = 1; \
7106 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7107 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7108 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7109 || rtype == REG_TYPE_VFD \
7110 || rtype == REG_TYPE_NQ); \
7111 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7115 #define po_imm_or_fail(min, max, popt) \
7118 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7120 inst.operands[i].imm = val; \
7124 #define po_scalar_or_goto(elsz, label, reg_type) \
7127 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7131 inst.operands[i].reg = val; \
7132 inst.operands[i].isscalar = 1; \
7136 #define po_misc_or_fail(expr) \
7144 #define po_misc_or_fail_no_backtrack(expr) \
7148 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7149 backtrack_pos = 0; \
7150 if (result != PARSE_OPERAND_SUCCESS) \
7155 #define po_barrier_or_imm(str) \
7158 val = parse_barrier (&str); \
7159 if (val == FAIL && ! ISALPHA (*str)) \
7162 /* ISB can only take SY as an option. */ \
7163 || ((inst.instruction & 0xf0) == 0x60 \
7166 inst.error = _("invalid barrier type"); \
7167 backtrack_pos = 0; \
7173 skip_whitespace (str
);
7175 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7177 op_parse_code
= upat
[i
];
7178 if (op_parse_code
>= 1<<16)
7179 op_parse_code
= thumb
? (op_parse_code
>> 16)
7180 : (op_parse_code
& ((1<<16)-1));
7182 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7184 /* Remember where we are in case we need to backtrack. */
7185 backtrack_pos
= str
;
7186 backtrack_error
= inst
.error
;
7187 backtrack_index
= i
;
7190 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7191 po_char_or_fail (',');
7193 switch (op_parse_code
)
7205 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7206 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7207 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7208 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7209 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7210 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7213 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7217 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7220 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7222 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7224 /* Also accept generic coprocessor regs for unknown registers. */
7226 po_reg_or_fail (REG_TYPE_CN
);
7228 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7229 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7230 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7231 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7232 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7233 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7234 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7235 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7236 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7237 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7240 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7243 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7244 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7247 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7251 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7253 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7256 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7258 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7261 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7263 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7268 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7271 po_reg_or_fail (REG_TYPE_NSDQ
);
7275 po_reg_or_fail (REG_TYPE_MQ
);
7277 /* Neon scalar. Using an element size of 8 means that some invalid
7278 scalars are accepted here, so deal with those in later code. */
7279 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7283 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7286 po_imm_or_fail (0, 0, TRUE
);
7291 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7295 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7300 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7303 if (parse_ifimm_zero (&str
))
7304 inst
.operands
[i
].imm
= 0;
7308 = _("only floating point zero is allowed as immediate value");
7316 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7319 po_reg_or_fail (REG_TYPE_RN
);
7323 case OP_RNSDQ_RNSC_MQ
:
7324 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7329 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7333 po_reg_or_fail (REG_TYPE_NSDQ
);
7340 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7343 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7346 po_reg_or_fail (REG_TYPE_NSD
);
7350 case OP_RNDQMQ_RNSC
:
7351 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7356 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7359 po_reg_or_fail (REG_TYPE_NDQ
);
7365 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7368 po_reg_or_fail (REG_TYPE_VFD
);
7373 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7374 not careful then bad things might happen. */
7375 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7378 case OP_RNDQMQ_Ibig
:
7379 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7384 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7387 /* There's a possibility of getting a 64-bit immediate here, so
7388 we need special handling. */
7389 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7392 inst
.error
= _("immediate value is out of range");
7400 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7403 po_imm_or_fail (0, 63, TRUE
);
7408 po_char_or_fail ('[');
7409 po_reg_or_fail (REG_TYPE_RN
);
7410 po_char_or_fail (']');
7416 po_reg_or_fail (REG_TYPE_RN
);
7417 if (skip_past_char (&str
, '!') == SUCCESS
)
7418 inst
.operands
[i
].writeback
= 1;
7422 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7423 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7424 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7425 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7426 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7427 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7428 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7429 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7430 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7431 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7432 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7433 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7435 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7437 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7438 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7440 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7441 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7442 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7443 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7445 /* Immediate variants */
7447 po_char_or_fail ('{');
7448 po_imm_or_fail (0, 255, TRUE
);
7449 po_char_or_fail ('}');
7453 /* The expression parser chokes on a trailing !, so we have
7454 to find it first and zap it. */
7457 while (*s
&& *s
!= ',')
7462 inst
.operands
[i
].writeback
= 1;
7464 po_imm_or_fail (0, 31, TRUE
);
7472 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7477 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7482 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7484 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7486 val
= parse_reloc (&str
);
7489 inst
.error
= _("unrecognized relocation suffix");
7492 else if (val
!= BFD_RELOC_UNUSED
)
7494 inst
.operands
[i
].imm
= val
;
7495 inst
.operands
[i
].hasreloc
= 1;
7501 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7503 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7505 inst
.operands
[i
].hasreloc
= 1;
7507 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7509 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7510 inst
.operands
[i
].hasreloc
= 0;
7514 /* Operand for MOVW or MOVT. */
7516 po_misc_or_fail (parse_half (&str
));
7519 /* Register or expression. */
7520 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7521 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7523 /* Register or immediate. */
7524 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7525 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7527 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7529 if (!is_immediate_prefix (*str
))
7532 val
= parse_fpa_immediate (&str
);
7535 /* FPA immediates are encoded as registers 8-15.
7536 parse_fpa_immediate has already applied the offset. */
7537 inst
.operands
[i
].reg
= val
;
7538 inst
.operands
[i
].isreg
= 1;
7541 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7542 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7544 /* Two kinds of register. */
7547 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7549 || (rege
->type
!= REG_TYPE_MMXWR
7550 && rege
->type
!= REG_TYPE_MMXWC
7551 && rege
->type
!= REG_TYPE_MMXWCG
))
7553 inst
.error
= _("iWMMXt data or control register expected");
7556 inst
.operands
[i
].reg
= rege
->number
;
7557 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7563 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7565 || (rege
->type
!= REG_TYPE_MMXWC
7566 && rege
->type
!= REG_TYPE_MMXWCG
))
7568 inst
.error
= _("iWMMXt control register expected");
7571 inst
.operands
[i
].reg
= rege
->number
;
7572 inst
.operands
[i
].isreg
= 1;
7577 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7578 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7579 case OP_oROR
: val
= parse_ror (&str
); break;
7581 case OP_COND
: val
= parse_cond (&str
); break;
7582 case OP_oBARRIER_I15
:
7583 po_barrier_or_imm (str
); break;
7585 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7591 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7592 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7594 inst
.error
= _("Banked registers are not available with this "
7600 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7604 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7607 val
= parse_sys_vldr_vstr (&str
);
7611 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7614 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7616 if (strncasecmp (str
, "APSR_", 5) == 0)
7623 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7624 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7625 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7626 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7627 default: found
= 16;
7631 inst
.operands
[i
].isvec
= 1;
7632 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7633 inst
.operands
[i
].reg
= REG_PC
;
7640 po_misc_or_fail (parse_tb (&str
));
7643 /* Register lists. */
7645 val
= parse_reg_list (&str
, REGLIST_RN
);
7648 inst
.operands
[i
].writeback
= 1;
7654 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7658 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7663 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7668 /* Allow Q registers too. */
7669 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7670 REGLIST_NEON_D
, &partial_match
);
7674 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7675 REGLIST_VFP_S
, &partial_match
);
7676 inst
.operands
[i
].issingle
= 1;
7681 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7682 REGLIST_VFP_D_VPR
, &partial_match
);
7683 if (val
== FAIL
&& !partial_match
)
7686 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7687 REGLIST_VFP_S_VPR
, &partial_match
);
7688 inst
.operands
[i
].issingle
= 1;
7693 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7694 REGLIST_NEON_D
, &partial_match
);
7699 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7700 1, &inst
.operands
[i
].vectype
);
7701 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7705 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7706 0, &inst
.operands
[i
].vectype
);
7709 /* Addressing modes */
7711 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7715 po_misc_or_fail (parse_address (&str
, i
));
7719 po_misc_or_fail_no_backtrack (
7720 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7724 po_misc_or_fail_no_backtrack (
7725 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7729 po_misc_or_fail_no_backtrack (
7730 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7734 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7738 po_misc_or_fail_no_backtrack (
7739 parse_shifter_operand_group_reloc (&str
, i
));
7743 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7747 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7751 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7756 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
7759 po_reg_or_goto (REG_TYPE_RN
, ZR
);
7762 po_reg_or_fail (REG_TYPE_ZR
);
7766 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7769 /* Various value-based sanity checks and shared operations. We
7770 do not signal immediate failures for the register constraints;
7771 this allows a syntax error to take precedence. */
7772 switch (op_parse_code
)
7780 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7781 inst
.error
= BAD_PC
;
7786 if (inst
.operands
[i
].isreg
)
7788 if (inst
.operands
[i
].reg
== REG_PC
)
7789 inst
.error
= BAD_PC
;
7790 else if (inst
.operands
[i
].reg
== REG_SP
7791 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7792 relaxed since ARMv8-A. */
7793 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7796 inst
.error
= BAD_SP
;
7802 if (inst
.operands
[i
].isreg
7803 && inst
.operands
[i
].reg
== REG_PC
7804 && (inst
.operands
[i
].writeback
|| thumb
))
7805 inst
.error
= BAD_PC
;
7810 if (inst
.operands
[i
].isreg
)
7820 case OP_oBARRIER_I15
:
7833 inst
.operands
[i
].imm
= val
;
7838 if (inst
.operands
[i
].reg
!= REG_LR
)
7839 inst
.error
= _("operand must be LR register");
7844 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
7845 inst
.error
= BAD_PC
;
7849 if (inst
.operands
[i
].isreg
7850 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
7851 inst
.error
= BAD_ODD
;
7855 if (inst
.operands
[i
].isreg
)
7857 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
7858 inst
.error
= BAD_EVEN
;
7859 else if (inst
.operands
[i
].reg
== REG_SP
)
7860 as_tsktsk (MVE_BAD_SP
);
7861 else if (inst
.operands
[i
].reg
== REG_PC
)
7862 inst
.error
= BAD_PC
;
7870 /* If we get here, this operand was successfully parsed. */
7871 inst
.operands
[i
].present
= 1;
7875 inst
.error
= BAD_ARGS
;
7880 /* The parse routine should already have set inst.error, but set a
7881 default here just in case. */
7883 inst
.error
= BAD_SYNTAX
;
7887 /* Do not backtrack over a trailing optional argument that
7888 absorbed some text. We will only fail again, with the
7889 'garbage following instruction' error message, which is
7890 probably less helpful than the current one. */
7891 if (backtrack_index
== i
&& backtrack_pos
!= str
7892 && upat
[i
+1] == OP_stop
)
7895 inst
.error
= BAD_SYNTAX
;
7899 /* Try again, skipping the optional argument at backtrack_pos. */
7900 str
= backtrack_pos
;
7901 inst
.error
= backtrack_error
;
7902 inst
.operands
[backtrack_index
].present
= 0;
7903 i
= backtrack_index
;
7907 /* Check that we have parsed all the arguments. */
7908 if (*str
!= '\0' && !inst
.error
)
7909 inst
.error
= _("garbage following instruction");
7911 return inst
.error
? FAIL
: SUCCESS
;
7914 #undef po_char_or_fail
7915 #undef po_reg_or_fail
7916 #undef po_reg_or_goto
7917 #undef po_imm_or_fail
7918 #undef po_scalar_or_fail
7919 #undef po_barrier_or_imm
7921 /* Shorthand macro for instruction encoding functions issuing errors. */
7922 #define constraint(expr, err) \
7933 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7934 instructions are unpredictable if these registers are used. This
7935 is the BadReg predicate in ARM's Thumb-2 documentation.
7937 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7938 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7939 #define reject_bad_reg(reg) \
7941 if (reg == REG_PC) \
7943 inst.error = BAD_PC; \
7946 else if (reg == REG_SP \
7947 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7949 inst.error = BAD_SP; \
7954 /* If REG is R13 (the stack pointer), warn that its use is
7956 #define warn_deprecated_sp(reg) \
7958 if (warn_on_deprecated && reg == REG_SP) \
7959 as_tsktsk (_("use of r13 is deprecated")); \
7962 /* Functions for operand encoding. ARM, then Thumb. */
7964 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7966 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7968 The only binary encoding difference is the Coprocessor number. Coprocessor
7969 9 is used for half-precision calculations or conversions. The format of the
7970 instruction is the same as the equivalent Coprocessor 10 instruction that
7971 exists for Single-Precision operation. */
7974 do_scalar_fp16_v82_encode (void)
7976 if (inst
.cond
< COND_ALWAYS
)
7977 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7978 " the behaviour is UNPREDICTABLE"));
7979 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7982 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7983 mark_feature_used (&arm_ext_fp16
);
7986 /* If VAL can be encoded in the immediate field of an ARM instruction,
7987 return the encoded form. Otherwise, return FAIL. */
7990 encode_arm_immediate (unsigned int val
)
7997 for (i
= 2; i
< 32; i
+= 2)
7998 if ((a
= rotate_left (val
, i
)) <= 0xff)
7999 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8004 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8005 return the encoded form. Otherwise, return FAIL. */
8007 encode_thumb32_immediate (unsigned int val
)
8014 for (i
= 1; i
<= 24; i
++)
8017 if ((val
& ~(0xff << i
)) == 0)
8018 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8022 if (val
== ((a
<< 16) | a
))
8024 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8028 if (val
== ((a
<< 16) | a
))
8029 return 0x200 | (a
>> 8);
8033 /* Encode a VFP SP or DP register number into inst.instruction. */
8036 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8038 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8041 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8044 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8047 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8052 first_error (_("D register out of range for selected VFP version"));
8060 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8064 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8068 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8072 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8076 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8080 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8088 /* Encode a <shift> in an ARM-format instruction. The immediate,
8089 if any, is handled by md_apply_fix. */
8091 encode_arm_shift (int i
)
8093 /* register-shifted register. */
8094 if (inst
.operands
[i
].immisreg
)
8097 for (op_index
= 0; op_index
<= i
; ++op_index
)
8099 /* Check the operand only when it's presented. In pre-UAL syntax,
8100 if the destination register is the same as the first operand, two
8101 register form of the instruction can be used. */
8102 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8103 && inst
.operands
[op_index
].reg
== REG_PC
)
8104 as_warn (UNPRED_REG ("r15"));
8107 if (inst
.operands
[i
].imm
== REG_PC
)
8108 as_warn (UNPRED_REG ("r15"));
8111 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8112 inst
.instruction
|= SHIFT_ROR
<< 5;
8115 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8116 if (inst
.operands
[i
].immisreg
)
8118 inst
.instruction
|= SHIFT_BY_REG
;
8119 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8122 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8127 encode_arm_shifter_operand (int i
)
8129 if (inst
.operands
[i
].isreg
)
8131 inst
.instruction
|= inst
.operands
[i
].reg
;
8132 encode_arm_shift (i
);
8136 inst
.instruction
|= INST_IMMEDIATE
;
8137 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8138 inst
.instruction
|= inst
.operands
[i
].imm
;
8142 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8144 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8147 Generate an error if the operand is not a register. */
8148 constraint (!inst
.operands
[i
].isreg
,
8149 _("Instruction does not support =N addresses"));
8151 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8153 if (inst
.operands
[i
].preind
)
8157 inst
.error
= _("instruction does not accept preindexed addressing");
8160 inst
.instruction
|= PRE_INDEX
;
8161 if (inst
.operands
[i
].writeback
)
8162 inst
.instruction
|= WRITE_BACK
;
8165 else if (inst
.operands
[i
].postind
)
8167 gas_assert (inst
.operands
[i
].writeback
);
8169 inst
.instruction
|= WRITE_BACK
;
8171 else /* unindexed - only for coprocessor */
8173 inst
.error
= _("instruction does not accept unindexed addressing");
8177 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8178 && (((inst
.instruction
& 0x000f0000) >> 16)
8179 == ((inst
.instruction
& 0x0000f000) >> 12)))
8180 as_warn ((inst
.instruction
& LOAD_BIT
)
8181 ? _("destination register same as write-back base")
8182 : _("source register same as write-back base"));
8185 /* inst.operands[i] was set up by parse_address. Encode it into an
8186 ARM-format mode 2 load or store instruction. If is_t is true,
8187 reject forms that cannot be used with a T instruction (i.e. not
8190 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8192 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8194 encode_arm_addr_mode_common (i
, is_t
);
8196 if (inst
.operands
[i
].immisreg
)
8198 constraint ((inst
.operands
[i
].imm
== REG_PC
8199 || (is_pc
&& inst
.operands
[i
].writeback
)),
8201 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8202 inst
.instruction
|= inst
.operands
[i
].imm
;
8203 if (!inst
.operands
[i
].negative
)
8204 inst
.instruction
|= INDEX_UP
;
8205 if (inst
.operands
[i
].shifted
)
8207 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8208 inst
.instruction
|= SHIFT_ROR
<< 5;
8211 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8212 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8216 else /* immediate offset in inst.relocs[0] */
8218 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8220 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8222 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8223 cannot use PC in addressing.
8224 PC cannot be used in writeback addressing, either. */
8225 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8228 /* Use of PC in str is deprecated for ARMv7. */
8229 if (warn_on_deprecated
8231 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8232 as_tsktsk (_("use of PC in this instruction is deprecated"));
8235 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8237 /* Prefer + for zero encoded value. */
8238 if (!inst
.operands
[i
].negative
)
8239 inst
.instruction
|= INDEX_UP
;
8240 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8245 /* inst.operands[i] was set up by parse_address. Encode it into an
8246 ARM-format mode 3 load or store instruction. Reject forms that
8247 cannot be used with such instructions. If is_t is true, reject
8248 forms that cannot be used with a T instruction (i.e. not
8251 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8253 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8255 inst
.error
= _("instruction does not accept scaled register index");
8259 encode_arm_addr_mode_common (i
, is_t
);
8261 if (inst
.operands
[i
].immisreg
)
8263 constraint ((inst
.operands
[i
].imm
== REG_PC
8264 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8266 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8268 inst
.instruction
|= inst
.operands
[i
].imm
;
8269 if (!inst
.operands
[i
].negative
)
8270 inst
.instruction
|= INDEX_UP
;
8272 else /* immediate offset in inst.relocs[0] */
8274 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8275 && inst
.operands
[i
].writeback
),
8277 inst
.instruction
|= HWOFFSET_IMM
;
8278 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8280 /* Prefer + for zero encoded value. */
8281 if (!inst
.operands
[i
].negative
)
8282 inst
.instruction
|= INDEX_UP
;
8284 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8289 /* Write immediate bits [7:0] to the following locations:
8291 |28/24|23 19|18 16|15 4|3 0|
8292 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8294 This function is used by VMOV/VMVN/VORR/VBIC. */
8297 neon_write_immbits (unsigned immbits
)
8299 inst
.instruction
|= immbits
& 0xf;
8300 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8301 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8304 /* Invert low-order SIZE bits of XHI:XLO. */
8307 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8309 unsigned immlo
= xlo
? *xlo
: 0;
8310 unsigned immhi
= xhi
? *xhi
: 0;
8315 immlo
= (~immlo
) & 0xff;
8319 immlo
= (~immlo
) & 0xffff;
8323 immhi
= (~immhi
) & 0xffffffff;
8327 immlo
= (~immlo
) & 0xffffffff;
8341 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8345 neon_bits_same_in_bytes (unsigned imm
)
8347 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8348 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8349 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8350 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8353 /* For immediate of above form, return 0bABCD. */
8356 neon_squash_bits (unsigned imm
)
8358 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8359 | ((imm
& 0x01000000) >> 21);
8362 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8365 neon_qfloat_bits (unsigned imm
)
8367 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8370 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8371 the instruction. *OP is passed as the initial value of the op field, and
8372 may be set to a different value depending on the constant (i.e.
8373 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8374 MVN). If the immediate looks like a repeated pattern then also
8375 try smaller element sizes. */
8378 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8379 unsigned *immbits
, int *op
, int size
,
8380 enum neon_el_type type
)
8382 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8384 if (type
== NT_float
&& !float_p
)
8387 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8389 if (size
!= 32 || *op
== 1)
8391 *immbits
= neon_qfloat_bits (immlo
);
8397 if (neon_bits_same_in_bytes (immhi
)
8398 && neon_bits_same_in_bytes (immlo
))
8402 *immbits
= (neon_squash_bits (immhi
) << 4)
8403 | neon_squash_bits (immlo
);
8414 if (immlo
== (immlo
& 0x000000ff))
8419 else if (immlo
== (immlo
& 0x0000ff00))
8421 *immbits
= immlo
>> 8;
8424 else if (immlo
== (immlo
& 0x00ff0000))
8426 *immbits
= immlo
>> 16;
8429 else if (immlo
== (immlo
& 0xff000000))
8431 *immbits
= immlo
>> 24;
8434 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8436 *immbits
= (immlo
>> 8) & 0xff;
8439 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8441 *immbits
= (immlo
>> 16) & 0xff;
8445 if ((immlo
& 0xffff) != (immlo
>> 16))
8452 if (immlo
== (immlo
& 0x000000ff))
8457 else if (immlo
== (immlo
& 0x0000ff00))
8459 *immbits
= immlo
>> 8;
8463 if ((immlo
& 0xff) != (immlo
>> 8))
8468 if (immlo
== (immlo
& 0x000000ff))
8470 /* Don't allow MVN with 8-bit immediate. */
8480 #if defined BFD_HOST_64_BIT
8481 /* Returns TRUE if double precision value V may be cast
8482 to single precision without loss of accuracy. */
8485 is_double_a_single (bfd_int64_t v
)
8487 int exp
= (int)((v
>> 52) & 0x7FF);
8488 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8490 return (exp
== 0 || exp
== 0x7FF
8491 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8492 && (mantissa
& 0x1FFFFFFFl
) == 0;
8495 /* Returns a double precision value casted to single precision
8496 (ignoring the least significant bits in exponent and mantissa). */
8499 double_to_single (bfd_int64_t v
)
8501 int sign
= (int) ((v
>> 63) & 1l);
8502 int exp
= (int) ((v
>> 52) & 0x7FF);
8503 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8509 exp
= exp
- 1023 + 127;
8518 /* No denormalized numbers. */
8524 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8526 #endif /* BFD_HOST_64_BIT */
8535 static void do_vfp_nsyn_opcode (const char *);
8537 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8538 Determine whether it can be performed with a move instruction; if
8539 it can, convert inst.instruction to that move instruction and
8540 return TRUE; if it can't, convert inst.instruction to a literal-pool
8541 load and return FALSE. If this is not a valid thing to do in the
8542 current context, set inst.error and return TRUE.
8544 inst.operands[i] describes the destination register. */
8547 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8550 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8551 bfd_boolean arm_p
= (t
== CONST_ARM
);
8554 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8558 if ((inst
.instruction
& tbit
) == 0)
8560 inst
.error
= _("invalid pseudo operation");
8564 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8565 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8566 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8568 inst
.error
= _("constant expression expected");
8572 if (inst
.relocs
[0].exp
.X_op
== O_constant
8573 || inst
.relocs
[0].exp
.X_op
== O_big
)
8575 #if defined BFD_HOST_64_BIT
8580 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8582 LITTLENUM_TYPE w
[X_PRECISION
];
8585 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8587 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8589 /* FIXME: Should we check words w[2..5] ? */
8594 #if defined BFD_HOST_64_BIT
8596 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8597 << LITTLENUM_NUMBER_OF_BITS
)
8598 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8599 << LITTLENUM_NUMBER_OF_BITS
)
8600 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8601 << LITTLENUM_NUMBER_OF_BITS
)
8602 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8604 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8605 | (l
[0] & LITTLENUM_MASK
);
8609 v
= inst
.relocs
[0].exp
.X_add_number
;
8611 if (!inst
.operands
[i
].issingle
)
8615 /* LDR should not use lead in a flag-setting instruction being
8616 chosen so we do not check whether movs can be used. */
8618 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8619 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8620 && inst
.operands
[i
].reg
!= 13
8621 && inst
.operands
[i
].reg
!= 15)
8623 /* Check if on thumb2 it can be done with a mov.w, mvn or
8624 movw instruction. */
8625 unsigned int newimm
;
8626 bfd_boolean isNegated
;
8628 newimm
= encode_thumb32_immediate (v
);
8629 if (newimm
!= (unsigned int) FAIL
)
8633 newimm
= encode_thumb32_immediate (~v
);
8634 if (newimm
!= (unsigned int) FAIL
)
8638 /* The number can be loaded with a mov.w or mvn
8640 if (newimm
!= (unsigned int) FAIL
8641 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8643 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8644 | (inst
.operands
[i
].reg
<< 8));
8645 /* Change to MOVN. */
8646 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8647 inst
.instruction
|= (newimm
& 0x800) << 15;
8648 inst
.instruction
|= (newimm
& 0x700) << 4;
8649 inst
.instruction
|= (newimm
& 0x0ff);
8652 /* The number can be loaded with a movw instruction. */
8653 else if ((v
& ~0xFFFF) == 0
8654 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8656 int imm
= v
& 0xFFFF;
8658 inst
.instruction
= 0xf2400000; /* MOVW. */
8659 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8660 inst
.instruction
|= (imm
& 0xf000) << 4;
8661 inst
.instruction
|= (imm
& 0x0800) << 15;
8662 inst
.instruction
|= (imm
& 0x0700) << 4;
8663 inst
.instruction
|= (imm
& 0x00ff);
8670 int value
= encode_arm_immediate (v
);
8674 /* This can be done with a mov instruction. */
8675 inst
.instruction
&= LITERAL_MASK
;
8676 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8677 inst
.instruction
|= value
& 0xfff;
8681 value
= encode_arm_immediate (~ v
);
8684 /* This can be done with a mvn instruction. */
8685 inst
.instruction
&= LITERAL_MASK
;
8686 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8687 inst
.instruction
|= value
& 0xfff;
8691 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8694 unsigned immbits
= 0;
8695 unsigned immlo
= inst
.operands
[1].imm
;
8696 unsigned immhi
= inst
.operands
[1].regisimm
8697 ? inst
.operands
[1].reg
8698 : inst
.relocs
[0].exp
.X_unsigned
8700 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8701 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8702 &op
, 64, NT_invtype
);
8706 neon_invert_size (&immlo
, &immhi
, 64);
8708 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8709 &op
, 64, NT_invtype
);
8714 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8720 /* Fill other bits in vmov encoding for both thumb and arm. */
8722 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8724 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8725 neon_write_immbits (immbits
);
8733 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8734 if (inst
.operands
[i
].issingle
8735 && is_quarter_float (inst
.operands
[1].imm
)
8736 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8738 inst
.operands
[1].imm
=
8739 neon_qfloat_bits (v
);
8740 do_vfp_nsyn_opcode ("fconsts");
8744 /* If our host does not support a 64-bit type then we cannot perform
8745 the following optimization. This mean that there will be a
8746 discrepancy between the output produced by an assembler built for
8747 a 32-bit-only host and the output produced from a 64-bit host, but
8748 this cannot be helped. */
8749 #if defined BFD_HOST_64_BIT
8750 else if (!inst
.operands
[1].issingle
8751 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8753 if (is_double_a_single (v
)
8754 && is_quarter_float (double_to_single (v
)))
8756 inst
.operands
[1].imm
=
8757 neon_qfloat_bits (double_to_single (v
));
8758 do_vfp_nsyn_opcode ("fconstd");
8766 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8767 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8770 inst
.operands
[1].reg
= REG_PC
;
8771 inst
.operands
[1].isreg
= 1;
8772 inst
.operands
[1].preind
= 1;
8773 inst
.relocs
[0].pc_rel
= 1;
8774 inst
.relocs
[0].type
= (thumb_p
8775 ? BFD_RELOC_ARM_THUMB_OFFSET
8777 ? BFD_RELOC_ARM_HWLITERAL
8778 : BFD_RELOC_ARM_LITERAL
));
8782 /* inst.operands[i] was set up by parse_address. Encode it into an
8783 ARM-format instruction. Reject all forms which cannot be encoded
8784 into a coprocessor load/store instruction. If wb_ok is false,
8785 reject use of writeback; if unind_ok is false, reject use of
8786 unindexed addressing. If reloc_override is not 0, use it instead
8787 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8788 (in which case it is preserved). */
8791 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8793 if (!inst
.operands
[i
].isreg
)
8796 if (! inst
.operands
[0].isvec
)
8798 inst
.error
= _("invalid co-processor operand");
8801 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8805 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8807 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8809 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8811 gas_assert (!inst
.operands
[i
].writeback
);
8814 inst
.error
= _("instruction does not support unindexed addressing");
8817 inst
.instruction
|= inst
.operands
[i
].imm
;
8818 inst
.instruction
|= INDEX_UP
;
8822 if (inst
.operands
[i
].preind
)
8823 inst
.instruction
|= PRE_INDEX
;
8825 if (inst
.operands
[i
].writeback
)
8827 if (inst
.operands
[i
].reg
== REG_PC
)
8829 inst
.error
= _("pc may not be used with write-back");
8834 inst
.error
= _("instruction does not support writeback");
8837 inst
.instruction
|= WRITE_BACK
;
8841 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
8842 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8843 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
8844 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8847 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8849 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8852 /* Prefer + for zero encoded value. */
8853 if (!inst
.operands
[i
].negative
)
8854 inst
.instruction
|= INDEX_UP
;
8859 /* Functions for instruction encoding, sorted by sub-architecture.
8860 First some generics; their names are taken from the conventional
8861 bit positions for register arguments in ARM format instructions. */
8871 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8877 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8883 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8884 inst
.instruction
|= inst
.operands
[1].reg
;
8890 inst
.instruction
|= inst
.operands
[0].reg
;
8891 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8897 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8898 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8904 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8905 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8911 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8912 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8916 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8918 if (ARM_CPU_IS_ANY (cpu_variant
))
8920 as_tsktsk ("%s", msg
);
8923 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8935 unsigned Rn
= inst
.operands
[2].reg
;
8936 /* Enforce restrictions on SWP instruction. */
8937 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8939 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8940 _("Rn must not overlap other operands"));
8942 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8944 if (!check_obsolete (&arm_ext_v8
,
8945 _("swp{b} use is obsoleted for ARMv8 and later"))
8946 && warn_on_deprecated
8947 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8948 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8951 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8952 inst
.instruction
|= inst
.operands
[1].reg
;
8953 inst
.instruction
|= Rn
<< 16;
8959 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8960 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8961 inst
.instruction
|= inst
.operands
[2].reg
;
8967 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8968 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
8969 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
8970 || inst
.relocs
[0].exp
.X_add_number
!= 0),
8972 inst
.instruction
|= inst
.operands
[0].reg
;
8973 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8974 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8980 inst
.instruction
|= inst
.operands
[0].imm
;
8986 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8987 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8990 /* ARM instructions, in alphabetical order by function name (except
8991 that wrapper functions appear immediately after the function they
8994 /* This is a pseudo-op of the form "adr rd, label" to be converted
8995 into a relative address of the form "add rd, pc, #label-.-8". */
9000 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9002 /* Frag hacking will turn this into a sub instruction if the offset turns
9003 out to be negative. */
9004 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9005 inst
.relocs
[0].pc_rel
= 1;
9006 inst
.relocs
[0].exp
.X_add_number
-= 8;
9008 if (support_interwork
9009 && inst
.relocs
[0].exp
.X_op
== O_symbol
9010 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9011 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9012 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9013 inst
.relocs
[0].exp
.X_add_number
|= 1;
9016 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9017 into a relative address of the form:
9018 add rd, pc, #low(label-.-8)"
9019 add rd, rd, #high(label-.-8)" */
9024 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9026 /* Frag hacking will turn this into a sub instruction if the offset turns
9027 out to be negative. */
9028 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9029 inst
.relocs
[0].pc_rel
= 1;
9030 inst
.size
= INSN_SIZE
* 2;
9031 inst
.relocs
[0].exp
.X_add_number
-= 8;
9033 if (support_interwork
9034 && inst
.relocs
[0].exp
.X_op
== O_symbol
9035 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9036 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9037 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9038 inst
.relocs
[0].exp
.X_add_number
|= 1;
9044 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9045 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9047 if (!inst
.operands
[1].present
)
9048 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9049 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9050 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9051 encode_arm_shifter_operand (2);
9057 if (inst
.operands
[0].present
)
9058 inst
.instruction
|= inst
.operands
[0].imm
;
9060 inst
.instruction
|= 0xf;
9066 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9067 constraint (msb
> 32, _("bit-field extends past end of register"));
9068 /* The instruction encoding stores the LSB and MSB,
9069 not the LSB and width. */
9070 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9071 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9072 inst
.instruction
|= (msb
- 1) << 16;
9080 /* #0 in second position is alternative syntax for bfc, which is
9081 the same instruction but with REG_PC in the Rm field. */
9082 if (!inst
.operands
[1].isreg
)
9083 inst
.operands
[1].reg
= REG_PC
;
9085 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9086 constraint (msb
> 32, _("bit-field extends past end of register"));
9087 /* The instruction encoding stores the LSB and MSB,
9088 not the LSB and width. */
9089 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9090 inst
.instruction
|= inst
.operands
[1].reg
;
9091 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9092 inst
.instruction
|= (msb
- 1) << 16;
9098 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9099 _("bit-field extends past end of register"));
9100 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9101 inst
.instruction
|= inst
.operands
[1].reg
;
9102 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9103 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9106 /* ARM V5 breakpoint instruction (argument parse)
9107 BKPT <16 bit unsigned immediate>
9108 Instruction is not conditional.
9109 The bit pattern given in insns[] has the COND_ALWAYS condition,
9110 and it is an error if the caller tried to override that. */
9115 /* Top 12 of 16 bits to bits 19:8. */
9116 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9118 /* Bottom 4 of 16 bits to bits 3:0. */
9119 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9123 encode_branch (int default_reloc
)
9125 if (inst
.operands
[0].hasreloc
)
9127 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9128 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9129 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9130 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9131 ? BFD_RELOC_ARM_PLT32
9132 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9135 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9136 inst
.relocs
[0].pc_rel
= 1;
9143 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9144 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9147 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9154 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9156 if (inst
.cond
== COND_ALWAYS
)
9157 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9159 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9163 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9166 /* ARM V5 branch-link-exchange instruction (argument parse)
9167 BLX <target_addr> ie BLX(1)
9168 BLX{<condition>} <Rm> ie BLX(2)
9169 Unfortunately, there are two different opcodes for this mnemonic.
9170 So, the insns[].value is not used, and the code here zaps values
9171 into inst.instruction.
9172 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9177 if (inst
.operands
[0].isreg
)
9179 /* Arg is a register; the opcode provided by insns[] is correct.
9180 It is not illegal to do "blx pc", just useless. */
9181 if (inst
.operands
[0].reg
== REG_PC
)
9182 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9184 inst
.instruction
|= inst
.operands
[0].reg
;
9188 /* Arg is an address; this instruction cannot be executed
9189 conditionally, and the opcode must be adjusted.
9190 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9191 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9192 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9193 inst
.instruction
= 0xfa000000;
9194 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9201 bfd_boolean want_reloc
;
9203 if (inst
.operands
[0].reg
== REG_PC
)
9204 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9206 inst
.instruction
|= inst
.operands
[0].reg
;
9207 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9208 it is for ARMv4t or earlier. */
9209 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9210 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9211 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9215 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9220 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9224 /* ARM v5TEJ. Jump to Jazelle code. */
9229 if (inst
.operands
[0].reg
== REG_PC
)
9230 as_tsktsk (_("use of r15 in bxj is not really useful"));
9232 inst
.instruction
|= inst
.operands
[0].reg
;
9235 /* Co-processor data operation:
9236 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9237 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9241 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9242 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9243 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9244 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9245 inst
.instruction
|= inst
.operands
[4].reg
;
9246 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9252 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9253 encode_arm_shifter_operand (1);
9256 /* Transfer between coprocessor and ARM registers.
9257 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9262 No special properties. */
9264 struct deprecated_coproc_regs_s
9271 arm_feature_set deprecated
;
9272 arm_feature_set obsoleted
;
9273 const char *dep_msg
;
9274 const char *obs_msg
;
9277 #define DEPR_ACCESS_V8 \
9278 N_("This coprocessor register access is deprecated in ARMv8")
9280 /* Table of all deprecated coprocessor registers. */
9281 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9283 {15, 0, 7, 10, 5, /* CP15DMB. */
9284 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9285 DEPR_ACCESS_V8
, NULL
},
9286 {15, 0, 7, 10, 4, /* CP15DSB. */
9287 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9288 DEPR_ACCESS_V8
, NULL
},
9289 {15, 0, 7, 5, 4, /* CP15ISB. */
9290 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9291 DEPR_ACCESS_V8
, NULL
},
9292 {14, 6, 1, 0, 0, /* TEEHBR. */
9293 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9294 DEPR_ACCESS_V8
, NULL
},
9295 {14, 6, 0, 0, 0, /* TEECR. */
9296 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9297 DEPR_ACCESS_V8
, NULL
},
9300 #undef DEPR_ACCESS_V8
9302 static const size_t deprecated_coproc_reg_count
=
9303 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9311 Rd
= inst
.operands
[2].reg
;
9314 if (inst
.instruction
== 0xee000010
9315 || inst
.instruction
== 0xfe000010)
9317 reject_bad_reg (Rd
);
9318 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9320 constraint (Rd
== REG_SP
, BAD_SP
);
9325 if (inst
.instruction
== 0xe000010)
9326 constraint (Rd
== REG_PC
, BAD_PC
);
9329 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9331 const struct deprecated_coproc_regs_s
*r
=
9332 deprecated_coproc_regs
+ i
;
9334 if (inst
.operands
[0].reg
== r
->cp
9335 && inst
.operands
[1].imm
== r
->opc1
9336 && inst
.operands
[3].reg
== r
->crn
9337 && inst
.operands
[4].reg
== r
->crm
9338 && inst
.operands
[5].imm
== r
->opc2
)
9340 if (! ARM_CPU_IS_ANY (cpu_variant
)
9341 && warn_on_deprecated
9342 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9343 as_tsktsk ("%s", r
->dep_msg
);
9347 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9348 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9349 inst
.instruction
|= Rd
<< 12;
9350 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9351 inst
.instruction
|= inst
.operands
[4].reg
;
9352 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9355 /* Transfer between coprocessor register and pair of ARM registers.
9356 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9361 Two XScale instructions are special cases of these:
9363 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9364 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9366 Result unpredictable if Rd or Rn is R15. */
9373 Rd
= inst
.operands
[2].reg
;
9374 Rn
= inst
.operands
[3].reg
;
9378 reject_bad_reg (Rd
);
9379 reject_bad_reg (Rn
);
9383 constraint (Rd
== REG_PC
, BAD_PC
);
9384 constraint (Rn
== REG_PC
, BAD_PC
);
9387 /* Only check the MRRC{2} variants. */
9388 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9390 /* If Rd == Rn, error that the operation is
9391 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9392 constraint (Rd
== Rn
, BAD_OVERLAP
);
9395 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9396 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9397 inst
.instruction
|= Rd
<< 12;
9398 inst
.instruction
|= Rn
<< 16;
9399 inst
.instruction
|= inst
.operands
[4].reg
;
9405 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9406 if (inst
.operands
[1].present
)
9408 inst
.instruction
|= CPSI_MMOD
;
9409 inst
.instruction
|= inst
.operands
[1].imm
;
9416 inst
.instruction
|= inst
.operands
[0].imm
;
9422 unsigned Rd
, Rn
, Rm
;
9424 Rd
= inst
.operands
[0].reg
;
9425 Rn
= (inst
.operands
[1].present
9426 ? inst
.operands
[1].reg
: Rd
);
9427 Rm
= inst
.operands
[2].reg
;
9429 constraint ((Rd
== REG_PC
), BAD_PC
);
9430 constraint ((Rn
== REG_PC
), BAD_PC
);
9431 constraint ((Rm
== REG_PC
), BAD_PC
);
9433 inst
.instruction
|= Rd
<< 16;
9434 inst
.instruction
|= Rn
<< 0;
9435 inst
.instruction
|= Rm
<< 8;
9441 /* There is no IT instruction in ARM mode. We
9442 process it to do the validation as if in
9443 thumb mode, just in case the code gets
9444 assembled for thumb using the unified syntax. */
9449 set_pred_insn_type (IT_INSN
);
9450 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9451 now_pred
.cc
= inst
.operands
[0].imm
;
9455 /* If there is only one register in the register list,
9456 then return its register number. Otherwise return -1. */
9458 only_one_reg_in_list (int range
)
9460 int i
= ffs (range
) - 1;
9461 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9465 encode_ldmstm(int from_push_pop_mnem
)
9467 int base_reg
= inst
.operands
[0].reg
;
9468 int range
= inst
.operands
[1].imm
;
9471 inst
.instruction
|= base_reg
<< 16;
9472 inst
.instruction
|= range
;
9474 if (inst
.operands
[1].writeback
)
9475 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9477 if (inst
.operands
[0].writeback
)
9479 inst
.instruction
|= WRITE_BACK
;
9480 /* Check for unpredictable uses of writeback. */
9481 if (inst
.instruction
& LOAD_BIT
)
9483 /* Not allowed in LDM type 2. */
9484 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9485 && ((range
& (1 << REG_PC
)) == 0))
9486 as_warn (_("writeback of base register is UNPREDICTABLE"));
9487 /* Only allowed if base reg not in list for other types. */
9488 else if (range
& (1 << base_reg
))
9489 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9493 /* Not allowed for type 2. */
9494 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9495 as_warn (_("writeback of base register is UNPREDICTABLE"));
9496 /* Only allowed if base reg not in list, or first in list. */
9497 else if ((range
& (1 << base_reg
))
9498 && (range
& ((1 << base_reg
) - 1)))
9499 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9503 /* If PUSH/POP has only one register, then use the A2 encoding. */
9504 one_reg
= only_one_reg_in_list (range
);
9505 if (from_push_pop_mnem
&& one_reg
>= 0)
9507 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9509 if (is_push
&& one_reg
== 13 /* SP */)
9510 /* PR 22483: The A2 encoding cannot be used when
9511 pushing the stack pointer as this is UNPREDICTABLE. */
9514 inst
.instruction
&= A_COND_MASK
;
9515 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9516 inst
.instruction
|= one_reg
<< 12;
9523 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9526 /* ARMv5TE load-consecutive (argument parse)
9535 constraint (inst
.operands
[0].reg
% 2 != 0,
9536 _("first transfer register must be even"));
9537 constraint (inst
.operands
[1].present
9538 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9539 _("can only transfer two consecutive registers"));
9540 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9541 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9543 if (!inst
.operands
[1].present
)
9544 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9546 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9547 register and the first register written; we have to diagnose
9548 overlap between the base and the second register written here. */
9550 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9551 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9552 as_warn (_("base register written back, and overlaps "
9553 "second transfer register"));
9555 if (!(inst
.instruction
& V4_STR_BIT
))
9557 /* For an index-register load, the index register must not overlap the
9558 destination (even if not write-back). */
9559 if (inst
.operands
[2].immisreg
9560 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9561 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9562 as_warn (_("index register overlaps transfer register"));
9564 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9565 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9571 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9572 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9573 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9574 || inst
.operands
[1].negative
9575 /* This can arise if the programmer has written
9577 or if they have mistakenly used a register name as the last
9580 It is very difficult to distinguish between these two cases
9581 because "rX" might actually be a label. ie the register
9582 name has been occluded by a symbol of the same name. So we
9583 just generate a general 'bad addressing mode' type error
9584 message and leave it up to the programmer to discover the
9585 true cause and fix their mistake. */
9586 || (inst
.operands
[1].reg
== REG_PC
),
9589 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9590 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9591 _("offset must be zero in ARM encoding"));
9593 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9595 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9596 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9597 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9603 constraint (inst
.operands
[0].reg
% 2 != 0,
9604 _("even register required"));
9605 constraint (inst
.operands
[1].present
9606 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9607 _("can only load two consecutive registers"));
9608 /* If op 1 were present and equal to PC, this function wouldn't
9609 have been called in the first place. */
9610 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9612 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9613 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9616 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9617 which is not a multiple of four is UNPREDICTABLE. */
9619 check_ldr_r15_aligned (void)
9621 constraint (!(inst
.operands
[1].immisreg
)
9622 && (inst
.operands
[0].reg
== REG_PC
9623 && inst
.operands
[1].reg
== REG_PC
9624 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9625 _("ldr to register 15 must be 4-byte aligned"));
9631 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9632 if (!inst
.operands
[1].isreg
)
9633 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9635 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9636 check_ldr_r15_aligned ();
9642 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9644 if (inst
.operands
[1].preind
)
9646 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9647 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9648 _("this instruction requires a post-indexed address"));
9650 inst
.operands
[1].preind
= 0;
9651 inst
.operands
[1].postind
= 1;
9652 inst
.operands
[1].writeback
= 1;
9654 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9655 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9658 /* Halfword and signed-byte load/store operations. */
9663 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9664 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9665 if (!inst
.operands
[1].isreg
)
9666 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9668 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9674 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9676 if (inst
.operands
[1].preind
)
9678 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9679 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9680 _("this instruction requires a post-indexed address"));
9682 inst
.operands
[1].preind
= 0;
9683 inst
.operands
[1].postind
= 1;
9684 inst
.operands
[1].writeback
= 1;
9686 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9687 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9690 /* Co-processor register load/store.
9691 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9695 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9696 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9697 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9703 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9704 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9705 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9706 && !(inst
.instruction
& 0x00400000))
9707 as_tsktsk (_("Rd and Rm should be different in mla"));
9709 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9710 inst
.instruction
|= inst
.operands
[1].reg
;
9711 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9712 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9718 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9719 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9721 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9722 encode_arm_shifter_operand (1);
9725 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9732 top
= (inst
.instruction
& 0x00400000) != 0;
9733 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9734 _(":lower16: not allowed in this instruction"));
9735 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9736 _(":upper16: not allowed in this instruction"));
9737 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9738 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9740 imm
= inst
.relocs
[0].exp
.X_add_number
;
9741 /* The value is in two pieces: 0:11, 16:19. */
9742 inst
.instruction
|= (imm
& 0x00000fff);
9743 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9748 do_vfp_nsyn_mrs (void)
9750 if (inst
.operands
[0].isvec
)
9752 if (inst
.operands
[1].reg
!= 1)
9753 first_error (_("operand 1 must be FPSCR"));
9754 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9755 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9756 do_vfp_nsyn_opcode ("fmstat");
9758 else if (inst
.operands
[1].isvec
)
9759 do_vfp_nsyn_opcode ("fmrx");
9767 do_vfp_nsyn_msr (void)
9769 if (inst
.operands
[0].isvec
)
9770 do_vfp_nsyn_opcode ("fmxr");
9780 unsigned Rt
= inst
.operands
[0].reg
;
9782 if (thumb_mode
&& Rt
== REG_SP
)
9784 inst
.error
= BAD_SP
;
9788 /* MVFR2 is only valid at ARMv8-A. */
9789 if (inst
.operands
[1].reg
== 5)
9790 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9793 /* APSR_ sets isvec. All other refs to PC are illegal. */
9794 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9796 inst
.error
= BAD_PC
;
9800 /* If we get through parsing the register name, we just insert the number
9801 generated into the instruction without further validation. */
9802 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9803 inst
.instruction
|= (Rt
<< 12);
9809 unsigned Rt
= inst
.operands
[1].reg
;
9812 reject_bad_reg (Rt
);
9813 else if (Rt
== REG_PC
)
9815 inst
.error
= BAD_PC
;
9819 /* MVFR2 is only valid for ARMv8-A. */
9820 if (inst
.operands
[0].reg
== 5)
9821 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9824 /* If we get through parsing the register name, we just insert the number
9825 generated into the instruction without further validation. */
9826 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9827 inst
.instruction
|= (Rt
<< 12);
9835 if (do_vfp_nsyn_mrs () == SUCCESS
)
9838 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9839 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9841 if (inst
.operands
[1].isreg
)
9843 br
= inst
.operands
[1].reg
;
9844 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9845 as_bad (_("bad register for mrs"));
9849 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9850 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9852 _("'APSR', 'CPSR' or 'SPSR' expected"));
9853 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9856 inst
.instruction
|= br
;
9859 /* Two possible forms:
9860 "{C|S}PSR_<field>, Rm",
9861 "{C|S}PSR_f, #expression". */
9866 if (do_vfp_nsyn_msr () == SUCCESS
)
9869 inst
.instruction
|= inst
.operands
[0].imm
;
9870 if (inst
.operands
[1].isreg
)
9871 inst
.instruction
|= inst
.operands
[1].reg
;
9874 inst
.instruction
|= INST_IMMEDIATE
;
9875 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9876 inst
.relocs
[0].pc_rel
= 0;
9883 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9885 if (!inst
.operands
[2].present
)
9886 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9887 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9888 inst
.instruction
|= inst
.operands
[1].reg
;
9889 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9891 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9892 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9893 as_tsktsk (_("Rd and Rm should be different in mul"));
9896 /* Long Multiply Parser
9897 UMULL RdLo, RdHi, Rm, Rs
9898 SMULL RdLo, RdHi, Rm, Rs
9899 UMLAL RdLo, RdHi, Rm, Rs
9900 SMLAL RdLo, RdHi, Rm, Rs. */
9905 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9906 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9907 inst
.instruction
|= inst
.operands
[2].reg
;
9908 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9910 /* rdhi and rdlo must be different. */
9911 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9912 as_tsktsk (_("rdhi and rdlo must be different"));
9914 /* rdhi, rdlo and rm must all be different before armv6. */
9915 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9916 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9917 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9918 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9924 if (inst
.operands
[0].present
9925 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9927 /* Architectural NOP hints are CPSR sets with no bits selected. */
9928 inst
.instruction
&= 0xf0000000;
9929 inst
.instruction
|= 0x0320f000;
9930 if (inst
.operands
[0].present
)
9931 inst
.instruction
|= inst
.operands
[0].imm
;
9935 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9936 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9937 Condition defaults to COND_ALWAYS.
9938 Error if Rd, Rn or Rm are R15. */
9943 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9944 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9945 inst
.instruction
|= inst
.operands
[2].reg
;
9946 if (inst
.operands
[3].present
)
9947 encode_arm_shift (3);
9950 /* ARM V6 PKHTB (Argument Parse). */
9955 if (!inst
.operands
[3].present
)
9957 /* If the shift specifier is omitted, turn the instruction
9958 into pkhbt rd, rm, rn. */
9959 inst
.instruction
&= 0xfff00010;
9960 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9961 inst
.instruction
|= inst
.operands
[1].reg
;
9962 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9966 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9967 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9968 inst
.instruction
|= inst
.operands
[2].reg
;
9969 encode_arm_shift (3);
9973 /* ARMv5TE: Preload-Cache
9974 MP Extensions: Preload for write
9978 Syntactically, like LDR with B=1, W=0, L=1. */
9983 constraint (!inst
.operands
[0].isreg
,
9984 _("'[' expected after PLD mnemonic"));
9985 constraint (inst
.operands
[0].postind
,
9986 _("post-indexed expression used in preload instruction"));
9987 constraint (inst
.operands
[0].writeback
,
9988 _("writeback used in preload instruction"));
9989 constraint (!inst
.operands
[0].preind
,
9990 _("unindexed addressing used in preload instruction"));
9991 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9994 /* ARMv7: PLI <addr_mode> */
9998 constraint (!inst
.operands
[0].isreg
,
9999 _("'[' expected after PLI mnemonic"));
10000 constraint (inst
.operands
[0].postind
,
10001 _("post-indexed expression used in preload instruction"));
10002 constraint (inst
.operands
[0].writeback
,
10003 _("writeback used in preload instruction"));
10004 constraint (!inst
.operands
[0].preind
,
10005 _("unindexed addressing used in preload instruction"));
10006 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10007 inst
.instruction
&= ~PRE_INDEX
;
10013 constraint (inst
.operands
[0].writeback
,
10014 _("push/pop do not support {reglist}^"));
10015 inst
.operands
[1] = inst
.operands
[0];
10016 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10017 inst
.operands
[0].isreg
= 1;
10018 inst
.operands
[0].writeback
= 1;
10019 inst
.operands
[0].reg
= REG_SP
;
10020 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10023 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10024 word at the specified address and the following word
10026 Unconditionally executed.
10027 Error if Rn is R15. */
10032 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10033 if (inst
.operands
[0].writeback
)
10034 inst
.instruction
|= WRITE_BACK
;
10037 /* ARM V6 ssat (argument parse). */
10042 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10043 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10044 inst
.instruction
|= inst
.operands
[2].reg
;
10046 if (inst
.operands
[3].present
)
10047 encode_arm_shift (3);
10050 /* ARM V6 usat (argument parse). */
10055 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10056 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10057 inst
.instruction
|= inst
.operands
[2].reg
;
10059 if (inst
.operands
[3].present
)
10060 encode_arm_shift (3);
10063 /* ARM V6 ssat16 (argument parse). */
10068 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10069 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10070 inst
.instruction
|= inst
.operands
[2].reg
;
10076 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10077 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10078 inst
.instruction
|= inst
.operands
[2].reg
;
10081 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10082 preserving the other bits.
10084 setend <endian_specifier>, where <endian_specifier> is either
10090 if (warn_on_deprecated
10091 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10092 as_tsktsk (_("setend use is deprecated for ARMv8"));
10094 if (inst
.operands
[0].imm
)
10095 inst
.instruction
|= 0x200;
10101 unsigned int Rm
= (inst
.operands
[1].present
10102 ? inst
.operands
[1].reg
10103 : inst
.operands
[0].reg
);
10105 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10106 inst
.instruction
|= Rm
;
10107 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10109 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10110 inst
.instruction
|= SHIFT_BY_REG
;
10111 /* PR 12854: Error on extraneous shifts. */
10112 constraint (inst
.operands
[2].shifted
,
10113 _("extraneous shift as part of operand to shift insn"));
10116 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10122 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10123 inst
.relocs
[0].pc_rel
= 0;
10129 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10130 inst
.relocs
[0].pc_rel
= 0;
10136 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10137 inst
.relocs
[0].pc_rel
= 0;
10143 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10144 _("selected processor does not support SETPAN instruction"));
10146 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10152 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10153 _("selected processor does not support SETPAN instruction"));
10155 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10158 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10159 SMLAxy{cond} Rd,Rm,Rs,Rn
10160 SMLAWy{cond} Rd,Rm,Rs,Rn
10161 Error if any register is R15. */
10166 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10167 inst
.instruction
|= inst
.operands
[1].reg
;
10168 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10169 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10172 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10173 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10174 Error if any register is R15.
10175 Warning if Rdlo == Rdhi. */
10180 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10181 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10182 inst
.instruction
|= inst
.operands
[2].reg
;
10183 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10185 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10186 as_tsktsk (_("rdhi and rdlo must be different"));
10189 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10190 SMULxy{cond} Rd,Rm,Rs
10191 Error if any register is R15. */
10196 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10197 inst
.instruction
|= inst
.operands
[1].reg
;
10198 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10201 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10202 the same for both ARM and Thumb-2. */
10209 if (inst
.operands
[0].present
)
10211 reg
= inst
.operands
[0].reg
;
10212 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10217 inst
.instruction
|= reg
<< 16;
10218 inst
.instruction
|= inst
.operands
[1].imm
;
10219 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10220 inst
.instruction
|= WRITE_BACK
;
10223 /* ARM V6 strex (argument parse). */
10228 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10229 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10230 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10231 || inst
.operands
[2].negative
10232 /* See comment in do_ldrex(). */
10233 || (inst
.operands
[2].reg
== REG_PC
),
10236 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10237 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10239 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10240 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10241 _("offset must be zero in ARM encoding"));
10243 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10244 inst
.instruction
|= inst
.operands
[1].reg
;
10245 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10246 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10250 do_t_strexbh (void)
10252 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10253 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10254 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10255 || inst
.operands
[2].negative
,
10258 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10259 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10267 constraint (inst
.operands
[1].reg
% 2 != 0,
10268 _("even register required"));
10269 constraint (inst
.operands
[2].present
10270 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10271 _("can only store two consecutive registers"));
10272 /* If op 2 were present and equal to PC, this function wouldn't
10273 have been called in the first place. */
10274 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10276 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10277 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10278 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10281 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10282 inst
.instruction
|= inst
.operands
[1].reg
;
10283 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10290 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10291 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10299 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10300 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10305 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10306 extends it to 32-bits, and adds the result to a value in another
10307 register. You can specify a rotation by 0, 8, 16, or 24 bits
10308 before extracting the 16-bit value.
10309 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10310 Condition defaults to COND_ALWAYS.
10311 Error if any register uses R15. */
10316 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10317 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10318 inst
.instruction
|= inst
.operands
[2].reg
;
10319 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10324 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10325 Condition defaults to COND_ALWAYS.
10326 Error if any register uses R15. */
10331 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10332 inst
.instruction
|= inst
.operands
[1].reg
;
10333 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10336 /* VFP instructions. In a logical order: SP variant first, monad
10337 before dyad, arithmetic then move then load/store. */
10340 do_vfp_sp_monadic (void)
10342 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10343 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10346 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10347 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10351 do_vfp_sp_dyadic (void)
10353 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10354 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10355 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10359 do_vfp_sp_compare_z (void)
10361 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10365 do_vfp_dp_sp_cvt (void)
10367 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10368 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10372 do_vfp_sp_dp_cvt (void)
10374 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10375 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10379 do_vfp_reg_from_sp (void)
10381 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10382 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10385 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10386 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10390 do_vfp_reg2_from_sp2 (void)
10392 constraint (inst
.operands
[2].imm
!= 2,
10393 _("only two consecutive VFP SP registers allowed here"));
10394 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10395 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10396 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10400 do_vfp_sp_from_reg (void)
10402 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10403 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10406 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10407 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10411 do_vfp_sp2_from_reg2 (void)
10413 constraint (inst
.operands
[0].imm
!= 2,
10414 _("only two consecutive VFP SP registers allowed here"));
10415 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10416 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10417 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10421 do_vfp_sp_ldst (void)
10423 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10424 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10428 do_vfp_dp_ldst (void)
10430 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10431 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10436 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10438 if (inst
.operands
[0].writeback
)
10439 inst
.instruction
|= WRITE_BACK
;
10441 constraint (ldstm_type
!= VFP_LDSTMIA
,
10442 _("this addressing mode requires base-register writeback"));
10443 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10444 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10445 inst
.instruction
|= inst
.operands
[1].imm
;
10449 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10453 if (inst
.operands
[0].writeback
)
10454 inst
.instruction
|= WRITE_BACK
;
10456 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10457 _("this addressing mode requires base-register writeback"));
10459 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10460 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10462 count
= inst
.operands
[1].imm
<< 1;
10463 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10466 inst
.instruction
|= count
;
10470 do_vfp_sp_ldstmia (void)
10472 vfp_sp_ldstm (VFP_LDSTMIA
);
10476 do_vfp_sp_ldstmdb (void)
10478 vfp_sp_ldstm (VFP_LDSTMDB
);
10482 do_vfp_dp_ldstmia (void)
10484 vfp_dp_ldstm (VFP_LDSTMIA
);
10488 do_vfp_dp_ldstmdb (void)
10490 vfp_dp_ldstm (VFP_LDSTMDB
);
10494 do_vfp_xp_ldstmia (void)
10496 vfp_dp_ldstm (VFP_LDSTMIAX
);
10500 do_vfp_xp_ldstmdb (void)
10502 vfp_dp_ldstm (VFP_LDSTMDBX
);
10506 do_vfp_dp_rd_rm (void)
10508 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10509 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10512 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10513 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10517 do_vfp_dp_rn_rd (void)
10519 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10520 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10524 do_vfp_dp_rd_rn (void)
10526 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10527 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10531 do_vfp_dp_rd_rn_rm (void)
10533 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10534 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10537 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10538 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10539 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10543 do_vfp_dp_rd (void)
10545 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10549 do_vfp_dp_rm_rd_rn (void)
10551 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10552 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10555 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10556 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10557 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10560 /* VFPv3 instructions. */
10562 do_vfp_sp_const (void)
10564 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10565 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10566 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10570 do_vfp_dp_const (void)
10572 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10573 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10574 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10578 vfp_conv (int srcsize
)
10580 int immbits
= srcsize
- inst
.operands
[1].imm
;
10582 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10584 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10585 i.e. immbits must be in range 0 - 16. */
10586 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10589 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10591 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10592 i.e. immbits must be in range 0 - 31. */
10593 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10597 inst
.instruction
|= (immbits
& 1) << 5;
10598 inst
.instruction
|= (immbits
>> 1);
10602 do_vfp_sp_conv_16 (void)
10604 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10609 do_vfp_dp_conv_16 (void)
10611 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10616 do_vfp_sp_conv_32 (void)
10618 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10623 do_vfp_dp_conv_32 (void)
10625 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10629 /* FPA instructions. Also in a logical order. */
10634 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10635 inst
.instruction
|= inst
.operands
[1].reg
;
10639 do_fpa_ldmstm (void)
10641 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10642 switch (inst
.operands
[1].imm
)
10644 case 1: inst
.instruction
|= CP_T_X
; break;
10645 case 2: inst
.instruction
|= CP_T_Y
; break;
10646 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10651 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10653 /* The instruction specified "ea" or "fd", so we can only accept
10654 [Rn]{!}. The instruction does not really support stacking or
10655 unstacking, so we have to emulate these by setting appropriate
10656 bits and offsets. */
10657 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10658 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10659 _("this instruction does not support indexing"));
10661 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10662 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10664 if (!(inst
.instruction
& INDEX_UP
))
10665 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10667 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10669 inst
.operands
[2].preind
= 0;
10670 inst
.operands
[2].postind
= 1;
10674 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10677 /* iWMMXt instructions: strictly in alphabetical order. */
10680 do_iwmmxt_tandorc (void)
10682 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10686 do_iwmmxt_textrc (void)
10688 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10689 inst
.instruction
|= inst
.operands
[1].imm
;
10693 do_iwmmxt_textrm (void)
10695 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10696 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10697 inst
.instruction
|= inst
.operands
[2].imm
;
10701 do_iwmmxt_tinsr (void)
10703 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10704 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10705 inst
.instruction
|= inst
.operands
[2].imm
;
10709 do_iwmmxt_tmia (void)
10711 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10712 inst
.instruction
|= inst
.operands
[1].reg
;
10713 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10717 do_iwmmxt_waligni (void)
10719 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10720 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10721 inst
.instruction
|= inst
.operands
[2].reg
;
10722 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10726 do_iwmmxt_wmerge (void)
10728 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10729 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10730 inst
.instruction
|= inst
.operands
[2].reg
;
10731 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10735 do_iwmmxt_wmov (void)
10737 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10738 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10739 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10740 inst
.instruction
|= inst
.operands
[1].reg
;
10744 do_iwmmxt_wldstbh (void)
10747 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10749 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10751 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10752 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10756 do_iwmmxt_wldstw (void)
10758 /* RIWR_RIWC clears .isreg for a control register. */
10759 if (!inst
.operands
[0].isreg
)
10761 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10762 inst
.instruction
|= 0xf0000000;
10765 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10766 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10770 do_iwmmxt_wldstd (void)
10772 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10773 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10774 && inst
.operands
[1].immisreg
)
10776 inst
.instruction
&= ~0x1a000ff;
10777 inst
.instruction
|= (0xfU
<< 28);
10778 if (inst
.operands
[1].preind
)
10779 inst
.instruction
|= PRE_INDEX
;
10780 if (!inst
.operands
[1].negative
)
10781 inst
.instruction
|= INDEX_UP
;
10782 if (inst
.operands
[1].writeback
)
10783 inst
.instruction
|= WRITE_BACK
;
10784 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10785 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10786 inst
.instruction
|= inst
.operands
[1].imm
;
10789 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10793 do_iwmmxt_wshufh (void)
10795 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10796 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10797 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10798 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10802 do_iwmmxt_wzero (void)
10804 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10805 inst
.instruction
|= inst
.operands
[0].reg
;
10806 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10807 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10811 do_iwmmxt_wrwrwr_or_imm5 (void)
10813 if (inst
.operands
[2].isreg
)
10816 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10817 _("immediate operand requires iWMMXt2"));
10819 if (inst
.operands
[2].imm
== 0)
10821 switch ((inst
.instruction
>> 20) & 0xf)
10827 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10828 inst
.operands
[2].imm
= 16;
10829 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10835 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10836 inst
.operands
[2].imm
= 32;
10837 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10844 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10846 wrn
= (inst
.instruction
>> 16) & 0xf;
10847 inst
.instruction
&= 0xff0fff0f;
10848 inst
.instruction
|= wrn
;
10849 /* Bail out here; the instruction is now assembled. */
10854 /* Map 32 -> 0, etc. */
10855 inst
.operands
[2].imm
&= 0x1f;
10856 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10860 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10861 operations first, then control, shift, and load/store. */
10863 /* Insns like "foo X,Y,Z". */
10866 do_mav_triple (void)
10868 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10869 inst
.instruction
|= inst
.operands
[1].reg
;
10870 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10873 /* Insns like "foo W,X,Y,Z".
10874 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10879 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10880 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10881 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10882 inst
.instruction
|= inst
.operands
[3].reg
;
10885 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10887 do_mav_dspsc (void)
10889 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10892 /* Maverick shift immediate instructions.
10893 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10894 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10897 do_mav_shift (void)
10899 int imm
= inst
.operands
[2].imm
;
10901 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10902 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10904 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10905 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10906 Bit 4 should be 0. */
10907 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10909 inst
.instruction
|= imm
;
10912 /* XScale instructions. Also sorted arithmetic before move. */
10914 /* Xscale multiply-accumulate (argument parse)
10917 MIAxycc acc0,Rm,Rs. */
10922 inst
.instruction
|= inst
.operands
[1].reg
;
10923 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10926 /* Xscale move-accumulator-register (argument parse)
10928 MARcc acc0,RdLo,RdHi. */
10933 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10934 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10937 /* Xscale move-register-accumulator (argument parse)
10939 MRAcc RdLo,RdHi,acc0. */
10944 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10945 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10946 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10949 /* Encoding functions relevant only to Thumb. */
10951 /* inst.operands[i] is a shifted-register operand; encode
10952 it into inst.instruction in the format used by Thumb32. */
10955 encode_thumb32_shifted_operand (int i
)
10957 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10958 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10960 constraint (inst
.operands
[i
].immisreg
,
10961 _("shift by register not allowed in thumb mode"));
10962 inst
.instruction
|= inst
.operands
[i
].reg
;
10963 if (shift
== SHIFT_RRX
)
10964 inst
.instruction
|= SHIFT_ROR
<< 4;
10967 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
10968 _("expression too complex"));
10970 constraint (value
> 32
10971 || (value
== 32 && (shift
== SHIFT_LSL
10972 || shift
== SHIFT_ROR
)),
10973 _("shift expression is too large"));
10977 else if (value
== 32)
10980 inst
.instruction
|= shift
<< 4;
10981 inst
.instruction
|= (value
& 0x1c) << 10;
10982 inst
.instruction
|= (value
& 0x03) << 6;
10987 /* inst.operands[i] was set up by parse_address. Encode it into a
10988 Thumb32 format load or store instruction. Reject forms that cannot
10989 be used with such instructions. If is_t is true, reject forms that
10990 cannot be used with a T instruction; if is_d is true, reject forms
10991 that cannot be used with a D instruction. If it is a store insn,
10992 reject PC in Rn. */
10995 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10997 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10999 constraint (!inst
.operands
[i
].isreg
,
11000 _("Instruction does not support =N addresses"));
11002 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11003 if (inst
.operands
[i
].immisreg
)
11005 constraint (is_pc
, BAD_PC_ADDRESSING
);
11006 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11007 constraint (inst
.operands
[i
].negative
,
11008 _("Thumb does not support negative register indexing"));
11009 constraint (inst
.operands
[i
].postind
,
11010 _("Thumb does not support register post-indexing"));
11011 constraint (inst
.operands
[i
].writeback
,
11012 _("Thumb does not support register indexing with writeback"));
11013 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11014 _("Thumb supports only LSL in shifted register indexing"));
11016 inst
.instruction
|= inst
.operands
[i
].imm
;
11017 if (inst
.operands
[i
].shifted
)
11019 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11020 _("expression too complex"));
11021 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11022 || inst
.relocs
[0].exp
.X_add_number
> 3,
11023 _("shift out of range"));
11024 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11026 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11028 else if (inst
.operands
[i
].preind
)
11030 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11031 constraint (is_t
&& inst
.operands
[i
].writeback
,
11032 _("cannot use writeback with this instruction"));
11033 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11034 BAD_PC_ADDRESSING
);
11038 inst
.instruction
|= 0x01000000;
11039 if (inst
.operands
[i
].writeback
)
11040 inst
.instruction
|= 0x00200000;
11044 inst
.instruction
|= 0x00000c00;
11045 if (inst
.operands
[i
].writeback
)
11046 inst
.instruction
|= 0x00000100;
11048 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11050 else if (inst
.operands
[i
].postind
)
11052 gas_assert (inst
.operands
[i
].writeback
);
11053 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11054 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11057 inst
.instruction
|= 0x00200000;
11059 inst
.instruction
|= 0x00000900;
11060 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11062 else /* unindexed - only for coprocessor */
11063 inst
.error
= _("instruction does not accept unindexed addressing");
11066 /* Table of Thumb instructions which exist in both 16- and 32-bit
11067 encodings (the latter only in post-V6T2 cores). The index is the
11068 value used in the insns table below. When there is more than one
11069 possible 16-bit encoding for the instruction, this table always
11071 Also contains several pseudo-instructions used during relaxation. */
11072 #define T16_32_TAB \
11073 X(_adc, 4140, eb400000), \
11074 X(_adcs, 4140, eb500000), \
11075 X(_add, 1c00, eb000000), \
11076 X(_adds, 1c00, eb100000), \
11077 X(_addi, 0000, f1000000), \
11078 X(_addis, 0000, f1100000), \
11079 X(_add_pc,000f, f20f0000), \
11080 X(_add_sp,000d, f10d0000), \
11081 X(_adr, 000f, f20f0000), \
11082 X(_and, 4000, ea000000), \
11083 X(_ands, 4000, ea100000), \
11084 X(_asr, 1000, fa40f000), \
11085 X(_asrs, 1000, fa50f000), \
11086 X(_b, e000, f000b000), \
11087 X(_bcond, d000, f0008000), \
11088 X(_bf, 0000, f040e001), \
11089 X(_bfcsel,0000, f000e001), \
11090 X(_bfx, 0000, f060e001), \
11091 X(_bfl, 0000, f000c001), \
11092 X(_bflx, 0000, f070e001), \
11093 X(_bic, 4380, ea200000), \
11094 X(_bics, 4380, ea300000), \
11095 X(_cmn, 42c0, eb100f00), \
11096 X(_cmp, 2800, ebb00f00), \
11097 X(_cpsie, b660, f3af8400), \
11098 X(_cpsid, b670, f3af8600), \
11099 X(_cpy, 4600, ea4f0000), \
11100 X(_dec_sp,80dd, f1ad0d00), \
11101 X(_dls, 0000, f040e001), \
11102 X(_eor, 4040, ea800000), \
11103 X(_eors, 4040, ea900000), \
11104 X(_inc_sp,00dd, f10d0d00), \
11105 X(_ldmia, c800, e8900000), \
11106 X(_ldr, 6800, f8500000), \
11107 X(_ldrb, 7800, f8100000), \
11108 X(_ldrh, 8800, f8300000), \
11109 X(_ldrsb, 5600, f9100000), \
11110 X(_ldrsh, 5e00, f9300000), \
11111 X(_ldr_pc,4800, f85f0000), \
11112 X(_ldr_pc2,4800, f85f0000), \
11113 X(_ldr_sp,9800, f85d0000), \
11114 X(_le, 0000, f00fc001), \
11115 X(_lsl, 0000, fa00f000), \
11116 X(_lsls, 0000, fa10f000), \
11117 X(_lsr, 0800, fa20f000), \
11118 X(_lsrs, 0800, fa30f000), \
11119 X(_mov, 2000, ea4f0000), \
11120 X(_movs, 2000, ea5f0000), \
11121 X(_mul, 4340, fb00f000), \
11122 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11123 X(_mvn, 43c0, ea6f0000), \
11124 X(_mvns, 43c0, ea7f0000), \
11125 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11126 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11127 X(_orr, 4300, ea400000), \
11128 X(_orrs, 4300, ea500000), \
11129 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11130 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11131 X(_rev, ba00, fa90f080), \
11132 X(_rev16, ba40, fa90f090), \
11133 X(_revsh, bac0, fa90f0b0), \
11134 X(_ror, 41c0, fa60f000), \
11135 X(_rors, 41c0, fa70f000), \
11136 X(_sbc, 4180, eb600000), \
11137 X(_sbcs, 4180, eb700000), \
11138 X(_stmia, c000, e8800000), \
11139 X(_str, 6000, f8400000), \
11140 X(_strb, 7000, f8000000), \
11141 X(_strh, 8000, f8200000), \
11142 X(_str_sp,9000, f84d0000), \
11143 X(_sub, 1e00, eba00000), \
11144 X(_subs, 1e00, ebb00000), \
11145 X(_subi, 8000, f1a00000), \
11146 X(_subis, 8000, f1b00000), \
11147 X(_sxtb, b240, fa4ff080), \
11148 X(_sxth, b200, fa0ff080), \
11149 X(_tst, 4200, ea100f00), \
11150 X(_uxtb, b2c0, fa5ff080), \
11151 X(_uxth, b280, fa1ff080), \
11152 X(_nop, bf00, f3af8000), \
11153 X(_yield, bf10, f3af8001), \
11154 X(_wfe, bf20, f3af8002), \
11155 X(_wfi, bf30, f3af8003), \
11156 X(_wls, 0000, f040c001), \
11157 X(_sev, bf40, f3af8004), \
11158 X(_sevl, bf50, f3af8005), \
11159 X(_udf, de00, f7f0a000)
11161 /* To catch errors in encoding functions, the codes are all offset by
11162 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11163 as 16-bit instructions. */
11164 #define X(a,b,c) T_MNEM##a
11165 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11168 #define X(a,b,c) 0x##b
11169 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11170 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11173 #define X(a,b,c) 0x##c
11174 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11175 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11176 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11180 /* Thumb instruction encoders, in alphabetical order. */
11182 /* ADDW or SUBW. */
11185 do_t_add_sub_w (void)
11189 Rd
= inst
.operands
[0].reg
;
11190 Rn
= inst
.operands
[1].reg
;
11192 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11193 is the SP-{plus,minus}-immediate form of the instruction. */
11195 constraint (Rd
== REG_PC
, BAD_PC
);
11197 reject_bad_reg (Rd
);
11199 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11200 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11203 /* Parse an add or subtract instruction. We get here with inst.instruction
11204 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11207 do_t_add_sub (void)
11211 Rd
= inst
.operands
[0].reg
;
11212 Rs
= (inst
.operands
[1].present
11213 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11214 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11217 set_pred_insn_type_last ();
11219 if (unified_syntax
)
11222 bfd_boolean narrow
;
11225 flags
= (inst
.instruction
== T_MNEM_adds
11226 || inst
.instruction
== T_MNEM_subs
);
11228 narrow
= !in_pred_block ();
11230 narrow
= in_pred_block ();
11231 if (!inst
.operands
[2].isreg
)
11235 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11236 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11238 add
= (inst
.instruction
== T_MNEM_add
11239 || inst
.instruction
== T_MNEM_adds
);
11241 if (inst
.size_req
!= 4)
11243 /* Attempt to use a narrow opcode, with relaxation if
11245 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11246 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11247 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11248 opcode
= T_MNEM_add_sp
;
11249 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11250 opcode
= T_MNEM_add_pc
;
11251 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11254 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11256 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11260 inst
.instruction
= THUMB_OP16(opcode
);
11261 inst
.instruction
|= (Rd
<< 4) | Rs
;
11262 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11263 || (inst
.relocs
[0].type
11264 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11266 if (inst
.size_req
== 2)
11267 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11269 inst
.relax
= opcode
;
11273 constraint (inst
.size_req
== 2, BAD_HIREG
);
11275 if (inst
.size_req
== 4
11276 || (inst
.size_req
!= 2 && !opcode
))
11278 constraint ((inst
.relocs
[0].type
11279 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11280 && (inst
.relocs
[0].type
11281 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11282 THUMB1_RELOC_ONLY
);
11285 constraint (add
, BAD_PC
);
11286 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11287 _("only SUBS PC, LR, #const allowed"));
11288 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11289 _("expression too complex"));
11290 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11291 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11292 _("immediate value out of range"));
11293 inst
.instruction
= T2_SUBS_PC_LR
11294 | inst
.relocs
[0].exp
.X_add_number
;
11295 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11298 else if (Rs
== REG_PC
)
11300 /* Always use addw/subw. */
11301 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11302 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11306 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11307 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11310 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11312 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11314 inst
.instruction
|= Rd
<< 8;
11315 inst
.instruction
|= Rs
<< 16;
11320 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11321 unsigned int shift
= inst
.operands
[2].shift_kind
;
11323 Rn
= inst
.operands
[2].reg
;
11324 /* See if we can do this with a 16-bit instruction. */
11325 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11327 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11332 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11333 || inst
.instruction
== T_MNEM_add
)
11335 : T_OPCODE_SUB_R3
);
11336 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11340 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11342 /* Thumb-1 cores (except v6-M) require at least one high
11343 register in a narrow non flag setting add. */
11344 if (Rd
> 7 || Rn
> 7
11345 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11346 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11353 inst
.instruction
= T_OPCODE_ADD_HI
;
11354 inst
.instruction
|= (Rd
& 8) << 4;
11355 inst
.instruction
|= (Rd
& 7);
11356 inst
.instruction
|= Rn
<< 3;
11362 constraint (Rd
== REG_PC
, BAD_PC
);
11363 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11364 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11365 constraint (Rs
== REG_PC
, BAD_PC
);
11366 reject_bad_reg (Rn
);
11368 /* If we get here, it can't be done in 16 bits. */
11369 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11370 _("shift must be constant"));
11371 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11372 inst
.instruction
|= Rd
<< 8;
11373 inst
.instruction
|= Rs
<< 16;
11374 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11375 _("shift value over 3 not allowed in thumb mode"));
11376 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11377 _("only LSL shift allowed in thumb mode"));
11378 encode_thumb32_shifted_operand (2);
11383 constraint (inst
.instruction
== T_MNEM_adds
11384 || inst
.instruction
== T_MNEM_subs
,
11387 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11389 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11390 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11393 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11394 ? 0x0000 : 0x8000);
11395 inst
.instruction
|= (Rd
<< 4) | Rs
;
11396 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11400 Rn
= inst
.operands
[2].reg
;
11401 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11403 /* We now have Rd, Rs, and Rn set to registers. */
11404 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11406 /* Can't do this for SUB. */
11407 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11408 inst
.instruction
= T_OPCODE_ADD_HI
;
11409 inst
.instruction
|= (Rd
& 8) << 4;
11410 inst
.instruction
|= (Rd
& 7);
11412 inst
.instruction
|= Rn
<< 3;
11414 inst
.instruction
|= Rs
<< 3;
11416 constraint (1, _("dest must overlap one source register"));
11420 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11421 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11422 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11432 Rd
= inst
.operands
[0].reg
;
11433 reject_bad_reg (Rd
);
11435 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11437 /* Defer to section relaxation. */
11438 inst
.relax
= inst
.instruction
;
11439 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11440 inst
.instruction
|= Rd
<< 4;
11442 else if (unified_syntax
&& inst
.size_req
!= 2)
11444 /* Generate a 32-bit opcode. */
11445 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11446 inst
.instruction
|= Rd
<< 8;
11447 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11448 inst
.relocs
[0].pc_rel
= 1;
11452 /* Generate a 16-bit opcode. */
11453 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11454 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11455 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11456 inst
.relocs
[0].pc_rel
= 1;
11457 inst
.instruction
|= Rd
<< 4;
11460 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11461 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11462 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11463 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11464 inst
.relocs
[0].exp
.X_add_number
+= 1;
11467 /* Arithmetic instructions for which there is just one 16-bit
11468 instruction encoding, and it allows only two low registers.
11469 For maximal compatibility with ARM syntax, we allow three register
11470 operands even when Thumb-32 instructions are not available, as long
11471 as the first two are identical. For instance, both "sbc r0,r1" and
11472 "sbc r0,r0,r1" are allowed. */
11478 Rd
= inst
.operands
[0].reg
;
11479 Rs
= (inst
.operands
[1].present
11480 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11481 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11482 Rn
= inst
.operands
[2].reg
;
11484 reject_bad_reg (Rd
);
11485 reject_bad_reg (Rs
);
11486 if (inst
.operands
[2].isreg
)
11487 reject_bad_reg (Rn
);
11489 if (unified_syntax
)
11491 if (!inst
.operands
[2].isreg
)
11493 /* For an immediate, we always generate a 32-bit opcode;
11494 section relaxation will shrink it later if possible. */
11495 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11496 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11497 inst
.instruction
|= Rd
<< 8;
11498 inst
.instruction
|= Rs
<< 16;
11499 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11503 bfd_boolean narrow
;
11505 /* See if we can do this with a 16-bit instruction. */
11506 if (THUMB_SETS_FLAGS (inst
.instruction
))
11507 narrow
= !in_pred_block ();
11509 narrow
= in_pred_block ();
11511 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11513 if (inst
.operands
[2].shifted
)
11515 if (inst
.size_req
== 4)
11521 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11522 inst
.instruction
|= Rd
;
11523 inst
.instruction
|= Rn
<< 3;
11527 /* If we get here, it can't be done in 16 bits. */
11528 constraint (inst
.operands
[2].shifted
11529 && inst
.operands
[2].immisreg
,
11530 _("shift must be constant"));
11531 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11532 inst
.instruction
|= Rd
<< 8;
11533 inst
.instruction
|= Rs
<< 16;
11534 encode_thumb32_shifted_operand (2);
11539 /* On its face this is a lie - the instruction does set the
11540 flags. However, the only supported mnemonic in this mode
11541 says it doesn't. */
11542 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11544 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11545 _("unshifted register required"));
11546 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11547 constraint (Rd
!= Rs
,
11548 _("dest and source1 must be the same register"));
11550 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11551 inst
.instruction
|= Rd
;
11552 inst
.instruction
|= Rn
<< 3;
11556 /* Similarly, but for instructions where the arithmetic operation is
11557 commutative, so we can allow either of them to be different from
11558 the destination operand in a 16-bit instruction. For instance, all
11559 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11566 Rd
= inst
.operands
[0].reg
;
11567 Rs
= (inst
.operands
[1].present
11568 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11569 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11570 Rn
= inst
.operands
[2].reg
;
11572 reject_bad_reg (Rd
);
11573 reject_bad_reg (Rs
);
11574 if (inst
.operands
[2].isreg
)
11575 reject_bad_reg (Rn
);
11577 if (unified_syntax
)
11579 if (!inst
.operands
[2].isreg
)
11581 /* For an immediate, we always generate a 32-bit opcode;
11582 section relaxation will shrink it later if possible. */
11583 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11584 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11585 inst
.instruction
|= Rd
<< 8;
11586 inst
.instruction
|= Rs
<< 16;
11587 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11591 bfd_boolean narrow
;
11593 /* See if we can do this with a 16-bit instruction. */
11594 if (THUMB_SETS_FLAGS (inst
.instruction
))
11595 narrow
= !in_pred_block ();
11597 narrow
= in_pred_block ();
11599 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11601 if (inst
.operands
[2].shifted
)
11603 if (inst
.size_req
== 4)
11610 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11611 inst
.instruction
|= Rd
;
11612 inst
.instruction
|= Rn
<< 3;
11617 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11618 inst
.instruction
|= Rd
;
11619 inst
.instruction
|= Rs
<< 3;
11624 /* If we get here, it can't be done in 16 bits. */
11625 constraint (inst
.operands
[2].shifted
11626 && inst
.operands
[2].immisreg
,
11627 _("shift must be constant"));
11628 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11629 inst
.instruction
|= Rd
<< 8;
11630 inst
.instruction
|= Rs
<< 16;
11631 encode_thumb32_shifted_operand (2);
11636 /* On its face this is a lie - the instruction does set the
11637 flags. However, the only supported mnemonic in this mode
11638 says it doesn't. */
11639 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11641 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11642 _("unshifted register required"));
11643 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11645 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11646 inst
.instruction
|= Rd
;
11649 inst
.instruction
|= Rn
<< 3;
11651 inst
.instruction
|= Rs
<< 3;
11653 constraint (1, _("dest must overlap one source register"));
11661 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11662 constraint (msb
> 32, _("bit-field extends past end of register"));
11663 /* The instruction encoding stores the LSB and MSB,
11664 not the LSB and width. */
11665 Rd
= inst
.operands
[0].reg
;
11666 reject_bad_reg (Rd
);
11667 inst
.instruction
|= Rd
<< 8;
11668 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11669 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11670 inst
.instruction
|= msb
- 1;
11679 Rd
= inst
.operands
[0].reg
;
11680 reject_bad_reg (Rd
);
11682 /* #0 in second position is alternative syntax for bfc, which is
11683 the same instruction but with REG_PC in the Rm field. */
11684 if (!inst
.operands
[1].isreg
)
11688 Rn
= inst
.operands
[1].reg
;
11689 reject_bad_reg (Rn
);
11692 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11693 constraint (msb
> 32, _("bit-field extends past end of register"));
11694 /* The instruction encoding stores the LSB and MSB,
11695 not the LSB and width. */
11696 inst
.instruction
|= Rd
<< 8;
11697 inst
.instruction
|= Rn
<< 16;
11698 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11699 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11700 inst
.instruction
|= msb
- 1;
11708 Rd
= inst
.operands
[0].reg
;
11709 Rn
= inst
.operands
[1].reg
;
11711 reject_bad_reg (Rd
);
11712 reject_bad_reg (Rn
);
11714 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11715 _("bit-field extends past end of register"));
11716 inst
.instruction
|= Rd
<< 8;
11717 inst
.instruction
|= Rn
<< 16;
11718 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11719 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11720 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11723 /* ARM V5 Thumb BLX (argument parse)
11724 BLX <target_addr> which is BLX(1)
11725 BLX <Rm> which is BLX(2)
11726 Unfortunately, there are two different opcodes for this mnemonic.
11727 So, the insns[].value is not used, and the code here zaps values
11728 into inst.instruction.
11730 ??? How to take advantage of the additional two bits of displacement
11731 available in Thumb32 mode? Need new relocation? */
11736 set_pred_insn_type_last ();
11738 if (inst
.operands
[0].isreg
)
11740 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11741 /* We have a register, so this is BLX(2). */
11742 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11746 /* No register. This must be BLX(1). */
11747 inst
.instruction
= 0xf000e800;
11748 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11757 bfd_reloc_code_real_type reloc
;
11760 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
11762 if (in_pred_block ())
11764 /* Conditional branches inside IT blocks are encoded as unconditional
11766 cond
= COND_ALWAYS
;
11771 if (cond
!= COND_ALWAYS
)
11772 opcode
= T_MNEM_bcond
;
11774 opcode
= inst
.instruction
;
11777 && (inst
.size_req
== 4
11778 || (inst
.size_req
!= 2
11779 && (inst
.operands
[0].hasreloc
11780 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
11782 inst
.instruction
= THUMB_OP32(opcode
);
11783 if (cond
== COND_ALWAYS
)
11784 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11787 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11788 _("selected architecture does not support "
11789 "wide conditional branch instruction"));
11791 gas_assert (cond
!= 0xF);
11792 inst
.instruction
|= cond
<< 22;
11793 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11798 inst
.instruction
= THUMB_OP16(opcode
);
11799 if (cond
== COND_ALWAYS
)
11800 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11803 inst
.instruction
|= cond
<< 8;
11804 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11806 /* Allow section relaxation. */
11807 if (unified_syntax
&& inst
.size_req
!= 2)
11808 inst
.relax
= opcode
;
11810 inst
.relocs
[0].type
= reloc
;
11811 inst
.relocs
[0].pc_rel
= 1;
11814 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11815 between the two is the maximum immediate allowed - which is passed in
11818 do_t_bkpt_hlt1 (int range
)
11820 constraint (inst
.cond
!= COND_ALWAYS
,
11821 _("instruction is always unconditional"));
11822 if (inst
.operands
[0].present
)
11824 constraint (inst
.operands
[0].imm
> range
,
11825 _("immediate value out of range"));
11826 inst
.instruction
|= inst
.operands
[0].imm
;
11829 set_pred_insn_type (NEUTRAL_IT_INSN
);
11835 do_t_bkpt_hlt1 (63);
11841 do_t_bkpt_hlt1 (255);
11845 do_t_branch23 (void)
11847 set_pred_insn_type_last ();
11848 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11850 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11851 this file. We used to simply ignore the PLT reloc type here --
11852 the branch encoding is now needed to deal with TLSCALL relocs.
11853 So if we see a PLT reloc now, put it back to how it used to be to
11854 keep the preexisting behaviour. */
11855 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
11856 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11858 #if defined(OBJ_COFF)
11859 /* If the destination of the branch is a defined symbol which does not have
11860 the THUMB_FUNC attribute, then we must be calling a function which has
11861 the (interfacearm) attribute. We look for the Thumb entry point to that
11862 function and change the branch to refer to that function instead. */
11863 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
11864 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11865 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11866 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11867 inst
.relocs
[0].exp
.X_add_symbol
11868 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
11875 set_pred_insn_type_last ();
11876 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11877 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11878 should cause the alignment to be checked once it is known. This is
11879 because BX PC only works if the instruction is word aligned. */
11887 set_pred_insn_type_last ();
11888 Rm
= inst
.operands
[0].reg
;
11889 reject_bad_reg (Rm
);
11890 inst
.instruction
|= Rm
<< 16;
11899 Rd
= inst
.operands
[0].reg
;
11900 Rm
= inst
.operands
[1].reg
;
11902 reject_bad_reg (Rd
);
11903 reject_bad_reg (Rm
);
11905 inst
.instruction
|= Rd
<< 8;
11906 inst
.instruction
|= Rm
<< 16;
11907 inst
.instruction
|= Rm
;
11913 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11919 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11920 inst
.instruction
|= inst
.operands
[0].imm
;
11926 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11928 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11929 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11931 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11932 inst
.instruction
= 0xf3af8000;
11933 inst
.instruction
|= imod
<< 9;
11934 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11935 if (inst
.operands
[1].present
)
11936 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11940 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11941 && (inst
.operands
[0].imm
& 4),
11942 _("selected processor does not support 'A' form "
11943 "of this instruction"));
11944 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11945 _("Thumb does not support the 2-argument "
11946 "form of this instruction"));
11947 inst
.instruction
|= inst
.operands
[0].imm
;
11951 /* THUMB CPY instruction (argument parse). */
11956 if (inst
.size_req
== 4)
11958 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11959 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11960 inst
.instruction
|= inst
.operands
[1].reg
;
11964 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11965 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11966 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11973 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11974 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11975 inst
.instruction
|= inst
.operands
[0].reg
;
11976 inst
.relocs
[0].pc_rel
= 1;
11977 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11983 inst
.instruction
|= inst
.operands
[0].imm
;
11989 unsigned Rd
, Rn
, Rm
;
11991 Rd
= inst
.operands
[0].reg
;
11992 Rn
= (inst
.operands
[1].present
11993 ? inst
.operands
[1].reg
: Rd
);
11994 Rm
= inst
.operands
[2].reg
;
11996 reject_bad_reg (Rd
);
11997 reject_bad_reg (Rn
);
11998 reject_bad_reg (Rm
);
12000 inst
.instruction
|= Rd
<< 8;
12001 inst
.instruction
|= Rn
<< 16;
12002 inst
.instruction
|= Rm
;
12008 if (unified_syntax
&& inst
.size_req
== 4)
12009 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12011 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12017 unsigned int cond
= inst
.operands
[0].imm
;
12019 set_pred_insn_type (IT_INSN
);
12020 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12021 now_pred
.cc
= cond
;
12022 now_pred
.warn_deprecated
= FALSE
;
12023 now_pred
.type
= SCALAR_PRED
;
12025 /* If the condition is a negative condition, invert the mask. */
12026 if ((cond
& 0x1) == 0x0)
12028 unsigned int mask
= inst
.instruction
& 0x000f;
12030 if ((mask
& 0x7) == 0)
12032 /* No conversion needed. */
12033 now_pred
.block_length
= 1;
12035 else if ((mask
& 0x3) == 0)
12038 now_pred
.block_length
= 2;
12040 else if ((mask
& 0x1) == 0)
12043 now_pred
.block_length
= 3;
12048 now_pred
.block_length
= 4;
12051 inst
.instruction
&= 0xfff0;
12052 inst
.instruction
|= mask
;
12055 inst
.instruction
|= cond
<< 4;
12058 /* Helper function used for both push/pop and ldm/stm. */
12060 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12061 bfd_boolean writeback
)
12063 bfd_boolean load
, store
;
12065 gas_assert (base
!= -1 || !do_io
);
12066 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12067 store
= do_io
&& !load
;
12069 if (mask
& (1 << 13))
12070 inst
.error
= _("SP not allowed in register list");
12072 if (do_io
&& (mask
& (1 << base
)) != 0
12074 inst
.error
= _("having the base register in the register list when "
12075 "using write back is UNPREDICTABLE");
12079 if (mask
& (1 << 15))
12081 if (mask
& (1 << 14))
12082 inst
.error
= _("LR and PC should not both be in register list");
12084 set_pred_insn_type_last ();
12089 if (mask
& (1 << 15))
12090 inst
.error
= _("PC not allowed in register list");
12093 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12095 /* Single register transfers implemented as str/ldr. */
12098 if (inst
.instruction
& (1 << 23))
12099 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12101 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12105 if (inst
.instruction
& (1 << 23))
12106 inst
.instruction
= 0x00800000; /* ia -> [base] */
12108 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12111 inst
.instruction
|= 0xf8400000;
12113 inst
.instruction
|= 0x00100000;
12115 mask
= ffs (mask
) - 1;
12118 else if (writeback
)
12119 inst
.instruction
|= WRITE_BACK
;
12121 inst
.instruction
|= mask
;
12123 inst
.instruction
|= base
<< 16;
12129 /* This really doesn't seem worth it. */
12130 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12131 _("expression too complex"));
12132 constraint (inst
.operands
[1].writeback
,
12133 _("Thumb load/store multiple does not support {reglist}^"));
12135 if (unified_syntax
)
12137 bfd_boolean narrow
;
12141 /* See if we can use a 16-bit instruction. */
12142 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12143 && inst
.size_req
!= 4
12144 && !(inst
.operands
[1].imm
& ~0xff))
12146 mask
= 1 << inst
.operands
[0].reg
;
12148 if (inst
.operands
[0].reg
<= 7)
12150 if (inst
.instruction
== T_MNEM_stmia
12151 ? inst
.operands
[0].writeback
12152 : (inst
.operands
[0].writeback
12153 == !(inst
.operands
[1].imm
& mask
)))
12155 if (inst
.instruction
== T_MNEM_stmia
12156 && (inst
.operands
[1].imm
& mask
)
12157 && (inst
.operands
[1].imm
& (mask
- 1)))
12158 as_warn (_("value stored for r%d is UNKNOWN"),
12159 inst
.operands
[0].reg
);
12161 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12162 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12163 inst
.instruction
|= inst
.operands
[1].imm
;
12166 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12168 /* This means 1 register in reg list one of 3 situations:
12169 1. Instruction is stmia, but without writeback.
12170 2. lmdia without writeback, but with Rn not in
12172 3. ldmia with writeback, but with Rn in reglist.
12173 Case 3 is UNPREDICTABLE behaviour, so we handle
12174 case 1 and 2 which can be converted into a 16-bit
12175 str or ldr. The SP cases are handled below. */
12176 unsigned long opcode
;
12177 /* First, record an error for Case 3. */
12178 if (inst
.operands
[1].imm
& mask
12179 && inst
.operands
[0].writeback
)
12181 _("having the base register in the register list when "
12182 "using write back is UNPREDICTABLE");
12184 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12186 inst
.instruction
= THUMB_OP16 (opcode
);
12187 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12188 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12192 else if (inst
.operands
[0] .reg
== REG_SP
)
12194 if (inst
.operands
[0].writeback
)
12197 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12198 ? T_MNEM_push
: T_MNEM_pop
);
12199 inst
.instruction
|= inst
.operands
[1].imm
;
12202 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12205 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12206 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12207 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12215 if (inst
.instruction
< 0xffff)
12216 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12218 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12219 inst
.operands
[1].imm
,
12220 inst
.operands
[0].writeback
);
12225 constraint (inst
.operands
[0].reg
> 7
12226 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12227 constraint (inst
.instruction
!= T_MNEM_ldmia
12228 && inst
.instruction
!= T_MNEM_stmia
,
12229 _("Thumb-2 instruction only valid in unified syntax"));
12230 if (inst
.instruction
== T_MNEM_stmia
)
12232 if (!inst
.operands
[0].writeback
)
12233 as_warn (_("this instruction will write back the base register"));
12234 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12235 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12236 as_warn (_("value stored for r%d is UNKNOWN"),
12237 inst
.operands
[0].reg
);
12241 if (!inst
.operands
[0].writeback
12242 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12243 as_warn (_("this instruction will write back the base register"));
12244 else if (inst
.operands
[0].writeback
12245 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12246 as_warn (_("this instruction will not write back the base register"));
12249 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12250 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12251 inst
.instruction
|= inst
.operands
[1].imm
;
12258 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12259 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12260 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12261 || inst
.operands
[1].negative
,
12264 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12266 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12267 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12268 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12274 if (!inst
.operands
[1].present
)
12276 constraint (inst
.operands
[0].reg
== REG_LR
,
12277 _("r14 not allowed as first register "
12278 "when second register is omitted"));
12279 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12281 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12284 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12285 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12286 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12292 unsigned long opcode
;
12295 if (inst
.operands
[0].isreg
12296 && !inst
.operands
[0].preind
12297 && inst
.operands
[0].reg
== REG_PC
)
12298 set_pred_insn_type_last ();
12300 opcode
= inst
.instruction
;
12301 if (unified_syntax
)
12303 if (!inst
.operands
[1].isreg
)
12305 if (opcode
<= 0xffff)
12306 inst
.instruction
= THUMB_OP32 (opcode
);
12307 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12310 if (inst
.operands
[1].isreg
12311 && !inst
.operands
[1].writeback
12312 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12313 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12314 && opcode
<= 0xffff
12315 && inst
.size_req
!= 4)
12317 /* Insn may have a 16-bit form. */
12318 Rn
= inst
.operands
[1].reg
;
12319 if (inst
.operands
[1].immisreg
)
12321 inst
.instruction
= THUMB_OP16 (opcode
);
12323 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12325 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12326 reject_bad_reg (inst
.operands
[1].imm
);
12328 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12329 && opcode
!= T_MNEM_ldrsb
)
12330 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12331 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12338 if (inst
.relocs
[0].pc_rel
)
12339 opcode
= T_MNEM_ldr_pc2
;
12341 opcode
= T_MNEM_ldr_pc
;
12345 if (opcode
== T_MNEM_ldr
)
12346 opcode
= T_MNEM_ldr_sp
;
12348 opcode
= T_MNEM_str_sp
;
12350 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12354 inst
.instruction
= inst
.operands
[0].reg
;
12355 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12357 inst
.instruction
|= THUMB_OP16 (opcode
);
12358 if (inst
.size_req
== 2)
12359 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12361 inst
.relax
= opcode
;
12365 /* Definitely a 32-bit variant. */
12367 /* Warning for Erratum 752419. */
12368 if (opcode
== T_MNEM_ldr
12369 && inst
.operands
[0].reg
== REG_SP
12370 && inst
.operands
[1].writeback
== 1
12371 && !inst
.operands
[1].immisreg
)
12373 if (no_cpu_selected ()
12374 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12375 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12376 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12377 as_warn (_("This instruction may be unpredictable "
12378 "if executed on M-profile cores "
12379 "with interrupts enabled."));
12382 /* Do some validations regarding addressing modes. */
12383 if (inst
.operands
[1].immisreg
)
12384 reject_bad_reg (inst
.operands
[1].imm
);
12386 constraint (inst
.operands
[1].writeback
== 1
12387 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12390 inst
.instruction
= THUMB_OP32 (opcode
);
12391 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12392 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12393 check_ldr_r15_aligned ();
12397 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12399 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12401 /* Only [Rn,Rm] is acceptable. */
12402 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12403 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12404 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12405 || inst
.operands
[1].negative
,
12406 _("Thumb does not support this addressing mode"));
12407 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12411 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12412 if (!inst
.operands
[1].isreg
)
12413 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12416 constraint (!inst
.operands
[1].preind
12417 || inst
.operands
[1].shifted
12418 || inst
.operands
[1].writeback
,
12419 _("Thumb does not support this addressing mode"));
12420 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12422 constraint (inst
.instruction
& 0x0600,
12423 _("byte or halfword not valid for base register"));
12424 constraint (inst
.operands
[1].reg
== REG_PC
12425 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12426 _("r15 based store not allowed"));
12427 constraint (inst
.operands
[1].immisreg
,
12428 _("invalid base register for register offset"));
12430 if (inst
.operands
[1].reg
== REG_PC
)
12431 inst
.instruction
= T_OPCODE_LDR_PC
;
12432 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12433 inst
.instruction
= T_OPCODE_LDR_SP
;
12435 inst
.instruction
= T_OPCODE_STR_SP
;
12437 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12438 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12442 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12443 if (!inst
.operands
[1].immisreg
)
12445 /* Immediate offset. */
12446 inst
.instruction
|= inst
.operands
[0].reg
;
12447 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12448 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12452 /* Register offset. */
12453 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12454 constraint (inst
.operands
[1].negative
,
12455 _("Thumb does not support this addressing mode"));
12458 switch (inst
.instruction
)
12460 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12461 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12462 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12463 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12464 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12465 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12466 case 0x5600 /* ldrsb */:
12467 case 0x5e00 /* ldrsh */: break;
12471 inst
.instruction
|= inst
.operands
[0].reg
;
12472 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12473 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12479 if (!inst
.operands
[1].present
)
12481 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12482 constraint (inst
.operands
[0].reg
== REG_LR
,
12483 _("r14 not allowed here"));
12484 constraint (inst
.operands
[0].reg
== REG_R12
,
12485 _("r12 not allowed here"));
12488 if (inst
.operands
[2].writeback
12489 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12490 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12491 as_warn (_("base register written back, and overlaps "
12492 "one of transfer registers"));
12494 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12495 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12496 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12502 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12503 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12509 unsigned Rd
, Rn
, Rm
, Ra
;
12511 Rd
= inst
.operands
[0].reg
;
12512 Rn
= inst
.operands
[1].reg
;
12513 Rm
= inst
.operands
[2].reg
;
12514 Ra
= inst
.operands
[3].reg
;
12516 reject_bad_reg (Rd
);
12517 reject_bad_reg (Rn
);
12518 reject_bad_reg (Rm
);
12519 reject_bad_reg (Ra
);
12521 inst
.instruction
|= Rd
<< 8;
12522 inst
.instruction
|= Rn
<< 16;
12523 inst
.instruction
|= Rm
;
12524 inst
.instruction
|= Ra
<< 12;
12530 unsigned RdLo
, RdHi
, Rn
, Rm
;
12532 RdLo
= inst
.operands
[0].reg
;
12533 RdHi
= inst
.operands
[1].reg
;
12534 Rn
= inst
.operands
[2].reg
;
12535 Rm
= inst
.operands
[3].reg
;
12537 reject_bad_reg (RdLo
);
12538 reject_bad_reg (RdHi
);
12539 reject_bad_reg (Rn
);
12540 reject_bad_reg (Rm
);
12542 inst
.instruction
|= RdLo
<< 12;
12543 inst
.instruction
|= RdHi
<< 8;
12544 inst
.instruction
|= Rn
<< 16;
12545 inst
.instruction
|= Rm
;
12549 do_t_mov_cmp (void)
12553 Rn
= inst
.operands
[0].reg
;
12554 Rm
= inst
.operands
[1].reg
;
12557 set_pred_insn_type_last ();
12559 if (unified_syntax
)
12561 int r0off
= (inst
.instruction
== T_MNEM_mov
12562 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12563 unsigned long opcode
;
12564 bfd_boolean narrow
;
12565 bfd_boolean low_regs
;
12567 low_regs
= (Rn
<= 7 && Rm
<= 7);
12568 opcode
= inst
.instruction
;
12569 if (in_pred_block ())
12570 narrow
= opcode
!= T_MNEM_movs
;
12572 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12573 if (inst
.size_req
== 4
12574 || inst
.operands
[1].shifted
)
12577 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12578 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12579 && !inst
.operands
[1].shifted
12583 inst
.instruction
= T2_SUBS_PC_LR
;
12587 if (opcode
== T_MNEM_cmp
)
12589 constraint (Rn
== REG_PC
, BAD_PC
);
12592 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12594 warn_deprecated_sp (Rm
);
12595 /* R15 was documented as a valid choice for Rm in ARMv6,
12596 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12597 tools reject R15, so we do too. */
12598 constraint (Rm
== REG_PC
, BAD_PC
);
12601 reject_bad_reg (Rm
);
12603 else if (opcode
== T_MNEM_mov
12604 || opcode
== T_MNEM_movs
)
12606 if (inst
.operands
[1].isreg
)
12608 if (opcode
== T_MNEM_movs
)
12610 reject_bad_reg (Rn
);
12611 reject_bad_reg (Rm
);
12615 /* This is mov.n. */
12616 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12617 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12619 as_tsktsk (_("Use of r%u as a source register is "
12620 "deprecated when r%u is the destination "
12621 "register."), Rm
, Rn
);
12626 /* This is mov.w. */
12627 constraint (Rn
== REG_PC
, BAD_PC
);
12628 constraint (Rm
== REG_PC
, BAD_PC
);
12629 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12630 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12634 reject_bad_reg (Rn
);
12637 if (!inst
.operands
[1].isreg
)
12639 /* Immediate operand. */
12640 if (!in_pred_block () && opcode
== T_MNEM_mov
)
12642 if (low_regs
&& narrow
)
12644 inst
.instruction
= THUMB_OP16 (opcode
);
12645 inst
.instruction
|= Rn
<< 8;
12646 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12647 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12649 if (inst
.size_req
== 2)
12650 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12652 inst
.relax
= opcode
;
12657 constraint ((inst
.relocs
[0].type
12658 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12659 && (inst
.relocs
[0].type
12660 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12661 THUMB1_RELOC_ONLY
);
12663 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12664 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12665 inst
.instruction
|= Rn
<< r0off
;
12666 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12669 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12670 && (inst
.instruction
== T_MNEM_mov
12671 || inst
.instruction
== T_MNEM_movs
))
12673 /* Register shifts are encoded as separate shift instructions. */
12674 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12676 if (in_pred_block ())
12681 if (inst
.size_req
== 4)
12684 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12690 switch (inst
.operands
[1].shift_kind
)
12693 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12696 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12699 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12702 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12708 inst
.instruction
= opcode
;
12711 inst
.instruction
|= Rn
;
12712 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12717 inst
.instruction
|= CONDS_BIT
;
12719 inst
.instruction
|= Rn
<< 8;
12720 inst
.instruction
|= Rm
<< 16;
12721 inst
.instruction
|= inst
.operands
[1].imm
;
12726 /* Some mov with immediate shift have narrow variants.
12727 Register shifts are handled above. */
12728 if (low_regs
&& inst
.operands
[1].shifted
12729 && (inst
.instruction
== T_MNEM_mov
12730 || inst
.instruction
== T_MNEM_movs
))
12732 if (in_pred_block ())
12733 narrow
= (inst
.instruction
== T_MNEM_mov
);
12735 narrow
= (inst
.instruction
== T_MNEM_movs
);
12740 switch (inst
.operands
[1].shift_kind
)
12742 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12743 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12744 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12745 default: narrow
= FALSE
; break;
12751 inst
.instruction
|= Rn
;
12752 inst
.instruction
|= Rm
<< 3;
12753 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12757 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12758 inst
.instruction
|= Rn
<< r0off
;
12759 encode_thumb32_shifted_operand (1);
12763 switch (inst
.instruction
)
12766 /* In v4t or v5t a move of two lowregs produces unpredictable
12767 results. Don't allow this. */
12770 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12771 "MOV Rd, Rs with two low registers is not "
12772 "permitted on this architecture");
12773 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12777 inst
.instruction
= T_OPCODE_MOV_HR
;
12778 inst
.instruction
|= (Rn
& 0x8) << 4;
12779 inst
.instruction
|= (Rn
& 0x7);
12780 inst
.instruction
|= Rm
<< 3;
12784 /* We know we have low registers at this point.
12785 Generate LSLS Rd, Rs, #0. */
12786 inst
.instruction
= T_OPCODE_LSL_I
;
12787 inst
.instruction
|= Rn
;
12788 inst
.instruction
|= Rm
<< 3;
12794 inst
.instruction
= T_OPCODE_CMP_LR
;
12795 inst
.instruction
|= Rn
;
12796 inst
.instruction
|= Rm
<< 3;
12800 inst
.instruction
= T_OPCODE_CMP_HR
;
12801 inst
.instruction
|= (Rn
& 0x8) << 4;
12802 inst
.instruction
|= (Rn
& 0x7);
12803 inst
.instruction
|= Rm
<< 3;
12810 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12812 /* PR 10443: Do not silently ignore shifted operands. */
12813 constraint (inst
.operands
[1].shifted
,
12814 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12816 if (inst
.operands
[1].isreg
)
12818 if (Rn
< 8 && Rm
< 8)
12820 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12821 since a MOV instruction produces unpredictable results. */
12822 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12823 inst
.instruction
= T_OPCODE_ADD_I3
;
12825 inst
.instruction
= T_OPCODE_CMP_LR
;
12827 inst
.instruction
|= Rn
;
12828 inst
.instruction
|= Rm
<< 3;
12832 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12833 inst
.instruction
= T_OPCODE_MOV_HR
;
12835 inst
.instruction
= T_OPCODE_CMP_HR
;
12841 constraint (Rn
> 7,
12842 _("only lo regs allowed with immediate"));
12843 inst
.instruction
|= Rn
<< 8;
12844 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12855 top
= (inst
.instruction
& 0x00800000) != 0;
12856 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
12858 constraint (top
, _(":lower16: not allowed in this instruction"));
12859 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
12861 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
12863 constraint (!top
, _(":upper16: not allowed in this instruction"));
12864 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
12867 Rd
= inst
.operands
[0].reg
;
12868 reject_bad_reg (Rd
);
12870 inst
.instruction
|= Rd
<< 8;
12871 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
12873 imm
= inst
.relocs
[0].exp
.X_add_number
;
12874 inst
.instruction
|= (imm
& 0xf000) << 4;
12875 inst
.instruction
|= (imm
& 0x0800) << 15;
12876 inst
.instruction
|= (imm
& 0x0700) << 4;
12877 inst
.instruction
|= (imm
& 0x00ff);
12882 do_t_mvn_tst (void)
12886 Rn
= inst
.operands
[0].reg
;
12887 Rm
= inst
.operands
[1].reg
;
12889 if (inst
.instruction
== T_MNEM_cmp
12890 || inst
.instruction
== T_MNEM_cmn
)
12891 constraint (Rn
== REG_PC
, BAD_PC
);
12893 reject_bad_reg (Rn
);
12894 reject_bad_reg (Rm
);
12896 if (unified_syntax
)
12898 int r0off
= (inst
.instruction
== T_MNEM_mvn
12899 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12900 bfd_boolean narrow
;
12902 if (inst
.size_req
== 4
12903 || inst
.instruction
> 0xffff
12904 || inst
.operands
[1].shifted
12905 || Rn
> 7 || Rm
> 7)
12907 else if (inst
.instruction
== T_MNEM_cmn
12908 || inst
.instruction
== T_MNEM_tst
)
12910 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12911 narrow
= !in_pred_block ();
12913 narrow
= in_pred_block ();
12915 if (!inst
.operands
[1].isreg
)
12917 /* For an immediate, we always generate a 32-bit opcode;
12918 section relaxation will shrink it later if possible. */
12919 if (inst
.instruction
< 0xffff)
12920 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12921 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12922 inst
.instruction
|= Rn
<< r0off
;
12923 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12927 /* See if we can do this with a 16-bit instruction. */
12930 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12931 inst
.instruction
|= Rn
;
12932 inst
.instruction
|= Rm
<< 3;
12936 constraint (inst
.operands
[1].shifted
12937 && inst
.operands
[1].immisreg
,
12938 _("shift must be constant"));
12939 if (inst
.instruction
< 0xffff)
12940 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12941 inst
.instruction
|= Rn
<< r0off
;
12942 encode_thumb32_shifted_operand (1);
12948 constraint (inst
.instruction
> 0xffff
12949 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12950 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12951 _("unshifted register required"));
12952 constraint (Rn
> 7 || Rm
> 7,
12955 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12956 inst
.instruction
|= Rn
;
12957 inst
.instruction
|= Rm
<< 3;
12966 if (do_vfp_nsyn_mrs () == SUCCESS
)
12969 Rd
= inst
.operands
[0].reg
;
12970 reject_bad_reg (Rd
);
12971 inst
.instruction
|= Rd
<< 8;
12973 if (inst
.operands
[1].isreg
)
12975 unsigned br
= inst
.operands
[1].reg
;
12976 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12977 as_bad (_("bad register for mrs"));
12979 inst
.instruction
|= br
& (0xf << 16);
12980 inst
.instruction
|= (br
& 0x300) >> 4;
12981 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12985 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12987 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12989 /* PR gas/12698: The constraint is only applied for m_profile.
12990 If the user has specified -march=all, we want to ignore it as
12991 we are building for any CPU type, including non-m variants. */
12992 bfd_boolean m_profile
=
12993 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12994 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12995 "not support requested special purpose register"));
12998 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13000 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13001 _("'APSR', 'CPSR' or 'SPSR' expected"));
13003 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13004 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13005 inst
.instruction
|= 0xf0000;
13015 if (do_vfp_nsyn_msr () == SUCCESS
)
13018 constraint (!inst
.operands
[1].isreg
,
13019 _("Thumb encoding does not support an immediate here"));
13021 if (inst
.operands
[0].isreg
)
13022 flags
= (int)(inst
.operands
[0].reg
);
13024 flags
= inst
.operands
[0].imm
;
13026 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13028 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13030 /* PR gas/12698: The constraint is only applied for m_profile.
13031 If the user has specified -march=all, we want to ignore it as
13032 we are building for any CPU type, including non-m variants. */
13033 bfd_boolean m_profile
=
13034 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13035 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13036 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13037 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13038 && bits
!= PSR_f
)) && m_profile
,
13039 _("selected processor does not support requested special "
13040 "purpose register"));
13043 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13044 "requested special purpose register"));
13046 Rn
= inst
.operands
[1].reg
;
13047 reject_bad_reg (Rn
);
13049 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13050 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13051 inst
.instruction
|= (flags
& 0x300) >> 4;
13052 inst
.instruction
|= (flags
& 0xff);
13053 inst
.instruction
|= Rn
<< 16;
13059 bfd_boolean narrow
;
13060 unsigned Rd
, Rn
, Rm
;
13062 if (!inst
.operands
[2].present
)
13063 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13065 Rd
= inst
.operands
[0].reg
;
13066 Rn
= inst
.operands
[1].reg
;
13067 Rm
= inst
.operands
[2].reg
;
13069 if (unified_syntax
)
13071 if (inst
.size_req
== 4
13077 else if (inst
.instruction
== T_MNEM_muls
)
13078 narrow
= !in_pred_block ();
13080 narrow
= in_pred_block ();
13084 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13085 constraint (Rn
> 7 || Rm
> 7,
13092 /* 16-bit MULS/Conditional MUL. */
13093 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13094 inst
.instruction
|= Rd
;
13097 inst
.instruction
|= Rm
<< 3;
13099 inst
.instruction
|= Rn
<< 3;
13101 constraint (1, _("dest must overlap one source register"));
13105 constraint (inst
.instruction
!= T_MNEM_mul
,
13106 _("Thumb-2 MUL must not set flags"));
13108 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13109 inst
.instruction
|= Rd
<< 8;
13110 inst
.instruction
|= Rn
<< 16;
13111 inst
.instruction
|= Rm
<< 0;
13113 reject_bad_reg (Rd
);
13114 reject_bad_reg (Rn
);
13115 reject_bad_reg (Rm
);
13122 unsigned RdLo
, RdHi
, Rn
, Rm
;
13124 RdLo
= inst
.operands
[0].reg
;
13125 RdHi
= inst
.operands
[1].reg
;
13126 Rn
= inst
.operands
[2].reg
;
13127 Rm
= inst
.operands
[3].reg
;
13129 reject_bad_reg (RdLo
);
13130 reject_bad_reg (RdHi
);
13131 reject_bad_reg (Rn
);
13132 reject_bad_reg (Rm
);
13134 inst
.instruction
|= RdLo
<< 12;
13135 inst
.instruction
|= RdHi
<< 8;
13136 inst
.instruction
|= Rn
<< 16;
13137 inst
.instruction
|= Rm
;
13140 as_tsktsk (_("rdhi and rdlo must be different"));
13146 set_pred_insn_type (NEUTRAL_IT_INSN
);
13148 if (unified_syntax
)
13150 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13152 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13153 inst
.instruction
|= inst
.operands
[0].imm
;
13157 /* PR9722: Check for Thumb2 availability before
13158 generating a thumb2 nop instruction. */
13159 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13161 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13162 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13165 inst
.instruction
= 0x46c0;
13170 constraint (inst
.operands
[0].present
,
13171 _("Thumb does not support NOP with hints"));
13172 inst
.instruction
= 0x46c0;
13179 if (unified_syntax
)
13181 bfd_boolean narrow
;
13183 if (THUMB_SETS_FLAGS (inst
.instruction
))
13184 narrow
= !in_pred_block ();
13186 narrow
= in_pred_block ();
13187 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13189 if (inst
.size_req
== 4)
13194 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13195 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13196 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13200 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13201 inst
.instruction
|= inst
.operands
[0].reg
;
13202 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13207 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13209 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13211 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13212 inst
.instruction
|= inst
.operands
[0].reg
;
13213 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13222 Rd
= inst
.operands
[0].reg
;
13223 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13225 reject_bad_reg (Rd
);
13226 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13227 reject_bad_reg (Rn
);
13229 inst
.instruction
|= Rd
<< 8;
13230 inst
.instruction
|= Rn
<< 16;
13232 if (!inst
.operands
[2].isreg
)
13234 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13235 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13241 Rm
= inst
.operands
[2].reg
;
13242 reject_bad_reg (Rm
);
13244 constraint (inst
.operands
[2].shifted
13245 && inst
.operands
[2].immisreg
,
13246 _("shift must be constant"));
13247 encode_thumb32_shifted_operand (2);
13254 unsigned Rd
, Rn
, Rm
;
13256 Rd
= inst
.operands
[0].reg
;
13257 Rn
= inst
.operands
[1].reg
;
13258 Rm
= inst
.operands
[2].reg
;
13260 reject_bad_reg (Rd
);
13261 reject_bad_reg (Rn
);
13262 reject_bad_reg (Rm
);
13264 inst
.instruction
|= Rd
<< 8;
13265 inst
.instruction
|= Rn
<< 16;
13266 inst
.instruction
|= Rm
;
13267 if (inst
.operands
[3].present
)
13269 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13270 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13271 _("expression too complex"));
13272 inst
.instruction
|= (val
& 0x1c) << 10;
13273 inst
.instruction
|= (val
& 0x03) << 6;
13280 if (!inst
.operands
[3].present
)
13284 inst
.instruction
&= ~0x00000020;
13286 /* PR 10168. Swap the Rm and Rn registers. */
13287 Rtmp
= inst
.operands
[1].reg
;
13288 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13289 inst
.operands
[2].reg
= Rtmp
;
13297 if (inst
.operands
[0].immisreg
)
13298 reject_bad_reg (inst
.operands
[0].imm
);
13300 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13304 do_t_push_pop (void)
13308 constraint (inst
.operands
[0].writeback
,
13309 _("push/pop do not support {reglist}^"));
13310 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13311 _("expression too complex"));
13313 mask
= inst
.operands
[0].imm
;
13314 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13315 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13316 else if (inst
.size_req
!= 4
13317 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13318 ? REG_LR
: REG_PC
)))
13320 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13321 inst
.instruction
|= THUMB_PP_PC_LR
;
13322 inst
.instruction
|= mask
& 0xff;
13324 else if (unified_syntax
)
13326 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13327 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13331 inst
.error
= _("invalid register list to push/pop instruction");
13339 if (unified_syntax
)
13340 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13343 inst
.error
= _("invalid register list to push/pop instruction");
13349 do_t_vscclrm (void)
13351 if (inst
.operands
[0].issingle
)
13353 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13354 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13355 inst
.instruction
|= inst
.operands
[0].imm
;
13359 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13360 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13361 inst
.instruction
|= 1 << 8;
13362 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13371 Rd
= inst
.operands
[0].reg
;
13372 Rm
= inst
.operands
[1].reg
;
13374 reject_bad_reg (Rd
);
13375 reject_bad_reg (Rm
);
13377 inst
.instruction
|= Rd
<< 8;
13378 inst
.instruction
|= Rm
<< 16;
13379 inst
.instruction
|= Rm
;
13387 Rd
= inst
.operands
[0].reg
;
13388 Rm
= inst
.operands
[1].reg
;
13390 reject_bad_reg (Rd
);
13391 reject_bad_reg (Rm
);
13393 if (Rd
<= 7 && Rm
<= 7
13394 && inst
.size_req
!= 4)
13396 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13397 inst
.instruction
|= Rd
;
13398 inst
.instruction
|= Rm
<< 3;
13400 else if (unified_syntax
)
13402 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13403 inst
.instruction
|= Rd
<< 8;
13404 inst
.instruction
|= Rm
<< 16;
13405 inst
.instruction
|= Rm
;
13408 inst
.error
= BAD_HIREG
;
13416 Rd
= inst
.operands
[0].reg
;
13417 Rm
= inst
.operands
[1].reg
;
13419 reject_bad_reg (Rd
);
13420 reject_bad_reg (Rm
);
13422 inst
.instruction
|= Rd
<< 8;
13423 inst
.instruction
|= Rm
;
13431 Rd
= inst
.operands
[0].reg
;
13432 Rs
= (inst
.operands
[1].present
13433 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13434 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13436 reject_bad_reg (Rd
);
13437 reject_bad_reg (Rs
);
13438 if (inst
.operands
[2].isreg
)
13439 reject_bad_reg (inst
.operands
[2].reg
);
13441 inst
.instruction
|= Rd
<< 8;
13442 inst
.instruction
|= Rs
<< 16;
13443 if (!inst
.operands
[2].isreg
)
13445 bfd_boolean narrow
;
13447 if ((inst
.instruction
& 0x00100000) != 0)
13448 narrow
= !in_pred_block ();
13450 narrow
= in_pred_block ();
13452 if (Rd
> 7 || Rs
> 7)
13455 if (inst
.size_req
== 4 || !unified_syntax
)
13458 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13459 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13462 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13463 relaxation, but it doesn't seem worth the hassle. */
13466 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13467 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13468 inst
.instruction
|= Rs
<< 3;
13469 inst
.instruction
|= Rd
;
13473 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13474 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13478 encode_thumb32_shifted_operand (2);
13484 if (warn_on_deprecated
13485 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13486 as_tsktsk (_("setend use is deprecated for ARMv8"));
13488 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13489 if (inst
.operands
[0].imm
)
13490 inst
.instruction
|= 0x8;
13496 if (!inst
.operands
[1].present
)
13497 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13499 if (unified_syntax
)
13501 bfd_boolean narrow
;
13504 switch (inst
.instruction
)
13507 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13509 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13511 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13513 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13517 if (THUMB_SETS_FLAGS (inst
.instruction
))
13518 narrow
= !in_pred_block ();
13520 narrow
= in_pred_block ();
13521 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13523 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13525 if (inst
.operands
[2].isreg
13526 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13527 || inst
.operands
[2].reg
> 7))
13529 if (inst
.size_req
== 4)
13532 reject_bad_reg (inst
.operands
[0].reg
);
13533 reject_bad_reg (inst
.operands
[1].reg
);
13537 if (inst
.operands
[2].isreg
)
13539 reject_bad_reg (inst
.operands
[2].reg
);
13540 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13541 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13542 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13543 inst
.instruction
|= inst
.operands
[2].reg
;
13545 /* PR 12854: Error on extraneous shifts. */
13546 constraint (inst
.operands
[2].shifted
,
13547 _("extraneous shift as part of operand to shift insn"));
13551 inst
.operands
[1].shifted
= 1;
13552 inst
.operands
[1].shift_kind
= shift_kind
;
13553 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13554 ? T_MNEM_movs
: T_MNEM_mov
);
13555 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13556 encode_thumb32_shifted_operand (1);
13557 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13558 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13563 if (inst
.operands
[2].isreg
)
13565 switch (shift_kind
)
13567 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13568 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13569 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13570 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13574 inst
.instruction
|= inst
.operands
[0].reg
;
13575 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13577 /* PR 12854: Error on extraneous shifts. */
13578 constraint (inst
.operands
[2].shifted
,
13579 _("extraneous shift as part of operand to shift insn"));
13583 switch (shift_kind
)
13585 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13586 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13587 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13590 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13591 inst
.instruction
|= inst
.operands
[0].reg
;
13592 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13598 constraint (inst
.operands
[0].reg
> 7
13599 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13600 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13602 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13604 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13605 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13606 _("source1 and dest must be same register"));
13608 switch (inst
.instruction
)
13610 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13611 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13612 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13613 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13617 inst
.instruction
|= inst
.operands
[0].reg
;
13618 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13620 /* PR 12854: Error on extraneous shifts. */
13621 constraint (inst
.operands
[2].shifted
,
13622 _("extraneous shift as part of operand to shift insn"));
13626 switch (inst
.instruction
)
13628 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13629 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13630 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13631 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13634 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13635 inst
.instruction
|= inst
.operands
[0].reg
;
13636 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13644 unsigned Rd
, Rn
, Rm
;
13646 Rd
= inst
.operands
[0].reg
;
13647 Rn
= inst
.operands
[1].reg
;
13648 Rm
= inst
.operands
[2].reg
;
13650 reject_bad_reg (Rd
);
13651 reject_bad_reg (Rn
);
13652 reject_bad_reg (Rm
);
13654 inst
.instruction
|= Rd
<< 8;
13655 inst
.instruction
|= Rn
<< 16;
13656 inst
.instruction
|= Rm
;
13662 unsigned Rd
, Rn
, Rm
;
13664 Rd
= inst
.operands
[0].reg
;
13665 Rm
= inst
.operands
[1].reg
;
13666 Rn
= inst
.operands
[2].reg
;
13668 reject_bad_reg (Rd
);
13669 reject_bad_reg (Rn
);
13670 reject_bad_reg (Rm
);
13672 inst
.instruction
|= Rd
<< 8;
13673 inst
.instruction
|= Rn
<< 16;
13674 inst
.instruction
|= Rm
;
13680 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13681 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13682 _("SMC is not permitted on this architecture"));
13683 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13684 _("expression too complex"));
13685 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13686 inst
.instruction
|= (value
& 0xf000) >> 12;
13687 inst
.instruction
|= (value
& 0x0ff0);
13688 inst
.instruction
|= (value
& 0x000f) << 16;
13689 /* PR gas/15623: SMC instructions must be last in an IT block. */
13690 set_pred_insn_type_last ();
13696 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13698 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13699 inst
.instruction
|= (value
& 0x0fff);
13700 inst
.instruction
|= (value
& 0xf000) << 4;
13704 do_t_ssat_usat (int bias
)
13708 Rd
= inst
.operands
[0].reg
;
13709 Rn
= inst
.operands
[2].reg
;
13711 reject_bad_reg (Rd
);
13712 reject_bad_reg (Rn
);
13714 inst
.instruction
|= Rd
<< 8;
13715 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13716 inst
.instruction
|= Rn
<< 16;
13718 if (inst
.operands
[3].present
)
13720 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
13722 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13724 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13725 _("expression too complex"));
13727 if (shift_amount
!= 0)
13729 constraint (shift_amount
> 31,
13730 _("shift expression is too large"));
13732 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13733 inst
.instruction
|= 0x00200000; /* sh bit. */
13735 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13736 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13744 do_t_ssat_usat (1);
13752 Rd
= inst
.operands
[0].reg
;
13753 Rn
= inst
.operands
[2].reg
;
13755 reject_bad_reg (Rd
);
13756 reject_bad_reg (Rn
);
13758 inst
.instruction
|= Rd
<< 8;
13759 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13760 inst
.instruction
|= Rn
<< 16;
13766 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13767 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13768 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13769 || inst
.operands
[2].negative
,
13772 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13774 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13775 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13776 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13777 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13783 if (!inst
.operands
[2].present
)
13784 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13786 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13787 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13788 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13791 inst
.instruction
|= inst
.operands
[0].reg
;
13792 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13793 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13794 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13800 unsigned Rd
, Rn
, Rm
;
13802 Rd
= inst
.operands
[0].reg
;
13803 Rn
= inst
.operands
[1].reg
;
13804 Rm
= inst
.operands
[2].reg
;
13806 reject_bad_reg (Rd
);
13807 reject_bad_reg (Rn
);
13808 reject_bad_reg (Rm
);
13810 inst
.instruction
|= Rd
<< 8;
13811 inst
.instruction
|= Rn
<< 16;
13812 inst
.instruction
|= Rm
;
13813 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13821 Rd
= inst
.operands
[0].reg
;
13822 Rm
= inst
.operands
[1].reg
;
13824 reject_bad_reg (Rd
);
13825 reject_bad_reg (Rm
);
13827 if (inst
.instruction
<= 0xffff
13828 && inst
.size_req
!= 4
13829 && Rd
<= 7 && Rm
<= 7
13830 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13832 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13833 inst
.instruction
|= Rd
;
13834 inst
.instruction
|= Rm
<< 3;
13836 else if (unified_syntax
)
13838 if (inst
.instruction
<= 0xffff)
13839 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13840 inst
.instruction
|= Rd
<< 8;
13841 inst
.instruction
|= Rm
;
13842 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13846 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13847 _("Thumb encoding does not support rotation"));
13848 constraint (1, BAD_HIREG
);
13855 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
13864 half
= (inst
.instruction
& 0x10) != 0;
13865 set_pred_insn_type_last ();
13866 constraint (inst
.operands
[0].immisreg
,
13867 _("instruction requires register index"));
13869 Rn
= inst
.operands
[0].reg
;
13870 Rm
= inst
.operands
[0].imm
;
13872 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13873 constraint (Rn
== REG_SP
, BAD_SP
);
13874 reject_bad_reg (Rm
);
13876 constraint (!half
&& inst
.operands
[0].shifted
,
13877 _("instruction does not allow shifted index"));
13878 inst
.instruction
|= (Rn
<< 16) | Rm
;
13884 if (!inst
.operands
[0].present
)
13885 inst
.operands
[0].imm
= 0;
13887 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13889 constraint (inst
.size_req
== 2,
13890 _("immediate value out of range"));
13891 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13892 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13893 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13897 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13898 inst
.instruction
|= inst
.operands
[0].imm
;
13901 set_pred_insn_type (NEUTRAL_IT_INSN
);
13908 do_t_ssat_usat (0);
13916 Rd
= inst
.operands
[0].reg
;
13917 Rn
= inst
.operands
[2].reg
;
13919 reject_bad_reg (Rd
);
13920 reject_bad_reg (Rn
);
13922 inst
.instruction
|= Rd
<< 8;
13923 inst
.instruction
|= inst
.operands
[1].imm
;
13924 inst
.instruction
|= Rn
<< 16;
13927 /* Checking the range of the branch offset (VAL) with NBITS bits
13928 and IS_SIGNED signedness. Also checks the LSB to be 0. */
13930 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
13932 gas_assert (nbits
> 0 && nbits
<= 32);
13935 int cmp
= (1 << (nbits
- 1));
13936 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
13941 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
13947 /* For branches in Armv8.1-M Mainline. */
13949 do_t_branch_future (void)
13951 unsigned long insn
= inst
.instruction
;
13953 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13954 if (inst
.operands
[0].hasreloc
== 0)
13956 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
13957 as_bad (BAD_BRANCH_OFF
);
13959 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
13963 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
13964 inst
.relocs
[0].pc_rel
= 1;
13970 if (inst
.operands
[1].hasreloc
== 0)
13972 int val
= inst
.operands
[1].imm
;
13973 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
13974 as_bad (BAD_BRANCH_OFF
);
13976 int immA
= (val
& 0x0001f000) >> 12;
13977 int immB
= (val
& 0x00000ffc) >> 2;
13978 int immC
= (val
& 0x00000002) >> 1;
13979 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
13983 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
13984 inst
.relocs
[1].pc_rel
= 1;
13989 if (inst
.operands
[1].hasreloc
== 0)
13991 int val
= inst
.operands
[1].imm
;
13992 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
13993 as_bad (BAD_BRANCH_OFF
);
13995 int immA
= (val
& 0x0007f000) >> 12;
13996 int immB
= (val
& 0x00000ffc) >> 2;
13997 int immC
= (val
& 0x00000002) >> 1;
13998 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14002 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14003 inst
.relocs
[1].pc_rel
= 1;
14007 case T_MNEM_bfcsel
:
14009 if (inst
.operands
[1].hasreloc
== 0)
14011 int val
= inst
.operands
[1].imm
;
14012 int immA
= (val
& 0x00001000) >> 12;
14013 int immB
= (val
& 0x00000ffc) >> 2;
14014 int immC
= (val
& 0x00000002) >> 1;
14015 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14019 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14020 inst
.relocs
[1].pc_rel
= 1;
14024 if (inst
.operands
[2].hasreloc
== 0)
14026 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14027 int val2
= inst
.operands
[2].imm
;
14028 int val0
= inst
.operands
[0].imm
& 0x1f;
14029 int diff
= val2
- val0
;
14031 inst
.instruction
|= 1 << 17; /* T bit. */
14032 else if (diff
!= 2)
14033 as_bad (_("out of range label-relative fixup value"));
14037 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14038 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14039 inst
.relocs
[2].pc_rel
= 1;
14043 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14044 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14049 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14056 /* Helper function for do_t_loloop to handle relocations. */
14058 v8_1_loop_reloc (int is_le
)
14060 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14062 int value
= inst
.relocs
[0].exp
.X_add_number
;
14063 value
= (is_le
) ? -value
: value
;
14065 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14066 as_bad (BAD_BRANCH_OFF
);
14070 immh
= (value
& 0x00000ffc) >> 2;
14071 imml
= (value
& 0x00000002) >> 1;
14073 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14077 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14078 inst
.relocs
[0].pc_rel
= 1;
14082 /* To handle the Scalar Low Overhead Loop instructions
14083 in Armv8.1-M Mainline. */
14087 unsigned long insn
= inst
.instruction
;
14089 set_pred_insn_type (OUTSIDE_PRED_INSN
);
14090 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14096 if (!inst
.operands
[0].present
)
14097 inst
.instruction
|= 1 << 21;
14099 v8_1_loop_reloc (TRUE
);
14103 v8_1_loop_reloc (FALSE
);
14104 /* Fall through. */
14106 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
14107 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
14114 /* MVE instruction encoder helpers. */
14115 #define M_MNEM_vabav 0xee800f01
14116 #define M_MNEM_vmladav 0xeef00e00
14117 #define M_MNEM_vmladava 0xeef00e20
14118 #define M_MNEM_vmladavx 0xeef01e00
14119 #define M_MNEM_vmladavax 0xeef01e20
14120 #define M_MNEM_vmlsdav 0xeef00e01
14121 #define M_MNEM_vmlsdava 0xeef00e21
14122 #define M_MNEM_vmlsdavx 0xeef01e01
14123 #define M_MNEM_vmlsdavax 0xeef01e21
14124 #define M_MNEM_vmullt 0xee011e00
14125 #define M_MNEM_vmullb 0xee010e00
14126 #define M_MNEM_vst20 0xfc801e00
14127 #define M_MNEM_vst21 0xfc801e20
14128 #define M_MNEM_vst40 0xfc801e01
14129 #define M_MNEM_vst41 0xfc801e21
14130 #define M_MNEM_vst42 0xfc801e41
14131 #define M_MNEM_vst43 0xfc801e61
14132 #define M_MNEM_vld20 0xfc901e00
14133 #define M_MNEM_vld21 0xfc901e20
14134 #define M_MNEM_vld40 0xfc901e01
14135 #define M_MNEM_vld41 0xfc901e21
14136 #define M_MNEM_vld42 0xfc901e41
14137 #define M_MNEM_vld43 0xfc901e61
14138 #define M_MNEM_vstrb 0xec000e00
14139 #define M_MNEM_vstrh 0xec000e10
14140 #define M_MNEM_vstrw 0xec000e40
14141 #define M_MNEM_vstrd 0xec000e50
14142 #define M_MNEM_vldrb 0xec100e00
14143 #define M_MNEM_vldrh 0xec100e10
14144 #define M_MNEM_vldrw 0xec100e40
14145 #define M_MNEM_vldrd 0xec100e50
14146 #define M_MNEM_vmovlt 0xeea01f40
14147 #define M_MNEM_vmovlb 0xeea00f40
14148 #define M_MNEM_vmovnt 0xfe311e81
14149 #define M_MNEM_vmovnb 0xfe310e81
14150 #define M_MNEM_vadc 0xee300f00
14151 #define M_MNEM_vadci 0xee301f00
14152 #define M_MNEM_vbrsr 0xfe011e60
14153 #define M_MNEM_vaddlv 0xee890f00
14154 #define M_MNEM_vaddlva 0xee890f20
14155 #define M_MNEM_vaddv 0xeef10f00
14156 #define M_MNEM_vaddva 0xeef10f20
14158 /* Neon instruction encoder helpers. */
14160 /* Encodings for the different types for various Neon opcodes. */
14162 /* An "invalid" code for the following tables. */
14165 struct neon_tab_entry
14168 unsigned float_or_poly
;
14169 unsigned scalar_or_imm
;
14172 /* Map overloaded Neon opcodes to their respective encodings. */
14173 #define NEON_ENC_TAB \
14174 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14175 X(vabdl, 0x0800700, N_INV, N_INV), \
14176 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14177 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14178 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14179 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14180 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14181 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14182 X(vaddl, 0x0800000, N_INV, N_INV), \
14183 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14184 X(vsubl, 0x0800200, N_INV, N_INV), \
14185 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14186 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14187 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14188 /* Register variants of the following two instructions are encoded as
14189 vcge / vcgt with the operands reversed. */ \
14190 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14191 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14192 X(vfma, N_INV, 0x0000c10, N_INV), \
14193 X(vfms, N_INV, 0x0200c10, N_INV), \
14194 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14195 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14196 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14197 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14198 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14199 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14200 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14201 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14202 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14203 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14204 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14205 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14206 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14207 X(vshl, 0x0000400, N_INV, 0x0800510), \
14208 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14209 X(vand, 0x0000110, N_INV, 0x0800030), \
14210 X(vbic, 0x0100110, N_INV, 0x0800030), \
14211 X(veor, 0x1000110, N_INV, N_INV), \
14212 X(vorn, 0x0300110, N_INV, 0x0800010), \
14213 X(vorr, 0x0200110, N_INV, 0x0800010), \
14214 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14215 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14216 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14217 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14218 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14219 X(vst1, 0x0000000, 0x0800000, N_INV), \
14220 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14221 X(vst2, 0x0000100, 0x0800100, N_INV), \
14222 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14223 X(vst3, 0x0000200, 0x0800200, N_INV), \
14224 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14225 X(vst4, 0x0000300, 0x0800300, N_INV), \
14226 X(vmovn, 0x1b20200, N_INV, N_INV), \
14227 X(vtrn, 0x1b20080, N_INV, N_INV), \
14228 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14229 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14230 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14231 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14232 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14233 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14234 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14235 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14236 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14237 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14238 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14239 X(vseleq, 0xe000a00, N_INV, N_INV), \
14240 X(vselvs, 0xe100a00, N_INV, N_INV), \
14241 X(vselge, 0xe200a00, N_INV, N_INV), \
14242 X(vselgt, 0xe300a00, N_INV, N_INV), \
14243 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14244 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14245 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14246 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14247 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14248 X(aes, 0x3b00300, N_INV, N_INV), \
14249 X(sha3op, 0x2000c00, N_INV, N_INV), \
14250 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14251 X(sha2op, 0x3ba0380, N_INV, N_INV)
14255 #define X(OPC,I,F,S) N_MNEM_##OPC
14260 static const struct neon_tab_entry neon_enc_tab
[] =
14262 #define X(OPC,I,F,S) { (I), (F), (S) }
14267 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14268 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14269 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14270 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14271 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14272 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14273 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14274 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14275 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14276 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14277 #define NEON_ENC_SINGLE_(X) \
14278 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14279 #define NEON_ENC_DOUBLE_(X) \
14280 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14281 #define NEON_ENC_FPV8_(X) \
14282 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14284 #define NEON_ENCODE(type, inst) \
14287 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14288 inst.is_neon = 1; \
14292 #define check_neon_suffixes \
14295 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14297 as_bad (_("invalid neon suffix for non neon instruction")); \
14303 /* Define shapes for instruction operands. The following mnemonic characters
14304 are used in this table:
14306 F - VFP S<n> register
14307 D - Neon D<n> register
14308 Q - Neon Q<n> register
14312 L - D<n> register list
14314 This table is used to generate various data:
14315 - enumerations of the form NS_DDR to be used as arguments to
14317 - a table classifying shapes into single, double, quad, mixed.
14318 - a table used to drive neon_select_shape. */
14320 #define NEON_SHAPE_DEF \
14321 X(4, (R, R, S, S), QUAD), \
14322 X(4, (S, S, R, R), QUAD), \
14323 X(3, (I, Q, Q), QUAD), \
14324 X(3, (I, Q, R), QUAD), \
14325 X(3, (R, Q, Q), QUAD), \
14326 X(3, (D, D, D), DOUBLE), \
14327 X(3, (Q, Q, Q), QUAD), \
14328 X(3, (D, D, I), DOUBLE), \
14329 X(3, (Q, Q, I), QUAD), \
14330 X(3, (D, D, S), DOUBLE), \
14331 X(3, (Q, Q, S), QUAD), \
14332 X(3, (Q, Q, R), QUAD), \
14333 X(3, (R, R, Q), QUAD), \
14334 X(2, (R, Q), QUAD), \
14335 X(2, (D, D), DOUBLE), \
14336 X(2, (Q, Q), QUAD), \
14337 X(2, (D, S), DOUBLE), \
14338 X(2, (Q, S), QUAD), \
14339 X(2, (D, R), DOUBLE), \
14340 X(2, (Q, R), QUAD), \
14341 X(2, (D, I), DOUBLE), \
14342 X(2, (Q, I), QUAD), \
14343 X(3, (D, L, D), DOUBLE), \
14344 X(2, (D, Q), MIXED), \
14345 X(2, (Q, D), MIXED), \
14346 X(3, (D, Q, I), MIXED), \
14347 X(3, (Q, D, I), MIXED), \
14348 X(3, (Q, D, D), MIXED), \
14349 X(3, (D, Q, Q), MIXED), \
14350 X(3, (Q, Q, D), MIXED), \
14351 X(3, (Q, D, S), MIXED), \
14352 X(3, (D, Q, S), MIXED), \
14353 X(4, (D, D, D, I), DOUBLE), \
14354 X(4, (Q, Q, Q, I), QUAD), \
14355 X(4, (D, D, S, I), DOUBLE), \
14356 X(4, (Q, Q, S, I), QUAD), \
14357 X(2, (F, F), SINGLE), \
14358 X(3, (F, F, F), SINGLE), \
14359 X(2, (F, I), SINGLE), \
14360 X(2, (F, D), MIXED), \
14361 X(2, (D, F), MIXED), \
14362 X(3, (F, F, I), MIXED), \
14363 X(4, (R, R, F, F), SINGLE), \
14364 X(4, (F, F, R, R), SINGLE), \
14365 X(3, (D, R, R), DOUBLE), \
14366 X(3, (R, R, D), DOUBLE), \
14367 X(2, (S, R), SINGLE), \
14368 X(2, (R, S), SINGLE), \
14369 X(2, (F, R), SINGLE), \
14370 X(2, (R, F), SINGLE), \
14371 /* Half float shape supported so far. */\
14372 X (2, (H, D), MIXED), \
14373 X (2, (D, H), MIXED), \
14374 X (2, (H, F), MIXED), \
14375 X (2, (F, H), MIXED), \
14376 X (2, (H, H), HALF), \
14377 X (2, (H, R), HALF), \
14378 X (2, (R, H), HALF), \
14379 X (2, (H, I), HALF), \
14380 X (3, (H, H, H), HALF), \
14381 X (3, (H, F, I), MIXED), \
14382 X (3, (F, H, I), MIXED), \
14383 X (3, (D, H, H), MIXED), \
14384 X (3, (D, H, S), MIXED)
14386 #define S2(A,B) NS_##A##B
14387 #define S3(A,B,C) NS_##A##B##C
14388 #define S4(A,B,C,D) NS_##A##B##C##D
14390 #define X(N, L, C) S##N L
14403 enum neon_shape_class
14412 #define X(N, L, C) SC_##C
14414 static enum neon_shape_class neon_shape_class
[] =
14433 /* Register widths of above. */
14434 static unsigned neon_shape_el_size
[] =
14446 struct neon_shape_info
14449 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14452 #define S2(A,B) { SE_##A, SE_##B }
14453 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14454 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14456 #define X(N, L, C) { N, S##N L }
14458 static struct neon_shape_info neon_shape_tab
[] =
14468 /* Bit masks used in type checking given instructions.
14469 'N_EQK' means the type must be the same as (or based on in some way) the key
14470 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14471 set, various other bits can be set as well in order to modify the meaning of
14472 the type constraint. */
14474 enum neon_type_mask
14498 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14499 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14500 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14501 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14502 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14503 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14504 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14505 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14506 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14507 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14508 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14510 N_MAX_NONSPECIAL
= N_P64
14513 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14515 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14516 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14517 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14518 #define N_S_32 (N_S8 | N_S16 | N_S32)
14519 #define N_F_16_32 (N_F16 | N_F32)
14520 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14521 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14522 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14523 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14524 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14525 #define N_F_MVE (N_F16 | N_F32)
14526 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14528 /* Pass this as the first type argument to neon_check_type to ignore types
14530 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14532 /* Select a "shape" for the current instruction (describing register types or
14533 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14534 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14535 function of operand parsing, so this function doesn't need to be called.
14536 Shapes should be listed in order of decreasing length. */
14538 static enum neon_shape
14539 neon_select_shape (enum neon_shape shape
, ...)
14542 enum neon_shape first_shape
= shape
;
14544 /* Fix missing optional operands. FIXME: we don't know at this point how
14545 many arguments we should have, so this makes the assumption that we have
14546 > 1. This is true of all current Neon opcodes, I think, but may not be
14547 true in the future. */
14548 if (!inst
.operands
[1].present
)
14549 inst
.operands
[1] = inst
.operands
[0];
14551 va_start (ap
, shape
);
14553 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14558 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14560 if (!inst
.operands
[j
].present
)
14566 switch (neon_shape_tab
[shape
].el
[j
])
14568 /* If a .f16, .16, .u16, .s16 type specifier is given over
14569 a VFP single precision register operand, it's essentially
14570 means only half of the register is used.
14572 If the type specifier is given after the mnemonics, the
14573 information is stored in inst.vectype. If the type specifier
14574 is given after register operand, the information is stored
14575 in inst.operands[].vectype.
14577 When there is only one type specifier, and all the register
14578 operands are the same type of hardware register, the type
14579 specifier applies to all register operands.
14581 If no type specifier is given, the shape is inferred from
14582 operand information.
14585 vadd.f16 s0, s1, s2: NS_HHH
14586 vabs.f16 s0, s1: NS_HH
14587 vmov.f16 s0, r1: NS_HR
14588 vmov.f16 r0, s1: NS_RH
14589 vcvt.f16 r0, s1: NS_RH
14590 vcvt.f16.s32 s2, s2, #29: NS_HFI
14591 vcvt.f16.s32 s2, s2: NS_HF
14594 if (!(inst
.operands
[j
].isreg
14595 && inst
.operands
[j
].isvec
14596 && inst
.operands
[j
].issingle
14597 && !inst
.operands
[j
].isquad
14598 && ((inst
.vectype
.elems
== 1
14599 && inst
.vectype
.el
[0].size
== 16)
14600 || (inst
.vectype
.elems
> 1
14601 && inst
.vectype
.el
[j
].size
== 16)
14602 || (inst
.vectype
.elems
== 0
14603 && inst
.operands
[j
].vectype
.type
!= NT_invtype
14604 && inst
.operands
[j
].vectype
.size
== 16))))
14609 if (!(inst
.operands
[j
].isreg
14610 && inst
.operands
[j
].isvec
14611 && inst
.operands
[j
].issingle
14612 && !inst
.operands
[j
].isquad
14613 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
14614 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
14615 || (inst
.vectype
.elems
== 0
14616 && (inst
.operands
[j
].vectype
.size
== 32
14617 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
14622 if (!(inst
.operands
[j
].isreg
14623 && inst
.operands
[j
].isvec
14624 && !inst
.operands
[j
].isquad
14625 && !inst
.operands
[j
].issingle
))
14630 if (!(inst
.operands
[j
].isreg
14631 && !inst
.operands
[j
].isvec
))
14636 if (!(inst
.operands
[j
].isreg
14637 && inst
.operands
[j
].isvec
14638 && inst
.operands
[j
].isquad
14639 && !inst
.operands
[j
].issingle
))
14644 if (!(!inst
.operands
[j
].isreg
14645 && !inst
.operands
[j
].isscalar
))
14650 if (!(!inst
.operands
[j
].isreg
14651 && inst
.operands
[j
].isscalar
))
14661 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
14662 /* We've matched all the entries in the shape table, and we don't
14663 have any left over operands which have not been matched. */
14669 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
14670 first_error (_("invalid instruction shape"));
14675 /* True if SHAPE is predominantly a quadword operation (most of the time, this
14676 means the Q bit should be set). */
14679 neon_quad (enum neon_shape shape
)
14681 return neon_shape_class
[shape
] == SC_QUAD
;
14685 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
14688 /* Allow modification to be made to types which are constrained to be
14689 based on the key element, based on bits set alongside N_EQK. */
14690 if ((typebits
& N_EQK
) != 0)
14692 if ((typebits
& N_HLF
) != 0)
14694 else if ((typebits
& N_DBL
) != 0)
14696 if ((typebits
& N_SGN
) != 0)
14697 *g_type
= NT_signed
;
14698 else if ((typebits
& N_UNS
) != 0)
14699 *g_type
= NT_unsigned
;
14700 else if ((typebits
& N_INT
) != 0)
14701 *g_type
= NT_integer
;
14702 else if ((typebits
& N_FLT
) != 0)
14703 *g_type
= NT_float
;
14704 else if ((typebits
& N_SIZ
) != 0)
14705 *g_type
= NT_untyped
;
14709 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
14710 operand type, i.e. the single type specified in a Neon instruction when it
14711 is the only one given. */
14713 static struct neon_type_el
14714 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
14716 struct neon_type_el dest
= *key
;
14718 gas_assert ((thisarg
& N_EQK
) != 0);
14720 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
14725 /* Convert Neon type and size into compact bitmask representation. */
14727 static enum neon_type_mask
14728 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
14735 case 8: return N_8
;
14736 case 16: return N_16
;
14737 case 32: return N_32
;
14738 case 64: return N_64
;
14746 case 8: return N_I8
;
14747 case 16: return N_I16
;
14748 case 32: return N_I32
;
14749 case 64: return N_I64
;
14757 case 16: return N_F16
;
14758 case 32: return N_F32
;
14759 case 64: return N_F64
;
14767 case 8: return N_P8
;
14768 case 16: return N_P16
;
14769 case 64: return N_P64
;
14777 case 8: return N_S8
;
14778 case 16: return N_S16
;
14779 case 32: return N_S32
;
14780 case 64: return N_S64
;
14788 case 8: return N_U8
;
14789 case 16: return N_U16
;
14790 case 32: return N_U32
;
14791 case 64: return N_U64
;
14802 /* Convert compact Neon bitmask type representation to a type and size. Only
14803 handles the case where a single bit is set in the mask. */
14806 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
14807 enum neon_type_mask mask
)
14809 if ((mask
& N_EQK
) != 0)
14812 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
14814 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
14816 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
14818 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
14823 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
14825 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
14826 *type
= NT_unsigned
;
14827 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
14828 *type
= NT_integer
;
14829 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
14830 *type
= NT_untyped
;
14831 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
14833 else if ((mask
& (N_F_ALL
)) != 0)
14841 /* Modify a bitmask of allowed types. This is only needed for type
14845 modify_types_allowed (unsigned allowed
, unsigned mods
)
14848 enum neon_el_type type
;
14854 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
14856 if (el_type_of_type_chk (&type
, &size
,
14857 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
14859 neon_modify_type_size (mods
, &type
, &size
);
14860 destmask
|= type_chk_of_el_type (type
, size
);
14867 /* Check type and return type classification.
14868 The manual states (paraphrase): If one datatype is given, it indicates the
14870 - the second operand, if there is one
14871 - the operand, if there is no second operand
14872 - the result, if there are no operands.
14873 This isn't quite good enough though, so we use a concept of a "key" datatype
14874 which is set on a per-instruction basis, which is the one which matters when
14875 only one data type is written.
14876 Note: this function has side-effects (e.g. filling in missing operands). All
14877 Neon instructions should call it before performing bit encoding. */
14879 static struct neon_type_el
14880 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
14883 unsigned i
, pass
, key_el
= 0;
14884 unsigned types
[NEON_MAX_TYPE_ELS
];
14885 enum neon_el_type k_type
= NT_invtype
;
14886 unsigned k_size
= -1u;
14887 struct neon_type_el badtype
= {NT_invtype
, -1};
14888 unsigned key_allowed
= 0;
14890 /* Optional registers in Neon instructions are always (not) in operand 1.
14891 Fill in the missing operand here, if it was omitted. */
14892 if (els
> 1 && !inst
.operands
[1].present
)
14893 inst
.operands
[1] = inst
.operands
[0];
14895 /* Suck up all the varargs. */
14897 for (i
= 0; i
< els
; i
++)
14899 unsigned thisarg
= va_arg (ap
, unsigned);
14900 if (thisarg
== N_IGNORE_TYPE
)
14905 types
[i
] = thisarg
;
14906 if ((thisarg
& N_KEY
) != 0)
14911 if (inst
.vectype
.elems
> 0)
14912 for (i
= 0; i
< els
; i
++)
14913 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
14915 first_error (_("types specified in both the mnemonic and operands"));
14919 /* Duplicate inst.vectype elements here as necessary.
14920 FIXME: No idea if this is exactly the same as the ARM assembler,
14921 particularly when an insn takes one register and one non-register
14923 if (inst
.vectype
.elems
== 1 && els
> 1)
14926 inst
.vectype
.elems
= els
;
14927 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
14928 for (j
= 0; j
< els
; j
++)
14930 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14933 else if (inst
.vectype
.elems
== 0 && els
> 0)
14936 /* No types were given after the mnemonic, so look for types specified
14937 after each operand. We allow some flexibility here; as long as the
14938 "key" operand has a type, we can infer the others. */
14939 for (j
= 0; j
< els
; j
++)
14940 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
14941 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
14943 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
14945 for (j
= 0; j
< els
; j
++)
14946 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
14947 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14952 first_error (_("operand types can't be inferred"));
14956 else if (inst
.vectype
.elems
!= els
)
14958 first_error (_("type specifier has the wrong number of parts"));
14962 for (pass
= 0; pass
< 2; pass
++)
14964 for (i
= 0; i
< els
; i
++)
14966 unsigned thisarg
= types
[i
];
14967 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
14968 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
14969 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
14970 unsigned g_size
= inst
.vectype
.el
[i
].size
;
14972 /* Decay more-specific signed & unsigned types to sign-insensitive
14973 integer types if sign-specific variants are unavailable. */
14974 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
14975 && (types_allowed
& N_SU_ALL
) == 0)
14976 g_type
= NT_integer
;
14978 /* If only untyped args are allowed, decay any more specific types to
14979 them. Some instructions only care about signs for some element
14980 sizes, so handle that properly. */
14981 if (((types_allowed
& N_UNT
) == 0)
14982 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14983 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14984 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
14985 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
14986 g_type
= NT_untyped
;
14990 if ((thisarg
& N_KEY
) != 0)
14994 key_allowed
= thisarg
& ~N_KEY
;
14996 /* Check architecture constraint on FP16 extension. */
14998 && k_type
== NT_float
14999 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15001 inst
.error
= _(BAD_FP16
);
15008 if ((thisarg
& N_VFP
) != 0)
15010 enum neon_shape_el regshape
;
15011 unsigned regwidth
, match
;
15013 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15016 first_error (_("invalid instruction shape"));
15019 regshape
= neon_shape_tab
[ns
].el
[i
];
15020 regwidth
= neon_shape_el_size
[regshape
];
15022 /* In VFP mode, operands must match register widths. If we
15023 have a key operand, use its width, else use the width of
15024 the current operand. */
15030 /* FP16 will use a single precision register. */
15031 if (regwidth
== 32 && match
== 16)
15033 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15037 inst
.error
= _(BAD_FP16
);
15042 if (regwidth
!= match
)
15044 first_error (_("operand size must match register width"));
15049 if ((thisarg
& N_EQK
) == 0)
15051 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15053 if ((given_type
& types_allowed
) == 0)
15055 first_error (BAD_SIMD_TYPE
);
15061 enum neon_el_type mod_k_type
= k_type
;
15062 unsigned mod_k_size
= k_size
;
15063 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15064 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15066 first_error (_("inconsistent types in Neon instruction"));
15074 return inst
.vectype
.el
[key_el
];
15077 /* Neon-style VFP instruction forwarding. */
15079 /* Thumb VFP instructions have 0xE in the condition field. */
15082 do_vfp_cond_or_thumb (void)
15087 inst
.instruction
|= 0xe0000000;
15089 inst
.instruction
|= inst
.cond
<< 28;
15092 /* Look up and encode a simple mnemonic, for use as a helper function for the
15093 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15094 etc. It is assumed that operand parsing has already been done, and that the
15095 operands are in the form expected by the given opcode (this isn't necessarily
15096 the same as the form in which they were parsed, hence some massaging must
15097 take place before this function is called).
15098 Checks current arch version against that in the looked-up opcode. */
15101 do_vfp_nsyn_opcode (const char *opname
)
15103 const struct asm_opcode
*opcode
;
15105 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15110 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15111 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15118 inst
.instruction
= opcode
->tvalue
;
15119 opcode
->tencode ();
15123 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15124 opcode
->aencode ();
15129 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15131 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15133 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15136 do_vfp_nsyn_opcode ("fadds");
15138 do_vfp_nsyn_opcode ("fsubs");
15140 /* ARMv8.2 fp16 instruction. */
15142 do_scalar_fp16_v82_encode ();
15147 do_vfp_nsyn_opcode ("faddd");
15149 do_vfp_nsyn_opcode ("fsubd");
15153 /* Check operand types to see if this is a VFP instruction, and if so call
15157 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15159 enum neon_shape rs
;
15160 struct neon_type_el et
;
15165 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15166 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15170 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15171 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15172 N_F_ALL
| N_KEY
| N_VFP
);
15179 if (et
.type
!= NT_invtype
)
15190 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15192 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15194 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15197 do_vfp_nsyn_opcode ("fmacs");
15199 do_vfp_nsyn_opcode ("fnmacs");
15201 /* ARMv8.2 fp16 instruction. */
15203 do_scalar_fp16_v82_encode ();
15208 do_vfp_nsyn_opcode ("fmacd");
15210 do_vfp_nsyn_opcode ("fnmacd");
15215 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15217 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15219 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15222 do_vfp_nsyn_opcode ("ffmas");
15224 do_vfp_nsyn_opcode ("ffnmas");
15226 /* ARMv8.2 fp16 instruction. */
15228 do_scalar_fp16_v82_encode ();
15233 do_vfp_nsyn_opcode ("ffmad");
15235 do_vfp_nsyn_opcode ("ffnmad");
15240 do_vfp_nsyn_mul (enum neon_shape rs
)
15242 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15244 do_vfp_nsyn_opcode ("fmuls");
15246 /* ARMv8.2 fp16 instruction. */
15248 do_scalar_fp16_v82_encode ();
15251 do_vfp_nsyn_opcode ("fmuld");
15255 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15257 int is_neg
= (inst
.instruction
& 0x80) != 0;
15258 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15260 if (rs
== NS_FF
|| rs
== NS_HH
)
15263 do_vfp_nsyn_opcode ("fnegs");
15265 do_vfp_nsyn_opcode ("fabss");
15267 /* ARMv8.2 fp16 instruction. */
15269 do_scalar_fp16_v82_encode ();
15274 do_vfp_nsyn_opcode ("fnegd");
15276 do_vfp_nsyn_opcode ("fabsd");
15280 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15281 insns belong to Neon, and are handled elsewhere. */
15284 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15286 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15290 do_vfp_nsyn_opcode ("fldmdbs");
15292 do_vfp_nsyn_opcode ("fldmias");
15297 do_vfp_nsyn_opcode ("fstmdbs");
15299 do_vfp_nsyn_opcode ("fstmias");
15304 do_vfp_nsyn_sqrt (void)
15306 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15307 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15309 if (rs
== NS_FF
|| rs
== NS_HH
)
15311 do_vfp_nsyn_opcode ("fsqrts");
15313 /* ARMv8.2 fp16 instruction. */
15315 do_scalar_fp16_v82_encode ();
15318 do_vfp_nsyn_opcode ("fsqrtd");
15322 do_vfp_nsyn_div (void)
15324 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15325 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15326 N_F_ALL
| N_KEY
| N_VFP
);
15328 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15330 do_vfp_nsyn_opcode ("fdivs");
15332 /* ARMv8.2 fp16 instruction. */
15334 do_scalar_fp16_v82_encode ();
15337 do_vfp_nsyn_opcode ("fdivd");
15341 do_vfp_nsyn_nmul (void)
15343 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15344 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15345 N_F_ALL
| N_KEY
| N_VFP
);
15347 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15349 NEON_ENCODE (SINGLE
, inst
);
15350 do_vfp_sp_dyadic ();
15352 /* ARMv8.2 fp16 instruction. */
15354 do_scalar_fp16_v82_encode ();
15358 NEON_ENCODE (DOUBLE
, inst
);
15359 do_vfp_dp_rd_rn_rm ();
15361 do_vfp_cond_or_thumb ();
15365 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15369 neon_logbits (unsigned x
)
15371 return ffs (x
) - 4;
15374 #define LOW4(R) ((R) & 0xf)
15375 #define HI1(R) (((R) >> 4) & 1)
15378 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15383 first_error (BAD_EL_TYPE
);
15386 switch (inst
.operands
[0].imm
)
15389 first_error (_("invalid condition"));
15411 /* only accept eq and ne. */
15412 if (inst
.operands
[0].imm
> 1)
15414 first_error (_("invalid condition"));
15417 return inst
.operands
[0].imm
;
15419 if (inst
.operands
[0].imm
== 0x2)
15421 else if (inst
.operands
[0].imm
== 0x8)
15425 first_error (_("invalid condition"));
15429 switch (inst
.operands
[0].imm
)
15432 first_error (_("invalid condition"));
15448 /* Should be unreachable. */
15455 /* We are dealing with a vector predicated block. */
15456 if (inst
.operands
[0].present
)
15458 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15459 struct neon_type_el et
15460 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15463 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15465 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15467 if (et
.type
== NT_invtype
)
15470 if (et
.type
== NT_float
)
15472 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15474 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
15475 inst
.instruction
|= (et
.size
== 16) << 28;
15476 inst
.instruction
|= 0x3 << 20;
15480 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
15482 inst
.instruction
|= 1 << 28;
15483 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15486 if (inst
.operands
[2].isquad
)
15488 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15489 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15490 inst
.instruction
|= (fcond
& 0x2) >> 1;
15494 if (inst
.operands
[2].reg
== REG_SP
)
15495 as_tsktsk (MVE_BAD_SP
);
15496 inst
.instruction
|= 1 << 6;
15497 inst
.instruction
|= (fcond
& 0x2) << 4;
15498 inst
.instruction
|= inst
.operands
[2].reg
;
15500 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15501 inst
.instruction
|= (fcond
& 0x4) << 10;
15502 inst
.instruction
|= (fcond
& 0x1) << 7;
15505 set_pred_insn_type (VPT_INSN
);
15507 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
15508 | ((inst
.instruction
& 0xe000) >> 13);
15509 now_pred
.warn_deprecated
= FALSE
;
15510 now_pred
.type
= VECTOR_PRED
;
15517 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
15518 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
15519 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
15520 if (!inst
.operands
[2].present
)
15521 first_error (_("MVE vector or ARM register expected"));
15522 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15524 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15525 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
15526 && inst
.operands
[1].isquad
)
15528 inst
.instruction
= N_MNEM_vcmp
;
15532 if (inst
.cond
> COND_ALWAYS
)
15533 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15535 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15537 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15538 struct neon_type_el et
15539 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15542 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
15543 && !inst
.operands
[2].iszr
, BAD_PC
);
15545 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15547 inst
.instruction
= 0xee010f00;
15548 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15549 inst
.instruction
|= (fcond
& 0x4) << 10;
15550 inst
.instruction
|= (fcond
& 0x1) << 7;
15551 if (et
.type
== NT_float
)
15553 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15555 inst
.instruction
|= (et
.size
== 16) << 28;
15556 inst
.instruction
|= 0x3 << 20;
15560 inst
.instruction
|= 1 << 28;
15561 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15563 if (inst
.operands
[2].isquad
)
15565 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15566 inst
.instruction
|= (fcond
& 0x2) >> 1;
15567 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15571 if (inst
.operands
[2].reg
== REG_SP
)
15572 as_tsktsk (MVE_BAD_SP
);
15573 inst
.instruction
|= 1 << 6;
15574 inst
.instruction
|= (fcond
& 0x2) << 4;
15575 inst
.instruction
|= inst
.operands
[2].reg
;
15583 do_mve_vcmul (void)
15585 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
15586 struct neon_type_el et
15587 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
15589 if (inst
.cond
> COND_ALWAYS
)
15590 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15592 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15594 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
15595 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
15596 _("immediate out of range"));
15598 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
15599 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
15600 as_tsktsk (BAD_MVE_SRCDEST
);
15602 inst
.instruction
|= (et
.size
== 32) << 28;
15603 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15604 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15605 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15606 inst
.instruction
|= (rot
> 90) << 12;
15607 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15608 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15609 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15610 inst
.instruction
|= (rot
== 90 || rot
== 270);
15615 do_vfp_nsyn_cmp (void)
15617 enum neon_shape rs
;
15618 if (!inst
.operands
[0].isreg
)
15625 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
15626 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
15630 if (inst
.operands
[1].isreg
)
15632 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15633 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15635 if (rs
== NS_FF
|| rs
== NS_HH
)
15637 NEON_ENCODE (SINGLE
, inst
);
15638 do_vfp_sp_monadic ();
15642 NEON_ENCODE (DOUBLE
, inst
);
15643 do_vfp_dp_rd_rm ();
15648 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
15649 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
15651 switch (inst
.instruction
& 0x0fffffff)
15654 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
15657 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
15663 if (rs
== NS_FI
|| rs
== NS_HI
)
15665 NEON_ENCODE (SINGLE
, inst
);
15666 do_vfp_sp_compare_z ();
15670 NEON_ENCODE (DOUBLE
, inst
);
15674 do_vfp_cond_or_thumb ();
15676 /* ARMv8.2 fp16 instruction. */
15677 if (rs
== NS_HI
|| rs
== NS_HH
)
15678 do_scalar_fp16_v82_encode ();
15682 nsyn_insert_sp (void)
15684 inst
.operands
[1] = inst
.operands
[0];
15685 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
15686 inst
.operands
[0].reg
= REG_SP
;
15687 inst
.operands
[0].isreg
= 1;
15688 inst
.operands
[0].writeback
= 1;
15689 inst
.operands
[0].present
= 1;
15693 do_vfp_nsyn_push (void)
15697 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15698 _("register list must contain at least 1 and at most 16 "
15701 if (inst
.operands
[1].issingle
)
15702 do_vfp_nsyn_opcode ("fstmdbs");
15704 do_vfp_nsyn_opcode ("fstmdbd");
15708 do_vfp_nsyn_pop (void)
15712 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15713 _("register list must contain at least 1 and at most 16 "
15716 if (inst
.operands
[1].issingle
)
15717 do_vfp_nsyn_opcode ("fldmias");
15719 do_vfp_nsyn_opcode ("fldmiad");
15722 /* Fix up Neon data-processing instructions, ORing in the correct bits for
15723 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
15726 neon_dp_fixup (struct arm_it
* insn
)
15728 unsigned int i
= insn
->instruction
;
15733 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
15744 insn
->instruction
= i
;
15748 mve_encode_qqr (int size
, int fp
)
15750 if (inst
.operands
[2].reg
== REG_SP
)
15751 as_tsktsk (MVE_BAD_SP
);
15752 else if (inst
.operands
[2].reg
== REG_PC
)
15753 as_tsktsk (MVE_BAD_PC
);
15758 if (((unsigned)inst
.instruction
) == 0xd00)
15759 inst
.instruction
= 0xee300f40;
15761 else if (((unsigned)inst
.instruction
) == 0x200d00)
15762 inst
.instruction
= 0xee301f40;
15764 /* Setting size which is 1 for F16 and 0 for F32. */
15765 inst
.instruction
|= (size
== 16) << 28;
15770 if (((unsigned)inst
.instruction
) == 0x800)
15771 inst
.instruction
= 0xee010f40;
15773 else if (((unsigned)inst
.instruction
) == 0x1000800)
15774 inst
.instruction
= 0xee011f40;
15775 /* Setting bits for size. */
15776 inst
.instruction
|= neon_logbits (size
) << 20;
15778 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15779 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15780 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15781 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15782 inst
.instruction
|= inst
.operands
[2].reg
;
15787 mve_encode_rqq (unsigned bit28
, unsigned size
)
15789 inst
.instruction
|= bit28
<< 28;
15790 inst
.instruction
|= neon_logbits (size
) << 20;
15791 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15792 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15793 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15794 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15795 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15800 mve_encode_qqq (int ubit
, int size
)
15803 inst
.instruction
|= (ubit
!= 0) << 28;
15804 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15805 inst
.instruction
|= neon_logbits (size
) << 20;
15806 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15807 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15808 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15809 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15810 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15816 mve_encode_rq (unsigned bit28
, unsigned size
)
15818 inst
.instruction
|= bit28
<< 28;
15819 inst
.instruction
|= neon_logbits (size
) << 18;
15820 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15821 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15825 /* Encode insns with bit pattern:
15827 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15828 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
15830 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
15831 different meaning for some instruction. */
15834 neon_three_same (int isquad
, int ubit
, int size
)
15836 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15837 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15838 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15839 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15840 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15841 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15842 inst
.instruction
|= (isquad
!= 0) << 6;
15843 inst
.instruction
|= (ubit
!= 0) << 24;
15845 inst
.instruction
|= neon_logbits (size
) << 20;
15847 neon_dp_fixup (&inst
);
15850 /* Encode instructions of the form:
15852 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
15853 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
15855 Don't write size if SIZE == -1. */
15858 neon_two_same (int qbit
, int ubit
, int size
)
15860 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15861 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15862 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15863 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15864 inst
.instruction
|= (qbit
!= 0) << 6;
15865 inst
.instruction
|= (ubit
!= 0) << 24;
15868 inst
.instruction
|= neon_logbits (size
) << 18;
15870 neon_dp_fixup (&inst
);
15873 /* Neon instruction encoders, in approximate order of appearance. */
15876 do_neon_dyadic_i_su (void)
15878 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15879 struct neon_type_el et
= neon_check_type (3, rs
,
15880 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
15881 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15885 do_neon_dyadic_i64_su (void)
15887 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15888 struct neon_type_el et
= neon_check_type (3, rs
,
15889 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
15890 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15894 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
15897 unsigned size
= et
.size
>> 3;
15898 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15899 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15900 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15901 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15902 inst
.instruction
|= (isquad
!= 0) << 6;
15903 inst
.instruction
|= immbits
<< 16;
15904 inst
.instruction
|= (size
>> 3) << 7;
15905 inst
.instruction
|= (size
& 0x7) << 19;
15907 inst
.instruction
|= (uval
!= 0) << 24;
15909 neon_dp_fixup (&inst
);
15913 do_neon_shl_imm (void)
15915 if (!inst
.operands
[2].isreg
)
15917 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15918 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
15919 int imm
= inst
.operands
[2].imm
;
15921 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15922 _("immediate out of range for shift"));
15923 NEON_ENCODE (IMMED
, inst
);
15924 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15928 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15929 struct neon_type_el et
= neon_check_type (3, rs
,
15930 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
15933 /* VSHL/VQSHL 3-register variants have syntax such as:
15935 whereas other 3-register operations encoded by neon_three_same have
15938 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
15940 tmp
= inst
.operands
[2].reg
;
15941 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
15942 inst
.operands
[1].reg
= tmp
;
15943 NEON_ENCODE (INTEGER
, inst
);
15944 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15949 do_neon_qshl_imm (void)
15951 if (!inst
.operands
[2].isreg
)
15953 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15954 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
15955 int imm
= inst
.operands
[2].imm
;
15957 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15958 _("immediate out of range for shift"));
15959 NEON_ENCODE (IMMED
, inst
);
15960 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
15964 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15965 struct neon_type_el et
= neon_check_type (3, rs
,
15966 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
15969 /* See note in do_neon_shl_imm. */
15970 tmp
= inst
.operands
[2].reg
;
15971 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
15972 inst
.operands
[1].reg
= tmp
;
15973 NEON_ENCODE (INTEGER
, inst
);
15974 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15979 do_neon_rshl (void)
15981 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15982 struct neon_type_el et
= neon_check_type (3, rs
,
15983 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
15986 tmp
= inst
.operands
[2].reg
;
15987 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
15988 inst
.operands
[1].reg
= tmp
;
15989 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
15993 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
15995 /* Handle .I8 pseudo-instructions. */
15998 /* Unfortunately, this will make everything apart from zero out-of-range.
15999 FIXME is this the intended semantics? There doesn't seem much point in
16000 accepting .I8 if so. */
16001 immediate
|= immediate
<< 8;
16007 if (immediate
== (immediate
& 0x000000ff))
16009 *immbits
= immediate
;
16012 else if (immediate
== (immediate
& 0x0000ff00))
16014 *immbits
= immediate
>> 8;
16017 else if (immediate
== (immediate
& 0x00ff0000))
16019 *immbits
= immediate
>> 16;
16022 else if (immediate
== (immediate
& 0xff000000))
16024 *immbits
= immediate
>> 24;
16027 if ((immediate
& 0xffff) != (immediate
>> 16))
16028 goto bad_immediate
;
16029 immediate
&= 0xffff;
16032 if (immediate
== (immediate
& 0x000000ff))
16034 *immbits
= immediate
;
16037 else if (immediate
== (immediate
& 0x0000ff00))
16039 *immbits
= immediate
>> 8;
16044 first_error (_("immediate value out of range"));
16048 enum vfp_or_neon_is_neon_bits
16051 NEON_CHECK_ARCH
= 2,
16052 NEON_CHECK_ARCH8
= 4
16055 /* Call this function if an instruction which may have belonged to the VFP or
16056 Neon instruction sets, but turned out to be a Neon instruction (due to the
16057 operand types involved, etc.). We have to check and/or fix-up a couple of
16060 - Make sure the user hasn't attempted to make a Neon instruction
16062 - Alter the value in the condition code field if necessary.
16063 - Make sure that the arch supports Neon instructions.
16065 Which of these operations take place depends on bits from enum
16066 vfp_or_neon_is_neon_bits.
16068 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16069 current instruction's condition is COND_ALWAYS, the condition field is
16070 changed to inst.uncond_value. This is necessary because instructions shared
16071 between VFP and Neon may be conditional for the VFP variants only, and the
16072 unconditional Neon version must have, e.g., 0xF in the condition field. */
16075 vfp_or_neon_is_neon (unsigned check
)
16077 /* Conditions are always legal in Thumb mode (IT blocks). */
16078 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16080 if (inst
.cond
!= COND_ALWAYS
)
16082 first_error (_(BAD_COND
));
16085 if (inst
.uncond_value
!= -1)
16086 inst
.instruction
|= inst
.uncond_value
<< 28;
16090 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16091 || ((check
& NEON_CHECK_ARCH8
)
16092 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16094 first_error (_(BAD_FPU
));
16102 check_simd_pred_availability (int fp
, unsigned check
)
16104 if (inst
.cond
> COND_ALWAYS
)
16106 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16108 inst
.error
= BAD_FPU
;
16111 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16113 else if (inst
.cond
< COND_ALWAYS
)
16115 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16116 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16117 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16122 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16123 && vfp_or_neon_is_neon (check
) == FAIL
)
16126 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16127 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16133 do_neon_logic (void)
16135 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
16137 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16139 && check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
)
16142 else if (rs
!= NS_QQQ
16143 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
16144 first_error (BAD_FPU
);
16146 neon_check_type (3, rs
, N_IGNORE_TYPE
);
16147 /* U bit and size field were set as part of the bitmask. */
16148 NEON_ENCODE (INTEGER
, inst
);
16149 neon_three_same (neon_quad (rs
), 0, -1);
16153 const int three_ops_form
= (inst
.operands
[2].present
16154 && !inst
.operands
[2].isreg
);
16155 const int immoperand
= (three_ops_form
? 2 : 1);
16156 enum neon_shape rs
= (three_ops_form
16157 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
16158 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
16159 /* Because neon_select_shape makes the second operand a copy of the first
16160 if the second operand is not present. */
16162 && check_simd_pred_availability (0, NEON_CHECK_ARCH
| NEON_CHECK_CC
)
16165 else if (rs
!= NS_QQI
16166 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
16167 first_error (BAD_FPU
);
16169 struct neon_type_el et
;
16170 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16171 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
16173 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
16176 if (et
.type
== NT_invtype
)
16178 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
16183 if (three_ops_form
)
16184 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16185 _("first and second operands shall be the same register"));
16187 NEON_ENCODE (IMMED
, inst
);
16189 immbits
= inst
.operands
[immoperand
].imm
;
16192 /* .i64 is a pseudo-op, so the immediate must be a repeating
16194 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
16195 inst
.operands
[immoperand
].reg
: 0))
16197 /* Set immbits to an invalid constant. */
16198 immbits
= 0xdeadbeef;
16205 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16209 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16213 /* Pseudo-instruction for VBIC. */
16214 neon_invert_size (&immbits
, 0, et
.size
);
16215 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16219 /* Pseudo-instruction for VORR. */
16220 neon_invert_size (&immbits
, 0, et
.size
);
16221 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16231 inst
.instruction
|= neon_quad (rs
) << 6;
16232 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16233 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16234 inst
.instruction
|= cmode
<< 8;
16235 neon_write_immbits (immbits
);
16237 neon_dp_fixup (&inst
);
16242 do_neon_bitfield (void)
16244 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16245 neon_check_type (3, rs
, N_IGNORE_TYPE
);
16246 neon_three_same (neon_quad (rs
), 0, -1);
16250 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
16253 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16254 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
16256 if (et
.type
== NT_float
)
16258 NEON_ENCODE (FLOAT
, inst
);
16260 mve_encode_qqr (et
.size
, 1);
16262 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
16266 NEON_ENCODE (INTEGER
, inst
);
16268 mve_encode_qqr (et
.size
, 0);
16270 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
16276 do_neon_dyadic_if_su_d (void)
16278 /* This version only allow D registers, but that constraint is enforced during
16279 operand parsing so we don't need to do anything extra here. */
16280 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
16284 do_neon_dyadic_if_i_d (void)
16286 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16287 affected if we specify unsigned args. */
16288 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
16292 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
16294 constraint (size
< 32, BAD_ADDR_MODE
);
16295 constraint (size
!= elsize
, BAD_EL_TYPE
);
16296 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16297 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
16298 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
16299 _("destination register and offset register may not be the"
16302 int imm
= inst
.relocs
[0].exp
.X_add_number
;
16309 constraint ((imm
% (size
/ 8) != 0)
16310 || imm
> (0x7f << neon_logbits (size
)),
16311 (size
== 32) ? _("immediate must be a multiple of 4 in the"
16312 " range of +/-[0,508]")
16313 : _("immediate must be a multiple of 8 in the"
16314 " range of +/-[0,1016]"));
16315 inst
.instruction
|= 0x11 << 24;
16316 inst
.instruction
|= add
<< 23;
16317 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16318 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16319 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16320 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16321 inst
.instruction
|= 1 << 12;
16322 inst
.instruction
|= (size
== 64) << 8;
16323 inst
.instruction
&= 0xffffff00;
16324 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16325 inst
.instruction
|= imm
>> neon_logbits (size
);
16329 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
16331 unsigned os
= inst
.operands
[1].imm
>> 5;
16332 constraint (os
!= 0 && size
== 8,
16333 _("can not shift offsets when accessing less than half-word"));
16334 constraint (os
&& os
!= neon_logbits (size
),
16335 _("shift immediate must be 1, 2 or 3 for half-word, word"
16336 " or double-word accesses respectively"));
16337 if (inst
.operands
[1].reg
== REG_PC
)
16338 as_tsktsk (MVE_BAD_PC
);
16343 constraint (elsize
>= 64, BAD_EL_TYPE
);
16346 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
16350 constraint (elsize
!= size
, BAD_EL_TYPE
);
16355 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
16359 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
16360 _("destination register and offset register may not be"
16362 constraint (size
== elsize
&& inst
.vectype
.el
[0].type
!= NT_unsigned
,
16364 constraint (inst
.vectype
.el
[0].type
!= NT_unsigned
16365 && inst
.vectype
.el
[0].type
!= NT_signed
, BAD_EL_TYPE
);
16366 inst
.instruction
|= (inst
.vectype
.el
[0].type
== NT_unsigned
) << 28;
16370 constraint (inst
.vectype
.el
[0].type
!= NT_untyped
, BAD_EL_TYPE
);
16373 inst
.instruction
|= 1 << 23;
16374 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16375 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16376 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16377 inst
.instruction
|= neon_logbits (elsize
) << 7;
16378 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
16379 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
16380 inst
.instruction
|= !!os
;
16384 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
16386 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
16388 constraint (size
>= 64, BAD_ADDR_MODE
);
16392 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
16395 constraint (elsize
!= size
, BAD_EL_TYPE
);
16402 constraint (elsize
!= size
&& type
!= NT_unsigned
16403 && type
!= NT_signed
, BAD_EL_TYPE
);
16407 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
16410 int imm
= inst
.relocs
[0].exp
.X_add_number
;
16418 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
16423 constraint (1, _("immediate must be in the range of +/-[0,127]"));
16426 constraint (1, _("immediate must be a multiple of 2 in the"
16427 " range of +/-[0,254]"));
16430 constraint (1, _("immediate must be a multiple of 4 in the"
16431 " range of +/-[0,508]"));
16436 if (size
!= elsize
)
16438 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
16439 constraint (inst
.operands
[0].reg
> 14,
16440 _("MVE vector register in the range [Q0..Q7] expected"));
16441 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
16442 inst
.instruction
|= (size
== 16) << 19;
16443 inst
.instruction
|= neon_logbits (elsize
) << 7;
16447 if (inst
.operands
[1].reg
== REG_PC
)
16448 as_tsktsk (MVE_BAD_PC
);
16449 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
16450 as_tsktsk (MVE_BAD_SP
);
16451 inst
.instruction
|= 1 << 12;
16452 inst
.instruction
|= neon_logbits (size
) << 7;
16454 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
16455 inst
.instruction
|= add
<< 23;
16456 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16457 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16458 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16459 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16460 inst
.instruction
&= 0xffffff80;
16461 inst
.instruction
|= imm
>> neon_logbits (size
);
16466 do_mve_vstr_vldr (void)
16471 if (inst
.cond
> COND_ALWAYS
)
16472 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16474 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16476 switch (inst
.instruction
)
16483 /* fall through. */
16489 /* fall through. */
16495 /* fall through. */
16501 /* fall through. */
16506 unsigned elsize
= inst
.vectype
.el
[0].size
;
16508 if (inst
.operands
[1].isquad
)
16510 /* We are dealing with [Q, imm]{!} cases. */
16511 do_mve_vstr_vldr_QI (size
, elsize
, load
);
16515 if (inst
.operands
[1].immisreg
== 2)
16517 /* We are dealing with [R, Q, {UXTW #os}] cases. */
16518 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
16520 else if (!inst
.operands
[1].immisreg
)
16522 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
16523 do_mve_vstr_vldr_RI (size
, elsize
, load
);
16526 constraint (1, BAD_ADDR_MODE
);
16533 do_mve_vst_vld (void)
16535 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16538 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
16539 || inst
.relocs
[0].exp
.X_add_number
!= 0
16540 || inst
.operands
[1].immisreg
!= 0,
16542 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
16543 if (inst
.operands
[1].reg
== REG_PC
)
16544 as_tsktsk (MVE_BAD_PC
);
16545 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
16546 as_tsktsk (MVE_BAD_SP
);
16549 /* These instructions are one of the "exceptions" mentioned in
16550 handle_pred_state. They are MVE instructions that are not VPT compatible
16551 and do not accept a VPT code, thus appending such a code is a syntax
16553 if (inst
.cond
> COND_ALWAYS
)
16554 first_error (BAD_SYNTAX
);
16555 /* If we append a scalar condition code we can set this to
16556 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
16557 else if (inst
.cond
< COND_ALWAYS
)
16558 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16560 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
16562 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16563 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16564 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16565 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16566 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
16571 do_mve_vaddlv (void)
16573 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
16574 struct neon_type_el et
16575 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
16577 if (et
.type
== NT_invtype
)
16578 first_error (BAD_EL_TYPE
);
16580 if (inst
.cond
> COND_ALWAYS
)
16581 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16583 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16585 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16587 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16588 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
16589 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16590 inst
.instruction
|= inst
.operands
[2].reg
;
16595 do_neon_dyadic_if_su (void)
16597 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16598 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
16601 if (check_simd_pred_availability (et
.type
== NT_float
,
16602 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16605 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
16609 do_neon_addsub_if_i (void)
16611 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
16612 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
16615 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16616 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
16617 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
16619 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
16620 /* If we are parsing Q registers and the element types match MVE, which NEON
16621 also supports, then we must check whether this is an instruction that can
16622 be used by both MVE/NEON. This distinction can be made based on whether
16623 they are predicated or not. */
16624 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
16626 if (check_simd_pred_availability (et
.type
== NT_float
,
16627 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16632 /* If they are either in a D register or are using an unsupported. */
16634 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16638 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16639 affected if we specify unsigned args. */
16640 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
16643 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
16645 V<op> A,B (A is operand 0, B is operand 2)
16650 so handle that case specially. */
16653 neon_exchange_operands (void)
16655 if (inst
.operands
[1].present
)
16657 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
16659 /* Swap operands[1] and operands[2]. */
16660 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
16661 inst
.operands
[1] = inst
.operands
[2];
16662 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
16667 inst
.operands
[1] = inst
.operands
[2];
16668 inst
.operands
[2] = inst
.operands
[0];
16673 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
16675 if (inst
.operands
[2].isreg
)
16678 neon_exchange_operands ();
16679 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
16683 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16684 struct neon_type_el et
= neon_check_type (2, rs
,
16685 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
16687 NEON_ENCODE (IMMED
, inst
);
16688 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16689 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16690 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16691 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16692 inst
.instruction
|= neon_quad (rs
) << 6;
16693 inst
.instruction
|= (et
.type
== NT_float
) << 10;
16694 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16696 neon_dp_fixup (&inst
);
16703 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
16707 do_neon_cmp_inv (void)
16709 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
16715 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
16718 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
16719 scalars, which are encoded in 5 bits, M : Rm.
16720 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
16721 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
16724 Dot Product instructions are similar to multiply instructions except elsize
16725 should always be 32.
16727 This function translates SCALAR, which is GAS's internal encoding of indexed
16728 scalar register, to raw encoding. There is also register and index range
16729 check based on ELSIZE. */
16732 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
16734 unsigned regno
= NEON_SCALAR_REG (scalar
);
16735 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
16740 if (regno
> 7 || elno
> 3)
16742 return regno
| (elno
<< 3);
16745 if (regno
> 15 || elno
> 1)
16747 return regno
| (elno
<< 4);
16751 first_error (_("scalar out of range for multiply instruction"));
16757 /* Encode multiply / multiply-accumulate scalar instructions. */
16760 neon_mul_mac (struct neon_type_el et
, int ubit
)
16764 /* Give a more helpful error message if we have an invalid type. */
16765 if (et
.type
== NT_invtype
)
16768 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
16769 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16770 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16771 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16772 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16773 inst
.instruction
|= LOW4 (scalar
);
16774 inst
.instruction
|= HI1 (scalar
) << 5;
16775 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16776 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16777 inst
.instruction
|= (ubit
!= 0) << 24;
16779 neon_dp_fixup (&inst
);
16783 do_neon_mac_maybe_scalar (void)
16785 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
16788 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16791 if (inst
.operands
[2].isscalar
)
16793 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
16794 struct neon_type_el et
= neon_check_type (3, rs
,
16795 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
16796 NEON_ENCODE (SCALAR
, inst
);
16797 neon_mul_mac (et
, neon_quad (rs
));
16801 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16802 affected if we specify unsigned args. */
16803 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
16808 do_neon_fmac (void)
16810 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
16813 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16816 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
16822 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16823 struct neon_type_el et
= neon_check_type (3, rs
,
16824 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16825 neon_three_same (neon_quad (rs
), 0, et
.size
);
16828 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
16829 same types as the MAC equivalents. The polynomial type for this instruction
16830 is encoded the same as the integer type. */
16835 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
16838 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16841 if (inst
.operands
[2].isscalar
)
16842 do_neon_mac_maybe_scalar ();
16844 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
16848 do_neon_qdmulh (void)
16850 if (inst
.operands
[2].isscalar
)
16852 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
16853 struct neon_type_el et
= neon_check_type (3, rs
,
16854 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16855 NEON_ENCODE (SCALAR
, inst
);
16856 neon_mul_mac (et
, neon_quad (rs
));
16860 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16861 struct neon_type_el et
= neon_check_type (3, rs
,
16862 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16863 NEON_ENCODE (INTEGER
, inst
);
16864 /* The U bit (rounding) comes from bit mask. */
16865 neon_three_same (neon_quad (rs
), 0, et
.size
);
16870 do_mve_vaddv (void)
16872 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
16873 struct neon_type_el et
16874 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16876 if (et
.type
== NT_invtype
)
16877 first_error (BAD_EL_TYPE
);
16879 if (inst
.cond
> COND_ALWAYS
)
16880 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16882 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16884 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16886 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
16892 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
16893 struct neon_type_el et
16894 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
16896 if (et
.type
== NT_invtype
)
16897 first_error (BAD_EL_TYPE
);
16899 if (inst
.cond
> COND_ALWAYS
)
16900 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16902 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16904 mve_encode_qqq (0, 64);
16908 do_mve_vbrsr (void)
16910 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16911 struct neon_type_el et
16912 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16914 if (inst
.cond
> COND_ALWAYS
)
16915 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16917 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16919 mve_encode_qqr (et
.size
, 0);
16925 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
16927 if (inst
.cond
> COND_ALWAYS
)
16928 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16930 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16932 mve_encode_qqq (1, 64);
16936 do_mve_vmull (void)
16939 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
16940 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
16941 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
16942 && inst
.cond
== COND_ALWAYS
16943 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
16948 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
16949 N_SUF_32
| N_F64
| N_P8
16950 | N_P16
| N_I_MVE
| N_KEY
);
16951 if (((et
.type
== NT_poly
) && et
.size
== 8
16952 && ARM_CPU_IS_ANY (cpu_variant
))
16953 || (et
.type
== NT_integer
) || (et
.type
== NT_float
))
16960 constraint (rs
!= NS_QQQ
, BAD_FPU
);
16961 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
16962 N_SU_32
| N_P8
| N_P16
| N_KEY
);
16964 /* We are dealing with MVE's vmullt. */
16966 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
16967 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
16968 as_tsktsk (BAD_MVE_SRCDEST
);
16970 if (inst
.cond
> COND_ALWAYS
)
16971 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16973 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16975 if (et
.type
== NT_poly
)
16976 mve_encode_qqq (neon_logbits (et
.size
), 64);
16978 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
16983 inst
.instruction
= N_MNEM_vmul
;
16986 inst
.pred_insn_type
= INSIDE_IT_INSN
;
16991 do_mve_vabav (void)
16993 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
16998 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17001 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
17002 | N_S16
| N_S32
| N_U8
| N_U16
17005 if (inst
.cond
> COND_ALWAYS
)
17006 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17008 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17010 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
17014 do_mve_vmladav (void)
17016 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
17017 struct neon_type_el et
= neon_check_type (3, rs
,
17018 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17020 if (et
.type
== NT_unsigned
17021 && (inst
.instruction
== M_MNEM_vmladavx
17022 || inst
.instruction
== M_MNEM_vmladavax
17023 || inst
.instruction
== M_MNEM_vmlsdav
17024 || inst
.instruction
== M_MNEM_vmlsdava
17025 || inst
.instruction
== M_MNEM_vmlsdavx
17026 || inst
.instruction
== M_MNEM_vmlsdavax
))
17027 first_error (BAD_SIMD_TYPE
);
17029 constraint (inst
.operands
[2].reg
> 14,
17030 _("MVE vector register in the range [Q0..Q7] expected"));
17032 if (inst
.cond
> COND_ALWAYS
)
17033 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17035 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17037 if (inst
.instruction
== M_MNEM_vmlsdav
17038 || inst
.instruction
== M_MNEM_vmlsdava
17039 || inst
.instruction
== M_MNEM_vmlsdavx
17040 || inst
.instruction
== M_MNEM_vmlsdavax
)
17041 inst
.instruction
|= (et
.size
== 8) << 28;
17043 inst
.instruction
|= (et
.size
== 8) << 8;
17045 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
17046 inst
.instruction
|= (et
.size
== 32) << 16;
17050 do_neon_qrdmlah (void)
17052 /* Check we're on the correct architecture. */
17053 if (!mark_feature_used (&fpu_neon_ext_armv8
))
17055 _("instruction form not available on this architecture.");
17056 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
17058 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
17059 record_feature_use (&fpu_neon_ext_v8_1
);
17062 if (inst
.operands
[2].isscalar
)
17064 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17065 struct neon_type_el et
= neon_check_type (3, rs
,
17066 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17067 NEON_ENCODE (SCALAR
, inst
);
17068 neon_mul_mac (et
, neon_quad (rs
));
17072 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17073 struct neon_type_el et
= neon_check_type (3, rs
,
17074 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17075 NEON_ENCODE (INTEGER
, inst
);
17076 /* The U bit (rounding) comes from bit mask. */
17077 neon_three_same (neon_quad (rs
), 0, et
.size
);
17082 do_neon_fcmp_absolute (void)
17084 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17085 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17086 N_F_16_32
| N_KEY
);
17087 /* Size field comes from bit mask. */
17088 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
17092 do_neon_fcmp_absolute_inv (void)
17094 neon_exchange_operands ();
17095 do_neon_fcmp_absolute ();
17099 do_neon_step (void)
17101 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17102 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17103 N_F_16_32
| N_KEY
);
17104 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
17108 do_neon_abs_neg (void)
17110 enum neon_shape rs
;
17111 struct neon_type_el et
;
17113 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
17116 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
17117 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
17119 if (check_simd_pred_availability (et
.type
== NT_float
,
17120 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17123 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17124 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17125 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17126 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17127 inst
.instruction
|= neon_quad (rs
) << 6;
17128 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17129 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17131 neon_dp_fixup (&inst
);
17137 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17138 struct neon_type_el et
= neon_check_type (2, rs
,
17139 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
17140 int imm
= inst
.operands
[2].imm
;
17141 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
17142 _("immediate out of range for insert"));
17143 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
17149 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17150 struct neon_type_el et
= neon_check_type (2, rs
,
17151 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
17152 int imm
= inst
.operands
[2].imm
;
17153 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17154 _("immediate out of range for insert"));
17155 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
17159 do_neon_qshlu_imm (void)
17161 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17162 struct neon_type_el et
= neon_check_type (2, rs
,
17163 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
17164 int imm
= inst
.operands
[2].imm
;
17165 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
17166 _("immediate out of range for shift"));
17167 /* Only encodes the 'U present' variant of the instruction.
17168 In this case, signed types have OP (bit 8) set to 0.
17169 Unsigned types have OP set to 1. */
17170 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
17171 /* The rest of the bits are the same as other immediate shifts. */
17172 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
17176 do_neon_qmovn (void)
17178 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
17179 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
17180 /* Saturating move where operands can be signed or unsigned, and the
17181 destination has the same signedness. */
17182 NEON_ENCODE (INTEGER
, inst
);
17183 if (et
.type
== NT_unsigned
)
17184 inst
.instruction
|= 0xc0;
17186 inst
.instruction
|= 0x80;
17187 neon_two_same (0, 1, et
.size
/ 2);
17191 do_neon_qmovun (void)
17193 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
17194 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
17195 /* Saturating move with unsigned results. Operands must be signed. */
17196 NEON_ENCODE (INTEGER
, inst
);
17197 neon_two_same (0, 1, et
.size
/ 2);
17201 do_neon_rshift_sat_narrow (void)
17203 /* FIXME: Types for narrowing. If operands are signed, results can be signed
17204 or unsigned. If operands are unsigned, results must also be unsigned. */
17205 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
17206 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
17207 int imm
= inst
.operands
[2].imm
;
17208 /* This gets the bounds check, size encoding and immediate bits calculation
17212 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
17213 VQMOVN.I<size> <Dd>, <Qm>. */
17216 inst
.operands
[2].present
= 0;
17217 inst
.instruction
= N_MNEM_vqmovn
;
17222 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17223 _("immediate out of range"));
17224 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
17228 do_neon_rshift_sat_narrow_u (void)
17230 /* FIXME: Types for narrowing. If operands are signed, results can be signed
17231 or unsigned. If operands are unsigned, results must also be unsigned. */
17232 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
17233 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
17234 int imm
= inst
.operands
[2].imm
;
17235 /* This gets the bounds check, size encoding and immediate bits calculation
17239 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
17240 VQMOVUN.I<size> <Dd>, <Qm>. */
17243 inst
.operands
[2].present
= 0;
17244 inst
.instruction
= N_MNEM_vqmovun
;
17249 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17250 _("immediate out of range"));
17251 /* FIXME: The manual is kind of unclear about what value U should have in
17252 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
17254 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
17258 do_neon_movn (void)
17260 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
17261 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
17262 NEON_ENCODE (INTEGER
, inst
);
17263 neon_two_same (0, 1, et
.size
/ 2);
17267 do_neon_rshift_narrow (void)
17269 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
17270 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
17271 int imm
= inst
.operands
[2].imm
;
17272 /* This gets the bounds check, size encoding and immediate bits calculation
17276 /* If immediate is zero then we are a pseudo-instruction for
17277 VMOVN.I<size> <Dd>, <Qm> */
17280 inst
.operands
[2].present
= 0;
17281 inst
.instruction
= N_MNEM_vmovn
;
17286 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
17287 _("immediate out of range for narrowing operation"));
17288 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
17292 do_neon_shll (void)
17294 /* FIXME: Type checking when lengthening. */
17295 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
17296 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
17297 unsigned imm
= inst
.operands
[2].imm
;
17299 if (imm
== et
.size
)
17301 /* Maximum shift variant. */
17302 NEON_ENCODE (INTEGER
, inst
);
17303 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17304 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17305 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17306 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17307 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17309 neon_dp_fixup (&inst
);
17313 /* A more-specific type check for non-max versions. */
17314 et
= neon_check_type (2, NS_QDI
,
17315 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
17316 NEON_ENCODE (IMMED
, inst
);
17317 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
17321 /* Check the various types for the VCVT instruction, and return which version
17322 the current instruction is. */
17324 #define CVT_FLAVOUR_VAR \
17325 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
17326 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
17327 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
17328 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
17329 /* Half-precision conversions. */ \
17330 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
17331 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
17332 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
17333 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
17334 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
17335 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
17336 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
17337 Compared with single/double precision variants, only the co-processor \
17338 field is different, so the encoding flow is reused here. */ \
17339 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
17340 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
17341 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
17342 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
17343 /* VFP instructions. */ \
17344 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
17345 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
17346 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
17347 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
17348 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
17349 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
17350 /* VFP instructions with bitshift. */ \
17351 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
17352 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
17353 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
17354 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
17355 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
17356 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
17357 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
17358 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
17360 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
17361 neon_cvt_flavour_##C,
17363 /* The different types of conversions we can do. */
17364 enum neon_cvt_flavour
17367 neon_cvt_flavour_invalid
,
17368 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
17373 static enum neon_cvt_flavour
17374 get_neon_cvt_flavour (enum neon_shape rs
)
17376 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
17377 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
17378 if (et.type != NT_invtype) \
17380 inst.error = NULL; \
17381 return (neon_cvt_flavour_##C); \
17384 struct neon_type_el et
;
17385 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
17386 || rs
== NS_FF
) ? N_VFP
: 0;
17387 /* The instruction versions which take an immediate take one register
17388 argument, which is extended to the width of the full register. Thus the
17389 "source" and "destination" registers must have the same width. Hack that
17390 here by making the size equal to the key (wider, in this case) operand. */
17391 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
17395 return neon_cvt_flavour_invalid
;
17410 /* Neon-syntax VFP conversions. */
17413 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
17415 const char *opname
= 0;
17417 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
17418 || rs
== NS_FHI
|| rs
== NS_HFI
)
17420 /* Conversions with immediate bitshift. */
17421 const char *enc
[] =
17423 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
17429 if (flavour
< (int) ARRAY_SIZE (enc
))
17431 opname
= enc
[flavour
];
17432 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17433 _("operands 0 and 1 must be the same register"));
17434 inst
.operands
[1] = inst
.operands
[2];
17435 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
17440 /* Conversions without bitshift. */
17441 const char *enc
[] =
17443 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
17449 if (flavour
< (int) ARRAY_SIZE (enc
))
17450 opname
= enc
[flavour
];
17454 do_vfp_nsyn_opcode (opname
);
17456 /* ARMv8.2 fp16 VCVT instruction. */
17457 if (flavour
== neon_cvt_flavour_s32_f16
17458 || flavour
== neon_cvt_flavour_u32_f16
17459 || flavour
== neon_cvt_flavour_f16_u32
17460 || flavour
== neon_cvt_flavour_f16_s32
)
17461 do_scalar_fp16_v82_encode ();
17465 do_vfp_nsyn_cvtz (void)
17467 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
17468 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
17469 const char *enc
[] =
17471 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
17477 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
17478 do_vfp_nsyn_opcode (enc
[flavour
]);
17482 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
17483 enum neon_cvt_mode mode
)
17488 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17489 D register operands. */
17490 if (flavour
== neon_cvt_flavour_s32_f64
17491 || flavour
== neon_cvt_flavour_u32_f64
)
17492 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17495 if (flavour
== neon_cvt_flavour_s32_f16
17496 || flavour
== neon_cvt_flavour_u32_f16
)
17497 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
17500 set_pred_insn_type (OUTSIDE_PRED_INSN
);
17504 case neon_cvt_flavour_s32_f64
:
17508 case neon_cvt_flavour_s32_f32
:
17512 case neon_cvt_flavour_s32_f16
:
17516 case neon_cvt_flavour_u32_f64
:
17520 case neon_cvt_flavour_u32_f32
:
17524 case neon_cvt_flavour_u32_f16
:
17529 first_error (_("invalid instruction shape"));
17535 case neon_cvt_mode_a
: rm
= 0; break;
17536 case neon_cvt_mode_n
: rm
= 1; break;
17537 case neon_cvt_mode_p
: rm
= 2; break;
17538 case neon_cvt_mode_m
: rm
= 3; break;
17539 default: first_error (_("invalid rounding mode")); return;
17542 NEON_ENCODE (FPV8
, inst
);
17543 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
17544 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
17545 inst
.instruction
|= sz
<< 8;
17547 /* ARMv8.2 fp16 VCVT instruction. */
17548 if (flavour
== neon_cvt_flavour_s32_f16
17549 ||flavour
== neon_cvt_flavour_u32_f16
)
17550 do_scalar_fp16_v82_encode ();
17551 inst
.instruction
|= op
<< 7;
17552 inst
.instruction
|= rm
<< 16;
17553 inst
.instruction
|= 0xf0000000;
17554 inst
.is_neon
= TRUE
;
17558 do_neon_cvt_1 (enum neon_cvt_mode mode
)
17560 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
17561 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
17562 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
17564 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
17566 if (flavour
== neon_cvt_flavour_invalid
)
17569 /* PR11109: Handle round-to-zero for VCVT conversions. */
17570 if (mode
== neon_cvt_mode_z
17571 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
17572 && (flavour
== neon_cvt_flavour_s16_f16
17573 || flavour
== neon_cvt_flavour_u16_f16
17574 || flavour
== neon_cvt_flavour_s32_f32
17575 || flavour
== neon_cvt_flavour_u32_f32
17576 || flavour
== neon_cvt_flavour_s32_f64
17577 || flavour
== neon_cvt_flavour_u32_f64
)
17578 && (rs
== NS_FD
|| rs
== NS_FF
))
17580 do_vfp_nsyn_cvtz ();
17584 /* ARMv8.2 fp16 VCVT conversions. */
17585 if (mode
== neon_cvt_mode_z
17586 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
17587 && (flavour
== neon_cvt_flavour_s32_f16
17588 || flavour
== neon_cvt_flavour_u32_f16
)
17591 do_vfp_nsyn_cvtz ();
17592 do_scalar_fp16_v82_encode ();
17596 /* VFP rather than Neon conversions. */
17597 if (flavour
>= neon_cvt_flavour_first_fp
)
17599 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
17600 do_vfp_nsyn_cvt (rs
, flavour
);
17602 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
17610 if (mode
== neon_cvt_mode_z
17611 && (flavour
== neon_cvt_flavour_f16_s16
17612 || flavour
== neon_cvt_flavour_f16_u16
17613 || flavour
== neon_cvt_flavour_s16_f16
17614 || flavour
== neon_cvt_flavour_u16_f16
17615 || flavour
== neon_cvt_flavour_f32_u32
17616 || flavour
== neon_cvt_flavour_f32_s32
17617 || flavour
== neon_cvt_flavour_s32_f32
17618 || flavour
== neon_cvt_flavour_u32_f32
))
17620 if (check_simd_pred_availability (1, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17623 else if (mode
== neon_cvt_mode_n
)
17625 /* We are dealing with vcvt with the 'ne' condition. */
17627 inst
.instruction
= N_MNEM_vcvt
;
17628 do_neon_cvt_1 (neon_cvt_mode_z
);
17631 /* fall through. */
17635 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
17636 0x0000100, 0x1000100, 0x0, 0x1000000};
17638 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17639 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17642 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17644 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
17645 _("immediate value out of range"));
17648 case neon_cvt_flavour_f16_s16
:
17649 case neon_cvt_flavour_f16_u16
:
17650 case neon_cvt_flavour_s16_f16
:
17651 case neon_cvt_flavour_u16_f16
:
17652 constraint (inst
.operands
[2].imm
> 16,
17653 _("immediate value out of range"));
17655 case neon_cvt_flavour_f32_u32
:
17656 case neon_cvt_flavour_f32_s32
:
17657 case neon_cvt_flavour_s32_f32
:
17658 case neon_cvt_flavour_u32_f32
:
17659 constraint (inst
.operands
[2].imm
> 32,
17660 _("immediate value out of range"));
17663 inst
.error
= BAD_FPU
;
17668 /* Fixed-point conversion with #0 immediate is encoded as an
17669 integer conversion. */
17670 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
17672 NEON_ENCODE (IMMED
, inst
);
17673 if (flavour
!= neon_cvt_flavour_invalid
)
17674 inst
.instruction
|= enctab
[flavour
];
17675 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17676 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17677 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17678 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17679 inst
.instruction
|= neon_quad (rs
) << 6;
17680 inst
.instruction
|= 1 << 21;
17681 if (flavour
< neon_cvt_flavour_s16_f16
)
17683 inst
.instruction
|= 1 << 21;
17684 immbits
= 32 - inst
.operands
[2].imm
;
17685 inst
.instruction
|= immbits
<< 16;
17689 inst
.instruction
|= 3 << 20;
17690 immbits
= 16 - inst
.operands
[2].imm
;
17691 inst
.instruction
|= immbits
<< 16;
17692 inst
.instruction
&= ~(1 << 9);
17695 neon_dp_fixup (&inst
);
17700 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17701 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
17702 && (flavour
== neon_cvt_flavour_s16_f16
17703 || flavour
== neon_cvt_flavour_u16_f16
17704 || flavour
== neon_cvt_flavour_s32_f32
17705 || flavour
== neon_cvt_flavour_u32_f32
))
17707 if (check_simd_pred_availability (1,
17708 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
17711 else if (mode
== neon_cvt_mode_z
17712 && (flavour
== neon_cvt_flavour_f16_s16
17713 || flavour
== neon_cvt_flavour_f16_u16
17714 || flavour
== neon_cvt_flavour_s16_f16
17715 || flavour
== neon_cvt_flavour_u16_f16
17716 || flavour
== neon_cvt_flavour_f32_u32
17717 || flavour
== neon_cvt_flavour_f32_s32
17718 || flavour
== neon_cvt_flavour_s32_f32
17719 || flavour
== neon_cvt_flavour_u32_f32
))
17721 if (check_simd_pred_availability (1,
17722 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17725 /* fall through. */
17727 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
17730 NEON_ENCODE (FLOAT
, inst
);
17731 if (check_simd_pred_availability (1,
17732 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
17735 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17736 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17737 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17738 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17739 inst
.instruction
|= neon_quad (rs
) << 6;
17740 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
17741 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
17742 inst
.instruction
|= mode
<< 8;
17743 if (flavour
== neon_cvt_flavour_u16_f16
17744 || flavour
== neon_cvt_flavour_s16_f16
)
17745 /* Mask off the original size bits and reencode them. */
17746 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
17749 inst
.instruction
|= 0xfc000000;
17751 inst
.instruction
|= 0xf0000000;
17757 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
17758 0x100, 0x180, 0x0, 0x080};
17760 NEON_ENCODE (INTEGER
, inst
);
17762 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17764 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17768 if (flavour
!= neon_cvt_flavour_invalid
)
17769 inst
.instruction
|= enctab
[flavour
];
17771 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17772 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17773 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17774 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17775 inst
.instruction
|= neon_quad (rs
) << 6;
17776 if (flavour
>= neon_cvt_flavour_s16_f16
17777 && flavour
<= neon_cvt_flavour_f16_u16
)
17778 /* Half precision. */
17779 inst
.instruction
|= 1 << 18;
17781 inst
.instruction
|= 2 << 18;
17783 neon_dp_fixup (&inst
);
17788 /* Half-precision conversions for Advanced SIMD -- neon. */
17791 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17795 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
17797 as_bad (_("operand size must match register width"));
17802 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
17804 as_bad (_("operand size must match register width"));
17809 inst
.instruction
= 0x3b60600;
17811 inst
.instruction
= 0x3b60700;
17813 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17814 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17815 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17816 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17817 neon_dp_fixup (&inst
);
17821 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
17822 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
17823 do_vfp_nsyn_cvt (rs
, flavour
);
17825 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
17830 do_neon_cvtr (void)
17832 do_neon_cvt_1 (neon_cvt_mode_x
);
17838 do_neon_cvt_1 (neon_cvt_mode_z
);
17842 do_neon_cvta (void)
17844 do_neon_cvt_1 (neon_cvt_mode_a
);
17848 do_neon_cvtn (void)
17850 do_neon_cvt_1 (neon_cvt_mode_n
);
17854 do_neon_cvtp (void)
17856 do_neon_cvt_1 (neon_cvt_mode_p
);
17860 do_neon_cvtm (void)
17862 do_neon_cvt_1 (neon_cvt_mode_m
);
17866 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
17869 mark_feature_used (&fpu_vfp_ext_armv8
);
17871 encode_arm_vfp_reg (inst
.operands
[0].reg
,
17872 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
17873 encode_arm_vfp_reg (inst
.operands
[1].reg
,
17874 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
17875 inst
.instruction
|= to
? 0x10000 : 0;
17876 inst
.instruction
|= t
? 0x80 : 0;
17877 inst
.instruction
|= is_double
? 0x100 : 0;
17878 do_vfp_cond_or_thumb ();
17882 do_neon_cvttb_1 (bfd_boolean t
)
17884 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
17885 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
17889 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
17891 int single_to_half
= 0;
17892 if (check_simd_pred_availability (1, NEON_CHECK_ARCH
))
17895 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
17897 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
17898 && (flavour
== neon_cvt_flavour_u16_f16
17899 || flavour
== neon_cvt_flavour_s16_f16
17900 || flavour
== neon_cvt_flavour_f16_s16
17901 || flavour
== neon_cvt_flavour_f16_u16
17902 || flavour
== neon_cvt_flavour_u32_f32
17903 || flavour
== neon_cvt_flavour_s32_f32
17904 || flavour
== neon_cvt_flavour_f32_s32
17905 || flavour
== neon_cvt_flavour_f32_u32
))
17908 inst
.instruction
= N_MNEM_vcvt
;
17909 set_pred_insn_type (INSIDE_VPT_INSN
);
17910 do_neon_cvt_1 (neon_cvt_mode_z
);
17913 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
17914 single_to_half
= 1;
17915 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
17917 first_error (BAD_FPU
);
17921 inst
.instruction
= 0xee3f0e01;
17922 inst
.instruction
|= single_to_half
<< 28;
17923 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17924 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
17925 inst
.instruction
|= t
<< 12;
17926 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17927 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
17930 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
17933 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
17935 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
17938 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
17940 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
17942 /* The VCVTB and VCVTT instructions with D-register operands
17943 don't work for SP only targets. */
17944 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17948 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
17950 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
17952 /* The VCVTB and VCVTT instructions with D-register operands
17953 don't work for SP only targets. */
17954 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17958 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
17965 do_neon_cvtb (void)
17967 do_neon_cvttb_1 (FALSE
);
17972 do_neon_cvtt (void)
17974 do_neon_cvttb_1 (TRUE
);
17978 neon_move_immediate (void)
17980 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
17981 struct neon_type_el et
= neon_check_type (2, rs
,
17982 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
17983 unsigned immlo
, immhi
= 0, immbits
;
17984 int op
, cmode
, float_p
;
17986 constraint (et
.type
== NT_invtype
,
17987 _("operand size must be specified for immediate VMOV"));
17989 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
17990 op
= (inst
.instruction
& (1 << 5)) != 0;
17992 immlo
= inst
.operands
[1].imm
;
17993 if (inst
.operands
[1].regisimm
)
17994 immhi
= inst
.operands
[1].reg
;
17996 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
17997 _("immediate has bits set outside the operand size"));
17999 float_p
= inst
.operands
[1].immisfloat
;
18001 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
18002 et
.size
, et
.type
)) == FAIL
)
18004 /* Invert relevant bits only. */
18005 neon_invert_size (&immlo
, &immhi
, et
.size
);
18006 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
18007 with one or the other; those cases are caught by
18008 neon_cmode_for_move_imm. */
18010 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
18011 &op
, et
.size
, et
.type
)) == FAIL
)
18013 first_error (_("immediate out of range"));
18018 inst
.instruction
&= ~(1 << 5);
18019 inst
.instruction
|= op
<< 5;
18021 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18022 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18023 inst
.instruction
|= neon_quad (rs
) << 6;
18024 inst
.instruction
|= cmode
<< 8;
18026 neon_write_immbits (immbits
);
18032 if (inst
.operands
[1].isreg
)
18034 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18036 NEON_ENCODE (INTEGER
, inst
);
18037 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18038 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18039 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18040 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18041 inst
.instruction
|= neon_quad (rs
) << 6;
18045 NEON_ENCODE (IMMED
, inst
);
18046 neon_move_immediate ();
18049 neon_dp_fixup (&inst
);
18052 /* Encode instructions of form:
18054 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
18055 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
18058 neon_mixed_length (struct neon_type_el et
, unsigned size
)
18060 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18061 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18062 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
18063 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
18064 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
18065 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
18066 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
18067 inst
.instruction
|= neon_logbits (size
) << 20;
18069 neon_dp_fixup (&inst
);
18073 do_neon_dyadic_long (void)
18075 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
18078 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
18081 NEON_ENCODE (INTEGER
, inst
);
18082 /* FIXME: Type checking for lengthening op. */
18083 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18084 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
18085 neon_mixed_length (et
, et
.size
);
18087 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18088 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
18090 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
18091 in an IT block with le/lt conditions. */
18093 if (inst
.cond
== 0xf)
18095 else if (inst
.cond
== 0x10)
18098 inst
.pred_insn_type
= INSIDE_IT_INSN
;
18100 if (inst
.instruction
== N_MNEM_vaddl
)
18102 inst
.instruction
= N_MNEM_vadd
;
18103 do_neon_addsub_if_i ();
18105 else if (inst
.instruction
== N_MNEM_vsubl
)
18107 inst
.instruction
= N_MNEM_vsub
;
18108 do_neon_addsub_if_i ();
18110 else if (inst
.instruction
== N_MNEM_vabdl
)
18112 inst
.instruction
= N_MNEM_vabd
;
18113 do_neon_dyadic_if_su ();
18117 first_error (BAD_FPU
);
18121 do_neon_abal (void)
18123 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18124 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
18125 neon_mixed_length (et
, et
.size
);
18129 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
18131 if (inst
.operands
[2].isscalar
)
18133 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
18134 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
18135 NEON_ENCODE (SCALAR
, inst
);
18136 neon_mul_mac (et
, et
.type
== NT_unsigned
);
18140 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18141 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
18142 NEON_ENCODE (INTEGER
, inst
);
18143 neon_mixed_length (et
, et
.size
);
18148 do_neon_mac_maybe_scalar_long (void)
18150 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
18153 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
18154 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
18157 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
18159 unsigned regno
= NEON_SCALAR_REG (scalar
);
18160 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
18164 if (regno
> 7 || elno
> 3)
18167 return ((regno
& 0x7)
18168 | ((elno
& 0x1) << 3)
18169 | (((elno
>> 1) & 0x1) << 5));
18173 if (regno
> 15 || elno
> 1)
18176 return (((regno
& 0x1) << 5)
18177 | ((regno
>> 1) & 0x7)
18178 | ((elno
& 0x1) << 3));
18182 first_error (_("scalar out of range for multiply instruction"));
18187 do_neon_fmac_maybe_scalar_long (int subtype
)
18189 enum neon_shape rs
;
18191 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
18192 field (bits[21:20]) has different meaning. For scalar index variant, it's
18193 used to differentiate add and subtract, otherwise it's with fixed value
18197 if (inst
.cond
!= COND_ALWAYS
)
18198 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
18199 "behaviour is UNPREDICTABLE"));
18201 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
18204 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
18207 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
18208 be a scalar index register. */
18209 if (inst
.operands
[2].isscalar
)
18211 high8
= 0xfe000000;
18214 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
18218 high8
= 0xfc000000;
18221 inst
.instruction
|= (0x1 << 23);
18222 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
18225 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
18227 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
18228 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
18229 so we simply pass -1 as size. */
18230 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
18231 neon_three_same (quad_p
, 0, size
);
18233 /* Undo neon_dp_fixup. Redo the high eight bits. */
18234 inst
.instruction
&= 0x00ffffff;
18235 inst
.instruction
|= high8
;
18237 #define LOW1(R) ((R) & 0x1)
18238 #define HI4(R) (((R) >> 1) & 0xf)
18239 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
18240 whether the instruction is in Q form and whether Vm is a scalar indexed
18242 if (inst
.operands
[2].isscalar
)
18245 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
18246 inst
.instruction
&= 0xffffffd0;
18247 inst
.instruction
|= rm
;
18251 /* Redo Rn as well. */
18252 inst
.instruction
&= 0xfff0ff7f;
18253 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
18254 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
18259 /* Redo Rn and Rm. */
18260 inst
.instruction
&= 0xfff0ff50;
18261 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
18262 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
18263 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
18264 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
18269 do_neon_vfmal (void)
18271 return do_neon_fmac_maybe_scalar_long (0);
18275 do_neon_vfmsl (void)
18277 return do_neon_fmac_maybe_scalar_long (1);
18281 do_neon_dyadic_wide (void)
18283 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
18284 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18285 neon_mixed_length (et
, et
.size
);
18289 do_neon_dyadic_narrow (void)
18291 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18292 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
18293 /* Operand sign is unimportant, and the U bit is part of the opcode,
18294 so force the operand type to integer. */
18295 et
.type
= NT_integer
;
18296 neon_mixed_length (et
, et
.size
/ 2);
18300 do_neon_mul_sat_scalar_long (void)
18302 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
18306 do_neon_vmull (void)
18308 if (inst
.operands
[2].isscalar
)
18309 do_neon_mac_maybe_scalar_long ();
18312 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
18313 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
18315 if (et
.type
== NT_poly
)
18316 NEON_ENCODE (POLY
, inst
);
18318 NEON_ENCODE (INTEGER
, inst
);
18320 /* For polynomial encoding the U bit must be zero, and the size must
18321 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
18322 obviously, as 0b10). */
18325 /* Check we're on the correct architecture. */
18326 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
18328 _("Instruction form not available on this architecture.");
18333 neon_mixed_length (et
, et
.size
);
18340 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
18341 struct neon_type_el et
= neon_check_type (3, rs
,
18342 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18343 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
18345 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
18346 _("shift out of range"));
18347 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18348 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18349 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
18350 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
18351 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
18352 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
18353 inst
.instruction
|= neon_quad (rs
) << 6;
18354 inst
.instruction
|= imm
<< 8;
18356 neon_dp_fixup (&inst
);
18362 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18363 struct neon_type_el et
= neon_check_type (2, rs
,
18364 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18365 unsigned op
= (inst
.instruction
>> 7) & 3;
18366 /* N (width of reversed regions) is encoded as part of the bitmask. We
18367 extract it here to check the elements to be reversed are smaller.
18368 Otherwise we'd get a reserved instruction. */
18369 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
18370 gas_assert (elsize
!= 0);
18371 constraint (et
.size
>= elsize
,
18372 _("elements must be smaller than reversal region"));
18373 neon_two_same (neon_quad (rs
), 1, et
.size
);
18379 if (inst
.operands
[1].isscalar
)
18381 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
18382 struct neon_type_el et
= neon_check_type (2, rs
,
18383 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18384 unsigned sizebits
= et
.size
>> 3;
18385 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
18386 int logsize
= neon_logbits (et
.size
);
18387 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
18389 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
18392 NEON_ENCODE (SCALAR
, inst
);
18393 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18394 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18395 inst
.instruction
|= LOW4 (dm
);
18396 inst
.instruction
|= HI1 (dm
) << 5;
18397 inst
.instruction
|= neon_quad (rs
) << 6;
18398 inst
.instruction
|= x
<< 17;
18399 inst
.instruction
|= sizebits
<< 16;
18401 neon_dp_fixup (&inst
);
18405 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
18406 struct neon_type_el et
= neon_check_type (2, rs
,
18407 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
18408 /* Duplicate ARM register to lanes of vector. */
18409 NEON_ENCODE (ARMREG
, inst
);
18412 case 8: inst
.instruction
|= 0x400000; break;
18413 case 16: inst
.instruction
|= 0x000020; break;
18414 case 32: inst
.instruction
|= 0x000000; break;
18417 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
18418 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
18419 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
18420 inst
.instruction
|= neon_quad (rs
) << 21;
18421 /* The encoding for this instruction is identical for the ARM and Thumb
18422 variants, except for the condition field. */
18423 do_vfp_cond_or_thumb ();
18428 do_mve_mov (int toQ
)
18430 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18432 if (inst
.cond
> COND_ALWAYS
)
18433 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
18435 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
18444 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
18445 _("Index one must be [2,3] and index two must be two less than"
18447 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
18448 _("General purpose registers may not be the same"));
18449 constraint (inst
.operands
[Rt
].reg
== REG_SP
18450 || inst
.operands
[Rt2
].reg
== REG_SP
,
18452 constraint (inst
.operands
[Rt
].reg
== REG_PC
18453 || inst
.operands
[Rt2
].reg
== REG_PC
,
18456 inst
.instruction
= 0xec000f00;
18457 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
18458 inst
.instruction
|= !!toQ
<< 20;
18459 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
18460 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
18461 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
18462 inst
.instruction
|= inst
.operands
[Rt
].reg
;
18468 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18471 if (inst
.cond
> COND_ALWAYS
)
18472 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18474 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18476 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
18479 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18480 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
18481 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18482 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18483 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18488 /* VMOV has particularly many variations. It can be one of:
18489 0. VMOV<c><q> <Qd>, <Qm>
18490 1. VMOV<c><q> <Dd>, <Dm>
18491 (Register operations, which are VORR with Rm = Rn.)
18492 2. VMOV<c><q>.<dt> <Qd>, #<imm>
18493 3. VMOV<c><q>.<dt> <Dd>, #<imm>
18495 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
18496 (ARM register to scalar.)
18497 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
18498 (Two ARM registers to vector.)
18499 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
18500 (Scalar to ARM register.)
18501 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
18502 (Vector to two ARM registers.)
18503 8. VMOV.F32 <Sd>, <Sm>
18504 9. VMOV.F64 <Dd>, <Dm>
18505 (VFP register moves.)
18506 10. VMOV.F32 <Sd>, #imm
18507 11. VMOV.F64 <Dd>, #imm
18508 (VFP float immediate load.)
18509 12. VMOV <Rd>, <Sm>
18510 (VFP single to ARM reg.)
18511 13. VMOV <Sd>, <Rm>
18512 (ARM reg to VFP single.)
18513 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
18514 (Two ARM regs to two VFP singles.)
18515 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
18516 (Two VFP singles to two ARM regs.)
18517 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
18518 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
18519 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
18520 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
18522 These cases can be disambiguated using neon_select_shape, except cases 1/9
18523 and 3/11 which depend on the operand type too.
18525 All the encoded bits are hardcoded by this function.
18527 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
18528 Cases 5, 7 may be used with VFPv2 and above.
18530 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
18531 can specify a type where it doesn't make sense to, and is ignored). */
18536 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
18537 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
18538 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
18539 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
18541 struct neon_type_el et
;
18542 const char *ldconst
= 0;
18546 case NS_DD
: /* case 1/9. */
18547 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
18548 /* It is not an error here if no type is given. */
18550 if (et
.type
== NT_float
&& et
.size
== 64)
18552 do_vfp_nsyn_opcode ("fcpyd");
18555 /* fall through. */
18557 case NS_QQ
: /* case 0/1. */
18559 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18561 /* The architecture manual I have doesn't explicitly state which
18562 value the U bit should have for register->register moves, but
18563 the equivalent VORR instruction has U = 0, so do that. */
18564 inst
.instruction
= 0x0200110;
18565 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18566 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18567 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18568 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18569 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
18570 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
18571 inst
.instruction
|= neon_quad (rs
) << 6;
18573 neon_dp_fixup (&inst
);
18577 case NS_DI
: /* case 3/11. */
18578 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
18580 if (et
.type
== NT_float
&& et
.size
== 64)
18582 /* case 11 (fconstd). */
18583 ldconst
= "fconstd";
18584 goto encode_fconstd
;
18586 /* fall through. */
18588 case NS_QI
: /* case 2/3. */
18589 if (check_simd_pred_availability (0, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18591 inst
.instruction
= 0x0800010;
18592 neon_move_immediate ();
18593 neon_dp_fixup (&inst
);
18596 case NS_SR
: /* case 4. */
18598 unsigned bcdebits
= 0;
18600 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
18601 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
18603 /* .<size> is optional here, defaulting to .32. */
18604 if (inst
.vectype
.elems
== 0
18605 && inst
.operands
[0].vectype
.type
== NT_invtype
18606 && inst
.operands
[1].vectype
.type
== NT_invtype
)
18608 inst
.vectype
.el
[0].type
= NT_untyped
;
18609 inst
.vectype
.el
[0].size
= 32;
18610 inst
.vectype
.elems
= 1;
18613 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
18614 logsize
= neon_logbits (et
.size
);
18618 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18619 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
18624 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
18625 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18629 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18631 if (inst
.operands
[1].reg
== REG_SP
)
18632 as_tsktsk (MVE_BAD_SP
);
18633 else if (inst
.operands
[1].reg
== REG_PC
)
18634 as_tsktsk (MVE_BAD_PC
);
18636 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
18638 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
18639 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
18644 case 8: bcdebits
= 0x8; break;
18645 case 16: bcdebits
= 0x1; break;
18646 case 32: bcdebits
= 0x0; break;
18650 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
18652 inst
.instruction
= 0xe000b10;
18653 do_vfp_cond_or_thumb ();
18654 inst
.instruction
|= LOW4 (dn
) << 16;
18655 inst
.instruction
|= HI1 (dn
) << 7;
18656 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
18657 inst
.instruction
|= (bcdebits
& 3) << 5;
18658 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
18659 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
18663 case NS_DRR
: /* case 5 (fmdrr). */
18664 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
18665 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18668 inst
.instruction
= 0xc400b10;
18669 do_vfp_cond_or_thumb ();
18670 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
18671 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
18672 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
18673 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
18676 case NS_RS
: /* case 6. */
18679 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
18680 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
18681 unsigned abcdebits
= 0;
18683 /* .<dt> is optional here, defaulting to .32. */
18684 if (inst
.vectype
.elems
== 0
18685 && inst
.operands
[0].vectype
.type
== NT_invtype
18686 && inst
.operands
[1].vectype
.type
== NT_invtype
)
18688 inst
.vectype
.el
[0].type
= NT_untyped
;
18689 inst
.vectype
.el
[0].size
= 32;
18690 inst
.vectype
.elems
= 1;
18693 et
= neon_check_type (2, NS_NULL
,
18694 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
18695 logsize
= neon_logbits (et
.size
);
18699 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18700 && vfp_or_neon_is_neon (NEON_CHECK_CC
18701 | NEON_CHECK_ARCH
) == FAIL
)
18706 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
18707 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18711 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18713 if (inst
.operands
[0].reg
== REG_SP
)
18714 as_tsktsk (MVE_BAD_SP
);
18715 else if (inst
.operands
[0].reg
== REG_PC
)
18716 as_tsktsk (MVE_BAD_PC
);
18719 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
18721 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
18722 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
18726 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
18727 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
18728 case 32: abcdebits
= 0x00; break;
18732 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
18733 inst
.instruction
= 0xe100b10;
18734 do_vfp_cond_or_thumb ();
18735 inst
.instruction
|= LOW4 (dn
) << 16;
18736 inst
.instruction
|= HI1 (dn
) << 7;
18737 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
18738 inst
.instruction
|= (abcdebits
& 3) << 5;
18739 inst
.instruction
|= (abcdebits
>> 2) << 21;
18740 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
18744 case NS_RRD
: /* case 7 (fmrrd). */
18745 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
18746 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18749 inst
.instruction
= 0xc500b10;
18750 do_vfp_cond_or_thumb ();
18751 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
18752 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
18753 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
18754 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
18757 case NS_FF
: /* case 8 (fcpys). */
18758 do_vfp_nsyn_opcode ("fcpys");
18762 case NS_FI
: /* case 10 (fconsts). */
18763 ldconst
= "fconsts";
18765 if (!inst
.operands
[1].immisfloat
)
18768 /* Immediate has to fit in 8 bits so float is enough. */
18769 float imm
= (float) inst
.operands
[1].imm
;
18770 memcpy (&new_imm
, &imm
, sizeof (float));
18771 /* But the assembly may have been written to provide an integer
18772 bit pattern that equates to a float, so check that the
18773 conversion has worked. */
18774 if (is_quarter_float (new_imm
))
18776 if (is_quarter_float (inst
.operands
[1].imm
))
18777 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
18779 inst
.operands
[1].imm
= new_imm
;
18780 inst
.operands
[1].immisfloat
= 1;
18784 if (is_quarter_float (inst
.operands
[1].imm
))
18786 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
18787 do_vfp_nsyn_opcode (ldconst
);
18789 /* ARMv8.2 fp16 vmov.f16 instruction. */
18791 do_scalar_fp16_v82_encode ();
18794 first_error (_("immediate out of range"));
18798 case NS_RF
: /* case 12 (fmrs). */
18799 do_vfp_nsyn_opcode ("fmrs");
18800 /* ARMv8.2 fp16 vmov.f16 instruction. */
18802 do_scalar_fp16_v82_encode ();
18806 case NS_FR
: /* case 13 (fmsr). */
18807 do_vfp_nsyn_opcode ("fmsr");
18808 /* ARMv8.2 fp16 vmov.f16 instruction. */
18810 do_scalar_fp16_v82_encode ();
18820 /* The encoders for the fmrrs and fmsrr instructions expect three operands
18821 (one of which is a list), but we have parsed four. Do some fiddling to
18822 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
18824 case NS_RRFF
: /* case 14 (fmrrs). */
18825 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
18826 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18828 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
18829 _("VFP registers must be adjacent"));
18830 inst
.operands
[2].imm
= 2;
18831 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
18832 do_vfp_nsyn_opcode ("fmrrs");
18835 case NS_FFRR
: /* case 15 (fmsrr). */
18836 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
18837 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
18839 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
18840 _("VFP registers must be adjacent"));
18841 inst
.operands
[1] = inst
.operands
[2];
18842 inst
.operands
[2] = inst
.operands
[3];
18843 inst
.operands
[0].imm
= 2;
18844 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
18845 do_vfp_nsyn_opcode ("fmsrr");
18849 /* neon_select_shape has determined that the instruction
18850 shape is wrong and has already set the error message. */
18861 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
18862 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
18863 && !inst
.operands
[2].present
))
18865 inst
.instruction
= 0;
18868 set_pred_insn_type (INSIDE_IT_INSN
);
18873 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18876 if (inst
.cond
!= COND_ALWAYS
)
18877 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18879 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
18880 | N_S16
| N_U16
| N_KEY
);
18882 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
18883 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18884 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
18885 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18886 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18887 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18892 do_neon_rshift_round_imm (void)
18894 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18895 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
18896 int imm
= inst
.operands
[2].imm
;
18898 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
18901 inst
.operands
[2].present
= 0;
18906 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18907 _("immediate out of range for shift"));
18908 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
18913 do_neon_movhf (void)
18915 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
18916 constraint (rs
!= NS_HH
, _("invalid suffix"));
18918 if (inst
.cond
!= COND_ALWAYS
)
18922 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
18923 " the behaviour is UNPREDICTABLE"));
18927 inst
.error
= BAD_COND
;
18932 do_vfp_sp_monadic ();
18935 inst
.instruction
|= 0xf0000000;
18939 do_neon_movl (void)
18941 struct neon_type_el et
= neon_check_type (2, NS_QD
,
18942 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18943 unsigned sizebits
= et
.size
>> 3;
18944 inst
.instruction
|= sizebits
<< 19;
18945 neon_two_same (0, et
.type
== NT_unsigned
, -1);
18951 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18952 struct neon_type_el et
= neon_check_type (2, rs
,
18953 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18954 NEON_ENCODE (INTEGER
, inst
);
18955 neon_two_same (neon_quad (rs
), 1, et
.size
);
18959 do_neon_zip_uzp (void)
18961 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18962 struct neon_type_el et
= neon_check_type (2, rs
,
18963 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18964 if (rs
== NS_DD
&& et
.size
== 32)
18966 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
18967 inst
.instruction
= N_MNEM_vtrn
;
18971 neon_two_same (neon_quad (rs
), 1, et
.size
);
18975 do_neon_sat_abs_neg (void)
18977 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18978 struct neon_type_el et
= neon_check_type (2, rs
,
18979 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18980 neon_two_same (neon_quad (rs
), 1, et
.size
);
18984 do_neon_pair_long (void)
18986 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18987 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
18988 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
18989 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
18990 neon_two_same (neon_quad (rs
), 1, et
.size
);
18994 do_neon_recip_est (void)
18996 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18997 struct neon_type_el et
= neon_check_type (2, rs
,
18998 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
18999 inst
.instruction
|= (et
.type
== NT_float
) << 8;
19000 neon_two_same (neon_quad (rs
), 1, et
.size
);
19006 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19007 struct neon_type_el et
= neon_check_type (2, rs
,
19008 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
19009 neon_two_same (neon_quad (rs
), 1, et
.size
);
19015 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19016 struct neon_type_el et
= neon_check_type (2, rs
,
19017 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
19018 neon_two_same (neon_quad (rs
), 1, et
.size
);
19024 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19025 struct neon_type_el et
= neon_check_type (2, rs
,
19026 N_EQK
| N_INT
, N_8
| N_KEY
);
19027 neon_two_same (neon_quad (rs
), 1, et
.size
);
19033 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19034 neon_two_same (neon_quad (rs
), 1, -1);
19038 do_neon_tbl_tbx (void)
19040 unsigned listlenbits
;
19041 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
19043 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
19045 first_error (_("bad list length for table lookup"));
19049 listlenbits
= inst
.operands
[1].imm
- 1;
19050 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19051 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19052 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19053 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19054 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19055 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19056 inst
.instruction
|= listlenbits
<< 8;
19058 neon_dp_fixup (&inst
);
19062 do_neon_ldm_stm (void)
19064 /* P, U and L bits are part of bitmask. */
19065 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
19066 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
19068 if (inst
.operands
[1].issingle
)
19070 do_vfp_nsyn_ldm_stm (is_dbmode
);
19074 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
19075 _("writeback (!) must be used for VLDMDB and VSTMDB"));
19077 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
19078 _("register list must contain at least 1 and at most 16 "
19081 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
19082 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
19083 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19084 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
19086 inst
.instruction
|= offsetbits
;
19088 do_vfp_cond_or_thumb ();
19092 do_neon_ldr_str (void)
19094 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
19096 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
19097 And is UNPREDICTABLE in thumb mode. */
19099 && inst
.operands
[1].reg
== REG_PC
19100 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
19103 inst
.error
= _("Use of PC here is UNPREDICTABLE");
19104 else if (warn_on_deprecated
)
19105 as_tsktsk (_("Use of PC here is deprecated"));
19108 if (inst
.operands
[0].issingle
)
19111 do_vfp_nsyn_opcode ("flds");
19113 do_vfp_nsyn_opcode ("fsts");
19115 /* ARMv8.2 vldr.16/vstr.16 instruction. */
19116 if (inst
.vectype
.el
[0].size
== 16)
19117 do_scalar_fp16_v82_encode ();
19122 do_vfp_nsyn_opcode ("fldd");
19124 do_vfp_nsyn_opcode ("fstd");
19129 do_t_vldr_vstr_sysreg (void)
19131 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
19132 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
19134 /* Use of PC is UNPREDICTABLE. */
19135 if (inst
.operands
[1].reg
== REG_PC
)
19136 inst
.error
= _("Use of PC here is UNPREDICTABLE");
19138 if (inst
.operands
[1].immisreg
)
19139 inst
.error
= _("instruction does not accept register index");
19141 if (!inst
.operands
[1].isreg
)
19142 inst
.error
= _("instruction does not accept PC-relative addressing");
19144 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
19145 inst
.error
= _("immediate value out of range");
19147 inst
.instruction
= 0xec000f80;
19149 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
19150 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
19151 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
19152 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
19156 do_vldr_vstr (void)
19158 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
19160 /* VLDR/VSTR (System Register). */
19163 if (!mark_feature_used (&arm_ext_v8_1m_main
))
19164 as_bad (_("Instruction not permitted on this architecture"));
19166 do_t_vldr_vstr_sysreg ();
19171 if (!mark_feature_used (&fpu_vfp_ext_v1xd
))
19172 as_bad (_("Instruction not permitted on this architecture"));
19173 do_neon_ldr_str ();
19177 /* "interleave" version also handles non-interleaving register VLD1/VST1
19181 do_neon_ld_st_interleave (void)
19183 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
19184 N_8
| N_16
| N_32
| N_64
);
19185 unsigned alignbits
= 0;
19187 /* The bits in this table go:
19188 0: register stride of one (0) or two (1)
19189 1,2: register list length, minus one (1, 2, 3, 4).
19190 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
19191 We use -1 for invalid entries. */
19192 const int typetable
[] =
19194 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
19195 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
19196 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
19197 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
19201 if (et
.type
== NT_invtype
)
19204 if (inst
.operands
[1].immisalign
)
19205 switch (inst
.operands
[1].imm
>> 8)
19207 case 64: alignbits
= 1; break;
19209 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
19210 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
19211 goto bad_alignment
;
19215 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
19216 goto bad_alignment
;
19221 first_error (_("bad alignment"));
19225 inst
.instruction
|= alignbits
<< 4;
19226 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19228 /* Bits [4:6] of the immediate in a list specifier encode register stride
19229 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
19230 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
19231 up the right value for "type" in a table based on this value and the given
19232 list style, then stick it back. */
19233 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
19234 | (((inst
.instruction
>> 8) & 3) << 3);
19236 typebits
= typetable
[idx
];
19238 constraint (typebits
== -1, _("bad list type for instruction"));
19239 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
19242 inst
.instruction
&= ~0xf00;
19243 inst
.instruction
|= typebits
<< 8;
19246 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
19247 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
19248 otherwise. The variable arguments are a list of pairs of legal (size, align)
19249 values, terminated with -1. */
19252 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
19255 int result
= FAIL
, thissize
, thisalign
;
19257 if (!inst
.operands
[1].immisalign
)
19263 va_start (ap
, do_alignment
);
19267 thissize
= va_arg (ap
, int);
19268 if (thissize
== -1)
19270 thisalign
= va_arg (ap
, int);
19272 if (size
== thissize
&& align
== thisalign
)
19275 while (result
!= SUCCESS
);
19279 if (result
== SUCCESS
)
19282 first_error (_("unsupported alignment for instruction"));
19288 do_neon_ld_st_lane (void)
19290 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
19291 int align_good
, do_alignment
= 0;
19292 int logsize
= neon_logbits (et
.size
);
19293 int align
= inst
.operands
[1].imm
>> 8;
19294 int n
= (inst
.instruction
>> 8) & 3;
19295 int max_el
= 64 / et
.size
;
19297 if (et
.type
== NT_invtype
)
19300 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
19301 _("bad list length"));
19302 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
19303 _("scalar index out of range"));
19304 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
19306 _("stride of 2 unavailable when element size is 8"));
19310 case 0: /* VLD1 / VST1. */
19311 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
19313 if (align_good
== FAIL
)
19317 unsigned alignbits
= 0;
19320 case 16: alignbits
= 0x1; break;
19321 case 32: alignbits
= 0x3; break;
19324 inst
.instruction
|= alignbits
<< 4;
19328 case 1: /* VLD2 / VST2. */
19329 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
19330 16, 32, 32, 64, -1);
19331 if (align_good
== FAIL
)
19334 inst
.instruction
|= 1 << 4;
19337 case 2: /* VLD3 / VST3. */
19338 constraint (inst
.operands
[1].immisalign
,
19339 _("can't use alignment with this instruction"));
19342 case 3: /* VLD4 / VST4. */
19343 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
19344 16, 64, 32, 64, 32, 128, -1);
19345 if (align_good
== FAIL
)
19349 unsigned alignbits
= 0;
19352 case 8: alignbits
= 0x1; break;
19353 case 16: alignbits
= 0x1; break;
19354 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
19357 inst
.instruction
|= alignbits
<< 4;
19364 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
19365 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
19366 inst
.instruction
|= 1 << (4 + logsize
);
19368 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
19369 inst
.instruction
|= logsize
<< 10;
19372 /* Encode single n-element structure to all lanes VLD<n> instructions. */
19375 do_neon_ld_dup (void)
19377 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
19378 int align_good
, do_alignment
= 0;
19380 if (et
.type
== NT_invtype
)
19383 switch ((inst
.instruction
>> 8) & 3)
19385 case 0: /* VLD1. */
19386 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
19387 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
19388 &do_alignment
, 16, 16, 32, 32, -1);
19389 if (align_good
== FAIL
)
19391 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
19394 case 2: inst
.instruction
|= 1 << 5; break;
19395 default: first_error (_("bad list length")); return;
19397 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19400 case 1: /* VLD2. */
19401 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
19402 &do_alignment
, 8, 16, 16, 32, 32, 64,
19404 if (align_good
== FAIL
)
19406 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
19407 _("bad list length"));
19408 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
19409 inst
.instruction
|= 1 << 5;
19410 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19413 case 2: /* VLD3. */
19414 constraint (inst
.operands
[1].immisalign
,
19415 _("can't use alignment with this instruction"));
19416 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
19417 _("bad list length"));
19418 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
19419 inst
.instruction
|= 1 << 5;
19420 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19423 case 3: /* VLD4. */
19425 int align
= inst
.operands
[1].imm
>> 8;
19426 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
19427 16, 64, 32, 64, 32, 128, -1);
19428 if (align_good
== FAIL
)
19430 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
19431 _("bad list length"));
19432 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
19433 inst
.instruction
|= 1 << 5;
19434 if (et
.size
== 32 && align
== 128)
19435 inst
.instruction
|= 0x3 << 6;
19437 inst
.instruction
|= neon_logbits (et
.size
) << 6;
19444 inst
.instruction
|= do_alignment
<< 4;
19447 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
19448 apart from bits [11:4]. */
19451 do_neon_ldx_stx (void)
19453 if (inst
.operands
[1].isreg
)
19454 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
19456 switch (NEON_LANE (inst
.operands
[0].imm
))
19458 case NEON_INTERLEAVE_LANES
:
19459 NEON_ENCODE (INTERLV
, inst
);
19460 do_neon_ld_st_interleave ();
19463 case NEON_ALL_LANES
:
19464 NEON_ENCODE (DUP
, inst
);
19465 if (inst
.instruction
== N_INV
)
19467 first_error ("only loads support such operands");
19474 NEON_ENCODE (LANE
, inst
);
19475 do_neon_ld_st_lane ();
19478 /* L bit comes from bit mask. */
19479 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19480 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19481 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
19483 if (inst
.operands
[1].postind
)
19485 int postreg
= inst
.operands
[1].imm
& 0xf;
19486 constraint (!inst
.operands
[1].immisreg
,
19487 _("post-index must be a register"));
19488 constraint (postreg
== 0xd || postreg
== 0xf,
19489 _("bad register for post-index"));
19490 inst
.instruction
|= postreg
;
19494 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
19495 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
19496 || inst
.relocs
[0].exp
.X_add_number
!= 0,
19499 if (inst
.operands
[1].writeback
)
19501 inst
.instruction
|= 0xd;
19504 inst
.instruction
|= 0xf;
19508 inst
.instruction
|= 0xf9000000;
19510 inst
.instruction
|= 0xf4000000;
19515 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
19517 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
19518 D register operands. */
19519 if (neon_shape_class
[rs
] == SC_DOUBLE
)
19520 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19523 NEON_ENCODE (FPV8
, inst
);
19525 if (rs
== NS_FFF
|| rs
== NS_HHH
)
19527 do_vfp_sp_dyadic ();
19529 /* ARMv8.2 fp16 instruction. */
19531 do_scalar_fp16_v82_encode ();
19534 do_vfp_dp_rd_rn_rm ();
19537 inst
.instruction
|= 0x100;
19539 inst
.instruction
|= 0xf0000000;
19545 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19547 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
19548 first_error (_("invalid instruction shape"));
19554 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19556 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
19559 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
19562 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
19566 do_vrint_1 (enum neon_cvt_mode mode
)
19568 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
19569 struct neon_type_el et
;
19574 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
19575 D register operands. */
19576 if (neon_shape_class
[rs
] == SC_DOUBLE
)
19577 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19580 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
19582 if (et
.type
!= NT_invtype
)
19584 /* VFP encodings. */
19585 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
19586 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
19587 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19589 NEON_ENCODE (FPV8
, inst
);
19590 if (rs
== NS_FF
|| rs
== NS_HH
)
19591 do_vfp_sp_monadic ();
19593 do_vfp_dp_rd_rm ();
19597 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
19598 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
19599 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
19600 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
19601 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
19602 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
19603 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
19607 inst
.instruction
|= (rs
== NS_DD
) << 8;
19608 do_vfp_cond_or_thumb ();
19610 /* ARMv8.2 fp16 vrint instruction. */
19612 do_scalar_fp16_v82_encode ();
19616 /* Neon encodings (or something broken...). */
19618 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
19620 if (et
.type
== NT_invtype
)
19623 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19624 NEON_ENCODE (FLOAT
, inst
);
19626 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
19629 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19630 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19631 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19632 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19633 inst
.instruction
|= neon_quad (rs
) << 6;
19634 /* Mask off the original size bits and reencode them. */
19635 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
19636 | neon_logbits (et
.size
) << 18);
19640 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
19641 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
19642 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
19643 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
19644 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
19645 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
19646 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
19651 inst
.instruction
|= 0xfc000000;
19653 inst
.instruction
|= 0xf0000000;
19660 do_vrint_1 (neon_cvt_mode_x
);
19666 do_vrint_1 (neon_cvt_mode_z
);
19672 do_vrint_1 (neon_cvt_mode_r
);
19678 do_vrint_1 (neon_cvt_mode_a
);
19684 do_vrint_1 (neon_cvt_mode_n
);
19690 do_vrint_1 (neon_cvt_mode_p
);
19696 do_vrint_1 (neon_cvt_mode_m
);
19700 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
19702 unsigned regno
= NEON_SCALAR_REG (opnd
);
19703 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
19705 if (elsize
== 16 && elno
< 2 && regno
< 16)
19706 return regno
| (elno
<< 4);
19707 else if (elsize
== 32 && elno
== 0)
19710 first_error (_("scalar out of range"));
19717 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
19718 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
19719 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
19720 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
19721 _("expression too complex"));
19722 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
19723 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
19724 _("immediate out of range"));
19727 if (check_simd_pred_availability (1, NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
19730 if (inst
.operands
[2].isscalar
)
19732 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19733 first_error (_("invalid instruction shape"));
19734 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
19735 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
19736 N_KEY
| N_F16
| N_F32
).size
;
19737 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
19739 inst
.instruction
= 0xfe000800;
19740 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19741 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19742 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19743 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19744 inst
.instruction
|= LOW4 (m
);
19745 inst
.instruction
|= HI1 (m
) << 5;
19746 inst
.instruction
|= neon_quad (rs
) << 6;
19747 inst
.instruction
|= rot
<< 20;
19748 inst
.instruction
|= (size
== 32) << 23;
19752 enum neon_shape rs
;
19753 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19754 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
19756 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19758 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
19759 N_KEY
| N_F16
| N_F32
).size
;
19760 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
19761 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
19762 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
19763 as_tsktsk (BAD_MVE_SRCDEST
);
19765 neon_three_same (neon_quad (rs
), 0, -1);
19766 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
19767 inst
.instruction
|= 0xfc200800;
19768 inst
.instruction
|= rot
<< 23;
19769 inst
.instruction
|= (size
== 32) << 20;
19776 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19777 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
19778 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
19779 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
19780 _("expression too complex"));
19782 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
19783 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
19784 enum neon_shape rs
;
19785 struct neon_type_el et
;
19786 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19788 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19789 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
19793 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
19794 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
19796 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
19797 as_tsktsk (_("Warning: 32-bit element size and same first and third "
19798 "operand makes instruction UNPREDICTABLE"));
19801 if (et
.type
== NT_invtype
)
19804 if (check_simd_pred_availability (et
.type
== NT_float
, NEON_CHECK_ARCH8
19808 if (et
.type
== NT_float
)
19810 neon_three_same (neon_quad (rs
), 0, -1);
19811 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
19812 inst
.instruction
|= 0xfc800800;
19813 inst
.instruction
|= (rot
== 270) << 24;
19814 inst
.instruction
|= (et
.size
== 32) << 20;
19818 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
19819 inst
.instruction
= 0xfe000f00;
19820 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19821 inst
.instruction
|= neon_logbits (et
.size
) << 20;
19822 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19823 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19824 inst
.instruction
|= (rot
== 270) << 12;
19825 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19826 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19827 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19832 /* Dot Product instructions encoding support. */
19835 do_neon_dotproduct (int unsigned_p
)
19837 enum neon_shape rs
;
19838 unsigned scalar_oprd2
= 0;
19841 if (inst
.cond
!= COND_ALWAYS
)
19842 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
19843 "is UNPREDICTABLE"));
19845 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19848 /* Dot Product instructions are in three-same D/Q register format or the third
19849 operand can be a scalar index register. */
19850 if (inst
.operands
[2].isscalar
)
19852 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
19853 high8
= 0xfe000000;
19854 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
19858 high8
= 0xfc000000;
19859 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
19863 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
19865 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
19867 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
19868 Product instruction, so we pass 0 as the "ubit" parameter. And the
19869 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
19870 neon_three_same (neon_quad (rs
), 0, 32);
19872 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
19873 different NEON three-same encoding. */
19874 inst
.instruction
&= 0x00ffffff;
19875 inst
.instruction
|= high8
;
19876 /* Encode 'U' bit which indicates signedness. */
19877 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
19878 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
19879 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
19880 the instruction encoding. */
19881 if (inst
.operands
[2].isscalar
)
19883 inst
.instruction
&= 0xffffffd0;
19884 inst
.instruction
|= LOW4 (scalar_oprd2
);
19885 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
19889 /* Dot Product instructions for signed integer. */
19892 do_neon_dotproduct_s (void)
19894 return do_neon_dotproduct (0);
19897 /* Dot Product instructions for unsigned integer. */
19900 do_neon_dotproduct_u (void)
19902 return do_neon_dotproduct (1);
19905 /* Crypto v1 instructions. */
19907 do_crypto_2op_1 (unsigned elttype
, int op
)
19909 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19911 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
19917 NEON_ENCODE (INTEGER
, inst
);
19918 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19919 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19920 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19921 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19923 inst
.instruction
|= op
<< 6;
19926 inst
.instruction
|= 0xfc000000;
19928 inst
.instruction
|= 0xf0000000;
19932 do_crypto_3op_1 (int u
, int op
)
19934 set_pred_insn_type (OUTSIDE_PRED_INSN
);
19936 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
19937 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
19942 NEON_ENCODE (INTEGER
, inst
);
19943 neon_three_same (1, u
, 8 << op
);
19949 do_crypto_2op_1 (N_8
, 0);
19955 do_crypto_2op_1 (N_8
, 1);
19961 do_crypto_2op_1 (N_8
, 2);
19967 do_crypto_2op_1 (N_8
, 3);
19973 do_crypto_3op_1 (0, 0);
19979 do_crypto_3op_1 (0, 1);
19985 do_crypto_3op_1 (0, 2);
19991 do_crypto_3op_1 (0, 3);
19997 do_crypto_3op_1 (1, 0);
20003 do_crypto_3op_1 (1, 1);
20007 do_sha256su1 (void)
20009 do_crypto_3op_1 (1, 2);
20015 do_crypto_2op_1 (N_32
, -1);
20021 do_crypto_2op_1 (N_32
, 0);
20025 do_sha256su0 (void)
20027 do_crypto_2op_1 (N_32
, 1);
20031 do_crc32_1 (unsigned int poly
, unsigned int sz
)
20033 unsigned int Rd
= inst
.operands
[0].reg
;
20034 unsigned int Rn
= inst
.operands
[1].reg
;
20035 unsigned int Rm
= inst
.operands
[2].reg
;
20037 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20038 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
20039 inst
.instruction
|= LOW4 (Rn
) << 16;
20040 inst
.instruction
|= LOW4 (Rm
);
20041 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
20042 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
20044 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
20045 as_warn (UNPRED_REG ("r15"));
20087 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20089 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
20090 do_vfp_sp_dp_cvt ();
20091 do_vfp_cond_or_thumb ();
20095 /* Overall per-instruction processing. */
20097 /* We need to be able to fix up arbitrary expressions in some statements.
20098 This is so that we can handle symbols that are an arbitrary distance from
20099 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
20100 which returns part of an address in a form which will be valid for
20101 a data instruction. We do this by pushing the expression into a symbol
20102 in the expr_section, and creating a fix for that. */
20105 fix_new_arm (fragS
* frag
,
20119 /* Create an absolute valued symbol, so we have something to
20120 refer to in the object file. Unfortunately for us, gas's
20121 generic expression parsing will already have folded out
20122 any use of .set foo/.type foo %function that may have
20123 been used to set type information of the target location,
20124 that's being specified symbolically. We have to presume
20125 the user knows what they are doing. */
20129 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
20131 symbol
= symbol_find_or_make (name
);
20132 S_SET_SEGMENT (symbol
, absolute_section
);
20133 symbol_set_frag (symbol
, &zero_address_frag
);
20134 S_SET_VALUE (symbol
, exp
->X_add_number
);
20135 exp
->X_op
= O_symbol
;
20136 exp
->X_add_symbol
= symbol
;
20137 exp
->X_add_number
= 0;
20143 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
20144 (enum bfd_reloc_code_real
) reloc
);
20148 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
20149 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
20153 /* Mark whether the fix is to a THUMB instruction, or an ARM
20155 new_fix
->tc_fix_data
= thumb_mode
;
20158 /* Create a frg for an instruction requiring relaxation. */
20160 output_relax_insn (void)
20166 /* The size of the instruction is unknown, so tie the debug info to the
20167 start of the instruction. */
20168 dwarf2_emit_insn (0);
20170 switch (inst
.relocs
[0].exp
.X_op
)
20173 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
20174 offset
= inst
.relocs
[0].exp
.X_add_number
;
20178 offset
= inst
.relocs
[0].exp
.X_add_number
;
20181 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
20185 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
20186 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
20187 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
20190 /* Write a 32-bit thumb instruction to buf. */
20192 put_thumb32_insn (char * buf
, unsigned long insn
)
20194 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
20195 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
20199 output_inst (const char * str
)
20205 as_bad ("%s -- `%s'", inst
.error
, str
);
20210 output_relax_insn ();
20213 if (inst
.size
== 0)
20216 to
= frag_more (inst
.size
);
20217 /* PR 9814: Record the thumb mode into the current frag so that we know
20218 what type of NOP padding to use, if necessary. We override any previous
20219 setting so that if the mode has changed then the NOPS that we use will
20220 match the encoding of the last instruction in the frag. */
20221 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
20223 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
20225 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
20226 put_thumb32_insn (to
, inst
.instruction
);
20228 else if (inst
.size
> INSN_SIZE
)
20230 gas_assert (inst
.size
== (2 * INSN_SIZE
));
20231 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
20232 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
20235 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
20238 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
20240 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
20241 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
20242 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
20243 inst
.relocs
[r
].type
);
20246 dwarf2_emit_insn (inst
.size
);
20250 output_it_inst (int cond
, int mask
, char * to
)
20252 unsigned long instruction
= 0xbf00;
20255 instruction
|= mask
;
20256 instruction
|= cond
<< 4;
20260 to
= frag_more (2);
20262 dwarf2_emit_insn (2);
20266 md_number_to_chars (to
, instruction
, 2);
20271 /* Tag values used in struct asm_opcode's tag field. */
20274 OT_unconditional
, /* Instruction cannot be conditionalized.
20275 The ARM condition field is still 0xE. */
20276 OT_unconditionalF
, /* Instruction cannot be conditionalized
20277 and carries 0xF in its ARM condition field. */
20278 OT_csuffix
, /* Instruction takes a conditional suffix. */
20279 OT_csuffixF
, /* Some forms of the instruction take a scalar
20280 conditional suffix, others place 0xF where the
20281 condition field would be, others take a vector
20282 conditional suffix. */
20283 OT_cinfix3
, /* Instruction takes a conditional infix,
20284 beginning at character index 3. (In
20285 unified mode, it becomes a suffix.) */
20286 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
20287 tsts, cmps, cmns, and teqs. */
20288 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
20289 character index 3, even in unified mode. Used for
20290 legacy instructions where suffix and infix forms
20291 may be ambiguous. */
20292 OT_csuf_or_in3
, /* Instruction takes either a conditional
20293 suffix or an infix at character index 3. */
20294 OT_odd_infix_unc
, /* This is the unconditional variant of an
20295 instruction that takes a conditional infix
20296 at an unusual position. In unified mode,
20297 this variant will accept a suffix. */
20298 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
20299 are the conditional variants of instructions that
20300 take conditional infixes in unusual positions.
20301 The infix appears at character index
20302 (tag - OT_odd_infix_0). These are not accepted
20303 in unified mode. */
20306 /* Subroutine of md_assemble, responsible for looking up the primary
20307 opcode from the mnemonic the user wrote. STR points to the
20308 beginning of the mnemonic.
20310 This is not simply a hash table lookup, because of conditional
20311 variants. Most instructions have conditional variants, which are
20312 expressed with a _conditional affix_ to the mnemonic. If we were
20313 to encode each conditional variant as a literal string in the opcode
20314 table, it would have approximately 20,000 entries.
20316 Most mnemonics take this affix as a suffix, and in unified syntax,
20317 'most' is upgraded to 'all'. However, in the divided syntax, some
20318 instructions take the affix as an infix, notably the s-variants of
20319 the arithmetic instructions. Of those instructions, all but six
20320 have the infix appear after the third character of the mnemonic.
20322 Accordingly, the algorithm for looking up primary opcodes given
20325 1. Look up the identifier in the opcode table.
20326 If we find a match, go to step U.
20328 2. Look up the last two characters of the identifier in the
20329 conditions table. If we find a match, look up the first N-2
20330 characters of the identifier in the opcode table. If we
20331 find a match, go to step CE.
20333 3. Look up the fourth and fifth characters of the identifier in
20334 the conditions table. If we find a match, extract those
20335 characters from the identifier, and look up the remaining
20336 characters in the opcode table. If we find a match, go
20341 U. Examine the tag field of the opcode structure, in case this is
20342 one of the six instructions with its conditional infix in an
20343 unusual place. If it is, the tag tells us where to find the
20344 infix; look it up in the conditions table and set inst.cond
20345 accordingly. Otherwise, this is an unconditional instruction.
20346 Again set inst.cond accordingly. Return the opcode structure.
20348 CE. Examine the tag field to make sure this is an instruction that
20349 should receive a conditional suffix. If it is not, fail.
20350 Otherwise, set inst.cond from the suffix we already looked up,
20351 and return the opcode structure.
20353 CM. Examine the tag field to make sure this is an instruction that
20354 should receive a conditional infix after the third character.
20355 If it is not, fail. Otherwise, undo the edits to the current
20356 line of input and proceed as for case CE. */
20358 static const struct asm_opcode
*
20359 opcode_lookup (char **str
)
20363 const struct asm_opcode
*opcode
;
20364 const struct asm_cond
*cond
;
20367 /* Scan up to the end of the mnemonic, which must end in white space,
20368 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
20369 for (base
= end
= *str
; *end
!= '\0'; end
++)
20370 if (*end
== ' ' || *end
== '.')
20376 /* Handle a possible width suffix and/or Neon type suffix. */
20381 /* The .w and .n suffixes are only valid if the unified syntax is in
20383 if (unified_syntax
&& end
[1] == 'w')
20385 else if (unified_syntax
&& end
[1] == 'n')
20390 inst
.vectype
.elems
= 0;
20392 *str
= end
+ offset
;
20394 if (end
[offset
] == '.')
20396 /* See if we have a Neon type suffix (possible in either unified or
20397 non-unified ARM syntax mode). */
20398 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
20401 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
20407 /* Look for unaffixed or special-case affixed mnemonic. */
20408 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
20413 if (opcode
->tag
< OT_odd_infix_0
)
20415 inst
.cond
= COND_ALWAYS
;
20419 if (warn_on_deprecated
&& unified_syntax
)
20420 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
20421 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
20422 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
20425 inst
.cond
= cond
->value
;
20428 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20430 /* Cannot have a conditional suffix on a mnemonic of less than a character.
20432 if (end
- base
< 2)
20435 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
20436 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
20438 /* If this opcode can not be vector predicated then don't accept it with a
20439 vector predication code. */
20440 if (opcode
&& !opcode
->mayBeVecPred
)
20443 if (!opcode
|| !cond
)
20445 /* Cannot have a conditional suffix on a mnemonic of less than two
20447 if (end
- base
< 3)
20450 /* Look for suffixed mnemonic. */
20452 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
20453 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
20457 if (opcode
&& cond
)
20460 switch (opcode
->tag
)
20462 case OT_cinfix3_legacy
:
20463 /* Ignore conditional suffixes matched on infix only mnemonics. */
20467 case OT_cinfix3_deprecated
:
20468 case OT_odd_infix_unc
:
20469 if (!unified_syntax
)
20471 /* Fall through. */
20475 case OT_csuf_or_in3
:
20476 inst
.cond
= cond
->value
;
20479 case OT_unconditional
:
20480 case OT_unconditionalF
:
20482 inst
.cond
= cond
->value
;
20485 /* Delayed diagnostic. */
20486 inst
.error
= BAD_COND
;
20487 inst
.cond
= COND_ALWAYS
;
20496 /* Cannot have a usual-position infix on a mnemonic of less than
20497 six characters (five would be a suffix). */
20498 if (end
- base
< 6)
20501 /* Look for infixed mnemonic in the usual position. */
20503 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
20507 memcpy (save
, affix
, 2);
20508 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
20509 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
20511 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
20512 memcpy (affix
, save
, 2);
20515 && (opcode
->tag
== OT_cinfix3
20516 || opcode
->tag
== OT_cinfix3_deprecated
20517 || opcode
->tag
== OT_csuf_or_in3
20518 || opcode
->tag
== OT_cinfix3_legacy
))
20521 if (warn_on_deprecated
&& unified_syntax
20522 && (opcode
->tag
== OT_cinfix3
20523 || opcode
->tag
== OT_cinfix3_deprecated
))
20524 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
20526 inst
.cond
= cond
->value
;
20533 /* This function generates an initial IT instruction, leaving its block
20534 virtually open for the new instructions. Eventually,
20535 the mask will be updated by now_pred_add_mask () each time
20536 a new instruction needs to be included in the IT block.
20537 Finally, the block is closed with close_automatic_it_block ().
20538 The block closure can be requested either from md_assemble (),
20539 a tencode (), or due to a label hook. */
20542 new_automatic_it_block (int cond
)
20544 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
20545 now_pred
.mask
= 0x18;
20546 now_pred
.cc
= cond
;
20547 now_pred
.block_length
= 1;
20548 mapping_state (MAP_THUMB
);
20549 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
20550 now_pred
.warn_deprecated
= FALSE
;
20551 now_pred
.insn_cond
= TRUE
;
20554 /* Close an automatic IT block.
20555 See comments in new_automatic_it_block (). */
20558 close_automatic_it_block (void)
20560 now_pred
.mask
= 0x10;
20561 now_pred
.block_length
= 0;
20564 /* Update the mask of the current automatically-generated IT
20565 instruction. See comments in new_automatic_it_block (). */
20568 now_pred_add_mask (int cond
)
20570 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
20571 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
20572 | ((bitvalue) << (nbit)))
20573 const int resulting_bit
= (cond
& 1);
20575 now_pred
.mask
&= 0xf;
20576 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
20578 (5 - now_pred
.block_length
));
20579 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
20581 ((5 - now_pred
.block_length
) - 1));
20582 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
20585 #undef SET_BIT_VALUE
20588 /* The IT blocks handling machinery is accessed through the these functions:
20589 it_fsm_pre_encode () from md_assemble ()
20590 set_pred_insn_type () optional, from the tencode functions
20591 set_pred_insn_type_last () ditto
20592 in_pred_block () ditto
20593 it_fsm_post_encode () from md_assemble ()
20594 force_automatic_it_block_close () from label handling functions
20597 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
20598 initializing the IT insn type with a generic initial value depending
20599 on the inst.condition.
20600 2) During the tencode function, two things may happen:
20601 a) The tencode function overrides the IT insn type by
20602 calling either set_pred_insn_type (type) or
20603 set_pred_insn_type_last ().
20604 b) The tencode function queries the IT block state by
20605 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
20607 Both set_pred_insn_type and in_pred_block run the internal FSM state
20608 handling function (handle_pred_state), because: a) setting the IT insn
20609 type may incur in an invalid state (exiting the function),
20610 and b) querying the state requires the FSM to be updated.
20611 Specifically we want to avoid creating an IT block for conditional
20612 branches, so it_fsm_pre_encode is actually a guess and we can't
20613 determine whether an IT block is required until the tencode () routine
20614 has decided what type of instruction this actually it.
20615 Because of this, if set_pred_insn_type and in_pred_block have to be
20616 used, set_pred_insn_type has to be called first.
20618 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
20619 that determines the insn IT type depending on the inst.cond code.
20620 When a tencode () routine encodes an instruction that can be
20621 either outside an IT block, or, in the case of being inside, has to be
20622 the last one, set_pred_insn_type_last () will determine the proper
20623 IT instruction type based on the inst.cond code. Otherwise,
20624 set_pred_insn_type can be called for overriding that logic or
20625 for covering other cases.
20627 Calling handle_pred_state () may not transition the IT block state to
20628 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
20629 still queried. Instead, if the FSM determines that the state should
20630 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
20631 after the tencode () function: that's what it_fsm_post_encode () does.
20633 Since in_pred_block () calls the state handling function to get an
20634 updated state, an error may occur (due to invalid insns combination).
20635 In that case, inst.error is set.
20636 Therefore, inst.error has to be checked after the execution of
20637 the tencode () routine.
20639 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
20640 any pending state change (if any) that didn't take place in
20641 handle_pred_state () as explained above. */
20644 it_fsm_pre_encode (void)
20646 if (inst
.cond
!= COND_ALWAYS
)
20647 inst
.pred_insn_type
= INSIDE_IT_INSN
;
20649 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
20651 now_pred
.state_handled
= 0;
20654 /* IT state FSM handling function. */
20655 /* MVE instructions and non-MVE instructions are handled differently because of
20656 the introduction of VPT blocks.
20657 Specifications say that any non-MVE instruction inside a VPT block is
20658 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
20659 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
20660 few exceptions we have MVE_UNPREDICABLE_INSN.
20661 The error messages provided depending on the different combinations possible
20662 are described in the cases below:
20663 For 'most' MVE instructions:
20664 1) In an IT block, with an IT code: syntax error
20665 2) In an IT block, with a VPT code: error: must be in a VPT block
20666 3) In an IT block, with no code: warning: UNPREDICTABLE
20667 4) In a VPT block, with an IT code: syntax error
20668 5) In a VPT block, with a VPT code: OK!
20669 6) In a VPT block, with no code: error: missing code
20670 7) Outside a pred block, with an IT code: error: syntax error
20671 8) Outside a pred block, with a VPT code: error: should be in a VPT block
20672 9) Outside a pred block, with no code: OK!
20673 For non-MVE instructions:
20674 10) In an IT block, with an IT code: OK!
20675 11) In an IT block, with a VPT code: syntax error
20676 12) In an IT block, with no code: error: missing code
20677 13) In a VPT block, with an IT code: error: should be in an IT block
20678 14) In a VPT block, with a VPT code: syntax error
20679 15) In a VPT block, with no code: UNPREDICTABLE
20680 16) Outside a pred block, with an IT code: error: should be in an IT block
20681 17) Outside a pred block, with a VPT code: syntax error
20682 18) Outside a pred block, with no code: OK!
20687 handle_pred_state (void)
20689 now_pred
.state_handled
= 1;
20690 now_pred
.insn_cond
= FALSE
;
20692 switch (now_pred
.state
)
20694 case OUTSIDE_PRED_BLOCK
:
20695 switch (inst
.pred_insn_type
)
20697 case MVE_UNPREDICABLE_INSN
:
20698 case MVE_OUTSIDE_PRED_INSN
:
20699 if (inst
.cond
< COND_ALWAYS
)
20701 /* Case 7: Outside a pred block, with an IT code: error: syntax
20703 inst
.error
= BAD_SYNTAX
;
20706 /* Case 9: Outside a pred block, with no code: OK! */
20708 case OUTSIDE_PRED_INSN
:
20709 if (inst
.cond
> COND_ALWAYS
)
20711 /* Case 17: Outside a pred block, with a VPT code: syntax error.
20713 inst
.error
= BAD_SYNTAX
;
20716 /* Case 18: Outside a pred block, with no code: OK! */
20719 case INSIDE_VPT_INSN
:
20720 /* Case 8: Outside a pred block, with a VPT code: error: should be in
20722 inst
.error
= BAD_OUT_VPT
;
20725 case INSIDE_IT_INSN
:
20726 case INSIDE_IT_LAST_INSN
:
20727 if (inst
.cond
< COND_ALWAYS
)
20729 /* Case 16: Outside a pred block, with an IT code: error: should
20730 be in an IT block. */
20731 if (thumb_mode
== 0)
20734 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
20735 as_tsktsk (_("Warning: conditional outside an IT block"\
20740 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
20741 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
20743 /* Automatically generate the IT instruction. */
20744 new_automatic_it_block (inst
.cond
);
20745 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
20746 close_automatic_it_block ();
20750 inst
.error
= BAD_OUT_IT
;
20756 else if (inst
.cond
> COND_ALWAYS
)
20758 /* Case 17: Outside a pred block, with a VPT code: syntax error.
20760 inst
.error
= BAD_SYNTAX
;
20765 case IF_INSIDE_IT_LAST_INSN
:
20766 case NEUTRAL_IT_INSN
:
20770 if (inst
.cond
!= COND_ALWAYS
)
20771 first_error (BAD_SYNTAX
);
20772 now_pred
.state
= MANUAL_PRED_BLOCK
;
20773 now_pred
.block_length
= 0;
20774 now_pred
.type
= VECTOR_PRED
;
20778 now_pred
.state
= MANUAL_PRED_BLOCK
;
20779 now_pred
.block_length
= 0;
20780 now_pred
.type
= SCALAR_PRED
;
20785 case AUTOMATIC_PRED_BLOCK
:
20786 /* Three things may happen now:
20787 a) We should increment current it block size;
20788 b) We should close current it block (closing insn or 4 insns);
20789 c) We should close current it block and start a new one (due
20790 to incompatible conditions or
20791 4 insns-length block reached). */
20793 switch (inst
.pred_insn_type
)
20795 case INSIDE_VPT_INSN
:
20797 case MVE_UNPREDICABLE_INSN
:
20798 case MVE_OUTSIDE_PRED_INSN
:
20800 case OUTSIDE_PRED_INSN
:
20801 /* The closure of the block shall happen immediately,
20802 so any in_pred_block () call reports the block as closed. */
20803 force_automatic_it_block_close ();
20806 case INSIDE_IT_INSN
:
20807 case INSIDE_IT_LAST_INSN
:
20808 case IF_INSIDE_IT_LAST_INSN
:
20809 now_pred
.block_length
++;
20811 if (now_pred
.block_length
> 4
20812 || !now_pred_compatible (inst
.cond
))
20814 force_automatic_it_block_close ();
20815 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
20816 new_automatic_it_block (inst
.cond
);
20820 now_pred
.insn_cond
= TRUE
;
20821 now_pred_add_mask (inst
.cond
);
20824 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
20825 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
20826 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
20827 close_automatic_it_block ();
20830 case NEUTRAL_IT_INSN
:
20831 now_pred
.block_length
++;
20832 now_pred
.insn_cond
= TRUE
;
20834 if (now_pred
.block_length
> 4)
20835 force_automatic_it_block_close ();
20837 now_pred_add_mask (now_pred
.cc
& 1);
20841 close_automatic_it_block ();
20842 now_pred
.state
= MANUAL_PRED_BLOCK
;
20847 case MANUAL_PRED_BLOCK
:
20850 if (now_pred
.type
== SCALAR_PRED
)
20852 /* Check conditional suffixes. */
20853 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
20854 now_pred
.mask
<<= 1;
20855 now_pred
.mask
&= 0x1f;
20856 is_last
= (now_pred
.mask
== 0x10);
20860 now_pred
.cc
^= (now_pred
.mask
>> 4);
20861 cond
= now_pred
.cc
+ 0xf;
20862 now_pred
.mask
<<= 1;
20863 now_pred
.mask
&= 0x1f;
20864 is_last
= now_pred
.mask
== 0x10;
20866 now_pred
.insn_cond
= TRUE
;
20868 switch (inst
.pred_insn_type
)
20870 case OUTSIDE_PRED_INSN
:
20871 if (now_pred
.type
== SCALAR_PRED
)
20873 if (inst
.cond
== COND_ALWAYS
)
20875 /* Case 12: In an IT block, with no code: error: missing
20877 inst
.error
= BAD_NOT_IT
;
20880 else if (inst
.cond
> COND_ALWAYS
)
20882 /* Case 11: In an IT block, with a VPT code: syntax error.
20884 inst
.error
= BAD_SYNTAX
;
20887 else if (thumb_mode
)
20889 /* This is for some special cases where a non-MVE
20890 instruction is not allowed in an IT block, such as cbz,
20891 but are put into one with a condition code.
20892 You could argue this should be a syntax error, but we
20893 gave the 'not allowed in IT block' diagnostic in the
20894 past so we will keep doing so. */
20895 inst
.error
= BAD_NOT_IT
;
20902 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
20903 as_tsktsk (MVE_NOT_VPT
);
20906 case MVE_OUTSIDE_PRED_INSN
:
20907 if (now_pred
.type
== SCALAR_PRED
)
20909 if (inst
.cond
== COND_ALWAYS
)
20911 /* Case 3: In an IT block, with no code: warning:
20913 as_tsktsk (MVE_NOT_IT
);
20916 else if (inst
.cond
< COND_ALWAYS
)
20918 /* Case 1: In an IT block, with an IT code: syntax error.
20920 inst
.error
= BAD_SYNTAX
;
20928 if (inst
.cond
< COND_ALWAYS
)
20930 /* Case 4: In a VPT block, with an IT code: syntax error.
20932 inst
.error
= BAD_SYNTAX
;
20935 else if (inst
.cond
== COND_ALWAYS
)
20937 /* Case 6: In a VPT block, with no code: error: missing
20939 inst
.error
= BAD_NOT_VPT
;
20947 case MVE_UNPREDICABLE_INSN
:
20948 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
20950 case INSIDE_IT_INSN
:
20951 if (inst
.cond
> COND_ALWAYS
)
20953 /* Case 11: In an IT block, with a VPT code: syntax error. */
20954 /* Case 14: In a VPT block, with a VPT code: syntax error. */
20955 inst
.error
= BAD_SYNTAX
;
20958 else if (now_pred
.type
== SCALAR_PRED
)
20960 /* Case 10: In an IT block, with an IT code: OK! */
20961 if (cond
!= inst
.cond
)
20963 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
20970 /* Case 13: In a VPT block, with an IT code: error: should be
20972 inst
.error
= BAD_OUT_IT
;
20977 case INSIDE_VPT_INSN
:
20978 if (now_pred
.type
== SCALAR_PRED
)
20980 /* Case 2: In an IT block, with a VPT code: error: must be in a
20982 inst
.error
= BAD_OUT_VPT
;
20985 /* Case 5: In a VPT block, with a VPT code: OK! */
20986 else if (cond
!= inst
.cond
)
20988 inst
.error
= BAD_VPT_COND
;
20992 case INSIDE_IT_LAST_INSN
:
20993 case IF_INSIDE_IT_LAST_INSN
:
20994 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
20996 /* Case 4: In a VPT block, with an IT code: syntax error. */
20997 /* Case 11: In an IT block, with a VPT code: syntax error. */
20998 inst
.error
= BAD_SYNTAX
;
21001 else if (cond
!= inst
.cond
)
21003 inst
.error
= BAD_IT_COND
;
21008 inst
.error
= BAD_BRANCH
;
21013 case NEUTRAL_IT_INSN
:
21014 /* The BKPT instruction is unconditional even in a IT or VPT
21019 if (now_pred
.type
== SCALAR_PRED
)
21021 inst
.error
= BAD_IT_IT
;
21024 /* fall through. */
21026 if (inst
.cond
== COND_ALWAYS
)
21028 /* Executing a VPT/VPST instruction inside an IT block or a
21029 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
21031 if (now_pred
.type
== SCALAR_PRED
)
21032 as_tsktsk (MVE_NOT_IT
);
21034 as_tsktsk (MVE_NOT_VPT
);
21039 /* VPT/VPST do not accept condition codes. */
21040 inst
.error
= BAD_SYNTAX
;
21051 struct depr_insn_mask
21053 unsigned long pattern
;
21054 unsigned long mask
;
21055 const char* description
;
21058 /* List of 16-bit instruction patterns deprecated in an IT block in
21060 static const struct depr_insn_mask depr_it_insns
[] = {
21061 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
21062 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
21063 { 0xa000, 0xb800, N_("ADR") },
21064 { 0x4800, 0xf800, N_("Literal loads") },
21065 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
21066 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
21067 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
21068 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
21069 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
21074 it_fsm_post_encode (void)
21078 if (!now_pred
.state_handled
)
21079 handle_pred_state ();
21081 if (now_pred
.insn_cond
21082 && !now_pred
.warn_deprecated
21083 && warn_on_deprecated
21084 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
21085 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
21087 if (inst
.instruction
>= 0x10000)
21089 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
21090 "performance deprecated in ARMv8-A and ARMv8-R"));
21091 now_pred
.warn_deprecated
= TRUE
;
21095 const struct depr_insn_mask
*p
= depr_it_insns
;
21097 while (p
->mask
!= 0)
21099 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
21101 as_tsktsk (_("IT blocks containing 16-bit Thumb "
21102 "instructions of the following class are "
21103 "performance deprecated in ARMv8-A and "
21104 "ARMv8-R: %s"), p
->description
);
21105 now_pred
.warn_deprecated
= TRUE
;
21113 if (now_pred
.block_length
> 1)
21115 as_tsktsk (_("IT blocks containing more than one conditional "
21116 "instruction are performance deprecated in ARMv8-A and "
21118 now_pred
.warn_deprecated
= TRUE
;
21122 is_last
= (now_pred
.mask
== 0x10);
21125 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
21131 force_automatic_it_block_close (void)
21133 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
21135 close_automatic_it_block ();
21136 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
21142 in_pred_block (void)
21144 if (!now_pred
.state_handled
)
21145 handle_pred_state ();
21147 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
21150 /* Whether OPCODE only has T32 encoding. Since this function is only used by
21151 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
21152 here, hence the "known" in the function name. */
21155 known_t32_only_insn (const struct asm_opcode
*opcode
)
21157 /* Original Thumb-1 wide instruction. */
21158 if (opcode
->tencode
== do_t_blx
21159 || opcode
->tencode
== do_t_branch23
21160 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
21161 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
21164 /* Wide-only instruction added to ARMv8-M Baseline. */
21165 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
21166 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
21167 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
21168 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
21174 /* Whether wide instruction variant can be used if available for a valid OPCODE
21178 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
21180 if (known_t32_only_insn (opcode
))
21183 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
21184 of variant T3 of B.W is checked in do_t_branch. */
21185 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
21186 && opcode
->tencode
== do_t_branch
)
21189 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
21190 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
21191 && opcode
->tencode
== do_t_mov_cmp
21192 /* Make sure CMP instruction is not affected. */
21193 && opcode
->aencode
== do_mov
)
21196 /* Wide instruction variants of all instructions with narrow *and* wide
21197 variants become available with ARMv6t2. Other opcodes are either
21198 narrow-only or wide-only and are thus available if OPCODE is valid. */
21199 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
21202 /* OPCODE with narrow only instruction variant or wide variant not
21208 md_assemble (char *str
)
21211 const struct asm_opcode
* opcode
;
21213 /* Align the previous label if needed. */
21214 if (last_label_seen
!= NULL
)
21216 symbol_set_frag (last_label_seen
, frag_now
);
21217 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
21218 S_SET_SEGMENT (last_label_seen
, now_seg
);
21221 memset (&inst
, '\0', sizeof (inst
));
21223 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
21224 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
21226 opcode
= opcode_lookup (&p
);
21229 /* It wasn't an instruction, but it might be a register alias of
21230 the form alias .req reg, or a Neon .dn/.qn directive. */
21231 if (! create_register_alias (str
, p
)
21232 && ! create_neon_reg_alias (str
, p
))
21233 as_bad (_("bad instruction `%s'"), str
);
21238 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
21239 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
21241 /* The value which unconditional instructions should have in place of the
21242 condition field. */
21243 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
21247 arm_feature_set variant
;
21249 variant
= cpu_variant
;
21250 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
21251 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
21252 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
21253 /* Check that this instruction is supported for this CPU. */
21254 if (!opcode
->tvariant
21255 || (thumb_mode
== 1
21256 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
21258 if (opcode
->tencode
== do_t_swi
)
21259 as_bad (_("SVC is not permitted on this architecture"));
21261 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
21264 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
21265 && opcode
->tencode
!= do_t_branch
)
21267 as_bad (_("Thumb does not support conditional execution"));
21271 /* Two things are addressed here:
21272 1) Implicit require narrow instructions on Thumb-1.
21273 This avoids relaxation accidentally introducing Thumb-2
21275 2) Reject wide instructions in non Thumb-2 cores.
21277 Only instructions with narrow and wide variants need to be handled
21278 but selecting all non wide-only instructions is easier. */
21279 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
21280 && !t32_insn_ok (variant
, opcode
))
21282 if (inst
.size_req
== 0)
21284 else if (inst
.size_req
== 4)
21286 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
21287 as_bad (_("selected processor does not support 32bit wide "
21288 "variant of instruction `%s'"), str
);
21290 as_bad (_("selected processor does not support `%s' in "
21291 "Thumb-2 mode"), str
);
21296 inst
.instruction
= opcode
->tvalue
;
21298 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
21300 /* Prepare the pred_insn_type for those encodings that don't set
21302 it_fsm_pre_encode ();
21304 opcode
->tencode ();
21306 it_fsm_post_encode ();
21309 if (!(inst
.error
|| inst
.relax
))
21311 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
21312 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
21313 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
21315 as_bad (_("cannot honor width suffix -- `%s'"), str
);
21320 /* Something has gone badly wrong if we try to relax a fixed size
21322 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
21324 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
21325 *opcode
->tvariant
);
21326 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
21327 set those bits when Thumb-2 32-bit instructions are seen. The impact
21328 of relaxable instructions will be considered later after we finish all
21330 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
21331 variant
= arm_arch_none
;
21333 variant
= cpu_variant
;
21334 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
21335 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
21338 check_neon_suffixes
;
21342 mapping_state (MAP_THUMB
);
21345 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21349 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
21350 is_bx
= (opcode
->aencode
== do_bx
);
21352 /* Check that this instruction is supported for this CPU. */
21353 if (!(is_bx
&& fix_v4bx
)
21354 && !(opcode
->avariant
&&
21355 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
21357 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
21362 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
21366 inst
.instruction
= opcode
->avalue
;
21367 if (opcode
->tag
== OT_unconditionalF
)
21368 inst
.instruction
|= 0xFU
<< 28;
21370 inst
.instruction
|= inst
.cond
<< 28;
21371 inst
.size
= INSN_SIZE
;
21372 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
21374 it_fsm_pre_encode ();
21375 opcode
->aencode ();
21376 it_fsm_post_encode ();
21378 /* Arm mode bx is marked as both v4T and v5 because it's still required
21379 on a hypothetical non-thumb v5 core. */
21381 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
21383 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
21384 *opcode
->avariant
);
21386 check_neon_suffixes
;
21390 mapping_state (MAP_ARM
);
21395 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
21403 check_pred_blocks_finished (void)
21408 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
21409 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
21410 == MANUAL_PRED_BLOCK
)
21412 if (now_pred
.type
== SCALAR_PRED
)
21413 as_warn (_("section '%s' finished with an open IT block."),
21416 as_warn (_("section '%s' finished with an open VPT/VPST block."),
21420 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
21422 if (now_pred
.type
== SCALAR_PRED
)
21423 as_warn (_("file finished with an open IT block."));
21425 as_warn (_("file finished with an open VPT/VPST block."));
21430 /* Various frobbings of labels and their addresses. */
21433 arm_start_line_hook (void)
21435 last_label_seen
= NULL
;
21439 arm_frob_label (symbolS
* sym
)
21441 last_label_seen
= sym
;
21443 ARM_SET_THUMB (sym
, thumb_mode
);
21445 #if defined OBJ_COFF || defined OBJ_ELF
21446 ARM_SET_INTERWORK (sym
, support_interwork
);
21449 force_automatic_it_block_close ();
21451 /* Note - do not allow local symbols (.Lxxx) to be labelled
21452 as Thumb functions. This is because these labels, whilst
21453 they exist inside Thumb code, are not the entry points for
21454 possible ARM->Thumb calls. Also, these labels can be used
21455 as part of a computed goto or switch statement. eg gcc
21456 can generate code that looks like this:
21458 ldr r2, [pc, .Laaa]
21468 The first instruction loads the address of the jump table.
21469 The second instruction converts a table index into a byte offset.
21470 The third instruction gets the jump address out of the table.
21471 The fourth instruction performs the jump.
21473 If the address stored at .Laaa is that of a symbol which has the
21474 Thumb_Func bit set, then the linker will arrange for this address
21475 to have the bottom bit set, which in turn would mean that the
21476 address computation performed by the third instruction would end
21477 up with the bottom bit set. Since the ARM is capable of unaligned
21478 word loads, the instruction would then load the incorrect address
21479 out of the jump table, and chaos would ensue. */
21480 if (label_is_thumb_function_name
21481 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
21482 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
21484 /* When the address of a Thumb function is taken the bottom
21485 bit of that address should be set. This will allow
21486 interworking between Arm and Thumb functions to work
21489 THUMB_SET_FUNC (sym
, 1);
21491 label_is_thumb_function_name
= FALSE
;
21494 dwarf2_emit_label (sym
);
21498 arm_data_in_code (void)
21500 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
21502 *input_line_pointer
= '/';
21503 input_line_pointer
+= 5;
21504 *input_line_pointer
= 0;
21512 arm_canonicalize_symbol_name (char * name
)
21516 if (thumb_mode
&& (len
= strlen (name
)) > 5
21517 && streq (name
+ len
- 5, "/data"))
21518 *(name
+ len
- 5) = 0;
21523 /* Table of all register names defined by default. The user can
21524 define additional names with .req. Note that all register names
21525 should appear in both upper and lowercase variants. Some registers
21526 also have mixed-case names. */
21528 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
21529 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
21530 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
21531 #define REGSET(p,t) \
21532 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
21533 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
21534 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
21535 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
21536 #define REGSETH(p,t) \
21537 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
21538 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
21539 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
21540 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
21541 #define REGSET2(p,t) \
21542 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
21543 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
21544 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
21545 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
21546 #define SPLRBANK(base,bank,t) \
21547 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
21548 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
21549 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
21550 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
21551 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
21552 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
21554 static const struct reg_entry reg_names
[] =
21556 /* ARM integer registers. */
21557 REGSET(r
, RN
), REGSET(R
, RN
),
21559 /* ATPCS synonyms. */
21560 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
21561 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
21562 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
21564 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
21565 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
21566 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
21568 /* Well-known aliases. */
21569 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
21570 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
21572 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
21573 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
21575 /* Defining the new Zero register from ARMv8.1-M. */
21579 /* Coprocessor numbers. */
21580 REGSET(p
, CP
), REGSET(P
, CP
),
21582 /* Coprocessor register numbers. The "cr" variants are for backward
21584 REGSET(c
, CN
), REGSET(C
, CN
),
21585 REGSET(cr
, CN
), REGSET(CR
, CN
),
21587 /* ARM banked registers. */
21588 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
21589 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
21590 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
21591 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
21592 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
21593 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
21594 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
21596 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
21597 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
21598 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
21599 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
21600 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
21601 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
21602 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
21603 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
21605 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
21606 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
21607 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
21608 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
21609 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
21610 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
21611 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
21612 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
21613 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
21615 /* FPA registers. */
21616 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
21617 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
21619 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
21620 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
21622 /* VFP SP registers. */
21623 REGSET(s
,VFS
), REGSET(S
,VFS
),
21624 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
21626 /* VFP DP Registers. */
21627 REGSET(d
,VFD
), REGSET(D
,VFD
),
21628 /* Extra Neon DP registers. */
21629 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
21631 /* Neon QP registers. */
21632 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
21634 /* VFP control registers. */
21635 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
21636 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
21637 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
21638 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
21639 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
21640 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
21641 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
21643 /* Maverick DSP coprocessor registers. */
21644 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
21645 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
21647 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
21648 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
21649 REGDEF(dspsc
,0,DSPSC
),
21651 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
21652 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
21653 REGDEF(DSPSC
,0,DSPSC
),
21655 /* iWMMXt data registers - p0, c0-15. */
21656 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
21658 /* iWMMXt control registers - p1, c0-3. */
21659 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
21660 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
21661 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
21662 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
21664 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
21665 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
21666 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
21667 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
21668 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
21670 /* XScale accumulator registers. */
21671 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
21677 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
21678 within psr_required_here. */
21679 static const struct asm_psr psrs
[] =
21681 /* Backward compatibility notation. Note that "all" is no longer
21682 truly all possible PSR bits. */
21683 {"all", PSR_c
| PSR_f
},
21687 /* Individual flags. */
21693 /* Combinations of flags. */
21694 {"fs", PSR_f
| PSR_s
},
21695 {"fx", PSR_f
| PSR_x
},
21696 {"fc", PSR_f
| PSR_c
},
21697 {"sf", PSR_s
| PSR_f
},
21698 {"sx", PSR_s
| PSR_x
},
21699 {"sc", PSR_s
| PSR_c
},
21700 {"xf", PSR_x
| PSR_f
},
21701 {"xs", PSR_x
| PSR_s
},
21702 {"xc", PSR_x
| PSR_c
},
21703 {"cf", PSR_c
| PSR_f
},
21704 {"cs", PSR_c
| PSR_s
},
21705 {"cx", PSR_c
| PSR_x
},
21706 {"fsx", PSR_f
| PSR_s
| PSR_x
},
21707 {"fsc", PSR_f
| PSR_s
| PSR_c
},
21708 {"fxs", PSR_f
| PSR_x
| PSR_s
},
21709 {"fxc", PSR_f
| PSR_x
| PSR_c
},
21710 {"fcs", PSR_f
| PSR_c
| PSR_s
},
21711 {"fcx", PSR_f
| PSR_c
| PSR_x
},
21712 {"sfx", PSR_s
| PSR_f
| PSR_x
},
21713 {"sfc", PSR_s
| PSR_f
| PSR_c
},
21714 {"sxf", PSR_s
| PSR_x
| PSR_f
},
21715 {"sxc", PSR_s
| PSR_x
| PSR_c
},
21716 {"scf", PSR_s
| PSR_c
| PSR_f
},
21717 {"scx", PSR_s
| PSR_c
| PSR_x
},
21718 {"xfs", PSR_x
| PSR_f
| PSR_s
},
21719 {"xfc", PSR_x
| PSR_f
| PSR_c
},
21720 {"xsf", PSR_x
| PSR_s
| PSR_f
},
21721 {"xsc", PSR_x
| PSR_s
| PSR_c
},
21722 {"xcf", PSR_x
| PSR_c
| PSR_f
},
21723 {"xcs", PSR_x
| PSR_c
| PSR_s
},
21724 {"cfs", PSR_c
| PSR_f
| PSR_s
},
21725 {"cfx", PSR_c
| PSR_f
| PSR_x
},
21726 {"csf", PSR_c
| PSR_s
| PSR_f
},
21727 {"csx", PSR_c
| PSR_s
| PSR_x
},
21728 {"cxf", PSR_c
| PSR_x
| PSR_f
},
21729 {"cxs", PSR_c
| PSR_x
| PSR_s
},
21730 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
21731 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
21732 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
21733 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
21734 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
21735 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
21736 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
21737 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
21738 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
21739 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
21740 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
21741 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
21742 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
21743 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
21744 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
21745 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
21746 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
21747 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
21748 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
21749 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
21750 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
21751 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
21752 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
21753 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
21756 /* Table of V7M psr names. */
21757 static const struct asm_psr v7m_psrs
[] =
21759 {"apsr", 0x0 }, {"APSR", 0x0 },
21760 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
21761 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
21762 {"psr", 0x3 }, {"PSR", 0x3 },
21763 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
21764 {"ipsr", 0x5 }, {"IPSR", 0x5 },
21765 {"epsr", 0x6 }, {"EPSR", 0x6 },
21766 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
21767 {"msp", 0x8 }, {"MSP", 0x8 },
21768 {"psp", 0x9 }, {"PSP", 0x9 },
21769 {"msplim", 0xa }, {"MSPLIM", 0xa },
21770 {"psplim", 0xb }, {"PSPLIM", 0xb },
21771 {"primask", 0x10}, {"PRIMASK", 0x10},
21772 {"basepri", 0x11}, {"BASEPRI", 0x11},
21773 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
21774 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
21775 {"control", 0x14}, {"CONTROL", 0x14},
21776 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
21777 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
21778 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
21779 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
21780 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
21781 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
21782 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
21783 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
21784 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
21787 /* Table of all shift-in-operand names. */
21788 static const struct asm_shift_name shift_names
[] =
21790 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
21791 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
21792 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
21793 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
21794 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
21795 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
21796 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
21799 /* Table of all explicit relocation names. */
21801 static struct reloc_entry reloc_names
[] =
21803 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
21804 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
21805 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
21806 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
21807 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
21808 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
21809 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
21810 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
21811 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
21812 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
21813 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
21814 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
21815 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
21816 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
21817 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
21818 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
21819 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
21820 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
21821 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
21822 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
21823 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
21824 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
21825 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
21826 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
21827 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
21828 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
21829 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
21833 /* Table of all conditional affixes. */
21834 static const struct asm_cond conds
[] =
21838 {"cs", 0x2}, {"hs", 0x2},
21839 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
21852 static const struct asm_cond vconds
[] =
21858 #define UL_BARRIER(L,U,CODE,FEAT) \
21859 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
21860 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
21862 static struct asm_barrier_opt barrier_opt_names
[] =
21864 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
21865 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
21866 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
21867 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
21868 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
21869 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
21870 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
21871 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
21872 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
21873 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
21874 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
21875 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
21876 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
21877 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
21878 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
21879 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
21884 /* Table of ARM-format instructions. */
21886 /* Macros for gluing together operand strings. N.B. In all cases
21887 other than OPS0, the trailing OP_stop comes from default
21888 zero-initialization of the unspecified elements of the array. */
21889 #define OPS0() { OP_stop, }
21890 #define OPS1(a) { OP_##a, }
21891 #define OPS2(a,b) { OP_##a,OP_##b, }
21892 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
21893 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
21894 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
21895 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
21897 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
21898 This is useful when mixing operands for ARM and THUMB, i.e. using the
21899 MIX_ARM_THUMB_OPERANDS macro.
21900 In order to use these macros, prefix the number of operands with _
21902 #define OPS_1(a) { a, }
21903 #define OPS_2(a,b) { a,b, }
21904 #define OPS_3(a,b,c) { a,b,c, }
21905 #define OPS_4(a,b,c,d) { a,b,c,d, }
21906 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
21907 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
21909 /* These macros abstract out the exact format of the mnemonic table and
21910 save some repeated characters. */
21912 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
21913 #define TxCE(mnem, op, top, nops, ops, ae, te) \
21914 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
21915 THUMB_VARIANT, do_##ae, do_##te, 0 }
21917 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
21918 a T_MNEM_xyz enumerator. */
21919 #define TCE(mnem, aop, top, nops, ops, ae, te) \
21920 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
21921 #define tCE(mnem, aop, top, nops, ops, ae, te) \
21922 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
21924 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
21925 infix after the third character. */
21926 #define TxC3(mnem, op, top, nops, ops, ae, te) \
21927 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
21928 THUMB_VARIANT, do_##ae, do_##te, 0 }
21929 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
21930 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
21931 THUMB_VARIANT, do_##ae, do_##te, 0 }
21932 #define TC3(mnem, aop, top, nops, ops, ae, te) \
21933 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
21934 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
21935 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
21936 #define tC3(mnem, aop, top, nops, ops, ae, te) \
21937 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
21938 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
21939 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
21941 /* Mnemonic that cannot be conditionalized. The ARM condition-code
21942 field is still 0xE. Many of the Thumb variants can be executed
21943 conditionally, so this is checked separately. */
21944 #define TUE(mnem, op, top, nops, ops, ae, te) \
21945 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
21946 THUMB_VARIANT, do_##ae, do_##te, 0 }
21948 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
21949 Used by mnemonics that have very minimal differences in the encoding for
21950 ARM and Thumb variants and can be handled in a common function. */
21951 #define TUEc(mnem, op, top, nops, ops, en) \
21952 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
21953 THUMB_VARIANT, do_##en, do_##en, 0 }
21955 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
21956 condition code field. */
21957 #define TUF(mnem, op, top, nops, ops, ae, te) \
21958 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
21959 THUMB_VARIANT, do_##ae, do_##te, 0 }
21961 /* ARM-only variants of all the above. */
21962 #define CE(mnem, op, nops, ops, ae) \
21963 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
21965 #define C3(mnem, op, nops, ops, ae) \
21966 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
21968 /* Thumb-only variants of TCE and TUE. */
21969 #define ToC(mnem, top, nops, ops, te) \
21970 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
21973 #define ToU(mnem, top, nops, ops, te) \
21974 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
21977 /* T_MNEM_xyz enumerator variants of ToC. */
21978 #define toC(mnem, top, nops, ops, te) \
21979 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
21982 /* T_MNEM_xyz enumerator variants of ToU. */
21983 #define toU(mnem, top, nops, ops, te) \
21984 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
21987 /* Legacy mnemonics that always have conditional infix after the third
21989 #define CL(mnem, op, nops, ops, ae) \
21990 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
21991 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
21993 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
21994 #define cCE(mnem, op, nops, ops, ae) \
21995 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
21997 /* mov instructions that are shared between coprocessor and MVE. */
21998 #define mcCE(mnem, op, nops, ops, ae) \
21999 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
22001 /* Legacy coprocessor instructions where conditional infix and conditional
22002 suffix are ambiguous. For consistency this includes all FPA instructions,
22003 not just the potentially ambiguous ones. */
22004 #define cCL(mnem, op, nops, ops, ae) \
22005 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
22006 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
22008 /* Coprocessor, takes either a suffix or a position-3 infix
22009 (for an FPA corner case). */
22010 #define C3E(mnem, op, nops, ops, ae) \
22011 { mnem, OPS##nops ops, OT_csuf_or_in3, \
22012 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
22014 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
22015 { m1 #m2 m3, OPS##nops ops, \
22016 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
22017 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22019 #define CM(m1, m2, op, nops, ops, ae) \
22020 xCM_ (m1, , m2, op, nops, ops, ae), \
22021 xCM_ (m1, eq, m2, op, nops, ops, ae), \
22022 xCM_ (m1, ne, m2, op, nops, ops, ae), \
22023 xCM_ (m1, cs, m2, op, nops, ops, ae), \
22024 xCM_ (m1, hs, m2, op, nops, ops, ae), \
22025 xCM_ (m1, cc, m2, op, nops, ops, ae), \
22026 xCM_ (m1, ul, m2, op, nops, ops, ae), \
22027 xCM_ (m1, lo, m2, op, nops, ops, ae), \
22028 xCM_ (m1, mi, m2, op, nops, ops, ae), \
22029 xCM_ (m1, pl, m2, op, nops, ops, ae), \
22030 xCM_ (m1, vs, m2, op, nops, ops, ae), \
22031 xCM_ (m1, vc, m2, op, nops, ops, ae), \
22032 xCM_ (m1, hi, m2, op, nops, ops, ae), \
22033 xCM_ (m1, ls, m2, op, nops, ops, ae), \
22034 xCM_ (m1, ge, m2, op, nops, ops, ae), \
22035 xCM_ (m1, lt, m2, op, nops, ops, ae), \
22036 xCM_ (m1, gt, m2, op, nops, ops, ae), \
22037 xCM_ (m1, le, m2, op, nops, ops, ae), \
22038 xCM_ (m1, al, m2, op, nops, ops, ae)
22040 #define UE(mnem, op, nops, ops, ae) \
22041 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22043 #define UF(mnem, op, nops, ops, ae) \
22044 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
22046 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
22047 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
22048 use the same encoding function for each. */
22049 #define NUF(mnem, op, nops, ops, enc) \
22050 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
22051 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
22053 /* Neon data processing, version which indirects through neon_enc_tab for
22054 the various overloaded versions of opcodes. */
22055 #define nUF(mnem, op, nops, ops, enc) \
22056 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
22057 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
22059 /* Neon insn with conditional suffix for the ARM version, non-overloaded
22061 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
22062 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
22063 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
22065 #define NCE(mnem, op, nops, ops, enc) \
22066 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
22068 #define NCEF(mnem, op, nops, ops, enc) \
22069 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
22071 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
22072 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
22073 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
22074 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
22076 #define nCE(mnem, op, nops, ops, enc) \
22077 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
22079 #define nCEF(mnem, op, nops, ops, enc) \
22080 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
22083 #define mCEF(mnem, op, nops, ops, enc) \
22084 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
22085 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
22088 /* nCEF but for MVE predicated instructions. */
22089 #define mnCEF(mnem, op, nops, ops, enc) \
22090 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
22092 /* nCE but for MVE predicated instructions. */
22093 #define mnCE(mnem, op, nops, ops, enc) \
22094 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
22096 /* NUF but for potentially MVE predicated instructions. */
22097 #define MNUF(mnem, op, nops, ops, enc) \
22098 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
22099 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
22101 /* nUF but for potentially MVE predicated instructions. */
22102 #define mnUF(mnem, op, nops, ops, enc) \
22103 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
22104 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
22106 /* ToC but for potentially MVE predicated instructions. */
22107 #define mToC(mnem, top, nops, ops, te) \
22108 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
22111 /* NCE but for MVE predicated instructions. */
22112 #define MNCE(mnem, op, nops, ops, enc) \
22113 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
22115 /* NCEF but for MVE predicated instructions. */
22116 #define MNCEF(mnem, op, nops, ops, enc) \
22117 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
22120 static const struct asm_opcode insns
[] =
22122 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
22123 #define THUMB_VARIANT & arm_ext_v4t
22124 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22125 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22126 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22127 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22128 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
22129 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
22130 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
22131 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
22132 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22133 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22134 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
22135 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
22136 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22137 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
22138 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
22139 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
22141 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
22142 for setting PSR flag bits. They are obsolete in V6 and do not
22143 have Thumb equivalents. */
22144 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22145 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22146 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
22147 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
22148 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
22149 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
22150 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22151 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22152 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
22154 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
22155 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
22156 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
22157 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
22159 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
22160 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
22161 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
22163 OP_ADDRGLDR
),ldst
, t_ldst
),
22164 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
22166 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22167 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22168 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22169 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22170 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22171 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22173 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
22174 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
22177 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
22178 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
22179 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
22180 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
22182 /* Thumb-compatibility pseudo ops. */
22183 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22184 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22185 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22186 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22187 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22188 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22189 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22190 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
22191 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
22192 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
22193 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
22194 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
22196 /* These may simplify to neg. */
22197 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
22198 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
22200 #undef THUMB_VARIANT
22201 #define THUMB_VARIANT & arm_ext_os
22203 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
22204 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
22206 #undef THUMB_VARIANT
22207 #define THUMB_VARIANT & arm_ext_v6
22209 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
22211 /* V1 instructions with no Thumb analogue prior to V6T2. */
22212 #undef THUMB_VARIANT
22213 #define THUMB_VARIANT & arm_ext_v6t2
22215 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22216 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
22217 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
22219 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
22220 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
22221 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
22222 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
22224 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22225 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22227 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22228 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
22230 /* V1 instructions with no Thumb analogue at all. */
22231 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
22232 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
22234 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
22235 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
22236 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
22237 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
22238 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
22239 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
22240 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
22241 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
22244 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
22245 #undef THUMB_VARIANT
22246 #define THUMB_VARIANT & arm_ext_v4t
22248 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
22249 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
22251 #undef THUMB_VARIANT
22252 #define THUMB_VARIANT & arm_ext_v6t2
22254 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
22255 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
22257 /* Generic coprocessor instructions. */
22258 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
22259 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22260 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22261 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22262 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22263 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
22264 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
22267 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
22269 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
22270 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
22273 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
22274 #undef THUMB_VARIANT
22275 #define THUMB_VARIANT & arm_ext_msr
22277 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
22278 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
22281 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
22282 #undef THUMB_VARIANT
22283 #define THUMB_VARIANT & arm_ext_v6t2
22285 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
22286 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
22287 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
22288 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
22289 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
22290 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
22291 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
22292 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
22295 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
22296 #undef THUMB_VARIANT
22297 #define THUMB_VARIANT & arm_ext_v4t
22299 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22300 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22301 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22302 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22303 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22304 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
22307 #define ARM_VARIANT & arm_ext_v4t_5
22309 /* ARM Architecture 4T. */
22310 /* Note: bx (and blx) are required on V5, even if the processor does
22311 not support Thumb. */
22312 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
22315 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
22316 #undef THUMB_VARIANT
22317 #define THUMB_VARIANT & arm_ext_v5t
22319 /* Note: blx has 2 variants; the .value coded here is for
22320 BLX(2). Only this variant has conditional execution. */
22321 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
22322 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
22324 #undef THUMB_VARIANT
22325 #define THUMB_VARIANT & arm_ext_v6t2
22327 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
22328 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22329 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22330 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22331 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
22332 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
22333 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
22334 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
22337 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
22338 #undef THUMB_VARIANT
22339 #define THUMB_VARIANT & arm_ext_v5exp
22341 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22342 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22343 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22344 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22346 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22347 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
22349 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
22350 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
22351 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
22352 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
22354 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22355 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22356 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22357 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22359 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22360 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22362 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
22363 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
22364 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
22365 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
22368 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
22369 #undef THUMB_VARIANT
22370 #define THUMB_VARIANT & arm_ext_v6t2
22372 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
22373 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
22375 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
22376 ADDRGLDRS
), ldrd
, t_ldstd
),
22378 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
22379 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
22382 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
22384 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
22387 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
22388 #undef THUMB_VARIANT
22389 #define THUMB_VARIANT & arm_ext_v6
22391 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
22392 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
22393 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
22394 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
22395 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
22396 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22397 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22398 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22399 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22400 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
22402 #undef THUMB_VARIANT
22403 #define THUMB_VARIANT & arm_ext_v6t2_v8m
22405 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
22406 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
22408 #undef THUMB_VARIANT
22409 #define THUMB_VARIANT & arm_ext_v6t2
22411 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
22412 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
22414 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
22415 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
22417 /* ARM V6 not included in V7M. */
22418 #undef THUMB_VARIANT
22419 #define THUMB_VARIANT & arm_ext_v6_notm
22420 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
22421 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
22422 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
22423 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
22424 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
22425 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
22426 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
22427 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
22428 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
22429 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
22430 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
22431 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
22432 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
22433 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
22434 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
22435 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
22436 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
22437 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
22438 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
22440 /* ARM V6 not included in V7M (eg. integer SIMD). */
22441 #undef THUMB_VARIANT
22442 #define THUMB_VARIANT & arm_ext_v6_dsp
22443 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
22444 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
22445 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22446 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22447 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22448 /* Old name for QASX. */
22449 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22450 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22451 /* Old name for QSAX. */
22452 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22453 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22454 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22455 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22456 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22457 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22458 /* Old name for SASX. */
22459 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22460 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22461 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22462 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22463 /* Old name for SHASX. */
22464 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22465 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22466 /* Old name for SHSAX. */
22467 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22468 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22469 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22470 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22471 /* Old name for SSAX. */
22472 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22473 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22474 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22475 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22476 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22477 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22478 /* Old name for UASX. */
22479 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22480 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22481 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22482 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22483 /* Old name for UHASX. */
22484 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22485 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22486 /* Old name for UHSAX. */
22487 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22488 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22489 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22490 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22491 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22492 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22493 /* Old name for UQASX. */
22494 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22495 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22496 /* Old name for UQSAX. */
22497 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22498 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22499 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22500 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22501 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22502 /* Old name for USAX. */
22503 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22504 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22505 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22506 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22507 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22508 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22509 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22510 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22511 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
22512 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
22513 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
22514 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22515 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22516 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
22517 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
22518 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22519 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22520 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
22521 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
22522 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22523 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22524 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22525 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22526 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22527 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22528 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22529 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22530 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22531 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22532 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
22533 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
22534 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
22535 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
22536 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
22539 #define ARM_VARIANT & arm_ext_v6k_v6t2
22540 #undef THUMB_VARIANT
22541 #define THUMB_VARIANT & arm_ext_v6k_v6t2
22543 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
22544 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
22545 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
22546 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
22548 #undef THUMB_VARIANT
22549 #define THUMB_VARIANT & arm_ext_v6_notm
22550 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
22552 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
22553 RRnpcb
), strexd
, t_strexd
),
22555 #undef THUMB_VARIANT
22556 #define THUMB_VARIANT & arm_ext_v6t2_v8m
22557 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
22559 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
22561 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
22563 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
22565 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
22568 #define ARM_VARIANT & arm_ext_sec
22569 #undef THUMB_VARIANT
22570 #define THUMB_VARIANT & arm_ext_sec
22572 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
22575 #define ARM_VARIANT & arm_ext_virt
22576 #undef THUMB_VARIANT
22577 #define THUMB_VARIANT & arm_ext_virt
22579 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
22580 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
22583 #define ARM_VARIANT & arm_ext_pan
22584 #undef THUMB_VARIANT
22585 #define THUMB_VARIANT & arm_ext_pan
22587 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
22590 #define ARM_VARIANT & arm_ext_v6t2
22591 #undef THUMB_VARIANT
22592 #define THUMB_VARIANT & arm_ext_v6t2
22594 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
22595 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
22596 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
22597 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
22599 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
22600 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
22602 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
22603 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
22604 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
22605 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
22608 #define ARM_VARIANT & arm_ext_v3
22609 #undef THUMB_VARIANT
22610 #define THUMB_VARIANT & arm_ext_v6t2
22612 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
22613 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
22614 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
22617 #define ARM_VARIANT & arm_ext_v6t2
22618 #undef THUMB_VARIANT
22619 #define THUMB_VARIANT & arm_ext_v6t2_v8m
22620 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
22621 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
22623 /* Thumb-only instructions. */
22625 #define ARM_VARIANT NULL
22626 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
22627 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
22629 /* ARM does not really have an IT instruction, so always allow it.
22630 The opcode is copied from Thumb in order to allow warnings in
22631 -mimplicit-it=[never | arm] modes. */
22633 #define ARM_VARIANT & arm_ext_v1
22634 #undef THUMB_VARIANT
22635 #define THUMB_VARIANT & arm_ext_v6t2
22637 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
22638 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
22639 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
22640 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
22641 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
22642 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
22643 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
22644 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
22645 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
22646 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
22647 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
22648 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
22649 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
22650 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
22651 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
22652 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
22653 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
22654 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
22656 /* Thumb2 only instructions. */
22658 #define ARM_VARIANT NULL
22660 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
22661 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
22662 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
22663 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
22664 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
22665 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
22667 /* Hardware division instructions. */
22669 #define ARM_VARIANT & arm_ext_adiv
22670 #undef THUMB_VARIANT
22671 #define THUMB_VARIANT & arm_ext_div
22673 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
22674 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
22676 /* ARM V6M/V7 instructions. */
22678 #define ARM_VARIANT & arm_ext_barrier
22679 #undef THUMB_VARIANT
22680 #define THUMB_VARIANT & arm_ext_barrier
22682 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
22683 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
22684 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
22686 /* ARM V7 instructions. */
22688 #define ARM_VARIANT & arm_ext_v7
22689 #undef THUMB_VARIANT
22690 #define THUMB_VARIANT & arm_ext_v7
22692 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
22693 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
22696 #define ARM_VARIANT & arm_ext_mp
22697 #undef THUMB_VARIANT
22698 #define THUMB_VARIANT & arm_ext_mp
22700 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
22702 /* AArchv8 instructions. */
22704 #define ARM_VARIANT & arm_ext_v8
22706 /* Instructions shared between armv8-a and armv8-m. */
22707 #undef THUMB_VARIANT
22708 #define THUMB_VARIANT & arm_ext_atomics
22710 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
22711 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
22712 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
22713 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
22714 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
22715 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
22716 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
22717 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
22718 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
22719 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
22721 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
22723 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
22725 #undef THUMB_VARIANT
22726 #define THUMB_VARIANT & arm_ext_v8
22728 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
22729 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
22731 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
22734 /* Defined in V8 but is in undefined encoding space for earlier
22735 architectures. However earlier architectures are required to treat
22736 this instuction as a semihosting trap as well. Hence while not explicitly
22737 defined as such, it is in fact correct to define the instruction for all
22739 #undef THUMB_VARIANT
22740 #define THUMB_VARIANT & arm_ext_v1
22742 #define ARM_VARIANT & arm_ext_v1
22743 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
22745 /* ARMv8 T32 only. */
22747 #define ARM_VARIANT NULL
22748 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
22749 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
22750 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
22752 /* FP for ARMv8. */
22754 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
22755 #undef THUMB_VARIANT
22756 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
22758 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
22759 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
22760 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
22761 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
22762 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
22763 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
22764 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
22765 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
22766 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
22767 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
22768 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
22769 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
22770 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
22772 /* Crypto v1 extensions. */
22774 #define ARM_VARIANT & fpu_crypto_ext_armv8
22775 #undef THUMB_VARIANT
22776 #define THUMB_VARIANT & fpu_crypto_ext_armv8
22778 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
22779 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
22780 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
22781 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
22782 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
22783 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
22784 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
22785 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
22786 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
22787 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
22788 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
22789 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
22790 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
22791 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
22794 #define ARM_VARIANT & crc_ext_armv8
22795 #undef THUMB_VARIANT
22796 #define THUMB_VARIANT & crc_ext_armv8
22797 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
22798 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
22799 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
22800 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
22801 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
22802 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
22804 /* ARMv8.2 RAS extension. */
22806 #define ARM_VARIANT & arm_ext_ras
22807 #undef THUMB_VARIANT
22808 #define THUMB_VARIANT & arm_ext_ras
22809 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
22812 #define ARM_VARIANT & arm_ext_v8_3
22813 #undef THUMB_VARIANT
22814 #define THUMB_VARIANT & arm_ext_v8_3
22815 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
22818 #define ARM_VARIANT & fpu_neon_ext_dotprod
22819 #undef THUMB_VARIANT
22820 #define THUMB_VARIANT & fpu_neon_ext_dotprod
22821 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
22822 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
22825 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
22826 #undef THUMB_VARIANT
22827 #define THUMB_VARIANT NULL
22829 cCE("wfs", e200110
, 1, (RR
), rd
),
22830 cCE("rfs", e300110
, 1, (RR
), rd
),
22831 cCE("wfc", e400110
, 1, (RR
), rd
),
22832 cCE("rfc", e500110
, 1, (RR
), rd
),
22834 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22835 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22836 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22837 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22839 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22840 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22841 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22842 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
22844 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
22845 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
22846 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
22847 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
22848 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
22849 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
22850 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
22851 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
22852 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
22853 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
22854 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
22855 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
22857 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
22858 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
22859 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
22860 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
22861 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
22862 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
22863 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
22864 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
22865 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
22866 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
22867 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
22868 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
22870 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
22871 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
22872 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
22873 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
22874 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
22875 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
22876 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
22877 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
22878 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
22879 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
22880 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
22881 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
22883 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
22884 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
22885 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
22886 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
22887 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
22888 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
22889 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
22890 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
22891 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
22892 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
22893 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
22894 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
22896 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
22897 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
22898 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
22899 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
22900 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
22901 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
22902 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
22903 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
22904 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
22905 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
22906 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
22907 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
22909 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
22910 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
22911 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
22912 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
22913 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
22914 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
22915 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
22916 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
22917 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
22918 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
22919 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
22920 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
22922 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
22923 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
22924 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
22925 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
22926 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
22927 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
22928 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
22929 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
22930 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
22931 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
22932 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
22933 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
22935 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
22936 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
22937 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
22938 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
22939 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
22940 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
22941 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
22942 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
22943 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
22944 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
22945 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
22946 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
22948 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
22949 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
22950 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
22951 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
22952 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
22953 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
22954 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
22955 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
22956 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
22957 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
22958 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
22959 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
22961 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
22962 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
22963 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
22964 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
22965 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
22966 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
22967 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
22968 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
22969 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
22970 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
22971 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
22972 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
22974 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
22975 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
22976 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
22977 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
22978 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
22979 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
22980 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
22981 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
22982 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
22983 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
22984 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
22985 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
22987 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
22988 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
22989 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
22990 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
22991 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
22992 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
22993 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
22994 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
22995 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
22996 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
22997 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
22998 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
23000 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
23001 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
23002 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
23003 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
23004 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
23005 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
23006 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
23007 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
23008 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
23009 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
23010 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
23011 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
23013 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
23014 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
23015 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
23016 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
23017 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
23018 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
23019 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
23020 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
23021 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
23022 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
23023 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
23024 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
23026 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
23027 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
23028 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
23029 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
23030 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
23031 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
23032 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
23033 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
23034 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
23035 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
23036 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
23037 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
23039 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
23040 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
23041 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
23042 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
23043 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
23044 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
23045 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
23046 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
23047 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
23048 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
23049 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
23050 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
23052 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23053 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23054 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23055 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23056 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23057 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23058 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23059 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23060 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23061 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23062 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23063 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23065 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23066 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23067 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23068 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23069 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23070 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23071 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23072 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23073 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23074 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23075 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23076 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23078 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23079 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23080 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23081 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23082 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23083 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23084 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23085 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23086 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23087 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23088 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23089 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23091 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23092 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23093 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23094 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23095 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23096 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23097 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23098 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23099 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23100 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23101 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23102 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23104 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23105 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23106 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23107 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23108 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23109 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23110 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23111 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23112 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23113 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23114 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23115 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23117 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23118 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23119 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23120 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23121 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23122 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23123 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23124 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23125 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23126 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23127 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23128 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23130 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23131 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23132 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23133 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23134 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23135 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23136 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23137 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23138 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23139 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23140 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23141 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23143 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23144 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23145 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23146 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23147 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23148 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23149 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23150 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23151 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23152 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23153 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23154 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23156 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23157 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23158 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23159 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23160 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23161 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23162 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23163 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23164 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23165 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23166 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23167 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23169 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23170 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23171 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23172 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23173 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23174 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23175 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23176 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23177 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23178 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23179 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23180 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23182 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23183 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23184 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23185 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23186 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23187 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23188 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23189 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23190 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23191 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23192 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23193 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23195 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23196 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23197 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23198 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23199 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23200 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23201 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23202 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23203 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23204 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23205 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23206 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23208 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23209 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23210 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23211 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23212 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23213 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23214 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23215 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23216 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23217 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23218 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23219 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
23221 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
23222 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
23223 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
23224 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
23226 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
23227 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
23228 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
23229 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
23230 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
23231 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
23232 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
23233 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
23234 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
23235 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
23236 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
23237 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
23239 /* The implementation of the FIX instruction is broken on some
23240 assemblers, in that it accepts a precision specifier as well as a
23241 rounding specifier, despite the fact that this is meaningless.
23242 To be more compatible, we accept it as well, though of course it
23243 does not set any bits. */
23244 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
23245 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
23246 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
23247 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
23248 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
23249 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
23250 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
23251 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
23252 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
23253 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
23254 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
23255 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
23256 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
23258 /* Instructions that were new with the real FPA, call them V2. */
23260 #define ARM_VARIANT & fpu_fpa_ext_v2
23262 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23263 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23264 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23265 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23266 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23267 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
23270 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
23272 /* Moves and type conversions. */
23273 cCE("fmstat", ef1fa10
, 0, (), noargs
),
23274 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
23275 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
23276 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23277 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23278 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23279 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23280 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23281 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23282 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
23283 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
23285 /* Memory operations. */
23286 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
23287 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
23288 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
23289 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
23290 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
23291 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
23292 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
23293 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
23294 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
23295 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
23296 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
23297 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
23298 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
23299 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
23300 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
23301 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
23302 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
23303 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
23305 /* Monadic operations. */
23306 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23307 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23308 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23310 /* Dyadic operations. */
23311 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23312 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23313 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23314 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23315 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23316 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23317 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23318 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23319 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23322 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23323 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
23324 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
23325 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
23327 /* Double precision load/store are still present on single precision
23328 implementations. */
23329 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
23330 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
23331 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
23332 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
23333 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
23334 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
23335 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
23336 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
23337 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
23338 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
23341 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
23343 /* Moves and type conversions. */
23344 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
23345 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23346 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
23347 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
23348 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
23349 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
23350 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
23351 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
23352 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23353 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23354 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23355 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
23357 /* Monadic operations. */
23358 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23359 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23360 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23362 /* Dyadic operations. */
23363 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23364 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23365 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23366 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23367 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23368 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23369 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23370 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23371 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23374 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23375 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
23376 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
23377 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
23379 /* Instructions which may belong to either the Neon or VFP instruction sets.
23380 Individual encoder functions perform additional architecture checks. */
23382 #define ARM_VARIANT & fpu_vfp_ext_v1xd
23383 #undef THUMB_VARIANT
23384 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
23386 /* These mnemonics are unique to VFP. */
23387 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
23388 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
23389 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23390 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23391 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23392 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
23393 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
23394 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
23396 /* Mnemonics shared by Neon and VFP. */
23397 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
23398 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
23399 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
23401 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23402 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23403 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23404 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23405 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23406 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
23408 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
23409 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
23410 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
23411 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
23414 /* NOTE: All VMOV encoding is special-cased! */
23415 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
23417 #undef THUMB_VARIANT
23418 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
23419 by different feature bits. Since we are setting the Thumb guard, we can
23420 require Thumb-1 which makes it a nop guard and set the right feature bit in
23421 do_vldr_vstr (). */
23422 #define THUMB_VARIANT & arm_ext_v4t
23423 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
23424 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
23427 #define ARM_VARIANT & arm_ext_fp16
23428 #undef THUMB_VARIANT
23429 #define THUMB_VARIANT & arm_ext_fp16
23430 /* New instructions added from v8.2, allowing the extraction and insertion of
23431 the upper 16 bits of a 32-bit vector register. */
23432 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
23433 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
23435 /* New backported fma/fms instructions optional in v8.2. */
23436 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
23437 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
23439 #undef THUMB_VARIANT
23440 #define THUMB_VARIANT & fpu_neon_ext_v1
23442 #define ARM_VARIANT & fpu_neon_ext_v1
23444 /* Data processing with three registers of the same length. */
23445 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
23446 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
23447 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
23448 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
23449 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
23450 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
23451 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
23452 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
23453 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
23454 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
23455 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
23456 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
23457 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
23458 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
23459 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
23460 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
23461 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
23462 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
23463 /* If not immediate, fall back to neon_dyadic_i64_su.
23464 shl_imm should accept I8 I16 I32 I64,
23465 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
23466 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
23467 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
23468 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
23469 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
23470 /* Logic ops, types optional & ignored. */
23471 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
23472 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
23473 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
23474 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
23475 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
23476 /* Bitfield ops, untyped. */
23477 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
23478 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
23479 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
23480 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
23481 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
23482 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
23483 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
23484 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
23485 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
23486 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
23487 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
23488 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
23489 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
23490 back to neon_dyadic_if_su. */
23491 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
23492 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
23493 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
23494 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
23495 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
23496 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
23497 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
23498 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
23499 /* Comparison. Type I8 I16 I32 F32. */
23500 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
23501 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
23502 /* As above, D registers only. */
23503 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
23504 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
23505 /* Int and float variants, signedness unimportant. */
23506 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
23507 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
23508 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
23509 /* Add/sub take types I8 I16 I32 I64 F32. */
23510 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
23511 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
23512 /* vtst takes sizes 8, 16, 32. */
23513 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
23514 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
23515 /* VMUL takes I8 I16 I32 F32 P8. */
23516 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
23517 /* VQD{R}MULH takes S16 S32. */
23518 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
23519 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
23520 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
23521 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
23522 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
23523 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
23524 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
23525 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
23526 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
23527 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
23528 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
23529 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
23530 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
23531 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
23532 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
23533 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
23534 /* ARM v8.1 extension. */
23535 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
23536 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
23537 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
23538 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
23540 /* Two address, int/float. Types S8 S16 S32 F32. */
23541 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
23542 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
23544 /* Data processing with two registers and a shift amount. */
23545 /* Right shifts, and variants with rounding.
23546 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
23547 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
23548 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
23549 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
23550 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
23551 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
23552 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
23553 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
23554 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
23555 /* Shift and insert. Sizes accepted 8 16 32 64. */
23556 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
23557 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
23558 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
23559 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
23560 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
23561 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
23562 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
23563 /* Right shift immediate, saturating & narrowing, with rounding variants.
23564 Types accepted S16 S32 S64 U16 U32 U64. */
23565 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
23566 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
23567 /* As above, unsigned. Types accepted S16 S32 S64. */
23568 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
23569 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
23570 /* Right shift narrowing. Types accepted I16 I32 I64. */
23571 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
23572 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
23573 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
23574 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
23575 /* CVT with optional immediate for fixed-point variant. */
23576 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
23578 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
23579 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
23581 /* Data processing, three registers of different lengths. */
23582 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
23583 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
23584 /* If not scalar, fall back to neon_dyadic_long.
23585 Vector types as above, scalar types S16 S32 U16 U32. */
23586 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
23587 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
23588 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
23589 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
23590 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
23591 /* Dyadic, narrowing insns. Types I16 I32 I64. */
23592 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
23593 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
23594 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
23595 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
23596 /* Saturating doubling multiplies. Types S16 S32. */
23597 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
23598 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
23599 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
23600 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
23601 S16 S32 U16 U32. */
23602 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
23604 /* Extract. Size 8. */
23605 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
23606 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
23608 /* Two registers, miscellaneous. */
23609 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
23610 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
23611 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
23612 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
23613 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
23614 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
23615 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
23616 /* Vector replicate. Sizes 8 16 32. */
23617 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
23618 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
23619 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
23620 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
23621 /* VMOVN. Types I16 I32 I64. */
23622 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
23623 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
23624 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
23625 /* VQMOVUN. Types S16 S32 S64. */
23626 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
23627 /* VZIP / VUZP. Sizes 8 16 32. */
23628 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
23629 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
23630 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
23631 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
23632 /* VQABS / VQNEG. Types S8 S16 S32. */
23633 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
23634 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
23635 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
23636 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
23637 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
23638 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
23639 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
23640 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
23641 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
23642 /* Reciprocal estimates. Types U32 F16 F32. */
23643 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
23644 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
23645 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
23646 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
23647 /* VCLS. Types S8 S16 S32. */
23648 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
23649 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
23650 /* VCLZ. Types I8 I16 I32. */
23651 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
23652 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
23653 /* VCNT. Size 8. */
23654 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
23655 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
23656 /* Two address, untyped. */
23657 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
23658 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
23659 /* VTRN. Sizes 8 16 32. */
23660 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
23661 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
23663 /* Table lookup. Size 8. */
23664 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
23665 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
23667 #undef THUMB_VARIANT
23668 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
23670 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
23672 /* Neon element/structure load/store. */
23673 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23674 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23675 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23676 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23677 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23678 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23679 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23680 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
23682 #undef THUMB_VARIANT
23683 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
23685 #define ARM_VARIANT & fpu_vfp_ext_v3xd
23686 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
23687 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
23688 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
23689 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
23690 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
23691 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
23692 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
23693 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
23694 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
23696 #undef THUMB_VARIANT
23697 #define THUMB_VARIANT & fpu_vfp_ext_v3
23699 #define ARM_VARIANT & fpu_vfp_ext_v3
23701 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
23702 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
23703 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
23704 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
23705 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
23706 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
23707 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
23708 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
23709 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
23712 #define ARM_VARIANT & fpu_vfp_ext_fma
23713 #undef THUMB_VARIANT
23714 #define THUMB_VARIANT & fpu_vfp_ext_fma
23715 /* Mnemonics shared by Neon and VFP. These are included in the
23716 VFP FMA variant; NEON and VFP FMA always includes the NEON
23717 FMA instructions. */
23718 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
23719 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
23720 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
23721 the v form should always be used. */
23722 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23723 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
23724 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23725 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
23726 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23727 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
23729 #undef THUMB_VARIANT
23731 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
23733 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23734 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23735 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23736 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23737 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23738 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
23739 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
23740 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
23743 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
23745 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
23746 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
23747 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
23748 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
23749 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
23750 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
23751 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
23752 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
23753 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
23754 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23755 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23756 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23757 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23758 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23759 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
23760 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
23761 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
23762 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
23763 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
23764 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
23765 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23766 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23767 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23768 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23769 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23770 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
23771 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
23772 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
23773 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
23774 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
23775 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
23776 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
23777 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
23778 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
23779 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23780 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23781 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23782 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23783 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23784 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23785 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23786 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23787 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23788 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23789 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23790 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23791 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
23792 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23793 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23794 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23795 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23796 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23797 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23798 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23799 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23800 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23801 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23802 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23803 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23804 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23805 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23806 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23807 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23808 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23809 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23810 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23811 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
23812 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
23813 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
23814 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
23815 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23816 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23817 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23818 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23819 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23820 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23821 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23822 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23823 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23824 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23825 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23826 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23827 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23828 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23829 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23830 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23831 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23832 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23833 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
23834 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23835 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23836 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23837 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23838 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23839 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23840 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23841 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23842 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23843 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23844 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23845 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23846 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23847 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23848 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23849 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23850 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23851 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23852 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23853 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23854 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23855 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
23856 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23857 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23858 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23859 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23860 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23861 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23862 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23863 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23864 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23865 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23866 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23867 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23868 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23869 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23870 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23871 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23872 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
23873 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
23874 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
23875 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
23876 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
23877 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
23878 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23879 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23880 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23881 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23882 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23883 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23884 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23885 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23886 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23887 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23888 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23889 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23890 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23891 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23892 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
23893 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23894 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23895 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23896 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23897 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23898 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23899 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23900 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23901 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
23902 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23903 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23904 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23905 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23906 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
23909 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
23911 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
23912 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
23913 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
23914 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23915 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23916 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
23917 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23918 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23919 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23920 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23921 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23922 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23923 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23924 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23925 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23926 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23927 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23928 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23929 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23930 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23931 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
23932 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23933 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23934 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23935 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23936 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23937 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23938 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23939 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23940 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23941 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23942 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23943 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23944 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23945 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23946 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23947 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23948 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23949 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23950 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23951 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23952 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23953 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23954 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23955 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23956 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23957 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23958 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23959 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23960 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23961 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23962 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23963 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23964 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23965 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23966 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23967 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
23970 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
23972 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
23973 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
23974 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
23975 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
23976 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
23977 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
23978 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
23979 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
23980 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
23981 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
23982 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
23983 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
23984 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
23985 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
23986 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
23987 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
23988 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
23989 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
23990 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
23991 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
23992 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
23993 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
23994 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
23995 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
23996 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
23997 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
23998 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
23999 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
24000 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
24001 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
24002 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
24003 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
24004 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
24005 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
24006 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
24007 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
24008 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
24009 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
24010 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
24011 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
24012 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
24013 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
24014 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
24015 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
24016 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
24017 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
24018 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
24019 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
24020 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
24021 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
24022 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
24023 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
24024 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
24025 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
24026 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
24027 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
24028 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
24029 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
24030 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
24031 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
24032 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
24033 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
24034 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
24035 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
24036 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
24037 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
24038 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
24039 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
24040 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
24041 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
24042 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
24043 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
24044 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
24045 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
24046 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
24047 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
24049 /* ARMv8.5-A instructions. */
24051 #define ARM_VARIANT & arm_ext_sb
24052 #undef THUMB_VARIANT
24053 #define THUMB_VARIANT & arm_ext_sb
24054 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
24057 #define ARM_VARIANT & arm_ext_predres
24058 #undef THUMB_VARIANT
24059 #define THUMB_VARIANT & arm_ext_predres
24060 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
24061 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
24062 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
24064 /* ARMv8-M instructions. */
24066 #define ARM_VARIANT NULL
24067 #undef THUMB_VARIANT
24068 #define THUMB_VARIANT & arm_ext_v8m
24069 ToU("sg", e97fe97f
, 0, (), noargs
),
24070 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
24071 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
24072 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
24073 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
24074 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
24075 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
24077 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
24078 instructions behave as nop if no VFP is present. */
24079 #undef THUMB_VARIANT
24080 #define THUMB_VARIANT & arm_ext_v8m_main
24081 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
24082 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
24084 /* Armv8.1-M Mainline instructions. */
24085 #undef THUMB_VARIANT
24086 #define THUMB_VARIANT & arm_ext_v8_1m_main
24087 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
24088 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
24089 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
24090 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
24091 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
24093 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
24094 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
24095 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
24097 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
24098 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
24100 #undef THUMB_VARIANT
24101 #define THUMB_VARIANT & mve_ext
24103 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24104 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24105 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24106 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24107 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24108 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24109 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24110 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24111 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24112 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24113 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24114 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24115 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24116 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24117 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
24119 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
24120 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
24121 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
24122 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
24123 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
24124 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
24125 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
24126 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
24127 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
24128 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
24129 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
24130 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
24131 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
24132 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
24133 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
24135 /* MVE and MVE FP only. */
24136 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
24137 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
24138 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
24139 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
24140 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
24141 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
24142 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24143 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24144 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24145 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24146 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24147 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24148 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24149 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24150 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24151 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
24153 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
24154 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
24155 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24156 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24157 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24158 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24159 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
24160 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
24161 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24162 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24163 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24164 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
24165 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24166 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24167 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24168 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24169 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24170 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24171 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24172 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
24174 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
24175 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
24176 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
24177 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
24178 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
24179 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
24180 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
24182 #undef THUMB_VARIANT
24183 #define THUMB_VARIANT & mve_fp_ext
24184 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
24187 #define ARM_VARIANT & fpu_vfp_ext_v1
24188 #undef THUMB_VARIANT
24189 #define THUMB_VARIANT & arm_ext_v6t2
24191 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24194 #define ARM_VARIANT & fpu_vfp_ext_v1xd
24196 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
24197 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
24198 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
24199 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24201 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
24202 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
24203 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
24205 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
24206 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
24208 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
24209 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
24211 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
24212 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
24215 #define ARM_VARIANT & fpu_vfp_ext_v2
24217 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
24218 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
24219 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
24220 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
24223 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
24224 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
24225 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
24226 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
24227 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
24230 #define ARM_VARIANT & fpu_neon_ext_v1
24231 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
24232 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
24233 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
24234 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
24235 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
24236 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
24237 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
24238 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
24239 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
24242 #define ARM_VARIANT & arm_ext_v8_3
24243 #undef THUMB_VARIANT
24244 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24245 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
24246 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
24249 #undef THUMB_VARIANT
24281 /* MD interface: bits in the object file. */
24283 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
24284 for use in the a.out file, and stores them in the array pointed to by buf.
24285 This knows about the endian-ness of the target machine and does
24286 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
24287 2 (short) and 4 (long) Floating numbers are put out as a series of
24288 LITTLENUMS (shorts, here at least). */
24291 md_number_to_chars (char * buf
, valueT val
, int n
)
24293 if (target_big_endian
)
24294 number_to_chars_bigendian (buf
, val
, n
);
24296 number_to_chars_littleendian (buf
, val
, n
);
24300 md_chars_to_number (char * buf
, int n
)
24303 unsigned char * where
= (unsigned char *) buf
;
24305 if (target_big_endian
)
24310 result
|= (*where
++ & 255);
24318 result
|= (where
[n
] & 255);
24325 /* MD interface: Sections. */
24327 /* Calculate the maximum variable size (i.e., excluding fr_fix)
24328 that an rs_machine_dependent frag may reach. */
24331 arm_frag_max_var (fragS
*fragp
)
24333 /* We only use rs_machine_dependent for variable-size Thumb instructions,
24334 which are either THUMB_SIZE (2) or INSN_SIZE (4).
24336 Note that we generate relaxable instructions even for cases that don't
24337 really need it, like an immediate that's a trivial constant. So we're
24338 overestimating the instruction size for some of those cases. Rather
24339 than putting more intelligence here, it would probably be better to
24340 avoid generating a relaxation frag in the first place when it can be
24341 determined up front that a short instruction will suffice. */
24343 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
24347 /* Estimate the size of a frag before relaxing. Assume everything fits in
24351 md_estimate_size_before_relax (fragS
* fragp
,
24352 segT segtype ATTRIBUTE_UNUSED
)
24358 /* Convert a machine dependent frag. */
24361 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
24363 unsigned long insn
;
24364 unsigned long old_op
;
24372 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
24374 old_op
= bfd_get_16(abfd
, buf
);
24375 if (fragp
->fr_symbol
)
24377 exp
.X_op
= O_symbol
;
24378 exp
.X_add_symbol
= fragp
->fr_symbol
;
24382 exp
.X_op
= O_constant
;
24384 exp
.X_add_number
= fragp
->fr_offset
;
24385 opcode
= fragp
->fr_subtype
;
24388 case T_MNEM_ldr_pc
:
24389 case T_MNEM_ldr_pc2
:
24390 case T_MNEM_ldr_sp
:
24391 case T_MNEM_str_sp
:
24398 if (fragp
->fr_var
== 4)
24400 insn
= THUMB_OP32 (opcode
);
24401 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
24403 insn
|= (old_op
& 0x700) << 4;
24407 insn
|= (old_op
& 7) << 12;
24408 insn
|= (old_op
& 0x38) << 13;
24410 insn
|= 0x00000c00;
24411 put_thumb32_insn (buf
, insn
);
24412 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
24416 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
24418 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
24421 if (fragp
->fr_var
== 4)
24423 insn
= THUMB_OP32 (opcode
);
24424 insn
|= (old_op
& 0xf0) << 4;
24425 put_thumb32_insn (buf
, insn
);
24426 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
24430 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
24431 exp
.X_add_number
-= 4;
24439 if (fragp
->fr_var
== 4)
24441 int r0off
= (opcode
== T_MNEM_mov
24442 || opcode
== T_MNEM_movs
) ? 0 : 8;
24443 insn
= THUMB_OP32 (opcode
);
24444 insn
= (insn
& 0xe1ffffff) | 0x10000000;
24445 insn
|= (old_op
& 0x700) << r0off
;
24446 put_thumb32_insn (buf
, insn
);
24447 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
24451 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
24456 if (fragp
->fr_var
== 4)
24458 insn
= THUMB_OP32(opcode
);
24459 put_thumb32_insn (buf
, insn
);
24460 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
24463 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
24467 if (fragp
->fr_var
== 4)
24469 insn
= THUMB_OP32(opcode
);
24470 insn
|= (old_op
& 0xf00) << 14;
24471 put_thumb32_insn (buf
, insn
);
24472 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
24475 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
24478 case T_MNEM_add_sp
:
24479 case T_MNEM_add_pc
:
24480 case T_MNEM_inc_sp
:
24481 case T_MNEM_dec_sp
:
24482 if (fragp
->fr_var
== 4)
24484 /* ??? Choose between add and addw. */
24485 insn
= THUMB_OP32 (opcode
);
24486 insn
|= (old_op
& 0xf0) << 4;
24487 put_thumb32_insn (buf
, insn
);
24488 if (opcode
== T_MNEM_add_pc
)
24489 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
24491 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
24494 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
24502 if (fragp
->fr_var
== 4)
24504 insn
= THUMB_OP32 (opcode
);
24505 insn
|= (old_op
& 0xf0) << 4;
24506 insn
|= (old_op
& 0xf) << 16;
24507 put_thumb32_insn (buf
, insn
);
24508 if (insn
& (1 << 20))
24509 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
24511 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
24514 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
24520 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
24521 (enum bfd_reloc_code_real
) reloc_type
);
24522 fixp
->fx_file
= fragp
->fr_file
;
24523 fixp
->fx_line
= fragp
->fr_line
;
24524 fragp
->fr_fix
+= fragp
->fr_var
;
24526 /* Set whether we use thumb-2 ISA based on final relaxation results. */
24527 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
24528 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
24529 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
24532 /* Return the size of a relaxable immediate operand instruction.
24533 SHIFT and SIZE specify the form of the allowable immediate. */
24535 relax_immediate (fragS
*fragp
, int size
, int shift
)
24541 /* ??? Should be able to do better than this. */
24542 if (fragp
->fr_symbol
)
24545 low
= (1 << shift
) - 1;
24546 mask
= (1 << (shift
+ size
)) - (1 << shift
);
24547 offset
= fragp
->fr_offset
;
24548 /* Force misaligned offsets to 32-bit variant. */
24551 if (offset
& ~mask
)
24556 /* Get the address of a symbol during relaxation. */
24558 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
24564 sym
= fragp
->fr_symbol
;
24565 sym_frag
= symbol_get_frag (sym
);
24566 know (S_GET_SEGMENT (sym
) != absolute_section
24567 || sym_frag
== &zero_address_frag
);
24568 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
24570 /* If frag has yet to be reached on this pass, assume it will
24571 move by STRETCH just as we did. If this is not so, it will
24572 be because some frag between grows, and that will force
24576 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
24580 /* Adjust stretch for any alignment frag. Note that if have
24581 been expanding the earlier code, the symbol may be
24582 defined in what appears to be an earlier frag. FIXME:
24583 This doesn't handle the fr_subtype field, which specifies
24584 a maximum number of bytes to skip when doing an
24586 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
24588 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
24591 stretch
= - ((- stretch
)
24592 & ~ ((1 << (int) f
->fr_offset
) - 1));
24594 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
24606 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
24609 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
24614 /* Assume worst case for symbols not known to be in the same section. */
24615 if (fragp
->fr_symbol
== NULL
24616 || !S_IS_DEFINED (fragp
->fr_symbol
)
24617 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
24618 || S_IS_WEAK (fragp
->fr_symbol
))
24621 val
= relaxed_symbol_addr (fragp
, stretch
);
24622 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
24623 addr
= (addr
+ 4) & ~3;
24624 /* Force misaligned targets to 32-bit variant. */
24628 if (val
< 0 || val
> 1020)
24633 /* Return the size of a relaxable add/sub immediate instruction. */
24635 relax_addsub (fragS
*fragp
, asection
*sec
)
24640 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
24641 op
= bfd_get_16(sec
->owner
, buf
);
24642 if ((op
& 0xf) == ((op
>> 4) & 0xf))
24643 return relax_immediate (fragp
, 8, 0);
24645 return relax_immediate (fragp
, 3, 0);
24648 /* Return TRUE iff the definition of symbol S could be pre-empted
24649 (overridden) at link or load time. */
24651 symbol_preemptible (symbolS
*s
)
24653 /* Weak symbols can always be pre-empted. */
24657 /* Non-global symbols cannot be pre-empted. */
24658 if (! S_IS_EXTERNAL (s
))
24662 /* In ELF, a global symbol can be marked protected, or private. In that
24663 case it can't be pre-empted (other definitions in the same link unit
24664 would violate the ODR). */
24665 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
24669 /* Other global symbols might be pre-empted. */
24673 /* Return the size of a relaxable branch instruction. BITS is the
24674 size of the offset field in the narrow instruction. */
24677 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
24683 /* Assume worst case for symbols not known to be in the same section. */
24684 if (!S_IS_DEFINED (fragp
->fr_symbol
)
24685 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
24686 || S_IS_WEAK (fragp
->fr_symbol
))
24690 /* A branch to a function in ARM state will require interworking. */
24691 if (S_IS_DEFINED (fragp
->fr_symbol
)
24692 && ARM_IS_FUNC (fragp
->fr_symbol
))
24696 if (symbol_preemptible (fragp
->fr_symbol
))
24699 val
= relaxed_symbol_addr (fragp
, stretch
);
24700 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
24703 /* Offset is a signed value *2 */
24705 if (val
>= limit
|| val
< -limit
)
24711 /* Relax a machine dependent frag. This returns the amount by which
24712 the current size of the frag should change. */
24715 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
24720 oldsize
= fragp
->fr_var
;
24721 switch (fragp
->fr_subtype
)
24723 case T_MNEM_ldr_pc2
:
24724 newsize
= relax_adr (fragp
, sec
, stretch
);
24726 case T_MNEM_ldr_pc
:
24727 case T_MNEM_ldr_sp
:
24728 case T_MNEM_str_sp
:
24729 newsize
= relax_immediate (fragp
, 8, 2);
24733 newsize
= relax_immediate (fragp
, 5, 2);
24737 newsize
= relax_immediate (fragp
, 5, 1);
24741 newsize
= relax_immediate (fragp
, 5, 0);
24744 newsize
= relax_adr (fragp
, sec
, stretch
);
24750 newsize
= relax_immediate (fragp
, 8, 0);
24753 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
24756 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
24758 case T_MNEM_add_sp
:
24759 case T_MNEM_add_pc
:
24760 newsize
= relax_immediate (fragp
, 8, 2);
24762 case T_MNEM_inc_sp
:
24763 case T_MNEM_dec_sp
:
24764 newsize
= relax_immediate (fragp
, 7, 2);
24770 newsize
= relax_addsub (fragp
, sec
);
24776 fragp
->fr_var
= newsize
;
24777 /* Freeze wide instructions that are at or before the same location as
24778 in the previous pass. This avoids infinite loops.
24779 Don't freeze them unconditionally because targets may be artificially
24780 misaligned by the expansion of preceding frags. */
24781 if (stretch
<= 0 && newsize
> 2)
24783 md_convert_frag (sec
->owner
, sec
, fragp
);
24787 return newsize
- oldsize
;
24790 /* Round up a section size to the appropriate boundary. */
24793 md_section_align (segT segment ATTRIBUTE_UNUSED
,
24799 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
24800 of an rs_align_code fragment. */
24803 arm_handle_align (fragS
* fragP
)
24805 static unsigned char const arm_noop
[2][2][4] =
24808 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
24809 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
24812 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
24813 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
24816 static unsigned char const thumb_noop
[2][2][2] =
24819 {0xc0, 0x46}, /* LE */
24820 {0x46, 0xc0}, /* BE */
24823 {0x00, 0xbf}, /* LE */
24824 {0xbf, 0x00} /* BE */
24827 static unsigned char const wide_thumb_noop
[2][4] =
24828 { /* Wide Thumb-2 */
24829 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
24830 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
24833 unsigned bytes
, fix
, noop_size
;
24835 const unsigned char * noop
;
24836 const unsigned char *narrow_noop
= NULL
;
24841 if (fragP
->fr_type
!= rs_align_code
)
24844 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
24845 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
24848 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
24849 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
24851 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
24853 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
24855 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
24856 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
24858 narrow_noop
= thumb_noop
[1][target_big_endian
];
24859 noop
= wide_thumb_noop
[target_big_endian
];
24862 noop
= thumb_noop
[0][target_big_endian
];
24870 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
24871 ? selected_cpu
: arm_arch_none
,
24873 [target_big_endian
];
24880 fragP
->fr_var
= noop_size
;
24882 if (bytes
& (noop_size
- 1))
24884 fix
= bytes
& (noop_size
- 1);
24886 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
24888 memset (p
, 0, fix
);
24895 if (bytes
& noop_size
)
24897 /* Insert a narrow noop. */
24898 memcpy (p
, narrow_noop
, noop_size
);
24900 bytes
-= noop_size
;
24904 /* Use wide noops for the remainder */
24908 while (bytes
>= noop_size
)
24910 memcpy (p
, noop
, noop_size
);
24912 bytes
-= noop_size
;
24916 fragP
->fr_fix
+= fix
;
24919 /* Called from md_do_align. Used to create an alignment
24920 frag in a code section. */
24923 arm_frag_align_code (int n
, int max
)
24927 /* We assume that there will never be a requirement
24928 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
24929 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
24934 _("alignments greater than %d bytes not supported in .text sections."),
24935 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
24936 as_fatal ("%s", err_msg
);
24939 p
= frag_var (rs_align_code
,
24940 MAX_MEM_FOR_RS_ALIGN_CODE
,
24942 (relax_substateT
) max
,
24949 /* Perform target specific initialisation of a frag.
24950 Note - despite the name this initialisation is not done when the frag
24951 is created, but only when its type is assigned. A frag can be created
24952 and used a long time before its type is set, so beware of assuming that
24953 this initialisation is performed first. */
24957 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
24959 /* Record whether this frag is in an ARM or a THUMB area. */
24960 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
24963 #else /* OBJ_ELF is defined. */
24965 arm_init_frag (fragS
* fragP
, int max_chars
)
24967 bfd_boolean frag_thumb_mode
;
24969 /* If the current ARM vs THUMB mode has not already
24970 been recorded into this frag then do so now. */
24971 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
24972 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
24974 /* PR 21809: Do not set a mapping state for debug sections
24975 - it just confuses other tools. */
24976 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
24979 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
24981 /* Record a mapping symbol for alignment frags. We will delete this
24982 later if the alignment ends up empty. */
24983 switch (fragP
->fr_type
)
24986 case rs_align_test
:
24988 mapping_state_2 (MAP_DATA
, max_chars
);
24990 case rs_align_code
:
24991 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
24998 /* When we change sections we need to issue a new mapping symbol. */
25001 arm_elf_change_section (void)
25003 /* Link an unlinked unwind index table section to the .text section. */
25004 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
25005 && elf_linked_to_section (now_seg
) == NULL
)
25006 elf_linked_to_section (now_seg
) = text_section
;
25010 arm_elf_section_type (const char * str
, size_t len
)
25012 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
25013 return SHT_ARM_EXIDX
;
25018 /* Code to deal with unwinding tables. */
25020 static void add_unwind_adjustsp (offsetT
);
25022 /* Generate any deferred unwind frame offset. */
25025 flush_pending_unwind (void)
25029 offset
= unwind
.pending_offset
;
25030 unwind
.pending_offset
= 0;
25032 add_unwind_adjustsp (offset
);
25035 /* Add an opcode to this list for this function. Two-byte opcodes should
25036 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
25040 add_unwind_opcode (valueT op
, int length
)
25042 /* Add any deferred stack adjustment. */
25043 if (unwind
.pending_offset
)
25044 flush_pending_unwind ();
25046 unwind
.sp_restored
= 0;
25048 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
25050 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
25051 if (unwind
.opcodes
)
25052 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
25053 unwind
.opcode_alloc
);
25055 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
25060 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
25062 unwind
.opcode_count
++;
25066 /* Add unwind opcodes to adjust the stack pointer. */
25069 add_unwind_adjustsp (offsetT offset
)
25073 if (offset
> 0x200)
25075 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
25080 /* Long form: 0xb2, uleb128. */
25081 /* This might not fit in a word so add the individual bytes,
25082 remembering the list is built in reverse order. */
25083 o
= (valueT
) ((offset
- 0x204) >> 2);
25085 add_unwind_opcode (0, 1);
25087 /* Calculate the uleb128 encoding of the offset. */
25091 bytes
[n
] = o
& 0x7f;
25097 /* Add the insn. */
25099 add_unwind_opcode (bytes
[n
- 1], 1);
25100 add_unwind_opcode (0xb2, 1);
25102 else if (offset
> 0x100)
25104 /* Two short opcodes. */
25105 add_unwind_opcode (0x3f, 1);
25106 op
= (offset
- 0x104) >> 2;
25107 add_unwind_opcode (op
, 1);
25109 else if (offset
> 0)
25111 /* Short opcode. */
25112 op
= (offset
- 4) >> 2;
25113 add_unwind_opcode (op
, 1);
25115 else if (offset
< 0)
25118 while (offset
> 0x100)
25120 add_unwind_opcode (0x7f, 1);
25123 op
= ((offset
- 4) >> 2) | 0x40;
25124 add_unwind_opcode (op
, 1);
25128 /* Finish the list of unwind opcodes for this function. */
25131 finish_unwind_opcodes (void)
25135 if (unwind
.fp_used
)
25137 /* Adjust sp as necessary. */
25138 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
25139 flush_pending_unwind ();
25141 /* After restoring sp from the frame pointer. */
25142 op
= 0x90 | unwind
.fp_reg
;
25143 add_unwind_opcode (op
, 1);
25146 flush_pending_unwind ();
25150 /* Start an exception table entry. If idx is nonzero this is an index table
25154 start_unwind_section (const segT text_seg
, int idx
)
25156 const char * text_name
;
25157 const char * prefix
;
25158 const char * prefix_once
;
25159 const char * group_name
;
25167 prefix
= ELF_STRING_ARM_unwind
;
25168 prefix_once
= ELF_STRING_ARM_unwind_once
;
25169 type
= SHT_ARM_EXIDX
;
25173 prefix
= ELF_STRING_ARM_unwind_info
;
25174 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
25175 type
= SHT_PROGBITS
;
25178 text_name
= segment_name (text_seg
);
25179 if (streq (text_name
, ".text"))
25182 if (strncmp (text_name
, ".gnu.linkonce.t.",
25183 strlen (".gnu.linkonce.t.")) == 0)
25185 prefix
= prefix_once
;
25186 text_name
+= strlen (".gnu.linkonce.t.");
25189 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
25195 /* Handle COMDAT group. */
25196 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
25198 group_name
= elf_group_name (text_seg
);
25199 if (group_name
== NULL
)
25201 as_bad (_("Group section `%s' has no group signature"),
25202 segment_name (text_seg
));
25203 ignore_rest_of_line ();
25206 flags
|= SHF_GROUP
;
25210 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
25213 /* Set the section link for index tables. */
25215 elf_linked_to_section (now_seg
) = text_seg
;
25219 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
25220 personality routine data. Returns zero, or the index table value for
25221 an inline entry. */
25224 create_unwind_entry (int have_data
)
25229 /* The current word of data. */
25231 /* The number of bytes left in this word. */
25234 finish_unwind_opcodes ();
25236 /* Remember the current text section. */
25237 unwind
.saved_seg
= now_seg
;
25238 unwind
.saved_subseg
= now_subseg
;
25240 start_unwind_section (now_seg
, 0);
25242 if (unwind
.personality_routine
== NULL
)
25244 if (unwind
.personality_index
== -2)
25247 as_bad (_("handlerdata in cantunwind frame"));
25248 return 1; /* EXIDX_CANTUNWIND. */
25251 /* Use a default personality routine if none is specified. */
25252 if (unwind
.personality_index
== -1)
25254 if (unwind
.opcode_count
> 3)
25255 unwind
.personality_index
= 1;
25257 unwind
.personality_index
= 0;
25260 /* Space for the personality routine entry. */
25261 if (unwind
.personality_index
== 0)
25263 if (unwind
.opcode_count
> 3)
25264 as_bad (_("too many unwind opcodes for personality routine 0"));
25268 /* All the data is inline in the index table. */
25271 while (unwind
.opcode_count
> 0)
25273 unwind
.opcode_count
--;
25274 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
25278 /* Pad with "finish" opcodes. */
25280 data
= (data
<< 8) | 0xb0;
25287 /* We get two opcodes "free" in the first word. */
25288 size
= unwind
.opcode_count
- 2;
25292 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
25293 if (unwind
.personality_index
!= -1)
25295 as_bad (_("attempt to recreate an unwind entry"));
25299 /* An extra byte is required for the opcode count. */
25300 size
= unwind
.opcode_count
+ 1;
25303 size
= (size
+ 3) >> 2;
25305 as_bad (_("too many unwind opcodes"));
25307 frag_align (2, 0, 0);
25308 record_alignment (now_seg
, 2);
25309 unwind
.table_entry
= expr_build_dot ();
25311 /* Allocate the table entry. */
25312 ptr
= frag_more ((size
<< 2) + 4);
25313 /* PR 13449: Zero the table entries in case some of them are not used. */
25314 memset (ptr
, 0, (size
<< 2) + 4);
25315 where
= frag_now_fix () - ((size
<< 2) + 4);
25317 switch (unwind
.personality_index
)
25320 /* ??? Should this be a PLT generating relocation? */
25321 /* Custom personality routine. */
25322 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
25323 BFD_RELOC_ARM_PREL31
);
25328 /* Set the first byte to the number of additional words. */
25329 data
= size
> 0 ? size
- 1 : 0;
25333 /* ABI defined personality routines. */
25335 /* Three opcodes bytes are packed into the first word. */
25342 /* The size and first two opcode bytes go in the first word. */
25343 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
25348 /* Should never happen. */
25352 /* Pack the opcodes into words (MSB first), reversing the list at the same
25354 while (unwind
.opcode_count
> 0)
25358 md_number_to_chars (ptr
, data
, 4);
25363 unwind
.opcode_count
--;
25365 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
25368 /* Finish off the last word. */
25371 /* Pad with "finish" opcodes. */
25373 data
= (data
<< 8) | 0xb0;
25375 md_number_to_chars (ptr
, data
, 4);
25380 /* Add an empty descriptor if there is no user-specified data. */
25381 ptr
= frag_more (4);
25382 md_number_to_chars (ptr
, 0, 4);
25389 /* Initialize the DWARF-2 unwind information for this procedure. */
25392 tc_arm_frame_initial_instructions (void)
25394 cfi_add_CFA_def_cfa (REG_SP
, 0);
25396 #endif /* OBJ_ELF */
25398 /* Convert REGNAME to a DWARF-2 register number. */
25401 tc_arm_regname_to_dw2regnum (char *regname
)
25403 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
25407 /* PR 16694: Allow VFP registers as well. */
25408 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
25412 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
25421 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
25425 exp
.X_op
= O_secrel
;
25426 exp
.X_add_symbol
= symbol
;
25427 exp
.X_add_number
= 0;
25428 emit_expr (&exp
, size
);
25432 /* MD interface: Symbol and relocation handling. */
25434 /* Return the address within the segment that a PC-relative fixup is
25435 relative to. For ARM, PC-relative fixups applied to instructions
25436 are generally relative to the location of the fixup plus 8 bytes.
25437 Thumb branches are offset by 4, and Thumb loads relative to PC
25438 require special handling. */
25441 md_pcrel_from_section (fixS
* fixP
, segT seg
)
25443 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25445 /* If this is pc-relative and we are going to emit a relocation
25446 then we just want to put out any pipeline compensation that the linker
25447 will need. Otherwise we want to use the calculated base.
25448 For WinCE we skip the bias for externals as well, since this
25449 is how the MS ARM-CE assembler behaves and we want to be compatible. */
25451 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
25452 || (arm_force_relocation (fixP
)
25454 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
25460 switch (fixP
->fx_r_type
)
25462 /* PC relative addressing on the Thumb is slightly odd as the
25463 bottom two bits of the PC are forced to zero for the
25464 calculation. This happens *after* application of the
25465 pipeline offset. However, Thumb adrl already adjusts for
25466 this, so we need not do it again. */
25467 case BFD_RELOC_ARM_THUMB_ADD
:
25470 case BFD_RELOC_ARM_THUMB_OFFSET
:
25471 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
25472 case BFD_RELOC_ARM_T32_ADD_PC12
:
25473 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
25474 return (base
+ 4) & ~3;
25476 /* Thumb branches are simply offset by +4. */
25477 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
25478 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
25479 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
25480 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
25481 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
25482 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
25483 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
25484 case BFD_RELOC_ARM_THUMB_BF17
:
25485 case BFD_RELOC_ARM_THUMB_BF19
:
25486 case BFD_RELOC_ARM_THUMB_BF13
:
25487 case BFD_RELOC_ARM_THUMB_LOOP12
:
25490 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25492 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25493 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25494 && ARM_IS_FUNC (fixP
->fx_addsy
)
25495 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
25496 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25499 /* BLX is like branches above, but forces the low two bits of PC to
25501 case BFD_RELOC_THUMB_PCREL_BLX
:
25503 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25504 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25505 && THUMB_IS_FUNC (fixP
->fx_addsy
)
25506 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
25507 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25508 return (base
+ 4) & ~3;
25510 /* ARM mode branches are offset by +8. However, the Windows CE
25511 loader expects the relocation not to take this into account. */
25512 case BFD_RELOC_ARM_PCREL_BLX
:
25514 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25515 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25516 && ARM_IS_FUNC (fixP
->fx_addsy
)
25517 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
25518 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25521 case BFD_RELOC_ARM_PCREL_CALL
:
25523 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25524 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
25525 && THUMB_IS_FUNC (fixP
->fx_addsy
)
25526 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
25527 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
25530 case BFD_RELOC_ARM_PCREL_BRANCH
:
25531 case BFD_RELOC_ARM_PCREL_JUMP
:
25532 case BFD_RELOC_ARM_PLT32
:
25534 /* When handling fixups immediately, because we have already
25535 discovered the value of a symbol, or the address of the frag involved
25536 we must account for the offset by +8, as the OS loader will never see the reloc.
25537 see fixup_segment() in write.c
25538 The S_IS_EXTERNAL test handles the case of global symbols.
25539 Those need the calculated base, not just the pipe compensation the linker will need. */
25541 && fixP
->fx_addsy
!= NULL
25542 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
25543 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
25551 /* ARM mode loads relative to PC are also offset by +8. Unlike
25552 branches, the Windows CE loader *does* expect the relocation
25553 to take this into account. */
25554 case BFD_RELOC_ARM_OFFSET_IMM
:
25555 case BFD_RELOC_ARM_OFFSET_IMM8
:
25556 case BFD_RELOC_ARM_HWLITERAL
:
25557 case BFD_RELOC_ARM_LITERAL
:
25558 case BFD_RELOC_ARM_CP_OFF_IMM
:
25562 /* Other PC-relative relocations are un-offset. */
25568 static bfd_boolean flag_warn_syms
= TRUE
;
25571 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
25573 /* PR 18347 - Warn if the user attempts to create a symbol with the same
25574 name as an ARM instruction. Whilst strictly speaking it is allowed, it
25575 does mean that the resulting code might be very confusing to the reader.
25576 Also this warning can be triggered if the user omits an operand before
25577 an immediate address, eg:
25581 GAS treats this as an assignment of the value of the symbol foo to a
25582 symbol LDR, and so (without this code) it will not issue any kind of
25583 warning or error message.
25585 Note - ARM instructions are case-insensitive but the strings in the hash
25586 table are all stored in lower case, so we must first ensure that name is
25588 if (flag_warn_syms
&& arm_ops_hsh
)
25590 char * nbuf
= strdup (name
);
25593 for (p
= nbuf
; *p
; p
++)
25595 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
25597 static struct hash_control
* already_warned
= NULL
;
25599 if (already_warned
== NULL
)
25600 already_warned
= hash_new ();
25601 /* Only warn about the symbol once. To keep the code
25602 simple we let hash_insert do the lookup for us. */
25603 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
25604 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
25613 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
25614 Otherwise we have no need to default values of symbols. */
25617 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
25620 if (name
[0] == '_' && name
[1] == 'G'
25621 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
25625 if (symbol_find (name
))
25626 as_bad (_("GOT already in the symbol table"));
25628 GOT_symbol
= symbol_new (name
, undefined_section
,
25629 (valueT
) 0, & zero_address_frag
);
25639 /* Subroutine of md_apply_fix. Check to see if an immediate can be
25640 computed as two separate immediate values, added together. We
25641 already know that this value cannot be computed by just one ARM
25644 static unsigned int
25645 validate_immediate_twopart (unsigned int val
,
25646 unsigned int * highpart
)
25651 for (i
= 0; i
< 32; i
+= 2)
25652 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
25658 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
25660 else if (a
& 0xff0000)
25662 if (a
& 0xff000000)
25664 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
25668 gas_assert (a
& 0xff000000);
25669 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
25672 return (a
& 0xff) | (i
<< 7);
25679 validate_offset_imm (unsigned int val
, int hwse
)
25681 if ((hwse
&& val
> 255) || val
> 4095)
25686 /* Subroutine of md_apply_fix. Do those data_ops which can take a
25687 negative immediate constant by altering the instruction. A bit of
25692 by inverting the second operand, and
25695 by negating the second operand. */
25698 negate_data_op (unsigned long * instruction
,
25699 unsigned long value
)
25702 unsigned long negated
, inverted
;
25704 negated
= encode_arm_immediate (-value
);
25705 inverted
= encode_arm_immediate (~value
);
25707 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
25710 /* First negates. */
25711 case OPCODE_SUB
: /* ADD <-> SUB */
25712 new_inst
= OPCODE_ADD
;
25717 new_inst
= OPCODE_SUB
;
25721 case OPCODE_CMP
: /* CMP <-> CMN */
25722 new_inst
= OPCODE_CMN
;
25727 new_inst
= OPCODE_CMP
;
25731 /* Now Inverted ops. */
25732 case OPCODE_MOV
: /* MOV <-> MVN */
25733 new_inst
= OPCODE_MVN
;
25738 new_inst
= OPCODE_MOV
;
25742 case OPCODE_AND
: /* AND <-> BIC */
25743 new_inst
= OPCODE_BIC
;
25748 new_inst
= OPCODE_AND
;
25752 case OPCODE_ADC
: /* ADC <-> SBC */
25753 new_inst
= OPCODE_SBC
;
25758 new_inst
= OPCODE_ADC
;
25762 /* We cannot do anything. */
25767 if (value
== (unsigned) FAIL
)
25770 *instruction
&= OPCODE_MASK
;
25771 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
25775 /* Like negate_data_op, but for Thumb-2. */
25777 static unsigned int
25778 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
25782 unsigned int negated
, inverted
;
25784 negated
= encode_thumb32_immediate (-value
);
25785 inverted
= encode_thumb32_immediate (~value
);
25787 rd
= (*instruction
>> 8) & 0xf;
25788 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
25791 /* ADD <-> SUB. Includes CMP <-> CMN. */
25792 case T2_OPCODE_SUB
:
25793 new_inst
= T2_OPCODE_ADD
;
25797 case T2_OPCODE_ADD
:
25798 new_inst
= T2_OPCODE_SUB
;
25802 /* ORR <-> ORN. Includes MOV <-> MVN. */
25803 case T2_OPCODE_ORR
:
25804 new_inst
= T2_OPCODE_ORN
;
25808 case T2_OPCODE_ORN
:
25809 new_inst
= T2_OPCODE_ORR
;
25813 /* AND <-> BIC. TST has no inverted equivalent. */
25814 case T2_OPCODE_AND
:
25815 new_inst
= T2_OPCODE_BIC
;
25822 case T2_OPCODE_BIC
:
25823 new_inst
= T2_OPCODE_AND
;
25828 case T2_OPCODE_ADC
:
25829 new_inst
= T2_OPCODE_SBC
;
25833 case T2_OPCODE_SBC
:
25834 new_inst
= T2_OPCODE_ADC
;
25838 /* We cannot do anything. */
25843 if (value
== (unsigned int)FAIL
)
25846 *instruction
&= T2_OPCODE_MASK
;
25847 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
25851 /* Read a 32-bit thumb instruction from buf. */
25853 static unsigned long
25854 get_thumb32_insn (char * buf
)
25856 unsigned long insn
;
25857 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
25858 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25863 /* We usually want to set the low bit on the address of thumb function
25864 symbols. In particular .word foo - . should have the low bit set.
25865 Generic code tries to fold the difference of two symbols to
25866 a constant. Prevent this and force a relocation when the first symbols
25867 is a thumb function. */
25870 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
25872 if (op
== O_subtract
25873 && l
->X_op
== O_symbol
25874 && r
->X_op
== O_symbol
25875 && THUMB_IS_FUNC (l
->X_add_symbol
))
25877 l
->X_op
= O_subtract
;
25878 l
->X_op_symbol
= r
->X_add_symbol
;
25879 l
->X_add_number
-= r
->X_add_number
;
25883 /* Process as normal. */
25887 /* Encode Thumb2 unconditional branches and calls. The encoding
25888 for the 2 are identical for the immediate values. */
25891 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
25893 #define T2I1I2MASK ((1 << 13) | (1 << 11))
25896 addressT S
, I1
, I2
, lo
, hi
;
25898 S
= (value
>> 24) & 0x01;
25899 I1
= (value
>> 23) & 0x01;
25900 I2
= (value
>> 22) & 0x01;
25901 hi
= (value
>> 12) & 0x3ff;
25902 lo
= (value
>> 1) & 0x7ff;
25903 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
25904 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
25905 newval
|= (S
<< 10) | hi
;
25906 newval2
&= ~T2I1I2MASK
;
25907 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
25908 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
25909 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
25913 md_apply_fix (fixS
* fixP
,
25917 offsetT value
= * valP
;
25919 unsigned int newimm
;
25920 unsigned long temp
;
25922 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
25924 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
25926 /* Note whether this will delete the relocation. */
25928 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
25931 /* On a 64-bit host, silently truncate 'value' to 32 bits for
25932 consistency with the behaviour on 32-bit hosts. Remember value
25934 value
&= 0xffffffff;
25935 value
^= 0x80000000;
25936 value
-= 0x80000000;
25939 fixP
->fx_addnumber
= value
;
25941 /* Same treatment for fixP->fx_offset. */
25942 fixP
->fx_offset
&= 0xffffffff;
25943 fixP
->fx_offset
^= 0x80000000;
25944 fixP
->fx_offset
-= 0x80000000;
25946 switch (fixP
->fx_r_type
)
25948 case BFD_RELOC_NONE
:
25949 /* This will need to go in the object file. */
25953 case BFD_RELOC_ARM_IMMEDIATE
:
25954 /* We claim that this fixup has been processed here,
25955 even if in fact we generate an error because we do
25956 not have a reloc for it, so tc_gen_reloc will reject it. */
25959 if (fixP
->fx_addsy
)
25961 const char *msg
= 0;
25963 if (! S_IS_DEFINED (fixP
->fx_addsy
))
25964 msg
= _("undefined symbol %s used as an immediate value");
25965 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
25966 msg
= _("symbol %s is in a different section");
25967 else if (S_IS_WEAK (fixP
->fx_addsy
))
25968 msg
= _("symbol %s is weak and may be overridden later");
25972 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
25973 msg
, S_GET_NAME (fixP
->fx_addsy
));
25978 temp
= md_chars_to_number (buf
, INSN_SIZE
);
25980 /* If the offset is negative, we should use encoding A2 for ADR. */
25981 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
25982 newimm
= negate_data_op (&temp
, value
);
25985 newimm
= encode_arm_immediate (value
);
25987 /* If the instruction will fail, see if we can fix things up by
25988 changing the opcode. */
25989 if (newimm
== (unsigned int) FAIL
)
25990 newimm
= negate_data_op (&temp
, value
);
25991 /* MOV accepts both ARM modified immediate (A1 encoding) and
25992 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
25993 When disassembling, MOV is preferred when there is no encoding
25995 if (newimm
== (unsigned int) FAIL
25996 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
25997 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
25998 && !((temp
>> SBIT_SHIFT
) & 0x1)
25999 && value
>= 0 && value
<= 0xffff)
26001 /* Clear bits[23:20] to change encoding from A1 to A2. */
26002 temp
&= 0xff0fffff;
26003 /* Encoding high 4bits imm. Code below will encode the remaining
26005 temp
|= (value
& 0x0000f000) << 4;
26006 newimm
= value
& 0x00000fff;
26010 if (newimm
== (unsigned int) FAIL
)
26012 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26013 _("invalid constant (%lx) after fixup"),
26014 (unsigned long) value
);
26018 newimm
|= (temp
& 0xfffff000);
26019 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
26022 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
26024 unsigned int highpart
= 0;
26025 unsigned int newinsn
= 0xe1a00000; /* nop. */
26027 if (fixP
->fx_addsy
)
26029 const char *msg
= 0;
26031 if (! S_IS_DEFINED (fixP
->fx_addsy
))
26032 msg
= _("undefined symbol %s used as an immediate value");
26033 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
26034 msg
= _("symbol %s is in a different section");
26035 else if (S_IS_WEAK (fixP
->fx_addsy
))
26036 msg
= _("symbol %s is weak and may be overridden later");
26040 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26041 msg
, S_GET_NAME (fixP
->fx_addsy
));
26046 newimm
= encode_arm_immediate (value
);
26047 temp
= md_chars_to_number (buf
, INSN_SIZE
);
26049 /* If the instruction will fail, see if we can fix things up by
26050 changing the opcode. */
26051 if (newimm
== (unsigned int) FAIL
26052 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
26054 /* No ? OK - try using two ADD instructions to generate
26056 newimm
= validate_immediate_twopart (value
, & highpart
);
26058 /* Yes - then make sure that the second instruction is
26060 if (newimm
!= (unsigned int) FAIL
)
26062 /* Still No ? Try using a negated value. */
26063 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
26064 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
26065 /* Otherwise - give up. */
26068 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26069 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
26074 /* Replace the first operand in the 2nd instruction (which
26075 is the PC) with the destination register. We have
26076 already added in the PC in the first instruction and we
26077 do not want to do it again. */
26078 newinsn
&= ~ 0xf0000;
26079 newinsn
|= ((newinsn
& 0x0f000) << 4);
26082 newimm
|= (temp
& 0xfffff000);
26083 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
26085 highpart
|= (newinsn
& 0xfffff000);
26086 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
26090 case BFD_RELOC_ARM_OFFSET_IMM
:
26091 if (!fixP
->fx_done
&& seg
->use_rela_p
)
26093 /* Fall through. */
26095 case BFD_RELOC_ARM_LITERAL
:
26101 if (validate_offset_imm (value
, 0) == FAIL
)
26103 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
26104 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26105 _("invalid literal constant: pool needs to be closer"));
26107 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26108 _("bad immediate value for offset (%ld)"),
26113 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26115 newval
&= 0xfffff000;
26118 newval
&= 0xff7ff000;
26119 newval
|= value
| (sign
? INDEX_UP
: 0);
26121 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26124 case BFD_RELOC_ARM_OFFSET_IMM8
:
26125 case BFD_RELOC_ARM_HWLITERAL
:
26131 if (validate_offset_imm (value
, 1) == FAIL
)
26133 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
26134 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26135 _("invalid literal constant: pool needs to be closer"));
26137 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26138 _("bad immediate value for 8-bit offset (%ld)"),
26143 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26145 newval
&= 0xfffff0f0;
26148 newval
&= 0xff7ff0f0;
26149 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
26151 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26154 case BFD_RELOC_ARM_T32_OFFSET_U8
:
26155 if (value
< 0 || value
> 1020 || value
% 4 != 0)
26156 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26157 _("bad immediate value for offset (%ld)"), (long) value
);
26160 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
26162 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
26165 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
26166 /* This is a complicated relocation used for all varieties of Thumb32
26167 load/store instruction with immediate offset:
26169 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
26170 *4, optional writeback(W)
26171 (doubleword load/store)
26173 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
26174 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
26175 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
26176 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
26177 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
26179 Uppercase letters indicate bits that are already encoded at
26180 this point. Lowercase letters are our problem. For the
26181 second block of instructions, the secondary opcode nybble
26182 (bits 8..11) is present, and bit 23 is zero, even if this is
26183 a PC-relative operation. */
26184 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26186 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
26188 if ((newval
& 0xf0000000) == 0xe0000000)
26190 /* Doubleword load/store: 8-bit offset, scaled by 4. */
26192 newval
|= (1 << 23);
26195 if (value
% 4 != 0)
26197 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26198 _("offset not a multiple of 4"));
26204 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26205 _("offset out of range"));
26210 else if ((newval
& 0x000f0000) == 0x000f0000)
26212 /* PC-relative, 12-bit offset. */
26214 newval
|= (1 << 23);
26219 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26220 _("offset out of range"));
26225 else if ((newval
& 0x00000100) == 0x00000100)
26227 /* Writeback: 8-bit, +/- offset. */
26229 newval
|= (1 << 9);
26234 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26235 _("offset out of range"));
26240 else if ((newval
& 0x00000f00) == 0x00000e00)
26242 /* T-instruction: positive 8-bit offset. */
26243 if (value
< 0 || value
> 0xff)
26245 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26246 _("offset out of range"));
26254 /* Positive 12-bit or negative 8-bit offset. */
26258 newval
|= (1 << 23);
26268 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26269 _("offset out of range"));
26276 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
26277 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
26280 case BFD_RELOC_ARM_SHIFT_IMM
:
26281 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26282 if (((unsigned long) value
) > 32
26284 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
26286 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26287 _("shift expression is too large"));
26292 /* Shifts of zero must be done as lsl. */
26294 else if (value
== 32)
26296 newval
&= 0xfffff07f;
26297 newval
|= (value
& 0x1f) << 7;
26298 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26301 case BFD_RELOC_ARM_T32_IMMEDIATE
:
26302 case BFD_RELOC_ARM_T32_ADD_IMM
:
26303 case BFD_RELOC_ARM_T32_IMM12
:
26304 case BFD_RELOC_ARM_T32_ADD_PC12
:
26305 /* We claim that this fixup has been processed here,
26306 even if in fact we generate an error because we do
26307 not have a reloc for it, so tc_gen_reloc will reject it. */
26311 && ! S_IS_DEFINED (fixP
->fx_addsy
))
26313 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26314 _("undefined symbol %s used as an immediate value"),
26315 S_GET_NAME (fixP
->fx_addsy
));
26319 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26321 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
26324 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
26325 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
26326 Thumb2 modified immediate encoding (T2). */
26327 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
26328 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
26330 newimm
= encode_thumb32_immediate (value
);
26331 if (newimm
== (unsigned int) FAIL
)
26332 newimm
= thumb32_negate_data_op (&newval
, value
);
26334 if (newimm
== (unsigned int) FAIL
)
26336 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
26338 /* Turn add/sum into addw/subw. */
26339 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
26340 newval
= (newval
& 0xfeffffff) | 0x02000000;
26341 /* No flat 12-bit imm encoding for addsw/subsw. */
26342 if ((newval
& 0x00100000) == 0)
26344 /* 12 bit immediate for addw/subw. */
26348 newval
^= 0x00a00000;
26351 newimm
= (unsigned int) FAIL
;
26358 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
26359 UINT16 (T3 encoding), MOVW only accepts UINT16. When
26360 disassembling, MOV is preferred when there is no encoding
26362 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
26363 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
26364 but with the Rn field [19:16] set to 1111. */
26365 && (((newval
>> 16) & 0xf) == 0xf)
26366 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
26367 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
26368 && value
>= 0 && value
<= 0xffff)
26370 /* Toggle bit[25] to change encoding from T2 to T3. */
26372 /* Clear bits[19:16]. */
26373 newval
&= 0xfff0ffff;
26374 /* Encoding high 4bits imm. Code below will encode the
26375 remaining low 12bits. */
26376 newval
|= (value
& 0x0000f000) << 4;
26377 newimm
= value
& 0x00000fff;
26382 if (newimm
== (unsigned int)FAIL
)
26384 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26385 _("invalid constant (%lx) after fixup"),
26386 (unsigned long) value
);
26390 newval
|= (newimm
& 0x800) << 15;
26391 newval
|= (newimm
& 0x700) << 4;
26392 newval
|= (newimm
& 0x0ff);
26394 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
26395 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
26398 case BFD_RELOC_ARM_SMC
:
26399 if (((unsigned long) value
) > 0xffff)
26400 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26401 _("invalid smc expression"));
26402 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26403 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
26404 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26407 case BFD_RELOC_ARM_HVC
:
26408 if (((unsigned long) value
) > 0xffff)
26409 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26410 _("invalid hvc expression"));
26411 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26412 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
26413 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26416 case BFD_RELOC_ARM_SWI
:
26417 if (fixP
->tc_fix_data
!= 0)
26419 if (((unsigned long) value
) > 0xff)
26420 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26421 _("invalid swi expression"));
26422 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26424 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26428 if (((unsigned long) value
) > 0x00ffffff)
26429 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26430 _("invalid swi expression"));
26431 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26433 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26437 case BFD_RELOC_ARM_MULTI
:
26438 if (((unsigned long) value
) > 0xffff)
26439 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26440 _("invalid expression in load/store multiple"));
26441 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
26442 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26446 case BFD_RELOC_ARM_PCREL_CALL
:
26448 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26450 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26451 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26452 && THUMB_IS_FUNC (fixP
->fx_addsy
))
26453 /* Flip the bl to blx. This is a simple flip
26454 bit here because we generate PCREL_CALL for
26455 unconditional bls. */
26457 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26458 newval
= newval
| 0x10000000;
26459 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26465 goto arm_branch_common
;
26467 case BFD_RELOC_ARM_PCREL_JUMP
:
26468 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26470 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26471 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26472 && THUMB_IS_FUNC (fixP
->fx_addsy
))
26474 /* This would map to a bl<cond>, b<cond>,
26475 b<always> to a Thumb function. We
26476 need to force a relocation for this particular
26478 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26481 /* Fall through. */
26483 case BFD_RELOC_ARM_PLT32
:
26485 case BFD_RELOC_ARM_PCREL_BRANCH
:
26487 goto arm_branch_common
;
26489 case BFD_RELOC_ARM_PCREL_BLX
:
26492 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26494 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26495 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26496 && ARM_IS_FUNC (fixP
->fx_addsy
))
26498 /* Flip the blx to a bl and warn. */
26499 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
26500 newval
= 0xeb000000;
26501 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
26502 _("blx to '%s' an ARM ISA state function changed to bl"),
26504 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26510 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
26511 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
26515 /* We are going to store value (shifted right by two) in the
26516 instruction, in a 24 bit, signed field. Bits 26 through 32 either
26517 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
26520 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26521 _("misaligned branch destination"));
26522 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
26523 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
26524 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26526 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26528 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26529 newval
|= (value
>> 2) & 0x00ffffff;
26530 /* Set the H bit on BLX instructions. */
26534 newval
|= 0x01000000;
26536 newval
&= ~0x01000000;
26538 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26542 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
26543 /* CBZ can only branch forward. */
26545 /* Attempts to use CBZ to branch to the next instruction
26546 (which, strictly speaking, are prohibited) will be turned into
26549 FIXME: It may be better to remove the instruction completely and
26550 perform relaxation. */
26553 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26554 newval
= 0xbf00; /* NOP encoding T1 */
26555 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26560 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26562 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26564 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26565 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
26566 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26571 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
26572 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
26573 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26575 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26577 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26578 newval
|= (value
& 0x1ff) >> 1;
26579 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26583 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
26584 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
26585 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26587 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26589 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26590 newval
|= (value
& 0xfff) >> 1;
26591 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26595 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
26597 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26598 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26599 && ARM_IS_FUNC (fixP
->fx_addsy
)
26600 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26602 /* Force a relocation for a branch 20 bits wide. */
26605 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
26606 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26607 _("conditional branch out of range"));
26609 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26612 addressT S
, J1
, J2
, lo
, hi
;
26614 S
= (value
& 0x00100000) >> 20;
26615 J2
= (value
& 0x00080000) >> 19;
26616 J1
= (value
& 0x00040000) >> 18;
26617 hi
= (value
& 0x0003f000) >> 12;
26618 lo
= (value
& 0x00000ffe) >> 1;
26620 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26621 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26622 newval
|= (S
<< 10) | hi
;
26623 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
26624 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26625 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
26629 case BFD_RELOC_THUMB_PCREL_BLX
:
26630 /* If there is a blx from a thumb state function to
26631 another thumb function flip this to a bl and warn
26635 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26636 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26637 && THUMB_IS_FUNC (fixP
->fx_addsy
))
26639 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
26640 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
26641 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
26643 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26644 newval
= newval
| 0x1000;
26645 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
26646 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
26651 goto thumb_bl_common
;
26653 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26654 /* A bl from Thumb state ISA to an internal ARM state function
26655 is converted to a blx. */
26657 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26658 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26659 && ARM_IS_FUNC (fixP
->fx_addsy
)
26660 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26662 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
26663 newval
= newval
& ~0x1000;
26664 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
26665 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
26671 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
26672 /* For a BLX instruction, make sure that the relocation is rounded up
26673 to a word boundary. This follows the semantics of the instruction
26674 which specifies that bit 1 of the target address will come from bit
26675 1 of the base address. */
26676 value
= (value
+ 3) & ~ 3;
26679 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
26680 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
26681 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
26684 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
26686 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
26687 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26688 else if ((value
& ~0x1ffffff)
26689 && ((value
& ~0x1ffffff) != ~0x1ffffff))
26690 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26691 _("Thumb2 branch out of range"));
26694 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26695 encode_thumb2_b_bl_offset (buf
, value
);
26699 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
26700 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
26701 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
26703 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26704 encode_thumb2_b_bl_offset (buf
, value
);
26709 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26714 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26715 md_number_to_chars (buf
, value
, 2);
26719 case BFD_RELOC_ARM_TLS_CALL
:
26720 case BFD_RELOC_ARM_THM_TLS_CALL
:
26721 case BFD_RELOC_ARM_TLS_DESCSEQ
:
26722 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
26723 case BFD_RELOC_ARM_TLS_GOTDESC
:
26724 case BFD_RELOC_ARM_TLS_GD32
:
26725 case BFD_RELOC_ARM_TLS_LE32
:
26726 case BFD_RELOC_ARM_TLS_IE32
:
26727 case BFD_RELOC_ARM_TLS_LDM32
:
26728 case BFD_RELOC_ARM_TLS_LDO32
:
26729 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
26732 /* Same handling as above, but with the arm_fdpic guard. */
26733 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
26734 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
26735 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
26738 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
26742 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26743 _("Relocation supported only in FDPIC mode"));
26747 case BFD_RELOC_ARM_GOT32
:
26748 case BFD_RELOC_ARM_GOTOFF
:
26751 case BFD_RELOC_ARM_GOT_PREL
:
26752 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26753 md_number_to_chars (buf
, value
, 4);
26756 case BFD_RELOC_ARM_TARGET2
:
26757 /* TARGET2 is not partial-inplace, so we need to write the
26758 addend here for REL targets, because it won't be written out
26759 during reloc processing later. */
26760 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26761 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
26764 /* Relocations for FDPIC. */
26765 case BFD_RELOC_ARM_GOTFUNCDESC
:
26766 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
26767 case BFD_RELOC_ARM_FUNCDESC
:
26770 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26771 md_number_to_chars (buf
, 0, 4);
26775 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26776 _("Relocation supported only in FDPIC mode"));
26781 case BFD_RELOC_RVA
:
26783 case BFD_RELOC_ARM_TARGET1
:
26784 case BFD_RELOC_ARM_ROSEGREL32
:
26785 case BFD_RELOC_ARM_SBREL32
:
26786 case BFD_RELOC_32_PCREL
:
26788 case BFD_RELOC_32_SECREL
:
26790 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26792 /* For WinCE we only do this for pcrel fixups. */
26793 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
26795 md_number_to_chars (buf
, value
, 4);
26799 case BFD_RELOC_ARM_PREL31
:
26800 if (fixP
->fx_done
|| !seg
->use_rela_p
)
26802 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
26803 if ((value
^ (value
>> 1)) & 0x40000000)
26805 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26806 _("rel31 relocation overflow"));
26808 newval
|= value
& 0x7fffffff;
26809 md_number_to_chars (buf
, newval
, 4);
26814 case BFD_RELOC_ARM_CP_OFF_IMM
:
26815 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
26816 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
26817 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
26818 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26820 newval
= get_thumb32_insn (buf
);
26821 if ((newval
& 0x0f200f00) == 0x0d000900)
26823 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
26824 has permitted values that are multiples of 2, in the range 0
26826 if (value
< -510 || value
> 510 || (value
& 1))
26827 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26828 _("co-processor offset out of range"));
26830 else if ((newval
& 0xfe001f80) == 0xec000f80)
26832 if (value
< -511 || value
> 512 || (value
& 3))
26833 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26834 _("co-processor offset out of range"));
26836 else if (value
< -1023 || value
> 1023 || (value
& 3))
26837 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26838 _("co-processor offset out of range"));
26843 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
26844 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
26845 newval
= md_chars_to_number (buf
, INSN_SIZE
);
26847 newval
= get_thumb32_insn (buf
);
26850 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
26851 newval
&= 0xffffff80;
26853 newval
&= 0xffffff00;
26857 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
26858 newval
&= 0xff7fff80;
26860 newval
&= 0xff7fff00;
26861 if ((newval
& 0x0f200f00) == 0x0d000900)
26863 /* This is a fp16 vstr/vldr.
26865 It requires the immediate offset in the instruction is shifted
26866 left by 1 to be a half-word offset.
26868 Here, left shift by 1 first, and later right shift by 2
26869 should get the right offset. */
26872 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
26874 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
26875 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
26876 md_number_to_chars (buf
, newval
, INSN_SIZE
);
26878 put_thumb32_insn (buf
, newval
);
26881 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
26882 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
26883 if (value
< -255 || value
> 255)
26884 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26885 _("co-processor offset out of range"));
26887 goto cp_off_common
;
26889 case BFD_RELOC_ARM_THUMB_OFFSET
:
26890 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26891 /* Exactly what ranges, and where the offset is inserted depends
26892 on the type of instruction, we can establish this from the
26894 switch (newval
>> 12)
26896 case 4: /* PC load. */
26897 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
26898 forced to zero for these loads; md_pcrel_from has already
26899 compensated for this. */
26901 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26902 _("invalid offset, target not word aligned (0x%08lX)"),
26903 (((unsigned long) fixP
->fx_frag
->fr_address
26904 + (unsigned long) fixP
->fx_where
) & ~3)
26905 + (unsigned long) value
);
26907 if (value
& ~0x3fc)
26908 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26909 _("invalid offset, value too big (0x%08lX)"),
26912 newval
|= value
>> 2;
26915 case 9: /* SP load/store. */
26916 if (value
& ~0x3fc)
26917 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26918 _("invalid offset, value too big (0x%08lX)"),
26920 newval
|= value
>> 2;
26923 case 6: /* Word load/store. */
26925 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26926 _("invalid offset, value too big (0x%08lX)"),
26928 newval
|= value
<< 4; /* 6 - 2. */
26931 case 7: /* Byte load/store. */
26933 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26934 _("invalid offset, value too big (0x%08lX)"),
26936 newval
|= value
<< 6;
26939 case 8: /* Halfword load/store. */
26941 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26942 _("invalid offset, value too big (0x%08lX)"),
26944 newval
|= value
<< 5; /* 6 - 1. */
26948 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26949 "Unable to process relocation for thumb opcode: %lx",
26950 (unsigned long) newval
);
26953 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
26956 case BFD_RELOC_ARM_THUMB_ADD
:
26957 /* This is a complicated relocation, since we use it for all of
26958 the following immediate relocations:
26962 9bit ADD/SUB SP word-aligned
26963 10bit ADD PC/SP word-aligned
26965 The type of instruction being processed is encoded in the
26972 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
26974 int rd
= (newval
>> 4) & 0xf;
26975 int rs
= newval
& 0xf;
26976 int subtract
= !!(newval
& 0x8000);
26978 /* Check for HI regs, only very restricted cases allowed:
26979 Adjusting SP, and using PC or SP to get an address. */
26980 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
26981 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
26982 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26983 _("invalid Hi register with immediate"));
26985 /* If value is negative, choose the opposite instruction. */
26989 subtract
= !subtract
;
26991 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26992 _("immediate value out of range"));
26997 if (value
& ~0x1fc)
26998 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
26999 _("invalid immediate for stack address calculation"));
27000 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
27001 newval
|= value
>> 2;
27003 else if (rs
== REG_PC
|| rs
== REG_SP
)
27005 /* PR gas/18541. If the addition is for a defined symbol
27006 within range of an ADR instruction then accept it. */
27009 && fixP
->fx_addsy
!= NULL
)
27013 if (! S_IS_DEFINED (fixP
->fx_addsy
)
27014 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
27015 || S_IS_WEAK (fixP
->fx_addsy
))
27017 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27018 _("address calculation needs a strongly defined nearby symbol"));
27022 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27024 /* Round up to the next 4-byte boundary. */
27029 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
27033 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27034 _("symbol too far away"));
27044 if (subtract
|| value
& ~0x3fc)
27045 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27046 _("invalid immediate for address calculation (value = 0x%08lX)"),
27047 (unsigned long) (subtract
? - value
: value
));
27048 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
27050 newval
|= value
>> 2;
27055 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27056 _("immediate value out of range"));
27057 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
27058 newval
|= (rd
<< 8) | value
;
27063 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27064 _("immediate value out of range"));
27065 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
27066 newval
|= rd
| (rs
<< 3) | (value
<< 6);
27069 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27072 case BFD_RELOC_ARM_THUMB_IMM
:
27073 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27074 if (value
< 0 || value
> 255)
27075 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27076 _("invalid immediate: %ld is out of range"),
27079 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27082 case BFD_RELOC_ARM_THUMB_SHIFT
:
27083 /* 5bit shift value (0..32). LSL cannot take 32. */
27084 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
27085 temp
= newval
& 0xf800;
27086 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
27087 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27088 _("invalid shift value: %ld"), (long) value
);
27089 /* Shifts of zero must be encoded as LSL. */
27091 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
27092 /* Shifts of 32 are encoded as zero. */
27093 else if (value
== 32)
27095 newval
|= value
<< 6;
27096 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27099 case BFD_RELOC_VTABLE_INHERIT
:
27100 case BFD_RELOC_VTABLE_ENTRY
:
27104 case BFD_RELOC_ARM_MOVW
:
27105 case BFD_RELOC_ARM_MOVT
:
27106 case BFD_RELOC_ARM_THUMB_MOVW
:
27107 case BFD_RELOC_ARM_THUMB_MOVT
:
27108 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27110 /* REL format relocations are limited to a 16-bit addend. */
27111 if (!fixP
->fx_done
)
27113 if (value
< -0x8000 || value
> 0x7fff)
27114 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27115 _("offset out of range"));
27117 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
27118 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
27123 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
27124 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
27126 newval
= get_thumb32_insn (buf
);
27127 newval
&= 0xfbf08f00;
27128 newval
|= (value
& 0xf000) << 4;
27129 newval
|= (value
& 0x0800) << 15;
27130 newval
|= (value
& 0x0700) << 4;
27131 newval
|= (value
& 0x00ff);
27132 put_thumb32_insn (buf
, newval
);
27136 newval
= md_chars_to_number (buf
, 4);
27137 newval
&= 0xfff0f000;
27138 newval
|= value
& 0x0fff;
27139 newval
|= (value
& 0xf000) << 4;
27140 md_number_to_chars (buf
, newval
, 4);
27145 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
27146 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
27147 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
27148 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
27149 gas_assert (!fixP
->fx_done
);
27152 bfd_boolean is_mov
;
27153 bfd_vma encoded_addend
= value
;
27155 /* Check that addend can be encoded in instruction. */
27156 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
27157 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27158 _("the offset 0x%08lX is not representable"),
27159 (unsigned long) encoded_addend
);
27161 /* Extract the instruction. */
27162 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
27163 is_mov
= (insn
& 0xf800) == 0x2000;
27168 if (!seg
->use_rela_p
)
27169 insn
|= encoded_addend
;
27175 /* Extract the instruction. */
27176 /* Encoding is the following
27181 /* The following conditions must be true :
27186 rd
= (insn
>> 4) & 0xf;
27188 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
27189 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27190 _("Unable to process relocation for thumb opcode: %lx"),
27191 (unsigned long) insn
);
27193 /* Encode as ADD immediate8 thumb 1 code. */
27194 insn
= 0x3000 | (rd
<< 8);
27196 /* Place the encoded addend into the first 8 bits of the
27198 if (!seg
->use_rela_p
)
27199 insn
|= encoded_addend
;
27202 /* Update the instruction. */
27203 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
27207 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
27208 case BFD_RELOC_ARM_ALU_PC_G0
:
27209 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
27210 case BFD_RELOC_ARM_ALU_PC_G1
:
27211 case BFD_RELOC_ARM_ALU_PC_G2
:
27212 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
27213 case BFD_RELOC_ARM_ALU_SB_G0
:
27214 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
27215 case BFD_RELOC_ARM_ALU_SB_G1
:
27216 case BFD_RELOC_ARM_ALU_SB_G2
:
27217 gas_assert (!fixP
->fx_done
);
27218 if (!seg
->use_rela_p
)
27221 bfd_vma encoded_addend
;
27222 bfd_vma addend_abs
= llabs (value
);
27224 /* Check that the absolute value of the addend can be
27225 expressed as an 8-bit constant plus a rotation. */
27226 encoded_addend
= encode_arm_immediate (addend_abs
);
27227 if (encoded_addend
== (unsigned int) FAIL
)
27228 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27229 _("the offset 0x%08lX is not representable"),
27230 (unsigned long) addend_abs
);
27232 /* Extract the instruction. */
27233 insn
= md_chars_to_number (buf
, INSN_SIZE
);
27235 /* If the addend is positive, use an ADD instruction.
27236 Otherwise use a SUB. Take care not to destroy the S bit. */
27237 insn
&= 0xff1fffff;
27243 /* Place the encoded addend into the first 12 bits of the
27245 insn
&= 0xfffff000;
27246 insn
|= encoded_addend
;
27248 /* Update the instruction. */
27249 md_number_to_chars (buf
, insn
, INSN_SIZE
);
27253 case BFD_RELOC_ARM_LDR_PC_G0
:
27254 case BFD_RELOC_ARM_LDR_PC_G1
:
27255 case BFD_RELOC_ARM_LDR_PC_G2
:
27256 case BFD_RELOC_ARM_LDR_SB_G0
:
27257 case BFD_RELOC_ARM_LDR_SB_G1
:
27258 case BFD_RELOC_ARM_LDR_SB_G2
:
27259 gas_assert (!fixP
->fx_done
);
27260 if (!seg
->use_rela_p
)
27263 bfd_vma addend_abs
= llabs (value
);
27265 /* Check that the absolute value of the addend can be
27266 encoded in 12 bits. */
27267 if (addend_abs
>= 0x1000)
27268 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27269 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
27270 (unsigned long) addend_abs
);
27272 /* Extract the instruction. */
27273 insn
= md_chars_to_number (buf
, INSN_SIZE
);
27275 /* If the addend is negative, clear bit 23 of the instruction.
27276 Otherwise set it. */
27278 insn
&= ~(1 << 23);
27282 /* Place the absolute value of the addend into the first 12 bits
27283 of the instruction. */
27284 insn
&= 0xfffff000;
27285 insn
|= addend_abs
;
27287 /* Update the instruction. */
27288 md_number_to_chars (buf
, insn
, INSN_SIZE
);
27292 case BFD_RELOC_ARM_LDRS_PC_G0
:
27293 case BFD_RELOC_ARM_LDRS_PC_G1
:
27294 case BFD_RELOC_ARM_LDRS_PC_G2
:
27295 case BFD_RELOC_ARM_LDRS_SB_G0
:
27296 case BFD_RELOC_ARM_LDRS_SB_G1
:
27297 case BFD_RELOC_ARM_LDRS_SB_G2
:
27298 gas_assert (!fixP
->fx_done
);
27299 if (!seg
->use_rela_p
)
27302 bfd_vma addend_abs
= llabs (value
);
27304 /* Check that the absolute value of the addend can be
27305 encoded in 8 bits. */
27306 if (addend_abs
>= 0x100)
27307 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27308 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
27309 (unsigned long) addend_abs
);
27311 /* Extract the instruction. */
27312 insn
= md_chars_to_number (buf
, INSN_SIZE
);
27314 /* If the addend is negative, clear bit 23 of the instruction.
27315 Otherwise set it. */
27317 insn
&= ~(1 << 23);
27321 /* Place the first four bits of the absolute value of the addend
27322 into the first 4 bits of the instruction, and the remaining
27323 four into bits 8 .. 11. */
27324 insn
&= 0xfffff0f0;
27325 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
27327 /* Update the instruction. */
27328 md_number_to_chars (buf
, insn
, INSN_SIZE
);
27332 case BFD_RELOC_ARM_LDC_PC_G0
:
27333 case BFD_RELOC_ARM_LDC_PC_G1
:
27334 case BFD_RELOC_ARM_LDC_PC_G2
:
27335 case BFD_RELOC_ARM_LDC_SB_G0
:
27336 case BFD_RELOC_ARM_LDC_SB_G1
:
27337 case BFD_RELOC_ARM_LDC_SB_G2
:
27338 gas_assert (!fixP
->fx_done
);
27339 if (!seg
->use_rela_p
)
27342 bfd_vma addend_abs
= llabs (value
);
27344 /* Check that the absolute value of the addend is a multiple of
27345 four and, when divided by four, fits in 8 bits. */
27346 if (addend_abs
& 0x3)
27347 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27348 _("bad offset 0x%08lX (must be word-aligned)"),
27349 (unsigned long) addend_abs
);
27351 if ((addend_abs
>> 2) > 0xff)
27352 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27353 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
27354 (unsigned long) addend_abs
);
27356 /* Extract the instruction. */
27357 insn
= md_chars_to_number (buf
, INSN_SIZE
);
27359 /* If the addend is negative, clear bit 23 of the instruction.
27360 Otherwise set it. */
27362 insn
&= ~(1 << 23);
27366 /* Place the addend (divided by four) into the first eight
27367 bits of the instruction. */
27368 insn
&= 0xfffffff0;
27369 insn
|= addend_abs
>> 2;
27371 /* Update the instruction. */
27372 md_number_to_chars (buf
, insn
, INSN_SIZE
);
27376 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
27378 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27379 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27380 && ARM_IS_FUNC (fixP
->fx_addsy
)
27381 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27383 /* Force a relocation for a branch 5 bits wide. */
27386 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
27387 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27390 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27392 addressT boff
= value
>> 1;
27394 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27395 newval
|= (boff
<< 7);
27396 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27400 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
27402 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27403 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27404 && ARM_IS_FUNC (fixP
->fx_addsy
)
27405 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27409 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
27410 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27411 _("branch out of range"));
27413 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27415 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27417 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
27418 addressT diff
= value
- boff
;
27422 newval
|= 1 << 1; /* T bit. */
27424 else if (diff
!= 2)
27426 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27427 _("out of range label-relative fixup value"));
27429 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27433 case BFD_RELOC_ARM_THUMB_BF17
:
27435 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27436 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27437 && ARM_IS_FUNC (fixP
->fx_addsy
)
27438 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27440 /* Force a relocation for a branch 17 bits wide. */
27444 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
27445 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27448 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27451 addressT immA
, immB
, immC
;
27453 immA
= (value
& 0x0001f000) >> 12;
27454 immB
= (value
& 0x00000ffc) >> 2;
27455 immC
= (value
& 0x00000002) >> 1;
27457 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27458 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27460 newval2
|= (immC
<< 11) | (immB
<< 1);
27461 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27462 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27466 case BFD_RELOC_ARM_THUMB_BF19
:
27468 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27469 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27470 && ARM_IS_FUNC (fixP
->fx_addsy
)
27471 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27473 /* Force a relocation for a branch 19 bits wide. */
27477 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
27478 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27481 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27484 addressT immA
, immB
, immC
;
27486 immA
= (value
& 0x0007f000) >> 12;
27487 immB
= (value
& 0x00000ffc) >> 2;
27488 immC
= (value
& 0x00000002) >> 1;
27490 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27491 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27493 newval2
|= (immC
<< 11) | (immB
<< 1);
27494 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27495 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27499 case BFD_RELOC_ARM_THUMB_BF13
:
27501 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27502 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27503 && ARM_IS_FUNC (fixP
->fx_addsy
)
27504 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27506 /* Force a relocation for a branch 13 bits wide. */
27510 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
27511 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27514 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27517 addressT immA
, immB
, immC
;
27519 immA
= (value
& 0x00001000) >> 12;
27520 immB
= (value
& 0x00000ffc) >> 2;
27521 immC
= (value
& 0x00000002) >> 1;
27523 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27524 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27526 newval2
|= (immC
<< 11) | (immB
<< 1);
27527 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27528 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27532 case BFD_RELOC_ARM_THUMB_LOOP12
:
27534 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27535 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27536 && ARM_IS_FUNC (fixP
->fx_addsy
)
27537 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
27539 /* Force a relocation for a branch 12 bits wide. */
27543 bfd_vma insn
= get_thumb32_insn (buf
);
27544 /* le lr, <label> or le <label> */
27545 if (((insn
& 0xffffffff) == 0xf00fc001)
27546 || ((insn
& 0xffffffff) == 0xf02fc001))
27549 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
27550 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27552 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27554 addressT imml
, immh
;
27556 immh
= (value
& 0x00000ffc) >> 2;
27557 imml
= (value
& 0x00000002) >> 1;
27559 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27560 newval
|= (imml
<< 11) | (immh
<< 1);
27561 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
27565 case BFD_RELOC_ARM_V4BX
:
27566 /* This will need to go in the object file. */
27570 case BFD_RELOC_UNUSED
:
27572 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27573 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
27577 /* Translate internal representation of relocation info to BFD target
27581 tc_gen_reloc (asection
*section
, fixS
*fixp
)
27584 bfd_reloc_code_real_type code
;
27586 reloc
= XNEW (arelent
);
27588 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
27589 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
27590 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
27592 if (fixp
->fx_pcrel
)
27594 if (section
->use_rela_p
)
27595 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
27597 fixp
->fx_offset
= reloc
->address
;
27599 reloc
->addend
= fixp
->fx_offset
;
27601 switch (fixp
->fx_r_type
)
27604 if (fixp
->fx_pcrel
)
27606 code
= BFD_RELOC_8_PCREL
;
27609 /* Fall through. */
27612 if (fixp
->fx_pcrel
)
27614 code
= BFD_RELOC_16_PCREL
;
27617 /* Fall through. */
27620 if (fixp
->fx_pcrel
)
27622 code
= BFD_RELOC_32_PCREL
;
27625 /* Fall through. */
27627 case BFD_RELOC_ARM_MOVW
:
27628 if (fixp
->fx_pcrel
)
27630 code
= BFD_RELOC_ARM_MOVW_PCREL
;
27633 /* Fall through. */
27635 case BFD_RELOC_ARM_MOVT
:
27636 if (fixp
->fx_pcrel
)
27638 code
= BFD_RELOC_ARM_MOVT_PCREL
;
27641 /* Fall through. */
27643 case BFD_RELOC_ARM_THUMB_MOVW
:
27644 if (fixp
->fx_pcrel
)
27646 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
27649 /* Fall through. */
27651 case BFD_RELOC_ARM_THUMB_MOVT
:
27652 if (fixp
->fx_pcrel
)
27654 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
27657 /* Fall through. */
27659 case BFD_RELOC_NONE
:
27660 case BFD_RELOC_ARM_PCREL_BRANCH
:
27661 case BFD_RELOC_ARM_PCREL_BLX
:
27662 case BFD_RELOC_RVA
:
27663 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
27664 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
27665 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
27666 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27667 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27668 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27669 case BFD_RELOC_VTABLE_ENTRY
:
27670 case BFD_RELOC_VTABLE_INHERIT
:
27672 case BFD_RELOC_32_SECREL
:
27674 code
= fixp
->fx_r_type
;
27677 case BFD_RELOC_THUMB_PCREL_BLX
:
27679 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
27680 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
27683 code
= BFD_RELOC_THUMB_PCREL_BLX
;
27686 case BFD_RELOC_ARM_LITERAL
:
27687 case BFD_RELOC_ARM_HWLITERAL
:
27688 /* If this is called then the a literal has
27689 been referenced across a section boundary. */
27690 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27691 _("literal referenced across section boundary"));
27695 case BFD_RELOC_ARM_TLS_CALL
:
27696 case BFD_RELOC_ARM_THM_TLS_CALL
:
27697 case BFD_RELOC_ARM_TLS_DESCSEQ
:
27698 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
27699 case BFD_RELOC_ARM_GOT32
:
27700 case BFD_RELOC_ARM_GOTOFF
:
27701 case BFD_RELOC_ARM_GOT_PREL
:
27702 case BFD_RELOC_ARM_PLT32
:
27703 case BFD_RELOC_ARM_TARGET1
:
27704 case BFD_RELOC_ARM_ROSEGREL32
:
27705 case BFD_RELOC_ARM_SBREL32
:
27706 case BFD_RELOC_ARM_PREL31
:
27707 case BFD_RELOC_ARM_TARGET2
:
27708 case BFD_RELOC_ARM_TLS_LDO32
:
27709 case BFD_RELOC_ARM_PCREL_CALL
:
27710 case BFD_RELOC_ARM_PCREL_JUMP
:
27711 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
27712 case BFD_RELOC_ARM_ALU_PC_G0
:
27713 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
27714 case BFD_RELOC_ARM_ALU_PC_G1
:
27715 case BFD_RELOC_ARM_ALU_PC_G2
:
27716 case BFD_RELOC_ARM_LDR_PC_G0
:
27717 case BFD_RELOC_ARM_LDR_PC_G1
:
27718 case BFD_RELOC_ARM_LDR_PC_G2
:
27719 case BFD_RELOC_ARM_LDRS_PC_G0
:
27720 case BFD_RELOC_ARM_LDRS_PC_G1
:
27721 case BFD_RELOC_ARM_LDRS_PC_G2
:
27722 case BFD_RELOC_ARM_LDC_PC_G0
:
27723 case BFD_RELOC_ARM_LDC_PC_G1
:
27724 case BFD_RELOC_ARM_LDC_PC_G2
:
27725 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
27726 case BFD_RELOC_ARM_ALU_SB_G0
:
27727 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
27728 case BFD_RELOC_ARM_ALU_SB_G1
:
27729 case BFD_RELOC_ARM_ALU_SB_G2
:
27730 case BFD_RELOC_ARM_LDR_SB_G0
:
27731 case BFD_RELOC_ARM_LDR_SB_G1
:
27732 case BFD_RELOC_ARM_LDR_SB_G2
:
27733 case BFD_RELOC_ARM_LDRS_SB_G0
:
27734 case BFD_RELOC_ARM_LDRS_SB_G1
:
27735 case BFD_RELOC_ARM_LDRS_SB_G2
:
27736 case BFD_RELOC_ARM_LDC_SB_G0
:
27737 case BFD_RELOC_ARM_LDC_SB_G1
:
27738 case BFD_RELOC_ARM_LDC_SB_G2
:
27739 case BFD_RELOC_ARM_V4BX
:
27740 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
27741 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
27742 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
27743 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
27744 case BFD_RELOC_ARM_GOTFUNCDESC
:
27745 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
27746 case BFD_RELOC_ARM_FUNCDESC
:
27747 case BFD_RELOC_ARM_THUMB_BF17
:
27748 case BFD_RELOC_ARM_THUMB_BF19
:
27749 case BFD_RELOC_ARM_THUMB_BF13
:
27750 code
= fixp
->fx_r_type
;
27753 case BFD_RELOC_ARM_TLS_GOTDESC
:
27754 case BFD_RELOC_ARM_TLS_GD32
:
27755 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
27756 case BFD_RELOC_ARM_TLS_LE32
:
27757 case BFD_RELOC_ARM_TLS_IE32
:
27758 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
27759 case BFD_RELOC_ARM_TLS_LDM32
:
27760 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
27761 /* BFD will include the symbol's address in the addend.
27762 But we don't want that, so subtract it out again here. */
27763 if (!S_IS_COMMON (fixp
->fx_addsy
))
27764 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
27765 code
= fixp
->fx_r_type
;
27769 case BFD_RELOC_ARM_IMMEDIATE
:
27770 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27771 _("internal relocation (type: IMMEDIATE) not fixed up"));
27774 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
27775 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27776 _("ADRL used for a symbol not defined in the same file"));
27779 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
27780 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
27781 case BFD_RELOC_ARM_THUMB_LOOP12
:
27782 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27783 _("%s used for a symbol not defined in the same file"),
27784 bfd_get_reloc_code_name (fixp
->fx_r_type
));
27787 case BFD_RELOC_ARM_OFFSET_IMM
:
27788 if (section
->use_rela_p
)
27790 code
= fixp
->fx_r_type
;
27794 if (fixp
->fx_addsy
!= NULL
27795 && !S_IS_DEFINED (fixp
->fx_addsy
)
27796 && S_IS_LOCAL (fixp
->fx_addsy
))
27798 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27799 _("undefined local label `%s'"),
27800 S_GET_NAME (fixp
->fx_addsy
));
27804 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27805 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
27812 switch (fixp
->fx_r_type
)
27814 case BFD_RELOC_NONE
: type
= "NONE"; break;
27815 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
27816 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
27817 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
27818 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
27819 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
27820 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
27821 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
27822 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
27823 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
27824 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
27825 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
27826 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
27827 default: type
= _("<unknown>"); break;
27829 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27830 _("cannot represent %s relocation in this object file format"),
27837 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
27839 && fixp
->fx_addsy
== GOT_symbol
)
27841 code
= BFD_RELOC_ARM_GOTPC
;
27842 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
27846 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
27848 if (reloc
->howto
== NULL
)
27850 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
27851 _("cannot represent %s relocation in this object file format"),
27852 bfd_get_reloc_code_name (code
));
27856 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
27857 vtable entry to be used in the relocation's section offset. */
27858 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
27859 reloc
->address
= fixp
->fx_offset
;
27864 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
27867 cons_fix_new_arm (fragS
* frag
,
27871 bfd_reloc_code_real_type reloc
)
27876 FIXME: @@ Should look at CPU word size. */
27880 reloc
= BFD_RELOC_8
;
27883 reloc
= BFD_RELOC_16
;
27887 reloc
= BFD_RELOC_32
;
27890 reloc
= BFD_RELOC_64
;
27895 if (exp
->X_op
== O_secrel
)
27897 exp
->X_op
= O_symbol
;
27898 reloc
= BFD_RELOC_32_SECREL
;
27902 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
27905 #if defined (OBJ_COFF)
27907 arm_validate_fix (fixS
* fixP
)
27909 /* If the destination of the branch is a defined symbol which does not have
27910 the THUMB_FUNC attribute, then we must be calling a function which has
27911 the (interfacearm) attribute. We look for the Thumb entry point to that
27912 function and change the branch to refer to that function instead. */
27913 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
27914 && fixP
->fx_addsy
!= NULL
27915 && S_IS_DEFINED (fixP
->fx_addsy
)
27916 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
27918 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
27925 arm_force_relocation (struct fix
* fixp
)
27927 #if defined (OBJ_COFF) && defined (TE_PE)
27928 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
27932 /* In case we have a call or a branch to a function in ARM ISA mode from
27933 a thumb function or vice-versa force the relocation. These relocations
27934 are cleared off for some cores that might have blx and simple transformations
27938 switch (fixp
->fx_r_type
)
27940 case BFD_RELOC_ARM_PCREL_JUMP
:
27941 case BFD_RELOC_ARM_PCREL_CALL
:
27942 case BFD_RELOC_THUMB_PCREL_BLX
:
27943 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
27947 case BFD_RELOC_ARM_PCREL_BLX
:
27948 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27949 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27950 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27951 if (ARM_IS_FUNC (fixp
->fx_addsy
))
27960 /* Resolve these relocations even if the symbol is extern or weak.
27961 Technically this is probably wrong due to symbol preemption.
27962 In practice these relocations do not have enough range to be useful
27963 at dynamic link time, and some code (e.g. in the Linux kernel)
27964 expects these references to be resolved. */
27965 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
27966 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
27967 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
27968 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
27969 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
27970 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
27971 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
27972 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
27973 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
27974 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
27975 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
27976 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
27977 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
27978 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
27981 /* Always leave these relocations for the linker. */
27982 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
27983 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
27984 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
27987 /* Always generate relocations against function symbols. */
27988 if (fixp
->fx_r_type
== BFD_RELOC_32
27990 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
27993 return generic_force_reloc (fixp
);
27996 #if defined (OBJ_ELF) || defined (OBJ_COFF)
27997 /* Relocations against function names must be left unadjusted,
27998 so that the linker can use this information to generate interworking
27999 stubs. The MIPS version of this function
28000 also prevents relocations that are mips-16 specific, but I do not
28001 know why it does this.
28004 There is one other problem that ought to be addressed here, but
28005 which currently is not: Taking the address of a label (rather
28006 than a function) and then later jumping to that address. Such
28007 addresses also ought to have their bottom bit set (assuming that
28008 they reside in Thumb code), but at the moment they will not. */
28011 arm_fix_adjustable (fixS
* fixP
)
28013 if (fixP
->fx_addsy
== NULL
)
28016 /* Preserve relocations against symbols with function type. */
28017 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
28020 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
28021 && fixP
->fx_subsy
== NULL
)
28024 /* We need the symbol name for the VTABLE entries. */
28025 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
28026 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
28029 /* Don't allow symbols to be discarded on GOT related relocs. */
28030 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
28031 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
28032 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
28033 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
28034 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
28035 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
28036 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
28037 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
28038 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
28039 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
28040 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
28041 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
28042 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
28043 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
28044 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
28045 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
28046 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
28049 /* Similarly for group relocations. */
28050 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
28051 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
28052 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
28055 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
28056 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
28057 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
28058 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
28059 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
28060 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
28061 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
28062 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
28063 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
28066 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
28067 offsets, so keep these symbols. */
28068 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
28069 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
28074 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
28078 elf32_arm_target_format (void)
28081 return (target_big_endian
28082 ? "elf32-bigarm-symbian"
28083 : "elf32-littlearm-symbian");
28084 #elif defined (TE_VXWORKS)
28085 return (target_big_endian
28086 ? "elf32-bigarm-vxworks"
28087 : "elf32-littlearm-vxworks");
28088 #elif defined (TE_NACL)
28089 return (target_big_endian
28090 ? "elf32-bigarm-nacl"
28091 : "elf32-littlearm-nacl");
28095 if (target_big_endian
)
28096 return "elf32-bigarm-fdpic";
28098 return "elf32-littlearm-fdpic";
28102 if (target_big_endian
)
28103 return "elf32-bigarm";
28105 return "elf32-littlearm";
28111 armelf_frob_symbol (symbolS
* symp
,
28114 elf_frob_symbol (symp
, puntp
);
28118 /* MD interface: Finalization. */
28123 literal_pool
* pool
;
28125 /* Ensure that all the predication blocks are properly closed. */
28126 check_pred_blocks_finished ();
28128 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
28130 /* Put it at the end of the relevant section. */
28131 subseg_set (pool
->section
, pool
->sub_section
);
28133 arm_elf_change_section ();
28140 /* Remove any excess mapping symbols generated for alignment frags in
28141 SEC. We may have created a mapping symbol before a zero byte
28142 alignment; remove it if there's a mapping symbol after the
28145 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
28146 void *dummy ATTRIBUTE_UNUSED
)
28148 segment_info_type
*seginfo
= seg_info (sec
);
28151 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
28154 for (fragp
= seginfo
->frchainP
->frch_root
;
28156 fragp
= fragp
->fr_next
)
28158 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
28159 fragS
*next
= fragp
->fr_next
;
28161 /* Variable-sized frags have been converted to fixed size by
28162 this point. But if this was variable-sized to start with,
28163 there will be a fixed-size frag after it. So don't handle
28165 if (sym
== NULL
|| next
== NULL
)
28168 if (S_GET_VALUE (sym
) < next
->fr_address
)
28169 /* Not at the end of this frag. */
28171 know (S_GET_VALUE (sym
) == next
->fr_address
);
28175 if (next
->tc_frag_data
.first_map
!= NULL
)
28177 /* Next frag starts with a mapping symbol. Discard this
28179 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
28183 if (next
->fr_next
== NULL
)
28185 /* This mapping symbol is at the end of the section. Discard
28187 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
28188 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
28192 /* As long as we have empty frags without any mapping symbols,
28194 /* If the next frag is non-empty and does not start with a
28195 mapping symbol, then this mapping symbol is required. */
28196 if (next
->fr_address
!= next
->fr_next
->fr_address
)
28199 next
= next
->fr_next
;
28201 while (next
!= NULL
);
28206 /* Adjust the symbol table. This marks Thumb symbols as distinct from
28210 arm_adjust_symtab (void)
28215 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
28217 if (ARM_IS_THUMB (sym
))
28219 if (THUMB_IS_FUNC (sym
))
28221 /* Mark the symbol as a Thumb function. */
28222 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
28223 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
28224 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
28226 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
28227 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
28229 as_bad (_("%s: unexpected function type: %d"),
28230 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
28232 else switch (S_GET_STORAGE_CLASS (sym
))
28235 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
28238 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
28241 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
28249 if (ARM_IS_INTERWORK (sym
))
28250 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
28257 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
28259 if (ARM_IS_THUMB (sym
))
28261 elf_symbol_type
* elf_sym
;
28263 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
28264 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
28266 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
28267 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
28269 /* If it's a .thumb_func, declare it as so,
28270 otherwise tag label as .code 16. */
28271 if (THUMB_IS_FUNC (sym
))
28272 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
28273 ST_BRANCH_TO_THUMB
);
28274 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
28275 elf_sym
->internal_elf_sym
.st_info
=
28276 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
28281 /* Remove any overlapping mapping symbols generated by alignment frags. */
28282 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
28283 /* Now do generic ELF adjustments. */
28284 elf_adjust_symtab ();
28288 /* MD interface: Initialization. */
28291 set_constant_flonums (void)
28295 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
28296 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
28300 /* Auto-select Thumb mode if it's the only available instruction set for the
28301 given architecture. */
28304 autoselect_thumb_from_cpu_variant (void)
28306 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
28307 opcode_select (16);
28316 if ( (arm_ops_hsh
= hash_new ()) == NULL
28317 || (arm_cond_hsh
= hash_new ()) == NULL
28318 || (arm_vcond_hsh
= hash_new ()) == NULL
28319 || (arm_shift_hsh
= hash_new ()) == NULL
28320 || (arm_psr_hsh
= hash_new ()) == NULL
28321 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
28322 || (arm_reg_hsh
= hash_new ()) == NULL
28323 || (arm_reloc_hsh
= hash_new ()) == NULL
28324 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
28325 as_fatal (_("virtual memory exhausted"));
28327 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
28328 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
28329 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
28330 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
28331 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
28332 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
28333 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
28334 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
28335 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
28336 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
28337 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
28338 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
28339 (void *) (v7m_psrs
+ i
));
28340 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
28341 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
28343 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
28345 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
28346 (void *) (barrier_opt_names
+ i
));
28348 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
28350 struct reloc_entry
* entry
= reloc_names
+ i
;
28352 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
28353 /* This makes encode_branch() use the EABI versions of this relocation. */
28354 entry
->reloc
= BFD_RELOC_UNUSED
;
28356 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
28360 set_constant_flonums ();
28362 /* Set the cpu variant based on the command-line options. We prefer
28363 -mcpu= over -march= if both are set (as for GCC); and we prefer
28364 -mfpu= over any other way of setting the floating point unit.
28365 Use of legacy options with new options are faulted. */
28368 if (mcpu_cpu_opt
|| march_cpu_opt
)
28369 as_bad (_("use of old and new-style options to set CPU type"));
28371 selected_arch
= *legacy_cpu
;
28373 else if (mcpu_cpu_opt
)
28375 selected_arch
= *mcpu_cpu_opt
;
28376 selected_ext
= *mcpu_ext_opt
;
28378 else if (march_cpu_opt
)
28380 selected_arch
= *march_cpu_opt
;
28381 selected_ext
= *march_ext_opt
;
28383 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
28388 as_bad (_("use of old and new-style options to set FPU type"));
28390 selected_fpu
= *legacy_fpu
;
28393 selected_fpu
= *mfpu_opt
;
28396 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
28397 || defined (TE_NetBSD) || defined (TE_VXWORKS))
28398 /* Some environments specify a default FPU. If they don't, infer it
28399 from the processor. */
28401 selected_fpu
= *mcpu_fpu_opt
;
28402 else if (march_fpu_opt
)
28403 selected_fpu
= *march_fpu_opt
;
28405 selected_fpu
= fpu_default
;
28409 if (ARM_FEATURE_ZERO (selected_fpu
))
28411 if (!no_cpu_selected ())
28412 selected_fpu
= fpu_default
;
28414 selected_fpu
= fpu_arch_fpa
;
28418 if (ARM_FEATURE_ZERO (selected_arch
))
28420 selected_arch
= cpu_default
;
28421 selected_cpu
= selected_arch
;
28423 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28425 /* Autodection of feature mode: allow all features in cpu_variant but leave
28426 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
28427 after all instruction have been processed and we can decide what CPU
28428 should be selected. */
28429 if (ARM_FEATURE_ZERO (selected_arch
))
28430 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
28432 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
28435 autoselect_thumb_from_cpu_variant ();
28437 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
28439 #if defined OBJ_COFF || defined OBJ_ELF
28441 unsigned int flags
= 0;
28443 #if defined OBJ_ELF
28444 flags
= meabi_flags
;
28446 switch (meabi_flags
)
28448 case EF_ARM_EABI_UNKNOWN
:
28450 /* Set the flags in the private structure. */
28451 if (uses_apcs_26
) flags
|= F_APCS26
;
28452 if (support_interwork
) flags
|= F_INTERWORK
;
28453 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
28454 if (pic_code
) flags
|= F_PIC
;
28455 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
28456 flags
|= F_SOFT_FLOAT
;
28458 switch (mfloat_abi_opt
)
28460 case ARM_FLOAT_ABI_SOFT
:
28461 case ARM_FLOAT_ABI_SOFTFP
:
28462 flags
|= F_SOFT_FLOAT
;
28465 case ARM_FLOAT_ABI_HARD
:
28466 if (flags
& F_SOFT_FLOAT
)
28467 as_bad (_("hard-float conflicts with specified fpu"));
28471 /* Using pure-endian doubles (even if soft-float). */
28472 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
28473 flags
|= F_VFP_FLOAT
;
28475 #if defined OBJ_ELF
28476 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
28477 flags
|= EF_ARM_MAVERICK_FLOAT
;
28480 case EF_ARM_EABI_VER4
:
28481 case EF_ARM_EABI_VER5
:
28482 /* No additional flags to set. */
28489 bfd_set_private_flags (stdoutput
, flags
);
28491 /* We have run out flags in the COFF header to encode the
28492 status of ATPCS support, so instead we create a dummy,
28493 empty, debug section called .arm.atpcs. */
28498 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
28502 bfd_set_section_flags
28503 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
28504 bfd_set_section_size (stdoutput
, sec
, 0);
28505 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
28511 /* Record the CPU type as well. */
28512 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
28513 mach
= bfd_mach_arm_iWMMXt2
;
28514 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
28515 mach
= bfd_mach_arm_iWMMXt
;
28516 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
28517 mach
= bfd_mach_arm_XScale
;
28518 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
28519 mach
= bfd_mach_arm_ep9312
;
28520 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
28521 mach
= bfd_mach_arm_5TE
;
28522 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
28524 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
28525 mach
= bfd_mach_arm_5T
;
28527 mach
= bfd_mach_arm_5
;
28529 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
28531 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
28532 mach
= bfd_mach_arm_4T
;
28534 mach
= bfd_mach_arm_4
;
28536 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
28537 mach
= bfd_mach_arm_3M
;
28538 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
28539 mach
= bfd_mach_arm_3
;
28540 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
28541 mach
= bfd_mach_arm_2a
;
28542 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
28543 mach
= bfd_mach_arm_2
;
28545 mach
= bfd_mach_arm_unknown
;
28547 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
28550 /* Command line processing. */
28553 Invocation line includes a switch not recognized by the base assembler.
28554 See if it's a processor-specific option.
28556 This routine is somewhat complicated by the need for backwards
28557 compatibility (since older releases of gcc can't be changed).
28558 The new options try to make the interface as compatible as
28561 New options (supported) are:
28563 -mcpu=<cpu name> Assemble for selected processor
28564 -march=<architecture name> Assemble for selected architecture
28565 -mfpu=<fpu architecture> Assemble for selected FPU.
28566 -EB/-mbig-endian Big-endian
28567 -EL/-mlittle-endian Little-endian
28568 -k Generate PIC code
28569 -mthumb Start in Thumb mode
28570 -mthumb-interwork Code supports ARM/Thumb interworking
28572 -m[no-]warn-deprecated Warn about deprecated features
28573 -m[no-]warn-syms Warn when symbols match instructions
28575 For now we will also provide support for:
28577 -mapcs-32 32-bit Program counter
28578 -mapcs-26 26-bit Program counter
28579 -macps-float Floats passed in FP registers
28580 -mapcs-reentrant Reentrant code
28582 (sometime these will probably be replaced with -mapcs=<list of options>
28583 and -matpcs=<list of options>)
28585 The remaining options are only supported for back-wards compatibility.
28586 Cpu variants, the arm part is optional:
28587 -m[arm]1 Currently not supported.
28588 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
28589 -m[arm]3 Arm 3 processor
28590 -m[arm]6[xx], Arm 6 processors
28591 -m[arm]7[xx][t][[d]m] Arm 7 processors
28592 -m[arm]8[10] Arm 8 processors
28593 -m[arm]9[20][tdmi] Arm 9 processors
28594 -mstrongarm[110[0]] StrongARM processors
28595 -mxscale XScale processors
28596 -m[arm]v[2345[t[e]]] Arm architectures
28597 -mall All (except the ARM1)
28599 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
28600 -mfpe-old (No float load/store multiples)
28601 -mvfpxd VFP Single precision
28603 -mno-fpu Disable all floating point instructions
28605 The following CPU names are recognized:
28606 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
28607 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
28608 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
28609 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
28610 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
28611 arm10t arm10e, arm1020t, arm1020e, arm10200e,
28612 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
28616 const char * md_shortopts
= "m:k";
28618 #ifdef ARM_BI_ENDIAN
28619 #define OPTION_EB (OPTION_MD_BASE + 0)
28620 #define OPTION_EL (OPTION_MD_BASE + 1)
28622 #if TARGET_BYTES_BIG_ENDIAN
28623 #define OPTION_EB (OPTION_MD_BASE + 0)
28625 #define OPTION_EL (OPTION_MD_BASE + 1)
28628 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
28629 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
28631 struct option md_longopts
[] =
28634 {"EB", no_argument
, NULL
, OPTION_EB
},
28637 {"EL", no_argument
, NULL
, OPTION_EL
},
28639 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
28641 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
28643 {NULL
, no_argument
, NULL
, 0}
28646 size_t md_longopts_size
= sizeof (md_longopts
);
28648 struct arm_option_table
28650 const char * option
; /* Option name to match. */
28651 const char * help
; /* Help information. */
28652 int * var
; /* Variable to change. */
28653 int value
; /* What to change it to. */
28654 const char * deprecated
; /* If non-null, print this message. */
28657 struct arm_option_table arm_opts
[] =
28659 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
28660 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
28661 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
28662 &support_interwork
, 1, NULL
},
28663 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
28664 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
28665 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
28667 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
28668 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
28669 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
28670 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
28673 /* These are recognized by the assembler, but have no affect on code. */
28674 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
28675 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
28677 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
28678 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
28679 &warn_on_deprecated
, 0, NULL
},
28680 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
28681 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
28682 {NULL
, NULL
, NULL
, 0, NULL
}
28685 struct arm_legacy_option_table
28687 const char * option
; /* Option name to match. */
28688 const arm_feature_set
** var
; /* Variable to change. */
28689 const arm_feature_set value
; /* What to change it to. */
28690 const char * deprecated
; /* If non-null, print this message. */
28693 const struct arm_legacy_option_table arm_legacy_opts
[] =
28695 /* DON'T add any new processors to this list -- we want the whole list
28696 to go away... Add them to the processors table instead. */
28697 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
28698 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
28699 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
28700 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
28701 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
28702 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
28703 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
28704 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
28705 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
28706 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
28707 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
28708 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
28709 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
28710 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
28711 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
28712 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
28713 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
28714 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
28715 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
28716 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
28717 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
28718 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
28719 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
28720 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
28721 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
28722 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
28723 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
28724 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
28725 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
28726 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
28727 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
28728 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
28729 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
28730 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
28731 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
28732 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
28733 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
28734 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
28735 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
28736 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
28737 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
28738 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
28739 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
28740 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
28741 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
28742 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
28743 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
28744 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
28745 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
28746 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
28747 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
28748 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
28749 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
28750 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
28751 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
28752 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
28753 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
28754 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
28755 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
28756 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
28757 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
28758 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
28759 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
28760 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
28761 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
28762 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
28763 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
28764 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
28765 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
28766 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
28767 N_("use -mcpu=strongarm110")},
28768 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
28769 N_("use -mcpu=strongarm1100")},
28770 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
28771 N_("use -mcpu=strongarm1110")},
28772 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
28773 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
28774 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
28776 /* Architecture variants -- don't add any more to this list either. */
28777 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
28778 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
28779 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
28780 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
28781 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
28782 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
28783 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
28784 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
28785 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
28786 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
28787 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
28788 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
28789 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
28790 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
28791 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
28792 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
28793 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
28794 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
28796 /* Floating point variants -- don't add any more to this list either. */
28797 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
28798 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
28799 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
28800 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
28801 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
28803 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
28806 struct arm_cpu_option_table
28810 const arm_feature_set value
;
28811 const arm_feature_set ext
;
28812 /* For some CPUs we assume an FPU unless the user explicitly sets
28814 const arm_feature_set default_fpu
;
28815 /* The canonical name of the CPU, or NULL to use NAME converted to upper
28817 const char * canonical_name
;
28820 /* This list should, at a minimum, contain all the cpu names
28821 recognized by GCC. */
28822 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
28824 static const struct arm_cpu_option_table arm_cpus
[] =
28826 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
28829 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
28832 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
28835 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
28838 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
28841 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
28844 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
28847 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
28850 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
28853 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
28856 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
28859 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
28862 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
28865 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
28868 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
28871 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
28874 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
28877 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
28880 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
28883 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
28886 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
28889 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
28892 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
28895 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
28898 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
28901 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
28904 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
28907 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
28910 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
28913 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
28916 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
28919 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
28922 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
28925 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
28928 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
28931 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
28934 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
28937 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
28940 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
28943 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
28946 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
28949 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
28952 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
28955 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
28958 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
28961 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
28965 /* For V5 or later processors we default to using VFP; but the user
28966 should really set the FPU type explicitly. */
28967 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
28970 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
28973 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
28976 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
28979 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
28982 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
28985 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
28988 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
28991 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
28994 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
28997 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
29000 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
29003 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
29006 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
29009 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
29012 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
29015 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
29018 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
29021 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
29024 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
29027 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
29030 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
29033 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
29036 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
29039 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
29042 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
29045 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
29048 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
29051 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
29054 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
29057 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
29060 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
29063 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
29066 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
29069 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
29072 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
29075 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
29076 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
29078 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
29080 FPU_ARCH_NEON_VFP_V4
),
29081 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
29082 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
29083 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
29084 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
29085 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
29086 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
29087 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
29089 FPU_ARCH_NEON_VFP_V4
),
29090 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
29092 FPU_ARCH_NEON_VFP_V4
),
29093 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
29095 FPU_ARCH_NEON_VFP_V4
),
29096 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
29097 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29098 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29099 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
29100 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29101 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29102 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
29103 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29104 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29105 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
29106 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29107 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
29108 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
29109 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29110 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29111 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
29112 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29113 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29114 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
29115 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29116 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29117 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
29118 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29119 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
29120 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
29121 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29122 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
29123 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
29124 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29125 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
29126 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
29129 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
29131 FPU_ARCH_VFP_V3D16
),
29132 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
29133 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
29135 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
29136 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
29137 FPU_ARCH_VFP_V3D16
),
29138 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
29139 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
29140 FPU_ARCH_VFP_V3D16
),
29141 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
29142 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29143 FPU_ARCH_NEON_VFP_ARMV8
),
29144 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
29145 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29147 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
29150 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
29153 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
29156 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
29159 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
29162 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
29165 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
29168 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
29169 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29170 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29171 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
29172 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29173 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
29174 /* ??? XSCALE is really an architecture. */
29175 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
29179 /* ??? iwmmxt is not a processor. */
29180 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
29183 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
29186 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
29191 ARM_CPU_OPT ("ep9312", "ARM920T",
29192 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
29193 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
29195 /* Marvell processors. */
29196 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
29197 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
29198 FPU_ARCH_VFP_V3D16
),
29199 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
29200 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
29201 FPU_ARCH_NEON_VFP_V4
),
29203 /* APM X-Gene family. */
29204 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
29206 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29207 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
29208 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29209 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
29211 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
29215 struct arm_ext_table
29219 const arm_feature_set merge
;
29220 const arm_feature_set clear
;
29223 struct arm_arch_option_table
29227 const arm_feature_set value
;
29228 const arm_feature_set default_fpu
;
29229 const struct arm_ext_table
* ext_table
;
29232 /* Used to add support for +E and +noE extension. */
29233 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
29234 /* Used to add support for a +E extension. */
29235 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
29236 /* Used to add support for a +noE extension. */
29237 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
29239 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
29240 ~0 & ~FPU_ENDIAN_PURE)
29242 static const struct arm_ext_table armv5te_ext_table
[] =
29244 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
29245 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29248 static const struct arm_ext_table armv7_ext_table
[] =
29250 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
29251 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29254 static const struct arm_ext_table armv7ve_ext_table
[] =
29256 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
29257 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
29258 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
29259 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
29260 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
29261 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
29262 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
29264 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
29265 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
29267 /* Aliases for +simd. */
29268 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
29270 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
29271 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
29272 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
29274 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29277 static const struct arm_ext_table armv7a_ext_table
[] =
29279 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
29280 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
29281 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
29282 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
29283 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
29284 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
29285 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
29287 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
29288 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
29290 /* Aliases for +simd. */
29291 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
29292 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
29294 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
29295 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
29297 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
29298 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
29299 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29302 static const struct arm_ext_table armv7r_ext_table
[] =
29304 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
29305 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
29306 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
29307 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
29308 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
29309 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
29310 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
29311 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
29312 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29315 static const struct arm_ext_table armv7em_ext_table
[] =
29317 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
29318 /* Alias for +fp, used to be known as fpv4-sp-d16. */
29319 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
29320 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
29321 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
29322 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
29323 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29326 static const struct arm_ext_table armv8a_ext_table
[] =
29328 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
29329 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
29330 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
29331 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29333 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29334 should use the +simd option to turn on FP. */
29335 ARM_REMOVE ("fp", ALL_FP
),
29336 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
29337 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
29338 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29342 static const struct arm_ext_table armv81a_ext_table
[] =
29344 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
29345 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
29346 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29348 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29349 should use the +simd option to turn on FP. */
29350 ARM_REMOVE ("fp", ALL_FP
),
29351 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
29352 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
29353 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29356 static const struct arm_ext_table armv82a_ext_table
[] =
29358 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
29359 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
29360 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
29361 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
29362 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29363 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
29365 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29366 should use the +simd option to turn on FP. */
29367 ARM_REMOVE ("fp", ALL_FP
),
29368 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
29369 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
29370 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29373 static const struct arm_ext_table armv84a_ext_table
[] =
29375 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
29376 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
29377 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
29378 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29380 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29381 should use the +simd option to turn on FP. */
29382 ARM_REMOVE ("fp", ALL_FP
),
29383 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
29384 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
29385 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29388 static const struct arm_ext_table armv85a_ext_table
[] =
29390 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
29391 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
29392 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
29393 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29395 /* Armv8-a does not allow an FP implementation without SIMD, so the user
29396 should use the +simd option to turn on FP. */
29397 ARM_REMOVE ("fp", ALL_FP
),
29398 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29401 static const struct arm_ext_table armv8m_main_ext_table
[] =
29403 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29404 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
29405 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
29406 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
29407 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29410 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
29412 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29413 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
29415 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
29416 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
29419 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
29420 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
29421 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE
),
29422 ARM_FEATURE_COPROC (FPU_MVE
| FPU_MVE_FP
)),
29424 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
29425 FPU_MVE
| FPU_MVE_FP
| FPU_VFP_V5_SP_D16
|
29426 FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
29427 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29430 static const struct arm_ext_table armv8r_ext_table
[] =
29432 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
29433 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
29434 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
29435 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
29436 ARM_REMOVE ("fp", ALL_FP
),
29437 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
29438 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
29441 /* This list should, at a minimum, contain all the architecture names
29442 recognized by GCC. */
29443 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
29444 #define ARM_ARCH_OPT2(N, V, DF, ext) \
29445 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
29447 static const struct arm_arch_option_table arm_archs
[] =
29449 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
29450 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
29451 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
29452 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
29453 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
29454 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
29455 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
29456 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
29457 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
29458 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
29459 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
29460 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
29461 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
29462 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
29463 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
29464 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
29465 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
29466 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
29467 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
29468 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
29469 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
29470 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
29471 kept to preserve existing behaviour. */
29472 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
29473 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
29474 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
29475 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
29476 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
29477 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
29478 kept to preserve existing behaviour. */
29479 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
29480 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
29481 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
29482 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
29483 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
29484 /* The official spelling of the ARMv7 profile variants is the dashed form.
29485 Accept the non-dashed form for compatibility with old toolchains. */
29486 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
29487 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
29488 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
29489 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
29490 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
29491 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
29492 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
29493 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
29494 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
29495 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
29497 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
29499 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
29500 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
29501 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
29502 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
29503 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
29504 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
29505 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
29506 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
29507 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
29508 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
29509 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
29511 #undef ARM_ARCH_OPT
29513 /* ISA extensions in the co-processor and main instruction set space. */
29515 struct arm_option_extension_value_table
29519 const arm_feature_set merge_value
;
29520 const arm_feature_set clear_value
;
29521 /* List of architectures for which an extension is available. ARM_ARCH_NONE
29522 indicates that an extension is available for all architectures while
29523 ARM_ANY marks an empty entry. */
29524 const arm_feature_set allowed_archs
[2];
29527 /* The following table must be in alphabetical order with a NULL last entry. */
29529 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
29530 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
29532 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
29533 use the context sensitive approach using arm_ext_table's. */
29534 static const struct arm_option_extension_value_table arm_extensions
[] =
29536 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
29537 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
29538 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
29539 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
29540 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
29541 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
29542 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
29544 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29545 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
29546 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
29547 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
29548 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
29549 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29550 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
29552 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
29553 | ARM_EXT2_FP16_FML
),
29554 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
29555 | ARM_EXT2_FP16_FML
),
29557 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
29558 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
29559 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
29560 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
29561 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
29562 Thumb divide instruction. Due to this having the same name as the
29563 previous entry, this will be ignored when doing command-line parsing and
29564 only considered by build attribute selection code. */
29565 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
29566 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
29567 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
29568 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
29569 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
29570 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
29571 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
29572 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
29573 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
29574 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
29575 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
29576 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
29577 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
29578 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
29579 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
29580 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
29581 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
29582 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
29583 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
29584 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
29585 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
29587 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
29588 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
29589 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
29590 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
29591 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
29592 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
29593 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
29594 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
29596 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
29597 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
29598 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
29599 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
29600 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
29601 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
29602 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
29603 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
29605 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
29606 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
29607 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
29608 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
29609 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
29613 /* ISA floating-point and Advanced SIMD extensions. */
29614 struct arm_option_fpu_value_table
29617 const arm_feature_set value
;
29620 /* This list should, at a minimum, contain all the fpu names
29621 recognized by GCC. */
29622 static const struct arm_option_fpu_value_table arm_fpus
[] =
29624 {"softfpa", FPU_NONE
},
29625 {"fpe", FPU_ARCH_FPE
},
29626 {"fpe2", FPU_ARCH_FPE
},
29627 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
29628 {"fpa", FPU_ARCH_FPA
},
29629 {"fpa10", FPU_ARCH_FPA
},
29630 {"fpa11", FPU_ARCH_FPA
},
29631 {"arm7500fe", FPU_ARCH_FPA
},
29632 {"softvfp", FPU_ARCH_VFP
},
29633 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
29634 {"vfp", FPU_ARCH_VFP_V2
},
29635 {"vfp9", FPU_ARCH_VFP_V2
},
29636 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
29637 {"vfp10", FPU_ARCH_VFP_V2
},
29638 {"vfp10-r0", FPU_ARCH_VFP_V1
},
29639 {"vfpxd", FPU_ARCH_VFP_V1xD
},
29640 {"vfpv2", FPU_ARCH_VFP_V2
},
29641 {"vfpv3", FPU_ARCH_VFP_V3
},
29642 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
29643 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
29644 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
29645 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
29646 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
29647 {"arm1020t", FPU_ARCH_VFP_V1
},
29648 {"arm1020e", FPU_ARCH_VFP_V2
},
29649 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
29650 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
29651 {"maverick", FPU_ARCH_MAVERICK
},
29652 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
29653 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
29654 {"neon-fp16", FPU_ARCH_NEON_FP16
},
29655 {"vfpv4", FPU_ARCH_VFP_V4
},
29656 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
29657 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
29658 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
29659 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
29660 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
29661 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
29662 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
29663 {"crypto-neon-fp-armv8",
29664 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
29665 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
29666 {"crypto-neon-fp-armv8.1",
29667 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
29668 {NULL
, ARM_ARCH_NONE
}
29671 struct arm_option_value_table
29677 static const struct arm_option_value_table arm_float_abis
[] =
29679 {"hard", ARM_FLOAT_ABI_HARD
},
29680 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
29681 {"soft", ARM_FLOAT_ABI_SOFT
},
29686 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
29687 static const struct arm_option_value_table arm_eabis
[] =
29689 {"gnu", EF_ARM_EABI_UNKNOWN
},
29690 {"4", EF_ARM_EABI_VER4
},
29691 {"5", EF_ARM_EABI_VER5
},
29696 struct arm_long_option_table
29698 const char * option
; /* Substring to match. */
29699 const char * help
; /* Help information. */
29700 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
29701 const char * deprecated
; /* If non-null, print this message. */
29705 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
29706 arm_feature_set
*ext_set
,
29707 const struct arm_ext_table
*ext_table
)
29709 /* We insist on extensions being specified in alphabetical order, and with
29710 extensions being added before being removed. We achieve this by having
29711 the global ARM_EXTENSIONS table in alphabetical order, and using the
29712 ADDING_VALUE variable to indicate whether we are adding an extension (1)
29713 or removing it (0) and only allowing it to change in the order
29715 const struct arm_option_extension_value_table
* opt
= NULL
;
29716 const arm_feature_set arm_any
= ARM_ANY
;
29717 int adding_value
= -1;
29719 while (str
!= NULL
&& *str
!= 0)
29726 as_bad (_("invalid architectural extension"));
29731 ext
= strchr (str
, '+');
29736 len
= strlen (str
);
29738 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
29740 if (adding_value
!= 0)
29743 opt
= arm_extensions
;
29751 if (adding_value
== -1)
29754 opt
= arm_extensions
;
29756 else if (adding_value
!= 1)
29758 as_bad (_("must specify extensions to add before specifying "
29759 "those to remove"));
29766 as_bad (_("missing architectural extension"));
29770 gas_assert (adding_value
!= -1);
29771 gas_assert (opt
!= NULL
);
29773 if (ext_table
!= NULL
)
29775 const struct arm_ext_table
* ext_opt
= ext_table
;
29776 bfd_boolean found
= FALSE
;
29777 for (; ext_opt
->name
!= NULL
; ext_opt
++)
29778 if (ext_opt
->name_len
== len
29779 && strncmp (ext_opt
->name
, str
, len
) == 0)
29783 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
29784 /* TODO: Option not supported. When we remove the
29785 legacy table this case should error out. */
29788 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
29792 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
29793 /* TODO: Option not supported. When we remove the
29794 legacy table this case should error out. */
29796 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
29808 /* Scan over the options table trying to find an exact match. */
29809 for (; opt
->name
!= NULL
; opt
++)
29810 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
29812 int i
, nb_allowed_archs
=
29813 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
29814 /* Check we can apply the extension to this architecture. */
29815 for (i
= 0; i
< nb_allowed_archs
; i
++)
29818 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
29820 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
29823 if (i
== nb_allowed_archs
)
29825 as_bad (_("extension does not apply to the base architecture"));
29829 /* Add or remove the extension. */
29831 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
29833 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
29835 /* Allowing Thumb division instructions for ARMv7 in autodetection
29836 rely on this break so that duplicate extensions (extensions
29837 with the same name as a previous extension in the list) are not
29838 considered for command-line parsing. */
29842 if (opt
->name
== NULL
)
29844 /* Did we fail to find an extension because it wasn't specified in
29845 alphabetical order, or because it does not exist? */
29847 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
29848 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
29851 if (opt
->name
== NULL
)
29852 as_bad (_("unknown architectural extension `%s'"), str
);
29854 as_bad (_("architectural extensions must be specified in "
29855 "alphabetical order"));
29861 /* We should skip the extension we've just matched the next time
29873 arm_parse_cpu (const char *str
)
29875 const struct arm_cpu_option_table
*opt
;
29876 const char *ext
= strchr (str
, '+');
29882 len
= strlen (str
);
29886 as_bad (_("missing cpu name `%s'"), str
);
29890 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
29891 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
29893 mcpu_cpu_opt
= &opt
->value
;
29894 if (mcpu_ext_opt
== NULL
)
29895 mcpu_ext_opt
= XNEW (arm_feature_set
);
29896 *mcpu_ext_opt
= opt
->ext
;
29897 mcpu_fpu_opt
= &opt
->default_fpu
;
29898 if (opt
->canonical_name
)
29900 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
29901 strcpy (selected_cpu_name
, opt
->canonical_name
);
29907 if (len
>= sizeof selected_cpu_name
)
29908 len
= (sizeof selected_cpu_name
) - 1;
29910 for (i
= 0; i
< len
; i
++)
29911 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
29912 selected_cpu_name
[i
] = 0;
29916 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
29921 as_bad (_("unknown cpu `%s'"), str
);
29926 arm_parse_arch (const char *str
)
29928 const struct arm_arch_option_table
*opt
;
29929 const char *ext
= strchr (str
, '+');
29935 len
= strlen (str
);
29939 as_bad (_("missing architecture name `%s'"), str
);
29943 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
29944 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
29946 march_cpu_opt
= &opt
->value
;
29947 if (march_ext_opt
== NULL
)
29948 march_ext_opt
= XNEW (arm_feature_set
);
29949 *march_ext_opt
= arm_arch_none
;
29950 march_fpu_opt
= &opt
->default_fpu
;
29951 strcpy (selected_cpu_name
, opt
->name
);
29954 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
29960 as_bad (_("unknown architecture `%s'\n"), str
);
29965 arm_parse_fpu (const char * str
)
29967 const struct arm_option_fpu_value_table
* opt
;
29969 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
29970 if (streq (opt
->name
, str
))
29972 mfpu_opt
= &opt
->value
;
29976 as_bad (_("unknown floating point format `%s'\n"), str
);
29981 arm_parse_float_abi (const char * str
)
29983 const struct arm_option_value_table
* opt
;
29985 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
29986 if (streq (opt
->name
, str
))
29988 mfloat_abi_opt
= opt
->value
;
29992 as_bad (_("unknown floating point abi `%s'\n"), str
);
29998 arm_parse_eabi (const char * str
)
30000 const struct arm_option_value_table
*opt
;
30002 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
30003 if (streq (opt
->name
, str
))
30005 meabi_flags
= opt
->value
;
30008 as_bad (_("unknown EABI `%s'\n"), str
);
30014 arm_parse_it_mode (const char * str
)
30016 bfd_boolean ret
= TRUE
;
30018 if (streq ("arm", str
))
30019 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
30020 else if (streq ("thumb", str
))
30021 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
30022 else if (streq ("always", str
))
30023 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
30024 else if (streq ("never", str
))
30025 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
30028 as_bad (_("unknown implicit IT mode `%s', should be "\
30029 "arm, thumb, always, or never."), str
);
30037 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
30039 codecomposer_syntax
= TRUE
;
30040 arm_comment_chars
[0] = ';';
30041 arm_line_separator_chars
[0] = 0;
30045 struct arm_long_option_table arm_long_opts
[] =
30047 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
30048 arm_parse_cpu
, NULL
},
30049 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
30050 arm_parse_arch
, NULL
},
30051 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
30052 arm_parse_fpu
, NULL
},
30053 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
30054 arm_parse_float_abi
, NULL
},
30056 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
30057 arm_parse_eabi
, NULL
},
30059 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
30060 arm_parse_it_mode
, NULL
},
30061 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
30062 arm_ccs_mode
, NULL
},
30063 {NULL
, NULL
, 0, NULL
}
30067 md_parse_option (int c
, const char * arg
)
30069 struct arm_option_table
*opt
;
30070 const struct arm_legacy_option_table
*fopt
;
30071 struct arm_long_option_table
*lopt
;
30077 target_big_endian
= 1;
30083 target_big_endian
= 0;
30087 case OPTION_FIX_V4BX
:
30095 #endif /* OBJ_ELF */
30098 /* Listing option. Just ignore these, we don't support additional
30103 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
30105 if (c
== opt
->option
[0]
30106 && ((arg
== NULL
&& opt
->option
[1] == 0)
30107 || streq (arg
, opt
->option
+ 1)))
30109 /* If the option is deprecated, tell the user. */
30110 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
30111 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
30112 arg
? arg
: "", _(opt
->deprecated
));
30114 if (opt
->var
!= NULL
)
30115 *opt
->var
= opt
->value
;
30121 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
30123 if (c
== fopt
->option
[0]
30124 && ((arg
== NULL
&& fopt
->option
[1] == 0)
30125 || streq (arg
, fopt
->option
+ 1)))
30127 /* If the option is deprecated, tell the user. */
30128 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
30129 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
30130 arg
? arg
: "", _(fopt
->deprecated
));
30132 if (fopt
->var
!= NULL
)
30133 *fopt
->var
= &fopt
->value
;
30139 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
30141 /* These options are expected to have an argument. */
30142 if (c
== lopt
->option
[0]
30144 && strncmp (arg
, lopt
->option
+ 1,
30145 strlen (lopt
->option
+ 1)) == 0)
30147 /* If the option is deprecated, tell the user. */
30148 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
30149 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
30150 _(lopt
->deprecated
));
30152 /* Call the sup-option parser. */
30153 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
30164 md_show_usage (FILE * fp
)
30166 struct arm_option_table
*opt
;
30167 struct arm_long_option_table
*lopt
;
30169 fprintf (fp
, _(" ARM-specific assembler options:\n"));
30171 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
30172 if (opt
->help
!= NULL
)
30173 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
30175 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
30176 if (lopt
->help
!= NULL
)
30177 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
30181 -EB assemble code for a big-endian cpu\n"));
30186 -EL assemble code for a little-endian cpu\n"));
30190 --fix-v4bx Allow BX in ARMv4 code\n"));
30194 --fdpic generate an FDPIC object file\n"));
30195 #endif /* OBJ_ELF */
30203 arm_feature_set flags
;
30204 } cpu_arch_ver_table
;
30206 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
30207 chronologically for architectures, with an exception for ARMv6-M and
30208 ARMv6S-M due to legacy reasons. No new architecture should have a
30209 special case. This allows for build attribute selection results to be
30210 stable when new architectures are added. */
30211 static const cpu_arch_ver_table cpu_arch_ver
[] =
30213 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
30214 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
30215 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
30216 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
30217 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
30218 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
30219 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
30220 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
30221 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
30222 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
30223 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
30224 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
30225 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
30226 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
30227 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
30228 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
30229 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
30230 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
30231 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
30232 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
30233 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
30234 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
30235 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
30236 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
30238 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
30239 always selected build attributes to match those of ARMv6-M
30240 (resp. ARMv6S-M). However, due to these architectures being a strict
30241 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
30242 would be selected when fully respecting chronology of architectures.
30243 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
30244 move them before ARMv7 architectures. */
30245 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
30246 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
30248 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
30249 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
30250 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
30251 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
30252 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
30253 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
30254 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
30255 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
30256 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
30257 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
30258 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
30259 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
30260 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
30261 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
30262 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
30263 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
30264 {-1, ARM_ARCH_NONE
}
30267 /* Set an attribute if it has not already been set by the user. */
30270 aeabi_set_attribute_int (int tag
, int value
)
30273 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
30274 || !attributes_set_explicitly
[tag
])
30275 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
30279 aeabi_set_attribute_string (int tag
, const char *value
)
30282 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
30283 || !attributes_set_explicitly
[tag
])
30284 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
30287 /* Return whether features in the *NEEDED feature set are available via
30288 extensions for the architecture whose feature set is *ARCH_FSET. */
30291 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
30292 const arm_feature_set
*needed
)
30294 int i
, nb_allowed_archs
;
30295 arm_feature_set ext_fset
;
30296 const struct arm_option_extension_value_table
*opt
;
30298 ext_fset
= arm_arch_none
;
30299 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
30301 /* Extension does not provide any feature we need. */
30302 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
30306 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
30307 for (i
= 0; i
< nb_allowed_archs
; i
++)
30310 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
30313 /* Extension is available, add it. */
30314 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
30315 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
30319 /* Can we enable all features in *needed? */
30320 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
30323 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
30324 a given architecture feature set *ARCH_EXT_FSET including extension feature
30325 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
30326 - if true, check for an exact match of the architecture modulo extensions;
30327 - otherwise, select build attribute value of the first superset
30328 architecture released so that results remains stable when new architectures
30330 For -march/-mcpu=all the build attribute value of the most featureful
30331 architecture is returned. Tag_CPU_arch_profile result is returned in
30335 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
30336 const arm_feature_set
*ext_fset
,
30337 char *profile
, int exact_match
)
30339 arm_feature_set arch_fset
;
30340 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
30342 /* Select most featureful architecture with all its extensions if building
30343 for -march=all as the feature sets used to set build attributes. */
30344 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
30346 /* Force revisiting of decision for each new architecture. */
30347 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
30349 return TAG_CPU_ARCH_V8
;
30352 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
30354 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
30356 arm_feature_set known_arch_fset
;
30358 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
30361 /* Base architecture match user-specified architecture and
30362 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
30363 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
30368 /* Base architecture match user-specified architecture only
30369 (eg. ARMv6-M in the same case as above). Record it in case we
30370 find a match with above condition. */
30371 else if (p_ver_ret
== NULL
30372 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
30378 /* Architecture has all features wanted. */
30379 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
30381 arm_feature_set added_fset
;
30383 /* Compute features added by this architecture over the one
30384 recorded in p_ver_ret. */
30385 if (p_ver_ret
!= NULL
)
30386 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
30388 /* First architecture that match incl. with extensions, or the
30389 only difference in features over the recorded match is
30390 features that were optional and are now mandatory. */
30391 if (p_ver_ret
== NULL
30392 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
30398 else if (p_ver_ret
== NULL
)
30400 arm_feature_set needed_ext_fset
;
30402 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
30404 /* Architecture has all features needed when using some
30405 extensions. Record it and continue searching in case there
30406 exist an architecture providing all needed features without
30407 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
30409 if (have_ext_for_needed_feat_p (&known_arch_fset
,
30416 if (p_ver_ret
== NULL
)
30420 /* Tag_CPU_arch_profile. */
30421 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
30422 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
30423 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
30424 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
30426 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
30428 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
30432 return p_ver_ret
->val
;
30435 /* Set the public EABI object attributes. */
30438 aeabi_set_public_attributes (void)
30440 char profile
= '\0';
30443 int fp16_optional
= 0;
30444 int skip_exact_match
= 0;
30445 arm_feature_set flags
, flags_arch
, flags_ext
;
30447 /* Autodetection mode, choose the architecture based the instructions
30449 if (no_cpu_selected ())
30451 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
30453 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
30454 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
30456 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
30457 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
30459 /* Code run during relaxation relies on selected_cpu being set. */
30460 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
30461 flags_ext
= arm_arch_none
;
30462 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
30463 selected_ext
= flags_ext
;
30464 selected_cpu
= flags
;
30466 /* Otherwise, choose the architecture based on the capabilities of the
30470 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
30471 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
30472 flags_ext
= selected_ext
;
30473 flags
= selected_cpu
;
30475 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
30477 /* Allow the user to override the reported architecture. */
30478 if (!ARM_FEATURE_ZERO (selected_object_arch
))
30480 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
30481 flags_ext
= arm_arch_none
;
30484 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
30486 /* When this function is run again after relaxation has happened there is no
30487 way to determine whether an architecture or CPU was specified by the user:
30488 - selected_cpu is set above for relaxation to work;
30489 - march_cpu_opt is not set if only -mcpu or .cpu is used;
30490 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
30491 Therefore, if not in -march=all case we first try an exact match and fall
30492 back to autodetection. */
30493 if (!skip_exact_match
)
30494 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
30496 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
30498 as_bad (_("no architecture contains all the instructions used\n"));
30500 /* Tag_CPU_name. */
30501 if (selected_cpu_name
[0])
30505 q
= selected_cpu_name
;
30506 if (strncmp (q
, "armv", 4) == 0)
30511 for (i
= 0; q
[i
]; i
++)
30512 q
[i
] = TOUPPER (q
[i
]);
30514 aeabi_set_attribute_string (Tag_CPU_name
, q
);
30517 /* Tag_CPU_arch. */
30518 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
30520 /* Tag_CPU_arch_profile. */
30521 if (profile
!= '\0')
30522 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
30524 /* Tag_DSP_extension. */
30525 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
30526 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
30528 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
30529 /* Tag_ARM_ISA_use. */
30530 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
30531 || ARM_FEATURE_ZERO (flags_arch
))
30532 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
30534 /* Tag_THUMB_ISA_use. */
30535 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
30536 || ARM_FEATURE_ZERO (flags_arch
))
30540 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
30541 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
30543 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
30547 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
30550 /* Tag_VFP_arch. */
30551 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
30552 aeabi_set_attribute_int (Tag_VFP_arch
,
30553 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
30555 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
30556 aeabi_set_attribute_int (Tag_VFP_arch
,
30557 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
30559 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
30562 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
30564 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
30566 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
30569 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
30570 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
30571 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
30572 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
30573 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
30575 /* Tag_ABI_HardFP_use. */
30576 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
30577 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
30578 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
30580 /* Tag_WMMX_arch. */
30581 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
30582 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
30583 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
30584 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
30586 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
30587 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
30588 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
30589 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
30590 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
30591 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
30593 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
30595 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
30599 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
30604 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
30605 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
30606 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
30607 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
30609 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
30610 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
30611 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
30615 We set Tag_DIV_use to two when integer divide instructions have been used
30616 in ARM state, or when Thumb integer divide instructions have been used,
30617 but we have no architecture profile set, nor have we any ARM instructions.
30619 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
30620 by the base architecture.
30622 For new architectures we will have to check these tests. */
30623 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
30624 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
30625 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
30626 aeabi_set_attribute_int (Tag_DIV_use
, 0);
30627 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
30628 || (profile
== '\0'
30629 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
30630 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
30631 aeabi_set_attribute_int (Tag_DIV_use
, 2);
30633 /* Tag_MP_extension_use. */
30634 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
30635 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
30637 /* Tag Virtualization_use. */
30638 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
30640 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
30643 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
30646 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
30647 finished and free extension feature bits which will not be used anymore. */
30650 arm_md_post_relax (void)
30652 aeabi_set_public_attributes ();
30653 XDELETE (mcpu_ext_opt
);
30654 mcpu_ext_opt
= NULL
;
30655 XDELETE (march_ext_opt
);
30656 march_ext_opt
= NULL
;
30659 /* Add the default contents for the .ARM.attributes section. */
30664 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
30667 aeabi_set_public_attributes ();
30669 #endif /* OBJ_ELF */
30671 /* Parse a .cpu directive. */
30674 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
30676 const struct arm_cpu_option_table
*opt
;
30680 name
= input_line_pointer
;
30681 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
30682 input_line_pointer
++;
30683 saved_char
= *input_line_pointer
;
30684 *input_line_pointer
= 0;
30686 /* Skip the first "all" entry. */
30687 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
30688 if (streq (opt
->name
, name
))
30690 selected_arch
= opt
->value
;
30691 selected_ext
= opt
->ext
;
30692 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
30693 if (opt
->canonical_name
)
30694 strcpy (selected_cpu_name
, opt
->canonical_name
);
30698 for (i
= 0; opt
->name
[i
]; i
++)
30699 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
30701 selected_cpu_name
[i
] = 0;
30703 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30705 *input_line_pointer
= saved_char
;
30706 demand_empty_rest_of_line ();
30709 as_bad (_("unknown cpu `%s'"), name
);
30710 *input_line_pointer
= saved_char
;
30711 ignore_rest_of_line ();
30714 /* Parse a .arch directive. */
30717 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
30719 const struct arm_arch_option_table
*opt
;
30723 name
= input_line_pointer
;
30724 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
30725 input_line_pointer
++;
30726 saved_char
= *input_line_pointer
;
30727 *input_line_pointer
= 0;
30729 /* Skip the first "all" entry. */
30730 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
30731 if (streq (opt
->name
, name
))
30733 selected_arch
= opt
->value
;
30734 selected_ext
= arm_arch_none
;
30735 selected_cpu
= selected_arch
;
30736 strcpy (selected_cpu_name
, opt
->name
);
30737 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30738 *input_line_pointer
= saved_char
;
30739 demand_empty_rest_of_line ();
30743 as_bad (_("unknown architecture `%s'\n"), name
);
30744 *input_line_pointer
= saved_char
;
30745 ignore_rest_of_line ();
30748 /* Parse a .object_arch directive. */
30751 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
30753 const struct arm_arch_option_table
*opt
;
30757 name
= input_line_pointer
;
30758 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
30759 input_line_pointer
++;
30760 saved_char
= *input_line_pointer
;
30761 *input_line_pointer
= 0;
30763 /* Skip the first "all" entry. */
30764 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
30765 if (streq (opt
->name
, name
))
30767 selected_object_arch
= opt
->value
;
30768 *input_line_pointer
= saved_char
;
30769 demand_empty_rest_of_line ();
30773 as_bad (_("unknown architecture `%s'\n"), name
);
30774 *input_line_pointer
= saved_char
;
30775 ignore_rest_of_line ();
30778 /* Parse a .arch_extension directive. */
30781 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
30783 const struct arm_option_extension_value_table
*opt
;
30786 int adding_value
= 1;
30788 name
= input_line_pointer
;
30789 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
30790 input_line_pointer
++;
30791 saved_char
= *input_line_pointer
;
30792 *input_line_pointer
= 0;
30794 if (strlen (name
) >= 2
30795 && strncmp (name
, "no", 2) == 0)
30801 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
30802 if (streq (opt
->name
, name
))
30804 int i
, nb_allowed_archs
=
30805 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
30806 for (i
= 0; i
< nb_allowed_archs
; i
++)
30809 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
30811 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
30815 if (i
== nb_allowed_archs
)
30817 as_bad (_("architectural extension `%s' is not allowed for the "
30818 "current base architecture"), name
);
30823 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
30826 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
30828 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
30829 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30830 *input_line_pointer
= saved_char
;
30831 demand_empty_rest_of_line ();
30832 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
30833 on this return so that duplicate extensions (extensions with the
30834 same name as a previous extension in the list) are not considered
30835 for command-line parsing. */
30839 if (opt
->name
== NULL
)
30840 as_bad (_("unknown architecture extension `%s'\n"), name
);
30842 *input_line_pointer
= saved_char
;
30843 ignore_rest_of_line ();
30846 /* Parse a .fpu directive. */
30849 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
30851 const struct arm_option_fpu_value_table
*opt
;
30855 name
= input_line_pointer
;
30856 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
30857 input_line_pointer
++;
30858 saved_char
= *input_line_pointer
;
30859 *input_line_pointer
= 0;
30861 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
30862 if (streq (opt
->name
, name
))
30864 selected_fpu
= opt
->value
;
30865 #ifndef CPU_DEFAULT
30866 if (no_cpu_selected ())
30867 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
30870 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30871 *input_line_pointer
= saved_char
;
30872 demand_empty_rest_of_line ();
30876 as_bad (_("unknown floating point format `%s'\n"), name
);
30877 *input_line_pointer
= saved_char
;
30878 ignore_rest_of_line ();
30881 /* Copy symbol information. */
30884 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
30886 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
30890 /* Given a symbolic attribute NAME, return the proper integer value.
30891 Returns -1 if the attribute is not known. */
30894 arm_convert_symbolic_attribute (const char *name
)
30896 static const struct
30901 attribute_table
[] =
30903 /* When you modify this table you should
30904 also modify the list in doc/c-arm.texi. */
30905 #define T(tag) {#tag, tag}
30906 T (Tag_CPU_raw_name
),
30909 T (Tag_CPU_arch_profile
),
30910 T (Tag_ARM_ISA_use
),
30911 T (Tag_THUMB_ISA_use
),
30915 T (Tag_Advanced_SIMD_arch
),
30916 T (Tag_PCS_config
),
30917 T (Tag_ABI_PCS_R9_use
),
30918 T (Tag_ABI_PCS_RW_data
),
30919 T (Tag_ABI_PCS_RO_data
),
30920 T (Tag_ABI_PCS_GOT_use
),
30921 T (Tag_ABI_PCS_wchar_t
),
30922 T (Tag_ABI_FP_rounding
),
30923 T (Tag_ABI_FP_denormal
),
30924 T (Tag_ABI_FP_exceptions
),
30925 T (Tag_ABI_FP_user_exceptions
),
30926 T (Tag_ABI_FP_number_model
),
30927 T (Tag_ABI_align_needed
),
30928 T (Tag_ABI_align8_needed
),
30929 T (Tag_ABI_align_preserved
),
30930 T (Tag_ABI_align8_preserved
),
30931 T (Tag_ABI_enum_size
),
30932 T (Tag_ABI_HardFP_use
),
30933 T (Tag_ABI_VFP_args
),
30934 T (Tag_ABI_WMMX_args
),
30935 T (Tag_ABI_optimization_goals
),
30936 T (Tag_ABI_FP_optimization_goals
),
30937 T (Tag_compatibility
),
30938 T (Tag_CPU_unaligned_access
),
30939 T (Tag_FP_HP_extension
),
30940 T (Tag_VFP_HP_extension
),
30941 T (Tag_ABI_FP_16bit_format
),
30942 T (Tag_MPextension_use
),
30944 T (Tag_nodefaults
),
30945 T (Tag_also_compatible_with
),
30946 T (Tag_conformance
),
30948 T (Tag_Virtualization_use
),
30949 T (Tag_DSP_extension
),
30951 /* We deliberately do not include Tag_MPextension_use_legacy. */
30959 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
30960 if (streq (name
, attribute_table
[i
].name
))
30961 return attribute_table
[i
].tag
;
30966 /* Apply sym value for relocations only in the case that they are for
30967 local symbols in the same segment as the fixup and you have the
30968 respective architectural feature for blx and simple switches. */
30971 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
30974 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
30975 /* PR 17444: If the local symbol is in a different section then a reloc
30976 will always be generated for it, so applying the symbol value now
30977 will result in a double offset being stored in the relocation. */
30978 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
30979 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
30981 switch (fixP
->fx_r_type
)
30983 case BFD_RELOC_ARM_PCREL_BLX
:
30984 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
30985 if (ARM_IS_FUNC (fixP
->fx_addsy
))
30989 case BFD_RELOC_ARM_PCREL_CALL
:
30990 case BFD_RELOC_THUMB_PCREL_BLX
:
30991 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
31002 #endif /* OBJ_ELF */