1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2018 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 static const arm_feature_set arm_ext_v6_notm
=
208 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
209 static const arm_feature_set arm_ext_v6_dsp
=
210 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
211 static const arm_feature_set arm_ext_barrier
=
212 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
213 static const arm_feature_set arm_ext_msr
=
214 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
215 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
216 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
217 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
218 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
220 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
222 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
223 static const arm_feature_set arm_ext_m
=
224 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
225 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
226 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
227 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
228 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
229 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
230 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
231 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
232 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
233 static const arm_feature_set arm_ext_v8m_main
=
234 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
235 /* Instructions in ARMv8-M only found in M profile architectures. */
236 static const arm_feature_set arm_ext_v8m_m_only
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v6t2_v8m
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
240 /* Instructions shared between ARMv8-A and ARMv8-M. */
241 static const arm_feature_set arm_ext_atomics
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
244 /* DSP instructions Tag_DSP_extension refers to. */
245 static const arm_feature_set arm_ext_dsp
=
246 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
248 static const arm_feature_set arm_ext_ras
=
249 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
250 /* FP16 instructions. */
251 static const arm_feature_set arm_ext_fp16
=
252 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
253 static const arm_feature_set arm_ext_fp16_fml
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
255 static const arm_feature_set arm_ext_v8_2
=
256 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
257 static const arm_feature_set arm_ext_v8_3
=
258 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
260 static const arm_feature_set arm_arch_any
= ARM_ANY
;
262 static const arm_feature_set fpu_any
= FPU_ANY
;
264 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
265 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
266 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
268 static const arm_feature_set arm_cext_iwmmxt2
=
269 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
270 static const arm_feature_set arm_cext_iwmmxt
=
271 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
272 static const arm_feature_set arm_cext_xscale
=
273 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
274 static const arm_feature_set arm_cext_maverick
=
275 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
276 static const arm_feature_set fpu_fpa_ext_v1
=
277 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
278 static const arm_feature_set fpu_fpa_ext_v2
=
279 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
280 static const arm_feature_set fpu_vfp_ext_v1xd
=
281 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
282 static const arm_feature_set fpu_vfp_ext_v1
=
283 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
284 static const arm_feature_set fpu_vfp_ext_v2
=
285 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
286 static const arm_feature_set fpu_vfp_ext_v3xd
=
287 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
288 static const arm_feature_set fpu_vfp_ext_v3
=
289 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
290 static const arm_feature_set fpu_vfp_ext_d32
=
291 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
292 static const arm_feature_set fpu_neon_ext_v1
=
293 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
294 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
295 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
297 static const arm_feature_set fpu_vfp_fp16
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
299 static const arm_feature_set fpu_neon_ext_fma
=
300 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
302 static const arm_feature_set fpu_vfp_ext_fma
=
303 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
304 static const arm_feature_set fpu_vfp_ext_armv8
=
305 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
306 static const arm_feature_set fpu_vfp_ext_armv8xd
=
307 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
308 static const arm_feature_set fpu_neon_ext_armv8
=
309 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
310 static const arm_feature_set fpu_crypto_ext_armv8
=
311 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
312 static const arm_feature_set crc_ext_armv8
=
313 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
314 static const arm_feature_set fpu_neon_ext_v8_1
=
315 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
316 static const arm_feature_set fpu_neon_ext_dotprod
=
317 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
319 static int mfloat_abi_opt
= -1;
320 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
322 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
323 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
325 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
326 /* Feature bits selected by the last -mcpu/-march or by the combination of the
327 last .cpu/.arch directive .arch_extension directives since that
329 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
330 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
331 static arm_feature_set selected_fpu
= FPU_NONE
;
332 /* Feature bits selected by the last .object_arch directive. */
333 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
334 /* Must be long enough to hold any of the names in arm_cpus. */
335 static char selected_cpu_name
[20];
337 extern FLONUM_TYPE generic_floating_point_number
;
339 /* Return if no cpu was selected on command-line. */
341 no_cpu_selected (void)
343 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
348 static int meabi_flags
= EABI_DEFAULT
;
350 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
353 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
358 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
363 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
364 symbolS
* GOT_symbol
;
367 /* 0: assemble for ARM,
368 1: assemble for Thumb,
369 2: assemble for Thumb even though target CPU does not support thumb
371 static int thumb_mode
= 0;
372 /* A value distinct from the possible values for thumb_mode that we
373 can use to record whether thumb_mode has been copied into the
374 tc_frag_data field of a frag. */
375 #define MODE_RECORDED (1 << 4)
377 /* Specifies the intrinsic IT insn behavior mode. */
378 enum implicit_it_mode
380 IMPLICIT_IT_MODE_NEVER
= 0x00,
381 IMPLICIT_IT_MODE_ARM
= 0x01,
382 IMPLICIT_IT_MODE_THUMB
= 0x02,
383 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
385 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
387 /* If unified_syntax is true, we are processing the new unified
388 ARM/Thumb syntax. Important differences from the old ARM mode:
390 - Immediate operands do not require a # prefix.
391 - Conditional affixes always appear at the end of the
392 instruction. (For backward compatibility, those instructions
393 that formerly had them in the middle, continue to accept them
395 - The IT instruction may appear, and if it does is validated
396 against subsequent conditional affixes. It does not generate
399 Important differences from the old Thumb mode:
401 - Immediate operands do not require a # prefix.
402 - Most of the V6T2 instructions are only available in unified mode.
403 - The .N and .W suffixes are recognized and honored (it is an error
404 if they cannot be honored).
405 - All instructions set the flags if and only if they have an 's' affix.
406 - Conditional affixes may be used. They are validated against
407 preceding IT instructions. Unlike ARM mode, you cannot use a
408 conditional affix except in the scope of an IT instruction. */
410 static bfd_boolean unified_syntax
= FALSE
;
412 /* An immediate operand can start with #, and ld*, st*, pld operands
413 can contain [ and ]. We need to tell APP not to elide whitespace
414 before a [, which can appear as the first operand for pld.
415 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
416 const char arm_symbol_chars
[] = "#[]{}";
431 enum neon_el_type type
;
435 #define NEON_MAX_TYPE_ELS 4
439 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
443 enum it_instruction_type
448 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
449 if inside, should be the last one. */
450 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
451 i.e. BKPT and NOP. */
452 IT_INSN
/* The IT insn has been parsed. */
455 /* The maximum number of operands we need. */
456 #define ARM_IT_MAX_OPERANDS 6
461 unsigned long instruction
;
465 /* "uncond_value" is set to the value in place of the conditional field in
466 unconditional versions of the instruction, or -1 if nothing is
469 struct neon_type vectype
;
470 /* This does not indicate an actual NEON instruction, only that
471 the mnemonic accepts neon-style type suffixes. */
473 /* Set to the opcode if the instruction needs relaxation.
474 Zero if the instruction is not relaxed. */
478 bfd_reloc_code_real_type type
;
483 enum it_instruction_type it_insn_type
;
489 struct neon_type_el vectype
;
490 unsigned present
: 1; /* Operand present. */
491 unsigned isreg
: 1; /* Operand was a register. */
492 unsigned immisreg
: 1; /* .imm field is a second register. */
493 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
494 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
495 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
496 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
497 instructions. This allows us to disambiguate ARM <-> vector insns. */
498 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
499 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
500 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
501 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
502 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
503 unsigned writeback
: 1; /* Operand has trailing ! */
504 unsigned preind
: 1; /* Preindexed address. */
505 unsigned postind
: 1; /* Postindexed address. */
506 unsigned negative
: 1; /* Index register was negated. */
507 unsigned shifted
: 1; /* Shift applied to operation. */
508 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
509 } operands
[ARM_IT_MAX_OPERANDS
];
512 static struct arm_it inst
;
514 #define NUM_FLOAT_VALS 8
516 const char * fp_const
[] =
518 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
521 /* Number of littlenums required to hold an extended precision number. */
522 #define MAX_LITTLENUMS 6
524 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
534 #define CP_T_X 0x00008000
535 #define CP_T_Y 0x00400000
537 #define CONDS_BIT 0x00100000
538 #define LOAD_BIT 0x00100000
540 #define DOUBLE_LOAD_FLAG 0x00000001
544 const char * template_name
;
548 #define COND_ALWAYS 0xE
552 const char * template_name
;
556 struct asm_barrier_opt
558 const char * template_name
;
560 const arm_feature_set arch
;
563 /* The bit that distinguishes CPSR and SPSR. */
564 #define SPSR_BIT (1 << 22)
566 /* The individual PSR flag bits. */
567 #define PSR_c (1 << 16)
568 #define PSR_x (1 << 17)
569 #define PSR_s (1 << 18)
570 #define PSR_f (1 << 19)
575 bfd_reloc_code_real_type reloc
;
580 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
581 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
586 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
589 /* Bits for DEFINED field in neon_typed_alias. */
590 #define NTA_HASTYPE 1
591 #define NTA_HASINDEX 2
593 struct neon_typed_alias
595 unsigned char defined
;
597 struct neon_type_el eltype
;
600 /* ARM register categories. This includes coprocessor numbers and various
601 architecture extensions' registers. Each entry should have an error message
602 in reg_expected_msgs below. */
630 /* Structure for a hash table entry for a register.
631 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
632 information which states whether a vector type or index is specified (for a
633 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
639 unsigned char builtin
;
640 struct neon_typed_alias
* neon
;
643 /* Diagnostics used when we don't get a register of the expected type. */
644 const char * const reg_expected_msgs
[] =
646 [REG_TYPE_RN
] = N_("ARM register expected"),
647 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
648 [REG_TYPE_CN
] = N_("co-processor register expected"),
649 [REG_TYPE_FN
] = N_("FPA register expected"),
650 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
651 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
652 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
653 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
654 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
655 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
656 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
658 [REG_TYPE_VFC
] = N_("VFP system register expected"),
659 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
660 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
661 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
662 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
663 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
664 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
665 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
666 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
667 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
668 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
669 [REG_TYPE_RNB
] = N_("")
672 /* Some well known registers that we refer to directly elsewhere. */
678 /* ARM instructions take 4bytes in the object file, Thumb instructions
684 /* Basic string to match. */
685 const char * template_name
;
687 /* Parameters to instruction. */
688 unsigned int operands
[8];
690 /* Conditional tag - see opcode_lookup. */
691 unsigned int tag
: 4;
693 /* Basic instruction code. */
694 unsigned int avalue
: 28;
696 /* Thumb-format instruction code. */
699 /* Which architecture variant provides this instruction. */
700 const arm_feature_set
* avariant
;
701 const arm_feature_set
* tvariant
;
703 /* Function to call to encode instruction in ARM format. */
704 void (* aencode
) (void);
706 /* Function to call to encode instruction in Thumb format. */
707 void (* tencode
) (void);
710 /* Defines for various bits that we will want to toggle. */
711 #define INST_IMMEDIATE 0x02000000
712 #define OFFSET_REG 0x02000000
713 #define HWOFFSET_IMM 0x00400000
714 #define SHIFT_BY_REG 0x00000010
715 #define PRE_INDEX 0x01000000
716 #define INDEX_UP 0x00800000
717 #define WRITE_BACK 0x00200000
718 #define LDM_TYPE_2_OR_3 0x00400000
719 #define CPSI_MMOD 0x00020000
721 #define LITERAL_MASK 0xf000f000
722 #define OPCODE_MASK 0xfe1fffff
723 #define V4_STR_BIT 0x00000020
724 #define VLDR_VMOV_SAME 0x0040f000
726 #define T2_SUBS_PC_LR 0xf3de8f00
728 #define DATA_OP_SHIFT 21
729 #define SBIT_SHIFT 20
731 #define T2_OPCODE_MASK 0xfe1fffff
732 #define T2_DATA_OP_SHIFT 21
733 #define T2_SBIT_SHIFT 20
735 #define A_COND_MASK 0xf0000000
736 #define A_PUSH_POP_OP_MASK 0x0fff0000
738 /* Opcodes for pushing/poping registers to/from the stack. */
739 #define A1_OPCODE_PUSH 0x092d0000
740 #define A2_OPCODE_PUSH 0x052d0004
741 #define A2_OPCODE_POP 0x049d0004
743 /* Codes to distinguish the arithmetic instructions. */
754 #define OPCODE_CMP 10
755 #define OPCODE_CMN 11
756 #define OPCODE_ORR 12
757 #define OPCODE_MOV 13
758 #define OPCODE_BIC 14
759 #define OPCODE_MVN 15
761 #define T2_OPCODE_AND 0
762 #define T2_OPCODE_BIC 1
763 #define T2_OPCODE_ORR 2
764 #define T2_OPCODE_ORN 3
765 #define T2_OPCODE_EOR 4
766 #define T2_OPCODE_ADD 8
767 #define T2_OPCODE_ADC 10
768 #define T2_OPCODE_SBC 11
769 #define T2_OPCODE_SUB 13
770 #define T2_OPCODE_RSB 14
772 #define T_OPCODE_MUL 0x4340
773 #define T_OPCODE_TST 0x4200
774 #define T_OPCODE_CMN 0x42c0
775 #define T_OPCODE_NEG 0x4240
776 #define T_OPCODE_MVN 0x43c0
778 #define T_OPCODE_ADD_R3 0x1800
779 #define T_OPCODE_SUB_R3 0x1a00
780 #define T_OPCODE_ADD_HI 0x4400
781 #define T_OPCODE_ADD_ST 0xb000
782 #define T_OPCODE_SUB_ST 0xb080
783 #define T_OPCODE_ADD_SP 0xa800
784 #define T_OPCODE_ADD_PC 0xa000
785 #define T_OPCODE_ADD_I8 0x3000
786 #define T_OPCODE_SUB_I8 0x3800
787 #define T_OPCODE_ADD_I3 0x1c00
788 #define T_OPCODE_SUB_I3 0x1e00
790 #define T_OPCODE_ASR_R 0x4100
791 #define T_OPCODE_LSL_R 0x4080
792 #define T_OPCODE_LSR_R 0x40c0
793 #define T_OPCODE_ROR_R 0x41c0
794 #define T_OPCODE_ASR_I 0x1000
795 #define T_OPCODE_LSL_I 0x0000
796 #define T_OPCODE_LSR_I 0x0800
798 #define T_OPCODE_MOV_I8 0x2000
799 #define T_OPCODE_CMP_I8 0x2800
800 #define T_OPCODE_CMP_LR 0x4280
801 #define T_OPCODE_MOV_HR 0x4600
802 #define T_OPCODE_CMP_HR 0x4500
804 #define T_OPCODE_LDR_PC 0x4800
805 #define T_OPCODE_LDR_SP 0x9800
806 #define T_OPCODE_STR_SP 0x9000
807 #define T_OPCODE_LDR_IW 0x6800
808 #define T_OPCODE_STR_IW 0x6000
809 #define T_OPCODE_LDR_IH 0x8800
810 #define T_OPCODE_STR_IH 0x8000
811 #define T_OPCODE_LDR_IB 0x7800
812 #define T_OPCODE_STR_IB 0x7000
813 #define T_OPCODE_LDR_RW 0x5800
814 #define T_OPCODE_STR_RW 0x5000
815 #define T_OPCODE_LDR_RH 0x5a00
816 #define T_OPCODE_STR_RH 0x5200
817 #define T_OPCODE_LDR_RB 0x5c00
818 #define T_OPCODE_STR_RB 0x5400
820 #define T_OPCODE_PUSH 0xb400
821 #define T_OPCODE_POP 0xbc00
823 #define T_OPCODE_BRANCH 0xe000
825 #define THUMB_SIZE 2 /* Size of thumb instruction. */
826 #define THUMB_PP_PC_LR 0x0100
827 #define THUMB_LOAD_BIT 0x0800
828 #define THUMB2_LOAD_BIT 0x00100000
830 #define BAD_ARGS _("bad arguments to instruction")
831 #define BAD_SP _("r13 not allowed here")
832 #define BAD_PC _("r15 not allowed here")
833 #define BAD_COND _("instruction cannot be conditional")
834 #define BAD_OVERLAP _("registers may not be the same")
835 #define BAD_HIREG _("lo register required")
836 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
837 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
838 #define BAD_BRANCH _("branch must be last instruction in IT block")
839 #define BAD_NOT_IT _("instruction not allowed in IT block")
840 #define BAD_FPU _("selected FPU does not support instruction")
841 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
842 #define BAD_IT_COND _("incorrect condition in IT block")
843 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
844 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
845 #define BAD_PC_ADDRESSING \
846 _("cannot use register index with PC-relative addressing")
847 #define BAD_PC_WRITEBACK \
848 _("cannot use writeback with PC-relative addressing")
849 #define BAD_RANGE _("branch out of range")
850 #define BAD_FP16 _("selected processor does not support fp16 instruction")
851 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
852 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
854 static struct hash_control
* arm_ops_hsh
;
855 static struct hash_control
* arm_cond_hsh
;
856 static struct hash_control
* arm_shift_hsh
;
857 static struct hash_control
* arm_psr_hsh
;
858 static struct hash_control
* arm_v7m_psr_hsh
;
859 static struct hash_control
* arm_reg_hsh
;
860 static struct hash_control
* arm_reloc_hsh
;
861 static struct hash_control
* arm_barrier_opt_hsh
;
863 /* Stuff needed to resolve the label ambiguity
872 symbolS
* last_label_seen
;
873 static int label_is_thumb_function_name
= FALSE
;
875 /* Literal pool structure. Held on a per-section
876 and per-sub-section basis. */
878 #define MAX_LITERAL_POOL_SIZE 1024
879 typedef struct literal_pool
881 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
882 unsigned int next_free_entry
;
888 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
890 struct literal_pool
* next
;
891 unsigned int alignment
;
894 /* Pointer to a linked list of literal pools. */
895 literal_pool
* list_of_pools
= NULL
;
897 typedef enum asmfunc_states
900 WAITING_ASMFUNC_NAME
,
904 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
907 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
909 static struct current_it now_it
;
913 now_it_compatible (int cond
)
915 return (cond
& ~1) == (now_it
.cc
& ~1);
919 conditional_insn (void)
921 return inst
.cond
!= COND_ALWAYS
;
924 static int in_it_block (void);
926 static int handle_it_state (void);
928 static void force_automatic_it_block_close (void);
930 static void it_fsm_post_encode (void);
932 #define set_it_insn_type(type) \
935 inst.it_insn_type = type; \
936 if (handle_it_state () == FAIL) \
941 #define set_it_insn_type_nonvoid(type, failret) \
944 inst.it_insn_type = type; \
945 if (handle_it_state () == FAIL) \
950 #define set_it_insn_type_last() \
953 if (inst.cond == COND_ALWAYS) \
954 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
956 set_it_insn_type (INSIDE_IT_LAST_INSN); \
962 /* This array holds the chars that always start a comment. If the
963 pre-processor is disabled, these aren't very useful. */
964 char arm_comment_chars
[] = "@";
966 /* This array holds the chars that only start a comment at the beginning of
967 a line. If the line seems to have the form '# 123 filename'
968 .line and .file directives will appear in the pre-processed output. */
969 /* Note that input_file.c hand checks for '#' at the beginning of the
970 first line of the input file. This is because the compiler outputs
971 #NO_APP at the beginning of its output. */
972 /* Also note that comments like this one will always work. */
973 const char line_comment_chars
[] = "#";
975 char arm_line_separator_chars
[] = ";";
977 /* Chars that can be used to separate mant
978 from exp in floating point numbers. */
979 const char EXP_CHARS
[] = "eE";
981 /* Chars that mean this number is a floating point constant. */
985 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
987 /* Prefix characters that indicate the start of an immediate
989 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
991 /* Separator character handling. */
993 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
996 skip_past_char (char ** str
, char c
)
998 /* PR gas/14987: Allow for whitespace before the expected character. */
999 skip_whitespace (*str
);
1010 #define skip_past_comma(str) skip_past_char (str, ',')
1012 /* Arithmetic expressions (possibly involving symbols). */
1014 /* Return TRUE if anything in the expression is a bignum. */
1017 walk_no_bignums (symbolS
* sp
)
1019 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1022 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1024 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1025 || (symbol_get_value_expression (sp
)->X_op_symbol
1026 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1032 static bfd_boolean in_my_get_expression
= FALSE
;
1034 /* Third argument to my_get_expression. */
1035 #define GE_NO_PREFIX 0
1036 #define GE_IMM_PREFIX 1
1037 #define GE_OPT_PREFIX 2
1038 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1039 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1040 #define GE_OPT_PREFIX_BIG 3
1043 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1047 /* In unified syntax, all prefixes are optional. */
1049 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1052 switch (prefix_mode
)
1054 case GE_NO_PREFIX
: break;
1056 if (!is_immediate_prefix (**str
))
1058 inst
.error
= _("immediate expression requires a # prefix");
1064 case GE_OPT_PREFIX_BIG
:
1065 if (is_immediate_prefix (**str
))
1072 memset (ep
, 0, sizeof (expressionS
));
1074 save_in
= input_line_pointer
;
1075 input_line_pointer
= *str
;
1076 in_my_get_expression
= TRUE
;
1078 in_my_get_expression
= FALSE
;
1080 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1082 /* We found a bad or missing expression in md_operand(). */
1083 *str
= input_line_pointer
;
1084 input_line_pointer
= save_in
;
1085 if (inst
.error
== NULL
)
1086 inst
.error
= (ep
->X_op
== O_absent
1087 ? _("missing expression") :_("bad expression"));
1091 /* Get rid of any bignums now, so that we don't generate an error for which
1092 we can't establish a line number later on. Big numbers are never valid
1093 in instructions, which is where this routine is always called. */
1094 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1095 && (ep
->X_op
== O_big
1096 || (ep
->X_add_symbol
1097 && (walk_no_bignums (ep
->X_add_symbol
)
1099 && walk_no_bignums (ep
->X_op_symbol
))))))
1101 inst
.error
= _("invalid constant");
1102 *str
= input_line_pointer
;
1103 input_line_pointer
= save_in
;
1107 *str
= input_line_pointer
;
1108 input_line_pointer
= save_in
;
1112 /* Turn a string in input_line_pointer into a floating point constant
1113 of type TYPE, and store the appropriate bytes in *LITP. The number
1114 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1115 returned, or NULL on OK.
1117 Note that fp constants aren't represent in the normal way on the ARM.
1118 In big endian mode, things are as expected. However, in little endian
1119 mode fp constants are big-endian word-wise, and little-endian byte-wise
1120 within the words. For example, (double) 1.1 in big endian mode is
1121 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1122 the byte sequence 99 99 f1 3f 9a 99 99 99.
1124 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1127 md_atof (int type
, char * litP
, int * sizeP
)
1130 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1162 return _("Unrecognized or unsupported floating point constant");
1165 t
= atof_ieee (input_line_pointer
, type
, words
);
1167 input_line_pointer
= t
;
1168 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1170 if (target_big_endian
)
1172 for (i
= 0; i
< prec
; i
++)
1174 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1175 litP
+= sizeof (LITTLENUM_TYPE
);
1180 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1181 for (i
= prec
- 1; i
>= 0; i
--)
1183 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1184 litP
+= sizeof (LITTLENUM_TYPE
);
1187 /* For a 4 byte float the order of elements in `words' is 1 0.
1188 For an 8 byte float the order is 1 0 3 2. */
1189 for (i
= 0; i
< prec
; i
+= 2)
1191 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1192 sizeof (LITTLENUM_TYPE
));
1193 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1194 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1195 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1202 /* We handle all bad expressions here, so that we can report the faulty
1203 instruction in the error message. */
1206 md_operand (expressionS
* exp
)
1208 if (in_my_get_expression
)
1209 exp
->X_op
= O_illegal
;
1212 /* Immediate values. */
1215 /* Generic immediate-value read function for use in directives.
1216 Accepts anything that 'expression' can fold to a constant.
1217 *val receives the number. */
1220 immediate_for_directive (int *val
)
1223 exp
.X_op
= O_illegal
;
1225 if (is_immediate_prefix (*input_line_pointer
))
1227 input_line_pointer
++;
1231 if (exp
.X_op
!= O_constant
)
1233 as_bad (_("expected #constant"));
1234 ignore_rest_of_line ();
1237 *val
= exp
.X_add_number
;
1242 /* Register parsing. */
1244 /* Generic register parser. CCP points to what should be the
1245 beginning of a register name. If it is indeed a valid register
1246 name, advance CCP over it and return the reg_entry structure;
1247 otherwise return NULL. Does not issue diagnostics. */
1249 static struct reg_entry
*
1250 arm_reg_parse_multi (char **ccp
)
1254 struct reg_entry
*reg
;
1256 skip_whitespace (start
);
1258 #ifdef REGISTER_PREFIX
1259 if (*start
!= REGISTER_PREFIX
)
1263 #ifdef OPTIONAL_REGISTER_PREFIX
1264 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1269 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1274 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1276 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1286 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1287 enum arm_reg_type type
)
1289 /* Alternative syntaxes are accepted for a few register classes. */
1296 /* Generic coprocessor register names are allowed for these. */
1297 if (reg
&& reg
->type
== REG_TYPE_CN
)
1302 /* For backward compatibility, a bare number is valid here. */
1304 unsigned long processor
= strtoul (start
, ccp
, 10);
1305 if (*ccp
!= start
&& processor
<= 15)
1310 case REG_TYPE_MMXWC
:
1311 /* WC includes WCG. ??? I'm not sure this is true for all
1312 instructions that take WC registers. */
1313 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1324 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1325 return value is the register number or FAIL. */
1328 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1331 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1334 /* Do not allow a scalar (reg+index) to parse as a register. */
1335 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1338 if (reg
&& reg
->type
== type
)
1341 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1348 /* Parse a Neon type specifier. *STR should point at the leading '.'
1349 character. Does no verification at this stage that the type fits the opcode
1356 Can all be legally parsed by this function.
1358 Fills in neon_type struct pointer with parsed information, and updates STR
1359 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1360 type, FAIL if not. */
1363 parse_neon_type (struct neon_type
*type
, char **str
)
1370 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1372 enum neon_el_type thistype
= NT_untyped
;
1373 unsigned thissize
= -1u;
1380 /* Just a size without an explicit type. */
1384 switch (TOLOWER (*ptr
))
1386 case 'i': thistype
= NT_integer
; break;
1387 case 'f': thistype
= NT_float
; break;
1388 case 'p': thistype
= NT_poly
; break;
1389 case 's': thistype
= NT_signed
; break;
1390 case 'u': thistype
= NT_unsigned
; break;
1392 thistype
= NT_float
;
1397 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1403 /* .f is an abbreviation for .f32. */
1404 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1409 thissize
= strtoul (ptr
, &ptr
, 10);
1411 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1414 as_bad (_("bad size %d in type specifier"), thissize
);
1422 type
->el
[type
->elems
].type
= thistype
;
1423 type
->el
[type
->elems
].size
= thissize
;
1428 /* Empty/missing type is not a successful parse. */
1429 if (type
->elems
== 0)
1437 /* Errors may be set multiple times during parsing or bit encoding
1438 (particularly in the Neon bits), but usually the earliest error which is set
1439 will be the most meaningful. Avoid overwriting it with later (cascading)
1440 errors by calling this function. */
1443 first_error (const char *err
)
1449 /* Parse a single type, e.g. ".s32", leading period included. */
1451 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1454 struct neon_type optype
;
1458 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1460 if (optype
.elems
== 1)
1461 *vectype
= optype
.el
[0];
1464 first_error (_("only one type should be specified for operand"));
1470 first_error (_("vector type expected"));
1482 /* Special meanings for indices (which have a range of 0-7), which will fit into
1485 #define NEON_ALL_LANES 15
1486 #define NEON_INTERLEAVE_LANES 14
1488 /* Parse either a register or a scalar, with an optional type. Return the
1489 register number, and optionally fill in the actual type of the register
1490 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1491 type/index information in *TYPEINFO. */
1494 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1495 enum arm_reg_type
*rtype
,
1496 struct neon_typed_alias
*typeinfo
)
1499 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1500 struct neon_typed_alias atype
;
1501 struct neon_type_el parsetype
;
1505 atype
.eltype
.type
= NT_invtype
;
1506 atype
.eltype
.size
= -1;
1508 /* Try alternate syntax for some types of register. Note these are mutually
1509 exclusive with the Neon syntax extensions. */
1512 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1520 /* Undo polymorphism when a set of register types may be accepted. */
1521 if ((type
== REG_TYPE_NDQ
1522 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1523 || (type
== REG_TYPE_VFSD
1524 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1525 || (type
== REG_TYPE_NSDQ
1526 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1527 || reg
->type
== REG_TYPE_NQ
))
1528 || (type
== REG_TYPE_NSD
1529 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1530 || (type
== REG_TYPE_MMXWC
1531 && (reg
->type
== REG_TYPE_MMXWCG
)))
1532 type
= (enum arm_reg_type
) reg
->type
;
1534 if (type
!= reg
->type
)
1540 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1542 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1544 first_error (_("can't redefine type for operand"));
1547 atype
.defined
|= NTA_HASTYPE
;
1548 atype
.eltype
= parsetype
;
1551 if (skip_past_char (&str
, '[') == SUCCESS
)
1553 if (type
!= REG_TYPE_VFD
1554 && !(type
== REG_TYPE_VFS
1555 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
)))
1557 first_error (_("only D registers may be indexed"));
1561 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1563 first_error (_("can't change index for operand"));
1567 atype
.defined
|= NTA_HASINDEX
;
1569 if (skip_past_char (&str
, ']') == SUCCESS
)
1570 atype
.index
= NEON_ALL_LANES
;
1575 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1577 if (exp
.X_op
!= O_constant
)
1579 first_error (_("constant expression required"));
1583 if (skip_past_char (&str
, ']') == FAIL
)
1586 atype
.index
= exp
.X_add_number
;
1601 /* Like arm_reg_parse, but allow allow the following extra features:
1602 - If RTYPE is non-zero, return the (possibly restricted) type of the
1603 register (e.g. Neon double or quad reg when either has been requested).
1604 - If this is a Neon vector type with additional type information, fill
1605 in the struct pointed to by VECTYPE (if non-NULL).
1606 This function will fault on encountering a scalar. */
1609 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1610 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1612 struct neon_typed_alias atype
;
1614 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1619 /* Do not allow regname(... to parse as a register. */
1623 /* Do not allow a scalar (reg+index) to parse as a register. */
1624 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1626 first_error (_("register operand expected, but got scalar"));
1631 *vectype
= atype
.eltype
;
1638 #define NEON_SCALAR_REG(X) ((X) >> 4)
1639 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1641 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1642 have enough information to be able to do a good job bounds-checking. So, we
1643 just do easy checks here, and do further checks later. */
1646 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1650 struct neon_typed_alias atype
;
1651 enum arm_reg_type reg_type
= REG_TYPE_VFD
;
1654 reg_type
= REG_TYPE_VFS
;
1656 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1658 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1661 if (atype
.index
== NEON_ALL_LANES
)
1663 first_error (_("scalar must have an index"));
1666 else if (atype
.index
>= 64 / elsize
)
1668 first_error (_("scalar index out of range"));
1673 *type
= atype
.eltype
;
1677 return reg
* 16 + atype
.index
;
1680 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1683 parse_reg_list (char ** strp
)
1685 char * str
= * strp
;
1689 /* We come back here if we get ranges concatenated by '+' or '|'. */
1692 skip_whitespace (str
);
1706 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1708 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1718 first_error (_("bad range in register list"));
1722 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1724 if (range
& (1 << i
))
1726 (_("Warning: duplicated register (r%d) in register list"),
1734 if (range
& (1 << reg
))
1735 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1737 else if (reg
<= cur_reg
)
1738 as_tsktsk (_("Warning: register range not in ascending order"));
1743 while (skip_past_comma (&str
) != FAIL
1744 || (in_range
= 1, *str
++ == '-'));
1747 if (skip_past_char (&str
, '}') == FAIL
)
1749 first_error (_("missing `}'"));
1757 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1760 if (exp
.X_op
== O_constant
)
1762 if (exp
.X_add_number
1763 != (exp
.X_add_number
& 0x0000ffff))
1765 inst
.error
= _("invalid register mask");
1769 if ((range
& exp
.X_add_number
) != 0)
1771 int regno
= range
& exp
.X_add_number
;
1774 regno
= (1 << regno
) - 1;
1776 (_("Warning: duplicated register (r%d) in register list"),
1780 range
|= exp
.X_add_number
;
1784 if (inst
.reloc
.type
!= 0)
1786 inst
.error
= _("expression too complex");
1790 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1791 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1792 inst
.reloc
.pc_rel
= 0;
1796 if (*str
== '|' || *str
== '+')
1802 while (another_range
);
1808 /* Types of registers in a list. */
1817 /* Parse a VFP register list. If the string is invalid return FAIL.
1818 Otherwise return the number of registers, and set PBASE to the first
1819 register. Parses registers of type ETYPE.
1820 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1821 - Q registers can be used to specify pairs of D registers
1822 - { } can be omitted from around a singleton register list
1823 FIXME: This is not implemented, as it would require backtracking in
1826 This could be done (the meaning isn't really ambiguous), but doesn't
1827 fit in well with the current parsing framework.
1828 - 32 D registers may be used (also true for VFPv3).
1829 FIXME: Types are ignored in these register lists, which is probably a
1833 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1838 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1842 unsigned long mask
= 0;
1845 if (skip_past_char (&str
, '{') == FAIL
)
1847 inst
.error
= _("expecting {");
1854 regtype
= REG_TYPE_VFS
;
1859 regtype
= REG_TYPE_VFD
;
1862 case REGLIST_NEON_D
:
1863 regtype
= REG_TYPE_NDQ
;
1867 if (etype
!= REGLIST_VFP_S
)
1869 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1870 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1874 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1877 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1884 base_reg
= max_regs
;
1888 int setmask
= 1, addregs
= 1;
1890 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1892 if (new_base
== FAIL
)
1894 first_error (_(reg_expected_msgs
[regtype
]));
1898 if (new_base
>= max_regs
)
1900 first_error (_("register out of range in list"));
1904 /* Note: a value of 2 * n is returned for the register Q<n>. */
1905 if (regtype
== REG_TYPE_NQ
)
1911 if (new_base
< base_reg
)
1912 base_reg
= new_base
;
1914 if (mask
& (setmask
<< new_base
))
1916 first_error (_("invalid register list"));
1920 if ((mask
>> new_base
) != 0 && ! warned
)
1922 as_tsktsk (_("register list not in ascending order"));
1926 mask
|= setmask
<< new_base
;
1929 if (*str
== '-') /* We have the start of a range expression */
1935 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1938 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1942 if (high_range
>= max_regs
)
1944 first_error (_("register out of range in list"));
1948 if (regtype
== REG_TYPE_NQ
)
1949 high_range
= high_range
+ 1;
1951 if (high_range
<= new_base
)
1953 inst
.error
= _("register range not in ascending order");
1957 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1959 if (mask
& (setmask
<< new_base
))
1961 inst
.error
= _("invalid register list");
1965 mask
|= setmask
<< new_base
;
1970 while (skip_past_comma (&str
) != FAIL
);
1974 /* Sanity check -- should have raised a parse error above. */
1975 if (count
== 0 || count
> max_regs
)
1980 /* Final test -- the registers must be consecutive. */
1982 for (i
= 0; i
< count
; i
++)
1984 if ((mask
& (1u << i
)) == 0)
1986 inst
.error
= _("non-contiguous register range");
1996 /* True if two alias types are the same. */
1999 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2007 if (a
->defined
!= b
->defined
)
2010 if ((a
->defined
& NTA_HASTYPE
) != 0
2011 && (a
->eltype
.type
!= b
->eltype
.type
2012 || a
->eltype
.size
!= b
->eltype
.size
))
2015 if ((a
->defined
& NTA_HASINDEX
) != 0
2016 && (a
->index
!= b
->index
))
2022 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2023 The base register is put in *PBASE.
2024 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2026 The register stride (minus one) is put in bit 4 of the return value.
2027 Bits [6:5] encode the list length (minus one).
2028 The type of the list elements is put in *ELTYPE, if non-NULL. */
2030 #define NEON_LANE(X) ((X) & 0xf)
2031 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2032 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2035 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2036 struct neon_type_el
*eltype
)
2043 int leading_brace
= 0;
2044 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2045 const char *const incr_error
= _("register stride must be 1 or 2");
2046 const char *const type_error
= _("mismatched element/structure types in list");
2047 struct neon_typed_alias firsttype
;
2048 firsttype
.defined
= 0;
2049 firsttype
.eltype
.type
= NT_invtype
;
2050 firsttype
.eltype
.size
= -1;
2051 firsttype
.index
= -1;
2053 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2058 struct neon_typed_alias atype
;
2059 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2063 first_error (_(reg_expected_msgs
[rtype
]));
2070 if (rtype
== REG_TYPE_NQ
)
2076 else if (reg_incr
== -1)
2078 reg_incr
= getreg
- base_reg
;
2079 if (reg_incr
< 1 || reg_incr
> 2)
2081 first_error (_(incr_error
));
2085 else if (getreg
!= base_reg
+ reg_incr
* count
)
2087 first_error (_(incr_error
));
2091 if (! neon_alias_types_same (&atype
, &firsttype
))
2093 first_error (_(type_error
));
2097 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2101 struct neon_typed_alias htype
;
2102 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2104 lane
= NEON_INTERLEAVE_LANES
;
2105 else if (lane
!= NEON_INTERLEAVE_LANES
)
2107 first_error (_(type_error
));
2112 else if (reg_incr
!= 1)
2114 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2118 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2121 first_error (_(reg_expected_msgs
[rtype
]));
2124 if (! neon_alias_types_same (&htype
, &firsttype
))
2126 first_error (_(type_error
));
2129 count
+= hireg
+ dregs
- getreg
;
2133 /* If we're using Q registers, we can't use [] or [n] syntax. */
2134 if (rtype
== REG_TYPE_NQ
)
2140 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2144 else if (lane
!= atype
.index
)
2146 first_error (_(type_error
));
2150 else if (lane
== -1)
2151 lane
= NEON_INTERLEAVE_LANES
;
2152 else if (lane
!= NEON_INTERLEAVE_LANES
)
2154 first_error (_(type_error
));
2159 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2161 /* No lane set by [x]. We must be interleaving structures. */
2163 lane
= NEON_INTERLEAVE_LANES
;
2166 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2167 || (count
> 1 && reg_incr
== -1))
2169 first_error (_("error parsing element/structure list"));
2173 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2175 first_error (_("expected }"));
2183 *eltype
= firsttype
.eltype
;
2188 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2191 /* Parse an explicit relocation suffix on an expression. This is
2192 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2193 arm_reloc_hsh contains no entries, so this function can only
2194 succeed if there is no () after the word. Returns -1 on error,
2195 BFD_RELOC_UNUSED if there wasn't any suffix. */
2198 parse_reloc (char **str
)
2200 struct reloc_entry
*r
;
2204 return BFD_RELOC_UNUSED
;
2209 while (*q
&& *q
!= ')' && *q
!= ',')
2214 if ((r
= (struct reloc_entry
*)
2215 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2222 /* Directives: register aliases. */
2224 static struct reg_entry
*
2225 insert_reg_alias (char *str
, unsigned number
, int type
)
2227 struct reg_entry
*new_reg
;
2230 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2232 if (new_reg
->builtin
)
2233 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2235 /* Only warn about a redefinition if it's not defined as the
2237 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2238 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2243 name
= xstrdup (str
);
2244 new_reg
= XNEW (struct reg_entry
);
2246 new_reg
->name
= name
;
2247 new_reg
->number
= number
;
2248 new_reg
->type
= type
;
2249 new_reg
->builtin
= FALSE
;
2250 new_reg
->neon
= NULL
;
2252 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2259 insert_neon_reg_alias (char *str
, int number
, int type
,
2260 struct neon_typed_alias
*atype
)
2262 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2266 first_error (_("attempt to redefine typed alias"));
2272 reg
->neon
= XNEW (struct neon_typed_alias
);
2273 *reg
->neon
= *atype
;
2277 /* Look for the .req directive. This is of the form:
2279 new_register_name .req existing_register_name
2281 If we find one, or if it looks sufficiently like one that we want to
2282 handle any error here, return TRUE. Otherwise return FALSE. */
2285 create_register_alias (char * newname
, char *p
)
2287 struct reg_entry
*old
;
2288 char *oldname
, *nbuf
;
2291 /* The input scrubber ensures that whitespace after the mnemonic is
2292 collapsed to single spaces. */
2294 if (strncmp (oldname
, " .req ", 6) != 0)
2298 if (*oldname
== '\0')
2301 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2304 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2308 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2309 the desired alias name, and p points to its end. If not, then
2310 the desired alias name is in the global original_case_string. */
2311 #ifdef TC_CASE_SENSITIVE
2314 newname
= original_case_string
;
2315 nlen
= strlen (newname
);
2318 nbuf
= xmemdup0 (newname
, nlen
);
2320 /* Create aliases under the new name as stated; an all-lowercase
2321 version of the new name; and an all-uppercase version of the new
2323 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2325 for (p
= nbuf
; *p
; p
++)
2328 if (strncmp (nbuf
, newname
, nlen
))
2330 /* If this attempt to create an additional alias fails, do not bother
2331 trying to create the all-lower case alias. We will fail and issue
2332 a second, duplicate error message. This situation arises when the
2333 programmer does something like:
2336 The second .req creates the "Foo" alias but then fails to create
2337 the artificial FOO alias because it has already been created by the
2339 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2346 for (p
= nbuf
; *p
; p
++)
2349 if (strncmp (nbuf
, newname
, nlen
))
2350 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2357 /* Create a Neon typed/indexed register alias using directives, e.g.:
2362 These typed registers can be used instead of the types specified after the
2363 Neon mnemonic, so long as all operands given have types. Types can also be
2364 specified directly, e.g.:
2365 vadd d0.s32, d1.s32, d2.s32 */
2368 create_neon_reg_alias (char *newname
, char *p
)
2370 enum arm_reg_type basetype
;
2371 struct reg_entry
*basereg
;
2372 struct reg_entry mybasereg
;
2373 struct neon_type ntype
;
2374 struct neon_typed_alias typeinfo
;
2375 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2378 typeinfo
.defined
= 0;
2379 typeinfo
.eltype
.type
= NT_invtype
;
2380 typeinfo
.eltype
.size
= -1;
2381 typeinfo
.index
= -1;
2385 if (strncmp (p
, " .dn ", 5) == 0)
2386 basetype
= REG_TYPE_VFD
;
2387 else if (strncmp (p
, " .qn ", 5) == 0)
2388 basetype
= REG_TYPE_NQ
;
2397 basereg
= arm_reg_parse_multi (&p
);
2399 if (basereg
&& basereg
->type
!= basetype
)
2401 as_bad (_("bad type for register"));
2405 if (basereg
== NULL
)
2408 /* Try parsing as an integer. */
2409 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2410 if (exp
.X_op
!= O_constant
)
2412 as_bad (_("expression must be constant"));
2415 basereg
= &mybasereg
;
2416 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2422 typeinfo
= *basereg
->neon
;
2424 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2426 /* We got a type. */
2427 if (typeinfo
.defined
& NTA_HASTYPE
)
2429 as_bad (_("can't redefine the type of a register alias"));
2433 typeinfo
.defined
|= NTA_HASTYPE
;
2434 if (ntype
.elems
!= 1)
2436 as_bad (_("you must specify a single type only"));
2439 typeinfo
.eltype
= ntype
.el
[0];
2442 if (skip_past_char (&p
, '[') == SUCCESS
)
2445 /* We got a scalar index. */
2447 if (typeinfo
.defined
& NTA_HASINDEX
)
2449 as_bad (_("can't redefine the index of a scalar alias"));
2453 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2455 if (exp
.X_op
!= O_constant
)
2457 as_bad (_("scalar index must be constant"));
2461 typeinfo
.defined
|= NTA_HASINDEX
;
2462 typeinfo
.index
= exp
.X_add_number
;
2464 if (skip_past_char (&p
, ']') == FAIL
)
2466 as_bad (_("expecting ]"));
2471 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2472 the desired alias name, and p points to its end. If not, then
2473 the desired alias name is in the global original_case_string. */
2474 #ifdef TC_CASE_SENSITIVE
2475 namelen
= nameend
- newname
;
2477 newname
= original_case_string
;
2478 namelen
= strlen (newname
);
2481 namebuf
= xmemdup0 (newname
, namelen
);
2483 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2484 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2486 /* Insert name in all uppercase. */
2487 for (p
= namebuf
; *p
; p
++)
2490 if (strncmp (namebuf
, newname
, namelen
))
2491 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2492 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2494 /* Insert name in all lowercase. */
2495 for (p
= namebuf
; *p
; p
++)
2498 if (strncmp (namebuf
, newname
, namelen
))
2499 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2500 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2506 /* Should never be called, as .req goes between the alias and the
2507 register name, not at the beginning of the line. */
2510 s_req (int a ATTRIBUTE_UNUSED
)
2512 as_bad (_("invalid syntax for .req directive"));
2516 s_dn (int a ATTRIBUTE_UNUSED
)
2518 as_bad (_("invalid syntax for .dn directive"));
2522 s_qn (int a ATTRIBUTE_UNUSED
)
2524 as_bad (_("invalid syntax for .qn directive"));
2527 /* The .unreq directive deletes an alias which was previously defined
2528 by .req. For example:
2534 s_unreq (int a ATTRIBUTE_UNUSED
)
2539 name
= input_line_pointer
;
2541 while (*input_line_pointer
!= 0
2542 && *input_line_pointer
!= ' '
2543 && *input_line_pointer
!= '\n')
2544 ++input_line_pointer
;
2546 saved_char
= *input_line_pointer
;
2547 *input_line_pointer
= 0;
2550 as_bad (_("invalid syntax for .unreq directive"));
2553 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2557 as_bad (_("unknown register alias '%s'"), name
);
2558 else if (reg
->builtin
)
2559 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2566 hash_delete (arm_reg_hsh
, name
, FALSE
);
2567 free ((char *) reg
->name
);
2572 /* Also locate the all upper case and all lower case versions.
2573 Do not complain if we cannot find one or the other as it
2574 was probably deleted above. */
2576 nbuf
= strdup (name
);
2577 for (p
= nbuf
; *p
; p
++)
2579 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2582 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2583 free ((char *) reg
->name
);
2589 for (p
= nbuf
; *p
; p
++)
2591 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2594 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2595 free ((char *) reg
->name
);
2605 *input_line_pointer
= saved_char
;
2606 demand_empty_rest_of_line ();
2609 /* Directives: Instruction set selection. */
2612 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2613 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2614 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2615 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2617 /* Create a new mapping symbol for the transition to STATE. */
2620 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2623 const char * symname
;
2630 type
= BSF_NO_FLAGS
;
2634 type
= BSF_NO_FLAGS
;
2638 type
= BSF_NO_FLAGS
;
2644 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2645 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2650 THUMB_SET_FUNC (symbolP
, 0);
2651 ARM_SET_THUMB (symbolP
, 0);
2652 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2656 THUMB_SET_FUNC (symbolP
, 1);
2657 ARM_SET_THUMB (symbolP
, 1);
2658 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2666 /* Save the mapping symbols for future reference. Also check that
2667 we do not place two mapping symbols at the same offset within a
2668 frag. We'll handle overlap between frags in
2669 check_mapping_symbols.
2671 If .fill or other data filling directive generates zero sized data,
2672 the mapping symbol for the following code will have the same value
2673 as the one generated for the data filling directive. In this case,
2674 we replace the old symbol with the new one at the same address. */
2677 if (frag
->tc_frag_data
.first_map
!= NULL
)
2679 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2680 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2682 frag
->tc_frag_data
.first_map
= symbolP
;
2684 if (frag
->tc_frag_data
.last_map
!= NULL
)
2686 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2687 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2688 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2690 frag
->tc_frag_data
.last_map
= symbolP
;
2693 /* We must sometimes convert a region marked as code to data during
2694 code alignment, if an odd number of bytes have to be padded. The
2695 code mapping symbol is pushed to an aligned address. */
2698 insert_data_mapping_symbol (enum mstate state
,
2699 valueT value
, fragS
*frag
, offsetT bytes
)
2701 /* If there was already a mapping symbol, remove it. */
2702 if (frag
->tc_frag_data
.last_map
!= NULL
2703 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2705 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2709 know (frag
->tc_frag_data
.first_map
== symp
);
2710 frag
->tc_frag_data
.first_map
= NULL
;
2712 frag
->tc_frag_data
.last_map
= NULL
;
2713 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2716 make_mapping_symbol (MAP_DATA
, value
, frag
);
2717 make_mapping_symbol (state
, value
+ bytes
, frag
);
2720 static void mapping_state_2 (enum mstate state
, int max_chars
);
2722 /* Set the mapping state to STATE. Only call this when about to
2723 emit some STATE bytes to the file. */
2725 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2727 mapping_state (enum mstate state
)
2729 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2731 if (mapstate
== state
)
2732 /* The mapping symbol has already been emitted.
2733 There is nothing else to do. */
2736 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2738 All ARM instructions require 4-byte alignment.
2739 (Almost) all Thumb instructions require 2-byte alignment.
2741 When emitting instructions into any section, mark the section
2744 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2745 but themselves require 2-byte alignment; this applies to some
2746 PC- relative forms. However, these cases will involve implicit
2747 literal pool generation or an explicit .align >=2, both of
2748 which will cause the section to me marked with sufficient
2749 alignment. Thus, we don't handle those cases here. */
2750 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2752 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2753 /* This case will be evaluated later. */
2756 mapping_state_2 (state
, 0);
2759 /* Same as mapping_state, but MAX_CHARS bytes have already been
2760 allocated. Put the mapping symbol that far back. */
2763 mapping_state_2 (enum mstate state
, int max_chars
)
2765 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2767 if (!SEG_NORMAL (now_seg
))
2770 if (mapstate
== state
)
2771 /* The mapping symbol has already been emitted.
2772 There is nothing else to do. */
2775 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2776 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2778 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2779 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2782 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2785 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2786 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2790 #define mapping_state(x) ((void)0)
2791 #define mapping_state_2(x, y) ((void)0)
2794 /* Find the real, Thumb encoded start of a Thumb function. */
2798 find_real_start (symbolS
* symbolP
)
2801 const char * name
= S_GET_NAME (symbolP
);
2802 symbolS
* new_target
;
2804 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2805 #define STUB_NAME ".real_start_of"
2810 /* The compiler may generate BL instructions to local labels because
2811 it needs to perform a branch to a far away location. These labels
2812 do not have a corresponding ".real_start_of" label. We check
2813 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2814 the ".real_start_of" convention for nonlocal branches. */
2815 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2818 real_start
= concat (STUB_NAME
, name
, NULL
);
2819 new_target
= symbol_find (real_start
);
2822 if (new_target
== NULL
)
2824 as_warn (_("Failed to find real start of function: %s\n"), name
);
2825 new_target
= symbolP
;
2833 opcode_select (int width
)
2840 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2841 as_bad (_("selected processor does not support THUMB opcodes"));
2844 /* No need to force the alignment, since we will have been
2845 coming from ARM mode, which is word-aligned. */
2846 record_alignment (now_seg
, 1);
2853 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2854 as_bad (_("selected processor does not support ARM opcodes"));
2859 frag_align (2, 0, 0);
2861 record_alignment (now_seg
, 1);
2866 as_bad (_("invalid instruction size selected (%d)"), width
);
2871 s_arm (int ignore ATTRIBUTE_UNUSED
)
2874 demand_empty_rest_of_line ();
2878 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2881 demand_empty_rest_of_line ();
2885 s_code (int unused ATTRIBUTE_UNUSED
)
2889 temp
= get_absolute_expression ();
2894 opcode_select (temp
);
2898 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2903 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2905 /* If we are not already in thumb mode go into it, EVEN if
2906 the target processor does not support thumb instructions.
2907 This is used by gcc/config/arm/lib1funcs.asm for example
2908 to compile interworking support functions even if the
2909 target processor should not support interworking. */
2913 record_alignment (now_seg
, 1);
2916 demand_empty_rest_of_line ();
2920 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2924 /* The following label is the name/address of the start of a Thumb function.
2925 We need to know this for the interworking support. */
2926 label_is_thumb_function_name
= TRUE
;
2929 /* Perform a .set directive, but also mark the alias as
2930 being a thumb function. */
2933 s_thumb_set (int equiv
)
2935 /* XXX the following is a duplicate of the code for s_set() in read.c
2936 We cannot just call that code as we need to get at the symbol that
2943 /* Especial apologies for the random logic:
2944 This just grew, and could be parsed much more simply!
2946 delim
= get_symbol_name (& name
);
2947 end_name
= input_line_pointer
;
2948 (void) restore_line_pointer (delim
);
2950 if (*input_line_pointer
!= ',')
2953 as_bad (_("expected comma after name \"%s\""), name
);
2955 ignore_rest_of_line ();
2959 input_line_pointer
++;
2962 if (name
[0] == '.' && name
[1] == '\0')
2964 /* XXX - this should not happen to .thumb_set. */
2968 if ((symbolP
= symbol_find (name
)) == NULL
2969 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2972 /* When doing symbol listings, play games with dummy fragments living
2973 outside the normal fragment chain to record the file and line info
2975 if (listing
& LISTING_SYMBOLS
)
2977 extern struct list_info_struct
* listing_tail
;
2978 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2980 memset (dummy_frag
, 0, sizeof (fragS
));
2981 dummy_frag
->fr_type
= rs_fill
;
2982 dummy_frag
->line
= listing_tail
;
2983 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2984 dummy_frag
->fr_symbol
= symbolP
;
2988 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2991 /* "set" symbols are local unless otherwise specified. */
2992 SF_SET_LOCAL (symbolP
);
2993 #endif /* OBJ_COFF */
2994 } /* Make a new symbol. */
2996 symbol_table_insert (symbolP
);
3001 && S_IS_DEFINED (symbolP
)
3002 && S_GET_SEGMENT (symbolP
) != reg_section
)
3003 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3005 pseudo_set (symbolP
);
3007 demand_empty_rest_of_line ();
3009 /* XXX Now we come to the Thumb specific bit of code. */
3011 THUMB_SET_FUNC (symbolP
, 1);
3012 ARM_SET_THUMB (symbolP
, 1);
3013 #if defined OBJ_ELF || defined OBJ_COFF
3014 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3018 /* Directives: Mode selection. */
3020 /* .syntax [unified|divided] - choose the new unified syntax
3021 (same for Arm and Thumb encoding, modulo slight differences in what
3022 can be represented) or the old divergent syntax for each mode. */
3024 s_syntax (int unused ATTRIBUTE_UNUSED
)
3028 delim
= get_symbol_name (& name
);
3030 if (!strcasecmp (name
, "unified"))
3031 unified_syntax
= TRUE
;
3032 else if (!strcasecmp (name
, "divided"))
3033 unified_syntax
= FALSE
;
3036 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3039 (void) restore_line_pointer (delim
);
3040 demand_empty_rest_of_line ();
3043 /* Directives: sectioning and alignment. */
3046 s_bss (int ignore ATTRIBUTE_UNUSED
)
3048 /* We don't support putting frags in the BSS segment, we fake it by
3049 marking in_bss, then looking at s_skip for clues. */
3050 subseg_set (bss_section
, 0);
3051 demand_empty_rest_of_line ();
3053 #ifdef md_elf_section_change_hook
3054 md_elf_section_change_hook ();
3059 s_even (int ignore ATTRIBUTE_UNUSED
)
3061 /* Never make frag if expect extra pass. */
3063 frag_align (1, 0, 0);
3065 record_alignment (now_seg
, 1);
3067 demand_empty_rest_of_line ();
3070 /* Directives: CodeComposer Studio. */
3072 /* .ref (for CodeComposer Studio syntax only). */
3074 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3076 if (codecomposer_syntax
)
3077 ignore_rest_of_line ();
3079 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3082 /* If name is not NULL, then it is used for marking the beginning of a
3083 function, whereas if it is NULL then it means the function end. */
3085 asmfunc_debug (const char * name
)
3087 static const char * last_name
= NULL
;
3091 gas_assert (last_name
== NULL
);
3094 if (debug_type
== DEBUG_STABS
)
3095 stabs_generate_asm_func (name
, name
);
3099 gas_assert (last_name
!= NULL
);
3101 if (debug_type
== DEBUG_STABS
)
3102 stabs_generate_asm_endfunc (last_name
, last_name
);
3109 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3111 if (codecomposer_syntax
)
3113 switch (asmfunc_state
)
3115 case OUTSIDE_ASMFUNC
:
3116 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3119 case WAITING_ASMFUNC_NAME
:
3120 as_bad (_(".asmfunc repeated."));
3123 case WAITING_ENDASMFUNC
:
3124 as_bad (_(".asmfunc without function."));
3127 demand_empty_rest_of_line ();
3130 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3134 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3136 if (codecomposer_syntax
)
3138 switch (asmfunc_state
)
3140 case OUTSIDE_ASMFUNC
:
3141 as_bad (_(".endasmfunc without a .asmfunc."));
3144 case WAITING_ASMFUNC_NAME
:
3145 as_bad (_(".endasmfunc without function."));
3148 case WAITING_ENDASMFUNC
:
3149 asmfunc_state
= OUTSIDE_ASMFUNC
;
3150 asmfunc_debug (NULL
);
3153 demand_empty_rest_of_line ();
3156 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3160 s_ccs_def (int name
)
3162 if (codecomposer_syntax
)
3165 as_bad (_(".def pseudo-op only available with -mccs flag."));
3168 /* Directives: Literal pools. */
3170 static literal_pool
*
3171 find_literal_pool (void)
3173 literal_pool
* pool
;
3175 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3177 if (pool
->section
== now_seg
3178 && pool
->sub_section
== now_subseg
)
3185 static literal_pool
*
3186 find_or_make_literal_pool (void)
3188 /* Next literal pool ID number. */
3189 static unsigned int latest_pool_num
= 1;
3190 literal_pool
* pool
;
3192 pool
= find_literal_pool ();
3196 /* Create a new pool. */
3197 pool
= XNEW (literal_pool
);
3201 pool
->next_free_entry
= 0;
3202 pool
->section
= now_seg
;
3203 pool
->sub_section
= now_subseg
;
3204 pool
->next
= list_of_pools
;
3205 pool
->symbol
= NULL
;
3206 pool
->alignment
= 2;
3208 /* Add it to the list. */
3209 list_of_pools
= pool
;
3212 /* New pools, and emptied pools, will have a NULL symbol. */
3213 if (pool
->symbol
== NULL
)
3215 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3216 (valueT
) 0, &zero_address_frag
);
3217 pool
->id
= latest_pool_num
++;
3224 /* Add the literal in the global 'inst'
3225 structure to the relevant literal pool. */
3228 add_to_lit_pool (unsigned int nbytes
)
3230 #define PADDING_SLOT 0x1
3231 #define LIT_ENTRY_SIZE_MASK 0xFF
3232 literal_pool
* pool
;
3233 unsigned int entry
, pool_size
= 0;
3234 bfd_boolean padding_slot_p
= FALSE
;
3240 imm1
= inst
.operands
[1].imm
;
3241 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3242 : inst
.reloc
.exp
.X_unsigned
? 0
3243 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3244 if (target_big_endian
)
3247 imm2
= inst
.operands
[1].imm
;
3251 pool
= find_or_make_literal_pool ();
3253 /* Check if this literal value is already in the pool. */
3254 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3258 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3259 && (inst
.reloc
.exp
.X_op
== O_constant
)
3260 && (pool
->literals
[entry
].X_add_number
3261 == inst
.reloc
.exp
.X_add_number
)
3262 && (pool
->literals
[entry
].X_md
== nbytes
)
3263 && (pool
->literals
[entry
].X_unsigned
3264 == inst
.reloc
.exp
.X_unsigned
))
3267 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3268 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3269 && (pool
->literals
[entry
].X_add_number
3270 == inst
.reloc
.exp
.X_add_number
)
3271 && (pool
->literals
[entry
].X_add_symbol
3272 == inst
.reloc
.exp
.X_add_symbol
)
3273 && (pool
->literals
[entry
].X_op_symbol
3274 == inst
.reloc
.exp
.X_op_symbol
)
3275 && (pool
->literals
[entry
].X_md
== nbytes
))
3278 else if ((nbytes
== 8)
3279 && !(pool_size
& 0x7)
3280 && ((entry
+ 1) != pool
->next_free_entry
)
3281 && (pool
->literals
[entry
].X_op
== O_constant
)
3282 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3283 && (pool
->literals
[entry
].X_unsigned
3284 == inst
.reloc
.exp
.X_unsigned
)
3285 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3286 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3287 && (pool
->literals
[entry
+ 1].X_unsigned
3288 == inst
.reloc
.exp
.X_unsigned
))
3291 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3292 if (padding_slot_p
&& (nbytes
== 4))
3298 /* Do we need to create a new entry? */
3299 if (entry
== pool
->next_free_entry
)
3301 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3303 inst
.error
= _("literal pool overflow");
3309 /* For 8-byte entries, we align to an 8-byte boundary,
3310 and split it into two 4-byte entries, because on 32-bit
3311 host, 8-byte constants are treated as big num, thus
3312 saved in "generic_bignum" which will be overwritten
3313 by later assignments.
3315 We also need to make sure there is enough space for
3318 We also check to make sure the literal operand is a
3320 if (!(inst
.reloc
.exp
.X_op
== O_constant
3321 || inst
.reloc
.exp
.X_op
== O_big
))
3323 inst
.error
= _("invalid type for literal pool");
3326 else if (pool_size
& 0x7)
3328 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3330 inst
.error
= _("literal pool overflow");
3334 pool
->literals
[entry
] = inst
.reloc
.exp
;
3335 pool
->literals
[entry
].X_op
= O_constant
;
3336 pool
->literals
[entry
].X_add_number
= 0;
3337 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3338 pool
->next_free_entry
+= 1;
3341 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3343 inst
.error
= _("literal pool overflow");
3347 pool
->literals
[entry
] = inst
.reloc
.exp
;
3348 pool
->literals
[entry
].X_op
= O_constant
;
3349 pool
->literals
[entry
].X_add_number
= imm1
;
3350 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3351 pool
->literals
[entry
++].X_md
= 4;
3352 pool
->literals
[entry
] = inst
.reloc
.exp
;
3353 pool
->literals
[entry
].X_op
= O_constant
;
3354 pool
->literals
[entry
].X_add_number
= imm2
;
3355 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3356 pool
->literals
[entry
].X_md
= 4;
3357 pool
->alignment
= 3;
3358 pool
->next_free_entry
+= 1;
3362 pool
->literals
[entry
] = inst
.reloc
.exp
;
3363 pool
->literals
[entry
].X_md
= 4;
3367 /* PR ld/12974: Record the location of the first source line to reference
3368 this entry in the literal pool. If it turns out during linking that the
3369 symbol does not exist we will be able to give an accurate line number for
3370 the (first use of the) missing reference. */
3371 if (debug_type
== DEBUG_DWARF2
)
3372 dwarf2_where (pool
->locs
+ entry
);
3374 pool
->next_free_entry
+= 1;
3376 else if (padding_slot_p
)
3378 pool
->literals
[entry
] = inst
.reloc
.exp
;
3379 pool
->literals
[entry
].X_md
= nbytes
;
3382 inst
.reloc
.exp
.X_op
= O_symbol
;
3383 inst
.reloc
.exp
.X_add_number
= pool_size
;
3384 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3390 tc_start_label_without_colon (void)
3392 bfd_boolean ret
= TRUE
;
3394 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3396 const char *label
= input_line_pointer
;
3398 while (!is_end_of_line
[(int) label
[-1]])
3403 as_bad (_("Invalid label '%s'"), label
);
3407 asmfunc_debug (label
);
3409 asmfunc_state
= WAITING_ENDASMFUNC
;
3415 /* Can't use symbol_new here, so have to create a symbol and then at
3416 a later date assign it a value. That's what these functions do. */
3419 symbol_locate (symbolS
* symbolP
,
3420 const char * name
, /* It is copied, the caller can modify. */
3421 segT segment
, /* Segment identifier (SEG_<something>). */
3422 valueT valu
, /* Symbol value. */
3423 fragS
* frag
) /* Associated fragment. */
3426 char * preserved_copy_of_name
;
3428 name_length
= strlen (name
) + 1; /* +1 for \0. */
3429 obstack_grow (¬es
, name
, name_length
);
3430 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3432 #ifdef tc_canonicalize_symbol_name
3433 preserved_copy_of_name
=
3434 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3437 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3439 S_SET_SEGMENT (symbolP
, segment
);
3440 S_SET_VALUE (symbolP
, valu
);
3441 symbol_clear_list_pointers (symbolP
);
3443 symbol_set_frag (symbolP
, frag
);
3445 /* Link to end of symbol chain. */
3447 extern int symbol_table_frozen
;
3449 if (symbol_table_frozen
)
3453 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3455 obj_symbol_new_hook (symbolP
);
3457 #ifdef tc_symbol_new_hook
3458 tc_symbol_new_hook (symbolP
);
3462 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3463 #endif /* DEBUG_SYMS */
3467 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3470 literal_pool
* pool
;
3473 pool
= find_literal_pool ();
3475 || pool
->symbol
== NULL
3476 || pool
->next_free_entry
== 0)
3479 /* Align pool as you have word accesses.
3480 Only make a frag if we have to. */
3482 frag_align (pool
->alignment
, 0, 0);
3484 record_alignment (now_seg
, 2);
3487 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3488 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3490 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3492 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3493 (valueT
) frag_now_fix (), frag_now
);
3494 symbol_table_insert (pool
->symbol
);
3496 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3498 #if defined OBJ_COFF || defined OBJ_ELF
3499 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3502 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3505 if (debug_type
== DEBUG_DWARF2
)
3506 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3508 /* First output the expression in the instruction to the pool. */
3509 emit_expr (&(pool
->literals
[entry
]),
3510 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3513 /* Mark the pool as empty. */
3514 pool
->next_free_entry
= 0;
3515 pool
->symbol
= NULL
;
3519 /* Forward declarations for functions below, in the MD interface
3521 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3522 static valueT
create_unwind_entry (int);
3523 static void start_unwind_section (const segT
, int);
3524 static void add_unwind_opcode (valueT
, int);
3525 static void flush_pending_unwind (void);
3527 /* Directives: Data. */
3530 s_arm_elf_cons (int nbytes
)
3534 #ifdef md_flush_pending_output
3535 md_flush_pending_output ();
3538 if (is_it_end_of_statement ())
3540 demand_empty_rest_of_line ();
3544 #ifdef md_cons_align
3545 md_cons_align (nbytes
);
3548 mapping_state (MAP_DATA
);
3552 char *base
= input_line_pointer
;
3556 if (exp
.X_op
!= O_symbol
)
3557 emit_expr (&exp
, (unsigned int) nbytes
);
3560 char *before_reloc
= input_line_pointer
;
3561 reloc
= parse_reloc (&input_line_pointer
);
3564 as_bad (_("unrecognized relocation suffix"));
3565 ignore_rest_of_line ();
3568 else if (reloc
== BFD_RELOC_UNUSED
)
3569 emit_expr (&exp
, (unsigned int) nbytes
);
3572 reloc_howto_type
*howto
= (reloc_howto_type
*)
3573 bfd_reloc_type_lookup (stdoutput
,
3574 (bfd_reloc_code_real_type
) reloc
);
3575 int size
= bfd_get_reloc_size (howto
);
3577 if (reloc
== BFD_RELOC_ARM_PLT32
)
3579 as_bad (_("(plt) is only valid on branch targets"));
3580 reloc
= BFD_RELOC_UNUSED
;
3585 as_bad (ngettext ("%s relocations do not fit in %d byte",
3586 "%s relocations do not fit in %d bytes",
3588 howto
->name
, nbytes
);
3591 /* We've parsed an expression stopping at O_symbol.
3592 But there may be more expression left now that we
3593 have parsed the relocation marker. Parse it again.
3594 XXX Surely there is a cleaner way to do this. */
3595 char *p
= input_line_pointer
;
3597 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3599 memcpy (save_buf
, base
, input_line_pointer
- base
);
3600 memmove (base
+ (input_line_pointer
- before_reloc
),
3601 base
, before_reloc
- base
);
3603 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3605 memcpy (base
, save_buf
, p
- base
);
3607 offset
= nbytes
- size
;
3608 p
= frag_more (nbytes
);
3609 memset (p
, 0, nbytes
);
3610 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3611 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3617 while (*input_line_pointer
++ == ',');
3619 /* Put terminator back into stream. */
3620 input_line_pointer
--;
3621 demand_empty_rest_of_line ();
3624 /* Emit an expression containing a 32-bit thumb instruction.
3625 Implementation based on put_thumb32_insn. */
3628 emit_thumb32_expr (expressionS
* exp
)
3630 expressionS exp_high
= *exp
;
3632 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3633 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3634 exp
->X_add_number
&= 0xffff;
3635 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3638 /* Guess the instruction size based on the opcode. */
3641 thumb_insn_size (int opcode
)
3643 if ((unsigned int) opcode
< 0xe800u
)
3645 else if ((unsigned int) opcode
>= 0xe8000000u
)
3652 emit_insn (expressionS
*exp
, int nbytes
)
3656 if (exp
->X_op
== O_constant
)
3661 size
= thumb_insn_size (exp
->X_add_number
);
3665 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3667 as_bad (_(".inst.n operand too big. "\
3668 "Use .inst.w instead"));
3673 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3674 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3676 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3678 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3679 emit_thumb32_expr (exp
);
3681 emit_expr (exp
, (unsigned int) size
);
3683 it_fsm_post_encode ();
3687 as_bad (_("cannot determine Thumb instruction size. " \
3688 "Use .inst.n/.inst.w instead"));
3691 as_bad (_("constant expression required"));
3696 /* Like s_arm_elf_cons but do not use md_cons_align and
3697 set the mapping state to MAP_ARM/MAP_THUMB. */
3700 s_arm_elf_inst (int nbytes
)
3702 if (is_it_end_of_statement ())
3704 demand_empty_rest_of_line ();
3708 /* Calling mapping_state () here will not change ARM/THUMB,
3709 but will ensure not to be in DATA state. */
3712 mapping_state (MAP_THUMB
);
3717 as_bad (_("width suffixes are invalid in ARM mode"));
3718 ignore_rest_of_line ();
3724 mapping_state (MAP_ARM
);
3733 if (! emit_insn (& exp
, nbytes
))
3735 ignore_rest_of_line ();
3739 while (*input_line_pointer
++ == ',');
3741 /* Put terminator back into stream. */
3742 input_line_pointer
--;
3743 demand_empty_rest_of_line ();
3746 /* Parse a .rel31 directive. */
3749 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3756 if (*input_line_pointer
== '1')
3757 highbit
= 0x80000000;
3758 else if (*input_line_pointer
!= '0')
3759 as_bad (_("expected 0 or 1"));
3761 input_line_pointer
++;
3762 if (*input_line_pointer
!= ',')
3763 as_bad (_("missing comma"));
3764 input_line_pointer
++;
3766 #ifdef md_flush_pending_output
3767 md_flush_pending_output ();
3770 #ifdef md_cons_align
3774 mapping_state (MAP_DATA
);
3779 md_number_to_chars (p
, highbit
, 4);
3780 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3781 BFD_RELOC_ARM_PREL31
);
3783 demand_empty_rest_of_line ();
3786 /* Directives: AEABI stack-unwind tables. */
3788 /* Parse an unwind_fnstart directive. Simply records the current location. */
3791 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3793 demand_empty_rest_of_line ();
3794 if (unwind
.proc_start
)
3796 as_bad (_("duplicate .fnstart directive"));
3800 /* Mark the start of the function. */
3801 unwind
.proc_start
= expr_build_dot ();
3803 /* Reset the rest of the unwind info. */
3804 unwind
.opcode_count
= 0;
3805 unwind
.table_entry
= NULL
;
3806 unwind
.personality_routine
= NULL
;
3807 unwind
.personality_index
= -1;
3808 unwind
.frame_size
= 0;
3809 unwind
.fp_offset
= 0;
3810 unwind
.fp_reg
= REG_SP
;
3812 unwind
.sp_restored
= 0;
3816 /* Parse a handlerdata directive. Creates the exception handling table entry
3817 for the function. */
3820 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3822 demand_empty_rest_of_line ();
3823 if (!unwind
.proc_start
)
3824 as_bad (MISSING_FNSTART
);
3826 if (unwind
.table_entry
)
3827 as_bad (_("duplicate .handlerdata directive"));
3829 create_unwind_entry (1);
3832 /* Parse an unwind_fnend directive. Generates the index table entry. */
3835 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3840 unsigned int marked_pr_dependency
;
3842 demand_empty_rest_of_line ();
3844 if (!unwind
.proc_start
)
3846 as_bad (_(".fnend directive without .fnstart"));
3850 /* Add eh table entry. */
3851 if (unwind
.table_entry
== NULL
)
3852 val
= create_unwind_entry (0);
3856 /* Add index table entry. This is two words. */
3857 start_unwind_section (unwind
.saved_seg
, 1);
3858 frag_align (2, 0, 0);
3859 record_alignment (now_seg
, 2);
3861 ptr
= frag_more (8);
3863 where
= frag_now_fix () - 8;
3865 /* Self relative offset of the function start. */
3866 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3867 BFD_RELOC_ARM_PREL31
);
3869 /* Indicate dependency on EHABI-defined personality routines to the
3870 linker, if it hasn't been done already. */
3871 marked_pr_dependency
3872 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3873 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3874 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3876 static const char *const name
[] =
3878 "__aeabi_unwind_cpp_pr0",
3879 "__aeabi_unwind_cpp_pr1",
3880 "__aeabi_unwind_cpp_pr2"
3882 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3883 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3884 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3885 |= 1 << unwind
.personality_index
;
3889 /* Inline exception table entry. */
3890 md_number_to_chars (ptr
+ 4, val
, 4);
3892 /* Self relative offset of the table entry. */
3893 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3894 BFD_RELOC_ARM_PREL31
);
3896 /* Restore the original section. */
3897 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3899 unwind
.proc_start
= NULL
;
3903 /* Parse an unwind_cantunwind directive. */
3906 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3908 demand_empty_rest_of_line ();
3909 if (!unwind
.proc_start
)
3910 as_bad (MISSING_FNSTART
);
3912 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3913 as_bad (_("personality routine specified for cantunwind frame"));
3915 unwind
.personality_index
= -2;
3919 /* Parse a personalityindex directive. */
3922 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3926 if (!unwind
.proc_start
)
3927 as_bad (MISSING_FNSTART
);
3929 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3930 as_bad (_("duplicate .personalityindex directive"));
3934 if (exp
.X_op
!= O_constant
3935 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3937 as_bad (_("bad personality routine number"));
3938 ignore_rest_of_line ();
3942 unwind
.personality_index
= exp
.X_add_number
;
3944 demand_empty_rest_of_line ();
3948 /* Parse a personality directive. */
3951 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3955 if (!unwind
.proc_start
)
3956 as_bad (MISSING_FNSTART
);
3958 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3959 as_bad (_("duplicate .personality directive"));
3961 c
= get_symbol_name (& name
);
3962 p
= input_line_pointer
;
3964 ++ input_line_pointer
;
3965 unwind
.personality_routine
= symbol_find_or_make (name
);
3967 demand_empty_rest_of_line ();
3971 /* Parse a directive saving core registers. */
3974 s_arm_unwind_save_core (void)
3980 range
= parse_reg_list (&input_line_pointer
);
3983 as_bad (_("expected register list"));
3984 ignore_rest_of_line ();
3988 demand_empty_rest_of_line ();
3990 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3991 into .unwind_save {..., sp...}. We aren't bothered about the value of
3992 ip because it is clobbered by calls. */
3993 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3994 && (range
& 0x3000) == 0x1000)
3996 unwind
.opcode_count
--;
3997 unwind
.sp_restored
= 0;
3998 range
= (range
| 0x2000) & ~0x1000;
3999 unwind
.pending_offset
= 0;
4005 /* See if we can use the short opcodes. These pop a block of up to 8
4006 registers starting with r4, plus maybe r14. */
4007 for (n
= 0; n
< 8; n
++)
4009 /* Break at the first non-saved register. */
4010 if ((range
& (1 << (n
+ 4))) == 0)
4013 /* See if there are any other bits set. */
4014 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4016 /* Use the long form. */
4017 op
= 0x8000 | ((range
>> 4) & 0xfff);
4018 add_unwind_opcode (op
, 2);
4022 /* Use the short form. */
4024 op
= 0xa8; /* Pop r14. */
4026 op
= 0xa0; /* Do not pop r14. */
4028 add_unwind_opcode (op
, 1);
4035 op
= 0xb100 | (range
& 0xf);
4036 add_unwind_opcode (op
, 2);
4039 /* Record the number of bytes pushed. */
4040 for (n
= 0; n
< 16; n
++)
4042 if (range
& (1 << n
))
4043 unwind
.frame_size
+= 4;
4048 /* Parse a directive saving FPA registers. */
4051 s_arm_unwind_save_fpa (int reg
)
4057 /* Get Number of registers to transfer. */
4058 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4061 exp
.X_op
= O_illegal
;
4063 if (exp
.X_op
!= O_constant
)
4065 as_bad (_("expected , <constant>"));
4066 ignore_rest_of_line ();
4070 num_regs
= exp
.X_add_number
;
4072 if (num_regs
< 1 || num_regs
> 4)
4074 as_bad (_("number of registers must be in the range [1:4]"));
4075 ignore_rest_of_line ();
4079 demand_empty_rest_of_line ();
4084 op
= 0xb4 | (num_regs
- 1);
4085 add_unwind_opcode (op
, 1);
4090 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4091 add_unwind_opcode (op
, 2);
4093 unwind
.frame_size
+= num_regs
* 12;
4097 /* Parse a directive saving VFP registers for ARMv6 and above. */
4100 s_arm_unwind_save_vfp_armv6 (void)
4105 int num_vfpv3_regs
= 0;
4106 int num_regs_below_16
;
4108 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4111 as_bad (_("expected register list"));
4112 ignore_rest_of_line ();
4116 demand_empty_rest_of_line ();
4118 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4119 than FSTMX/FLDMX-style ones). */
4121 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4123 num_vfpv3_regs
= count
;
4124 else if (start
+ count
> 16)
4125 num_vfpv3_regs
= start
+ count
- 16;
4127 if (num_vfpv3_regs
> 0)
4129 int start_offset
= start
> 16 ? start
- 16 : 0;
4130 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4131 add_unwind_opcode (op
, 2);
4134 /* Generate opcode for registers numbered in the range 0 .. 15. */
4135 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4136 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4137 if (num_regs_below_16
> 0)
4139 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4140 add_unwind_opcode (op
, 2);
4143 unwind
.frame_size
+= count
* 8;
4147 /* Parse a directive saving VFP registers for pre-ARMv6. */
4150 s_arm_unwind_save_vfp (void)
4156 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4159 as_bad (_("expected register list"));
4160 ignore_rest_of_line ();
4164 demand_empty_rest_of_line ();
4169 op
= 0xb8 | (count
- 1);
4170 add_unwind_opcode (op
, 1);
4175 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4176 add_unwind_opcode (op
, 2);
4178 unwind
.frame_size
+= count
* 8 + 4;
4182 /* Parse a directive saving iWMMXt data registers. */
4185 s_arm_unwind_save_mmxwr (void)
4193 if (*input_line_pointer
== '{')
4194 input_line_pointer
++;
4198 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4202 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4207 as_tsktsk (_("register list not in ascending order"));
4210 if (*input_line_pointer
== '-')
4212 input_line_pointer
++;
4213 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4216 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4219 else if (reg
>= hi_reg
)
4221 as_bad (_("bad register range"));
4224 for (; reg
< hi_reg
; reg
++)
4228 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4230 skip_past_char (&input_line_pointer
, '}');
4232 demand_empty_rest_of_line ();
4234 /* Generate any deferred opcodes because we're going to be looking at
4236 flush_pending_unwind ();
4238 for (i
= 0; i
< 16; i
++)
4240 if (mask
& (1 << i
))
4241 unwind
.frame_size
+= 8;
4244 /* Attempt to combine with a previous opcode. We do this because gcc
4245 likes to output separate unwind directives for a single block of
4247 if (unwind
.opcode_count
> 0)
4249 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4250 if ((i
& 0xf8) == 0xc0)
4253 /* Only merge if the blocks are contiguous. */
4256 if ((mask
& 0xfe00) == (1 << 9))
4258 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4259 unwind
.opcode_count
--;
4262 else if (i
== 6 && unwind
.opcode_count
>= 2)
4264 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4268 op
= 0xffff << (reg
- 1);
4270 && ((mask
& op
) == (1u << (reg
- 1))))
4272 op
= (1 << (reg
+ i
+ 1)) - 1;
4273 op
&= ~((1 << reg
) - 1);
4275 unwind
.opcode_count
-= 2;
4282 /* We want to generate opcodes in the order the registers have been
4283 saved, ie. descending order. */
4284 for (reg
= 15; reg
>= -1; reg
--)
4286 /* Save registers in blocks. */
4288 || !(mask
& (1 << reg
)))
4290 /* We found an unsaved reg. Generate opcodes to save the
4297 op
= 0xc0 | (hi_reg
- 10);
4298 add_unwind_opcode (op
, 1);
4303 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4304 add_unwind_opcode (op
, 2);
4313 ignore_rest_of_line ();
4317 s_arm_unwind_save_mmxwcg (void)
4324 if (*input_line_pointer
== '{')
4325 input_line_pointer
++;
4327 skip_whitespace (input_line_pointer
);
4331 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4335 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4341 as_tsktsk (_("register list not in ascending order"));
4344 if (*input_line_pointer
== '-')
4346 input_line_pointer
++;
4347 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4350 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4353 else if (reg
>= hi_reg
)
4355 as_bad (_("bad register range"));
4358 for (; reg
< hi_reg
; reg
++)
4362 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4364 skip_past_char (&input_line_pointer
, '}');
4366 demand_empty_rest_of_line ();
4368 /* Generate any deferred opcodes because we're going to be looking at
4370 flush_pending_unwind ();
4372 for (reg
= 0; reg
< 16; reg
++)
4374 if (mask
& (1 << reg
))
4375 unwind
.frame_size
+= 4;
4378 add_unwind_opcode (op
, 2);
4381 ignore_rest_of_line ();
4385 /* Parse an unwind_save directive.
4386 If the argument is non-zero, this is a .vsave directive. */
4389 s_arm_unwind_save (int arch_v6
)
4392 struct reg_entry
*reg
;
4393 bfd_boolean had_brace
= FALSE
;
4395 if (!unwind
.proc_start
)
4396 as_bad (MISSING_FNSTART
);
4398 /* Figure out what sort of save we have. */
4399 peek
= input_line_pointer
;
4407 reg
= arm_reg_parse_multi (&peek
);
4411 as_bad (_("register expected"));
4412 ignore_rest_of_line ();
4421 as_bad (_("FPA .unwind_save does not take a register list"));
4422 ignore_rest_of_line ();
4425 input_line_pointer
= peek
;
4426 s_arm_unwind_save_fpa (reg
->number
);
4430 s_arm_unwind_save_core ();
4435 s_arm_unwind_save_vfp_armv6 ();
4437 s_arm_unwind_save_vfp ();
4440 case REG_TYPE_MMXWR
:
4441 s_arm_unwind_save_mmxwr ();
4444 case REG_TYPE_MMXWCG
:
4445 s_arm_unwind_save_mmxwcg ();
4449 as_bad (_(".unwind_save does not support this kind of register"));
4450 ignore_rest_of_line ();
4455 /* Parse an unwind_movsp directive. */
4458 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4464 if (!unwind
.proc_start
)
4465 as_bad (MISSING_FNSTART
);
4467 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4470 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4471 ignore_rest_of_line ();
4475 /* Optional constant. */
4476 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4478 if (immediate_for_directive (&offset
) == FAIL
)
4484 demand_empty_rest_of_line ();
4486 if (reg
== REG_SP
|| reg
== REG_PC
)
4488 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4492 if (unwind
.fp_reg
!= REG_SP
)
4493 as_bad (_("unexpected .unwind_movsp directive"));
4495 /* Generate opcode to restore the value. */
4497 add_unwind_opcode (op
, 1);
4499 /* Record the information for later. */
4500 unwind
.fp_reg
= reg
;
4501 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4502 unwind
.sp_restored
= 1;
4505 /* Parse an unwind_pad directive. */
4508 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4512 if (!unwind
.proc_start
)
4513 as_bad (MISSING_FNSTART
);
4515 if (immediate_for_directive (&offset
) == FAIL
)
4520 as_bad (_("stack increment must be multiple of 4"));
4521 ignore_rest_of_line ();
4525 /* Don't generate any opcodes, just record the details for later. */
4526 unwind
.frame_size
+= offset
;
4527 unwind
.pending_offset
+= offset
;
4529 demand_empty_rest_of_line ();
4532 /* Parse an unwind_setfp directive. */
4535 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4541 if (!unwind
.proc_start
)
4542 as_bad (MISSING_FNSTART
);
4544 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4545 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4548 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4550 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4552 as_bad (_("expected <reg>, <reg>"));
4553 ignore_rest_of_line ();
4557 /* Optional constant. */
4558 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4560 if (immediate_for_directive (&offset
) == FAIL
)
4566 demand_empty_rest_of_line ();
4568 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4570 as_bad (_("register must be either sp or set by a previous"
4571 "unwind_movsp directive"));
4575 /* Don't generate any opcodes, just record the information for later. */
4576 unwind
.fp_reg
= fp_reg
;
4578 if (sp_reg
== REG_SP
)
4579 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4581 unwind
.fp_offset
-= offset
;
4584 /* Parse an unwind_raw directive. */
4587 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4590 /* This is an arbitrary limit. */
4591 unsigned char op
[16];
4594 if (!unwind
.proc_start
)
4595 as_bad (MISSING_FNSTART
);
4598 if (exp
.X_op
== O_constant
4599 && skip_past_comma (&input_line_pointer
) != FAIL
)
4601 unwind
.frame_size
+= exp
.X_add_number
;
4605 exp
.X_op
= O_illegal
;
4607 if (exp
.X_op
!= O_constant
)
4609 as_bad (_("expected <offset>, <opcode>"));
4610 ignore_rest_of_line ();
4616 /* Parse the opcode. */
4621 as_bad (_("unwind opcode too long"));
4622 ignore_rest_of_line ();
4624 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4626 as_bad (_("invalid unwind opcode"));
4627 ignore_rest_of_line ();
4630 op
[count
++] = exp
.X_add_number
;
4632 /* Parse the next byte. */
4633 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4639 /* Add the opcode bytes in reverse order. */
4641 add_unwind_opcode (op
[count
], 1);
4643 demand_empty_rest_of_line ();
4647 /* Parse a .eabi_attribute directive. */
4650 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4652 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4654 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4655 attributes_set_explicitly
[tag
] = 1;
4658 /* Emit a tls fix for the symbol. */
4661 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4665 #ifdef md_flush_pending_output
4666 md_flush_pending_output ();
4669 #ifdef md_cons_align
4673 /* Since we're just labelling the code, there's no need to define a
4676 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4677 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4678 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4679 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4681 #endif /* OBJ_ELF */
4683 static void s_arm_arch (int);
4684 static void s_arm_object_arch (int);
4685 static void s_arm_cpu (int);
4686 static void s_arm_fpu (int);
4687 static void s_arm_arch_extension (int);
4692 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4699 if (exp
.X_op
== O_symbol
)
4700 exp
.X_op
= O_secrel
;
4702 emit_expr (&exp
, 4);
4704 while (*input_line_pointer
++ == ',');
4706 input_line_pointer
--;
4707 demand_empty_rest_of_line ();
4711 /* This table describes all the machine specific pseudo-ops the assembler
4712 has to support. The fields are:
4713 pseudo-op name without dot
4714 function to call to execute this pseudo-op
4715 Integer arg to pass to the function. */
4717 const pseudo_typeS md_pseudo_table
[] =
4719 /* Never called because '.req' does not start a line. */
4720 { "req", s_req
, 0 },
4721 /* Following two are likewise never called. */
4724 { "unreq", s_unreq
, 0 },
4725 { "bss", s_bss
, 0 },
4726 { "align", s_align_ptwo
, 2 },
4727 { "arm", s_arm
, 0 },
4728 { "thumb", s_thumb
, 0 },
4729 { "code", s_code
, 0 },
4730 { "force_thumb", s_force_thumb
, 0 },
4731 { "thumb_func", s_thumb_func
, 0 },
4732 { "thumb_set", s_thumb_set
, 0 },
4733 { "even", s_even
, 0 },
4734 { "ltorg", s_ltorg
, 0 },
4735 { "pool", s_ltorg
, 0 },
4736 { "syntax", s_syntax
, 0 },
4737 { "cpu", s_arm_cpu
, 0 },
4738 { "arch", s_arm_arch
, 0 },
4739 { "object_arch", s_arm_object_arch
, 0 },
4740 { "fpu", s_arm_fpu
, 0 },
4741 { "arch_extension", s_arm_arch_extension
, 0 },
4743 { "word", s_arm_elf_cons
, 4 },
4744 { "long", s_arm_elf_cons
, 4 },
4745 { "inst.n", s_arm_elf_inst
, 2 },
4746 { "inst.w", s_arm_elf_inst
, 4 },
4747 { "inst", s_arm_elf_inst
, 0 },
4748 { "rel31", s_arm_rel31
, 0 },
4749 { "fnstart", s_arm_unwind_fnstart
, 0 },
4750 { "fnend", s_arm_unwind_fnend
, 0 },
4751 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4752 { "personality", s_arm_unwind_personality
, 0 },
4753 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4754 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4755 { "save", s_arm_unwind_save
, 0 },
4756 { "vsave", s_arm_unwind_save
, 1 },
4757 { "movsp", s_arm_unwind_movsp
, 0 },
4758 { "pad", s_arm_unwind_pad
, 0 },
4759 { "setfp", s_arm_unwind_setfp
, 0 },
4760 { "unwind_raw", s_arm_unwind_raw
, 0 },
4761 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4762 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4766 /* These are used for dwarf. */
4770 /* These are used for dwarf2. */
4771 { "file", dwarf2_directive_file
, 0 },
4772 { "loc", dwarf2_directive_loc
, 0 },
4773 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4775 { "extend", float_cons
, 'x' },
4776 { "ldouble", float_cons
, 'x' },
4777 { "packed", float_cons
, 'p' },
4779 {"secrel32", pe_directive_secrel
, 0},
4782 /* These are for compatibility with CodeComposer Studio. */
4783 {"ref", s_ccs_ref
, 0},
4784 {"def", s_ccs_def
, 0},
4785 {"asmfunc", s_ccs_asmfunc
, 0},
4786 {"endasmfunc", s_ccs_endasmfunc
, 0},
4791 /* Parser functions used exclusively in instruction operands. */
4793 /* Generic immediate-value read function for use in insn parsing.
4794 STR points to the beginning of the immediate (the leading #);
4795 VAL receives the value; if the value is outside [MIN, MAX]
4796 issue an error. PREFIX_OPT is true if the immediate prefix is
4800 parse_immediate (char **str
, int *val
, int min
, int max
,
4801 bfd_boolean prefix_opt
)
4805 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4806 if (exp
.X_op
!= O_constant
)
4808 inst
.error
= _("constant expression required");
4812 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4814 inst
.error
= _("immediate value out of range");
4818 *val
= exp
.X_add_number
;
4822 /* Less-generic immediate-value read function with the possibility of loading a
4823 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4824 instructions. Puts the result directly in inst.operands[i]. */
4827 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4828 bfd_boolean allow_symbol_p
)
4831 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4834 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4836 if (exp_p
->X_op
== O_constant
)
4838 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4839 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4840 O_constant. We have to be careful not to break compilation for
4841 32-bit X_add_number, though. */
4842 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4844 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4845 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4847 inst
.operands
[i
].regisimm
= 1;
4850 else if (exp_p
->X_op
== O_big
4851 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4853 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4855 /* Bignums have their least significant bits in
4856 generic_bignum[0]. Make sure we put 32 bits in imm and
4857 32 bits in reg, in a (hopefully) portable way. */
4858 gas_assert (parts
!= 0);
4860 /* Make sure that the number is not too big.
4861 PR 11972: Bignums can now be sign-extended to the
4862 size of a .octa so check that the out of range bits
4863 are all zero or all one. */
4864 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4866 LITTLENUM_TYPE m
= -1;
4868 if (generic_bignum
[parts
* 2] != 0
4869 && generic_bignum
[parts
* 2] != m
)
4872 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4873 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4877 inst
.operands
[i
].imm
= 0;
4878 for (j
= 0; j
< parts
; j
++, idx
++)
4879 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4880 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4881 inst
.operands
[i
].reg
= 0;
4882 for (j
= 0; j
< parts
; j
++, idx
++)
4883 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4884 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4885 inst
.operands
[i
].regisimm
= 1;
4887 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4895 /* Returns the pseudo-register number of an FPA immediate constant,
4896 or FAIL if there isn't a valid constant here. */
4899 parse_fpa_immediate (char ** str
)
4901 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4907 /* First try and match exact strings, this is to guarantee
4908 that some formats will work even for cross assembly. */
4910 for (i
= 0; fp_const
[i
]; i
++)
4912 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4916 *str
+= strlen (fp_const
[i
]);
4917 if (is_end_of_line
[(unsigned char) **str
])
4923 /* Just because we didn't get a match doesn't mean that the constant
4924 isn't valid, just that it is in a format that we don't
4925 automatically recognize. Try parsing it with the standard
4926 expression routines. */
4928 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4930 /* Look for a raw floating point number. */
4931 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4932 && is_end_of_line
[(unsigned char) *save_in
])
4934 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4936 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4938 if (words
[j
] != fp_values
[i
][j
])
4942 if (j
== MAX_LITTLENUMS
)
4950 /* Try and parse a more complex expression, this will probably fail
4951 unless the code uses a floating point prefix (eg "0f"). */
4952 save_in
= input_line_pointer
;
4953 input_line_pointer
= *str
;
4954 if (expression (&exp
) == absolute_section
4955 && exp
.X_op
== O_big
4956 && exp
.X_add_number
< 0)
4958 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4960 #define X_PRECISION 5
4961 #define E_PRECISION 15L
4962 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4964 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4966 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4968 if (words
[j
] != fp_values
[i
][j
])
4972 if (j
== MAX_LITTLENUMS
)
4974 *str
= input_line_pointer
;
4975 input_line_pointer
= save_in
;
4982 *str
= input_line_pointer
;
4983 input_line_pointer
= save_in
;
4984 inst
.error
= _("invalid FPA immediate expression");
4988 /* Returns 1 if a number has "quarter-precision" float format
4989 0baBbbbbbc defgh000 00000000 00000000. */
4992 is_quarter_float (unsigned imm
)
4994 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4995 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4999 /* Detect the presence of a floating point or integer zero constant,
5003 parse_ifimm_zero (char **in
)
5007 if (!is_immediate_prefix (**in
))
5009 /* In unified syntax, all prefixes are optional. */
5010 if (!unified_syntax
)
5016 /* Accept #0x0 as a synonym for #0. */
5017 if (strncmp (*in
, "0x", 2) == 0)
5020 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5025 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5026 &generic_floating_point_number
);
5029 && generic_floating_point_number
.sign
== '+'
5030 && (generic_floating_point_number
.low
5031 > generic_floating_point_number
.leader
))
5037 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5038 0baBbbbbbc defgh000 00000000 00000000.
5039 The zero and minus-zero cases need special handling, since they can't be
5040 encoded in the "quarter-precision" float format, but can nonetheless be
5041 loaded as integer constants. */
5044 parse_qfloat_immediate (char **ccp
, int *immed
)
5048 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5049 int found_fpchar
= 0;
5051 skip_past_char (&str
, '#');
5053 /* We must not accidentally parse an integer as a floating-point number. Make
5054 sure that the value we parse is not an integer by checking for special
5055 characters '.' or 'e'.
5056 FIXME: This is a horrible hack, but doing better is tricky because type
5057 information isn't in a very usable state at parse time. */
5059 skip_whitespace (fpnum
);
5061 if (strncmp (fpnum
, "0x", 2) == 0)
5065 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5066 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5076 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5078 unsigned fpword
= 0;
5081 /* Our FP word must be 32 bits (single-precision FP). */
5082 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5084 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5088 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5101 /* Shift operands. */
5104 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5107 struct asm_shift_name
5110 enum shift_kind kind
;
5113 /* Third argument to parse_shift. */
5114 enum parse_shift_mode
5116 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5117 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5118 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5119 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5120 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5123 /* Parse a <shift> specifier on an ARM data processing instruction.
5124 This has three forms:
5126 (LSL|LSR|ASL|ASR|ROR) Rs
5127 (LSL|LSR|ASL|ASR|ROR) #imm
5130 Note that ASL is assimilated to LSL in the instruction encoding, and
5131 RRX to ROR #0 (which cannot be written as such). */
5134 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5136 const struct asm_shift_name
*shift_name
;
5137 enum shift_kind shift
;
5142 for (p
= *str
; ISALPHA (*p
); p
++)
5147 inst
.error
= _("shift expression expected");
5151 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5154 if (shift_name
== NULL
)
5156 inst
.error
= _("shift expression expected");
5160 shift
= shift_name
->kind
;
5164 case NO_SHIFT_RESTRICT
:
5165 case SHIFT_IMMEDIATE
: break;
5167 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5168 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5170 inst
.error
= _("'LSL' or 'ASR' required");
5175 case SHIFT_LSL_IMMEDIATE
:
5176 if (shift
!= SHIFT_LSL
)
5178 inst
.error
= _("'LSL' required");
5183 case SHIFT_ASR_IMMEDIATE
:
5184 if (shift
!= SHIFT_ASR
)
5186 inst
.error
= _("'ASR' required");
5194 if (shift
!= SHIFT_RRX
)
5196 /* Whitespace can appear here if the next thing is a bare digit. */
5197 skip_whitespace (p
);
5199 if (mode
== NO_SHIFT_RESTRICT
5200 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5202 inst
.operands
[i
].imm
= reg
;
5203 inst
.operands
[i
].immisreg
= 1;
5205 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5208 inst
.operands
[i
].shift_kind
= shift
;
5209 inst
.operands
[i
].shifted
= 1;
5214 /* Parse a <shifter_operand> for an ARM data processing instruction:
5217 #<immediate>, <rotate>
5221 where <shift> is defined by parse_shift above, and <rotate> is a
5222 multiple of 2 between 0 and 30. Validation of immediate operands
5223 is deferred to md_apply_fix. */
5226 parse_shifter_operand (char **str
, int i
)
5231 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5233 inst
.operands
[i
].reg
= value
;
5234 inst
.operands
[i
].isreg
= 1;
5236 /* parse_shift will override this if appropriate */
5237 inst
.reloc
.exp
.X_op
= O_constant
;
5238 inst
.reloc
.exp
.X_add_number
= 0;
5240 if (skip_past_comma (str
) == FAIL
)
5243 /* Shift operation on register. */
5244 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5247 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5250 if (skip_past_comma (str
) == SUCCESS
)
5252 /* #x, y -- ie explicit rotation by Y. */
5253 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5256 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5258 inst
.error
= _("constant expression expected");
5262 value
= exp
.X_add_number
;
5263 if (value
< 0 || value
> 30 || value
% 2 != 0)
5265 inst
.error
= _("invalid rotation");
5268 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5270 inst
.error
= _("invalid constant");
5274 /* Encode as specified. */
5275 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5279 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5280 inst
.reloc
.pc_rel
= 0;
5284 /* Group relocation information. Each entry in the table contains the
5285 textual name of the relocation as may appear in assembler source
5286 and must end with a colon.
5287 Along with this textual name are the relocation codes to be used if
5288 the corresponding instruction is an ALU instruction (ADD or SUB only),
5289 an LDR, an LDRS, or an LDC. */
5291 struct group_reloc_table_entry
5302 /* Varieties of non-ALU group relocation. */
5309 static struct group_reloc_table_entry group_reloc_table
[] =
5310 { /* Program counter relative: */
5312 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5317 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5318 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5319 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5320 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5322 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5327 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5328 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5329 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5330 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5332 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5333 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5334 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5335 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5336 /* Section base relative */
5338 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5343 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5344 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5345 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5346 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5348 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5353 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5354 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5355 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5356 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5358 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5359 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5360 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5361 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5362 /* Absolute thumb alu relocations. */
5364 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5369 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5374 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5379 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5384 /* Given the address of a pointer pointing to the textual name of a group
5385 relocation as may appear in assembler source, attempt to find its details
5386 in group_reloc_table. The pointer will be updated to the character after
5387 the trailing colon. On failure, FAIL will be returned; SUCCESS
5388 otherwise. On success, *entry will be updated to point at the relevant
5389 group_reloc_table entry. */
5392 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5395 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5397 int length
= strlen (group_reloc_table
[i
].name
);
5399 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5400 && (*str
)[length
] == ':')
5402 *out
= &group_reloc_table
[i
];
5403 *str
+= (length
+ 1);
5411 /* Parse a <shifter_operand> for an ARM data processing instruction
5412 (as for parse_shifter_operand) where group relocations are allowed:
5415 #<immediate>, <rotate>
5416 #:<group_reloc>:<expression>
5420 where <group_reloc> is one of the strings defined in group_reloc_table.
5421 The hashes are optional.
5423 Everything else is as for parse_shifter_operand. */
5425 static parse_operand_result
5426 parse_shifter_operand_group_reloc (char **str
, int i
)
5428 /* Determine if we have the sequence of characters #: or just :
5429 coming next. If we do, then we check for a group relocation.
5430 If we don't, punt the whole lot to parse_shifter_operand. */
5432 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5433 || (*str
)[0] == ':')
5435 struct group_reloc_table_entry
*entry
;
5437 if ((*str
)[0] == '#')
5442 /* Try to parse a group relocation. Anything else is an error. */
5443 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5445 inst
.error
= _("unknown group relocation");
5446 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5449 /* We now have the group relocation table entry corresponding to
5450 the name in the assembler source. Next, we parse the expression. */
5451 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5452 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5454 /* Record the relocation type (always the ALU variant here). */
5455 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5456 gas_assert (inst
.reloc
.type
!= 0);
5458 return PARSE_OPERAND_SUCCESS
;
5461 return parse_shifter_operand (str
, i
) == SUCCESS
5462 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5464 /* Never reached. */
5467 /* Parse a Neon alignment expression. Information is written to
5468 inst.operands[i]. We assume the initial ':' has been skipped.
5470 align .imm = align << 8, .immisalign=1, .preind=0 */
5471 static parse_operand_result
5472 parse_neon_alignment (char **str
, int i
)
5477 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5479 if (exp
.X_op
!= O_constant
)
5481 inst
.error
= _("alignment must be constant");
5482 return PARSE_OPERAND_FAIL
;
5485 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5486 inst
.operands
[i
].immisalign
= 1;
5487 /* Alignments are not pre-indexes. */
5488 inst
.operands
[i
].preind
= 0;
5491 return PARSE_OPERAND_SUCCESS
;
5494 /* Parse all forms of an ARM address expression. Information is written
5495 to inst.operands[i] and/or inst.reloc.
5497 Preindexed addressing (.preind=1):
5499 [Rn, #offset] .reg=Rn .reloc.exp=offset
5500 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5501 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5502 .shift_kind=shift .reloc.exp=shift_imm
5504 These three may have a trailing ! which causes .writeback to be set also.
5506 Postindexed addressing (.postind=1, .writeback=1):
5508 [Rn], #offset .reg=Rn .reloc.exp=offset
5509 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5510 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5511 .shift_kind=shift .reloc.exp=shift_imm
5513 Unindexed addressing (.preind=0, .postind=0):
5515 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5519 [Rn]{!} shorthand for [Rn,#0]{!}
5520 =immediate .isreg=0 .reloc.exp=immediate
5521 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5523 It is the caller's responsibility to check for addressing modes not
5524 supported by the instruction, and to set inst.reloc.type. */
5526 static parse_operand_result
5527 parse_address_main (char **str
, int i
, int group_relocations
,
5528 group_reloc_type group_type
)
5533 if (skip_past_char (&p
, '[') == FAIL
)
5535 if (skip_past_char (&p
, '=') == FAIL
)
5537 /* Bare address - translate to PC-relative offset. */
5538 inst
.reloc
.pc_rel
= 1;
5539 inst
.operands
[i
].reg
= REG_PC
;
5540 inst
.operands
[i
].isreg
= 1;
5541 inst
.operands
[i
].preind
= 1;
5543 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5544 return PARSE_OPERAND_FAIL
;
5546 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5547 /*allow_symbol_p=*/TRUE
))
5548 return PARSE_OPERAND_FAIL
;
5551 return PARSE_OPERAND_SUCCESS
;
5554 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5555 skip_whitespace (p
);
5557 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5559 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5560 return PARSE_OPERAND_FAIL
;
5562 inst
.operands
[i
].reg
= reg
;
5563 inst
.operands
[i
].isreg
= 1;
5565 if (skip_past_comma (&p
) == SUCCESS
)
5567 inst
.operands
[i
].preind
= 1;
5570 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5572 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5574 inst
.operands
[i
].imm
= reg
;
5575 inst
.operands
[i
].immisreg
= 1;
5577 if (skip_past_comma (&p
) == SUCCESS
)
5578 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5579 return PARSE_OPERAND_FAIL
;
5581 else if (skip_past_char (&p
, ':') == SUCCESS
)
5583 /* FIXME: '@' should be used here, but it's filtered out by generic
5584 code before we get to see it here. This may be subject to
5586 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5588 if (result
!= PARSE_OPERAND_SUCCESS
)
5593 if (inst
.operands
[i
].negative
)
5595 inst
.operands
[i
].negative
= 0;
5599 if (group_relocations
5600 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5602 struct group_reloc_table_entry
*entry
;
5604 /* Skip over the #: or : sequence. */
5610 /* Try to parse a group relocation. Anything else is an
5612 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5614 inst
.error
= _("unknown group relocation");
5615 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5618 /* We now have the group relocation table entry corresponding to
5619 the name in the assembler source. Next, we parse the
5621 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5622 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5624 /* Record the relocation type. */
5628 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5632 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5636 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5643 if (inst
.reloc
.type
== 0)
5645 inst
.error
= _("this group relocation is not allowed on this instruction");
5646 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5653 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5654 return PARSE_OPERAND_FAIL
;
5655 /* If the offset is 0, find out if it's a +0 or -0. */
5656 if (inst
.reloc
.exp
.X_op
== O_constant
5657 && inst
.reloc
.exp
.X_add_number
== 0)
5659 skip_whitespace (q
);
5663 skip_whitespace (q
);
5666 inst
.operands
[i
].negative
= 1;
5671 else if (skip_past_char (&p
, ':') == SUCCESS
)
5673 /* FIXME: '@' should be used here, but it's filtered out by generic code
5674 before we get to see it here. This may be subject to change. */
5675 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5677 if (result
!= PARSE_OPERAND_SUCCESS
)
5681 if (skip_past_char (&p
, ']') == FAIL
)
5683 inst
.error
= _("']' expected");
5684 return PARSE_OPERAND_FAIL
;
5687 if (skip_past_char (&p
, '!') == SUCCESS
)
5688 inst
.operands
[i
].writeback
= 1;
5690 else if (skip_past_comma (&p
) == SUCCESS
)
5692 if (skip_past_char (&p
, '{') == SUCCESS
)
5694 /* [Rn], {expr} - unindexed, with option */
5695 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5696 0, 255, TRUE
) == FAIL
)
5697 return PARSE_OPERAND_FAIL
;
5699 if (skip_past_char (&p
, '}') == FAIL
)
5701 inst
.error
= _("'}' expected at end of 'option' field");
5702 return PARSE_OPERAND_FAIL
;
5704 if (inst
.operands
[i
].preind
)
5706 inst
.error
= _("cannot combine index with option");
5707 return PARSE_OPERAND_FAIL
;
5710 return PARSE_OPERAND_SUCCESS
;
5714 inst
.operands
[i
].postind
= 1;
5715 inst
.operands
[i
].writeback
= 1;
5717 if (inst
.operands
[i
].preind
)
5719 inst
.error
= _("cannot combine pre- and post-indexing");
5720 return PARSE_OPERAND_FAIL
;
5724 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5726 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5728 /* We might be using the immediate for alignment already. If we
5729 are, OR the register number into the low-order bits. */
5730 if (inst
.operands
[i
].immisalign
)
5731 inst
.operands
[i
].imm
|= reg
;
5733 inst
.operands
[i
].imm
= reg
;
5734 inst
.operands
[i
].immisreg
= 1;
5736 if (skip_past_comma (&p
) == SUCCESS
)
5737 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5738 return PARSE_OPERAND_FAIL
;
5744 if (inst
.operands
[i
].negative
)
5746 inst
.operands
[i
].negative
= 0;
5749 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5750 return PARSE_OPERAND_FAIL
;
5751 /* If the offset is 0, find out if it's a +0 or -0. */
5752 if (inst
.reloc
.exp
.X_op
== O_constant
5753 && inst
.reloc
.exp
.X_add_number
== 0)
5755 skip_whitespace (q
);
5759 skip_whitespace (q
);
5762 inst
.operands
[i
].negative
= 1;
5768 /* If at this point neither .preind nor .postind is set, we have a
5769 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5770 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5772 inst
.operands
[i
].preind
= 1;
5773 inst
.reloc
.exp
.X_op
= O_constant
;
5774 inst
.reloc
.exp
.X_add_number
= 0;
5777 return PARSE_OPERAND_SUCCESS
;
5781 parse_address (char **str
, int i
)
5783 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5787 static parse_operand_result
5788 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5790 return parse_address_main (str
, i
, 1, type
);
5793 /* Parse an operand for a MOVW or MOVT instruction. */
5795 parse_half (char **str
)
5800 skip_past_char (&p
, '#');
5801 if (strncasecmp (p
, ":lower16:", 9) == 0)
5802 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5803 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5804 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5806 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5809 skip_whitespace (p
);
5812 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5815 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5817 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5819 inst
.error
= _("constant expression expected");
5822 if (inst
.reloc
.exp
.X_add_number
< 0
5823 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5825 inst
.error
= _("immediate value out of range");
5833 /* Miscellaneous. */
5835 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5836 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5838 parse_psr (char **str
, bfd_boolean lhs
)
5841 unsigned long psr_field
;
5842 const struct asm_psr
*psr
;
5844 bfd_boolean is_apsr
= FALSE
;
5845 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5847 /* PR gas/12698: If the user has specified -march=all then m_profile will
5848 be TRUE, but we want to ignore it in this case as we are building for any
5849 CPU type, including non-m variants. */
5850 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5853 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5854 feature for ease of use and backwards compatibility. */
5856 if (strncasecmp (p
, "SPSR", 4) == 0)
5859 goto unsupported_psr
;
5861 psr_field
= SPSR_BIT
;
5863 else if (strncasecmp (p
, "CPSR", 4) == 0)
5866 goto unsupported_psr
;
5870 else if (strncasecmp (p
, "APSR", 4) == 0)
5872 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5873 and ARMv7-R architecture CPUs. */
5882 while (ISALNUM (*p
) || *p
== '_');
5884 if (strncasecmp (start
, "iapsr", 5) == 0
5885 || strncasecmp (start
, "eapsr", 5) == 0
5886 || strncasecmp (start
, "xpsr", 4) == 0
5887 || strncasecmp (start
, "psr", 3) == 0)
5888 p
= start
+ strcspn (start
, "rR") + 1;
5890 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5896 /* If APSR is being written, a bitfield may be specified. Note that
5897 APSR itself is handled above. */
5898 if (psr
->field
<= 3)
5900 psr_field
= psr
->field
;
5906 /* M-profile MSR instructions have the mask field set to "10", except
5907 *PSR variants which modify APSR, which may use a different mask (and
5908 have been handled already). Do that by setting the PSR_f field
5910 return psr
->field
| (lhs
? PSR_f
: 0);
5913 goto unsupported_psr
;
5919 /* A suffix follows. */
5925 while (ISALNUM (*p
) || *p
== '_');
5929 /* APSR uses a notation for bits, rather than fields. */
5930 unsigned int nzcvq_bits
= 0;
5931 unsigned int g_bit
= 0;
5934 for (bit
= start
; bit
!= p
; bit
++)
5936 switch (TOLOWER (*bit
))
5939 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5943 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5947 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5951 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5955 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5959 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5963 inst
.error
= _("unexpected bit specified after APSR");
5968 if (nzcvq_bits
== 0x1f)
5973 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5975 inst
.error
= _("selected processor does not "
5976 "support DSP extension");
5983 if ((nzcvq_bits
& 0x20) != 0
5984 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5985 || (g_bit
& 0x2) != 0)
5987 inst
.error
= _("bad bitmask specified after APSR");
5993 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5998 psr_field
|= psr
->field
;
6004 goto error
; /* Garbage after "[CS]PSR". */
6006 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6007 is deprecated, but allow it anyway. */
6011 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6014 else if (!m_profile
)
6015 /* These bits are never right for M-profile devices: don't set them
6016 (only code paths which read/write APSR reach here). */
6017 psr_field
|= (PSR_c
| PSR_f
);
6023 inst
.error
= _("selected processor does not support requested special "
6024 "purpose register");
6028 inst
.error
= _("flag for {c}psr instruction expected");
6032 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6033 value suitable for splatting into the AIF field of the instruction. */
6036 parse_cps_flags (char **str
)
6045 case '\0': case ',':
6048 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6049 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6050 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6053 inst
.error
= _("unrecognized CPS flag");
6058 if (saw_a_flag
== 0)
6060 inst
.error
= _("missing CPS flags");
6068 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6069 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6072 parse_endian_specifier (char **str
)
6077 if (strncasecmp (s
, "BE", 2))
6079 else if (strncasecmp (s
, "LE", 2))
6083 inst
.error
= _("valid endian specifiers are be or le");
6087 if (ISALNUM (s
[2]) || s
[2] == '_')
6089 inst
.error
= _("valid endian specifiers are be or le");
6094 return little_endian
;
6097 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6098 value suitable for poking into the rotate field of an sxt or sxta
6099 instruction, or FAIL on error. */
6102 parse_ror (char **str
)
6107 if (strncasecmp (s
, "ROR", 3) == 0)
6111 inst
.error
= _("missing rotation field after comma");
6115 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6120 case 0: *str
= s
; return 0x0;
6121 case 8: *str
= s
; return 0x1;
6122 case 16: *str
= s
; return 0x2;
6123 case 24: *str
= s
; return 0x3;
6126 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6131 /* Parse a conditional code (from conds[] below). The value returned is in the
6132 range 0 .. 14, or FAIL. */
6134 parse_cond (char **str
)
6137 const struct asm_cond
*c
;
6139 /* Condition codes are always 2 characters, so matching up to
6140 3 characters is sufficient. */
6145 while (ISALPHA (*q
) && n
< 3)
6147 cond
[n
] = TOLOWER (*q
);
6152 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6155 inst
.error
= _("condition required");
6163 /* Record a use of the given feature. */
6165 record_feature_use (const arm_feature_set
*feature
)
6168 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6170 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6173 /* If the given feature is currently allowed, mark it as used and return TRUE.
6174 Return FALSE otherwise. */
6176 mark_feature_used (const arm_feature_set
*feature
)
6178 /* Ensure the option is currently allowed. */
6179 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6182 /* Add the appropriate architecture feature for the barrier option used. */
6183 record_feature_use (feature
);
6188 /* Parse an option for a barrier instruction. Returns the encoding for the
6191 parse_barrier (char **str
)
6194 const struct asm_barrier_opt
*o
;
6197 while (ISALPHA (*q
))
6200 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6205 if (!mark_feature_used (&o
->arch
))
6212 /* Parse the operands of a table branch instruction. Similar to a memory
6215 parse_tb (char **str
)
6220 if (skip_past_char (&p
, '[') == FAIL
)
6222 inst
.error
= _("'[' expected");
6226 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6228 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6231 inst
.operands
[0].reg
= reg
;
6233 if (skip_past_comma (&p
) == FAIL
)
6235 inst
.error
= _("',' expected");
6239 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6241 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6244 inst
.operands
[0].imm
= reg
;
6246 if (skip_past_comma (&p
) == SUCCESS
)
6248 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6250 if (inst
.reloc
.exp
.X_add_number
!= 1)
6252 inst
.error
= _("invalid shift");
6255 inst
.operands
[0].shifted
= 1;
6258 if (skip_past_char (&p
, ']') == FAIL
)
6260 inst
.error
= _("']' expected");
6267 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6268 information on the types the operands can take and how they are encoded.
6269 Up to four operands may be read; this function handles setting the
6270 ".present" field for each read operand itself.
6271 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6272 else returns FAIL. */
6275 parse_neon_mov (char **str
, int *which_operand
)
6277 int i
= *which_operand
, val
;
6278 enum arm_reg_type rtype
;
6280 struct neon_type_el optype
;
6282 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6284 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6285 inst
.operands
[i
].reg
= val
;
6286 inst
.operands
[i
].isscalar
= 1;
6287 inst
.operands
[i
].vectype
= optype
;
6288 inst
.operands
[i
++].present
= 1;
6290 if (skip_past_comma (&ptr
) == FAIL
)
6293 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6296 inst
.operands
[i
].reg
= val
;
6297 inst
.operands
[i
].isreg
= 1;
6298 inst
.operands
[i
].present
= 1;
6300 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6303 /* Cases 0, 1, 2, 3, 5 (D only). */
6304 if (skip_past_comma (&ptr
) == FAIL
)
6307 inst
.operands
[i
].reg
= val
;
6308 inst
.operands
[i
].isreg
= 1;
6309 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6310 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6311 inst
.operands
[i
].isvec
= 1;
6312 inst
.operands
[i
].vectype
= optype
;
6313 inst
.operands
[i
++].present
= 1;
6315 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6317 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6318 Case 13: VMOV <Sd>, <Rm> */
6319 inst
.operands
[i
].reg
= val
;
6320 inst
.operands
[i
].isreg
= 1;
6321 inst
.operands
[i
].present
= 1;
6323 if (rtype
== REG_TYPE_NQ
)
6325 first_error (_("can't use Neon quad register here"));
6328 else if (rtype
!= REG_TYPE_VFS
)
6331 if (skip_past_comma (&ptr
) == FAIL
)
6333 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6335 inst
.operands
[i
].reg
= val
;
6336 inst
.operands
[i
].isreg
= 1;
6337 inst
.operands
[i
].present
= 1;
6340 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6343 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6344 Case 1: VMOV<c><q> <Dd>, <Dm>
6345 Case 8: VMOV.F32 <Sd>, <Sm>
6346 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6348 inst
.operands
[i
].reg
= val
;
6349 inst
.operands
[i
].isreg
= 1;
6350 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6351 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6352 inst
.operands
[i
].isvec
= 1;
6353 inst
.operands
[i
].vectype
= optype
;
6354 inst
.operands
[i
].present
= 1;
6356 if (skip_past_comma (&ptr
) == SUCCESS
)
6361 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6364 inst
.operands
[i
].reg
= val
;
6365 inst
.operands
[i
].isreg
= 1;
6366 inst
.operands
[i
++].present
= 1;
6368 if (skip_past_comma (&ptr
) == FAIL
)
6371 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6374 inst
.operands
[i
].reg
= val
;
6375 inst
.operands
[i
].isreg
= 1;
6376 inst
.operands
[i
].present
= 1;
6379 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6380 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6381 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6382 Case 10: VMOV.F32 <Sd>, #<imm>
6383 Case 11: VMOV.F64 <Dd>, #<imm> */
6384 inst
.operands
[i
].immisfloat
= 1;
6385 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6387 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6388 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6392 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6396 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6399 inst
.operands
[i
].reg
= val
;
6400 inst
.operands
[i
].isreg
= 1;
6401 inst
.operands
[i
++].present
= 1;
6403 if (skip_past_comma (&ptr
) == FAIL
)
6406 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6408 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6409 inst
.operands
[i
].reg
= val
;
6410 inst
.operands
[i
].isscalar
= 1;
6411 inst
.operands
[i
].present
= 1;
6412 inst
.operands
[i
].vectype
= optype
;
6414 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6416 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6417 inst
.operands
[i
].reg
= val
;
6418 inst
.operands
[i
].isreg
= 1;
6419 inst
.operands
[i
++].present
= 1;
6421 if (skip_past_comma (&ptr
) == FAIL
)
6424 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6427 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6431 inst
.operands
[i
].reg
= val
;
6432 inst
.operands
[i
].isreg
= 1;
6433 inst
.operands
[i
].isvec
= 1;
6434 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6435 inst
.operands
[i
].vectype
= optype
;
6436 inst
.operands
[i
].present
= 1;
6438 if (rtype
== REG_TYPE_VFS
)
6442 if (skip_past_comma (&ptr
) == FAIL
)
6444 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6447 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6450 inst
.operands
[i
].reg
= val
;
6451 inst
.operands
[i
].isreg
= 1;
6452 inst
.operands
[i
].isvec
= 1;
6453 inst
.operands
[i
].issingle
= 1;
6454 inst
.operands
[i
].vectype
= optype
;
6455 inst
.operands
[i
].present
= 1;
6458 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6462 inst
.operands
[i
].reg
= val
;
6463 inst
.operands
[i
].isreg
= 1;
6464 inst
.operands
[i
].isvec
= 1;
6465 inst
.operands
[i
].issingle
= 1;
6466 inst
.operands
[i
].vectype
= optype
;
6467 inst
.operands
[i
].present
= 1;
6472 first_error (_("parse error"));
6476 /* Successfully parsed the operands. Update args. */
6482 first_error (_("expected comma"));
6486 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6490 /* Use this macro when the operand constraints are different
6491 for ARM and THUMB (e.g. ldrd). */
6492 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6493 ((arm_operand) | ((thumb_operand) << 16))
6495 /* Matcher codes for parse_operands. */
6496 enum operand_parse_code
6498 OP_stop
, /* end of line */
6500 OP_RR
, /* ARM register */
6501 OP_RRnpc
, /* ARM register, not r15 */
6502 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6503 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6504 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6505 optional trailing ! */
6506 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6507 OP_RCP
, /* Coprocessor number */
6508 OP_RCN
, /* Coprocessor register */
6509 OP_RF
, /* FPA register */
6510 OP_RVS
, /* VFP single precision register */
6511 OP_RVD
, /* VFP double precision register (0..15) */
6512 OP_RND
, /* Neon double precision register (0..31) */
6513 OP_RNQ
, /* Neon quad precision register */
6514 OP_RVSD
, /* VFP single or double precision register */
6515 OP_RNSD
, /* Neon single or double precision register */
6516 OP_RNDQ
, /* Neon double or quad precision register */
6517 OP_RNSDQ
, /* Neon single, double or quad precision register */
6518 OP_RNSC
, /* Neon scalar D[X] */
6519 OP_RVC
, /* VFP control register */
6520 OP_RMF
, /* Maverick F register */
6521 OP_RMD
, /* Maverick D register */
6522 OP_RMFX
, /* Maverick FX register */
6523 OP_RMDX
, /* Maverick DX register */
6524 OP_RMAX
, /* Maverick AX register */
6525 OP_RMDS
, /* Maverick DSPSC register */
6526 OP_RIWR
, /* iWMMXt wR register */
6527 OP_RIWC
, /* iWMMXt wC register */
6528 OP_RIWG
, /* iWMMXt wCG register */
6529 OP_RXA
, /* XScale accumulator register */
6531 OP_REGLST
, /* ARM register list */
6532 OP_VRSLST
, /* VFP single-precision register list */
6533 OP_VRDLST
, /* VFP double-precision register list */
6534 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6535 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6536 OP_NSTRLST
, /* Neon element/structure list */
6538 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6539 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6540 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6541 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6542 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6543 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6544 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6545 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6546 OP_VMOV
, /* Neon VMOV operands. */
6547 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6548 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6549 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6551 OP_I0
, /* immediate zero */
6552 OP_I7
, /* immediate value 0 .. 7 */
6553 OP_I15
, /* 0 .. 15 */
6554 OP_I16
, /* 1 .. 16 */
6555 OP_I16z
, /* 0 .. 16 */
6556 OP_I31
, /* 0 .. 31 */
6557 OP_I31w
, /* 0 .. 31, optional trailing ! */
6558 OP_I32
, /* 1 .. 32 */
6559 OP_I32z
, /* 0 .. 32 */
6560 OP_I63
, /* 0 .. 63 */
6561 OP_I63s
, /* -64 .. 63 */
6562 OP_I64
, /* 1 .. 64 */
6563 OP_I64z
, /* 0 .. 64 */
6564 OP_I255
, /* 0 .. 255 */
6566 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6567 OP_I7b
, /* 0 .. 7 */
6568 OP_I15b
, /* 0 .. 15 */
6569 OP_I31b
, /* 0 .. 31 */
6571 OP_SH
, /* shifter operand */
6572 OP_SHG
, /* shifter operand with possible group relocation */
6573 OP_ADDR
, /* Memory address expression (any mode) */
6574 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6575 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6576 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6577 OP_EXP
, /* arbitrary expression */
6578 OP_EXPi
, /* same, with optional immediate prefix */
6579 OP_EXPr
, /* same, with optional relocation suffix */
6580 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6581 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6582 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6584 OP_CPSF
, /* CPS flags */
6585 OP_ENDI
, /* Endianness specifier */
6586 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6587 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6588 OP_COND
, /* conditional code */
6589 OP_TB
, /* Table branch. */
6591 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6593 OP_RRnpc_I0
, /* ARM register or literal 0 */
6594 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
6595 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6596 OP_RF_IF
, /* FPA register or immediate */
6597 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6598 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6600 /* Optional operands. */
6601 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6602 OP_oI31b
, /* 0 .. 31 */
6603 OP_oI32b
, /* 1 .. 32 */
6604 OP_oI32z
, /* 0 .. 32 */
6605 OP_oIffffb
, /* 0 .. 65535 */
6606 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6608 OP_oRR
, /* ARM register */
6609 OP_oRRnpc
, /* ARM register, not the PC */
6610 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6611 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6612 OP_oRND
, /* Optional Neon double precision register */
6613 OP_oRNQ
, /* Optional Neon quad precision register */
6614 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6615 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6616 OP_oSHll
, /* LSL immediate */
6617 OP_oSHar
, /* ASR immediate */
6618 OP_oSHllar
, /* LSL or ASR immediate */
6619 OP_oROR
, /* ROR 0/8/16/24 */
6620 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6622 /* Some pre-defined mixed (ARM/THUMB) operands. */
6623 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6624 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6625 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6627 OP_FIRST_OPTIONAL
= OP_oI7b
6630 /* Generic instruction operand parser. This does no encoding and no
6631 semantic validation; it merely squirrels values away in the inst
6632 structure. Returns SUCCESS or FAIL depending on whether the
6633 specified grammar matched. */
6635 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6637 unsigned const int *upat
= pattern
;
6638 char *backtrack_pos
= 0;
6639 const char *backtrack_error
= 0;
6640 int i
, val
= 0, backtrack_index
= 0;
6641 enum arm_reg_type rtype
;
6642 parse_operand_result result
;
6643 unsigned int op_parse_code
;
6645 #define po_char_or_fail(chr) \
6648 if (skip_past_char (&str, chr) == FAIL) \
6653 #define po_reg_or_fail(regtype) \
6656 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6657 & inst.operands[i].vectype); \
6660 first_error (_(reg_expected_msgs[regtype])); \
6663 inst.operands[i].reg = val; \
6664 inst.operands[i].isreg = 1; \
6665 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6666 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6667 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6668 || rtype == REG_TYPE_VFD \
6669 || rtype == REG_TYPE_NQ); \
6673 #define po_reg_or_goto(regtype, label) \
6676 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6677 & inst.operands[i].vectype); \
6681 inst.operands[i].reg = val; \
6682 inst.operands[i].isreg = 1; \
6683 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6684 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6685 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6686 || rtype == REG_TYPE_VFD \
6687 || rtype == REG_TYPE_NQ); \
6691 #define po_imm_or_fail(min, max, popt) \
6694 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6696 inst.operands[i].imm = val; \
6700 #define po_scalar_or_goto(elsz, label) \
6703 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6706 inst.operands[i].reg = val; \
6707 inst.operands[i].isscalar = 1; \
6711 #define po_misc_or_fail(expr) \
6719 #define po_misc_or_fail_no_backtrack(expr) \
6723 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6724 backtrack_pos = 0; \
6725 if (result != PARSE_OPERAND_SUCCESS) \
6730 #define po_barrier_or_imm(str) \
6733 val = parse_barrier (&str); \
6734 if (val == FAIL && ! ISALPHA (*str)) \
6737 /* ISB can only take SY as an option. */ \
6738 || ((inst.instruction & 0xf0) == 0x60 \
6741 inst.error = _("invalid barrier type"); \
6742 backtrack_pos = 0; \
6748 skip_whitespace (str
);
6750 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6752 op_parse_code
= upat
[i
];
6753 if (op_parse_code
>= 1<<16)
6754 op_parse_code
= thumb
? (op_parse_code
>> 16)
6755 : (op_parse_code
& ((1<<16)-1));
6757 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6759 /* Remember where we are in case we need to backtrack. */
6760 gas_assert (!backtrack_pos
);
6761 backtrack_pos
= str
;
6762 backtrack_error
= inst
.error
;
6763 backtrack_index
= i
;
6766 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6767 po_char_or_fail (',');
6769 switch (op_parse_code
)
6777 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6778 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6779 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6780 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6781 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6782 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6784 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6786 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6788 /* Also accept generic coprocessor regs for unknown registers. */
6790 po_reg_or_fail (REG_TYPE_CN
);
6792 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6793 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6794 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6795 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6796 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6797 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6798 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6799 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6800 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6801 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6803 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6804 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
6806 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6807 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6809 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6811 /* Neon scalar. Using an element size of 8 means that some invalid
6812 scalars are accepted here, so deal with those in later code. */
6813 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6817 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6820 po_imm_or_fail (0, 0, TRUE
);
6825 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6830 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6833 if (parse_ifimm_zero (&str
))
6834 inst
.operands
[i
].imm
= 0;
6838 = _("only floating point zero is allowed as immediate value");
6846 po_scalar_or_goto (8, try_rr
);
6849 po_reg_or_fail (REG_TYPE_RN
);
6855 po_scalar_or_goto (8, try_nsdq
);
6858 po_reg_or_fail (REG_TYPE_NSDQ
);
6864 po_scalar_or_goto (8, try_s_scalar
);
6867 po_scalar_or_goto (4, try_nsd
);
6870 po_reg_or_fail (REG_TYPE_NSD
);
6876 po_scalar_or_goto (8, try_ndq
);
6879 po_reg_or_fail (REG_TYPE_NDQ
);
6885 po_scalar_or_goto (8, try_vfd
);
6888 po_reg_or_fail (REG_TYPE_VFD
);
6893 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6894 not careful then bad things might happen. */
6895 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6900 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6903 /* There's a possibility of getting a 64-bit immediate here, so
6904 we need special handling. */
6905 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6908 inst
.error
= _("immediate value is out of range");
6916 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6919 po_imm_or_fail (0, 63, TRUE
);
6924 po_char_or_fail ('[');
6925 po_reg_or_fail (REG_TYPE_RN
);
6926 po_char_or_fail (']');
6932 po_reg_or_fail (REG_TYPE_RN
);
6933 if (skip_past_char (&str
, '!') == SUCCESS
)
6934 inst
.operands
[i
].writeback
= 1;
6938 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6939 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6940 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6941 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6942 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6943 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6944 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6945 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6946 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6947 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6948 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6949 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6951 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6953 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6954 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6956 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6957 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6958 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6959 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6961 /* Immediate variants */
6963 po_char_or_fail ('{');
6964 po_imm_or_fail (0, 255, TRUE
);
6965 po_char_or_fail ('}');
6969 /* The expression parser chokes on a trailing !, so we have
6970 to find it first and zap it. */
6973 while (*s
&& *s
!= ',')
6978 inst
.operands
[i
].writeback
= 1;
6980 po_imm_or_fail (0, 31, TRUE
);
6988 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6993 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6998 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
7000 if (inst
.reloc
.exp
.X_op
== O_symbol
)
7002 val
= parse_reloc (&str
);
7005 inst
.error
= _("unrecognized relocation suffix");
7008 else if (val
!= BFD_RELOC_UNUSED
)
7010 inst
.operands
[i
].imm
= val
;
7011 inst
.operands
[i
].hasreloc
= 1;
7016 /* Operand for MOVW or MOVT. */
7018 po_misc_or_fail (parse_half (&str
));
7021 /* Register or expression. */
7022 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7023 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7025 /* Register or immediate. */
7026 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7027 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7029 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7031 if (!is_immediate_prefix (*str
))
7034 val
= parse_fpa_immediate (&str
);
7037 /* FPA immediates are encoded as registers 8-15.
7038 parse_fpa_immediate has already applied the offset. */
7039 inst
.operands
[i
].reg
= val
;
7040 inst
.operands
[i
].isreg
= 1;
7043 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7044 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7046 /* Two kinds of register. */
7049 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7051 || (rege
->type
!= REG_TYPE_MMXWR
7052 && rege
->type
!= REG_TYPE_MMXWC
7053 && rege
->type
!= REG_TYPE_MMXWCG
))
7055 inst
.error
= _("iWMMXt data or control register expected");
7058 inst
.operands
[i
].reg
= rege
->number
;
7059 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7065 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7067 || (rege
->type
!= REG_TYPE_MMXWC
7068 && rege
->type
!= REG_TYPE_MMXWCG
))
7070 inst
.error
= _("iWMMXt control register expected");
7073 inst
.operands
[i
].reg
= rege
->number
;
7074 inst
.operands
[i
].isreg
= 1;
7079 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7080 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7081 case OP_oROR
: val
= parse_ror (&str
); break;
7082 case OP_COND
: val
= parse_cond (&str
); break;
7083 case OP_oBARRIER_I15
:
7084 po_barrier_or_imm (str
); break;
7086 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7092 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7093 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7095 inst
.error
= _("Banked registers are not available with this "
7101 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7105 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7108 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7110 if (strncasecmp (str
, "APSR_", 5) == 0)
7117 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7118 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7119 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7120 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7121 default: found
= 16;
7125 inst
.operands
[i
].isvec
= 1;
7126 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7127 inst
.operands
[i
].reg
= REG_PC
;
7134 po_misc_or_fail (parse_tb (&str
));
7137 /* Register lists. */
7139 val
= parse_reg_list (&str
);
7142 inst
.operands
[i
].writeback
= 1;
7148 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7152 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7156 /* Allow Q registers too. */
7157 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7162 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7164 inst
.operands
[i
].issingle
= 1;
7169 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7174 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7175 &inst
.operands
[i
].vectype
);
7178 /* Addressing modes */
7180 po_misc_or_fail (parse_address (&str
, i
));
7184 po_misc_or_fail_no_backtrack (
7185 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7189 po_misc_or_fail_no_backtrack (
7190 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7194 po_misc_or_fail_no_backtrack (
7195 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7199 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7203 po_misc_or_fail_no_backtrack (
7204 parse_shifter_operand_group_reloc (&str
, i
));
7208 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7212 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7216 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7220 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7223 /* Various value-based sanity checks and shared operations. We
7224 do not signal immediate failures for the register constraints;
7225 this allows a syntax error to take precedence. */
7226 switch (op_parse_code
)
7234 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7235 inst
.error
= BAD_PC
;
7240 if (inst
.operands
[i
].isreg
)
7242 if (inst
.operands
[i
].reg
== REG_PC
)
7243 inst
.error
= BAD_PC
;
7244 else if (inst
.operands
[i
].reg
== REG_SP
7245 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7246 relaxed since ARMv8-A. */
7247 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7250 inst
.error
= BAD_SP
;
7256 if (inst
.operands
[i
].isreg
7257 && inst
.operands
[i
].reg
== REG_PC
7258 && (inst
.operands
[i
].writeback
|| thumb
))
7259 inst
.error
= BAD_PC
;
7268 case OP_oBARRIER_I15
:
7277 inst
.operands
[i
].imm
= val
;
7284 /* If we get here, this operand was successfully parsed. */
7285 inst
.operands
[i
].present
= 1;
7289 inst
.error
= BAD_ARGS
;
7294 /* The parse routine should already have set inst.error, but set a
7295 default here just in case. */
7297 inst
.error
= _("syntax error");
7301 /* Do not backtrack over a trailing optional argument that
7302 absorbed some text. We will only fail again, with the
7303 'garbage following instruction' error message, which is
7304 probably less helpful than the current one. */
7305 if (backtrack_index
== i
&& backtrack_pos
!= str
7306 && upat
[i
+1] == OP_stop
)
7309 inst
.error
= _("syntax error");
7313 /* Try again, skipping the optional argument at backtrack_pos. */
7314 str
= backtrack_pos
;
7315 inst
.error
= backtrack_error
;
7316 inst
.operands
[backtrack_index
].present
= 0;
7317 i
= backtrack_index
;
7321 /* Check that we have parsed all the arguments. */
7322 if (*str
!= '\0' && !inst
.error
)
7323 inst
.error
= _("garbage following instruction");
7325 return inst
.error
? FAIL
: SUCCESS
;
7328 #undef po_char_or_fail
7329 #undef po_reg_or_fail
7330 #undef po_reg_or_goto
7331 #undef po_imm_or_fail
7332 #undef po_scalar_or_fail
7333 #undef po_barrier_or_imm
7335 /* Shorthand macro for instruction encoding functions issuing errors. */
7336 #define constraint(expr, err) \
7347 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7348 instructions are unpredictable if these registers are used. This
7349 is the BadReg predicate in ARM's Thumb-2 documentation.
7351 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7352 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7353 #define reject_bad_reg(reg) \
7355 if (reg == REG_PC) \
7357 inst.error = BAD_PC; \
7360 else if (reg == REG_SP \
7361 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7363 inst.error = BAD_SP; \
7368 /* If REG is R13 (the stack pointer), warn that its use is
7370 #define warn_deprecated_sp(reg) \
7372 if (warn_on_deprecated && reg == REG_SP) \
7373 as_tsktsk (_("use of r13 is deprecated")); \
7376 /* Functions for operand encoding. ARM, then Thumb. */
7378 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7380 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7382 The only binary encoding difference is the Coprocessor number. Coprocessor
7383 9 is used for half-precision calculations or conversions. The format of the
7384 instruction is the same as the equivalent Coprocessor 10 instruction that
7385 exists for Single-Precision operation. */
7388 do_scalar_fp16_v82_encode (void)
7390 if (inst
.cond
!= COND_ALWAYS
)
7391 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7392 " the behaviour is UNPREDICTABLE"));
7393 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7396 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7397 mark_feature_used (&arm_ext_fp16
);
7400 /* If VAL can be encoded in the immediate field of an ARM instruction,
7401 return the encoded form. Otherwise, return FAIL. */
7404 encode_arm_immediate (unsigned int val
)
7411 for (i
= 2; i
< 32; i
+= 2)
7412 if ((a
= rotate_left (val
, i
)) <= 0xff)
7413 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7418 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7419 return the encoded form. Otherwise, return FAIL. */
7421 encode_thumb32_immediate (unsigned int val
)
7428 for (i
= 1; i
<= 24; i
++)
7431 if ((val
& ~(0xff << i
)) == 0)
7432 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7436 if (val
== ((a
<< 16) | a
))
7438 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7442 if (val
== ((a
<< 16) | a
))
7443 return 0x200 | (a
>> 8);
7447 /* Encode a VFP SP or DP register number into inst.instruction. */
7450 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7452 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7455 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7458 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7461 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7466 first_error (_("D register out of range for selected VFP version"));
7474 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7478 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7482 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7486 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7490 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7494 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7502 /* Encode a <shift> in an ARM-format instruction. The immediate,
7503 if any, is handled by md_apply_fix. */
7505 encode_arm_shift (int i
)
7507 /* register-shifted register. */
7508 if (inst
.operands
[i
].immisreg
)
7511 for (op_index
= 0; op_index
<= i
; ++op_index
)
7513 /* Check the operand only when it's presented. In pre-UAL syntax,
7514 if the destination register is the same as the first operand, two
7515 register form of the instruction can be used. */
7516 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
7517 && inst
.operands
[op_index
].reg
== REG_PC
)
7518 as_warn (UNPRED_REG ("r15"));
7521 if (inst
.operands
[i
].imm
== REG_PC
)
7522 as_warn (UNPRED_REG ("r15"));
7525 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7526 inst
.instruction
|= SHIFT_ROR
<< 5;
7529 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7530 if (inst
.operands
[i
].immisreg
)
7532 inst
.instruction
|= SHIFT_BY_REG
;
7533 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7536 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7541 encode_arm_shifter_operand (int i
)
7543 if (inst
.operands
[i
].isreg
)
7545 inst
.instruction
|= inst
.operands
[i
].reg
;
7546 encode_arm_shift (i
);
7550 inst
.instruction
|= INST_IMMEDIATE
;
7551 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7552 inst
.instruction
|= inst
.operands
[i
].imm
;
7556 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7558 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7561 Generate an error if the operand is not a register. */
7562 constraint (!inst
.operands
[i
].isreg
,
7563 _("Instruction does not support =N addresses"));
7565 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7567 if (inst
.operands
[i
].preind
)
7571 inst
.error
= _("instruction does not accept preindexed addressing");
7574 inst
.instruction
|= PRE_INDEX
;
7575 if (inst
.operands
[i
].writeback
)
7576 inst
.instruction
|= WRITE_BACK
;
7579 else if (inst
.operands
[i
].postind
)
7581 gas_assert (inst
.operands
[i
].writeback
);
7583 inst
.instruction
|= WRITE_BACK
;
7585 else /* unindexed - only for coprocessor */
7587 inst
.error
= _("instruction does not accept unindexed addressing");
7591 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7592 && (((inst
.instruction
& 0x000f0000) >> 16)
7593 == ((inst
.instruction
& 0x0000f000) >> 12)))
7594 as_warn ((inst
.instruction
& LOAD_BIT
)
7595 ? _("destination register same as write-back base")
7596 : _("source register same as write-back base"));
7599 /* inst.operands[i] was set up by parse_address. Encode it into an
7600 ARM-format mode 2 load or store instruction. If is_t is true,
7601 reject forms that cannot be used with a T instruction (i.e. not
7604 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7606 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7608 encode_arm_addr_mode_common (i
, is_t
);
7610 if (inst
.operands
[i
].immisreg
)
7612 constraint ((inst
.operands
[i
].imm
== REG_PC
7613 || (is_pc
&& inst
.operands
[i
].writeback
)),
7615 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7616 inst
.instruction
|= inst
.operands
[i
].imm
;
7617 if (!inst
.operands
[i
].negative
)
7618 inst
.instruction
|= INDEX_UP
;
7619 if (inst
.operands
[i
].shifted
)
7621 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7622 inst
.instruction
|= SHIFT_ROR
<< 5;
7625 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7626 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7630 else /* immediate offset in inst.reloc */
7632 if (is_pc
&& !inst
.reloc
.pc_rel
)
7634 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7636 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7637 cannot use PC in addressing.
7638 PC cannot be used in writeback addressing, either. */
7639 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7642 /* Use of PC in str is deprecated for ARMv7. */
7643 if (warn_on_deprecated
7645 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7646 as_tsktsk (_("use of PC in this instruction is deprecated"));
7649 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7651 /* Prefer + for zero encoded value. */
7652 if (!inst
.operands
[i
].negative
)
7653 inst
.instruction
|= INDEX_UP
;
7654 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7659 /* inst.operands[i] was set up by parse_address. Encode it into an
7660 ARM-format mode 3 load or store instruction. Reject forms that
7661 cannot be used with such instructions. If is_t is true, reject
7662 forms that cannot be used with a T instruction (i.e. not
7665 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7667 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7669 inst
.error
= _("instruction does not accept scaled register index");
7673 encode_arm_addr_mode_common (i
, is_t
);
7675 if (inst
.operands
[i
].immisreg
)
7677 constraint ((inst
.operands
[i
].imm
== REG_PC
7678 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7680 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7682 inst
.instruction
|= inst
.operands
[i
].imm
;
7683 if (!inst
.operands
[i
].negative
)
7684 inst
.instruction
|= INDEX_UP
;
7686 else /* immediate offset in inst.reloc */
7688 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7689 && inst
.operands
[i
].writeback
),
7691 inst
.instruction
|= HWOFFSET_IMM
;
7692 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7694 /* Prefer + for zero encoded value. */
7695 if (!inst
.operands
[i
].negative
)
7696 inst
.instruction
|= INDEX_UP
;
7698 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7703 /* Write immediate bits [7:0] to the following locations:
7705 |28/24|23 19|18 16|15 4|3 0|
7706 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7708 This function is used by VMOV/VMVN/VORR/VBIC. */
7711 neon_write_immbits (unsigned immbits
)
7713 inst
.instruction
|= immbits
& 0xf;
7714 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7715 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7718 /* Invert low-order SIZE bits of XHI:XLO. */
7721 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7723 unsigned immlo
= xlo
? *xlo
: 0;
7724 unsigned immhi
= xhi
? *xhi
: 0;
7729 immlo
= (~immlo
) & 0xff;
7733 immlo
= (~immlo
) & 0xffff;
7737 immhi
= (~immhi
) & 0xffffffff;
7741 immlo
= (~immlo
) & 0xffffffff;
7755 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7759 neon_bits_same_in_bytes (unsigned imm
)
7761 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7762 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7763 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7764 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7767 /* For immediate of above form, return 0bABCD. */
7770 neon_squash_bits (unsigned imm
)
7772 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7773 | ((imm
& 0x01000000) >> 21);
7776 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7779 neon_qfloat_bits (unsigned imm
)
7781 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7784 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7785 the instruction. *OP is passed as the initial value of the op field, and
7786 may be set to a different value depending on the constant (i.e.
7787 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7788 MVN). If the immediate looks like a repeated pattern then also
7789 try smaller element sizes. */
7792 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7793 unsigned *immbits
, int *op
, int size
,
7794 enum neon_el_type type
)
7796 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7798 if (type
== NT_float
&& !float_p
)
7801 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7803 if (size
!= 32 || *op
== 1)
7805 *immbits
= neon_qfloat_bits (immlo
);
7811 if (neon_bits_same_in_bytes (immhi
)
7812 && neon_bits_same_in_bytes (immlo
))
7816 *immbits
= (neon_squash_bits (immhi
) << 4)
7817 | neon_squash_bits (immlo
);
7828 if (immlo
== (immlo
& 0x000000ff))
7833 else if (immlo
== (immlo
& 0x0000ff00))
7835 *immbits
= immlo
>> 8;
7838 else if (immlo
== (immlo
& 0x00ff0000))
7840 *immbits
= immlo
>> 16;
7843 else if (immlo
== (immlo
& 0xff000000))
7845 *immbits
= immlo
>> 24;
7848 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7850 *immbits
= (immlo
>> 8) & 0xff;
7853 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7855 *immbits
= (immlo
>> 16) & 0xff;
7859 if ((immlo
& 0xffff) != (immlo
>> 16))
7866 if (immlo
== (immlo
& 0x000000ff))
7871 else if (immlo
== (immlo
& 0x0000ff00))
7873 *immbits
= immlo
>> 8;
7877 if ((immlo
& 0xff) != (immlo
>> 8))
7882 if (immlo
== (immlo
& 0x000000ff))
7884 /* Don't allow MVN with 8-bit immediate. */
7894 #if defined BFD_HOST_64_BIT
7895 /* Returns TRUE if double precision value V may be cast
7896 to single precision without loss of accuracy. */
7899 is_double_a_single (bfd_int64_t v
)
7901 int exp
= (int)((v
>> 52) & 0x7FF);
7902 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7904 return (exp
== 0 || exp
== 0x7FF
7905 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7906 && (mantissa
& 0x1FFFFFFFl
) == 0;
7909 /* Returns a double precision value casted to single precision
7910 (ignoring the least significant bits in exponent and mantissa). */
7913 double_to_single (bfd_int64_t v
)
7915 int sign
= (int) ((v
>> 63) & 1l);
7916 int exp
= (int) ((v
>> 52) & 0x7FF);
7917 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7923 exp
= exp
- 1023 + 127;
7932 /* No denormalized numbers. */
7938 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7940 #endif /* BFD_HOST_64_BIT */
7949 static void do_vfp_nsyn_opcode (const char *);
7951 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7952 Determine whether it can be performed with a move instruction; if
7953 it can, convert inst.instruction to that move instruction and
7954 return TRUE; if it can't, convert inst.instruction to a literal-pool
7955 load and return FALSE. If this is not a valid thing to do in the
7956 current context, set inst.error and return TRUE.
7958 inst.operands[i] describes the destination register. */
7961 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7964 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7965 bfd_boolean arm_p
= (t
== CONST_ARM
);
7968 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7972 if ((inst
.instruction
& tbit
) == 0)
7974 inst
.error
= _("invalid pseudo operation");
7978 if (inst
.reloc
.exp
.X_op
!= O_constant
7979 && inst
.reloc
.exp
.X_op
!= O_symbol
7980 && inst
.reloc
.exp
.X_op
!= O_big
)
7982 inst
.error
= _("constant expression expected");
7986 if (inst
.reloc
.exp
.X_op
== O_constant
7987 || inst
.reloc
.exp
.X_op
== O_big
)
7989 #if defined BFD_HOST_64_BIT
7994 if (inst
.reloc
.exp
.X_op
== O_big
)
7996 LITTLENUM_TYPE w
[X_PRECISION
];
7999 if (inst
.reloc
.exp
.X_add_number
== -1)
8001 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8003 /* FIXME: Should we check words w[2..5] ? */
8008 #if defined BFD_HOST_64_BIT
8010 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8011 << LITTLENUM_NUMBER_OF_BITS
)
8012 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8013 << LITTLENUM_NUMBER_OF_BITS
)
8014 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8015 << LITTLENUM_NUMBER_OF_BITS
)
8016 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8018 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8019 | (l
[0] & LITTLENUM_MASK
);
8023 v
= inst
.reloc
.exp
.X_add_number
;
8025 if (!inst
.operands
[i
].issingle
)
8029 /* LDR should not use lead in a flag-setting instruction being
8030 chosen so we do not check whether movs can be used. */
8032 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8033 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8034 && inst
.operands
[i
].reg
!= 13
8035 && inst
.operands
[i
].reg
!= 15)
8037 /* Check if on thumb2 it can be done with a mov.w, mvn or
8038 movw instruction. */
8039 unsigned int newimm
;
8040 bfd_boolean isNegated
;
8042 newimm
= encode_thumb32_immediate (v
);
8043 if (newimm
!= (unsigned int) FAIL
)
8047 newimm
= encode_thumb32_immediate (~v
);
8048 if (newimm
!= (unsigned int) FAIL
)
8052 /* The number can be loaded with a mov.w or mvn
8054 if (newimm
!= (unsigned int) FAIL
8055 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8057 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8058 | (inst
.operands
[i
].reg
<< 8));
8059 /* Change to MOVN. */
8060 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8061 inst
.instruction
|= (newimm
& 0x800) << 15;
8062 inst
.instruction
|= (newimm
& 0x700) << 4;
8063 inst
.instruction
|= (newimm
& 0x0ff);
8066 /* The number can be loaded with a movw instruction. */
8067 else if ((v
& ~0xFFFF) == 0
8068 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8070 int imm
= v
& 0xFFFF;
8072 inst
.instruction
= 0xf2400000; /* MOVW. */
8073 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8074 inst
.instruction
|= (imm
& 0xf000) << 4;
8075 inst
.instruction
|= (imm
& 0x0800) << 15;
8076 inst
.instruction
|= (imm
& 0x0700) << 4;
8077 inst
.instruction
|= (imm
& 0x00ff);
8084 int value
= encode_arm_immediate (v
);
8088 /* This can be done with a mov instruction. */
8089 inst
.instruction
&= LITERAL_MASK
;
8090 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8091 inst
.instruction
|= value
& 0xfff;
8095 value
= encode_arm_immediate (~ v
);
8098 /* This can be done with a mvn instruction. */
8099 inst
.instruction
&= LITERAL_MASK
;
8100 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8101 inst
.instruction
|= value
& 0xfff;
8105 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8108 unsigned immbits
= 0;
8109 unsigned immlo
= inst
.operands
[1].imm
;
8110 unsigned immhi
= inst
.operands
[1].regisimm
8111 ? inst
.operands
[1].reg
8112 : inst
.reloc
.exp
.X_unsigned
8114 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8115 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8116 &op
, 64, NT_invtype
);
8120 neon_invert_size (&immlo
, &immhi
, 64);
8122 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8123 &op
, 64, NT_invtype
);
8128 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8134 /* Fill other bits in vmov encoding for both thumb and arm. */
8136 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8138 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8139 neon_write_immbits (immbits
);
8147 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8148 if (inst
.operands
[i
].issingle
8149 && is_quarter_float (inst
.operands
[1].imm
)
8150 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8152 inst
.operands
[1].imm
=
8153 neon_qfloat_bits (v
);
8154 do_vfp_nsyn_opcode ("fconsts");
8158 /* If our host does not support a 64-bit type then we cannot perform
8159 the following optimization. This mean that there will be a
8160 discrepancy between the output produced by an assembler built for
8161 a 32-bit-only host and the output produced from a 64-bit host, but
8162 this cannot be helped. */
8163 #if defined BFD_HOST_64_BIT
8164 else if (!inst
.operands
[1].issingle
8165 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8167 if (is_double_a_single (v
)
8168 && is_quarter_float (double_to_single (v
)))
8170 inst
.operands
[1].imm
=
8171 neon_qfloat_bits (double_to_single (v
));
8172 do_vfp_nsyn_opcode ("fconstd");
8180 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8181 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8184 inst
.operands
[1].reg
= REG_PC
;
8185 inst
.operands
[1].isreg
= 1;
8186 inst
.operands
[1].preind
= 1;
8187 inst
.reloc
.pc_rel
= 1;
8188 inst
.reloc
.type
= (thumb_p
8189 ? BFD_RELOC_ARM_THUMB_OFFSET
8191 ? BFD_RELOC_ARM_HWLITERAL
8192 : BFD_RELOC_ARM_LITERAL
));
8196 /* inst.operands[i] was set up by parse_address. Encode it into an
8197 ARM-format instruction. Reject all forms which cannot be encoded
8198 into a coprocessor load/store instruction. If wb_ok is false,
8199 reject use of writeback; if unind_ok is false, reject use of
8200 unindexed addressing. If reloc_override is not 0, use it instead
8201 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8202 (in which case it is preserved). */
8205 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8207 if (!inst
.operands
[i
].isreg
)
8210 if (! inst
.operands
[0].isvec
)
8212 inst
.error
= _("invalid co-processor operand");
8215 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8219 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8221 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8223 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8225 gas_assert (!inst
.operands
[i
].writeback
);
8228 inst
.error
= _("instruction does not support unindexed addressing");
8231 inst
.instruction
|= inst
.operands
[i
].imm
;
8232 inst
.instruction
|= INDEX_UP
;
8236 if (inst
.operands
[i
].preind
)
8237 inst
.instruction
|= PRE_INDEX
;
8239 if (inst
.operands
[i
].writeback
)
8241 if (inst
.operands
[i
].reg
== REG_PC
)
8243 inst
.error
= _("pc may not be used with write-back");
8248 inst
.error
= _("instruction does not support writeback");
8251 inst
.instruction
|= WRITE_BACK
;
8255 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8256 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8257 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8258 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8261 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8263 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8266 /* Prefer + for zero encoded value. */
8267 if (!inst
.operands
[i
].negative
)
8268 inst
.instruction
|= INDEX_UP
;
8273 /* Functions for instruction encoding, sorted by sub-architecture.
8274 First some generics; their names are taken from the conventional
8275 bit positions for register arguments in ARM format instructions. */
8285 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8291 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8297 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8298 inst
.instruction
|= inst
.operands
[1].reg
;
8304 inst
.instruction
|= inst
.operands
[0].reg
;
8305 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8311 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8312 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8318 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8319 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8325 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8326 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8330 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8332 if (ARM_CPU_IS_ANY (cpu_variant
))
8334 as_tsktsk ("%s", msg
);
8337 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8349 unsigned Rn
= inst
.operands
[2].reg
;
8350 /* Enforce restrictions on SWP instruction. */
8351 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8353 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8354 _("Rn must not overlap other operands"));
8356 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8358 if (!check_obsolete (&arm_ext_v8
,
8359 _("swp{b} use is obsoleted for ARMv8 and later"))
8360 && warn_on_deprecated
8361 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8362 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8365 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8366 inst
.instruction
|= inst
.operands
[1].reg
;
8367 inst
.instruction
|= Rn
<< 16;
8373 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8374 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8375 inst
.instruction
|= inst
.operands
[2].reg
;
8381 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8382 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8383 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8384 || inst
.reloc
.exp
.X_add_number
!= 0),
8386 inst
.instruction
|= inst
.operands
[0].reg
;
8387 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8388 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8394 inst
.instruction
|= inst
.operands
[0].imm
;
8400 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8401 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8404 /* ARM instructions, in alphabetical order by function name (except
8405 that wrapper functions appear immediately after the function they
8408 /* This is a pseudo-op of the form "adr rd, label" to be converted
8409 into a relative address of the form "add rd, pc, #label-.-8". */
8414 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8416 /* Frag hacking will turn this into a sub instruction if the offset turns
8417 out to be negative. */
8418 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8419 inst
.reloc
.pc_rel
= 1;
8420 inst
.reloc
.exp
.X_add_number
-= 8;
8422 if (inst
.reloc
.exp
.X_op
== O_symbol
8423 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8424 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8425 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8426 inst
.reloc
.exp
.X_add_number
+= 1;
8429 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8430 into a relative address of the form:
8431 add rd, pc, #low(label-.-8)"
8432 add rd, rd, #high(label-.-8)" */
8437 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8439 /* Frag hacking will turn this into a sub instruction if the offset turns
8440 out to be negative. */
8441 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8442 inst
.reloc
.pc_rel
= 1;
8443 inst
.size
= INSN_SIZE
* 2;
8444 inst
.reloc
.exp
.X_add_number
-= 8;
8446 if (inst
.reloc
.exp
.X_op
== O_symbol
8447 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8448 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8449 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8450 inst
.reloc
.exp
.X_add_number
+= 1;
8456 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8457 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8459 if (!inst
.operands
[1].present
)
8460 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8461 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8462 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8463 encode_arm_shifter_operand (2);
8469 if (inst
.operands
[0].present
)
8470 inst
.instruction
|= inst
.operands
[0].imm
;
8472 inst
.instruction
|= 0xf;
8478 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8479 constraint (msb
> 32, _("bit-field extends past end of register"));
8480 /* The instruction encoding stores the LSB and MSB,
8481 not the LSB and width. */
8482 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8483 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8484 inst
.instruction
|= (msb
- 1) << 16;
8492 /* #0 in second position is alternative syntax for bfc, which is
8493 the same instruction but with REG_PC in the Rm field. */
8494 if (!inst
.operands
[1].isreg
)
8495 inst
.operands
[1].reg
= REG_PC
;
8497 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8498 constraint (msb
> 32, _("bit-field extends past end of register"));
8499 /* The instruction encoding stores the LSB and MSB,
8500 not the LSB and width. */
8501 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8502 inst
.instruction
|= inst
.operands
[1].reg
;
8503 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8504 inst
.instruction
|= (msb
- 1) << 16;
8510 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8511 _("bit-field extends past end of register"));
8512 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8513 inst
.instruction
|= inst
.operands
[1].reg
;
8514 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8515 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8518 /* ARM V5 breakpoint instruction (argument parse)
8519 BKPT <16 bit unsigned immediate>
8520 Instruction is not conditional.
8521 The bit pattern given in insns[] has the COND_ALWAYS condition,
8522 and it is an error if the caller tried to override that. */
8527 /* Top 12 of 16 bits to bits 19:8. */
8528 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8530 /* Bottom 4 of 16 bits to bits 3:0. */
8531 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8535 encode_branch (int default_reloc
)
8537 if (inst
.operands
[0].hasreloc
)
8539 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8540 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8541 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8542 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8543 ? BFD_RELOC_ARM_PLT32
8544 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8547 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8548 inst
.reloc
.pc_rel
= 1;
8555 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8556 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8559 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8566 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8568 if (inst
.cond
== COND_ALWAYS
)
8569 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8571 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8575 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8578 /* ARM V5 branch-link-exchange instruction (argument parse)
8579 BLX <target_addr> ie BLX(1)
8580 BLX{<condition>} <Rm> ie BLX(2)
8581 Unfortunately, there are two different opcodes for this mnemonic.
8582 So, the insns[].value is not used, and the code here zaps values
8583 into inst.instruction.
8584 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8589 if (inst
.operands
[0].isreg
)
8591 /* Arg is a register; the opcode provided by insns[] is correct.
8592 It is not illegal to do "blx pc", just useless. */
8593 if (inst
.operands
[0].reg
== REG_PC
)
8594 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8596 inst
.instruction
|= inst
.operands
[0].reg
;
8600 /* Arg is an address; this instruction cannot be executed
8601 conditionally, and the opcode must be adjusted.
8602 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8603 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8604 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8605 inst
.instruction
= 0xfa000000;
8606 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8613 bfd_boolean want_reloc
;
8615 if (inst
.operands
[0].reg
== REG_PC
)
8616 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8618 inst
.instruction
|= inst
.operands
[0].reg
;
8619 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8620 it is for ARMv4t or earlier. */
8621 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8622 if (!ARM_FEATURE_ZERO (selected_object_arch
)
8623 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
8627 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8632 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8636 /* ARM v5TEJ. Jump to Jazelle code. */
8641 if (inst
.operands
[0].reg
== REG_PC
)
8642 as_tsktsk (_("use of r15 in bxj is not really useful"));
8644 inst
.instruction
|= inst
.operands
[0].reg
;
8647 /* Co-processor data operation:
8648 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8649 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8653 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8654 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8655 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8656 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8657 inst
.instruction
|= inst
.operands
[4].reg
;
8658 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8664 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8665 encode_arm_shifter_operand (1);
8668 /* Transfer between coprocessor and ARM registers.
8669 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8674 No special properties. */
8676 struct deprecated_coproc_regs_s
8683 arm_feature_set deprecated
;
8684 arm_feature_set obsoleted
;
8685 const char *dep_msg
;
8686 const char *obs_msg
;
8689 #define DEPR_ACCESS_V8 \
8690 N_("This coprocessor register access is deprecated in ARMv8")
8692 /* Table of all deprecated coprocessor registers. */
8693 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8695 {15, 0, 7, 10, 5, /* CP15DMB. */
8696 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8697 DEPR_ACCESS_V8
, NULL
},
8698 {15, 0, 7, 10, 4, /* CP15DSB. */
8699 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8700 DEPR_ACCESS_V8
, NULL
},
8701 {15, 0, 7, 5, 4, /* CP15ISB. */
8702 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8703 DEPR_ACCESS_V8
, NULL
},
8704 {14, 6, 1, 0, 0, /* TEEHBR. */
8705 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8706 DEPR_ACCESS_V8
, NULL
},
8707 {14, 6, 0, 0, 0, /* TEECR. */
8708 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8709 DEPR_ACCESS_V8
, NULL
},
8712 #undef DEPR_ACCESS_V8
8714 static const size_t deprecated_coproc_reg_count
=
8715 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8723 Rd
= inst
.operands
[2].reg
;
8726 if (inst
.instruction
== 0xee000010
8727 || inst
.instruction
== 0xfe000010)
8729 reject_bad_reg (Rd
);
8730 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8732 constraint (Rd
== REG_SP
, BAD_SP
);
8737 if (inst
.instruction
== 0xe000010)
8738 constraint (Rd
== REG_PC
, BAD_PC
);
8741 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8743 const struct deprecated_coproc_regs_s
*r
=
8744 deprecated_coproc_regs
+ i
;
8746 if (inst
.operands
[0].reg
== r
->cp
8747 && inst
.operands
[1].imm
== r
->opc1
8748 && inst
.operands
[3].reg
== r
->crn
8749 && inst
.operands
[4].reg
== r
->crm
8750 && inst
.operands
[5].imm
== r
->opc2
)
8752 if (! ARM_CPU_IS_ANY (cpu_variant
)
8753 && warn_on_deprecated
8754 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8755 as_tsktsk ("%s", r
->dep_msg
);
8759 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8760 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8761 inst
.instruction
|= Rd
<< 12;
8762 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8763 inst
.instruction
|= inst
.operands
[4].reg
;
8764 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8767 /* Transfer between coprocessor register and pair of ARM registers.
8768 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8773 Two XScale instructions are special cases of these:
8775 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8776 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8778 Result unpredictable if Rd or Rn is R15. */
8785 Rd
= inst
.operands
[2].reg
;
8786 Rn
= inst
.operands
[3].reg
;
8790 reject_bad_reg (Rd
);
8791 reject_bad_reg (Rn
);
8795 constraint (Rd
== REG_PC
, BAD_PC
);
8796 constraint (Rn
== REG_PC
, BAD_PC
);
8799 /* Only check the MRRC{2} variants. */
8800 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8802 /* If Rd == Rn, error that the operation is
8803 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8804 constraint (Rd
== Rn
, BAD_OVERLAP
);
8807 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8808 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8809 inst
.instruction
|= Rd
<< 12;
8810 inst
.instruction
|= Rn
<< 16;
8811 inst
.instruction
|= inst
.operands
[4].reg
;
8817 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8818 if (inst
.operands
[1].present
)
8820 inst
.instruction
|= CPSI_MMOD
;
8821 inst
.instruction
|= inst
.operands
[1].imm
;
8828 inst
.instruction
|= inst
.operands
[0].imm
;
8834 unsigned Rd
, Rn
, Rm
;
8836 Rd
= inst
.operands
[0].reg
;
8837 Rn
= (inst
.operands
[1].present
8838 ? inst
.operands
[1].reg
: Rd
);
8839 Rm
= inst
.operands
[2].reg
;
8841 constraint ((Rd
== REG_PC
), BAD_PC
);
8842 constraint ((Rn
== REG_PC
), BAD_PC
);
8843 constraint ((Rm
== REG_PC
), BAD_PC
);
8845 inst
.instruction
|= Rd
<< 16;
8846 inst
.instruction
|= Rn
<< 0;
8847 inst
.instruction
|= Rm
<< 8;
8853 /* There is no IT instruction in ARM mode. We
8854 process it to do the validation as if in
8855 thumb mode, just in case the code gets
8856 assembled for thumb using the unified syntax. */
8861 set_it_insn_type (IT_INSN
);
8862 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8863 now_it
.cc
= inst
.operands
[0].imm
;
8867 /* If there is only one register in the register list,
8868 then return its register number. Otherwise return -1. */
8870 only_one_reg_in_list (int range
)
8872 int i
= ffs (range
) - 1;
8873 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8877 encode_ldmstm(int from_push_pop_mnem
)
8879 int base_reg
= inst
.operands
[0].reg
;
8880 int range
= inst
.operands
[1].imm
;
8883 inst
.instruction
|= base_reg
<< 16;
8884 inst
.instruction
|= range
;
8886 if (inst
.operands
[1].writeback
)
8887 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8889 if (inst
.operands
[0].writeback
)
8891 inst
.instruction
|= WRITE_BACK
;
8892 /* Check for unpredictable uses of writeback. */
8893 if (inst
.instruction
& LOAD_BIT
)
8895 /* Not allowed in LDM type 2. */
8896 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8897 && ((range
& (1 << REG_PC
)) == 0))
8898 as_warn (_("writeback of base register is UNPREDICTABLE"));
8899 /* Only allowed if base reg not in list for other types. */
8900 else if (range
& (1 << base_reg
))
8901 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8905 /* Not allowed for type 2. */
8906 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8907 as_warn (_("writeback of base register is UNPREDICTABLE"));
8908 /* Only allowed if base reg not in list, or first in list. */
8909 else if ((range
& (1 << base_reg
))
8910 && (range
& ((1 << base_reg
) - 1)))
8911 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8915 /* If PUSH/POP has only one register, then use the A2 encoding. */
8916 one_reg
= only_one_reg_in_list (range
);
8917 if (from_push_pop_mnem
&& one_reg
>= 0)
8919 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8921 if (is_push
&& one_reg
== 13 /* SP */)
8922 /* PR 22483: The A2 encoding cannot be used when
8923 pushing the stack pointer as this is UNPREDICTABLE. */
8926 inst
.instruction
&= A_COND_MASK
;
8927 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8928 inst
.instruction
|= one_reg
<< 12;
8935 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8938 /* ARMv5TE load-consecutive (argument parse)
8947 constraint (inst
.operands
[0].reg
% 2 != 0,
8948 _("first transfer register must be even"));
8949 constraint (inst
.operands
[1].present
8950 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8951 _("can only transfer two consecutive registers"));
8952 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8953 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8955 if (!inst
.operands
[1].present
)
8956 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8958 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8959 register and the first register written; we have to diagnose
8960 overlap between the base and the second register written here. */
8962 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8963 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8964 as_warn (_("base register written back, and overlaps "
8965 "second transfer register"));
8967 if (!(inst
.instruction
& V4_STR_BIT
))
8969 /* For an index-register load, the index register must not overlap the
8970 destination (even if not write-back). */
8971 if (inst
.operands
[2].immisreg
8972 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8973 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8974 as_warn (_("index register overlaps transfer register"));
8976 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8977 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8983 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8984 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8985 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8986 || inst
.operands
[1].negative
8987 /* This can arise if the programmer has written
8989 or if they have mistakenly used a register name as the last
8992 It is very difficult to distinguish between these two cases
8993 because "rX" might actually be a label. ie the register
8994 name has been occluded by a symbol of the same name. So we
8995 just generate a general 'bad addressing mode' type error
8996 message and leave it up to the programmer to discover the
8997 true cause and fix their mistake. */
8998 || (inst
.operands
[1].reg
== REG_PC
),
9001 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9002 || inst
.reloc
.exp
.X_add_number
!= 0,
9003 _("offset must be zero in ARM encoding"));
9005 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9007 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9008 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9009 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9015 constraint (inst
.operands
[0].reg
% 2 != 0,
9016 _("even register required"));
9017 constraint (inst
.operands
[1].present
9018 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9019 _("can only load two consecutive registers"));
9020 /* If op 1 were present and equal to PC, this function wouldn't
9021 have been called in the first place. */
9022 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9024 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9025 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9028 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9029 which is not a multiple of four is UNPREDICTABLE. */
9031 check_ldr_r15_aligned (void)
9033 constraint (!(inst
.operands
[1].immisreg
)
9034 && (inst
.operands
[0].reg
== REG_PC
9035 && inst
.operands
[1].reg
== REG_PC
9036 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
9037 _("ldr to register 15 must be 4-byte aligned"));
9043 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9044 if (!inst
.operands
[1].isreg
)
9045 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9047 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9048 check_ldr_r15_aligned ();
9054 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9056 if (inst
.operands
[1].preind
)
9058 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9059 || inst
.reloc
.exp
.X_add_number
!= 0,
9060 _("this instruction requires a post-indexed address"));
9062 inst
.operands
[1].preind
= 0;
9063 inst
.operands
[1].postind
= 1;
9064 inst
.operands
[1].writeback
= 1;
9066 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9067 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9070 /* Halfword and signed-byte load/store operations. */
9075 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9076 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9077 if (!inst
.operands
[1].isreg
)
9078 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9080 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9086 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9088 if (inst
.operands
[1].preind
)
9090 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9091 || inst
.reloc
.exp
.X_add_number
!= 0,
9092 _("this instruction requires a post-indexed address"));
9094 inst
.operands
[1].preind
= 0;
9095 inst
.operands
[1].postind
= 1;
9096 inst
.operands
[1].writeback
= 1;
9098 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9099 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9102 /* Co-processor register load/store.
9103 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9107 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9108 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9109 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9115 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9116 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9117 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9118 && !(inst
.instruction
& 0x00400000))
9119 as_tsktsk (_("Rd and Rm should be different in mla"));
9121 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9122 inst
.instruction
|= inst
.operands
[1].reg
;
9123 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9124 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9130 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9131 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9133 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9134 encode_arm_shifter_operand (1);
9137 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9144 top
= (inst
.instruction
& 0x00400000) != 0;
9145 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9146 _(":lower16: not allowed in this instruction"));
9147 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9148 _(":upper16: not allowed in this instruction"));
9149 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9150 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9152 imm
= inst
.reloc
.exp
.X_add_number
;
9153 /* The value is in two pieces: 0:11, 16:19. */
9154 inst
.instruction
|= (imm
& 0x00000fff);
9155 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9160 do_vfp_nsyn_mrs (void)
9162 if (inst
.operands
[0].isvec
)
9164 if (inst
.operands
[1].reg
!= 1)
9165 first_error (_("operand 1 must be FPSCR"));
9166 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9167 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9168 do_vfp_nsyn_opcode ("fmstat");
9170 else if (inst
.operands
[1].isvec
)
9171 do_vfp_nsyn_opcode ("fmrx");
9179 do_vfp_nsyn_msr (void)
9181 if (inst
.operands
[0].isvec
)
9182 do_vfp_nsyn_opcode ("fmxr");
9192 unsigned Rt
= inst
.operands
[0].reg
;
9194 if (thumb_mode
&& Rt
== REG_SP
)
9196 inst
.error
= BAD_SP
;
9200 /* MVFR2 is only valid at ARMv8-A. */
9201 if (inst
.operands
[1].reg
== 5)
9202 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9205 /* APSR_ sets isvec. All other refs to PC are illegal. */
9206 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9208 inst
.error
= BAD_PC
;
9212 /* If we get through parsing the register name, we just insert the number
9213 generated into the instruction without further validation. */
9214 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9215 inst
.instruction
|= (Rt
<< 12);
9221 unsigned Rt
= inst
.operands
[1].reg
;
9224 reject_bad_reg (Rt
);
9225 else if (Rt
== REG_PC
)
9227 inst
.error
= BAD_PC
;
9231 /* MVFR2 is only valid for ARMv8-A. */
9232 if (inst
.operands
[0].reg
== 5)
9233 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9236 /* If we get through parsing the register name, we just insert the number
9237 generated into the instruction without further validation. */
9238 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9239 inst
.instruction
|= (Rt
<< 12);
9247 if (do_vfp_nsyn_mrs () == SUCCESS
)
9250 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9251 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9253 if (inst
.operands
[1].isreg
)
9255 br
= inst
.operands
[1].reg
;
9256 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9257 as_bad (_("bad register for mrs"));
9261 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9262 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9264 _("'APSR', 'CPSR' or 'SPSR' expected"));
9265 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9268 inst
.instruction
|= br
;
9271 /* Two possible forms:
9272 "{C|S}PSR_<field>, Rm",
9273 "{C|S}PSR_f, #expression". */
9278 if (do_vfp_nsyn_msr () == SUCCESS
)
9281 inst
.instruction
|= inst
.operands
[0].imm
;
9282 if (inst
.operands
[1].isreg
)
9283 inst
.instruction
|= inst
.operands
[1].reg
;
9286 inst
.instruction
|= INST_IMMEDIATE
;
9287 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9288 inst
.reloc
.pc_rel
= 0;
9295 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9297 if (!inst
.operands
[2].present
)
9298 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9299 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9300 inst
.instruction
|= inst
.operands
[1].reg
;
9301 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9303 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9304 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9305 as_tsktsk (_("Rd and Rm should be different in mul"));
9308 /* Long Multiply Parser
9309 UMULL RdLo, RdHi, Rm, Rs
9310 SMULL RdLo, RdHi, Rm, Rs
9311 UMLAL RdLo, RdHi, Rm, Rs
9312 SMLAL RdLo, RdHi, Rm, Rs. */
9317 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9318 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9319 inst
.instruction
|= inst
.operands
[2].reg
;
9320 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9322 /* rdhi and rdlo must be different. */
9323 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9324 as_tsktsk (_("rdhi and rdlo must be different"));
9326 /* rdhi, rdlo and rm must all be different before armv6. */
9327 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9328 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9329 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9330 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9336 if (inst
.operands
[0].present
9337 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9339 /* Architectural NOP hints are CPSR sets with no bits selected. */
9340 inst
.instruction
&= 0xf0000000;
9341 inst
.instruction
|= 0x0320f000;
9342 if (inst
.operands
[0].present
)
9343 inst
.instruction
|= inst
.operands
[0].imm
;
9347 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9348 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9349 Condition defaults to COND_ALWAYS.
9350 Error if Rd, Rn or Rm are R15. */
9355 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9356 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9357 inst
.instruction
|= inst
.operands
[2].reg
;
9358 if (inst
.operands
[3].present
)
9359 encode_arm_shift (3);
9362 /* ARM V6 PKHTB (Argument Parse). */
9367 if (!inst
.operands
[3].present
)
9369 /* If the shift specifier is omitted, turn the instruction
9370 into pkhbt rd, rm, rn. */
9371 inst
.instruction
&= 0xfff00010;
9372 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9373 inst
.instruction
|= inst
.operands
[1].reg
;
9374 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9378 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9379 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9380 inst
.instruction
|= inst
.operands
[2].reg
;
9381 encode_arm_shift (3);
9385 /* ARMv5TE: Preload-Cache
9386 MP Extensions: Preload for write
9390 Syntactically, like LDR with B=1, W=0, L=1. */
9395 constraint (!inst
.operands
[0].isreg
,
9396 _("'[' expected after PLD mnemonic"));
9397 constraint (inst
.operands
[0].postind
,
9398 _("post-indexed expression used in preload instruction"));
9399 constraint (inst
.operands
[0].writeback
,
9400 _("writeback used in preload instruction"));
9401 constraint (!inst
.operands
[0].preind
,
9402 _("unindexed addressing used in preload instruction"));
9403 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9406 /* ARMv7: PLI <addr_mode> */
9410 constraint (!inst
.operands
[0].isreg
,
9411 _("'[' expected after PLI mnemonic"));
9412 constraint (inst
.operands
[0].postind
,
9413 _("post-indexed expression used in preload instruction"));
9414 constraint (inst
.operands
[0].writeback
,
9415 _("writeback used in preload instruction"));
9416 constraint (!inst
.operands
[0].preind
,
9417 _("unindexed addressing used in preload instruction"));
9418 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9419 inst
.instruction
&= ~PRE_INDEX
;
9425 constraint (inst
.operands
[0].writeback
,
9426 _("push/pop do not support {reglist}^"));
9427 inst
.operands
[1] = inst
.operands
[0];
9428 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9429 inst
.operands
[0].isreg
= 1;
9430 inst
.operands
[0].writeback
= 1;
9431 inst
.operands
[0].reg
= REG_SP
;
9432 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9435 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9436 word at the specified address and the following word
9438 Unconditionally executed.
9439 Error if Rn is R15. */
9444 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9445 if (inst
.operands
[0].writeback
)
9446 inst
.instruction
|= WRITE_BACK
;
9449 /* ARM V6 ssat (argument parse). */
9454 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9455 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9456 inst
.instruction
|= inst
.operands
[2].reg
;
9458 if (inst
.operands
[3].present
)
9459 encode_arm_shift (3);
9462 /* ARM V6 usat (argument parse). */
9467 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9468 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9469 inst
.instruction
|= inst
.operands
[2].reg
;
9471 if (inst
.operands
[3].present
)
9472 encode_arm_shift (3);
9475 /* ARM V6 ssat16 (argument parse). */
9480 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9481 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9482 inst
.instruction
|= inst
.operands
[2].reg
;
9488 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9489 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9490 inst
.instruction
|= inst
.operands
[2].reg
;
9493 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9494 preserving the other bits.
9496 setend <endian_specifier>, where <endian_specifier> is either
9502 if (warn_on_deprecated
9503 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9504 as_tsktsk (_("setend use is deprecated for ARMv8"));
9506 if (inst
.operands
[0].imm
)
9507 inst
.instruction
|= 0x200;
9513 unsigned int Rm
= (inst
.operands
[1].present
9514 ? inst
.operands
[1].reg
9515 : inst
.operands
[0].reg
);
9517 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9518 inst
.instruction
|= Rm
;
9519 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9521 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9522 inst
.instruction
|= SHIFT_BY_REG
;
9523 /* PR 12854: Error on extraneous shifts. */
9524 constraint (inst
.operands
[2].shifted
,
9525 _("extraneous shift as part of operand to shift insn"));
9528 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9534 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9535 inst
.reloc
.pc_rel
= 0;
9541 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9542 inst
.reloc
.pc_rel
= 0;
9548 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9549 inst
.reloc
.pc_rel
= 0;
9555 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9556 _("selected processor does not support SETPAN instruction"));
9558 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9564 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9565 _("selected processor does not support SETPAN instruction"));
9567 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9570 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9571 SMLAxy{cond} Rd,Rm,Rs,Rn
9572 SMLAWy{cond} Rd,Rm,Rs,Rn
9573 Error if any register is R15. */
9578 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9579 inst
.instruction
|= inst
.operands
[1].reg
;
9580 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9581 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9584 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9585 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9586 Error if any register is R15.
9587 Warning if Rdlo == Rdhi. */
9592 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9593 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9594 inst
.instruction
|= inst
.operands
[2].reg
;
9595 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9597 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9598 as_tsktsk (_("rdhi and rdlo must be different"));
9601 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9602 SMULxy{cond} Rd,Rm,Rs
9603 Error if any register is R15. */
9608 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9609 inst
.instruction
|= inst
.operands
[1].reg
;
9610 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9613 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9614 the same for both ARM and Thumb-2. */
9621 if (inst
.operands
[0].present
)
9623 reg
= inst
.operands
[0].reg
;
9624 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9629 inst
.instruction
|= reg
<< 16;
9630 inst
.instruction
|= inst
.operands
[1].imm
;
9631 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9632 inst
.instruction
|= WRITE_BACK
;
9635 /* ARM V6 strex (argument parse). */
9640 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9641 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9642 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9643 || inst
.operands
[2].negative
9644 /* See comment in do_ldrex(). */
9645 || (inst
.operands
[2].reg
== REG_PC
),
9648 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9649 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9651 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9652 || inst
.reloc
.exp
.X_add_number
!= 0,
9653 _("offset must be zero in ARM encoding"));
9655 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9656 inst
.instruction
|= inst
.operands
[1].reg
;
9657 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9658 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9664 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9665 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9666 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9667 || inst
.operands
[2].negative
,
9670 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9671 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9679 constraint (inst
.operands
[1].reg
% 2 != 0,
9680 _("even register required"));
9681 constraint (inst
.operands
[2].present
9682 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9683 _("can only store two consecutive registers"));
9684 /* If op 2 were present and equal to PC, this function wouldn't
9685 have been called in the first place. */
9686 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9688 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9689 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9690 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9693 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9694 inst
.instruction
|= inst
.operands
[1].reg
;
9695 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9702 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9703 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9711 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9712 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9717 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9718 extends it to 32-bits, and adds the result to a value in another
9719 register. You can specify a rotation by 0, 8, 16, or 24 bits
9720 before extracting the 16-bit value.
9721 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9722 Condition defaults to COND_ALWAYS.
9723 Error if any register uses R15. */
9728 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9729 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9730 inst
.instruction
|= inst
.operands
[2].reg
;
9731 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9736 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9737 Condition defaults to COND_ALWAYS.
9738 Error if any register uses R15. */
9743 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9744 inst
.instruction
|= inst
.operands
[1].reg
;
9745 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9748 /* VFP instructions. In a logical order: SP variant first, monad
9749 before dyad, arithmetic then move then load/store. */
9752 do_vfp_sp_monadic (void)
9754 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9755 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9759 do_vfp_sp_dyadic (void)
9761 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9762 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9763 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9767 do_vfp_sp_compare_z (void)
9769 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9773 do_vfp_dp_sp_cvt (void)
9775 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9776 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9780 do_vfp_sp_dp_cvt (void)
9782 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9783 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9787 do_vfp_reg_from_sp (void)
9789 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9790 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9794 do_vfp_reg2_from_sp2 (void)
9796 constraint (inst
.operands
[2].imm
!= 2,
9797 _("only two consecutive VFP SP registers allowed here"));
9798 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9799 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9800 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9804 do_vfp_sp_from_reg (void)
9806 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9807 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9811 do_vfp_sp2_from_reg2 (void)
9813 constraint (inst
.operands
[0].imm
!= 2,
9814 _("only two consecutive VFP SP registers allowed here"));
9815 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9816 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9817 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9821 do_vfp_sp_ldst (void)
9823 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9824 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9828 do_vfp_dp_ldst (void)
9830 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9831 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9836 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9838 if (inst
.operands
[0].writeback
)
9839 inst
.instruction
|= WRITE_BACK
;
9841 constraint (ldstm_type
!= VFP_LDSTMIA
,
9842 _("this addressing mode requires base-register writeback"));
9843 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9844 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9845 inst
.instruction
|= inst
.operands
[1].imm
;
9849 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9853 if (inst
.operands
[0].writeback
)
9854 inst
.instruction
|= WRITE_BACK
;
9856 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9857 _("this addressing mode requires base-register writeback"));
9859 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9860 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9862 count
= inst
.operands
[1].imm
<< 1;
9863 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9866 inst
.instruction
|= count
;
9870 do_vfp_sp_ldstmia (void)
9872 vfp_sp_ldstm (VFP_LDSTMIA
);
9876 do_vfp_sp_ldstmdb (void)
9878 vfp_sp_ldstm (VFP_LDSTMDB
);
9882 do_vfp_dp_ldstmia (void)
9884 vfp_dp_ldstm (VFP_LDSTMIA
);
9888 do_vfp_dp_ldstmdb (void)
9890 vfp_dp_ldstm (VFP_LDSTMDB
);
9894 do_vfp_xp_ldstmia (void)
9896 vfp_dp_ldstm (VFP_LDSTMIAX
);
9900 do_vfp_xp_ldstmdb (void)
9902 vfp_dp_ldstm (VFP_LDSTMDBX
);
9906 do_vfp_dp_rd_rm (void)
9908 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9909 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9913 do_vfp_dp_rn_rd (void)
9915 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9916 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9920 do_vfp_dp_rd_rn (void)
9922 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9923 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9927 do_vfp_dp_rd_rn_rm (void)
9929 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9930 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9931 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9937 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9941 do_vfp_dp_rm_rd_rn (void)
9943 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9944 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9945 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9948 /* VFPv3 instructions. */
9950 do_vfp_sp_const (void)
9952 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9953 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9954 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9958 do_vfp_dp_const (void)
9960 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9961 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9962 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9966 vfp_conv (int srcsize
)
9968 int immbits
= srcsize
- inst
.operands
[1].imm
;
9970 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9972 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9973 i.e. immbits must be in range 0 - 16. */
9974 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9977 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9979 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9980 i.e. immbits must be in range 0 - 31. */
9981 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9985 inst
.instruction
|= (immbits
& 1) << 5;
9986 inst
.instruction
|= (immbits
>> 1);
9990 do_vfp_sp_conv_16 (void)
9992 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9997 do_vfp_dp_conv_16 (void)
9999 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10004 do_vfp_sp_conv_32 (void)
10006 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10011 do_vfp_dp_conv_32 (void)
10013 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10017 /* FPA instructions. Also in a logical order. */
10022 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10023 inst
.instruction
|= inst
.operands
[1].reg
;
10027 do_fpa_ldmstm (void)
10029 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10030 switch (inst
.operands
[1].imm
)
10032 case 1: inst
.instruction
|= CP_T_X
; break;
10033 case 2: inst
.instruction
|= CP_T_Y
; break;
10034 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10039 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10041 /* The instruction specified "ea" or "fd", so we can only accept
10042 [Rn]{!}. The instruction does not really support stacking or
10043 unstacking, so we have to emulate these by setting appropriate
10044 bits and offsets. */
10045 constraint (inst
.reloc
.exp
.X_op
!= O_constant
10046 || inst
.reloc
.exp
.X_add_number
!= 0,
10047 _("this instruction does not support indexing"));
10049 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10050 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10052 if (!(inst
.instruction
& INDEX_UP
))
10053 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
10055 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10057 inst
.operands
[2].preind
= 0;
10058 inst
.operands
[2].postind
= 1;
10062 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10065 /* iWMMXt instructions: strictly in alphabetical order. */
10068 do_iwmmxt_tandorc (void)
10070 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10074 do_iwmmxt_textrc (void)
10076 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10077 inst
.instruction
|= inst
.operands
[1].imm
;
10081 do_iwmmxt_textrm (void)
10083 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10084 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10085 inst
.instruction
|= inst
.operands
[2].imm
;
10089 do_iwmmxt_tinsr (void)
10091 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10092 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10093 inst
.instruction
|= inst
.operands
[2].imm
;
10097 do_iwmmxt_tmia (void)
10099 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10100 inst
.instruction
|= inst
.operands
[1].reg
;
10101 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10105 do_iwmmxt_waligni (void)
10107 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10108 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10109 inst
.instruction
|= inst
.operands
[2].reg
;
10110 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10114 do_iwmmxt_wmerge (void)
10116 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10117 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10118 inst
.instruction
|= inst
.operands
[2].reg
;
10119 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10123 do_iwmmxt_wmov (void)
10125 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10126 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10127 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10128 inst
.instruction
|= inst
.operands
[1].reg
;
10132 do_iwmmxt_wldstbh (void)
10135 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10137 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10139 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10140 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10144 do_iwmmxt_wldstw (void)
10146 /* RIWR_RIWC clears .isreg for a control register. */
10147 if (!inst
.operands
[0].isreg
)
10149 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10150 inst
.instruction
|= 0xf0000000;
10153 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10154 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10158 do_iwmmxt_wldstd (void)
10160 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10161 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10162 && inst
.operands
[1].immisreg
)
10164 inst
.instruction
&= ~0x1a000ff;
10165 inst
.instruction
|= (0xfU
<< 28);
10166 if (inst
.operands
[1].preind
)
10167 inst
.instruction
|= PRE_INDEX
;
10168 if (!inst
.operands
[1].negative
)
10169 inst
.instruction
|= INDEX_UP
;
10170 if (inst
.operands
[1].writeback
)
10171 inst
.instruction
|= WRITE_BACK
;
10172 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10173 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10174 inst
.instruction
|= inst
.operands
[1].imm
;
10177 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10181 do_iwmmxt_wshufh (void)
10183 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10184 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10185 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10186 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10190 do_iwmmxt_wzero (void)
10192 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10193 inst
.instruction
|= inst
.operands
[0].reg
;
10194 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10195 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10199 do_iwmmxt_wrwrwr_or_imm5 (void)
10201 if (inst
.operands
[2].isreg
)
10204 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10205 _("immediate operand requires iWMMXt2"));
10207 if (inst
.operands
[2].imm
== 0)
10209 switch ((inst
.instruction
>> 20) & 0xf)
10215 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10216 inst
.operands
[2].imm
= 16;
10217 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10223 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10224 inst
.operands
[2].imm
= 32;
10225 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10232 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10234 wrn
= (inst
.instruction
>> 16) & 0xf;
10235 inst
.instruction
&= 0xff0fff0f;
10236 inst
.instruction
|= wrn
;
10237 /* Bail out here; the instruction is now assembled. */
10242 /* Map 32 -> 0, etc. */
10243 inst
.operands
[2].imm
&= 0x1f;
10244 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10248 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10249 operations first, then control, shift, and load/store. */
10251 /* Insns like "foo X,Y,Z". */
10254 do_mav_triple (void)
10256 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10257 inst
.instruction
|= inst
.operands
[1].reg
;
10258 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10261 /* Insns like "foo W,X,Y,Z".
10262 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10267 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10268 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10269 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10270 inst
.instruction
|= inst
.operands
[3].reg
;
10273 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10275 do_mav_dspsc (void)
10277 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10280 /* Maverick shift immediate instructions.
10281 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10282 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10285 do_mav_shift (void)
10287 int imm
= inst
.operands
[2].imm
;
10289 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10290 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10292 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10293 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10294 Bit 4 should be 0. */
10295 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10297 inst
.instruction
|= imm
;
10300 /* XScale instructions. Also sorted arithmetic before move. */
10302 /* Xscale multiply-accumulate (argument parse)
10305 MIAxycc acc0,Rm,Rs. */
10310 inst
.instruction
|= inst
.operands
[1].reg
;
10311 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10314 /* Xscale move-accumulator-register (argument parse)
10316 MARcc acc0,RdLo,RdHi. */
10321 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10322 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10325 /* Xscale move-register-accumulator (argument parse)
10327 MRAcc RdLo,RdHi,acc0. */
10332 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10333 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10334 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10337 /* Encoding functions relevant only to Thumb. */
10339 /* inst.operands[i] is a shifted-register operand; encode
10340 it into inst.instruction in the format used by Thumb32. */
10343 encode_thumb32_shifted_operand (int i
)
10345 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10346 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10348 constraint (inst
.operands
[i
].immisreg
,
10349 _("shift by register not allowed in thumb mode"));
10350 inst
.instruction
|= inst
.operands
[i
].reg
;
10351 if (shift
== SHIFT_RRX
)
10352 inst
.instruction
|= SHIFT_ROR
<< 4;
10355 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10356 _("expression too complex"));
10358 constraint (value
> 32
10359 || (value
== 32 && (shift
== SHIFT_LSL
10360 || shift
== SHIFT_ROR
)),
10361 _("shift expression is too large"));
10365 else if (value
== 32)
10368 inst
.instruction
|= shift
<< 4;
10369 inst
.instruction
|= (value
& 0x1c) << 10;
10370 inst
.instruction
|= (value
& 0x03) << 6;
10375 /* inst.operands[i] was set up by parse_address. Encode it into a
10376 Thumb32 format load or store instruction. Reject forms that cannot
10377 be used with such instructions. If is_t is true, reject forms that
10378 cannot be used with a T instruction; if is_d is true, reject forms
10379 that cannot be used with a D instruction. If it is a store insn,
10380 reject PC in Rn. */
10383 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10385 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10387 constraint (!inst
.operands
[i
].isreg
,
10388 _("Instruction does not support =N addresses"));
10390 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10391 if (inst
.operands
[i
].immisreg
)
10393 constraint (is_pc
, BAD_PC_ADDRESSING
);
10394 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10395 constraint (inst
.operands
[i
].negative
,
10396 _("Thumb does not support negative register indexing"));
10397 constraint (inst
.operands
[i
].postind
,
10398 _("Thumb does not support register post-indexing"));
10399 constraint (inst
.operands
[i
].writeback
,
10400 _("Thumb does not support register indexing with writeback"));
10401 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10402 _("Thumb supports only LSL in shifted register indexing"));
10404 inst
.instruction
|= inst
.operands
[i
].imm
;
10405 if (inst
.operands
[i
].shifted
)
10407 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10408 _("expression too complex"));
10409 constraint (inst
.reloc
.exp
.X_add_number
< 0
10410 || inst
.reloc
.exp
.X_add_number
> 3,
10411 _("shift out of range"));
10412 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10414 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10416 else if (inst
.operands
[i
].preind
)
10418 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10419 constraint (is_t
&& inst
.operands
[i
].writeback
,
10420 _("cannot use writeback with this instruction"));
10421 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10422 BAD_PC_ADDRESSING
);
10426 inst
.instruction
|= 0x01000000;
10427 if (inst
.operands
[i
].writeback
)
10428 inst
.instruction
|= 0x00200000;
10432 inst
.instruction
|= 0x00000c00;
10433 if (inst
.operands
[i
].writeback
)
10434 inst
.instruction
|= 0x00000100;
10436 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10438 else if (inst
.operands
[i
].postind
)
10440 gas_assert (inst
.operands
[i
].writeback
);
10441 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10442 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10445 inst
.instruction
|= 0x00200000;
10447 inst
.instruction
|= 0x00000900;
10448 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10450 else /* unindexed - only for coprocessor */
10451 inst
.error
= _("instruction does not accept unindexed addressing");
10454 /* Table of Thumb instructions which exist in both 16- and 32-bit
10455 encodings (the latter only in post-V6T2 cores). The index is the
10456 value used in the insns table below. When there is more than one
10457 possible 16-bit encoding for the instruction, this table always
10459 Also contains several pseudo-instructions used during relaxation. */
10460 #define T16_32_TAB \
10461 X(_adc, 4140, eb400000), \
10462 X(_adcs, 4140, eb500000), \
10463 X(_add, 1c00, eb000000), \
10464 X(_adds, 1c00, eb100000), \
10465 X(_addi, 0000, f1000000), \
10466 X(_addis, 0000, f1100000), \
10467 X(_add_pc,000f, f20f0000), \
10468 X(_add_sp,000d, f10d0000), \
10469 X(_adr, 000f, f20f0000), \
10470 X(_and, 4000, ea000000), \
10471 X(_ands, 4000, ea100000), \
10472 X(_asr, 1000, fa40f000), \
10473 X(_asrs, 1000, fa50f000), \
10474 X(_b, e000, f000b000), \
10475 X(_bcond, d000, f0008000), \
10476 X(_bic, 4380, ea200000), \
10477 X(_bics, 4380, ea300000), \
10478 X(_cmn, 42c0, eb100f00), \
10479 X(_cmp, 2800, ebb00f00), \
10480 X(_cpsie, b660, f3af8400), \
10481 X(_cpsid, b670, f3af8600), \
10482 X(_cpy, 4600, ea4f0000), \
10483 X(_dec_sp,80dd, f1ad0d00), \
10484 X(_eor, 4040, ea800000), \
10485 X(_eors, 4040, ea900000), \
10486 X(_inc_sp,00dd, f10d0d00), \
10487 X(_ldmia, c800, e8900000), \
10488 X(_ldr, 6800, f8500000), \
10489 X(_ldrb, 7800, f8100000), \
10490 X(_ldrh, 8800, f8300000), \
10491 X(_ldrsb, 5600, f9100000), \
10492 X(_ldrsh, 5e00, f9300000), \
10493 X(_ldr_pc,4800, f85f0000), \
10494 X(_ldr_pc2,4800, f85f0000), \
10495 X(_ldr_sp,9800, f85d0000), \
10496 X(_lsl, 0000, fa00f000), \
10497 X(_lsls, 0000, fa10f000), \
10498 X(_lsr, 0800, fa20f000), \
10499 X(_lsrs, 0800, fa30f000), \
10500 X(_mov, 2000, ea4f0000), \
10501 X(_movs, 2000, ea5f0000), \
10502 X(_mul, 4340, fb00f000), \
10503 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10504 X(_mvn, 43c0, ea6f0000), \
10505 X(_mvns, 43c0, ea7f0000), \
10506 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10507 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10508 X(_orr, 4300, ea400000), \
10509 X(_orrs, 4300, ea500000), \
10510 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10511 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10512 X(_rev, ba00, fa90f080), \
10513 X(_rev16, ba40, fa90f090), \
10514 X(_revsh, bac0, fa90f0b0), \
10515 X(_ror, 41c0, fa60f000), \
10516 X(_rors, 41c0, fa70f000), \
10517 X(_sbc, 4180, eb600000), \
10518 X(_sbcs, 4180, eb700000), \
10519 X(_stmia, c000, e8800000), \
10520 X(_str, 6000, f8400000), \
10521 X(_strb, 7000, f8000000), \
10522 X(_strh, 8000, f8200000), \
10523 X(_str_sp,9000, f84d0000), \
10524 X(_sub, 1e00, eba00000), \
10525 X(_subs, 1e00, ebb00000), \
10526 X(_subi, 8000, f1a00000), \
10527 X(_subis, 8000, f1b00000), \
10528 X(_sxtb, b240, fa4ff080), \
10529 X(_sxth, b200, fa0ff080), \
10530 X(_tst, 4200, ea100f00), \
10531 X(_uxtb, b2c0, fa5ff080), \
10532 X(_uxth, b280, fa1ff080), \
10533 X(_nop, bf00, f3af8000), \
10534 X(_yield, bf10, f3af8001), \
10535 X(_wfe, bf20, f3af8002), \
10536 X(_wfi, bf30, f3af8003), \
10537 X(_sev, bf40, f3af8004), \
10538 X(_sevl, bf50, f3af8005), \
10539 X(_udf, de00, f7f0a000)
10541 /* To catch errors in encoding functions, the codes are all offset by
10542 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10543 as 16-bit instructions. */
10544 #define X(a,b,c) T_MNEM##a
10545 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10548 #define X(a,b,c) 0x##b
10549 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10550 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10553 #define X(a,b,c) 0x##c
10554 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10555 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10556 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10560 /* Thumb instruction encoders, in alphabetical order. */
10562 /* ADDW or SUBW. */
10565 do_t_add_sub_w (void)
10569 Rd
= inst
.operands
[0].reg
;
10570 Rn
= inst
.operands
[1].reg
;
10572 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10573 is the SP-{plus,minus}-immediate form of the instruction. */
10575 constraint (Rd
== REG_PC
, BAD_PC
);
10577 reject_bad_reg (Rd
);
10579 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10580 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10583 /* Parse an add or subtract instruction. We get here with inst.instruction
10584 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
10587 do_t_add_sub (void)
10591 Rd
= inst
.operands
[0].reg
;
10592 Rs
= (inst
.operands
[1].present
10593 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10594 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10597 set_it_insn_type_last ();
10599 if (unified_syntax
)
10602 bfd_boolean narrow
;
10605 flags
= (inst
.instruction
== T_MNEM_adds
10606 || inst
.instruction
== T_MNEM_subs
);
10608 narrow
= !in_it_block ();
10610 narrow
= in_it_block ();
10611 if (!inst
.operands
[2].isreg
)
10615 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10616 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10618 add
= (inst
.instruction
== T_MNEM_add
10619 || inst
.instruction
== T_MNEM_adds
);
10621 if (inst
.size_req
!= 4)
10623 /* Attempt to use a narrow opcode, with relaxation if
10625 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10626 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10627 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10628 opcode
= T_MNEM_add_sp
;
10629 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10630 opcode
= T_MNEM_add_pc
;
10631 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10634 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10636 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10640 inst
.instruction
= THUMB_OP16(opcode
);
10641 inst
.instruction
|= (Rd
<< 4) | Rs
;
10642 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10643 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10645 if (inst
.size_req
== 2)
10646 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10648 inst
.relax
= opcode
;
10652 constraint (inst
.size_req
== 2, BAD_HIREG
);
10654 if (inst
.size_req
== 4
10655 || (inst
.size_req
!= 2 && !opcode
))
10657 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10658 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10659 THUMB1_RELOC_ONLY
);
10662 constraint (add
, BAD_PC
);
10663 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10664 _("only SUBS PC, LR, #const allowed"));
10665 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10666 _("expression too complex"));
10667 constraint (inst
.reloc
.exp
.X_add_number
< 0
10668 || inst
.reloc
.exp
.X_add_number
> 0xff,
10669 _("immediate value out of range"));
10670 inst
.instruction
= T2_SUBS_PC_LR
10671 | inst
.reloc
.exp
.X_add_number
;
10672 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10675 else if (Rs
== REG_PC
)
10677 /* Always use addw/subw. */
10678 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10679 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10683 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10684 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10687 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10689 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10691 inst
.instruction
|= Rd
<< 8;
10692 inst
.instruction
|= Rs
<< 16;
10697 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10698 unsigned int shift
= inst
.operands
[2].shift_kind
;
10700 Rn
= inst
.operands
[2].reg
;
10701 /* See if we can do this with a 16-bit instruction. */
10702 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10704 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10709 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10710 || inst
.instruction
== T_MNEM_add
)
10712 : T_OPCODE_SUB_R3
);
10713 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10717 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10719 /* Thumb-1 cores (except v6-M) require at least one high
10720 register in a narrow non flag setting add. */
10721 if (Rd
> 7 || Rn
> 7
10722 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10723 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10730 inst
.instruction
= T_OPCODE_ADD_HI
;
10731 inst
.instruction
|= (Rd
& 8) << 4;
10732 inst
.instruction
|= (Rd
& 7);
10733 inst
.instruction
|= Rn
<< 3;
10739 constraint (Rd
== REG_PC
, BAD_PC
);
10740 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10741 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10742 constraint (Rs
== REG_PC
, BAD_PC
);
10743 reject_bad_reg (Rn
);
10745 /* If we get here, it can't be done in 16 bits. */
10746 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10747 _("shift must be constant"));
10748 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10749 inst
.instruction
|= Rd
<< 8;
10750 inst
.instruction
|= Rs
<< 16;
10751 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10752 _("shift value over 3 not allowed in thumb mode"));
10753 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10754 _("only LSL shift allowed in thumb mode"));
10755 encode_thumb32_shifted_operand (2);
10760 constraint (inst
.instruction
== T_MNEM_adds
10761 || inst
.instruction
== T_MNEM_subs
,
10764 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10766 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10767 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10770 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10771 ? 0x0000 : 0x8000);
10772 inst
.instruction
|= (Rd
<< 4) | Rs
;
10773 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10777 Rn
= inst
.operands
[2].reg
;
10778 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10780 /* We now have Rd, Rs, and Rn set to registers. */
10781 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10783 /* Can't do this for SUB. */
10784 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10785 inst
.instruction
= T_OPCODE_ADD_HI
;
10786 inst
.instruction
|= (Rd
& 8) << 4;
10787 inst
.instruction
|= (Rd
& 7);
10789 inst
.instruction
|= Rn
<< 3;
10791 inst
.instruction
|= Rs
<< 3;
10793 constraint (1, _("dest must overlap one source register"));
10797 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10798 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10799 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10809 Rd
= inst
.operands
[0].reg
;
10810 reject_bad_reg (Rd
);
10812 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10814 /* Defer to section relaxation. */
10815 inst
.relax
= inst
.instruction
;
10816 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10817 inst
.instruction
|= Rd
<< 4;
10819 else if (unified_syntax
&& inst
.size_req
!= 2)
10821 /* Generate a 32-bit opcode. */
10822 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10823 inst
.instruction
|= Rd
<< 8;
10824 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10825 inst
.reloc
.pc_rel
= 1;
10829 /* Generate a 16-bit opcode. */
10830 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10831 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10832 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10833 inst
.reloc
.pc_rel
= 1;
10834 inst
.instruction
|= Rd
<< 4;
10837 if (inst
.reloc
.exp
.X_op
== O_symbol
10838 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10839 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10840 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10841 inst
.reloc
.exp
.X_add_number
+= 1;
10844 /* Arithmetic instructions for which there is just one 16-bit
10845 instruction encoding, and it allows only two low registers.
10846 For maximal compatibility with ARM syntax, we allow three register
10847 operands even when Thumb-32 instructions are not available, as long
10848 as the first two are identical. For instance, both "sbc r0,r1" and
10849 "sbc r0,r0,r1" are allowed. */
10855 Rd
= inst
.operands
[0].reg
;
10856 Rs
= (inst
.operands
[1].present
10857 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10858 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10859 Rn
= inst
.operands
[2].reg
;
10861 reject_bad_reg (Rd
);
10862 reject_bad_reg (Rs
);
10863 if (inst
.operands
[2].isreg
)
10864 reject_bad_reg (Rn
);
10866 if (unified_syntax
)
10868 if (!inst
.operands
[2].isreg
)
10870 /* For an immediate, we always generate a 32-bit opcode;
10871 section relaxation will shrink it later if possible. */
10872 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10873 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10874 inst
.instruction
|= Rd
<< 8;
10875 inst
.instruction
|= Rs
<< 16;
10876 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10880 bfd_boolean narrow
;
10882 /* See if we can do this with a 16-bit instruction. */
10883 if (THUMB_SETS_FLAGS (inst
.instruction
))
10884 narrow
= !in_it_block ();
10886 narrow
= in_it_block ();
10888 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10890 if (inst
.operands
[2].shifted
)
10892 if (inst
.size_req
== 4)
10898 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10899 inst
.instruction
|= Rd
;
10900 inst
.instruction
|= Rn
<< 3;
10904 /* If we get here, it can't be done in 16 bits. */
10905 constraint (inst
.operands
[2].shifted
10906 && inst
.operands
[2].immisreg
,
10907 _("shift must be constant"));
10908 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10909 inst
.instruction
|= Rd
<< 8;
10910 inst
.instruction
|= Rs
<< 16;
10911 encode_thumb32_shifted_operand (2);
10916 /* On its face this is a lie - the instruction does set the
10917 flags. However, the only supported mnemonic in this mode
10918 says it doesn't. */
10919 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10921 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10922 _("unshifted register required"));
10923 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10924 constraint (Rd
!= Rs
,
10925 _("dest and source1 must be the same register"));
10927 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10928 inst
.instruction
|= Rd
;
10929 inst
.instruction
|= Rn
<< 3;
10933 /* Similarly, but for instructions where the arithmetic operation is
10934 commutative, so we can allow either of them to be different from
10935 the destination operand in a 16-bit instruction. For instance, all
10936 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10943 Rd
= inst
.operands
[0].reg
;
10944 Rs
= (inst
.operands
[1].present
10945 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10946 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10947 Rn
= inst
.operands
[2].reg
;
10949 reject_bad_reg (Rd
);
10950 reject_bad_reg (Rs
);
10951 if (inst
.operands
[2].isreg
)
10952 reject_bad_reg (Rn
);
10954 if (unified_syntax
)
10956 if (!inst
.operands
[2].isreg
)
10958 /* For an immediate, we always generate a 32-bit opcode;
10959 section relaxation will shrink it later if possible. */
10960 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10961 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10962 inst
.instruction
|= Rd
<< 8;
10963 inst
.instruction
|= Rs
<< 16;
10964 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10968 bfd_boolean narrow
;
10970 /* See if we can do this with a 16-bit instruction. */
10971 if (THUMB_SETS_FLAGS (inst
.instruction
))
10972 narrow
= !in_it_block ();
10974 narrow
= in_it_block ();
10976 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10978 if (inst
.operands
[2].shifted
)
10980 if (inst
.size_req
== 4)
10987 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10988 inst
.instruction
|= Rd
;
10989 inst
.instruction
|= Rn
<< 3;
10994 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10995 inst
.instruction
|= Rd
;
10996 inst
.instruction
|= Rs
<< 3;
11001 /* If we get here, it can't be done in 16 bits. */
11002 constraint (inst
.operands
[2].shifted
11003 && inst
.operands
[2].immisreg
,
11004 _("shift must be constant"));
11005 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11006 inst
.instruction
|= Rd
<< 8;
11007 inst
.instruction
|= Rs
<< 16;
11008 encode_thumb32_shifted_operand (2);
11013 /* On its face this is a lie - the instruction does set the
11014 flags. However, the only supported mnemonic in this mode
11015 says it doesn't. */
11016 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11018 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11019 _("unshifted register required"));
11020 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11022 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11023 inst
.instruction
|= Rd
;
11026 inst
.instruction
|= Rn
<< 3;
11028 inst
.instruction
|= Rs
<< 3;
11030 constraint (1, _("dest must overlap one source register"));
11038 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11039 constraint (msb
> 32, _("bit-field extends past end of register"));
11040 /* The instruction encoding stores the LSB and MSB,
11041 not the LSB and width. */
11042 Rd
= inst
.operands
[0].reg
;
11043 reject_bad_reg (Rd
);
11044 inst
.instruction
|= Rd
<< 8;
11045 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11046 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11047 inst
.instruction
|= msb
- 1;
11056 Rd
= inst
.operands
[0].reg
;
11057 reject_bad_reg (Rd
);
11059 /* #0 in second position is alternative syntax for bfc, which is
11060 the same instruction but with REG_PC in the Rm field. */
11061 if (!inst
.operands
[1].isreg
)
11065 Rn
= inst
.operands
[1].reg
;
11066 reject_bad_reg (Rn
);
11069 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11070 constraint (msb
> 32, _("bit-field extends past end of register"));
11071 /* The instruction encoding stores the LSB and MSB,
11072 not the LSB and width. */
11073 inst
.instruction
|= Rd
<< 8;
11074 inst
.instruction
|= Rn
<< 16;
11075 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11076 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11077 inst
.instruction
|= msb
- 1;
11085 Rd
= inst
.operands
[0].reg
;
11086 Rn
= inst
.operands
[1].reg
;
11088 reject_bad_reg (Rd
);
11089 reject_bad_reg (Rn
);
11091 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11092 _("bit-field extends past end of register"));
11093 inst
.instruction
|= Rd
<< 8;
11094 inst
.instruction
|= Rn
<< 16;
11095 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11096 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11097 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11100 /* ARM V5 Thumb BLX (argument parse)
11101 BLX <target_addr> which is BLX(1)
11102 BLX <Rm> which is BLX(2)
11103 Unfortunately, there are two different opcodes for this mnemonic.
11104 So, the insns[].value is not used, and the code here zaps values
11105 into inst.instruction.
11107 ??? How to take advantage of the additional two bits of displacement
11108 available in Thumb32 mode? Need new relocation? */
11113 set_it_insn_type_last ();
11115 if (inst
.operands
[0].isreg
)
11117 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11118 /* We have a register, so this is BLX(2). */
11119 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11123 /* No register. This must be BLX(1). */
11124 inst
.instruction
= 0xf000e800;
11125 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11134 bfd_reloc_code_real_type reloc
;
11137 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11139 if (in_it_block ())
11141 /* Conditional branches inside IT blocks are encoded as unconditional
11143 cond
= COND_ALWAYS
;
11148 if (cond
!= COND_ALWAYS
)
11149 opcode
= T_MNEM_bcond
;
11151 opcode
= inst
.instruction
;
11154 && (inst
.size_req
== 4
11155 || (inst
.size_req
!= 2
11156 && (inst
.operands
[0].hasreloc
11157 || inst
.reloc
.exp
.X_op
== O_constant
))))
11159 inst
.instruction
= THUMB_OP32(opcode
);
11160 if (cond
== COND_ALWAYS
)
11161 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11164 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11165 _("selected architecture does not support "
11166 "wide conditional branch instruction"));
11168 gas_assert (cond
!= 0xF);
11169 inst
.instruction
|= cond
<< 22;
11170 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11175 inst
.instruction
= THUMB_OP16(opcode
);
11176 if (cond
== COND_ALWAYS
)
11177 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11180 inst
.instruction
|= cond
<< 8;
11181 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11183 /* Allow section relaxation. */
11184 if (unified_syntax
&& inst
.size_req
!= 2)
11185 inst
.relax
= opcode
;
11187 inst
.reloc
.type
= reloc
;
11188 inst
.reloc
.pc_rel
= 1;
11191 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11192 between the two is the maximum immediate allowed - which is passed in
11195 do_t_bkpt_hlt1 (int range
)
11197 constraint (inst
.cond
!= COND_ALWAYS
,
11198 _("instruction is always unconditional"));
11199 if (inst
.operands
[0].present
)
11201 constraint (inst
.operands
[0].imm
> range
,
11202 _("immediate value out of range"));
11203 inst
.instruction
|= inst
.operands
[0].imm
;
11206 set_it_insn_type (NEUTRAL_IT_INSN
);
11212 do_t_bkpt_hlt1 (63);
11218 do_t_bkpt_hlt1 (255);
11222 do_t_branch23 (void)
11224 set_it_insn_type_last ();
11225 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11227 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11228 this file. We used to simply ignore the PLT reloc type here --
11229 the branch encoding is now needed to deal with TLSCALL relocs.
11230 So if we see a PLT reloc now, put it back to how it used to be to
11231 keep the preexisting behaviour. */
11232 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11233 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11235 #if defined(OBJ_COFF)
11236 /* If the destination of the branch is a defined symbol which does not have
11237 the THUMB_FUNC attribute, then we must be calling a function which has
11238 the (interfacearm) attribute. We look for the Thumb entry point to that
11239 function and change the branch to refer to that function instead. */
11240 if ( inst
.reloc
.exp
.X_op
== O_symbol
11241 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11242 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11243 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11244 inst
.reloc
.exp
.X_add_symbol
=
11245 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11252 set_it_insn_type_last ();
11253 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11254 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11255 should cause the alignment to be checked once it is known. This is
11256 because BX PC only works if the instruction is word aligned. */
11264 set_it_insn_type_last ();
11265 Rm
= inst
.operands
[0].reg
;
11266 reject_bad_reg (Rm
);
11267 inst
.instruction
|= Rm
<< 16;
11276 Rd
= inst
.operands
[0].reg
;
11277 Rm
= inst
.operands
[1].reg
;
11279 reject_bad_reg (Rd
);
11280 reject_bad_reg (Rm
);
11282 inst
.instruction
|= Rd
<< 8;
11283 inst
.instruction
|= Rm
<< 16;
11284 inst
.instruction
|= Rm
;
11290 set_it_insn_type (OUTSIDE_IT_INSN
);
11296 set_it_insn_type (OUTSIDE_IT_INSN
);
11297 inst
.instruction
|= inst
.operands
[0].imm
;
11303 set_it_insn_type (OUTSIDE_IT_INSN
);
11305 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11306 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11308 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11309 inst
.instruction
= 0xf3af8000;
11310 inst
.instruction
|= imod
<< 9;
11311 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11312 if (inst
.operands
[1].present
)
11313 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11317 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11318 && (inst
.operands
[0].imm
& 4),
11319 _("selected processor does not support 'A' form "
11320 "of this instruction"));
11321 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11322 _("Thumb does not support the 2-argument "
11323 "form of this instruction"));
11324 inst
.instruction
|= inst
.operands
[0].imm
;
11328 /* THUMB CPY instruction (argument parse). */
11333 if (inst
.size_req
== 4)
11335 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11336 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11337 inst
.instruction
|= inst
.operands
[1].reg
;
11341 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11342 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11343 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11350 set_it_insn_type (OUTSIDE_IT_INSN
);
11351 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11352 inst
.instruction
|= inst
.operands
[0].reg
;
11353 inst
.reloc
.pc_rel
= 1;
11354 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11360 inst
.instruction
|= inst
.operands
[0].imm
;
11366 unsigned Rd
, Rn
, Rm
;
11368 Rd
= inst
.operands
[0].reg
;
11369 Rn
= (inst
.operands
[1].present
11370 ? inst
.operands
[1].reg
: Rd
);
11371 Rm
= inst
.operands
[2].reg
;
11373 reject_bad_reg (Rd
);
11374 reject_bad_reg (Rn
);
11375 reject_bad_reg (Rm
);
11377 inst
.instruction
|= Rd
<< 8;
11378 inst
.instruction
|= Rn
<< 16;
11379 inst
.instruction
|= Rm
;
11385 if (unified_syntax
&& inst
.size_req
== 4)
11386 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11388 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11394 unsigned int cond
= inst
.operands
[0].imm
;
11396 set_it_insn_type (IT_INSN
);
11397 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11399 now_it
.warn_deprecated
= FALSE
;
11401 /* If the condition is a negative condition, invert the mask. */
11402 if ((cond
& 0x1) == 0x0)
11404 unsigned int mask
= inst
.instruction
& 0x000f;
11406 if ((mask
& 0x7) == 0)
11408 /* No conversion needed. */
11409 now_it
.block_length
= 1;
11411 else if ((mask
& 0x3) == 0)
11414 now_it
.block_length
= 2;
11416 else if ((mask
& 0x1) == 0)
11419 now_it
.block_length
= 3;
11424 now_it
.block_length
= 4;
11427 inst
.instruction
&= 0xfff0;
11428 inst
.instruction
|= mask
;
11431 inst
.instruction
|= cond
<< 4;
11434 /* Helper function used for both push/pop and ldm/stm. */
11436 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11440 load
= (inst
.instruction
& (1 << 20)) != 0;
11442 if (mask
& (1 << 13))
11443 inst
.error
= _("SP not allowed in register list");
11445 if ((mask
& (1 << base
)) != 0
11447 inst
.error
= _("having the base register in the register list when "
11448 "using write back is UNPREDICTABLE");
11452 if (mask
& (1 << 15))
11454 if (mask
& (1 << 14))
11455 inst
.error
= _("LR and PC should not both be in register list");
11457 set_it_insn_type_last ();
11462 if (mask
& (1 << 15))
11463 inst
.error
= _("PC not allowed in register list");
11466 if ((mask
& (mask
- 1)) == 0)
11468 /* Single register transfers implemented as str/ldr. */
11471 if (inst
.instruction
& (1 << 23))
11472 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11474 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11478 if (inst
.instruction
& (1 << 23))
11479 inst
.instruction
= 0x00800000; /* ia -> [base] */
11481 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11484 inst
.instruction
|= 0xf8400000;
11486 inst
.instruction
|= 0x00100000;
11488 mask
= ffs (mask
) - 1;
11491 else if (writeback
)
11492 inst
.instruction
|= WRITE_BACK
;
11494 inst
.instruction
|= mask
;
11495 inst
.instruction
|= base
<< 16;
11501 /* This really doesn't seem worth it. */
11502 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11503 _("expression too complex"));
11504 constraint (inst
.operands
[1].writeback
,
11505 _("Thumb load/store multiple does not support {reglist}^"));
11507 if (unified_syntax
)
11509 bfd_boolean narrow
;
11513 /* See if we can use a 16-bit instruction. */
11514 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11515 && inst
.size_req
!= 4
11516 && !(inst
.operands
[1].imm
& ~0xff))
11518 mask
= 1 << inst
.operands
[0].reg
;
11520 if (inst
.operands
[0].reg
<= 7)
11522 if (inst
.instruction
== T_MNEM_stmia
11523 ? inst
.operands
[0].writeback
11524 : (inst
.operands
[0].writeback
11525 == !(inst
.operands
[1].imm
& mask
)))
11527 if (inst
.instruction
== T_MNEM_stmia
11528 && (inst
.operands
[1].imm
& mask
)
11529 && (inst
.operands
[1].imm
& (mask
- 1)))
11530 as_warn (_("value stored for r%d is UNKNOWN"),
11531 inst
.operands
[0].reg
);
11533 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11534 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11535 inst
.instruction
|= inst
.operands
[1].imm
;
11538 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11540 /* This means 1 register in reg list one of 3 situations:
11541 1. Instruction is stmia, but without writeback.
11542 2. lmdia without writeback, but with Rn not in
11544 3. ldmia with writeback, but with Rn in reglist.
11545 Case 3 is UNPREDICTABLE behaviour, so we handle
11546 case 1 and 2 which can be converted into a 16-bit
11547 str or ldr. The SP cases are handled below. */
11548 unsigned long opcode
;
11549 /* First, record an error for Case 3. */
11550 if (inst
.operands
[1].imm
& mask
11551 && inst
.operands
[0].writeback
)
11553 _("having the base register in the register list when "
11554 "using write back is UNPREDICTABLE");
11556 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11558 inst
.instruction
= THUMB_OP16 (opcode
);
11559 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11560 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11564 else if (inst
.operands
[0] .reg
== REG_SP
)
11566 if (inst
.operands
[0].writeback
)
11569 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11570 ? T_MNEM_push
: T_MNEM_pop
);
11571 inst
.instruction
|= inst
.operands
[1].imm
;
11574 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11577 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11578 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11579 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11587 if (inst
.instruction
< 0xffff)
11588 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11590 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11591 inst
.operands
[0].writeback
);
11596 constraint (inst
.operands
[0].reg
> 7
11597 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11598 constraint (inst
.instruction
!= T_MNEM_ldmia
11599 && inst
.instruction
!= T_MNEM_stmia
,
11600 _("Thumb-2 instruction only valid in unified syntax"));
11601 if (inst
.instruction
== T_MNEM_stmia
)
11603 if (!inst
.operands
[0].writeback
)
11604 as_warn (_("this instruction will write back the base register"));
11605 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11606 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11607 as_warn (_("value stored for r%d is UNKNOWN"),
11608 inst
.operands
[0].reg
);
11612 if (!inst
.operands
[0].writeback
11613 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11614 as_warn (_("this instruction will write back the base register"));
11615 else if (inst
.operands
[0].writeback
11616 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11617 as_warn (_("this instruction will not write back the base register"));
11620 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11621 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11622 inst
.instruction
|= inst
.operands
[1].imm
;
11629 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11630 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11631 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11632 || inst
.operands
[1].negative
,
11635 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11637 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11638 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11639 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11645 if (!inst
.operands
[1].present
)
11647 constraint (inst
.operands
[0].reg
== REG_LR
,
11648 _("r14 not allowed as first register "
11649 "when second register is omitted"));
11650 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11652 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11655 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11656 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11657 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11663 unsigned long opcode
;
11666 if (inst
.operands
[0].isreg
11667 && !inst
.operands
[0].preind
11668 && inst
.operands
[0].reg
== REG_PC
)
11669 set_it_insn_type_last ();
11671 opcode
= inst
.instruction
;
11672 if (unified_syntax
)
11674 if (!inst
.operands
[1].isreg
)
11676 if (opcode
<= 0xffff)
11677 inst
.instruction
= THUMB_OP32 (opcode
);
11678 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11681 if (inst
.operands
[1].isreg
11682 && !inst
.operands
[1].writeback
11683 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11684 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11685 && opcode
<= 0xffff
11686 && inst
.size_req
!= 4)
11688 /* Insn may have a 16-bit form. */
11689 Rn
= inst
.operands
[1].reg
;
11690 if (inst
.operands
[1].immisreg
)
11692 inst
.instruction
= THUMB_OP16 (opcode
);
11694 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11696 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11697 reject_bad_reg (inst
.operands
[1].imm
);
11699 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11700 && opcode
!= T_MNEM_ldrsb
)
11701 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11702 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11709 if (inst
.reloc
.pc_rel
)
11710 opcode
= T_MNEM_ldr_pc2
;
11712 opcode
= T_MNEM_ldr_pc
;
11716 if (opcode
== T_MNEM_ldr
)
11717 opcode
= T_MNEM_ldr_sp
;
11719 opcode
= T_MNEM_str_sp
;
11721 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11725 inst
.instruction
= inst
.operands
[0].reg
;
11726 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11728 inst
.instruction
|= THUMB_OP16 (opcode
);
11729 if (inst
.size_req
== 2)
11730 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11732 inst
.relax
= opcode
;
11736 /* Definitely a 32-bit variant. */
11738 /* Warning for Erratum 752419. */
11739 if (opcode
== T_MNEM_ldr
11740 && inst
.operands
[0].reg
== REG_SP
11741 && inst
.operands
[1].writeback
== 1
11742 && !inst
.operands
[1].immisreg
)
11744 if (no_cpu_selected ()
11745 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11746 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11747 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11748 as_warn (_("This instruction may be unpredictable "
11749 "if executed on M-profile cores "
11750 "with interrupts enabled."));
11753 /* Do some validations regarding addressing modes. */
11754 if (inst
.operands
[1].immisreg
)
11755 reject_bad_reg (inst
.operands
[1].imm
);
11757 constraint (inst
.operands
[1].writeback
== 1
11758 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11761 inst
.instruction
= THUMB_OP32 (opcode
);
11762 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11763 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11764 check_ldr_r15_aligned ();
11768 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11770 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11772 /* Only [Rn,Rm] is acceptable. */
11773 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11774 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11775 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11776 || inst
.operands
[1].negative
,
11777 _("Thumb does not support this addressing mode"));
11778 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11782 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11783 if (!inst
.operands
[1].isreg
)
11784 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11787 constraint (!inst
.operands
[1].preind
11788 || inst
.operands
[1].shifted
11789 || inst
.operands
[1].writeback
,
11790 _("Thumb does not support this addressing mode"));
11791 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11793 constraint (inst
.instruction
& 0x0600,
11794 _("byte or halfword not valid for base register"));
11795 constraint (inst
.operands
[1].reg
== REG_PC
11796 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11797 _("r15 based store not allowed"));
11798 constraint (inst
.operands
[1].immisreg
,
11799 _("invalid base register for register offset"));
11801 if (inst
.operands
[1].reg
== REG_PC
)
11802 inst
.instruction
= T_OPCODE_LDR_PC
;
11803 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11804 inst
.instruction
= T_OPCODE_LDR_SP
;
11806 inst
.instruction
= T_OPCODE_STR_SP
;
11808 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11809 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11813 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11814 if (!inst
.operands
[1].immisreg
)
11816 /* Immediate offset. */
11817 inst
.instruction
|= inst
.operands
[0].reg
;
11818 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11819 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11823 /* Register offset. */
11824 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11825 constraint (inst
.operands
[1].negative
,
11826 _("Thumb does not support this addressing mode"));
11829 switch (inst
.instruction
)
11831 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11832 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11833 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11834 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11835 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11836 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11837 case 0x5600 /* ldrsb */:
11838 case 0x5e00 /* ldrsh */: break;
11842 inst
.instruction
|= inst
.operands
[0].reg
;
11843 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11844 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11850 if (!inst
.operands
[1].present
)
11852 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11853 constraint (inst
.operands
[0].reg
== REG_LR
,
11854 _("r14 not allowed here"));
11855 constraint (inst
.operands
[0].reg
== REG_R12
,
11856 _("r12 not allowed here"));
11859 if (inst
.operands
[2].writeback
11860 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11861 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11862 as_warn (_("base register written back, and overlaps "
11863 "one of transfer registers"));
11865 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11866 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11867 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11873 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11874 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11880 unsigned Rd
, Rn
, Rm
, Ra
;
11882 Rd
= inst
.operands
[0].reg
;
11883 Rn
= inst
.operands
[1].reg
;
11884 Rm
= inst
.operands
[2].reg
;
11885 Ra
= inst
.operands
[3].reg
;
11887 reject_bad_reg (Rd
);
11888 reject_bad_reg (Rn
);
11889 reject_bad_reg (Rm
);
11890 reject_bad_reg (Ra
);
11892 inst
.instruction
|= Rd
<< 8;
11893 inst
.instruction
|= Rn
<< 16;
11894 inst
.instruction
|= Rm
;
11895 inst
.instruction
|= Ra
<< 12;
11901 unsigned RdLo
, RdHi
, Rn
, Rm
;
11903 RdLo
= inst
.operands
[0].reg
;
11904 RdHi
= inst
.operands
[1].reg
;
11905 Rn
= inst
.operands
[2].reg
;
11906 Rm
= inst
.operands
[3].reg
;
11908 reject_bad_reg (RdLo
);
11909 reject_bad_reg (RdHi
);
11910 reject_bad_reg (Rn
);
11911 reject_bad_reg (Rm
);
11913 inst
.instruction
|= RdLo
<< 12;
11914 inst
.instruction
|= RdHi
<< 8;
11915 inst
.instruction
|= Rn
<< 16;
11916 inst
.instruction
|= Rm
;
11920 do_t_mov_cmp (void)
11924 Rn
= inst
.operands
[0].reg
;
11925 Rm
= inst
.operands
[1].reg
;
11928 set_it_insn_type_last ();
11930 if (unified_syntax
)
11932 int r0off
= (inst
.instruction
== T_MNEM_mov
11933 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11934 unsigned long opcode
;
11935 bfd_boolean narrow
;
11936 bfd_boolean low_regs
;
11938 low_regs
= (Rn
<= 7 && Rm
<= 7);
11939 opcode
= inst
.instruction
;
11940 if (in_it_block ())
11941 narrow
= opcode
!= T_MNEM_movs
;
11943 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11944 if (inst
.size_req
== 4
11945 || inst
.operands
[1].shifted
)
11948 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11949 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11950 && !inst
.operands
[1].shifted
11954 inst
.instruction
= T2_SUBS_PC_LR
;
11958 if (opcode
== T_MNEM_cmp
)
11960 constraint (Rn
== REG_PC
, BAD_PC
);
11963 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11965 warn_deprecated_sp (Rm
);
11966 /* R15 was documented as a valid choice for Rm in ARMv6,
11967 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11968 tools reject R15, so we do too. */
11969 constraint (Rm
== REG_PC
, BAD_PC
);
11972 reject_bad_reg (Rm
);
11974 else if (opcode
== T_MNEM_mov
11975 || opcode
== T_MNEM_movs
)
11977 if (inst
.operands
[1].isreg
)
11979 if (opcode
== T_MNEM_movs
)
11981 reject_bad_reg (Rn
);
11982 reject_bad_reg (Rm
);
11986 /* This is mov.n. */
11987 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11988 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11990 as_tsktsk (_("Use of r%u as a source register is "
11991 "deprecated when r%u is the destination "
11992 "register."), Rm
, Rn
);
11997 /* This is mov.w. */
11998 constraint (Rn
== REG_PC
, BAD_PC
);
11999 constraint (Rm
== REG_PC
, BAD_PC
);
12000 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12001 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12005 reject_bad_reg (Rn
);
12008 if (!inst
.operands
[1].isreg
)
12010 /* Immediate operand. */
12011 if (!in_it_block () && opcode
== T_MNEM_mov
)
12013 if (low_regs
&& narrow
)
12015 inst
.instruction
= THUMB_OP16 (opcode
);
12016 inst
.instruction
|= Rn
<< 8;
12017 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12018 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12020 if (inst
.size_req
== 2)
12021 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12023 inst
.relax
= opcode
;
12028 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12029 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
12030 THUMB1_RELOC_ONLY
);
12032 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12033 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12034 inst
.instruction
|= Rn
<< r0off
;
12035 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12038 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12039 && (inst
.instruction
== T_MNEM_mov
12040 || inst
.instruction
== T_MNEM_movs
))
12042 /* Register shifts are encoded as separate shift instructions. */
12043 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12045 if (in_it_block ())
12050 if (inst
.size_req
== 4)
12053 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12059 switch (inst
.operands
[1].shift_kind
)
12062 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12065 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12068 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12071 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12077 inst
.instruction
= opcode
;
12080 inst
.instruction
|= Rn
;
12081 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12086 inst
.instruction
|= CONDS_BIT
;
12088 inst
.instruction
|= Rn
<< 8;
12089 inst
.instruction
|= Rm
<< 16;
12090 inst
.instruction
|= inst
.operands
[1].imm
;
12095 /* Some mov with immediate shift have narrow variants.
12096 Register shifts are handled above. */
12097 if (low_regs
&& inst
.operands
[1].shifted
12098 && (inst
.instruction
== T_MNEM_mov
12099 || inst
.instruction
== T_MNEM_movs
))
12101 if (in_it_block ())
12102 narrow
= (inst
.instruction
== T_MNEM_mov
);
12104 narrow
= (inst
.instruction
== T_MNEM_movs
);
12109 switch (inst
.operands
[1].shift_kind
)
12111 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12112 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12113 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12114 default: narrow
= FALSE
; break;
12120 inst
.instruction
|= Rn
;
12121 inst
.instruction
|= Rm
<< 3;
12122 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12126 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12127 inst
.instruction
|= Rn
<< r0off
;
12128 encode_thumb32_shifted_operand (1);
12132 switch (inst
.instruction
)
12135 /* In v4t or v5t a move of two lowregs produces unpredictable
12136 results. Don't allow this. */
12139 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12140 "MOV Rd, Rs with two low registers is not "
12141 "permitted on this architecture");
12142 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12146 inst
.instruction
= T_OPCODE_MOV_HR
;
12147 inst
.instruction
|= (Rn
& 0x8) << 4;
12148 inst
.instruction
|= (Rn
& 0x7);
12149 inst
.instruction
|= Rm
<< 3;
12153 /* We know we have low registers at this point.
12154 Generate LSLS Rd, Rs, #0. */
12155 inst
.instruction
= T_OPCODE_LSL_I
;
12156 inst
.instruction
|= Rn
;
12157 inst
.instruction
|= Rm
<< 3;
12163 inst
.instruction
= T_OPCODE_CMP_LR
;
12164 inst
.instruction
|= Rn
;
12165 inst
.instruction
|= Rm
<< 3;
12169 inst
.instruction
= T_OPCODE_CMP_HR
;
12170 inst
.instruction
|= (Rn
& 0x8) << 4;
12171 inst
.instruction
|= (Rn
& 0x7);
12172 inst
.instruction
|= Rm
<< 3;
12179 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12181 /* PR 10443: Do not silently ignore shifted operands. */
12182 constraint (inst
.operands
[1].shifted
,
12183 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12185 if (inst
.operands
[1].isreg
)
12187 if (Rn
< 8 && Rm
< 8)
12189 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12190 since a MOV instruction produces unpredictable results. */
12191 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12192 inst
.instruction
= T_OPCODE_ADD_I3
;
12194 inst
.instruction
= T_OPCODE_CMP_LR
;
12196 inst
.instruction
|= Rn
;
12197 inst
.instruction
|= Rm
<< 3;
12201 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12202 inst
.instruction
= T_OPCODE_MOV_HR
;
12204 inst
.instruction
= T_OPCODE_CMP_HR
;
12210 constraint (Rn
> 7,
12211 _("only lo regs allowed with immediate"));
12212 inst
.instruction
|= Rn
<< 8;
12213 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12224 top
= (inst
.instruction
& 0x00800000) != 0;
12225 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12227 constraint (top
, _(":lower16: not allowed in this instruction"));
12228 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12230 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12232 constraint (!top
, _(":upper16: not allowed in this instruction"));
12233 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12236 Rd
= inst
.operands
[0].reg
;
12237 reject_bad_reg (Rd
);
12239 inst
.instruction
|= Rd
<< 8;
12240 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12242 imm
= inst
.reloc
.exp
.X_add_number
;
12243 inst
.instruction
|= (imm
& 0xf000) << 4;
12244 inst
.instruction
|= (imm
& 0x0800) << 15;
12245 inst
.instruction
|= (imm
& 0x0700) << 4;
12246 inst
.instruction
|= (imm
& 0x00ff);
12251 do_t_mvn_tst (void)
12255 Rn
= inst
.operands
[0].reg
;
12256 Rm
= inst
.operands
[1].reg
;
12258 if (inst
.instruction
== T_MNEM_cmp
12259 || inst
.instruction
== T_MNEM_cmn
)
12260 constraint (Rn
== REG_PC
, BAD_PC
);
12262 reject_bad_reg (Rn
);
12263 reject_bad_reg (Rm
);
12265 if (unified_syntax
)
12267 int r0off
= (inst
.instruction
== T_MNEM_mvn
12268 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12269 bfd_boolean narrow
;
12271 if (inst
.size_req
== 4
12272 || inst
.instruction
> 0xffff
12273 || inst
.operands
[1].shifted
12274 || Rn
> 7 || Rm
> 7)
12276 else if (inst
.instruction
== T_MNEM_cmn
12277 || inst
.instruction
== T_MNEM_tst
)
12279 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12280 narrow
= !in_it_block ();
12282 narrow
= in_it_block ();
12284 if (!inst
.operands
[1].isreg
)
12286 /* For an immediate, we always generate a 32-bit opcode;
12287 section relaxation will shrink it later if possible. */
12288 if (inst
.instruction
< 0xffff)
12289 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12290 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12291 inst
.instruction
|= Rn
<< r0off
;
12292 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12296 /* See if we can do this with a 16-bit instruction. */
12299 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12300 inst
.instruction
|= Rn
;
12301 inst
.instruction
|= Rm
<< 3;
12305 constraint (inst
.operands
[1].shifted
12306 && inst
.operands
[1].immisreg
,
12307 _("shift must be constant"));
12308 if (inst
.instruction
< 0xffff)
12309 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12310 inst
.instruction
|= Rn
<< r0off
;
12311 encode_thumb32_shifted_operand (1);
12317 constraint (inst
.instruction
> 0xffff
12318 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12319 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12320 _("unshifted register required"));
12321 constraint (Rn
> 7 || Rm
> 7,
12324 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12325 inst
.instruction
|= Rn
;
12326 inst
.instruction
|= Rm
<< 3;
12335 if (do_vfp_nsyn_mrs () == SUCCESS
)
12338 Rd
= inst
.operands
[0].reg
;
12339 reject_bad_reg (Rd
);
12340 inst
.instruction
|= Rd
<< 8;
12342 if (inst
.operands
[1].isreg
)
12344 unsigned br
= inst
.operands
[1].reg
;
12345 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12346 as_bad (_("bad register for mrs"));
12348 inst
.instruction
|= br
& (0xf << 16);
12349 inst
.instruction
|= (br
& 0x300) >> 4;
12350 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12354 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12356 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12358 /* PR gas/12698: The constraint is only applied for m_profile.
12359 If the user has specified -march=all, we want to ignore it as
12360 we are building for any CPU type, including non-m variants. */
12361 bfd_boolean m_profile
=
12362 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12363 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12364 "not support requested special purpose register"));
12367 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12369 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12370 _("'APSR', 'CPSR' or 'SPSR' expected"));
12372 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12373 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12374 inst
.instruction
|= 0xf0000;
12384 if (do_vfp_nsyn_msr () == SUCCESS
)
12387 constraint (!inst
.operands
[1].isreg
,
12388 _("Thumb encoding does not support an immediate here"));
12390 if (inst
.operands
[0].isreg
)
12391 flags
= (int)(inst
.operands
[0].reg
);
12393 flags
= inst
.operands
[0].imm
;
12395 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12397 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12399 /* PR gas/12698: The constraint is only applied for m_profile.
12400 If the user has specified -march=all, we want to ignore it as
12401 we are building for any CPU type, including non-m variants. */
12402 bfd_boolean m_profile
=
12403 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12404 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12405 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12406 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12407 && bits
!= PSR_f
)) && m_profile
,
12408 _("selected processor does not support requested special "
12409 "purpose register"));
12412 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12413 "requested special purpose register"));
12415 Rn
= inst
.operands
[1].reg
;
12416 reject_bad_reg (Rn
);
12418 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12419 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12420 inst
.instruction
|= (flags
& 0x300) >> 4;
12421 inst
.instruction
|= (flags
& 0xff);
12422 inst
.instruction
|= Rn
<< 16;
12428 bfd_boolean narrow
;
12429 unsigned Rd
, Rn
, Rm
;
12431 if (!inst
.operands
[2].present
)
12432 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12434 Rd
= inst
.operands
[0].reg
;
12435 Rn
= inst
.operands
[1].reg
;
12436 Rm
= inst
.operands
[2].reg
;
12438 if (unified_syntax
)
12440 if (inst
.size_req
== 4
12446 else if (inst
.instruction
== T_MNEM_muls
)
12447 narrow
= !in_it_block ();
12449 narrow
= in_it_block ();
12453 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12454 constraint (Rn
> 7 || Rm
> 7,
12461 /* 16-bit MULS/Conditional MUL. */
12462 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12463 inst
.instruction
|= Rd
;
12466 inst
.instruction
|= Rm
<< 3;
12468 inst
.instruction
|= Rn
<< 3;
12470 constraint (1, _("dest must overlap one source register"));
12474 constraint (inst
.instruction
!= T_MNEM_mul
,
12475 _("Thumb-2 MUL must not set flags"));
12477 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12478 inst
.instruction
|= Rd
<< 8;
12479 inst
.instruction
|= Rn
<< 16;
12480 inst
.instruction
|= Rm
<< 0;
12482 reject_bad_reg (Rd
);
12483 reject_bad_reg (Rn
);
12484 reject_bad_reg (Rm
);
12491 unsigned RdLo
, RdHi
, Rn
, Rm
;
12493 RdLo
= inst
.operands
[0].reg
;
12494 RdHi
= inst
.operands
[1].reg
;
12495 Rn
= inst
.operands
[2].reg
;
12496 Rm
= inst
.operands
[3].reg
;
12498 reject_bad_reg (RdLo
);
12499 reject_bad_reg (RdHi
);
12500 reject_bad_reg (Rn
);
12501 reject_bad_reg (Rm
);
12503 inst
.instruction
|= RdLo
<< 12;
12504 inst
.instruction
|= RdHi
<< 8;
12505 inst
.instruction
|= Rn
<< 16;
12506 inst
.instruction
|= Rm
;
12509 as_tsktsk (_("rdhi and rdlo must be different"));
12515 set_it_insn_type (NEUTRAL_IT_INSN
);
12517 if (unified_syntax
)
12519 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12521 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12522 inst
.instruction
|= inst
.operands
[0].imm
;
12526 /* PR9722: Check for Thumb2 availability before
12527 generating a thumb2 nop instruction. */
12528 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12530 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12531 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12534 inst
.instruction
= 0x46c0;
12539 constraint (inst
.operands
[0].present
,
12540 _("Thumb does not support NOP with hints"));
12541 inst
.instruction
= 0x46c0;
12548 if (unified_syntax
)
12550 bfd_boolean narrow
;
12552 if (THUMB_SETS_FLAGS (inst
.instruction
))
12553 narrow
= !in_it_block ();
12555 narrow
= in_it_block ();
12556 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12558 if (inst
.size_req
== 4)
12563 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12564 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12565 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12569 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12570 inst
.instruction
|= inst
.operands
[0].reg
;
12571 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12576 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12578 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12580 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12581 inst
.instruction
|= inst
.operands
[0].reg
;
12582 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12591 Rd
= inst
.operands
[0].reg
;
12592 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12594 reject_bad_reg (Rd
);
12595 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12596 reject_bad_reg (Rn
);
12598 inst
.instruction
|= Rd
<< 8;
12599 inst
.instruction
|= Rn
<< 16;
12601 if (!inst
.operands
[2].isreg
)
12603 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12604 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12610 Rm
= inst
.operands
[2].reg
;
12611 reject_bad_reg (Rm
);
12613 constraint (inst
.operands
[2].shifted
12614 && inst
.operands
[2].immisreg
,
12615 _("shift must be constant"));
12616 encode_thumb32_shifted_operand (2);
12623 unsigned Rd
, Rn
, Rm
;
12625 Rd
= inst
.operands
[0].reg
;
12626 Rn
= inst
.operands
[1].reg
;
12627 Rm
= inst
.operands
[2].reg
;
12629 reject_bad_reg (Rd
);
12630 reject_bad_reg (Rn
);
12631 reject_bad_reg (Rm
);
12633 inst
.instruction
|= Rd
<< 8;
12634 inst
.instruction
|= Rn
<< 16;
12635 inst
.instruction
|= Rm
;
12636 if (inst
.operands
[3].present
)
12638 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12639 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12640 _("expression too complex"));
12641 inst
.instruction
|= (val
& 0x1c) << 10;
12642 inst
.instruction
|= (val
& 0x03) << 6;
12649 if (!inst
.operands
[3].present
)
12653 inst
.instruction
&= ~0x00000020;
12655 /* PR 10168. Swap the Rm and Rn registers. */
12656 Rtmp
= inst
.operands
[1].reg
;
12657 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12658 inst
.operands
[2].reg
= Rtmp
;
12666 if (inst
.operands
[0].immisreg
)
12667 reject_bad_reg (inst
.operands
[0].imm
);
12669 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12673 do_t_push_pop (void)
12677 constraint (inst
.operands
[0].writeback
,
12678 _("push/pop do not support {reglist}^"));
12679 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12680 _("expression too complex"));
12682 mask
= inst
.operands
[0].imm
;
12683 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12684 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12685 else if (inst
.size_req
!= 4
12686 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12687 ? REG_LR
: REG_PC
)))
12689 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12690 inst
.instruction
|= THUMB_PP_PC_LR
;
12691 inst
.instruction
|= mask
& 0xff;
12693 else if (unified_syntax
)
12695 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12696 encode_thumb2_ldmstm (13, mask
, TRUE
);
12700 inst
.error
= _("invalid register list to push/pop instruction");
12710 Rd
= inst
.operands
[0].reg
;
12711 Rm
= inst
.operands
[1].reg
;
12713 reject_bad_reg (Rd
);
12714 reject_bad_reg (Rm
);
12716 inst
.instruction
|= Rd
<< 8;
12717 inst
.instruction
|= Rm
<< 16;
12718 inst
.instruction
|= Rm
;
12726 Rd
= inst
.operands
[0].reg
;
12727 Rm
= inst
.operands
[1].reg
;
12729 reject_bad_reg (Rd
);
12730 reject_bad_reg (Rm
);
12732 if (Rd
<= 7 && Rm
<= 7
12733 && inst
.size_req
!= 4)
12735 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12736 inst
.instruction
|= Rd
;
12737 inst
.instruction
|= Rm
<< 3;
12739 else if (unified_syntax
)
12741 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12742 inst
.instruction
|= Rd
<< 8;
12743 inst
.instruction
|= Rm
<< 16;
12744 inst
.instruction
|= Rm
;
12747 inst
.error
= BAD_HIREG
;
12755 Rd
= inst
.operands
[0].reg
;
12756 Rm
= inst
.operands
[1].reg
;
12758 reject_bad_reg (Rd
);
12759 reject_bad_reg (Rm
);
12761 inst
.instruction
|= Rd
<< 8;
12762 inst
.instruction
|= Rm
;
12770 Rd
= inst
.operands
[0].reg
;
12771 Rs
= (inst
.operands
[1].present
12772 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12773 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12775 reject_bad_reg (Rd
);
12776 reject_bad_reg (Rs
);
12777 if (inst
.operands
[2].isreg
)
12778 reject_bad_reg (inst
.operands
[2].reg
);
12780 inst
.instruction
|= Rd
<< 8;
12781 inst
.instruction
|= Rs
<< 16;
12782 if (!inst
.operands
[2].isreg
)
12784 bfd_boolean narrow
;
12786 if ((inst
.instruction
& 0x00100000) != 0)
12787 narrow
= !in_it_block ();
12789 narrow
= in_it_block ();
12791 if (Rd
> 7 || Rs
> 7)
12794 if (inst
.size_req
== 4 || !unified_syntax
)
12797 if (inst
.reloc
.exp
.X_op
!= O_constant
12798 || inst
.reloc
.exp
.X_add_number
!= 0)
12801 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12802 relaxation, but it doesn't seem worth the hassle. */
12805 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12806 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12807 inst
.instruction
|= Rs
<< 3;
12808 inst
.instruction
|= Rd
;
12812 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12813 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12817 encode_thumb32_shifted_operand (2);
12823 if (warn_on_deprecated
12824 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12825 as_tsktsk (_("setend use is deprecated for ARMv8"));
12827 set_it_insn_type (OUTSIDE_IT_INSN
);
12828 if (inst
.operands
[0].imm
)
12829 inst
.instruction
|= 0x8;
12835 if (!inst
.operands
[1].present
)
12836 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12838 if (unified_syntax
)
12840 bfd_boolean narrow
;
12843 switch (inst
.instruction
)
12846 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12848 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12850 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12852 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12856 if (THUMB_SETS_FLAGS (inst
.instruction
))
12857 narrow
= !in_it_block ();
12859 narrow
= in_it_block ();
12860 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12862 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12864 if (inst
.operands
[2].isreg
12865 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12866 || inst
.operands
[2].reg
> 7))
12868 if (inst
.size_req
== 4)
12871 reject_bad_reg (inst
.operands
[0].reg
);
12872 reject_bad_reg (inst
.operands
[1].reg
);
12876 if (inst
.operands
[2].isreg
)
12878 reject_bad_reg (inst
.operands
[2].reg
);
12879 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12880 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12881 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12882 inst
.instruction
|= inst
.operands
[2].reg
;
12884 /* PR 12854: Error on extraneous shifts. */
12885 constraint (inst
.operands
[2].shifted
,
12886 _("extraneous shift as part of operand to shift insn"));
12890 inst
.operands
[1].shifted
= 1;
12891 inst
.operands
[1].shift_kind
= shift_kind
;
12892 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12893 ? T_MNEM_movs
: T_MNEM_mov
);
12894 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12895 encode_thumb32_shifted_operand (1);
12896 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12897 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12902 if (inst
.operands
[2].isreg
)
12904 switch (shift_kind
)
12906 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12907 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12908 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12909 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12913 inst
.instruction
|= inst
.operands
[0].reg
;
12914 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12916 /* PR 12854: Error on extraneous shifts. */
12917 constraint (inst
.operands
[2].shifted
,
12918 _("extraneous shift as part of operand to shift insn"));
12922 switch (shift_kind
)
12924 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12925 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12926 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12929 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12930 inst
.instruction
|= inst
.operands
[0].reg
;
12931 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12937 constraint (inst
.operands
[0].reg
> 7
12938 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12939 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12941 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12943 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12944 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12945 _("source1 and dest must be same register"));
12947 switch (inst
.instruction
)
12949 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12950 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12951 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12952 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12956 inst
.instruction
|= inst
.operands
[0].reg
;
12957 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12959 /* PR 12854: Error on extraneous shifts. */
12960 constraint (inst
.operands
[2].shifted
,
12961 _("extraneous shift as part of operand to shift insn"));
12965 switch (inst
.instruction
)
12967 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12968 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12969 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12970 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12973 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12974 inst
.instruction
|= inst
.operands
[0].reg
;
12975 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12983 unsigned Rd
, Rn
, Rm
;
12985 Rd
= inst
.operands
[0].reg
;
12986 Rn
= inst
.operands
[1].reg
;
12987 Rm
= inst
.operands
[2].reg
;
12989 reject_bad_reg (Rd
);
12990 reject_bad_reg (Rn
);
12991 reject_bad_reg (Rm
);
12993 inst
.instruction
|= Rd
<< 8;
12994 inst
.instruction
|= Rn
<< 16;
12995 inst
.instruction
|= Rm
;
13001 unsigned Rd
, Rn
, Rm
;
13003 Rd
= inst
.operands
[0].reg
;
13004 Rm
= inst
.operands
[1].reg
;
13005 Rn
= inst
.operands
[2].reg
;
13007 reject_bad_reg (Rd
);
13008 reject_bad_reg (Rn
);
13009 reject_bad_reg (Rm
);
13011 inst
.instruction
|= Rd
<< 8;
13012 inst
.instruction
|= Rn
<< 16;
13013 inst
.instruction
|= Rm
;
13019 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
13020 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13021 _("SMC is not permitted on this architecture"));
13022 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
13023 _("expression too complex"));
13024 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13025 inst
.instruction
|= (value
& 0xf000) >> 12;
13026 inst
.instruction
|= (value
& 0x0ff0);
13027 inst
.instruction
|= (value
& 0x000f) << 16;
13028 /* PR gas/15623: SMC instructions must be last in an IT block. */
13029 set_it_insn_type_last ();
13035 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
13037 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13038 inst
.instruction
|= (value
& 0x0fff);
13039 inst
.instruction
|= (value
& 0xf000) << 4;
13043 do_t_ssat_usat (int bias
)
13047 Rd
= inst
.operands
[0].reg
;
13048 Rn
= inst
.operands
[2].reg
;
13050 reject_bad_reg (Rd
);
13051 reject_bad_reg (Rn
);
13053 inst
.instruction
|= Rd
<< 8;
13054 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13055 inst
.instruction
|= Rn
<< 16;
13057 if (inst
.operands
[3].present
)
13059 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
13061 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13063 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
13064 _("expression too complex"));
13066 if (shift_amount
!= 0)
13068 constraint (shift_amount
> 31,
13069 _("shift expression is too large"));
13071 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13072 inst
.instruction
|= 0x00200000; /* sh bit. */
13074 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13075 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13083 do_t_ssat_usat (1);
13091 Rd
= inst
.operands
[0].reg
;
13092 Rn
= inst
.operands
[2].reg
;
13094 reject_bad_reg (Rd
);
13095 reject_bad_reg (Rn
);
13097 inst
.instruction
|= Rd
<< 8;
13098 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13099 inst
.instruction
|= Rn
<< 16;
13105 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13106 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13107 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13108 || inst
.operands
[2].negative
,
13111 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13113 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13114 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13115 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13116 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13122 if (!inst
.operands
[2].present
)
13123 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13125 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13126 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13127 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13130 inst
.instruction
|= inst
.operands
[0].reg
;
13131 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13132 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13133 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13139 unsigned Rd
, Rn
, Rm
;
13141 Rd
= inst
.operands
[0].reg
;
13142 Rn
= inst
.operands
[1].reg
;
13143 Rm
= inst
.operands
[2].reg
;
13145 reject_bad_reg (Rd
);
13146 reject_bad_reg (Rn
);
13147 reject_bad_reg (Rm
);
13149 inst
.instruction
|= Rd
<< 8;
13150 inst
.instruction
|= Rn
<< 16;
13151 inst
.instruction
|= Rm
;
13152 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13160 Rd
= inst
.operands
[0].reg
;
13161 Rm
= inst
.operands
[1].reg
;
13163 reject_bad_reg (Rd
);
13164 reject_bad_reg (Rm
);
13166 if (inst
.instruction
<= 0xffff
13167 && inst
.size_req
!= 4
13168 && Rd
<= 7 && Rm
<= 7
13169 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13171 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13172 inst
.instruction
|= Rd
;
13173 inst
.instruction
|= Rm
<< 3;
13175 else if (unified_syntax
)
13177 if (inst
.instruction
<= 0xffff)
13178 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13179 inst
.instruction
|= Rd
<< 8;
13180 inst
.instruction
|= Rm
;
13181 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13185 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13186 _("Thumb encoding does not support rotation"));
13187 constraint (1, BAD_HIREG
);
13194 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13203 half
= (inst
.instruction
& 0x10) != 0;
13204 set_it_insn_type_last ();
13205 constraint (inst
.operands
[0].immisreg
,
13206 _("instruction requires register index"));
13208 Rn
= inst
.operands
[0].reg
;
13209 Rm
= inst
.operands
[0].imm
;
13211 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13212 constraint (Rn
== REG_SP
, BAD_SP
);
13213 reject_bad_reg (Rm
);
13215 constraint (!half
&& inst
.operands
[0].shifted
,
13216 _("instruction does not allow shifted index"));
13217 inst
.instruction
|= (Rn
<< 16) | Rm
;
13223 if (!inst
.operands
[0].present
)
13224 inst
.operands
[0].imm
= 0;
13226 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13228 constraint (inst
.size_req
== 2,
13229 _("immediate value out of range"));
13230 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13231 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13232 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13236 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13237 inst
.instruction
|= inst
.operands
[0].imm
;
13240 set_it_insn_type (NEUTRAL_IT_INSN
);
13247 do_t_ssat_usat (0);
13255 Rd
= inst
.operands
[0].reg
;
13256 Rn
= inst
.operands
[2].reg
;
13258 reject_bad_reg (Rd
);
13259 reject_bad_reg (Rn
);
13261 inst
.instruction
|= Rd
<< 8;
13262 inst
.instruction
|= inst
.operands
[1].imm
;
13263 inst
.instruction
|= Rn
<< 16;
13266 /* Neon instruction encoder helpers. */
13268 /* Encodings for the different types for various Neon opcodes. */
13270 /* An "invalid" code for the following tables. */
13273 struct neon_tab_entry
13276 unsigned float_or_poly
;
13277 unsigned scalar_or_imm
;
13280 /* Map overloaded Neon opcodes to their respective encodings. */
13281 #define NEON_ENC_TAB \
13282 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13283 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13284 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13285 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13286 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13287 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13288 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13289 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13290 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13291 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13292 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13293 /* Register variants of the following two instructions are encoded as
13294 vcge / vcgt with the operands reversed. */ \
13295 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13296 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13297 X(vfma, N_INV, 0x0000c10, N_INV), \
13298 X(vfms, N_INV, 0x0200c10, N_INV), \
13299 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13300 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13301 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13302 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13303 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13304 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13305 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13306 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13307 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13308 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13309 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13310 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13311 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13312 X(vshl, 0x0000400, N_INV, 0x0800510), \
13313 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13314 X(vand, 0x0000110, N_INV, 0x0800030), \
13315 X(vbic, 0x0100110, N_INV, 0x0800030), \
13316 X(veor, 0x1000110, N_INV, N_INV), \
13317 X(vorn, 0x0300110, N_INV, 0x0800010), \
13318 X(vorr, 0x0200110, N_INV, 0x0800010), \
13319 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13320 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13321 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13322 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13323 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13324 X(vst1, 0x0000000, 0x0800000, N_INV), \
13325 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13326 X(vst2, 0x0000100, 0x0800100, N_INV), \
13327 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13328 X(vst3, 0x0000200, 0x0800200, N_INV), \
13329 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13330 X(vst4, 0x0000300, 0x0800300, N_INV), \
13331 X(vmovn, 0x1b20200, N_INV, N_INV), \
13332 X(vtrn, 0x1b20080, N_INV, N_INV), \
13333 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13334 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13335 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13336 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13337 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13338 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13339 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13340 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13341 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13342 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13343 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13344 X(vseleq, 0xe000a00, N_INV, N_INV), \
13345 X(vselvs, 0xe100a00, N_INV, N_INV), \
13346 X(vselge, 0xe200a00, N_INV, N_INV), \
13347 X(vselgt, 0xe300a00, N_INV, N_INV), \
13348 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13349 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13350 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13351 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13352 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13353 X(aes, 0x3b00300, N_INV, N_INV), \
13354 X(sha3op, 0x2000c00, N_INV, N_INV), \
13355 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13356 X(sha2op, 0x3ba0380, N_INV, N_INV)
13360 #define X(OPC,I,F,S) N_MNEM_##OPC
13365 static const struct neon_tab_entry neon_enc_tab
[] =
13367 #define X(OPC,I,F,S) { (I), (F), (S) }
13372 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13373 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13374 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13375 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13376 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13377 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13378 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13379 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13380 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13381 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13382 #define NEON_ENC_SINGLE_(X) \
13383 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13384 #define NEON_ENC_DOUBLE_(X) \
13385 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13386 #define NEON_ENC_FPV8_(X) \
13387 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13389 #define NEON_ENCODE(type, inst) \
13392 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13393 inst.is_neon = 1; \
13397 #define check_neon_suffixes \
13400 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13402 as_bad (_("invalid neon suffix for non neon instruction")); \
13408 /* Define shapes for instruction operands. The following mnemonic characters
13409 are used in this table:
13411 F - VFP S<n> register
13412 D - Neon D<n> register
13413 Q - Neon Q<n> register
13417 L - D<n> register list
13419 This table is used to generate various data:
13420 - enumerations of the form NS_DDR to be used as arguments to
13422 - a table classifying shapes into single, double, quad, mixed.
13423 - a table used to drive neon_select_shape. */
13425 #define NEON_SHAPE_DEF \
13426 X(3, (D, D, D), DOUBLE), \
13427 X(3, (Q, Q, Q), QUAD), \
13428 X(3, (D, D, I), DOUBLE), \
13429 X(3, (Q, Q, I), QUAD), \
13430 X(3, (D, D, S), DOUBLE), \
13431 X(3, (Q, Q, S), QUAD), \
13432 X(2, (D, D), DOUBLE), \
13433 X(2, (Q, Q), QUAD), \
13434 X(2, (D, S), DOUBLE), \
13435 X(2, (Q, S), QUAD), \
13436 X(2, (D, R), DOUBLE), \
13437 X(2, (Q, R), QUAD), \
13438 X(2, (D, I), DOUBLE), \
13439 X(2, (Q, I), QUAD), \
13440 X(3, (D, L, D), DOUBLE), \
13441 X(2, (D, Q), MIXED), \
13442 X(2, (Q, D), MIXED), \
13443 X(3, (D, Q, I), MIXED), \
13444 X(3, (Q, D, I), MIXED), \
13445 X(3, (Q, D, D), MIXED), \
13446 X(3, (D, Q, Q), MIXED), \
13447 X(3, (Q, Q, D), MIXED), \
13448 X(3, (Q, D, S), MIXED), \
13449 X(3, (D, Q, S), MIXED), \
13450 X(4, (D, D, D, I), DOUBLE), \
13451 X(4, (Q, Q, Q, I), QUAD), \
13452 X(4, (D, D, S, I), DOUBLE), \
13453 X(4, (Q, Q, S, I), QUAD), \
13454 X(2, (F, F), SINGLE), \
13455 X(3, (F, F, F), SINGLE), \
13456 X(2, (F, I), SINGLE), \
13457 X(2, (F, D), MIXED), \
13458 X(2, (D, F), MIXED), \
13459 X(3, (F, F, I), MIXED), \
13460 X(4, (R, R, F, F), SINGLE), \
13461 X(4, (F, F, R, R), SINGLE), \
13462 X(3, (D, R, R), DOUBLE), \
13463 X(3, (R, R, D), DOUBLE), \
13464 X(2, (S, R), SINGLE), \
13465 X(2, (R, S), SINGLE), \
13466 X(2, (F, R), SINGLE), \
13467 X(2, (R, F), SINGLE), \
13468 /* Half float shape supported so far. */\
13469 X (2, (H, D), MIXED), \
13470 X (2, (D, H), MIXED), \
13471 X (2, (H, F), MIXED), \
13472 X (2, (F, H), MIXED), \
13473 X (2, (H, H), HALF), \
13474 X (2, (H, R), HALF), \
13475 X (2, (R, H), HALF), \
13476 X (2, (H, I), HALF), \
13477 X (3, (H, H, H), HALF), \
13478 X (3, (H, F, I), MIXED), \
13479 X (3, (F, H, I), MIXED), \
13480 X (3, (D, H, H), MIXED), \
13481 X (3, (D, H, S), MIXED)
13483 #define S2(A,B) NS_##A##B
13484 #define S3(A,B,C) NS_##A##B##C
13485 #define S4(A,B,C,D) NS_##A##B##C##D
13487 #define X(N, L, C) S##N L
13500 enum neon_shape_class
13509 #define X(N, L, C) SC_##C
13511 static enum neon_shape_class neon_shape_class
[] =
13530 /* Register widths of above. */
13531 static unsigned neon_shape_el_size
[] =
13543 struct neon_shape_info
13546 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13549 #define S2(A,B) { SE_##A, SE_##B }
13550 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13551 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13553 #define X(N, L, C) { N, S##N L }
13555 static struct neon_shape_info neon_shape_tab
[] =
13565 /* Bit masks used in type checking given instructions.
13566 'N_EQK' means the type must be the same as (or based on in some way) the key
13567 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13568 set, various other bits can be set as well in order to modify the meaning of
13569 the type constraint. */
13571 enum neon_type_mask
13595 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13596 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13597 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13598 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13599 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13600 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13601 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13602 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13603 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13604 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13605 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13607 N_MAX_NONSPECIAL
= N_P64
13610 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13612 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13613 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13614 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13615 #define N_S_32 (N_S8 | N_S16 | N_S32)
13616 #define N_F_16_32 (N_F16 | N_F32)
13617 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13618 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13619 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13620 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13622 /* Pass this as the first type argument to neon_check_type to ignore types
13624 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13626 /* Select a "shape" for the current instruction (describing register types or
13627 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13628 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13629 function of operand parsing, so this function doesn't need to be called.
13630 Shapes should be listed in order of decreasing length. */
13632 static enum neon_shape
13633 neon_select_shape (enum neon_shape shape
, ...)
13636 enum neon_shape first_shape
= shape
;
13638 /* Fix missing optional operands. FIXME: we don't know at this point how
13639 many arguments we should have, so this makes the assumption that we have
13640 > 1. This is true of all current Neon opcodes, I think, but may not be
13641 true in the future. */
13642 if (!inst
.operands
[1].present
)
13643 inst
.operands
[1] = inst
.operands
[0];
13645 va_start (ap
, shape
);
13647 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13652 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13654 if (!inst
.operands
[j
].present
)
13660 switch (neon_shape_tab
[shape
].el
[j
])
13662 /* If a .f16, .16, .u16, .s16 type specifier is given over
13663 a VFP single precision register operand, it's essentially
13664 means only half of the register is used.
13666 If the type specifier is given after the mnemonics, the
13667 information is stored in inst.vectype. If the type specifier
13668 is given after register operand, the information is stored
13669 in inst.operands[].vectype.
13671 When there is only one type specifier, and all the register
13672 operands are the same type of hardware register, the type
13673 specifier applies to all register operands.
13675 If no type specifier is given, the shape is inferred from
13676 operand information.
13679 vadd.f16 s0, s1, s2: NS_HHH
13680 vabs.f16 s0, s1: NS_HH
13681 vmov.f16 s0, r1: NS_HR
13682 vmov.f16 r0, s1: NS_RH
13683 vcvt.f16 r0, s1: NS_RH
13684 vcvt.f16.s32 s2, s2, #29: NS_HFI
13685 vcvt.f16.s32 s2, s2: NS_HF
13688 if (!(inst
.operands
[j
].isreg
13689 && inst
.operands
[j
].isvec
13690 && inst
.operands
[j
].issingle
13691 && !inst
.operands
[j
].isquad
13692 && ((inst
.vectype
.elems
== 1
13693 && inst
.vectype
.el
[0].size
== 16)
13694 || (inst
.vectype
.elems
> 1
13695 && inst
.vectype
.el
[j
].size
== 16)
13696 || (inst
.vectype
.elems
== 0
13697 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13698 && inst
.operands
[j
].vectype
.size
== 16))))
13703 if (!(inst
.operands
[j
].isreg
13704 && inst
.operands
[j
].isvec
13705 && inst
.operands
[j
].issingle
13706 && !inst
.operands
[j
].isquad
13707 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13708 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13709 || (inst
.vectype
.elems
== 0
13710 && (inst
.operands
[j
].vectype
.size
== 32
13711 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13716 if (!(inst
.operands
[j
].isreg
13717 && inst
.operands
[j
].isvec
13718 && !inst
.operands
[j
].isquad
13719 && !inst
.operands
[j
].issingle
))
13724 if (!(inst
.operands
[j
].isreg
13725 && !inst
.operands
[j
].isvec
))
13730 if (!(inst
.operands
[j
].isreg
13731 && inst
.operands
[j
].isvec
13732 && inst
.operands
[j
].isquad
13733 && !inst
.operands
[j
].issingle
))
13738 if (!(!inst
.operands
[j
].isreg
13739 && !inst
.operands
[j
].isscalar
))
13744 if (!(!inst
.operands
[j
].isreg
13745 && inst
.operands
[j
].isscalar
))
13755 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13756 /* We've matched all the entries in the shape table, and we don't
13757 have any left over operands which have not been matched. */
13763 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13764 first_error (_("invalid instruction shape"));
13769 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13770 means the Q bit should be set). */
13773 neon_quad (enum neon_shape shape
)
13775 return neon_shape_class
[shape
] == SC_QUAD
;
13779 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13782 /* Allow modification to be made to types which are constrained to be
13783 based on the key element, based on bits set alongside N_EQK. */
13784 if ((typebits
& N_EQK
) != 0)
13786 if ((typebits
& N_HLF
) != 0)
13788 else if ((typebits
& N_DBL
) != 0)
13790 if ((typebits
& N_SGN
) != 0)
13791 *g_type
= NT_signed
;
13792 else if ((typebits
& N_UNS
) != 0)
13793 *g_type
= NT_unsigned
;
13794 else if ((typebits
& N_INT
) != 0)
13795 *g_type
= NT_integer
;
13796 else if ((typebits
& N_FLT
) != 0)
13797 *g_type
= NT_float
;
13798 else if ((typebits
& N_SIZ
) != 0)
13799 *g_type
= NT_untyped
;
13803 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13804 operand type, i.e. the single type specified in a Neon instruction when it
13805 is the only one given. */
13807 static struct neon_type_el
13808 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13810 struct neon_type_el dest
= *key
;
13812 gas_assert ((thisarg
& N_EQK
) != 0);
13814 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13819 /* Convert Neon type and size into compact bitmask representation. */
13821 static enum neon_type_mask
13822 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13829 case 8: return N_8
;
13830 case 16: return N_16
;
13831 case 32: return N_32
;
13832 case 64: return N_64
;
13840 case 8: return N_I8
;
13841 case 16: return N_I16
;
13842 case 32: return N_I32
;
13843 case 64: return N_I64
;
13851 case 16: return N_F16
;
13852 case 32: return N_F32
;
13853 case 64: return N_F64
;
13861 case 8: return N_P8
;
13862 case 16: return N_P16
;
13863 case 64: return N_P64
;
13871 case 8: return N_S8
;
13872 case 16: return N_S16
;
13873 case 32: return N_S32
;
13874 case 64: return N_S64
;
13882 case 8: return N_U8
;
13883 case 16: return N_U16
;
13884 case 32: return N_U32
;
13885 case 64: return N_U64
;
13896 /* Convert compact Neon bitmask type representation to a type and size. Only
13897 handles the case where a single bit is set in the mask. */
13900 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13901 enum neon_type_mask mask
)
13903 if ((mask
& N_EQK
) != 0)
13906 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13908 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13910 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13912 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13917 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13919 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13920 *type
= NT_unsigned
;
13921 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13922 *type
= NT_integer
;
13923 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13924 *type
= NT_untyped
;
13925 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13927 else if ((mask
& (N_F_ALL
)) != 0)
13935 /* Modify a bitmask of allowed types. This is only needed for type
13939 modify_types_allowed (unsigned allowed
, unsigned mods
)
13942 enum neon_el_type type
;
13948 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13950 if (el_type_of_type_chk (&type
, &size
,
13951 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13953 neon_modify_type_size (mods
, &type
, &size
);
13954 destmask
|= type_chk_of_el_type (type
, size
);
13961 /* Check type and return type classification.
13962 The manual states (paraphrase): If one datatype is given, it indicates the
13964 - the second operand, if there is one
13965 - the operand, if there is no second operand
13966 - the result, if there are no operands.
13967 This isn't quite good enough though, so we use a concept of a "key" datatype
13968 which is set on a per-instruction basis, which is the one which matters when
13969 only one data type is written.
13970 Note: this function has side-effects (e.g. filling in missing operands). All
13971 Neon instructions should call it before performing bit encoding. */
13973 static struct neon_type_el
13974 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13977 unsigned i
, pass
, key_el
= 0;
13978 unsigned types
[NEON_MAX_TYPE_ELS
];
13979 enum neon_el_type k_type
= NT_invtype
;
13980 unsigned k_size
= -1u;
13981 struct neon_type_el badtype
= {NT_invtype
, -1};
13982 unsigned key_allowed
= 0;
13984 /* Optional registers in Neon instructions are always (not) in operand 1.
13985 Fill in the missing operand here, if it was omitted. */
13986 if (els
> 1 && !inst
.operands
[1].present
)
13987 inst
.operands
[1] = inst
.operands
[0];
13989 /* Suck up all the varargs. */
13991 for (i
= 0; i
< els
; i
++)
13993 unsigned thisarg
= va_arg (ap
, unsigned);
13994 if (thisarg
== N_IGNORE_TYPE
)
13999 types
[i
] = thisarg
;
14000 if ((thisarg
& N_KEY
) != 0)
14005 if (inst
.vectype
.elems
> 0)
14006 for (i
= 0; i
< els
; i
++)
14007 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
14009 first_error (_("types specified in both the mnemonic and operands"));
14013 /* Duplicate inst.vectype elements here as necessary.
14014 FIXME: No idea if this is exactly the same as the ARM assembler,
14015 particularly when an insn takes one register and one non-register
14017 if (inst
.vectype
.elems
== 1 && els
> 1)
14020 inst
.vectype
.elems
= els
;
14021 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
14022 for (j
= 0; j
< els
; j
++)
14024 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14027 else if (inst
.vectype
.elems
== 0 && els
> 0)
14030 /* No types were given after the mnemonic, so look for types specified
14031 after each operand. We allow some flexibility here; as long as the
14032 "key" operand has a type, we can infer the others. */
14033 for (j
= 0; j
< els
; j
++)
14034 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
14035 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
14037 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
14039 for (j
= 0; j
< els
; j
++)
14040 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
14041 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14046 first_error (_("operand types can't be inferred"));
14050 else if (inst
.vectype
.elems
!= els
)
14052 first_error (_("type specifier has the wrong number of parts"));
14056 for (pass
= 0; pass
< 2; pass
++)
14058 for (i
= 0; i
< els
; i
++)
14060 unsigned thisarg
= types
[i
];
14061 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
14062 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
14063 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
14064 unsigned g_size
= inst
.vectype
.el
[i
].size
;
14066 /* Decay more-specific signed & unsigned types to sign-insensitive
14067 integer types if sign-specific variants are unavailable. */
14068 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
14069 && (types_allowed
& N_SU_ALL
) == 0)
14070 g_type
= NT_integer
;
14072 /* If only untyped args are allowed, decay any more specific types to
14073 them. Some instructions only care about signs for some element
14074 sizes, so handle that properly. */
14075 if (((types_allowed
& N_UNT
) == 0)
14076 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14077 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14078 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
14079 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
14080 g_type
= NT_untyped
;
14084 if ((thisarg
& N_KEY
) != 0)
14088 key_allowed
= thisarg
& ~N_KEY
;
14090 /* Check architecture constraint on FP16 extension. */
14092 && k_type
== NT_float
14093 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14095 inst
.error
= _(BAD_FP16
);
14102 if ((thisarg
& N_VFP
) != 0)
14104 enum neon_shape_el regshape
;
14105 unsigned regwidth
, match
;
14107 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14110 first_error (_("invalid instruction shape"));
14113 regshape
= neon_shape_tab
[ns
].el
[i
];
14114 regwidth
= neon_shape_el_size
[regshape
];
14116 /* In VFP mode, operands must match register widths. If we
14117 have a key operand, use its width, else use the width of
14118 the current operand. */
14124 /* FP16 will use a single precision register. */
14125 if (regwidth
== 32 && match
== 16)
14127 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14131 inst
.error
= _(BAD_FP16
);
14136 if (regwidth
!= match
)
14138 first_error (_("operand size must match register width"));
14143 if ((thisarg
& N_EQK
) == 0)
14145 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14147 if ((given_type
& types_allowed
) == 0)
14149 first_error (_("bad type in Neon instruction"));
14155 enum neon_el_type mod_k_type
= k_type
;
14156 unsigned mod_k_size
= k_size
;
14157 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14158 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14160 first_error (_("inconsistent types in Neon instruction"));
14168 return inst
.vectype
.el
[key_el
];
14171 /* Neon-style VFP instruction forwarding. */
14173 /* Thumb VFP instructions have 0xE in the condition field. */
14176 do_vfp_cond_or_thumb (void)
14181 inst
.instruction
|= 0xe0000000;
14183 inst
.instruction
|= inst
.cond
<< 28;
14186 /* Look up and encode a simple mnemonic, for use as a helper function for the
14187 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14188 etc. It is assumed that operand parsing has already been done, and that the
14189 operands are in the form expected by the given opcode (this isn't necessarily
14190 the same as the form in which they were parsed, hence some massaging must
14191 take place before this function is called).
14192 Checks current arch version against that in the looked-up opcode. */
14195 do_vfp_nsyn_opcode (const char *opname
)
14197 const struct asm_opcode
*opcode
;
14199 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14204 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14205 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14212 inst
.instruction
= opcode
->tvalue
;
14213 opcode
->tencode ();
14217 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14218 opcode
->aencode ();
14223 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14225 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14227 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14230 do_vfp_nsyn_opcode ("fadds");
14232 do_vfp_nsyn_opcode ("fsubs");
14234 /* ARMv8.2 fp16 instruction. */
14236 do_scalar_fp16_v82_encode ();
14241 do_vfp_nsyn_opcode ("faddd");
14243 do_vfp_nsyn_opcode ("fsubd");
14247 /* Check operand types to see if this is a VFP instruction, and if so call
14251 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14253 enum neon_shape rs
;
14254 struct neon_type_el et
;
14259 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14260 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14264 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14265 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14266 N_F_ALL
| N_KEY
| N_VFP
);
14273 if (et
.type
!= NT_invtype
)
14284 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14286 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14288 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14291 do_vfp_nsyn_opcode ("fmacs");
14293 do_vfp_nsyn_opcode ("fnmacs");
14295 /* ARMv8.2 fp16 instruction. */
14297 do_scalar_fp16_v82_encode ();
14302 do_vfp_nsyn_opcode ("fmacd");
14304 do_vfp_nsyn_opcode ("fnmacd");
14309 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14311 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14313 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14316 do_vfp_nsyn_opcode ("ffmas");
14318 do_vfp_nsyn_opcode ("ffnmas");
14320 /* ARMv8.2 fp16 instruction. */
14322 do_scalar_fp16_v82_encode ();
14327 do_vfp_nsyn_opcode ("ffmad");
14329 do_vfp_nsyn_opcode ("ffnmad");
14334 do_vfp_nsyn_mul (enum neon_shape rs
)
14336 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14338 do_vfp_nsyn_opcode ("fmuls");
14340 /* ARMv8.2 fp16 instruction. */
14342 do_scalar_fp16_v82_encode ();
14345 do_vfp_nsyn_opcode ("fmuld");
14349 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14351 int is_neg
= (inst
.instruction
& 0x80) != 0;
14352 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14354 if (rs
== NS_FF
|| rs
== NS_HH
)
14357 do_vfp_nsyn_opcode ("fnegs");
14359 do_vfp_nsyn_opcode ("fabss");
14361 /* ARMv8.2 fp16 instruction. */
14363 do_scalar_fp16_v82_encode ();
14368 do_vfp_nsyn_opcode ("fnegd");
14370 do_vfp_nsyn_opcode ("fabsd");
14374 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14375 insns belong to Neon, and are handled elsewhere. */
14378 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14380 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14384 do_vfp_nsyn_opcode ("fldmdbs");
14386 do_vfp_nsyn_opcode ("fldmias");
14391 do_vfp_nsyn_opcode ("fstmdbs");
14393 do_vfp_nsyn_opcode ("fstmias");
14398 do_vfp_nsyn_sqrt (void)
14400 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14401 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14403 if (rs
== NS_FF
|| rs
== NS_HH
)
14405 do_vfp_nsyn_opcode ("fsqrts");
14407 /* ARMv8.2 fp16 instruction. */
14409 do_scalar_fp16_v82_encode ();
14412 do_vfp_nsyn_opcode ("fsqrtd");
14416 do_vfp_nsyn_div (void)
14418 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14419 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14420 N_F_ALL
| N_KEY
| N_VFP
);
14422 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14424 do_vfp_nsyn_opcode ("fdivs");
14426 /* ARMv8.2 fp16 instruction. */
14428 do_scalar_fp16_v82_encode ();
14431 do_vfp_nsyn_opcode ("fdivd");
14435 do_vfp_nsyn_nmul (void)
14437 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14438 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14439 N_F_ALL
| N_KEY
| N_VFP
);
14441 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14443 NEON_ENCODE (SINGLE
, inst
);
14444 do_vfp_sp_dyadic ();
14446 /* ARMv8.2 fp16 instruction. */
14448 do_scalar_fp16_v82_encode ();
14452 NEON_ENCODE (DOUBLE
, inst
);
14453 do_vfp_dp_rd_rn_rm ();
14455 do_vfp_cond_or_thumb ();
14460 do_vfp_nsyn_cmp (void)
14462 enum neon_shape rs
;
14463 if (inst
.operands
[1].isreg
)
14465 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14466 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14468 if (rs
== NS_FF
|| rs
== NS_HH
)
14470 NEON_ENCODE (SINGLE
, inst
);
14471 do_vfp_sp_monadic ();
14475 NEON_ENCODE (DOUBLE
, inst
);
14476 do_vfp_dp_rd_rm ();
14481 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14482 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14484 switch (inst
.instruction
& 0x0fffffff)
14487 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14490 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14496 if (rs
== NS_FI
|| rs
== NS_HI
)
14498 NEON_ENCODE (SINGLE
, inst
);
14499 do_vfp_sp_compare_z ();
14503 NEON_ENCODE (DOUBLE
, inst
);
14507 do_vfp_cond_or_thumb ();
14509 /* ARMv8.2 fp16 instruction. */
14510 if (rs
== NS_HI
|| rs
== NS_HH
)
14511 do_scalar_fp16_v82_encode ();
14515 nsyn_insert_sp (void)
14517 inst
.operands
[1] = inst
.operands
[0];
14518 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14519 inst
.operands
[0].reg
= REG_SP
;
14520 inst
.operands
[0].isreg
= 1;
14521 inst
.operands
[0].writeback
= 1;
14522 inst
.operands
[0].present
= 1;
14526 do_vfp_nsyn_push (void)
14530 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14531 _("register list must contain at least 1 and at most 16 "
14534 if (inst
.operands
[1].issingle
)
14535 do_vfp_nsyn_opcode ("fstmdbs");
14537 do_vfp_nsyn_opcode ("fstmdbd");
14541 do_vfp_nsyn_pop (void)
14545 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14546 _("register list must contain at least 1 and at most 16 "
14549 if (inst
.operands
[1].issingle
)
14550 do_vfp_nsyn_opcode ("fldmias");
14552 do_vfp_nsyn_opcode ("fldmiad");
14555 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14556 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14559 neon_dp_fixup (struct arm_it
* insn
)
14561 unsigned int i
= insn
->instruction
;
14566 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14577 insn
->instruction
= i
;
14580 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14584 neon_logbits (unsigned x
)
14586 return ffs (x
) - 4;
14589 #define LOW4(R) ((R) & 0xf)
14590 #define HI1(R) (((R) >> 4) & 1)
14592 /* Encode insns with bit pattern:
14594 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14595 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14597 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14598 different meaning for some instruction. */
14601 neon_three_same (int isquad
, int ubit
, int size
)
14603 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14604 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14605 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14606 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14607 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14608 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14609 inst
.instruction
|= (isquad
!= 0) << 6;
14610 inst
.instruction
|= (ubit
!= 0) << 24;
14612 inst
.instruction
|= neon_logbits (size
) << 20;
14614 neon_dp_fixup (&inst
);
14617 /* Encode instructions of the form:
14619 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14620 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14622 Don't write size if SIZE == -1. */
14625 neon_two_same (int qbit
, int ubit
, int size
)
14627 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14628 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14629 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14630 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14631 inst
.instruction
|= (qbit
!= 0) << 6;
14632 inst
.instruction
|= (ubit
!= 0) << 24;
14635 inst
.instruction
|= neon_logbits (size
) << 18;
14637 neon_dp_fixup (&inst
);
14640 /* Neon instruction encoders, in approximate order of appearance. */
14643 do_neon_dyadic_i_su (void)
14645 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14646 struct neon_type_el et
= neon_check_type (3, rs
,
14647 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14648 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14652 do_neon_dyadic_i64_su (void)
14654 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14655 struct neon_type_el et
= neon_check_type (3, rs
,
14656 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14657 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14661 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14664 unsigned size
= et
.size
>> 3;
14665 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14666 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14667 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14668 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14669 inst
.instruction
|= (isquad
!= 0) << 6;
14670 inst
.instruction
|= immbits
<< 16;
14671 inst
.instruction
|= (size
>> 3) << 7;
14672 inst
.instruction
|= (size
& 0x7) << 19;
14674 inst
.instruction
|= (uval
!= 0) << 24;
14676 neon_dp_fixup (&inst
);
14680 do_neon_shl_imm (void)
14682 if (!inst
.operands
[2].isreg
)
14684 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14685 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14686 int imm
= inst
.operands
[2].imm
;
14688 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14689 _("immediate out of range for shift"));
14690 NEON_ENCODE (IMMED
, inst
);
14691 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14695 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14696 struct neon_type_el et
= neon_check_type (3, rs
,
14697 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14700 /* VSHL/VQSHL 3-register variants have syntax such as:
14702 whereas other 3-register operations encoded by neon_three_same have
14705 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14707 tmp
= inst
.operands
[2].reg
;
14708 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14709 inst
.operands
[1].reg
= tmp
;
14710 NEON_ENCODE (INTEGER
, inst
);
14711 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14716 do_neon_qshl_imm (void)
14718 if (!inst
.operands
[2].isreg
)
14720 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14721 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14722 int imm
= inst
.operands
[2].imm
;
14724 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14725 _("immediate out of range for shift"));
14726 NEON_ENCODE (IMMED
, inst
);
14727 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14731 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14732 struct neon_type_el et
= neon_check_type (3, rs
,
14733 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14736 /* See note in do_neon_shl_imm. */
14737 tmp
= inst
.operands
[2].reg
;
14738 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14739 inst
.operands
[1].reg
= tmp
;
14740 NEON_ENCODE (INTEGER
, inst
);
14741 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14746 do_neon_rshl (void)
14748 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14749 struct neon_type_el et
= neon_check_type (3, rs
,
14750 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14753 tmp
= inst
.operands
[2].reg
;
14754 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14755 inst
.operands
[1].reg
= tmp
;
14756 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14760 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14762 /* Handle .I8 pseudo-instructions. */
14765 /* Unfortunately, this will make everything apart from zero out-of-range.
14766 FIXME is this the intended semantics? There doesn't seem much point in
14767 accepting .I8 if so. */
14768 immediate
|= immediate
<< 8;
14774 if (immediate
== (immediate
& 0x000000ff))
14776 *immbits
= immediate
;
14779 else if (immediate
== (immediate
& 0x0000ff00))
14781 *immbits
= immediate
>> 8;
14784 else if (immediate
== (immediate
& 0x00ff0000))
14786 *immbits
= immediate
>> 16;
14789 else if (immediate
== (immediate
& 0xff000000))
14791 *immbits
= immediate
>> 24;
14794 if ((immediate
& 0xffff) != (immediate
>> 16))
14795 goto bad_immediate
;
14796 immediate
&= 0xffff;
14799 if (immediate
== (immediate
& 0x000000ff))
14801 *immbits
= immediate
;
14804 else if (immediate
== (immediate
& 0x0000ff00))
14806 *immbits
= immediate
>> 8;
14811 first_error (_("immediate value out of range"));
14816 do_neon_logic (void)
14818 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14820 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14821 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14822 /* U bit and size field were set as part of the bitmask. */
14823 NEON_ENCODE (INTEGER
, inst
);
14824 neon_three_same (neon_quad (rs
), 0, -1);
14828 const int three_ops_form
= (inst
.operands
[2].present
14829 && !inst
.operands
[2].isreg
);
14830 const int immoperand
= (three_ops_form
? 2 : 1);
14831 enum neon_shape rs
= (three_ops_form
14832 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14833 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14834 struct neon_type_el et
= neon_check_type (2, rs
,
14835 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14836 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14840 if (et
.type
== NT_invtype
)
14843 if (three_ops_form
)
14844 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14845 _("first and second operands shall be the same register"));
14847 NEON_ENCODE (IMMED
, inst
);
14849 immbits
= inst
.operands
[immoperand
].imm
;
14852 /* .i64 is a pseudo-op, so the immediate must be a repeating
14854 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14855 inst
.operands
[immoperand
].reg
: 0))
14857 /* Set immbits to an invalid constant. */
14858 immbits
= 0xdeadbeef;
14865 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14869 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14873 /* Pseudo-instruction for VBIC. */
14874 neon_invert_size (&immbits
, 0, et
.size
);
14875 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14879 /* Pseudo-instruction for VORR. */
14880 neon_invert_size (&immbits
, 0, et
.size
);
14881 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14891 inst
.instruction
|= neon_quad (rs
) << 6;
14892 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14893 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14894 inst
.instruction
|= cmode
<< 8;
14895 neon_write_immbits (immbits
);
14897 neon_dp_fixup (&inst
);
14902 do_neon_bitfield (void)
14904 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14905 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14906 neon_three_same (neon_quad (rs
), 0, -1);
14910 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14913 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14914 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14916 if (et
.type
== NT_float
)
14918 NEON_ENCODE (FLOAT
, inst
);
14919 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14923 NEON_ENCODE (INTEGER
, inst
);
14924 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14929 do_neon_dyadic_if_su (void)
14931 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14935 do_neon_dyadic_if_su_d (void)
14937 /* This version only allow D registers, but that constraint is enforced during
14938 operand parsing so we don't need to do anything extra here. */
14939 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14943 do_neon_dyadic_if_i_d (void)
14945 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14946 affected if we specify unsigned args. */
14947 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14950 enum vfp_or_neon_is_neon_bits
14953 NEON_CHECK_ARCH
= 2,
14954 NEON_CHECK_ARCH8
= 4
14957 /* Call this function if an instruction which may have belonged to the VFP or
14958 Neon instruction sets, but turned out to be a Neon instruction (due to the
14959 operand types involved, etc.). We have to check and/or fix-up a couple of
14962 - Make sure the user hasn't attempted to make a Neon instruction
14964 - Alter the value in the condition code field if necessary.
14965 - Make sure that the arch supports Neon instructions.
14967 Which of these operations take place depends on bits from enum
14968 vfp_or_neon_is_neon_bits.
14970 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14971 current instruction's condition is COND_ALWAYS, the condition field is
14972 changed to inst.uncond_value. This is necessary because instructions shared
14973 between VFP and Neon may be conditional for the VFP variants only, and the
14974 unconditional Neon version must have, e.g., 0xF in the condition field. */
14977 vfp_or_neon_is_neon (unsigned check
)
14979 /* Conditions are always legal in Thumb mode (IT blocks). */
14980 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14982 if (inst
.cond
!= COND_ALWAYS
)
14984 first_error (_(BAD_COND
));
14987 if (inst
.uncond_value
!= -1)
14988 inst
.instruction
|= inst
.uncond_value
<< 28;
14991 if ((check
& NEON_CHECK_ARCH
)
14992 && !mark_feature_used (&fpu_neon_ext_v1
))
14994 first_error (_(BAD_FPU
));
14998 if ((check
& NEON_CHECK_ARCH8
)
14999 && !mark_feature_used (&fpu_neon_ext_armv8
))
15001 first_error (_(BAD_FPU
));
15009 do_neon_addsub_if_i (void)
15011 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
15014 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15017 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15018 affected if we specify unsigned args. */
15019 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
15022 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
15024 V<op> A,B (A is operand 0, B is operand 2)
15029 so handle that case specially. */
15032 neon_exchange_operands (void)
15034 if (inst
.operands
[1].present
)
15036 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
15038 /* Swap operands[1] and operands[2]. */
15039 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
15040 inst
.operands
[1] = inst
.operands
[2];
15041 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
15046 inst
.operands
[1] = inst
.operands
[2];
15047 inst
.operands
[2] = inst
.operands
[0];
15052 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
15054 if (inst
.operands
[2].isreg
)
15057 neon_exchange_operands ();
15058 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
15062 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15063 struct neon_type_el et
= neon_check_type (2, rs
,
15064 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
15066 NEON_ENCODE (IMMED
, inst
);
15067 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15068 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15069 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15070 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15071 inst
.instruction
|= neon_quad (rs
) << 6;
15072 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15073 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15075 neon_dp_fixup (&inst
);
15082 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
15086 do_neon_cmp_inv (void)
15088 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
15094 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
15097 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
15098 scalars, which are encoded in 5 bits, M : Rm.
15099 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
15100 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
15103 Dot Product instructions are similar to multiply instructions except elsize
15104 should always be 32.
15106 This function translates SCALAR, which is GAS's internal encoding of indexed
15107 scalar register, to raw encoding. There is also register and index range
15108 check based on ELSIZE. */
15111 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
15113 unsigned regno
= NEON_SCALAR_REG (scalar
);
15114 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15119 if (regno
> 7 || elno
> 3)
15121 return regno
| (elno
<< 3);
15124 if (regno
> 15 || elno
> 1)
15126 return regno
| (elno
<< 4);
15130 first_error (_("scalar out of range for multiply instruction"));
15136 /* Encode multiply / multiply-accumulate scalar instructions. */
15139 neon_mul_mac (struct neon_type_el et
, int ubit
)
15143 /* Give a more helpful error message if we have an invalid type. */
15144 if (et
.type
== NT_invtype
)
15147 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15148 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15149 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15150 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15151 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15152 inst
.instruction
|= LOW4 (scalar
);
15153 inst
.instruction
|= HI1 (scalar
) << 5;
15154 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15155 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15156 inst
.instruction
|= (ubit
!= 0) << 24;
15158 neon_dp_fixup (&inst
);
15162 do_neon_mac_maybe_scalar (void)
15164 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15167 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15170 if (inst
.operands
[2].isscalar
)
15172 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15173 struct neon_type_el et
= neon_check_type (3, rs
,
15174 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15175 NEON_ENCODE (SCALAR
, inst
);
15176 neon_mul_mac (et
, neon_quad (rs
));
15180 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15181 affected if we specify unsigned args. */
15182 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15187 do_neon_fmac (void)
15189 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15192 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15195 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15201 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15202 struct neon_type_el et
= neon_check_type (3, rs
,
15203 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15204 neon_three_same (neon_quad (rs
), 0, et
.size
);
15207 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15208 same types as the MAC equivalents. The polynomial type for this instruction
15209 is encoded the same as the integer type. */
15214 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15217 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15220 if (inst
.operands
[2].isscalar
)
15221 do_neon_mac_maybe_scalar ();
15223 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15227 do_neon_qdmulh (void)
15229 if (inst
.operands
[2].isscalar
)
15231 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15232 struct neon_type_el et
= neon_check_type (3, rs
,
15233 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15234 NEON_ENCODE (SCALAR
, inst
);
15235 neon_mul_mac (et
, neon_quad (rs
));
15239 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15240 struct neon_type_el et
= neon_check_type (3, rs
,
15241 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15242 NEON_ENCODE (INTEGER
, inst
);
15243 /* The U bit (rounding) comes from bit mask. */
15244 neon_three_same (neon_quad (rs
), 0, et
.size
);
15249 do_neon_qrdmlah (void)
15251 /* Check we're on the correct architecture. */
15252 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15254 _("instruction form not available on this architecture.");
15255 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15257 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15258 record_feature_use (&fpu_neon_ext_v8_1
);
15261 if (inst
.operands
[2].isscalar
)
15263 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15264 struct neon_type_el et
= neon_check_type (3, rs
,
15265 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15266 NEON_ENCODE (SCALAR
, inst
);
15267 neon_mul_mac (et
, neon_quad (rs
));
15271 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15272 struct neon_type_el et
= neon_check_type (3, rs
,
15273 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15274 NEON_ENCODE (INTEGER
, inst
);
15275 /* The U bit (rounding) comes from bit mask. */
15276 neon_three_same (neon_quad (rs
), 0, et
.size
);
15281 do_neon_fcmp_absolute (void)
15283 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15284 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15285 N_F_16_32
| N_KEY
);
15286 /* Size field comes from bit mask. */
15287 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15291 do_neon_fcmp_absolute_inv (void)
15293 neon_exchange_operands ();
15294 do_neon_fcmp_absolute ();
15298 do_neon_step (void)
15300 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15301 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15302 N_F_16_32
| N_KEY
);
15303 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15307 do_neon_abs_neg (void)
15309 enum neon_shape rs
;
15310 struct neon_type_el et
;
15312 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15315 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15318 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15319 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15321 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15322 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15323 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15324 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15325 inst
.instruction
|= neon_quad (rs
) << 6;
15326 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15327 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15329 neon_dp_fixup (&inst
);
15335 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15336 struct neon_type_el et
= neon_check_type (2, rs
,
15337 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15338 int imm
= inst
.operands
[2].imm
;
15339 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15340 _("immediate out of range for insert"));
15341 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15347 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15348 struct neon_type_el et
= neon_check_type (2, rs
,
15349 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15350 int imm
= inst
.operands
[2].imm
;
15351 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15352 _("immediate out of range for insert"));
15353 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15357 do_neon_qshlu_imm (void)
15359 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15360 struct neon_type_el et
= neon_check_type (2, rs
,
15361 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15362 int imm
= inst
.operands
[2].imm
;
15363 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15364 _("immediate out of range for shift"));
15365 /* Only encodes the 'U present' variant of the instruction.
15366 In this case, signed types have OP (bit 8) set to 0.
15367 Unsigned types have OP set to 1. */
15368 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15369 /* The rest of the bits are the same as other immediate shifts. */
15370 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15374 do_neon_qmovn (void)
15376 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15377 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15378 /* Saturating move where operands can be signed or unsigned, and the
15379 destination has the same signedness. */
15380 NEON_ENCODE (INTEGER
, inst
);
15381 if (et
.type
== NT_unsigned
)
15382 inst
.instruction
|= 0xc0;
15384 inst
.instruction
|= 0x80;
15385 neon_two_same (0, 1, et
.size
/ 2);
15389 do_neon_qmovun (void)
15391 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15392 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15393 /* Saturating move with unsigned results. Operands must be signed. */
15394 NEON_ENCODE (INTEGER
, inst
);
15395 neon_two_same (0, 1, et
.size
/ 2);
15399 do_neon_rshift_sat_narrow (void)
15401 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15402 or unsigned. If operands are unsigned, results must also be unsigned. */
15403 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15404 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15405 int imm
= inst
.operands
[2].imm
;
15406 /* This gets the bounds check, size encoding and immediate bits calculation
15410 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15411 VQMOVN.I<size> <Dd>, <Qm>. */
15414 inst
.operands
[2].present
= 0;
15415 inst
.instruction
= N_MNEM_vqmovn
;
15420 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15421 _("immediate out of range"));
15422 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15426 do_neon_rshift_sat_narrow_u (void)
15428 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15429 or unsigned. If operands are unsigned, results must also be unsigned. */
15430 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15431 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15432 int imm
= inst
.operands
[2].imm
;
15433 /* This gets the bounds check, size encoding and immediate bits calculation
15437 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15438 VQMOVUN.I<size> <Dd>, <Qm>. */
15441 inst
.operands
[2].present
= 0;
15442 inst
.instruction
= N_MNEM_vqmovun
;
15447 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15448 _("immediate out of range"));
15449 /* FIXME: The manual is kind of unclear about what value U should have in
15450 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15452 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15456 do_neon_movn (void)
15458 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15459 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15460 NEON_ENCODE (INTEGER
, inst
);
15461 neon_two_same (0, 1, et
.size
/ 2);
15465 do_neon_rshift_narrow (void)
15467 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15468 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15469 int imm
= inst
.operands
[2].imm
;
15470 /* This gets the bounds check, size encoding and immediate bits calculation
15474 /* If immediate is zero then we are a pseudo-instruction for
15475 VMOVN.I<size> <Dd>, <Qm> */
15478 inst
.operands
[2].present
= 0;
15479 inst
.instruction
= N_MNEM_vmovn
;
15484 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15485 _("immediate out of range for narrowing operation"));
15486 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15490 do_neon_shll (void)
15492 /* FIXME: Type checking when lengthening. */
15493 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15494 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15495 unsigned imm
= inst
.operands
[2].imm
;
15497 if (imm
== et
.size
)
15499 /* Maximum shift variant. */
15500 NEON_ENCODE (INTEGER
, inst
);
15501 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15502 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15503 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15504 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15505 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15507 neon_dp_fixup (&inst
);
15511 /* A more-specific type check for non-max versions. */
15512 et
= neon_check_type (2, NS_QDI
,
15513 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15514 NEON_ENCODE (IMMED
, inst
);
15515 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15519 /* Check the various types for the VCVT instruction, and return which version
15520 the current instruction is. */
15522 #define CVT_FLAVOUR_VAR \
15523 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15524 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15525 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15526 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15527 /* Half-precision conversions. */ \
15528 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15529 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15530 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15531 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15532 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15533 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15534 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15535 Compared with single/double precision variants, only the co-processor \
15536 field is different, so the encoding flow is reused here. */ \
15537 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15538 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15539 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15540 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15541 /* VFP instructions. */ \
15542 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15543 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15544 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15545 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15546 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15547 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15548 /* VFP instructions with bitshift. */ \
15549 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15550 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15551 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15552 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15553 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15554 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15555 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15556 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15558 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15559 neon_cvt_flavour_##C,
15561 /* The different types of conversions we can do. */
15562 enum neon_cvt_flavour
15565 neon_cvt_flavour_invalid
,
15566 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15571 static enum neon_cvt_flavour
15572 get_neon_cvt_flavour (enum neon_shape rs
)
15574 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15575 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15576 if (et.type != NT_invtype) \
15578 inst.error = NULL; \
15579 return (neon_cvt_flavour_##C); \
15582 struct neon_type_el et
;
15583 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15584 || rs
== NS_FF
) ? N_VFP
: 0;
15585 /* The instruction versions which take an immediate take one register
15586 argument, which is extended to the width of the full register. Thus the
15587 "source" and "destination" registers must have the same width. Hack that
15588 here by making the size equal to the key (wider, in this case) operand. */
15589 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15593 return neon_cvt_flavour_invalid
;
15608 /* Neon-syntax VFP conversions. */
15611 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15613 const char *opname
= 0;
15615 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15616 || rs
== NS_FHI
|| rs
== NS_HFI
)
15618 /* Conversions with immediate bitshift. */
15619 const char *enc
[] =
15621 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15627 if (flavour
< (int) ARRAY_SIZE (enc
))
15629 opname
= enc
[flavour
];
15630 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15631 _("operands 0 and 1 must be the same register"));
15632 inst
.operands
[1] = inst
.operands
[2];
15633 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15638 /* Conversions without bitshift. */
15639 const char *enc
[] =
15641 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15647 if (flavour
< (int) ARRAY_SIZE (enc
))
15648 opname
= enc
[flavour
];
15652 do_vfp_nsyn_opcode (opname
);
15654 /* ARMv8.2 fp16 VCVT instruction. */
15655 if (flavour
== neon_cvt_flavour_s32_f16
15656 || flavour
== neon_cvt_flavour_u32_f16
15657 || flavour
== neon_cvt_flavour_f16_u32
15658 || flavour
== neon_cvt_flavour_f16_s32
)
15659 do_scalar_fp16_v82_encode ();
15663 do_vfp_nsyn_cvtz (void)
15665 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15666 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15667 const char *enc
[] =
15669 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15675 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15676 do_vfp_nsyn_opcode (enc
[flavour
]);
15680 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15681 enum neon_cvt_mode mode
)
15686 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15687 D register operands. */
15688 if (flavour
== neon_cvt_flavour_s32_f64
15689 || flavour
== neon_cvt_flavour_u32_f64
)
15690 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15693 if (flavour
== neon_cvt_flavour_s32_f16
15694 || flavour
== neon_cvt_flavour_u32_f16
)
15695 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15698 set_it_insn_type (OUTSIDE_IT_INSN
);
15702 case neon_cvt_flavour_s32_f64
:
15706 case neon_cvt_flavour_s32_f32
:
15710 case neon_cvt_flavour_s32_f16
:
15714 case neon_cvt_flavour_u32_f64
:
15718 case neon_cvt_flavour_u32_f32
:
15722 case neon_cvt_flavour_u32_f16
:
15727 first_error (_("invalid instruction shape"));
15733 case neon_cvt_mode_a
: rm
= 0; break;
15734 case neon_cvt_mode_n
: rm
= 1; break;
15735 case neon_cvt_mode_p
: rm
= 2; break;
15736 case neon_cvt_mode_m
: rm
= 3; break;
15737 default: first_error (_("invalid rounding mode")); return;
15740 NEON_ENCODE (FPV8
, inst
);
15741 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15742 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15743 inst
.instruction
|= sz
<< 8;
15745 /* ARMv8.2 fp16 VCVT instruction. */
15746 if (flavour
== neon_cvt_flavour_s32_f16
15747 ||flavour
== neon_cvt_flavour_u32_f16
)
15748 do_scalar_fp16_v82_encode ();
15749 inst
.instruction
|= op
<< 7;
15750 inst
.instruction
|= rm
<< 16;
15751 inst
.instruction
|= 0xf0000000;
15752 inst
.is_neon
= TRUE
;
15756 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15758 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15759 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15760 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15762 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15764 if (flavour
== neon_cvt_flavour_invalid
)
15767 /* PR11109: Handle round-to-zero for VCVT conversions. */
15768 if (mode
== neon_cvt_mode_z
15769 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15770 && (flavour
== neon_cvt_flavour_s16_f16
15771 || flavour
== neon_cvt_flavour_u16_f16
15772 || flavour
== neon_cvt_flavour_s32_f32
15773 || flavour
== neon_cvt_flavour_u32_f32
15774 || flavour
== neon_cvt_flavour_s32_f64
15775 || flavour
== neon_cvt_flavour_u32_f64
)
15776 && (rs
== NS_FD
|| rs
== NS_FF
))
15778 do_vfp_nsyn_cvtz ();
15782 /* ARMv8.2 fp16 VCVT conversions. */
15783 if (mode
== neon_cvt_mode_z
15784 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15785 && (flavour
== neon_cvt_flavour_s32_f16
15786 || flavour
== neon_cvt_flavour_u32_f16
)
15789 do_vfp_nsyn_cvtz ();
15790 do_scalar_fp16_v82_encode ();
15794 /* VFP rather than Neon conversions. */
15795 if (flavour
>= neon_cvt_flavour_first_fp
)
15797 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15798 do_vfp_nsyn_cvt (rs
, flavour
);
15800 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15811 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15812 0x0000100, 0x1000100, 0x0, 0x1000000};
15814 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15817 /* Fixed-point conversion with #0 immediate is encoded as an
15818 integer conversion. */
15819 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15821 NEON_ENCODE (IMMED
, inst
);
15822 if (flavour
!= neon_cvt_flavour_invalid
)
15823 inst
.instruction
|= enctab
[flavour
];
15824 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15825 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15826 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15827 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15828 inst
.instruction
|= neon_quad (rs
) << 6;
15829 inst
.instruction
|= 1 << 21;
15830 if (flavour
< neon_cvt_flavour_s16_f16
)
15832 inst
.instruction
|= 1 << 21;
15833 immbits
= 32 - inst
.operands
[2].imm
;
15834 inst
.instruction
|= immbits
<< 16;
15838 inst
.instruction
|= 3 << 20;
15839 immbits
= 16 - inst
.operands
[2].imm
;
15840 inst
.instruction
|= immbits
<< 16;
15841 inst
.instruction
&= ~(1 << 9);
15844 neon_dp_fixup (&inst
);
15850 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15852 NEON_ENCODE (FLOAT
, inst
);
15853 set_it_insn_type (OUTSIDE_IT_INSN
);
15855 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15858 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15859 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15860 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15861 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15862 inst
.instruction
|= neon_quad (rs
) << 6;
15863 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15864 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15865 inst
.instruction
|= mode
<< 8;
15866 if (flavour
== neon_cvt_flavour_u16_f16
15867 || flavour
== neon_cvt_flavour_s16_f16
)
15868 /* Mask off the original size bits and reencode them. */
15869 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15872 inst
.instruction
|= 0xfc000000;
15874 inst
.instruction
|= 0xf0000000;
15880 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15881 0x100, 0x180, 0x0, 0x080};
15883 NEON_ENCODE (INTEGER
, inst
);
15885 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15888 if (flavour
!= neon_cvt_flavour_invalid
)
15889 inst
.instruction
|= enctab
[flavour
];
15891 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15892 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15893 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15894 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15895 inst
.instruction
|= neon_quad (rs
) << 6;
15896 if (flavour
>= neon_cvt_flavour_s16_f16
15897 && flavour
<= neon_cvt_flavour_f16_u16
)
15898 /* Half precision. */
15899 inst
.instruction
|= 1 << 18;
15901 inst
.instruction
|= 2 << 18;
15903 neon_dp_fixup (&inst
);
15908 /* Half-precision conversions for Advanced SIMD -- neon. */
15913 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15915 as_bad (_("operand size must match register width"));
15920 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15922 as_bad (_("operand size must match register width"));
15927 inst
.instruction
= 0x3b60600;
15929 inst
.instruction
= 0x3b60700;
15931 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15932 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15933 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15934 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15935 neon_dp_fixup (&inst
);
15939 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15940 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15941 do_vfp_nsyn_cvt (rs
, flavour
);
15943 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15948 do_neon_cvtr (void)
15950 do_neon_cvt_1 (neon_cvt_mode_x
);
15956 do_neon_cvt_1 (neon_cvt_mode_z
);
15960 do_neon_cvta (void)
15962 do_neon_cvt_1 (neon_cvt_mode_a
);
15966 do_neon_cvtn (void)
15968 do_neon_cvt_1 (neon_cvt_mode_n
);
15972 do_neon_cvtp (void)
15974 do_neon_cvt_1 (neon_cvt_mode_p
);
15978 do_neon_cvtm (void)
15980 do_neon_cvt_1 (neon_cvt_mode_m
);
15984 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15987 mark_feature_used (&fpu_vfp_ext_armv8
);
15989 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15990 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15991 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15992 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15993 inst
.instruction
|= to
? 0x10000 : 0;
15994 inst
.instruction
|= t
? 0x80 : 0;
15995 inst
.instruction
|= is_double
? 0x100 : 0;
15996 do_vfp_cond_or_thumb ();
16000 do_neon_cvttb_1 (bfd_boolean t
)
16002 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
16003 NS_DF
, NS_DH
, NS_NULL
);
16007 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
16010 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
16012 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
16015 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
16017 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
16019 /* The VCVTB and VCVTT instructions with D-register operands
16020 don't work for SP only targets. */
16021 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16025 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
16027 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
16029 /* The VCVTB and VCVTT instructions with D-register operands
16030 don't work for SP only targets. */
16031 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16035 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
16042 do_neon_cvtb (void)
16044 do_neon_cvttb_1 (FALSE
);
16049 do_neon_cvtt (void)
16051 do_neon_cvttb_1 (TRUE
);
16055 neon_move_immediate (void)
16057 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
16058 struct neon_type_el et
= neon_check_type (2, rs
,
16059 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
16060 unsigned immlo
, immhi
= 0, immbits
;
16061 int op
, cmode
, float_p
;
16063 constraint (et
.type
== NT_invtype
,
16064 _("operand size must be specified for immediate VMOV"));
16066 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
16067 op
= (inst
.instruction
& (1 << 5)) != 0;
16069 immlo
= inst
.operands
[1].imm
;
16070 if (inst
.operands
[1].regisimm
)
16071 immhi
= inst
.operands
[1].reg
;
16073 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
16074 _("immediate has bits set outside the operand size"));
16076 float_p
= inst
.operands
[1].immisfloat
;
16078 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
16079 et
.size
, et
.type
)) == FAIL
)
16081 /* Invert relevant bits only. */
16082 neon_invert_size (&immlo
, &immhi
, et
.size
);
16083 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
16084 with one or the other; those cases are caught by
16085 neon_cmode_for_move_imm. */
16087 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
16088 &op
, et
.size
, et
.type
)) == FAIL
)
16090 first_error (_("immediate out of range"));
16095 inst
.instruction
&= ~(1 << 5);
16096 inst
.instruction
|= op
<< 5;
16098 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16099 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16100 inst
.instruction
|= neon_quad (rs
) << 6;
16101 inst
.instruction
|= cmode
<< 8;
16103 neon_write_immbits (immbits
);
16109 if (inst
.operands
[1].isreg
)
16111 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16113 NEON_ENCODE (INTEGER
, inst
);
16114 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16115 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16116 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16117 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16118 inst
.instruction
|= neon_quad (rs
) << 6;
16122 NEON_ENCODE (IMMED
, inst
);
16123 neon_move_immediate ();
16126 neon_dp_fixup (&inst
);
16129 /* Encode instructions of form:
16131 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16132 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16135 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16137 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16138 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16139 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16140 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16141 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16142 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16143 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16144 inst
.instruction
|= neon_logbits (size
) << 20;
16146 neon_dp_fixup (&inst
);
16150 do_neon_dyadic_long (void)
16152 /* FIXME: Type checking for lengthening op. */
16153 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16154 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16155 neon_mixed_length (et
, et
.size
);
16159 do_neon_abal (void)
16161 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16162 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16163 neon_mixed_length (et
, et
.size
);
16167 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16169 if (inst
.operands
[2].isscalar
)
16171 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16172 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16173 NEON_ENCODE (SCALAR
, inst
);
16174 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16178 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16179 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16180 NEON_ENCODE (INTEGER
, inst
);
16181 neon_mixed_length (et
, et
.size
);
16186 do_neon_mac_maybe_scalar_long (void)
16188 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16191 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
16192 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
16195 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
16197 unsigned regno
= NEON_SCALAR_REG (scalar
);
16198 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
16202 if (regno
> 7 || elno
> 3)
16205 return ((regno
& 0x7)
16206 | ((elno
& 0x1) << 3)
16207 | (((elno
>> 1) & 0x1) << 5));
16211 if (regno
> 15 || elno
> 1)
16214 return (((regno
& 0x1) << 5)
16215 | ((regno
>> 1) & 0x7)
16216 | ((elno
& 0x1) << 3));
16220 first_error (_("scalar out of range for multiply instruction"));
16225 do_neon_fmac_maybe_scalar_long (int subtype
)
16227 enum neon_shape rs
;
16229 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
16230 field (bits[21:20]) has different meaning. For scalar index variant, it's
16231 used to differentiate add and subtract, otherwise it's with fixed value
16235 if (inst
.cond
!= COND_ALWAYS
)
16236 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
16237 "behaviour is UNPREDICTABLE"));
16239 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
16242 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
16245 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
16246 be a scalar index register. */
16247 if (inst
.operands
[2].isscalar
)
16249 high8
= 0xfe000000;
16252 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
16256 high8
= 0xfc000000;
16259 inst
.instruction
|= (0x1 << 23);
16260 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
16263 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
16265 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
16266 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
16267 so we simply pass -1 as size. */
16268 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
16269 neon_three_same (quad_p
, 0, size
);
16271 /* Undo neon_dp_fixup. Redo the high eight bits. */
16272 inst
.instruction
&= 0x00ffffff;
16273 inst
.instruction
|= high8
;
16275 #define LOW1(R) ((R) & 0x1)
16276 #define HI4(R) (((R) >> 1) & 0xf)
16277 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
16278 whether the instruction is in Q form and whether Vm is a scalar indexed
16280 if (inst
.operands
[2].isscalar
)
16283 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
16284 inst
.instruction
&= 0xffffffd0;
16285 inst
.instruction
|= rm
;
16289 /* Redo Rn as well. */
16290 inst
.instruction
&= 0xfff0ff7f;
16291 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16292 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16297 /* Redo Rn and Rm. */
16298 inst
.instruction
&= 0xfff0ff50;
16299 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16300 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16301 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
16302 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
16307 do_neon_vfmal (void)
16309 return do_neon_fmac_maybe_scalar_long (0);
16313 do_neon_vfmsl (void)
16315 return do_neon_fmac_maybe_scalar_long (1);
16319 do_neon_dyadic_wide (void)
16321 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16322 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16323 neon_mixed_length (et
, et
.size
);
16327 do_neon_dyadic_narrow (void)
16329 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16330 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16331 /* Operand sign is unimportant, and the U bit is part of the opcode,
16332 so force the operand type to integer. */
16333 et
.type
= NT_integer
;
16334 neon_mixed_length (et
, et
.size
/ 2);
16338 do_neon_mul_sat_scalar_long (void)
16340 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16344 do_neon_vmull (void)
16346 if (inst
.operands
[2].isscalar
)
16347 do_neon_mac_maybe_scalar_long ();
16350 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16351 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16353 if (et
.type
== NT_poly
)
16354 NEON_ENCODE (POLY
, inst
);
16356 NEON_ENCODE (INTEGER
, inst
);
16358 /* For polynomial encoding the U bit must be zero, and the size must
16359 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16360 obviously, as 0b10). */
16363 /* Check we're on the correct architecture. */
16364 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16366 _("Instruction form not available on this architecture.");
16371 neon_mixed_length (et
, et
.size
);
16378 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16379 struct neon_type_el et
= neon_check_type (3, rs
,
16380 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16381 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16383 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16384 _("shift out of range"));
16385 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16386 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16387 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16388 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16389 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16390 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16391 inst
.instruction
|= neon_quad (rs
) << 6;
16392 inst
.instruction
|= imm
<< 8;
16394 neon_dp_fixup (&inst
);
16400 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16401 struct neon_type_el et
= neon_check_type (2, rs
,
16402 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16403 unsigned op
= (inst
.instruction
>> 7) & 3;
16404 /* N (width of reversed regions) is encoded as part of the bitmask. We
16405 extract it here to check the elements to be reversed are smaller.
16406 Otherwise we'd get a reserved instruction. */
16407 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16408 gas_assert (elsize
!= 0);
16409 constraint (et
.size
>= elsize
,
16410 _("elements must be smaller than reversal region"));
16411 neon_two_same (neon_quad (rs
), 1, et
.size
);
16417 if (inst
.operands
[1].isscalar
)
16419 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16420 struct neon_type_el et
= neon_check_type (2, rs
,
16421 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16422 unsigned sizebits
= et
.size
>> 3;
16423 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16424 int logsize
= neon_logbits (et
.size
);
16425 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16427 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16430 NEON_ENCODE (SCALAR
, inst
);
16431 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16432 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16433 inst
.instruction
|= LOW4 (dm
);
16434 inst
.instruction
|= HI1 (dm
) << 5;
16435 inst
.instruction
|= neon_quad (rs
) << 6;
16436 inst
.instruction
|= x
<< 17;
16437 inst
.instruction
|= sizebits
<< 16;
16439 neon_dp_fixup (&inst
);
16443 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16444 struct neon_type_el et
= neon_check_type (2, rs
,
16445 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16446 /* Duplicate ARM register to lanes of vector. */
16447 NEON_ENCODE (ARMREG
, inst
);
16450 case 8: inst
.instruction
|= 0x400000; break;
16451 case 16: inst
.instruction
|= 0x000020; break;
16452 case 32: inst
.instruction
|= 0x000000; break;
16455 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16456 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16457 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16458 inst
.instruction
|= neon_quad (rs
) << 21;
16459 /* The encoding for this instruction is identical for the ARM and Thumb
16460 variants, except for the condition field. */
16461 do_vfp_cond_or_thumb ();
16465 /* VMOV has particularly many variations. It can be one of:
16466 0. VMOV<c><q> <Qd>, <Qm>
16467 1. VMOV<c><q> <Dd>, <Dm>
16468 (Register operations, which are VORR with Rm = Rn.)
16469 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16470 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16472 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16473 (ARM register to scalar.)
16474 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16475 (Two ARM registers to vector.)
16476 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16477 (Scalar to ARM register.)
16478 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16479 (Vector to two ARM registers.)
16480 8. VMOV.F32 <Sd>, <Sm>
16481 9. VMOV.F64 <Dd>, <Dm>
16482 (VFP register moves.)
16483 10. VMOV.F32 <Sd>, #imm
16484 11. VMOV.F64 <Dd>, #imm
16485 (VFP float immediate load.)
16486 12. VMOV <Rd>, <Sm>
16487 (VFP single to ARM reg.)
16488 13. VMOV <Sd>, <Rm>
16489 (ARM reg to VFP single.)
16490 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16491 (Two ARM regs to two VFP singles.)
16492 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16493 (Two VFP singles to two ARM regs.)
16495 These cases can be disambiguated using neon_select_shape, except cases 1/9
16496 and 3/11 which depend on the operand type too.
16498 All the encoded bits are hardcoded by this function.
16500 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16501 Cases 5, 7 may be used with VFPv2 and above.
16503 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16504 can specify a type where it doesn't make sense to, and is ignored). */
16509 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16510 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16511 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16512 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16513 struct neon_type_el et
;
16514 const char *ldconst
= 0;
16518 case NS_DD
: /* case 1/9. */
16519 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16520 /* It is not an error here if no type is given. */
16522 if (et
.type
== NT_float
&& et
.size
== 64)
16524 do_vfp_nsyn_opcode ("fcpyd");
16527 /* fall through. */
16529 case NS_QQ
: /* case 0/1. */
16531 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16533 /* The architecture manual I have doesn't explicitly state which
16534 value the U bit should have for register->register moves, but
16535 the equivalent VORR instruction has U = 0, so do that. */
16536 inst
.instruction
= 0x0200110;
16537 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16538 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16539 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16540 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16541 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16542 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16543 inst
.instruction
|= neon_quad (rs
) << 6;
16545 neon_dp_fixup (&inst
);
16549 case NS_DI
: /* case 3/11. */
16550 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16552 if (et
.type
== NT_float
&& et
.size
== 64)
16554 /* case 11 (fconstd). */
16555 ldconst
= "fconstd";
16556 goto encode_fconstd
;
16558 /* fall through. */
16560 case NS_QI
: /* case 2/3. */
16561 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16563 inst
.instruction
= 0x0800010;
16564 neon_move_immediate ();
16565 neon_dp_fixup (&inst
);
16568 case NS_SR
: /* case 4. */
16570 unsigned bcdebits
= 0;
16572 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16573 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16575 /* .<size> is optional here, defaulting to .32. */
16576 if (inst
.vectype
.elems
== 0
16577 && inst
.operands
[0].vectype
.type
== NT_invtype
16578 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16580 inst
.vectype
.el
[0].type
= NT_untyped
;
16581 inst
.vectype
.el
[0].size
= 32;
16582 inst
.vectype
.elems
= 1;
16585 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16586 logsize
= neon_logbits (et
.size
);
16588 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16590 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16591 && et
.size
!= 32, _(BAD_FPU
));
16592 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16593 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16597 case 8: bcdebits
= 0x8; break;
16598 case 16: bcdebits
= 0x1; break;
16599 case 32: bcdebits
= 0x0; break;
16603 bcdebits
|= x
<< logsize
;
16605 inst
.instruction
= 0xe000b10;
16606 do_vfp_cond_or_thumb ();
16607 inst
.instruction
|= LOW4 (dn
) << 16;
16608 inst
.instruction
|= HI1 (dn
) << 7;
16609 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16610 inst
.instruction
|= (bcdebits
& 3) << 5;
16611 inst
.instruction
|= (bcdebits
>> 2) << 21;
16615 case NS_DRR
: /* case 5 (fmdrr). */
16616 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16619 inst
.instruction
= 0xc400b10;
16620 do_vfp_cond_or_thumb ();
16621 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16622 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16623 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16624 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16627 case NS_RS
: /* case 6. */
16630 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16631 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16632 unsigned abcdebits
= 0;
16634 /* .<dt> is optional here, defaulting to .32. */
16635 if (inst
.vectype
.elems
== 0
16636 && inst
.operands
[0].vectype
.type
== NT_invtype
16637 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16639 inst
.vectype
.el
[0].type
= NT_untyped
;
16640 inst
.vectype
.el
[0].size
= 32;
16641 inst
.vectype
.elems
= 1;
16644 et
= neon_check_type (2, NS_NULL
,
16645 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16646 logsize
= neon_logbits (et
.size
);
16648 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16650 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16651 && et
.size
!= 32, _(BAD_FPU
));
16652 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16653 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16657 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16658 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16659 case 32: abcdebits
= 0x00; break;
16663 abcdebits
|= x
<< logsize
;
16664 inst
.instruction
= 0xe100b10;
16665 do_vfp_cond_or_thumb ();
16666 inst
.instruction
|= LOW4 (dn
) << 16;
16667 inst
.instruction
|= HI1 (dn
) << 7;
16668 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16669 inst
.instruction
|= (abcdebits
& 3) << 5;
16670 inst
.instruction
|= (abcdebits
>> 2) << 21;
16674 case NS_RRD
: /* case 7 (fmrrd). */
16675 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16678 inst
.instruction
= 0xc500b10;
16679 do_vfp_cond_or_thumb ();
16680 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16681 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16682 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16683 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16686 case NS_FF
: /* case 8 (fcpys). */
16687 do_vfp_nsyn_opcode ("fcpys");
16691 case NS_FI
: /* case 10 (fconsts). */
16692 ldconst
= "fconsts";
16694 if (!inst
.operands
[1].immisfloat
)
16696 /* Immediate has to fit in 8 bits so float is enough. */
16697 float imm
= (float)inst
.operands
[1].imm
;
16698 memcpy (&inst
.operands
[1].imm
, &imm
, sizeof (float));
16699 inst
.operands
[1].immisfloat
= 1;
16702 if (is_quarter_float (inst
.operands
[1].imm
))
16704 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16705 do_vfp_nsyn_opcode (ldconst
);
16707 /* ARMv8.2 fp16 vmov.f16 instruction. */
16709 do_scalar_fp16_v82_encode ();
16712 first_error (_("immediate out of range"));
16716 case NS_RF
: /* case 12 (fmrs). */
16717 do_vfp_nsyn_opcode ("fmrs");
16718 /* ARMv8.2 fp16 vmov.f16 instruction. */
16720 do_scalar_fp16_v82_encode ();
16724 case NS_FR
: /* case 13 (fmsr). */
16725 do_vfp_nsyn_opcode ("fmsr");
16726 /* ARMv8.2 fp16 vmov.f16 instruction. */
16728 do_scalar_fp16_v82_encode ();
16731 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16732 (one of which is a list), but we have parsed four. Do some fiddling to
16733 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16735 case NS_RRFF
: /* case 14 (fmrrs). */
16736 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16737 _("VFP registers must be adjacent"));
16738 inst
.operands
[2].imm
= 2;
16739 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16740 do_vfp_nsyn_opcode ("fmrrs");
16743 case NS_FFRR
: /* case 15 (fmsrr). */
16744 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16745 _("VFP registers must be adjacent"));
16746 inst
.operands
[1] = inst
.operands
[2];
16747 inst
.operands
[2] = inst
.operands
[3];
16748 inst
.operands
[0].imm
= 2;
16749 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16750 do_vfp_nsyn_opcode ("fmsrr");
16754 /* neon_select_shape has determined that the instruction
16755 shape is wrong and has already set the error message. */
16764 do_neon_rshift_round_imm (void)
16766 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16767 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16768 int imm
= inst
.operands
[2].imm
;
16770 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16773 inst
.operands
[2].present
= 0;
16778 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16779 _("immediate out of range for shift"));
16780 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16785 do_neon_movhf (void)
16787 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16788 constraint (rs
!= NS_HH
, _("invalid suffix"));
16790 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16793 if (inst
.cond
!= COND_ALWAYS
)
16797 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
16798 " the behaviour is UNPREDICTABLE"));
16802 inst
.error
= BAD_COND
;
16807 do_vfp_sp_monadic ();
16810 inst
.instruction
|= 0xf0000000;
16814 do_neon_movl (void)
16816 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16817 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16818 unsigned sizebits
= et
.size
>> 3;
16819 inst
.instruction
|= sizebits
<< 19;
16820 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16826 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16827 struct neon_type_el et
= neon_check_type (2, rs
,
16828 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16829 NEON_ENCODE (INTEGER
, inst
);
16830 neon_two_same (neon_quad (rs
), 1, et
.size
);
16834 do_neon_zip_uzp (void)
16836 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16837 struct neon_type_el et
= neon_check_type (2, rs
,
16838 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16839 if (rs
== NS_DD
&& et
.size
== 32)
16841 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16842 inst
.instruction
= N_MNEM_vtrn
;
16846 neon_two_same (neon_quad (rs
), 1, et
.size
);
16850 do_neon_sat_abs_neg (void)
16852 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16853 struct neon_type_el et
= neon_check_type (2, rs
,
16854 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16855 neon_two_same (neon_quad (rs
), 1, et
.size
);
16859 do_neon_pair_long (void)
16861 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16862 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16863 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16864 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16865 neon_two_same (neon_quad (rs
), 1, et
.size
);
16869 do_neon_recip_est (void)
16871 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16872 struct neon_type_el et
= neon_check_type (2, rs
,
16873 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16874 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16875 neon_two_same (neon_quad (rs
), 1, et
.size
);
16881 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16882 struct neon_type_el et
= neon_check_type (2, rs
,
16883 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16884 neon_two_same (neon_quad (rs
), 1, et
.size
);
16890 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16891 struct neon_type_el et
= neon_check_type (2, rs
,
16892 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16893 neon_two_same (neon_quad (rs
), 1, et
.size
);
16899 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16900 struct neon_type_el et
= neon_check_type (2, rs
,
16901 N_EQK
| N_INT
, N_8
| N_KEY
);
16902 neon_two_same (neon_quad (rs
), 1, et
.size
);
16908 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16909 neon_two_same (neon_quad (rs
), 1, -1);
16913 do_neon_tbl_tbx (void)
16915 unsigned listlenbits
;
16916 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16918 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16920 first_error (_("bad list length for table lookup"));
16924 listlenbits
= inst
.operands
[1].imm
- 1;
16925 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16926 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16927 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16928 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16929 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16930 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16931 inst
.instruction
|= listlenbits
<< 8;
16933 neon_dp_fixup (&inst
);
16937 do_neon_ldm_stm (void)
16939 /* P, U and L bits are part of bitmask. */
16940 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16941 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16943 if (inst
.operands
[1].issingle
)
16945 do_vfp_nsyn_ldm_stm (is_dbmode
);
16949 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16950 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16952 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16953 _("register list must contain at least 1 and at most 16 "
16956 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16957 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16958 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16959 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16961 inst
.instruction
|= offsetbits
;
16963 do_vfp_cond_or_thumb ();
16967 do_neon_ldr_str (void)
16969 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16971 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16972 And is UNPREDICTABLE in thumb mode. */
16974 && inst
.operands
[1].reg
== REG_PC
16975 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16978 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16979 else if (warn_on_deprecated
)
16980 as_tsktsk (_("Use of PC here is deprecated"));
16983 if (inst
.operands
[0].issingle
)
16986 do_vfp_nsyn_opcode ("flds");
16988 do_vfp_nsyn_opcode ("fsts");
16990 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16991 if (inst
.vectype
.el
[0].size
== 16)
16992 do_scalar_fp16_v82_encode ();
16997 do_vfp_nsyn_opcode ("fldd");
16999 do_vfp_nsyn_opcode ("fstd");
17003 /* "interleave" version also handles non-interleaving register VLD1/VST1
17007 do_neon_ld_st_interleave (void)
17009 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
17010 N_8
| N_16
| N_32
| N_64
);
17011 unsigned alignbits
= 0;
17013 /* The bits in this table go:
17014 0: register stride of one (0) or two (1)
17015 1,2: register list length, minus one (1, 2, 3, 4).
17016 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
17017 We use -1 for invalid entries. */
17018 const int typetable
[] =
17020 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
17021 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
17022 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
17023 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
17027 if (et
.type
== NT_invtype
)
17030 if (inst
.operands
[1].immisalign
)
17031 switch (inst
.operands
[1].imm
>> 8)
17033 case 64: alignbits
= 1; break;
17035 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
17036 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
17037 goto bad_alignment
;
17041 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
17042 goto bad_alignment
;
17047 first_error (_("bad alignment"));
17051 inst
.instruction
|= alignbits
<< 4;
17052 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17054 /* Bits [4:6] of the immediate in a list specifier encode register stride
17055 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
17056 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
17057 up the right value for "type" in a table based on this value and the given
17058 list style, then stick it back. */
17059 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
17060 | (((inst
.instruction
>> 8) & 3) << 3);
17062 typebits
= typetable
[idx
];
17064 constraint (typebits
== -1, _("bad list type for instruction"));
17065 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
17066 _("bad element type for instruction"));
17068 inst
.instruction
&= ~0xf00;
17069 inst
.instruction
|= typebits
<< 8;
17072 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
17073 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
17074 otherwise. The variable arguments are a list of pairs of legal (size, align)
17075 values, terminated with -1. */
17078 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
17081 int result
= FAIL
, thissize
, thisalign
;
17083 if (!inst
.operands
[1].immisalign
)
17089 va_start (ap
, do_alignment
);
17093 thissize
= va_arg (ap
, int);
17094 if (thissize
== -1)
17096 thisalign
= va_arg (ap
, int);
17098 if (size
== thissize
&& align
== thisalign
)
17101 while (result
!= SUCCESS
);
17105 if (result
== SUCCESS
)
17108 first_error (_("unsupported alignment for instruction"));
17114 do_neon_ld_st_lane (void)
17116 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17117 int align_good
, do_alignment
= 0;
17118 int logsize
= neon_logbits (et
.size
);
17119 int align
= inst
.operands
[1].imm
>> 8;
17120 int n
= (inst
.instruction
>> 8) & 3;
17121 int max_el
= 64 / et
.size
;
17123 if (et
.type
== NT_invtype
)
17126 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
17127 _("bad list length"));
17128 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
17129 _("scalar index out of range"));
17130 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
17132 _("stride of 2 unavailable when element size is 8"));
17136 case 0: /* VLD1 / VST1. */
17137 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
17139 if (align_good
== FAIL
)
17143 unsigned alignbits
= 0;
17146 case 16: alignbits
= 0x1; break;
17147 case 32: alignbits
= 0x3; break;
17150 inst
.instruction
|= alignbits
<< 4;
17154 case 1: /* VLD2 / VST2. */
17155 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
17156 16, 32, 32, 64, -1);
17157 if (align_good
== FAIL
)
17160 inst
.instruction
|= 1 << 4;
17163 case 2: /* VLD3 / VST3. */
17164 constraint (inst
.operands
[1].immisalign
,
17165 _("can't use alignment with this instruction"));
17168 case 3: /* VLD4 / VST4. */
17169 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17170 16, 64, 32, 64, 32, 128, -1);
17171 if (align_good
== FAIL
)
17175 unsigned alignbits
= 0;
17178 case 8: alignbits
= 0x1; break;
17179 case 16: alignbits
= 0x1; break;
17180 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
17183 inst
.instruction
|= alignbits
<< 4;
17190 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
17191 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17192 inst
.instruction
|= 1 << (4 + logsize
);
17194 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
17195 inst
.instruction
|= logsize
<< 10;
17198 /* Encode single n-element structure to all lanes VLD<n> instructions. */
17201 do_neon_ld_dup (void)
17203 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17204 int align_good
, do_alignment
= 0;
17206 if (et
.type
== NT_invtype
)
17209 switch ((inst
.instruction
>> 8) & 3)
17211 case 0: /* VLD1. */
17212 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
17213 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17214 &do_alignment
, 16, 16, 32, 32, -1);
17215 if (align_good
== FAIL
)
17217 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
17220 case 2: inst
.instruction
|= 1 << 5; break;
17221 default: first_error (_("bad list length")); return;
17223 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17226 case 1: /* VLD2. */
17227 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17228 &do_alignment
, 8, 16, 16, 32, 32, 64,
17230 if (align_good
== FAIL
)
17232 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
17233 _("bad list length"));
17234 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17235 inst
.instruction
|= 1 << 5;
17236 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17239 case 2: /* VLD3. */
17240 constraint (inst
.operands
[1].immisalign
,
17241 _("can't use alignment with this instruction"));
17242 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
17243 _("bad list length"));
17244 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17245 inst
.instruction
|= 1 << 5;
17246 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17249 case 3: /* VLD4. */
17251 int align
= inst
.operands
[1].imm
>> 8;
17252 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17253 16, 64, 32, 64, 32, 128, -1);
17254 if (align_good
== FAIL
)
17256 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
17257 _("bad list length"));
17258 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17259 inst
.instruction
|= 1 << 5;
17260 if (et
.size
== 32 && align
== 128)
17261 inst
.instruction
|= 0x3 << 6;
17263 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17270 inst
.instruction
|= do_alignment
<< 4;
17273 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17274 apart from bits [11:4]. */
17277 do_neon_ldx_stx (void)
17279 if (inst
.operands
[1].isreg
)
17280 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17282 switch (NEON_LANE (inst
.operands
[0].imm
))
17284 case NEON_INTERLEAVE_LANES
:
17285 NEON_ENCODE (INTERLV
, inst
);
17286 do_neon_ld_st_interleave ();
17289 case NEON_ALL_LANES
:
17290 NEON_ENCODE (DUP
, inst
);
17291 if (inst
.instruction
== N_INV
)
17293 first_error ("only loads support such operands");
17300 NEON_ENCODE (LANE
, inst
);
17301 do_neon_ld_st_lane ();
17304 /* L bit comes from bit mask. */
17305 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17306 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17307 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17309 if (inst
.operands
[1].postind
)
17311 int postreg
= inst
.operands
[1].imm
& 0xf;
17312 constraint (!inst
.operands
[1].immisreg
,
17313 _("post-index must be a register"));
17314 constraint (postreg
== 0xd || postreg
== 0xf,
17315 _("bad register for post-index"));
17316 inst
.instruction
|= postreg
;
17320 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17321 constraint (inst
.reloc
.exp
.X_op
!= O_constant
17322 || inst
.reloc
.exp
.X_add_number
!= 0,
17325 if (inst
.operands
[1].writeback
)
17327 inst
.instruction
|= 0xd;
17330 inst
.instruction
|= 0xf;
17334 inst
.instruction
|= 0xf9000000;
17336 inst
.instruction
|= 0xf4000000;
17341 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17343 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17344 D register operands. */
17345 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17346 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17349 NEON_ENCODE (FPV8
, inst
);
17351 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17353 do_vfp_sp_dyadic ();
17355 /* ARMv8.2 fp16 instruction. */
17357 do_scalar_fp16_v82_encode ();
17360 do_vfp_dp_rd_rn_rm ();
17363 inst
.instruction
|= 0x100;
17365 inst
.instruction
|= 0xf0000000;
17371 set_it_insn_type (OUTSIDE_IT_INSN
);
17373 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17374 first_error (_("invalid instruction shape"));
17380 set_it_insn_type (OUTSIDE_IT_INSN
);
17382 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17385 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17388 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17392 do_vrint_1 (enum neon_cvt_mode mode
)
17394 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17395 struct neon_type_el et
;
17400 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17401 D register operands. */
17402 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17403 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17406 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17408 if (et
.type
!= NT_invtype
)
17410 /* VFP encodings. */
17411 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17412 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17413 set_it_insn_type (OUTSIDE_IT_INSN
);
17415 NEON_ENCODE (FPV8
, inst
);
17416 if (rs
== NS_FF
|| rs
== NS_HH
)
17417 do_vfp_sp_monadic ();
17419 do_vfp_dp_rd_rm ();
17423 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17424 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17425 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17426 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17427 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17428 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17429 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17433 inst
.instruction
|= (rs
== NS_DD
) << 8;
17434 do_vfp_cond_or_thumb ();
17436 /* ARMv8.2 fp16 vrint instruction. */
17438 do_scalar_fp16_v82_encode ();
17442 /* Neon encodings (or something broken...). */
17444 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17446 if (et
.type
== NT_invtype
)
17449 set_it_insn_type (OUTSIDE_IT_INSN
);
17450 NEON_ENCODE (FLOAT
, inst
);
17452 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17455 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17456 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17457 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17458 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17459 inst
.instruction
|= neon_quad (rs
) << 6;
17460 /* Mask off the original size bits and reencode them. */
17461 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17462 | neon_logbits (et
.size
) << 18);
17466 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17467 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17468 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17469 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17470 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17471 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17472 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17477 inst
.instruction
|= 0xfc000000;
17479 inst
.instruction
|= 0xf0000000;
17486 do_vrint_1 (neon_cvt_mode_x
);
17492 do_vrint_1 (neon_cvt_mode_z
);
17498 do_vrint_1 (neon_cvt_mode_r
);
17504 do_vrint_1 (neon_cvt_mode_a
);
17510 do_vrint_1 (neon_cvt_mode_n
);
17516 do_vrint_1 (neon_cvt_mode_p
);
17522 do_vrint_1 (neon_cvt_mode_m
);
17526 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
17528 unsigned regno
= NEON_SCALAR_REG (opnd
);
17529 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
17531 if (elsize
== 16 && elno
< 2 && regno
< 16)
17532 return regno
| (elno
<< 4);
17533 else if (elsize
== 32 && elno
== 0)
17536 first_error (_("scalar out of range"));
17543 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17545 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17546 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17547 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
17548 _("immediate out of range"));
17550 if (inst
.operands
[2].isscalar
)
17552 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
17553 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17554 N_KEY
| N_F16
| N_F32
).size
;
17555 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
17557 inst
.instruction
= 0xfe000800;
17558 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17559 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17560 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17561 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17562 inst
.instruction
|= LOW4 (m
);
17563 inst
.instruction
|= HI1 (m
) << 5;
17564 inst
.instruction
|= neon_quad (rs
) << 6;
17565 inst
.instruction
|= rot
<< 20;
17566 inst
.instruction
|= (size
== 32) << 23;
17570 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17571 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17572 N_KEY
| N_F16
| N_F32
).size
;
17573 neon_three_same (neon_quad (rs
), 0, -1);
17574 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17575 inst
.instruction
|= 0xfc200800;
17576 inst
.instruction
|= rot
<< 23;
17577 inst
.instruction
|= (size
== 32) << 20;
17584 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17586 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17587 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17588 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17589 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17590 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17591 N_KEY
| N_F16
| N_F32
).size
;
17592 neon_three_same (neon_quad (rs
), 0, -1);
17593 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17594 inst
.instruction
|= 0xfc800800;
17595 inst
.instruction
|= (rot
== 270) << 24;
17596 inst
.instruction
|= (size
== 32) << 20;
17599 /* Dot Product instructions encoding support. */
17602 do_neon_dotproduct (int unsigned_p
)
17604 enum neon_shape rs
;
17605 unsigned scalar_oprd2
= 0;
17608 if (inst
.cond
!= COND_ALWAYS
)
17609 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
17610 "is UNPREDICTABLE"));
17612 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17615 /* Dot Product instructions are in three-same D/Q register format or the third
17616 operand can be a scalar index register. */
17617 if (inst
.operands
[2].isscalar
)
17619 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
17620 high8
= 0xfe000000;
17621 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17625 high8
= 0xfc000000;
17626 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17630 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
17632 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
17634 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
17635 Product instruction, so we pass 0 as the "ubit" parameter. And the
17636 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
17637 neon_three_same (neon_quad (rs
), 0, 32);
17639 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
17640 different NEON three-same encoding. */
17641 inst
.instruction
&= 0x00ffffff;
17642 inst
.instruction
|= high8
;
17643 /* Encode 'U' bit which indicates signedness. */
17644 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
17645 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
17646 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
17647 the instruction encoding. */
17648 if (inst
.operands
[2].isscalar
)
17650 inst
.instruction
&= 0xffffffd0;
17651 inst
.instruction
|= LOW4 (scalar_oprd2
);
17652 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
17656 /* Dot Product instructions for signed integer. */
17659 do_neon_dotproduct_s (void)
17661 return do_neon_dotproduct (0);
17664 /* Dot Product instructions for unsigned integer. */
17667 do_neon_dotproduct_u (void)
17669 return do_neon_dotproduct (1);
17672 /* Crypto v1 instructions. */
17674 do_crypto_2op_1 (unsigned elttype
, int op
)
17676 set_it_insn_type (OUTSIDE_IT_INSN
);
17678 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17684 NEON_ENCODE (INTEGER
, inst
);
17685 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17686 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17687 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17688 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17690 inst
.instruction
|= op
<< 6;
17693 inst
.instruction
|= 0xfc000000;
17695 inst
.instruction
|= 0xf0000000;
17699 do_crypto_3op_1 (int u
, int op
)
17701 set_it_insn_type (OUTSIDE_IT_INSN
);
17703 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17704 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17709 NEON_ENCODE (INTEGER
, inst
);
17710 neon_three_same (1, u
, 8 << op
);
17716 do_crypto_2op_1 (N_8
, 0);
17722 do_crypto_2op_1 (N_8
, 1);
17728 do_crypto_2op_1 (N_8
, 2);
17734 do_crypto_2op_1 (N_8
, 3);
17740 do_crypto_3op_1 (0, 0);
17746 do_crypto_3op_1 (0, 1);
17752 do_crypto_3op_1 (0, 2);
17758 do_crypto_3op_1 (0, 3);
17764 do_crypto_3op_1 (1, 0);
17770 do_crypto_3op_1 (1, 1);
17774 do_sha256su1 (void)
17776 do_crypto_3op_1 (1, 2);
17782 do_crypto_2op_1 (N_32
, -1);
17788 do_crypto_2op_1 (N_32
, 0);
17792 do_sha256su0 (void)
17794 do_crypto_2op_1 (N_32
, 1);
17798 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17800 unsigned int Rd
= inst
.operands
[0].reg
;
17801 unsigned int Rn
= inst
.operands
[1].reg
;
17802 unsigned int Rm
= inst
.operands
[2].reg
;
17804 set_it_insn_type (OUTSIDE_IT_INSN
);
17805 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17806 inst
.instruction
|= LOW4 (Rn
) << 16;
17807 inst
.instruction
|= LOW4 (Rm
);
17808 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17809 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17811 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17812 as_warn (UNPRED_REG ("r15"));
17854 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17856 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
17857 do_vfp_sp_dp_cvt ();
17858 do_vfp_cond_or_thumb ();
17862 /* Overall per-instruction processing. */
17864 /* We need to be able to fix up arbitrary expressions in some statements.
17865 This is so that we can handle symbols that are an arbitrary distance from
17866 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17867 which returns part of an address in a form which will be valid for
17868 a data instruction. We do this by pushing the expression into a symbol
17869 in the expr_section, and creating a fix for that. */
17872 fix_new_arm (fragS
* frag
,
17886 /* Create an absolute valued symbol, so we have something to
17887 refer to in the object file. Unfortunately for us, gas's
17888 generic expression parsing will already have folded out
17889 any use of .set foo/.type foo %function that may have
17890 been used to set type information of the target location,
17891 that's being specified symbolically. We have to presume
17892 the user knows what they are doing. */
17896 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17898 symbol
= symbol_find_or_make (name
);
17899 S_SET_SEGMENT (symbol
, absolute_section
);
17900 symbol_set_frag (symbol
, &zero_address_frag
);
17901 S_SET_VALUE (symbol
, exp
->X_add_number
);
17902 exp
->X_op
= O_symbol
;
17903 exp
->X_add_symbol
= symbol
;
17904 exp
->X_add_number
= 0;
17910 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17911 (enum bfd_reloc_code_real
) reloc
);
17915 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17916 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17920 /* Mark whether the fix is to a THUMB instruction, or an ARM
17922 new_fix
->tc_fix_data
= thumb_mode
;
17925 /* Create a frg for an instruction requiring relaxation. */
17927 output_relax_insn (void)
17933 /* The size of the instruction is unknown, so tie the debug info to the
17934 start of the instruction. */
17935 dwarf2_emit_insn (0);
17937 switch (inst
.reloc
.exp
.X_op
)
17940 sym
= inst
.reloc
.exp
.X_add_symbol
;
17941 offset
= inst
.reloc
.exp
.X_add_number
;
17945 offset
= inst
.reloc
.exp
.X_add_number
;
17948 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17952 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17953 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17954 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17957 /* Write a 32-bit thumb instruction to buf. */
17959 put_thumb32_insn (char * buf
, unsigned long insn
)
17961 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17962 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17966 output_inst (const char * str
)
17972 as_bad ("%s -- `%s'", inst
.error
, str
);
17977 output_relax_insn ();
17980 if (inst
.size
== 0)
17983 to
= frag_more (inst
.size
);
17984 /* PR 9814: Record the thumb mode into the current frag so that we know
17985 what type of NOP padding to use, if necessary. We override any previous
17986 setting so that if the mode has changed then the NOPS that we use will
17987 match the encoding of the last instruction in the frag. */
17988 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17990 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17992 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17993 put_thumb32_insn (to
, inst
.instruction
);
17995 else if (inst
.size
> INSN_SIZE
)
17997 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17998 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17999 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
18002 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
18004 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
18005 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
18006 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
18009 dwarf2_emit_insn (inst
.size
);
18013 output_it_inst (int cond
, int mask
, char * to
)
18015 unsigned long instruction
= 0xbf00;
18018 instruction
|= mask
;
18019 instruction
|= cond
<< 4;
18023 to
= frag_more (2);
18025 dwarf2_emit_insn (2);
18029 md_number_to_chars (to
, instruction
, 2);
18034 /* Tag values used in struct asm_opcode's tag field. */
18037 OT_unconditional
, /* Instruction cannot be conditionalized.
18038 The ARM condition field is still 0xE. */
18039 OT_unconditionalF
, /* Instruction cannot be conditionalized
18040 and carries 0xF in its ARM condition field. */
18041 OT_csuffix
, /* Instruction takes a conditional suffix. */
18042 OT_csuffixF
, /* Some forms of the instruction take a conditional
18043 suffix, others place 0xF where the condition field
18045 OT_cinfix3
, /* Instruction takes a conditional infix,
18046 beginning at character index 3. (In
18047 unified mode, it becomes a suffix.) */
18048 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
18049 tsts, cmps, cmns, and teqs. */
18050 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
18051 character index 3, even in unified mode. Used for
18052 legacy instructions where suffix and infix forms
18053 may be ambiguous. */
18054 OT_csuf_or_in3
, /* Instruction takes either a conditional
18055 suffix or an infix at character index 3. */
18056 OT_odd_infix_unc
, /* This is the unconditional variant of an
18057 instruction that takes a conditional infix
18058 at an unusual position. In unified mode,
18059 this variant will accept a suffix. */
18060 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
18061 are the conditional variants of instructions that
18062 take conditional infixes in unusual positions.
18063 The infix appears at character index
18064 (tag - OT_odd_infix_0). These are not accepted
18065 in unified mode. */
18068 /* Subroutine of md_assemble, responsible for looking up the primary
18069 opcode from the mnemonic the user wrote. STR points to the
18070 beginning of the mnemonic.
18072 This is not simply a hash table lookup, because of conditional
18073 variants. Most instructions have conditional variants, which are
18074 expressed with a _conditional affix_ to the mnemonic. If we were
18075 to encode each conditional variant as a literal string in the opcode
18076 table, it would have approximately 20,000 entries.
18078 Most mnemonics take this affix as a suffix, and in unified syntax,
18079 'most' is upgraded to 'all'. However, in the divided syntax, some
18080 instructions take the affix as an infix, notably the s-variants of
18081 the arithmetic instructions. Of those instructions, all but six
18082 have the infix appear after the third character of the mnemonic.
18084 Accordingly, the algorithm for looking up primary opcodes given
18087 1. Look up the identifier in the opcode table.
18088 If we find a match, go to step U.
18090 2. Look up the last two characters of the identifier in the
18091 conditions table. If we find a match, look up the first N-2
18092 characters of the identifier in the opcode table. If we
18093 find a match, go to step CE.
18095 3. Look up the fourth and fifth characters of the identifier in
18096 the conditions table. If we find a match, extract those
18097 characters from the identifier, and look up the remaining
18098 characters in the opcode table. If we find a match, go
18103 U. Examine the tag field of the opcode structure, in case this is
18104 one of the six instructions with its conditional infix in an
18105 unusual place. If it is, the tag tells us where to find the
18106 infix; look it up in the conditions table and set inst.cond
18107 accordingly. Otherwise, this is an unconditional instruction.
18108 Again set inst.cond accordingly. Return the opcode structure.
18110 CE. Examine the tag field to make sure this is an instruction that
18111 should receive a conditional suffix. If it is not, fail.
18112 Otherwise, set inst.cond from the suffix we already looked up,
18113 and return the opcode structure.
18115 CM. Examine the tag field to make sure this is an instruction that
18116 should receive a conditional infix after the third character.
18117 If it is not, fail. Otherwise, undo the edits to the current
18118 line of input and proceed as for case CE. */
18120 static const struct asm_opcode
*
18121 opcode_lookup (char **str
)
18125 const struct asm_opcode
*opcode
;
18126 const struct asm_cond
*cond
;
18129 /* Scan up to the end of the mnemonic, which must end in white space,
18130 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
18131 for (base
= end
= *str
; *end
!= '\0'; end
++)
18132 if (*end
== ' ' || *end
== '.')
18138 /* Handle a possible width suffix and/or Neon type suffix. */
18143 /* The .w and .n suffixes are only valid if the unified syntax is in
18145 if (unified_syntax
&& end
[1] == 'w')
18147 else if (unified_syntax
&& end
[1] == 'n')
18152 inst
.vectype
.elems
= 0;
18154 *str
= end
+ offset
;
18156 if (end
[offset
] == '.')
18158 /* See if we have a Neon type suffix (possible in either unified or
18159 non-unified ARM syntax mode). */
18160 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
18163 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
18169 /* Look for unaffixed or special-case affixed mnemonic. */
18170 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18175 if (opcode
->tag
< OT_odd_infix_0
)
18177 inst
.cond
= COND_ALWAYS
;
18181 if (warn_on_deprecated
&& unified_syntax
)
18182 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18183 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
18184 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18187 inst
.cond
= cond
->value
;
18191 /* Cannot have a conditional suffix on a mnemonic of less than two
18193 if (end
- base
< 3)
18196 /* Look for suffixed mnemonic. */
18198 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18199 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18201 if (opcode
&& cond
)
18204 switch (opcode
->tag
)
18206 case OT_cinfix3_legacy
:
18207 /* Ignore conditional suffixes matched on infix only mnemonics. */
18211 case OT_cinfix3_deprecated
:
18212 case OT_odd_infix_unc
:
18213 if (!unified_syntax
)
18215 /* Fall through. */
18219 case OT_csuf_or_in3
:
18220 inst
.cond
= cond
->value
;
18223 case OT_unconditional
:
18224 case OT_unconditionalF
:
18226 inst
.cond
= cond
->value
;
18229 /* Delayed diagnostic. */
18230 inst
.error
= BAD_COND
;
18231 inst
.cond
= COND_ALWAYS
;
18240 /* Cannot have a usual-position infix on a mnemonic of less than
18241 six characters (five would be a suffix). */
18242 if (end
- base
< 6)
18245 /* Look for infixed mnemonic in the usual position. */
18247 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18251 memcpy (save
, affix
, 2);
18252 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
18253 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18255 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
18256 memcpy (affix
, save
, 2);
18259 && (opcode
->tag
== OT_cinfix3
18260 || opcode
->tag
== OT_cinfix3_deprecated
18261 || opcode
->tag
== OT_csuf_or_in3
18262 || opcode
->tag
== OT_cinfix3_legacy
))
18265 if (warn_on_deprecated
&& unified_syntax
18266 && (opcode
->tag
== OT_cinfix3
18267 || opcode
->tag
== OT_cinfix3_deprecated
))
18268 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18270 inst
.cond
= cond
->value
;
18277 /* This function generates an initial IT instruction, leaving its block
18278 virtually open for the new instructions. Eventually,
18279 the mask will be updated by now_it_add_mask () each time
18280 a new instruction needs to be included in the IT block.
18281 Finally, the block is closed with close_automatic_it_block ().
18282 The block closure can be requested either from md_assemble (),
18283 a tencode (), or due to a label hook. */
18286 new_automatic_it_block (int cond
)
18288 now_it
.state
= AUTOMATIC_IT_BLOCK
;
18289 now_it
.mask
= 0x18;
18291 now_it
.block_length
= 1;
18292 mapping_state (MAP_THUMB
);
18293 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
18294 now_it
.warn_deprecated
= FALSE
;
18295 now_it
.insn_cond
= TRUE
;
18298 /* Close an automatic IT block.
18299 See comments in new_automatic_it_block (). */
18302 close_automatic_it_block (void)
18304 now_it
.mask
= 0x10;
18305 now_it
.block_length
= 0;
18308 /* Update the mask of the current automatically-generated IT
18309 instruction. See comments in new_automatic_it_block (). */
18312 now_it_add_mask (int cond
)
18314 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
18315 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
18316 | ((bitvalue) << (nbit)))
18317 const int resulting_bit
= (cond
& 1);
18319 now_it
.mask
&= 0xf;
18320 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18322 (5 - now_it
.block_length
));
18323 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18325 ((5 - now_it
.block_length
) - 1) );
18326 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
18329 #undef SET_BIT_VALUE
18332 /* The IT blocks handling machinery is accessed through the these functions:
18333 it_fsm_pre_encode () from md_assemble ()
18334 set_it_insn_type () optional, from the tencode functions
18335 set_it_insn_type_last () ditto
18336 in_it_block () ditto
18337 it_fsm_post_encode () from md_assemble ()
18338 force_automatic_it_block_close () from label handling functions
18341 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
18342 initializing the IT insn type with a generic initial value depending
18343 on the inst.condition.
18344 2) During the tencode function, two things may happen:
18345 a) The tencode function overrides the IT insn type by
18346 calling either set_it_insn_type (type) or set_it_insn_type_last ().
18347 b) The tencode function queries the IT block state by
18348 calling in_it_block () (i.e. to determine narrow/not narrow mode).
18350 Both set_it_insn_type and in_it_block run the internal FSM state
18351 handling function (handle_it_state), because: a) setting the IT insn
18352 type may incur in an invalid state (exiting the function),
18353 and b) querying the state requires the FSM to be updated.
18354 Specifically we want to avoid creating an IT block for conditional
18355 branches, so it_fsm_pre_encode is actually a guess and we can't
18356 determine whether an IT block is required until the tencode () routine
18357 has decided what type of instruction this actually it.
18358 Because of this, if set_it_insn_type and in_it_block have to be used,
18359 set_it_insn_type has to be called first.
18361 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
18362 determines the insn IT type depending on the inst.cond code.
18363 When a tencode () routine encodes an instruction that can be
18364 either outside an IT block, or, in the case of being inside, has to be
18365 the last one, set_it_insn_type_last () will determine the proper
18366 IT instruction type based on the inst.cond code. Otherwise,
18367 set_it_insn_type can be called for overriding that logic or
18368 for covering other cases.
18370 Calling handle_it_state () may not transition the IT block state to
18371 OUTSIDE_IT_BLOCK immediately, since the (current) state could be
18372 still queried. Instead, if the FSM determines that the state should
18373 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
18374 after the tencode () function: that's what it_fsm_post_encode () does.
18376 Since in_it_block () calls the state handling function to get an
18377 updated state, an error may occur (due to invalid insns combination).
18378 In that case, inst.error is set.
18379 Therefore, inst.error has to be checked after the execution of
18380 the tencode () routine.
18382 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
18383 any pending state change (if any) that didn't take place in
18384 handle_it_state () as explained above. */
18387 it_fsm_pre_encode (void)
18389 if (inst
.cond
!= COND_ALWAYS
)
18390 inst
.it_insn_type
= INSIDE_IT_INSN
;
18392 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
18394 now_it
.state_handled
= 0;
18397 /* IT state FSM handling function. */
18400 handle_it_state (void)
18402 now_it
.state_handled
= 1;
18403 now_it
.insn_cond
= FALSE
;
18405 switch (now_it
.state
)
18407 case OUTSIDE_IT_BLOCK
:
18408 switch (inst
.it_insn_type
)
18410 case OUTSIDE_IT_INSN
:
18413 case INSIDE_IT_INSN
:
18414 case INSIDE_IT_LAST_INSN
:
18415 if (thumb_mode
== 0)
18418 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
18419 as_tsktsk (_("Warning: conditional outside an IT block"\
18424 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
18425 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
18427 /* Automatically generate the IT instruction. */
18428 new_automatic_it_block (inst
.cond
);
18429 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
18430 close_automatic_it_block ();
18434 inst
.error
= BAD_OUT_IT
;
18440 case IF_INSIDE_IT_LAST_INSN
:
18441 case NEUTRAL_IT_INSN
:
18445 now_it
.state
= MANUAL_IT_BLOCK
;
18446 now_it
.block_length
= 0;
18451 case AUTOMATIC_IT_BLOCK
:
18452 /* Three things may happen now:
18453 a) We should increment current it block size;
18454 b) We should close current it block (closing insn or 4 insns);
18455 c) We should close current it block and start a new one (due
18456 to incompatible conditions or
18457 4 insns-length block reached). */
18459 switch (inst
.it_insn_type
)
18461 case OUTSIDE_IT_INSN
:
18462 /* The closure of the block shall happen immediately,
18463 so any in_it_block () call reports the block as closed. */
18464 force_automatic_it_block_close ();
18467 case INSIDE_IT_INSN
:
18468 case INSIDE_IT_LAST_INSN
:
18469 case IF_INSIDE_IT_LAST_INSN
:
18470 now_it
.block_length
++;
18472 if (now_it
.block_length
> 4
18473 || !now_it_compatible (inst
.cond
))
18475 force_automatic_it_block_close ();
18476 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18477 new_automatic_it_block (inst
.cond
);
18481 now_it
.insn_cond
= TRUE
;
18482 now_it_add_mask (inst
.cond
);
18485 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18486 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18487 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18488 close_automatic_it_block ();
18491 case NEUTRAL_IT_INSN
:
18492 now_it
.block_length
++;
18493 now_it
.insn_cond
= TRUE
;
18495 if (now_it
.block_length
> 4)
18496 force_automatic_it_block_close ();
18498 now_it_add_mask (now_it
.cc
& 1);
18502 close_automatic_it_block ();
18503 now_it
.state
= MANUAL_IT_BLOCK
;
18508 case MANUAL_IT_BLOCK
:
18510 /* Check conditional suffixes. */
18511 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18514 now_it
.mask
&= 0x1f;
18515 is_last
= (now_it
.mask
== 0x10);
18516 now_it
.insn_cond
= TRUE
;
18518 switch (inst
.it_insn_type
)
18520 case OUTSIDE_IT_INSN
:
18521 inst
.error
= BAD_NOT_IT
;
18524 case INSIDE_IT_INSN
:
18525 if (cond
!= inst
.cond
)
18527 inst
.error
= BAD_IT_COND
;
18532 case INSIDE_IT_LAST_INSN
:
18533 case IF_INSIDE_IT_LAST_INSN
:
18534 if (cond
!= inst
.cond
)
18536 inst
.error
= BAD_IT_COND
;
18541 inst
.error
= BAD_BRANCH
;
18546 case NEUTRAL_IT_INSN
:
18547 /* The BKPT instruction is unconditional even in an IT block. */
18551 inst
.error
= BAD_IT_IT
;
18561 struct depr_insn_mask
18563 unsigned long pattern
;
18564 unsigned long mask
;
18565 const char* description
;
18568 /* List of 16-bit instruction patterns deprecated in an IT block in
18570 static const struct depr_insn_mask depr_it_insns
[] = {
18571 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18572 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18573 { 0xa000, 0xb800, N_("ADR") },
18574 { 0x4800, 0xf800, N_("Literal loads") },
18575 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18576 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18577 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18578 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18579 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18584 it_fsm_post_encode (void)
18588 if (!now_it
.state_handled
)
18589 handle_it_state ();
18591 if (now_it
.insn_cond
18592 && !now_it
.warn_deprecated
18593 && warn_on_deprecated
18594 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
18595 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
18597 if (inst
.instruction
>= 0x10000)
18599 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18600 "performance deprecated in ARMv8-A and ARMv8-R"));
18601 now_it
.warn_deprecated
= TRUE
;
18605 const struct depr_insn_mask
*p
= depr_it_insns
;
18607 while (p
->mask
!= 0)
18609 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18611 as_tsktsk (_("IT blocks containing 16-bit Thumb "
18612 "instructions of the following class are "
18613 "performance deprecated in ARMv8-A and "
18614 "ARMv8-R: %s"), p
->description
);
18615 now_it
.warn_deprecated
= TRUE
;
18623 if (now_it
.block_length
> 1)
18625 as_tsktsk (_("IT blocks containing more than one conditional "
18626 "instruction are performance deprecated in ARMv8-A and "
18628 now_it
.warn_deprecated
= TRUE
;
18632 is_last
= (now_it
.mask
== 0x10);
18635 now_it
.state
= OUTSIDE_IT_BLOCK
;
18641 force_automatic_it_block_close (void)
18643 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18645 close_automatic_it_block ();
18646 now_it
.state
= OUTSIDE_IT_BLOCK
;
18654 if (!now_it
.state_handled
)
18655 handle_it_state ();
18657 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18660 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18661 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18662 here, hence the "known" in the function name. */
18665 known_t32_only_insn (const struct asm_opcode
*opcode
)
18667 /* Original Thumb-1 wide instruction. */
18668 if (opcode
->tencode
== do_t_blx
18669 || opcode
->tencode
== do_t_branch23
18670 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18671 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18674 /* Wide-only instruction added to ARMv8-M Baseline. */
18675 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18676 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18677 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18678 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18684 /* Whether wide instruction variant can be used if available for a valid OPCODE
18688 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18690 if (known_t32_only_insn (opcode
))
18693 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18694 of variant T3 of B.W is checked in do_t_branch. */
18695 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18696 && opcode
->tencode
== do_t_branch
)
18699 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
18700 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18701 && opcode
->tencode
== do_t_mov_cmp
18702 /* Make sure CMP instruction is not affected. */
18703 && opcode
->aencode
== do_mov
)
18706 /* Wide instruction variants of all instructions with narrow *and* wide
18707 variants become available with ARMv6t2. Other opcodes are either
18708 narrow-only or wide-only and are thus available if OPCODE is valid. */
18709 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18712 /* OPCODE with narrow only instruction variant or wide variant not
18718 md_assemble (char *str
)
18721 const struct asm_opcode
* opcode
;
18723 /* Align the previous label if needed. */
18724 if (last_label_seen
!= NULL
)
18726 symbol_set_frag (last_label_seen
, frag_now
);
18727 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18728 S_SET_SEGMENT (last_label_seen
, now_seg
);
18731 memset (&inst
, '\0', sizeof (inst
));
18732 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18734 opcode
= opcode_lookup (&p
);
18737 /* It wasn't an instruction, but it might be a register alias of
18738 the form alias .req reg, or a Neon .dn/.qn directive. */
18739 if (! create_register_alias (str
, p
)
18740 && ! create_neon_reg_alias (str
, p
))
18741 as_bad (_("bad instruction `%s'"), str
);
18746 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18747 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18749 /* The value which unconditional instructions should have in place of the
18750 condition field. */
18751 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18755 arm_feature_set variant
;
18757 variant
= cpu_variant
;
18758 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18759 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18760 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18761 /* Check that this instruction is supported for this CPU. */
18762 if (!opcode
->tvariant
18763 || (thumb_mode
== 1
18764 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18766 if (opcode
->tencode
== do_t_swi
)
18767 as_bad (_("SVC is not permitted on this architecture"));
18769 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18772 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18773 && opcode
->tencode
!= do_t_branch
)
18775 as_bad (_("Thumb does not support conditional execution"));
18779 /* Two things are addressed here:
18780 1) Implicit require narrow instructions on Thumb-1.
18781 This avoids relaxation accidentally introducing Thumb-2
18783 2) Reject wide instructions in non Thumb-2 cores.
18785 Only instructions with narrow and wide variants need to be handled
18786 but selecting all non wide-only instructions is easier. */
18787 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18788 && !t32_insn_ok (variant
, opcode
))
18790 if (inst
.size_req
== 0)
18792 else if (inst
.size_req
== 4)
18794 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18795 as_bad (_("selected processor does not support 32bit wide "
18796 "variant of instruction `%s'"), str
);
18798 as_bad (_("selected processor does not support `%s' in "
18799 "Thumb-2 mode"), str
);
18804 inst
.instruction
= opcode
->tvalue
;
18806 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18808 /* Prepare the it_insn_type for those encodings that don't set
18810 it_fsm_pre_encode ();
18812 opcode
->tencode ();
18814 it_fsm_post_encode ();
18817 if (!(inst
.error
|| inst
.relax
))
18819 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18820 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18821 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18823 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18828 /* Something has gone badly wrong if we try to relax a fixed size
18830 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18832 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18833 *opcode
->tvariant
);
18834 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18835 set those bits when Thumb-2 32-bit instructions are seen. The impact
18836 of relaxable instructions will be considered later after we finish all
18838 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18839 variant
= arm_arch_none
;
18841 variant
= cpu_variant
;
18842 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18843 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18846 check_neon_suffixes
;
18850 mapping_state (MAP_THUMB
);
18853 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18857 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18858 is_bx
= (opcode
->aencode
== do_bx
);
18860 /* Check that this instruction is supported for this CPU. */
18861 if (!(is_bx
&& fix_v4bx
)
18862 && !(opcode
->avariant
&&
18863 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18865 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18870 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18874 inst
.instruction
= opcode
->avalue
;
18875 if (opcode
->tag
== OT_unconditionalF
)
18876 inst
.instruction
|= 0xFU
<< 28;
18878 inst
.instruction
|= inst
.cond
<< 28;
18879 inst
.size
= INSN_SIZE
;
18880 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18882 it_fsm_pre_encode ();
18883 opcode
->aencode ();
18884 it_fsm_post_encode ();
18886 /* Arm mode bx is marked as both v4T and v5 because it's still required
18887 on a hypothetical non-thumb v5 core. */
18889 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18891 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18892 *opcode
->avariant
);
18894 check_neon_suffixes
;
18898 mapping_state (MAP_ARM
);
18903 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18911 check_it_blocks_finished (void)
18916 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18917 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18918 == MANUAL_IT_BLOCK
)
18920 as_warn (_("section '%s' finished with an open IT block."),
18924 if (now_it
.state
== MANUAL_IT_BLOCK
)
18925 as_warn (_("file finished with an open IT block."));
18929 /* Various frobbings of labels and their addresses. */
18932 arm_start_line_hook (void)
18934 last_label_seen
= NULL
;
18938 arm_frob_label (symbolS
* sym
)
18940 last_label_seen
= sym
;
18942 ARM_SET_THUMB (sym
, thumb_mode
);
18944 #if defined OBJ_COFF || defined OBJ_ELF
18945 ARM_SET_INTERWORK (sym
, support_interwork
);
18948 force_automatic_it_block_close ();
18950 /* Note - do not allow local symbols (.Lxxx) to be labelled
18951 as Thumb functions. This is because these labels, whilst
18952 they exist inside Thumb code, are not the entry points for
18953 possible ARM->Thumb calls. Also, these labels can be used
18954 as part of a computed goto or switch statement. eg gcc
18955 can generate code that looks like this:
18957 ldr r2, [pc, .Laaa]
18967 The first instruction loads the address of the jump table.
18968 The second instruction converts a table index into a byte offset.
18969 The third instruction gets the jump address out of the table.
18970 The fourth instruction performs the jump.
18972 If the address stored at .Laaa is that of a symbol which has the
18973 Thumb_Func bit set, then the linker will arrange for this address
18974 to have the bottom bit set, which in turn would mean that the
18975 address computation performed by the third instruction would end
18976 up with the bottom bit set. Since the ARM is capable of unaligned
18977 word loads, the instruction would then load the incorrect address
18978 out of the jump table, and chaos would ensue. */
18979 if (label_is_thumb_function_name
18980 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18981 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18983 /* When the address of a Thumb function is taken the bottom
18984 bit of that address should be set. This will allow
18985 interworking between Arm and Thumb functions to work
18988 THUMB_SET_FUNC (sym
, 1);
18990 label_is_thumb_function_name
= FALSE
;
18993 dwarf2_emit_label (sym
);
18997 arm_data_in_code (void)
18999 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
19001 *input_line_pointer
= '/';
19002 input_line_pointer
+= 5;
19003 *input_line_pointer
= 0;
19011 arm_canonicalize_symbol_name (char * name
)
19015 if (thumb_mode
&& (len
= strlen (name
)) > 5
19016 && streq (name
+ len
- 5, "/data"))
19017 *(name
+ len
- 5) = 0;
19022 /* Table of all register names defined by default. The user can
19023 define additional names with .req. Note that all register names
19024 should appear in both upper and lowercase variants. Some registers
19025 also have mixed-case names. */
19027 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
19028 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
19029 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
19030 #define REGSET(p,t) \
19031 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
19032 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
19033 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
19034 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
19035 #define REGSETH(p,t) \
19036 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
19037 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
19038 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
19039 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
19040 #define REGSET2(p,t) \
19041 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
19042 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
19043 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
19044 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
19045 #define SPLRBANK(base,bank,t) \
19046 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
19047 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
19048 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
19049 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
19050 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
19051 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
19053 static const struct reg_entry reg_names
[] =
19055 /* ARM integer registers. */
19056 REGSET(r
, RN
), REGSET(R
, RN
),
19058 /* ATPCS synonyms. */
19059 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
19060 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
19061 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
19063 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
19064 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
19065 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
19067 /* Well-known aliases. */
19068 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
19069 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
19071 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
19072 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
19074 /* Coprocessor numbers. */
19075 REGSET(p
, CP
), REGSET(P
, CP
),
19077 /* Coprocessor register numbers. The "cr" variants are for backward
19079 REGSET(c
, CN
), REGSET(C
, CN
),
19080 REGSET(cr
, CN
), REGSET(CR
, CN
),
19082 /* ARM banked registers. */
19083 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
19084 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
19085 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
19086 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
19087 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
19088 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
19089 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
19091 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
19092 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
19093 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
19094 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
19095 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
19096 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
19097 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
19098 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
19100 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
19101 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
19102 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
19103 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
19104 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
19105 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
19106 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
19107 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19108 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19110 /* FPA registers. */
19111 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
19112 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
19114 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
19115 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
19117 /* VFP SP registers. */
19118 REGSET(s
,VFS
), REGSET(S
,VFS
),
19119 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
19121 /* VFP DP Registers. */
19122 REGSET(d
,VFD
), REGSET(D
,VFD
),
19123 /* Extra Neon DP registers. */
19124 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
19126 /* Neon QP registers. */
19127 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
19129 /* VFP control registers. */
19130 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
19131 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
19132 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
19133 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
19134 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
19135 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
19136 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
19138 /* Maverick DSP coprocessor registers. */
19139 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
19140 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
19142 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
19143 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
19144 REGDEF(dspsc
,0,DSPSC
),
19146 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
19147 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
19148 REGDEF(DSPSC
,0,DSPSC
),
19150 /* iWMMXt data registers - p0, c0-15. */
19151 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
19153 /* iWMMXt control registers - p1, c0-3. */
19154 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
19155 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
19156 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
19157 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
19159 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
19160 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
19161 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
19162 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
19163 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
19165 /* XScale accumulator registers. */
19166 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
19172 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
19173 within psr_required_here. */
19174 static const struct asm_psr psrs
[] =
19176 /* Backward compatibility notation. Note that "all" is no longer
19177 truly all possible PSR bits. */
19178 {"all", PSR_c
| PSR_f
},
19182 /* Individual flags. */
19188 /* Combinations of flags. */
19189 {"fs", PSR_f
| PSR_s
},
19190 {"fx", PSR_f
| PSR_x
},
19191 {"fc", PSR_f
| PSR_c
},
19192 {"sf", PSR_s
| PSR_f
},
19193 {"sx", PSR_s
| PSR_x
},
19194 {"sc", PSR_s
| PSR_c
},
19195 {"xf", PSR_x
| PSR_f
},
19196 {"xs", PSR_x
| PSR_s
},
19197 {"xc", PSR_x
| PSR_c
},
19198 {"cf", PSR_c
| PSR_f
},
19199 {"cs", PSR_c
| PSR_s
},
19200 {"cx", PSR_c
| PSR_x
},
19201 {"fsx", PSR_f
| PSR_s
| PSR_x
},
19202 {"fsc", PSR_f
| PSR_s
| PSR_c
},
19203 {"fxs", PSR_f
| PSR_x
| PSR_s
},
19204 {"fxc", PSR_f
| PSR_x
| PSR_c
},
19205 {"fcs", PSR_f
| PSR_c
| PSR_s
},
19206 {"fcx", PSR_f
| PSR_c
| PSR_x
},
19207 {"sfx", PSR_s
| PSR_f
| PSR_x
},
19208 {"sfc", PSR_s
| PSR_f
| PSR_c
},
19209 {"sxf", PSR_s
| PSR_x
| PSR_f
},
19210 {"sxc", PSR_s
| PSR_x
| PSR_c
},
19211 {"scf", PSR_s
| PSR_c
| PSR_f
},
19212 {"scx", PSR_s
| PSR_c
| PSR_x
},
19213 {"xfs", PSR_x
| PSR_f
| PSR_s
},
19214 {"xfc", PSR_x
| PSR_f
| PSR_c
},
19215 {"xsf", PSR_x
| PSR_s
| PSR_f
},
19216 {"xsc", PSR_x
| PSR_s
| PSR_c
},
19217 {"xcf", PSR_x
| PSR_c
| PSR_f
},
19218 {"xcs", PSR_x
| PSR_c
| PSR_s
},
19219 {"cfs", PSR_c
| PSR_f
| PSR_s
},
19220 {"cfx", PSR_c
| PSR_f
| PSR_x
},
19221 {"csf", PSR_c
| PSR_s
| PSR_f
},
19222 {"csx", PSR_c
| PSR_s
| PSR_x
},
19223 {"cxf", PSR_c
| PSR_x
| PSR_f
},
19224 {"cxs", PSR_c
| PSR_x
| PSR_s
},
19225 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
19226 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
19227 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
19228 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
19229 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
19230 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
19231 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
19232 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
19233 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
19234 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
19235 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
19236 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
19237 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
19238 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
19239 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
19240 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
19241 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
19242 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
19243 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
19244 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
19245 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
19246 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
19247 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
19248 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
19251 /* Table of V7M psr names. */
19252 static const struct asm_psr v7m_psrs
[] =
19254 {"apsr", 0x0 }, {"APSR", 0x0 },
19255 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
19256 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
19257 {"psr", 0x3 }, {"PSR", 0x3 },
19258 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
19259 {"ipsr", 0x5 }, {"IPSR", 0x5 },
19260 {"epsr", 0x6 }, {"EPSR", 0x6 },
19261 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
19262 {"msp", 0x8 }, {"MSP", 0x8 },
19263 {"psp", 0x9 }, {"PSP", 0x9 },
19264 {"msplim", 0xa }, {"MSPLIM", 0xa },
19265 {"psplim", 0xb }, {"PSPLIM", 0xb },
19266 {"primask", 0x10}, {"PRIMASK", 0x10},
19267 {"basepri", 0x11}, {"BASEPRI", 0x11},
19268 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
19269 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
19270 {"control", 0x14}, {"CONTROL", 0x14},
19271 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
19272 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
19273 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
19274 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
19275 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
19276 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
19277 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
19278 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
19279 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
19282 /* Table of all shift-in-operand names. */
19283 static const struct asm_shift_name shift_names
[] =
19285 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
19286 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
19287 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
19288 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
19289 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
19290 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
19293 /* Table of all explicit relocation names. */
19295 static struct reloc_entry reloc_names
[] =
19297 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
19298 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
19299 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
19300 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
19301 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
19302 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
19303 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
19304 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
19305 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
19306 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
19307 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
19308 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
19309 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
19310 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
19311 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
19312 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
19313 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
19314 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
19315 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
19316 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
19317 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
19318 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
19319 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
19320 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
19321 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
19322 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
19323 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
19327 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
19328 static const struct asm_cond conds
[] =
19332 {"cs", 0x2}, {"hs", 0x2},
19333 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
19347 #define UL_BARRIER(L,U,CODE,FEAT) \
19348 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
19349 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
19351 static struct asm_barrier_opt barrier_opt_names
[] =
19353 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
19354 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
19355 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
19356 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
19357 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
19358 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
19359 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
19360 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
19361 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
19362 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
19363 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
19364 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
19365 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
19366 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
19367 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
19368 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
19373 /* Table of ARM-format instructions. */
19375 /* Macros for gluing together operand strings. N.B. In all cases
19376 other than OPS0, the trailing OP_stop comes from default
19377 zero-initialization of the unspecified elements of the array. */
19378 #define OPS0() { OP_stop, }
19379 #define OPS1(a) { OP_##a, }
19380 #define OPS2(a,b) { OP_##a,OP_##b, }
19381 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
19382 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
19383 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
19384 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
19386 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
19387 This is useful when mixing operands for ARM and THUMB, i.e. using the
19388 MIX_ARM_THUMB_OPERANDS macro.
19389 In order to use these macros, prefix the number of operands with _
19391 #define OPS_1(a) { a, }
19392 #define OPS_2(a,b) { a,b, }
19393 #define OPS_3(a,b,c) { a,b,c, }
19394 #define OPS_4(a,b,c,d) { a,b,c,d, }
19395 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
19396 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
19398 /* These macros abstract out the exact format of the mnemonic table and
19399 save some repeated characters. */
19401 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
19402 #define TxCE(mnem, op, top, nops, ops, ae, te) \
19403 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
19404 THUMB_VARIANT, do_##ae, do_##te }
19406 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
19407 a T_MNEM_xyz enumerator. */
19408 #define TCE(mnem, aop, top, nops, ops, ae, te) \
19409 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
19410 #define tCE(mnem, aop, top, nops, ops, ae, te) \
19411 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19413 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
19414 infix after the third character. */
19415 #define TxC3(mnem, op, top, nops, ops, ae, te) \
19416 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
19417 THUMB_VARIANT, do_##ae, do_##te }
19418 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
19419 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
19420 THUMB_VARIANT, do_##ae, do_##te }
19421 #define TC3(mnem, aop, top, nops, ops, ae, te) \
19422 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
19423 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
19424 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
19425 #define tC3(mnem, aop, top, nops, ops, ae, te) \
19426 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19427 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
19428 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19430 /* Mnemonic that cannot be conditionalized. The ARM condition-code
19431 field is still 0xE. Many of the Thumb variants can be executed
19432 conditionally, so this is checked separately. */
19433 #define TUE(mnem, op, top, nops, ops, ae, te) \
19434 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19435 THUMB_VARIANT, do_##ae, do_##te }
19437 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
19438 Used by mnemonics that have very minimal differences in the encoding for
19439 ARM and Thumb variants and can be handled in a common function. */
19440 #define TUEc(mnem, op, top, nops, ops, en) \
19441 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19442 THUMB_VARIANT, do_##en, do_##en }
19444 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
19445 condition code field. */
19446 #define TUF(mnem, op, top, nops, ops, ae, te) \
19447 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19448 THUMB_VARIANT, do_##ae, do_##te }
19450 /* ARM-only variants of all the above. */
19451 #define CE(mnem, op, nops, ops, ae) \
19452 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19454 #define C3(mnem, op, nops, ops, ae) \
19455 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19457 /* Thumb-only variants of TCE and TUE. */
19458 #define ToC(mnem, top, nops, ops, te) \
19459 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
19462 #define ToU(mnem, top, nops, ops, te) \
19463 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
19466 /* Legacy mnemonics that always have conditional infix after the third
19468 #define CL(mnem, op, nops, ops, ae) \
19469 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19470 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19472 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19473 #define cCE(mnem, op, nops, ops, ae) \
19474 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19476 /* Legacy coprocessor instructions where conditional infix and conditional
19477 suffix are ambiguous. For consistency this includes all FPA instructions,
19478 not just the potentially ambiguous ones. */
19479 #define cCL(mnem, op, nops, ops, ae) \
19480 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19481 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19483 /* Coprocessor, takes either a suffix or a position-3 infix
19484 (for an FPA corner case). */
19485 #define C3E(mnem, op, nops, ops, ae) \
19486 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19487 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19489 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19490 { m1 #m2 m3, OPS##nops ops, \
19491 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19492 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19494 #define CM(m1, m2, op, nops, ops, ae) \
19495 xCM_ (m1, , m2, op, nops, ops, ae), \
19496 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19497 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19498 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19499 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19500 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19501 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19502 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19503 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19504 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19505 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19506 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19507 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19508 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19509 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19510 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19511 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19512 xCM_ (m1, le, m2, op, nops, ops, ae), \
19513 xCM_ (m1, al, m2, op, nops, ops, ae)
19515 #define UE(mnem, op, nops, ops, ae) \
19516 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19518 #define UF(mnem, op, nops, ops, ae) \
19519 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19521 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19522 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19523 use the same encoding function for each. */
19524 #define NUF(mnem, op, nops, ops, enc) \
19525 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19526 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19528 /* Neon data processing, version which indirects through neon_enc_tab for
19529 the various overloaded versions of opcodes. */
19530 #define nUF(mnem, op, nops, ops, enc) \
19531 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19532 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19534 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19536 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19537 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19538 THUMB_VARIANT, do_##enc, do_##enc }
19540 #define NCE(mnem, op, nops, ops, enc) \
19541 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19543 #define NCEF(mnem, op, nops, ops, enc) \
19544 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19546 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19547 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19548 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19549 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19551 #define nCE(mnem, op, nops, ops, enc) \
19552 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19554 #define nCEF(mnem, op, nops, ops, enc) \
19555 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19559 static const struct asm_opcode insns
[] =
19561 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19562 #define THUMB_VARIANT & arm_ext_v4t
19563 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19564 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19565 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19566 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19567 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19568 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19569 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19570 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19571 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19572 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19573 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19574 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19575 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19576 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19577 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19578 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19580 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19581 for setting PSR flag bits. They are obsolete in V6 and do not
19582 have Thumb equivalents. */
19583 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19584 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19585 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19586 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19587 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19588 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19589 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19590 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19591 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19593 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19594 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19595 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19596 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19598 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19599 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19600 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19602 OP_ADDRGLDR
),ldst
, t_ldst
),
19603 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19605 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19606 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19607 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19608 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19609 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19610 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19612 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19613 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19616 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19617 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19618 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19619 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19621 /* Thumb-compatibility pseudo ops. */
19622 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19623 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19624 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19625 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19626 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19627 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19628 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19629 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19630 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19631 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19632 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19633 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19635 /* These may simplify to neg. */
19636 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19637 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19639 #undef THUMB_VARIANT
19640 #define THUMB_VARIANT & arm_ext_os
19642 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19643 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19645 #undef THUMB_VARIANT
19646 #define THUMB_VARIANT & arm_ext_v6
19648 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19650 /* V1 instructions with no Thumb analogue prior to V6T2. */
19651 #undef THUMB_VARIANT
19652 #define THUMB_VARIANT & arm_ext_v6t2
19654 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19655 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19656 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19658 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19659 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19660 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19661 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19663 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19664 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19666 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19667 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19669 /* V1 instructions with no Thumb analogue at all. */
19670 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19671 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19673 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19674 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19675 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19676 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19677 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19678 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19679 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19680 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19683 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19684 #undef THUMB_VARIANT
19685 #define THUMB_VARIANT & arm_ext_v4t
19687 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19688 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19690 #undef THUMB_VARIANT
19691 #define THUMB_VARIANT & arm_ext_v6t2
19693 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19694 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19696 /* Generic coprocessor instructions. */
19697 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19698 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19699 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19700 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19701 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19702 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19703 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19706 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19708 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19709 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19712 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19713 #undef THUMB_VARIANT
19714 #define THUMB_VARIANT & arm_ext_msr
19716 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19717 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19720 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19721 #undef THUMB_VARIANT
19722 #define THUMB_VARIANT & arm_ext_v6t2
19724 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19725 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19726 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19727 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19728 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19729 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19730 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19731 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19734 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19735 #undef THUMB_VARIANT
19736 #define THUMB_VARIANT & arm_ext_v4t
19738 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19739 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19740 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19741 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19742 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19743 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19746 #define ARM_VARIANT & arm_ext_v4t_5
19748 /* ARM Architecture 4T. */
19749 /* Note: bx (and blx) are required on V5, even if the processor does
19750 not support Thumb. */
19751 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19754 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19755 #undef THUMB_VARIANT
19756 #define THUMB_VARIANT & arm_ext_v5t
19758 /* Note: blx has 2 variants; the .value coded here is for
19759 BLX(2). Only this variant has conditional execution. */
19760 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19761 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19763 #undef THUMB_VARIANT
19764 #define THUMB_VARIANT & arm_ext_v6t2
19766 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19767 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19768 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19769 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19770 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19771 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19772 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19773 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19776 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19777 #undef THUMB_VARIANT
19778 #define THUMB_VARIANT & arm_ext_v5exp
19780 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19781 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19782 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19783 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19785 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19786 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19788 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19789 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19790 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19791 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19793 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19794 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19795 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19796 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19798 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19799 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19801 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19802 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19803 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19804 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19807 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19808 #undef THUMB_VARIANT
19809 #define THUMB_VARIANT & arm_ext_v6t2
19811 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19812 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19814 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19815 ADDRGLDRS
), ldrd
, t_ldstd
),
19817 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19818 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19821 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19823 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19826 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19827 #undef THUMB_VARIANT
19828 #define THUMB_VARIANT & arm_ext_v6
19830 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19831 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19832 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19833 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19834 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19835 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19836 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19837 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19838 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19839 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19841 #undef THUMB_VARIANT
19842 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19844 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19845 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19847 #undef THUMB_VARIANT
19848 #define THUMB_VARIANT & arm_ext_v6t2
19850 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19851 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19853 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19854 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19856 /* ARM V6 not included in V7M. */
19857 #undef THUMB_VARIANT
19858 #define THUMB_VARIANT & arm_ext_v6_notm
19859 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19860 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19861 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19862 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19863 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19864 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19865 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19866 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19867 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19868 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19869 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19870 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19871 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19872 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19873 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19874 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19875 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19876 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19877 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19879 /* ARM V6 not included in V7M (eg. integer SIMD). */
19880 #undef THUMB_VARIANT
19881 #define THUMB_VARIANT & arm_ext_v6_dsp
19882 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19883 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19884 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19885 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19886 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19887 /* Old name for QASX. */
19888 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19889 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19890 /* Old name for QSAX. */
19891 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19892 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19893 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19894 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19895 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19896 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19897 /* Old name for SASX. */
19898 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19899 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19900 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19901 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19902 /* Old name for SHASX. */
19903 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19904 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19905 /* Old name for SHSAX. */
19906 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19907 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19908 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19909 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19910 /* Old name for SSAX. */
19911 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19912 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19913 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19914 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19915 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19916 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19917 /* Old name for UASX. */
19918 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19919 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19920 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19921 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19922 /* Old name for UHASX. */
19923 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19924 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19925 /* Old name for UHSAX. */
19926 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19927 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19928 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19929 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19930 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19931 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19932 /* Old name for UQASX. */
19933 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19934 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19935 /* Old name for UQSAX. */
19936 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19937 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19938 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19939 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19940 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19941 /* Old name for USAX. */
19942 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19943 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19944 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19945 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19946 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19947 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19948 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19949 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19950 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19951 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19952 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19953 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19954 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19955 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19956 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19957 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19958 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19959 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19960 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19961 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19962 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19963 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19964 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19965 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19966 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19967 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19968 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19969 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19970 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19971 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19972 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19973 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19974 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19975 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19978 #define ARM_VARIANT & arm_ext_v6k
19979 #undef THUMB_VARIANT
19980 #define THUMB_VARIANT & arm_ext_v6k
19982 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19983 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19984 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19985 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19987 #undef THUMB_VARIANT
19988 #define THUMB_VARIANT & arm_ext_v6_notm
19989 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19991 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19992 RRnpcb
), strexd
, t_strexd
),
19994 #undef THUMB_VARIANT
19995 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19996 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19998 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
20000 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
20002 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
20004 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
20007 #define ARM_VARIANT & arm_ext_sec
20008 #undef THUMB_VARIANT
20009 #define THUMB_VARIANT & arm_ext_sec
20011 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
20014 #define ARM_VARIANT & arm_ext_virt
20015 #undef THUMB_VARIANT
20016 #define THUMB_VARIANT & arm_ext_virt
20018 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
20019 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
20022 #define ARM_VARIANT & arm_ext_pan
20023 #undef THUMB_VARIANT
20024 #define THUMB_VARIANT & arm_ext_pan
20026 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
20029 #define ARM_VARIANT & arm_ext_v6t2
20030 #undef THUMB_VARIANT
20031 #define THUMB_VARIANT & arm_ext_v6t2
20033 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
20034 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
20035 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
20036 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
20038 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
20039 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
20041 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20042 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20043 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20044 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20047 #define ARM_VARIANT & arm_ext_v3
20048 #undef THUMB_VARIANT
20049 #define THUMB_VARIANT & arm_ext_v6t2
20051 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
20054 #define ARM_VARIANT & arm_ext_v6t2
20055 #undef THUMB_VARIANT
20056 #define THUMB_VARIANT & arm_ext_v6t2_v8m
20057 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
20058 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
20060 /* Thumb-only instructions. */
20062 #define ARM_VARIANT NULL
20063 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
20064 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
20066 /* ARM does not really have an IT instruction, so always allow it.
20067 The opcode is copied from Thumb in order to allow warnings in
20068 -mimplicit-it=[never | arm] modes. */
20070 #define ARM_VARIANT & arm_ext_v1
20071 #undef THUMB_VARIANT
20072 #define THUMB_VARIANT & arm_ext_v6t2
20074 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
20075 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
20076 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
20077 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
20078 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
20079 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
20080 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
20081 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
20082 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
20083 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
20084 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
20085 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
20086 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
20087 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
20088 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
20089 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
20090 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20091 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20093 /* Thumb2 only instructions. */
20095 #define ARM_VARIANT NULL
20097 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20098 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20099 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20100 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20101 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
20102 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
20104 /* Hardware division instructions. */
20106 #define ARM_VARIANT & arm_ext_adiv
20107 #undef THUMB_VARIANT
20108 #define THUMB_VARIANT & arm_ext_div
20110 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20111 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20113 /* ARM V6M/V7 instructions. */
20115 #define ARM_VARIANT & arm_ext_barrier
20116 #undef THUMB_VARIANT
20117 #define THUMB_VARIANT & arm_ext_barrier
20119 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
20120 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
20121 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
20123 /* ARM V7 instructions. */
20125 #define ARM_VARIANT & arm_ext_v7
20126 #undef THUMB_VARIANT
20127 #define THUMB_VARIANT & arm_ext_v7
20129 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
20130 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
20133 #define ARM_VARIANT & arm_ext_mp
20134 #undef THUMB_VARIANT
20135 #define THUMB_VARIANT & arm_ext_mp
20137 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
20139 /* AArchv8 instructions. */
20141 #define ARM_VARIANT & arm_ext_v8
20143 /* Instructions shared between armv8-a and armv8-m. */
20144 #undef THUMB_VARIANT
20145 #define THUMB_VARIANT & arm_ext_atomics
20147 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20148 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20149 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20150 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20151 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20152 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20153 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20154 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
20155 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20156 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20158 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20160 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20162 #undef THUMB_VARIANT
20163 #define THUMB_VARIANT & arm_ext_v8
20165 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
20166 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
20167 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
20169 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
20171 /* ARMv8 T32 only. */
20173 #define ARM_VARIANT NULL
20174 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
20175 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
20176 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
20178 /* FP for ARMv8. */
20180 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
20181 #undef THUMB_VARIANT
20182 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
20184 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20185 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20186 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20187 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20188 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20189 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20190 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
20191 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
20192 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
20193 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
20194 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
20195 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
20196 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
20197 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
20198 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
20199 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
20200 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
20202 /* Crypto v1 extensions. */
20204 #define ARM_VARIANT & fpu_crypto_ext_armv8
20205 #undef THUMB_VARIANT
20206 #define THUMB_VARIANT & fpu_crypto_ext_armv8
20208 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
20209 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
20210 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
20211 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
20212 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
20213 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
20214 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
20215 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
20216 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
20217 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
20218 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
20219 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
20220 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
20221 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
20224 #define ARM_VARIANT & crc_ext_armv8
20225 #undef THUMB_VARIANT
20226 #define THUMB_VARIANT & crc_ext_armv8
20227 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
20228 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
20229 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
20230 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
20231 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
20232 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
20234 /* ARMv8.2 RAS extension. */
20236 #define ARM_VARIANT & arm_ext_ras
20237 #undef THUMB_VARIANT
20238 #define THUMB_VARIANT & arm_ext_ras
20239 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
20242 #define ARM_VARIANT & arm_ext_v8_3
20243 #undef THUMB_VARIANT
20244 #define THUMB_VARIANT & arm_ext_v8_3
20245 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
20246 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
20247 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
20250 #define ARM_VARIANT & fpu_neon_ext_dotprod
20251 #undef THUMB_VARIANT
20252 #define THUMB_VARIANT & fpu_neon_ext_dotprod
20253 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
20254 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
20257 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
20258 #undef THUMB_VARIANT
20259 #define THUMB_VARIANT NULL
20261 cCE("wfs", e200110
, 1, (RR
), rd
),
20262 cCE("rfs", e300110
, 1, (RR
), rd
),
20263 cCE("wfc", e400110
, 1, (RR
), rd
),
20264 cCE("rfc", e500110
, 1, (RR
), rd
),
20266 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20267 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20268 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20269 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20271 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20272 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20273 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20274 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20276 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
20277 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
20278 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
20279 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
20280 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
20281 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
20282 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
20283 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
20284 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
20285 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
20286 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
20287 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
20289 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
20290 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
20291 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
20292 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
20293 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
20294 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
20295 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
20296 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
20297 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
20298 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
20299 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
20300 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
20302 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
20303 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
20304 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
20305 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
20306 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
20307 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
20308 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
20309 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
20310 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
20311 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
20312 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
20313 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
20315 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
20316 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
20317 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
20318 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
20319 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
20320 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
20321 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
20322 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
20323 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
20324 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
20325 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
20326 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
20328 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
20329 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
20330 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
20331 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
20332 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
20333 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
20334 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
20335 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
20336 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
20337 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
20338 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
20339 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
20341 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
20342 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
20343 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
20344 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
20345 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
20346 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
20347 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
20348 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
20349 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
20350 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
20351 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
20352 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
20354 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
20355 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
20356 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
20357 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
20358 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
20359 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
20360 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
20361 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
20362 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
20363 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
20364 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
20365 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
20367 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
20368 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
20369 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
20370 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
20371 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
20372 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
20373 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
20374 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
20375 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
20376 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
20377 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
20378 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
20380 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
20381 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
20382 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
20383 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
20384 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
20385 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
20386 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
20387 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
20388 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
20389 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
20390 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
20391 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
20393 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
20394 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
20395 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
20396 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
20397 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
20398 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
20399 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
20400 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
20401 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
20402 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
20403 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
20404 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
20406 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
20407 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
20408 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
20409 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
20410 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
20411 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
20412 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
20413 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
20414 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
20415 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
20416 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
20417 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
20419 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
20420 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
20421 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
20422 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
20423 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
20424 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
20425 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
20426 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
20427 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
20428 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
20429 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
20430 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
20432 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
20433 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
20434 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
20435 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
20436 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
20437 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
20438 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
20439 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
20440 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
20441 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
20442 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
20443 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
20445 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
20446 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
20447 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
20448 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
20449 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
20450 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
20451 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
20452 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
20453 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
20454 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
20455 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
20456 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
20458 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
20459 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
20460 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
20461 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
20462 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
20463 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
20464 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
20465 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
20466 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
20467 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
20468 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
20469 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
20471 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
20472 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
20473 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
20474 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
20475 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
20476 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
20477 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
20478 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
20479 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
20480 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
20481 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
20482 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
20484 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20485 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20486 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20487 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20488 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20489 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20490 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20491 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20492 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20493 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20494 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20495 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20497 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20498 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20499 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20500 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20501 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20502 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20503 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20504 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20505 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20506 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20507 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20508 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20510 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20511 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20512 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20513 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20514 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20515 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20516 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20517 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20518 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20519 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20520 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20521 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20523 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20524 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20525 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20526 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20527 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20528 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20529 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20530 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20531 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20532 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20533 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20534 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20536 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20537 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20538 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20539 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20540 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20541 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20542 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20543 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20544 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20545 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20546 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20547 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20549 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20550 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20551 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20552 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20553 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20554 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20555 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20556 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20557 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20558 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20559 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20560 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20562 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20563 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20564 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20565 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20566 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20567 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20568 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20569 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20570 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20571 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20572 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20573 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20575 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20576 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20577 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20578 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20579 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20580 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20581 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20582 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20583 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20584 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20585 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20586 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20588 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20589 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20590 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20591 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20592 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20593 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20594 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20595 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20596 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20597 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20598 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20599 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20601 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20602 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20603 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20604 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20605 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20606 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20607 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20608 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20609 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20610 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20611 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20612 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20614 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20615 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20616 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20617 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20618 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20619 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20620 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20621 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20622 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20623 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20624 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20625 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20627 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20628 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20629 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20630 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20631 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20632 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20633 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20634 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20635 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20636 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20637 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20638 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20640 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20641 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20642 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20643 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20644 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20645 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20646 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20647 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20648 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20649 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20650 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20651 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20653 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20654 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20655 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20656 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20658 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20659 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20660 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20661 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20662 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20663 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20664 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20665 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20666 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20667 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20668 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20669 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20671 /* The implementation of the FIX instruction is broken on some
20672 assemblers, in that it accepts a precision specifier as well as a
20673 rounding specifier, despite the fact that this is meaningless.
20674 To be more compatible, we accept it as well, though of course it
20675 does not set any bits. */
20676 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20677 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20678 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20679 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20680 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20681 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20682 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20683 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20684 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20685 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20686 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20687 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20688 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20690 /* Instructions that were new with the real FPA, call them V2. */
20692 #define ARM_VARIANT & fpu_fpa_ext_v2
20694 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20695 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20696 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20697 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20698 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20699 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20702 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20704 /* Moves and type conversions. */
20705 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20706 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20707 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20708 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20709 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20710 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20711 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20712 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20713 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20714 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20715 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20716 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20717 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20718 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20720 /* Memory operations. */
20721 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20722 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20723 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20724 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20725 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20726 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20727 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20728 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20729 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20730 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20731 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20732 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20733 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20734 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20735 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20736 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20737 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20738 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20740 /* Monadic operations. */
20741 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20742 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20743 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20745 /* Dyadic operations. */
20746 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20747 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20748 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20749 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20750 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20751 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20752 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20753 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20754 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20757 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20758 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20759 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20760 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20762 /* Double precision load/store are still present on single precision
20763 implementations. */
20764 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20765 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20766 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20767 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20768 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20769 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20770 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20771 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20772 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20773 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20776 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20778 /* Moves and type conversions. */
20779 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20780 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20781 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20782 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20783 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20784 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20785 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20786 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20787 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20788 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20789 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20790 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20791 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20793 /* Monadic operations. */
20794 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20795 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20796 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20798 /* Dyadic operations. */
20799 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20800 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20801 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20802 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20803 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20804 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20805 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20806 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20807 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20810 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20811 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20812 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20813 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20816 #define ARM_VARIANT & fpu_vfp_ext_v2
20818 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20819 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20820 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20821 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20823 /* Instructions which may belong to either the Neon or VFP instruction sets.
20824 Individual encoder functions perform additional architecture checks. */
20826 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20827 #undef THUMB_VARIANT
20828 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20830 /* These mnemonics are unique to VFP. */
20831 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20832 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20833 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20834 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20835 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20836 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20837 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20838 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20839 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20840 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20842 /* Mnemonics shared by Neon and VFP. */
20843 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20844 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20845 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20847 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20848 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20850 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20851 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20853 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20854 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20855 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20856 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20857 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20858 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20859 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20860 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20862 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20863 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20864 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20865 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20868 /* NOTE: All VMOV encoding is special-cased! */
20869 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20870 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20873 #define ARM_VARIANT & arm_ext_fp16
20874 #undef THUMB_VARIANT
20875 #define THUMB_VARIANT & arm_ext_fp16
20876 /* New instructions added from v8.2, allowing the extraction and insertion of
20877 the upper 16 bits of a 32-bit vector register. */
20878 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20879 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20881 /* New backported fma/fms instructions optional in v8.2. */
20882 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
20883 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
20885 #undef THUMB_VARIANT
20886 #define THUMB_VARIANT & fpu_neon_ext_v1
20888 #define ARM_VARIANT & fpu_neon_ext_v1
20890 /* Data processing with three registers of the same length. */
20891 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20892 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20893 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20894 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20895 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20896 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20897 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20898 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20899 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20900 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20901 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20902 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20903 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20904 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20905 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20906 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20907 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20908 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20909 /* If not immediate, fall back to neon_dyadic_i64_su.
20910 shl_imm should accept I8 I16 I32 I64,
20911 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20912 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20913 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20914 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20915 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20916 /* Logic ops, types optional & ignored. */
20917 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20918 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20919 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20920 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20921 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20922 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20923 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20924 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20925 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20926 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20927 /* Bitfield ops, untyped. */
20928 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20929 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20930 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20931 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20932 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20933 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20934 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20935 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20936 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20937 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20938 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20939 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20940 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20941 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20942 back to neon_dyadic_if_su. */
20943 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20944 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20945 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20946 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20947 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20948 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20949 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20950 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20951 /* Comparison. Type I8 I16 I32 F32. */
20952 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20953 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20954 /* As above, D registers only. */
20955 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20956 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20957 /* Int and float variants, signedness unimportant. */
20958 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20959 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20960 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20961 /* Add/sub take types I8 I16 I32 I64 F32. */
20962 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20963 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20964 /* vtst takes sizes 8, 16, 32. */
20965 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20966 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20967 /* VMUL takes I8 I16 I32 F32 P8. */
20968 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20969 /* VQD{R}MULH takes S16 S32. */
20970 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20971 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20972 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20973 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20974 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20975 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20976 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20977 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20978 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20979 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20980 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20981 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20982 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20983 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20984 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20985 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20986 /* ARM v8.1 extension. */
20987 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20988 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20989 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20990 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20992 /* Two address, int/float. Types S8 S16 S32 F32. */
20993 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20994 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20996 /* Data processing with two registers and a shift amount. */
20997 /* Right shifts, and variants with rounding.
20998 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20999 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
21000 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
21001 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
21002 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
21003 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
21004 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
21005 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
21006 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
21007 /* Shift and insert. Sizes accepted 8 16 32 64. */
21008 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
21009 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
21010 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
21011 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
21012 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
21013 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
21014 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
21015 /* Right shift immediate, saturating & narrowing, with rounding variants.
21016 Types accepted S16 S32 S64 U16 U32 U64. */
21017 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
21018 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
21019 /* As above, unsigned. Types accepted S16 S32 S64. */
21020 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
21021 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
21022 /* Right shift narrowing. Types accepted I16 I32 I64. */
21023 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
21024 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
21025 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
21026 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
21027 /* CVT with optional immediate for fixed-point variant. */
21028 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
21030 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
21031 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
21033 /* Data processing, three registers of different lengths. */
21034 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
21035 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
21036 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21037 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21038 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21039 /* If not scalar, fall back to neon_dyadic_long.
21040 Vector types as above, scalar types S16 S32 U16 U32. */
21041 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
21042 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
21043 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
21044 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
21045 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
21046 /* Dyadic, narrowing insns. Types I16 I32 I64. */
21047 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21048 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21049 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21050 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21051 /* Saturating doubling multiplies. Types S16 S32. */
21052 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21053 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21054 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21055 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
21056 S16 S32 U16 U32. */
21057 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
21059 /* Extract. Size 8. */
21060 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
21061 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
21063 /* Two registers, miscellaneous. */
21064 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
21065 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
21066 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
21067 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
21068 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
21069 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
21070 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
21071 /* Vector replicate. Sizes 8 16 32. */
21072 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
21073 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
21074 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
21075 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
21076 /* VMOVN. Types I16 I32 I64. */
21077 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
21078 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
21079 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
21080 /* VQMOVUN. Types S16 S32 S64. */
21081 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
21082 /* VZIP / VUZP. Sizes 8 16 32. */
21083 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21084 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21085 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21086 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21087 /* VQABS / VQNEG. Types S8 S16 S32. */
21088 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21089 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21090 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21091 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21092 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
21093 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21094 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
21095 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21096 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
21097 /* Reciprocal estimates. Types U32 F16 F32. */
21098 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21099 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
21100 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21101 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
21102 /* VCLS. Types S8 S16 S32. */
21103 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
21104 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
21105 /* VCLZ. Types I8 I16 I32. */
21106 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
21107 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
21108 /* VCNT. Size 8. */
21109 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
21110 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
21111 /* Two address, untyped. */
21112 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
21113 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
21114 /* VTRN. Sizes 8 16 32. */
21115 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
21116 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
21118 /* Table lookup. Size 8. */
21119 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21120 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21122 #undef THUMB_VARIANT
21123 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
21125 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
21127 /* Neon element/structure load/store. */
21128 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21129 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21130 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21131 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21132 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21133 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21134 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21135 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21137 #undef THUMB_VARIANT
21138 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
21140 #define ARM_VARIANT & fpu_vfp_ext_v3xd
21141 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
21142 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21143 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21144 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21145 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21146 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21147 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21148 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21149 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21151 #undef THUMB_VARIANT
21152 #define THUMB_VARIANT & fpu_vfp_ext_v3
21154 #define ARM_VARIANT & fpu_vfp_ext_v3
21156 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
21157 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21158 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21159 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21160 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21161 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21162 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21163 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21164 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21167 #define ARM_VARIANT & fpu_vfp_ext_fma
21168 #undef THUMB_VARIANT
21169 #define THUMB_VARIANT & fpu_vfp_ext_fma
21170 /* Mnemonics shared by Neon and VFP. These are included in the
21171 VFP FMA variant; NEON and VFP FMA always includes the NEON
21172 FMA instructions. */
21173 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21174 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21175 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
21176 the v form should always be used. */
21177 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21178 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21179 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21180 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21181 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21182 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21184 #undef THUMB_VARIANT
21186 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
21188 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21189 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21190 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21191 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21192 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21193 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21194 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
21195 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
21198 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
21200 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
21201 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
21202 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
21203 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
21204 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
21205 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
21206 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
21207 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
21208 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
21209 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21210 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21211 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21212 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21213 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21214 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21215 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21216 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21217 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21218 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
21219 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
21220 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21221 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21222 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21223 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21224 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21225 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21226 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
21227 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
21228 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
21229 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
21230 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
21231 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
21232 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
21233 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
21234 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21235 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21236 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21237 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21238 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21239 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21240 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21241 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21242 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21243 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21244 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21245 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21246 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
21247 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21248 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21249 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21250 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21251 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21252 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21253 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21254 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21255 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21256 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21257 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21258 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21259 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21260 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21261 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21262 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21263 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21264 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21265 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21266 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21267 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21268 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21269 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21270 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21271 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21272 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21273 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21274 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21275 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21276 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21277 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21278 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21279 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21280 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21281 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21282 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21283 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21284 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21285 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21286 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21287 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21288 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
21289 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21290 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21291 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21292 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21293 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21294 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21295 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21296 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21297 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21298 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21299 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21300 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21301 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21302 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21303 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21304 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21305 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21306 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21307 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21308 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21309 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21310 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
21311 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21312 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21313 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21314 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21315 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21316 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21317 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21318 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21319 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21320 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21321 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21322 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21323 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21324 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21325 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21326 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21327 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21328 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21329 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21330 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21331 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21332 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21333 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21334 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21335 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21336 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21337 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21338 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21339 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21340 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21341 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21342 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21343 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21344 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21345 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21346 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21347 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21348 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21349 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21350 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21351 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21352 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21353 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21354 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21355 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21356 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21357 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21358 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21359 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21360 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21361 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
21364 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
21366 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
21367 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
21368 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
21369 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21370 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21371 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21372 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21373 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21374 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21375 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21376 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21377 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21378 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21379 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21380 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21381 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21382 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21383 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21384 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21385 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21386 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
21387 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21388 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21389 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21390 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21391 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21392 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21393 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21394 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21395 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21396 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21397 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21398 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21399 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21400 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21401 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21402 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21403 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21404 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21405 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21406 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21407 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21408 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21409 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21410 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21411 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21412 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21413 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21414 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21415 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21416 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21417 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21418 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21419 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21420 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21421 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21422 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21425 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
21427 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21428 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21429 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21430 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21431 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21432 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21433 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21434 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21435 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
21436 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
21437 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
21438 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
21439 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
21440 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
21441 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
21442 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
21443 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
21444 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
21445 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
21446 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
21447 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
21448 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
21449 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
21450 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
21451 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
21452 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
21453 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
21454 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
21455 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
21456 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
21457 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
21458 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
21459 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
21460 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
21461 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
21462 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
21463 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
21464 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
21465 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
21466 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
21467 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
21468 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
21469 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
21470 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
21471 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
21472 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
21473 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
21474 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
21475 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
21476 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
21477 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
21478 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
21479 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
21480 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
21481 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21482 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21483 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21484 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21485 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21486 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21487 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
21488 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
21489 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
21490 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
21491 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21492 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21493 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21494 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21495 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21496 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21497 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21498 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21499 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21500 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21501 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21502 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21504 /* ARMv8-M instructions. */
21506 #define ARM_VARIANT NULL
21507 #undef THUMB_VARIANT
21508 #define THUMB_VARIANT & arm_ext_v8m
21509 ToU("sg", e97fe97f
, 0, (), noargs
),
21510 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
21511 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
21512 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
21513 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
21514 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
21515 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
21517 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21518 instructions behave as nop if no VFP is present. */
21519 #undef THUMB_VARIANT
21520 #define THUMB_VARIANT & arm_ext_v8m_main
21521 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
21522 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
21525 #undef THUMB_VARIANT
21551 /* MD interface: bits in the object file. */
21553 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21554 for use in the a.out file, and stores them in the array pointed to by buf.
21555 This knows about the endian-ness of the target machine and does
21556 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21557 2 (short) and 4 (long) Floating numbers are put out as a series of
21558 LITTLENUMS (shorts, here at least). */
21561 md_number_to_chars (char * buf
, valueT val
, int n
)
21563 if (target_big_endian
)
21564 number_to_chars_bigendian (buf
, val
, n
);
21566 number_to_chars_littleendian (buf
, val
, n
);
21570 md_chars_to_number (char * buf
, int n
)
21573 unsigned char * where
= (unsigned char *) buf
;
21575 if (target_big_endian
)
21580 result
|= (*where
++ & 255);
21588 result
|= (where
[n
] & 255);
21595 /* MD interface: Sections. */
21597 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21598 that an rs_machine_dependent frag may reach. */
21601 arm_frag_max_var (fragS
*fragp
)
21603 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21604 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21606 Note that we generate relaxable instructions even for cases that don't
21607 really need it, like an immediate that's a trivial constant. So we're
21608 overestimating the instruction size for some of those cases. Rather
21609 than putting more intelligence here, it would probably be better to
21610 avoid generating a relaxation frag in the first place when it can be
21611 determined up front that a short instruction will suffice. */
21613 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21617 /* Estimate the size of a frag before relaxing. Assume everything fits in
21621 md_estimate_size_before_relax (fragS
* fragp
,
21622 segT segtype ATTRIBUTE_UNUSED
)
21628 /* Convert a machine dependent frag. */
21631 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21633 unsigned long insn
;
21634 unsigned long old_op
;
21642 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21644 old_op
= bfd_get_16(abfd
, buf
);
21645 if (fragp
->fr_symbol
)
21647 exp
.X_op
= O_symbol
;
21648 exp
.X_add_symbol
= fragp
->fr_symbol
;
21652 exp
.X_op
= O_constant
;
21654 exp
.X_add_number
= fragp
->fr_offset
;
21655 opcode
= fragp
->fr_subtype
;
21658 case T_MNEM_ldr_pc
:
21659 case T_MNEM_ldr_pc2
:
21660 case T_MNEM_ldr_sp
:
21661 case T_MNEM_str_sp
:
21668 if (fragp
->fr_var
== 4)
21670 insn
= THUMB_OP32 (opcode
);
21671 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21673 insn
|= (old_op
& 0x700) << 4;
21677 insn
|= (old_op
& 7) << 12;
21678 insn
|= (old_op
& 0x38) << 13;
21680 insn
|= 0x00000c00;
21681 put_thumb32_insn (buf
, insn
);
21682 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21686 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21688 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21691 if (fragp
->fr_var
== 4)
21693 insn
= THUMB_OP32 (opcode
);
21694 insn
|= (old_op
& 0xf0) << 4;
21695 put_thumb32_insn (buf
, insn
);
21696 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21700 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21701 exp
.X_add_number
-= 4;
21709 if (fragp
->fr_var
== 4)
21711 int r0off
= (opcode
== T_MNEM_mov
21712 || opcode
== T_MNEM_movs
) ? 0 : 8;
21713 insn
= THUMB_OP32 (opcode
);
21714 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21715 insn
|= (old_op
& 0x700) << r0off
;
21716 put_thumb32_insn (buf
, insn
);
21717 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21721 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21726 if (fragp
->fr_var
== 4)
21728 insn
= THUMB_OP32(opcode
);
21729 put_thumb32_insn (buf
, insn
);
21730 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21733 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21737 if (fragp
->fr_var
== 4)
21739 insn
= THUMB_OP32(opcode
);
21740 insn
|= (old_op
& 0xf00) << 14;
21741 put_thumb32_insn (buf
, insn
);
21742 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21745 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21748 case T_MNEM_add_sp
:
21749 case T_MNEM_add_pc
:
21750 case T_MNEM_inc_sp
:
21751 case T_MNEM_dec_sp
:
21752 if (fragp
->fr_var
== 4)
21754 /* ??? Choose between add and addw. */
21755 insn
= THUMB_OP32 (opcode
);
21756 insn
|= (old_op
& 0xf0) << 4;
21757 put_thumb32_insn (buf
, insn
);
21758 if (opcode
== T_MNEM_add_pc
)
21759 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21761 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21764 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21772 if (fragp
->fr_var
== 4)
21774 insn
= THUMB_OP32 (opcode
);
21775 insn
|= (old_op
& 0xf0) << 4;
21776 insn
|= (old_op
& 0xf) << 16;
21777 put_thumb32_insn (buf
, insn
);
21778 if (insn
& (1 << 20))
21779 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21781 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21784 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21790 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21791 (enum bfd_reloc_code_real
) reloc_type
);
21792 fixp
->fx_file
= fragp
->fr_file
;
21793 fixp
->fx_line
= fragp
->fr_line
;
21794 fragp
->fr_fix
+= fragp
->fr_var
;
21796 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21797 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21798 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21799 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21802 /* Return the size of a relaxable immediate operand instruction.
21803 SHIFT and SIZE specify the form of the allowable immediate. */
21805 relax_immediate (fragS
*fragp
, int size
, int shift
)
21811 /* ??? Should be able to do better than this. */
21812 if (fragp
->fr_symbol
)
21815 low
= (1 << shift
) - 1;
21816 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21817 offset
= fragp
->fr_offset
;
21818 /* Force misaligned offsets to 32-bit variant. */
21821 if (offset
& ~mask
)
21826 /* Get the address of a symbol during relaxation. */
21828 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21834 sym
= fragp
->fr_symbol
;
21835 sym_frag
= symbol_get_frag (sym
);
21836 know (S_GET_SEGMENT (sym
) != absolute_section
21837 || sym_frag
== &zero_address_frag
);
21838 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21840 /* If frag has yet to be reached on this pass, assume it will
21841 move by STRETCH just as we did. If this is not so, it will
21842 be because some frag between grows, and that will force
21846 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21850 /* Adjust stretch for any alignment frag. Note that if have
21851 been expanding the earlier code, the symbol may be
21852 defined in what appears to be an earlier frag. FIXME:
21853 This doesn't handle the fr_subtype field, which specifies
21854 a maximum number of bytes to skip when doing an
21856 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21858 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21861 stretch
= - ((- stretch
)
21862 & ~ ((1 << (int) f
->fr_offset
) - 1));
21864 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21876 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21879 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21884 /* Assume worst case for symbols not known to be in the same section. */
21885 if (fragp
->fr_symbol
== NULL
21886 || !S_IS_DEFINED (fragp
->fr_symbol
)
21887 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21888 || S_IS_WEAK (fragp
->fr_symbol
))
21891 val
= relaxed_symbol_addr (fragp
, stretch
);
21892 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21893 addr
= (addr
+ 4) & ~3;
21894 /* Force misaligned targets to 32-bit variant. */
21898 if (val
< 0 || val
> 1020)
21903 /* Return the size of a relaxable add/sub immediate instruction. */
21905 relax_addsub (fragS
*fragp
, asection
*sec
)
21910 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21911 op
= bfd_get_16(sec
->owner
, buf
);
21912 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21913 return relax_immediate (fragp
, 8, 0);
21915 return relax_immediate (fragp
, 3, 0);
21918 /* Return TRUE iff the definition of symbol S could be pre-empted
21919 (overridden) at link or load time. */
21921 symbol_preemptible (symbolS
*s
)
21923 /* Weak symbols can always be pre-empted. */
21927 /* Non-global symbols cannot be pre-empted. */
21928 if (! S_IS_EXTERNAL (s
))
21932 /* In ELF, a global symbol can be marked protected, or private. In that
21933 case it can't be pre-empted (other definitions in the same link unit
21934 would violate the ODR). */
21935 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21939 /* Other global symbols might be pre-empted. */
21943 /* Return the size of a relaxable branch instruction. BITS is the
21944 size of the offset field in the narrow instruction. */
21947 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21953 /* Assume worst case for symbols not known to be in the same section. */
21954 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21955 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21956 || S_IS_WEAK (fragp
->fr_symbol
))
21960 /* A branch to a function in ARM state will require interworking. */
21961 if (S_IS_DEFINED (fragp
->fr_symbol
)
21962 && ARM_IS_FUNC (fragp
->fr_symbol
))
21966 if (symbol_preemptible (fragp
->fr_symbol
))
21969 val
= relaxed_symbol_addr (fragp
, stretch
);
21970 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21973 /* Offset is a signed value *2 */
21975 if (val
>= limit
|| val
< -limit
)
21981 /* Relax a machine dependent frag. This returns the amount by which
21982 the current size of the frag should change. */
21985 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21990 oldsize
= fragp
->fr_var
;
21991 switch (fragp
->fr_subtype
)
21993 case T_MNEM_ldr_pc2
:
21994 newsize
= relax_adr (fragp
, sec
, stretch
);
21996 case T_MNEM_ldr_pc
:
21997 case T_MNEM_ldr_sp
:
21998 case T_MNEM_str_sp
:
21999 newsize
= relax_immediate (fragp
, 8, 2);
22003 newsize
= relax_immediate (fragp
, 5, 2);
22007 newsize
= relax_immediate (fragp
, 5, 1);
22011 newsize
= relax_immediate (fragp
, 5, 0);
22014 newsize
= relax_adr (fragp
, sec
, stretch
);
22020 newsize
= relax_immediate (fragp
, 8, 0);
22023 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
22026 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
22028 case T_MNEM_add_sp
:
22029 case T_MNEM_add_pc
:
22030 newsize
= relax_immediate (fragp
, 8, 2);
22032 case T_MNEM_inc_sp
:
22033 case T_MNEM_dec_sp
:
22034 newsize
= relax_immediate (fragp
, 7, 2);
22040 newsize
= relax_addsub (fragp
, sec
);
22046 fragp
->fr_var
= newsize
;
22047 /* Freeze wide instructions that are at or before the same location as
22048 in the previous pass. This avoids infinite loops.
22049 Don't freeze them unconditionally because targets may be artificially
22050 misaligned by the expansion of preceding frags. */
22051 if (stretch
<= 0 && newsize
> 2)
22053 md_convert_frag (sec
->owner
, sec
, fragp
);
22057 return newsize
- oldsize
;
22060 /* Round up a section size to the appropriate boundary. */
22063 md_section_align (segT segment ATTRIBUTE_UNUSED
,
22069 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
22070 of an rs_align_code fragment. */
22073 arm_handle_align (fragS
* fragP
)
22075 static unsigned char const arm_noop
[2][2][4] =
22078 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
22079 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
22082 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
22083 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
22086 static unsigned char const thumb_noop
[2][2][2] =
22089 {0xc0, 0x46}, /* LE */
22090 {0x46, 0xc0}, /* BE */
22093 {0x00, 0xbf}, /* LE */
22094 {0xbf, 0x00} /* BE */
22097 static unsigned char const wide_thumb_noop
[2][4] =
22098 { /* Wide Thumb-2 */
22099 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
22100 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
22103 unsigned bytes
, fix
, noop_size
;
22105 const unsigned char * noop
;
22106 const unsigned char *narrow_noop
= NULL
;
22111 if (fragP
->fr_type
!= rs_align_code
)
22114 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
22115 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
22118 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22119 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
22121 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
22123 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
22125 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22126 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
22128 narrow_noop
= thumb_noop
[1][target_big_endian
];
22129 noop
= wide_thumb_noop
[target_big_endian
];
22132 noop
= thumb_noop
[0][target_big_endian
];
22140 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22141 ? selected_cpu
: arm_arch_none
,
22143 [target_big_endian
];
22150 fragP
->fr_var
= noop_size
;
22152 if (bytes
& (noop_size
- 1))
22154 fix
= bytes
& (noop_size
- 1);
22156 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
22158 memset (p
, 0, fix
);
22165 if (bytes
& noop_size
)
22167 /* Insert a narrow noop. */
22168 memcpy (p
, narrow_noop
, noop_size
);
22170 bytes
-= noop_size
;
22174 /* Use wide noops for the remainder */
22178 while (bytes
>= noop_size
)
22180 memcpy (p
, noop
, noop_size
);
22182 bytes
-= noop_size
;
22186 fragP
->fr_fix
+= fix
;
22189 /* Called from md_do_align. Used to create an alignment
22190 frag in a code section. */
22193 arm_frag_align_code (int n
, int max
)
22197 /* We assume that there will never be a requirement
22198 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
22199 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22204 _("alignments greater than %d bytes not supported in .text sections."),
22205 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
22206 as_fatal ("%s", err_msg
);
22209 p
= frag_var (rs_align_code
,
22210 MAX_MEM_FOR_RS_ALIGN_CODE
,
22212 (relax_substateT
) max
,
22219 /* Perform target specific initialisation of a frag.
22220 Note - despite the name this initialisation is not done when the frag
22221 is created, but only when its type is assigned. A frag can be created
22222 and used a long time before its type is set, so beware of assuming that
22223 this initialisation is performed first. */
22227 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
22229 /* Record whether this frag is in an ARM or a THUMB area. */
22230 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22233 #else /* OBJ_ELF is defined. */
22235 arm_init_frag (fragS
* fragP
, int max_chars
)
22237 bfd_boolean frag_thumb_mode
;
22239 /* If the current ARM vs THUMB mode has not already
22240 been recorded into this frag then do so now. */
22241 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
22242 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22244 /* PR 21809: Do not set a mapping state for debug sections
22245 - it just confuses other tools. */
22246 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
22249 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
22251 /* Record a mapping symbol for alignment frags. We will delete this
22252 later if the alignment ends up empty. */
22253 switch (fragP
->fr_type
)
22256 case rs_align_test
:
22258 mapping_state_2 (MAP_DATA
, max_chars
);
22260 case rs_align_code
:
22261 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
22268 /* When we change sections we need to issue a new mapping symbol. */
22271 arm_elf_change_section (void)
22273 /* Link an unlinked unwind index table section to the .text section. */
22274 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
22275 && elf_linked_to_section (now_seg
) == NULL
)
22276 elf_linked_to_section (now_seg
) = text_section
;
22280 arm_elf_section_type (const char * str
, size_t len
)
22282 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
22283 return SHT_ARM_EXIDX
;
22288 /* Code to deal with unwinding tables. */
22290 static void add_unwind_adjustsp (offsetT
);
22292 /* Generate any deferred unwind frame offset. */
22295 flush_pending_unwind (void)
22299 offset
= unwind
.pending_offset
;
22300 unwind
.pending_offset
= 0;
22302 add_unwind_adjustsp (offset
);
22305 /* Add an opcode to this list for this function. Two-byte opcodes should
22306 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
22310 add_unwind_opcode (valueT op
, int length
)
22312 /* Add any deferred stack adjustment. */
22313 if (unwind
.pending_offset
)
22314 flush_pending_unwind ();
22316 unwind
.sp_restored
= 0;
22318 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
22320 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
22321 if (unwind
.opcodes
)
22322 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
22323 unwind
.opcode_alloc
);
22325 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
22330 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
22332 unwind
.opcode_count
++;
22336 /* Add unwind opcodes to adjust the stack pointer. */
22339 add_unwind_adjustsp (offsetT offset
)
22343 if (offset
> 0x200)
22345 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
22350 /* Long form: 0xb2, uleb128. */
22351 /* This might not fit in a word so add the individual bytes,
22352 remembering the list is built in reverse order. */
22353 o
= (valueT
) ((offset
- 0x204) >> 2);
22355 add_unwind_opcode (0, 1);
22357 /* Calculate the uleb128 encoding of the offset. */
22361 bytes
[n
] = o
& 0x7f;
22367 /* Add the insn. */
22369 add_unwind_opcode (bytes
[n
- 1], 1);
22370 add_unwind_opcode (0xb2, 1);
22372 else if (offset
> 0x100)
22374 /* Two short opcodes. */
22375 add_unwind_opcode (0x3f, 1);
22376 op
= (offset
- 0x104) >> 2;
22377 add_unwind_opcode (op
, 1);
22379 else if (offset
> 0)
22381 /* Short opcode. */
22382 op
= (offset
- 4) >> 2;
22383 add_unwind_opcode (op
, 1);
22385 else if (offset
< 0)
22388 while (offset
> 0x100)
22390 add_unwind_opcode (0x7f, 1);
22393 op
= ((offset
- 4) >> 2) | 0x40;
22394 add_unwind_opcode (op
, 1);
22398 /* Finish the list of unwind opcodes for this function. */
22401 finish_unwind_opcodes (void)
22405 if (unwind
.fp_used
)
22407 /* Adjust sp as necessary. */
22408 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
22409 flush_pending_unwind ();
22411 /* After restoring sp from the frame pointer. */
22412 op
= 0x90 | unwind
.fp_reg
;
22413 add_unwind_opcode (op
, 1);
22416 flush_pending_unwind ();
22420 /* Start an exception table entry. If idx is nonzero this is an index table
22424 start_unwind_section (const segT text_seg
, int idx
)
22426 const char * text_name
;
22427 const char * prefix
;
22428 const char * prefix_once
;
22429 const char * group_name
;
22437 prefix
= ELF_STRING_ARM_unwind
;
22438 prefix_once
= ELF_STRING_ARM_unwind_once
;
22439 type
= SHT_ARM_EXIDX
;
22443 prefix
= ELF_STRING_ARM_unwind_info
;
22444 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
22445 type
= SHT_PROGBITS
;
22448 text_name
= segment_name (text_seg
);
22449 if (streq (text_name
, ".text"))
22452 if (strncmp (text_name
, ".gnu.linkonce.t.",
22453 strlen (".gnu.linkonce.t.")) == 0)
22455 prefix
= prefix_once
;
22456 text_name
+= strlen (".gnu.linkonce.t.");
22459 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
22465 /* Handle COMDAT group. */
22466 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
22468 group_name
= elf_group_name (text_seg
);
22469 if (group_name
== NULL
)
22471 as_bad (_("Group section `%s' has no group signature"),
22472 segment_name (text_seg
));
22473 ignore_rest_of_line ();
22476 flags
|= SHF_GROUP
;
22480 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
22483 /* Set the section link for index tables. */
22485 elf_linked_to_section (now_seg
) = text_seg
;
22489 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22490 personality routine data. Returns zero, or the index table value for
22491 an inline entry. */
22494 create_unwind_entry (int have_data
)
22499 /* The current word of data. */
22501 /* The number of bytes left in this word. */
22504 finish_unwind_opcodes ();
22506 /* Remember the current text section. */
22507 unwind
.saved_seg
= now_seg
;
22508 unwind
.saved_subseg
= now_subseg
;
22510 start_unwind_section (now_seg
, 0);
22512 if (unwind
.personality_routine
== NULL
)
22514 if (unwind
.personality_index
== -2)
22517 as_bad (_("handlerdata in cantunwind frame"));
22518 return 1; /* EXIDX_CANTUNWIND. */
22521 /* Use a default personality routine if none is specified. */
22522 if (unwind
.personality_index
== -1)
22524 if (unwind
.opcode_count
> 3)
22525 unwind
.personality_index
= 1;
22527 unwind
.personality_index
= 0;
22530 /* Space for the personality routine entry. */
22531 if (unwind
.personality_index
== 0)
22533 if (unwind
.opcode_count
> 3)
22534 as_bad (_("too many unwind opcodes for personality routine 0"));
22538 /* All the data is inline in the index table. */
22541 while (unwind
.opcode_count
> 0)
22543 unwind
.opcode_count
--;
22544 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22548 /* Pad with "finish" opcodes. */
22550 data
= (data
<< 8) | 0xb0;
22557 /* We get two opcodes "free" in the first word. */
22558 size
= unwind
.opcode_count
- 2;
22562 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22563 if (unwind
.personality_index
!= -1)
22565 as_bad (_("attempt to recreate an unwind entry"));
22569 /* An extra byte is required for the opcode count. */
22570 size
= unwind
.opcode_count
+ 1;
22573 size
= (size
+ 3) >> 2;
22575 as_bad (_("too many unwind opcodes"));
22577 frag_align (2, 0, 0);
22578 record_alignment (now_seg
, 2);
22579 unwind
.table_entry
= expr_build_dot ();
22581 /* Allocate the table entry. */
22582 ptr
= frag_more ((size
<< 2) + 4);
22583 /* PR 13449: Zero the table entries in case some of them are not used. */
22584 memset (ptr
, 0, (size
<< 2) + 4);
22585 where
= frag_now_fix () - ((size
<< 2) + 4);
22587 switch (unwind
.personality_index
)
22590 /* ??? Should this be a PLT generating relocation? */
22591 /* Custom personality routine. */
22592 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22593 BFD_RELOC_ARM_PREL31
);
22598 /* Set the first byte to the number of additional words. */
22599 data
= size
> 0 ? size
- 1 : 0;
22603 /* ABI defined personality routines. */
22605 /* Three opcodes bytes are packed into the first word. */
22612 /* The size and first two opcode bytes go in the first word. */
22613 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22618 /* Should never happen. */
22622 /* Pack the opcodes into words (MSB first), reversing the list at the same
22624 while (unwind
.opcode_count
> 0)
22628 md_number_to_chars (ptr
, data
, 4);
22633 unwind
.opcode_count
--;
22635 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22638 /* Finish off the last word. */
22641 /* Pad with "finish" opcodes. */
22643 data
= (data
<< 8) | 0xb0;
22645 md_number_to_chars (ptr
, data
, 4);
22650 /* Add an empty descriptor if there is no user-specified data. */
22651 ptr
= frag_more (4);
22652 md_number_to_chars (ptr
, 0, 4);
22659 /* Initialize the DWARF-2 unwind information for this procedure. */
22662 tc_arm_frame_initial_instructions (void)
22664 cfi_add_CFA_def_cfa (REG_SP
, 0);
22666 #endif /* OBJ_ELF */
22668 /* Convert REGNAME to a DWARF-2 register number. */
22671 tc_arm_regname_to_dw2regnum (char *regname
)
22673 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22677 /* PR 16694: Allow VFP registers as well. */
22678 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22682 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22691 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22695 exp
.X_op
= O_secrel
;
22696 exp
.X_add_symbol
= symbol
;
22697 exp
.X_add_number
= 0;
22698 emit_expr (&exp
, size
);
22702 /* MD interface: Symbol and relocation handling. */
22704 /* Return the address within the segment that a PC-relative fixup is
22705 relative to. For ARM, PC-relative fixups applied to instructions
22706 are generally relative to the location of the fixup plus 8 bytes.
22707 Thumb branches are offset by 4, and Thumb loads relative to PC
22708 require special handling. */
22711 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22713 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22715 /* If this is pc-relative and we are going to emit a relocation
22716 then we just want to put out any pipeline compensation that the linker
22717 will need. Otherwise we want to use the calculated base.
22718 For WinCE we skip the bias for externals as well, since this
22719 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22721 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22722 || (arm_force_relocation (fixP
)
22724 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22730 switch (fixP
->fx_r_type
)
22732 /* PC relative addressing on the Thumb is slightly odd as the
22733 bottom two bits of the PC are forced to zero for the
22734 calculation. This happens *after* application of the
22735 pipeline offset. However, Thumb adrl already adjusts for
22736 this, so we need not do it again. */
22737 case BFD_RELOC_ARM_THUMB_ADD
:
22740 case BFD_RELOC_ARM_THUMB_OFFSET
:
22741 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22742 case BFD_RELOC_ARM_T32_ADD_PC12
:
22743 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22744 return (base
+ 4) & ~3;
22746 /* Thumb branches are simply offset by +4. */
22747 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22748 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22749 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22750 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22751 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22754 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22756 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22757 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22758 && ARM_IS_FUNC (fixP
->fx_addsy
)
22759 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22760 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22763 /* BLX is like branches above, but forces the low two bits of PC to
22765 case BFD_RELOC_THUMB_PCREL_BLX
:
22767 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22768 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22769 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22770 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22771 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22772 return (base
+ 4) & ~3;
22774 /* ARM mode branches are offset by +8. However, the Windows CE
22775 loader expects the relocation not to take this into account. */
22776 case BFD_RELOC_ARM_PCREL_BLX
:
22778 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22779 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22780 && ARM_IS_FUNC (fixP
->fx_addsy
)
22781 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22782 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22785 case BFD_RELOC_ARM_PCREL_CALL
:
22787 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22788 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22789 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22790 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22791 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22794 case BFD_RELOC_ARM_PCREL_BRANCH
:
22795 case BFD_RELOC_ARM_PCREL_JUMP
:
22796 case BFD_RELOC_ARM_PLT32
:
22798 /* When handling fixups immediately, because we have already
22799 discovered the value of a symbol, or the address of the frag involved
22800 we must account for the offset by +8, as the OS loader will never see the reloc.
22801 see fixup_segment() in write.c
22802 The S_IS_EXTERNAL test handles the case of global symbols.
22803 Those need the calculated base, not just the pipe compensation the linker will need. */
22805 && fixP
->fx_addsy
!= NULL
22806 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22807 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22815 /* ARM mode loads relative to PC are also offset by +8. Unlike
22816 branches, the Windows CE loader *does* expect the relocation
22817 to take this into account. */
22818 case BFD_RELOC_ARM_OFFSET_IMM
:
22819 case BFD_RELOC_ARM_OFFSET_IMM8
:
22820 case BFD_RELOC_ARM_HWLITERAL
:
22821 case BFD_RELOC_ARM_LITERAL
:
22822 case BFD_RELOC_ARM_CP_OFF_IMM
:
22826 /* Other PC-relative relocations are un-offset. */
22832 static bfd_boolean flag_warn_syms
= TRUE
;
22835 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22837 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22838 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22839 does mean that the resulting code might be very confusing to the reader.
22840 Also this warning can be triggered if the user omits an operand before
22841 an immediate address, eg:
22845 GAS treats this as an assignment of the value of the symbol foo to a
22846 symbol LDR, and so (without this code) it will not issue any kind of
22847 warning or error message.
22849 Note - ARM instructions are case-insensitive but the strings in the hash
22850 table are all stored in lower case, so we must first ensure that name is
22852 if (flag_warn_syms
&& arm_ops_hsh
)
22854 char * nbuf
= strdup (name
);
22857 for (p
= nbuf
; *p
; p
++)
22859 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22861 static struct hash_control
* already_warned
= NULL
;
22863 if (already_warned
== NULL
)
22864 already_warned
= hash_new ();
22865 /* Only warn about the symbol once. To keep the code
22866 simple we let hash_insert do the lookup for us. */
22867 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22868 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22877 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22878 Otherwise we have no need to default values of symbols. */
22881 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22884 if (name
[0] == '_' && name
[1] == 'G'
22885 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22889 if (symbol_find (name
))
22890 as_bad (_("GOT already in the symbol table"));
22892 GOT_symbol
= symbol_new (name
, undefined_section
,
22893 (valueT
) 0, & zero_address_frag
);
22903 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22904 computed as two separate immediate values, added together. We
22905 already know that this value cannot be computed by just one ARM
22908 static unsigned int
22909 validate_immediate_twopart (unsigned int val
,
22910 unsigned int * highpart
)
22915 for (i
= 0; i
< 32; i
+= 2)
22916 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22922 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22924 else if (a
& 0xff0000)
22926 if (a
& 0xff000000)
22928 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22932 gas_assert (a
& 0xff000000);
22933 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22936 return (a
& 0xff) | (i
<< 7);
22943 validate_offset_imm (unsigned int val
, int hwse
)
22945 if ((hwse
&& val
> 255) || val
> 4095)
22950 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22951 negative immediate constant by altering the instruction. A bit of
22956 by inverting the second operand, and
22959 by negating the second operand. */
22962 negate_data_op (unsigned long * instruction
,
22963 unsigned long value
)
22966 unsigned long negated
, inverted
;
22968 negated
= encode_arm_immediate (-value
);
22969 inverted
= encode_arm_immediate (~value
);
22971 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22974 /* First negates. */
22975 case OPCODE_SUB
: /* ADD <-> SUB */
22976 new_inst
= OPCODE_ADD
;
22981 new_inst
= OPCODE_SUB
;
22985 case OPCODE_CMP
: /* CMP <-> CMN */
22986 new_inst
= OPCODE_CMN
;
22991 new_inst
= OPCODE_CMP
;
22995 /* Now Inverted ops. */
22996 case OPCODE_MOV
: /* MOV <-> MVN */
22997 new_inst
= OPCODE_MVN
;
23002 new_inst
= OPCODE_MOV
;
23006 case OPCODE_AND
: /* AND <-> BIC */
23007 new_inst
= OPCODE_BIC
;
23012 new_inst
= OPCODE_AND
;
23016 case OPCODE_ADC
: /* ADC <-> SBC */
23017 new_inst
= OPCODE_SBC
;
23022 new_inst
= OPCODE_ADC
;
23026 /* We cannot do anything. */
23031 if (value
== (unsigned) FAIL
)
23034 *instruction
&= OPCODE_MASK
;
23035 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
23039 /* Like negate_data_op, but for Thumb-2. */
23041 static unsigned int
23042 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
23046 unsigned int negated
, inverted
;
23048 negated
= encode_thumb32_immediate (-value
);
23049 inverted
= encode_thumb32_immediate (~value
);
23051 rd
= (*instruction
>> 8) & 0xf;
23052 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
23055 /* ADD <-> SUB. Includes CMP <-> CMN. */
23056 case T2_OPCODE_SUB
:
23057 new_inst
= T2_OPCODE_ADD
;
23061 case T2_OPCODE_ADD
:
23062 new_inst
= T2_OPCODE_SUB
;
23066 /* ORR <-> ORN. Includes MOV <-> MVN. */
23067 case T2_OPCODE_ORR
:
23068 new_inst
= T2_OPCODE_ORN
;
23072 case T2_OPCODE_ORN
:
23073 new_inst
= T2_OPCODE_ORR
;
23077 /* AND <-> BIC. TST has no inverted equivalent. */
23078 case T2_OPCODE_AND
:
23079 new_inst
= T2_OPCODE_BIC
;
23086 case T2_OPCODE_BIC
:
23087 new_inst
= T2_OPCODE_AND
;
23092 case T2_OPCODE_ADC
:
23093 new_inst
= T2_OPCODE_SBC
;
23097 case T2_OPCODE_SBC
:
23098 new_inst
= T2_OPCODE_ADC
;
23102 /* We cannot do anything. */
23107 if (value
== (unsigned int)FAIL
)
23110 *instruction
&= T2_OPCODE_MASK
;
23111 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
23115 /* Read a 32-bit thumb instruction from buf. */
23117 static unsigned long
23118 get_thumb32_insn (char * buf
)
23120 unsigned long insn
;
23121 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
23122 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23127 /* We usually want to set the low bit on the address of thumb function
23128 symbols. In particular .word foo - . should have the low bit set.
23129 Generic code tries to fold the difference of two symbols to
23130 a constant. Prevent this and force a relocation when the first symbols
23131 is a thumb function. */
23134 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
23136 if (op
== O_subtract
23137 && l
->X_op
== O_symbol
23138 && r
->X_op
== O_symbol
23139 && THUMB_IS_FUNC (l
->X_add_symbol
))
23141 l
->X_op
= O_subtract
;
23142 l
->X_op_symbol
= r
->X_add_symbol
;
23143 l
->X_add_number
-= r
->X_add_number
;
23147 /* Process as normal. */
23151 /* Encode Thumb2 unconditional branches and calls. The encoding
23152 for the 2 are identical for the immediate values. */
23155 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
23157 #define T2I1I2MASK ((1 << 13) | (1 << 11))
23160 addressT S
, I1
, I2
, lo
, hi
;
23162 S
= (value
>> 24) & 0x01;
23163 I1
= (value
>> 23) & 0x01;
23164 I2
= (value
>> 22) & 0x01;
23165 hi
= (value
>> 12) & 0x3ff;
23166 lo
= (value
>> 1) & 0x7ff;
23167 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23168 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23169 newval
|= (S
<< 10) | hi
;
23170 newval2
&= ~T2I1I2MASK
;
23171 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
23172 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23173 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23177 md_apply_fix (fixS
* fixP
,
23181 offsetT value
= * valP
;
23183 unsigned int newimm
;
23184 unsigned long temp
;
23186 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
23188 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
23190 /* Note whether this will delete the relocation. */
23192 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
23195 /* On a 64-bit host, silently truncate 'value' to 32 bits for
23196 consistency with the behaviour on 32-bit hosts. Remember value
23198 value
&= 0xffffffff;
23199 value
^= 0x80000000;
23200 value
-= 0x80000000;
23203 fixP
->fx_addnumber
= value
;
23205 /* Same treatment for fixP->fx_offset. */
23206 fixP
->fx_offset
&= 0xffffffff;
23207 fixP
->fx_offset
^= 0x80000000;
23208 fixP
->fx_offset
-= 0x80000000;
23210 switch (fixP
->fx_r_type
)
23212 case BFD_RELOC_NONE
:
23213 /* This will need to go in the object file. */
23217 case BFD_RELOC_ARM_IMMEDIATE
:
23218 /* We claim that this fixup has been processed here,
23219 even if in fact we generate an error because we do
23220 not have a reloc for it, so tc_gen_reloc will reject it. */
23223 if (fixP
->fx_addsy
)
23225 const char *msg
= 0;
23227 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23228 msg
= _("undefined symbol %s used as an immediate value");
23229 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23230 msg
= _("symbol %s is in a different section");
23231 else if (S_IS_WEAK (fixP
->fx_addsy
))
23232 msg
= _("symbol %s is weak and may be overridden later");
23236 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23237 msg
, S_GET_NAME (fixP
->fx_addsy
));
23242 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23244 /* If the offset is negative, we should use encoding A2 for ADR. */
23245 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
23246 newimm
= negate_data_op (&temp
, value
);
23249 newimm
= encode_arm_immediate (value
);
23251 /* If the instruction will fail, see if we can fix things up by
23252 changing the opcode. */
23253 if (newimm
== (unsigned int) FAIL
)
23254 newimm
= negate_data_op (&temp
, value
);
23255 /* MOV accepts both ARM modified immediate (A1 encoding) and
23256 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
23257 When disassembling, MOV is preferred when there is no encoding
23259 if (newimm
== (unsigned int) FAIL
23260 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
23261 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
23262 && !((temp
>> SBIT_SHIFT
) & 0x1)
23263 && value
>= 0 && value
<= 0xffff)
23265 /* Clear bits[23:20] to change encoding from A1 to A2. */
23266 temp
&= 0xff0fffff;
23267 /* Encoding high 4bits imm. Code below will encode the remaining
23269 temp
|= (value
& 0x0000f000) << 4;
23270 newimm
= value
& 0x00000fff;
23274 if (newimm
== (unsigned int) FAIL
)
23276 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23277 _("invalid constant (%lx) after fixup"),
23278 (unsigned long) value
);
23282 newimm
|= (temp
& 0xfffff000);
23283 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23286 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23288 unsigned int highpart
= 0;
23289 unsigned int newinsn
= 0xe1a00000; /* nop. */
23291 if (fixP
->fx_addsy
)
23293 const char *msg
= 0;
23295 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23296 msg
= _("undefined symbol %s used as an immediate value");
23297 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23298 msg
= _("symbol %s is in a different section");
23299 else if (S_IS_WEAK (fixP
->fx_addsy
))
23300 msg
= _("symbol %s is weak and may be overridden later");
23304 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23305 msg
, S_GET_NAME (fixP
->fx_addsy
));
23310 newimm
= encode_arm_immediate (value
);
23311 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23313 /* If the instruction will fail, see if we can fix things up by
23314 changing the opcode. */
23315 if (newimm
== (unsigned int) FAIL
23316 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
23318 /* No ? OK - try using two ADD instructions to generate
23320 newimm
= validate_immediate_twopart (value
, & highpart
);
23322 /* Yes - then make sure that the second instruction is
23324 if (newimm
!= (unsigned int) FAIL
)
23326 /* Still No ? Try using a negated value. */
23327 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
23328 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
23329 /* Otherwise - give up. */
23332 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23333 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
23338 /* Replace the first operand in the 2nd instruction (which
23339 is the PC) with the destination register. We have
23340 already added in the PC in the first instruction and we
23341 do not want to do it again. */
23342 newinsn
&= ~ 0xf0000;
23343 newinsn
|= ((newinsn
& 0x0f000) << 4);
23346 newimm
|= (temp
& 0xfffff000);
23347 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23349 highpart
|= (newinsn
& 0xfffff000);
23350 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
23354 case BFD_RELOC_ARM_OFFSET_IMM
:
23355 if (!fixP
->fx_done
&& seg
->use_rela_p
)
23357 /* Fall through. */
23359 case BFD_RELOC_ARM_LITERAL
:
23365 if (validate_offset_imm (value
, 0) == FAIL
)
23367 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
23368 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23369 _("invalid literal constant: pool needs to be closer"));
23371 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23372 _("bad immediate value for offset (%ld)"),
23377 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23379 newval
&= 0xfffff000;
23382 newval
&= 0xff7ff000;
23383 newval
|= value
| (sign
? INDEX_UP
: 0);
23385 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23388 case BFD_RELOC_ARM_OFFSET_IMM8
:
23389 case BFD_RELOC_ARM_HWLITERAL
:
23395 if (validate_offset_imm (value
, 1) == FAIL
)
23397 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
23398 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23399 _("invalid literal constant: pool needs to be closer"));
23401 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23402 _("bad immediate value for 8-bit offset (%ld)"),
23407 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23409 newval
&= 0xfffff0f0;
23412 newval
&= 0xff7ff0f0;
23413 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
23415 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23418 case BFD_RELOC_ARM_T32_OFFSET_U8
:
23419 if (value
< 0 || value
> 1020 || value
% 4 != 0)
23420 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23421 _("bad immediate value for offset (%ld)"), (long) value
);
23424 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
23426 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
23429 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23430 /* This is a complicated relocation used for all varieties of Thumb32
23431 load/store instruction with immediate offset:
23433 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
23434 *4, optional writeback(W)
23435 (doubleword load/store)
23437 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
23438 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
23439 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
23440 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
23441 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
23443 Uppercase letters indicate bits that are already encoded at
23444 this point. Lowercase letters are our problem. For the
23445 second block of instructions, the secondary opcode nybble
23446 (bits 8..11) is present, and bit 23 is zero, even if this is
23447 a PC-relative operation. */
23448 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23450 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
23452 if ((newval
& 0xf0000000) == 0xe0000000)
23454 /* Doubleword load/store: 8-bit offset, scaled by 4. */
23456 newval
|= (1 << 23);
23459 if (value
% 4 != 0)
23461 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23462 _("offset not a multiple of 4"));
23468 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23469 _("offset out of range"));
23474 else if ((newval
& 0x000f0000) == 0x000f0000)
23476 /* PC-relative, 12-bit offset. */
23478 newval
|= (1 << 23);
23483 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23484 _("offset out of range"));
23489 else if ((newval
& 0x00000100) == 0x00000100)
23491 /* Writeback: 8-bit, +/- offset. */
23493 newval
|= (1 << 9);
23498 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23499 _("offset out of range"));
23504 else if ((newval
& 0x00000f00) == 0x00000e00)
23506 /* T-instruction: positive 8-bit offset. */
23507 if (value
< 0 || value
> 0xff)
23509 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23510 _("offset out of range"));
23518 /* Positive 12-bit or negative 8-bit offset. */
23522 newval
|= (1 << 23);
23532 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23533 _("offset out of range"));
23540 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23541 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23544 case BFD_RELOC_ARM_SHIFT_IMM
:
23545 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23546 if (((unsigned long) value
) > 32
23548 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23550 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23551 _("shift expression is too large"));
23556 /* Shifts of zero must be done as lsl. */
23558 else if (value
== 32)
23560 newval
&= 0xfffff07f;
23561 newval
|= (value
& 0x1f) << 7;
23562 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23565 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23566 case BFD_RELOC_ARM_T32_ADD_IMM
:
23567 case BFD_RELOC_ARM_T32_IMM12
:
23568 case BFD_RELOC_ARM_T32_ADD_PC12
:
23569 /* We claim that this fixup has been processed here,
23570 even if in fact we generate an error because we do
23571 not have a reloc for it, so tc_gen_reloc will reject it. */
23575 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23577 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23578 _("undefined symbol %s used as an immediate value"),
23579 S_GET_NAME (fixP
->fx_addsy
));
23583 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23585 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23588 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23589 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
23590 Thumb2 modified immediate encoding (T2). */
23591 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
23592 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23594 newimm
= encode_thumb32_immediate (value
);
23595 if (newimm
== (unsigned int) FAIL
)
23596 newimm
= thumb32_negate_data_op (&newval
, value
);
23598 if (newimm
== (unsigned int) FAIL
)
23600 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
23602 /* Turn add/sum into addw/subw. */
23603 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23604 newval
= (newval
& 0xfeffffff) | 0x02000000;
23605 /* No flat 12-bit imm encoding for addsw/subsw. */
23606 if ((newval
& 0x00100000) == 0)
23608 /* 12 bit immediate for addw/subw. */
23612 newval
^= 0x00a00000;
23615 newimm
= (unsigned int) FAIL
;
23622 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
23623 UINT16 (T3 encoding), MOVW only accepts UINT16. When
23624 disassembling, MOV is preferred when there is no encoding
23626 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
23627 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
23628 but with the Rn field [19:16] set to 1111. */
23629 && (((newval
>> 16) & 0xf) == 0xf)
23630 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
23631 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
23632 && value
>= 0 && value
<= 0xffff)
23634 /* Toggle bit[25] to change encoding from T2 to T3. */
23636 /* Clear bits[19:16]. */
23637 newval
&= 0xfff0ffff;
23638 /* Encoding high 4bits imm. Code below will encode the
23639 remaining low 12bits. */
23640 newval
|= (value
& 0x0000f000) << 4;
23641 newimm
= value
& 0x00000fff;
23646 if (newimm
== (unsigned int)FAIL
)
23648 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23649 _("invalid constant (%lx) after fixup"),
23650 (unsigned long) value
);
23654 newval
|= (newimm
& 0x800) << 15;
23655 newval
|= (newimm
& 0x700) << 4;
23656 newval
|= (newimm
& 0x0ff);
23658 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23659 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23662 case BFD_RELOC_ARM_SMC
:
23663 if (((unsigned long) value
) > 0xffff)
23664 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23665 _("invalid smc expression"));
23666 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23667 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23668 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23671 case BFD_RELOC_ARM_HVC
:
23672 if (((unsigned long) value
) > 0xffff)
23673 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23674 _("invalid hvc expression"));
23675 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23676 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23677 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23680 case BFD_RELOC_ARM_SWI
:
23681 if (fixP
->tc_fix_data
!= 0)
23683 if (((unsigned long) value
) > 0xff)
23684 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23685 _("invalid swi expression"));
23686 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23688 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23692 if (((unsigned long) value
) > 0x00ffffff)
23693 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23694 _("invalid swi expression"));
23695 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23697 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23701 case BFD_RELOC_ARM_MULTI
:
23702 if (((unsigned long) value
) > 0xffff)
23703 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23704 _("invalid expression in load/store multiple"));
23705 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23706 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23710 case BFD_RELOC_ARM_PCREL_CALL
:
23712 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23714 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23715 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23716 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23717 /* Flip the bl to blx. This is a simple flip
23718 bit here because we generate PCREL_CALL for
23719 unconditional bls. */
23721 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23722 newval
= newval
| 0x10000000;
23723 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23729 goto arm_branch_common
;
23731 case BFD_RELOC_ARM_PCREL_JUMP
:
23732 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23734 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23735 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23736 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23738 /* This would map to a bl<cond>, b<cond>,
23739 b<always> to a Thumb function. We
23740 need to force a relocation for this particular
23742 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23745 /* Fall through. */
23747 case BFD_RELOC_ARM_PLT32
:
23749 case BFD_RELOC_ARM_PCREL_BRANCH
:
23751 goto arm_branch_common
;
23753 case BFD_RELOC_ARM_PCREL_BLX
:
23756 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23758 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23759 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23760 && ARM_IS_FUNC (fixP
->fx_addsy
))
23762 /* Flip the blx to a bl and warn. */
23763 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23764 newval
= 0xeb000000;
23765 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23766 _("blx to '%s' an ARM ISA state function changed to bl"),
23768 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23774 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23775 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23779 /* We are going to store value (shifted right by two) in the
23780 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23781 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23784 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23785 _("misaligned branch destination"));
23786 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23787 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23788 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23790 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23792 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23793 newval
|= (value
>> 2) & 0x00ffffff;
23794 /* Set the H bit on BLX instructions. */
23798 newval
|= 0x01000000;
23800 newval
&= ~0x01000000;
23802 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23806 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23807 /* CBZ can only branch forward. */
23809 /* Attempts to use CBZ to branch to the next instruction
23810 (which, strictly speaking, are prohibited) will be turned into
23813 FIXME: It may be better to remove the instruction completely and
23814 perform relaxation. */
23817 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23818 newval
= 0xbf00; /* NOP encoding T1 */
23819 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23824 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23826 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23828 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23829 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23830 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23835 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23836 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23837 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23839 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23841 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23842 newval
|= (value
& 0x1ff) >> 1;
23843 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23847 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23848 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23849 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23851 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23853 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23854 newval
|= (value
& 0xfff) >> 1;
23855 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23859 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23861 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23862 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23863 && ARM_IS_FUNC (fixP
->fx_addsy
)
23864 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23866 /* Force a relocation for a branch 20 bits wide. */
23869 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23870 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23871 _("conditional branch out of range"));
23873 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23876 addressT S
, J1
, J2
, lo
, hi
;
23878 S
= (value
& 0x00100000) >> 20;
23879 J2
= (value
& 0x00080000) >> 19;
23880 J1
= (value
& 0x00040000) >> 18;
23881 hi
= (value
& 0x0003f000) >> 12;
23882 lo
= (value
& 0x00000ffe) >> 1;
23884 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23885 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23886 newval
|= (S
<< 10) | hi
;
23887 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23888 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23889 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23893 case BFD_RELOC_THUMB_PCREL_BLX
:
23894 /* If there is a blx from a thumb state function to
23895 another thumb function flip this to a bl and warn
23899 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23900 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23901 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23903 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23904 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23905 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23907 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23908 newval
= newval
| 0x1000;
23909 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23910 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23915 goto thumb_bl_common
;
23917 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23918 /* A bl from Thumb state ISA to an internal ARM state function
23919 is converted to a blx. */
23921 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23922 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23923 && ARM_IS_FUNC (fixP
->fx_addsy
)
23924 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23926 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23927 newval
= newval
& ~0x1000;
23928 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23929 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23935 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23936 /* For a BLX instruction, make sure that the relocation is rounded up
23937 to a word boundary. This follows the semantics of the instruction
23938 which specifies that bit 1 of the target address will come from bit
23939 1 of the base address. */
23940 value
= (value
+ 3) & ~ 3;
23943 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23944 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23945 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23948 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23950 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23951 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23952 else if ((value
& ~0x1ffffff)
23953 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23954 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23955 _("Thumb2 branch out of range"));
23958 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23959 encode_thumb2_b_bl_offset (buf
, value
);
23963 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23964 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23965 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23967 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23968 encode_thumb2_b_bl_offset (buf
, value
);
23973 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23978 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23979 md_number_to_chars (buf
, value
, 2);
23983 case BFD_RELOC_ARM_TLS_CALL
:
23984 case BFD_RELOC_ARM_THM_TLS_CALL
:
23985 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23986 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23987 case BFD_RELOC_ARM_TLS_GOTDESC
:
23988 case BFD_RELOC_ARM_TLS_GD32
:
23989 case BFD_RELOC_ARM_TLS_LE32
:
23990 case BFD_RELOC_ARM_TLS_IE32
:
23991 case BFD_RELOC_ARM_TLS_LDM32
:
23992 case BFD_RELOC_ARM_TLS_LDO32
:
23993 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23996 /* Same handling as above, but with the arm_fdpic guard. */
23997 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
23998 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
23999 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
24002 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
24006 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24007 _("Relocation supported only in FDPIC mode"));
24011 case BFD_RELOC_ARM_GOT32
:
24012 case BFD_RELOC_ARM_GOTOFF
:
24015 case BFD_RELOC_ARM_GOT_PREL
:
24016 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24017 md_number_to_chars (buf
, value
, 4);
24020 case BFD_RELOC_ARM_TARGET2
:
24021 /* TARGET2 is not partial-inplace, so we need to write the
24022 addend here for REL targets, because it won't be written out
24023 during reloc processing later. */
24024 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24025 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
24028 /* Relocations for FDPIC. */
24029 case BFD_RELOC_ARM_GOTFUNCDESC
:
24030 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
24031 case BFD_RELOC_ARM_FUNCDESC
:
24034 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24035 md_number_to_chars (buf
, 0, 4);
24039 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24040 _("Relocation supported only in FDPIC mode"));
24045 case BFD_RELOC_RVA
:
24047 case BFD_RELOC_ARM_TARGET1
:
24048 case BFD_RELOC_ARM_ROSEGREL32
:
24049 case BFD_RELOC_ARM_SBREL32
:
24050 case BFD_RELOC_32_PCREL
:
24052 case BFD_RELOC_32_SECREL
:
24054 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24056 /* For WinCE we only do this for pcrel fixups. */
24057 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
24059 md_number_to_chars (buf
, value
, 4);
24063 case BFD_RELOC_ARM_PREL31
:
24064 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24066 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
24067 if ((value
^ (value
>> 1)) & 0x40000000)
24069 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24070 _("rel31 relocation overflow"));
24072 newval
|= value
& 0x7fffffff;
24073 md_number_to_chars (buf
, newval
, 4);
24078 case BFD_RELOC_ARM_CP_OFF_IMM
:
24079 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
24080 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
24081 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24083 newval
= get_thumb32_insn (buf
);
24084 if ((newval
& 0x0f200f00) == 0x0d000900)
24086 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
24087 has permitted values that are multiples of 2, in the range 0
24089 if (value
< -510 || value
> 510 || (value
& 1))
24090 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24091 _("co-processor offset out of range"));
24093 else if (value
< -1023 || value
> 1023 || (value
& 3))
24094 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24095 _("co-processor offset out of range"));
24100 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24101 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24102 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24104 newval
= get_thumb32_insn (buf
);
24106 newval
&= 0xffffff00;
24109 newval
&= 0xff7fff00;
24110 if ((newval
& 0x0f200f00) == 0x0d000900)
24112 /* This is a fp16 vstr/vldr.
24114 It requires the immediate offset in the instruction is shifted
24115 left by 1 to be a half-word offset.
24117 Here, left shift by 1 first, and later right shift by 2
24118 should get the right offset. */
24121 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
24123 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24124 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24125 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24127 put_thumb32_insn (buf
, newval
);
24130 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
24131 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
24132 if (value
< -255 || value
> 255)
24133 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24134 _("co-processor offset out of range"));
24136 goto cp_off_common
;
24138 case BFD_RELOC_ARM_THUMB_OFFSET
:
24139 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24140 /* Exactly what ranges, and where the offset is inserted depends
24141 on the type of instruction, we can establish this from the
24143 switch (newval
>> 12)
24145 case 4: /* PC load. */
24146 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
24147 forced to zero for these loads; md_pcrel_from has already
24148 compensated for this. */
24150 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24151 _("invalid offset, target not word aligned (0x%08lX)"),
24152 (((unsigned long) fixP
->fx_frag
->fr_address
24153 + (unsigned long) fixP
->fx_where
) & ~3)
24154 + (unsigned long) value
);
24156 if (value
& ~0x3fc)
24157 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24158 _("invalid offset, value too big (0x%08lX)"),
24161 newval
|= value
>> 2;
24164 case 9: /* SP load/store. */
24165 if (value
& ~0x3fc)
24166 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24167 _("invalid offset, value too big (0x%08lX)"),
24169 newval
|= value
>> 2;
24172 case 6: /* Word load/store. */
24174 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24175 _("invalid offset, value too big (0x%08lX)"),
24177 newval
|= value
<< 4; /* 6 - 2. */
24180 case 7: /* Byte load/store. */
24182 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24183 _("invalid offset, value too big (0x%08lX)"),
24185 newval
|= value
<< 6;
24188 case 8: /* Halfword load/store. */
24190 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24191 _("invalid offset, value too big (0x%08lX)"),
24193 newval
|= value
<< 5; /* 6 - 1. */
24197 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24198 "Unable to process relocation for thumb opcode: %lx",
24199 (unsigned long) newval
);
24202 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24205 case BFD_RELOC_ARM_THUMB_ADD
:
24206 /* This is a complicated relocation, since we use it for all of
24207 the following immediate relocations:
24211 9bit ADD/SUB SP word-aligned
24212 10bit ADD PC/SP word-aligned
24214 The type of instruction being processed is encoded in the
24221 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24223 int rd
= (newval
>> 4) & 0xf;
24224 int rs
= newval
& 0xf;
24225 int subtract
= !!(newval
& 0x8000);
24227 /* Check for HI regs, only very restricted cases allowed:
24228 Adjusting SP, and using PC or SP to get an address. */
24229 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
24230 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
24231 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24232 _("invalid Hi register with immediate"));
24234 /* If value is negative, choose the opposite instruction. */
24238 subtract
= !subtract
;
24240 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24241 _("immediate value out of range"));
24246 if (value
& ~0x1fc)
24247 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24248 _("invalid immediate for stack address calculation"));
24249 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
24250 newval
|= value
>> 2;
24252 else if (rs
== REG_PC
|| rs
== REG_SP
)
24254 /* PR gas/18541. If the addition is for a defined symbol
24255 within range of an ADR instruction then accept it. */
24258 && fixP
->fx_addsy
!= NULL
)
24262 if (! S_IS_DEFINED (fixP
->fx_addsy
)
24263 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
24264 || S_IS_WEAK (fixP
->fx_addsy
))
24266 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24267 _("address calculation needs a strongly defined nearby symbol"));
24271 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
24273 /* Round up to the next 4-byte boundary. */
24278 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
24282 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24283 _("symbol too far away"));
24293 if (subtract
|| value
& ~0x3fc)
24294 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24295 _("invalid immediate for address calculation (value = 0x%08lX)"),
24296 (unsigned long) (subtract
? - value
: value
));
24297 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
24299 newval
|= value
>> 2;
24304 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24305 _("immediate value out of range"));
24306 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
24307 newval
|= (rd
<< 8) | value
;
24312 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24313 _("immediate value out of range"));
24314 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
24315 newval
|= rd
| (rs
<< 3) | (value
<< 6);
24318 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24321 case BFD_RELOC_ARM_THUMB_IMM
:
24322 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24323 if (value
< 0 || value
> 255)
24324 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24325 _("invalid immediate: %ld is out of range"),
24328 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24331 case BFD_RELOC_ARM_THUMB_SHIFT
:
24332 /* 5bit shift value (0..32). LSL cannot take 32. */
24333 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
24334 temp
= newval
& 0xf800;
24335 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
24336 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24337 _("invalid shift value: %ld"), (long) value
);
24338 /* Shifts of zero must be encoded as LSL. */
24340 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
24341 /* Shifts of 32 are encoded as zero. */
24342 else if (value
== 32)
24344 newval
|= value
<< 6;
24345 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24348 case BFD_RELOC_VTABLE_INHERIT
:
24349 case BFD_RELOC_VTABLE_ENTRY
:
24353 case BFD_RELOC_ARM_MOVW
:
24354 case BFD_RELOC_ARM_MOVT
:
24355 case BFD_RELOC_ARM_THUMB_MOVW
:
24356 case BFD_RELOC_ARM_THUMB_MOVT
:
24357 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24359 /* REL format relocations are limited to a 16-bit addend. */
24360 if (!fixP
->fx_done
)
24362 if (value
< -0x8000 || value
> 0x7fff)
24363 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24364 _("offset out of range"));
24366 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24367 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24372 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24373 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24375 newval
= get_thumb32_insn (buf
);
24376 newval
&= 0xfbf08f00;
24377 newval
|= (value
& 0xf000) << 4;
24378 newval
|= (value
& 0x0800) << 15;
24379 newval
|= (value
& 0x0700) << 4;
24380 newval
|= (value
& 0x00ff);
24381 put_thumb32_insn (buf
, newval
);
24385 newval
= md_chars_to_number (buf
, 4);
24386 newval
&= 0xfff0f000;
24387 newval
|= value
& 0x0fff;
24388 newval
|= (value
& 0xf000) << 4;
24389 md_number_to_chars (buf
, newval
, 4);
24394 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24395 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24396 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24397 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24398 gas_assert (!fixP
->fx_done
);
24401 bfd_boolean is_mov
;
24402 bfd_vma encoded_addend
= value
;
24404 /* Check that addend can be encoded in instruction. */
24405 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
24406 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24407 _("the offset 0x%08lX is not representable"),
24408 (unsigned long) encoded_addend
);
24410 /* Extract the instruction. */
24411 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
24412 is_mov
= (insn
& 0xf800) == 0x2000;
24417 if (!seg
->use_rela_p
)
24418 insn
|= encoded_addend
;
24424 /* Extract the instruction. */
24425 /* Encoding is the following
24430 /* The following conditions must be true :
24435 rd
= (insn
>> 4) & 0xf;
24437 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
24438 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24439 _("Unable to process relocation for thumb opcode: %lx"),
24440 (unsigned long) insn
);
24442 /* Encode as ADD immediate8 thumb 1 code. */
24443 insn
= 0x3000 | (rd
<< 8);
24445 /* Place the encoded addend into the first 8 bits of the
24447 if (!seg
->use_rela_p
)
24448 insn
|= encoded_addend
;
24451 /* Update the instruction. */
24452 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
24456 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24457 case BFD_RELOC_ARM_ALU_PC_G0
:
24458 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24459 case BFD_RELOC_ARM_ALU_PC_G1
:
24460 case BFD_RELOC_ARM_ALU_PC_G2
:
24461 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24462 case BFD_RELOC_ARM_ALU_SB_G0
:
24463 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24464 case BFD_RELOC_ARM_ALU_SB_G1
:
24465 case BFD_RELOC_ARM_ALU_SB_G2
:
24466 gas_assert (!fixP
->fx_done
);
24467 if (!seg
->use_rela_p
)
24470 bfd_vma encoded_addend
;
24471 bfd_vma addend_abs
= abs (value
);
24473 /* Check that the absolute value of the addend can be
24474 expressed as an 8-bit constant plus a rotation. */
24475 encoded_addend
= encode_arm_immediate (addend_abs
);
24476 if (encoded_addend
== (unsigned int) FAIL
)
24477 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24478 _("the offset 0x%08lX is not representable"),
24479 (unsigned long) addend_abs
);
24481 /* Extract the instruction. */
24482 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24484 /* If the addend is positive, use an ADD instruction.
24485 Otherwise use a SUB. Take care not to destroy the S bit. */
24486 insn
&= 0xff1fffff;
24492 /* Place the encoded addend into the first 12 bits of the
24494 insn
&= 0xfffff000;
24495 insn
|= encoded_addend
;
24497 /* Update the instruction. */
24498 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24502 case BFD_RELOC_ARM_LDR_PC_G0
:
24503 case BFD_RELOC_ARM_LDR_PC_G1
:
24504 case BFD_RELOC_ARM_LDR_PC_G2
:
24505 case BFD_RELOC_ARM_LDR_SB_G0
:
24506 case BFD_RELOC_ARM_LDR_SB_G1
:
24507 case BFD_RELOC_ARM_LDR_SB_G2
:
24508 gas_assert (!fixP
->fx_done
);
24509 if (!seg
->use_rela_p
)
24512 bfd_vma addend_abs
= abs (value
);
24514 /* Check that the absolute value of the addend can be
24515 encoded in 12 bits. */
24516 if (addend_abs
>= 0x1000)
24517 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24518 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
24519 (unsigned long) addend_abs
);
24521 /* Extract the instruction. */
24522 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24524 /* If the addend is negative, clear bit 23 of the instruction.
24525 Otherwise set it. */
24527 insn
&= ~(1 << 23);
24531 /* Place the absolute value of the addend into the first 12 bits
24532 of the instruction. */
24533 insn
&= 0xfffff000;
24534 insn
|= addend_abs
;
24536 /* Update the instruction. */
24537 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24541 case BFD_RELOC_ARM_LDRS_PC_G0
:
24542 case BFD_RELOC_ARM_LDRS_PC_G1
:
24543 case BFD_RELOC_ARM_LDRS_PC_G2
:
24544 case BFD_RELOC_ARM_LDRS_SB_G0
:
24545 case BFD_RELOC_ARM_LDRS_SB_G1
:
24546 case BFD_RELOC_ARM_LDRS_SB_G2
:
24547 gas_assert (!fixP
->fx_done
);
24548 if (!seg
->use_rela_p
)
24551 bfd_vma addend_abs
= abs (value
);
24553 /* Check that the absolute value of the addend can be
24554 encoded in 8 bits. */
24555 if (addend_abs
>= 0x100)
24556 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24557 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
24558 (unsigned long) addend_abs
);
24560 /* Extract the instruction. */
24561 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24563 /* If the addend is negative, clear bit 23 of the instruction.
24564 Otherwise set it. */
24566 insn
&= ~(1 << 23);
24570 /* Place the first four bits of the absolute value of the addend
24571 into the first 4 bits of the instruction, and the remaining
24572 four into bits 8 .. 11. */
24573 insn
&= 0xfffff0f0;
24574 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
24576 /* Update the instruction. */
24577 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24581 case BFD_RELOC_ARM_LDC_PC_G0
:
24582 case BFD_RELOC_ARM_LDC_PC_G1
:
24583 case BFD_RELOC_ARM_LDC_PC_G2
:
24584 case BFD_RELOC_ARM_LDC_SB_G0
:
24585 case BFD_RELOC_ARM_LDC_SB_G1
:
24586 case BFD_RELOC_ARM_LDC_SB_G2
:
24587 gas_assert (!fixP
->fx_done
);
24588 if (!seg
->use_rela_p
)
24591 bfd_vma addend_abs
= abs (value
);
24593 /* Check that the absolute value of the addend is a multiple of
24594 four and, when divided by four, fits in 8 bits. */
24595 if (addend_abs
& 0x3)
24596 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24597 _("bad offset 0x%08lX (must be word-aligned)"),
24598 (unsigned long) addend_abs
);
24600 if ((addend_abs
>> 2) > 0xff)
24601 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24602 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24603 (unsigned long) addend_abs
);
24605 /* Extract the instruction. */
24606 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24608 /* If the addend is negative, clear bit 23 of the instruction.
24609 Otherwise set it. */
24611 insn
&= ~(1 << 23);
24615 /* Place the addend (divided by four) into the first eight
24616 bits of the instruction. */
24617 insn
&= 0xfffffff0;
24618 insn
|= addend_abs
>> 2;
24620 /* Update the instruction. */
24621 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24625 case BFD_RELOC_ARM_V4BX
:
24626 /* This will need to go in the object file. */
24630 case BFD_RELOC_UNUSED
:
24632 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24633 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24637 /* Translate internal representation of relocation info to BFD target
24641 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24644 bfd_reloc_code_real_type code
;
24646 reloc
= XNEW (arelent
);
24648 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24649 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24650 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24652 if (fixp
->fx_pcrel
)
24654 if (section
->use_rela_p
)
24655 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24657 fixp
->fx_offset
= reloc
->address
;
24659 reloc
->addend
= fixp
->fx_offset
;
24661 switch (fixp
->fx_r_type
)
24664 if (fixp
->fx_pcrel
)
24666 code
= BFD_RELOC_8_PCREL
;
24669 /* Fall through. */
24672 if (fixp
->fx_pcrel
)
24674 code
= BFD_RELOC_16_PCREL
;
24677 /* Fall through. */
24680 if (fixp
->fx_pcrel
)
24682 code
= BFD_RELOC_32_PCREL
;
24685 /* Fall through. */
24687 case BFD_RELOC_ARM_MOVW
:
24688 if (fixp
->fx_pcrel
)
24690 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24693 /* Fall through. */
24695 case BFD_RELOC_ARM_MOVT
:
24696 if (fixp
->fx_pcrel
)
24698 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24701 /* Fall through. */
24703 case BFD_RELOC_ARM_THUMB_MOVW
:
24704 if (fixp
->fx_pcrel
)
24706 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24709 /* Fall through. */
24711 case BFD_RELOC_ARM_THUMB_MOVT
:
24712 if (fixp
->fx_pcrel
)
24714 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24717 /* Fall through. */
24719 case BFD_RELOC_NONE
:
24720 case BFD_RELOC_ARM_PCREL_BRANCH
:
24721 case BFD_RELOC_ARM_PCREL_BLX
:
24722 case BFD_RELOC_RVA
:
24723 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24724 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24725 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24726 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24727 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24728 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24729 case BFD_RELOC_VTABLE_ENTRY
:
24730 case BFD_RELOC_VTABLE_INHERIT
:
24732 case BFD_RELOC_32_SECREL
:
24734 code
= fixp
->fx_r_type
;
24737 case BFD_RELOC_THUMB_PCREL_BLX
:
24739 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24740 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24743 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24746 case BFD_RELOC_ARM_LITERAL
:
24747 case BFD_RELOC_ARM_HWLITERAL
:
24748 /* If this is called then the a literal has
24749 been referenced across a section boundary. */
24750 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24751 _("literal referenced across section boundary"));
24755 case BFD_RELOC_ARM_TLS_CALL
:
24756 case BFD_RELOC_ARM_THM_TLS_CALL
:
24757 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24758 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24759 case BFD_RELOC_ARM_GOT32
:
24760 case BFD_RELOC_ARM_GOTOFF
:
24761 case BFD_RELOC_ARM_GOT_PREL
:
24762 case BFD_RELOC_ARM_PLT32
:
24763 case BFD_RELOC_ARM_TARGET1
:
24764 case BFD_RELOC_ARM_ROSEGREL32
:
24765 case BFD_RELOC_ARM_SBREL32
:
24766 case BFD_RELOC_ARM_PREL31
:
24767 case BFD_RELOC_ARM_TARGET2
:
24768 case BFD_RELOC_ARM_TLS_LDO32
:
24769 case BFD_RELOC_ARM_PCREL_CALL
:
24770 case BFD_RELOC_ARM_PCREL_JUMP
:
24771 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24772 case BFD_RELOC_ARM_ALU_PC_G0
:
24773 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24774 case BFD_RELOC_ARM_ALU_PC_G1
:
24775 case BFD_RELOC_ARM_ALU_PC_G2
:
24776 case BFD_RELOC_ARM_LDR_PC_G0
:
24777 case BFD_RELOC_ARM_LDR_PC_G1
:
24778 case BFD_RELOC_ARM_LDR_PC_G2
:
24779 case BFD_RELOC_ARM_LDRS_PC_G0
:
24780 case BFD_RELOC_ARM_LDRS_PC_G1
:
24781 case BFD_RELOC_ARM_LDRS_PC_G2
:
24782 case BFD_RELOC_ARM_LDC_PC_G0
:
24783 case BFD_RELOC_ARM_LDC_PC_G1
:
24784 case BFD_RELOC_ARM_LDC_PC_G2
:
24785 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24786 case BFD_RELOC_ARM_ALU_SB_G0
:
24787 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24788 case BFD_RELOC_ARM_ALU_SB_G1
:
24789 case BFD_RELOC_ARM_ALU_SB_G2
:
24790 case BFD_RELOC_ARM_LDR_SB_G0
:
24791 case BFD_RELOC_ARM_LDR_SB_G1
:
24792 case BFD_RELOC_ARM_LDR_SB_G2
:
24793 case BFD_RELOC_ARM_LDRS_SB_G0
:
24794 case BFD_RELOC_ARM_LDRS_SB_G1
:
24795 case BFD_RELOC_ARM_LDRS_SB_G2
:
24796 case BFD_RELOC_ARM_LDC_SB_G0
:
24797 case BFD_RELOC_ARM_LDC_SB_G1
:
24798 case BFD_RELOC_ARM_LDC_SB_G2
:
24799 case BFD_RELOC_ARM_V4BX
:
24800 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24801 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24802 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24803 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24804 case BFD_RELOC_ARM_GOTFUNCDESC
:
24805 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
24806 case BFD_RELOC_ARM_FUNCDESC
:
24807 code
= fixp
->fx_r_type
;
24810 case BFD_RELOC_ARM_TLS_GOTDESC
:
24811 case BFD_RELOC_ARM_TLS_GD32
:
24812 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
24813 case BFD_RELOC_ARM_TLS_LE32
:
24814 case BFD_RELOC_ARM_TLS_IE32
:
24815 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
24816 case BFD_RELOC_ARM_TLS_LDM32
:
24817 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
24818 /* BFD will include the symbol's address in the addend.
24819 But we don't want that, so subtract it out again here. */
24820 if (!S_IS_COMMON (fixp
->fx_addsy
))
24821 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24822 code
= fixp
->fx_r_type
;
24826 case BFD_RELOC_ARM_IMMEDIATE
:
24827 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24828 _("internal relocation (type: IMMEDIATE) not fixed up"));
24831 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24832 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24833 _("ADRL used for a symbol not defined in the same file"));
24836 case BFD_RELOC_ARM_OFFSET_IMM
:
24837 if (section
->use_rela_p
)
24839 code
= fixp
->fx_r_type
;
24843 if (fixp
->fx_addsy
!= NULL
24844 && !S_IS_DEFINED (fixp
->fx_addsy
)
24845 && S_IS_LOCAL (fixp
->fx_addsy
))
24847 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24848 _("undefined local label `%s'"),
24849 S_GET_NAME (fixp
->fx_addsy
));
24853 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24854 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24861 switch (fixp
->fx_r_type
)
24863 case BFD_RELOC_NONE
: type
= "NONE"; break;
24864 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24865 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24866 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24867 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24868 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24869 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24870 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24871 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24872 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24873 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24874 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24875 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24876 default: type
= _("<unknown>"); break;
24878 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24879 _("cannot represent %s relocation in this object file format"),
24886 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24888 && fixp
->fx_addsy
== GOT_symbol
)
24890 code
= BFD_RELOC_ARM_GOTPC
;
24891 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24895 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24897 if (reloc
->howto
== NULL
)
24899 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24900 _("cannot represent %s relocation in this object file format"),
24901 bfd_get_reloc_code_name (code
));
24905 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24906 vtable entry to be used in the relocation's section offset. */
24907 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24908 reloc
->address
= fixp
->fx_offset
;
24913 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24916 cons_fix_new_arm (fragS
* frag
,
24920 bfd_reloc_code_real_type reloc
)
24925 FIXME: @@ Should look at CPU word size. */
24929 reloc
= BFD_RELOC_8
;
24932 reloc
= BFD_RELOC_16
;
24936 reloc
= BFD_RELOC_32
;
24939 reloc
= BFD_RELOC_64
;
24944 if (exp
->X_op
== O_secrel
)
24946 exp
->X_op
= O_symbol
;
24947 reloc
= BFD_RELOC_32_SECREL
;
24951 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24954 #if defined (OBJ_COFF)
24956 arm_validate_fix (fixS
* fixP
)
24958 /* If the destination of the branch is a defined symbol which does not have
24959 the THUMB_FUNC attribute, then we must be calling a function which has
24960 the (interfacearm) attribute. We look for the Thumb entry point to that
24961 function and change the branch to refer to that function instead. */
24962 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24963 && fixP
->fx_addsy
!= NULL
24964 && S_IS_DEFINED (fixP
->fx_addsy
)
24965 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24967 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24974 arm_force_relocation (struct fix
* fixp
)
24976 #if defined (OBJ_COFF) && defined (TE_PE)
24977 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24981 /* In case we have a call or a branch to a function in ARM ISA mode from
24982 a thumb function or vice-versa force the relocation. These relocations
24983 are cleared off for some cores that might have blx and simple transformations
24987 switch (fixp
->fx_r_type
)
24989 case BFD_RELOC_ARM_PCREL_JUMP
:
24990 case BFD_RELOC_ARM_PCREL_CALL
:
24991 case BFD_RELOC_THUMB_PCREL_BLX
:
24992 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24996 case BFD_RELOC_ARM_PCREL_BLX
:
24997 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24998 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24999 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25000 if (ARM_IS_FUNC (fixp
->fx_addsy
))
25009 /* Resolve these relocations even if the symbol is extern or weak.
25010 Technically this is probably wrong due to symbol preemption.
25011 In practice these relocations do not have enough range to be useful
25012 at dynamic link time, and some code (e.g. in the Linux kernel)
25013 expects these references to be resolved. */
25014 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
25015 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
25016 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
25017 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
25018 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
25019 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
25020 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
25021 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
25022 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
25023 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
25024 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
25025 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
25026 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
25027 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
25030 /* Always leave these relocations for the linker. */
25031 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
25032 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
25033 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
25036 /* Always generate relocations against function symbols. */
25037 if (fixp
->fx_r_type
== BFD_RELOC_32
25039 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
25042 return generic_force_reloc (fixp
);
25045 #if defined (OBJ_ELF) || defined (OBJ_COFF)
25046 /* Relocations against function names must be left unadjusted,
25047 so that the linker can use this information to generate interworking
25048 stubs. The MIPS version of this function
25049 also prevents relocations that are mips-16 specific, but I do not
25050 know why it does this.
25053 There is one other problem that ought to be addressed here, but
25054 which currently is not: Taking the address of a label (rather
25055 than a function) and then later jumping to that address. Such
25056 addresses also ought to have their bottom bit set (assuming that
25057 they reside in Thumb code), but at the moment they will not. */
25060 arm_fix_adjustable (fixS
* fixP
)
25062 if (fixP
->fx_addsy
== NULL
)
25065 /* Preserve relocations against symbols with function type. */
25066 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
25069 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
25070 && fixP
->fx_subsy
== NULL
)
25073 /* We need the symbol name for the VTABLE entries. */
25074 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
25075 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
25078 /* Don't allow symbols to be discarded on GOT related relocs. */
25079 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
25080 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
25081 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
25082 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
25083 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
25084 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
25085 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
25086 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
25087 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
25088 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
25089 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
25090 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
25091 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
25092 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
25093 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
25094 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
25095 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
25098 /* Similarly for group relocations. */
25099 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
25100 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
25101 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
25104 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
25105 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
25106 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
25107 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
25108 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
25109 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
25110 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
25111 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
25112 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
25115 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
25116 offsets, so keep these symbols. */
25117 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
25118 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
25123 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
25127 elf32_arm_target_format (void)
25130 return (target_big_endian
25131 ? "elf32-bigarm-symbian"
25132 : "elf32-littlearm-symbian");
25133 #elif defined (TE_VXWORKS)
25134 return (target_big_endian
25135 ? "elf32-bigarm-vxworks"
25136 : "elf32-littlearm-vxworks");
25137 #elif defined (TE_NACL)
25138 return (target_big_endian
25139 ? "elf32-bigarm-nacl"
25140 : "elf32-littlearm-nacl");
25144 if (target_big_endian
)
25145 return "elf32-bigarm-fdpic";
25147 return "elf32-littlearm-fdpic";
25151 if (target_big_endian
)
25152 return "elf32-bigarm";
25154 return "elf32-littlearm";
25160 armelf_frob_symbol (symbolS
* symp
,
25163 elf_frob_symbol (symp
, puntp
);
25167 /* MD interface: Finalization. */
25172 literal_pool
* pool
;
25174 /* Ensure that all the IT blocks are properly closed. */
25175 check_it_blocks_finished ();
25177 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
25179 /* Put it at the end of the relevant section. */
25180 subseg_set (pool
->section
, pool
->sub_section
);
25182 arm_elf_change_section ();
25189 /* Remove any excess mapping symbols generated for alignment frags in
25190 SEC. We may have created a mapping symbol before a zero byte
25191 alignment; remove it if there's a mapping symbol after the
25194 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
25195 void *dummy ATTRIBUTE_UNUSED
)
25197 segment_info_type
*seginfo
= seg_info (sec
);
25200 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
25203 for (fragp
= seginfo
->frchainP
->frch_root
;
25205 fragp
= fragp
->fr_next
)
25207 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
25208 fragS
*next
= fragp
->fr_next
;
25210 /* Variable-sized frags have been converted to fixed size by
25211 this point. But if this was variable-sized to start with,
25212 there will be a fixed-size frag after it. So don't handle
25214 if (sym
== NULL
|| next
== NULL
)
25217 if (S_GET_VALUE (sym
) < next
->fr_address
)
25218 /* Not at the end of this frag. */
25220 know (S_GET_VALUE (sym
) == next
->fr_address
);
25224 if (next
->tc_frag_data
.first_map
!= NULL
)
25226 /* Next frag starts with a mapping symbol. Discard this
25228 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25232 if (next
->fr_next
== NULL
)
25234 /* This mapping symbol is at the end of the section. Discard
25236 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
25237 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25241 /* As long as we have empty frags without any mapping symbols,
25243 /* If the next frag is non-empty and does not start with a
25244 mapping symbol, then this mapping symbol is required. */
25245 if (next
->fr_address
!= next
->fr_next
->fr_address
)
25248 next
= next
->fr_next
;
25250 while (next
!= NULL
);
25255 /* Adjust the symbol table. This marks Thumb symbols as distinct from
25259 arm_adjust_symtab (void)
25264 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25266 if (ARM_IS_THUMB (sym
))
25268 if (THUMB_IS_FUNC (sym
))
25270 /* Mark the symbol as a Thumb function. */
25271 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
25272 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
25273 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
25275 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
25276 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
25278 as_bad (_("%s: unexpected function type: %d"),
25279 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
25281 else switch (S_GET_STORAGE_CLASS (sym
))
25284 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
25287 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
25290 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
25298 if (ARM_IS_INTERWORK (sym
))
25299 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
25306 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25308 if (ARM_IS_THUMB (sym
))
25310 elf_symbol_type
* elf_sym
;
25312 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
25313 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
25315 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
25316 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
25318 /* If it's a .thumb_func, declare it as so,
25319 otherwise tag label as .code 16. */
25320 if (THUMB_IS_FUNC (sym
))
25321 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
25322 ST_BRANCH_TO_THUMB
);
25323 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25324 elf_sym
->internal_elf_sym
.st_info
=
25325 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
25330 /* Remove any overlapping mapping symbols generated by alignment frags. */
25331 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
25332 /* Now do generic ELF adjustments. */
25333 elf_adjust_symtab ();
25337 /* MD interface: Initialization. */
25340 set_constant_flonums (void)
25344 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
25345 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
25349 /* Auto-select Thumb mode if it's the only available instruction set for the
25350 given architecture. */
25353 autoselect_thumb_from_cpu_variant (void)
25355 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
25356 opcode_select (16);
25365 if ( (arm_ops_hsh
= hash_new ()) == NULL
25366 || (arm_cond_hsh
= hash_new ()) == NULL
25367 || (arm_shift_hsh
= hash_new ()) == NULL
25368 || (arm_psr_hsh
= hash_new ()) == NULL
25369 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
25370 || (arm_reg_hsh
= hash_new ()) == NULL
25371 || (arm_reloc_hsh
= hash_new ()) == NULL
25372 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
25373 as_fatal (_("virtual memory exhausted"));
25375 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
25376 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
25377 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
25378 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
25379 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
25380 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
25381 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
25382 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
25383 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
25384 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
25385 (void *) (v7m_psrs
+ i
));
25386 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
25387 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
25389 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
25391 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
25392 (void *) (barrier_opt_names
+ i
));
25394 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
25396 struct reloc_entry
* entry
= reloc_names
+ i
;
25398 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
25399 /* This makes encode_branch() use the EABI versions of this relocation. */
25400 entry
->reloc
= BFD_RELOC_UNUSED
;
25402 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
25406 set_constant_flonums ();
25408 /* Set the cpu variant based on the command-line options. We prefer
25409 -mcpu= over -march= if both are set (as for GCC); and we prefer
25410 -mfpu= over any other way of setting the floating point unit.
25411 Use of legacy options with new options are faulted. */
25414 if (mcpu_cpu_opt
|| march_cpu_opt
)
25415 as_bad (_("use of old and new-style options to set CPU type"));
25417 selected_arch
= *legacy_cpu
;
25419 else if (mcpu_cpu_opt
)
25421 selected_arch
= *mcpu_cpu_opt
;
25422 selected_ext
= *mcpu_ext_opt
;
25424 else if (march_cpu_opt
)
25426 selected_arch
= *march_cpu_opt
;
25427 selected_ext
= *march_ext_opt
;
25429 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
25434 as_bad (_("use of old and new-style options to set FPU type"));
25436 selected_fpu
= *legacy_fpu
;
25439 selected_fpu
= *mfpu_opt
;
25442 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
25443 || defined (TE_NetBSD) || defined (TE_VXWORKS))
25444 /* Some environments specify a default FPU. If they don't, infer it
25445 from the processor. */
25447 selected_fpu
= *mcpu_fpu_opt
;
25448 else if (march_fpu_opt
)
25449 selected_fpu
= *march_fpu_opt
;
25451 selected_fpu
= fpu_default
;
25455 if (ARM_FEATURE_ZERO (selected_fpu
))
25457 if (!no_cpu_selected ())
25458 selected_fpu
= fpu_default
;
25460 selected_fpu
= fpu_arch_fpa
;
25464 if (ARM_FEATURE_ZERO (selected_arch
))
25466 selected_arch
= cpu_default
;
25467 selected_cpu
= selected_arch
;
25469 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
25471 /* Autodection of feature mode: allow all features in cpu_variant but leave
25472 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
25473 after all instruction have been processed and we can decide what CPU
25474 should be selected. */
25475 if (ARM_FEATURE_ZERO (selected_arch
))
25476 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
25478 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
25481 autoselect_thumb_from_cpu_variant ();
25483 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
25485 #if defined OBJ_COFF || defined OBJ_ELF
25487 unsigned int flags
= 0;
25489 #if defined OBJ_ELF
25490 flags
= meabi_flags
;
25492 switch (meabi_flags
)
25494 case EF_ARM_EABI_UNKNOWN
:
25496 /* Set the flags in the private structure. */
25497 if (uses_apcs_26
) flags
|= F_APCS26
;
25498 if (support_interwork
) flags
|= F_INTERWORK
;
25499 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
25500 if (pic_code
) flags
|= F_PIC
;
25501 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
25502 flags
|= F_SOFT_FLOAT
;
25504 switch (mfloat_abi_opt
)
25506 case ARM_FLOAT_ABI_SOFT
:
25507 case ARM_FLOAT_ABI_SOFTFP
:
25508 flags
|= F_SOFT_FLOAT
;
25511 case ARM_FLOAT_ABI_HARD
:
25512 if (flags
& F_SOFT_FLOAT
)
25513 as_bad (_("hard-float conflicts with specified fpu"));
25517 /* Using pure-endian doubles (even if soft-float). */
25518 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
25519 flags
|= F_VFP_FLOAT
;
25521 #if defined OBJ_ELF
25522 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
25523 flags
|= EF_ARM_MAVERICK_FLOAT
;
25526 case EF_ARM_EABI_VER4
:
25527 case EF_ARM_EABI_VER5
:
25528 /* No additional flags to set. */
25535 bfd_set_private_flags (stdoutput
, flags
);
25537 /* We have run out flags in the COFF header to encode the
25538 status of ATPCS support, so instead we create a dummy,
25539 empty, debug section called .arm.atpcs. */
25544 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
25548 bfd_set_section_flags
25549 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
25550 bfd_set_section_size (stdoutput
, sec
, 0);
25551 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
25557 /* Record the CPU type as well. */
25558 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
25559 mach
= bfd_mach_arm_iWMMXt2
;
25560 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
25561 mach
= bfd_mach_arm_iWMMXt
;
25562 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
25563 mach
= bfd_mach_arm_XScale
;
25564 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
25565 mach
= bfd_mach_arm_ep9312
;
25566 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
25567 mach
= bfd_mach_arm_5TE
;
25568 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
25570 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25571 mach
= bfd_mach_arm_5T
;
25573 mach
= bfd_mach_arm_5
;
25575 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
25577 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25578 mach
= bfd_mach_arm_4T
;
25580 mach
= bfd_mach_arm_4
;
25582 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
25583 mach
= bfd_mach_arm_3M
;
25584 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
25585 mach
= bfd_mach_arm_3
;
25586 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
25587 mach
= bfd_mach_arm_2a
;
25588 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
25589 mach
= bfd_mach_arm_2
;
25591 mach
= bfd_mach_arm_unknown
;
25593 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
25596 /* Command line processing. */
25599 Invocation line includes a switch not recognized by the base assembler.
25600 See if it's a processor-specific option.
25602 This routine is somewhat complicated by the need for backwards
25603 compatibility (since older releases of gcc can't be changed).
25604 The new options try to make the interface as compatible as
25607 New options (supported) are:
25609 -mcpu=<cpu name> Assemble for selected processor
25610 -march=<architecture name> Assemble for selected architecture
25611 -mfpu=<fpu architecture> Assemble for selected FPU.
25612 -EB/-mbig-endian Big-endian
25613 -EL/-mlittle-endian Little-endian
25614 -k Generate PIC code
25615 -mthumb Start in Thumb mode
25616 -mthumb-interwork Code supports ARM/Thumb interworking
25618 -m[no-]warn-deprecated Warn about deprecated features
25619 -m[no-]warn-syms Warn when symbols match instructions
25621 For now we will also provide support for:
25623 -mapcs-32 32-bit Program counter
25624 -mapcs-26 26-bit Program counter
25625 -macps-float Floats passed in FP registers
25626 -mapcs-reentrant Reentrant code
25628 (sometime these will probably be replaced with -mapcs=<list of options>
25629 and -matpcs=<list of options>)
25631 The remaining options are only supported for back-wards compatibility.
25632 Cpu variants, the arm part is optional:
25633 -m[arm]1 Currently not supported.
25634 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25635 -m[arm]3 Arm 3 processor
25636 -m[arm]6[xx], Arm 6 processors
25637 -m[arm]7[xx][t][[d]m] Arm 7 processors
25638 -m[arm]8[10] Arm 8 processors
25639 -m[arm]9[20][tdmi] Arm 9 processors
25640 -mstrongarm[110[0]] StrongARM processors
25641 -mxscale XScale processors
25642 -m[arm]v[2345[t[e]]] Arm architectures
25643 -mall All (except the ARM1)
25645 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25646 -mfpe-old (No float load/store multiples)
25647 -mvfpxd VFP Single precision
25649 -mno-fpu Disable all floating point instructions
25651 The following CPU names are recognized:
25652 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25653 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25654 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25655 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25656 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25657 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25658 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25662 const char * md_shortopts
= "m:k";
25664 #ifdef ARM_BI_ENDIAN
25665 #define OPTION_EB (OPTION_MD_BASE + 0)
25666 #define OPTION_EL (OPTION_MD_BASE + 1)
25668 #if TARGET_BYTES_BIG_ENDIAN
25669 #define OPTION_EB (OPTION_MD_BASE + 0)
25671 #define OPTION_EL (OPTION_MD_BASE + 1)
25674 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25675 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
25677 struct option md_longopts
[] =
25680 {"EB", no_argument
, NULL
, OPTION_EB
},
25683 {"EL", no_argument
, NULL
, OPTION_EL
},
25685 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25687 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
25689 {NULL
, no_argument
, NULL
, 0}
25692 size_t md_longopts_size
= sizeof (md_longopts
);
25694 struct arm_option_table
25696 const char * option
; /* Option name to match. */
25697 const char * help
; /* Help information. */
25698 int * var
; /* Variable to change. */
25699 int value
; /* What to change it to. */
25700 const char * deprecated
; /* If non-null, print this message. */
25703 struct arm_option_table arm_opts
[] =
25705 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25706 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25707 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25708 &support_interwork
, 1, NULL
},
25709 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25710 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25711 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25713 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25714 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25715 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25716 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25719 /* These are recognized by the assembler, but have no affect on code. */
25720 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25721 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25723 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25724 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25725 &warn_on_deprecated
, 0, NULL
},
25726 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25727 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25728 {NULL
, NULL
, NULL
, 0, NULL
}
25731 struct arm_legacy_option_table
25733 const char * option
; /* Option name to match. */
25734 const arm_feature_set
** var
; /* Variable to change. */
25735 const arm_feature_set value
; /* What to change it to. */
25736 const char * deprecated
; /* If non-null, print this message. */
25739 const struct arm_legacy_option_table arm_legacy_opts
[] =
25741 /* DON'T add any new processors to this list -- we want the whole list
25742 to go away... Add them to the processors table instead. */
25743 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25744 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25745 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25746 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25747 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25748 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25749 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25750 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25751 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25752 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25753 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25754 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25755 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25756 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25757 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25758 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25759 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25760 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25761 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25762 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25763 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25764 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25765 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25766 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25767 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25768 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25769 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25770 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25771 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25772 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25773 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25774 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25775 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25776 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25777 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25778 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25779 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25780 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25781 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25782 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25783 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25784 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25785 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25786 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25787 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25788 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25789 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25790 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25791 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25792 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25793 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25794 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25795 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25796 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25797 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25798 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25799 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25800 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25801 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25802 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25803 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25804 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25805 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25806 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25807 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25808 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25809 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25810 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25811 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25812 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25813 N_("use -mcpu=strongarm110")},
25814 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25815 N_("use -mcpu=strongarm1100")},
25816 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25817 N_("use -mcpu=strongarm1110")},
25818 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25819 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25820 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25822 /* Architecture variants -- don't add any more to this list either. */
25823 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25824 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25825 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25826 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25827 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25828 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25829 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25830 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25831 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25832 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25833 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25834 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25835 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25836 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25837 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25838 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25839 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25840 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25842 /* Floating point variants -- don't add any more to this list either. */
25843 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25844 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25845 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25846 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25847 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25849 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25852 struct arm_cpu_option_table
25856 const arm_feature_set value
;
25857 const arm_feature_set ext
;
25858 /* For some CPUs we assume an FPU unless the user explicitly sets
25860 const arm_feature_set default_fpu
;
25861 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25863 const char * canonical_name
;
25866 /* This list should, at a minimum, contain all the cpu names
25867 recognized by GCC. */
25868 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
25870 static const struct arm_cpu_option_table arm_cpus
[] =
25872 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
25875 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
25878 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
25881 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
25884 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
25887 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
25890 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
25893 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
25896 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
25899 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
25902 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
25905 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
25908 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
25911 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
25914 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
25917 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
25920 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
25923 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
25926 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
25929 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
25932 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
25935 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
25938 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
25941 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
25944 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
25947 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
25950 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
25953 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
25956 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
25959 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
25962 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
25965 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
25968 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
25971 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
25974 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
25977 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
25980 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
25983 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
25986 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
25989 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
25992 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
25995 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
25998 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
26001 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
26004 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
26007 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
26011 /* For V5 or later processors we default to using VFP; but the user
26012 should really set the FPU type explicitly. */
26013 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
26016 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
26019 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
26022 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
26025 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
26028 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
26031 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
26034 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
26037 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
26040 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
26043 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
26046 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
26049 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
26052 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
26055 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
26058 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
26061 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
26064 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
26067 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
26070 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
26073 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
26076 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
26079 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
26082 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
26085 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
26088 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
26091 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
26094 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
26097 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
26100 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
26103 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
26106 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
26109 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
26112 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
26115 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
26118 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
26121 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
26122 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26124 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
26126 FPU_ARCH_NEON_VFP_V4
),
26127 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
26128 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26129 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26130 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
26131 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26132 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26133 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
26135 FPU_ARCH_NEON_VFP_V4
),
26136 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
26138 FPU_ARCH_NEON_VFP_V4
),
26139 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
26141 FPU_ARCH_NEON_VFP_V4
),
26142 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
26143 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26144 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26145 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
26146 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26147 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26148 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
26149 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26150 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26151 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
26152 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26153 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26154 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
26155 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26156 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26157 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
26158 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26159 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26160 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
26161 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26162 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26163 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
26164 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26165 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26166 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
26167 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26168 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26169 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
26172 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
26174 FPU_ARCH_VFP_V3D16
),
26175 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
26176 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26178 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
26179 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26180 FPU_ARCH_VFP_V3D16
),
26181 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
26182 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26183 FPU_ARCH_VFP_V3D16
),
26184 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
26185 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26186 FPU_ARCH_NEON_VFP_ARMV8
),
26187 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
26188 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26190 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
26193 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
26196 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
26199 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
26202 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
26205 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
26208 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
26211 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
26212 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26213 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26215 /* ??? XSCALE is really an architecture. */
26216 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
26220 /* ??? iwmmxt is not a processor. */
26221 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
26224 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
26227 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
26232 ARM_CPU_OPT ("ep9312", "ARM920T",
26233 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
26234 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
26236 /* Marvell processors. */
26237 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
26238 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26239 FPU_ARCH_VFP_V3D16
),
26240 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
26241 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26242 FPU_ARCH_NEON_VFP_V4
),
26244 /* APM X-Gene family. */
26245 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
26247 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26248 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
26249 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26250 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26252 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
26256 struct arm_arch_option_table
26260 const arm_feature_set value
;
26261 const arm_feature_set default_fpu
;
26264 /* This list should, at a minimum, contain all the architecture names
26265 recognized by GCC. */
26266 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
26268 static const struct arm_arch_option_table arm_archs
[] =
26270 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
26271 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
26272 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
26273 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
26274 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
26275 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
26276 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
26277 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
26278 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
26279 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
26280 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
26281 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
26282 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
26283 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
26284 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
26285 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
26286 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
26287 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
26288 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
26289 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
26290 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
26291 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
26292 kept to preserve existing behaviour. */
26293 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
26294 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
26295 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
26296 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
26297 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
26298 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
26299 kept to preserve existing behaviour. */
26300 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
26301 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
26302 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
26303 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
26304 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
26305 /* The official spelling of the ARMv7 profile variants is the dashed form.
26306 Accept the non-dashed form for compatibility with old toolchains. */
26307 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
26308 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
26309 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
26310 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26311 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
26312 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
26313 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26314 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
26315 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
26316 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
26317 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
26318 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
26319 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
26320 ARM_ARCH_OPT ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
),
26321 ARM_ARCH_OPT ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
),
26322 ARM_ARCH_OPT ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
),
26323 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
26324 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
26325 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
26326 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26328 #undef ARM_ARCH_OPT
26330 /* ISA extensions in the co-processor and main instruction set space. */
26332 struct arm_option_extension_value_table
26336 const arm_feature_set merge_value
;
26337 const arm_feature_set clear_value
;
26338 /* List of architectures for which an extension is available. ARM_ARCH_NONE
26339 indicates that an extension is available for all architectures while
26340 ARM_ANY marks an empty entry. */
26341 const arm_feature_set allowed_archs
[2];
26344 /* The following table must be in alphabetical order with a NULL last entry. */
26346 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
26347 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
26349 static const struct arm_option_extension_value_table arm_extensions
[] =
26351 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26352 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26353 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
26354 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
26355 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26356 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
26357 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
26359 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26360 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26361 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
26362 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
26363 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26364 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26365 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26367 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
26368 | ARM_EXT2_FP16_FML
),
26369 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
26370 | ARM_EXT2_FP16_FML
),
26372 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26373 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26374 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
26375 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
26376 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
26377 Thumb divide instruction. Due to this having the same name as the
26378 previous entry, this will be ignored when doing command-line parsing and
26379 only considered by build attribute selection code. */
26380 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
26381 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
26382 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
26383 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
26384 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
26385 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
26386 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
26387 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
26388 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
26389 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
26390 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
26391 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
26392 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
26393 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
26394 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
26395 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
26396 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
26397 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
26398 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26399 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
26400 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
26401 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26402 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
26403 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
26404 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26405 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26406 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26407 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
26408 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26409 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
26410 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
26411 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26412 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
26414 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
26415 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26416 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
26417 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
26418 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
26422 /* ISA floating-point and Advanced SIMD extensions. */
26423 struct arm_option_fpu_value_table
26426 const arm_feature_set value
;
26429 /* This list should, at a minimum, contain all the fpu names
26430 recognized by GCC. */
26431 static const struct arm_option_fpu_value_table arm_fpus
[] =
26433 {"softfpa", FPU_NONE
},
26434 {"fpe", FPU_ARCH_FPE
},
26435 {"fpe2", FPU_ARCH_FPE
},
26436 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
26437 {"fpa", FPU_ARCH_FPA
},
26438 {"fpa10", FPU_ARCH_FPA
},
26439 {"fpa11", FPU_ARCH_FPA
},
26440 {"arm7500fe", FPU_ARCH_FPA
},
26441 {"softvfp", FPU_ARCH_VFP
},
26442 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
26443 {"vfp", FPU_ARCH_VFP_V2
},
26444 {"vfp9", FPU_ARCH_VFP_V2
},
26445 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
26446 {"vfp10", FPU_ARCH_VFP_V2
},
26447 {"vfp10-r0", FPU_ARCH_VFP_V1
},
26448 {"vfpxd", FPU_ARCH_VFP_V1xD
},
26449 {"vfpv2", FPU_ARCH_VFP_V2
},
26450 {"vfpv3", FPU_ARCH_VFP_V3
},
26451 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
26452 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
26453 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
26454 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
26455 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
26456 {"arm1020t", FPU_ARCH_VFP_V1
},
26457 {"arm1020e", FPU_ARCH_VFP_V2
},
26458 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
26459 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
26460 {"maverick", FPU_ARCH_MAVERICK
},
26461 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26462 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26463 {"neon-fp16", FPU_ARCH_NEON_FP16
},
26464 {"vfpv4", FPU_ARCH_VFP_V4
},
26465 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
26466 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
26467 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
26468 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
26469 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
26470 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
26471 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
26472 {"crypto-neon-fp-armv8",
26473 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
26474 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
26475 {"crypto-neon-fp-armv8.1",
26476 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
26477 {NULL
, ARM_ARCH_NONE
}
26480 struct arm_option_value_table
26486 static const struct arm_option_value_table arm_float_abis
[] =
26488 {"hard", ARM_FLOAT_ABI_HARD
},
26489 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
26490 {"soft", ARM_FLOAT_ABI_SOFT
},
26495 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
26496 static const struct arm_option_value_table arm_eabis
[] =
26498 {"gnu", EF_ARM_EABI_UNKNOWN
},
26499 {"4", EF_ARM_EABI_VER4
},
26500 {"5", EF_ARM_EABI_VER5
},
26505 struct arm_long_option_table
26507 const char * option
; /* Substring to match. */
26508 const char * help
; /* Help information. */
26509 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
26510 const char * deprecated
; /* If non-null, print this message. */
26514 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
26515 arm_feature_set
*ext_set
)
26517 /* We insist on extensions being specified in alphabetical order, and with
26518 extensions being added before being removed. We achieve this by having
26519 the global ARM_EXTENSIONS table in alphabetical order, and using the
26520 ADDING_VALUE variable to indicate whether we are adding an extension (1)
26521 or removing it (0) and only allowing it to change in the order
26523 const struct arm_option_extension_value_table
* opt
= NULL
;
26524 const arm_feature_set arm_any
= ARM_ANY
;
26525 int adding_value
= -1;
26527 while (str
!= NULL
&& *str
!= 0)
26534 as_bad (_("invalid architectural extension"));
26539 ext
= strchr (str
, '+');
26544 len
= strlen (str
);
26546 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
26548 if (adding_value
!= 0)
26551 opt
= arm_extensions
;
26559 if (adding_value
== -1)
26562 opt
= arm_extensions
;
26564 else if (adding_value
!= 1)
26566 as_bad (_("must specify extensions to add before specifying "
26567 "those to remove"));
26574 as_bad (_("missing architectural extension"));
26578 gas_assert (adding_value
!= -1);
26579 gas_assert (opt
!= NULL
);
26581 /* Scan over the options table trying to find an exact match. */
26582 for (; opt
->name
!= NULL
; opt
++)
26583 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26585 int i
, nb_allowed_archs
=
26586 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
26587 /* Check we can apply the extension to this architecture. */
26588 for (i
= 0; i
< nb_allowed_archs
; i
++)
26591 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26593 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
26596 if (i
== nb_allowed_archs
)
26598 as_bad (_("extension does not apply to the base architecture"));
26602 /* Add or remove the extension. */
26604 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
26606 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
26608 /* Allowing Thumb division instructions for ARMv7 in autodetection
26609 rely on this break so that duplicate extensions (extensions
26610 with the same name as a previous extension in the list) are not
26611 considered for command-line parsing. */
26615 if (opt
->name
== NULL
)
26617 /* Did we fail to find an extension because it wasn't specified in
26618 alphabetical order, or because it does not exist? */
26620 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26621 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26624 if (opt
->name
== NULL
)
26625 as_bad (_("unknown architectural extension `%s'"), str
);
26627 as_bad (_("architectural extensions must be specified in "
26628 "alphabetical order"));
26634 /* We should skip the extension we've just matched the next time
26646 arm_parse_cpu (const char *str
)
26648 const struct arm_cpu_option_table
*opt
;
26649 const char *ext
= strchr (str
, '+');
26655 len
= strlen (str
);
26659 as_bad (_("missing cpu name `%s'"), str
);
26663 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
26664 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26666 mcpu_cpu_opt
= &opt
->value
;
26667 if (mcpu_ext_opt
== NULL
)
26668 mcpu_ext_opt
= XNEW (arm_feature_set
);
26669 *mcpu_ext_opt
= opt
->ext
;
26670 mcpu_fpu_opt
= &opt
->default_fpu
;
26671 if (opt
->canonical_name
)
26673 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
26674 strcpy (selected_cpu_name
, opt
->canonical_name
);
26680 if (len
>= sizeof selected_cpu_name
)
26681 len
= (sizeof selected_cpu_name
) - 1;
26683 for (i
= 0; i
< len
; i
++)
26684 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26685 selected_cpu_name
[i
] = 0;
26689 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
);
26694 as_bad (_("unknown cpu `%s'"), str
);
26699 arm_parse_arch (const char *str
)
26701 const struct arm_arch_option_table
*opt
;
26702 const char *ext
= strchr (str
, '+');
26708 len
= strlen (str
);
26712 as_bad (_("missing architecture name `%s'"), str
);
26716 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
26717 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26719 march_cpu_opt
= &opt
->value
;
26720 if (march_ext_opt
== NULL
)
26721 march_ext_opt
= XNEW (arm_feature_set
);
26722 *march_ext_opt
= arm_arch_none
;
26723 march_fpu_opt
= &opt
->default_fpu
;
26724 strcpy (selected_cpu_name
, opt
->name
);
26727 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
);
26732 as_bad (_("unknown architecture `%s'\n"), str
);
26737 arm_parse_fpu (const char * str
)
26739 const struct arm_option_fpu_value_table
* opt
;
26741 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26742 if (streq (opt
->name
, str
))
26744 mfpu_opt
= &opt
->value
;
26748 as_bad (_("unknown floating point format `%s'\n"), str
);
26753 arm_parse_float_abi (const char * str
)
26755 const struct arm_option_value_table
* opt
;
26757 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
26758 if (streq (opt
->name
, str
))
26760 mfloat_abi_opt
= opt
->value
;
26764 as_bad (_("unknown floating point abi `%s'\n"), str
);
26770 arm_parse_eabi (const char * str
)
26772 const struct arm_option_value_table
*opt
;
26774 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
26775 if (streq (opt
->name
, str
))
26777 meabi_flags
= opt
->value
;
26780 as_bad (_("unknown EABI `%s'\n"), str
);
26786 arm_parse_it_mode (const char * str
)
26788 bfd_boolean ret
= TRUE
;
26790 if (streq ("arm", str
))
26791 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
26792 else if (streq ("thumb", str
))
26793 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
26794 else if (streq ("always", str
))
26795 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
26796 else if (streq ("never", str
))
26797 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
26800 as_bad (_("unknown implicit IT mode `%s', should be "\
26801 "arm, thumb, always, or never."), str
);
26809 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
26811 codecomposer_syntax
= TRUE
;
26812 arm_comment_chars
[0] = ';';
26813 arm_line_separator_chars
[0] = 0;
26817 struct arm_long_option_table arm_long_opts
[] =
26819 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
26820 arm_parse_cpu
, NULL
},
26821 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
26822 arm_parse_arch
, NULL
},
26823 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
26824 arm_parse_fpu
, NULL
},
26825 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
26826 arm_parse_float_abi
, NULL
},
26828 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
26829 arm_parse_eabi
, NULL
},
26831 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
26832 arm_parse_it_mode
, NULL
},
26833 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
26834 arm_ccs_mode
, NULL
},
26835 {NULL
, NULL
, 0, NULL
}
26839 md_parse_option (int c
, const char * arg
)
26841 struct arm_option_table
*opt
;
26842 const struct arm_legacy_option_table
*fopt
;
26843 struct arm_long_option_table
*lopt
;
26849 target_big_endian
= 1;
26855 target_big_endian
= 0;
26859 case OPTION_FIX_V4BX
:
26867 #endif /* OBJ_ELF */
26870 /* Listing option. Just ignore these, we don't support additional
26875 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26877 if (c
== opt
->option
[0]
26878 && ((arg
== NULL
&& opt
->option
[1] == 0)
26879 || streq (arg
, opt
->option
+ 1)))
26881 /* If the option is deprecated, tell the user. */
26882 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
26883 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26884 arg
? arg
: "", _(opt
->deprecated
));
26886 if (opt
->var
!= NULL
)
26887 *opt
->var
= opt
->value
;
26893 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
26895 if (c
== fopt
->option
[0]
26896 && ((arg
== NULL
&& fopt
->option
[1] == 0)
26897 || streq (arg
, fopt
->option
+ 1)))
26899 /* If the option is deprecated, tell the user. */
26900 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
26901 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26902 arg
? arg
: "", _(fopt
->deprecated
));
26904 if (fopt
->var
!= NULL
)
26905 *fopt
->var
= &fopt
->value
;
26911 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26913 /* These options are expected to have an argument. */
26914 if (c
== lopt
->option
[0]
26916 && strncmp (arg
, lopt
->option
+ 1,
26917 strlen (lopt
->option
+ 1)) == 0)
26919 /* If the option is deprecated, tell the user. */
26920 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
26921 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
26922 _(lopt
->deprecated
));
26924 /* Call the sup-option parser. */
26925 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
26936 md_show_usage (FILE * fp
)
26938 struct arm_option_table
*opt
;
26939 struct arm_long_option_table
*lopt
;
26941 fprintf (fp
, _(" ARM-specific assembler options:\n"));
26943 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26944 if (opt
->help
!= NULL
)
26945 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
26947 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26948 if (lopt
->help
!= NULL
)
26949 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
26953 -EB assemble code for a big-endian cpu\n"));
26958 -EL assemble code for a little-endian cpu\n"));
26962 --fix-v4bx Allow BX in ARMv4 code\n"));
26966 --fdpic generate an FDPIC object file\n"));
26967 #endif /* OBJ_ELF */
26975 arm_feature_set flags
;
26976 } cpu_arch_ver_table
;
26978 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
26979 chronologically for architectures, with an exception for ARMv6-M and
26980 ARMv6S-M due to legacy reasons. No new architecture should have a
26981 special case. This allows for build attribute selection results to be
26982 stable when new architectures are added. */
26983 static const cpu_arch_ver_table cpu_arch_ver
[] =
26990 {1, ARM_ARCH_V4xM
},
26992 {2, ARM_ARCH_V4TxM
},
26994 {3, ARM_ARCH_V5xM
},
26996 {3, ARM_ARCH_V5TxM
},
26998 {4, ARM_ARCH_V5TExP
},
26999 {4, ARM_ARCH_V5TE
},
27000 {5, ARM_ARCH_V5TEJ
},
27003 {7, ARM_ARCH_V6KZ
},
27005 {8, ARM_ARCH_V6T2
},
27006 {8, ARM_ARCH_V6KT2
},
27007 {8, ARM_ARCH_V6ZT2
},
27008 {8, ARM_ARCH_V6KZT2
},
27010 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
27011 always selected build attributes to match those of ARMv6-M
27012 (resp. ARMv6S-M). However, due to these architectures being a strict
27013 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
27014 would be selected when fully respecting chronology of architectures.
27015 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
27016 move them before ARMv7 architectures. */
27017 {11, ARM_ARCH_V6M
},
27018 {12, ARM_ARCH_V6SM
},
27021 {10, ARM_ARCH_V7A
},
27022 {10, ARM_ARCH_V7R
},
27023 {10, ARM_ARCH_V7M
},
27024 {10, ARM_ARCH_V7VE
},
27025 {13, ARM_ARCH_V7EM
},
27026 {14, ARM_ARCH_V8A
},
27027 {14, ARM_ARCH_V8_1A
},
27028 {14, ARM_ARCH_V8_2A
},
27029 {14, ARM_ARCH_V8_3A
},
27030 {16, ARM_ARCH_V8M_BASE
},
27031 {17, ARM_ARCH_V8M_MAIN
},
27032 {15, ARM_ARCH_V8R
},
27033 {14, ARM_ARCH_V8_4A
},
27034 {-1, ARM_ARCH_NONE
}
27037 /* Set an attribute if it has not already been set by the user. */
27040 aeabi_set_attribute_int (int tag
, int value
)
27043 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
27044 || !attributes_set_explicitly
[tag
])
27045 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
27049 aeabi_set_attribute_string (int tag
, const char *value
)
27052 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
27053 || !attributes_set_explicitly
[tag
])
27054 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
27057 /* Return whether features in the *NEEDED feature set are available via
27058 extensions for the architecture whose feature set is *ARCH_FSET. */
27061 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
27062 const arm_feature_set
*needed
)
27064 int i
, nb_allowed_archs
;
27065 arm_feature_set ext_fset
;
27066 const struct arm_option_extension_value_table
*opt
;
27068 ext_fset
= arm_arch_none
;
27069 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27071 /* Extension does not provide any feature we need. */
27072 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
27076 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
27077 for (i
= 0; i
< nb_allowed_archs
; i
++)
27080 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
27083 /* Extension is available, add it. */
27084 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
27085 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
27089 /* Can we enable all features in *needed? */
27090 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
27093 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
27094 a given architecture feature set *ARCH_EXT_FSET including extension feature
27095 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
27096 - if true, check for an exact match of the architecture modulo extensions;
27097 - otherwise, select build attribute value of the first superset
27098 architecture released so that results remains stable when new architectures
27100 For -march/-mcpu=all the build attribute value of the most featureful
27101 architecture is returned. Tag_CPU_arch_profile result is returned in
27105 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
27106 const arm_feature_set
*ext_fset
,
27107 char *profile
, int exact_match
)
27109 arm_feature_set arch_fset
;
27110 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
27112 /* Select most featureful architecture with all its extensions if building
27113 for -march=all as the feature sets used to set build attributes. */
27114 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
27116 /* Force revisiting of decision for each new architecture. */
27117 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8M_MAIN
);
27119 return TAG_CPU_ARCH_V8
;
27122 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
27124 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
27126 arm_feature_set known_arch_fset
;
27128 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
27131 /* Base architecture match user-specified architecture and
27132 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
27133 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
27138 /* Base architecture match user-specified architecture only
27139 (eg. ARMv6-M in the same case as above). Record it in case we
27140 find a match with above condition. */
27141 else if (p_ver_ret
== NULL
27142 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
27148 /* Architecture has all features wanted. */
27149 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
27151 arm_feature_set added_fset
;
27153 /* Compute features added by this architecture over the one
27154 recorded in p_ver_ret. */
27155 if (p_ver_ret
!= NULL
)
27156 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
27158 /* First architecture that match incl. with extensions, or the
27159 only difference in features over the recorded match is
27160 features that were optional and are now mandatory. */
27161 if (p_ver_ret
== NULL
27162 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
27168 else if (p_ver_ret
== NULL
)
27170 arm_feature_set needed_ext_fset
;
27172 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
27174 /* Architecture has all features needed when using some
27175 extensions. Record it and continue searching in case there
27176 exist an architecture providing all needed features without
27177 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
27179 if (have_ext_for_needed_feat_p (&known_arch_fset
,
27186 if (p_ver_ret
== NULL
)
27190 /* Tag_CPU_arch_profile. */
27191 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
27192 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
27193 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
27194 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
27196 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
27198 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
27202 return p_ver_ret
->val
;
27205 /* Set the public EABI object attributes. */
27208 aeabi_set_public_attributes (void)
27210 char profile
= '\0';
27213 int fp16_optional
= 0;
27214 int skip_exact_match
= 0;
27215 arm_feature_set flags
, flags_arch
, flags_ext
;
27217 /* Autodetection mode, choose the architecture based the instructions
27219 if (no_cpu_selected ())
27221 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
27223 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
27224 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
27226 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
27227 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
27229 /* Code run during relaxation relies on selected_cpu being set. */
27230 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
27231 flags_ext
= arm_arch_none
;
27232 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
27233 selected_ext
= flags_ext
;
27234 selected_cpu
= flags
;
27236 /* Otherwise, choose the architecture based on the capabilities of the
27240 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
27241 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
27242 flags_ext
= selected_ext
;
27243 flags
= selected_cpu
;
27245 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
27247 /* Allow the user to override the reported architecture. */
27248 if (!ARM_FEATURE_ZERO (selected_object_arch
))
27250 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
27251 flags_ext
= arm_arch_none
;
27254 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
27256 /* When this function is run again after relaxation has happened there is no
27257 way to determine whether an architecture or CPU was specified by the user:
27258 - selected_cpu is set above for relaxation to work;
27259 - march_cpu_opt is not set if only -mcpu or .cpu is used;
27260 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
27261 Therefore, if not in -march=all case we first try an exact match and fall
27262 back to autodetection. */
27263 if (!skip_exact_match
)
27264 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
27266 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
27268 as_bad (_("no architecture contains all the instructions used\n"));
27270 /* Tag_CPU_name. */
27271 if (selected_cpu_name
[0])
27275 q
= selected_cpu_name
;
27276 if (strncmp (q
, "armv", 4) == 0)
27281 for (i
= 0; q
[i
]; i
++)
27282 q
[i
] = TOUPPER (q
[i
]);
27284 aeabi_set_attribute_string (Tag_CPU_name
, q
);
27287 /* Tag_CPU_arch. */
27288 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
27290 /* Tag_CPU_arch_profile. */
27291 if (profile
!= '\0')
27292 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
27294 /* Tag_DSP_extension. */
27295 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
27296 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
27298 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
27299 /* Tag_ARM_ISA_use. */
27300 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
27301 || ARM_FEATURE_ZERO (flags_arch
))
27302 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
27304 /* Tag_THUMB_ISA_use. */
27305 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
27306 || ARM_FEATURE_ZERO (flags_arch
))
27310 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
27311 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
27313 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
27317 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
27320 /* Tag_VFP_arch. */
27321 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
27322 aeabi_set_attribute_int (Tag_VFP_arch
,
27323 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
27325 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
27326 aeabi_set_attribute_int (Tag_VFP_arch
,
27327 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
27329 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
27332 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
27334 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
27336 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
27339 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
27340 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
27341 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
27342 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
27343 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
27345 /* Tag_ABI_HardFP_use. */
27346 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
27347 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
27348 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
27350 /* Tag_WMMX_arch. */
27351 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
27352 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
27353 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
27354 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
27356 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
27357 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
27358 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
27359 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
27360 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
27361 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
27363 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
27365 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
27369 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
27374 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
27375 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
27376 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
27380 We set Tag_DIV_use to two when integer divide instructions have been used
27381 in ARM state, or when Thumb integer divide instructions have been used,
27382 but we have no architecture profile set, nor have we any ARM instructions.
27384 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
27385 by the base architecture.
27387 For new architectures we will have to check these tests. */
27388 gas_assert (arch
<= TAG_CPU_ARCH_V8M_MAIN
);
27389 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
27390 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
27391 aeabi_set_attribute_int (Tag_DIV_use
, 0);
27392 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
27393 || (profile
== '\0'
27394 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
27395 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
27396 aeabi_set_attribute_int (Tag_DIV_use
, 2);
27398 /* Tag_MP_extension_use. */
27399 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
27400 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
27402 /* Tag Virtualization_use. */
27403 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
27405 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
27408 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
27411 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
27412 finished and free extension feature bits which will not be used anymore. */
27415 arm_md_post_relax (void)
27417 aeabi_set_public_attributes ();
27418 XDELETE (mcpu_ext_opt
);
27419 mcpu_ext_opt
= NULL
;
27420 XDELETE (march_ext_opt
);
27421 march_ext_opt
= NULL
;
27424 /* Add the default contents for the .ARM.attributes section. */
27429 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
27432 aeabi_set_public_attributes ();
27434 #endif /* OBJ_ELF */
27436 /* Parse a .cpu directive. */
27439 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
27441 const struct arm_cpu_option_table
*opt
;
27445 name
= input_line_pointer
;
27446 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27447 input_line_pointer
++;
27448 saved_char
= *input_line_pointer
;
27449 *input_line_pointer
= 0;
27451 /* Skip the first "all" entry. */
27452 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
27453 if (streq (opt
->name
, name
))
27455 selected_arch
= opt
->value
;
27456 selected_ext
= opt
->ext
;
27457 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
27458 if (opt
->canonical_name
)
27459 strcpy (selected_cpu_name
, opt
->canonical_name
);
27463 for (i
= 0; opt
->name
[i
]; i
++)
27464 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
27466 selected_cpu_name
[i
] = 0;
27468 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
27470 *input_line_pointer
= saved_char
;
27471 demand_empty_rest_of_line ();
27474 as_bad (_("unknown cpu `%s'"), name
);
27475 *input_line_pointer
= saved_char
;
27476 ignore_rest_of_line ();
27479 /* Parse a .arch directive. */
27482 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
27484 const struct arm_arch_option_table
*opt
;
27488 name
= input_line_pointer
;
27489 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27490 input_line_pointer
++;
27491 saved_char
= *input_line_pointer
;
27492 *input_line_pointer
= 0;
27494 /* Skip the first "all" entry. */
27495 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27496 if (streq (opt
->name
, name
))
27498 selected_arch
= opt
->value
;
27499 selected_ext
= arm_arch_none
;
27500 selected_cpu
= selected_arch
;
27501 strcpy (selected_cpu_name
, opt
->name
);
27502 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
27503 *input_line_pointer
= saved_char
;
27504 demand_empty_rest_of_line ();
27508 as_bad (_("unknown architecture `%s'\n"), name
);
27509 *input_line_pointer
= saved_char
;
27510 ignore_rest_of_line ();
27513 /* Parse a .object_arch directive. */
27516 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
27518 const struct arm_arch_option_table
*opt
;
27522 name
= input_line_pointer
;
27523 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27524 input_line_pointer
++;
27525 saved_char
= *input_line_pointer
;
27526 *input_line_pointer
= 0;
27528 /* Skip the first "all" entry. */
27529 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27530 if (streq (opt
->name
, name
))
27532 selected_object_arch
= opt
->value
;
27533 *input_line_pointer
= saved_char
;
27534 demand_empty_rest_of_line ();
27538 as_bad (_("unknown architecture `%s'\n"), name
);
27539 *input_line_pointer
= saved_char
;
27540 ignore_rest_of_line ();
27543 /* Parse a .arch_extension directive. */
27546 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
27548 const struct arm_option_extension_value_table
*opt
;
27551 int adding_value
= 1;
27553 name
= input_line_pointer
;
27554 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27555 input_line_pointer
++;
27556 saved_char
= *input_line_pointer
;
27557 *input_line_pointer
= 0;
27559 if (strlen (name
) >= 2
27560 && strncmp (name
, "no", 2) == 0)
27566 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27567 if (streq (opt
->name
, name
))
27569 int i
, nb_allowed_archs
=
27570 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
27571 for (i
= 0; i
< nb_allowed_archs
; i
++)
27574 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
27576 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
27580 if (i
== nb_allowed_archs
)
27582 as_bad (_("architectural extension `%s' is not allowed for the "
27583 "current base architecture"), name
);
27588 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
27591 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
27593 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
27594 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
27595 *input_line_pointer
= saved_char
;
27596 demand_empty_rest_of_line ();
27597 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
27598 on this return so that duplicate extensions (extensions with the
27599 same name as a previous extension in the list) are not considered
27600 for command-line parsing. */
27604 if (opt
->name
== NULL
)
27605 as_bad (_("unknown architecture extension `%s'\n"), name
);
27607 *input_line_pointer
= saved_char
;
27608 ignore_rest_of_line ();
27611 /* Parse a .fpu directive. */
27614 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
27616 const struct arm_option_fpu_value_table
*opt
;
27620 name
= input_line_pointer
;
27621 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27622 input_line_pointer
++;
27623 saved_char
= *input_line_pointer
;
27624 *input_line_pointer
= 0;
27626 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
27627 if (streq (opt
->name
, name
))
27629 selected_fpu
= opt
->value
;
27630 #ifndef CPU_DEFAULT
27631 if (no_cpu_selected ())
27632 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
27635 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
27636 *input_line_pointer
= saved_char
;
27637 demand_empty_rest_of_line ();
27641 as_bad (_("unknown floating point format `%s'\n"), name
);
27642 *input_line_pointer
= saved_char
;
27643 ignore_rest_of_line ();
27646 /* Copy symbol information. */
27649 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
27651 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
27655 /* Given a symbolic attribute NAME, return the proper integer value.
27656 Returns -1 if the attribute is not known. */
27659 arm_convert_symbolic_attribute (const char *name
)
27661 static const struct
27666 attribute_table
[] =
27668 /* When you modify this table you should
27669 also modify the list in doc/c-arm.texi. */
27670 #define T(tag) {#tag, tag}
27671 T (Tag_CPU_raw_name
),
27674 T (Tag_CPU_arch_profile
),
27675 T (Tag_ARM_ISA_use
),
27676 T (Tag_THUMB_ISA_use
),
27680 T (Tag_Advanced_SIMD_arch
),
27681 T (Tag_PCS_config
),
27682 T (Tag_ABI_PCS_R9_use
),
27683 T (Tag_ABI_PCS_RW_data
),
27684 T (Tag_ABI_PCS_RO_data
),
27685 T (Tag_ABI_PCS_GOT_use
),
27686 T (Tag_ABI_PCS_wchar_t
),
27687 T (Tag_ABI_FP_rounding
),
27688 T (Tag_ABI_FP_denormal
),
27689 T (Tag_ABI_FP_exceptions
),
27690 T (Tag_ABI_FP_user_exceptions
),
27691 T (Tag_ABI_FP_number_model
),
27692 T (Tag_ABI_align_needed
),
27693 T (Tag_ABI_align8_needed
),
27694 T (Tag_ABI_align_preserved
),
27695 T (Tag_ABI_align8_preserved
),
27696 T (Tag_ABI_enum_size
),
27697 T (Tag_ABI_HardFP_use
),
27698 T (Tag_ABI_VFP_args
),
27699 T (Tag_ABI_WMMX_args
),
27700 T (Tag_ABI_optimization_goals
),
27701 T (Tag_ABI_FP_optimization_goals
),
27702 T (Tag_compatibility
),
27703 T (Tag_CPU_unaligned_access
),
27704 T (Tag_FP_HP_extension
),
27705 T (Tag_VFP_HP_extension
),
27706 T (Tag_ABI_FP_16bit_format
),
27707 T (Tag_MPextension_use
),
27709 T (Tag_nodefaults
),
27710 T (Tag_also_compatible_with
),
27711 T (Tag_conformance
),
27713 T (Tag_Virtualization_use
),
27714 T (Tag_DSP_extension
),
27715 /* We deliberately do not include Tag_MPextension_use_legacy. */
27723 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
27724 if (streq (name
, attribute_table
[i
].name
))
27725 return attribute_table
[i
].tag
;
27730 /* Apply sym value for relocations only in the case that they are for
27731 local symbols in the same segment as the fixup and you have the
27732 respective architectural feature for blx and simple switches. */
27735 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
27738 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27739 /* PR 17444: If the local symbol is in a different section then a reloc
27740 will always be generated for it, so applying the symbol value now
27741 will result in a double offset being stored in the relocation. */
27742 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
27743 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
27745 switch (fixP
->fx_r_type
)
27747 case BFD_RELOC_ARM_PCREL_BLX
:
27748 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27749 if (ARM_IS_FUNC (fixP
->fx_addsy
))
27753 case BFD_RELOC_ARM_PCREL_CALL
:
27754 case BFD_RELOC_THUMB_PCREL_BLX
:
27755 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
27766 #endif /* OBJ_ELF */