1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
305 static const arm_feature_set mve_ext
=
306 ARM_FEATURE_COPROC (FPU_MVE
);
307 static const arm_feature_set mve_fp_ext
=
308 ARM_FEATURE_COPROC (FPU_MVE_FP
);
310 static const arm_feature_set fpu_vfp_fp16
=
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
312 static const arm_feature_set fpu_neon_ext_fma
=
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
315 static const arm_feature_set fpu_vfp_ext_fma
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
317 static const arm_feature_set fpu_vfp_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
319 static const arm_feature_set fpu_vfp_ext_armv8xd
=
320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
321 static const arm_feature_set fpu_neon_ext_armv8
=
322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
323 static const arm_feature_set fpu_crypto_ext_armv8
=
324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
325 static const arm_feature_set crc_ext_armv8
=
326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
327 static const arm_feature_set fpu_neon_ext_v8_1
=
328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
329 static const arm_feature_set fpu_neon_ext_dotprod
=
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
332 static int mfloat_abi_opt
= -1;
333 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
335 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
336 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
338 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
339 /* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
342 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
343 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
344 static arm_feature_set selected_fpu
= FPU_NONE
;
345 /* Feature bits selected by the last .object_arch directive. */
346 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
347 /* Must be long enough to hold any of the names in arm_cpus. */
348 static char selected_cpu_name
[20];
350 extern FLONUM_TYPE generic_floating_point_number
;
352 /* Return if no cpu was selected on command-line. */
354 no_cpu_selected (void)
356 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
361 static int meabi_flags
= EABI_DEFAULT
;
363 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
366 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
371 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
376 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
377 symbolS
* GOT_symbol
;
380 /* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
384 static int thumb_mode
= 0;
385 /* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388 #define MODE_RECORDED (1 << 4)
390 /* Specifies the intrinsic IT insn behavior mode. */
391 enum implicit_it_mode
393 IMPLICIT_IT_MODE_NEVER
= 0x00,
394 IMPLICIT_IT_MODE_ARM
= 0x01,
395 IMPLICIT_IT_MODE_THUMB
= 0x02,
396 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
398 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
400 /* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
412 Important differences from the old Thumb mode:
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
423 static bfd_boolean unified_syntax
= FALSE
;
425 /* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429 const char arm_symbol_chars
[] = "#[]{}";
444 enum neon_el_type type
;
448 #define NEON_MAX_TYPE_ELS 4
452 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
456 enum pred_instruction_type
462 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
463 if inside, should be the last one. */
464 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
465 i.e. BKPT and NOP. */
466 IT_INSN
, /* The IT insn has been parsed. */
467 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
468 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
469 a predication code. */
470 MVE_UNPREDICABLE_INSN
/* MVE instruction that is non-predicable. */
473 /* The maximum number of operands we need. */
474 #define ARM_IT_MAX_OPERANDS 6
475 #define ARM_IT_MAX_RELOCS 3
480 unsigned long instruction
;
484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
488 struct neon_type vectype
;
489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
497 bfd_reloc_code_real_type type
;
500 } relocs
[ARM_IT_MAX_RELOCS
];
502 enum pred_instruction_type pred_insn_type
;
508 struct neon_type_el vectype
;
509 unsigned present
: 1; /* Operand present. */
510 unsigned isreg
: 1; /* Operand was a register. */
511 unsigned immisreg
: 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
513 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
517 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
518 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
522 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
523 unsigned isquad
: 1; /* Operand is SIMD quad register. */
524 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
525 unsigned iszr
: 1; /* Operand is ZR register. */
526 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
527 unsigned writeback
: 1; /* Operand has trailing ! */
528 unsigned preind
: 1; /* Preindexed address. */
529 unsigned postind
: 1; /* Postindexed address. */
530 unsigned negative
: 1; /* Index register was negated. */
531 unsigned shifted
: 1; /* Shift applied to operation. */
532 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
533 } operands
[ARM_IT_MAX_OPERANDS
];
536 static struct arm_it inst
;
538 #define NUM_FLOAT_VALS 8
540 const char * fp_const
[] =
542 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
545 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
555 #define CP_T_X 0x00008000
556 #define CP_T_Y 0x00400000
558 #define CONDS_BIT 0x00100000
559 #define LOAD_BIT 0x00100000
561 #define DOUBLE_LOAD_FLAG 0x00000001
565 const char * template_name
;
569 #define COND_ALWAYS 0xE
573 const char * template_name
;
577 struct asm_barrier_opt
579 const char * template_name
;
581 const arm_feature_set arch
;
584 /* The bit that distinguishes CPSR and SPSR. */
585 #define SPSR_BIT (1 << 22)
587 /* The individual PSR flag bits. */
588 #define PSR_c (1 << 16)
589 #define PSR_x (1 << 17)
590 #define PSR_s (1 << 18)
591 #define PSR_f (1 << 19)
596 bfd_reloc_code_real_type reloc
;
601 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
602 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
607 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
610 /* Bits for DEFINED field in neon_typed_alias. */
611 #define NTA_HASTYPE 1
612 #define NTA_HASINDEX 2
614 struct neon_typed_alias
616 unsigned char defined
;
618 struct neon_type_el eltype
;
621 /* ARM register categories. This includes coprocessor numbers and various
622 architecture extensions' registers. Each entry should have an error message
623 in reg_expected_msgs below. */
653 /* Structure for a hash table entry for a register.
654 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
655 information which states whether a vector type or index is specified (for a
656 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
662 unsigned char builtin
;
663 struct neon_typed_alias
* neon
;
666 /* Diagnostics used when we don't get a register of the expected type. */
667 const char * const reg_expected_msgs
[] =
669 [REG_TYPE_RN
] = N_("ARM register expected"),
670 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
671 [REG_TYPE_CN
] = N_("co-processor register expected"),
672 [REG_TYPE_FN
] = N_("FPA register expected"),
673 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
674 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
675 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
676 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
677 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
678 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
679 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
681 [REG_TYPE_VFC
] = N_("VFP system register expected"),
682 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
683 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
684 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
685 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
686 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
687 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
688 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
689 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
690 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
691 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
692 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
693 [REG_TYPE_RNB
] = N_("")
696 /* Some well known registers that we refer to directly elsewhere. */
702 /* ARM instructions take 4bytes in the object file, Thumb instructions
708 /* Basic string to match. */
709 const char * template_name
;
711 /* Parameters to instruction. */
712 unsigned int operands
[8];
714 /* Conditional tag - see opcode_lookup. */
715 unsigned int tag
: 4;
717 /* Basic instruction code. */
720 /* Thumb-format instruction code. */
723 /* Which architecture variant provides this instruction. */
724 const arm_feature_set
* avariant
;
725 const arm_feature_set
* tvariant
;
727 /* Function to call to encode instruction in ARM format. */
728 void (* aencode
) (void);
730 /* Function to call to encode instruction in Thumb format. */
731 void (* tencode
) (void);
733 /* Indicates whether this instruction may be vector predicated. */
734 unsigned int mayBeVecPred
: 1;
737 /* Defines for various bits that we will want to toggle. */
738 #define INST_IMMEDIATE 0x02000000
739 #define OFFSET_REG 0x02000000
740 #define HWOFFSET_IMM 0x00400000
741 #define SHIFT_BY_REG 0x00000010
742 #define PRE_INDEX 0x01000000
743 #define INDEX_UP 0x00800000
744 #define WRITE_BACK 0x00200000
745 #define LDM_TYPE_2_OR_3 0x00400000
746 #define CPSI_MMOD 0x00020000
748 #define LITERAL_MASK 0xf000f000
749 #define OPCODE_MASK 0xfe1fffff
750 #define V4_STR_BIT 0x00000020
751 #define VLDR_VMOV_SAME 0x0040f000
753 #define T2_SUBS_PC_LR 0xf3de8f00
755 #define DATA_OP_SHIFT 21
756 #define SBIT_SHIFT 20
758 #define T2_OPCODE_MASK 0xfe1fffff
759 #define T2_DATA_OP_SHIFT 21
760 #define T2_SBIT_SHIFT 20
762 #define A_COND_MASK 0xf0000000
763 #define A_PUSH_POP_OP_MASK 0x0fff0000
765 /* Opcodes for pushing/poping registers to/from the stack. */
766 #define A1_OPCODE_PUSH 0x092d0000
767 #define A2_OPCODE_PUSH 0x052d0004
768 #define A2_OPCODE_POP 0x049d0004
770 /* Codes to distinguish the arithmetic instructions. */
781 #define OPCODE_CMP 10
782 #define OPCODE_CMN 11
783 #define OPCODE_ORR 12
784 #define OPCODE_MOV 13
785 #define OPCODE_BIC 14
786 #define OPCODE_MVN 15
788 #define T2_OPCODE_AND 0
789 #define T2_OPCODE_BIC 1
790 #define T2_OPCODE_ORR 2
791 #define T2_OPCODE_ORN 3
792 #define T2_OPCODE_EOR 4
793 #define T2_OPCODE_ADD 8
794 #define T2_OPCODE_ADC 10
795 #define T2_OPCODE_SBC 11
796 #define T2_OPCODE_SUB 13
797 #define T2_OPCODE_RSB 14
799 #define T_OPCODE_MUL 0x4340
800 #define T_OPCODE_TST 0x4200
801 #define T_OPCODE_CMN 0x42c0
802 #define T_OPCODE_NEG 0x4240
803 #define T_OPCODE_MVN 0x43c0
805 #define T_OPCODE_ADD_R3 0x1800
806 #define T_OPCODE_SUB_R3 0x1a00
807 #define T_OPCODE_ADD_HI 0x4400
808 #define T_OPCODE_ADD_ST 0xb000
809 #define T_OPCODE_SUB_ST 0xb080
810 #define T_OPCODE_ADD_SP 0xa800
811 #define T_OPCODE_ADD_PC 0xa000
812 #define T_OPCODE_ADD_I8 0x3000
813 #define T_OPCODE_SUB_I8 0x3800
814 #define T_OPCODE_ADD_I3 0x1c00
815 #define T_OPCODE_SUB_I3 0x1e00
817 #define T_OPCODE_ASR_R 0x4100
818 #define T_OPCODE_LSL_R 0x4080
819 #define T_OPCODE_LSR_R 0x40c0
820 #define T_OPCODE_ROR_R 0x41c0
821 #define T_OPCODE_ASR_I 0x1000
822 #define T_OPCODE_LSL_I 0x0000
823 #define T_OPCODE_LSR_I 0x0800
825 #define T_OPCODE_MOV_I8 0x2000
826 #define T_OPCODE_CMP_I8 0x2800
827 #define T_OPCODE_CMP_LR 0x4280
828 #define T_OPCODE_MOV_HR 0x4600
829 #define T_OPCODE_CMP_HR 0x4500
831 #define T_OPCODE_LDR_PC 0x4800
832 #define T_OPCODE_LDR_SP 0x9800
833 #define T_OPCODE_STR_SP 0x9000
834 #define T_OPCODE_LDR_IW 0x6800
835 #define T_OPCODE_STR_IW 0x6000
836 #define T_OPCODE_LDR_IH 0x8800
837 #define T_OPCODE_STR_IH 0x8000
838 #define T_OPCODE_LDR_IB 0x7800
839 #define T_OPCODE_STR_IB 0x7000
840 #define T_OPCODE_LDR_RW 0x5800
841 #define T_OPCODE_STR_RW 0x5000
842 #define T_OPCODE_LDR_RH 0x5a00
843 #define T_OPCODE_STR_RH 0x5200
844 #define T_OPCODE_LDR_RB 0x5c00
845 #define T_OPCODE_STR_RB 0x5400
847 #define T_OPCODE_PUSH 0xb400
848 #define T_OPCODE_POP 0xbc00
850 #define T_OPCODE_BRANCH 0xe000
852 #define THUMB_SIZE 2 /* Size of thumb instruction. */
853 #define THUMB_PP_PC_LR 0x0100
854 #define THUMB_LOAD_BIT 0x0800
855 #define THUMB2_LOAD_BIT 0x00100000
857 #define BAD_SYNTAX _("syntax error")
858 #define BAD_ARGS _("bad arguments to instruction")
859 #define BAD_SP _("r13 not allowed here")
860 #define BAD_PC _("r15 not allowed here")
861 #define BAD_ODD _("Odd register not allowed here")
862 #define BAD_EVEN _("Even register not allowed here")
863 #define BAD_COND _("instruction cannot be conditional")
864 #define BAD_OVERLAP _("registers may not be the same")
865 #define BAD_HIREG _("lo register required")
866 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
867 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
868 #define BAD_BRANCH _("branch must be last instruction in IT block")
869 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
870 #define BAD_NOT_IT _("instruction not allowed in IT block")
871 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
872 #define BAD_FPU _("selected FPU does not support instruction")
873 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
874 #define BAD_OUT_VPT \
875 _("vector predicated instruction should be in VPT/VPST block")
876 #define BAD_IT_COND _("incorrect condition in IT block")
877 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
878 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
879 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
880 #define BAD_PC_ADDRESSING \
881 _("cannot use register index with PC-relative addressing")
882 #define BAD_PC_WRITEBACK \
883 _("cannot use writeback with PC-relative addressing")
884 #define BAD_RANGE _("branch out of range")
885 #define BAD_FP16 _("selected processor does not support fp16 instruction")
886 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
887 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
888 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
890 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
892 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
894 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
896 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
897 #define BAD_MVE_AUTO \
898 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
899 " use a valid -march or -mcpu option.")
900 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
901 "and source operands makes instruction UNPREDICTABLE")
902 #define BAD_EL_TYPE _("bad element type for instruction")
903 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
905 static struct hash_control
* arm_ops_hsh
;
906 static struct hash_control
* arm_cond_hsh
;
907 static struct hash_control
* arm_vcond_hsh
;
908 static struct hash_control
* arm_shift_hsh
;
909 static struct hash_control
* arm_psr_hsh
;
910 static struct hash_control
* arm_v7m_psr_hsh
;
911 static struct hash_control
* arm_reg_hsh
;
912 static struct hash_control
* arm_reloc_hsh
;
913 static struct hash_control
* arm_barrier_opt_hsh
;
915 /* Stuff needed to resolve the label ambiguity
924 symbolS
* last_label_seen
;
925 static int label_is_thumb_function_name
= FALSE
;
927 /* Literal pool structure. Held on a per-section
928 and per-sub-section basis. */
930 #define MAX_LITERAL_POOL_SIZE 1024
931 typedef struct literal_pool
933 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
934 unsigned int next_free_entry
;
940 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
942 struct literal_pool
* next
;
943 unsigned int alignment
;
946 /* Pointer to a linked list of literal pools. */
947 literal_pool
* list_of_pools
= NULL
;
949 typedef enum asmfunc_states
952 WAITING_ASMFUNC_NAME
,
956 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
959 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
961 static struct current_pred now_pred
;
965 now_pred_compatible (int cond
)
967 return (cond
& ~1) == (now_pred
.cc
& ~1);
971 conditional_insn (void)
973 return inst
.cond
!= COND_ALWAYS
;
976 static int in_pred_block (void);
978 static int handle_pred_state (void);
980 static void force_automatic_it_block_close (void);
982 static void it_fsm_post_encode (void);
984 #define set_pred_insn_type(type) \
987 inst.pred_insn_type = type; \
988 if (handle_pred_state () == FAIL) \
993 #define set_pred_insn_type_nonvoid(type, failret) \
996 inst.pred_insn_type = type; \
997 if (handle_pred_state () == FAIL) \
1002 #define set_pred_insn_type_last() \
1005 if (inst.cond == COND_ALWAYS) \
1006 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1008 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1014 /* This array holds the chars that always start a comment. If the
1015 pre-processor is disabled, these aren't very useful. */
1016 char arm_comment_chars
[] = "@";
1018 /* This array holds the chars that only start a comment at the beginning of
1019 a line. If the line seems to have the form '# 123 filename'
1020 .line and .file directives will appear in the pre-processed output. */
1021 /* Note that input_file.c hand checks for '#' at the beginning of the
1022 first line of the input file. This is because the compiler outputs
1023 #NO_APP at the beginning of its output. */
1024 /* Also note that comments like this one will always work. */
1025 const char line_comment_chars
[] = "#";
1027 char arm_line_separator_chars
[] = ";";
1029 /* Chars that can be used to separate mant
1030 from exp in floating point numbers. */
1031 const char EXP_CHARS
[] = "eE";
1033 /* Chars that mean this number is a floating point constant. */
1034 /* As in 0f12.456 */
1035 /* or 0d1.2345e12 */
1037 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
1039 /* Prefix characters that indicate the start of an immediate
1041 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1043 /* Separator character handling. */
1045 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1048 skip_past_char (char ** str
, char c
)
1050 /* PR gas/14987: Allow for whitespace before the expected character. */
1051 skip_whitespace (*str
);
1062 #define skip_past_comma(str) skip_past_char (str, ',')
1064 /* Arithmetic expressions (possibly involving symbols). */
1066 /* Return TRUE if anything in the expression is a bignum. */
1069 walk_no_bignums (symbolS
* sp
)
1071 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1074 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1076 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1077 || (symbol_get_value_expression (sp
)->X_op_symbol
1078 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1084 static bfd_boolean in_my_get_expression
= FALSE
;
1086 /* Third argument to my_get_expression. */
1087 #define GE_NO_PREFIX 0
1088 #define GE_IMM_PREFIX 1
1089 #define GE_OPT_PREFIX 2
1090 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1091 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1092 #define GE_OPT_PREFIX_BIG 3
1095 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1099 /* In unified syntax, all prefixes are optional. */
1101 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1104 switch (prefix_mode
)
1106 case GE_NO_PREFIX
: break;
1108 if (!is_immediate_prefix (**str
))
1110 inst
.error
= _("immediate expression requires a # prefix");
1116 case GE_OPT_PREFIX_BIG
:
1117 if (is_immediate_prefix (**str
))
1124 memset (ep
, 0, sizeof (expressionS
));
1126 save_in
= input_line_pointer
;
1127 input_line_pointer
= *str
;
1128 in_my_get_expression
= TRUE
;
1130 in_my_get_expression
= FALSE
;
1132 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1134 /* We found a bad or missing expression in md_operand(). */
1135 *str
= input_line_pointer
;
1136 input_line_pointer
= save_in
;
1137 if (inst
.error
== NULL
)
1138 inst
.error
= (ep
->X_op
== O_absent
1139 ? _("missing expression") :_("bad expression"));
1143 /* Get rid of any bignums now, so that we don't generate an error for which
1144 we can't establish a line number later on. Big numbers are never valid
1145 in instructions, which is where this routine is always called. */
1146 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1147 && (ep
->X_op
== O_big
1148 || (ep
->X_add_symbol
1149 && (walk_no_bignums (ep
->X_add_symbol
)
1151 && walk_no_bignums (ep
->X_op_symbol
))))))
1153 inst
.error
= _("invalid constant");
1154 *str
= input_line_pointer
;
1155 input_line_pointer
= save_in
;
1159 *str
= input_line_pointer
;
1160 input_line_pointer
= save_in
;
1164 /* Turn a string in input_line_pointer into a floating point constant
1165 of type TYPE, and store the appropriate bytes in *LITP. The number
1166 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1167 returned, or NULL on OK.
1169 Note that fp constants aren't represent in the normal way on the ARM.
1170 In big endian mode, things are as expected. However, in little endian
1171 mode fp constants are big-endian word-wise, and little-endian byte-wise
1172 within the words. For example, (double) 1.1 in big endian mode is
1173 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1174 the byte sequence 99 99 f1 3f 9a 99 99 99.
1176 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1179 md_atof (int type
, char * litP
, int * sizeP
)
1182 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1214 return _("Unrecognized or unsupported floating point constant");
1217 t
= atof_ieee (input_line_pointer
, type
, words
);
1219 input_line_pointer
= t
;
1220 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1222 if (target_big_endian
)
1224 for (i
= 0; i
< prec
; i
++)
1226 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1227 litP
+= sizeof (LITTLENUM_TYPE
);
1232 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1233 for (i
= prec
- 1; i
>= 0; i
--)
1235 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1236 litP
+= sizeof (LITTLENUM_TYPE
);
1239 /* For a 4 byte float the order of elements in `words' is 1 0.
1240 For an 8 byte float the order is 1 0 3 2. */
1241 for (i
= 0; i
< prec
; i
+= 2)
1243 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1244 sizeof (LITTLENUM_TYPE
));
1245 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1246 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1247 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1254 /* We handle all bad expressions here, so that we can report the faulty
1255 instruction in the error message. */
1258 md_operand (expressionS
* exp
)
1260 if (in_my_get_expression
)
1261 exp
->X_op
= O_illegal
;
1264 /* Immediate values. */
1267 /* Generic immediate-value read function for use in directives.
1268 Accepts anything that 'expression' can fold to a constant.
1269 *val receives the number. */
1272 immediate_for_directive (int *val
)
1275 exp
.X_op
= O_illegal
;
1277 if (is_immediate_prefix (*input_line_pointer
))
1279 input_line_pointer
++;
1283 if (exp
.X_op
!= O_constant
)
1285 as_bad (_("expected #constant"));
1286 ignore_rest_of_line ();
1289 *val
= exp
.X_add_number
;
1294 /* Register parsing. */
1296 /* Generic register parser. CCP points to what should be the
1297 beginning of a register name. If it is indeed a valid register
1298 name, advance CCP over it and return the reg_entry structure;
1299 otherwise return NULL. Does not issue diagnostics. */
1301 static struct reg_entry
*
1302 arm_reg_parse_multi (char **ccp
)
1306 struct reg_entry
*reg
;
1308 skip_whitespace (start
);
1310 #ifdef REGISTER_PREFIX
1311 if (*start
!= REGISTER_PREFIX
)
1315 #ifdef OPTIONAL_REGISTER_PREFIX
1316 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1321 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1326 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1328 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1338 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1339 enum arm_reg_type type
)
1341 /* Alternative syntaxes are accepted for a few register classes. */
1348 /* Generic coprocessor register names are allowed for these. */
1349 if (reg
&& reg
->type
== REG_TYPE_CN
)
1354 /* For backward compatibility, a bare number is valid here. */
1356 unsigned long processor
= strtoul (start
, ccp
, 10);
1357 if (*ccp
!= start
&& processor
<= 15)
1362 case REG_TYPE_MMXWC
:
1363 /* WC includes WCG. ??? I'm not sure this is true for all
1364 instructions that take WC registers. */
1365 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1376 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1377 return value is the register number or FAIL. */
1380 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1383 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1386 /* Do not allow a scalar (reg+index) to parse as a register. */
1387 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1390 if (reg
&& reg
->type
== type
)
1393 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1400 /* Parse a Neon type specifier. *STR should point at the leading '.'
1401 character. Does no verification at this stage that the type fits the opcode
1408 Can all be legally parsed by this function.
1410 Fills in neon_type struct pointer with parsed information, and updates STR
1411 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1412 type, FAIL if not. */
1415 parse_neon_type (struct neon_type
*type
, char **str
)
1422 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1424 enum neon_el_type thistype
= NT_untyped
;
1425 unsigned thissize
= -1u;
1432 /* Just a size without an explicit type. */
1436 switch (TOLOWER (*ptr
))
1438 case 'i': thistype
= NT_integer
; break;
1439 case 'f': thistype
= NT_float
; break;
1440 case 'p': thistype
= NT_poly
; break;
1441 case 's': thistype
= NT_signed
; break;
1442 case 'u': thistype
= NT_unsigned
; break;
1444 thistype
= NT_float
;
1449 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1455 /* .f is an abbreviation for .f32. */
1456 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1461 thissize
= strtoul (ptr
, &ptr
, 10);
1463 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1466 as_bad (_("bad size %d in type specifier"), thissize
);
1474 type
->el
[type
->elems
].type
= thistype
;
1475 type
->el
[type
->elems
].size
= thissize
;
1480 /* Empty/missing type is not a successful parse. */
1481 if (type
->elems
== 0)
1489 /* Errors may be set multiple times during parsing or bit encoding
1490 (particularly in the Neon bits), but usually the earliest error which is set
1491 will be the most meaningful. Avoid overwriting it with later (cascading)
1492 errors by calling this function. */
1495 first_error (const char *err
)
1501 /* Parse a single type, e.g. ".s32", leading period included. */
1503 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1506 struct neon_type optype
;
1510 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1512 if (optype
.elems
== 1)
1513 *vectype
= optype
.el
[0];
1516 first_error (_("only one type should be specified for operand"));
1522 first_error (_("vector type expected"));
1534 /* Special meanings for indices (which have a range of 0-7), which will fit into
1537 #define NEON_ALL_LANES 15
1538 #define NEON_INTERLEAVE_LANES 14
1540 /* Record a use of the given feature. */
1542 record_feature_use (const arm_feature_set
*feature
)
1545 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1547 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1550 /* If the given feature available in the selected CPU, mark it as used.
1551 Returns TRUE iff feature is available. */
1553 mark_feature_used (const arm_feature_set
*feature
)
1556 /* Do not support the use of MVE only instructions when in auto-detection or
1558 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1559 && ARM_CPU_IS_ANY (cpu_variant
))
1561 first_error (BAD_MVE_AUTO
);
1564 /* Ensure the option is valid on the current architecture. */
1565 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1568 /* Add the appropriate architecture feature for the barrier option used.
1570 record_feature_use (feature
);
1575 /* Parse either a register or a scalar, with an optional type. Return the
1576 register number, and optionally fill in the actual type of the register
1577 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1578 type/index information in *TYPEINFO. */
1581 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1582 enum arm_reg_type
*rtype
,
1583 struct neon_typed_alias
*typeinfo
)
1586 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1587 struct neon_typed_alias atype
;
1588 struct neon_type_el parsetype
;
1592 atype
.eltype
.type
= NT_invtype
;
1593 atype
.eltype
.size
= -1;
1595 /* Try alternate syntax for some types of register. Note these are mutually
1596 exclusive with the Neon syntax extensions. */
1599 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1607 /* Undo polymorphism when a set of register types may be accepted. */
1608 if ((type
== REG_TYPE_NDQ
1609 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1610 || (type
== REG_TYPE_VFSD
1611 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1612 || (type
== REG_TYPE_NSDQ
1613 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1614 || reg
->type
== REG_TYPE_NQ
))
1615 || (type
== REG_TYPE_NSD
1616 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1617 || (type
== REG_TYPE_MMXWC
1618 && (reg
->type
== REG_TYPE_MMXWCG
)))
1619 type
= (enum arm_reg_type
) reg
->type
;
1621 if (type
== REG_TYPE_MQ
)
1623 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1626 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1629 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1631 first_error (_("expected MVE register [q0..q7]"));
1636 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1637 && (type
== REG_TYPE_NQ
))
1641 if (type
!= reg
->type
)
1647 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1649 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1651 first_error (_("can't redefine type for operand"));
1654 atype
.defined
|= NTA_HASTYPE
;
1655 atype
.eltype
= parsetype
;
1658 if (skip_past_char (&str
, '[') == SUCCESS
)
1660 if (type
!= REG_TYPE_VFD
1661 && !(type
== REG_TYPE_VFS
1662 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1663 && !(type
== REG_TYPE_NQ
1664 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1666 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1667 first_error (_("only D and Q registers may be indexed"));
1669 first_error (_("only D registers may be indexed"));
1673 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1675 first_error (_("can't change index for operand"));
1679 atype
.defined
|= NTA_HASINDEX
;
1681 if (skip_past_char (&str
, ']') == SUCCESS
)
1682 atype
.index
= NEON_ALL_LANES
;
1687 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1689 if (exp
.X_op
!= O_constant
)
1691 first_error (_("constant expression required"));
1695 if (skip_past_char (&str
, ']') == FAIL
)
1698 atype
.index
= exp
.X_add_number
;
1713 /* Like arm_reg_parse, but also allow the following extra features:
1714 - If RTYPE is non-zero, return the (possibly restricted) type of the
1715 register (e.g. Neon double or quad reg when either has been requested).
1716 - If this is a Neon vector type with additional type information, fill
1717 in the struct pointed to by VECTYPE (if non-NULL).
1718 This function will fault on encountering a scalar. */
1721 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1722 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1724 struct neon_typed_alias atype
;
1726 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1731 /* Do not allow regname(... to parse as a register. */
1735 /* Do not allow a scalar (reg+index) to parse as a register. */
1736 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1738 first_error (_("register operand expected, but got scalar"));
1743 *vectype
= atype
.eltype
;
1750 #define NEON_SCALAR_REG(X) ((X) >> 4)
1751 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1753 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1754 have enough information to be able to do a good job bounds-checking. So, we
1755 just do easy checks here, and do further checks later. */
1758 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1759 arm_reg_type reg_type
)
1763 struct neon_typed_alias atype
;
1766 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1784 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1787 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1789 first_error (_("scalar must have an index"));
1792 else if (atype
.index
>= reg_size
/ elsize
)
1794 first_error (_("scalar index out of range"));
1799 *type
= atype
.eltype
;
1803 return reg
* 16 + atype
.index
;
1806 /* Types of registers in a list. */
1819 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1822 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1828 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1830 /* We come back here if we get ranges concatenated by '+' or '|'. */
1833 skip_whitespace (str
);
1846 const char apsr_str
[] = "apsr";
1847 int apsr_str_len
= strlen (apsr_str
);
1849 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1850 if (etype
== REGLIST_CLRM
)
1852 if (reg
== REG_SP
|| reg
== REG_PC
)
1854 else if (reg
== FAIL
1855 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1856 && !ISALPHA (*(str
+ apsr_str_len
)))
1859 str
+= apsr_str_len
;
1864 first_error (_("r0-r12, lr or APSR expected"));
1868 else /* etype == REGLIST_RN. */
1872 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1883 first_error (_("bad range in register list"));
1887 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1889 if (range
& (1 << i
))
1891 (_("Warning: duplicated register (r%d) in register list"),
1899 if (range
& (1 << reg
))
1900 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1902 else if (reg
<= cur_reg
)
1903 as_tsktsk (_("Warning: register range not in ascending order"));
1908 while (skip_past_comma (&str
) != FAIL
1909 || (in_range
= 1, *str
++ == '-'));
1912 if (skip_past_char (&str
, '}') == FAIL
)
1914 first_error (_("missing `}'"));
1918 else if (etype
== REGLIST_RN
)
1922 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1925 if (exp
.X_op
== O_constant
)
1927 if (exp
.X_add_number
1928 != (exp
.X_add_number
& 0x0000ffff))
1930 inst
.error
= _("invalid register mask");
1934 if ((range
& exp
.X_add_number
) != 0)
1936 int regno
= range
& exp
.X_add_number
;
1939 regno
= (1 << regno
) - 1;
1941 (_("Warning: duplicated register (r%d) in register list"),
1945 range
|= exp
.X_add_number
;
1949 if (inst
.relocs
[0].type
!= 0)
1951 inst
.error
= _("expression too complex");
1955 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1956 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1957 inst
.relocs
[0].pc_rel
= 0;
1961 if (*str
== '|' || *str
== '+')
1967 while (another_range
);
1973 /* Parse a VFP register list. If the string is invalid return FAIL.
1974 Otherwise return the number of registers, and set PBASE to the first
1975 register. Parses registers of type ETYPE.
1976 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1977 - Q registers can be used to specify pairs of D registers
1978 - { } can be omitted from around a singleton register list
1979 FIXME: This is not implemented, as it would require backtracking in
1982 This could be done (the meaning isn't really ambiguous), but doesn't
1983 fit in well with the current parsing framework.
1984 - 32 D registers may be used (also true for VFPv3).
1985 FIXME: Types are ignored in these register lists, which is probably a
1989 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
1990 bfd_boolean
*partial_match
)
1995 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1999 unsigned long mask
= 0;
2001 bfd_boolean vpr_seen
= FALSE
;
2002 bfd_boolean expect_vpr
=
2003 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2005 if (skip_past_char (&str
, '{') == FAIL
)
2007 inst
.error
= _("expecting {");
2014 case REGLIST_VFP_S_VPR
:
2015 regtype
= REG_TYPE_VFS
;
2020 case REGLIST_VFP_D_VPR
:
2021 regtype
= REG_TYPE_VFD
;
2024 case REGLIST_NEON_D
:
2025 regtype
= REG_TYPE_NDQ
;
2032 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2034 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2035 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2039 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2042 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2049 base_reg
= max_regs
;
2050 *partial_match
= FALSE
;
2054 int setmask
= 1, addregs
= 1;
2055 const char vpr_str
[] = "vpr";
2056 int vpr_str_len
= strlen (vpr_str
);
2058 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2062 if (new_base
== FAIL
2063 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2064 && !ISALPHA (*(str
+ vpr_str_len
))
2070 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2074 first_error (_("VPR expected last"));
2077 else if (new_base
== FAIL
)
2079 if (regtype
== REG_TYPE_VFS
)
2080 first_error (_("VFP single precision register or VPR "
2082 else /* regtype == REG_TYPE_VFD. */
2083 first_error (_("VFP/Neon double precision register or VPR "
2088 else if (new_base
== FAIL
)
2090 first_error (_(reg_expected_msgs
[regtype
]));
2094 *partial_match
= TRUE
;
2098 if (new_base
>= max_regs
)
2100 first_error (_("register out of range in list"));
2104 /* Note: a value of 2 * n is returned for the register Q<n>. */
2105 if (regtype
== REG_TYPE_NQ
)
2111 if (new_base
< base_reg
)
2112 base_reg
= new_base
;
2114 if (mask
& (setmask
<< new_base
))
2116 first_error (_("invalid register list"));
2120 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2122 as_tsktsk (_("register list not in ascending order"));
2126 mask
|= setmask
<< new_base
;
2129 if (*str
== '-') /* We have the start of a range expression */
2135 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2138 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2142 if (high_range
>= max_regs
)
2144 first_error (_("register out of range in list"));
2148 if (regtype
== REG_TYPE_NQ
)
2149 high_range
= high_range
+ 1;
2151 if (high_range
<= new_base
)
2153 inst
.error
= _("register range not in ascending order");
2157 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2159 if (mask
& (setmask
<< new_base
))
2161 inst
.error
= _("invalid register list");
2165 mask
|= setmask
<< new_base
;
2170 while (skip_past_comma (&str
) != FAIL
);
2174 /* Sanity check -- should have raised a parse error above. */
2175 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2180 if (expect_vpr
&& !vpr_seen
)
2182 first_error (_("VPR expected last"));
2186 /* Final test -- the registers must be consecutive. */
2188 for (i
= 0; i
< count
; i
++)
2190 if ((mask
& (1u << i
)) == 0)
2192 inst
.error
= _("non-contiguous register range");
2202 /* True if two alias types are the same. */
2205 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2213 if (a
->defined
!= b
->defined
)
2216 if ((a
->defined
& NTA_HASTYPE
) != 0
2217 && (a
->eltype
.type
!= b
->eltype
.type
2218 || a
->eltype
.size
!= b
->eltype
.size
))
2221 if ((a
->defined
& NTA_HASINDEX
) != 0
2222 && (a
->index
!= b
->index
))
2228 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2229 The base register is put in *PBASE.
2230 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2232 The register stride (minus one) is put in bit 4 of the return value.
2233 Bits [6:5] encode the list length (minus one).
2234 The type of the list elements is put in *ELTYPE, if non-NULL. */
2236 #define NEON_LANE(X) ((X) & 0xf)
2237 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2238 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2241 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2243 struct neon_type_el
*eltype
)
2250 int leading_brace
= 0;
2251 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2252 const char *const incr_error
= mve
? _("register stride must be 1") :
2253 _("register stride must be 1 or 2");
2254 const char *const type_error
= _("mismatched element/structure types in list");
2255 struct neon_typed_alias firsttype
;
2256 firsttype
.defined
= 0;
2257 firsttype
.eltype
.type
= NT_invtype
;
2258 firsttype
.eltype
.size
= -1;
2259 firsttype
.index
= -1;
2261 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2266 struct neon_typed_alias atype
;
2268 rtype
= REG_TYPE_MQ
;
2269 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2273 first_error (_(reg_expected_msgs
[rtype
]));
2280 if (rtype
== REG_TYPE_NQ
)
2286 else if (reg_incr
== -1)
2288 reg_incr
= getreg
- base_reg
;
2289 if (reg_incr
< 1 || reg_incr
> 2)
2291 first_error (_(incr_error
));
2295 else if (getreg
!= base_reg
+ reg_incr
* count
)
2297 first_error (_(incr_error
));
2301 if (! neon_alias_types_same (&atype
, &firsttype
))
2303 first_error (_(type_error
));
2307 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2311 struct neon_typed_alias htype
;
2312 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2314 lane
= NEON_INTERLEAVE_LANES
;
2315 else if (lane
!= NEON_INTERLEAVE_LANES
)
2317 first_error (_(type_error
));
2322 else if (reg_incr
!= 1)
2324 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2328 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2331 first_error (_(reg_expected_msgs
[rtype
]));
2334 if (! neon_alias_types_same (&htype
, &firsttype
))
2336 first_error (_(type_error
));
2339 count
+= hireg
+ dregs
- getreg
;
2343 /* If we're using Q registers, we can't use [] or [n] syntax. */
2344 if (rtype
== REG_TYPE_NQ
)
2350 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2354 else if (lane
!= atype
.index
)
2356 first_error (_(type_error
));
2360 else if (lane
== -1)
2361 lane
= NEON_INTERLEAVE_LANES
;
2362 else if (lane
!= NEON_INTERLEAVE_LANES
)
2364 first_error (_(type_error
));
2369 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2371 /* No lane set by [x]. We must be interleaving structures. */
2373 lane
= NEON_INTERLEAVE_LANES
;
2376 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2377 || (count
> 1 && reg_incr
== -1))
2379 first_error (_("error parsing element/structure list"));
2383 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2385 first_error (_("expected }"));
2393 *eltype
= firsttype
.eltype
;
2398 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2401 /* Parse an explicit relocation suffix on an expression. This is
2402 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2403 arm_reloc_hsh contains no entries, so this function can only
2404 succeed if there is no () after the word. Returns -1 on error,
2405 BFD_RELOC_UNUSED if there wasn't any suffix. */
2408 parse_reloc (char **str
)
2410 struct reloc_entry
*r
;
2414 return BFD_RELOC_UNUSED
;
2419 while (*q
&& *q
!= ')' && *q
!= ',')
2424 if ((r
= (struct reloc_entry
*)
2425 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2432 /* Directives: register aliases. */
2434 static struct reg_entry
*
2435 insert_reg_alias (char *str
, unsigned number
, int type
)
2437 struct reg_entry
*new_reg
;
2440 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2442 if (new_reg
->builtin
)
2443 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2445 /* Only warn about a redefinition if it's not defined as the
2447 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2448 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2453 name
= xstrdup (str
);
2454 new_reg
= XNEW (struct reg_entry
);
2456 new_reg
->name
= name
;
2457 new_reg
->number
= number
;
2458 new_reg
->type
= type
;
2459 new_reg
->builtin
= FALSE
;
2460 new_reg
->neon
= NULL
;
2462 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2469 insert_neon_reg_alias (char *str
, int number
, int type
,
2470 struct neon_typed_alias
*atype
)
2472 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2476 first_error (_("attempt to redefine typed alias"));
2482 reg
->neon
= XNEW (struct neon_typed_alias
);
2483 *reg
->neon
= *atype
;
2487 /* Look for the .req directive. This is of the form:
2489 new_register_name .req existing_register_name
2491 If we find one, or if it looks sufficiently like one that we want to
2492 handle any error here, return TRUE. Otherwise return FALSE. */
2495 create_register_alias (char * newname
, char *p
)
2497 struct reg_entry
*old
;
2498 char *oldname
, *nbuf
;
2501 /* The input scrubber ensures that whitespace after the mnemonic is
2502 collapsed to single spaces. */
2504 if (strncmp (oldname
, " .req ", 6) != 0)
2508 if (*oldname
== '\0')
2511 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2514 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2518 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2519 the desired alias name, and p points to its end. If not, then
2520 the desired alias name is in the global original_case_string. */
2521 #ifdef TC_CASE_SENSITIVE
2524 newname
= original_case_string
;
2525 nlen
= strlen (newname
);
2528 nbuf
= xmemdup0 (newname
, nlen
);
2530 /* Create aliases under the new name as stated; an all-lowercase
2531 version of the new name; and an all-uppercase version of the new
2533 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2535 for (p
= nbuf
; *p
; p
++)
2538 if (strncmp (nbuf
, newname
, nlen
))
2540 /* If this attempt to create an additional alias fails, do not bother
2541 trying to create the all-lower case alias. We will fail and issue
2542 a second, duplicate error message. This situation arises when the
2543 programmer does something like:
2546 The second .req creates the "Foo" alias but then fails to create
2547 the artificial FOO alias because it has already been created by the
2549 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2556 for (p
= nbuf
; *p
; p
++)
2559 if (strncmp (nbuf
, newname
, nlen
))
2560 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2567 /* Create a Neon typed/indexed register alias using directives, e.g.:
2572 These typed registers can be used instead of the types specified after the
2573 Neon mnemonic, so long as all operands given have types. Types can also be
2574 specified directly, e.g.:
2575 vadd d0.s32, d1.s32, d2.s32 */
2578 create_neon_reg_alias (char *newname
, char *p
)
2580 enum arm_reg_type basetype
;
2581 struct reg_entry
*basereg
;
2582 struct reg_entry mybasereg
;
2583 struct neon_type ntype
;
2584 struct neon_typed_alias typeinfo
;
2585 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2588 typeinfo
.defined
= 0;
2589 typeinfo
.eltype
.type
= NT_invtype
;
2590 typeinfo
.eltype
.size
= -1;
2591 typeinfo
.index
= -1;
2595 if (strncmp (p
, " .dn ", 5) == 0)
2596 basetype
= REG_TYPE_VFD
;
2597 else if (strncmp (p
, " .qn ", 5) == 0)
2598 basetype
= REG_TYPE_NQ
;
2607 basereg
= arm_reg_parse_multi (&p
);
2609 if (basereg
&& basereg
->type
!= basetype
)
2611 as_bad (_("bad type for register"));
2615 if (basereg
== NULL
)
2618 /* Try parsing as an integer. */
2619 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2620 if (exp
.X_op
!= O_constant
)
2622 as_bad (_("expression must be constant"));
2625 basereg
= &mybasereg
;
2626 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2632 typeinfo
= *basereg
->neon
;
2634 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2636 /* We got a type. */
2637 if (typeinfo
.defined
& NTA_HASTYPE
)
2639 as_bad (_("can't redefine the type of a register alias"));
2643 typeinfo
.defined
|= NTA_HASTYPE
;
2644 if (ntype
.elems
!= 1)
2646 as_bad (_("you must specify a single type only"));
2649 typeinfo
.eltype
= ntype
.el
[0];
2652 if (skip_past_char (&p
, '[') == SUCCESS
)
2655 /* We got a scalar index. */
2657 if (typeinfo
.defined
& NTA_HASINDEX
)
2659 as_bad (_("can't redefine the index of a scalar alias"));
2663 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2665 if (exp
.X_op
!= O_constant
)
2667 as_bad (_("scalar index must be constant"));
2671 typeinfo
.defined
|= NTA_HASINDEX
;
2672 typeinfo
.index
= exp
.X_add_number
;
2674 if (skip_past_char (&p
, ']') == FAIL
)
2676 as_bad (_("expecting ]"));
2681 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2682 the desired alias name, and p points to its end. If not, then
2683 the desired alias name is in the global original_case_string. */
2684 #ifdef TC_CASE_SENSITIVE
2685 namelen
= nameend
- newname
;
2687 newname
= original_case_string
;
2688 namelen
= strlen (newname
);
2691 namebuf
= xmemdup0 (newname
, namelen
);
2693 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2694 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2696 /* Insert name in all uppercase. */
2697 for (p
= namebuf
; *p
; p
++)
2700 if (strncmp (namebuf
, newname
, namelen
))
2701 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2702 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2704 /* Insert name in all lowercase. */
2705 for (p
= namebuf
; *p
; p
++)
2708 if (strncmp (namebuf
, newname
, namelen
))
2709 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2710 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2716 /* Should never be called, as .req goes between the alias and the
2717 register name, not at the beginning of the line. */
2720 s_req (int a ATTRIBUTE_UNUSED
)
2722 as_bad (_("invalid syntax for .req directive"));
2726 s_dn (int a ATTRIBUTE_UNUSED
)
2728 as_bad (_("invalid syntax for .dn directive"));
2732 s_qn (int a ATTRIBUTE_UNUSED
)
2734 as_bad (_("invalid syntax for .qn directive"));
2737 /* The .unreq directive deletes an alias which was previously defined
2738 by .req. For example:
2744 s_unreq (int a ATTRIBUTE_UNUSED
)
2749 name
= input_line_pointer
;
2751 while (*input_line_pointer
!= 0
2752 && *input_line_pointer
!= ' '
2753 && *input_line_pointer
!= '\n')
2754 ++input_line_pointer
;
2756 saved_char
= *input_line_pointer
;
2757 *input_line_pointer
= 0;
2760 as_bad (_("invalid syntax for .unreq directive"));
2763 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2767 as_bad (_("unknown register alias '%s'"), name
);
2768 else if (reg
->builtin
)
2769 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2776 hash_delete (arm_reg_hsh
, name
, FALSE
);
2777 free ((char *) reg
->name
);
2782 /* Also locate the all upper case and all lower case versions.
2783 Do not complain if we cannot find one or the other as it
2784 was probably deleted above. */
2786 nbuf
= strdup (name
);
2787 for (p
= nbuf
; *p
; p
++)
2789 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2792 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2793 free ((char *) reg
->name
);
2799 for (p
= nbuf
; *p
; p
++)
2801 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2804 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2805 free ((char *) reg
->name
);
2815 *input_line_pointer
= saved_char
;
2816 demand_empty_rest_of_line ();
2819 /* Directives: Instruction set selection. */
2822 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2823 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2824 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2825 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2827 /* Create a new mapping symbol for the transition to STATE. */
2830 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2833 const char * symname
;
2840 type
= BSF_NO_FLAGS
;
2844 type
= BSF_NO_FLAGS
;
2848 type
= BSF_NO_FLAGS
;
2854 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2855 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2860 THUMB_SET_FUNC (symbolP
, 0);
2861 ARM_SET_THUMB (symbolP
, 0);
2862 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2866 THUMB_SET_FUNC (symbolP
, 1);
2867 ARM_SET_THUMB (symbolP
, 1);
2868 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2876 /* Save the mapping symbols for future reference. Also check that
2877 we do not place two mapping symbols at the same offset within a
2878 frag. We'll handle overlap between frags in
2879 check_mapping_symbols.
2881 If .fill or other data filling directive generates zero sized data,
2882 the mapping symbol for the following code will have the same value
2883 as the one generated for the data filling directive. In this case,
2884 we replace the old symbol with the new one at the same address. */
2887 if (frag
->tc_frag_data
.first_map
!= NULL
)
2889 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2890 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2892 frag
->tc_frag_data
.first_map
= symbolP
;
2894 if (frag
->tc_frag_data
.last_map
!= NULL
)
2896 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2897 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2898 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2900 frag
->tc_frag_data
.last_map
= symbolP
;
2903 /* We must sometimes convert a region marked as code to data during
2904 code alignment, if an odd number of bytes have to be padded. The
2905 code mapping symbol is pushed to an aligned address. */
2908 insert_data_mapping_symbol (enum mstate state
,
2909 valueT value
, fragS
*frag
, offsetT bytes
)
2911 /* If there was already a mapping symbol, remove it. */
2912 if (frag
->tc_frag_data
.last_map
!= NULL
2913 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2915 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2919 know (frag
->tc_frag_data
.first_map
== symp
);
2920 frag
->tc_frag_data
.first_map
= NULL
;
2922 frag
->tc_frag_data
.last_map
= NULL
;
2923 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2926 make_mapping_symbol (MAP_DATA
, value
, frag
);
2927 make_mapping_symbol (state
, value
+ bytes
, frag
);
2930 static void mapping_state_2 (enum mstate state
, int max_chars
);
2932 /* Set the mapping state to STATE. Only call this when about to
2933 emit some STATE bytes to the file. */
2935 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2937 mapping_state (enum mstate state
)
2939 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2941 if (mapstate
== state
)
2942 /* The mapping symbol has already been emitted.
2943 There is nothing else to do. */
2946 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2948 All ARM instructions require 4-byte alignment.
2949 (Almost) all Thumb instructions require 2-byte alignment.
2951 When emitting instructions into any section, mark the section
2954 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2955 but themselves require 2-byte alignment; this applies to some
2956 PC- relative forms. However, these cases will involve implicit
2957 literal pool generation or an explicit .align >=2, both of
2958 which will cause the section to me marked with sufficient
2959 alignment. Thus, we don't handle those cases here. */
2960 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2962 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2963 /* This case will be evaluated later. */
2966 mapping_state_2 (state
, 0);
2969 /* Same as mapping_state, but MAX_CHARS bytes have already been
2970 allocated. Put the mapping symbol that far back. */
2973 mapping_state_2 (enum mstate state
, int max_chars
)
2975 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2977 if (!SEG_NORMAL (now_seg
))
2980 if (mapstate
== state
)
2981 /* The mapping symbol has already been emitted.
2982 There is nothing else to do. */
2985 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2986 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2988 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2989 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2992 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2995 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2996 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3000 #define mapping_state(x) ((void)0)
3001 #define mapping_state_2(x, y) ((void)0)
3004 /* Find the real, Thumb encoded start of a Thumb function. */
3008 find_real_start (symbolS
* symbolP
)
3011 const char * name
= S_GET_NAME (symbolP
);
3012 symbolS
* new_target
;
3014 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3015 #define STUB_NAME ".real_start_of"
3020 /* The compiler may generate BL instructions to local labels because
3021 it needs to perform a branch to a far away location. These labels
3022 do not have a corresponding ".real_start_of" label. We check
3023 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3024 the ".real_start_of" convention for nonlocal branches. */
3025 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3028 real_start
= concat (STUB_NAME
, name
, NULL
);
3029 new_target
= symbol_find (real_start
);
3032 if (new_target
== NULL
)
3034 as_warn (_("Failed to find real start of function: %s\n"), name
);
3035 new_target
= symbolP
;
3043 opcode_select (int width
)
3050 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3051 as_bad (_("selected processor does not support THUMB opcodes"));
3054 /* No need to force the alignment, since we will have been
3055 coming from ARM mode, which is word-aligned. */
3056 record_alignment (now_seg
, 1);
3063 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3064 as_bad (_("selected processor does not support ARM opcodes"));
3069 frag_align (2, 0, 0);
3071 record_alignment (now_seg
, 1);
3076 as_bad (_("invalid instruction size selected (%d)"), width
);
3081 s_arm (int ignore ATTRIBUTE_UNUSED
)
3084 demand_empty_rest_of_line ();
3088 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3091 demand_empty_rest_of_line ();
3095 s_code (int unused ATTRIBUTE_UNUSED
)
3099 temp
= get_absolute_expression ();
3104 opcode_select (temp
);
3108 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3113 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3115 /* If we are not already in thumb mode go into it, EVEN if
3116 the target processor does not support thumb instructions.
3117 This is used by gcc/config/arm/lib1funcs.asm for example
3118 to compile interworking support functions even if the
3119 target processor should not support interworking. */
3123 record_alignment (now_seg
, 1);
3126 demand_empty_rest_of_line ();
3130 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3134 /* The following label is the name/address of the start of a Thumb function.
3135 We need to know this for the interworking support. */
3136 label_is_thumb_function_name
= TRUE
;
3139 /* Perform a .set directive, but also mark the alias as
3140 being a thumb function. */
3143 s_thumb_set (int equiv
)
3145 /* XXX the following is a duplicate of the code for s_set() in read.c
3146 We cannot just call that code as we need to get at the symbol that
3153 /* Especial apologies for the random logic:
3154 This just grew, and could be parsed much more simply!
3156 delim
= get_symbol_name (& name
);
3157 end_name
= input_line_pointer
;
3158 (void) restore_line_pointer (delim
);
3160 if (*input_line_pointer
!= ',')
3163 as_bad (_("expected comma after name \"%s\""), name
);
3165 ignore_rest_of_line ();
3169 input_line_pointer
++;
3172 if (name
[0] == '.' && name
[1] == '\0')
3174 /* XXX - this should not happen to .thumb_set. */
3178 if ((symbolP
= symbol_find (name
)) == NULL
3179 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3182 /* When doing symbol listings, play games with dummy fragments living
3183 outside the normal fragment chain to record the file and line info
3185 if (listing
& LISTING_SYMBOLS
)
3187 extern struct list_info_struct
* listing_tail
;
3188 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3190 memset (dummy_frag
, 0, sizeof (fragS
));
3191 dummy_frag
->fr_type
= rs_fill
;
3192 dummy_frag
->line
= listing_tail
;
3193 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3194 dummy_frag
->fr_symbol
= symbolP
;
3198 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3201 /* "set" symbols are local unless otherwise specified. */
3202 SF_SET_LOCAL (symbolP
);
3203 #endif /* OBJ_COFF */
3204 } /* Make a new symbol. */
3206 symbol_table_insert (symbolP
);
3211 && S_IS_DEFINED (symbolP
)
3212 && S_GET_SEGMENT (symbolP
) != reg_section
)
3213 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3215 pseudo_set (symbolP
);
3217 demand_empty_rest_of_line ();
3219 /* XXX Now we come to the Thumb specific bit of code. */
3221 THUMB_SET_FUNC (symbolP
, 1);
3222 ARM_SET_THUMB (symbolP
, 1);
3223 #if defined OBJ_ELF || defined OBJ_COFF
3224 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3228 /* Directives: Mode selection. */
3230 /* .syntax [unified|divided] - choose the new unified syntax
3231 (same for Arm and Thumb encoding, modulo slight differences in what
3232 can be represented) or the old divergent syntax for each mode. */
3234 s_syntax (int unused ATTRIBUTE_UNUSED
)
3238 delim
= get_symbol_name (& name
);
3240 if (!strcasecmp (name
, "unified"))
3241 unified_syntax
= TRUE
;
3242 else if (!strcasecmp (name
, "divided"))
3243 unified_syntax
= FALSE
;
3246 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3249 (void) restore_line_pointer (delim
);
3250 demand_empty_rest_of_line ();
3253 /* Directives: sectioning and alignment. */
3256 s_bss (int ignore ATTRIBUTE_UNUSED
)
3258 /* We don't support putting frags in the BSS segment, we fake it by
3259 marking in_bss, then looking at s_skip for clues. */
3260 subseg_set (bss_section
, 0);
3261 demand_empty_rest_of_line ();
3263 #ifdef md_elf_section_change_hook
3264 md_elf_section_change_hook ();
3269 s_even (int ignore ATTRIBUTE_UNUSED
)
3271 /* Never make frag if expect extra pass. */
3273 frag_align (1, 0, 0);
3275 record_alignment (now_seg
, 1);
3277 demand_empty_rest_of_line ();
3280 /* Directives: CodeComposer Studio. */
3282 /* .ref (for CodeComposer Studio syntax only). */
3284 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3286 if (codecomposer_syntax
)
3287 ignore_rest_of_line ();
3289 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3292 /* If name is not NULL, then it is used for marking the beginning of a
3293 function, whereas if it is NULL then it means the function end. */
3295 asmfunc_debug (const char * name
)
3297 static const char * last_name
= NULL
;
3301 gas_assert (last_name
== NULL
);
3304 if (debug_type
== DEBUG_STABS
)
3305 stabs_generate_asm_func (name
, name
);
3309 gas_assert (last_name
!= NULL
);
3311 if (debug_type
== DEBUG_STABS
)
3312 stabs_generate_asm_endfunc (last_name
, last_name
);
3319 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3321 if (codecomposer_syntax
)
3323 switch (asmfunc_state
)
3325 case OUTSIDE_ASMFUNC
:
3326 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3329 case WAITING_ASMFUNC_NAME
:
3330 as_bad (_(".asmfunc repeated."));
3333 case WAITING_ENDASMFUNC
:
3334 as_bad (_(".asmfunc without function."));
3337 demand_empty_rest_of_line ();
3340 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3344 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3346 if (codecomposer_syntax
)
3348 switch (asmfunc_state
)
3350 case OUTSIDE_ASMFUNC
:
3351 as_bad (_(".endasmfunc without a .asmfunc."));
3354 case WAITING_ASMFUNC_NAME
:
3355 as_bad (_(".endasmfunc without function."));
3358 case WAITING_ENDASMFUNC
:
3359 asmfunc_state
= OUTSIDE_ASMFUNC
;
3360 asmfunc_debug (NULL
);
3363 demand_empty_rest_of_line ();
3366 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3370 s_ccs_def (int name
)
3372 if (codecomposer_syntax
)
3375 as_bad (_(".def pseudo-op only available with -mccs flag."));
3378 /* Directives: Literal pools. */
3380 static literal_pool
*
3381 find_literal_pool (void)
3383 literal_pool
* pool
;
3385 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3387 if (pool
->section
== now_seg
3388 && pool
->sub_section
== now_subseg
)
3395 static literal_pool
*
3396 find_or_make_literal_pool (void)
3398 /* Next literal pool ID number. */
3399 static unsigned int latest_pool_num
= 1;
3400 literal_pool
* pool
;
3402 pool
= find_literal_pool ();
3406 /* Create a new pool. */
3407 pool
= XNEW (literal_pool
);
3411 pool
->next_free_entry
= 0;
3412 pool
->section
= now_seg
;
3413 pool
->sub_section
= now_subseg
;
3414 pool
->next
= list_of_pools
;
3415 pool
->symbol
= NULL
;
3416 pool
->alignment
= 2;
3418 /* Add it to the list. */
3419 list_of_pools
= pool
;
3422 /* New pools, and emptied pools, will have a NULL symbol. */
3423 if (pool
->symbol
== NULL
)
3425 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3426 (valueT
) 0, &zero_address_frag
);
3427 pool
->id
= latest_pool_num
++;
3434 /* Add the literal in the global 'inst'
3435 structure to the relevant literal pool. */
3438 add_to_lit_pool (unsigned int nbytes
)
3440 #define PADDING_SLOT 0x1
3441 #define LIT_ENTRY_SIZE_MASK 0xFF
3442 literal_pool
* pool
;
3443 unsigned int entry
, pool_size
= 0;
3444 bfd_boolean padding_slot_p
= FALSE
;
3450 imm1
= inst
.operands
[1].imm
;
3451 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3452 : inst
.relocs
[0].exp
.X_unsigned
? 0
3453 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3454 if (target_big_endian
)
3457 imm2
= inst
.operands
[1].imm
;
3461 pool
= find_or_make_literal_pool ();
3463 /* Check if this literal value is already in the pool. */
3464 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3468 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3469 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3470 && (pool
->literals
[entry
].X_add_number
3471 == inst
.relocs
[0].exp
.X_add_number
)
3472 && (pool
->literals
[entry
].X_md
== nbytes
)
3473 && (pool
->literals
[entry
].X_unsigned
3474 == inst
.relocs
[0].exp
.X_unsigned
))
3477 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3478 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3479 && (pool
->literals
[entry
].X_add_number
3480 == inst
.relocs
[0].exp
.X_add_number
)
3481 && (pool
->literals
[entry
].X_add_symbol
3482 == inst
.relocs
[0].exp
.X_add_symbol
)
3483 && (pool
->literals
[entry
].X_op_symbol
3484 == inst
.relocs
[0].exp
.X_op_symbol
)
3485 && (pool
->literals
[entry
].X_md
== nbytes
))
3488 else if ((nbytes
== 8)
3489 && !(pool_size
& 0x7)
3490 && ((entry
+ 1) != pool
->next_free_entry
)
3491 && (pool
->literals
[entry
].X_op
== O_constant
)
3492 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3493 && (pool
->literals
[entry
].X_unsigned
3494 == inst
.relocs
[0].exp
.X_unsigned
)
3495 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3496 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3497 && (pool
->literals
[entry
+ 1].X_unsigned
3498 == inst
.relocs
[0].exp
.X_unsigned
))
3501 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3502 if (padding_slot_p
&& (nbytes
== 4))
3508 /* Do we need to create a new entry? */
3509 if (entry
== pool
->next_free_entry
)
3511 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3513 inst
.error
= _("literal pool overflow");
3519 /* For 8-byte entries, we align to an 8-byte boundary,
3520 and split it into two 4-byte entries, because on 32-bit
3521 host, 8-byte constants are treated as big num, thus
3522 saved in "generic_bignum" which will be overwritten
3523 by later assignments.
3525 We also need to make sure there is enough space for
3528 We also check to make sure the literal operand is a
3530 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3531 || inst
.relocs
[0].exp
.X_op
== O_big
))
3533 inst
.error
= _("invalid type for literal pool");
3536 else if (pool_size
& 0x7)
3538 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3540 inst
.error
= _("literal pool overflow");
3544 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3545 pool
->literals
[entry
].X_op
= O_constant
;
3546 pool
->literals
[entry
].X_add_number
= 0;
3547 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3548 pool
->next_free_entry
+= 1;
3551 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3553 inst
.error
= _("literal pool overflow");
3557 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3558 pool
->literals
[entry
].X_op
= O_constant
;
3559 pool
->literals
[entry
].X_add_number
= imm1
;
3560 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3561 pool
->literals
[entry
++].X_md
= 4;
3562 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3563 pool
->literals
[entry
].X_op
= O_constant
;
3564 pool
->literals
[entry
].X_add_number
= imm2
;
3565 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3566 pool
->literals
[entry
].X_md
= 4;
3567 pool
->alignment
= 3;
3568 pool
->next_free_entry
+= 1;
3572 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3573 pool
->literals
[entry
].X_md
= 4;
3577 /* PR ld/12974: Record the location of the first source line to reference
3578 this entry in the literal pool. If it turns out during linking that the
3579 symbol does not exist we will be able to give an accurate line number for
3580 the (first use of the) missing reference. */
3581 if (debug_type
== DEBUG_DWARF2
)
3582 dwarf2_where (pool
->locs
+ entry
);
3584 pool
->next_free_entry
+= 1;
3586 else if (padding_slot_p
)
3588 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3589 pool
->literals
[entry
].X_md
= nbytes
;
3592 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3593 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3594 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3600 tc_start_label_without_colon (void)
3602 bfd_boolean ret
= TRUE
;
3604 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3606 const char *label
= input_line_pointer
;
3608 while (!is_end_of_line
[(int) label
[-1]])
3613 as_bad (_("Invalid label '%s'"), label
);
3617 asmfunc_debug (label
);
3619 asmfunc_state
= WAITING_ENDASMFUNC
;
3625 /* Can't use symbol_new here, so have to create a symbol and then at
3626 a later date assign it a value. That's what these functions do. */
3629 symbol_locate (symbolS
* symbolP
,
3630 const char * name
, /* It is copied, the caller can modify. */
3631 segT segment
, /* Segment identifier (SEG_<something>). */
3632 valueT valu
, /* Symbol value. */
3633 fragS
* frag
) /* Associated fragment. */
3636 char * preserved_copy_of_name
;
3638 name_length
= strlen (name
) + 1; /* +1 for \0. */
3639 obstack_grow (¬es
, name
, name_length
);
3640 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3642 #ifdef tc_canonicalize_symbol_name
3643 preserved_copy_of_name
=
3644 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3647 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3649 S_SET_SEGMENT (symbolP
, segment
);
3650 S_SET_VALUE (symbolP
, valu
);
3651 symbol_clear_list_pointers (symbolP
);
3653 symbol_set_frag (symbolP
, frag
);
3655 /* Link to end of symbol chain. */
3657 extern int symbol_table_frozen
;
3659 if (symbol_table_frozen
)
3663 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3665 obj_symbol_new_hook (symbolP
);
3667 #ifdef tc_symbol_new_hook
3668 tc_symbol_new_hook (symbolP
);
3672 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3673 #endif /* DEBUG_SYMS */
3677 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3680 literal_pool
* pool
;
3683 pool
= find_literal_pool ();
3685 || pool
->symbol
== NULL
3686 || pool
->next_free_entry
== 0)
3689 /* Align pool as you have word accesses.
3690 Only make a frag if we have to. */
3692 frag_align (pool
->alignment
, 0, 0);
3694 record_alignment (now_seg
, 2);
3697 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3698 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3700 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3702 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3703 (valueT
) frag_now_fix (), frag_now
);
3704 symbol_table_insert (pool
->symbol
);
3706 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3708 #if defined OBJ_COFF || defined OBJ_ELF
3709 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3712 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3715 if (debug_type
== DEBUG_DWARF2
)
3716 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3718 /* First output the expression in the instruction to the pool. */
3719 emit_expr (&(pool
->literals
[entry
]),
3720 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3723 /* Mark the pool as empty. */
3724 pool
->next_free_entry
= 0;
3725 pool
->symbol
= NULL
;
3729 /* Forward declarations for functions below, in the MD interface
3731 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3732 static valueT
create_unwind_entry (int);
3733 static void start_unwind_section (const segT
, int);
3734 static void add_unwind_opcode (valueT
, int);
3735 static void flush_pending_unwind (void);
3737 /* Directives: Data. */
3740 s_arm_elf_cons (int nbytes
)
3744 #ifdef md_flush_pending_output
3745 md_flush_pending_output ();
3748 if (is_it_end_of_statement ())
3750 demand_empty_rest_of_line ();
3754 #ifdef md_cons_align
3755 md_cons_align (nbytes
);
3758 mapping_state (MAP_DATA
);
3762 char *base
= input_line_pointer
;
3766 if (exp
.X_op
!= O_symbol
)
3767 emit_expr (&exp
, (unsigned int) nbytes
);
3770 char *before_reloc
= input_line_pointer
;
3771 reloc
= parse_reloc (&input_line_pointer
);
3774 as_bad (_("unrecognized relocation suffix"));
3775 ignore_rest_of_line ();
3778 else if (reloc
== BFD_RELOC_UNUSED
)
3779 emit_expr (&exp
, (unsigned int) nbytes
);
3782 reloc_howto_type
*howto
= (reloc_howto_type
*)
3783 bfd_reloc_type_lookup (stdoutput
,
3784 (bfd_reloc_code_real_type
) reloc
);
3785 int size
= bfd_get_reloc_size (howto
);
3787 if (reloc
== BFD_RELOC_ARM_PLT32
)
3789 as_bad (_("(plt) is only valid on branch targets"));
3790 reloc
= BFD_RELOC_UNUSED
;
3795 as_bad (ngettext ("%s relocations do not fit in %d byte",
3796 "%s relocations do not fit in %d bytes",
3798 howto
->name
, nbytes
);
3801 /* We've parsed an expression stopping at O_symbol.
3802 But there may be more expression left now that we
3803 have parsed the relocation marker. Parse it again.
3804 XXX Surely there is a cleaner way to do this. */
3805 char *p
= input_line_pointer
;
3807 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3809 memcpy (save_buf
, base
, input_line_pointer
- base
);
3810 memmove (base
+ (input_line_pointer
- before_reloc
),
3811 base
, before_reloc
- base
);
3813 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3815 memcpy (base
, save_buf
, p
- base
);
3817 offset
= nbytes
- size
;
3818 p
= frag_more (nbytes
);
3819 memset (p
, 0, nbytes
);
3820 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3821 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3827 while (*input_line_pointer
++ == ',');
3829 /* Put terminator back into stream. */
3830 input_line_pointer
--;
3831 demand_empty_rest_of_line ();
3834 /* Emit an expression containing a 32-bit thumb instruction.
3835 Implementation based on put_thumb32_insn. */
3838 emit_thumb32_expr (expressionS
* exp
)
3840 expressionS exp_high
= *exp
;
3842 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3843 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3844 exp
->X_add_number
&= 0xffff;
3845 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3848 /* Guess the instruction size based on the opcode. */
3851 thumb_insn_size (int opcode
)
3853 if ((unsigned int) opcode
< 0xe800u
)
3855 else if ((unsigned int) opcode
>= 0xe8000000u
)
3862 emit_insn (expressionS
*exp
, int nbytes
)
3866 if (exp
->X_op
== O_constant
)
3871 size
= thumb_insn_size (exp
->X_add_number
);
3875 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3877 as_bad (_(".inst.n operand too big. "\
3878 "Use .inst.w instead"));
3883 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3884 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3886 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3888 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3889 emit_thumb32_expr (exp
);
3891 emit_expr (exp
, (unsigned int) size
);
3893 it_fsm_post_encode ();
3897 as_bad (_("cannot determine Thumb instruction size. " \
3898 "Use .inst.n/.inst.w instead"));
3901 as_bad (_("constant expression required"));
3906 /* Like s_arm_elf_cons but do not use md_cons_align and
3907 set the mapping state to MAP_ARM/MAP_THUMB. */
3910 s_arm_elf_inst (int nbytes
)
3912 if (is_it_end_of_statement ())
3914 demand_empty_rest_of_line ();
3918 /* Calling mapping_state () here will not change ARM/THUMB,
3919 but will ensure not to be in DATA state. */
3922 mapping_state (MAP_THUMB
);
3927 as_bad (_("width suffixes are invalid in ARM mode"));
3928 ignore_rest_of_line ();
3934 mapping_state (MAP_ARM
);
3943 if (! emit_insn (& exp
, nbytes
))
3945 ignore_rest_of_line ();
3949 while (*input_line_pointer
++ == ',');
3951 /* Put terminator back into stream. */
3952 input_line_pointer
--;
3953 demand_empty_rest_of_line ();
3956 /* Parse a .rel31 directive. */
3959 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3966 if (*input_line_pointer
== '1')
3967 highbit
= 0x80000000;
3968 else if (*input_line_pointer
!= '0')
3969 as_bad (_("expected 0 or 1"));
3971 input_line_pointer
++;
3972 if (*input_line_pointer
!= ',')
3973 as_bad (_("missing comma"));
3974 input_line_pointer
++;
3976 #ifdef md_flush_pending_output
3977 md_flush_pending_output ();
3980 #ifdef md_cons_align
3984 mapping_state (MAP_DATA
);
3989 md_number_to_chars (p
, highbit
, 4);
3990 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3991 BFD_RELOC_ARM_PREL31
);
3993 demand_empty_rest_of_line ();
3996 /* Directives: AEABI stack-unwind tables. */
3998 /* Parse an unwind_fnstart directive. Simply records the current location. */
4001 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4003 demand_empty_rest_of_line ();
4004 if (unwind
.proc_start
)
4006 as_bad (_("duplicate .fnstart directive"));
4010 /* Mark the start of the function. */
4011 unwind
.proc_start
= expr_build_dot ();
4013 /* Reset the rest of the unwind info. */
4014 unwind
.opcode_count
= 0;
4015 unwind
.table_entry
= NULL
;
4016 unwind
.personality_routine
= NULL
;
4017 unwind
.personality_index
= -1;
4018 unwind
.frame_size
= 0;
4019 unwind
.fp_offset
= 0;
4020 unwind
.fp_reg
= REG_SP
;
4022 unwind
.sp_restored
= 0;
4026 /* Parse a handlerdata directive. Creates the exception handling table entry
4027 for the function. */
4030 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4032 demand_empty_rest_of_line ();
4033 if (!unwind
.proc_start
)
4034 as_bad (MISSING_FNSTART
);
4036 if (unwind
.table_entry
)
4037 as_bad (_("duplicate .handlerdata directive"));
4039 create_unwind_entry (1);
4042 /* Parse an unwind_fnend directive. Generates the index table entry. */
4045 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4050 unsigned int marked_pr_dependency
;
4052 demand_empty_rest_of_line ();
4054 if (!unwind
.proc_start
)
4056 as_bad (_(".fnend directive without .fnstart"));
4060 /* Add eh table entry. */
4061 if (unwind
.table_entry
== NULL
)
4062 val
= create_unwind_entry (0);
4066 /* Add index table entry. This is two words. */
4067 start_unwind_section (unwind
.saved_seg
, 1);
4068 frag_align (2, 0, 0);
4069 record_alignment (now_seg
, 2);
4071 ptr
= frag_more (8);
4073 where
= frag_now_fix () - 8;
4075 /* Self relative offset of the function start. */
4076 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4077 BFD_RELOC_ARM_PREL31
);
4079 /* Indicate dependency on EHABI-defined personality routines to the
4080 linker, if it hasn't been done already. */
4081 marked_pr_dependency
4082 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4083 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4084 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4086 static const char *const name
[] =
4088 "__aeabi_unwind_cpp_pr0",
4089 "__aeabi_unwind_cpp_pr1",
4090 "__aeabi_unwind_cpp_pr2"
4092 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4093 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4094 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4095 |= 1 << unwind
.personality_index
;
4099 /* Inline exception table entry. */
4100 md_number_to_chars (ptr
+ 4, val
, 4);
4102 /* Self relative offset of the table entry. */
4103 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4104 BFD_RELOC_ARM_PREL31
);
4106 /* Restore the original section. */
4107 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4109 unwind
.proc_start
= NULL
;
4113 /* Parse an unwind_cantunwind directive. */
4116 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4118 demand_empty_rest_of_line ();
4119 if (!unwind
.proc_start
)
4120 as_bad (MISSING_FNSTART
);
4122 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4123 as_bad (_("personality routine specified for cantunwind frame"));
4125 unwind
.personality_index
= -2;
4129 /* Parse a personalityindex directive. */
4132 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4136 if (!unwind
.proc_start
)
4137 as_bad (MISSING_FNSTART
);
4139 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4140 as_bad (_("duplicate .personalityindex directive"));
4144 if (exp
.X_op
!= O_constant
4145 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4147 as_bad (_("bad personality routine number"));
4148 ignore_rest_of_line ();
4152 unwind
.personality_index
= exp
.X_add_number
;
4154 demand_empty_rest_of_line ();
4158 /* Parse a personality directive. */
4161 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4165 if (!unwind
.proc_start
)
4166 as_bad (MISSING_FNSTART
);
4168 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4169 as_bad (_("duplicate .personality directive"));
4171 c
= get_symbol_name (& name
);
4172 p
= input_line_pointer
;
4174 ++ input_line_pointer
;
4175 unwind
.personality_routine
= symbol_find_or_make (name
);
4177 demand_empty_rest_of_line ();
4181 /* Parse a directive saving core registers. */
4184 s_arm_unwind_save_core (void)
4190 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4193 as_bad (_("expected register list"));
4194 ignore_rest_of_line ();
4198 demand_empty_rest_of_line ();
4200 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4201 into .unwind_save {..., sp...}. We aren't bothered about the value of
4202 ip because it is clobbered by calls. */
4203 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4204 && (range
& 0x3000) == 0x1000)
4206 unwind
.opcode_count
--;
4207 unwind
.sp_restored
= 0;
4208 range
= (range
| 0x2000) & ~0x1000;
4209 unwind
.pending_offset
= 0;
4215 /* See if we can use the short opcodes. These pop a block of up to 8
4216 registers starting with r4, plus maybe r14. */
4217 for (n
= 0; n
< 8; n
++)
4219 /* Break at the first non-saved register. */
4220 if ((range
& (1 << (n
+ 4))) == 0)
4223 /* See if there are any other bits set. */
4224 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4226 /* Use the long form. */
4227 op
= 0x8000 | ((range
>> 4) & 0xfff);
4228 add_unwind_opcode (op
, 2);
4232 /* Use the short form. */
4234 op
= 0xa8; /* Pop r14. */
4236 op
= 0xa0; /* Do not pop r14. */
4238 add_unwind_opcode (op
, 1);
4245 op
= 0xb100 | (range
& 0xf);
4246 add_unwind_opcode (op
, 2);
4249 /* Record the number of bytes pushed. */
4250 for (n
= 0; n
< 16; n
++)
4252 if (range
& (1 << n
))
4253 unwind
.frame_size
+= 4;
4258 /* Parse a directive saving FPA registers. */
4261 s_arm_unwind_save_fpa (int reg
)
4267 /* Get Number of registers to transfer. */
4268 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4271 exp
.X_op
= O_illegal
;
4273 if (exp
.X_op
!= O_constant
)
4275 as_bad (_("expected , <constant>"));
4276 ignore_rest_of_line ();
4280 num_regs
= exp
.X_add_number
;
4282 if (num_regs
< 1 || num_regs
> 4)
4284 as_bad (_("number of registers must be in the range [1:4]"));
4285 ignore_rest_of_line ();
4289 demand_empty_rest_of_line ();
4294 op
= 0xb4 | (num_regs
- 1);
4295 add_unwind_opcode (op
, 1);
4300 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4301 add_unwind_opcode (op
, 2);
4303 unwind
.frame_size
+= num_regs
* 12;
4307 /* Parse a directive saving VFP registers for ARMv6 and above. */
4310 s_arm_unwind_save_vfp_armv6 (void)
4315 int num_vfpv3_regs
= 0;
4316 int num_regs_below_16
;
4317 bfd_boolean partial_match
;
4319 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4323 as_bad (_("expected register list"));
4324 ignore_rest_of_line ();
4328 demand_empty_rest_of_line ();
4330 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4331 than FSTMX/FLDMX-style ones). */
4333 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4335 num_vfpv3_regs
= count
;
4336 else if (start
+ count
> 16)
4337 num_vfpv3_regs
= start
+ count
- 16;
4339 if (num_vfpv3_regs
> 0)
4341 int start_offset
= start
> 16 ? start
- 16 : 0;
4342 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4343 add_unwind_opcode (op
, 2);
4346 /* Generate opcode for registers numbered in the range 0 .. 15. */
4347 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4348 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4349 if (num_regs_below_16
> 0)
4351 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4352 add_unwind_opcode (op
, 2);
4355 unwind
.frame_size
+= count
* 8;
4359 /* Parse a directive saving VFP registers for pre-ARMv6. */
4362 s_arm_unwind_save_vfp (void)
4367 bfd_boolean partial_match
;
4369 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4373 as_bad (_("expected register list"));
4374 ignore_rest_of_line ();
4378 demand_empty_rest_of_line ();
4383 op
= 0xb8 | (count
- 1);
4384 add_unwind_opcode (op
, 1);
4389 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4390 add_unwind_opcode (op
, 2);
4392 unwind
.frame_size
+= count
* 8 + 4;
4396 /* Parse a directive saving iWMMXt data registers. */
4399 s_arm_unwind_save_mmxwr (void)
4407 if (*input_line_pointer
== '{')
4408 input_line_pointer
++;
4412 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4416 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4421 as_tsktsk (_("register list not in ascending order"));
4424 if (*input_line_pointer
== '-')
4426 input_line_pointer
++;
4427 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4430 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4433 else if (reg
>= hi_reg
)
4435 as_bad (_("bad register range"));
4438 for (; reg
< hi_reg
; reg
++)
4442 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4444 skip_past_char (&input_line_pointer
, '}');
4446 demand_empty_rest_of_line ();
4448 /* Generate any deferred opcodes because we're going to be looking at
4450 flush_pending_unwind ();
4452 for (i
= 0; i
< 16; i
++)
4454 if (mask
& (1 << i
))
4455 unwind
.frame_size
+= 8;
4458 /* Attempt to combine with a previous opcode. We do this because gcc
4459 likes to output separate unwind directives for a single block of
4461 if (unwind
.opcode_count
> 0)
4463 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4464 if ((i
& 0xf8) == 0xc0)
4467 /* Only merge if the blocks are contiguous. */
4470 if ((mask
& 0xfe00) == (1 << 9))
4472 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4473 unwind
.opcode_count
--;
4476 else if (i
== 6 && unwind
.opcode_count
>= 2)
4478 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4482 op
= 0xffff << (reg
- 1);
4484 && ((mask
& op
) == (1u << (reg
- 1))))
4486 op
= (1 << (reg
+ i
+ 1)) - 1;
4487 op
&= ~((1 << reg
) - 1);
4489 unwind
.opcode_count
-= 2;
4496 /* We want to generate opcodes in the order the registers have been
4497 saved, ie. descending order. */
4498 for (reg
= 15; reg
>= -1; reg
--)
4500 /* Save registers in blocks. */
4502 || !(mask
& (1 << reg
)))
4504 /* We found an unsaved reg. Generate opcodes to save the
4511 op
= 0xc0 | (hi_reg
- 10);
4512 add_unwind_opcode (op
, 1);
4517 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4518 add_unwind_opcode (op
, 2);
4527 ignore_rest_of_line ();
4531 s_arm_unwind_save_mmxwcg (void)
4538 if (*input_line_pointer
== '{')
4539 input_line_pointer
++;
4541 skip_whitespace (input_line_pointer
);
4545 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4549 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4555 as_tsktsk (_("register list not in ascending order"));
4558 if (*input_line_pointer
== '-')
4560 input_line_pointer
++;
4561 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4564 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4567 else if (reg
>= hi_reg
)
4569 as_bad (_("bad register range"));
4572 for (; reg
< hi_reg
; reg
++)
4576 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4578 skip_past_char (&input_line_pointer
, '}');
4580 demand_empty_rest_of_line ();
4582 /* Generate any deferred opcodes because we're going to be looking at
4584 flush_pending_unwind ();
4586 for (reg
= 0; reg
< 16; reg
++)
4588 if (mask
& (1 << reg
))
4589 unwind
.frame_size
+= 4;
4592 add_unwind_opcode (op
, 2);
4595 ignore_rest_of_line ();
4599 /* Parse an unwind_save directive.
4600 If the argument is non-zero, this is a .vsave directive. */
4603 s_arm_unwind_save (int arch_v6
)
4606 struct reg_entry
*reg
;
4607 bfd_boolean had_brace
= FALSE
;
4609 if (!unwind
.proc_start
)
4610 as_bad (MISSING_FNSTART
);
4612 /* Figure out what sort of save we have. */
4613 peek
= input_line_pointer
;
4621 reg
= arm_reg_parse_multi (&peek
);
4625 as_bad (_("register expected"));
4626 ignore_rest_of_line ();
4635 as_bad (_("FPA .unwind_save does not take a register list"));
4636 ignore_rest_of_line ();
4639 input_line_pointer
= peek
;
4640 s_arm_unwind_save_fpa (reg
->number
);
4644 s_arm_unwind_save_core ();
4649 s_arm_unwind_save_vfp_armv6 ();
4651 s_arm_unwind_save_vfp ();
4654 case REG_TYPE_MMXWR
:
4655 s_arm_unwind_save_mmxwr ();
4658 case REG_TYPE_MMXWCG
:
4659 s_arm_unwind_save_mmxwcg ();
4663 as_bad (_(".unwind_save does not support this kind of register"));
4664 ignore_rest_of_line ();
4669 /* Parse an unwind_movsp directive. */
4672 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4678 if (!unwind
.proc_start
)
4679 as_bad (MISSING_FNSTART
);
4681 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4684 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4685 ignore_rest_of_line ();
4689 /* Optional constant. */
4690 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4692 if (immediate_for_directive (&offset
) == FAIL
)
4698 demand_empty_rest_of_line ();
4700 if (reg
== REG_SP
|| reg
== REG_PC
)
4702 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4706 if (unwind
.fp_reg
!= REG_SP
)
4707 as_bad (_("unexpected .unwind_movsp directive"));
4709 /* Generate opcode to restore the value. */
4711 add_unwind_opcode (op
, 1);
4713 /* Record the information for later. */
4714 unwind
.fp_reg
= reg
;
4715 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4716 unwind
.sp_restored
= 1;
4719 /* Parse an unwind_pad directive. */
4722 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4726 if (!unwind
.proc_start
)
4727 as_bad (MISSING_FNSTART
);
4729 if (immediate_for_directive (&offset
) == FAIL
)
4734 as_bad (_("stack increment must be multiple of 4"));
4735 ignore_rest_of_line ();
4739 /* Don't generate any opcodes, just record the details for later. */
4740 unwind
.frame_size
+= offset
;
4741 unwind
.pending_offset
+= offset
;
4743 demand_empty_rest_of_line ();
4746 /* Parse an unwind_setfp directive. */
4749 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4755 if (!unwind
.proc_start
)
4756 as_bad (MISSING_FNSTART
);
4758 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4759 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4762 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4764 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4766 as_bad (_("expected <reg>, <reg>"));
4767 ignore_rest_of_line ();
4771 /* Optional constant. */
4772 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4774 if (immediate_for_directive (&offset
) == FAIL
)
4780 demand_empty_rest_of_line ();
4782 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4784 as_bad (_("register must be either sp or set by a previous"
4785 "unwind_movsp directive"));
4789 /* Don't generate any opcodes, just record the information for later. */
4790 unwind
.fp_reg
= fp_reg
;
4792 if (sp_reg
== REG_SP
)
4793 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4795 unwind
.fp_offset
-= offset
;
4798 /* Parse an unwind_raw directive. */
4801 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4804 /* This is an arbitrary limit. */
4805 unsigned char op
[16];
4808 if (!unwind
.proc_start
)
4809 as_bad (MISSING_FNSTART
);
4812 if (exp
.X_op
== O_constant
4813 && skip_past_comma (&input_line_pointer
) != FAIL
)
4815 unwind
.frame_size
+= exp
.X_add_number
;
4819 exp
.X_op
= O_illegal
;
4821 if (exp
.X_op
!= O_constant
)
4823 as_bad (_("expected <offset>, <opcode>"));
4824 ignore_rest_of_line ();
4830 /* Parse the opcode. */
4835 as_bad (_("unwind opcode too long"));
4836 ignore_rest_of_line ();
4838 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4840 as_bad (_("invalid unwind opcode"));
4841 ignore_rest_of_line ();
4844 op
[count
++] = exp
.X_add_number
;
4846 /* Parse the next byte. */
4847 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4853 /* Add the opcode bytes in reverse order. */
4855 add_unwind_opcode (op
[count
], 1);
4857 demand_empty_rest_of_line ();
4861 /* Parse a .eabi_attribute directive. */
4864 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4866 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4868 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4869 attributes_set_explicitly
[tag
] = 1;
4872 /* Emit a tls fix for the symbol. */
4875 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4879 #ifdef md_flush_pending_output
4880 md_flush_pending_output ();
4883 #ifdef md_cons_align
4887 /* Since we're just labelling the code, there's no need to define a
4890 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4891 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4892 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4893 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4895 #endif /* OBJ_ELF */
4897 static void s_arm_arch (int);
4898 static void s_arm_object_arch (int);
4899 static void s_arm_cpu (int);
4900 static void s_arm_fpu (int);
4901 static void s_arm_arch_extension (int);
4906 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4913 if (exp
.X_op
== O_symbol
)
4914 exp
.X_op
= O_secrel
;
4916 emit_expr (&exp
, 4);
4918 while (*input_line_pointer
++ == ',');
4920 input_line_pointer
--;
4921 demand_empty_rest_of_line ();
4925 /* This table describes all the machine specific pseudo-ops the assembler
4926 has to support. The fields are:
4927 pseudo-op name without dot
4928 function to call to execute this pseudo-op
4929 Integer arg to pass to the function. */
4931 const pseudo_typeS md_pseudo_table
[] =
4933 /* Never called because '.req' does not start a line. */
4934 { "req", s_req
, 0 },
4935 /* Following two are likewise never called. */
4938 { "unreq", s_unreq
, 0 },
4939 { "bss", s_bss
, 0 },
4940 { "align", s_align_ptwo
, 2 },
4941 { "arm", s_arm
, 0 },
4942 { "thumb", s_thumb
, 0 },
4943 { "code", s_code
, 0 },
4944 { "force_thumb", s_force_thumb
, 0 },
4945 { "thumb_func", s_thumb_func
, 0 },
4946 { "thumb_set", s_thumb_set
, 0 },
4947 { "even", s_even
, 0 },
4948 { "ltorg", s_ltorg
, 0 },
4949 { "pool", s_ltorg
, 0 },
4950 { "syntax", s_syntax
, 0 },
4951 { "cpu", s_arm_cpu
, 0 },
4952 { "arch", s_arm_arch
, 0 },
4953 { "object_arch", s_arm_object_arch
, 0 },
4954 { "fpu", s_arm_fpu
, 0 },
4955 { "arch_extension", s_arm_arch_extension
, 0 },
4957 { "word", s_arm_elf_cons
, 4 },
4958 { "long", s_arm_elf_cons
, 4 },
4959 { "inst.n", s_arm_elf_inst
, 2 },
4960 { "inst.w", s_arm_elf_inst
, 4 },
4961 { "inst", s_arm_elf_inst
, 0 },
4962 { "rel31", s_arm_rel31
, 0 },
4963 { "fnstart", s_arm_unwind_fnstart
, 0 },
4964 { "fnend", s_arm_unwind_fnend
, 0 },
4965 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4966 { "personality", s_arm_unwind_personality
, 0 },
4967 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4968 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4969 { "save", s_arm_unwind_save
, 0 },
4970 { "vsave", s_arm_unwind_save
, 1 },
4971 { "movsp", s_arm_unwind_movsp
, 0 },
4972 { "pad", s_arm_unwind_pad
, 0 },
4973 { "setfp", s_arm_unwind_setfp
, 0 },
4974 { "unwind_raw", s_arm_unwind_raw
, 0 },
4975 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4976 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4980 /* These are used for dwarf. */
4984 /* These are used for dwarf2. */
4985 { "file", dwarf2_directive_file
, 0 },
4986 { "loc", dwarf2_directive_loc
, 0 },
4987 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4989 { "extend", float_cons
, 'x' },
4990 { "ldouble", float_cons
, 'x' },
4991 { "packed", float_cons
, 'p' },
4993 {"secrel32", pe_directive_secrel
, 0},
4996 /* These are for compatibility with CodeComposer Studio. */
4997 {"ref", s_ccs_ref
, 0},
4998 {"def", s_ccs_def
, 0},
4999 {"asmfunc", s_ccs_asmfunc
, 0},
5000 {"endasmfunc", s_ccs_endasmfunc
, 0},
5005 /* Parser functions used exclusively in instruction operands. */
5007 /* Generic immediate-value read function for use in insn parsing.
5008 STR points to the beginning of the immediate (the leading #);
5009 VAL receives the value; if the value is outside [MIN, MAX]
5010 issue an error. PREFIX_OPT is true if the immediate prefix is
5014 parse_immediate (char **str
, int *val
, int min
, int max
,
5015 bfd_boolean prefix_opt
)
5019 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5020 if (exp
.X_op
!= O_constant
)
5022 inst
.error
= _("constant expression required");
5026 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5028 inst
.error
= _("immediate value out of range");
5032 *val
= exp
.X_add_number
;
5036 /* Less-generic immediate-value read function with the possibility of loading a
5037 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5038 instructions. Puts the result directly in inst.operands[i]. */
5041 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5042 bfd_boolean allow_symbol_p
)
5045 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5048 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5050 if (exp_p
->X_op
== O_constant
)
5052 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5053 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5054 O_constant. We have to be careful not to break compilation for
5055 32-bit X_add_number, though. */
5056 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5058 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5059 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5061 inst
.operands
[i
].regisimm
= 1;
5064 else if (exp_p
->X_op
== O_big
5065 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5067 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5069 /* Bignums have their least significant bits in
5070 generic_bignum[0]. Make sure we put 32 bits in imm and
5071 32 bits in reg, in a (hopefully) portable way. */
5072 gas_assert (parts
!= 0);
5074 /* Make sure that the number is not too big.
5075 PR 11972: Bignums can now be sign-extended to the
5076 size of a .octa so check that the out of range bits
5077 are all zero or all one. */
5078 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5080 LITTLENUM_TYPE m
= -1;
5082 if (generic_bignum
[parts
* 2] != 0
5083 && generic_bignum
[parts
* 2] != m
)
5086 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5087 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5091 inst
.operands
[i
].imm
= 0;
5092 for (j
= 0; j
< parts
; j
++, idx
++)
5093 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5094 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5095 inst
.operands
[i
].reg
= 0;
5096 for (j
= 0; j
< parts
; j
++, idx
++)
5097 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5098 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5099 inst
.operands
[i
].regisimm
= 1;
5101 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5109 /* Returns the pseudo-register number of an FPA immediate constant,
5110 or FAIL if there isn't a valid constant here. */
5113 parse_fpa_immediate (char ** str
)
5115 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5121 /* First try and match exact strings, this is to guarantee
5122 that some formats will work even for cross assembly. */
5124 for (i
= 0; fp_const
[i
]; i
++)
5126 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5130 *str
+= strlen (fp_const
[i
]);
5131 if (is_end_of_line
[(unsigned char) **str
])
5137 /* Just because we didn't get a match doesn't mean that the constant
5138 isn't valid, just that it is in a format that we don't
5139 automatically recognize. Try parsing it with the standard
5140 expression routines. */
5142 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5144 /* Look for a raw floating point number. */
5145 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5146 && is_end_of_line
[(unsigned char) *save_in
])
5148 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5150 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5152 if (words
[j
] != fp_values
[i
][j
])
5156 if (j
== MAX_LITTLENUMS
)
5164 /* Try and parse a more complex expression, this will probably fail
5165 unless the code uses a floating point prefix (eg "0f"). */
5166 save_in
= input_line_pointer
;
5167 input_line_pointer
= *str
;
5168 if (expression (&exp
) == absolute_section
5169 && exp
.X_op
== O_big
5170 && exp
.X_add_number
< 0)
5172 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5174 #define X_PRECISION 5
5175 #define E_PRECISION 15L
5176 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5178 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5180 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5182 if (words
[j
] != fp_values
[i
][j
])
5186 if (j
== MAX_LITTLENUMS
)
5188 *str
= input_line_pointer
;
5189 input_line_pointer
= save_in
;
5196 *str
= input_line_pointer
;
5197 input_line_pointer
= save_in
;
5198 inst
.error
= _("invalid FPA immediate expression");
5202 /* Returns 1 if a number has "quarter-precision" float format
5203 0baBbbbbbc defgh000 00000000 00000000. */
5206 is_quarter_float (unsigned imm
)
5208 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5209 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5213 /* Detect the presence of a floating point or integer zero constant,
5217 parse_ifimm_zero (char **in
)
5221 if (!is_immediate_prefix (**in
))
5223 /* In unified syntax, all prefixes are optional. */
5224 if (!unified_syntax
)
5230 /* Accept #0x0 as a synonym for #0. */
5231 if (strncmp (*in
, "0x", 2) == 0)
5234 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5239 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5240 &generic_floating_point_number
);
5243 && generic_floating_point_number
.sign
== '+'
5244 && (generic_floating_point_number
.low
5245 > generic_floating_point_number
.leader
))
5251 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5252 0baBbbbbbc defgh000 00000000 00000000.
5253 The zero and minus-zero cases need special handling, since they can't be
5254 encoded in the "quarter-precision" float format, but can nonetheless be
5255 loaded as integer constants. */
5258 parse_qfloat_immediate (char **ccp
, int *immed
)
5262 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5263 int found_fpchar
= 0;
5265 skip_past_char (&str
, '#');
5267 /* We must not accidentally parse an integer as a floating-point number. Make
5268 sure that the value we parse is not an integer by checking for special
5269 characters '.' or 'e'.
5270 FIXME: This is a horrible hack, but doing better is tricky because type
5271 information isn't in a very usable state at parse time. */
5273 skip_whitespace (fpnum
);
5275 if (strncmp (fpnum
, "0x", 2) == 0)
5279 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5280 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5290 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5292 unsigned fpword
= 0;
5295 /* Our FP word must be 32 bits (single-precision FP). */
5296 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5298 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5302 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5315 /* Shift operands. */
5318 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5321 struct asm_shift_name
5324 enum shift_kind kind
;
5327 /* Third argument to parse_shift. */
5328 enum parse_shift_mode
5330 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5331 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5332 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5333 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5334 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5335 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5338 /* Parse a <shift> specifier on an ARM data processing instruction.
5339 This has three forms:
5341 (LSL|LSR|ASL|ASR|ROR) Rs
5342 (LSL|LSR|ASL|ASR|ROR) #imm
5345 Note that ASL is assimilated to LSL in the instruction encoding, and
5346 RRX to ROR #0 (which cannot be written as such). */
5349 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5351 const struct asm_shift_name
*shift_name
;
5352 enum shift_kind shift
;
5357 for (p
= *str
; ISALPHA (*p
); p
++)
5362 inst
.error
= _("shift expression expected");
5366 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5369 if (shift_name
== NULL
)
5371 inst
.error
= _("shift expression expected");
5375 shift
= shift_name
->kind
;
5379 case NO_SHIFT_RESTRICT
:
5380 case SHIFT_IMMEDIATE
:
5381 if (shift
== SHIFT_UXTW
)
5383 inst
.error
= _("'UXTW' not allowed here");
5388 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5389 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5391 inst
.error
= _("'LSL' or 'ASR' required");
5396 case SHIFT_LSL_IMMEDIATE
:
5397 if (shift
!= SHIFT_LSL
)
5399 inst
.error
= _("'LSL' required");
5404 case SHIFT_ASR_IMMEDIATE
:
5405 if (shift
!= SHIFT_ASR
)
5407 inst
.error
= _("'ASR' required");
5411 case SHIFT_UXTW_IMMEDIATE
:
5412 if (shift
!= SHIFT_UXTW
)
5414 inst
.error
= _("'UXTW' required");
5422 if (shift
!= SHIFT_RRX
)
5424 /* Whitespace can appear here if the next thing is a bare digit. */
5425 skip_whitespace (p
);
5427 if (mode
== NO_SHIFT_RESTRICT
5428 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5430 inst
.operands
[i
].imm
= reg
;
5431 inst
.operands
[i
].immisreg
= 1;
5433 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5436 inst
.operands
[i
].shift_kind
= shift
;
5437 inst
.operands
[i
].shifted
= 1;
5442 /* Parse a <shifter_operand> for an ARM data processing instruction:
5445 #<immediate>, <rotate>
5449 where <shift> is defined by parse_shift above, and <rotate> is a
5450 multiple of 2 between 0 and 30. Validation of immediate operands
5451 is deferred to md_apply_fix. */
5454 parse_shifter_operand (char **str
, int i
)
5459 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5461 inst
.operands
[i
].reg
= value
;
5462 inst
.operands
[i
].isreg
= 1;
5464 /* parse_shift will override this if appropriate */
5465 inst
.relocs
[0].exp
.X_op
= O_constant
;
5466 inst
.relocs
[0].exp
.X_add_number
= 0;
5468 if (skip_past_comma (str
) == FAIL
)
5471 /* Shift operation on register. */
5472 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5475 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5478 if (skip_past_comma (str
) == SUCCESS
)
5480 /* #x, y -- ie explicit rotation by Y. */
5481 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5484 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5486 inst
.error
= _("constant expression expected");
5490 value
= exp
.X_add_number
;
5491 if (value
< 0 || value
> 30 || value
% 2 != 0)
5493 inst
.error
= _("invalid rotation");
5496 if (inst
.relocs
[0].exp
.X_add_number
< 0
5497 || inst
.relocs
[0].exp
.X_add_number
> 255)
5499 inst
.error
= _("invalid constant");
5503 /* Encode as specified. */
5504 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5508 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5509 inst
.relocs
[0].pc_rel
= 0;
5513 /* Group relocation information. Each entry in the table contains the
5514 textual name of the relocation as may appear in assembler source
5515 and must end with a colon.
5516 Along with this textual name are the relocation codes to be used if
5517 the corresponding instruction is an ALU instruction (ADD or SUB only),
5518 an LDR, an LDRS, or an LDC. */
5520 struct group_reloc_table_entry
5531 /* Varieties of non-ALU group relocation. */
5539 static struct group_reloc_table_entry group_reloc_table
[] =
5540 { /* Program counter relative: */
5542 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5547 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5548 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5549 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5550 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5552 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5557 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5558 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5559 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5560 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5562 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5563 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5564 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5565 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5566 /* Section base relative */
5568 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5573 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5574 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5575 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5576 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5578 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5583 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5584 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5585 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5586 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5588 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5589 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5590 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5591 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5592 /* Absolute thumb alu relocations. */
5594 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5599 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5604 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5609 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5614 /* Given the address of a pointer pointing to the textual name of a group
5615 relocation as may appear in assembler source, attempt to find its details
5616 in group_reloc_table. The pointer will be updated to the character after
5617 the trailing colon. On failure, FAIL will be returned; SUCCESS
5618 otherwise. On success, *entry will be updated to point at the relevant
5619 group_reloc_table entry. */
5622 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5625 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5627 int length
= strlen (group_reloc_table
[i
].name
);
5629 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5630 && (*str
)[length
] == ':')
5632 *out
= &group_reloc_table
[i
];
5633 *str
+= (length
+ 1);
5641 /* Parse a <shifter_operand> for an ARM data processing instruction
5642 (as for parse_shifter_operand) where group relocations are allowed:
5645 #<immediate>, <rotate>
5646 #:<group_reloc>:<expression>
5650 where <group_reloc> is one of the strings defined in group_reloc_table.
5651 The hashes are optional.
5653 Everything else is as for parse_shifter_operand. */
5655 static parse_operand_result
5656 parse_shifter_operand_group_reloc (char **str
, int i
)
5658 /* Determine if we have the sequence of characters #: or just :
5659 coming next. If we do, then we check for a group relocation.
5660 If we don't, punt the whole lot to parse_shifter_operand. */
5662 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5663 || (*str
)[0] == ':')
5665 struct group_reloc_table_entry
*entry
;
5667 if ((*str
)[0] == '#')
5672 /* Try to parse a group relocation. Anything else is an error. */
5673 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5675 inst
.error
= _("unknown group relocation");
5676 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5679 /* We now have the group relocation table entry corresponding to
5680 the name in the assembler source. Next, we parse the expression. */
5681 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5682 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5684 /* Record the relocation type (always the ALU variant here). */
5685 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5686 gas_assert (inst
.relocs
[0].type
!= 0);
5688 return PARSE_OPERAND_SUCCESS
;
5691 return parse_shifter_operand (str
, i
) == SUCCESS
5692 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5694 /* Never reached. */
5697 /* Parse a Neon alignment expression. Information is written to
5698 inst.operands[i]. We assume the initial ':' has been skipped.
5700 align .imm = align << 8, .immisalign=1, .preind=0 */
5701 static parse_operand_result
5702 parse_neon_alignment (char **str
, int i
)
5707 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5709 if (exp
.X_op
!= O_constant
)
5711 inst
.error
= _("alignment must be constant");
5712 return PARSE_OPERAND_FAIL
;
5715 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5716 inst
.operands
[i
].immisalign
= 1;
5717 /* Alignments are not pre-indexes. */
5718 inst
.operands
[i
].preind
= 0;
5721 return PARSE_OPERAND_SUCCESS
;
5724 /* Parse all forms of an ARM address expression. Information is written
5725 to inst.operands[i] and/or inst.relocs[0].
5727 Preindexed addressing (.preind=1):
5729 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5730 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5731 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5732 .shift_kind=shift .relocs[0].exp=shift_imm
5734 These three may have a trailing ! which causes .writeback to be set also.
5736 Postindexed addressing (.postind=1, .writeback=1):
5738 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5739 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5740 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5741 .shift_kind=shift .relocs[0].exp=shift_imm
5743 Unindexed addressing (.preind=0, .postind=0):
5745 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5749 [Rn]{!} shorthand for [Rn,#0]{!}
5750 =immediate .isreg=0 .relocs[0].exp=immediate
5751 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5753 It is the caller's responsibility to check for addressing modes not
5754 supported by the instruction, and to set inst.relocs[0].type. */
5756 static parse_operand_result
5757 parse_address_main (char **str
, int i
, int group_relocations
,
5758 group_reloc_type group_type
)
5763 if (skip_past_char (&p
, '[') == FAIL
)
5765 if (skip_past_char (&p
, '=') == FAIL
)
5767 /* Bare address - translate to PC-relative offset. */
5768 inst
.relocs
[0].pc_rel
= 1;
5769 inst
.operands
[i
].reg
= REG_PC
;
5770 inst
.operands
[i
].isreg
= 1;
5771 inst
.operands
[i
].preind
= 1;
5773 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5774 return PARSE_OPERAND_FAIL
;
5776 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5777 /*allow_symbol_p=*/TRUE
))
5778 return PARSE_OPERAND_FAIL
;
5781 return PARSE_OPERAND_SUCCESS
;
5784 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5785 skip_whitespace (p
);
5787 if (group_type
== GROUP_MVE
)
5789 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5790 struct neon_type_el et
;
5791 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5793 inst
.operands
[i
].isquad
= 1;
5795 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5797 inst
.error
= BAD_ADDR_MODE
;
5798 return PARSE_OPERAND_FAIL
;
5801 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5803 if (group_type
== GROUP_MVE
)
5804 inst
.error
= BAD_ADDR_MODE
;
5806 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5807 return PARSE_OPERAND_FAIL
;
5809 inst
.operands
[i
].reg
= reg
;
5810 inst
.operands
[i
].isreg
= 1;
5812 if (skip_past_comma (&p
) == SUCCESS
)
5814 inst
.operands
[i
].preind
= 1;
5817 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5819 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5820 struct neon_type_el et
;
5821 if (group_type
== GROUP_MVE
5822 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5824 inst
.operands
[i
].immisreg
= 2;
5825 inst
.operands
[i
].imm
= reg
;
5827 if (skip_past_comma (&p
) == SUCCESS
)
5829 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
5831 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
5832 inst
.relocs
[0].exp
.X_add_number
= 0;
5835 return PARSE_OPERAND_FAIL
;
5838 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5840 inst
.operands
[i
].imm
= reg
;
5841 inst
.operands
[i
].immisreg
= 1;
5843 if (skip_past_comma (&p
) == SUCCESS
)
5844 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5845 return PARSE_OPERAND_FAIL
;
5847 else if (skip_past_char (&p
, ':') == SUCCESS
)
5849 /* FIXME: '@' should be used here, but it's filtered out by generic
5850 code before we get to see it here. This may be subject to
5852 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5854 if (result
!= PARSE_OPERAND_SUCCESS
)
5859 if (inst
.operands
[i
].negative
)
5861 inst
.operands
[i
].negative
= 0;
5865 if (group_relocations
5866 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5868 struct group_reloc_table_entry
*entry
;
5870 /* Skip over the #: or : sequence. */
5876 /* Try to parse a group relocation. Anything else is an
5878 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5880 inst
.error
= _("unknown group relocation");
5881 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5884 /* We now have the group relocation table entry corresponding to
5885 the name in the assembler source. Next, we parse the
5887 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5888 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5890 /* Record the relocation type. */
5895 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5900 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5905 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5912 if (inst
.relocs
[0].type
== 0)
5914 inst
.error
= _("this group relocation is not allowed on this instruction");
5915 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5922 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5923 return PARSE_OPERAND_FAIL
;
5924 /* If the offset is 0, find out if it's a +0 or -0. */
5925 if (inst
.relocs
[0].exp
.X_op
== O_constant
5926 && inst
.relocs
[0].exp
.X_add_number
== 0)
5928 skip_whitespace (q
);
5932 skip_whitespace (q
);
5935 inst
.operands
[i
].negative
= 1;
5940 else if (skip_past_char (&p
, ':') == SUCCESS
)
5942 /* FIXME: '@' should be used here, but it's filtered out by generic code
5943 before we get to see it here. This may be subject to change. */
5944 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5946 if (result
!= PARSE_OPERAND_SUCCESS
)
5950 if (skip_past_char (&p
, ']') == FAIL
)
5952 inst
.error
= _("']' expected");
5953 return PARSE_OPERAND_FAIL
;
5956 if (skip_past_char (&p
, '!') == SUCCESS
)
5957 inst
.operands
[i
].writeback
= 1;
5959 else if (skip_past_comma (&p
) == SUCCESS
)
5961 if (skip_past_char (&p
, '{') == SUCCESS
)
5963 /* [Rn], {expr} - unindexed, with option */
5964 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5965 0, 255, TRUE
) == FAIL
)
5966 return PARSE_OPERAND_FAIL
;
5968 if (skip_past_char (&p
, '}') == FAIL
)
5970 inst
.error
= _("'}' expected at end of 'option' field");
5971 return PARSE_OPERAND_FAIL
;
5973 if (inst
.operands
[i
].preind
)
5975 inst
.error
= _("cannot combine index with option");
5976 return PARSE_OPERAND_FAIL
;
5979 return PARSE_OPERAND_SUCCESS
;
5983 inst
.operands
[i
].postind
= 1;
5984 inst
.operands
[i
].writeback
= 1;
5986 if (inst
.operands
[i
].preind
)
5988 inst
.error
= _("cannot combine pre- and post-indexing");
5989 return PARSE_OPERAND_FAIL
;
5993 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5995 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5996 struct neon_type_el et
;
5997 if (group_type
== GROUP_MVE
5998 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6000 inst
.operands
[i
].immisreg
= 2;
6001 inst
.operands
[i
].imm
= reg
;
6003 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6005 /* We might be using the immediate for alignment already. If we
6006 are, OR the register number into the low-order bits. */
6007 if (inst
.operands
[i
].immisalign
)
6008 inst
.operands
[i
].imm
|= reg
;
6010 inst
.operands
[i
].imm
= reg
;
6011 inst
.operands
[i
].immisreg
= 1;
6013 if (skip_past_comma (&p
) == SUCCESS
)
6014 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6015 return PARSE_OPERAND_FAIL
;
6021 if (inst
.operands
[i
].negative
)
6023 inst
.operands
[i
].negative
= 0;
6026 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6027 return PARSE_OPERAND_FAIL
;
6028 /* If the offset is 0, find out if it's a +0 or -0. */
6029 if (inst
.relocs
[0].exp
.X_op
== O_constant
6030 && inst
.relocs
[0].exp
.X_add_number
== 0)
6032 skip_whitespace (q
);
6036 skip_whitespace (q
);
6039 inst
.operands
[i
].negative
= 1;
6045 /* If at this point neither .preind nor .postind is set, we have a
6046 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6047 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6049 inst
.operands
[i
].preind
= 1;
6050 inst
.relocs
[0].exp
.X_op
= O_constant
;
6051 inst
.relocs
[0].exp
.X_add_number
= 0;
6054 return PARSE_OPERAND_SUCCESS
;
6058 parse_address (char **str
, int i
)
6060 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6064 static parse_operand_result
6065 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6067 return parse_address_main (str
, i
, 1, type
);
6070 /* Parse an operand for a MOVW or MOVT instruction. */
6072 parse_half (char **str
)
6077 skip_past_char (&p
, '#');
6078 if (strncasecmp (p
, ":lower16:", 9) == 0)
6079 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6080 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6081 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6083 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6086 skip_whitespace (p
);
6089 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6092 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6094 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6096 inst
.error
= _("constant expression expected");
6099 if (inst
.relocs
[0].exp
.X_add_number
< 0
6100 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6102 inst
.error
= _("immediate value out of range");
6110 /* Miscellaneous. */
6112 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6113 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6115 parse_psr (char **str
, bfd_boolean lhs
)
6118 unsigned long psr_field
;
6119 const struct asm_psr
*psr
;
6121 bfd_boolean is_apsr
= FALSE
;
6122 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6124 /* PR gas/12698: If the user has specified -march=all then m_profile will
6125 be TRUE, but we want to ignore it in this case as we are building for any
6126 CPU type, including non-m variants. */
6127 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6130 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6131 feature for ease of use and backwards compatibility. */
6133 if (strncasecmp (p
, "SPSR", 4) == 0)
6136 goto unsupported_psr
;
6138 psr_field
= SPSR_BIT
;
6140 else if (strncasecmp (p
, "CPSR", 4) == 0)
6143 goto unsupported_psr
;
6147 else if (strncasecmp (p
, "APSR", 4) == 0)
6149 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6150 and ARMv7-R architecture CPUs. */
6159 while (ISALNUM (*p
) || *p
== '_');
6161 if (strncasecmp (start
, "iapsr", 5) == 0
6162 || strncasecmp (start
, "eapsr", 5) == 0
6163 || strncasecmp (start
, "xpsr", 4) == 0
6164 || strncasecmp (start
, "psr", 3) == 0)
6165 p
= start
+ strcspn (start
, "rR") + 1;
6167 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6173 /* If APSR is being written, a bitfield may be specified. Note that
6174 APSR itself is handled above. */
6175 if (psr
->field
<= 3)
6177 psr_field
= psr
->field
;
6183 /* M-profile MSR instructions have the mask field set to "10", except
6184 *PSR variants which modify APSR, which may use a different mask (and
6185 have been handled already). Do that by setting the PSR_f field
6187 return psr
->field
| (lhs
? PSR_f
: 0);
6190 goto unsupported_psr
;
6196 /* A suffix follows. */
6202 while (ISALNUM (*p
) || *p
== '_');
6206 /* APSR uses a notation for bits, rather than fields. */
6207 unsigned int nzcvq_bits
= 0;
6208 unsigned int g_bit
= 0;
6211 for (bit
= start
; bit
!= p
; bit
++)
6213 switch (TOLOWER (*bit
))
6216 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6220 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6224 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6228 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6232 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6236 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6240 inst
.error
= _("unexpected bit specified after APSR");
6245 if (nzcvq_bits
== 0x1f)
6250 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6252 inst
.error
= _("selected processor does not "
6253 "support DSP extension");
6260 if ((nzcvq_bits
& 0x20) != 0
6261 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6262 || (g_bit
& 0x2) != 0)
6264 inst
.error
= _("bad bitmask specified after APSR");
6270 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6275 psr_field
|= psr
->field
;
6281 goto error
; /* Garbage after "[CS]PSR". */
6283 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6284 is deprecated, but allow it anyway. */
6288 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6291 else if (!m_profile
)
6292 /* These bits are never right for M-profile devices: don't set them
6293 (only code paths which read/write APSR reach here). */
6294 psr_field
|= (PSR_c
| PSR_f
);
6300 inst
.error
= _("selected processor does not support requested special "
6301 "purpose register");
6305 inst
.error
= _("flag for {c}psr instruction expected");
6310 parse_sys_vldr_vstr (char **str
)
6319 {"FPSCR", 0x1, 0x0},
6320 {"FPSCR_nzcvqc", 0x2, 0x0},
6323 {"FPCXTNS", 0x6, 0x1},
6324 {"FPCXTS", 0x7, 0x1}
6326 char *op_end
= strchr (*str
, ',');
6327 size_t op_strlen
= op_end
- *str
;
6329 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6331 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6333 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6342 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6343 value suitable for splatting into the AIF field of the instruction. */
6346 parse_cps_flags (char **str
)
6355 case '\0': case ',':
6358 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6359 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6360 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6363 inst
.error
= _("unrecognized CPS flag");
6368 if (saw_a_flag
== 0)
6370 inst
.error
= _("missing CPS flags");
6378 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6379 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6382 parse_endian_specifier (char **str
)
6387 if (strncasecmp (s
, "BE", 2))
6389 else if (strncasecmp (s
, "LE", 2))
6393 inst
.error
= _("valid endian specifiers are be or le");
6397 if (ISALNUM (s
[2]) || s
[2] == '_')
6399 inst
.error
= _("valid endian specifiers are be or le");
6404 return little_endian
;
6407 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6408 value suitable for poking into the rotate field of an sxt or sxta
6409 instruction, or FAIL on error. */
6412 parse_ror (char **str
)
6417 if (strncasecmp (s
, "ROR", 3) == 0)
6421 inst
.error
= _("missing rotation field after comma");
6425 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6430 case 0: *str
= s
; return 0x0;
6431 case 8: *str
= s
; return 0x1;
6432 case 16: *str
= s
; return 0x2;
6433 case 24: *str
= s
; return 0x3;
6436 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6441 /* Parse a conditional code (from conds[] below). The value returned is in the
6442 range 0 .. 14, or FAIL. */
6444 parse_cond (char **str
)
6447 const struct asm_cond
*c
;
6449 /* Condition codes are always 2 characters, so matching up to
6450 3 characters is sufficient. */
6455 while (ISALPHA (*q
) && n
< 3)
6457 cond
[n
] = TOLOWER (*q
);
6462 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6465 inst
.error
= _("condition required");
6473 /* Parse an option for a barrier instruction. Returns the encoding for the
6476 parse_barrier (char **str
)
6479 const struct asm_barrier_opt
*o
;
6482 while (ISALPHA (*q
))
6485 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6490 if (!mark_feature_used (&o
->arch
))
6497 /* Parse the operands of a table branch instruction. Similar to a memory
6500 parse_tb (char **str
)
6505 if (skip_past_char (&p
, '[') == FAIL
)
6507 inst
.error
= _("'[' expected");
6511 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6513 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6516 inst
.operands
[0].reg
= reg
;
6518 if (skip_past_comma (&p
) == FAIL
)
6520 inst
.error
= _("',' expected");
6524 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6526 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6529 inst
.operands
[0].imm
= reg
;
6531 if (skip_past_comma (&p
) == SUCCESS
)
6533 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6535 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6537 inst
.error
= _("invalid shift");
6540 inst
.operands
[0].shifted
= 1;
6543 if (skip_past_char (&p
, ']') == FAIL
)
6545 inst
.error
= _("']' expected");
6552 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6553 information on the types the operands can take and how they are encoded.
6554 Up to four operands may be read; this function handles setting the
6555 ".present" field for each read operand itself.
6556 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6557 else returns FAIL. */
6560 parse_neon_mov (char **str
, int *which_operand
)
6562 int i
= *which_operand
, val
;
6563 enum arm_reg_type rtype
;
6565 struct neon_type_el optype
;
6567 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6569 /* Cases 17 or 19. */
6570 inst
.operands
[i
].reg
= val
;
6571 inst
.operands
[i
].isvec
= 1;
6572 inst
.operands
[i
].isscalar
= 2;
6573 inst
.operands
[i
].vectype
= optype
;
6574 inst
.operands
[i
++].present
= 1;
6576 if (skip_past_comma (&ptr
) == FAIL
)
6579 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6581 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6582 inst
.operands
[i
].reg
= val
;
6583 inst
.operands
[i
].isreg
= 1;
6584 inst
.operands
[i
].present
= 1;
6586 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6588 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6589 inst
.operands
[i
].reg
= val
;
6590 inst
.operands
[i
].isvec
= 1;
6591 inst
.operands
[i
].isscalar
= 2;
6592 inst
.operands
[i
].vectype
= optype
;
6593 inst
.operands
[i
++].present
= 1;
6595 if (skip_past_comma (&ptr
) == FAIL
)
6598 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6601 inst
.operands
[i
].reg
= val
;
6602 inst
.operands
[i
].isreg
= 1;
6603 inst
.operands
[i
++].present
= 1;
6605 if (skip_past_comma (&ptr
) == FAIL
)
6608 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6611 inst
.operands
[i
].reg
= val
;
6612 inst
.operands
[i
].isreg
= 1;
6613 inst
.operands
[i
].present
= 1;
6617 first_error (_("expected ARM or MVE vector register"));
6621 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6623 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6624 inst
.operands
[i
].reg
= val
;
6625 inst
.operands
[i
].isscalar
= 1;
6626 inst
.operands
[i
].vectype
= optype
;
6627 inst
.operands
[i
++].present
= 1;
6629 if (skip_past_comma (&ptr
) == FAIL
)
6632 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6635 inst
.operands
[i
].reg
= val
;
6636 inst
.operands
[i
].isreg
= 1;
6637 inst
.operands
[i
].present
= 1;
6639 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6641 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6644 /* Cases 0, 1, 2, 3, 5 (D only). */
6645 if (skip_past_comma (&ptr
) == FAIL
)
6648 inst
.operands
[i
].reg
= val
;
6649 inst
.operands
[i
].isreg
= 1;
6650 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6651 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6652 inst
.operands
[i
].isvec
= 1;
6653 inst
.operands
[i
].vectype
= optype
;
6654 inst
.operands
[i
++].present
= 1;
6656 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6658 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6659 Case 13: VMOV <Sd>, <Rm> */
6660 inst
.operands
[i
].reg
= val
;
6661 inst
.operands
[i
].isreg
= 1;
6662 inst
.operands
[i
].present
= 1;
6664 if (rtype
== REG_TYPE_NQ
)
6666 first_error (_("can't use Neon quad register here"));
6669 else if (rtype
!= REG_TYPE_VFS
)
6672 if (skip_past_comma (&ptr
) == FAIL
)
6674 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6676 inst
.operands
[i
].reg
= val
;
6677 inst
.operands
[i
].isreg
= 1;
6678 inst
.operands
[i
].present
= 1;
6681 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6684 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6685 Case 1: VMOV<c><q> <Dd>, <Dm>
6686 Case 8: VMOV.F32 <Sd>, <Sm>
6687 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6689 inst
.operands
[i
].reg
= val
;
6690 inst
.operands
[i
].isreg
= 1;
6691 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6692 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6693 inst
.operands
[i
].isvec
= 1;
6694 inst
.operands
[i
].vectype
= optype
;
6695 inst
.operands
[i
].present
= 1;
6697 if (skip_past_comma (&ptr
) == SUCCESS
)
6702 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6705 inst
.operands
[i
].reg
= val
;
6706 inst
.operands
[i
].isreg
= 1;
6707 inst
.operands
[i
++].present
= 1;
6709 if (skip_past_comma (&ptr
) == FAIL
)
6712 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6715 inst
.operands
[i
].reg
= val
;
6716 inst
.operands
[i
].isreg
= 1;
6717 inst
.operands
[i
].present
= 1;
6720 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6721 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6722 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6723 Case 10: VMOV.F32 <Sd>, #<imm>
6724 Case 11: VMOV.F64 <Dd>, #<imm> */
6725 inst
.operands
[i
].immisfloat
= 1;
6726 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6728 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6729 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6733 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6737 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6739 /* Cases 6, 7, 16, 18. */
6740 inst
.operands
[i
].reg
= val
;
6741 inst
.operands
[i
].isreg
= 1;
6742 inst
.operands
[i
++].present
= 1;
6744 if (skip_past_comma (&ptr
) == FAIL
)
6747 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6749 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6750 inst
.operands
[i
].reg
= val
;
6751 inst
.operands
[i
].isscalar
= 2;
6752 inst
.operands
[i
].present
= 1;
6753 inst
.operands
[i
].vectype
= optype
;
6755 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6757 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6758 inst
.operands
[i
].reg
= val
;
6759 inst
.operands
[i
].isscalar
= 1;
6760 inst
.operands
[i
].present
= 1;
6761 inst
.operands
[i
].vectype
= optype
;
6763 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6765 inst
.operands
[i
].reg
= val
;
6766 inst
.operands
[i
].isreg
= 1;
6767 inst
.operands
[i
++].present
= 1;
6769 if (skip_past_comma (&ptr
) == FAIL
)
6772 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6775 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6777 inst
.operands
[i
].reg
= val
;
6778 inst
.operands
[i
].isreg
= 1;
6779 inst
.operands
[i
].isvec
= 1;
6780 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6781 inst
.operands
[i
].vectype
= optype
;
6782 inst
.operands
[i
].present
= 1;
6784 if (rtype
== REG_TYPE_VFS
)
6788 if (skip_past_comma (&ptr
) == FAIL
)
6790 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6793 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6796 inst
.operands
[i
].reg
= val
;
6797 inst
.operands
[i
].isreg
= 1;
6798 inst
.operands
[i
].isvec
= 1;
6799 inst
.operands
[i
].issingle
= 1;
6800 inst
.operands
[i
].vectype
= optype
;
6801 inst
.operands
[i
].present
= 1;
6806 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6809 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6810 inst
.operands
[i
].reg
= val
;
6811 inst
.operands
[i
].isvec
= 1;
6812 inst
.operands
[i
].isscalar
= 2;
6813 inst
.operands
[i
].vectype
= optype
;
6814 inst
.operands
[i
++].present
= 1;
6816 if (skip_past_comma (&ptr
) == FAIL
)
6819 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6822 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
6825 inst
.operands
[i
].reg
= val
;
6826 inst
.operands
[i
].isvec
= 1;
6827 inst
.operands
[i
].isscalar
= 2;
6828 inst
.operands
[i
].vectype
= optype
;
6829 inst
.operands
[i
].present
= 1;
6833 first_error (_("VFP single, double or MVE vector register"
6839 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6843 inst
.operands
[i
].reg
= val
;
6844 inst
.operands
[i
].isreg
= 1;
6845 inst
.operands
[i
].isvec
= 1;
6846 inst
.operands
[i
].issingle
= 1;
6847 inst
.operands
[i
].vectype
= optype
;
6848 inst
.operands
[i
].present
= 1;
6853 first_error (_("parse error"));
6857 /* Successfully parsed the operands. Update args. */
6863 first_error (_("expected comma"));
6867 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6871 /* Use this macro when the operand constraints are different
6872 for ARM and THUMB (e.g. ldrd). */
6873 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6874 ((arm_operand) | ((thumb_operand) << 16))
6876 /* Matcher codes for parse_operands. */
6877 enum operand_parse_code
6879 OP_stop
, /* end of line */
6881 OP_RR
, /* ARM register */
6882 OP_RRnpc
, /* ARM register, not r15 */
6883 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6884 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6885 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6886 optional trailing ! */
6887 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6888 OP_RCP
, /* Coprocessor number */
6889 OP_RCN
, /* Coprocessor register */
6890 OP_RF
, /* FPA register */
6891 OP_RVS
, /* VFP single precision register */
6892 OP_RVD
, /* VFP double precision register (0..15) */
6893 OP_RND
, /* Neon double precision register (0..31) */
6894 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
6895 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
6897 OP_RNQ
, /* Neon quad precision register */
6898 OP_RNQMQ
, /* Neon quad or MVE vector register. */
6899 OP_RVSD
, /* VFP single or double precision register */
6900 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
6901 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
6902 OP_RNSD
, /* Neon single or double precision register */
6903 OP_RNDQ
, /* Neon double or quad precision register */
6904 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
6905 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
6906 OP_RNSDQ
, /* Neon single, double or quad precision register */
6907 OP_RNSC
, /* Neon scalar D[X] */
6908 OP_RVC
, /* VFP control register */
6909 OP_RMF
, /* Maverick F register */
6910 OP_RMD
, /* Maverick D register */
6911 OP_RMFX
, /* Maverick FX register */
6912 OP_RMDX
, /* Maverick DX register */
6913 OP_RMAX
, /* Maverick AX register */
6914 OP_RMDS
, /* Maverick DSPSC register */
6915 OP_RIWR
, /* iWMMXt wR register */
6916 OP_RIWC
, /* iWMMXt wC register */
6917 OP_RIWG
, /* iWMMXt wCG register */
6918 OP_RXA
, /* XScale accumulator register */
6920 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
6922 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
6924 OP_RMQ
, /* MVE vector register. */
6925 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
6926 OP_RMQRR
, /* MVE vector or ARM register. */
6928 /* New operands for Armv8.1-M Mainline. */
6929 OP_LR
, /* ARM LR register */
6930 OP_RRe
, /* ARM register, only even numbered. */
6931 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
6932 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
6934 OP_REGLST
, /* ARM register list */
6935 OP_CLRMLST
, /* CLRM register list */
6936 OP_VRSLST
, /* VFP single-precision register list */
6937 OP_VRDLST
, /* VFP double-precision register list */
6938 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6939 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6940 OP_NSTRLST
, /* Neon element/structure list */
6941 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
6942 OP_MSTRLST2
, /* MVE vector list with two elements. */
6943 OP_MSTRLST4
, /* MVE vector list with four elements. */
6945 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6946 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6947 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6948 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
6950 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6951 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6952 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6953 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
6955 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
6956 scalar, or ARM register. */
6957 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6958 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
6959 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
6961 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
6962 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6963 OP_VMOV
, /* Neon VMOV operands. */
6964 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6965 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
6967 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6968 OP_RNDQMQ_I63b_RR
, /* Neon D or Q reg, immediate for shift, MVE vector or
6970 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6971 OP_VLDR
, /* VLDR operand. */
6973 OP_I0
, /* immediate zero */
6974 OP_I7
, /* immediate value 0 .. 7 */
6975 OP_I15
, /* 0 .. 15 */
6976 OP_I16
, /* 1 .. 16 */
6977 OP_I16z
, /* 0 .. 16 */
6978 OP_I31
, /* 0 .. 31 */
6979 OP_I31w
, /* 0 .. 31, optional trailing ! */
6980 OP_I32
, /* 1 .. 32 */
6981 OP_I32z
, /* 0 .. 32 */
6982 OP_I63
, /* 0 .. 63 */
6983 OP_I63s
, /* -64 .. 63 */
6984 OP_I64
, /* 1 .. 64 */
6985 OP_I64z
, /* 0 .. 64 */
6986 OP_I255
, /* 0 .. 255 */
6988 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6989 OP_I7b
, /* 0 .. 7 */
6990 OP_I15b
, /* 0 .. 15 */
6991 OP_I31b
, /* 0 .. 31 */
6993 OP_SH
, /* shifter operand */
6994 OP_SHG
, /* shifter operand with possible group relocation */
6995 OP_ADDR
, /* Memory address expression (any mode) */
6996 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
6997 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6998 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6999 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
7000 OP_EXP
, /* arbitrary expression */
7001 OP_EXPi
, /* same, with optional immediate prefix */
7002 OP_EXPr
, /* same, with optional relocation suffix */
7003 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7004 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7005 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7006 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7008 OP_CPSF
, /* CPS flags */
7009 OP_ENDI
, /* Endianness specifier */
7010 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7011 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7012 OP_COND
, /* conditional code */
7013 OP_TB
, /* Table branch. */
7015 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7017 OP_RRnpc_I0
, /* ARM register or literal 0 */
7018 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7019 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7020 OP_RF_IF
, /* FPA register or immediate */
7021 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7022 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7024 /* Optional operands. */
7025 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7026 OP_oI31b
, /* 0 .. 31 */
7027 OP_oI32b
, /* 1 .. 32 */
7028 OP_oI32z
, /* 0 .. 32 */
7029 OP_oIffffb
, /* 0 .. 65535 */
7030 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7032 OP_oRR
, /* ARM register */
7033 OP_oLR
, /* ARM LR register */
7034 OP_oRRnpc
, /* ARM register, not the PC */
7035 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7036 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7037 OP_oRND
, /* Optional Neon double precision register */
7038 OP_oRNQ
, /* Optional Neon quad precision register */
7039 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7040 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7041 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7042 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7044 OP_oSHll
, /* LSL immediate */
7045 OP_oSHar
, /* ASR immediate */
7046 OP_oSHllar
, /* LSL or ASR immediate */
7047 OP_oROR
, /* ROR 0/8/16/24 */
7048 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7050 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7052 /* Some pre-defined mixed (ARM/THUMB) operands. */
7053 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7054 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7055 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7057 OP_FIRST_OPTIONAL
= OP_oI7b
7060 /* Generic instruction operand parser. This does no encoding and no
7061 semantic validation; it merely squirrels values away in the inst
7062 structure. Returns SUCCESS or FAIL depending on whether the
7063 specified grammar matched. */
7065 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7067 unsigned const int *upat
= pattern
;
7068 char *backtrack_pos
= 0;
7069 const char *backtrack_error
= 0;
7070 int i
, val
= 0, backtrack_index
= 0;
7071 enum arm_reg_type rtype
;
7072 parse_operand_result result
;
7073 unsigned int op_parse_code
;
7074 bfd_boolean partial_match
;
7076 #define po_char_or_fail(chr) \
7079 if (skip_past_char (&str, chr) == FAIL) \
7084 #define po_reg_or_fail(regtype) \
7087 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7088 & inst.operands[i].vectype); \
7091 first_error (_(reg_expected_msgs[regtype])); \
7094 inst.operands[i].reg = val; \
7095 inst.operands[i].isreg = 1; \
7096 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7097 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7098 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7099 || rtype == REG_TYPE_VFD \
7100 || rtype == REG_TYPE_NQ); \
7101 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7105 #define po_reg_or_goto(regtype, label) \
7108 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7109 & inst.operands[i].vectype); \
7113 inst.operands[i].reg = val; \
7114 inst.operands[i].isreg = 1; \
7115 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7116 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7117 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7118 || rtype == REG_TYPE_VFD \
7119 || rtype == REG_TYPE_NQ); \
7120 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7124 #define po_imm_or_fail(min, max, popt) \
7127 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7129 inst.operands[i].imm = val; \
7133 #define po_scalar_or_goto(elsz, label, reg_type) \
7136 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7140 inst.operands[i].reg = val; \
7141 inst.operands[i].isscalar = 1; \
7145 #define po_misc_or_fail(expr) \
7153 #define po_misc_or_fail_no_backtrack(expr) \
7157 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7158 backtrack_pos = 0; \
7159 if (result != PARSE_OPERAND_SUCCESS) \
7164 #define po_barrier_or_imm(str) \
7167 val = parse_barrier (&str); \
7168 if (val == FAIL && ! ISALPHA (*str)) \
7171 /* ISB can only take SY as an option. */ \
7172 || ((inst.instruction & 0xf0) == 0x60 \
7175 inst.error = _("invalid barrier type"); \
7176 backtrack_pos = 0; \
7182 skip_whitespace (str
);
7184 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7186 op_parse_code
= upat
[i
];
7187 if (op_parse_code
>= 1<<16)
7188 op_parse_code
= thumb
? (op_parse_code
>> 16)
7189 : (op_parse_code
& ((1<<16)-1));
7191 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7193 /* Remember where we are in case we need to backtrack. */
7194 backtrack_pos
= str
;
7195 backtrack_error
= inst
.error
;
7196 backtrack_index
= i
;
7199 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7200 po_char_or_fail (',');
7202 switch (op_parse_code
)
7214 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7215 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7216 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7217 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7218 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7219 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7222 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7226 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7229 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7231 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7233 /* Also accept generic coprocessor regs for unknown registers. */
7235 po_reg_or_fail (REG_TYPE_CN
);
7237 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7238 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7239 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7240 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7241 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7242 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7243 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7244 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7245 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7246 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7249 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7252 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7253 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7255 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7260 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7264 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7266 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7269 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7271 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7274 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7276 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7281 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7284 po_reg_or_fail (REG_TYPE_NSDQ
);
7288 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7292 po_reg_or_fail (REG_TYPE_MQ
);
7294 /* Neon scalar. Using an element size of 8 means that some invalid
7295 scalars are accepted here, so deal with those in later code. */
7296 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7300 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7303 po_imm_or_fail (0, 0, TRUE
);
7308 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7312 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7317 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7320 if (parse_ifimm_zero (&str
))
7321 inst
.operands
[i
].imm
= 0;
7325 = _("only floating point zero is allowed as immediate value");
7333 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7336 po_reg_or_fail (REG_TYPE_RN
);
7340 case OP_RNSDQ_RNSC_MQ_RR
:
7341 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7344 case OP_RNSDQ_RNSC_MQ
:
7345 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7350 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7354 po_reg_or_fail (REG_TYPE_NSDQ
);
7361 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7364 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7367 po_reg_or_fail (REG_TYPE_NSD
);
7371 case OP_RNDQMQ_RNSC_RR
:
7372 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7375 case OP_RNDQ_RNSC_RR
:
7376 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7378 case OP_RNDQMQ_RNSC
:
7379 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7384 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7387 po_reg_or_fail (REG_TYPE_NDQ
);
7393 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7396 po_reg_or_fail (REG_TYPE_VFD
);
7401 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7402 not careful then bad things might happen. */
7403 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7406 case OP_RNDQMQ_Ibig
:
7407 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7412 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7415 /* There's a possibility of getting a 64-bit immediate here, so
7416 we need special handling. */
7417 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7420 inst
.error
= _("immediate value is out of range");
7426 case OP_RNDQMQ_I63b_RR
:
7427 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_i63b_rr
);
7430 po_reg_or_goto (REG_TYPE_RN
, try_rndq_i63b
);
7435 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7438 po_imm_or_fail (0, 63, TRUE
);
7443 po_char_or_fail ('[');
7444 po_reg_or_fail (REG_TYPE_RN
);
7445 po_char_or_fail (']');
7451 po_reg_or_fail (REG_TYPE_RN
);
7452 if (skip_past_char (&str
, '!') == SUCCESS
)
7453 inst
.operands
[i
].writeback
= 1;
7457 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7458 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7459 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7460 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7461 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7462 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7463 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7464 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7465 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7466 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7467 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7468 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7470 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7472 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7473 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7475 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7476 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7477 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7478 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7480 /* Immediate variants */
7482 po_char_or_fail ('{');
7483 po_imm_or_fail (0, 255, TRUE
);
7484 po_char_or_fail ('}');
7488 /* The expression parser chokes on a trailing !, so we have
7489 to find it first and zap it. */
7492 while (*s
&& *s
!= ',')
7497 inst
.operands
[i
].writeback
= 1;
7499 po_imm_or_fail (0, 31, TRUE
);
7507 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7512 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7517 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7519 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7521 val
= parse_reloc (&str
);
7524 inst
.error
= _("unrecognized relocation suffix");
7527 else if (val
!= BFD_RELOC_UNUSED
)
7529 inst
.operands
[i
].imm
= val
;
7530 inst
.operands
[i
].hasreloc
= 1;
7536 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7538 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7540 inst
.operands
[i
].hasreloc
= 1;
7542 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7544 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7545 inst
.operands
[i
].hasreloc
= 0;
7549 /* Operand for MOVW or MOVT. */
7551 po_misc_or_fail (parse_half (&str
));
7554 /* Register or expression. */
7555 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7556 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7558 /* Register or immediate. */
7559 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7560 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7562 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7564 if (!is_immediate_prefix (*str
))
7567 val
= parse_fpa_immediate (&str
);
7570 /* FPA immediates are encoded as registers 8-15.
7571 parse_fpa_immediate has already applied the offset. */
7572 inst
.operands
[i
].reg
= val
;
7573 inst
.operands
[i
].isreg
= 1;
7576 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7577 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7579 /* Two kinds of register. */
7582 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7584 || (rege
->type
!= REG_TYPE_MMXWR
7585 && rege
->type
!= REG_TYPE_MMXWC
7586 && rege
->type
!= REG_TYPE_MMXWCG
))
7588 inst
.error
= _("iWMMXt data or control register expected");
7591 inst
.operands
[i
].reg
= rege
->number
;
7592 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7598 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7600 || (rege
->type
!= REG_TYPE_MMXWC
7601 && rege
->type
!= REG_TYPE_MMXWCG
))
7603 inst
.error
= _("iWMMXt control register expected");
7606 inst
.operands
[i
].reg
= rege
->number
;
7607 inst
.operands
[i
].isreg
= 1;
7612 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7613 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7614 case OP_oROR
: val
= parse_ror (&str
); break;
7616 case OP_COND
: val
= parse_cond (&str
); break;
7617 case OP_oBARRIER_I15
:
7618 po_barrier_or_imm (str
); break;
7620 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7626 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7627 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7629 inst
.error
= _("Banked registers are not available with this "
7635 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7639 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7642 val
= parse_sys_vldr_vstr (&str
);
7646 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7649 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7651 if (strncasecmp (str
, "APSR_", 5) == 0)
7658 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7659 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7660 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7661 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7662 default: found
= 16;
7666 inst
.operands
[i
].isvec
= 1;
7667 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7668 inst
.operands
[i
].reg
= REG_PC
;
7675 po_misc_or_fail (parse_tb (&str
));
7678 /* Register lists. */
7680 val
= parse_reg_list (&str
, REGLIST_RN
);
7683 inst
.operands
[i
].writeback
= 1;
7689 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7693 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7698 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7703 /* Allow Q registers too. */
7704 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7705 REGLIST_NEON_D
, &partial_match
);
7709 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7710 REGLIST_VFP_S
, &partial_match
);
7711 inst
.operands
[i
].issingle
= 1;
7716 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7717 REGLIST_VFP_D_VPR
, &partial_match
);
7718 if (val
== FAIL
&& !partial_match
)
7721 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7722 REGLIST_VFP_S_VPR
, &partial_match
);
7723 inst
.operands
[i
].issingle
= 1;
7728 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7729 REGLIST_NEON_D
, &partial_match
);
7734 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7735 1, &inst
.operands
[i
].vectype
);
7736 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7740 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7741 0, &inst
.operands
[i
].vectype
);
7744 /* Addressing modes */
7746 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7750 po_misc_or_fail (parse_address (&str
, i
));
7754 po_misc_or_fail_no_backtrack (
7755 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7759 po_misc_or_fail_no_backtrack (
7760 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7764 po_misc_or_fail_no_backtrack (
7765 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7769 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7773 po_misc_or_fail_no_backtrack (
7774 parse_shifter_operand_group_reloc (&str
, i
));
7778 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7782 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7786 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7791 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
7794 po_reg_or_goto (REG_TYPE_RN
, ZR
);
7797 po_reg_or_fail (REG_TYPE_ZR
);
7801 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7804 /* Various value-based sanity checks and shared operations. We
7805 do not signal immediate failures for the register constraints;
7806 this allows a syntax error to take precedence. */
7807 switch (op_parse_code
)
7815 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7816 inst
.error
= BAD_PC
;
7821 if (inst
.operands
[i
].isreg
)
7823 if (inst
.operands
[i
].reg
== REG_PC
)
7824 inst
.error
= BAD_PC
;
7825 else if (inst
.operands
[i
].reg
== REG_SP
7826 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7827 relaxed since ARMv8-A. */
7828 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7831 inst
.error
= BAD_SP
;
7837 if (inst
.operands
[i
].isreg
7838 && inst
.operands
[i
].reg
== REG_PC
7839 && (inst
.operands
[i
].writeback
|| thumb
))
7840 inst
.error
= BAD_PC
;
7845 if (inst
.operands
[i
].isreg
)
7855 case OP_oBARRIER_I15
:
7868 inst
.operands
[i
].imm
= val
;
7873 if (inst
.operands
[i
].reg
!= REG_LR
)
7874 inst
.error
= _("operand must be LR register");
7879 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
7880 inst
.error
= BAD_PC
;
7884 if (inst
.operands
[i
].isreg
7885 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
7886 inst
.error
= BAD_ODD
;
7890 if (inst
.operands
[i
].isreg
)
7892 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
7893 inst
.error
= BAD_EVEN
;
7894 else if (inst
.operands
[i
].reg
== REG_SP
)
7895 as_tsktsk (MVE_BAD_SP
);
7896 else if (inst
.operands
[i
].reg
== REG_PC
)
7897 inst
.error
= BAD_PC
;
7905 /* If we get here, this operand was successfully parsed. */
7906 inst
.operands
[i
].present
= 1;
7910 inst
.error
= BAD_ARGS
;
7915 /* The parse routine should already have set inst.error, but set a
7916 default here just in case. */
7918 inst
.error
= BAD_SYNTAX
;
7922 /* Do not backtrack over a trailing optional argument that
7923 absorbed some text. We will only fail again, with the
7924 'garbage following instruction' error message, which is
7925 probably less helpful than the current one. */
7926 if (backtrack_index
== i
&& backtrack_pos
!= str
7927 && upat
[i
+1] == OP_stop
)
7930 inst
.error
= BAD_SYNTAX
;
7934 /* Try again, skipping the optional argument at backtrack_pos. */
7935 str
= backtrack_pos
;
7936 inst
.error
= backtrack_error
;
7937 inst
.operands
[backtrack_index
].present
= 0;
7938 i
= backtrack_index
;
7942 /* Check that we have parsed all the arguments. */
7943 if (*str
!= '\0' && !inst
.error
)
7944 inst
.error
= _("garbage following instruction");
7946 return inst
.error
? FAIL
: SUCCESS
;
7949 #undef po_char_or_fail
7950 #undef po_reg_or_fail
7951 #undef po_reg_or_goto
7952 #undef po_imm_or_fail
7953 #undef po_scalar_or_fail
7954 #undef po_barrier_or_imm
7956 /* Shorthand macro for instruction encoding functions issuing errors. */
7957 #define constraint(expr, err) \
7968 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7969 instructions are unpredictable if these registers are used. This
7970 is the BadReg predicate in ARM's Thumb-2 documentation.
7972 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7973 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7974 #define reject_bad_reg(reg) \
7976 if (reg == REG_PC) \
7978 inst.error = BAD_PC; \
7981 else if (reg == REG_SP \
7982 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7984 inst.error = BAD_SP; \
7989 /* If REG is R13 (the stack pointer), warn that its use is
7991 #define warn_deprecated_sp(reg) \
7993 if (warn_on_deprecated && reg == REG_SP) \
7994 as_tsktsk (_("use of r13 is deprecated")); \
7997 /* Functions for operand encoding. ARM, then Thumb. */
7999 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8001 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8003 The only binary encoding difference is the Coprocessor number. Coprocessor
8004 9 is used for half-precision calculations or conversions. The format of the
8005 instruction is the same as the equivalent Coprocessor 10 instruction that
8006 exists for Single-Precision operation. */
8009 do_scalar_fp16_v82_encode (void)
8011 if (inst
.cond
< COND_ALWAYS
)
8012 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8013 " the behaviour is UNPREDICTABLE"));
8014 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8017 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8018 mark_feature_used (&arm_ext_fp16
);
8021 /* If VAL can be encoded in the immediate field of an ARM instruction,
8022 return the encoded form. Otherwise, return FAIL. */
8025 encode_arm_immediate (unsigned int val
)
8032 for (i
= 2; i
< 32; i
+= 2)
8033 if ((a
= rotate_left (val
, i
)) <= 0xff)
8034 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8039 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8040 return the encoded form. Otherwise, return FAIL. */
8042 encode_thumb32_immediate (unsigned int val
)
8049 for (i
= 1; i
<= 24; i
++)
8052 if ((val
& ~(0xff << i
)) == 0)
8053 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8057 if (val
== ((a
<< 16) | a
))
8059 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8063 if (val
== ((a
<< 16) | a
))
8064 return 0x200 | (a
>> 8);
8068 /* Encode a VFP SP or DP register number into inst.instruction. */
8071 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8073 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8076 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8079 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8082 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8087 first_error (_("D register out of range for selected VFP version"));
8095 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8099 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8103 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8107 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8111 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8115 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8123 /* Encode a <shift> in an ARM-format instruction. The immediate,
8124 if any, is handled by md_apply_fix. */
8126 encode_arm_shift (int i
)
8128 /* register-shifted register. */
8129 if (inst
.operands
[i
].immisreg
)
8132 for (op_index
= 0; op_index
<= i
; ++op_index
)
8134 /* Check the operand only when it's presented. In pre-UAL syntax,
8135 if the destination register is the same as the first operand, two
8136 register form of the instruction can be used. */
8137 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8138 && inst
.operands
[op_index
].reg
== REG_PC
)
8139 as_warn (UNPRED_REG ("r15"));
8142 if (inst
.operands
[i
].imm
== REG_PC
)
8143 as_warn (UNPRED_REG ("r15"));
8146 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8147 inst
.instruction
|= SHIFT_ROR
<< 5;
8150 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8151 if (inst
.operands
[i
].immisreg
)
8153 inst
.instruction
|= SHIFT_BY_REG
;
8154 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8157 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8162 encode_arm_shifter_operand (int i
)
8164 if (inst
.operands
[i
].isreg
)
8166 inst
.instruction
|= inst
.operands
[i
].reg
;
8167 encode_arm_shift (i
);
8171 inst
.instruction
|= INST_IMMEDIATE
;
8172 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8173 inst
.instruction
|= inst
.operands
[i
].imm
;
8177 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8179 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8182 Generate an error if the operand is not a register. */
8183 constraint (!inst
.operands
[i
].isreg
,
8184 _("Instruction does not support =N addresses"));
8186 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8188 if (inst
.operands
[i
].preind
)
8192 inst
.error
= _("instruction does not accept preindexed addressing");
8195 inst
.instruction
|= PRE_INDEX
;
8196 if (inst
.operands
[i
].writeback
)
8197 inst
.instruction
|= WRITE_BACK
;
8200 else if (inst
.operands
[i
].postind
)
8202 gas_assert (inst
.operands
[i
].writeback
);
8204 inst
.instruction
|= WRITE_BACK
;
8206 else /* unindexed - only for coprocessor */
8208 inst
.error
= _("instruction does not accept unindexed addressing");
8212 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8213 && (((inst
.instruction
& 0x000f0000) >> 16)
8214 == ((inst
.instruction
& 0x0000f000) >> 12)))
8215 as_warn ((inst
.instruction
& LOAD_BIT
)
8216 ? _("destination register same as write-back base")
8217 : _("source register same as write-back base"));
8220 /* inst.operands[i] was set up by parse_address. Encode it into an
8221 ARM-format mode 2 load or store instruction. If is_t is true,
8222 reject forms that cannot be used with a T instruction (i.e. not
8225 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8227 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8229 encode_arm_addr_mode_common (i
, is_t
);
8231 if (inst
.operands
[i
].immisreg
)
8233 constraint ((inst
.operands
[i
].imm
== REG_PC
8234 || (is_pc
&& inst
.operands
[i
].writeback
)),
8236 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8237 inst
.instruction
|= inst
.operands
[i
].imm
;
8238 if (!inst
.operands
[i
].negative
)
8239 inst
.instruction
|= INDEX_UP
;
8240 if (inst
.operands
[i
].shifted
)
8242 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8243 inst
.instruction
|= SHIFT_ROR
<< 5;
8246 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8247 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8251 else /* immediate offset in inst.relocs[0] */
8253 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8255 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8257 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8258 cannot use PC in addressing.
8259 PC cannot be used in writeback addressing, either. */
8260 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8263 /* Use of PC in str is deprecated for ARMv7. */
8264 if (warn_on_deprecated
8266 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8267 as_tsktsk (_("use of PC in this instruction is deprecated"));
8270 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8272 /* Prefer + for zero encoded value. */
8273 if (!inst
.operands
[i
].negative
)
8274 inst
.instruction
|= INDEX_UP
;
8275 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8280 /* inst.operands[i] was set up by parse_address. Encode it into an
8281 ARM-format mode 3 load or store instruction. Reject forms that
8282 cannot be used with such instructions. If is_t is true, reject
8283 forms that cannot be used with a T instruction (i.e. not
8286 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8288 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8290 inst
.error
= _("instruction does not accept scaled register index");
8294 encode_arm_addr_mode_common (i
, is_t
);
8296 if (inst
.operands
[i
].immisreg
)
8298 constraint ((inst
.operands
[i
].imm
== REG_PC
8299 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8301 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8303 inst
.instruction
|= inst
.operands
[i
].imm
;
8304 if (!inst
.operands
[i
].negative
)
8305 inst
.instruction
|= INDEX_UP
;
8307 else /* immediate offset in inst.relocs[0] */
8309 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8310 && inst
.operands
[i
].writeback
),
8312 inst
.instruction
|= HWOFFSET_IMM
;
8313 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8315 /* Prefer + for zero encoded value. */
8316 if (!inst
.operands
[i
].negative
)
8317 inst
.instruction
|= INDEX_UP
;
8319 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8324 /* Write immediate bits [7:0] to the following locations:
8326 |28/24|23 19|18 16|15 4|3 0|
8327 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8329 This function is used by VMOV/VMVN/VORR/VBIC. */
8332 neon_write_immbits (unsigned immbits
)
8334 inst
.instruction
|= immbits
& 0xf;
8335 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8336 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8339 /* Invert low-order SIZE bits of XHI:XLO. */
8342 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8344 unsigned immlo
= xlo
? *xlo
: 0;
8345 unsigned immhi
= xhi
? *xhi
: 0;
8350 immlo
= (~immlo
) & 0xff;
8354 immlo
= (~immlo
) & 0xffff;
8358 immhi
= (~immhi
) & 0xffffffff;
8362 immlo
= (~immlo
) & 0xffffffff;
8376 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8380 neon_bits_same_in_bytes (unsigned imm
)
8382 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8383 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8384 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8385 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8388 /* For immediate of above form, return 0bABCD. */
8391 neon_squash_bits (unsigned imm
)
8393 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8394 | ((imm
& 0x01000000) >> 21);
8397 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8400 neon_qfloat_bits (unsigned imm
)
8402 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8405 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8406 the instruction. *OP is passed as the initial value of the op field, and
8407 may be set to a different value depending on the constant (i.e.
8408 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8409 MVN). If the immediate looks like a repeated pattern then also
8410 try smaller element sizes. */
8413 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8414 unsigned *immbits
, int *op
, int size
,
8415 enum neon_el_type type
)
8417 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8419 if (type
== NT_float
&& !float_p
)
8422 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8424 if (size
!= 32 || *op
== 1)
8426 *immbits
= neon_qfloat_bits (immlo
);
8432 if (neon_bits_same_in_bytes (immhi
)
8433 && neon_bits_same_in_bytes (immlo
))
8437 *immbits
= (neon_squash_bits (immhi
) << 4)
8438 | neon_squash_bits (immlo
);
8449 if (immlo
== (immlo
& 0x000000ff))
8454 else if (immlo
== (immlo
& 0x0000ff00))
8456 *immbits
= immlo
>> 8;
8459 else if (immlo
== (immlo
& 0x00ff0000))
8461 *immbits
= immlo
>> 16;
8464 else if (immlo
== (immlo
& 0xff000000))
8466 *immbits
= immlo
>> 24;
8469 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8471 *immbits
= (immlo
>> 8) & 0xff;
8474 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8476 *immbits
= (immlo
>> 16) & 0xff;
8480 if ((immlo
& 0xffff) != (immlo
>> 16))
8487 if (immlo
== (immlo
& 0x000000ff))
8492 else if (immlo
== (immlo
& 0x0000ff00))
8494 *immbits
= immlo
>> 8;
8498 if ((immlo
& 0xff) != (immlo
>> 8))
8503 if (immlo
== (immlo
& 0x000000ff))
8505 /* Don't allow MVN with 8-bit immediate. */
8515 #if defined BFD_HOST_64_BIT
8516 /* Returns TRUE if double precision value V may be cast
8517 to single precision without loss of accuracy. */
8520 is_double_a_single (bfd_int64_t v
)
8522 int exp
= (int)((v
>> 52) & 0x7FF);
8523 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8525 return (exp
== 0 || exp
== 0x7FF
8526 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8527 && (mantissa
& 0x1FFFFFFFl
) == 0;
8530 /* Returns a double precision value casted to single precision
8531 (ignoring the least significant bits in exponent and mantissa). */
8534 double_to_single (bfd_int64_t v
)
8536 int sign
= (int) ((v
>> 63) & 1l);
8537 int exp
= (int) ((v
>> 52) & 0x7FF);
8538 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8544 exp
= exp
- 1023 + 127;
8553 /* No denormalized numbers. */
8559 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8561 #endif /* BFD_HOST_64_BIT */
8570 static void do_vfp_nsyn_opcode (const char *);
8572 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8573 Determine whether it can be performed with a move instruction; if
8574 it can, convert inst.instruction to that move instruction and
8575 return TRUE; if it can't, convert inst.instruction to a literal-pool
8576 load and return FALSE. If this is not a valid thing to do in the
8577 current context, set inst.error and return TRUE.
8579 inst.operands[i] describes the destination register. */
8582 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8585 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8586 bfd_boolean arm_p
= (t
== CONST_ARM
);
8589 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8593 if ((inst
.instruction
& tbit
) == 0)
8595 inst
.error
= _("invalid pseudo operation");
8599 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8600 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8601 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8603 inst
.error
= _("constant expression expected");
8607 if (inst
.relocs
[0].exp
.X_op
== O_constant
8608 || inst
.relocs
[0].exp
.X_op
== O_big
)
8610 #if defined BFD_HOST_64_BIT
8615 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8617 LITTLENUM_TYPE w
[X_PRECISION
];
8620 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8622 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8624 /* FIXME: Should we check words w[2..5] ? */
8629 #if defined BFD_HOST_64_BIT
8631 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8632 << LITTLENUM_NUMBER_OF_BITS
)
8633 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8634 << LITTLENUM_NUMBER_OF_BITS
)
8635 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8636 << LITTLENUM_NUMBER_OF_BITS
)
8637 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8639 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8640 | (l
[0] & LITTLENUM_MASK
);
8644 v
= inst
.relocs
[0].exp
.X_add_number
;
8646 if (!inst
.operands
[i
].issingle
)
8650 /* LDR should not use lead in a flag-setting instruction being
8651 chosen so we do not check whether movs can be used. */
8653 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8654 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8655 && inst
.operands
[i
].reg
!= 13
8656 && inst
.operands
[i
].reg
!= 15)
8658 /* Check if on thumb2 it can be done with a mov.w, mvn or
8659 movw instruction. */
8660 unsigned int newimm
;
8661 bfd_boolean isNegated
;
8663 newimm
= encode_thumb32_immediate (v
);
8664 if (newimm
!= (unsigned int) FAIL
)
8668 newimm
= encode_thumb32_immediate (~v
);
8669 if (newimm
!= (unsigned int) FAIL
)
8673 /* The number can be loaded with a mov.w or mvn
8675 if (newimm
!= (unsigned int) FAIL
8676 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8678 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8679 | (inst
.operands
[i
].reg
<< 8));
8680 /* Change to MOVN. */
8681 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8682 inst
.instruction
|= (newimm
& 0x800) << 15;
8683 inst
.instruction
|= (newimm
& 0x700) << 4;
8684 inst
.instruction
|= (newimm
& 0x0ff);
8687 /* The number can be loaded with a movw instruction. */
8688 else if ((v
& ~0xFFFF) == 0
8689 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8691 int imm
= v
& 0xFFFF;
8693 inst
.instruction
= 0xf2400000; /* MOVW. */
8694 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8695 inst
.instruction
|= (imm
& 0xf000) << 4;
8696 inst
.instruction
|= (imm
& 0x0800) << 15;
8697 inst
.instruction
|= (imm
& 0x0700) << 4;
8698 inst
.instruction
|= (imm
& 0x00ff);
8699 /* In case this replacement is being done on Armv8-M
8700 Baseline we need to make sure to disable the
8701 instruction size check, as otherwise GAS will reject
8702 the use of this T32 instruction. */
8710 int value
= encode_arm_immediate (v
);
8714 /* This can be done with a mov instruction. */
8715 inst
.instruction
&= LITERAL_MASK
;
8716 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8717 inst
.instruction
|= value
& 0xfff;
8721 value
= encode_arm_immediate (~ v
);
8724 /* This can be done with a mvn instruction. */
8725 inst
.instruction
&= LITERAL_MASK
;
8726 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8727 inst
.instruction
|= value
& 0xfff;
8731 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8734 unsigned immbits
= 0;
8735 unsigned immlo
= inst
.operands
[1].imm
;
8736 unsigned immhi
= inst
.operands
[1].regisimm
8737 ? inst
.operands
[1].reg
8738 : inst
.relocs
[0].exp
.X_unsigned
8740 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8741 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8742 &op
, 64, NT_invtype
);
8746 neon_invert_size (&immlo
, &immhi
, 64);
8748 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8749 &op
, 64, NT_invtype
);
8754 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8760 /* Fill other bits in vmov encoding for both thumb and arm. */
8762 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8764 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8765 neon_write_immbits (immbits
);
8773 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8774 if (inst
.operands
[i
].issingle
8775 && is_quarter_float (inst
.operands
[1].imm
)
8776 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8778 inst
.operands
[1].imm
=
8779 neon_qfloat_bits (v
);
8780 do_vfp_nsyn_opcode ("fconsts");
8784 /* If our host does not support a 64-bit type then we cannot perform
8785 the following optimization. This mean that there will be a
8786 discrepancy between the output produced by an assembler built for
8787 a 32-bit-only host and the output produced from a 64-bit host, but
8788 this cannot be helped. */
8789 #if defined BFD_HOST_64_BIT
8790 else if (!inst
.operands
[1].issingle
8791 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8793 if (is_double_a_single (v
)
8794 && is_quarter_float (double_to_single (v
)))
8796 inst
.operands
[1].imm
=
8797 neon_qfloat_bits (double_to_single (v
));
8798 do_vfp_nsyn_opcode ("fconstd");
8806 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8807 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8810 inst
.operands
[1].reg
= REG_PC
;
8811 inst
.operands
[1].isreg
= 1;
8812 inst
.operands
[1].preind
= 1;
8813 inst
.relocs
[0].pc_rel
= 1;
8814 inst
.relocs
[0].type
= (thumb_p
8815 ? BFD_RELOC_ARM_THUMB_OFFSET
8817 ? BFD_RELOC_ARM_HWLITERAL
8818 : BFD_RELOC_ARM_LITERAL
));
8822 /* inst.operands[i] was set up by parse_address. Encode it into an
8823 ARM-format instruction. Reject all forms which cannot be encoded
8824 into a coprocessor load/store instruction. If wb_ok is false,
8825 reject use of writeback; if unind_ok is false, reject use of
8826 unindexed addressing. If reloc_override is not 0, use it instead
8827 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8828 (in which case it is preserved). */
8831 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8833 if (!inst
.operands
[i
].isreg
)
8836 if (! inst
.operands
[0].isvec
)
8838 inst
.error
= _("invalid co-processor operand");
8841 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8845 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8847 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8849 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8851 gas_assert (!inst
.operands
[i
].writeback
);
8854 inst
.error
= _("instruction does not support unindexed addressing");
8857 inst
.instruction
|= inst
.operands
[i
].imm
;
8858 inst
.instruction
|= INDEX_UP
;
8862 if (inst
.operands
[i
].preind
)
8863 inst
.instruction
|= PRE_INDEX
;
8865 if (inst
.operands
[i
].writeback
)
8867 if (inst
.operands
[i
].reg
== REG_PC
)
8869 inst
.error
= _("pc may not be used with write-back");
8874 inst
.error
= _("instruction does not support writeback");
8877 inst
.instruction
|= WRITE_BACK
;
8881 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
8882 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8883 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
8884 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8887 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8889 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8892 /* Prefer + for zero encoded value. */
8893 if (!inst
.operands
[i
].negative
)
8894 inst
.instruction
|= INDEX_UP
;
8899 /* Functions for instruction encoding, sorted by sub-architecture.
8900 First some generics; their names are taken from the conventional
8901 bit positions for register arguments in ARM format instructions. */
8911 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8917 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8923 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8924 inst
.instruction
|= inst
.operands
[1].reg
;
8930 inst
.instruction
|= inst
.operands
[0].reg
;
8931 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8937 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8938 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8944 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8945 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8951 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8952 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8956 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8958 if (ARM_CPU_IS_ANY (cpu_variant
))
8960 as_tsktsk ("%s", msg
);
8963 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8975 unsigned Rn
= inst
.operands
[2].reg
;
8976 /* Enforce restrictions on SWP instruction. */
8977 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8979 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8980 _("Rn must not overlap other operands"));
8982 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8984 if (!check_obsolete (&arm_ext_v8
,
8985 _("swp{b} use is obsoleted for ARMv8 and later"))
8986 && warn_on_deprecated
8987 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8988 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8991 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8992 inst
.instruction
|= inst
.operands
[1].reg
;
8993 inst
.instruction
|= Rn
<< 16;
8999 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9000 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9001 inst
.instruction
|= inst
.operands
[2].reg
;
9007 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
9008 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
9009 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
9010 || inst
.relocs
[0].exp
.X_add_number
!= 0),
9012 inst
.instruction
|= inst
.operands
[0].reg
;
9013 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9014 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9020 inst
.instruction
|= inst
.operands
[0].imm
;
9026 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9027 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9030 /* ARM instructions, in alphabetical order by function name (except
9031 that wrapper functions appear immediately after the function they
9034 /* This is a pseudo-op of the form "adr rd, label" to be converted
9035 into a relative address of the form "add rd, pc, #label-.-8". */
9040 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9042 /* Frag hacking will turn this into a sub instruction if the offset turns
9043 out to be negative. */
9044 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9045 inst
.relocs
[0].pc_rel
= 1;
9046 inst
.relocs
[0].exp
.X_add_number
-= 8;
9048 if (support_interwork
9049 && inst
.relocs
[0].exp
.X_op
== O_symbol
9050 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9051 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9052 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9053 inst
.relocs
[0].exp
.X_add_number
|= 1;
9056 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9057 into a relative address of the form:
9058 add rd, pc, #low(label-.-8)"
9059 add rd, rd, #high(label-.-8)" */
9064 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9066 /* Frag hacking will turn this into a sub instruction if the offset turns
9067 out to be negative. */
9068 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9069 inst
.relocs
[0].pc_rel
= 1;
9070 inst
.size
= INSN_SIZE
* 2;
9071 inst
.relocs
[0].exp
.X_add_number
-= 8;
9073 if (support_interwork
9074 && inst
.relocs
[0].exp
.X_op
== O_symbol
9075 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9076 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9077 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9078 inst
.relocs
[0].exp
.X_add_number
|= 1;
9084 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9085 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9087 if (!inst
.operands
[1].present
)
9088 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9089 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9090 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9091 encode_arm_shifter_operand (2);
9097 if (inst
.operands
[0].present
)
9098 inst
.instruction
|= inst
.operands
[0].imm
;
9100 inst
.instruction
|= 0xf;
9106 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9107 constraint (msb
> 32, _("bit-field extends past end of register"));
9108 /* The instruction encoding stores the LSB and MSB,
9109 not the LSB and width. */
9110 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9111 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9112 inst
.instruction
|= (msb
- 1) << 16;
9120 /* #0 in second position is alternative syntax for bfc, which is
9121 the same instruction but with REG_PC in the Rm field. */
9122 if (!inst
.operands
[1].isreg
)
9123 inst
.operands
[1].reg
= REG_PC
;
9125 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9126 constraint (msb
> 32, _("bit-field extends past end of register"));
9127 /* The instruction encoding stores the LSB and MSB,
9128 not the LSB and width. */
9129 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9130 inst
.instruction
|= inst
.operands
[1].reg
;
9131 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9132 inst
.instruction
|= (msb
- 1) << 16;
9138 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9139 _("bit-field extends past end of register"));
9140 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9141 inst
.instruction
|= inst
.operands
[1].reg
;
9142 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9143 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9146 /* ARM V5 breakpoint instruction (argument parse)
9147 BKPT <16 bit unsigned immediate>
9148 Instruction is not conditional.
9149 The bit pattern given in insns[] has the COND_ALWAYS condition,
9150 and it is an error if the caller tried to override that. */
9155 /* Top 12 of 16 bits to bits 19:8. */
9156 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9158 /* Bottom 4 of 16 bits to bits 3:0. */
9159 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9163 encode_branch (int default_reloc
)
9165 if (inst
.operands
[0].hasreloc
)
9167 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9168 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9169 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9170 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9171 ? BFD_RELOC_ARM_PLT32
9172 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9175 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9176 inst
.relocs
[0].pc_rel
= 1;
9183 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9184 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9187 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9194 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9196 if (inst
.cond
== COND_ALWAYS
)
9197 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9199 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9203 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9206 /* ARM V5 branch-link-exchange instruction (argument parse)
9207 BLX <target_addr> ie BLX(1)
9208 BLX{<condition>} <Rm> ie BLX(2)
9209 Unfortunately, there are two different opcodes for this mnemonic.
9210 So, the insns[].value is not used, and the code here zaps values
9211 into inst.instruction.
9212 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9217 if (inst
.operands
[0].isreg
)
9219 /* Arg is a register; the opcode provided by insns[] is correct.
9220 It is not illegal to do "blx pc", just useless. */
9221 if (inst
.operands
[0].reg
== REG_PC
)
9222 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9224 inst
.instruction
|= inst
.operands
[0].reg
;
9228 /* Arg is an address; this instruction cannot be executed
9229 conditionally, and the opcode must be adjusted.
9230 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9231 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9232 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9233 inst
.instruction
= 0xfa000000;
9234 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9241 bfd_boolean want_reloc
;
9243 if (inst
.operands
[0].reg
== REG_PC
)
9244 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9246 inst
.instruction
|= inst
.operands
[0].reg
;
9247 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9248 it is for ARMv4t or earlier. */
9249 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9250 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9251 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9255 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9260 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9264 /* ARM v5TEJ. Jump to Jazelle code. */
9269 if (inst
.operands
[0].reg
== REG_PC
)
9270 as_tsktsk (_("use of r15 in bxj is not really useful"));
9272 inst
.instruction
|= inst
.operands
[0].reg
;
9275 /* Co-processor data operation:
9276 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9277 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9281 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9282 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9283 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9284 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9285 inst
.instruction
|= inst
.operands
[4].reg
;
9286 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9292 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9293 encode_arm_shifter_operand (1);
9296 /* Transfer between coprocessor and ARM registers.
9297 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9302 No special properties. */
9304 struct deprecated_coproc_regs_s
9311 arm_feature_set deprecated
;
9312 arm_feature_set obsoleted
;
9313 const char *dep_msg
;
9314 const char *obs_msg
;
9317 #define DEPR_ACCESS_V8 \
9318 N_("This coprocessor register access is deprecated in ARMv8")
9320 /* Table of all deprecated coprocessor registers. */
9321 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9323 {15, 0, 7, 10, 5, /* CP15DMB. */
9324 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9325 DEPR_ACCESS_V8
, NULL
},
9326 {15, 0, 7, 10, 4, /* CP15DSB. */
9327 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9328 DEPR_ACCESS_V8
, NULL
},
9329 {15, 0, 7, 5, 4, /* CP15ISB. */
9330 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9331 DEPR_ACCESS_V8
, NULL
},
9332 {14, 6, 1, 0, 0, /* TEEHBR. */
9333 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9334 DEPR_ACCESS_V8
, NULL
},
9335 {14, 6, 0, 0, 0, /* TEECR. */
9336 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9337 DEPR_ACCESS_V8
, NULL
},
9340 #undef DEPR_ACCESS_V8
9342 static const size_t deprecated_coproc_reg_count
=
9343 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9351 Rd
= inst
.operands
[2].reg
;
9354 if (inst
.instruction
== 0xee000010
9355 || inst
.instruction
== 0xfe000010)
9357 reject_bad_reg (Rd
);
9358 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9360 constraint (Rd
== REG_SP
, BAD_SP
);
9365 if (inst
.instruction
== 0xe000010)
9366 constraint (Rd
== REG_PC
, BAD_PC
);
9369 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9371 const struct deprecated_coproc_regs_s
*r
=
9372 deprecated_coproc_regs
+ i
;
9374 if (inst
.operands
[0].reg
== r
->cp
9375 && inst
.operands
[1].imm
== r
->opc1
9376 && inst
.operands
[3].reg
== r
->crn
9377 && inst
.operands
[4].reg
== r
->crm
9378 && inst
.operands
[5].imm
== r
->opc2
)
9380 if (! ARM_CPU_IS_ANY (cpu_variant
)
9381 && warn_on_deprecated
9382 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9383 as_tsktsk ("%s", r
->dep_msg
);
9387 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9388 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9389 inst
.instruction
|= Rd
<< 12;
9390 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9391 inst
.instruction
|= inst
.operands
[4].reg
;
9392 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9395 /* Transfer between coprocessor register and pair of ARM registers.
9396 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9401 Two XScale instructions are special cases of these:
9403 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9404 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9406 Result unpredictable if Rd or Rn is R15. */
9413 Rd
= inst
.operands
[2].reg
;
9414 Rn
= inst
.operands
[3].reg
;
9418 reject_bad_reg (Rd
);
9419 reject_bad_reg (Rn
);
9423 constraint (Rd
== REG_PC
, BAD_PC
);
9424 constraint (Rn
== REG_PC
, BAD_PC
);
9427 /* Only check the MRRC{2} variants. */
9428 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9430 /* If Rd == Rn, error that the operation is
9431 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9432 constraint (Rd
== Rn
, BAD_OVERLAP
);
9435 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9436 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9437 inst
.instruction
|= Rd
<< 12;
9438 inst
.instruction
|= Rn
<< 16;
9439 inst
.instruction
|= inst
.operands
[4].reg
;
9445 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9446 if (inst
.operands
[1].present
)
9448 inst
.instruction
|= CPSI_MMOD
;
9449 inst
.instruction
|= inst
.operands
[1].imm
;
9456 inst
.instruction
|= inst
.operands
[0].imm
;
9462 unsigned Rd
, Rn
, Rm
;
9464 Rd
= inst
.operands
[0].reg
;
9465 Rn
= (inst
.operands
[1].present
9466 ? inst
.operands
[1].reg
: Rd
);
9467 Rm
= inst
.operands
[2].reg
;
9469 constraint ((Rd
== REG_PC
), BAD_PC
);
9470 constraint ((Rn
== REG_PC
), BAD_PC
);
9471 constraint ((Rm
== REG_PC
), BAD_PC
);
9473 inst
.instruction
|= Rd
<< 16;
9474 inst
.instruction
|= Rn
<< 0;
9475 inst
.instruction
|= Rm
<< 8;
9481 /* There is no IT instruction in ARM mode. We
9482 process it to do the validation as if in
9483 thumb mode, just in case the code gets
9484 assembled for thumb using the unified syntax. */
9489 set_pred_insn_type (IT_INSN
);
9490 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9491 now_pred
.cc
= inst
.operands
[0].imm
;
9495 /* If there is only one register in the register list,
9496 then return its register number. Otherwise return -1. */
9498 only_one_reg_in_list (int range
)
9500 int i
= ffs (range
) - 1;
9501 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9505 encode_ldmstm(int from_push_pop_mnem
)
9507 int base_reg
= inst
.operands
[0].reg
;
9508 int range
= inst
.operands
[1].imm
;
9511 inst
.instruction
|= base_reg
<< 16;
9512 inst
.instruction
|= range
;
9514 if (inst
.operands
[1].writeback
)
9515 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9517 if (inst
.operands
[0].writeback
)
9519 inst
.instruction
|= WRITE_BACK
;
9520 /* Check for unpredictable uses of writeback. */
9521 if (inst
.instruction
& LOAD_BIT
)
9523 /* Not allowed in LDM type 2. */
9524 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9525 && ((range
& (1 << REG_PC
)) == 0))
9526 as_warn (_("writeback of base register is UNPREDICTABLE"));
9527 /* Only allowed if base reg not in list for other types. */
9528 else if (range
& (1 << base_reg
))
9529 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9533 /* Not allowed for type 2. */
9534 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9535 as_warn (_("writeback of base register is UNPREDICTABLE"));
9536 /* Only allowed if base reg not in list, or first in list. */
9537 else if ((range
& (1 << base_reg
))
9538 && (range
& ((1 << base_reg
) - 1)))
9539 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9543 /* If PUSH/POP has only one register, then use the A2 encoding. */
9544 one_reg
= only_one_reg_in_list (range
);
9545 if (from_push_pop_mnem
&& one_reg
>= 0)
9547 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9549 if (is_push
&& one_reg
== 13 /* SP */)
9550 /* PR 22483: The A2 encoding cannot be used when
9551 pushing the stack pointer as this is UNPREDICTABLE. */
9554 inst
.instruction
&= A_COND_MASK
;
9555 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9556 inst
.instruction
|= one_reg
<< 12;
9563 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9566 /* ARMv5TE load-consecutive (argument parse)
9575 constraint (inst
.operands
[0].reg
% 2 != 0,
9576 _("first transfer register must be even"));
9577 constraint (inst
.operands
[1].present
9578 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9579 _("can only transfer two consecutive registers"));
9580 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9581 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9583 if (!inst
.operands
[1].present
)
9584 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9586 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9587 register and the first register written; we have to diagnose
9588 overlap between the base and the second register written here. */
9590 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9591 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9592 as_warn (_("base register written back, and overlaps "
9593 "second transfer register"));
9595 if (!(inst
.instruction
& V4_STR_BIT
))
9597 /* For an index-register load, the index register must not overlap the
9598 destination (even if not write-back). */
9599 if (inst
.operands
[2].immisreg
9600 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9601 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9602 as_warn (_("index register overlaps transfer register"));
9604 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9605 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9611 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9612 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9613 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9614 || inst
.operands
[1].negative
9615 /* This can arise if the programmer has written
9617 or if they have mistakenly used a register name as the last
9620 It is very difficult to distinguish between these two cases
9621 because "rX" might actually be a label. ie the register
9622 name has been occluded by a symbol of the same name. So we
9623 just generate a general 'bad addressing mode' type error
9624 message and leave it up to the programmer to discover the
9625 true cause and fix their mistake. */
9626 || (inst
.operands
[1].reg
== REG_PC
),
9629 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9630 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9631 _("offset must be zero in ARM encoding"));
9633 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9635 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9636 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9637 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9643 constraint (inst
.operands
[0].reg
% 2 != 0,
9644 _("even register required"));
9645 constraint (inst
.operands
[1].present
9646 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9647 _("can only load two consecutive registers"));
9648 /* If op 1 were present and equal to PC, this function wouldn't
9649 have been called in the first place. */
9650 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9652 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9653 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9656 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9657 which is not a multiple of four is UNPREDICTABLE. */
9659 check_ldr_r15_aligned (void)
9661 constraint (!(inst
.operands
[1].immisreg
)
9662 && (inst
.operands
[0].reg
== REG_PC
9663 && inst
.operands
[1].reg
== REG_PC
9664 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9665 _("ldr to register 15 must be 4-byte aligned"));
9671 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9672 if (!inst
.operands
[1].isreg
)
9673 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9675 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9676 check_ldr_r15_aligned ();
9682 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9684 if (inst
.operands
[1].preind
)
9686 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9687 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9688 _("this instruction requires a post-indexed address"));
9690 inst
.operands
[1].preind
= 0;
9691 inst
.operands
[1].postind
= 1;
9692 inst
.operands
[1].writeback
= 1;
9694 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9695 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9698 /* Halfword and signed-byte load/store operations. */
9703 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9704 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9705 if (!inst
.operands
[1].isreg
)
9706 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9708 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9714 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9716 if (inst
.operands
[1].preind
)
9718 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9719 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9720 _("this instruction requires a post-indexed address"));
9722 inst
.operands
[1].preind
= 0;
9723 inst
.operands
[1].postind
= 1;
9724 inst
.operands
[1].writeback
= 1;
9726 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9727 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9730 /* Co-processor register load/store.
9731 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9735 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9736 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9737 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9743 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9744 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9745 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9746 && !(inst
.instruction
& 0x00400000))
9747 as_tsktsk (_("Rd and Rm should be different in mla"));
9749 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9750 inst
.instruction
|= inst
.operands
[1].reg
;
9751 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9752 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9758 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9759 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9761 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9762 encode_arm_shifter_operand (1);
9765 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9772 top
= (inst
.instruction
& 0x00400000) != 0;
9773 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9774 _(":lower16: not allowed in this instruction"));
9775 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9776 _(":upper16: not allowed in this instruction"));
9777 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9778 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9780 imm
= inst
.relocs
[0].exp
.X_add_number
;
9781 /* The value is in two pieces: 0:11, 16:19. */
9782 inst
.instruction
|= (imm
& 0x00000fff);
9783 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9788 do_vfp_nsyn_mrs (void)
9790 if (inst
.operands
[0].isvec
)
9792 if (inst
.operands
[1].reg
!= 1)
9793 first_error (_("operand 1 must be FPSCR"));
9794 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9795 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9796 do_vfp_nsyn_opcode ("fmstat");
9798 else if (inst
.operands
[1].isvec
)
9799 do_vfp_nsyn_opcode ("fmrx");
9807 do_vfp_nsyn_msr (void)
9809 if (inst
.operands
[0].isvec
)
9810 do_vfp_nsyn_opcode ("fmxr");
9820 unsigned Rt
= inst
.operands
[0].reg
;
9822 if (thumb_mode
&& Rt
== REG_SP
)
9824 inst
.error
= BAD_SP
;
9828 /* MVFR2 is only valid at ARMv8-A. */
9829 if (inst
.operands
[1].reg
== 5)
9830 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9833 /* APSR_ sets isvec. All other refs to PC are illegal. */
9834 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9836 inst
.error
= BAD_PC
;
9840 /* If we get through parsing the register name, we just insert the number
9841 generated into the instruction without further validation. */
9842 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9843 inst
.instruction
|= (Rt
<< 12);
9849 unsigned Rt
= inst
.operands
[1].reg
;
9852 reject_bad_reg (Rt
);
9853 else if (Rt
== REG_PC
)
9855 inst
.error
= BAD_PC
;
9859 /* MVFR2 is only valid for ARMv8-A. */
9860 if (inst
.operands
[0].reg
== 5)
9861 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9864 /* If we get through parsing the register name, we just insert the number
9865 generated into the instruction without further validation. */
9866 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9867 inst
.instruction
|= (Rt
<< 12);
9875 if (do_vfp_nsyn_mrs () == SUCCESS
)
9878 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9879 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9881 if (inst
.operands
[1].isreg
)
9883 br
= inst
.operands
[1].reg
;
9884 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9885 as_bad (_("bad register for mrs"));
9889 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9890 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9892 _("'APSR', 'CPSR' or 'SPSR' expected"));
9893 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9896 inst
.instruction
|= br
;
9899 /* Two possible forms:
9900 "{C|S}PSR_<field>, Rm",
9901 "{C|S}PSR_f, #expression". */
9906 if (do_vfp_nsyn_msr () == SUCCESS
)
9909 inst
.instruction
|= inst
.operands
[0].imm
;
9910 if (inst
.operands
[1].isreg
)
9911 inst
.instruction
|= inst
.operands
[1].reg
;
9914 inst
.instruction
|= INST_IMMEDIATE
;
9915 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9916 inst
.relocs
[0].pc_rel
= 0;
9923 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9925 if (!inst
.operands
[2].present
)
9926 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9927 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9928 inst
.instruction
|= inst
.operands
[1].reg
;
9929 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9931 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9932 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9933 as_tsktsk (_("Rd and Rm should be different in mul"));
9936 /* Long Multiply Parser
9937 UMULL RdLo, RdHi, Rm, Rs
9938 SMULL RdLo, RdHi, Rm, Rs
9939 UMLAL RdLo, RdHi, Rm, Rs
9940 SMLAL RdLo, RdHi, Rm, Rs. */
9945 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9946 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9947 inst
.instruction
|= inst
.operands
[2].reg
;
9948 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9950 /* rdhi and rdlo must be different. */
9951 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9952 as_tsktsk (_("rdhi and rdlo must be different"));
9954 /* rdhi, rdlo and rm must all be different before armv6. */
9955 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9956 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9957 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9958 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9964 if (inst
.operands
[0].present
9965 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9967 /* Architectural NOP hints are CPSR sets with no bits selected. */
9968 inst
.instruction
&= 0xf0000000;
9969 inst
.instruction
|= 0x0320f000;
9970 if (inst
.operands
[0].present
)
9971 inst
.instruction
|= inst
.operands
[0].imm
;
9975 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9976 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9977 Condition defaults to COND_ALWAYS.
9978 Error if Rd, Rn or Rm are R15. */
9983 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9984 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9985 inst
.instruction
|= inst
.operands
[2].reg
;
9986 if (inst
.operands
[3].present
)
9987 encode_arm_shift (3);
9990 /* ARM V6 PKHTB (Argument Parse). */
9995 if (!inst
.operands
[3].present
)
9997 /* If the shift specifier is omitted, turn the instruction
9998 into pkhbt rd, rm, rn. */
9999 inst
.instruction
&= 0xfff00010;
10000 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10001 inst
.instruction
|= inst
.operands
[1].reg
;
10002 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10006 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10007 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10008 inst
.instruction
|= inst
.operands
[2].reg
;
10009 encode_arm_shift (3);
10013 /* ARMv5TE: Preload-Cache
10014 MP Extensions: Preload for write
10018 Syntactically, like LDR with B=1, W=0, L=1. */
10023 constraint (!inst
.operands
[0].isreg
,
10024 _("'[' expected after PLD mnemonic"));
10025 constraint (inst
.operands
[0].postind
,
10026 _("post-indexed expression used in preload instruction"));
10027 constraint (inst
.operands
[0].writeback
,
10028 _("writeback used in preload instruction"));
10029 constraint (!inst
.operands
[0].preind
,
10030 _("unindexed addressing used in preload instruction"));
10031 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10034 /* ARMv7: PLI <addr_mode> */
10038 constraint (!inst
.operands
[0].isreg
,
10039 _("'[' expected after PLI mnemonic"));
10040 constraint (inst
.operands
[0].postind
,
10041 _("post-indexed expression used in preload instruction"));
10042 constraint (inst
.operands
[0].writeback
,
10043 _("writeback used in preload instruction"));
10044 constraint (!inst
.operands
[0].preind
,
10045 _("unindexed addressing used in preload instruction"));
10046 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10047 inst
.instruction
&= ~PRE_INDEX
;
10053 constraint (inst
.operands
[0].writeback
,
10054 _("push/pop do not support {reglist}^"));
10055 inst
.operands
[1] = inst
.operands
[0];
10056 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10057 inst
.operands
[0].isreg
= 1;
10058 inst
.operands
[0].writeback
= 1;
10059 inst
.operands
[0].reg
= REG_SP
;
10060 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10063 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10064 word at the specified address and the following word
10066 Unconditionally executed.
10067 Error if Rn is R15. */
10072 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10073 if (inst
.operands
[0].writeback
)
10074 inst
.instruction
|= WRITE_BACK
;
10077 /* ARM V6 ssat (argument parse). */
10082 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10083 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10084 inst
.instruction
|= inst
.operands
[2].reg
;
10086 if (inst
.operands
[3].present
)
10087 encode_arm_shift (3);
10090 /* ARM V6 usat (argument parse). */
10095 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10096 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10097 inst
.instruction
|= inst
.operands
[2].reg
;
10099 if (inst
.operands
[3].present
)
10100 encode_arm_shift (3);
10103 /* ARM V6 ssat16 (argument parse). */
10108 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10109 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10110 inst
.instruction
|= inst
.operands
[2].reg
;
10116 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10117 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10118 inst
.instruction
|= inst
.operands
[2].reg
;
10121 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10122 preserving the other bits.
10124 setend <endian_specifier>, where <endian_specifier> is either
10130 if (warn_on_deprecated
10131 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10132 as_tsktsk (_("setend use is deprecated for ARMv8"));
10134 if (inst
.operands
[0].imm
)
10135 inst
.instruction
|= 0x200;
10141 unsigned int Rm
= (inst
.operands
[1].present
10142 ? inst
.operands
[1].reg
10143 : inst
.operands
[0].reg
);
10145 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10146 inst
.instruction
|= Rm
;
10147 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10149 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10150 inst
.instruction
|= SHIFT_BY_REG
;
10151 /* PR 12854: Error on extraneous shifts. */
10152 constraint (inst
.operands
[2].shifted
,
10153 _("extraneous shift as part of operand to shift insn"));
10156 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10162 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10163 inst
.relocs
[0].pc_rel
= 0;
10169 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10170 inst
.relocs
[0].pc_rel
= 0;
10176 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10177 inst
.relocs
[0].pc_rel
= 0;
10183 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10184 _("selected processor does not support SETPAN instruction"));
10186 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10192 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10193 _("selected processor does not support SETPAN instruction"));
10195 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10198 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10199 SMLAxy{cond} Rd,Rm,Rs,Rn
10200 SMLAWy{cond} Rd,Rm,Rs,Rn
10201 Error if any register is R15. */
10206 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10207 inst
.instruction
|= inst
.operands
[1].reg
;
10208 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10209 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10212 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10213 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10214 Error if any register is R15.
10215 Warning if Rdlo == Rdhi. */
10220 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10221 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10222 inst
.instruction
|= inst
.operands
[2].reg
;
10223 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10225 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10226 as_tsktsk (_("rdhi and rdlo must be different"));
10229 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10230 SMULxy{cond} Rd,Rm,Rs
10231 Error if any register is R15. */
10236 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10237 inst
.instruction
|= inst
.operands
[1].reg
;
10238 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10241 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10242 the same for both ARM and Thumb-2. */
10249 if (inst
.operands
[0].present
)
10251 reg
= inst
.operands
[0].reg
;
10252 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10257 inst
.instruction
|= reg
<< 16;
10258 inst
.instruction
|= inst
.operands
[1].imm
;
10259 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10260 inst
.instruction
|= WRITE_BACK
;
10263 /* ARM V6 strex (argument parse). */
10268 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10269 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10270 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10271 || inst
.operands
[2].negative
10272 /* See comment in do_ldrex(). */
10273 || (inst
.operands
[2].reg
== REG_PC
),
10276 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10277 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10279 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10280 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10281 _("offset must be zero in ARM encoding"));
10283 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10284 inst
.instruction
|= inst
.operands
[1].reg
;
10285 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10286 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10290 do_t_strexbh (void)
10292 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10293 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10294 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10295 || inst
.operands
[2].negative
,
10298 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10299 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10307 constraint (inst
.operands
[1].reg
% 2 != 0,
10308 _("even register required"));
10309 constraint (inst
.operands
[2].present
10310 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10311 _("can only store two consecutive registers"));
10312 /* If op 2 were present and equal to PC, this function wouldn't
10313 have been called in the first place. */
10314 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10316 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10317 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10318 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10321 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10322 inst
.instruction
|= inst
.operands
[1].reg
;
10323 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10330 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10331 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10339 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10340 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10345 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10346 extends it to 32-bits, and adds the result to a value in another
10347 register. You can specify a rotation by 0, 8, 16, or 24 bits
10348 before extracting the 16-bit value.
10349 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10350 Condition defaults to COND_ALWAYS.
10351 Error if any register uses R15. */
10356 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10357 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10358 inst
.instruction
|= inst
.operands
[2].reg
;
10359 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10364 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10365 Condition defaults to COND_ALWAYS.
10366 Error if any register uses R15. */
10371 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10372 inst
.instruction
|= inst
.operands
[1].reg
;
10373 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10376 /* VFP instructions. In a logical order: SP variant first, monad
10377 before dyad, arithmetic then move then load/store. */
10380 do_vfp_sp_monadic (void)
10382 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10383 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10386 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10387 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10391 do_vfp_sp_dyadic (void)
10393 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10394 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10395 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10399 do_vfp_sp_compare_z (void)
10401 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10405 do_vfp_dp_sp_cvt (void)
10407 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10408 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10412 do_vfp_sp_dp_cvt (void)
10414 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10415 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10419 do_vfp_reg_from_sp (void)
10421 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10422 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10425 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10426 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10430 do_vfp_reg2_from_sp2 (void)
10432 constraint (inst
.operands
[2].imm
!= 2,
10433 _("only two consecutive VFP SP registers allowed here"));
10434 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10435 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10436 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10440 do_vfp_sp_from_reg (void)
10442 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10443 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10446 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10447 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10451 do_vfp_sp2_from_reg2 (void)
10453 constraint (inst
.operands
[0].imm
!= 2,
10454 _("only two consecutive VFP SP registers allowed here"));
10455 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10456 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10457 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10461 do_vfp_sp_ldst (void)
10463 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10464 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10468 do_vfp_dp_ldst (void)
10470 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10471 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10476 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10478 if (inst
.operands
[0].writeback
)
10479 inst
.instruction
|= WRITE_BACK
;
10481 constraint (ldstm_type
!= VFP_LDSTMIA
,
10482 _("this addressing mode requires base-register writeback"));
10483 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10484 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10485 inst
.instruction
|= inst
.operands
[1].imm
;
10489 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10493 if (inst
.operands
[0].writeback
)
10494 inst
.instruction
|= WRITE_BACK
;
10496 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10497 _("this addressing mode requires base-register writeback"));
10499 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10500 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10502 count
= inst
.operands
[1].imm
<< 1;
10503 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10506 inst
.instruction
|= count
;
10510 do_vfp_sp_ldstmia (void)
10512 vfp_sp_ldstm (VFP_LDSTMIA
);
10516 do_vfp_sp_ldstmdb (void)
10518 vfp_sp_ldstm (VFP_LDSTMDB
);
10522 do_vfp_dp_ldstmia (void)
10524 vfp_dp_ldstm (VFP_LDSTMIA
);
10528 do_vfp_dp_ldstmdb (void)
10530 vfp_dp_ldstm (VFP_LDSTMDB
);
10534 do_vfp_xp_ldstmia (void)
10536 vfp_dp_ldstm (VFP_LDSTMIAX
);
10540 do_vfp_xp_ldstmdb (void)
10542 vfp_dp_ldstm (VFP_LDSTMDBX
);
10546 do_vfp_dp_rd_rm (void)
10548 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10549 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10552 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10553 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10557 do_vfp_dp_rn_rd (void)
10559 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10560 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10564 do_vfp_dp_rd_rn (void)
10566 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10567 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10571 do_vfp_dp_rd_rn_rm (void)
10573 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10574 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10577 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10578 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10579 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10583 do_vfp_dp_rd (void)
10585 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10589 do_vfp_dp_rm_rd_rn (void)
10591 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10592 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10595 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10596 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10597 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10600 /* VFPv3 instructions. */
10602 do_vfp_sp_const (void)
10604 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10605 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10606 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10610 do_vfp_dp_const (void)
10612 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10613 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10614 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10618 vfp_conv (int srcsize
)
10620 int immbits
= srcsize
- inst
.operands
[1].imm
;
10622 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10624 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10625 i.e. immbits must be in range 0 - 16. */
10626 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10629 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10631 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10632 i.e. immbits must be in range 0 - 31. */
10633 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10637 inst
.instruction
|= (immbits
& 1) << 5;
10638 inst
.instruction
|= (immbits
>> 1);
10642 do_vfp_sp_conv_16 (void)
10644 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10649 do_vfp_dp_conv_16 (void)
10651 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10656 do_vfp_sp_conv_32 (void)
10658 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10663 do_vfp_dp_conv_32 (void)
10665 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10669 /* FPA instructions. Also in a logical order. */
10674 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10675 inst
.instruction
|= inst
.operands
[1].reg
;
10679 do_fpa_ldmstm (void)
10681 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10682 switch (inst
.operands
[1].imm
)
10684 case 1: inst
.instruction
|= CP_T_X
; break;
10685 case 2: inst
.instruction
|= CP_T_Y
; break;
10686 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10691 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10693 /* The instruction specified "ea" or "fd", so we can only accept
10694 [Rn]{!}. The instruction does not really support stacking or
10695 unstacking, so we have to emulate these by setting appropriate
10696 bits and offsets. */
10697 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10698 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10699 _("this instruction does not support indexing"));
10701 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10702 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10704 if (!(inst
.instruction
& INDEX_UP
))
10705 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10707 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10709 inst
.operands
[2].preind
= 0;
10710 inst
.operands
[2].postind
= 1;
10714 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10717 /* iWMMXt instructions: strictly in alphabetical order. */
10720 do_iwmmxt_tandorc (void)
10722 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10726 do_iwmmxt_textrc (void)
10728 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10729 inst
.instruction
|= inst
.operands
[1].imm
;
10733 do_iwmmxt_textrm (void)
10735 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10736 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10737 inst
.instruction
|= inst
.operands
[2].imm
;
10741 do_iwmmxt_tinsr (void)
10743 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10744 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10745 inst
.instruction
|= inst
.operands
[2].imm
;
10749 do_iwmmxt_tmia (void)
10751 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10752 inst
.instruction
|= inst
.operands
[1].reg
;
10753 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10757 do_iwmmxt_waligni (void)
10759 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10760 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10761 inst
.instruction
|= inst
.operands
[2].reg
;
10762 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10766 do_iwmmxt_wmerge (void)
10768 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10769 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10770 inst
.instruction
|= inst
.operands
[2].reg
;
10771 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10775 do_iwmmxt_wmov (void)
10777 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10778 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10779 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10780 inst
.instruction
|= inst
.operands
[1].reg
;
10784 do_iwmmxt_wldstbh (void)
10787 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10789 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10791 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10792 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10796 do_iwmmxt_wldstw (void)
10798 /* RIWR_RIWC clears .isreg for a control register. */
10799 if (!inst
.operands
[0].isreg
)
10801 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10802 inst
.instruction
|= 0xf0000000;
10805 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10806 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10810 do_iwmmxt_wldstd (void)
10812 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10813 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10814 && inst
.operands
[1].immisreg
)
10816 inst
.instruction
&= ~0x1a000ff;
10817 inst
.instruction
|= (0xfU
<< 28);
10818 if (inst
.operands
[1].preind
)
10819 inst
.instruction
|= PRE_INDEX
;
10820 if (!inst
.operands
[1].negative
)
10821 inst
.instruction
|= INDEX_UP
;
10822 if (inst
.operands
[1].writeback
)
10823 inst
.instruction
|= WRITE_BACK
;
10824 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10825 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10826 inst
.instruction
|= inst
.operands
[1].imm
;
10829 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10833 do_iwmmxt_wshufh (void)
10835 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10836 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10837 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10838 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10842 do_iwmmxt_wzero (void)
10844 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10845 inst
.instruction
|= inst
.operands
[0].reg
;
10846 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10847 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10851 do_iwmmxt_wrwrwr_or_imm5 (void)
10853 if (inst
.operands
[2].isreg
)
10856 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10857 _("immediate operand requires iWMMXt2"));
10859 if (inst
.operands
[2].imm
== 0)
10861 switch ((inst
.instruction
>> 20) & 0xf)
10867 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10868 inst
.operands
[2].imm
= 16;
10869 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10875 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10876 inst
.operands
[2].imm
= 32;
10877 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10884 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10886 wrn
= (inst
.instruction
>> 16) & 0xf;
10887 inst
.instruction
&= 0xff0fff0f;
10888 inst
.instruction
|= wrn
;
10889 /* Bail out here; the instruction is now assembled. */
10894 /* Map 32 -> 0, etc. */
10895 inst
.operands
[2].imm
&= 0x1f;
10896 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10900 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10901 operations first, then control, shift, and load/store. */
10903 /* Insns like "foo X,Y,Z". */
10906 do_mav_triple (void)
10908 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10909 inst
.instruction
|= inst
.operands
[1].reg
;
10910 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10913 /* Insns like "foo W,X,Y,Z".
10914 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10919 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10920 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10921 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10922 inst
.instruction
|= inst
.operands
[3].reg
;
10925 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10927 do_mav_dspsc (void)
10929 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10932 /* Maverick shift immediate instructions.
10933 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10934 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10937 do_mav_shift (void)
10939 int imm
= inst
.operands
[2].imm
;
10941 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10942 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10944 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10945 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10946 Bit 4 should be 0. */
10947 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10949 inst
.instruction
|= imm
;
10952 /* XScale instructions. Also sorted arithmetic before move. */
10954 /* Xscale multiply-accumulate (argument parse)
10957 MIAxycc acc0,Rm,Rs. */
10962 inst
.instruction
|= inst
.operands
[1].reg
;
10963 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10966 /* Xscale move-accumulator-register (argument parse)
10968 MARcc acc0,RdLo,RdHi. */
10973 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10974 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10977 /* Xscale move-register-accumulator (argument parse)
10979 MRAcc RdLo,RdHi,acc0. */
10984 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10985 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10986 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10989 /* Encoding functions relevant only to Thumb. */
10991 /* inst.operands[i] is a shifted-register operand; encode
10992 it into inst.instruction in the format used by Thumb32. */
10995 encode_thumb32_shifted_operand (int i
)
10997 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10998 unsigned int shift
= inst
.operands
[i
].shift_kind
;
11000 constraint (inst
.operands
[i
].immisreg
,
11001 _("shift by register not allowed in thumb mode"));
11002 inst
.instruction
|= inst
.operands
[i
].reg
;
11003 if (shift
== SHIFT_RRX
)
11004 inst
.instruction
|= SHIFT_ROR
<< 4;
11007 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11008 _("expression too complex"));
11010 constraint (value
> 32
11011 || (value
== 32 && (shift
== SHIFT_LSL
11012 || shift
== SHIFT_ROR
)),
11013 _("shift expression is too large"));
11017 else if (value
== 32)
11020 inst
.instruction
|= shift
<< 4;
11021 inst
.instruction
|= (value
& 0x1c) << 10;
11022 inst
.instruction
|= (value
& 0x03) << 6;
11027 /* inst.operands[i] was set up by parse_address. Encode it into a
11028 Thumb32 format load or store instruction. Reject forms that cannot
11029 be used with such instructions. If is_t is true, reject forms that
11030 cannot be used with a T instruction; if is_d is true, reject forms
11031 that cannot be used with a D instruction. If it is a store insn,
11032 reject PC in Rn. */
11035 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11037 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11039 constraint (!inst
.operands
[i
].isreg
,
11040 _("Instruction does not support =N addresses"));
11042 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11043 if (inst
.operands
[i
].immisreg
)
11045 constraint (is_pc
, BAD_PC_ADDRESSING
);
11046 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11047 constraint (inst
.operands
[i
].negative
,
11048 _("Thumb does not support negative register indexing"));
11049 constraint (inst
.operands
[i
].postind
,
11050 _("Thumb does not support register post-indexing"));
11051 constraint (inst
.operands
[i
].writeback
,
11052 _("Thumb does not support register indexing with writeback"));
11053 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11054 _("Thumb supports only LSL in shifted register indexing"));
11056 inst
.instruction
|= inst
.operands
[i
].imm
;
11057 if (inst
.operands
[i
].shifted
)
11059 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11060 _("expression too complex"));
11061 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11062 || inst
.relocs
[0].exp
.X_add_number
> 3,
11063 _("shift out of range"));
11064 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11066 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11068 else if (inst
.operands
[i
].preind
)
11070 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11071 constraint (is_t
&& inst
.operands
[i
].writeback
,
11072 _("cannot use writeback with this instruction"));
11073 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11074 BAD_PC_ADDRESSING
);
11078 inst
.instruction
|= 0x01000000;
11079 if (inst
.operands
[i
].writeback
)
11080 inst
.instruction
|= 0x00200000;
11084 inst
.instruction
|= 0x00000c00;
11085 if (inst
.operands
[i
].writeback
)
11086 inst
.instruction
|= 0x00000100;
11088 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11090 else if (inst
.operands
[i
].postind
)
11092 gas_assert (inst
.operands
[i
].writeback
);
11093 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11094 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11097 inst
.instruction
|= 0x00200000;
11099 inst
.instruction
|= 0x00000900;
11100 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11102 else /* unindexed - only for coprocessor */
11103 inst
.error
= _("instruction does not accept unindexed addressing");
11106 /* Table of Thumb instructions which exist in both 16- and 32-bit
11107 encodings (the latter only in post-V6T2 cores). The index is the
11108 value used in the insns table below. When there is more than one
11109 possible 16-bit encoding for the instruction, this table always
11111 Also contains several pseudo-instructions used during relaxation. */
11112 #define T16_32_TAB \
11113 X(_adc, 4140, eb400000), \
11114 X(_adcs, 4140, eb500000), \
11115 X(_add, 1c00, eb000000), \
11116 X(_adds, 1c00, eb100000), \
11117 X(_addi, 0000, f1000000), \
11118 X(_addis, 0000, f1100000), \
11119 X(_add_pc,000f, f20f0000), \
11120 X(_add_sp,000d, f10d0000), \
11121 X(_adr, 000f, f20f0000), \
11122 X(_and, 4000, ea000000), \
11123 X(_ands, 4000, ea100000), \
11124 X(_asr, 1000, fa40f000), \
11125 X(_asrs, 1000, fa50f000), \
11126 X(_b, e000, f000b000), \
11127 X(_bcond, d000, f0008000), \
11128 X(_bf, 0000, f040e001), \
11129 X(_bfcsel,0000, f000e001), \
11130 X(_bfx, 0000, f060e001), \
11131 X(_bfl, 0000, f000c001), \
11132 X(_bflx, 0000, f070e001), \
11133 X(_bic, 4380, ea200000), \
11134 X(_bics, 4380, ea300000), \
11135 X(_cmn, 42c0, eb100f00), \
11136 X(_cmp, 2800, ebb00f00), \
11137 X(_cpsie, b660, f3af8400), \
11138 X(_cpsid, b670, f3af8600), \
11139 X(_cpy, 4600, ea4f0000), \
11140 X(_dec_sp,80dd, f1ad0d00), \
11141 X(_dls, 0000, f040e001), \
11142 X(_dlstp, 0000, f000e001), \
11143 X(_eor, 4040, ea800000), \
11144 X(_eors, 4040, ea900000), \
11145 X(_inc_sp,00dd, f10d0d00), \
11146 X(_lctp, 0000, f00fe001), \
11147 X(_ldmia, c800, e8900000), \
11148 X(_ldr, 6800, f8500000), \
11149 X(_ldrb, 7800, f8100000), \
11150 X(_ldrh, 8800, f8300000), \
11151 X(_ldrsb, 5600, f9100000), \
11152 X(_ldrsh, 5e00, f9300000), \
11153 X(_ldr_pc,4800, f85f0000), \
11154 X(_ldr_pc2,4800, f85f0000), \
11155 X(_ldr_sp,9800, f85d0000), \
11156 X(_le, 0000, f00fc001), \
11157 X(_letp, 0000, f01fc001), \
11158 X(_lsl, 0000, fa00f000), \
11159 X(_lsls, 0000, fa10f000), \
11160 X(_lsr, 0800, fa20f000), \
11161 X(_lsrs, 0800, fa30f000), \
11162 X(_mov, 2000, ea4f0000), \
11163 X(_movs, 2000, ea5f0000), \
11164 X(_mul, 4340, fb00f000), \
11165 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11166 X(_mvn, 43c0, ea6f0000), \
11167 X(_mvns, 43c0, ea7f0000), \
11168 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11169 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11170 X(_orr, 4300, ea400000), \
11171 X(_orrs, 4300, ea500000), \
11172 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11173 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11174 X(_rev, ba00, fa90f080), \
11175 X(_rev16, ba40, fa90f090), \
11176 X(_revsh, bac0, fa90f0b0), \
11177 X(_ror, 41c0, fa60f000), \
11178 X(_rors, 41c0, fa70f000), \
11179 X(_sbc, 4180, eb600000), \
11180 X(_sbcs, 4180, eb700000), \
11181 X(_stmia, c000, e8800000), \
11182 X(_str, 6000, f8400000), \
11183 X(_strb, 7000, f8000000), \
11184 X(_strh, 8000, f8200000), \
11185 X(_str_sp,9000, f84d0000), \
11186 X(_sub, 1e00, eba00000), \
11187 X(_subs, 1e00, ebb00000), \
11188 X(_subi, 8000, f1a00000), \
11189 X(_subis, 8000, f1b00000), \
11190 X(_sxtb, b240, fa4ff080), \
11191 X(_sxth, b200, fa0ff080), \
11192 X(_tst, 4200, ea100f00), \
11193 X(_uxtb, b2c0, fa5ff080), \
11194 X(_uxth, b280, fa1ff080), \
11195 X(_nop, bf00, f3af8000), \
11196 X(_yield, bf10, f3af8001), \
11197 X(_wfe, bf20, f3af8002), \
11198 X(_wfi, bf30, f3af8003), \
11199 X(_wls, 0000, f040c001), \
11200 X(_wlstp, 0000, f000c001), \
11201 X(_sev, bf40, f3af8004), \
11202 X(_sevl, bf50, f3af8005), \
11203 X(_udf, de00, f7f0a000)
11205 /* To catch errors in encoding functions, the codes are all offset by
11206 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11207 as 16-bit instructions. */
11208 #define X(a,b,c) T_MNEM##a
11209 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11212 #define X(a,b,c) 0x##b
11213 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11214 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11217 #define X(a,b,c) 0x##c
11218 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11219 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11220 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11224 /* Thumb instruction encoders, in alphabetical order. */
11226 /* ADDW or SUBW. */
11229 do_t_add_sub_w (void)
11233 Rd
= inst
.operands
[0].reg
;
11234 Rn
= inst
.operands
[1].reg
;
11236 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11237 is the SP-{plus,minus}-immediate form of the instruction. */
11239 constraint (Rd
== REG_PC
, BAD_PC
);
11241 reject_bad_reg (Rd
);
11243 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11244 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11247 /* Parse an add or subtract instruction. We get here with inst.instruction
11248 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11251 do_t_add_sub (void)
11255 Rd
= inst
.operands
[0].reg
;
11256 Rs
= (inst
.operands
[1].present
11257 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11258 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11261 set_pred_insn_type_last ();
11263 if (unified_syntax
)
11266 bfd_boolean narrow
;
11269 flags
= (inst
.instruction
== T_MNEM_adds
11270 || inst
.instruction
== T_MNEM_subs
);
11272 narrow
= !in_pred_block ();
11274 narrow
= in_pred_block ();
11275 if (!inst
.operands
[2].isreg
)
11279 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11280 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11282 add
= (inst
.instruction
== T_MNEM_add
11283 || inst
.instruction
== T_MNEM_adds
);
11285 if (inst
.size_req
!= 4)
11287 /* Attempt to use a narrow opcode, with relaxation if
11289 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11290 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11291 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11292 opcode
= T_MNEM_add_sp
;
11293 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11294 opcode
= T_MNEM_add_pc
;
11295 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11298 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11300 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11304 inst
.instruction
= THUMB_OP16(opcode
);
11305 inst
.instruction
|= (Rd
<< 4) | Rs
;
11306 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11307 || (inst
.relocs
[0].type
11308 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11310 if (inst
.size_req
== 2)
11311 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11313 inst
.relax
= opcode
;
11317 constraint (inst
.size_req
== 2, BAD_HIREG
);
11319 if (inst
.size_req
== 4
11320 || (inst
.size_req
!= 2 && !opcode
))
11322 constraint ((inst
.relocs
[0].type
11323 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11324 && (inst
.relocs
[0].type
11325 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11326 THUMB1_RELOC_ONLY
);
11329 constraint (add
, BAD_PC
);
11330 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11331 _("only SUBS PC, LR, #const allowed"));
11332 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11333 _("expression too complex"));
11334 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11335 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11336 _("immediate value out of range"));
11337 inst
.instruction
= T2_SUBS_PC_LR
11338 | inst
.relocs
[0].exp
.X_add_number
;
11339 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11342 else if (Rs
== REG_PC
)
11344 /* Always use addw/subw. */
11345 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11346 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11350 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11351 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11354 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11356 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11358 inst
.instruction
|= Rd
<< 8;
11359 inst
.instruction
|= Rs
<< 16;
11364 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11365 unsigned int shift
= inst
.operands
[2].shift_kind
;
11367 Rn
= inst
.operands
[2].reg
;
11368 /* See if we can do this with a 16-bit instruction. */
11369 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11371 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11376 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11377 || inst
.instruction
== T_MNEM_add
)
11379 : T_OPCODE_SUB_R3
);
11380 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11384 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11386 /* Thumb-1 cores (except v6-M) require at least one high
11387 register in a narrow non flag setting add. */
11388 if (Rd
> 7 || Rn
> 7
11389 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11390 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11397 inst
.instruction
= T_OPCODE_ADD_HI
;
11398 inst
.instruction
|= (Rd
& 8) << 4;
11399 inst
.instruction
|= (Rd
& 7);
11400 inst
.instruction
|= Rn
<< 3;
11406 constraint (Rd
== REG_PC
, BAD_PC
);
11407 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11408 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11409 constraint (Rs
== REG_PC
, BAD_PC
);
11410 reject_bad_reg (Rn
);
11412 /* If we get here, it can't be done in 16 bits. */
11413 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11414 _("shift must be constant"));
11415 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11416 inst
.instruction
|= Rd
<< 8;
11417 inst
.instruction
|= Rs
<< 16;
11418 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11419 _("shift value over 3 not allowed in thumb mode"));
11420 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11421 _("only LSL shift allowed in thumb mode"));
11422 encode_thumb32_shifted_operand (2);
11427 constraint (inst
.instruction
== T_MNEM_adds
11428 || inst
.instruction
== T_MNEM_subs
,
11431 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11433 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11434 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11437 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11438 ? 0x0000 : 0x8000);
11439 inst
.instruction
|= (Rd
<< 4) | Rs
;
11440 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11444 Rn
= inst
.operands
[2].reg
;
11445 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11447 /* We now have Rd, Rs, and Rn set to registers. */
11448 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11450 /* Can't do this for SUB. */
11451 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11452 inst
.instruction
= T_OPCODE_ADD_HI
;
11453 inst
.instruction
|= (Rd
& 8) << 4;
11454 inst
.instruction
|= (Rd
& 7);
11456 inst
.instruction
|= Rn
<< 3;
11458 inst
.instruction
|= Rs
<< 3;
11460 constraint (1, _("dest must overlap one source register"));
11464 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11465 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11466 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11476 Rd
= inst
.operands
[0].reg
;
11477 reject_bad_reg (Rd
);
11479 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11481 /* Defer to section relaxation. */
11482 inst
.relax
= inst
.instruction
;
11483 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11484 inst
.instruction
|= Rd
<< 4;
11486 else if (unified_syntax
&& inst
.size_req
!= 2)
11488 /* Generate a 32-bit opcode. */
11489 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11490 inst
.instruction
|= Rd
<< 8;
11491 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11492 inst
.relocs
[0].pc_rel
= 1;
11496 /* Generate a 16-bit opcode. */
11497 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11498 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11499 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11500 inst
.relocs
[0].pc_rel
= 1;
11501 inst
.instruction
|= Rd
<< 4;
11504 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11505 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11506 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11507 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11508 inst
.relocs
[0].exp
.X_add_number
+= 1;
11511 /* Arithmetic instructions for which there is just one 16-bit
11512 instruction encoding, and it allows only two low registers.
11513 For maximal compatibility with ARM syntax, we allow three register
11514 operands even when Thumb-32 instructions are not available, as long
11515 as the first two are identical. For instance, both "sbc r0,r1" and
11516 "sbc r0,r0,r1" are allowed. */
11522 Rd
= inst
.operands
[0].reg
;
11523 Rs
= (inst
.operands
[1].present
11524 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11525 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11526 Rn
= inst
.operands
[2].reg
;
11528 reject_bad_reg (Rd
);
11529 reject_bad_reg (Rs
);
11530 if (inst
.operands
[2].isreg
)
11531 reject_bad_reg (Rn
);
11533 if (unified_syntax
)
11535 if (!inst
.operands
[2].isreg
)
11537 /* For an immediate, we always generate a 32-bit opcode;
11538 section relaxation will shrink it later if possible. */
11539 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11540 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11541 inst
.instruction
|= Rd
<< 8;
11542 inst
.instruction
|= Rs
<< 16;
11543 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11547 bfd_boolean narrow
;
11549 /* See if we can do this with a 16-bit instruction. */
11550 if (THUMB_SETS_FLAGS (inst
.instruction
))
11551 narrow
= !in_pred_block ();
11553 narrow
= in_pred_block ();
11555 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11557 if (inst
.operands
[2].shifted
)
11559 if (inst
.size_req
== 4)
11565 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11566 inst
.instruction
|= Rd
;
11567 inst
.instruction
|= Rn
<< 3;
11571 /* If we get here, it can't be done in 16 bits. */
11572 constraint (inst
.operands
[2].shifted
11573 && inst
.operands
[2].immisreg
,
11574 _("shift must be constant"));
11575 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11576 inst
.instruction
|= Rd
<< 8;
11577 inst
.instruction
|= Rs
<< 16;
11578 encode_thumb32_shifted_operand (2);
11583 /* On its face this is a lie - the instruction does set the
11584 flags. However, the only supported mnemonic in this mode
11585 says it doesn't. */
11586 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11588 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11589 _("unshifted register required"));
11590 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11591 constraint (Rd
!= Rs
,
11592 _("dest and source1 must be the same register"));
11594 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11595 inst
.instruction
|= Rd
;
11596 inst
.instruction
|= Rn
<< 3;
11600 /* Similarly, but for instructions where the arithmetic operation is
11601 commutative, so we can allow either of them to be different from
11602 the destination operand in a 16-bit instruction. For instance, all
11603 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11610 Rd
= inst
.operands
[0].reg
;
11611 Rs
= (inst
.operands
[1].present
11612 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11613 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11614 Rn
= inst
.operands
[2].reg
;
11616 reject_bad_reg (Rd
);
11617 reject_bad_reg (Rs
);
11618 if (inst
.operands
[2].isreg
)
11619 reject_bad_reg (Rn
);
11621 if (unified_syntax
)
11623 if (!inst
.operands
[2].isreg
)
11625 /* For an immediate, we always generate a 32-bit opcode;
11626 section relaxation will shrink it later if possible. */
11627 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11628 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11629 inst
.instruction
|= Rd
<< 8;
11630 inst
.instruction
|= Rs
<< 16;
11631 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11635 bfd_boolean narrow
;
11637 /* See if we can do this with a 16-bit instruction. */
11638 if (THUMB_SETS_FLAGS (inst
.instruction
))
11639 narrow
= !in_pred_block ();
11641 narrow
= in_pred_block ();
11643 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11645 if (inst
.operands
[2].shifted
)
11647 if (inst
.size_req
== 4)
11654 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11655 inst
.instruction
|= Rd
;
11656 inst
.instruction
|= Rn
<< 3;
11661 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11662 inst
.instruction
|= Rd
;
11663 inst
.instruction
|= Rs
<< 3;
11668 /* If we get here, it can't be done in 16 bits. */
11669 constraint (inst
.operands
[2].shifted
11670 && inst
.operands
[2].immisreg
,
11671 _("shift must be constant"));
11672 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11673 inst
.instruction
|= Rd
<< 8;
11674 inst
.instruction
|= Rs
<< 16;
11675 encode_thumb32_shifted_operand (2);
11680 /* On its face this is a lie - the instruction does set the
11681 flags. However, the only supported mnemonic in this mode
11682 says it doesn't. */
11683 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11685 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11686 _("unshifted register required"));
11687 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11689 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11690 inst
.instruction
|= Rd
;
11693 inst
.instruction
|= Rn
<< 3;
11695 inst
.instruction
|= Rs
<< 3;
11697 constraint (1, _("dest must overlap one source register"));
11705 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11706 constraint (msb
> 32, _("bit-field extends past end of register"));
11707 /* The instruction encoding stores the LSB and MSB,
11708 not the LSB and width. */
11709 Rd
= inst
.operands
[0].reg
;
11710 reject_bad_reg (Rd
);
11711 inst
.instruction
|= Rd
<< 8;
11712 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11713 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11714 inst
.instruction
|= msb
- 1;
11723 Rd
= inst
.operands
[0].reg
;
11724 reject_bad_reg (Rd
);
11726 /* #0 in second position is alternative syntax for bfc, which is
11727 the same instruction but with REG_PC in the Rm field. */
11728 if (!inst
.operands
[1].isreg
)
11732 Rn
= inst
.operands
[1].reg
;
11733 reject_bad_reg (Rn
);
11736 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11737 constraint (msb
> 32, _("bit-field extends past end of register"));
11738 /* The instruction encoding stores the LSB and MSB,
11739 not the LSB and width. */
11740 inst
.instruction
|= Rd
<< 8;
11741 inst
.instruction
|= Rn
<< 16;
11742 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11743 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11744 inst
.instruction
|= msb
- 1;
11752 Rd
= inst
.operands
[0].reg
;
11753 Rn
= inst
.operands
[1].reg
;
11755 reject_bad_reg (Rd
);
11756 reject_bad_reg (Rn
);
11758 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11759 _("bit-field extends past end of register"));
11760 inst
.instruction
|= Rd
<< 8;
11761 inst
.instruction
|= Rn
<< 16;
11762 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11763 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11764 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11767 /* ARM V5 Thumb BLX (argument parse)
11768 BLX <target_addr> which is BLX(1)
11769 BLX <Rm> which is BLX(2)
11770 Unfortunately, there are two different opcodes for this mnemonic.
11771 So, the insns[].value is not used, and the code here zaps values
11772 into inst.instruction.
11774 ??? How to take advantage of the additional two bits of displacement
11775 available in Thumb32 mode? Need new relocation? */
11780 set_pred_insn_type_last ();
11782 if (inst
.operands
[0].isreg
)
11784 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11785 /* We have a register, so this is BLX(2). */
11786 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11790 /* No register. This must be BLX(1). */
11791 inst
.instruction
= 0xf000e800;
11792 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11801 bfd_reloc_code_real_type reloc
;
11804 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
11806 if (in_pred_block ())
11808 /* Conditional branches inside IT blocks are encoded as unconditional
11810 cond
= COND_ALWAYS
;
11815 if (cond
!= COND_ALWAYS
)
11816 opcode
= T_MNEM_bcond
;
11818 opcode
= inst
.instruction
;
11821 && (inst
.size_req
== 4
11822 || (inst
.size_req
!= 2
11823 && (inst
.operands
[0].hasreloc
11824 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
11826 inst
.instruction
= THUMB_OP32(opcode
);
11827 if (cond
== COND_ALWAYS
)
11828 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11831 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11832 _("selected architecture does not support "
11833 "wide conditional branch instruction"));
11835 gas_assert (cond
!= 0xF);
11836 inst
.instruction
|= cond
<< 22;
11837 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11842 inst
.instruction
= THUMB_OP16(opcode
);
11843 if (cond
== COND_ALWAYS
)
11844 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11847 inst
.instruction
|= cond
<< 8;
11848 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11850 /* Allow section relaxation. */
11851 if (unified_syntax
&& inst
.size_req
!= 2)
11852 inst
.relax
= opcode
;
11854 inst
.relocs
[0].type
= reloc
;
11855 inst
.relocs
[0].pc_rel
= 1;
11858 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11859 between the two is the maximum immediate allowed - which is passed in
11862 do_t_bkpt_hlt1 (int range
)
11864 constraint (inst
.cond
!= COND_ALWAYS
,
11865 _("instruction is always unconditional"));
11866 if (inst
.operands
[0].present
)
11868 constraint (inst
.operands
[0].imm
> range
,
11869 _("immediate value out of range"));
11870 inst
.instruction
|= inst
.operands
[0].imm
;
11873 set_pred_insn_type (NEUTRAL_IT_INSN
);
11879 do_t_bkpt_hlt1 (63);
11885 do_t_bkpt_hlt1 (255);
11889 do_t_branch23 (void)
11891 set_pred_insn_type_last ();
11892 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11894 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11895 this file. We used to simply ignore the PLT reloc type here --
11896 the branch encoding is now needed to deal with TLSCALL relocs.
11897 So if we see a PLT reloc now, put it back to how it used to be to
11898 keep the preexisting behaviour. */
11899 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
11900 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11902 #if defined(OBJ_COFF)
11903 /* If the destination of the branch is a defined symbol which does not have
11904 the THUMB_FUNC attribute, then we must be calling a function which has
11905 the (interfacearm) attribute. We look for the Thumb entry point to that
11906 function and change the branch to refer to that function instead. */
11907 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
11908 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11909 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11910 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11911 inst
.relocs
[0].exp
.X_add_symbol
11912 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
11919 set_pred_insn_type_last ();
11920 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11921 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11922 should cause the alignment to be checked once it is known. This is
11923 because BX PC only works if the instruction is word aligned. */
11931 set_pred_insn_type_last ();
11932 Rm
= inst
.operands
[0].reg
;
11933 reject_bad_reg (Rm
);
11934 inst
.instruction
|= Rm
<< 16;
11943 Rd
= inst
.operands
[0].reg
;
11944 Rm
= inst
.operands
[1].reg
;
11946 reject_bad_reg (Rd
);
11947 reject_bad_reg (Rm
);
11949 inst
.instruction
|= Rd
<< 8;
11950 inst
.instruction
|= Rm
<< 16;
11951 inst
.instruction
|= Rm
;
11957 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11963 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11964 inst
.instruction
|= inst
.operands
[0].imm
;
11970 set_pred_insn_type (OUTSIDE_PRED_INSN
);
11972 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11973 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11975 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11976 inst
.instruction
= 0xf3af8000;
11977 inst
.instruction
|= imod
<< 9;
11978 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11979 if (inst
.operands
[1].present
)
11980 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11984 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11985 && (inst
.operands
[0].imm
& 4),
11986 _("selected processor does not support 'A' form "
11987 "of this instruction"));
11988 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11989 _("Thumb does not support the 2-argument "
11990 "form of this instruction"));
11991 inst
.instruction
|= inst
.operands
[0].imm
;
11995 /* THUMB CPY instruction (argument parse). */
12000 if (inst
.size_req
== 4)
12002 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
12003 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12004 inst
.instruction
|= inst
.operands
[1].reg
;
12008 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
12009 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
12010 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12017 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12018 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12019 inst
.instruction
|= inst
.operands
[0].reg
;
12020 inst
.relocs
[0].pc_rel
= 1;
12021 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12027 inst
.instruction
|= inst
.operands
[0].imm
;
12033 unsigned Rd
, Rn
, Rm
;
12035 Rd
= inst
.operands
[0].reg
;
12036 Rn
= (inst
.operands
[1].present
12037 ? inst
.operands
[1].reg
: Rd
);
12038 Rm
= inst
.operands
[2].reg
;
12040 reject_bad_reg (Rd
);
12041 reject_bad_reg (Rn
);
12042 reject_bad_reg (Rm
);
12044 inst
.instruction
|= Rd
<< 8;
12045 inst
.instruction
|= Rn
<< 16;
12046 inst
.instruction
|= Rm
;
12052 if (unified_syntax
&& inst
.size_req
== 4)
12053 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12055 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12061 unsigned int cond
= inst
.operands
[0].imm
;
12063 set_pred_insn_type (IT_INSN
);
12064 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12065 now_pred
.cc
= cond
;
12066 now_pred
.warn_deprecated
= FALSE
;
12067 now_pred
.type
= SCALAR_PRED
;
12069 /* If the condition is a negative condition, invert the mask. */
12070 if ((cond
& 0x1) == 0x0)
12072 unsigned int mask
= inst
.instruction
& 0x000f;
12074 if ((mask
& 0x7) == 0)
12076 /* No conversion needed. */
12077 now_pred
.block_length
= 1;
12079 else if ((mask
& 0x3) == 0)
12082 now_pred
.block_length
= 2;
12084 else if ((mask
& 0x1) == 0)
12087 now_pred
.block_length
= 3;
12092 now_pred
.block_length
= 4;
12095 inst
.instruction
&= 0xfff0;
12096 inst
.instruction
|= mask
;
12099 inst
.instruction
|= cond
<< 4;
12102 /* Helper function used for both push/pop and ldm/stm. */
12104 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12105 bfd_boolean writeback
)
12107 bfd_boolean load
, store
;
12109 gas_assert (base
!= -1 || !do_io
);
12110 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12111 store
= do_io
&& !load
;
12113 if (mask
& (1 << 13))
12114 inst
.error
= _("SP not allowed in register list");
12116 if (do_io
&& (mask
& (1 << base
)) != 0
12118 inst
.error
= _("having the base register in the register list when "
12119 "using write back is UNPREDICTABLE");
12123 if (mask
& (1 << 15))
12125 if (mask
& (1 << 14))
12126 inst
.error
= _("LR and PC should not both be in register list");
12128 set_pred_insn_type_last ();
12133 if (mask
& (1 << 15))
12134 inst
.error
= _("PC not allowed in register list");
12137 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12139 /* Single register transfers implemented as str/ldr. */
12142 if (inst
.instruction
& (1 << 23))
12143 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12145 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12149 if (inst
.instruction
& (1 << 23))
12150 inst
.instruction
= 0x00800000; /* ia -> [base] */
12152 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12155 inst
.instruction
|= 0xf8400000;
12157 inst
.instruction
|= 0x00100000;
12159 mask
= ffs (mask
) - 1;
12162 else if (writeback
)
12163 inst
.instruction
|= WRITE_BACK
;
12165 inst
.instruction
|= mask
;
12167 inst
.instruction
|= base
<< 16;
12173 /* This really doesn't seem worth it. */
12174 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12175 _("expression too complex"));
12176 constraint (inst
.operands
[1].writeback
,
12177 _("Thumb load/store multiple does not support {reglist}^"));
12179 if (unified_syntax
)
12181 bfd_boolean narrow
;
12185 /* See if we can use a 16-bit instruction. */
12186 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12187 && inst
.size_req
!= 4
12188 && !(inst
.operands
[1].imm
& ~0xff))
12190 mask
= 1 << inst
.operands
[0].reg
;
12192 if (inst
.operands
[0].reg
<= 7)
12194 if (inst
.instruction
== T_MNEM_stmia
12195 ? inst
.operands
[0].writeback
12196 : (inst
.operands
[0].writeback
12197 == !(inst
.operands
[1].imm
& mask
)))
12199 if (inst
.instruction
== T_MNEM_stmia
12200 && (inst
.operands
[1].imm
& mask
)
12201 && (inst
.operands
[1].imm
& (mask
- 1)))
12202 as_warn (_("value stored for r%d is UNKNOWN"),
12203 inst
.operands
[0].reg
);
12205 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12206 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12207 inst
.instruction
|= inst
.operands
[1].imm
;
12210 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12212 /* This means 1 register in reg list one of 3 situations:
12213 1. Instruction is stmia, but without writeback.
12214 2. lmdia without writeback, but with Rn not in
12216 3. ldmia with writeback, but with Rn in reglist.
12217 Case 3 is UNPREDICTABLE behaviour, so we handle
12218 case 1 and 2 which can be converted into a 16-bit
12219 str or ldr. The SP cases are handled below. */
12220 unsigned long opcode
;
12221 /* First, record an error for Case 3. */
12222 if (inst
.operands
[1].imm
& mask
12223 && inst
.operands
[0].writeback
)
12225 _("having the base register in the register list when "
12226 "using write back is UNPREDICTABLE");
12228 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12230 inst
.instruction
= THUMB_OP16 (opcode
);
12231 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12232 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12236 else if (inst
.operands
[0] .reg
== REG_SP
)
12238 if (inst
.operands
[0].writeback
)
12241 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12242 ? T_MNEM_push
: T_MNEM_pop
);
12243 inst
.instruction
|= inst
.operands
[1].imm
;
12246 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12249 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12250 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12251 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12259 if (inst
.instruction
< 0xffff)
12260 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12262 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12263 inst
.operands
[1].imm
,
12264 inst
.operands
[0].writeback
);
12269 constraint (inst
.operands
[0].reg
> 7
12270 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12271 constraint (inst
.instruction
!= T_MNEM_ldmia
12272 && inst
.instruction
!= T_MNEM_stmia
,
12273 _("Thumb-2 instruction only valid in unified syntax"));
12274 if (inst
.instruction
== T_MNEM_stmia
)
12276 if (!inst
.operands
[0].writeback
)
12277 as_warn (_("this instruction will write back the base register"));
12278 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12279 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12280 as_warn (_("value stored for r%d is UNKNOWN"),
12281 inst
.operands
[0].reg
);
12285 if (!inst
.operands
[0].writeback
12286 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12287 as_warn (_("this instruction will write back the base register"));
12288 else if (inst
.operands
[0].writeback
12289 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12290 as_warn (_("this instruction will not write back the base register"));
12293 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12294 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12295 inst
.instruction
|= inst
.operands
[1].imm
;
12302 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12303 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12304 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12305 || inst
.operands
[1].negative
,
12308 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12310 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12311 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12312 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12318 if (!inst
.operands
[1].present
)
12320 constraint (inst
.operands
[0].reg
== REG_LR
,
12321 _("r14 not allowed as first register "
12322 "when second register is omitted"));
12323 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12325 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12328 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12329 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12330 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12336 unsigned long opcode
;
12339 if (inst
.operands
[0].isreg
12340 && !inst
.operands
[0].preind
12341 && inst
.operands
[0].reg
== REG_PC
)
12342 set_pred_insn_type_last ();
12344 opcode
= inst
.instruction
;
12345 if (unified_syntax
)
12347 if (!inst
.operands
[1].isreg
)
12349 if (opcode
<= 0xffff)
12350 inst
.instruction
= THUMB_OP32 (opcode
);
12351 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12354 if (inst
.operands
[1].isreg
12355 && !inst
.operands
[1].writeback
12356 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12357 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12358 && opcode
<= 0xffff
12359 && inst
.size_req
!= 4)
12361 /* Insn may have a 16-bit form. */
12362 Rn
= inst
.operands
[1].reg
;
12363 if (inst
.operands
[1].immisreg
)
12365 inst
.instruction
= THUMB_OP16 (opcode
);
12367 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12369 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12370 reject_bad_reg (inst
.operands
[1].imm
);
12372 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12373 && opcode
!= T_MNEM_ldrsb
)
12374 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12375 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12382 if (inst
.relocs
[0].pc_rel
)
12383 opcode
= T_MNEM_ldr_pc2
;
12385 opcode
= T_MNEM_ldr_pc
;
12389 if (opcode
== T_MNEM_ldr
)
12390 opcode
= T_MNEM_ldr_sp
;
12392 opcode
= T_MNEM_str_sp
;
12394 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12398 inst
.instruction
= inst
.operands
[0].reg
;
12399 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12401 inst
.instruction
|= THUMB_OP16 (opcode
);
12402 if (inst
.size_req
== 2)
12403 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12405 inst
.relax
= opcode
;
12409 /* Definitely a 32-bit variant. */
12411 /* Warning for Erratum 752419. */
12412 if (opcode
== T_MNEM_ldr
12413 && inst
.operands
[0].reg
== REG_SP
12414 && inst
.operands
[1].writeback
== 1
12415 && !inst
.operands
[1].immisreg
)
12417 if (no_cpu_selected ()
12418 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12419 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12420 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12421 as_warn (_("This instruction may be unpredictable "
12422 "if executed on M-profile cores "
12423 "with interrupts enabled."));
12426 /* Do some validations regarding addressing modes. */
12427 if (inst
.operands
[1].immisreg
)
12428 reject_bad_reg (inst
.operands
[1].imm
);
12430 constraint (inst
.operands
[1].writeback
== 1
12431 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12434 inst
.instruction
= THUMB_OP32 (opcode
);
12435 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12436 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12437 check_ldr_r15_aligned ();
12441 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12443 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12445 /* Only [Rn,Rm] is acceptable. */
12446 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12447 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12448 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12449 || inst
.operands
[1].negative
,
12450 _("Thumb does not support this addressing mode"));
12451 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12455 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12456 if (!inst
.operands
[1].isreg
)
12457 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12460 constraint (!inst
.operands
[1].preind
12461 || inst
.operands
[1].shifted
12462 || inst
.operands
[1].writeback
,
12463 _("Thumb does not support this addressing mode"));
12464 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12466 constraint (inst
.instruction
& 0x0600,
12467 _("byte or halfword not valid for base register"));
12468 constraint (inst
.operands
[1].reg
== REG_PC
12469 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12470 _("r15 based store not allowed"));
12471 constraint (inst
.operands
[1].immisreg
,
12472 _("invalid base register for register offset"));
12474 if (inst
.operands
[1].reg
== REG_PC
)
12475 inst
.instruction
= T_OPCODE_LDR_PC
;
12476 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12477 inst
.instruction
= T_OPCODE_LDR_SP
;
12479 inst
.instruction
= T_OPCODE_STR_SP
;
12481 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12482 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12486 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12487 if (!inst
.operands
[1].immisreg
)
12489 /* Immediate offset. */
12490 inst
.instruction
|= inst
.operands
[0].reg
;
12491 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12492 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12496 /* Register offset. */
12497 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12498 constraint (inst
.operands
[1].negative
,
12499 _("Thumb does not support this addressing mode"));
12502 switch (inst
.instruction
)
12504 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12505 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12506 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12507 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12508 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12509 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12510 case 0x5600 /* ldrsb */:
12511 case 0x5e00 /* ldrsh */: break;
12515 inst
.instruction
|= inst
.operands
[0].reg
;
12516 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12517 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12523 if (!inst
.operands
[1].present
)
12525 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12526 constraint (inst
.operands
[0].reg
== REG_LR
,
12527 _("r14 not allowed here"));
12528 constraint (inst
.operands
[0].reg
== REG_R12
,
12529 _("r12 not allowed here"));
12532 if (inst
.operands
[2].writeback
12533 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12534 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12535 as_warn (_("base register written back, and overlaps "
12536 "one of transfer registers"));
12538 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12539 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12540 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12546 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12547 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12553 unsigned Rd
, Rn
, Rm
, Ra
;
12555 Rd
= inst
.operands
[0].reg
;
12556 Rn
= inst
.operands
[1].reg
;
12557 Rm
= inst
.operands
[2].reg
;
12558 Ra
= inst
.operands
[3].reg
;
12560 reject_bad_reg (Rd
);
12561 reject_bad_reg (Rn
);
12562 reject_bad_reg (Rm
);
12563 reject_bad_reg (Ra
);
12565 inst
.instruction
|= Rd
<< 8;
12566 inst
.instruction
|= Rn
<< 16;
12567 inst
.instruction
|= Rm
;
12568 inst
.instruction
|= Ra
<< 12;
12574 unsigned RdLo
, RdHi
, Rn
, Rm
;
12576 RdLo
= inst
.operands
[0].reg
;
12577 RdHi
= inst
.operands
[1].reg
;
12578 Rn
= inst
.operands
[2].reg
;
12579 Rm
= inst
.operands
[3].reg
;
12581 reject_bad_reg (RdLo
);
12582 reject_bad_reg (RdHi
);
12583 reject_bad_reg (Rn
);
12584 reject_bad_reg (Rm
);
12586 inst
.instruction
|= RdLo
<< 12;
12587 inst
.instruction
|= RdHi
<< 8;
12588 inst
.instruction
|= Rn
<< 16;
12589 inst
.instruction
|= Rm
;
12593 do_t_mov_cmp (void)
12597 Rn
= inst
.operands
[0].reg
;
12598 Rm
= inst
.operands
[1].reg
;
12601 set_pred_insn_type_last ();
12603 if (unified_syntax
)
12605 int r0off
= (inst
.instruction
== T_MNEM_mov
12606 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12607 unsigned long opcode
;
12608 bfd_boolean narrow
;
12609 bfd_boolean low_regs
;
12611 low_regs
= (Rn
<= 7 && Rm
<= 7);
12612 opcode
= inst
.instruction
;
12613 if (in_pred_block ())
12614 narrow
= opcode
!= T_MNEM_movs
;
12616 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12617 if (inst
.size_req
== 4
12618 || inst
.operands
[1].shifted
)
12621 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12622 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12623 && !inst
.operands
[1].shifted
12627 inst
.instruction
= T2_SUBS_PC_LR
;
12631 if (opcode
== T_MNEM_cmp
)
12633 constraint (Rn
== REG_PC
, BAD_PC
);
12636 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12638 warn_deprecated_sp (Rm
);
12639 /* R15 was documented as a valid choice for Rm in ARMv6,
12640 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12641 tools reject R15, so we do too. */
12642 constraint (Rm
== REG_PC
, BAD_PC
);
12645 reject_bad_reg (Rm
);
12647 else if (opcode
== T_MNEM_mov
12648 || opcode
== T_MNEM_movs
)
12650 if (inst
.operands
[1].isreg
)
12652 if (opcode
== T_MNEM_movs
)
12654 reject_bad_reg (Rn
);
12655 reject_bad_reg (Rm
);
12659 /* This is mov.n. */
12660 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12661 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12663 as_tsktsk (_("Use of r%u as a source register is "
12664 "deprecated when r%u is the destination "
12665 "register."), Rm
, Rn
);
12670 /* This is mov.w. */
12671 constraint (Rn
== REG_PC
, BAD_PC
);
12672 constraint (Rm
== REG_PC
, BAD_PC
);
12673 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12674 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12678 reject_bad_reg (Rn
);
12681 if (!inst
.operands
[1].isreg
)
12683 /* Immediate operand. */
12684 if (!in_pred_block () && opcode
== T_MNEM_mov
)
12686 if (low_regs
&& narrow
)
12688 inst
.instruction
= THUMB_OP16 (opcode
);
12689 inst
.instruction
|= Rn
<< 8;
12690 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12691 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12693 if (inst
.size_req
== 2)
12694 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12696 inst
.relax
= opcode
;
12701 constraint ((inst
.relocs
[0].type
12702 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12703 && (inst
.relocs
[0].type
12704 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12705 THUMB1_RELOC_ONLY
);
12707 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12708 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12709 inst
.instruction
|= Rn
<< r0off
;
12710 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12713 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12714 && (inst
.instruction
== T_MNEM_mov
12715 || inst
.instruction
== T_MNEM_movs
))
12717 /* Register shifts are encoded as separate shift instructions. */
12718 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12720 if (in_pred_block ())
12725 if (inst
.size_req
== 4)
12728 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12734 switch (inst
.operands
[1].shift_kind
)
12737 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12740 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12743 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12746 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12752 inst
.instruction
= opcode
;
12755 inst
.instruction
|= Rn
;
12756 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12761 inst
.instruction
|= CONDS_BIT
;
12763 inst
.instruction
|= Rn
<< 8;
12764 inst
.instruction
|= Rm
<< 16;
12765 inst
.instruction
|= inst
.operands
[1].imm
;
12770 /* Some mov with immediate shift have narrow variants.
12771 Register shifts are handled above. */
12772 if (low_regs
&& inst
.operands
[1].shifted
12773 && (inst
.instruction
== T_MNEM_mov
12774 || inst
.instruction
== T_MNEM_movs
))
12776 if (in_pred_block ())
12777 narrow
= (inst
.instruction
== T_MNEM_mov
);
12779 narrow
= (inst
.instruction
== T_MNEM_movs
);
12784 switch (inst
.operands
[1].shift_kind
)
12786 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12787 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12788 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12789 default: narrow
= FALSE
; break;
12795 inst
.instruction
|= Rn
;
12796 inst
.instruction
|= Rm
<< 3;
12797 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12801 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12802 inst
.instruction
|= Rn
<< r0off
;
12803 encode_thumb32_shifted_operand (1);
12807 switch (inst
.instruction
)
12810 /* In v4t or v5t a move of two lowregs produces unpredictable
12811 results. Don't allow this. */
12814 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12815 "MOV Rd, Rs with two low registers is not "
12816 "permitted on this architecture");
12817 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12821 inst
.instruction
= T_OPCODE_MOV_HR
;
12822 inst
.instruction
|= (Rn
& 0x8) << 4;
12823 inst
.instruction
|= (Rn
& 0x7);
12824 inst
.instruction
|= Rm
<< 3;
12828 /* We know we have low registers at this point.
12829 Generate LSLS Rd, Rs, #0. */
12830 inst
.instruction
= T_OPCODE_LSL_I
;
12831 inst
.instruction
|= Rn
;
12832 inst
.instruction
|= Rm
<< 3;
12838 inst
.instruction
= T_OPCODE_CMP_LR
;
12839 inst
.instruction
|= Rn
;
12840 inst
.instruction
|= Rm
<< 3;
12844 inst
.instruction
= T_OPCODE_CMP_HR
;
12845 inst
.instruction
|= (Rn
& 0x8) << 4;
12846 inst
.instruction
|= (Rn
& 0x7);
12847 inst
.instruction
|= Rm
<< 3;
12854 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12856 /* PR 10443: Do not silently ignore shifted operands. */
12857 constraint (inst
.operands
[1].shifted
,
12858 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12860 if (inst
.operands
[1].isreg
)
12862 if (Rn
< 8 && Rm
< 8)
12864 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12865 since a MOV instruction produces unpredictable results. */
12866 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12867 inst
.instruction
= T_OPCODE_ADD_I3
;
12869 inst
.instruction
= T_OPCODE_CMP_LR
;
12871 inst
.instruction
|= Rn
;
12872 inst
.instruction
|= Rm
<< 3;
12876 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12877 inst
.instruction
= T_OPCODE_MOV_HR
;
12879 inst
.instruction
= T_OPCODE_CMP_HR
;
12885 constraint (Rn
> 7,
12886 _("only lo regs allowed with immediate"));
12887 inst
.instruction
|= Rn
<< 8;
12888 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12899 top
= (inst
.instruction
& 0x00800000) != 0;
12900 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
12902 constraint (top
, _(":lower16: not allowed in this instruction"));
12903 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
12905 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
12907 constraint (!top
, _(":upper16: not allowed in this instruction"));
12908 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
12911 Rd
= inst
.operands
[0].reg
;
12912 reject_bad_reg (Rd
);
12914 inst
.instruction
|= Rd
<< 8;
12915 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
12917 imm
= inst
.relocs
[0].exp
.X_add_number
;
12918 inst
.instruction
|= (imm
& 0xf000) << 4;
12919 inst
.instruction
|= (imm
& 0x0800) << 15;
12920 inst
.instruction
|= (imm
& 0x0700) << 4;
12921 inst
.instruction
|= (imm
& 0x00ff);
12926 do_t_mvn_tst (void)
12930 Rn
= inst
.operands
[0].reg
;
12931 Rm
= inst
.operands
[1].reg
;
12933 if (inst
.instruction
== T_MNEM_cmp
12934 || inst
.instruction
== T_MNEM_cmn
)
12935 constraint (Rn
== REG_PC
, BAD_PC
);
12937 reject_bad_reg (Rn
);
12938 reject_bad_reg (Rm
);
12940 if (unified_syntax
)
12942 int r0off
= (inst
.instruction
== T_MNEM_mvn
12943 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12944 bfd_boolean narrow
;
12946 if (inst
.size_req
== 4
12947 || inst
.instruction
> 0xffff
12948 || inst
.operands
[1].shifted
12949 || Rn
> 7 || Rm
> 7)
12951 else if (inst
.instruction
== T_MNEM_cmn
12952 || inst
.instruction
== T_MNEM_tst
)
12954 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12955 narrow
= !in_pred_block ();
12957 narrow
= in_pred_block ();
12959 if (!inst
.operands
[1].isreg
)
12961 /* For an immediate, we always generate a 32-bit opcode;
12962 section relaxation will shrink it later if possible. */
12963 if (inst
.instruction
< 0xffff)
12964 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12965 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12966 inst
.instruction
|= Rn
<< r0off
;
12967 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12971 /* See if we can do this with a 16-bit instruction. */
12974 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12975 inst
.instruction
|= Rn
;
12976 inst
.instruction
|= Rm
<< 3;
12980 constraint (inst
.operands
[1].shifted
12981 && inst
.operands
[1].immisreg
,
12982 _("shift must be constant"));
12983 if (inst
.instruction
< 0xffff)
12984 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12985 inst
.instruction
|= Rn
<< r0off
;
12986 encode_thumb32_shifted_operand (1);
12992 constraint (inst
.instruction
> 0xffff
12993 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12994 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12995 _("unshifted register required"));
12996 constraint (Rn
> 7 || Rm
> 7,
12999 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13000 inst
.instruction
|= Rn
;
13001 inst
.instruction
|= Rm
<< 3;
13010 if (do_vfp_nsyn_mrs () == SUCCESS
)
13013 Rd
= inst
.operands
[0].reg
;
13014 reject_bad_reg (Rd
);
13015 inst
.instruction
|= Rd
<< 8;
13017 if (inst
.operands
[1].isreg
)
13019 unsigned br
= inst
.operands
[1].reg
;
13020 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13021 as_bad (_("bad register for mrs"));
13023 inst
.instruction
|= br
& (0xf << 16);
13024 inst
.instruction
|= (br
& 0x300) >> 4;
13025 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13029 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13031 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13033 /* PR gas/12698: The constraint is only applied for m_profile.
13034 If the user has specified -march=all, we want to ignore it as
13035 we are building for any CPU type, including non-m variants. */
13036 bfd_boolean m_profile
=
13037 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13038 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13039 "not support requested special purpose register"));
13042 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13044 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13045 _("'APSR', 'CPSR' or 'SPSR' expected"));
13047 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13048 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13049 inst
.instruction
|= 0xf0000;
13059 if (do_vfp_nsyn_msr () == SUCCESS
)
13062 constraint (!inst
.operands
[1].isreg
,
13063 _("Thumb encoding does not support an immediate here"));
13065 if (inst
.operands
[0].isreg
)
13066 flags
= (int)(inst
.operands
[0].reg
);
13068 flags
= inst
.operands
[0].imm
;
13070 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13072 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13074 /* PR gas/12698: The constraint is only applied for m_profile.
13075 If the user has specified -march=all, we want to ignore it as
13076 we are building for any CPU type, including non-m variants. */
13077 bfd_boolean m_profile
=
13078 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13079 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13080 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13081 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13082 && bits
!= PSR_f
)) && m_profile
,
13083 _("selected processor does not support requested special "
13084 "purpose register"));
13087 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13088 "requested special purpose register"));
13090 Rn
= inst
.operands
[1].reg
;
13091 reject_bad_reg (Rn
);
13093 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13094 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13095 inst
.instruction
|= (flags
& 0x300) >> 4;
13096 inst
.instruction
|= (flags
& 0xff);
13097 inst
.instruction
|= Rn
<< 16;
13103 bfd_boolean narrow
;
13104 unsigned Rd
, Rn
, Rm
;
13106 if (!inst
.operands
[2].present
)
13107 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13109 Rd
= inst
.operands
[0].reg
;
13110 Rn
= inst
.operands
[1].reg
;
13111 Rm
= inst
.operands
[2].reg
;
13113 if (unified_syntax
)
13115 if (inst
.size_req
== 4
13121 else if (inst
.instruction
== T_MNEM_muls
)
13122 narrow
= !in_pred_block ();
13124 narrow
= in_pred_block ();
13128 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13129 constraint (Rn
> 7 || Rm
> 7,
13136 /* 16-bit MULS/Conditional MUL. */
13137 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13138 inst
.instruction
|= Rd
;
13141 inst
.instruction
|= Rm
<< 3;
13143 inst
.instruction
|= Rn
<< 3;
13145 constraint (1, _("dest must overlap one source register"));
13149 constraint (inst
.instruction
!= T_MNEM_mul
,
13150 _("Thumb-2 MUL must not set flags"));
13152 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13153 inst
.instruction
|= Rd
<< 8;
13154 inst
.instruction
|= Rn
<< 16;
13155 inst
.instruction
|= Rm
<< 0;
13157 reject_bad_reg (Rd
);
13158 reject_bad_reg (Rn
);
13159 reject_bad_reg (Rm
);
13166 unsigned RdLo
, RdHi
, Rn
, Rm
;
13168 RdLo
= inst
.operands
[0].reg
;
13169 RdHi
= inst
.operands
[1].reg
;
13170 Rn
= inst
.operands
[2].reg
;
13171 Rm
= inst
.operands
[3].reg
;
13173 reject_bad_reg (RdLo
);
13174 reject_bad_reg (RdHi
);
13175 reject_bad_reg (Rn
);
13176 reject_bad_reg (Rm
);
13178 inst
.instruction
|= RdLo
<< 12;
13179 inst
.instruction
|= RdHi
<< 8;
13180 inst
.instruction
|= Rn
<< 16;
13181 inst
.instruction
|= Rm
;
13184 as_tsktsk (_("rdhi and rdlo must be different"));
13190 set_pred_insn_type (NEUTRAL_IT_INSN
);
13192 if (unified_syntax
)
13194 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13196 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13197 inst
.instruction
|= inst
.operands
[0].imm
;
13201 /* PR9722: Check for Thumb2 availability before
13202 generating a thumb2 nop instruction. */
13203 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13205 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13206 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13209 inst
.instruction
= 0x46c0;
13214 constraint (inst
.operands
[0].present
,
13215 _("Thumb does not support NOP with hints"));
13216 inst
.instruction
= 0x46c0;
13223 if (unified_syntax
)
13225 bfd_boolean narrow
;
13227 if (THUMB_SETS_FLAGS (inst
.instruction
))
13228 narrow
= !in_pred_block ();
13230 narrow
= in_pred_block ();
13231 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13233 if (inst
.size_req
== 4)
13238 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13239 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13240 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13244 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13245 inst
.instruction
|= inst
.operands
[0].reg
;
13246 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13251 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13253 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13255 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13256 inst
.instruction
|= inst
.operands
[0].reg
;
13257 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13266 Rd
= inst
.operands
[0].reg
;
13267 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13269 reject_bad_reg (Rd
);
13270 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13271 reject_bad_reg (Rn
);
13273 inst
.instruction
|= Rd
<< 8;
13274 inst
.instruction
|= Rn
<< 16;
13276 if (!inst
.operands
[2].isreg
)
13278 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13279 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13285 Rm
= inst
.operands
[2].reg
;
13286 reject_bad_reg (Rm
);
13288 constraint (inst
.operands
[2].shifted
13289 && inst
.operands
[2].immisreg
,
13290 _("shift must be constant"));
13291 encode_thumb32_shifted_operand (2);
13298 unsigned Rd
, Rn
, Rm
;
13300 Rd
= inst
.operands
[0].reg
;
13301 Rn
= inst
.operands
[1].reg
;
13302 Rm
= inst
.operands
[2].reg
;
13304 reject_bad_reg (Rd
);
13305 reject_bad_reg (Rn
);
13306 reject_bad_reg (Rm
);
13308 inst
.instruction
|= Rd
<< 8;
13309 inst
.instruction
|= Rn
<< 16;
13310 inst
.instruction
|= Rm
;
13311 if (inst
.operands
[3].present
)
13313 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13314 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13315 _("expression too complex"));
13316 inst
.instruction
|= (val
& 0x1c) << 10;
13317 inst
.instruction
|= (val
& 0x03) << 6;
13324 if (!inst
.operands
[3].present
)
13328 inst
.instruction
&= ~0x00000020;
13330 /* PR 10168. Swap the Rm and Rn registers. */
13331 Rtmp
= inst
.operands
[1].reg
;
13332 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13333 inst
.operands
[2].reg
= Rtmp
;
13341 if (inst
.operands
[0].immisreg
)
13342 reject_bad_reg (inst
.operands
[0].imm
);
13344 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13348 do_t_push_pop (void)
13352 constraint (inst
.operands
[0].writeback
,
13353 _("push/pop do not support {reglist}^"));
13354 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13355 _("expression too complex"));
13357 mask
= inst
.operands
[0].imm
;
13358 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13359 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13360 else if (inst
.size_req
!= 4
13361 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13362 ? REG_LR
: REG_PC
)))
13364 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13365 inst
.instruction
|= THUMB_PP_PC_LR
;
13366 inst
.instruction
|= mask
& 0xff;
13368 else if (unified_syntax
)
13370 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13371 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13375 inst
.error
= _("invalid register list to push/pop instruction");
13383 if (unified_syntax
)
13384 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13387 inst
.error
= _("invalid register list to push/pop instruction");
13393 do_t_vscclrm (void)
13395 if (inst
.operands
[0].issingle
)
13397 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13398 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13399 inst
.instruction
|= inst
.operands
[0].imm
;
13403 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13404 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13405 inst
.instruction
|= 1 << 8;
13406 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13415 Rd
= inst
.operands
[0].reg
;
13416 Rm
= inst
.operands
[1].reg
;
13418 reject_bad_reg (Rd
);
13419 reject_bad_reg (Rm
);
13421 inst
.instruction
|= Rd
<< 8;
13422 inst
.instruction
|= Rm
<< 16;
13423 inst
.instruction
|= Rm
;
13431 Rd
= inst
.operands
[0].reg
;
13432 Rm
= inst
.operands
[1].reg
;
13434 reject_bad_reg (Rd
);
13435 reject_bad_reg (Rm
);
13437 if (Rd
<= 7 && Rm
<= 7
13438 && inst
.size_req
!= 4)
13440 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13441 inst
.instruction
|= Rd
;
13442 inst
.instruction
|= Rm
<< 3;
13444 else if (unified_syntax
)
13446 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13447 inst
.instruction
|= Rd
<< 8;
13448 inst
.instruction
|= Rm
<< 16;
13449 inst
.instruction
|= Rm
;
13452 inst
.error
= BAD_HIREG
;
13460 Rd
= inst
.operands
[0].reg
;
13461 Rm
= inst
.operands
[1].reg
;
13463 reject_bad_reg (Rd
);
13464 reject_bad_reg (Rm
);
13466 inst
.instruction
|= Rd
<< 8;
13467 inst
.instruction
|= Rm
;
13475 Rd
= inst
.operands
[0].reg
;
13476 Rs
= (inst
.operands
[1].present
13477 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13478 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13480 reject_bad_reg (Rd
);
13481 reject_bad_reg (Rs
);
13482 if (inst
.operands
[2].isreg
)
13483 reject_bad_reg (inst
.operands
[2].reg
);
13485 inst
.instruction
|= Rd
<< 8;
13486 inst
.instruction
|= Rs
<< 16;
13487 if (!inst
.operands
[2].isreg
)
13489 bfd_boolean narrow
;
13491 if ((inst
.instruction
& 0x00100000) != 0)
13492 narrow
= !in_pred_block ();
13494 narrow
= in_pred_block ();
13496 if (Rd
> 7 || Rs
> 7)
13499 if (inst
.size_req
== 4 || !unified_syntax
)
13502 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13503 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13506 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13507 relaxation, but it doesn't seem worth the hassle. */
13510 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13511 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13512 inst
.instruction
|= Rs
<< 3;
13513 inst
.instruction
|= Rd
;
13517 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13518 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13522 encode_thumb32_shifted_operand (2);
13528 if (warn_on_deprecated
13529 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13530 as_tsktsk (_("setend use is deprecated for ARMv8"));
13532 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13533 if (inst
.operands
[0].imm
)
13534 inst
.instruction
|= 0x8;
13540 if (!inst
.operands
[1].present
)
13541 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13543 if (unified_syntax
)
13545 bfd_boolean narrow
;
13548 switch (inst
.instruction
)
13551 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13553 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13555 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13557 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13561 if (THUMB_SETS_FLAGS (inst
.instruction
))
13562 narrow
= !in_pred_block ();
13564 narrow
= in_pred_block ();
13565 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13567 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13569 if (inst
.operands
[2].isreg
13570 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13571 || inst
.operands
[2].reg
> 7))
13573 if (inst
.size_req
== 4)
13576 reject_bad_reg (inst
.operands
[0].reg
);
13577 reject_bad_reg (inst
.operands
[1].reg
);
13581 if (inst
.operands
[2].isreg
)
13583 reject_bad_reg (inst
.operands
[2].reg
);
13584 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13585 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13586 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13587 inst
.instruction
|= inst
.operands
[2].reg
;
13589 /* PR 12854: Error on extraneous shifts. */
13590 constraint (inst
.operands
[2].shifted
,
13591 _("extraneous shift as part of operand to shift insn"));
13595 inst
.operands
[1].shifted
= 1;
13596 inst
.operands
[1].shift_kind
= shift_kind
;
13597 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13598 ? T_MNEM_movs
: T_MNEM_mov
);
13599 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13600 encode_thumb32_shifted_operand (1);
13601 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13602 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13607 if (inst
.operands
[2].isreg
)
13609 switch (shift_kind
)
13611 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13612 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13613 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13614 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13618 inst
.instruction
|= inst
.operands
[0].reg
;
13619 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13621 /* PR 12854: Error on extraneous shifts. */
13622 constraint (inst
.operands
[2].shifted
,
13623 _("extraneous shift as part of operand to shift insn"));
13627 switch (shift_kind
)
13629 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13630 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13631 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13634 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13635 inst
.instruction
|= inst
.operands
[0].reg
;
13636 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13642 constraint (inst
.operands
[0].reg
> 7
13643 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13644 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13646 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13648 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13649 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13650 _("source1 and dest must be same register"));
13652 switch (inst
.instruction
)
13654 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13655 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13656 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13657 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13661 inst
.instruction
|= inst
.operands
[0].reg
;
13662 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13664 /* PR 12854: Error on extraneous shifts. */
13665 constraint (inst
.operands
[2].shifted
,
13666 _("extraneous shift as part of operand to shift insn"));
13670 switch (inst
.instruction
)
13672 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13673 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13674 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13675 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13678 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13679 inst
.instruction
|= inst
.operands
[0].reg
;
13680 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13688 unsigned Rd
, Rn
, Rm
;
13690 Rd
= inst
.operands
[0].reg
;
13691 Rn
= inst
.operands
[1].reg
;
13692 Rm
= inst
.operands
[2].reg
;
13694 reject_bad_reg (Rd
);
13695 reject_bad_reg (Rn
);
13696 reject_bad_reg (Rm
);
13698 inst
.instruction
|= Rd
<< 8;
13699 inst
.instruction
|= Rn
<< 16;
13700 inst
.instruction
|= Rm
;
13706 unsigned Rd
, Rn
, Rm
;
13708 Rd
= inst
.operands
[0].reg
;
13709 Rm
= inst
.operands
[1].reg
;
13710 Rn
= inst
.operands
[2].reg
;
13712 reject_bad_reg (Rd
);
13713 reject_bad_reg (Rn
);
13714 reject_bad_reg (Rm
);
13716 inst
.instruction
|= Rd
<< 8;
13717 inst
.instruction
|= Rn
<< 16;
13718 inst
.instruction
|= Rm
;
13724 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13725 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13726 _("SMC is not permitted on this architecture"));
13727 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13728 _("expression too complex"));
13729 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13730 inst
.instruction
|= (value
& 0xf000) >> 12;
13731 inst
.instruction
|= (value
& 0x0ff0);
13732 inst
.instruction
|= (value
& 0x000f) << 16;
13733 /* PR gas/15623: SMC instructions must be last in an IT block. */
13734 set_pred_insn_type_last ();
13740 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13742 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13743 inst
.instruction
|= (value
& 0x0fff);
13744 inst
.instruction
|= (value
& 0xf000) << 4;
13748 do_t_ssat_usat (int bias
)
13752 Rd
= inst
.operands
[0].reg
;
13753 Rn
= inst
.operands
[2].reg
;
13755 reject_bad_reg (Rd
);
13756 reject_bad_reg (Rn
);
13758 inst
.instruction
|= Rd
<< 8;
13759 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13760 inst
.instruction
|= Rn
<< 16;
13762 if (inst
.operands
[3].present
)
13764 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
13766 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13768 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13769 _("expression too complex"));
13771 if (shift_amount
!= 0)
13773 constraint (shift_amount
> 31,
13774 _("shift expression is too large"));
13776 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13777 inst
.instruction
|= 0x00200000; /* sh bit. */
13779 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13780 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13788 do_t_ssat_usat (1);
13796 Rd
= inst
.operands
[0].reg
;
13797 Rn
= inst
.operands
[2].reg
;
13799 reject_bad_reg (Rd
);
13800 reject_bad_reg (Rn
);
13802 inst
.instruction
|= Rd
<< 8;
13803 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13804 inst
.instruction
|= Rn
<< 16;
13810 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13811 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13812 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13813 || inst
.operands
[2].negative
,
13816 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13818 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13819 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13820 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13821 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13827 if (!inst
.operands
[2].present
)
13828 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13830 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13831 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13832 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13835 inst
.instruction
|= inst
.operands
[0].reg
;
13836 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13837 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13838 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13844 unsigned Rd
, Rn
, Rm
;
13846 Rd
= inst
.operands
[0].reg
;
13847 Rn
= inst
.operands
[1].reg
;
13848 Rm
= inst
.operands
[2].reg
;
13850 reject_bad_reg (Rd
);
13851 reject_bad_reg (Rn
);
13852 reject_bad_reg (Rm
);
13854 inst
.instruction
|= Rd
<< 8;
13855 inst
.instruction
|= Rn
<< 16;
13856 inst
.instruction
|= Rm
;
13857 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13865 Rd
= inst
.operands
[0].reg
;
13866 Rm
= inst
.operands
[1].reg
;
13868 reject_bad_reg (Rd
);
13869 reject_bad_reg (Rm
);
13871 if (inst
.instruction
<= 0xffff
13872 && inst
.size_req
!= 4
13873 && Rd
<= 7 && Rm
<= 7
13874 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13876 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13877 inst
.instruction
|= Rd
;
13878 inst
.instruction
|= Rm
<< 3;
13880 else if (unified_syntax
)
13882 if (inst
.instruction
<= 0xffff)
13883 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13884 inst
.instruction
|= Rd
<< 8;
13885 inst
.instruction
|= Rm
;
13886 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13890 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13891 _("Thumb encoding does not support rotation"));
13892 constraint (1, BAD_HIREG
);
13899 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
13908 half
= (inst
.instruction
& 0x10) != 0;
13909 set_pred_insn_type_last ();
13910 constraint (inst
.operands
[0].immisreg
,
13911 _("instruction requires register index"));
13913 Rn
= inst
.operands
[0].reg
;
13914 Rm
= inst
.operands
[0].imm
;
13916 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13917 constraint (Rn
== REG_SP
, BAD_SP
);
13918 reject_bad_reg (Rm
);
13920 constraint (!half
&& inst
.operands
[0].shifted
,
13921 _("instruction does not allow shifted index"));
13922 inst
.instruction
|= (Rn
<< 16) | Rm
;
13928 if (!inst
.operands
[0].present
)
13929 inst
.operands
[0].imm
= 0;
13931 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13933 constraint (inst
.size_req
== 2,
13934 _("immediate value out of range"));
13935 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13936 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13937 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13941 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13942 inst
.instruction
|= inst
.operands
[0].imm
;
13945 set_pred_insn_type (NEUTRAL_IT_INSN
);
13952 do_t_ssat_usat (0);
13960 Rd
= inst
.operands
[0].reg
;
13961 Rn
= inst
.operands
[2].reg
;
13963 reject_bad_reg (Rd
);
13964 reject_bad_reg (Rn
);
13966 inst
.instruction
|= Rd
<< 8;
13967 inst
.instruction
|= inst
.operands
[1].imm
;
13968 inst
.instruction
|= Rn
<< 16;
13971 /* Checking the range of the branch offset (VAL) with NBITS bits
13972 and IS_SIGNED signedness. Also checks the LSB to be 0. */
13974 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
13976 gas_assert (nbits
> 0 && nbits
<= 32);
13979 int cmp
= (1 << (nbits
- 1));
13980 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
13985 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
13991 /* For branches in Armv8.1-M Mainline. */
13993 do_t_branch_future (void)
13995 unsigned long insn
= inst
.instruction
;
13997 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13998 if (inst
.operands
[0].hasreloc
== 0)
14000 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
14001 as_bad (BAD_BRANCH_OFF
);
14003 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
14007 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
14008 inst
.relocs
[0].pc_rel
= 1;
14014 if (inst
.operands
[1].hasreloc
== 0)
14016 int val
= inst
.operands
[1].imm
;
14017 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
14018 as_bad (BAD_BRANCH_OFF
);
14020 int immA
= (val
& 0x0001f000) >> 12;
14021 int immB
= (val
& 0x00000ffc) >> 2;
14022 int immC
= (val
& 0x00000002) >> 1;
14023 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14027 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14028 inst
.relocs
[1].pc_rel
= 1;
14033 if (inst
.operands
[1].hasreloc
== 0)
14035 int val
= inst
.operands
[1].imm
;
14036 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14037 as_bad (BAD_BRANCH_OFF
);
14039 int immA
= (val
& 0x0007f000) >> 12;
14040 int immB
= (val
& 0x00000ffc) >> 2;
14041 int immC
= (val
& 0x00000002) >> 1;
14042 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14046 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14047 inst
.relocs
[1].pc_rel
= 1;
14051 case T_MNEM_bfcsel
:
14053 if (inst
.operands
[1].hasreloc
== 0)
14055 int val
= inst
.operands
[1].imm
;
14056 int immA
= (val
& 0x00001000) >> 12;
14057 int immB
= (val
& 0x00000ffc) >> 2;
14058 int immC
= (val
& 0x00000002) >> 1;
14059 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14063 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14064 inst
.relocs
[1].pc_rel
= 1;
14068 if (inst
.operands
[2].hasreloc
== 0)
14070 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14071 int val2
= inst
.operands
[2].imm
;
14072 int val0
= inst
.operands
[0].imm
& 0x1f;
14073 int diff
= val2
- val0
;
14075 inst
.instruction
|= 1 << 17; /* T bit. */
14076 else if (diff
!= 2)
14077 as_bad (_("out of range label-relative fixup value"));
14081 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14082 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14083 inst
.relocs
[2].pc_rel
= 1;
14087 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14088 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14093 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14100 /* Helper function for do_t_loloop to handle relocations. */
14102 v8_1_loop_reloc (int is_le
)
14104 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14106 int value
= inst
.relocs
[0].exp
.X_add_number
;
14107 value
= (is_le
) ? -value
: value
;
14109 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14110 as_bad (BAD_BRANCH_OFF
);
14114 immh
= (value
& 0x00000ffc) >> 2;
14115 imml
= (value
& 0x00000002) >> 1;
14117 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14121 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14122 inst
.relocs
[0].pc_rel
= 1;
14126 /* MVE instruction encoder helpers. */
14127 #define M_MNEM_vabav 0xee800f01
14128 #define M_MNEM_vmladav 0xeef00e00
14129 #define M_MNEM_vmladava 0xeef00e20
14130 #define M_MNEM_vmladavx 0xeef01e00
14131 #define M_MNEM_vmladavax 0xeef01e20
14132 #define M_MNEM_vmlsdav 0xeef00e01
14133 #define M_MNEM_vmlsdava 0xeef00e21
14134 #define M_MNEM_vmlsdavx 0xeef01e01
14135 #define M_MNEM_vmlsdavax 0xeef01e21
14136 #define M_MNEM_vmullt 0xee011e00
14137 #define M_MNEM_vmullb 0xee010e00
14138 #define M_MNEM_vst20 0xfc801e00
14139 #define M_MNEM_vst21 0xfc801e20
14140 #define M_MNEM_vst40 0xfc801e01
14141 #define M_MNEM_vst41 0xfc801e21
14142 #define M_MNEM_vst42 0xfc801e41
14143 #define M_MNEM_vst43 0xfc801e61
14144 #define M_MNEM_vld20 0xfc901e00
14145 #define M_MNEM_vld21 0xfc901e20
14146 #define M_MNEM_vld40 0xfc901e01
14147 #define M_MNEM_vld41 0xfc901e21
14148 #define M_MNEM_vld42 0xfc901e41
14149 #define M_MNEM_vld43 0xfc901e61
14150 #define M_MNEM_vstrb 0xec000e00
14151 #define M_MNEM_vstrh 0xec000e10
14152 #define M_MNEM_vstrw 0xec000e40
14153 #define M_MNEM_vstrd 0xec000e50
14154 #define M_MNEM_vldrb 0xec100e00
14155 #define M_MNEM_vldrh 0xec100e10
14156 #define M_MNEM_vldrw 0xec100e40
14157 #define M_MNEM_vldrd 0xec100e50
14158 #define M_MNEM_vmovlt 0xeea01f40
14159 #define M_MNEM_vmovlb 0xeea00f40
14160 #define M_MNEM_vmovnt 0xfe311e81
14161 #define M_MNEM_vmovnb 0xfe310e81
14162 #define M_MNEM_vadc 0xee300f00
14163 #define M_MNEM_vadci 0xee301f00
14164 #define M_MNEM_vbrsr 0xfe011e60
14165 #define M_MNEM_vaddlv 0xee890f00
14166 #define M_MNEM_vaddlva 0xee890f20
14167 #define M_MNEM_vaddv 0xeef10f00
14168 #define M_MNEM_vaddva 0xeef10f20
14169 #define M_MNEM_vddup 0xee011f6e
14170 #define M_MNEM_vdwdup 0xee011f60
14171 #define M_MNEM_vidup 0xee010f6e
14172 #define M_MNEM_viwdup 0xee010f60
14173 #define M_MNEM_vmaxv 0xeee20f00
14174 #define M_MNEM_vmaxav 0xeee00f00
14175 #define M_MNEM_vminv 0xeee20f80
14176 #define M_MNEM_vminav 0xeee00f80
14177 #define M_MNEM_vmlaldav 0xee800e00
14178 #define M_MNEM_vmlaldava 0xee800e20
14179 #define M_MNEM_vmlaldavx 0xee801e00
14180 #define M_MNEM_vmlaldavax 0xee801e20
14181 #define M_MNEM_vmlsldav 0xee800e01
14182 #define M_MNEM_vmlsldava 0xee800e21
14183 #define M_MNEM_vmlsldavx 0xee801e01
14184 #define M_MNEM_vmlsldavax 0xee801e21
14185 #define M_MNEM_vrmlaldavhx 0xee801f00
14186 #define M_MNEM_vrmlaldavhax 0xee801f20
14187 #define M_MNEM_vrmlsldavh 0xfe800e01
14188 #define M_MNEM_vrmlsldavha 0xfe800e21
14189 #define M_MNEM_vrmlsldavhx 0xfe801e01
14190 #define M_MNEM_vrmlsldavhax 0xfe801e21
14191 #define M_MNEM_vqmovnt 0xee331e01
14192 #define M_MNEM_vqmovnb 0xee330e01
14193 #define M_MNEM_vqmovunt 0xee311e81
14194 #define M_MNEM_vqmovunb 0xee310e81
14195 #define M_MNEM_vshrnt 0xee801fc1
14196 #define M_MNEM_vshrnb 0xee800fc1
14197 #define M_MNEM_vrshrnt 0xfe801fc1
14198 #define M_MNEM_vqshrnt 0xee801f40
14199 #define M_MNEM_vqshrnb 0xee800f40
14200 #define M_MNEM_vqshrunt 0xee801fc0
14201 #define M_MNEM_vqshrunb 0xee800fc0
14202 #define M_MNEM_vrshrnb 0xfe800fc1
14203 #define M_MNEM_vqrshrnt 0xee801f41
14204 #define M_MNEM_vqrshrnb 0xee800f41
14205 #define M_MNEM_vqrshrunt 0xfe801fc0
14206 #define M_MNEM_vqrshrunb 0xfe800fc0
14208 /* Neon instruction encoder helpers. */
14210 /* Encodings for the different types for various Neon opcodes. */
14212 /* An "invalid" code for the following tables. */
14215 struct neon_tab_entry
14218 unsigned float_or_poly
;
14219 unsigned scalar_or_imm
;
14222 /* Map overloaded Neon opcodes to their respective encodings. */
14223 #define NEON_ENC_TAB \
14224 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14225 X(vabdl, 0x0800700, N_INV, N_INV), \
14226 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14227 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14228 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14229 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14230 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14231 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14232 X(vaddl, 0x0800000, N_INV, N_INV), \
14233 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14234 X(vsubl, 0x0800200, N_INV, N_INV), \
14235 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14236 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14237 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14238 /* Register variants of the following two instructions are encoded as
14239 vcge / vcgt with the operands reversed. */ \
14240 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14241 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14242 X(vfma, N_INV, 0x0000c10, N_INV), \
14243 X(vfms, N_INV, 0x0200c10, N_INV), \
14244 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14245 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14246 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14247 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14248 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14249 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14250 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14251 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14252 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14253 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14254 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14255 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14256 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14257 X(vshl, 0x0000400, N_INV, 0x0800510), \
14258 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14259 X(vand, 0x0000110, N_INV, 0x0800030), \
14260 X(vbic, 0x0100110, N_INV, 0x0800030), \
14261 X(veor, 0x1000110, N_INV, N_INV), \
14262 X(vorn, 0x0300110, N_INV, 0x0800010), \
14263 X(vorr, 0x0200110, N_INV, 0x0800010), \
14264 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14265 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14266 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14267 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14268 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14269 X(vst1, 0x0000000, 0x0800000, N_INV), \
14270 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14271 X(vst2, 0x0000100, 0x0800100, N_INV), \
14272 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14273 X(vst3, 0x0000200, 0x0800200, N_INV), \
14274 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14275 X(vst4, 0x0000300, 0x0800300, N_INV), \
14276 X(vmovn, 0x1b20200, N_INV, N_INV), \
14277 X(vtrn, 0x1b20080, N_INV, N_INV), \
14278 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14279 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14280 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14281 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14282 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14283 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14284 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14285 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14286 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14287 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14288 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14289 X(vseleq, 0xe000a00, N_INV, N_INV), \
14290 X(vselvs, 0xe100a00, N_INV, N_INV), \
14291 X(vselge, 0xe200a00, N_INV, N_INV), \
14292 X(vselgt, 0xe300a00, N_INV, N_INV), \
14293 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14294 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14295 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14296 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14297 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14298 X(aes, 0x3b00300, N_INV, N_INV), \
14299 X(sha3op, 0x2000c00, N_INV, N_INV), \
14300 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14301 X(sha2op, 0x3ba0380, N_INV, N_INV)
14305 #define X(OPC,I,F,S) N_MNEM_##OPC
14310 static const struct neon_tab_entry neon_enc_tab
[] =
14312 #define X(OPC,I,F,S) { (I), (F), (S) }
14317 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14318 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14319 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14320 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14321 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14322 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14323 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14324 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14325 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14326 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14327 #define NEON_ENC_SINGLE_(X) \
14328 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14329 #define NEON_ENC_DOUBLE_(X) \
14330 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14331 #define NEON_ENC_FPV8_(X) \
14332 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14334 #define NEON_ENCODE(type, inst) \
14337 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14338 inst.is_neon = 1; \
14342 #define check_neon_suffixes \
14345 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14347 as_bad (_("invalid neon suffix for non neon instruction")); \
14353 /* Define shapes for instruction operands. The following mnemonic characters
14354 are used in this table:
14356 F - VFP S<n> register
14357 D - Neon D<n> register
14358 Q - Neon Q<n> register
14362 L - D<n> register list
14364 This table is used to generate various data:
14365 - enumerations of the form NS_DDR to be used as arguments to
14367 - a table classifying shapes into single, double, quad, mixed.
14368 - a table used to drive neon_select_shape. */
14370 #define NEON_SHAPE_DEF \
14371 X(4, (R, R, Q, Q), QUAD), \
14372 X(4, (Q, R, R, I), QUAD), \
14373 X(4, (R, R, S, S), QUAD), \
14374 X(4, (S, S, R, R), QUAD), \
14375 X(3, (Q, R, I), QUAD), \
14376 X(3, (I, Q, Q), QUAD), \
14377 X(3, (I, Q, R), QUAD), \
14378 X(3, (R, Q, Q), QUAD), \
14379 X(3, (D, D, D), DOUBLE), \
14380 X(3, (Q, Q, Q), QUAD), \
14381 X(3, (D, D, I), DOUBLE), \
14382 X(3, (Q, Q, I), QUAD), \
14383 X(3, (D, D, S), DOUBLE), \
14384 X(3, (Q, Q, S), QUAD), \
14385 X(3, (Q, Q, R), QUAD), \
14386 X(3, (R, R, Q), QUAD), \
14387 X(2, (R, Q), QUAD), \
14388 X(2, (D, D), DOUBLE), \
14389 X(2, (Q, Q), QUAD), \
14390 X(2, (D, S), DOUBLE), \
14391 X(2, (Q, S), QUAD), \
14392 X(2, (D, R), DOUBLE), \
14393 X(2, (Q, R), QUAD), \
14394 X(2, (D, I), DOUBLE), \
14395 X(2, (Q, I), QUAD), \
14396 X(3, (D, L, D), DOUBLE), \
14397 X(2, (D, Q), MIXED), \
14398 X(2, (Q, D), MIXED), \
14399 X(3, (D, Q, I), MIXED), \
14400 X(3, (Q, D, I), MIXED), \
14401 X(3, (Q, D, D), MIXED), \
14402 X(3, (D, Q, Q), MIXED), \
14403 X(3, (Q, Q, D), MIXED), \
14404 X(3, (Q, D, S), MIXED), \
14405 X(3, (D, Q, S), MIXED), \
14406 X(4, (D, D, D, I), DOUBLE), \
14407 X(4, (Q, Q, Q, I), QUAD), \
14408 X(4, (D, D, S, I), DOUBLE), \
14409 X(4, (Q, Q, S, I), QUAD), \
14410 X(2, (F, F), SINGLE), \
14411 X(3, (F, F, F), SINGLE), \
14412 X(2, (F, I), SINGLE), \
14413 X(2, (F, D), MIXED), \
14414 X(2, (D, F), MIXED), \
14415 X(3, (F, F, I), MIXED), \
14416 X(4, (R, R, F, F), SINGLE), \
14417 X(4, (F, F, R, R), SINGLE), \
14418 X(3, (D, R, R), DOUBLE), \
14419 X(3, (R, R, D), DOUBLE), \
14420 X(2, (S, R), SINGLE), \
14421 X(2, (R, S), SINGLE), \
14422 X(2, (F, R), SINGLE), \
14423 X(2, (R, F), SINGLE), \
14424 /* Used for MVE tail predicated loop instructions. */\
14425 X(2, (R, R), QUAD), \
14426 /* Half float shape supported so far. */\
14427 X (2, (H, D), MIXED), \
14428 X (2, (D, H), MIXED), \
14429 X (2, (H, F), MIXED), \
14430 X (2, (F, H), MIXED), \
14431 X (2, (H, H), HALF), \
14432 X (2, (H, R), HALF), \
14433 X (2, (R, H), HALF), \
14434 X (2, (H, I), HALF), \
14435 X (3, (H, H, H), HALF), \
14436 X (3, (H, F, I), MIXED), \
14437 X (3, (F, H, I), MIXED), \
14438 X (3, (D, H, H), MIXED), \
14439 X (3, (D, H, S), MIXED)
14441 #define S2(A,B) NS_##A##B
14442 #define S3(A,B,C) NS_##A##B##C
14443 #define S4(A,B,C,D) NS_##A##B##C##D
14445 #define X(N, L, C) S##N L
14458 enum neon_shape_class
14467 #define X(N, L, C) SC_##C
14469 static enum neon_shape_class neon_shape_class
[] =
14488 /* Register widths of above. */
14489 static unsigned neon_shape_el_size
[] =
14501 struct neon_shape_info
14504 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14507 #define S2(A,B) { SE_##A, SE_##B }
14508 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14509 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14511 #define X(N, L, C) { N, S##N L }
14513 static struct neon_shape_info neon_shape_tab
[] =
14523 /* Bit masks used in type checking given instructions.
14524 'N_EQK' means the type must be the same as (or based on in some way) the key
14525 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14526 set, various other bits can be set as well in order to modify the meaning of
14527 the type constraint. */
14529 enum neon_type_mask
14553 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14554 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14555 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14556 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14557 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14558 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14559 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14560 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14561 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14562 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14563 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14565 N_MAX_NONSPECIAL
= N_P64
14568 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14570 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14571 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14572 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14573 #define N_S_32 (N_S8 | N_S16 | N_S32)
14574 #define N_F_16_32 (N_F16 | N_F32)
14575 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14576 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14577 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14578 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14579 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14580 #define N_F_MVE (N_F16 | N_F32)
14581 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14583 /* Pass this as the first type argument to neon_check_type to ignore types
14585 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14587 /* Select a "shape" for the current instruction (describing register types or
14588 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14589 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14590 function of operand parsing, so this function doesn't need to be called.
14591 Shapes should be listed in order of decreasing length. */
14593 static enum neon_shape
14594 neon_select_shape (enum neon_shape shape
, ...)
14597 enum neon_shape first_shape
= shape
;
14599 /* Fix missing optional operands. FIXME: we don't know at this point how
14600 many arguments we should have, so this makes the assumption that we have
14601 > 1. This is true of all current Neon opcodes, I think, but may not be
14602 true in the future. */
14603 if (!inst
.operands
[1].present
)
14604 inst
.operands
[1] = inst
.operands
[0];
14606 va_start (ap
, shape
);
14608 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14613 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14615 if (!inst
.operands
[j
].present
)
14621 switch (neon_shape_tab
[shape
].el
[j
])
14623 /* If a .f16, .16, .u16, .s16 type specifier is given over
14624 a VFP single precision register operand, it's essentially
14625 means only half of the register is used.
14627 If the type specifier is given after the mnemonics, the
14628 information is stored in inst.vectype. If the type specifier
14629 is given after register operand, the information is stored
14630 in inst.operands[].vectype.
14632 When there is only one type specifier, and all the register
14633 operands are the same type of hardware register, the type
14634 specifier applies to all register operands.
14636 If no type specifier is given, the shape is inferred from
14637 operand information.
14640 vadd.f16 s0, s1, s2: NS_HHH
14641 vabs.f16 s0, s1: NS_HH
14642 vmov.f16 s0, r1: NS_HR
14643 vmov.f16 r0, s1: NS_RH
14644 vcvt.f16 r0, s1: NS_RH
14645 vcvt.f16.s32 s2, s2, #29: NS_HFI
14646 vcvt.f16.s32 s2, s2: NS_HF
14649 if (!(inst
.operands
[j
].isreg
14650 && inst
.operands
[j
].isvec
14651 && inst
.operands
[j
].issingle
14652 && !inst
.operands
[j
].isquad
14653 && ((inst
.vectype
.elems
== 1
14654 && inst
.vectype
.el
[0].size
== 16)
14655 || (inst
.vectype
.elems
> 1
14656 && inst
.vectype
.el
[j
].size
== 16)
14657 || (inst
.vectype
.elems
== 0
14658 && inst
.operands
[j
].vectype
.type
!= NT_invtype
14659 && inst
.operands
[j
].vectype
.size
== 16))))
14664 if (!(inst
.operands
[j
].isreg
14665 && inst
.operands
[j
].isvec
14666 && inst
.operands
[j
].issingle
14667 && !inst
.operands
[j
].isquad
14668 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
14669 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
14670 || (inst
.vectype
.elems
== 0
14671 && (inst
.operands
[j
].vectype
.size
== 32
14672 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
14677 if (!(inst
.operands
[j
].isreg
14678 && inst
.operands
[j
].isvec
14679 && !inst
.operands
[j
].isquad
14680 && !inst
.operands
[j
].issingle
))
14685 if (!(inst
.operands
[j
].isreg
14686 && !inst
.operands
[j
].isvec
))
14691 if (!(inst
.operands
[j
].isreg
14692 && inst
.operands
[j
].isvec
14693 && inst
.operands
[j
].isquad
14694 && !inst
.operands
[j
].issingle
))
14699 if (!(!inst
.operands
[j
].isreg
14700 && !inst
.operands
[j
].isscalar
))
14705 if (!(!inst
.operands
[j
].isreg
14706 && inst
.operands
[j
].isscalar
))
14716 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
14717 /* We've matched all the entries in the shape table, and we don't
14718 have any left over operands which have not been matched. */
14724 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
14725 first_error (_("invalid instruction shape"));
14730 /* True if SHAPE is predominantly a quadword operation (most of the time, this
14731 means the Q bit should be set). */
14734 neon_quad (enum neon_shape shape
)
14736 return neon_shape_class
[shape
] == SC_QUAD
;
14740 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
14743 /* Allow modification to be made to types which are constrained to be
14744 based on the key element, based on bits set alongside N_EQK. */
14745 if ((typebits
& N_EQK
) != 0)
14747 if ((typebits
& N_HLF
) != 0)
14749 else if ((typebits
& N_DBL
) != 0)
14751 if ((typebits
& N_SGN
) != 0)
14752 *g_type
= NT_signed
;
14753 else if ((typebits
& N_UNS
) != 0)
14754 *g_type
= NT_unsigned
;
14755 else if ((typebits
& N_INT
) != 0)
14756 *g_type
= NT_integer
;
14757 else if ((typebits
& N_FLT
) != 0)
14758 *g_type
= NT_float
;
14759 else if ((typebits
& N_SIZ
) != 0)
14760 *g_type
= NT_untyped
;
14764 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
14765 operand type, i.e. the single type specified in a Neon instruction when it
14766 is the only one given. */
14768 static struct neon_type_el
14769 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
14771 struct neon_type_el dest
= *key
;
14773 gas_assert ((thisarg
& N_EQK
) != 0);
14775 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
14780 /* Convert Neon type and size into compact bitmask representation. */
14782 static enum neon_type_mask
14783 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
14790 case 8: return N_8
;
14791 case 16: return N_16
;
14792 case 32: return N_32
;
14793 case 64: return N_64
;
14801 case 8: return N_I8
;
14802 case 16: return N_I16
;
14803 case 32: return N_I32
;
14804 case 64: return N_I64
;
14812 case 16: return N_F16
;
14813 case 32: return N_F32
;
14814 case 64: return N_F64
;
14822 case 8: return N_P8
;
14823 case 16: return N_P16
;
14824 case 64: return N_P64
;
14832 case 8: return N_S8
;
14833 case 16: return N_S16
;
14834 case 32: return N_S32
;
14835 case 64: return N_S64
;
14843 case 8: return N_U8
;
14844 case 16: return N_U16
;
14845 case 32: return N_U32
;
14846 case 64: return N_U64
;
14857 /* Convert compact Neon bitmask type representation to a type and size. Only
14858 handles the case where a single bit is set in the mask. */
14861 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
14862 enum neon_type_mask mask
)
14864 if ((mask
& N_EQK
) != 0)
14867 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
14869 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
14871 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
14873 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
14878 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
14880 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
14881 *type
= NT_unsigned
;
14882 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
14883 *type
= NT_integer
;
14884 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
14885 *type
= NT_untyped
;
14886 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
14888 else if ((mask
& (N_F_ALL
)) != 0)
14896 /* Modify a bitmask of allowed types. This is only needed for type
14900 modify_types_allowed (unsigned allowed
, unsigned mods
)
14903 enum neon_el_type type
;
14909 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
14911 if (el_type_of_type_chk (&type
, &size
,
14912 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
14914 neon_modify_type_size (mods
, &type
, &size
);
14915 destmask
|= type_chk_of_el_type (type
, size
);
14922 /* Check type and return type classification.
14923 The manual states (paraphrase): If one datatype is given, it indicates the
14925 - the second operand, if there is one
14926 - the operand, if there is no second operand
14927 - the result, if there are no operands.
14928 This isn't quite good enough though, so we use a concept of a "key" datatype
14929 which is set on a per-instruction basis, which is the one which matters when
14930 only one data type is written.
14931 Note: this function has side-effects (e.g. filling in missing operands). All
14932 Neon instructions should call it before performing bit encoding. */
14934 static struct neon_type_el
14935 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
14938 unsigned i
, pass
, key_el
= 0;
14939 unsigned types
[NEON_MAX_TYPE_ELS
];
14940 enum neon_el_type k_type
= NT_invtype
;
14941 unsigned k_size
= -1u;
14942 struct neon_type_el badtype
= {NT_invtype
, -1};
14943 unsigned key_allowed
= 0;
14945 /* Optional registers in Neon instructions are always (not) in operand 1.
14946 Fill in the missing operand here, if it was omitted. */
14947 if (els
> 1 && !inst
.operands
[1].present
)
14948 inst
.operands
[1] = inst
.operands
[0];
14950 /* Suck up all the varargs. */
14952 for (i
= 0; i
< els
; i
++)
14954 unsigned thisarg
= va_arg (ap
, unsigned);
14955 if (thisarg
== N_IGNORE_TYPE
)
14960 types
[i
] = thisarg
;
14961 if ((thisarg
& N_KEY
) != 0)
14966 if (inst
.vectype
.elems
> 0)
14967 for (i
= 0; i
< els
; i
++)
14968 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
14970 first_error (_("types specified in both the mnemonic and operands"));
14974 /* Duplicate inst.vectype elements here as necessary.
14975 FIXME: No idea if this is exactly the same as the ARM assembler,
14976 particularly when an insn takes one register and one non-register
14978 if (inst
.vectype
.elems
== 1 && els
> 1)
14981 inst
.vectype
.elems
= els
;
14982 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
14983 for (j
= 0; j
< els
; j
++)
14985 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14988 else if (inst
.vectype
.elems
== 0 && els
> 0)
14991 /* No types were given after the mnemonic, so look for types specified
14992 after each operand. We allow some flexibility here; as long as the
14993 "key" operand has a type, we can infer the others. */
14994 for (j
= 0; j
< els
; j
++)
14995 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
14996 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
14998 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
15000 for (j
= 0; j
< els
; j
++)
15001 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
15002 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15007 first_error (_("operand types can't be inferred"));
15011 else if (inst
.vectype
.elems
!= els
)
15013 first_error (_("type specifier has the wrong number of parts"));
15017 for (pass
= 0; pass
< 2; pass
++)
15019 for (i
= 0; i
< els
; i
++)
15021 unsigned thisarg
= types
[i
];
15022 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15023 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15024 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15025 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15027 /* Decay more-specific signed & unsigned types to sign-insensitive
15028 integer types if sign-specific variants are unavailable. */
15029 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15030 && (types_allowed
& N_SU_ALL
) == 0)
15031 g_type
= NT_integer
;
15033 /* If only untyped args are allowed, decay any more specific types to
15034 them. Some instructions only care about signs for some element
15035 sizes, so handle that properly. */
15036 if (((types_allowed
& N_UNT
) == 0)
15037 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15038 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15039 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15040 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15041 g_type
= NT_untyped
;
15045 if ((thisarg
& N_KEY
) != 0)
15049 key_allowed
= thisarg
& ~N_KEY
;
15051 /* Check architecture constraint on FP16 extension. */
15053 && k_type
== NT_float
15054 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15056 inst
.error
= _(BAD_FP16
);
15063 if ((thisarg
& N_VFP
) != 0)
15065 enum neon_shape_el regshape
;
15066 unsigned regwidth
, match
;
15068 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15071 first_error (_("invalid instruction shape"));
15074 regshape
= neon_shape_tab
[ns
].el
[i
];
15075 regwidth
= neon_shape_el_size
[regshape
];
15077 /* In VFP mode, operands must match register widths. If we
15078 have a key operand, use its width, else use the width of
15079 the current operand. */
15085 /* FP16 will use a single precision register. */
15086 if (regwidth
== 32 && match
== 16)
15088 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15092 inst
.error
= _(BAD_FP16
);
15097 if (regwidth
!= match
)
15099 first_error (_("operand size must match register width"));
15104 if ((thisarg
& N_EQK
) == 0)
15106 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15108 if ((given_type
& types_allowed
) == 0)
15110 first_error (BAD_SIMD_TYPE
);
15116 enum neon_el_type mod_k_type
= k_type
;
15117 unsigned mod_k_size
= k_size
;
15118 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15119 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15121 first_error (_("inconsistent types in Neon instruction"));
15129 return inst
.vectype
.el
[key_el
];
15132 /* Neon-style VFP instruction forwarding. */
15134 /* Thumb VFP instructions have 0xE in the condition field. */
15137 do_vfp_cond_or_thumb (void)
15142 inst
.instruction
|= 0xe0000000;
15144 inst
.instruction
|= inst
.cond
<< 28;
15147 /* Look up and encode a simple mnemonic, for use as a helper function for the
15148 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15149 etc. It is assumed that operand parsing has already been done, and that the
15150 operands are in the form expected by the given opcode (this isn't necessarily
15151 the same as the form in which they were parsed, hence some massaging must
15152 take place before this function is called).
15153 Checks current arch version against that in the looked-up opcode. */
15156 do_vfp_nsyn_opcode (const char *opname
)
15158 const struct asm_opcode
*opcode
;
15160 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15165 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15166 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15173 inst
.instruction
= opcode
->tvalue
;
15174 opcode
->tencode ();
15178 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15179 opcode
->aencode ();
15184 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15186 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15188 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15191 do_vfp_nsyn_opcode ("fadds");
15193 do_vfp_nsyn_opcode ("fsubs");
15195 /* ARMv8.2 fp16 instruction. */
15197 do_scalar_fp16_v82_encode ();
15202 do_vfp_nsyn_opcode ("faddd");
15204 do_vfp_nsyn_opcode ("fsubd");
15208 /* Check operand types to see if this is a VFP instruction, and if so call
15212 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15214 enum neon_shape rs
;
15215 struct neon_type_el et
;
15220 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15221 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15225 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15226 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15227 N_F_ALL
| N_KEY
| N_VFP
);
15234 if (et
.type
!= NT_invtype
)
15245 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15247 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15249 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15252 do_vfp_nsyn_opcode ("fmacs");
15254 do_vfp_nsyn_opcode ("fnmacs");
15256 /* ARMv8.2 fp16 instruction. */
15258 do_scalar_fp16_v82_encode ();
15263 do_vfp_nsyn_opcode ("fmacd");
15265 do_vfp_nsyn_opcode ("fnmacd");
15270 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15272 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15274 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15277 do_vfp_nsyn_opcode ("ffmas");
15279 do_vfp_nsyn_opcode ("ffnmas");
15281 /* ARMv8.2 fp16 instruction. */
15283 do_scalar_fp16_v82_encode ();
15288 do_vfp_nsyn_opcode ("ffmad");
15290 do_vfp_nsyn_opcode ("ffnmad");
15295 do_vfp_nsyn_mul (enum neon_shape rs
)
15297 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15299 do_vfp_nsyn_opcode ("fmuls");
15301 /* ARMv8.2 fp16 instruction. */
15303 do_scalar_fp16_v82_encode ();
15306 do_vfp_nsyn_opcode ("fmuld");
15310 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15312 int is_neg
= (inst
.instruction
& 0x80) != 0;
15313 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15315 if (rs
== NS_FF
|| rs
== NS_HH
)
15318 do_vfp_nsyn_opcode ("fnegs");
15320 do_vfp_nsyn_opcode ("fabss");
15322 /* ARMv8.2 fp16 instruction. */
15324 do_scalar_fp16_v82_encode ();
15329 do_vfp_nsyn_opcode ("fnegd");
15331 do_vfp_nsyn_opcode ("fabsd");
15335 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15336 insns belong to Neon, and are handled elsewhere. */
15339 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15341 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15345 do_vfp_nsyn_opcode ("fldmdbs");
15347 do_vfp_nsyn_opcode ("fldmias");
15352 do_vfp_nsyn_opcode ("fstmdbs");
15354 do_vfp_nsyn_opcode ("fstmias");
15359 do_vfp_nsyn_sqrt (void)
15361 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15362 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15364 if (rs
== NS_FF
|| rs
== NS_HH
)
15366 do_vfp_nsyn_opcode ("fsqrts");
15368 /* ARMv8.2 fp16 instruction. */
15370 do_scalar_fp16_v82_encode ();
15373 do_vfp_nsyn_opcode ("fsqrtd");
15377 do_vfp_nsyn_div (void)
15379 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15380 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15381 N_F_ALL
| N_KEY
| N_VFP
);
15383 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15385 do_vfp_nsyn_opcode ("fdivs");
15387 /* ARMv8.2 fp16 instruction. */
15389 do_scalar_fp16_v82_encode ();
15392 do_vfp_nsyn_opcode ("fdivd");
15396 do_vfp_nsyn_nmul (void)
15398 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15399 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15400 N_F_ALL
| N_KEY
| N_VFP
);
15402 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15404 NEON_ENCODE (SINGLE
, inst
);
15405 do_vfp_sp_dyadic ();
15407 /* ARMv8.2 fp16 instruction. */
15409 do_scalar_fp16_v82_encode ();
15413 NEON_ENCODE (DOUBLE
, inst
);
15414 do_vfp_dp_rd_rn_rm ();
15416 do_vfp_cond_or_thumb ();
15420 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15424 neon_logbits (unsigned x
)
15426 return ffs (x
) - 4;
15429 #define LOW4(R) ((R) & 0xf)
15430 #define HI1(R) (((R) >> 4) & 1)
15433 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15438 first_error (BAD_EL_TYPE
);
15441 switch (inst
.operands
[0].imm
)
15444 first_error (_("invalid condition"));
15466 /* only accept eq and ne. */
15467 if (inst
.operands
[0].imm
> 1)
15469 first_error (_("invalid condition"));
15472 return inst
.operands
[0].imm
;
15474 if (inst
.operands
[0].imm
== 0x2)
15476 else if (inst
.operands
[0].imm
== 0x8)
15480 first_error (_("invalid condition"));
15484 switch (inst
.operands
[0].imm
)
15487 first_error (_("invalid condition"));
15503 /* Should be unreachable. */
15510 /* We are dealing with a vector predicated block. */
15511 if (inst
.operands
[0].present
)
15513 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15514 struct neon_type_el et
15515 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15518 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15520 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15522 if (et
.type
== NT_invtype
)
15525 if (et
.type
== NT_float
)
15527 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15529 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
15530 inst
.instruction
|= (et
.size
== 16) << 28;
15531 inst
.instruction
|= 0x3 << 20;
15535 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
15537 inst
.instruction
|= 1 << 28;
15538 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15541 if (inst
.operands
[2].isquad
)
15543 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15544 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15545 inst
.instruction
|= (fcond
& 0x2) >> 1;
15549 if (inst
.operands
[2].reg
== REG_SP
)
15550 as_tsktsk (MVE_BAD_SP
);
15551 inst
.instruction
|= 1 << 6;
15552 inst
.instruction
|= (fcond
& 0x2) << 4;
15553 inst
.instruction
|= inst
.operands
[2].reg
;
15555 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15556 inst
.instruction
|= (fcond
& 0x4) << 10;
15557 inst
.instruction
|= (fcond
& 0x1) << 7;
15560 set_pred_insn_type (VPT_INSN
);
15562 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
15563 | ((inst
.instruction
& 0xe000) >> 13);
15564 now_pred
.warn_deprecated
= FALSE
;
15565 now_pred
.type
= VECTOR_PRED
;
15572 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
15573 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
15574 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
15575 if (!inst
.operands
[2].present
)
15576 first_error (_("MVE vector or ARM register expected"));
15577 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15579 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15580 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
15581 && inst
.operands
[1].isquad
)
15583 inst
.instruction
= N_MNEM_vcmp
;
15587 if (inst
.cond
> COND_ALWAYS
)
15588 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15590 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15592 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15593 struct neon_type_el et
15594 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15597 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
15598 && !inst
.operands
[2].iszr
, BAD_PC
);
15600 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15602 inst
.instruction
= 0xee010f00;
15603 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15604 inst
.instruction
|= (fcond
& 0x4) << 10;
15605 inst
.instruction
|= (fcond
& 0x1) << 7;
15606 if (et
.type
== NT_float
)
15608 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15610 inst
.instruction
|= (et
.size
== 16) << 28;
15611 inst
.instruction
|= 0x3 << 20;
15615 inst
.instruction
|= 1 << 28;
15616 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15618 if (inst
.operands
[2].isquad
)
15620 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15621 inst
.instruction
|= (fcond
& 0x2) >> 1;
15622 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15626 if (inst
.operands
[2].reg
== REG_SP
)
15627 as_tsktsk (MVE_BAD_SP
);
15628 inst
.instruction
|= 1 << 6;
15629 inst
.instruction
|= (fcond
& 0x2) << 4;
15630 inst
.instruction
|= inst
.operands
[2].reg
;
15638 do_mve_vmaxa_vmina (void)
15640 if (inst
.cond
> COND_ALWAYS
)
15641 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15643 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15645 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
15646 struct neon_type_el et
15647 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
15649 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15650 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15651 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15652 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15653 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15658 do_mve_vfmas (void)
15660 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
15661 struct neon_type_el et
15662 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
15664 if (inst
.cond
> COND_ALWAYS
)
15665 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15667 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15669 if (inst
.operands
[2].reg
== REG_SP
)
15670 as_tsktsk (MVE_BAD_SP
);
15671 else if (inst
.operands
[2].reg
== REG_PC
)
15672 as_tsktsk (MVE_BAD_PC
);
15674 inst
.instruction
|= (et
.size
== 16) << 28;
15675 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15676 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15677 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15678 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15679 inst
.instruction
|= inst
.operands
[2].reg
;
15684 do_mve_viddup (void)
15686 if (inst
.cond
> COND_ALWAYS
)
15687 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15689 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15691 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
15692 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
15693 _("immediate must be either 1, 2, 4 or 8"));
15695 enum neon_shape rs
;
15696 struct neon_type_el et
;
15698 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
15700 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
15701 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
15706 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
15707 if (inst
.operands
[2].reg
== REG_SP
)
15708 as_tsktsk (MVE_BAD_SP
);
15709 else if (inst
.operands
[2].reg
== REG_PC
)
15710 first_error (BAD_PC
);
15712 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
15713 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
15714 Rm
= inst
.operands
[2].reg
>> 1;
15716 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15717 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15718 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15719 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15720 inst
.instruction
|= (imm
> 2) << 7;
15721 inst
.instruction
|= Rm
<< 1;
15722 inst
.instruction
|= (imm
== 2 || imm
== 8);
15727 do_mve_vmlas (void)
15729 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
15730 struct neon_type_el et
15731 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
15733 if (inst
.operands
[2].reg
== REG_PC
)
15734 as_tsktsk (MVE_BAD_PC
);
15735 else if (inst
.operands
[2].reg
== REG_SP
)
15736 as_tsktsk (MVE_BAD_SP
);
15738 if (inst
.cond
> COND_ALWAYS
)
15739 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15741 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15743 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15744 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15745 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15746 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15747 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15748 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15749 inst
.instruction
|= inst
.operands
[2].reg
;
15754 do_mve_vshll (void)
15756 struct neon_type_el et
15757 = neon_check_type (2, NS_QQI
, N_EQK
, N_S8
| N_U8
| N_S16
| N_U16
| N_KEY
);
15759 if (inst
.cond
> COND_ALWAYS
)
15760 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15762 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15764 int imm
= inst
.operands
[2].imm
;
15765 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15766 _("immediate value out of range"));
15768 if ((unsigned)imm
== et
.size
)
15770 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15771 inst
.instruction
|= 0x110001;
15775 inst
.instruction
|= (et
.size
+ imm
) << 16;
15776 inst
.instruction
|= 0x800140;
15779 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15780 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15781 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15782 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15783 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15788 do_mve_vshlc (void)
15790 if (inst
.cond
> COND_ALWAYS
)
15791 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15793 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15795 if (inst
.operands
[1].reg
== REG_PC
)
15796 as_tsktsk (MVE_BAD_PC
);
15797 else if (inst
.operands
[1].reg
== REG_SP
)
15798 as_tsktsk (MVE_BAD_SP
);
15800 int imm
= inst
.operands
[2].imm
;
15801 constraint (imm
< 1 || imm
> 32, _("immediate value out of range"));
15803 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15804 inst
.instruction
|= (imm
& 0x1f) << 16;
15805 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15806 inst
.instruction
|= inst
.operands
[1].reg
;
15811 do_mve_vshrn (void)
15814 switch (inst
.instruction
)
15816 case M_MNEM_vshrnt
:
15817 case M_MNEM_vshrnb
:
15818 case M_MNEM_vrshrnt
:
15819 case M_MNEM_vrshrnb
:
15820 types
= N_I16
| N_I32
;
15822 case M_MNEM_vqshrnt
:
15823 case M_MNEM_vqshrnb
:
15824 case M_MNEM_vqrshrnt
:
15825 case M_MNEM_vqrshrnb
:
15826 types
= N_U16
| N_U32
| N_S16
| N_S32
;
15828 case M_MNEM_vqshrunt
:
15829 case M_MNEM_vqshrunb
:
15830 case M_MNEM_vqrshrunt
:
15831 case M_MNEM_vqrshrunb
:
15832 types
= N_S16
| N_S32
;
15838 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
15840 if (inst
.cond
> COND_ALWAYS
)
15841 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15843 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15845 unsigned Qd
= inst
.operands
[0].reg
;
15846 unsigned Qm
= inst
.operands
[1].reg
;
15847 unsigned imm
= inst
.operands
[2].imm
;
15848 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
15850 ? _("immediate operand expected in the range [1,8]")
15851 : _("immediate operand expected in the range [1,16]"));
15853 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15854 inst
.instruction
|= HI1 (Qd
) << 22;
15855 inst
.instruction
|= (et
.size
- imm
) << 16;
15856 inst
.instruction
|= LOW4 (Qd
) << 12;
15857 inst
.instruction
|= HI1 (Qm
) << 5;
15858 inst
.instruction
|= LOW4 (Qm
);
15863 do_mve_vqmovn (void)
15865 struct neon_type_el et
;
15866 if (inst
.instruction
== M_MNEM_vqmovnt
15867 || inst
.instruction
== M_MNEM_vqmovnb
)
15868 et
= neon_check_type (2, NS_QQ
, N_EQK
,
15869 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
15871 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15873 if (inst
.cond
> COND_ALWAYS
)
15874 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15876 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15878 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15879 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15880 inst
.instruction
|= (et
.size
== 32) << 18;
15881 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15882 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15883 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15888 do_mve_vpsel (void)
15890 neon_select_shape (NS_QQQ
, NS_NULL
);
15892 if (inst
.cond
> COND_ALWAYS
)
15893 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15895 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15897 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15898 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15899 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15900 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15901 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15902 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15907 do_mve_vpnot (void)
15909 if (inst
.cond
> COND_ALWAYS
)
15910 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15912 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15916 do_mve_vmaxnma_vminnma (void)
15918 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
15919 struct neon_type_el et
15920 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
15922 if (inst
.cond
> COND_ALWAYS
)
15923 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15925 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15927 inst
.instruction
|= (et
.size
== 16) << 28;
15928 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15929 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15930 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15931 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15936 do_mve_vcmul (void)
15938 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
15939 struct neon_type_el et
15940 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
15942 if (inst
.cond
> COND_ALWAYS
)
15943 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15945 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15947 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
15948 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
15949 _("immediate out of range"));
15951 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
15952 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
15953 as_tsktsk (BAD_MVE_SRCDEST
);
15955 inst
.instruction
|= (et
.size
== 32) << 28;
15956 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15957 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15958 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15959 inst
.instruction
|= (rot
> 90) << 12;
15960 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15961 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15962 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15963 inst
.instruction
|= (rot
== 90 || rot
== 270);
15967 /* To handle the Low Overhead Loop instructions
15968 in Armv8.1-M Mainline and MVE. */
15972 unsigned long insn
= inst
.instruction
;
15974 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
15976 if (insn
== T_MNEM_lctp
)
15979 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN
);
15981 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
15983 struct neon_type_el et
15984 = neon_check_type (2, NS_RR
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15985 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15992 constraint (!inst
.operands
[0].present
,
15994 /* fall through. */
15997 if (!inst
.operands
[0].present
)
15998 inst
.instruction
|= 1 << 21;
16000 v8_1_loop_reloc (TRUE
);
16005 v8_1_loop_reloc (FALSE
);
16006 /* fall through. */
16009 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
16011 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16012 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16013 else if (inst
.operands
[1].reg
== REG_PC
)
16014 as_tsktsk (MVE_BAD_PC
);
16015 if (inst
.operands
[1].reg
== REG_SP
)
16016 as_tsktsk (MVE_BAD_SP
);
16018 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
16028 do_vfp_nsyn_cmp (void)
16030 enum neon_shape rs
;
16031 if (!inst
.operands
[0].isreg
)
16038 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
16039 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
16043 if (inst
.operands
[1].isreg
)
16045 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
16046 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
16048 if (rs
== NS_FF
|| rs
== NS_HH
)
16050 NEON_ENCODE (SINGLE
, inst
);
16051 do_vfp_sp_monadic ();
16055 NEON_ENCODE (DOUBLE
, inst
);
16056 do_vfp_dp_rd_rm ();
16061 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
16062 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
16064 switch (inst
.instruction
& 0x0fffffff)
16067 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
16070 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
16076 if (rs
== NS_FI
|| rs
== NS_HI
)
16078 NEON_ENCODE (SINGLE
, inst
);
16079 do_vfp_sp_compare_z ();
16083 NEON_ENCODE (DOUBLE
, inst
);
16087 do_vfp_cond_or_thumb ();
16089 /* ARMv8.2 fp16 instruction. */
16090 if (rs
== NS_HI
|| rs
== NS_HH
)
16091 do_scalar_fp16_v82_encode ();
16095 nsyn_insert_sp (void)
16097 inst
.operands
[1] = inst
.operands
[0];
16098 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
16099 inst
.operands
[0].reg
= REG_SP
;
16100 inst
.operands
[0].isreg
= 1;
16101 inst
.operands
[0].writeback
= 1;
16102 inst
.operands
[0].present
= 1;
16106 do_vfp_nsyn_push (void)
16110 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16111 _("register list must contain at least 1 and at most 16 "
16114 if (inst
.operands
[1].issingle
)
16115 do_vfp_nsyn_opcode ("fstmdbs");
16117 do_vfp_nsyn_opcode ("fstmdbd");
16121 do_vfp_nsyn_pop (void)
16125 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16126 _("register list must contain at least 1 and at most 16 "
16129 if (inst
.operands
[1].issingle
)
16130 do_vfp_nsyn_opcode ("fldmias");
16132 do_vfp_nsyn_opcode ("fldmiad");
16135 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16136 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16139 neon_dp_fixup (struct arm_it
* insn
)
16141 unsigned int i
= insn
->instruction
;
16146 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16157 insn
->instruction
= i
;
16161 mve_encode_qqr (int size
, int U
, int fp
)
16163 if (inst
.operands
[2].reg
== REG_SP
)
16164 as_tsktsk (MVE_BAD_SP
);
16165 else if (inst
.operands
[2].reg
== REG_PC
)
16166 as_tsktsk (MVE_BAD_PC
);
16171 if (((unsigned)inst
.instruction
) == 0xd00)
16172 inst
.instruction
= 0xee300f40;
16174 else if (((unsigned)inst
.instruction
) == 0x200d00)
16175 inst
.instruction
= 0xee301f40;
16177 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16178 inst
.instruction
= 0xee310e60;
16180 /* Setting size which is 1 for F16 and 0 for F32. */
16181 inst
.instruction
|= (size
== 16) << 28;
16186 if (((unsigned)inst
.instruction
) == 0x800)
16187 inst
.instruction
= 0xee010f40;
16189 else if (((unsigned)inst
.instruction
) == 0x1000800)
16190 inst
.instruction
= 0xee011f40;
16192 else if (((unsigned)inst
.instruction
) == 0)
16193 inst
.instruction
= 0xee000f40;
16195 else if (((unsigned)inst
.instruction
) == 0x200)
16196 inst
.instruction
= 0xee001f40;
16198 else if (((unsigned)inst
.instruction
) == 0x900)
16199 inst
.instruction
= 0xee010e40;
16201 else if (((unsigned)inst
.instruction
) == 0x910)
16202 inst
.instruction
= 0xee011e60;
16204 else if (((unsigned)inst
.instruction
) == 0x10)
16205 inst
.instruction
= 0xee000f60;
16207 else if (((unsigned)inst
.instruction
) == 0x210)
16208 inst
.instruction
= 0xee001f60;
16210 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16211 inst
.instruction
= 0xee000e40;
16213 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16214 inst
.instruction
= 0xee010e60;
16216 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16217 inst
.instruction
= 0xfe010e60;
16220 inst
.instruction
|= U
<< 28;
16222 /* Setting bits for size. */
16223 inst
.instruction
|= neon_logbits (size
) << 20;
16225 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16226 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16227 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16228 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16229 inst
.instruction
|= inst
.operands
[2].reg
;
16234 mve_encode_rqq (unsigned bit28
, unsigned size
)
16236 inst
.instruction
|= bit28
<< 28;
16237 inst
.instruction
|= neon_logbits (size
) << 20;
16238 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16239 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16240 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16241 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16242 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16247 mve_encode_qqq (int ubit
, int size
)
16250 inst
.instruction
|= (ubit
!= 0) << 28;
16251 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16252 inst
.instruction
|= neon_logbits (size
) << 20;
16253 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16254 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16255 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16256 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16257 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16263 mve_encode_rq (unsigned bit28
, unsigned size
)
16265 inst
.instruction
|= bit28
<< 28;
16266 inst
.instruction
|= neon_logbits (size
) << 18;
16267 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16268 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16273 mve_encode_rrqq (unsigned U
, unsigned size
)
16275 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16277 inst
.instruction
|= U
<< 28;
16278 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16279 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16280 inst
.instruction
|= (size
== 32) << 16;
16281 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16282 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16283 inst
.instruction
|= inst
.operands
[3].reg
;
16287 /* Encode insns with bit pattern:
16289 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16290 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16292 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16293 different meaning for some instruction. */
16296 neon_three_same (int isquad
, int ubit
, int size
)
16298 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16299 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16300 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16301 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16302 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16303 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16304 inst
.instruction
|= (isquad
!= 0) << 6;
16305 inst
.instruction
|= (ubit
!= 0) << 24;
16307 inst
.instruction
|= neon_logbits (size
) << 20;
16309 neon_dp_fixup (&inst
);
16312 /* Encode instructions of the form:
16314 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16315 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16317 Don't write size if SIZE == -1. */
16320 neon_two_same (int qbit
, int ubit
, int size
)
16322 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16323 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16324 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16325 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16326 inst
.instruction
|= (qbit
!= 0) << 6;
16327 inst
.instruction
|= (ubit
!= 0) << 24;
16330 inst
.instruction
|= neon_logbits (size
) << 18;
16332 neon_dp_fixup (&inst
);
16335 enum vfp_or_neon_is_neon_bits
16338 NEON_CHECK_ARCH
= 2,
16339 NEON_CHECK_ARCH8
= 4
16342 /* Call this function if an instruction which may have belonged to the VFP or
16343 Neon instruction sets, but turned out to be a Neon instruction (due to the
16344 operand types involved, etc.). We have to check and/or fix-up a couple of
16347 - Make sure the user hasn't attempted to make a Neon instruction
16349 - Alter the value in the condition code field if necessary.
16350 - Make sure that the arch supports Neon instructions.
16352 Which of these operations take place depends on bits from enum
16353 vfp_or_neon_is_neon_bits.
16355 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16356 current instruction's condition is COND_ALWAYS, the condition field is
16357 changed to inst.uncond_value. This is necessary because instructions shared
16358 between VFP and Neon may be conditional for the VFP variants only, and the
16359 unconditional Neon version must have, e.g., 0xF in the condition field. */
16362 vfp_or_neon_is_neon (unsigned check
)
16364 /* Conditions are always legal in Thumb mode (IT blocks). */
16365 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16367 if (inst
.cond
!= COND_ALWAYS
)
16369 first_error (_(BAD_COND
));
16372 if (inst
.uncond_value
!= -1)
16373 inst
.instruction
|= inst
.uncond_value
<< 28;
16377 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16378 || ((check
& NEON_CHECK_ARCH8
)
16379 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16381 first_error (_(BAD_FPU
));
16389 /* Return TRUE if the SIMD instruction is available for the current
16390 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16391 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16392 vfp_or_neon_is_neon for the NEON specific checks. */
16395 check_simd_pred_availability (int fp
, unsigned check
)
16397 if (inst
.cond
> COND_ALWAYS
)
16399 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16401 inst
.error
= BAD_FPU
;
16404 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16406 else if (inst
.cond
< COND_ALWAYS
)
16408 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16409 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16410 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16415 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16416 && vfp_or_neon_is_neon (check
) == FAIL
)
16419 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16420 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16425 /* Neon instruction encoders, in approximate order of appearance. */
16428 do_neon_dyadic_i_su (void)
16430 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16433 enum neon_shape rs
;
16434 struct neon_type_el et
;
16435 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16436 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16438 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16440 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16444 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16446 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16450 do_neon_dyadic_i64_su (void)
16452 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16454 enum neon_shape rs
;
16455 struct neon_type_el et
;
16456 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16458 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16459 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16463 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16464 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16467 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16469 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16473 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16476 unsigned size
= et
.size
>> 3;
16477 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16478 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16479 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16480 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16481 inst
.instruction
|= (isquad
!= 0) << 6;
16482 inst
.instruction
|= immbits
<< 16;
16483 inst
.instruction
|= (size
>> 3) << 7;
16484 inst
.instruction
|= (size
& 0x7) << 19;
16486 inst
.instruction
|= (uval
!= 0) << 24;
16488 neon_dp_fixup (&inst
);
16494 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16497 if (!inst
.operands
[2].isreg
)
16499 enum neon_shape rs
;
16500 struct neon_type_el et
;
16501 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16503 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16504 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_MVE
);
16508 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16509 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16511 int imm
= inst
.operands
[2].imm
;
16513 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16514 _("immediate out of range for shift"));
16515 NEON_ENCODE (IMMED
, inst
);
16516 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16520 enum neon_shape rs
;
16521 struct neon_type_el et
;
16522 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16524 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16525 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16529 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16530 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16536 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16537 _("invalid instruction shape"));
16538 if (inst
.operands
[2].reg
== REG_SP
)
16539 as_tsktsk (MVE_BAD_SP
);
16540 else if (inst
.operands
[2].reg
== REG_PC
)
16541 as_tsktsk (MVE_BAD_PC
);
16543 inst
.instruction
= 0xee311e60;
16544 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16545 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16546 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16547 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16548 inst
.instruction
|= inst
.operands
[2].reg
;
16555 /* VSHL/VQSHL 3-register variants have syntax such as:
16557 whereas other 3-register operations encoded by neon_three_same have
16560 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
16561 operands[2].reg here. */
16562 tmp
= inst
.operands
[2].reg
;
16563 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16564 inst
.operands
[1].reg
= tmp
;
16565 NEON_ENCODE (INTEGER
, inst
);
16566 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16572 do_neon_qshl (void)
16574 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16577 if (!inst
.operands
[2].isreg
)
16579 enum neon_shape rs
;
16580 struct neon_type_el et
;
16581 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16583 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16584 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_SU_MVE
);
16588 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16589 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16591 int imm
= inst
.operands
[2].imm
;
16593 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16594 _("immediate out of range for shift"));
16595 NEON_ENCODE (IMMED
, inst
);
16596 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
16600 enum neon_shape rs
;
16601 struct neon_type_el et
;
16603 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16605 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16606 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16610 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16611 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16616 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16617 _("invalid instruction shape"));
16618 if (inst
.operands
[2].reg
== REG_SP
)
16619 as_tsktsk (MVE_BAD_SP
);
16620 else if (inst
.operands
[2].reg
== REG_PC
)
16621 as_tsktsk (MVE_BAD_PC
);
16623 inst
.instruction
= 0xee311ee0;
16624 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16625 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16626 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16627 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16628 inst
.instruction
|= inst
.operands
[2].reg
;
16635 /* See note in do_neon_shl. */
16636 tmp
= inst
.operands
[2].reg
;
16637 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16638 inst
.operands
[1].reg
= tmp
;
16639 NEON_ENCODE (INTEGER
, inst
);
16640 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16646 do_neon_rshl (void)
16648 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16651 enum neon_shape rs
;
16652 struct neon_type_el et
;
16653 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16655 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16656 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16660 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16661 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16668 if (inst
.operands
[2].reg
== REG_PC
)
16669 as_tsktsk (MVE_BAD_PC
);
16670 else if (inst
.operands
[2].reg
== REG_SP
)
16671 as_tsktsk (MVE_BAD_SP
);
16673 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16674 _("invalid instruction shape"));
16676 if (inst
.instruction
== 0x0000510)
16677 /* We are dealing with vqrshl. */
16678 inst
.instruction
= 0xee331ee0;
16680 /* We are dealing with vrshl. */
16681 inst
.instruction
= 0xee331e60;
16683 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16684 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16685 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16686 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16687 inst
.instruction
|= inst
.operands
[2].reg
;
16692 tmp
= inst
.operands
[2].reg
;
16693 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16694 inst
.operands
[1].reg
= tmp
;
16695 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16700 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
16702 /* Handle .I8 pseudo-instructions. */
16705 /* Unfortunately, this will make everything apart from zero out-of-range.
16706 FIXME is this the intended semantics? There doesn't seem much point in
16707 accepting .I8 if so. */
16708 immediate
|= immediate
<< 8;
16714 if (immediate
== (immediate
& 0x000000ff))
16716 *immbits
= immediate
;
16719 else if (immediate
== (immediate
& 0x0000ff00))
16721 *immbits
= immediate
>> 8;
16724 else if (immediate
== (immediate
& 0x00ff0000))
16726 *immbits
= immediate
>> 16;
16729 else if (immediate
== (immediate
& 0xff000000))
16731 *immbits
= immediate
>> 24;
16734 if ((immediate
& 0xffff) != (immediate
>> 16))
16735 goto bad_immediate
;
16736 immediate
&= 0xffff;
16739 if (immediate
== (immediate
& 0x000000ff))
16741 *immbits
= immediate
;
16744 else if (immediate
== (immediate
& 0x0000ff00))
16746 *immbits
= immediate
>> 8;
16751 first_error (_("immediate value out of range"));
16756 do_neon_logic (void)
16758 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
16760 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16762 && !check_simd_pred_availability (FALSE
,
16763 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16765 else if (rs
!= NS_QQQ
16766 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
16767 first_error (BAD_FPU
);
16769 neon_check_type (3, rs
, N_IGNORE_TYPE
);
16770 /* U bit and size field were set as part of the bitmask. */
16771 NEON_ENCODE (INTEGER
, inst
);
16772 neon_three_same (neon_quad (rs
), 0, -1);
16776 const int three_ops_form
= (inst
.operands
[2].present
16777 && !inst
.operands
[2].isreg
);
16778 const int immoperand
= (three_ops_form
? 2 : 1);
16779 enum neon_shape rs
= (three_ops_form
16780 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
16781 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
16782 /* Because neon_select_shape makes the second operand a copy of the first
16783 if the second operand is not present. */
16785 && !check_simd_pred_availability (FALSE
,
16786 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16788 else if (rs
!= NS_QQI
16789 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
16790 first_error (BAD_FPU
);
16792 struct neon_type_el et
;
16793 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16794 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
16796 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
16799 if (et
.type
== NT_invtype
)
16801 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
16806 if (three_ops_form
)
16807 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16808 _("first and second operands shall be the same register"));
16810 NEON_ENCODE (IMMED
, inst
);
16812 immbits
= inst
.operands
[immoperand
].imm
;
16815 /* .i64 is a pseudo-op, so the immediate must be a repeating
16817 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
16818 inst
.operands
[immoperand
].reg
: 0))
16820 /* Set immbits to an invalid constant. */
16821 immbits
= 0xdeadbeef;
16828 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16832 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16836 /* Pseudo-instruction for VBIC. */
16837 neon_invert_size (&immbits
, 0, et
.size
);
16838 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16842 /* Pseudo-instruction for VORR. */
16843 neon_invert_size (&immbits
, 0, et
.size
);
16844 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
16854 inst
.instruction
|= neon_quad (rs
) << 6;
16855 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16856 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16857 inst
.instruction
|= cmode
<< 8;
16858 neon_write_immbits (immbits
);
16860 neon_dp_fixup (&inst
);
16865 do_neon_bitfield (void)
16867 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16868 neon_check_type (3, rs
, N_IGNORE_TYPE
);
16869 neon_three_same (neon_quad (rs
), 0, -1);
16873 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
16876 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
16877 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
16879 if (et
.type
== NT_float
)
16881 NEON_ENCODE (FLOAT
, inst
);
16883 mve_encode_qqr (et
.size
, 0, 1);
16885 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
16889 NEON_ENCODE (INTEGER
, inst
);
16891 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
16893 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
16899 do_neon_dyadic_if_su_d (void)
16901 /* This version only allow D registers, but that constraint is enforced during
16902 operand parsing so we don't need to do anything extra here. */
16903 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
16907 do_neon_dyadic_if_i_d (void)
16909 /* The "untyped" case can't happen. Do this to stop the "U" bit being
16910 affected if we specify unsigned args. */
16911 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
16915 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
16917 constraint (size
< 32, BAD_ADDR_MODE
);
16918 constraint (size
!= elsize
, BAD_EL_TYPE
);
16919 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16920 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
16921 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
16922 _("destination register and offset register may not be the"
16925 int imm
= inst
.relocs
[0].exp
.X_add_number
;
16932 constraint ((imm
% (size
/ 8) != 0)
16933 || imm
> (0x7f << neon_logbits (size
)),
16934 (size
== 32) ? _("immediate must be a multiple of 4 in the"
16935 " range of +/-[0,508]")
16936 : _("immediate must be a multiple of 8 in the"
16937 " range of +/-[0,1016]"));
16938 inst
.instruction
|= 0x11 << 24;
16939 inst
.instruction
|= add
<< 23;
16940 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16941 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
16942 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16943 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16944 inst
.instruction
|= 1 << 12;
16945 inst
.instruction
|= (size
== 64) << 8;
16946 inst
.instruction
&= 0xffffff00;
16947 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16948 inst
.instruction
|= imm
>> neon_logbits (size
);
16952 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
16954 unsigned os
= inst
.operands
[1].imm
>> 5;
16955 constraint (os
!= 0 && size
== 8,
16956 _("can not shift offsets when accessing less than half-word"));
16957 constraint (os
&& os
!= neon_logbits (size
),
16958 _("shift immediate must be 1, 2 or 3 for half-word, word"
16959 " or double-word accesses respectively"));
16960 if (inst
.operands
[1].reg
== REG_PC
)
16961 as_tsktsk (MVE_BAD_PC
);
16966 constraint (elsize
>= 64, BAD_EL_TYPE
);
16969 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
16973 constraint (elsize
!= size
, BAD_EL_TYPE
);
16978 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
16982 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
16983 _("destination register and offset register may not be"
16985 constraint (size
== elsize
&& inst
.vectype
.el
[0].type
!= NT_unsigned
,
16987 constraint (inst
.vectype
.el
[0].type
!= NT_unsigned
16988 && inst
.vectype
.el
[0].type
!= NT_signed
, BAD_EL_TYPE
);
16989 inst
.instruction
|= (inst
.vectype
.el
[0].type
== NT_unsigned
) << 28;
16993 constraint (inst
.vectype
.el
[0].type
!= NT_untyped
, BAD_EL_TYPE
);
16996 inst
.instruction
|= 1 << 23;
16997 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16998 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16999 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17000 inst
.instruction
|= neon_logbits (elsize
) << 7;
17001 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
17002 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
17003 inst
.instruction
|= !!os
;
17007 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
17009 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
17011 constraint (size
>= 64, BAD_ADDR_MODE
);
17015 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17018 constraint (elsize
!= size
, BAD_EL_TYPE
);
17025 constraint (elsize
!= size
&& type
!= NT_unsigned
17026 && type
!= NT_signed
, BAD_EL_TYPE
);
17030 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
17033 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17041 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
17046 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17049 constraint (1, _("immediate must be a multiple of 2 in the"
17050 " range of +/-[0,254]"));
17053 constraint (1, _("immediate must be a multiple of 4 in the"
17054 " range of +/-[0,508]"));
17059 if (size
!= elsize
)
17061 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
17062 constraint (inst
.operands
[0].reg
> 14,
17063 _("MVE vector register in the range [Q0..Q7] expected"));
17064 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
17065 inst
.instruction
|= (size
== 16) << 19;
17066 inst
.instruction
|= neon_logbits (elsize
) << 7;
17070 if (inst
.operands
[1].reg
== REG_PC
)
17071 as_tsktsk (MVE_BAD_PC
);
17072 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17073 as_tsktsk (MVE_BAD_SP
);
17074 inst
.instruction
|= 1 << 12;
17075 inst
.instruction
|= neon_logbits (size
) << 7;
17077 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
17078 inst
.instruction
|= add
<< 23;
17079 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17080 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17081 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17082 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17083 inst
.instruction
&= 0xffffff80;
17084 inst
.instruction
|= imm
>> neon_logbits (size
);
17089 do_mve_vstr_vldr (void)
17094 if (inst
.cond
> COND_ALWAYS
)
17095 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17097 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17099 switch (inst
.instruction
)
17106 /* fall through. */
17112 /* fall through. */
17118 /* fall through. */
17124 /* fall through. */
17129 unsigned elsize
= inst
.vectype
.el
[0].size
;
17131 if (inst
.operands
[1].isquad
)
17133 /* We are dealing with [Q, imm]{!} cases. */
17134 do_mve_vstr_vldr_QI (size
, elsize
, load
);
17138 if (inst
.operands
[1].immisreg
== 2)
17140 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17141 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
17143 else if (!inst
.operands
[1].immisreg
)
17145 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17146 do_mve_vstr_vldr_RI (size
, elsize
, load
);
17149 constraint (1, BAD_ADDR_MODE
);
17156 do_mve_vst_vld (void)
17158 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17161 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
17162 || inst
.relocs
[0].exp
.X_add_number
!= 0
17163 || inst
.operands
[1].immisreg
!= 0,
17165 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
17166 if (inst
.operands
[1].reg
== REG_PC
)
17167 as_tsktsk (MVE_BAD_PC
);
17168 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17169 as_tsktsk (MVE_BAD_SP
);
17172 /* These instructions are one of the "exceptions" mentioned in
17173 handle_pred_state. They are MVE instructions that are not VPT compatible
17174 and do not accept a VPT code, thus appending such a code is a syntax
17176 if (inst
.cond
> COND_ALWAYS
)
17177 first_error (BAD_SYNTAX
);
17178 /* If we append a scalar condition code we can set this to
17179 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17180 else if (inst
.cond
< COND_ALWAYS
)
17181 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17183 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
17185 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17186 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17187 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17188 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17189 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
17194 do_mve_vaddlv (void)
17196 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
17197 struct neon_type_el et
17198 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17200 if (et
.type
== NT_invtype
)
17201 first_error (BAD_EL_TYPE
);
17203 if (inst
.cond
> COND_ALWAYS
)
17204 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17206 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17208 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17210 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17211 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17212 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17213 inst
.instruction
|= inst
.operands
[2].reg
;
17218 do_neon_dyadic_if_su (void)
17220 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17221 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17224 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17225 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17226 && et
.type
== NT_float
17227 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17229 if (!check_simd_pred_availability (et
.type
== NT_float
,
17230 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17233 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17237 do_neon_addsub_if_i (void)
17239 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17240 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17243 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17244 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17245 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17247 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17248 /* If we are parsing Q registers and the element types match MVE, which NEON
17249 also supports, then we must check whether this is an instruction that can
17250 be used by both MVE/NEON. This distinction can be made based on whether
17251 they are predicated or not. */
17252 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17254 if (!check_simd_pred_availability (et
.type
== NT_float
,
17255 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17260 /* If they are either in a D register or are using an unsupported. */
17262 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17266 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17267 affected if we specify unsigned args. */
17268 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17271 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17273 V<op> A,B (A is operand 0, B is operand 2)
17278 so handle that case specially. */
17281 neon_exchange_operands (void)
17283 if (inst
.operands
[1].present
)
17285 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17287 /* Swap operands[1] and operands[2]. */
17288 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17289 inst
.operands
[1] = inst
.operands
[2];
17290 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17295 inst
.operands
[1] = inst
.operands
[2];
17296 inst
.operands
[2] = inst
.operands
[0];
17301 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17303 if (inst
.operands
[2].isreg
)
17306 neon_exchange_operands ();
17307 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17311 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17312 struct neon_type_el et
= neon_check_type (2, rs
,
17313 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17315 NEON_ENCODE (IMMED
, inst
);
17316 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17317 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17318 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17319 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17320 inst
.instruction
|= neon_quad (rs
) << 6;
17321 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17322 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17324 neon_dp_fixup (&inst
);
17331 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
17335 do_neon_cmp_inv (void)
17337 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
17343 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
17346 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17347 scalars, which are encoded in 5 bits, M : Rm.
17348 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17349 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17352 Dot Product instructions are similar to multiply instructions except elsize
17353 should always be 32.
17355 This function translates SCALAR, which is GAS's internal encoding of indexed
17356 scalar register, to raw encoding. There is also register and index range
17357 check based on ELSIZE. */
17360 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17362 unsigned regno
= NEON_SCALAR_REG (scalar
);
17363 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17368 if (regno
> 7 || elno
> 3)
17370 return regno
| (elno
<< 3);
17373 if (regno
> 15 || elno
> 1)
17375 return regno
| (elno
<< 4);
17379 first_error (_("scalar out of range for multiply instruction"));
17385 /* Encode multiply / multiply-accumulate scalar instructions. */
17388 neon_mul_mac (struct neon_type_el et
, int ubit
)
17392 /* Give a more helpful error message if we have an invalid type. */
17393 if (et
.type
== NT_invtype
)
17396 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17397 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17398 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17399 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17400 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17401 inst
.instruction
|= LOW4 (scalar
);
17402 inst
.instruction
|= HI1 (scalar
) << 5;
17403 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17404 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17405 inst
.instruction
|= (ubit
!= 0) << 24;
17407 neon_dp_fixup (&inst
);
17411 do_neon_mac_maybe_scalar (void)
17413 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17416 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17419 if (inst
.operands
[2].isscalar
)
17421 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17422 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17423 struct neon_type_el et
= neon_check_type (3, rs
,
17424 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17425 NEON_ENCODE (SCALAR
, inst
);
17426 neon_mul_mac (et
, neon_quad (rs
));
17428 else if (!inst
.operands
[2].isvec
)
17430 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17432 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17433 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17435 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17439 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17440 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17441 affected if we specify unsigned args. */
17442 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17447 do_neon_fmac (void)
17449 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17450 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17453 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17456 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17458 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17459 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17464 if (inst
.operands
[2].reg
== REG_SP
)
17465 as_tsktsk (MVE_BAD_SP
);
17466 else if (inst
.operands
[2].reg
== REG_PC
)
17467 as_tsktsk (MVE_BAD_PC
);
17469 inst
.instruction
= 0xee310e40;
17470 inst
.instruction
|= (et
.size
== 16) << 28;
17471 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17472 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17473 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17474 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17475 inst
.instruction
|= inst
.operands
[2].reg
;
17482 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17485 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17491 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17492 struct neon_type_el et
= neon_check_type (3, rs
,
17493 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17494 neon_three_same (neon_quad (rs
), 0, et
.size
);
17497 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
17498 same types as the MAC equivalents. The polynomial type for this instruction
17499 is encoded the same as the integer type. */
17504 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
17507 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17510 if (inst
.operands
[2].isscalar
)
17512 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17513 do_neon_mac_maybe_scalar ();
17517 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17519 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17520 struct neon_type_el et
17521 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
17522 if (et
.type
== NT_float
)
17523 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
17526 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
17530 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17531 neon_dyadic_misc (NT_poly
,
17532 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
17538 do_neon_qdmulh (void)
17540 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17543 if (inst
.operands
[2].isscalar
)
17545 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17546 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17547 struct neon_type_el et
= neon_check_type (3, rs
,
17548 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17549 NEON_ENCODE (SCALAR
, inst
);
17550 neon_mul_mac (et
, neon_quad (rs
));
17554 enum neon_shape rs
;
17555 struct neon_type_el et
;
17556 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17558 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17559 et
= neon_check_type (3, rs
,
17560 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17564 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17565 et
= neon_check_type (3, rs
,
17566 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17569 NEON_ENCODE (INTEGER
, inst
);
17571 mve_encode_qqr (et
.size
, 0, 0);
17573 /* The U bit (rounding) comes from bit mask. */
17574 neon_three_same (neon_quad (rs
), 0, et
.size
);
17579 do_mve_vaddv (void)
17581 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17582 struct neon_type_el et
17583 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
17585 if (et
.type
== NT_invtype
)
17586 first_error (BAD_EL_TYPE
);
17588 if (inst
.cond
> COND_ALWAYS
)
17589 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17591 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17593 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17595 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
17599 do_mve_vhcadd (void)
17601 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
17602 struct neon_type_el et
17603 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17605 if (inst
.cond
> COND_ALWAYS
)
17606 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17608 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17610 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
17611 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17613 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
17614 as_tsktsk (_("Warning: 32-bit element size and same first and third "
17615 "operand makes instruction UNPREDICTABLE"));
17617 mve_encode_qqq (0, et
.size
);
17618 inst
.instruction
|= (rot
== 270) << 12;
17623 do_mve_vqdmull (void)
17625 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17626 struct neon_type_el et
17627 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17630 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17631 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
17632 as_tsktsk (BAD_MVE_SRCDEST
);
17634 if (inst
.cond
> COND_ALWAYS
)
17635 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17637 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17641 mve_encode_qqq (et
.size
== 32, 64);
17642 inst
.instruction
|= 1;
17646 mve_encode_qqr (64, et
.size
== 32, 0);
17647 inst
.instruction
|= 0x3 << 5;
17654 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17655 struct neon_type_el et
17656 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
17658 if (et
.type
== NT_invtype
)
17659 first_error (BAD_EL_TYPE
);
17661 if (inst
.cond
> COND_ALWAYS
)
17662 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17664 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17666 mve_encode_qqq (0, 64);
17670 do_mve_vbrsr (void)
17672 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17673 struct neon_type_el et
17674 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17676 if (inst
.cond
> COND_ALWAYS
)
17677 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17679 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17681 mve_encode_qqr (et
.size
, 0, 0);
17687 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
17689 if (inst
.cond
> COND_ALWAYS
)
17690 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17692 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17694 mve_encode_qqq (1, 64);
17698 do_mve_vmulh (void)
17700 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17701 struct neon_type_el et
17702 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17704 if (inst
.cond
> COND_ALWAYS
)
17705 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17707 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17709 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
17713 do_mve_vqdmlah (void)
17715 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17716 struct neon_type_el et
17717 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17719 if (inst
.cond
> COND_ALWAYS
)
17720 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17722 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17724 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
17728 do_mve_vqdmladh (void)
17730 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17731 struct neon_type_el et
17732 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17734 if (inst
.cond
> COND_ALWAYS
)
17735 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17737 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17740 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17741 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
17742 as_tsktsk (BAD_MVE_SRCDEST
);
17744 mve_encode_qqq (0, et
.size
);
17749 do_mve_vmull (void)
17752 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
17753 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
17754 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
17755 && inst
.cond
== COND_ALWAYS
17756 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
17761 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17762 N_SUF_32
| N_F64
| N_P8
17763 | N_P16
| N_I_MVE
| N_KEY
);
17764 if (((et
.type
== NT_poly
) && et
.size
== 8
17765 && ARM_CPU_IS_ANY (cpu_variant
))
17766 || (et
.type
== NT_integer
) || (et
.type
== NT_float
))
17773 constraint (rs
!= NS_QQQ
, BAD_FPU
);
17774 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17775 N_SU_32
| N_P8
| N_P16
| N_KEY
);
17777 /* We are dealing with MVE's vmullt. */
17779 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17780 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
17781 as_tsktsk (BAD_MVE_SRCDEST
);
17783 if (inst
.cond
> COND_ALWAYS
)
17784 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17786 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17788 if (et
.type
== NT_poly
)
17789 mve_encode_qqq (neon_logbits (et
.size
), 64);
17791 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
17796 inst
.instruction
= N_MNEM_vmul
;
17799 inst
.pred_insn_type
= INSIDE_IT_INSN
;
17804 do_mve_vabav (void)
17806 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
17811 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17814 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
17815 | N_S16
| N_S32
| N_U8
| N_U16
17818 if (inst
.cond
> COND_ALWAYS
)
17819 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17821 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17823 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
17827 do_mve_vmladav (void)
17829 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
17830 struct neon_type_el et
= neon_check_type (3, rs
,
17831 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17833 if (et
.type
== NT_unsigned
17834 && (inst
.instruction
== M_MNEM_vmladavx
17835 || inst
.instruction
== M_MNEM_vmladavax
17836 || inst
.instruction
== M_MNEM_vmlsdav
17837 || inst
.instruction
== M_MNEM_vmlsdava
17838 || inst
.instruction
== M_MNEM_vmlsdavx
17839 || inst
.instruction
== M_MNEM_vmlsdavax
))
17840 first_error (BAD_SIMD_TYPE
);
17842 constraint (inst
.operands
[2].reg
> 14,
17843 _("MVE vector register in the range [Q0..Q7] expected"));
17845 if (inst
.cond
> COND_ALWAYS
)
17846 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17848 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17850 if (inst
.instruction
== M_MNEM_vmlsdav
17851 || inst
.instruction
== M_MNEM_vmlsdava
17852 || inst
.instruction
== M_MNEM_vmlsdavx
17853 || inst
.instruction
== M_MNEM_vmlsdavax
)
17854 inst
.instruction
|= (et
.size
== 8) << 28;
17856 inst
.instruction
|= (et
.size
== 8) << 8;
17858 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
17859 inst
.instruction
|= (et
.size
== 32) << 16;
17863 do_mve_vmlaldav (void)
17865 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
17866 struct neon_type_el et
17867 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
17868 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
17870 if (et
.type
== NT_unsigned
17871 && (inst
.instruction
== M_MNEM_vmlsldav
17872 || inst
.instruction
== M_MNEM_vmlsldava
17873 || inst
.instruction
== M_MNEM_vmlsldavx
17874 || inst
.instruction
== M_MNEM_vmlsldavax
))
17875 first_error (BAD_SIMD_TYPE
);
17877 if (inst
.cond
> COND_ALWAYS
)
17878 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17880 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17882 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
17886 do_mve_vrmlaldavh (void)
17888 struct neon_type_el et
;
17889 if (inst
.instruction
== M_MNEM_vrmlsldavh
17890 || inst
.instruction
== M_MNEM_vrmlsldavha
17891 || inst
.instruction
== M_MNEM_vrmlsldavhx
17892 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
17894 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
17895 if (inst
.operands
[1].reg
== REG_SP
)
17896 as_tsktsk (MVE_BAD_SP
);
17900 if (inst
.instruction
== M_MNEM_vrmlaldavhx
17901 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
17902 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
17904 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
17905 N_U32
| N_S32
| N_KEY
);
17906 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
17907 with vmax/min instructions, making the use of SP in assembly really
17908 nonsensical, so instead of issuing a warning like we do for other uses
17909 of SP for the odd register operand we error out. */
17910 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
17913 /* Make sure we still check the second operand is an odd one and that PC is
17914 disallowed. This because we are parsing for any GPR operand, to be able
17915 to distinguish between giving a warning or an error for SP as described
17917 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
17918 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17920 if (inst
.cond
> COND_ALWAYS
)
17921 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17923 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17925 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
17930 do_mve_vmaxnmv (void)
17932 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17933 struct neon_type_el et
17934 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
17936 if (inst
.cond
> COND_ALWAYS
)
17937 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17939 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17941 if (inst
.operands
[0].reg
== REG_SP
)
17942 as_tsktsk (MVE_BAD_SP
);
17943 else if (inst
.operands
[0].reg
== REG_PC
)
17944 as_tsktsk (MVE_BAD_PC
);
17946 mve_encode_rq (et
.size
== 16, 64);
17950 do_mve_vmaxv (void)
17952 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17953 struct neon_type_el et
;
17955 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
17956 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
17958 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17960 if (inst
.cond
> COND_ALWAYS
)
17961 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17963 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17965 if (inst
.operands
[0].reg
== REG_SP
)
17966 as_tsktsk (MVE_BAD_SP
);
17967 else if (inst
.operands
[0].reg
== REG_PC
)
17968 as_tsktsk (MVE_BAD_PC
);
17970 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
17975 do_neon_qrdmlah (void)
17977 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17979 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17981 /* Check we're on the correct architecture. */
17982 if (!mark_feature_used (&fpu_neon_ext_armv8
))
17984 = _("instruction form not available on this architecture.");
17985 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
17987 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
17988 record_feature_use (&fpu_neon_ext_v8_1
);
17990 if (inst
.operands
[2].isscalar
)
17992 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17993 struct neon_type_el et
= neon_check_type (3, rs
,
17994 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17995 NEON_ENCODE (SCALAR
, inst
);
17996 neon_mul_mac (et
, neon_quad (rs
));
18000 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18001 struct neon_type_el et
= neon_check_type (3, rs
,
18002 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18003 NEON_ENCODE (INTEGER
, inst
);
18004 /* The U bit (rounding) comes from bit mask. */
18005 neon_three_same (neon_quad (rs
), 0, et
.size
);
18010 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18011 struct neon_type_el et
18012 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18014 NEON_ENCODE (INTEGER
, inst
);
18015 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18020 do_neon_fcmp_absolute (void)
18022 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18023 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18024 N_F_16_32
| N_KEY
);
18025 /* Size field comes from bit mask. */
18026 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
18030 do_neon_fcmp_absolute_inv (void)
18032 neon_exchange_operands ();
18033 do_neon_fcmp_absolute ();
18037 do_neon_step (void)
18039 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18040 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18041 N_F_16_32
| N_KEY
);
18042 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
18046 do_neon_abs_neg (void)
18048 enum neon_shape rs
;
18049 struct neon_type_el et
;
18051 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
18054 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18055 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
18057 if (!check_simd_pred_availability (et
.type
== NT_float
,
18058 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18061 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18062 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18063 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18064 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18065 inst
.instruction
|= neon_quad (rs
) << 6;
18066 inst
.instruction
|= (et
.type
== NT_float
) << 10;
18067 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18069 neon_dp_fixup (&inst
);
18075 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18078 enum neon_shape rs
;
18079 struct neon_type_el et
;
18080 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18082 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18083 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18087 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18088 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18092 int imm
= inst
.operands
[2].imm
;
18093 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18094 _("immediate out of range for insert"));
18095 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18101 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18104 enum neon_shape rs
;
18105 struct neon_type_el et
;
18106 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18108 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18109 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18113 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18114 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18117 int imm
= inst
.operands
[2].imm
;
18118 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18119 _("immediate out of range for insert"));
18120 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
18124 do_neon_qshlu_imm (void)
18126 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18129 enum neon_shape rs
;
18130 struct neon_type_el et
;
18131 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18133 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18134 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18138 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18139 et
= neon_check_type (2, rs
, N_EQK
| N_UNS
,
18140 N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
18143 int imm
= inst
.operands
[2].imm
;
18144 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18145 _("immediate out of range for shift"));
18146 /* Only encodes the 'U present' variant of the instruction.
18147 In this case, signed types have OP (bit 8) set to 0.
18148 Unsigned types have OP set to 1. */
18149 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
18150 /* The rest of the bits are the same as other immediate shifts. */
18151 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18155 do_neon_qmovn (void)
18157 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18158 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18159 /* Saturating move where operands can be signed or unsigned, and the
18160 destination has the same signedness. */
18161 NEON_ENCODE (INTEGER
, inst
);
18162 if (et
.type
== NT_unsigned
)
18163 inst
.instruction
|= 0xc0;
18165 inst
.instruction
|= 0x80;
18166 neon_two_same (0, 1, et
.size
/ 2);
18170 do_neon_qmovun (void)
18172 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18173 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18174 /* Saturating move with unsigned results. Operands must be signed. */
18175 NEON_ENCODE (INTEGER
, inst
);
18176 neon_two_same (0, 1, et
.size
/ 2);
18180 do_neon_rshift_sat_narrow (void)
18182 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18183 or unsigned. If operands are unsigned, results must also be unsigned. */
18184 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18185 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18186 int imm
= inst
.operands
[2].imm
;
18187 /* This gets the bounds check, size encoding and immediate bits calculation
18191 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18192 VQMOVN.I<size> <Dd>, <Qm>. */
18195 inst
.operands
[2].present
= 0;
18196 inst
.instruction
= N_MNEM_vqmovn
;
18201 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18202 _("immediate out of range"));
18203 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
18207 do_neon_rshift_sat_narrow_u (void)
18209 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18210 or unsigned. If operands are unsigned, results must also be unsigned. */
18211 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18212 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18213 int imm
= inst
.operands
[2].imm
;
18214 /* This gets the bounds check, size encoding and immediate bits calculation
18218 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18219 VQMOVUN.I<size> <Dd>, <Qm>. */
18222 inst
.operands
[2].present
= 0;
18223 inst
.instruction
= N_MNEM_vqmovun
;
18228 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18229 _("immediate out of range"));
18230 /* FIXME: The manual is kind of unclear about what value U should have in
18231 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18233 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
18237 do_neon_movn (void)
18239 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18240 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18241 NEON_ENCODE (INTEGER
, inst
);
18242 neon_two_same (0, 1, et
.size
/ 2);
18246 do_neon_rshift_narrow (void)
18248 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18249 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18250 int imm
= inst
.operands
[2].imm
;
18251 /* This gets the bounds check, size encoding and immediate bits calculation
18255 /* If immediate is zero then we are a pseudo-instruction for
18256 VMOVN.I<size> <Dd>, <Qm> */
18259 inst
.operands
[2].present
= 0;
18260 inst
.instruction
= N_MNEM_vmovn
;
18265 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18266 _("immediate out of range for narrowing operation"));
18267 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
18271 do_neon_shll (void)
18273 /* FIXME: Type checking when lengthening. */
18274 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18275 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18276 unsigned imm
= inst
.operands
[2].imm
;
18278 if (imm
== et
.size
)
18280 /* Maximum shift variant. */
18281 NEON_ENCODE (INTEGER
, inst
);
18282 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18283 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18284 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18285 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18286 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18288 neon_dp_fixup (&inst
);
18292 /* A more-specific type check for non-max versions. */
18293 et
= neon_check_type (2, NS_QDI
,
18294 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18295 NEON_ENCODE (IMMED
, inst
);
18296 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
18300 /* Check the various types for the VCVT instruction, and return which version
18301 the current instruction is. */
18303 #define CVT_FLAVOUR_VAR \
18304 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18305 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18306 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18307 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18308 /* Half-precision conversions. */ \
18309 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18310 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18311 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18312 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18313 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18314 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18315 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18316 Compared with single/double precision variants, only the co-processor \
18317 field is different, so the encoding flow is reused here. */ \
18318 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18319 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18320 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18321 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18322 /* VFP instructions. */ \
18323 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18324 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18325 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18326 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18327 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18328 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18329 /* VFP instructions with bitshift. */ \
18330 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18331 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18332 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18333 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18334 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18335 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18336 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18337 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18339 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18340 neon_cvt_flavour_##C,
18342 /* The different types of conversions we can do. */
18343 enum neon_cvt_flavour
18346 neon_cvt_flavour_invalid
,
18347 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18352 static enum neon_cvt_flavour
18353 get_neon_cvt_flavour (enum neon_shape rs
)
18355 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18356 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18357 if (et.type != NT_invtype) \
18359 inst.error = NULL; \
18360 return (neon_cvt_flavour_##C); \
18363 struct neon_type_el et
;
18364 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18365 || rs
== NS_FF
) ? N_VFP
: 0;
18366 /* The instruction versions which take an immediate take one register
18367 argument, which is extended to the width of the full register. Thus the
18368 "source" and "destination" registers must have the same width. Hack that
18369 here by making the size equal to the key (wider, in this case) operand. */
18370 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18374 return neon_cvt_flavour_invalid
;
18389 /* Neon-syntax VFP conversions. */
18392 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18394 const char *opname
= 0;
18396 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18397 || rs
== NS_FHI
|| rs
== NS_HFI
)
18399 /* Conversions with immediate bitshift. */
18400 const char *enc
[] =
18402 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18408 if (flavour
< (int) ARRAY_SIZE (enc
))
18410 opname
= enc
[flavour
];
18411 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18412 _("operands 0 and 1 must be the same register"));
18413 inst
.operands
[1] = inst
.operands
[2];
18414 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18419 /* Conversions without bitshift. */
18420 const char *enc
[] =
18422 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18428 if (flavour
< (int) ARRAY_SIZE (enc
))
18429 opname
= enc
[flavour
];
18433 do_vfp_nsyn_opcode (opname
);
18435 /* ARMv8.2 fp16 VCVT instruction. */
18436 if (flavour
== neon_cvt_flavour_s32_f16
18437 || flavour
== neon_cvt_flavour_u32_f16
18438 || flavour
== neon_cvt_flavour_f16_u32
18439 || flavour
== neon_cvt_flavour_f16_s32
)
18440 do_scalar_fp16_v82_encode ();
18444 do_vfp_nsyn_cvtz (void)
18446 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18447 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18448 const char *enc
[] =
18450 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18456 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18457 do_vfp_nsyn_opcode (enc
[flavour
]);
18461 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18462 enum neon_cvt_mode mode
)
18467 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18468 D register operands. */
18469 if (flavour
== neon_cvt_flavour_s32_f64
18470 || flavour
== neon_cvt_flavour_u32_f64
)
18471 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18474 if (flavour
== neon_cvt_flavour_s32_f16
18475 || flavour
== neon_cvt_flavour_u32_f16
)
18476 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18479 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18483 case neon_cvt_flavour_s32_f64
:
18487 case neon_cvt_flavour_s32_f32
:
18491 case neon_cvt_flavour_s32_f16
:
18495 case neon_cvt_flavour_u32_f64
:
18499 case neon_cvt_flavour_u32_f32
:
18503 case neon_cvt_flavour_u32_f16
:
18508 first_error (_("invalid instruction shape"));
18514 case neon_cvt_mode_a
: rm
= 0; break;
18515 case neon_cvt_mode_n
: rm
= 1; break;
18516 case neon_cvt_mode_p
: rm
= 2; break;
18517 case neon_cvt_mode_m
: rm
= 3; break;
18518 default: first_error (_("invalid rounding mode")); return;
18521 NEON_ENCODE (FPV8
, inst
);
18522 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
18523 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
18524 inst
.instruction
|= sz
<< 8;
18526 /* ARMv8.2 fp16 VCVT instruction. */
18527 if (flavour
== neon_cvt_flavour_s32_f16
18528 ||flavour
== neon_cvt_flavour_u32_f16
)
18529 do_scalar_fp16_v82_encode ();
18530 inst
.instruction
|= op
<< 7;
18531 inst
.instruction
|= rm
<< 16;
18532 inst
.instruction
|= 0xf0000000;
18533 inst
.is_neon
= TRUE
;
18537 do_neon_cvt_1 (enum neon_cvt_mode mode
)
18539 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
18540 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
18541 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
18543 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18545 if (flavour
== neon_cvt_flavour_invalid
)
18548 /* PR11109: Handle round-to-zero for VCVT conversions. */
18549 if (mode
== neon_cvt_mode_z
18550 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
18551 && (flavour
== neon_cvt_flavour_s16_f16
18552 || flavour
== neon_cvt_flavour_u16_f16
18553 || flavour
== neon_cvt_flavour_s32_f32
18554 || flavour
== neon_cvt_flavour_u32_f32
18555 || flavour
== neon_cvt_flavour_s32_f64
18556 || flavour
== neon_cvt_flavour_u32_f64
)
18557 && (rs
== NS_FD
|| rs
== NS_FF
))
18559 do_vfp_nsyn_cvtz ();
18563 /* ARMv8.2 fp16 VCVT conversions. */
18564 if (mode
== neon_cvt_mode_z
18565 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
18566 && (flavour
== neon_cvt_flavour_s32_f16
18567 || flavour
== neon_cvt_flavour_u32_f16
)
18570 do_vfp_nsyn_cvtz ();
18571 do_scalar_fp16_v82_encode ();
18575 /* VFP rather than Neon conversions. */
18576 if (flavour
>= neon_cvt_flavour_first_fp
)
18578 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
18579 do_vfp_nsyn_cvt (rs
, flavour
);
18581 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
18589 if (mode
== neon_cvt_mode_z
18590 && (flavour
== neon_cvt_flavour_f16_s16
18591 || flavour
== neon_cvt_flavour_f16_u16
18592 || flavour
== neon_cvt_flavour_s16_f16
18593 || flavour
== neon_cvt_flavour_u16_f16
18594 || flavour
== neon_cvt_flavour_f32_u32
18595 || flavour
== neon_cvt_flavour_f32_s32
18596 || flavour
== neon_cvt_flavour_s32_f32
18597 || flavour
== neon_cvt_flavour_u32_f32
))
18599 if (!check_simd_pred_availability (TRUE
,
18600 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18603 else if (mode
== neon_cvt_mode_n
)
18605 /* We are dealing with vcvt with the 'ne' condition. */
18607 inst
.instruction
= N_MNEM_vcvt
;
18608 do_neon_cvt_1 (neon_cvt_mode_z
);
18611 /* fall through. */
18615 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
18616 0x0000100, 0x1000100, 0x0, 0x1000000};
18618 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18619 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18622 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18624 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
18625 _("immediate value out of range"));
18628 case neon_cvt_flavour_f16_s16
:
18629 case neon_cvt_flavour_f16_u16
:
18630 case neon_cvt_flavour_s16_f16
:
18631 case neon_cvt_flavour_u16_f16
:
18632 constraint (inst
.operands
[2].imm
> 16,
18633 _("immediate value out of range"));
18635 case neon_cvt_flavour_f32_u32
:
18636 case neon_cvt_flavour_f32_s32
:
18637 case neon_cvt_flavour_s32_f32
:
18638 case neon_cvt_flavour_u32_f32
:
18639 constraint (inst
.operands
[2].imm
> 32,
18640 _("immediate value out of range"));
18643 inst
.error
= BAD_FPU
;
18648 /* Fixed-point conversion with #0 immediate is encoded as an
18649 integer conversion. */
18650 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
18652 NEON_ENCODE (IMMED
, inst
);
18653 if (flavour
!= neon_cvt_flavour_invalid
)
18654 inst
.instruction
|= enctab
[flavour
];
18655 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18656 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18657 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18658 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18659 inst
.instruction
|= neon_quad (rs
) << 6;
18660 inst
.instruction
|= 1 << 21;
18661 if (flavour
< neon_cvt_flavour_s16_f16
)
18663 inst
.instruction
|= 1 << 21;
18664 immbits
= 32 - inst
.operands
[2].imm
;
18665 inst
.instruction
|= immbits
<< 16;
18669 inst
.instruction
|= 3 << 20;
18670 immbits
= 16 - inst
.operands
[2].imm
;
18671 inst
.instruction
|= immbits
<< 16;
18672 inst
.instruction
&= ~(1 << 9);
18675 neon_dp_fixup (&inst
);
18680 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
18681 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
18682 && (flavour
== neon_cvt_flavour_s16_f16
18683 || flavour
== neon_cvt_flavour_u16_f16
18684 || flavour
== neon_cvt_flavour_s32_f32
18685 || flavour
== neon_cvt_flavour_u32_f32
))
18687 if (!check_simd_pred_availability (TRUE
,
18688 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
18691 else if (mode
== neon_cvt_mode_z
18692 && (flavour
== neon_cvt_flavour_f16_s16
18693 || flavour
== neon_cvt_flavour_f16_u16
18694 || flavour
== neon_cvt_flavour_s16_f16
18695 || flavour
== neon_cvt_flavour_u16_f16
18696 || flavour
== neon_cvt_flavour_f32_u32
18697 || flavour
== neon_cvt_flavour_f32_s32
18698 || flavour
== neon_cvt_flavour_s32_f32
18699 || flavour
== neon_cvt_flavour_u32_f32
))
18701 if (!check_simd_pred_availability (TRUE
,
18702 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18705 /* fall through. */
18707 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
18710 NEON_ENCODE (FLOAT
, inst
);
18711 if (!check_simd_pred_availability (TRUE
,
18712 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
18715 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18716 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18717 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18718 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18719 inst
.instruction
|= neon_quad (rs
) << 6;
18720 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
18721 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
18722 inst
.instruction
|= mode
<< 8;
18723 if (flavour
== neon_cvt_flavour_u16_f16
18724 || flavour
== neon_cvt_flavour_s16_f16
)
18725 /* Mask off the original size bits and reencode them. */
18726 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
18729 inst
.instruction
|= 0xfc000000;
18731 inst
.instruction
|= 0xf0000000;
18737 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
18738 0x100, 0x180, 0x0, 0x080};
18740 NEON_ENCODE (INTEGER
, inst
);
18742 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18744 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18748 if (flavour
!= neon_cvt_flavour_invalid
)
18749 inst
.instruction
|= enctab
[flavour
];
18751 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18752 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18753 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18754 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18755 inst
.instruction
|= neon_quad (rs
) << 6;
18756 if (flavour
>= neon_cvt_flavour_s16_f16
18757 && flavour
<= neon_cvt_flavour_f16_u16
)
18758 /* Half precision. */
18759 inst
.instruction
|= 1 << 18;
18761 inst
.instruction
|= 2 << 18;
18763 neon_dp_fixup (&inst
);
18768 /* Half-precision conversions for Advanced SIMD -- neon. */
18771 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18775 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
18777 as_bad (_("operand size must match register width"));
18782 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
18784 as_bad (_("operand size must match register width"));
18789 inst
.instruction
= 0x3b60600;
18791 inst
.instruction
= 0x3b60700;
18793 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18794 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18795 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18796 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18797 neon_dp_fixup (&inst
);
18801 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
18802 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
18803 do_vfp_nsyn_cvt (rs
, flavour
);
18805 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
18810 do_neon_cvtr (void)
18812 do_neon_cvt_1 (neon_cvt_mode_x
);
18818 do_neon_cvt_1 (neon_cvt_mode_z
);
18822 do_neon_cvta (void)
18824 do_neon_cvt_1 (neon_cvt_mode_a
);
18828 do_neon_cvtn (void)
18830 do_neon_cvt_1 (neon_cvt_mode_n
);
18834 do_neon_cvtp (void)
18836 do_neon_cvt_1 (neon_cvt_mode_p
);
18840 do_neon_cvtm (void)
18842 do_neon_cvt_1 (neon_cvt_mode_m
);
18846 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
18849 mark_feature_used (&fpu_vfp_ext_armv8
);
18851 encode_arm_vfp_reg (inst
.operands
[0].reg
,
18852 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
18853 encode_arm_vfp_reg (inst
.operands
[1].reg
,
18854 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
18855 inst
.instruction
|= to
? 0x10000 : 0;
18856 inst
.instruction
|= t
? 0x80 : 0;
18857 inst
.instruction
|= is_double
? 0x100 : 0;
18858 do_vfp_cond_or_thumb ();
18862 do_neon_cvttb_1 (bfd_boolean t
)
18864 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
18865 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
18869 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
18871 int single_to_half
= 0;
18872 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_ARCH
))
18875 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18877 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18878 && (flavour
== neon_cvt_flavour_u16_f16
18879 || flavour
== neon_cvt_flavour_s16_f16
18880 || flavour
== neon_cvt_flavour_f16_s16
18881 || flavour
== neon_cvt_flavour_f16_u16
18882 || flavour
== neon_cvt_flavour_u32_f32
18883 || flavour
== neon_cvt_flavour_s32_f32
18884 || flavour
== neon_cvt_flavour_f32_s32
18885 || flavour
== neon_cvt_flavour_f32_u32
))
18888 inst
.instruction
= N_MNEM_vcvt
;
18889 set_pred_insn_type (INSIDE_VPT_INSN
);
18890 do_neon_cvt_1 (neon_cvt_mode_z
);
18893 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
18894 single_to_half
= 1;
18895 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
18897 first_error (BAD_FPU
);
18901 inst
.instruction
= 0xee3f0e01;
18902 inst
.instruction
|= single_to_half
<< 28;
18903 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18904 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
18905 inst
.instruction
|= t
<< 12;
18906 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18907 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
18910 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
18913 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
18915 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
18918 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
18920 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
18922 /* The VCVTB and VCVTT instructions with D-register operands
18923 don't work for SP only targets. */
18924 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18928 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
18930 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
18932 /* The VCVTB and VCVTT instructions with D-register operands
18933 don't work for SP only targets. */
18934 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18938 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
18945 do_neon_cvtb (void)
18947 do_neon_cvttb_1 (FALSE
);
18952 do_neon_cvtt (void)
18954 do_neon_cvttb_1 (TRUE
);
18958 neon_move_immediate (void)
18960 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
18961 struct neon_type_el et
= neon_check_type (2, rs
,
18962 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
18963 unsigned immlo
, immhi
= 0, immbits
;
18964 int op
, cmode
, float_p
;
18966 constraint (et
.type
== NT_invtype
,
18967 _("operand size must be specified for immediate VMOV"));
18969 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
18970 op
= (inst
.instruction
& (1 << 5)) != 0;
18972 immlo
= inst
.operands
[1].imm
;
18973 if (inst
.operands
[1].regisimm
)
18974 immhi
= inst
.operands
[1].reg
;
18976 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
18977 _("immediate has bits set outside the operand size"));
18979 float_p
= inst
.operands
[1].immisfloat
;
18981 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
18982 et
.size
, et
.type
)) == FAIL
)
18984 /* Invert relevant bits only. */
18985 neon_invert_size (&immlo
, &immhi
, et
.size
);
18986 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
18987 with one or the other; those cases are caught by
18988 neon_cmode_for_move_imm. */
18990 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
18991 &op
, et
.size
, et
.type
)) == FAIL
)
18993 first_error (_("immediate out of range"));
18998 inst
.instruction
&= ~(1 << 5);
18999 inst
.instruction
|= op
<< 5;
19001 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19002 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19003 inst
.instruction
|= neon_quad (rs
) << 6;
19004 inst
.instruction
|= cmode
<< 8;
19006 neon_write_immbits (immbits
);
19012 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19015 if (inst
.operands
[1].isreg
)
19017 enum neon_shape rs
;
19018 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19019 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19021 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19023 NEON_ENCODE (INTEGER
, inst
);
19024 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19025 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19026 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19027 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19028 inst
.instruction
|= neon_quad (rs
) << 6;
19032 NEON_ENCODE (IMMED
, inst
);
19033 neon_move_immediate ();
19036 neon_dp_fixup (&inst
);
19038 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19040 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
19041 constraint ((inst
.instruction
& 0xd00) == 0xd00,
19042 _("immediate value out of range"));
19046 /* Encode instructions of form:
19048 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19049 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19052 neon_mixed_length (struct neon_type_el et
, unsigned size
)
19054 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19055 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19056 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19057 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19058 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19059 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19060 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
19061 inst
.instruction
|= neon_logbits (size
) << 20;
19063 neon_dp_fixup (&inst
);
19067 do_neon_dyadic_long (void)
19069 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
19072 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
19075 NEON_ENCODE (INTEGER
, inst
);
19076 /* FIXME: Type checking for lengthening op. */
19077 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19078 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19079 neon_mixed_length (et
, et
.size
);
19081 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19082 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
19084 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19085 in an IT block with le/lt conditions. */
19087 if (inst
.cond
== 0xf)
19089 else if (inst
.cond
== 0x10)
19092 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19094 if (inst
.instruction
== N_MNEM_vaddl
)
19096 inst
.instruction
= N_MNEM_vadd
;
19097 do_neon_addsub_if_i ();
19099 else if (inst
.instruction
== N_MNEM_vsubl
)
19101 inst
.instruction
= N_MNEM_vsub
;
19102 do_neon_addsub_if_i ();
19104 else if (inst
.instruction
== N_MNEM_vabdl
)
19106 inst
.instruction
= N_MNEM_vabd
;
19107 do_neon_dyadic_if_su ();
19111 first_error (BAD_FPU
);
19115 do_neon_abal (void)
19117 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19118 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19119 neon_mixed_length (et
, et
.size
);
19123 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
19125 if (inst
.operands
[2].isscalar
)
19127 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
19128 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
19129 NEON_ENCODE (SCALAR
, inst
);
19130 neon_mul_mac (et
, et
.type
== NT_unsigned
);
19134 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19135 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
19136 NEON_ENCODE (INTEGER
, inst
);
19137 neon_mixed_length (et
, et
.size
);
19142 do_neon_mac_maybe_scalar_long (void)
19144 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
19147 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19148 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19151 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
19153 unsigned regno
= NEON_SCALAR_REG (scalar
);
19154 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
19158 if (regno
> 7 || elno
> 3)
19161 return ((regno
& 0x7)
19162 | ((elno
& 0x1) << 3)
19163 | (((elno
>> 1) & 0x1) << 5));
19167 if (regno
> 15 || elno
> 1)
19170 return (((regno
& 0x1) << 5)
19171 | ((regno
>> 1) & 0x7)
19172 | ((elno
& 0x1) << 3));
19176 first_error (_("scalar out of range for multiply instruction"));
19181 do_neon_fmac_maybe_scalar_long (int subtype
)
19183 enum neon_shape rs
;
19185 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19186 field (bits[21:20]) has different meaning. For scalar index variant, it's
19187 used to differentiate add and subtract, otherwise it's with fixed value
19191 if (inst
.cond
!= COND_ALWAYS
)
19192 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19193 "behaviour is UNPREDICTABLE"));
19195 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
19198 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19201 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19202 be a scalar index register. */
19203 if (inst
.operands
[2].isscalar
)
19205 high8
= 0xfe000000;
19208 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
19212 high8
= 0xfc000000;
19215 inst
.instruction
|= (0x1 << 23);
19216 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19219 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
19221 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19222 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19223 so we simply pass -1 as size. */
19224 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19225 neon_three_same (quad_p
, 0, size
);
19227 /* Undo neon_dp_fixup. Redo the high eight bits. */
19228 inst
.instruction
&= 0x00ffffff;
19229 inst
.instruction
|= high8
;
19231 #define LOW1(R) ((R) & 0x1)
19232 #define HI4(R) (((R) >> 1) & 0xf)
19233 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19234 whether the instruction is in Q form and whether Vm is a scalar indexed
19236 if (inst
.operands
[2].isscalar
)
19239 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19240 inst
.instruction
&= 0xffffffd0;
19241 inst
.instruction
|= rm
;
19245 /* Redo Rn as well. */
19246 inst
.instruction
&= 0xfff0ff7f;
19247 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19248 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19253 /* Redo Rn and Rm. */
19254 inst
.instruction
&= 0xfff0ff50;
19255 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19256 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19257 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19258 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19263 do_neon_vfmal (void)
19265 return do_neon_fmac_maybe_scalar_long (0);
19269 do_neon_vfmsl (void)
19271 return do_neon_fmac_maybe_scalar_long (1);
19275 do_neon_dyadic_wide (void)
19277 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19278 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19279 neon_mixed_length (et
, et
.size
);
19283 do_neon_dyadic_narrow (void)
19285 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19286 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19287 /* Operand sign is unimportant, and the U bit is part of the opcode,
19288 so force the operand type to integer. */
19289 et
.type
= NT_integer
;
19290 neon_mixed_length (et
, et
.size
/ 2);
19294 do_neon_mul_sat_scalar_long (void)
19296 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19300 do_neon_vmull (void)
19302 if (inst
.operands
[2].isscalar
)
19303 do_neon_mac_maybe_scalar_long ();
19306 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19307 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19309 if (et
.type
== NT_poly
)
19310 NEON_ENCODE (POLY
, inst
);
19312 NEON_ENCODE (INTEGER
, inst
);
19314 /* For polynomial encoding the U bit must be zero, and the size must
19315 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19316 obviously, as 0b10). */
19319 /* Check we're on the correct architecture. */
19320 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19322 _("Instruction form not available on this architecture.");
19327 neon_mixed_length (et
, et
.size
);
19334 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19335 struct neon_type_el et
= neon_check_type (3, rs
,
19336 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19337 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19339 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19340 _("shift out of range"));
19341 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19342 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19343 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19344 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19345 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19346 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19347 inst
.instruction
|= neon_quad (rs
) << 6;
19348 inst
.instruction
|= imm
<< 8;
19350 neon_dp_fixup (&inst
);
19356 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19359 enum neon_shape rs
;
19360 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19361 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19363 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19365 struct neon_type_el et
= neon_check_type (2, rs
,
19366 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19368 unsigned op
= (inst
.instruction
>> 7) & 3;
19369 /* N (width of reversed regions) is encoded as part of the bitmask. We
19370 extract it here to check the elements to be reversed are smaller.
19371 Otherwise we'd get a reserved instruction. */
19372 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19374 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19375 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19376 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19377 " operands makes instruction UNPREDICTABLE"));
19379 gas_assert (elsize
!= 0);
19380 constraint (et
.size
>= elsize
,
19381 _("elements must be smaller than reversal region"));
19382 neon_two_same (neon_quad (rs
), 1, et
.size
);
19388 if (inst
.operands
[1].isscalar
)
19390 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19392 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19393 struct neon_type_el et
= neon_check_type (2, rs
,
19394 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19395 unsigned sizebits
= et
.size
>> 3;
19396 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19397 int logsize
= neon_logbits (et
.size
);
19398 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19400 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19403 NEON_ENCODE (SCALAR
, inst
);
19404 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19405 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19406 inst
.instruction
|= LOW4 (dm
);
19407 inst
.instruction
|= HI1 (dm
) << 5;
19408 inst
.instruction
|= neon_quad (rs
) << 6;
19409 inst
.instruction
|= x
<< 17;
19410 inst
.instruction
|= sizebits
<< 16;
19412 neon_dp_fixup (&inst
);
19416 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19417 struct neon_type_el et
= neon_check_type (2, rs
,
19418 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19421 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
))
19425 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19428 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19430 if (inst
.operands
[1].reg
== REG_SP
)
19431 as_tsktsk (MVE_BAD_SP
);
19432 else if (inst
.operands
[1].reg
== REG_PC
)
19433 as_tsktsk (MVE_BAD_PC
);
19436 /* Duplicate ARM register to lanes of vector. */
19437 NEON_ENCODE (ARMREG
, inst
);
19440 case 8: inst
.instruction
|= 0x400000; break;
19441 case 16: inst
.instruction
|= 0x000020; break;
19442 case 32: inst
.instruction
|= 0x000000; break;
19445 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19446 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19447 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19448 inst
.instruction
|= neon_quad (rs
) << 21;
19449 /* The encoding for this instruction is identical for the ARM and Thumb
19450 variants, except for the condition field. */
19451 do_vfp_cond_or_thumb ();
19456 do_mve_mov (int toQ
)
19458 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19460 if (inst
.cond
> COND_ALWAYS
)
19461 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
19463 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
19472 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
19473 _("Index one must be [2,3] and index two must be two less than"
19475 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
19476 _("General purpose registers may not be the same"));
19477 constraint (inst
.operands
[Rt
].reg
== REG_SP
19478 || inst
.operands
[Rt2
].reg
== REG_SP
,
19480 constraint (inst
.operands
[Rt
].reg
== REG_PC
19481 || inst
.operands
[Rt2
].reg
== REG_PC
,
19484 inst
.instruction
= 0xec000f00;
19485 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
19486 inst
.instruction
|= !!toQ
<< 20;
19487 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
19488 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
19489 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
19490 inst
.instruction
|= inst
.operands
[Rt
].reg
;
19496 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19499 if (inst
.cond
> COND_ALWAYS
)
19500 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
19502 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
19504 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
19507 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19508 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
19509 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19510 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19511 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19516 /* VMOV has particularly many variations. It can be one of:
19517 0. VMOV<c><q> <Qd>, <Qm>
19518 1. VMOV<c><q> <Dd>, <Dm>
19519 (Register operations, which are VORR with Rm = Rn.)
19520 2. VMOV<c><q>.<dt> <Qd>, #<imm>
19521 3. VMOV<c><q>.<dt> <Dd>, #<imm>
19523 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
19524 (ARM register to scalar.)
19525 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
19526 (Two ARM registers to vector.)
19527 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
19528 (Scalar to ARM register.)
19529 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
19530 (Vector to two ARM registers.)
19531 8. VMOV.F32 <Sd>, <Sm>
19532 9. VMOV.F64 <Dd>, <Dm>
19533 (VFP register moves.)
19534 10. VMOV.F32 <Sd>, #imm
19535 11. VMOV.F64 <Dd>, #imm
19536 (VFP float immediate load.)
19537 12. VMOV <Rd>, <Sm>
19538 (VFP single to ARM reg.)
19539 13. VMOV <Sd>, <Rm>
19540 (ARM reg to VFP single.)
19541 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
19542 (Two ARM regs to two VFP singles.)
19543 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
19544 (Two VFP singles to two ARM regs.)
19545 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
19546 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
19547 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
19548 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
19550 These cases can be disambiguated using neon_select_shape, except cases 1/9
19551 and 3/11 which depend on the operand type too.
19553 All the encoded bits are hardcoded by this function.
19555 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
19556 Cases 5, 7 may be used with VFPv2 and above.
19558 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
19559 can specify a type where it doesn't make sense to, and is ignored). */
19564 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
19565 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
19566 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
19567 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
19569 struct neon_type_el et
;
19570 const char *ldconst
= 0;
19574 case NS_DD
: /* case 1/9. */
19575 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19576 /* It is not an error here if no type is given. */
19578 if (et
.type
== NT_float
&& et
.size
== 64)
19580 do_vfp_nsyn_opcode ("fcpyd");
19583 /* fall through. */
19585 case NS_QQ
: /* case 0/1. */
19587 if (!check_simd_pred_availability (FALSE
,
19588 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19590 /* The architecture manual I have doesn't explicitly state which
19591 value the U bit should have for register->register moves, but
19592 the equivalent VORR instruction has U = 0, so do that. */
19593 inst
.instruction
= 0x0200110;
19594 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19595 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19596 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19597 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19598 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19599 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19600 inst
.instruction
|= neon_quad (rs
) << 6;
19602 neon_dp_fixup (&inst
);
19606 case NS_DI
: /* case 3/11. */
19607 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19609 if (et
.type
== NT_float
&& et
.size
== 64)
19611 /* case 11 (fconstd). */
19612 ldconst
= "fconstd";
19613 goto encode_fconstd
;
19615 /* fall through. */
19617 case NS_QI
: /* case 2/3. */
19618 if (!check_simd_pred_availability (FALSE
,
19619 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19621 inst
.instruction
= 0x0800010;
19622 neon_move_immediate ();
19623 neon_dp_fixup (&inst
);
19626 case NS_SR
: /* case 4. */
19628 unsigned bcdebits
= 0;
19630 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
19631 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
19633 /* .<size> is optional here, defaulting to .32. */
19634 if (inst
.vectype
.elems
== 0
19635 && inst
.operands
[0].vectype
.type
== NT_invtype
19636 && inst
.operands
[1].vectype
.type
== NT_invtype
)
19638 inst
.vectype
.el
[0].type
= NT_untyped
;
19639 inst
.vectype
.el
[0].size
= 32;
19640 inst
.vectype
.elems
= 1;
19643 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19644 logsize
= neon_logbits (et
.size
);
19648 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19649 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
19654 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
19655 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19659 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19661 if (inst
.operands
[1].reg
== REG_SP
)
19662 as_tsktsk (MVE_BAD_SP
);
19663 else if (inst
.operands
[1].reg
== REG_PC
)
19664 as_tsktsk (MVE_BAD_PC
);
19666 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
19668 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
19669 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
19674 case 8: bcdebits
= 0x8; break;
19675 case 16: bcdebits
= 0x1; break;
19676 case 32: bcdebits
= 0x0; break;
19680 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
19682 inst
.instruction
= 0xe000b10;
19683 do_vfp_cond_or_thumb ();
19684 inst
.instruction
|= LOW4 (dn
) << 16;
19685 inst
.instruction
|= HI1 (dn
) << 7;
19686 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
19687 inst
.instruction
|= (bcdebits
& 3) << 5;
19688 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
19689 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
19693 case NS_DRR
: /* case 5 (fmdrr). */
19694 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19695 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19698 inst
.instruction
= 0xc400b10;
19699 do_vfp_cond_or_thumb ();
19700 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
19701 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
19702 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
19703 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
19706 case NS_RS
: /* case 6. */
19709 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19710 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
19711 unsigned abcdebits
= 0;
19713 /* .<dt> is optional here, defaulting to .32. */
19714 if (inst
.vectype
.elems
== 0
19715 && inst
.operands
[0].vectype
.type
== NT_invtype
19716 && inst
.operands
[1].vectype
.type
== NT_invtype
)
19718 inst
.vectype
.el
[0].type
= NT_untyped
;
19719 inst
.vectype
.el
[0].size
= 32;
19720 inst
.vectype
.elems
= 1;
19723 et
= neon_check_type (2, NS_NULL
,
19724 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
19725 logsize
= neon_logbits (et
.size
);
19729 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19730 && vfp_or_neon_is_neon (NEON_CHECK_CC
19731 | NEON_CHECK_ARCH
) == FAIL
)
19736 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
19737 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19741 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19743 if (inst
.operands
[0].reg
== REG_SP
)
19744 as_tsktsk (MVE_BAD_SP
);
19745 else if (inst
.operands
[0].reg
== REG_PC
)
19746 as_tsktsk (MVE_BAD_PC
);
19749 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
19751 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
19752 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
19756 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
19757 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
19758 case 32: abcdebits
= 0x00; break;
19762 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
19763 inst
.instruction
= 0xe100b10;
19764 do_vfp_cond_or_thumb ();
19765 inst
.instruction
|= LOW4 (dn
) << 16;
19766 inst
.instruction
|= HI1 (dn
) << 7;
19767 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
19768 inst
.instruction
|= (abcdebits
& 3) << 5;
19769 inst
.instruction
|= (abcdebits
>> 2) << 21;
19770 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
19774 case NS_RRD
: /* case 7 (fmrrd). */
19775 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19776 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19779 inst
.instruction
= 0xc500b10;
19780 do_vfp_cond_or_thumb ();
19781 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
19782 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
19783 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19784 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19787 case NS_FF
: /* case 8 (fcpys). */
19788 do_vfp_nsyn_opcode ("fcpys");
19792 case NS_FI
: /* case 10 (fconsts). */
19793 ldconst
= "fconsts";
19795 if (!inst
.operands
[1].immisfloat
)
19798 /* Immediate has to fit in 8 bits so float is enough. */
19799 float imm
= (float) inst
.operands
[1].imm
;
19800 memcpy (&new_imm
, &imm
, sizeof (float));
19801 /* But the assembly may have been written to provide an integer
19802 bit pattern that equates to a float, so check that the
19803 conversion has worked. */
19804 if (is_quarter_float (new_imm
))
19806 if (is_quarter_float (inst
.operands
[1].imm
))
19807 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
19809 inst
.operands
[1].imm
= new_imm
;
19810 inst
.operands
[1].immisfloat
= 1;
19814 if (is_quarter_float (inst
.operands
[1].imm
))
19816 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
19817 do_vfp_nsyn_opcode (ldconst
);
19819 /* ARMv8.2 fp16 vmov.f16 instruction. */
19821 do_scalar_fp16_v82_encode ();
19824 first_error (_("immediate out of range"));
19828 case NS_RF
: /* case 12 (fmrs). */
19829 do_vfp_nsyn_opcode ("fmrs");
19830 /* ARMv8.2 fp16 vmov.f16 instruction. */
19832 do_scalar_fp16_v82_encode ();
19836 case NS_FR
: /* case 13 (fmsr). */
19837 do_vfp_nsyn_opcode ("fmsr");
19838 /* ARMv8.2 fp16 vmov.f16 instruction. */
19840 do_scalar_fp16_v82_encode ();
19850 /* The encoders for the fmrrs and fmsrr instructions expect three operands
19851 (one of which is a list), but we have parsed four. Do some fiddling to
19852 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
19854 case NS_RRFF
: /* case 14 (fmrrs). */
19855 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19856 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19858 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
19859 _("VFP registers must be adjacent"));
19860 inst
.operands
[2].imm
= 2;
19861 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
19862 do_vfp_nsyn_opcode ("fmrrs");
19865 case NS_FFRR
: /* case 15 (fmsrr). */
19866 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19867 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19869 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
19870 _("VFP registers must be adjacent"));
19871 inst
.operands
[1] = inst
.operands
[2];
19872 inst
.operands
[2] = inst
.operands
[3];
19873 inst
.operands
[0].imm
= 2;
19874 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
19875 do_vfp_nsyn_opcode ("fmsrr");
19879 /* neon_select_shape has determined that the instruction
19880 shape is wrong and has already set the error message. */
19891 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
19892 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
19893 && !inst
.operands
[2].present
))
19895 inst
.instruction
= 0;
19898 set_pred_insn_type (INSIDE_IT_INSN
);
19903 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19906 if (inst
.cond
!= COND_ALWAYS
)
19907 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
19909 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
19910 | N_S16
| N_U16
| N_KEY
);
19912 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
19913 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19914 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
19915 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19916 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19917 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19922 do_neon_rshift_round_imm (void)
19924 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19927 enum neon_shape rs
;
19928 struct neon_type_el et
;
19930 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19932 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
19933 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
19937 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
19938 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
19940 int imm
= inst
.operands
[2].imm
;
19942 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
19945 inst
.operands
[2].present
= 0;
19950 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
19951 _("immediate out of range for shift"));
19952 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
19957 do_neon_movhf (void)
19959 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
19960 constraint (rs
!= NS_HH
, _("invalid suffix"));
19962 if (inst
.cond
!= COND_ALWAYS
)
19966 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
19967 " the behaviour is UNPREDICTABLE"));
19971 inst
.error
= BAD_COND
;
19976 do_vfp_sp_monadic ();
19979 inst
.instruction
|= 0xf0000000;
19983 do_neon_movl (void)
19985 struct neon_type_el et
= neon_check_type (2, NS_QD
,
19986 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19987 unsigned sizebits
= et
.size
>> 3;
19988 inst
.instruction
|= sizebits
<< 19;
19989 neon_two_same (0, et
.type
== NT_unsigned
, -1);
19995 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19996 struct neon_type_el et
= neon_check_type (2, rs
,
19997 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19998 NEON_ENCODE (INTEGER
, inst
);
19999 neon_two_same (neon_quad (rs
), 1, et
.size
);
20003 do_neon_zip_uzp (void)
20005 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20006 struct neon_type_el et
= neon_check_type (2, rs
,
20007 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20008 if (rs
== NS_DD
&& et
.size
== 32)
20010 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20011 inst
.instruction
= N_MNEM_vtrn
;
20015 neon_two_same (neon_quad (rs
), 1, et
.size
);
20019 do_neon_sat_abs_neg (void)
20021 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20024 enum neon_shape rs
;
20025 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20026 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20028 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20029 struct neon_type_el et
= neon_check_type (2, rs
,
20030 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20031 neon_two_same (neon_quad (rs
), 1, et
.size
);
20035 do_neon_pair_long (void)
20037 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20038 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
20039 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20040 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
20041 neon_two_same (neon_quad (rs
), 1, et
.size
);
20045 do_neon_recip_est (void)
20047 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20048 struct neon_type_el et
= neon_check_type (2, rs
,
20049 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
20050 inst
.instruction
|= (et
.type
== NT_float
) << 8;
20051 neon_two_same (neon_quad (rs
), 1, et
.size
);
20057 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20060 enum neon_shape rs
;
20061 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20062 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20064 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20066 struct neon_type_el et
= neon_check_type (2, rs
,
20067 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20068 neon_two_same (neon_quad (rs
), 1, et
.size
);
20074 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20077 enum neon_shape rs
;
20078 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20079 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20081 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20083 struct neon_type_el et
= neon_check_type (2, rs
,
20084 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
20085 neon_two_same (neon_quad (rs
), 1, et
.size
);
20091 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20092 struct neon_type_el et
= neon_check_type (2, rs
,
20093 N_EQK
| N_INT
, N_8
| N_KEY
);
20094 neon_two_same (neon_quad (rs
), 1, et
.size
);
20100 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20101 neon_two_same (neon_quad (rs
), 1, -1);
20105 do_neon_tbl_tbx (void)
20107 unsigned listlenbits
;
20108 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
20110 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
20112 first_error (_("bad list length for table lookup"));
20116 listlenbits
= inst
.operands
[1].imm
- 1;
20117 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20118 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20119 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20120 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20121 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20122 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20123 inst
.instruction
|= listlenbits
<< 8;
20125 neon_dp_fixup (&inst
);
20129 do_neon_ldm_stm (void)
20131 /* P, U and L bits are part of bitmask. */
20132 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
20133 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
20135 if (inst
.operands
[1].issingle
)
20137 do_vfp_nsyn_ldm_stm (is_dbmode
);
20141 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
20142 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20144 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20145 _("register list must contain at least 1 and at most 16 "
20148 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
20149 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
20150 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
20151 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
20153 inst
.instruction
|= offsetbits
;
20155 do_vfp_cond_or_thumb ();
20159 do_neon_ldr_str (void)
20161 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
20163 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20164 And is UNPREDICTABLE in thumb mode. */
20166 && inst
.operands
[1].reg
== REG_PC
20167 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
20170 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20171 else if (warn_on_deprecated
)
20172 as_tsktsk (_("Use of PC here is deprecated"));
20175 if (inst
.operands
[0].issingle
)
20178 do_vfp_nsyn_opcode ("flds");
20180 do_vfp_nsyn_opcode ("fsts");
20182 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20183 if (inst
.vectype
.el
[0].size
== 16)
20184 do_scalar_fp16_v82_encode ();
20189 do_vfp_nsyn_opcode ("fldd");
20191 do_vfp_nsyn_opcode ("fstd");
20196 do_t_vldr_vstr_sysreg (void)
20198 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
20199 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
20201 /* Use of PC is UNPREDICTABLE. */
20202 if (inst
.operands
[1].reg
== REG_PC
)
20203 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20205 if (inst
.operands
[1].immisreg
)
20206 inst
.error
= _("instruction does not accept register index");
20208 if (!inst
.operands
[1].isreg
)
20209 inst
.error
= _("instruction does not accept PC-relative addressing");
20211 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
20212 inst
.error
= _("immediate value out of range");
20214 inst
.instruction
= 0xec000f80;
20216 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20217 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20218 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20219 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20223 do_vldr_vstr (void)
20225 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
20227 /* VLDR/VSTR (System Register). */
20230 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20231 as_bad (_("Instruction not permitted on this architecture"));
20233 do_t_vldr_vstr_sysreg ();
20238 if (!mark_feature_used (&fpu_vfp_ext_v1xd
))
20239 as_bad (_("Instruction not permitted on this architecture"));
20240 do_neon_ldr_str ();
20244 /* "interleave" version also handles non-interleaving register VLD1/VST1
20248 do_neon_ld_st_interleave (void)
20250 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20251 N_8
| N_16
| N_32
| N_64
);
20252 unsigned alignbits
= 0;
20254 /* The bits in this table go:
20255 0: register stride of one (0) or two (1)
20256 1,2: register list length, minus one (1, 2, 3, 4).
20257 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20258 We use -1 for invalid entries. */
20259 const int typetable
[] =
20261 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20262 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20263 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20264 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20268 if (et
.type
== NT_invtype
)
20271 if (inst
.operands
[1].immisalign
)
20272 switch (inst
.operands
[1].imm
>> 8)
20274 case 64: alignbits
= 1; break;
20276 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20277 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20278 goto bad_alignment
;
20282 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20283 goto bad_alignment
;
20288 first_error (_("bad alignment"));
20292 inst
.instruction
|= alignbits
<< 4;
20293 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20295 /* Bits [4:6] of the immediate in a list specifier encode register stride
20296 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20297 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20298 up the right value for "type" in a table based on this value and the given
20299 list style, then stick it back. */
20300 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20301 | (((inst
.instruction
>> 8) & 3) << 3);
20303 typebits
= typetable
[idx
];
20305 constraint (typebits
== -1, _("bad list type for instruction"));
20306 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20309 inst
.instruction
&= ~0xf00;
20310 inst
.instruction
|= typebits
<< 8;
20313 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20314 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20315 otherwise. The variable arguments are a list of pairs of legal (size, align)
20316 values, terminated with -1. */
20319 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20322 int result
= FAIL
, thissize
, thisalign
;
20324 if (!inst
.operands
[1].immisalign
)
20330 va_start (ap
, do_alignment
);
20334 thissize
= va_arg (ap
, int);
20335 if (thissize
== -1)
20337 thisalign
= va_arg (ap
, int);
20339 if (size
== thissize
&& align
== thisalign
)
20342 while (result
!= SUCCESS
);
20346 if (result
== SUCCESS
)
20349 first_error (_("unsupported alignment for instruction"));
20355 do_neon_ld_st_lane (void)
20357 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20358 int align_good
, do_alignment
= 0;
20359 int logsize
= neon_logbits (et
.size
);
20360 int align
= inst
.operands
[1].imm
>> 8;
20361 int n
= (inst
.instruction
>> 8) & 3;
20362 int max_el
= 64 / et
.size
;
20364 if (et
.type
== NT_invtype
)
20367 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20368 _("bad list length"));
20369 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20370 _("scalar index out of range"));
20371 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20373 _("stride of 2 unavailable when element size is 8"));
20377 case 0: /* VLD1 / VST1. */
20378 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20380 if (align_good
== FAIL
)
20384 unsigned alignbits
= 0;
20387 case 16: alignbits
= 0x1; break;
20388 case 32: alignbits
= 0x3; break;
20391 inst
.instruction
|= alignbits
<< 4;
20395 case 1: /* VLD2 / VST2. */
20396 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20397 16, 32, 32, 64, -1);
20398 if (align_good
== FAIL
)
20401 inst
.instruction
|= 1 << 4;
20404 case 2: /* VLD3 / VST3. */
20405 constraint (inst
.operands
[1].immisalign
,
20406 _("can't use alignment with this instruction"));
20409 case 3: /* VLD4 / VST4. */
20410 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20411 16, 64, 32, 64, 32, 128, -1);
20412 if (align_good
== FAIL
)
20416 unsigned alignbits
= 0;
20419 case 8: alignbits
= 0x1; break;
20420 case 16: alignbits
= 0x1; break;
20421 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
20424 inst
.instruction
|= alignbits
<< 4;
20431 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
20432 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20433 inst
.instruction
|= 1 << (4 + logsize
);
20435 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
20436 inst
.instruction
|= logsize
<< 10;
20439 /* Encode single n-element structure to all lanes VLD<n> instructions. */
20442 do_neon_ld_dup (void)
20444 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20445 int align_good
, do_alignment
= 0;
20447 if (et
.type
== NT_invtype
)
20450 switch ((inst
.instruction
>> 8) & 3)
20452 case 0: /* VLD1. */
20453 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
20454 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20455 &do_alignment
, 16, 16, 32, 32, -1);
20456 if (align_good
== FAIL
)
20458 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
20461 case 2: inst
.instruction
|= 1 << 5; break;
20462 default: first_error (_("bad list length")); return;
20464 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20467 case 1: /* VLD2. */
20468 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20469 &do_alignment
, 8, 16, 16, 32, 32, 64,
20471 if (align_good
== FAIL
)
20473 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
20474 _("bad list length"));
20475 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20476 inst
.instruction
|= 1 << 5;
20477 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20480 case 2: /* VLD3. */
20481 constraint (inst
.operands
[1].immisalign
,
20482 _("can't use alignment with this instruction"));
20483 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
20484 _("bad list length"));
20485 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20486 inst
.instruction
|= 1 << 5;
20487 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20490 case 3: /* VLD4. */
20492 int align
= inst
.operands
[1].imm
>> 8;
20493 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20494 16, 64, 32, 64, 32, 128, -1);
20495 if (align_good
== FAIL
)
20497 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
20498 _("bad list length"));
20499 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20500 inst
.instruction
|= 1 << 5;
20501 if (et
.size
== 32 && align
== 128)
20502 inst
.instruction
|= 0x3 << 6;
20504 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20511 inst
.instruction
|= do_alignment
<< 4;
20514 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
20515 apart from bits [11:4]. */
20518 do_neon_ldx_stx (void)
20520 if (inst
.operands
[1].isreg
)
20521 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
20523 switch (NEON_LANE (inst
.operands
[0].imm
))
20525 case NEON_INTERLEAVE_LANES
:
20526 NEON_ENCODE (INTERLV
, inst
);
20527 do_neon_ld_st_interleave ();
20530 case NEON_ALL_LANES
:
20531 NEON_ENCODE (DUP
, inst
);
20532 if (inst
.instruction
== N_INV
)
20534 first_error ("only loads support such operands");
20541 NEON_ENCODE (LANE
, inst
);
20542 do_neon_ld_st_lane ();
20545 /* L bit comes from bit mask. */
20546 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20547 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20548 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20550 if (inst
.operands
[1].postind
)
20552 int postreg
= inst
.operands
[1].imm
& 0xf;
20553 constraint (!inst
.operands
[1].immisreg
,
20554 _("post-index must be a register"));
20555 constraint (postreg
== 0xd || postreg
== 0xf,
20556 _("bad register for post-index"));
20557 inst
.instruction
|= postreg
;
20561 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
20562 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
20563 || inst
.relocs
[0].exp
.X_add_number
!= 0,
20566 if (inst
.operands
[1].writeback
)
20568 inst
.instruction
|= 0xd;
20571 inst
.instruction
|= 0xf;
20575 inst
.instruction
|= 0xf9000000;
20577 inst
.instruction
|= 0xf4000000;
20582 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
20584 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20585 D register operands. */
20586 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20587 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20590 NEON_ENCODE (FPV8
, inst
);
20592 if (rs
== NS_FFF
|| rs
== NS_HHH
)
20594 do_vfp_sp_dyadic ();
20596 /* ARMv8.2 fp16 instruction. */
20598 do_scalar_fp16_v82_encode ();
20601 do_vfp_dp_rd_rn_rm ();
20604 inst
.instruction
|= 0x100;
20606 inst
.instruction
|= 0xf0000000;
20612 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20614 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
20615 first_error (_("invalid instruction shape"));
20621 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20622 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20624 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
20627 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20630 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
20634 do_vrint_1 (enum neon_cvt_mode mode
)
20636 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
20637 struct neon_type_el et
;
20642 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20643 D register operands. */
20644 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20645 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20648 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
20650 if (et
.type
!= NT_invtype
)
20652 /* VFP encodings. */
20653 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
20654 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
20655 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20657 NEON_ENCODE (FPV8
, inst
);
20658 if (rs
== NS_FF
|| rs
== NS_HH
)
20659 do_vfp_sp_monadic ();
20661 do_vfp_dp_rd_rm ();
20665 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
20666 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
20667 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
20668 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
20669 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
20670 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
20671 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
20675 inst
.instruction
|= (rs
== NS_DD
) << 8;
20676 do_vfp_cond_or_thumb ();
20678 /* ARMv8.2 fp16 vrint instruction. */
20680 do_scalar_fp16_v82_encode ();
20684 /* Neon encodings (or something broken...). */
20686 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
20688 if (et
.type
== NT_invtype
)
20691 if (!check_simd_pred_availability (TRUE
,
20692 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20695 NEON_ENCODE (FLOAT
, inst
);
20697 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20698 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20699 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20700 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20701 inst
.instruction
|= neon_quad (rs
) << 6;
20702 /* Mask off the original size bits and reencode them. */
20703 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
20704 | neon_logbits (et
.size
) << 18);
20708 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
20709 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
20710 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
20711 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
20712 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
20713 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
20714 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
20719 inst
.instruction
|= 0xfc000000;
20721 inst
.instruction
|= 0xf0000000;
20728 do_vrint_1 (neon_cvt_mode_x
);
20734 do_vrint_1 (neon_cvt_mode_z
);
20740 do_vrint_1 (neon_cvt_mode_r
);
20746 do_vrint_1 (neon_cvt_mode_a
);
20752 do_vrint_1 (neon_cvt_mode_n
);
20758 do_vrint_1 (neon_cvt_mode_p
);
20764 do_vrint_1 (neon_cvt_mode_m
);
20768 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
20770 unsigned regno
= NEON_SCALAR_REG (opnd
);
20771 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
20773 if (elsize
== 16 && elno
< 2 && regno
< 16)
20774 return regno
| (elno
<< 4);
20775 else if (elsize
== 32 && elno
== 0)
20778 first_error (_("scalar out of range"));
20785 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
20786 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
20787 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
20788 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
20789 _("expression too complex"));
20790 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
20791 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
20792 _("immediate out of range"));
20795 if (!check_simd_pred_availability (TRUE
,
20796 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
20799 if (inst
.operands
[2].isscalar
)
20801 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
20802 first_error (_("invalid instruction shape"));
20803 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
20804 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
20805 N_KEY
| N_F16
| N_F32
).size
;
20806 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
20808 inst
.instruction
= 0xfe000800;
20809 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20810 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20811 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20812 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20813 inst
.instruction
|= LOW4 (m
);
20814 inst
.instruction
|= HI1 (m
) << 5;
20815 inst
.instruction
|= neon_quad (rs
) << 6;
20816 inst
.instruction
|= rot
<< 20;
20817 inst
.instruction
|= (size
== 32) << 23;
20821 enum neon_shape rs
;
20822 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
20823 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
20825 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
20827 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
20828 N_KEY
| N_F16
| N_F32
).size
;
20829 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
20830 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
20831 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
20832 as_tsktsk (BAD_MVE_SRCDEST
);
20834 neon_three_same (neon_quad (rs
), 0, -1);
20835 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
20836 inst
.instruction
|= 0xfc200800;
20837 inst
.instruction
|= rot
<< 23;
20838 inst
.instruction
|= (size
== 32) << 20;
20845 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20846 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
20847 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
20848 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
20849 _("expression too complex"));
20851 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
20852 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
20853 enum neon_shape rs
;
20854 struct neon_type_el et
;
20855 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20857 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
20858 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
20862 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
20863 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
20865 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
20866 as_tsktsk (_("Warning: 32-bit element size and same first and third "
20867 "operand makes instruction UNPREDICTABLE"));
20870 if (et
.type
== NT_invtype
)
20873 if (!check_simd_pred_availability (et
.type
== NT_float
,
20874 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
20877 if (et
.type
== NT_float
)
20879 neon_three_same (neon_quad (rs
), 0, -1);
20880 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
20881 inst
.instruction
|= 0xfc800800;
20882 inst
.instruction
|= (rot
== 270) << 24;
20883 inst
.instruction
|= (et
.size
== 32) << 20;
20887 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
20888 inst
.instruction
= 0xfe000f00;
20889 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20890 inst
.instruction
|= neon_logbits (et
.size
) << 20;
20891 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20892 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20893 inst
.instruction
|= (rot
== 270) << 12;
20894 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20895 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20896 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20901 /* Dot Product instructions encoding support. */
20904 do_neon_dotproduct (int unsigned_p
)
20906 enum neon_shape rs
;
20907 unsigned scalar_oprd2
= 0;
20910 if (inst
.cond
!= COND_ALWAYS
)
20911 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
20912 "is UNPREDICTABLE"));
20914 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
20917 /* Dot Product instructions are in three-same D/Q register format or the third
20918 operand can be a scalar index register. */
20919 if (inst
.operands
[2].isscalar
)
20921 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
20922 high8
= 0xfe000000;
20923 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
20927 high8
= 0xfc000000;
20928 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
20932 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
20934 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
20936 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
20937 Product instruction, so we pass 0 as the "ubit" parameter. And the
20938 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
20939 neon_three_same (neon_quad (rs
), 0, 32);
20941 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
20942 different NEON three-same encoding. */
20943 inst
.instruction
&= 0x00ffffff;
20944 inst
.instruction
|= high8
;
20945 /* Encode 'U' bit which indicates signedness. */
20946 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
20947 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
20948 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
20949 the instruction encoding. */
20950 if (inst
.operands
[2].isscalar
)
20952 inst
.instruction
&= 0xffffffd0;
20953 inst
.instruction
|= LOW4 (scalar_oprd2
);
20954 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
20958 /* Dot Product instructions for signed integer. */
20961 do_neon_dotproduct_s (void)
20963 return do_neon_dotproduct (0);
20966 /* Dot Product instructions for unsigned integer. */
20969 do_neon_dotproduct_u (void)
20971 return do_neon_dotproduct (1);
20974 /* Crypto v1 instructions. */
20976 do_crypto_2op_1 (unsigned elttype
, int op
)
20978 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20980 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
20986 NEON_ENCODE (INTEGER
, inst
);
20987 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20988 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20989 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20990 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20992 inst
.instruction
|= op
<< 6;
20995 inst
.instruction
|= 0xfc000000;
20997 inst
.instruction
|= 0xf0000000;
21001 do_crypto_3op_1 (int u
, int op
)
21003 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21005 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
21006 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
21011 NEON_ENCODE (INTEGER
, inst
);
21012 neon_three_same (1, u
, 8 << op
);
21018 do_crypto_2op_1 (N_8
, 0);
21024 do_crypto_2op_1 (N_8
, 1);
21030 do_crypto_2op_1 (N_8
, 2);
21036 do_crypto_2op_1 (N_8
, 3);
21042 do_crypto_3op_1 (0, 0);
21048 do_crypto_3op_1 (0, 1);
21054 do_crypto_3op_1 (0, 2);
21060 do_crypto_3op_1 (0, 3);
21066 do_crypto_3op_1 (1, 0);
21072 do_crypto_3op_1 (1, 1);
21076 do_sha256su1 (void)
21078 do_crypto_3op_1 (1, 2);
21084 do_crypto_2op_1 (N_32
, -1);
21090 do_crypto_2op_1 (N_32
, 0);
21094 do_sha256su0 (void)
21096 do_crypto_2op_1 (N_32
, 1);
21100 do_crc32_1 (unsigned int poly
, unsigned int sz
)
21102 unsigned int Rd
= inst
.operands
[0].reg
;
21103 unsigned int Rn
= inst
.operands
[1].reg
;
21104 unsigned int Rm
= inst
.operands
[2].reg
;
21106 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21107 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
21108 inst
.instruction
|= LOW4 (Rn
) << 16;
21109 inst
.instruction
|= LOW4 (Rm
);
21110 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
21111 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
21113 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
21114 as_warn (UNPRED_REG ("r15"));
21156 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21158 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
21159 do_vfp_sp_dp_cvt ();
21160 do_vfp_cond_or_thumb ();
21164 /* Overall per-instruction processing. */
21166 /* We need to be able to fix up arbitrary expressions in some statements.
21167 This is so that we can handle symbols that are an arbitrary distance from
21168 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
21169 which returns part of an address in a form which will be valid for
21170 a data instruction. We do this by pushing the expression into a symbol
21171 in the expr_section, and creating a fix for that. */
21174 fix_new_arm (fragS
* frag
,
21188 /* Create an absolute valued symbol, so we have something to
21189 refer to in the object file. Unfortunately for us, gas's
21190 generic expression parsing will already have folded out
21191 any use of .set foo/.type foo %function that may have
21192 been used to set type information of the target location,
21193 that's being specified symbolically. We have to presume
21194 the user knows what they are doing. */
21198 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
21200 symbol
= symbol_find_or_make (name
);
21201 S_SET_SEGMENT (symbol
, absolute_section
);
21202 symbol_set_frag (symbol
, &zero_address_frag
);
21203 S_SET_VALUE (symbol
, exp
->X_add_number
);
21204 exp
->X_op
= O_symbol
;
21205 exp
->X_add_symbol
= symbol
;
21206 exp
->X_add_number
= 0;
21212 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
21213 (enum bfd_reloc_code_real
) reloc
);
21217 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
21218 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
21222 /* Mark whether the fix is to a THUMB instruction, or an ARM
21224 new_fix
->tc_fix_data
= thumb_mode
;
21227 /* Create a frg for an instruction requiring relaxation. */
21229 output_relax_insn (void)
21235 /* The size of the instruction is unknown, so tie the debug info to the
21236 start of the instruction. */
21237 dwarf2_emit_insn (0);
21239 switch (inst
.relocs
[0].exp
.X_op
)
21242 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
21243 offset
= inst
.relocs
[0].exp
.X_add_number
;
21247 offset
= inst
.relocs
[0].exp
.X_add_number
;
21250 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
21254 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
21255 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
21256 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
21259 /* Write a 32-bit thumb instruction to buf. */
21261 put_thumb32_insn (char * buf
, unsigned long insn
)
21263 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
21264 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
21268 output_inst (const char * str
)
21274 as_bad ("%s -- `%s'", inst
.error
, str
);
21279 output_relax_insn ();
21282 if (inst
.size
== 0)
21285 to
= frag_more (inst
.size
);
21286 /* PR 9814: Record the thumb mode into the current frag so that we know
21287 what type of NOP padding to use, if necessary. We override any previous
21288 setting so that if the mode has changed then the NOPS that we use will
21289 match the encoding of the last instruction in the frag. */
21290 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21292 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
21294 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
21295 put_thumb32_insn (to
, inst
.instruction
);
21297 else if (inst
.size
> INSN_SIZE
)
21299 gas_assert (inst
.size
== (2 * INSN_SIZE
));
21300 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
21301 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
21304 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
21307 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
21309 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
21310 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
21311 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
21312 inst
.relocs
[r
].type
);
21315 dwarf2_emit_insn (inst
.size
);
21319 output_it_inst (int cond
, int mask
, char * to
)
21321 unsigned long instruction
= 0xbf00;
21324 instruction
|= mask
;
21325 instruction
|= cond
<< 4;
21329 to
= frag_more (2);
21331 dwarf2_emit_insn (2);
21335 md_number_to_chars (to
, instruction
, 2);
21340 /* Tag values used in struct asm_opcode's tag field. */
21343 OT_unconditional
, /* Instruction cannot be conditionalized.
21344 The ARM condition field is still 0xE. */
21345 OT_unconditionalF
, /* Instruction cannot be conditionalized
21346 and carries 0xF in its ARM condition field. */
21347 OT_csuffix
, /* Instruction takes a conditional suffix. */
21348 OT_csuffixF
, /* Some forms of the instruction take a scalar
21349 conditional suffix, others place 0xF where the
21350 condition field would be, others take a vector
21351 conditional suffix. */
21352 OT_cinfix3
, /* Instruction takes a conditional infix,
21353 beginning at character index 3. (In
21354 unified mode, it becomes a suffix.) */
21355 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
21356 tsts, cmps, cmns, and teqs. */
21357 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
21358 character index 3, even in unified mode. Used for
21359 legacy instructions where suffix and infix forms
21360 may be ambiguous. */
21361 OT_csuf_or_in3
, /* Instruction takes either a conditional
21362 suffix or an infix at character index 3. */
21363 OT_odd_infix_unc
, /* This is the unconditional variant of an
21364 instruction that takes a conditional infix
21365 at an unusual position. In unified mode,
21366 this variant will accept a suffix. */
21367 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
21368 are the conditional variants of instructions that
21369 take conditional infixes in unusual positions.
21370 The infix appears at character index
21371 (tag - OT_odd_infix_0). These are not accepted
21372 in unified mode. */
21375 /* Subroutine of md_assemble, responsible for looking up the primary
21376 opcode from the mnemonic the user wrote. STR points to the
21377 beginning of the mnemonic.
21379 This is not simply a hash table lookup, because of conditional
21380 variants. Most instructions have conditional variants, which are
21381 expressed with a _conditional affix_ to the mnemonic. If we were
21382 to encode each conditional variant as a literal string in the opcode
21383 table, it would have approximately 20,000 entries.
21385 Most mnemonics take this affix as a suffix, and in unified syntax,
21386 'most' is upgraded to 'all'. However, in the divided syntax, some
21387 instructions take the affix as an infix, notably the s-variants of
21388 the arithmetic instructions. Of those instructions, all but six
21389 have the infix appear after the third character of the mnemonic.
21391 Accordingly, the algorithm for looking up primary opcodes given
21394 1. Look up the identifier in the opcode table.
21395 If we find a match, go to step U.
21397 2. Look up the last two characters of the identifier in the
21398 conditions table. If we find a match, look up the first N-2
21399 characters of the identifier in the opcode table. If we
21400 find a match, go to step CE.
21402 3. Look up the fourth and fifth characters of the identifier in
21403 the conditions table. If we find a match, extract those
21404 characters from the identifier, and look up the remaining
21405 characters in the opcode table. If we find a match, go
21410 U. Examine the tag field of the opcode structure, in case this is
21411 one of the six instructions with its conditional infix in an
21412 unusual place. If it is, the tag tells us where to find the
21413 infix; look it up in the conditions table and set inst.cond
21414 accordingly. Otherwise, this is an unconditional instruction.
21415 Again set inst.cond accordingly. Return the opcode structure.
21417 CE. Examine the tag field to make sure this is an instruction that
21418 should receive a conditional suffix. If it is not, fail.
21419 Otherwise, set inst.cond from the suffix we already looked up,
21420 and return the opcode structure.
21422 CM. Examine the tag field to make sure this is an instruction that
21423 should receive a conditional infix after the third character.
21424 If it is not, fail. Otherwise, undo the edits to the current
21425 line of input and proceed as for case CE. */
21427 static const struct asm_opcode
*
21428 opcode_lookup (char **str
)
21432 const struct asm_opcode
*opcode
;
21433 const struct asm_cond
*cond
;
21436 /* Scan up to the end of the mnemonic, which must end in white space,
21437 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
21438 for (base
= end
= *str
; *end
!= '\0'; end
++)
21439 if (*end
== ' ' || *end
== '.')
21445 /* Handle a possible width suffix and/or Neon type suffix. */
21450 /* The .w and .n suffixes are only valid if the unified syntax is in
21452 if (unified_syntax
&& end
[1] == 'w')
21454 else if (unified_syntax
&& end
[1] == 'n')
21459 inst
.vectype
.elems
= 0;
21461 *str
= end
+ offset
;
21463 if (end
[offset
] == '.')
21465 /* See if we have a Neon type suffix (possible in either unified or
21466 non-unified ARM syntax mode). */
21467 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
21470 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
21476 /* Look for unaffixed or special-case affixed mnemonic. */
21477 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21482 if (opcode
->tag
< OT_odd_infix_0
)
21484 inst
.cond
= COND_ALWAYS
;
21488 if (warn_on_deprecated
&& unified_syntax
)
21489 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21490 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
21491 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21494 inst
.cond
= cond
->value
;
21497 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21499 /* Cannot have a conditional suffix on a mnemonic of less than a character.
21501 if (end
- base
< 2)
21504 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
21505 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21507 /* If this opcode can not be vector predicated then don't accept it with a
21508 vector predication code. */
21509 if (opcode
&& !opcode
->mayBeVecPred
)
21512 if (!opcode
|| !cond
)
21514 /* Cannot have a conditional suffix on a mnemonic of less than two
21516 if (end
- base
< 3)
21519 /* Look for suffixed mnemonic. */
21521 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21522 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21526 if (opcode
&& cond
)
21529 switch (opcode
->tag
)
21531 case OT_cinfix3_legacy
:
21532 /* Ignore conditional suffixes matched on infix only mnemonics. */
21536 case OT_cinfix3_deprecated
:
21537 case OT_odd_infix_unc
:
21538 if (!unified_syntax
)
21540 /* Fall through. */
21544 case OT_csuf_or_in3
:
21545 inst
.cond
= cond
->value
;
21548 case OT_unconditional
:
21549 case OT_unconditionalF
:
21551 inst
.cond
= cond
->value
;
21554 /* Delayed diagnostic. */
21555 inst
.error
= BAD_COND
;
21556 inst
.cond
= COND_ALWAYS
;
21565 /* Cannot have a usual-position infix on a mnemonic of less than
21566 six characters (five would be a suffix). */
21567 if (end
- base
< 6)
21570 /* Look for infixed mnemonic in the usual position. */
21572 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21576 memcpy (save
, affix
, 2);
21577 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
21578 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21580 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
21581 memcpy (affix
, save
, 2);
21584 && (opcode
->tag
== OT_cinfix3
21585 || opcode
->tag
== OT_cinfix3_deprecated
21586 || opcode
->tag
== OT_csuf_or_in3
21587 || opcode
->tag
== OT_cinfix3_legacy
))
21590 if (warn_on_deprecated
&& unified_syntax
21591 && (opcode
->tag
== OT_cinfix3
21592 || opcode
->tag
== OT_cinfix3_deprecated
))
21593 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21595 inst
.cond
= cond
->value
;
21602 /* This function generates an initial IT instruction, leaving its block
21603 virtually open for the new instructions. Eventually,
21604 the mask will be updated by now_pred_add_mask () each time
21605 a new instruction needs to be included in the IT block.
21606 Finally, the block is closed with close_automatic_it_block ().
21607 The block closure can be requested either from md_assemble (),
21608 a tencode (), or due to a label hook. */
21611 new_automatic_it_block (int cond
)
21613 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
21614 now_pred
.mask
= 0x18;
21615 now_pred
.cc
= cond
;
21616 now_pred
.block_length
= 1;
21617 mapping_state (MAP_THUMB
);
21618 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
21619 now_pred
.warn_deprecated
= FALSE
;
21620 now_pred
.insn_cond
= TRUE
;
21623 /* Close an automatic IT block.
21624 See comments in new_automatic_it_block (). */
21627 close_automatic_it_block (void)
21629 now_pred
.mask
= 0x10;
21630 now_pred
.block_length
= 0;
21633 /* Update the mask of the current automatically-generated IT
21634 instruction. See comments in new_automatic_it_block (). */
21637 now_pred_add_mask (int cond
)
21639 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
21640 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
21641 | ((bitvalue) << (nbit)))
21642 const int resulting_bit
= (cond
& 1);
21644 now_pred
.mask
&= 0xf;
21645 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21647 (5 - now_pred
.block_length
));
21648 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21650 ((5 - now_pred
.block_length
) - 1));
21651 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
21654 #undef SET_BIT_VALUE
21657 /* The IT blocks handling machinery is accessed through the these functions:
21658 it_fsm_pre_encode () from md_assemble ()
21659 set_pred_insn_type () optional, from the tencode functions
21660 set_pred_insn_type_last () ditto
21661 in_pred_block () ditto
21662 it_fsm_post_encode () from md_assemble ()
21663 force_automatic_it_block_close () from label handling functions
21666 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
21667 initializing the IT insn type with a generic initial value depending
21668 on the inst.condition.
21669 2) During the tencode function, two things may happen:
21670 a) The tencode function overrides the IT insn type by
21671 calling either set_pred_insn_type (type) or
21672 set_pred_insn_type_last ().
21673 b) The tencode function queries the IT block state by
21674 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
21676 Both set_pred_insn_type and in_pred_block run the internal FSM state
21677 handling function (handle_pred_state), because: a) setting the IT insn
21678 type may incur in an invalid state (exiting the function),
21679 and b) querying the state requires the FSM to be updated.
21680 Specifically we want to avoid creating an IT block for conditional
21681 branches, so it_fsm_pre_encode is actually a guess and we can't
21682 determine whether an IT block is required until the tencode () routine
21683 has decided what type of instruction this actually it.
21684 Because of this, if set_pred_insn_type and in_pred_block have to be
21685 used, set_pred_insn_type has to be called first.
21687 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
21688 that determines the insn IT type depending on the inst.cond code.
21689 When a tencode () routine encodes an instruction that can be
21690 either outside an IT block, or, in the case of being inside, has to be
21691 the last one, set_pred_insn_type_last () will determine the proper
21692 IT instruction type based on the inst.cond code. Otherwise,
21693 set_pred_insn_type can be called for overriding that logic or
21694 for covering other cases.
21696 Calling handle_pred_state () may not transition the IT block state to
21697 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
21698 still queried. Instead, if the FSM determines that the state should
21699 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
21700 after the tencode () function: that's what it_fsm_post_encode () does.
21702 Since in_pred_block () calls the state handling function to get an
21703 updated state, an error may occur (due to invalid insns combination).
21704 In that case, inst.error is set.
21705 Therefore, inst.error has to be checked after the execution of
21706 the tencode () routine.
21708 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
21709 any pending state change (if any) that didn't take place in
21710 handle_pred_state () as explained above. */
21713 it_fsm_pre_encode (void)
21715 if (inst
.cond
!= COND_ALWAYS
)
21716 inst
.pred_insn_type
= INSIDE_IT_INSN
;
21718 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
21720 now_pred
.state_handled
= 0;
21723 /* IT state FSM handling function. */
21724 /* MVE instructions and non-MVE instructions are handled differently because of
21725 the introduction of VPT blocks.
21726 Specifications say that any non-MVE instruction inside a VPT block is
21727 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
21728 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
21729 few exceptions we have MVE_UNPREDICABLE_INSN.
21730 The error messages provided depending on the different combinations possible
21731 are described in the cases below:
21732 For 'most' MVE instructions:
21733 1) In an IT block, with an IT code: syntax error
21734 2) In an IT block, with a VPT code: error: must be in a VPT block
21735 3) In an IT block, with no code: warning: UNPREDICTABLE
21736 4) In a VPT block, with an IT code: syntax error
21737 5) In a VPT block, with a VPT code: OK!
21738 6) In a VPT block, with no code: error: missing code
21739 7) Outside a pred block, with an IT code: error: syntax error
21740 8) Outside a pred block, with a VPT code: error: should be in a VPT block
21741 9) Outside a pred block, with no code: OK!
21742 For non-MVE instructions:
21743 10) In an IT block, with an IT code: OK!
21744 11) In an IT block, with a VPT code: syntax error
21745 12) In an IT block, with no code: error: missing code
21746 13) In a VPT block, with an IT code: error: should be in an IT block
21747 14) In a VPT block, with a VPT code: syntax error
21748 15) In a VPT block, with no code: UNPREDICTABLE
21749 16) Outside a pred block, with an IT code: error: should be in an IT block
21750 17) Outside a pred block, with a VPT code: syntax error
21751 18) Outside a pred block, with no code: OK!
21756 handle_pred_state (void)
21758 now_pred
.state_handled
= 1;
21759 now_pred
.insn_cond
= FALSE
;
21761 switch (now_pred
.state
)
21763 case OUTSIDE_PRED_BLOCK
:
21764 switch (inst
.pred_insn_type
)
21766 case MVE_UNPREDICABLE_INSN
:
21767 case MVE_OUTSIDE_PRED_INSN
:
21768 if (inst
.cond
< COND_ALWAYS
)
21770 /* Case 7: Outside a pred block, with an IT code: error: syntax
21772 inst
.error
= BAD_SYNTAX
;
21775 /* Case 9: Outside a pred block, with no code: OK! */
21777 case OUTSIDE_PRED_INSN
:
21778 if (inst
.cond
> COND_ALWAYS
)
21780 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21782 inst
.error
= BAD_SYNTAX
;
21785 /* Case 18: Outside a pred block, with no code: OK! */
21788 case INSIDE_VPT_INSN
:
21789 /* Case 8: Outside a pred block, with a VPT code: error: should be in
21791 inst
.error
= BAD_OUT_VPT
;
21794 case INSIDE_IT_INSN
:
21795 case INSIDE_IT_LAST_INSN
:
21796 if (inst
.cond
< COND_ALWAYS
)
21798 /* Case 16: Outside a pred block, with an IT code: error: should
21799 be in an IT block. */
21800 if (thumb_mode
== 0)
21803 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
21804 as_tsktsk (_("Warning: conditional outside an IT block"\
21809 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
21810 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
21812 /* Automatically generate the IT instruction. */
21813 new_automatic_it_block (inst
.cond
);
21814 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
21815 close_automatic_it_block ();
21819 inst
.error
= BAD_OUT_IT
;
21825 else if (inst
.cond
> COND_ALWAYS
)
21827 /* Case 17: Outside a pred block, with a VPT code: syntax error.
21829 inst
.error
= BAD_SYNTAX
;
21834 case IF_INSIDE_IT_LAST_INSN
:
21835 case NEUTRAL_IT_INSN
:
21839 if (inst
.cond
!= COND_ALWAYS
)
21840 first_error (BAD_SYNTAX
);
21841 now_pred
.state
= MANUAL_PRED_BLOCK
;
21842 now_pred
.block_length
= 0;
21843 now_pred
.type
= VECTOR_PRED
;
21847 now_pred
.state
= MANUAL_PRED_BLOCK
;
21848 now_pred
.block_length
= 0;
21849 now_pred
.type
= SCALAR_PRED
;
21854 case AUTOMATIC_PRED_BLOCK
:
21855 /* Three things may happen now:
21856 a) We should increment current it block size;
21857 b) We should close current it block (closing insn or 4 insns);
21858 c) We should close current it block and start a new one (due
21859 to incompatible conditions or
21860 4 insns-length block reached). */
21862 switch (inst
.pred_insn_type
)
21864 case INSIDE_VPT_INSN
:
21866 case MVE_UNPREDICABLE_INSN
:
21867 case MVE_OUTSIDE_PRED_INSN
:
21869 case OUTSIDE_PRED_INSN
:
21870 /* The closure of the block shall happen immediately,
21871 so any in_pred_block () call reports the block as closed. */
21872 force_automatic_it_block_close ();
21875 case INSIDE_IT_INSN
:
21876 case INSIDE_IT_LAST_INSN
:
21877 case IF_INSIDE_IT_LAST_INSN
:
21878 now_pred
.block_length
++;
21880 if (now_pred
.block_length
> 4
21881 || !now_pred_compatible (inst
.cond
))
21883 force_automatic_it_block_close ();
21884 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
21885 new_automatic_it_block (inst
.cond
);
21889 now_pred
.insn_cond
= TRUE
;
21890 now_pred_add_mask (inst
.cond
);
21893 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
21894 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
21895 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
21896 close_automatic_it_block ();
21899 case NEUTRAL_IT_INSN
:
21900 now_pred
.block_length
++;
21901 now_pred
.insn_cond
= TRUE
;
21903 if (now_pred
.block_length
> 4)
21904 force_automatic_it_block_close ();
21906 now_pred_add_mask (now_pred
.cc
& 1);
21910 close_automatic_it_block ();
21911 now_pred
.state
= MANUAL_PRED_BLOCK
;
21916 case MANUAL_PRED_BLOCK
:
21919 if (now_pred
.type
== SCALAR_PRED
)
21921 /* Check conditional suffixes. */
21922 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
21923 now_pred
.mask
<<= 1;
21924 now_pred
.mask
&= 0x1f;
21925 is_last
= (now_pred
.mask
== 0x10);
21929 now_pred
.cc
^= (now_pred
.mask
>> 4);
21930 cond
= now_pred
.cc
+ 0xf;
21931 now_pred
.mask
<<= 1;
21932 now_pred
.mask
&= 0x1f;
21933 is_last
= now_pred
.mask
== 0x10;
21935 now_pred
.insn_cond
= TRUE
;
21937 switch (inst
.pred_insn_type
)
21939 case OUTSIDE_PRED_INSN
:
21940 if (now_pred
.type
== SCALAR_PRED
)
21942 if (inst
.cond
== COND_ALWAYS
)
21944 /* Case 12: In an IT block, with no code: error: missing
21946 inst
.error
= BAD_NOT_IT
;
21949 else if (inst
.cond
> COND_ALWAYS
)
21951 /* Case 11: In an IT block, with a VPT code: syntax error.
21953 inst
.error
= BAD_SYNTAX
;
21956 else if (thumb_mode
)
21958 /* This is for some special cases where a non-MVE
21959 instruction is not allowed in an IT block, such as cbz,
21960 but are put into one with a condition code.
21961 You could argue this should be a syntax error, but we
21962 gave the 'not allowed in IT block' diagnostic in the
21963 past so we will keep doing so. */
21964 inst
.error
= BAD_NOT_IT
;
21971 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
21972 as_tsktsk (MVE_NOT_VPT
);
21975 case MVE_OUTSIDE_PRED_INSN
:
21976 if (now_pred
.type
== SCALAR_PRED
)
21978 if (inst
.cond
== COND_ALWAYS
)
21980 /* Case 3: In an IT block, with no code: warning:
21982 as_tsktsk (MVE_NOT_IT
);
21985 else if (inst
.cond
< COND_ALWAYS
)
21987 /* Case 1: In an IT block, with an IT code: syntax error.
21989 inst
.error
= BAD_SYNTAX
;
21997 if (inst
.cond
< COND_ALWAYS
)
21999 /* Case 4: In a VPT block, with an IT code: syntax error.
22001 inst
.error
= BAD_SYNTAX
;
22004 else if (inst
.cond
== COND_ALWAYS
)
22006 /* Case 6: In a VPT block, with no code: error: missing
22008 inst
.error
= BAD_NOT_VPT
;
22016 case MVE_UNPREDICABLE_INSN
:
22017 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
22019 case INSIDE_IT_INSN
:
22020 if (inst
.cond
> COND_ALWAYS
)
22022 /* Case 11: In an IT block, with a VPT code: syntax error. */
22023 /* Case 14: In a VPT block, with a VPT code: syntax error. */
22024 inst
.error
= BAD_SYNTAX
;
22027 else if (now_pred
.type
== SCALAR_PRED
)
22029 /* Case 10: In an IT block, with an IT code: OK! */
22030 if (cond
!= inst
.cond
)
22032 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
22039 /* Case 13: In a VPT block, with an IT code: error: should be
22041 inst
.error
= BAD_OUT_IT
;
22046 case INSIDE_VPT_INSN
:
22047 if (now_pred
.type
== SCALAR_PRED
)
22049 /* Case 2: In an IT block, with a VPT code: error: must be in a
22051 inst
.error
= BAD_OUT_VPT
;
22054 /* Case 5: In a VPT block, with a VPT code: OK! */
22055 else if (cond
!= inst
.cond
)
22057 inst
.error
= BAD_VPT_COND
;
22061 case INSIDE_IT_LAST_INSN
:
22062 case IF_INSIDE_IT_LAST_INSN
:
22063 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
22065 /* Case 4: In a VPT block, with an IT code: syntax error. */
22066 /* Case 11: In an IT block, with a VPT code: syntax error. */
22067 inst
.error
= BAD_SYNTAX
;
22070 else if (cond
!= inst
.cond
)
22072 inst
.error
= BAD_IT_COND
;
22077 inst
.error
= BAD_BRANCH
;
22082 case NEUTRAL_IT_INSN
:
22083 /* The BKPT instruction is unconditional even in a IT or VPT
22088 if (now_pred
.type
== SCALAR_PRED
)
22090 inst
.error
= BAD_IT_IT
;
22093 /* fall through. */
22095 if (inst
.cond
== COND_ALWAYS
)
22097 /* Executing a VPT/VPST instruction inside an IT block or a
22098 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
22100 if (now_pred
.type
== SCALAR_PRED
)
22101 as_tsktsk (MVE_NOT_IT
);
22103 as_tsktsk (MVE_NOT_VPT
);
22108 /* VPT/VPST do not accept condition codes. */
22109 inst
.error
= BAD_SYNTAX
;
22120 struct depr_insn_mask
22122 unsigned long pattern
;
22123 unsigned long mask
;
22124 const char* description
;
22127 /* List of 16-bit instruction patterns deprecated in an IT block in
22129 static const struct depr_insn_mask depr_it_insns
[] = {
22130 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
22131 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
22132 { 0xa000, 0xb800, N_("ADR") },
22133 { 0x4800, 0xf800, N_("Literal loads") },
22134 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
22135 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
22136 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
22137 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
22138 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
22143 it_fsm_post_encode (void)
22147 if (!now_pred
.state_handled
)
22148 handle_pred_state ();
22150 if (now_pred
.insn_cond
22151 && !now_pred
.warn_deprecated
22152 && warn_on_deprecated
22153 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
22154 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
22156 if (inst
.instruction
>= 0x10000)
22158 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
22159 "performance deprecated in ARMv8-A and ARMv8-R"));
22160 now_pred
.warn_deprecated
= TRUE
;
22164 const struct depr_insn_mask
*p
= depr_it_insns
;
22166 while (p
->mask
!= 0)
22168 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
22170 as_tsktsk (_("IT blocks containing 16-bit Thumb "
22171 "instructions of the following class are "
22172 "performance deprecated in ARMv8-A and "
22173 "ARMv8-R: %s"), p
->description
);
22174 now_pred
.warn_deprecated
= TRUE
;
22182 if (now_pred
.block_length
> 1)
22184 as_tsktsk (_("IT blocks containing more than one conditional "
22185 "instruction are performance deprecated in ARMv8-A and "
22187 now_pred
.warn_deprecated
= TRUE
;
22191 is_last
= (now_pred
.mask
== 0x10);
22194 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22200 force_automatic_it_block_close (void)
22202 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
22204 close_automatic_it_block ();
22205 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22211 in_pred_block (void)
22213 if (!now_pred
.state_handled
)
22214 handle_pred_state ();
22216 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
22219 /* Whether OPCODE only has T32 encoding. Since this function is only used by
22220 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
22221 here, hence the "known" in the function name. */
22224 known_t32_only_insn (const struct asm_opcode
*opcode
)
22226 /* Original Thumb-1 wide instruction. */
22227 if (opcode
->tencode
== do_t_blx
22228 || opcode
->tencode
== do_t_branch23
22229 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
22230 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
22233 /* Wide-only instruction added to ARMv8-M Baseline. */
22234 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
22235 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
22236 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
22237 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
22243 /* Whether wide instruction variant can be used if available for a valid OPCODE
22247 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
22249 if (known_t32_only_insn (opcode
))
22252 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
22253 of variant T3 of B.W is checked in do_t_branch. */
22254 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22255 && opcode
->tencode
== do_t_branch
)
22258 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
22259 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22260 && opcode
->tencode
== do_t_mov_cmp
22261 /* Make sure CMP instruction is not affected. */
22262 && opcode
->aencode
== do_mov
)
22265 /* Wide instruction variants of all instructions with narrow *and* wide
22266 variants become available with ARMv6t2. Other opcodes are either
22267 narrow-only or wide-only and are thus available if OPCODE is valid. */
22268 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
22271 /* OPCODE with narrow only instruction variant or wide variant not
22277 md_assemble (char *str
)
22280 const struct asm_opcode
* opcode
;
22282 /* Align the previous label if needed. */
22283 if (last_label_seen
!= NULL
)
22285 symbol_set_frag (last_label_seen
, frag_now
);
22286 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
22287 S_SET_SEGMENT (last_label_seen
, now_seg
);
22290 memset (&inst
, '\0', sizeof (inst
));
22292 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22293 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
22295 opcode
= opcode_lookup (&p
);
22298 /* It wasn't an instruction, but it might be a register alias of
22299 the form alias .req reg, or a Neon .dn/.qn directive. */
22300 if (! create_register_alias (str
, p
)
22301 && ! create_neon_reg_alias (str
, p
))
22302 as_bad (_("bad instruction `%s'"), str
);
22307 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
22308 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
22310 /* The value which unconditional instructions should have in place of the
22311 condition field. */
22312 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
22316 arm_feature_set variant
;
22318 variant
= cpu_variant
;
22319 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
22320 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
22321 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
22322 /* Check that this instruction is supported for this CPU. */
22323 if (!opcode
->tvariant
22324 || (thumb_mode
== 1
22325 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
22327 if (opcode
->tencode
== do_t_swi
)
22328 as_bad (_("SVC is not permitted on this architecture"));
22330 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
22333 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
22334 && opcode
->tencode
!= do_t_branch
)
22336 as_bad (_("Thumb does not support conditional execution"));
22340 /* Two things are addressed here:
22341 1) Implicit require narrow instructions on Thumb-1.
22342 This avoids relaxation accidentally introducing Thumb-2
22344 2) Reject wide instructions in non Thumb-2 cores.
22346 Only instructions with narrow and wide variants need to be handled
22347 but selecting all non wide-only instructions is easier. */
22348 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
22349 && !t32_insn_ok (variant
, opcode
))
22351 if (inst
.size_req
== 0)
22353 else if (inst
.size_req
== 4)
22355 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
22356 as_bad (_("selected processor does not support 32bit wide "
22357 "variant of instruction `%s'"), str
);
22359 as_bad (_("selected processor does not support `%s' in "
22360 "Thumb-2 mode"), str
);
22365 inst
.instruction
= opcode
->tvalue
;
22367 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
22369 /* Prepare the pred_insn_type for those encodings that don't set
22371 it_fsm_pre_encode ();
22373 opcode
->tencode ();
22375 it_fsm_post_encode ();
22378 if (!(inst
.error
|| inst
.relax
))
22380 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
22381 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
22382 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
22384 as_bad (_("cannot honor width suffix -- `%s'"), str
);
22389 /* Something has gone badly wrong if we try to relax a fixed size
22391 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
22393 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22394 *opcode
->tvariant
);
22395 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
22396 set those bits when Thumb-2 32-bit instructions are seen. The impact
22397 of relaxable instructions will be considered later after we finish all
22399 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
22400 variant
= arm_arch_none
;
22402 variant
= cpu_variant
;
22403 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
22404 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22407 check_neon_suffixes
;
22411 mapping_state (MAP_THUMB
);
22414 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
22418 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
22419 is_bx
= (opcode
->aencode
== do_bx
);
22421 /* Check that this instruction is supported for this CPU. */
22422 if (!(is_bx
&& fix_v4bx
)
22423 && !(opcode
->avariant
&&
22424 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
22426 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
22431 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
22435 inst
.instruction
= opcode
->avalue
;
22436 if (opcode
->tag
== OT_unconditionalF
)
22437 inst
.instruction
|= 0xFU
<< 28;
22439 inst
.instruction
|= inst
.cond
<< 28;
22440 inst
.size
= INSN_SIZE
;
22441 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
22443 it_fsm_pre_encode ();
22444 opcode
->aencode ();
22445 it_fsm_post_encode ();
22447 /* Arm mode bx is marked as both v4T and v5 because it's still required
22448 on a hypothetical non-thumb v5 core. */
22450 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
22452 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
22453 *opcode
->avariant
);
22455 check_neon_suffixes
;
22459 mapping_state (MAP_ARM
);
22464 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
22472 check_pred_blocks_finished (void)
22477 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
22478 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
22479 == MANUAL_PRED_BLOCK
)
22481 if (now_pred
.type
== SCALAR_PRED
)
22482 as_warn (_("section '%s' finished with an open IT block."),
22485 as_warn (_("section '%s' finished with an open VPT/VPST block."),
22489 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
22491 if (now_pred
.type
== SCALAR_PRED
)
22492 as_warn (_("file finished with an open IT block."));
22494 as_warn (_("file finished with an open VPT/VPST block."));
22499 /* Various frobbings of labels and their addresses. */
22502 arm_start_line_hook (void)
22504 last_label_seen
= NULL
;
22508 arm_frob_label (symbolS
* sym
)
22510 last_label_seen
= sym
;
22512 ARM_SET_THUMB (sym
, thumb_mode
);
22514 #if defined OBJ_COFF || defined OBJ_ELF
22515 ARM_SET_INTERWORK (sym
, support_interwork
);
22518 force_automatic_it_block_close ();
22520 /* Note - do not allow local symbols (.Lxxx) to be labelled
22521 as Thumb functions. This is because these labels, whilst
22522 they exist inside Thumb code, are not the entry points for
22523 possible ARM->Thumb calls. Also, these labels can be used
22524 as part of a computed goto or switch statement. eg gcc
22525 can generate code that looks like this:
22527 ldr r2, [pc, .Laaa]
22537 The first instruction loads the address of the jump table.
22538 The second instruction converts a table index into a byte offset.
22539 The third instruction gets the jump address out of the table.
22540 The fourth instruction performs the jump.
22542 If the address stored at .Laaa is that of a symbol which has the
22543 Thumb_Func bit set, then the linker will arrange for this address
22544 to have the bottom bit set, which in turn would mean that the
22545 address computation performed by the third instruction would end
22546 up with the bottom bit set. Since the ARM is capable of unaligned
22547 word loads, the instruction would then load the incorrect address
22548 out of the jump table, and chaos would ensue. */
22549 if (label_is_thumb_function_name
22550 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
22551 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
22553 /* When the address of a Thumb function is taken the bottom
22554 bit of that address should be set. This will allow
22555 interworking between Arm and Thumb functions to work
22558 THUMB_SET_FUNC (sym
, 1);
22560 label_is_thumb_function_name
= FALSE
;
22563 dwarf2_emit_label (sym
);
22567 arm_data_in_code (void)
22569 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
22571 *input_line_pointer
= '/';
22572 input_line_pointer
+= 5;
22573 *input_line_pointer
= 0;
22581 arm_canonicalize_symbol_name (char * name
)
22585 if (thumb_mode
&& (len
= strlen (name
)) > 5
22586 && streq (name
+ len
- 5, "/data"))
22587 *(name
+ len
- 5) = 0;
22592 /* Table of all register names defined by default. The user can
22593 define additional names with .req. Note that all register names
22594 should appear in both upper and lowercase variants. Some registers
22595 also have mixed-case names. */
22597 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
22598 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
22599 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
22600 #define REGSET(p,t) \
22601 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
22602 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
22603 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
22604 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
22605 #define REGSETH(p,t) \
22606 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
22607 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
22608 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
22609 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
22610 #define REGSET2(p,t) \
22611 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
22612 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
22613 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
22614 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
22615 #define SPLRBANK(base,bank,t) \
22616 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
22617 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
22618 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
22619 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
22620 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
22621 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
22623 static const struct reg_entry reg_names
[] =
22625 /* ARM integer registers. */
22626 REGSET(r
, RN
), REGSET(R
, RN
),
22628 /* ATPCS synonyms. */
22629 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
22630 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
22631 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
22633 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
22634 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
22635 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
22637 /* Well-known aliases. */
22638 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
22639 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
22641 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
22642 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
22644 /* Defining the new Zero register from ARMv8.1-M. */
22648 /* Coprocessor numbers. */
22649 REGSET(p
, CP
), REGSET(P
, CP
),
22651 /* Coprocessor register numbers. The "cr" variants are for backward
22653 REGSET(c
, CN
), REGSET(C
, CN
),
22654 REGSET(cr
, CN
), REGSET(CR
, CN
),
22656 /* ARM banked registers. */
22657 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
22658 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
22659 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
22660 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
22661 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
22662 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
22663 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
22665 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
22666 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
22667 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
22668 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
22669 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
22670 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
22671 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
22672 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
22674 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
22675 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
22676 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
22677 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
22678 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
22679 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
22680 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
22681 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
22682 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
22684 /* FPA registers. */
22685 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
22686 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
22688 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
22689 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
22691 /* VFP SP registers. */
22692 REGSET(s
,VFS
), REGSET(S
,VFS
),
22693 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
22695 /* VFP DP Registers. */
22696 REGSET(d
,VFD
), REGSET(D
,VFD
),
22697 /* Extra Neon DP registers. */
22698 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
22700 /* Neon QP registers. */
22701 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
22703 /* VFP control registers. */
22704 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
22705 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
22706 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
22707 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
22708 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
22709 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
22710 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
22712 /* Maverick DSP coprocessor registers. */
22713 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
22714 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
22716 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
22717 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
22718 REGDEF(dspsc
,0,DSPSC
),
22720 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
22721 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
22722 REGDEF(DSPSC
,0,DSPSC
),
22724 /* iWMMXt data registers - p0, c0-15. */
22725 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
22727 /* iWMMXt control registers - p1, c0-3. */
22728 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
22729 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
22730 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
22731 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
22733 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
22734 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
22735 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
22736 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
22737 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
22739 /* XScale accumulator registers. */
22740 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
22746 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
22747 within psr_required_here. */
22748 static const struct asm_psr psrs
[] =
22750 /* Backward compatibility notation. Note that "all" is no longer
22751 truly all possible PSR bits. */
22752 {"all", PSR_c
| PSR_f
},
22756 /* Individual flags. */
22762 /* Combinations of flags. */
22763 {"fs", PSR_f
| PSR_s
},
22764 {"fx", PSR_f
| PSR_x
},
22765 {"fc", PSR_f
| PSR_c
},
22766 {"sf", PSR_s
| PSR_f
},
22767 {"sx", PSR_s
| PSR_x
},
22768 {"sc", PSR_s
| PSR_c
},
22769 {"xf", PSR_x
| PSR_f
},
22770 {"xs", PSR_x
| PSR_s
},
22771 {"xc", PSR_x
| PSR_c
},
22772 {"cf", PSR_c
| PSR_f
},
22773 {"cs", PSR_c
| PSR_s
},
22774 {"cx", PSR_c
| PSR_x
},
22775 {"fsx", PSR_f
| PSR_s
| PSR_x
},
22776 {"fsc", PSR_f
| PSR_s
| PSR_c
},
22777 {"fxs", PSR_f
| PSR_x
| PSR_s
},
22778 {"fxc", PSR_f
| PSR_x
| PSR_c
},
22779 {"fcs", PSR_f
| PSR_c
| PSR_s
},
22780 {"fcx", PSR_f
| PSR_c
| PSR_x
},
22781 {"sfx", PSR_s
| PSR_f
| PSR_x
},
22782 {"sfc", PSR_s
| PSR_f
| PSR_c
},
22783 {"sxf", PSR_s
| PSR_x
| PSR_f
},
22784 {"sxc", PSR_s
| PSR_x
| PSR_c
},
22785 {"scf", PSR_s
| PSR_c
| PSR_f
},
22786 {"scx", PSR_s
| PSR_c
| PSR_x
},
22787 {"xfs", PSR_x
| PSR_f
| PSR_s
},
22788 {"xfc", PSR_x
| PSR_f
| PSR_c
},
22789 {"xsf", PSR_x
| PSR_s
| PSR_f
},
22790 {"xsc", PSR_x
| PSR_s
| PSR_c
},
22791 {"xcf", PSR_x
| PSR_c
| PSR_f
},
22792 {"xcs", PSR_x
| PSR_c
| PSR_s
},
22793 {"cfs", PSR_c
| PSR_f
| PSR_s
},
22794 {"cfx", PSR_c
| PSR_f
| PSR_x
},
22795 {"csf", PSR_c
| PSR_s
| PSR_f
},
22796 {"csx", PSR_c
| PSR_s
| PSR_x
},
22797 {"cxf", PSR_c
| PSR_x
| PSR_f
},
22798 {"cxs", PSR_c
| PSR_x
| PSR_s
},
22799 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
22800 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
22801 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
22802 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
22803 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
22804 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
22805 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
22806 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
22807 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
22808 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
22809 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
22810 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
22811 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
22812 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
22813 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
22814 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
22815 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
22816 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
22817 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
22818 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
22819 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
22820 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
22821 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
22822 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
22825 /* Table of V7M psr names. */
22826 static const struct asm_psr v7m_psrs
[] =
22828 {"apsr", 0x0 }, {"APSR", 0x0 },
22829 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
22830 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
22831 {"psr", 0x3 }, {"PSR", 0x3 },
22832 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
22833 {"ipsr", 0x5 }, {"IPSR", 0x5 },
22834 {"epsr", 0x6 }, {"EPSR", 0x6 },
22835 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
22836 {"msp", 0x8 }, {"MSP", 0x8 },
22837 {"psp", 0x9 }, {"PSP", 0x9 },
22838 {"msplim", 0xa }, {"MSPLIM", 0xa },
22839 {"psplim", 0xb }, {"PSPLIM", 0xb },
22840 {"primask", 0x10}, {"PRIMASK", 0x10},
22841 {"basepri", 0x11}, {"BASEPRI", 0x11},
22842 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
22843 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
22844 {"control", 0x14}, {"CONTROL", 0x14},
22845 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
22846 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
22847 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
22848 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
22849 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
22850 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
22851 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
22852 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
22853 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
22856 /* Table of all shift-in-operand names. */
22857 static const struct asm_shift_name shift_names
[] =
22859 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
22860 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
22861 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
22862 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
22863 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
22864 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
22865 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
22868 /* Table of all explicit relocation names. */
22870 static struct reloc_entry reloc_names
[] =
22872 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
22873 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
22874 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
22875 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
22876 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
22877 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
22878 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
22879 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
22880 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
22881 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
22882 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
22883 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
22884 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
22885 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
22886 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
22887 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
22888 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
22889 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
22890 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
22891 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
22892 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
22893 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
22894 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
22895 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
22896 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
22897 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
22898 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
22902 /* Table of all conditional affixes. */
22903 static const struct asm_cond conds
[] =
22907 {"cs", 0x2}, {"hs", 0x2},
22908 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
22921 static const struct asm_cond vconds
[] =
22927 #define UL_BARRIER(L,U,CODE,FEAT) \
22928 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
22929 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
22931 static struct asm_barrier_opt barrier_opt_names
[] =
22933 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
22934 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
22935 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
22936 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
22937 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
22938 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
22939 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
22940 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
22941 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
22942 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
22943 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
22944 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
22945 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
22946 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
22947 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
22948 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
22953 /* Table of ARM-format instructions. */
22955 /* Macros for gluing together operand strings. N.B. In all cases
22956 other than OPS0, the trailing OP_stop comes from default
22957 zero-initialization of the unspecified elements of the array. */
22958 #define OPS0() { OP_stop, }
22959 #define OPS1(a) { OP_##a, }
22960 #define OPS2(a,b) { OP_##a,OP_##b, }
22961 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
22962 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
22963 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
22964 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
22966 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
22967 This is useful when mixing operands for ARM and THUMB, i.e. using the
22968 MIX_ARM_THUMB_OPERANDS macro.
22969 In order to use these macros, prefix the number of operands with _
22971 #define OPS_1(a) { a, }
22972 #define OPS_2(a,b) { a,b, }
22973 #define OPS_3(a,b,c) { a,b,c, }
22974 #define OPS_4(a,b,c,d) { a,b,c,d, }
22975 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
22976 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
22978 /* These macros abstract out the exact format of the mnemonic table and
22979 save some repeated characters. */
22981 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
22982 #define TxCE(mnem, op, top, nops, ops, ae, te) \
22983 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
22984 THUMB_VARIANT, do_##ae, do_##te, 0 }
22986 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
22987 a T_MNEM_xyz enumerator. */
22988 #define TCE(mnem, aop, top, nops, ops, ae, te) \
22989 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
22990 #define tCE(mnem, aop, top, nops, ops, ae, te) \
22991 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
22993 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
22994 infix after the third character. */
22995 #define TxC3(mnem, op, top, nops, ops, ae, te) \
22996 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
22997 THUMB_VARIANT, do_##ae, do_##te, 0 }
22998 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
22999 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
23000 THUMB_VARIANT, do_##ae, do_##te, 0 }
23001 #define TC3(mnem, aop, top, nops, ops, ae, te) \
23002 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
23003 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
23004 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
23005 #define tC3(mnem, aop, top, nops, ops, ae, te) \
23006 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23007 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
23008 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23010 /* Mnemonic that cannot be conditionalized. The ARM condition-code
23011 field is still 0xE. Many of the Thumb variants can be executed
23012 conditionally, so this is checked separately. */
23013 #define TUE(mnem, op, top, nops, ops, ae, te) \
23014 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23015 THUMB_VARIANT, do_##ae, do_##te, 0 }
23017 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
23018 Used by mnemonics that have very minimal differences in the encoding for
23019 ARM and Thumb variants and can be handled in a common function. */
23020 #define TUEc(mnem, op, top, nops, ops, en) \
23021 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23022 THUMB_VARIANT, do_##en, do_##en, 0 }
23024 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
23025 condition code field. */
23026 #define TUF(mnem, op, top, nops, ops, ae, te) \
23027 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
23028 THUMB_VARIANT, do_##ae, do_##te, 0 }
23030 /* ARM-only variants of all the above. */
23031 #define CE(mnem, op, nops, ops, ae) \
23032 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23034 #define C3(mnem, op, nops, ops, ae) \
23035 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23037 /* Thumb-only variants of TCE and TUE. */
23038 #define ToC(mnem, top, nops, ops, te) \
23039 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23042 #define ToU(mnem, top, nops, ops, te) \
23043 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
23046 /* T_MNEM_xyz enumerator variants of ToC. */
23047 #define toC(mnem, top, nops, ops, te) \
23048 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
23051 /* T_MNEM_xyz enumerator variants of ToU. */
23052 #define toU(mnem, top, nops, ops, te) \
23053 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
23056 /* Legacy mnemonics that always have conditional infix after the third
23058 #define CL(mnem, op, nops, ops, ae) \
23059 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23060 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23062 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
23063 #define cCE(mnem, op, nops, ops, ae) \
23064 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23066 /* mov instructions that are shared between coprocessor and MVE. */
23067 #define mcCE(mnem, op, nops, ops, ae) \
23068 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
23070 /* Legacy coprocessor instructions where conditional infix and conditional
23071 suffix are ambiguous. For consistency this includes all FPA instructions,
23072 not just the potentially ambiguous ones. */
23073 #define cCL(mnem, op, nops, ops, ae) \
23074 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23075 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23077 /* Coprocessor, takes either a suffix or a position-3 infix
23078 (for an FPA corner case). */
23079 #define C3E(mnem, op, nops, ops, ae) \
23080 { mnem, OPS##nops ops, OT_csuf_or_in3, \
23081 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23083 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
23084 { m1 #m2 m3, OPS##nops ops, \
23085 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
23086 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23088 #define CM(m1, m2, op, nops, ops, ae) \
23089 xCM_ (m1, , m2, op, nops, ops, ae), \
23090 xCM_ (m1, eq, m2, op, nops, ops, ae), \
23091 xCM_ (m1, ne, m2, op, nops, ops, ae), \
23092 xCM_ (m1, cs, m2, op, nops, ops, ae), \
23093 xCM_ (m1, hs, m2, op, nops, ops, ae), \
23094 xCM_ (m1, cc, m2, op, nops, ops, ae), \
23095 xCM_ (m1, ul, m2, op, nops, ops, ae), \
23096 xCM_ (m1, lo, m2, op, nops, ops, ae), \
23097 xCM_ (m1, mi, m2, op, nops, ops, ae), \
23098 xCM_ (m1, pl, m2, op, nops, ops, ae), \
23099 xCM_ (m1, vs, m2, op, nops, ops, ae), \
23100 xCM_ (m1, vc, m2, op, nops, ops, ae), \
23101 xCM_ (m1, hi, m2, op, nops, ops, ae), \
23102 xCM_ (m1, ls, m2, op, nops, ops, ae), \
23103 xCM_ (m1, ge, m2, op, nops, ops, ae), \
23104 xCM_ (m1, lt, m2, op, nops, ops, ae), \
23105 xCM_ (m1, gt, m2, op, nops, ops, ae), \
23106 xCM_ (m1, le, m2, op, nops, ops, ae), \
23107 xCM_ (m1, al, m2, op, nops, ops, ae)
23109 #define UE(mnem, op, nops, ops, ae) \
23110 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23112 #define UF(mnem, op, nops, ops, ae) \
23113 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23115 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
23116 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
23117 use the same encoding function for each. */
23118 #define NUF(mnem, op, nops, ops, enc) \
23119 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23120 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23122 /* Neon data processing, version which indirects through neon_enc_tab for
23123 the various overloaded versions of opcodes. */
23124 #define nUF(mnem, op, nops, ops, enc) \
23125 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23126 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23128 /* Neon insn with conditional suffix for the ARM version, non-overloaded
23130 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23131 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
23132 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23134 #define NCE(mnem, op, nops, ops, enc) \
23135 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23137 #define NCEF(mnem, op, nops, ops, enc) \
23138 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23140 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
23141 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23142 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
23143 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23145 #define nCE(mnem, op, nops, ops, enc) \
23146 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23148 #define nCEF(mnem, op, nops, ops, enc) \
23149 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23152 #define mCEF(mnem, op, nops, ops, enc) \
23153 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
23154 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23157 /* nCEF but for MVE predicated instructions. */
23158 #define mnCEF(mnem, op, nops, ops, enc) \
23159 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23161 /* nCE but for MVE predicated instructions. */
23162 #define mnCE(mnem, op, nops, ops, enc) \
23163 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23165 /* NUF but for potentially MVE predicated instructions. */
23166 #define MNUF(mnem, op, nops, ops, enc) \
23167 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23168 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23170 /* nUF but for potentially MVE predicated instructions. */
23171 #define mnUF(mnem, op, nops, ops, enc) \
23172 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23173 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23175 /* ToC but for potentially MVE predicated instructions. */
23176 #define mToC(mnem, top, nops, ops, te) \
23177 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23180 /* NCE but for MVE predicated instructions. */
23181 #define MNCE(mnem, op, nops, ops, enc) \
23182 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23184 /* NCEF but for MVE predicated instructions. */
23185 #define MNCEF(mnem, op, nops, ops, enc) \
23186 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23189 static const struct asm_opcode insns
[] =
23191 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
23192 #define THUMB_VARIANT & arm_ext_v4t
23193 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23194 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23195 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23196 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23197 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23198 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23199 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23200 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23201 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23202 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23203 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23204 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23205 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23206 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23207 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23208 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23210 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
23211 for setting PSR flag bits. They are obsolete in V6 and do not
23212 have Thumb equivalents. */
23213 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23214 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23215 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
23216 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23217 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23218 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
23219 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23220 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23221 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
23223 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
23224 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
23225 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23226 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23228 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
23229 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23230 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
23232 OP_ADDRGLDR
),ldst
, t_ldst
),
23233 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23235 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23236 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23237 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23238 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23239 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23240 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23242 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
23243 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
23246 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
23247 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
23248 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
23249 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
23251 /* Thumb-compatibility pseudo ops. */
23252 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23253 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23254 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23255 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23256 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23257 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23258 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23259 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23260 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
23261 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
23262 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
23263 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
23265 /* These may simplify to neg. */
23266 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23267 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23269 #undef THUMB_VARIANT
23270 #define THUMB_VARIANT & arm_ext_os
23272 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23273 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23275 #undef THUMB_VARIANT
23276 #define THUMB_VARIANT & arm_ext_v6
23278 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
23280 /* V1 instructions with no Thumb analogue prior to V6T2. */
23281 #undef THUMB_VARIANT
23282 #define THUMB_VARIANT & arm_ext_v6t2
23284 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23285 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23286 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
23288 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23289 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23290 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
23291 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23293 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23294 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23296 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23297 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23299 /* V1 instructions with no Thumb analogue at all. */
23300 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
23301 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
23303 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23304 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23305 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23306 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23307 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23308 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23309 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23310 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23313 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
23314 #undef THUMB_VARIANT
23315 #define THUMB_VARIANT & arm_ext_v4t
23317 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23318 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23320 #undef THUMB_VARIANT
23321 #define THUMB_VARIANT & arm_ext_v6t2
23323 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23324 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
23326 /* Generic coprocessor instructions. */
23327 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23328 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23329 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23330 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23331 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23332 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23333 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23336 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
23338 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23339 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23342 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
23343 #undef THUMB_VARIANT
23344 #define THUMB_VARIANT & arm_ext_msr
23346 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
23347 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
23350 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
23351 #undef THUMB_VARIANT
23352 #define THUMB_VARIANT & arm_ext_v6t2
23354 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23355 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23356 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23357 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23358 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23359 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23360 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23361 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23364 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
23365 #undef THUMB_VARIANT
23366 #define THUMB_VARIANT & arm_ext_v4t
23368 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23369 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23370 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23371 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23372 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23373 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23376 #define ARM_VARIANT & arm_ext_v4t_5
23378 /* ARM Architecture 4T. */
23379 /* Note: bx (and blx) are required on V5, even if the processor does
23380 not support Thumb. */
23381 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
23384 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
23385 #undef THUMB_VARIANT
23386 #define THUMB_VARIANT & arm_ext_v5t
23388 /* Note: blx has 2 variants; the .value coded here is for
23389 BLX(2). Only this variant has conditional execution. */
23390 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
23391 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
23393 #undef THUMB_VARIANT
23394 #define THUMB_VARIANT & arm_ext_v6t2
23396 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
23397 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23398 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23399 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23400 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23401 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23402 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23403 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23406 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
23407 #undef THUMB_VARIANT
23408 #define THUMB_VARIANT & arm_ext_v5exp
23410 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23411 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23412 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23413 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23415 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23416 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23418 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23419 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23420 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23421 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23423 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23424 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23425 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23426 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23428 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23429 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23431 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23432 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23433 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23434 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23437 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
23438 #undef THUMB_VARIANT
23439 #define THUMB_VARIANT & arm_ext_v6t2
23441 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
23442 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
23444 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
23445 ADDRGLDRS
), ldrd
, t_ldstd
),
23447 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23448 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23451 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
23453 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
23456 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
23457 #undef THUMB_VARIANT
23458 #define THUMB_VARIANT & arm_ext_v6
23460 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23461 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23462 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23463 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23464 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23465 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23466 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23467 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23468 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23469 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
23471 #undef THUMB_VARIANT
23472 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23474 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
23475 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23477 #undef THUMB_VARIANT
23478 #define THUMB_VARIANT & arm_ext_v6t2
23480 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23481 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23483 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
23484 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
23486 /* ARM V6 not included in V7M. */
23487 #undef THUMB_VARIANT
23488 #define THUMB_VARIANT & arm_ext_v6_notm
23489 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23490 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23491 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
23492 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
23493 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23494 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23495 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
23496 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23497 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
23498 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23499 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23500 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23501 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23502 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23503 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
23504 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
23505 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23506 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23507 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
23509 /* ARM V6 not included in V7M (eg. integer SIMD). */
23510 #undef THUMB_VARIANT
23511 #define THUMB_VARIANT & arm_ext_v6_dsp
23512 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
23513 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
23514 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23515 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23516 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23517 /* Old name for QASX. */
23518 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23519 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23520 /* Old name for QSAX. */
23521 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23522 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23523 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23524 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23525 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23526 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23527 /* Old name for SASX. */
23528 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23529 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23530 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23531 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23532 /* Old name for SHASX. */
23533 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23534 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23535 /* Old name for SHSAX. */
23536 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23537 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23538 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23539 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23540 /* Old name for SSAX. */
23541 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23542 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23543 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23544 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23545 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23546 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23547 /* Old name for UASX. */
23548 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23549 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23550 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23551 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23552 /* Old name for UHASX. */
23553 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23554 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23555 /* Old name for UHSAX. */
23556 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23557 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23558 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23559 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23560 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23561 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23562 /* Old name for UQASX. */
23563 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23564 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23565 /* Old name for UQSAX. */
23566 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23567 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23568 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23569 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23570 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23571 /* Old name for USAX. */
23572 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23573 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23574 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23575 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23576 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23577 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23578 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23579 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23580 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23581 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23582 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23583 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23584 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23585 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23586 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23587 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23588 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23589 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23590 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23591 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23592 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23593 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23594 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23595 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23596 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23597 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23598 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23599 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23600 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23601 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
23602 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
23603 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23604 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23605 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
23608 #define ARM_VARIANT & arm_ext_v6k_v6t2
23609 #undef THUMB_VARIANT
23610 #define THUMB_VARIANT & arm_ext_v6k_v6t2
23612 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
23613 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
23614 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
23615 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
23617 #undef THUMB_VARIANT
23618 #define THUMB_VARIANT & arm_ext_v6_notm
23619 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
23621 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
23622 RRnpcb
), strexd
, t_strexd
),
23624 #undef THUMB_VARIANT
23625 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23626 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
23628 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
23630 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23632 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23634 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
23637 #define ARM_VARIANT & arm_ext_sec
23638 #undef THUMB_VARIANT
23639 #define THUMB_VARIANT & arm_ext_sec
23641 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
23644 #define ARM_VARIANT & arm_ext_virt
23645 #undef THUMB_VARIANT
23646 #define THUMB_VARIANT & arm_ext_virt
23648 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
23649 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
23652 #define ARM_VARIANT & arm_ext_pan
23653 #undef THUMB_VARIANT
23654 #define THUMB_VARIANT & arm_ext_pan
23656 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
23659 #define ARM_VARIANT & arm_ext_v6t2
23660 #undef THUMB_VARIANT
23661 #define THUMB_VARIANT & arm_ext_v6t2
23663 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
23664 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
23665 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
23666 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
23668 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23669 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
23671 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23672 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23673 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23674 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23677 #define ARM_VARIANT & arm_ext_v3
23678 #undef THUMB_VARIANT
23679 #define THUMB_VARIANT & arm_ext_v6t2
23681 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
23682 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
23683 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
23686 #define ARM_VARIANT & arm_ext_v6t2
23687 #undef THUMB_VARIANT
23688 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23689 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
23690 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
23692 /* Thumb-only instructions. */
23694 #define ARM_VARIANT NULL
23695 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
23696 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
23698 /* ARM does not really have an IT instruction, so always allow it.
23699 The opcode is copied from Thumb in order to allow warnings in
23700 -mimplicit-it=[never | arm] modes. */
23702 #define ARM_VARIANT & arm_ext_v1
23703 #undef THUMB_VARIANT
23704 #define THUMB_VARIANT & arm_ext_v6t2
23706 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
23707 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
23708 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
23709 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
23710 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
23711 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
23712 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
23713 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
23714 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
23715 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
23716 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
23717 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
23718 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
23719 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
23720 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
23721 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
23722 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
23723 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
23725 /* Thumb2 only instructions. */
23727 #define ARM_VARIANT NULL
23729 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
23730 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
23731 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
23732 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
23733 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
23734 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
23736 /* Hardware division instructions. */
23738 #define ARM_VARIANT & arm_ext_adiv
23739 #undef THUMB_VARIANT
23740 #define THUMB_VARIANT & arm_ext_div
23742 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
23743 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
23745 /* ARM V6M/V7 instructions. */
23747 #define ARM_VARIANT & arm_ext_barrier
23748 #undef THUMB_VARIANT
23749 #define THUMB_VARIANT & arm_ext_barrier
23751 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
23752 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
23753 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
23755 /* ARM V7 instructions. */
23757 #define ARM_VARIANT & arm_ext_v7
23758 #undef THUMB_VARIANT
23759 #define THUMB_VARIANT & arm_ext_v7
23761 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
23762 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
23765 #define ARM_VARIANT & arm_ext_mp
23766 #undef THUMB_VARIANT
23767 #define THUMB_VARIANT & arm_ext_mp
23769 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
23771 /* AArchv8 instructions. */
23773 #define ARM_VARIANT & arm_ext_v8
23775 /* Instructions shared between armv8-a and armv8-m. */
23776 #undef THUMB_VARIANT
23777 #define THUMB_VARIANT & arm_ext_atomics
23779 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23780 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23781 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23782 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23783 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23784 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
23785 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23786 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
23787 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
23788 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23790 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23792 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
23794 #undef THUMB_VARIANT
23795 #define THUMB_VARIANT & arm_ext_v8
23797 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
23798 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
23800 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
23803 /* Defined in V8 but is in undefined encoding space for earlier
23804 architectures. However earlier architectures are required to treat
23805 this instuction as a semihosting trap as well. Hence while not explicitly
23806 defined as such, it is in fact correct to define the instruction for all
23808 #undef THUMB_VARIANT
23809 #define THUMB_VARIANT & arm_ext_v1
23811 #define ARM_VARIANT & arm_ext_v1
23812 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
23814 /* ARMv8 T32 only. */
23816 #define ARM_VARIANT NULL
23817 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
23818 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
23819 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
23821 /* FP for ARMv8. */
23823 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
23824 #undef THUMB_VARIANT
23825 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
23827 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23828 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23829 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23830 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
23831 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
23832 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
23833 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
23834 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
23835 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
23836 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
23837 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
23839 /* Crypto v1 extensions. */
23841 #define ARM_VARIANT & fpu_crypto_ext_armv8
23842 #undef THUMB_VARIANT
23843 #define THUMB_VARIANT & fpu_crypto_ext_armv8
23845 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
23846 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
23847 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
23848 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
23849 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
23850 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
23851 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
23852 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
23853 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
23854 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
23855 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
23856 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
23857 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
23858 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
23861 #define ARM_VARIANT & crc_ext_armv8
23862 #undef THUMB_VARIANT
23863 #define THUMB_VARIANT & crc_ext_armv8
23864 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
23865 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
23866 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
23867 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
23868 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
23869 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
23871 /* ARMv8.2 RAS extension. */
23873 #define ARM_VARIANT & arm_ext_ras
23874 #undef THUMB_VARIANT
23875 #define THUMB_VARIANT & arm_ext_ras
23876 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
23879 #define ARM_VARIANT & arm_ext_v8_3
23880 #undef THUMB_VARIANT
23881 #define THUMB_VARIANT & arm_ext_v8_3
23882 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
23885 #define ARM_VARIANT & fpu_neon_ext_dotprod
23886 #undef THUMB_VARIANT
23887 #define THUMB_VARIANT & fpu_neon_ext_dotprod
23888 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
23889 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
23892 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
23893 #undef THUMB_VARIANT
23894 #define THUMB_VARIANT NULL
23896 cCE("wfs", e200110
, 1, (RR
), rd
),
23897 cCE("rfs", e300110
, 1, (RR
), rd
),
23898 cCE("wfc", e400110
, 1, (RR
), rd
),
23899 cCE("rfc", e500110
, 1, (RR
), rd
),
23901 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23902 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23903 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23904 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23906 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23907 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23908 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23909 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
23911 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
23912 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
23913 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
23914 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
23915 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
23916 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
23917 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
23918 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
23919 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
23920 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
23921 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
23922 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
23924 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
23925 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
23926 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
23927 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
23928 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
23929 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
23930 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
23931 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
23932 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
23933 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
23934 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
23935 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
23937 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
23938 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
23939 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
23940 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
23941 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
23942 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
23943 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
23944 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
23945 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
23946 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
23947 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
23948 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
23950 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
23951 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
23952 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
23953 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
23954 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
23955 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
23956 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
23957 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
23958 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
23959 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
23960 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
23961 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
23963 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
23964 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
23965 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
23966 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
23967 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
23968 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
23969 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
23970 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
23971 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
23972 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
23973 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
23974 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
23976 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
23977 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
23978 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
23979 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
23980 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
23981 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
23982 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
23983 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
23984 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
23985 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
23986 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
23987 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
23989 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
23990 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
23991 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
23992 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
23993 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
23994 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
23995 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
23996 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
23997 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
23998 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
23999 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
24000 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
24002 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
24003 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
24004 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
24005 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
24006 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
24007 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
24008 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
24009 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
24010 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
24011 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
24012 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
24013 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
24015 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
24016 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
24017 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
24018 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
24019 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
24020 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
24021 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
24022 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
24023 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
24024 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
24025 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
24026 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
24028 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
24029 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
24030 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
24031 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
24032 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
24033 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
24034 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
24035 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
24036 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
24037 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
24038 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
24039 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
24041 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
24042 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
24043 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
24044 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
24045 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
24046 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
24047 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
24048 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
24049 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
24050 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
24051 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
24052 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
24054 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
24055 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
24056 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
24057 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
24058 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
24059 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
24060 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
24061 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
24062 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
24063 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
24064 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
24065 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
24067 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
24068 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
24069 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
24070 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
24071 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
24072 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
24073 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
24074 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
24075 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
24076 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
24077 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
24078 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
24080 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
24081 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
24082 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
24083 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
24084 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
24085 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
24086 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
24087 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
24088 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
24089 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
24090 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
24091 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
24093 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
24094 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
24095 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
24096 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
24097 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
24098 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
24099 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
24100 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
24101 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
24102 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
24103 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
24104 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
24106 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
24107 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
24108 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
24109 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
24110 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
24111 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
24112 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
24113 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
24114 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
24115 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
24116 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
24117 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
24119 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24120 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24121 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24122 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24123 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24124 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24125 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24126 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24127 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24128 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24129 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24130 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24132 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24133 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24134 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24135 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24136 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24137 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24138 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24139 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24140 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24141 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24142 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24143 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24145 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24146 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24147 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24148 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24149 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24150 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24151 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24152 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24153 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24154 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24155 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24156 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24158 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24159 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24160 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24161 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24162 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24163 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24164 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24165 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24166 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24167 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24168 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24169 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24171 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24172 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24173 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24174 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24175 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24176 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24177 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24178 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24179 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24180 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24181 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24182 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24184 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24185 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24186 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24187 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24188 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24189 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24190 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24191 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24192 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24193 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24194 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24195 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24197 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24198 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24199 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24200 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24201 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24202 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24203 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24204 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24205 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24206 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24207 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24208 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24210 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24211 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24212 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24213 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24214 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24215 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24216 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24217 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24218 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24219 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24220 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24221 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24223 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24224 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24225 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24226 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24227 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24228 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24229 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24230 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24231 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24232 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24233 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24234 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24236 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24237 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24238 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24239 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24240 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24241 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24242 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24243 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24244 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24245 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24246 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24247 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24249 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24250 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24251 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24252 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24253 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24254 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24255 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24256 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24257 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24258 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24259 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24260 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24262 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24263 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24264 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24265 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24266 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24267 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24268 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24269 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24270 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24271 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24272 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24273 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24275 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24276 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24277 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24278 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24279 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24280 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24281 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24282 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24283 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24284 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24285 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24286 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24288 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24289 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24290 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24291 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24293 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
24294 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
24295 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
24296 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
24297 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
24298 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
24299 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
24300 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
24301 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
24302 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
24303 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
24304 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
24306 /* The implementation of the FIX instruction is broken on some
24307 assemblers, in that it accepts a precision specifier as well as a
24308 rounding specifier, despite the fact that this is meaningless.
24309 To be more compatible, we accept it as well, though of course it
24310 does not set any bits. */
24311 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
24312 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
24313 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
24314 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
24315 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
24316 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
24317 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
24318 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
24319 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
24320 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
24321 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
24322 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
24323 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
24325 /* Instructions that were new with the real FPA, call them V2. */
24327 #define ARM_VARIANT & fpu_fpa_ext_v2
24329 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24330 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24331 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24332 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24333 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24334 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24337 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
24339 /* Moves and type conversions. */
24340 cCE("fmstat", ef1fa10
, 0, (), noargs
),
24341 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
24342 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
24343 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24344 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24345 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24346 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24347 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24348 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24349 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
24350 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
24352 /* Memory operations. */
24353 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24354 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24355 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24356 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24357 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24358 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24359 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24360 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24361 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24362 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24363 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24364 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24365 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24366 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24367 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24368 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24369 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24370 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24372 /* Monadic operations. */
24373 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24374 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24375 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24377 /* Dyadic operations. */
24378 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24379 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24380 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24381 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24382 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24383 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24384 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24385 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24386 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24389 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24390 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
24391 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24392 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
24394 /* Double precision load/store are still present on single precision
24395 implementations. */
24396 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24397 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24398 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24399 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24400 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24401 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24402 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24403 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24404 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24405 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24408 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
24410 /* Moves and type conversions. */
24411 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24412 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24413 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24414 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24415 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24416 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24417 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24418 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24419 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24420 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24421 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24422 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24424 /* Monadic operations. */
24425 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24426 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24427 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24429 /* Dyadic operations. */
24430 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24431 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24432 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24433 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24434 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24435 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24436 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24437 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24438 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24441 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24442 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
24443 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24444 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
24446 /* Instructions which may belong to either the Neon or VFP instruction sets.
24447 Individual encoder functions perform additional architecture checks. */
24449 #define ARM_VARIANT & fpu_vfp_ext_v1xd
24450 #undef THUMB_VARIANT
24451 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
24453 /* These mnemonics are unique to VFP. */
24454 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
24455 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
24456 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24457 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24458 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24459 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
24460 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
24461 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
24463 /* Mnemonics shared by Neon and VFP. */
24464 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
24466 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24467 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24468 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24469 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24470 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24471 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24473 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
24474 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
24475 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
24476 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
24479 /* NOTE: All VMOV encoding is special-cased! */
24480 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
24482 #undef THUMB_VARIANT
24483 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
24484 by different feature bits. Since we are setting the Thumb guard, we can
24485 require Thumb-1 which makes it a nop guard and set the right feature bit in
24486 do_vldr_vstr (). */
24487 #define THUMB_VARIANT & arm_ext_v4t
24488 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24489 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24492 #define ARM_VARIANT & arm_ext_fp16
24493 #undef THUMB_VARIANT
24494 #define THUMB_VARIANT & arm_ext_fp16
24495 /* New instructions added from v8.2, allowing the extraction and insertion of
24496 the upper 16 bits of a 32-bit vector register. */
24497 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
24498 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
24500 /* New backported fma/fms instructions optional in v8.2. */
24501 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
24502 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
24504 #undef THUMB_VARIANT
24505 #define THUMB_VARIANT & fpu_neon_ext_v1
24507 #define ARM_VARIANT & fpu_neon_ext_v1
24509 /* Data processing with three registers of the same length. */
24510 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
24511 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
24512 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
24513 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24514 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24515 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24516 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
24517 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24518 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24519 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24520 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24521 /* If not immediate, fall back to neon_dyadic_i64_su.
24522 shl should accept I8 I16 I32 I64,
24523 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
24524 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl
),
24525 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl
),
24526 /* Logic ops, types optional & ignored. */
24527 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24528 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24529 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24530 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24531 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
24532 /* Bitfield ops, untyped. */
24533 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24534 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24535 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24536 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24537 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24538 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24539 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
24540 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24541 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24542 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24543 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
24544 back to neon_dyadic_if_su. */
24545 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24546 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24547 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24548 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24549 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24550 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24551 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24552 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24553 /* Comparison. Type I8 I16 I32 F32. */
24554 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
24555 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
24556 /* As above, D registers only. */
24557 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24558 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24559 /* Int and float variants, signedness unimportant. */
24560 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24561 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24562 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
24563 /* Add/sub take types I8 I16 I32 I64 F32. */
24564 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24565 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24566 /* vtst takes sizes 8, 16, 32. */
24567 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
24568 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
24569 /* VMUL takes I8 I16 I32 F32 P8. */
24570 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
24571 /* VQD{R}MULH takes S16 S32. */
24572 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24573 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24574 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24575 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24576 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24577 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24578 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24579 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24580 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24581 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24582 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24583 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24584 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24585 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24586 /* ARM v8.1 extension. */
24587 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24588 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
24589 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24591 /* Two address, int/float. Types S8 S16 S32 F32. */
24592 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24593 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24595 /* Data processing with two registers and a shift amount. */
24596 /* Right shifts, and variants with rounding.
24597 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
24598 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24599 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24600 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24601 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24602 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24603 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24604 /* Shift and insert. Sizes accepted 8 16 32 64. */
24605 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
24606 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
24607 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
24608 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
24609 /* Right shift immediate, saturating & narrowing, with rounding variants.
24610 Types accepted S16 S32 S64 U16 U32 U64. */
24611 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24612 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24613 /* As above, unsigned. Types accepted S16 S32 S64. */
24614 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24615 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24616 /* Right shift narrowing. Types accepted I16 I32 I64. */
24617 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24618 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24619 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
24620 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
24621 /* CVT with optional immediate for fixed-point variant. */
24622 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
24624 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
24626 /* Data processing, three registers of different lengths. */
24627 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
24628 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
24629 /* If not scalar, fall back to neon_dyadic_long.
24630 Vector types as above, scalar types S16 S32 U16 U32. */
24631 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24632 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24633 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
24634 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24635 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24636 /* Dyadic, narrowing insns. Types I16 I32 I64. */
24637 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24638 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24639 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24640 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24641 /* Saturating doubling multiplies. Types S16 S32. */
24642 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24643 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24644 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24645 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
24646 S16 S32 U16 U32. */
24647 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
24649 /* Extract. Size 8. */
24650 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
24651 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
24653 /* Two registers, miscellaneous. */
24654 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
24655 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
24656 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
24657 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
24658 /* Vector replicate. Sizes 8 16 32. */
24659 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
24660 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
24661 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
24662 /* VMOVN. Types I16 I32 I64. */
24663 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
24664 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
24665 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
24666 /* VQMOVUN. Types S16 S32 S64. */
24667 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
24668 /* VZIP / VUZP. Sizes 8 16 32. */
24669 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
24670 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
24671 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
24672 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
24673 /* VQABS / VQNEG. Types S8 S16 S32. */
24674 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
24675 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
24676 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
24677 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
24678 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
24679 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
24680 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
24681 /* Reciprocal estimates. Types U32 F16 F32. */
24682 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
24683 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
24684 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
24685 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
24686 /* VCLS. Types S8 S16 S32. */
24687 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
24688 /* VCLZ. Types I8 I16 I32. */
24689 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
24690 /* VCNT. Size 8. */
24691 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
24692 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
24693 /* Two address, untyped. */
24694 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
24695 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
24696 /* VTRN. Sizes 8 16 32. */
24697 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
24698 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
24700 /* Table lookup. Size 8. */
24701 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
24702 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
24704 #undef THUMB_VARIANT
24705 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
24707 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
24709 /* Neon element/structure load/store. */
24710 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24711 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24712 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24713 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24714 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24715 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24716 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24717 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24719 #undef THUMB_VARIANT
24720 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
24722 #define ARM_VARIANT & fpu_vfp_ext_v3xd
24723 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
24724 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24725 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24726 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24727 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24728 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24729 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24730 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24731 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24733 #undef THUMB_VARIANT
24734 #define THUMB_VARIANT & fpu_vfp_ext_v3
24736 #define ARM_VARIANT & fpu_vfp_ext_v3
24738 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
24739 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24740 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24741 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24742 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24743 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24744 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24745 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24746 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24749 #define ARM_VARIANT & fpu_vfp_ext_fma
24750 #undef THUMB_VARIANT
24751 #define THUMB_VARIANT & fpu_vfp_ext_fma
24752 /* Mnemonics shared by Neon, VFP and MVE. These are included in the
24753 VFP FMA variant; NEON and VFP FMA always includes the NEON
24754 FMA instructions. */
24755 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
24756 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
24758 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
24759 the v form should always be used. */
24760 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24761 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24762 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24763 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24764 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24765 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24767 #undef THUMB_VARIANT
24769 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
24771 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24772 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24773 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24774 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24775 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24776 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
24777 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
24778 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
24781 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
24783 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
24784 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
24785 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
24786 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
24787 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
24788 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
24789 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
24790 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
24791 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
24792 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24793 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24794 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24795 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24796 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24797 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
24798 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24799 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24800 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
24801 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
24802 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
24803 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24804 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24805 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24806 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24807 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24808 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
24809 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
24810 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
24811 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
24812 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
24813 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
24814 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
24815 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
24816 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
24817 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24818 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24819 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24820 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24821 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24822 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24823 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24824 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24825 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24826 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24827 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24828 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24829 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
24830 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24831 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24832 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24833 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24834 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24835 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24836 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24837 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24838 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24839 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24840 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24841 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24842 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24843 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24844 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24845 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24846 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24847 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24848 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24849 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24850 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24851 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
24852 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
24853 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24854 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24855 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24856 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24857 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24858 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24859 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24860 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24861 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24862 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24863 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24864 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24865 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24866 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24867 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24868 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24869 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24870 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24871 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
24872 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24873 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24874 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24875 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24876 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24877 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24878 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24879 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24880 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24881 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24882 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24883 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24884 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24885 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24886 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24887 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24888 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24889 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24890 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24891 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24892 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24893 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
24894 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24895 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24896 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24897 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24898 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24899 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24900 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24901 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24902 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24903 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24904 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24905 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24906 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24907 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24908 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24909 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24910 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
24911 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
24912 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24913 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
24914 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
24915 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
24916 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24917 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24918 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24919 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24920 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24921 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24922 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24923 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24924 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24925 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24926 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24927 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24928 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24929 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24930 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
24931 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24932 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24933 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24934 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24935 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24936 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24937 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24938 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24939 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
24940 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24941 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24942 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24943 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24944 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
24947 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
24949 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
24950 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
24951 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
24952 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24953 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24954 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
24955 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24956 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24957 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24958 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24959 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24960 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24961 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24962 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24963 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24964 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24965 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24966 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24967 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24968 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24969 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
24970 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24971 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24972 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24973 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24974 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24975 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24976 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24977 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24978 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24979 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24980 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24981 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24982 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24983 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24984 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24985 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24986 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24987 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24988 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24989 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24990 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24991 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24992 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24993 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24994 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24995 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24996 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24997 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24998 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
24999 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25000 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25001 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25002 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25003 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25004 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25005 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25008 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
25010 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25011 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25012 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25013 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25014 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25015 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25016 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25017 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25018 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
25019 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
25020 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
25021 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
25022 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
25023 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
25024 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
25025 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
25026 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
25027 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
25028 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
25029 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
25030 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
25031 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
25032 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
25033 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
25034 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
25035 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
25036 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
25037 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
25038 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
25039 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
25040 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
25041 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
25042 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
25043 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
25044 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
25045 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
25046 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
25047 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
25048 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
25049 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
25050 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
25051 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
25052 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
25053 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
25054 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
25055 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
25056 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
25057 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
25058 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
25059 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
25060 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
25061 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
25062 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
25063 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
25064 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25065 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25066 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25067 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25068 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25069 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25070 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
25071 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
25072 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
25073 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
25074 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25075 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25076 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25077 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25078 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25079 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25080 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25081 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25082 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25083 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25084 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25085 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25087 /* ARMv8.5-A instructions. */
25089 #define ARM_VARIANT & arm_ext_sb
25090 #undef THUMB_VARIANT
25091 #define THUMB_VARIANT & arm_ext_sb
25092 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
25095 #define ARM_VARIANT & arm_ext_predres
25096 #undef THUMB_VARIANT
25097 #define THUMB_VARIANT & arm_ext_predres
25098 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
25099 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
25100 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
25102 /* ARMv8-M instructions. */
25104 #define ARM_VARIANT NULL
25105 #undef THUMB_VARIANT
25106 #define THUMB_VARIANT & arm_ext_v8m
25107 ToU("sg", e97fe97f
, 0, (), noargs
),
25108 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
25109 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
25110 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
25111 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
25112 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
25113 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
25115 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
25116 instructions behave as nop if no VFP is present. */
25117 #undef THUMB_VARIANT
25118 #define THUMB_VARIANT & arm_ext_v8m_main
25119 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
25120 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
25122 /* Armv8.1-M Mainline instructions. */
25123 #undef THUMB_VARIANT
25124 #define THUMB_VARIANT & arm_ext_v8_1m_main
25125 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
25126 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
25127 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25128 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
25129 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25131 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
25132 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
25133 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
25135 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
25136 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
25138 #undef THUMB_VARIANT
25139 #define THUMB_VARIANT & mve_ext
25141 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25142 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25143 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25144 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25145 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25146 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25147 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25148 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25149 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25150 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25151 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25152 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25153 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25154 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25155 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25157 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
25158 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
25159 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
25160 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
25161 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
25162 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
25163 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
25164 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
25165 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
25166 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
25167 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
25168 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
25169 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
25170 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
25171 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
25173 /* MVE and MVE FP only. */
25174 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
25175 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25176 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25177 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25178 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25179 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
25180 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
25181 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25182 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25183 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25184 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25185 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25186 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25187 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25188 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25189 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25190 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25192 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25193 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25194 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25195 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25196 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25197 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25198 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25199 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25200 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25201 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25202 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25203 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25204 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25205 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25206 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25207 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25208 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25209 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25210 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25211 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25213 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
25214 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
25215 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
25216 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25217 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25218 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
25219 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
25220 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25221 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25222 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25223 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25224 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25225 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25226 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
25227 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
25228 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
25229 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
25231 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25232 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25233 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25234 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25235 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25236 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25237 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25238 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25239 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25240 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25241 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25242 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25243 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25244 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25245 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25246 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25247 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25248 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25249 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25250 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25252 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
25253 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25254 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25255 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
25256 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
25258 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25259 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25260 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25261 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25262 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25263 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25264 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25265 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25266 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25267 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25268 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25269 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25270 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25271 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25272 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25273 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25274 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25276 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25277 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25278 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25279 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25280 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25281 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25282 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25283 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25284 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25285 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25286 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25287 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25289 mToC("vshlc", eea00fc0
, 3, (RMQ
, RR
, I32z
), mve_vshlc
),
25290 mToC("vshllt", ee201e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25291 mToC("vshllb", ee200e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25293 toU("dlstp", _dlstp
, 2, (LR
, RR
), t_loloop
),
25294 toU("wlstp", _wlstp
, 3, (LR
, RR
, EXP
), t_loloop
),
25295 toU("letp", _letp
, 2, (LR
, EXP
), t_loloop
),
25296 toU("lctp", _lctp
, 0, (), t_loloop
),
25298 #undef THUMB_VARIANT
25299 #define THUMB_VARIANT & mve_fp_ext
25300 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
25301 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
25302 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25303 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25304 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25305 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25306 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25307 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25310 #define ARM_VARIANT & fpu_vfp_ext_v1
25311 #undef THUMB_VARIANT
25312 #define THUMB_VARIANT & arm_ext_v6t2
25313 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
25314 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
25316 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25319 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25321 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
25322 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
25323 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
25324 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25326 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
25327 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25328 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25330 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25331 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25333 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
25334 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
25336 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25337 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25340 #define ARM_VARIANT & fpu_vfp_ext_v2
25342 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
25343 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
25344 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
25345 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
25348 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
25349 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
25350 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
25351 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
25352 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
25353 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25354 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25357 #define ARM_VARIANT & fpu_neon_ext_v1
25358 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25359 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
25360 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25361 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25362 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25363 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25364 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25365 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25366 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
25367 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
25368 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
25369 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
25370 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25371 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
25372 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25373 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25374 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25375 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25376 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25377 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
25378 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25379 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25380 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
25381 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25382 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25383 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25384 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25385 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25386 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25387 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
25388 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
25389 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25390 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25391 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25392 mnUF(vshl
, _vshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_shl
),
25393 mnUF(vqshl
, _vqshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_qshl
),
25394 MNUF(vqshlu
, 1800610, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_qshlu_imm
),
25397 #define ARM_VARIANT & arm_ext_v8_3
25398 #undef THUMB_VARIANT
25399 #define THUMB_VARIANT & arm_ext_v6t2_v8m
25400 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
25401 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
25404 #undef THUMB_VARIANT
25436 /* MD interface: bits in the object file. */
25438 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
25439 for use in the a.out file, and stores them in the array pointed to by buf.
25440 This knows about the endian-ness of the target machine and does
25441 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
25442 2 (short) and 4 (long) Floating numbers are put out as a series of
25443 LITTLENUMS (shorts, here at least). */
25446 md_number_to_chars (char * buf
, valueT val
, int n
)
25448 if (target_big_endian
)
25449 number_to_chars_bigendian (buf
, val
, n
);
25451 number_to_chars_littleendian (buf
, val
, n
);
25455 md_chars_to_number (char * buf
, int n
)
25458 unsigned char * where
= (unsigned char *) buf
;
25460 if (target_big_endian
)
25465 result
|= (*where
++ & 255);
25473 result
|= (where
[n
] & 255);
25480 /* MD interface: Sections. */
25482 /* Calculate the maximum variable size (i.e., excluding fr_fix)
25483 that an rs_machine_dependent frag may reach. */
25486 arm_frag_max_var (fragS
*fragp
)
25488 /* We only use rs_machine_dependent for variable-size Thumb instructions,
25489 which are either THUMB_SIZE (2) or INSN_SIZE (4).
25491 Note that we generate relaxable instructions even for cases that don't
25492 really need it, like an immediate that's a trivial constant. So we're
25493 overestimating the instruction size for some of those cases. Rather
25494 than putting more intelligence here, it would probably be better to
25495 avoid generating a relaxation frag in the first place when it can be
25496 determined up front that a short instruction will suffice. */
25498 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
25502 /* Estimate the size of a frag before relaxing. Assume everything fits in
25506 md_estimate_size_before_relax (fragS
* fragp
,
25507 segT segtype ATTRIBUTE_UNUSED
)
25513 /* Convert a machine dependent frag. */
25516 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
25518 unsigned long insn
;
25519 unsigned long old_op
;
25527 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
25529 old_op
= bfd_get_16(abfd
, buf
);
25530 if (fragp
->fr_symbol
)
25532 exp
.X_op
= O_symbol
;
25533 exp
.X_add_symbol
= fragp
->fr_symbol
;
25537 exp
.X_op
= O_constant
;
25539 exp
.X_add_number
= fragp
->fr_offset
;
25540 opcode
= fragp
->fr_subtype
;
25543 case T_MNEM_ldr_pc
:
25544 case T_MNEM_ldr_pc2
:
25545 case T_MNEM_ldr_sp
:
25546 case T_MNEM_str_sp
:
25553 if (fragp
->fr_var
== 4)
25555 insn
= THUMB_OP32 (opcode
);
25556 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
25558 insn
|= (old_op
& 0x700) << 4;
25562 insn
|= (old_op
& 7) << 12;
25563 insn
|= (old_op
& 0x38) << 13;
25565 insn
|= 0x00000c00;
25566 put_thumb32_insn (buf
, insn
);
25567 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
25571 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
25573 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
25576 if (fragp
->fr_var
== 4)
25578 insn
= THUMB_OP32 (opcode
);
25579 insn
|= (old_op
& 0xf0) << 4;
25580 put_thumb32_insn (buf
, insn
);
25581 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
25585 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25586 exp
.X_add_number
-= 4;
25594 if (fragp
->fr_var
== 4)
25596 int r0off
= (opcode
== T_MNEM_mov
25597 || opcode
== T_MNEM_movs
) ? 0 : 8;
25598 insn
= THUMB_OP32 (opcode
);
25599 insn
= (insn
& 0xe1ffffff) | 0x10000000;
25600 insn
|= (old_op
& 0x700) << r0off
;
25601 put_thumb32_insn (buf
, insn
);
25602 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25606 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
25611 if (fragp
->fr_var
== 4)
25613 insn
= THUMB_OP32(opcode
);
25614 put_thumb32_insn (buf
, insn
);
25615 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
25618 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
25622 if (fragp
->fr_var
== 4)
25624 insn
= THUMB_OP32(opcode
);
25625 insn
|= (old_op
& 0xf00) << 14;
25626 put_thumb32_insn (buf
, insn
);
25627 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
25630 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
25633 case T_MNEM_add_sp
:
25634 case T_MNEM_add_pc
:
25635 case T_MNEM_inc_sp
:
25636 case T_MNEM_dec_sp
:
25637 if (fragp
->fr_var
== 4)
25639 /* ??? Choose between add and addw. */
25640 insn
= THUMB_OP32 (opcode
);
25641 insn
|= (old_op
& 0xf0) << 4;
25642 put_thumb32_insn (buf
, insn
);
25643 if (opcode
== T_MNEM_add_pc
)
25644 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
25646 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
25649 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25657 if (fragp
->fr_var
== 4)
25659 insn
= THUMB_OP32 (opcode
);
25660 insn
|= (old_op
& 0xf0) << 4;
25661 insn
|= (old_op
& 0xf) << 16;
25662 put_thumb32_insn (buf
, insn
);
25663 if (insn
& (1 << 20))
25664 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
25666 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25669 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25675 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
25676 (enum bfd_reloc_code_real
) reloc_type
);
25677 fixp
->fx_file
= fragp
->fr_file
;
25678 fixp
->fx_line
= fragp
->fr_line
;
25679 fragp
->fr_fix
+= fragp
->fr_var
;
25681 /* Set whether we use thumb-2 ISA based on final relaxation results. */
25682 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
25683 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
25684 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
25687 /* Return the size of a relaxable immediate operand instruction.
25688 SHIFT and SIZE specify the form of the allowable immediate. */
25690 relax_immediate (fragS
*fragp
, int size
, int shift
)
25696 /* ??? Should be able to do better than this. */
25697 if (fragp
->fr_symbol
)
25700 low
= (1 << shift
) - 1;
25701 mask
= (1 << (shift
+ size
)) - (1 << shift
);
25702 offset
= fragp
->fr_offset
;
25703 /* Force misaligned offsets to 32-bit variant. */
25706 if (offset
& ~mask
)
25711 /* Get the address of a symbol during relaxation. */
25713 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
25719 sym
= fragp
->fr_symbol
;
25720 sym_frag
= symbol_get_frag (sym
);
25721 know (S_GET_SEGMENT (sym
) != absolute_section
25722 || sym_frag
== &zero_address_frag
);
25723 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
25725 /* If frag has yet to be reached on this pass, assume it will
25726 move by STRETCH just as we did. If this is not so, it will
25727 be because some frag between grows, and that will force
25731 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
25735 /* Adjust stretch for any alignment frag. Note that if have
25736 been expanding the earlier code, the symbol may be
25737 defined in what appears to be an earlier frag. FIXME:
25738 This doesn't handle the fr_subtype field, which specifies
25739 a maximum number of bytes to skip when doing an
25741 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
25743 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
25746 stretch
= - ((- stretch
)
25747 & ~ ((1 << (int) f
->fr_offset
) - 1));
25749 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
25761 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
25764 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
25769 /* Assume worst case for symbols not known to be in the same section. */
25770 if (fragp
->fr_symbol
== NULL
25771 || !S_IS_DEFINED (fragp
->fr_symbol
)
25772 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
25773 || S_IS_WEAK (fragp
->fr_symbol
))
25776 val
= relaxed_symbol_addr (fragp
, stretch
);
25777 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
25778 addr
= (addr
+ 4) & ~3;
25779 /* Force misaligned targets to 32-bit variant. */
25783 if (val
< 0 || val
> 1020)
25788 /* Return the size of a relaxable add/sub immediate instruction. */
25790 relax_addsub (fragS
*fragp
, asection
*sec
)
25795 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
25796 op
= bfd_get_16(sec
->owner
, buf
);
25797 if ((op
& 0xf) == ((op
>> 4) & 0xf))
25798 return relax_immediate (fragp
, 8, 0);
25800 return relax_immediate (fragp
, 3, 0);
25803 /* Return TRUE iff the definition of symbol S could be pre-empted
25804 (overridden) at link or load time. */
25806 symbol_preemptible (symbolS
*s
)
25808 /* Weak symbols can always be pre-empted. */
25812 /* Non-global symbols cannot be pre-empted. */
25813 if (! S_IS_EXTERNAL (s
))
25817 /* In ELF, a global symbol can be marked protected, or private. In that
25818 case it can't be pre-empted (other definitions in the same link unit
25819 would violate the ODR). */
25820 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
25824 /* Other global symbols might be pre-empted. */
25828 /* Return the size of a relaxable branch instruction. BITS is the
25829 size of the offset field in the narrow instruction. */
25832 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
25838 /* Assume worst case for symbols not known to be in the same section. */
25839 if (!S_IS_DEFINED (fragp
->fr_symbol
)
25840 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
25841 || S_IS_WEAK (fragp
->fr_symbol
))
25845 /* A branch to a function in ARM state will require interworking. */
25846 if (S_IS_DEFINED (fragp
->fr_symbol
)
25847 && ARM_IS_FUNC (fragp
->fr_symbol
))
25851 if (symbol_preemptible (fragp
->fr_symbol
))
25854 val
= relaxed_symbol_addr (fragp
, stretch
);
25855 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
25858 /* Offset is a signed value *2 */
25860 if (val
>= limit
|| val
< -limit
)
25866 /* Relax a machine dependent frag. This returns the amount by which
25867 the current size of the frag should change. */
25870 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
25875 oldsize
= fragp
->fr_var
;
25876 switch (fragp
->fr_subtype
)
25878 case T_MNEM_ldr_pc2
:
25879 newsize
= relax_adr (fragp
, sec
, stretch
);
25881 case T_MNEM_ldr_pc
:
25882 case T_MNEM_ldr_sp
:
25883 case T_MNEM_str_sp
:
25884 newsize
= relax_immediate (fragp
, 8, 2);
25888 newsize
= relax_immediate (fragp
, 5, 2);
25892 newsize
= relax_immediate (fragp
, 5, 1);
25896 newsize
= relax_immediate (fragp
, 5, 0);
25899 newsize
= relax_adr (fragp
, sec
, stretch
);
25905 newsize
= relax_immediate (fragp
, 8, 0);
25908 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
25911 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
25913 case T_MNEM_add_sp
:
25914 case T_MNEM_add_pc
:
25915 newsize
= relax_immediate (fragp
, 8, 2);
25917 case T_MNEM_inc_sp
:
25918 case T_MNEM_dec_sp
:
25919 newsize
= relax_immediate (fragp
, 7, 2);
25925 newsize
= relax_addsub (fragp
, sec
);
25931 fragp
->fr_var
= newsize
;
25932 /* Freeze wide instructions that are at or before the same location as
25933 in the previous pass. This avoids infinite loops.
25934 Don't freeze them unconditionally because targets may be artificially
25935 misaligned by the expansion of preceding frags. */
25936 if (stretch
<= 0 && newsize
> 2)
25938 md_convert_frag (sec
->owner
, sec
, fragp
);
25942 return newsize
- oldsize
;
25945 /* Round up a section size to the appropriate boundary. */
25948 md_section_align (segT segment ATTRIBUTE_UNUSED
,
25954 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
25955 of an rs_align_code fragment. */
25958 arm_handle_align (fragS
* fragP
)
25960 static unsigned char const arm_noop
[2][2][4] =
25963 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
25964 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
25967 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
25968 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
25971 static unsigned char const thumb_noop
[2][2][2] =
25974 {0xc0, 0x46}, /* LE */
25975 {0x46, 0xc0}, /* BE */
25978 {0x00, 0xbf}, /* LE */
25979 {0xbf, 0x00} /* BE */
25982 static unsigned char const wide_thumb_noop
[2][4] =
25983 { /* Wide Thumb-2 */
25984 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
25985 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
25988 unsigned bytes
, fix
, noop_size
;
25990 const unsigned char * noop
;
25991 const unsigned char *narrow_noop
= NULL
;
25996 if (fragP
->fr_type
!= rs_align_code
)
25999 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
26000 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
26003 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26004 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
26006 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
26008 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
26010 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26011 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
26013 narrow_noop
= thumb_noop
[1][target_big_endian
];
26014 noop
= wide_thumb_noop
[target_big_endian
];
26017 noop
= thumb_noop
[0][target_big_endian
];
26025 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26026 ? selected_cpu
: arm_arch_none
,
26028 [target_big_endian
];
26035 fragP
->fr_var
= noop_size
;
26037 if (bytes
& (noop_size
- 1))
26039 fix
= bytes
& (noop_size
- 1);
26041 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
26043 memset (p
, 0, fix
);
26050 if (bytes
& noop_size
)
26052 /* Insert a narrow noop. */
26053 memcpy (p
, narrow_noop
, noop_size
);
26055 bytes
-= noop_size
;
26059 /* Use wide noops for the remainder */
26063 while (bytes
>= noop_size
)
26065 memcpy (p
, noop
, noop_size
);
26067 bytes
-= noop_size
;
26071 fragP
->fr_fix
+= fix
;
26074 /* Called from md_do_align. Used to create an alignment
26075 frag in a code section. */
26078 arm_frag_align_code (int n
, int max
)
26082 /* We assume that there will never be a requirement
26083 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
26084 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26089 _("alignments greater than %d bytes not supported in .text sections."),
26090 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
26091 as_fatal ("%s", err_msg
);
26094 p
= frag_var (rs_align_code
,
26095 MAX_MEM_FOR_RS_ALIGN_CODE
,
26097 (relax_substateT
) max
,
26104 /* Perform target specific initialisation of a frag.
26105 Note - despite the name this initialisation is not done when the frag
26106 is created, but only when its type is assigned. A frag can be created
26107 and used a long time before its type is set, so beware of assuming that
26108 this initialisation is performed first. */
26112 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
26114 /* Record whether this frag is in an ARM or a THUMB area. */
26115 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26118 #else /* OBJ_ELF is defined. */
26120 arm_init_frag (fragS
* fragP
, int max_chars
)
26122 bfd_boolean frag_thumb_mode
;
26124 /* If the current ARM vs THUMB mode has not already
26125 been recorded into this frag then do so now. */
26126 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
26127 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26129 /* PR 21809: Do not set a mapping state for debug sections
26130 - it just confuses other tools. */
26131 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
26134 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
26136 /* Record a mapping symbol for alignment frags. We will delete this
26137 later if the alignment ends up empty. */
26138 switch (fragP
->fr_type
)
26141 case rs_align_test
:
26143 mapping_state_2 (MAP_DATA
, max_chars
);
26145 case rs_align_code
:
26146 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
26153 /* When we change sections we need to issue a new mapping symbol. */
26156 arm_elf_change_section (void)
26158 /* Link an unlinked unwind index table section to the .text section. */
26159 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
26160 && elf_linked_to_section (now_seg
) == NULL
)
26161 elf_linked_to_section (now_seg
) = text_section
;
26165 arm_elf_section_type (const char * str
, size_t len
)
26167 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
26168 return SHT_ARM_EXIDX
;
26173 /* Code to deal with unwinding tables. */
26175 static void add_unwind_adjustsp (offsetT
);
26177 /* Generate any deferred unwind frame offset. */
26180 flush_pending_unwind (void)
26184 offset
= unwind
.pending_offset
;
26185 unwind
.pending_offset
= 0;
26187 add_unwind_adjustsp (offset
);
26190 /* Add an opcode to this list for this function. Two-byte opcodes should
26191 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
26195 add_unwind_opcode (valueT op
, int length
)
26197 /* Add any deferred stack adjustment. */
26198 if (unwind
.pending_offset
)
26199 flush_pending_unwind ();
26201 unwind
.sp_restored
= 0;
26203 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
26205 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
26206 if (unwind
.opcodes
)
26207 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
26208 unwind
.opcode_alloc
);
26210 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
26215 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
26217 unwind
.opcode_count
++;
26221 /* Add unwind opcodes to adjust the stack pointer. */
26224 add_unwind_adjustsp (offsetT offset
)
26228 if (offset
> 0x200)
26230 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
26235 /* Long form: 0xb2, uleb128. */
26236 /* This might not fit in a word so add the individual bytes,
26237 remembering the list is built in reverse order. */
26238 o
= (valueT
) ((offset
- 0x204) >> 2);
26240 add_unwind_opcode (0, 1);
26242 /* Calculate the uleb128 encoding of the offset. */
26246 bytes
[n
] = o
& 0x7f;
26252 /* Add the insn. */
26254 add_unwind_opcode (bytes
[n
- 1], 1);
26255 add_unwind_opcode (0xb2, 1);
26257 else if (offset
> 0x100)
26259 /* Two short opcodes. */
26260 add_unwind_opcode (0x3f, 1);
26261 op
= (offset
- 0x104) >> 2;
26262 add_unwind_opcode (op
, 1);
26264 else if (offset
> 0)
26266 /* Short opcode. */
26267 op
= (offset
- 4) >> 2;
26268 add_unwind_opcode (op
, 1);
26270 else if (offset
< 0)
26273 while (offset
> 0x100)
26275 add_unwind_opcode (0x7f, 1);
26278 op
= ((offset
- 4) >> 2) | 0x40;
26279 add_unwind_opcode (op
, 1);
26283 /* Finish the list of unwind opcodes for this function. */
26286 finish_unwind_opcodes (void)
26290 if (unwind
.fp_used
)
26292 /* Adjust sp as necessary. */
26293 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
26294 flush_pending_unwind ();
26296 /* After restoring sp from the frame pointer. */
26297 op
= 0x90 | unwind
.fp_reg
;
26298 add_unwind_opcode (op
, 1);
26301 flush_pending_unwind ();
26305 /* Start an exception table entry. If idx is nonzero this is an index table
26309 start_unwind_section (const segT text_seg
, int idx
)
26311 const char * text_name
;
26312 const char * prefix
;
26313 const char * prefix_once
;
26314 const char * group_name
;
26322 prefix
= ELF_STRING_ARM_unwind
;
26323 prefix_once
= ELF_STRING_ARM_unwind_once
;
26324 type
= SHT_ARM_EXIDX
;
26328 prefix
= ELF_STRING_ARM_unwind_info
;
26329 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
26330 type
= SHT_PROGBITS
;
26333 text_name
= segment_name (text_seg
);
26334 if (streq (text_name
, ".text"))
26337 if (strncmp (text_name
, ".gnu.linkonce.t.",
26338 strlen (".gnu.linkonce.t.")) == 0)
26340 prefix
= prefix_once
;
26341 text_name
+= strlen (".gnu.linkonce.t.");
26344 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
26350 /* Handle COMDAT group. */
26351 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
26353 group_name
= elf_group_name (text_seg
);
26354 if (group_name
== NULL
)
26356 as_bad (_("Group section `%s' has no group signature"),
26357 segment_name (text_seg
));
26358 ignore_rest_of_line ();
26361 flags
|= SHF_GROUP
;
26365 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
26368 /* Set the section link for index tables. */
26370 elf_linked_to_section (now_seg
) = text_seg
;
26374 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
26375 personality routine data. Returns zero, or the index table value for
26376 an inline entry. */
26379 create_unwind_entry (int have_data
)
26384 /* The current word of data. */
26386 /* The number of bytes left in this word. */
26389 finish_unwind_opcodes ();
26391 /* Remember the current text section. */
26392 unwind
.saved_seg
= now_seg
;
26393 unwind
.saved_subseg
= now_subseg
;
26395 start_unwind_section (now_seg
, 0);
26397 if (unwind
.personality_routine
== NULL
)
26399 if (unwind
.personality_index
== -2)
26402 as_bad (_("handlerdata in cantunwind frame"));
26403 return 1; /* EXIDX_CANTUNWIND. */
26406 /* Use a default personality routine if none is specified. */
26407 if (unwind
.personality_index
== -1)
26409 if (unwind
.opcode_count
> 3)
26410 unwind
.personality_index
= 1;
26412 unwind
.personality_index
= 0;
26415 /* Space for the personality routine entry. */
26416 if (unwind
.personality_index
== 0)
26418 if (unwind
.opcode_count
> 3)
26419 as_bad (_("too many unwind opcodes for personality routine 0"));
26423 /* All the data is inline in the index table. */
26426 while (unwind
.opcode_count
> 0)
26428 unwind
.opcode_count
--;
26429 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26433 /* Pad with "finish" opcodes. */
26435 data
= (data
<< 8) | 0xb0;
26442 /* We get two opcodes "free" in the first word. */
26443 size
= unwind
.opcode_count
- 2;
26447 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
26448 if (unwind
.personality_index
!= -1)
26450 as_bad (_("attempt to recreate an unwind entry"));
26454 /* An extra byte is required for the opcode count. */
26455 size
= unwind
.opcode_count
+ 1;
26458 size
= (size
+ 3) >> 2;
26460 as_bad (_("too many unwind opcodes"));
26462 frag_align (2, 0, 0);
26463 record_alignment (now_seg
, 2);
26464 unwind
.table_entry
= expr_build_dot ();
26466 /* Allocate the table entry. */
26467 ptr
= frag_more ((size
<< 2) + 4);
26468 /* PR 13449: Zero the table entries in case some of them are not used. */
26469 memset (ptr
, 0, (size
<< 2) + 4);
26470 where
= frag_now_fix () - ((size
<< 2) + 4);
26472 switch (unwind
.personality_index
)
26475 /* ??? Should this be a PLT generating relocation? */
26476 /* Custom personality routine. */
26477 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
26478 BFD_RELOC_ARM_PREL31
);
26483 /* Set the first byte to the number of additional words. */
26484 data
= size
> 0 ? size
- 1 : 0;
26488 /* ABI defined personality routines. */
26490 /* Three opcodes bytes are packed into the first word. */
26497 /* The size and first two opcode bytes go in the first word. */
26498 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
26503 /* Should never happen. */
26507 /* Pack the opcodes into words (MSB first), reversing the list at the same
26509 while (unwind
.opcode_count
> 0)
26513 md_number_to_chars (ptr
, data
, 4);
26518 unwind
.opcode_count
--;
26520 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26523 /* Finish off the last word. */
26526 /* Pad with "finish" opcodes. */
26528 data
= (data
<< 8) | 0xb0;
26530 md_number_to_chars (ptr
, data
, 4);
26535 /* Add an empty descriptor if there is no user-specified data. */
26536 ptr
= frag_more (4);
26537 md_number_to_chars (ptr
, 0, 4);
26544 /* Initialize the DWARF-2 unwind information for this procedure. */
26547 tc_arm_frame_initial_instructions (void)
26549 cfi_add_CFA_def_cfa (REG_SP
, 0);
26551 #endif /* OBJ_ELF */
26553 /* Convert REGNAME to a DWARF-2 register number. */
26556 tc_arm_regname_to_dw2regnum (char *regname
)
26558 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
26562 /* PR 16694: Allow VFP registers as well. */
26563 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
26567 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
26576 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
26580 exp
.X_op
= O_secrel
;
26581 exp
.X_add_symbol
= symbol
;
26582 exp
.X_add_number
= 0;
26583 emit_expr (&exp
, size
);
26587 /* MD interface: Symbol and relocation handling. */
26589 /* Return the address within the segment that a PC-relative fixup is
26590 relative to. For ARM, PC-relative fixups applied to instructions
26591 are generally relative to the location of the fixup plus 8 bytes.
26592 Thumb branches are offset by 4, and Thumb loads relative to PC
26593 require special handling. */
26596 md_pcrel_from_section (fixS
* fixP
, segT seg
)
26598 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26600 /* If this is pc-relative and we are going to emit a relocation
26601 then we just want to put out any pipeline compensation that the linker
26602 will need. Otherwise we want to use the calculated base.
26603 For WinCE we skip the bias for externals as well, since this
26604 is how the MS ARM-CE assembler behaves and we want to be compatible. */
26606 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
26607 || (arm_force_relocation (fixP
)
26609 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
26615 switch (fixP
->fx_r_type
)
26617 /* PC relative addressing on the Thumb is slightly odd as the
26618 bottom two bits of the PC are forced to zero for the
26619 calculation. This happens *after* application of the
26620 pipeline offset. However, Thumb adrl already adjusts for
26621 this, so we need not do it again. */
26622 case BFD_RELOC_ARM_THUMB_ADD
:
26625 case BFD_RELOC_ARM_THUMB_OFFSET
:
26626 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
26627 case BFD_RELOC_ARM_T32_ADD_PC12
:
26628 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
26629 return (base
+ 4) & ~3;
26631 /* Thumb branches are simply offset by +4. */
26632 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
26633 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
26634 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
26635 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
26636 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
26637 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
26638 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
26639 case BFD_RELOC_ARM_THUMB_BF17
:
26640 case BFD_RELOC_ARM_THUMB_BF19
:
26641 case BFD_RELOC_ARM_THUMB_BF13
:
26642 case BFD_RELOC_ARM_THUMB_LOOP12
:
26645 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26647 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26648 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26649 && ARM_IS_FUNC (fixP
->fx_addsy
)
26650 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26651 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26654 /* BLX is like branches above, but forces the low two bits of PC to
26656 case BFD_RELOC_THUMB_PCREL_BLX
:
26658 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26659 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26660 && THUMB_IS_FUNC (fixP
->fx_addsy
)
26661 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26662 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26663 return (base
+ 4) & ~3;
26665 /* ARM mode branches are offset by +8. However, the Windows CE
26666 loader expects the relocation not to take this into account. */
26667 case BFD_RELOC_ARM_PCREL_BLX
:
26669 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26670 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26671 && ARM_IS_FUNC (fixP
->fx_addsy
)
26672 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26673 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26676 case BFD_RELOC_ARM_PCREL_CALL
:
26678 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26679 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26680 && THUMB_IS_FUNC (fixP
->fx_addsy
)
26681 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26682 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26685 case BFD_RELOC_ARM_PCREL_BRANCH
:
26686 case BFD_RELOC_ARM_PCREL_JUMP
:
26687 case BFD_RELOC_ARM_PLT32
:
26689 /* When handling fixups immediately, because we have already
26690 discovered the value of a symbol, or the address of the frag involved
26691 we must account for the offset by +8, as the OS loader will never see the reloc.
26692 see fixup_segment() in write.c
26693 The S_IS_EXTERNAL test handles the case of global symbols.
26694 Those need the calculated base, not just the pipe compensation the linker will need. */
26696 && fixP
->fx_addsy
!= NULL
26697 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26698 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
26706 /* ARM mode loads relative to PC are also offset by +8. Unlike
26707 branches, the Windows CE loader *does* expect the relocation
26708 to take this into account. */
26709 case BFD_RELOC_ARM_OFFSET_IMM
:
26710 case BFD_RELOC_ARM_OFFSET_IMM8
:
26711 case BFD_RELOC_ARM_HWLITERAL
:
26712 case BFD_RELOC_ARM_LITERAL
:
26713 case BFD_RELOC_ARM_CP_OFF_IMM
:
26717 /* Other PC-relative relocations are un-offset. */
26723 static bfd_boolean flag_warn_syms
= TRUE
;
26726 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
26728 /* PR 18347 - Warn if the user attempts to create a symbol with the same
26729 name as an ARM instruction. Whilst strictly speaking it is allowed, it
26730 does mean that the resulting code might be very confusing to the reader.
26731 Also this warning can be triggered if the user omits an operand before
26732 an immediate address, eg:
26736 GAS treats this as an assignment of the value of the symbol foo to a
26737 symbol LDR, and so (without this code) it will not issue any kind of
26738 warning or error message.
26740 Note - ARM instructions are case-insensitive but the strings in the hash
26741 table are all stored in lower case, so we must first ensure that name is
26743 if (flag_warn_syms
&& arm_ops_hsh
)
26745 char * nbuf
= strdup (name
);
26748 for (p
= nbuf
; *p
; p
++)
26750 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
26752 static struct hash_control
* already_warned
= NULL
;
26754 if (already_warned
== NULL
)
26755 already_warned
= hash_new ();
26756 /* Only warn about the symbol once. To keep the code
26757 simple we let hash_insert do the lookup for us. */
26758 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
26759 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
26768 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
26769 Otherwise we have no need to default values of symbols. */
26772 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
26775 if (name
[0] == '_' && name
[1] == 'G'
26776 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
26780 if (symbol_find (name
))
26781 as_bad (_("GOT already in the symbol table"));
26783 GOT_symbol
= symbol_new (name
, undefined_section
,
26784 (valueT
) 0, & zero_address_frag
);
26794 /* Subroutine of md_apply_fix. Check to see if an immediate can be
26795 computed as two separate immediate values, added together. We
26796 already know that this value cannot be computed by just one ARM
26799 static unsigned int
26800 validate_immediate_twopart (unsigned int val
,
26801 unsigned int * highpart
)
26806 for (i
= 0; i
< 32; i
+= 2)
26807 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
26813 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
26815 else if (a
& 0xff0000)
26817 if (a
& 0xff000000)
26819 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
26823 gas_assert (a
& 0xff000000);
26824 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
26827 return (a
& 0xff) | (i
<< 7);
26834 validate_offset_imm (unsigned int val
, int hwse
)
26836 if ((hwse
&& val
> 255) || val
> 4095)
26841 /* Subroutine of md_apply_fix. Do those data_ops which can take a
26842 negative immediate constant by altering the instruction. A bit of
26847 by inverting the second operand, and
26850 by negating the second operand. */
26853 negate_data_op (unsigned long * instruction
,
26854 unsigned long value
)
26857 unsigned long negated
, inverted
;
26859 negated
= encode_arm_immediate (-value
);
26860 inverted
= encode_arm_immediate (~value
);
26862 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
26865 /* First negates. */
26866 case OPCODE_SUB
: /* ADD <-> SUB */
26867 new_inst
= OPCODE_ADD
;
26872 new_inst
= OPCODE_SUB
;
26876 case OPCODE_CMP
: /* CMP <-> CMN */
26877 new_inst
= OPCODE_CMN
;
26882 new_inst
= OPCODE_CMP
;
26886 /* Now Inverted ops. */
26887 case OPCODE_MOV
: /* MOV <-> MVN */
26888 new_inst
= OPCODE_MVN
;
26893 new_inst
= OPCODE_MOV
;
26897 case OPCODE_AND
: /* AND <-> BIC */
26898 new_inst
= OPCODE_BIC
;
26903 new_inst
= OPCODE_AND
;
26907 case OPCODE_ADC
: /* ADC <-> SBC */
26908 new_inst
= OPCODE_SBC
;
26913 new_inst
= OPCODE_ADC
;
26917 /* We cannot do anything. */
26922 if (value
== (unsigned) FAIL
)
26925 *instruction
&= OPCODE_MASK
;
26926 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
26930 /* Like negate_data_op, but for Thumb-2. */
26932 static unsigned int
26933 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
26937 unsigned int negated
, inverted
;
26939 negated
= encode_thumb32_immediate (-value
);
26940 inverted
= encode_thumb32_immediate (~value
);
26942 rd
= (*instruction
>> 8) & 0xf;
26943 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
26946 /* ADD <-> SUB. Includes CMP <-> CMN. */
26947 case T2_OPCODE_SUB
:
26948 new_inst
= T2_OPCODE_ADD
;
26952 case T2_OPCODE_ADD
:
26953 new_inst
= T2_OPCODE_SUB
;
26957 /* ORR <-> ORN. Includes MOV <-> MVN. */
26958 case T2_OPCODE_ORR
:
26959 new_inst
= T2_OPCODE_ORN
;
26963 case T2_OPCODE_ORN
:
26964 new_inst
= T2_OPCODE_ORR
;
26968 /* AND <-> BIC. TST has no inverted equivalent. */
26969 case T2_OPCODE_AND
:
26970 new_inst
= T2_OPCODE_BIC
;
26977 case T2_OPCODE_BIC
:
26978 new_inst
= T2_OPCODE_AND
;
26983 case T2_OPCODE_ADC
:
26984 new_inst
= T2_OPCODE_SBC
;
26988 case T2_OPCODE_SBC
:
26989 new_inst
= T2_OPCODE_ADC
;
26993 /* We cannot do anything. */
26998 if (value
== (unsigned int)FAIL
)
27001 *instruction
&= T2_OPCODE_MASK
;
27002 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
27006 /* Read a 32-bit thumb instruction from buf. */
27008 static unsigned long
27009 get_thumb32_insn (char * buf
)
27011 unsigned long insn
;
27012 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
27013 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27018 /* We usually want to set the low bit on the address of thumb function
27019 symbols. In particular .word foo - . should have the low bit set.
27020 Generic code tries to fold the difference of two symbols to
27021 a constant. Prevent this and force a relocation when the first symbols
27022 is a thumb function. */
27025 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
27027 if (op
== O_subtract
27028 && l
->X_op
== O_symbol
27029 && r
->X_op
== O_symbol
27030 && THUMB_IS_FUNC (l
->X_add_symbol
))
27032 l
->X_op
= O_subtract
;
27033 l
->X_op_symbol
= r
->X_add_symbol
;
27034 l
->X_add_number
-= r
->X_add_number
;
27038 /* Process as normal. */
27042 /* Encode Thumb2 unconditional branches and calls. The encoding
27043 for the 2 are identical for the immediate values. */
27046 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
27048 #define T2I1I2MASK ((1 << 13) | (1 << 11))
27051 addressT S
, I1
, I2
, lo
, hi
;
27053 S
= (value
>> 24) & 0x01;
27054 I1
= (value
>> 23) & 0x01;
27055 I2
= (value
>> 22) & 0x01;
27056 hi
= (value
>> 12) & 0x3ff;
27057 lo
= (value
>> 1) & 0x7ff;
27058 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27059 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27060 newval
|= (S
<< 10) | hi
;
27061 newval2
&= ~T2I1I2MASK
;
27062 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
27063 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27064 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27068 md_apply_fix (fixS
* fixP
,
27072 offsetT value
= * valP
;
27074 unsigned int newimm
;
27075 unsigned long temp
;
27077 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
27079 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
27081 /* Note whether this will delete the relocation. */
27083 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
27086 /* On a 64-bit host, silently truncate 'value' to 32 bits for
27087 consistency with the behaviour on 32-bit hosts. Remember value
27089 value
&= 0xffffffff;
27090 value
^= 0x80000000;
27091 value
-= 0x80000000;
27094 fixP
->fx_addnumber
= value
;
27096 /* Same treatment for fixP->fx_offset. */
27097 fixP
->fx_offset
&= 0xffffffff;
27098 fixP
->fx_offset
^= 0x80000000;
27099 fixP
->fx_offset
-= 0x80000000;
27101 switch (fixP
->fx_r_type
)
27103 case BFD_RELOC_NONE
:
27104 /* This will need to go in the object file. */
27108 case BFD_RELOC_ARM_IMMEDIATE
:
27109 /* We claim that this fixup has been processed here,
27110 even if in fact we generate an error because we do
27111 not have a reloc for it, so tc_gen_reloc will reject it. */
27114 if (fixP
->fx_addsy
)
27116 const char *msg
= 0;
27118 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27119 msg
= _("undefined symbol %s used as an immediate value");
27120 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27121 msg
= _("symbol %s is in a different section");
27122 else if (S_IS_WEAK (fixP
->fx_addsy
))
27123 msg
= _("symbol %s is weak and may be overridden later");
27127 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27128 msg
, S_GET_NAME (fixP
->fx_addsy
));
27133 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27135 /* If the offset is negative, we should use encoding A2 for ADR. */
27136 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
27137 newimm
= negate_data_op (&temp
, value
);
27140 newimm
= encode_arm_immediate (value
);
27142 /* If the instruction will fail, see if we can fix things up by
27143 changing the opcode. */
27144 if (newimm
== (unsigned int) FAIL
)
27145 newimm
= negate_data_op (&temp
, value
);
27146 /* MOV accepts both ARM modified immediate (A1 encoding) and
27147 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
27148 When disassembling, MOV is preferred when there is no encoding
27150 if (newimm
== (unsigned int) FAIL
27151 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
27152 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
27153 && !((temp
>> SBIT_SHIFT
) & 0x1)
27154 && value
>= 0 && value
<= 0xffff)
27156 /* Clear bits[23:20] to change encoding from A1 to A2. */
27157 temp
&= 0xff0fffff;
27158 /* Encoding high 4bits imm. Code below will encode the remaining
27160 temp
|= (value
& 0x0000f000) << 4;
27161 newimm
= value
& 0x00000fff;
27165 if (newimm
== (unsigned int) FAIL
)
27167 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27168 _("invalid constant (%lx) after fixup"),
27169 (unsigned long) value
);
27173 newimm
|= (temp
& 0xfffff000);
27174 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27177 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
27179 unsigned int highpart
= 0;
27180 unsigned int newinsn
= 0xe1a00000; /* nop. */
27182 if (fixP
->fx_addsy
)
27184 const char *msg
= 0;
27186 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27187 msg
= _("undefined symbol %s used as an immediate value");
27188 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27189 msg
= _("symbol %s is in a different section");
27190 else if (S_IS_WEAK (fixP
->fx_addsy
))
27191 msg
= _("symbol %s is weak and may be overridden later");
27195 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27196 msg
, S_GET_NAME (fixP
->fx_addsy
));
27201 newimm
= encode_arm_immediate (value
);
27202 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27204 /* If the instruction will fail, see if we can fix things up by
27205 changing the opcode. */
27206 if (newimm
== (unsigned int) FAIL
27207 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
27209 /* No ? OK - try using two ADD instructions to generate
27211 newimm
= validate_immediate_twopart (value
, & highpart
);
27213 /* Yes - then make sure that the second instruction is
27215 if (newimm
!= (unsigned int) FAIL
)
27217 /* Still No ? Try using a negated value. */
27218 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
27219 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
27220 /* Otherwise - give up. */
27223 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27224 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
27229 /* Replace the first operand in the 2nd instruction (which
27230 is the PC) with the destination register. We have
27231 already added in the PC in the first instruction and we
27232 do not want to do it again. */
27233 newinsn
&= ~ 0xf0000;
27234 newinsn
|= ((newinsn
& 0x0f000) << 4);
27237 newimm
|= (temp
& 0xfffff000);
27238 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27240 highpart
|= (newinsn
& 0xfffff000);
27241 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
27245 case BFD_RELOC_ARM_OFFSET_IMM
:
27246 if (!fixP
->fx_done
&& seg
->use_rela_p
)
27248 /* Fall through. */
27250 case BFD_RELOC_ARM_LITERAL
:
27256 if (validate_offset_imm (value
, 0) == FAIL
)
27258 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
27259 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27260 _("invalid literal constant: pool needs to be closer"));
27262 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27263 _("bad immediate value for offset (%ld)"),
27268 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27270 newval
&= 0xfffff000;
27273 newval
&= 0xff7ff000;
27274 newval
|= value
| (sign
? INDEX_UP
: 0);
27276 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27279 case BFD_RELOC_ARM_OFFSET_IMM8
:
27280 case BFD_RELOC_ARM_HWLITERAL
:
27286 if (validate_offset_imm (value
, 1) == FAIL
)
27288 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
27289 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27290 _("invalid literal constant: pool needs to be closer"));
27292 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27293 _("bad immediate value for 8-bit offset (%ld)"),
27298 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27300 newval
&= 0xfffff0f0;
27303 newval
&= 0xff7ff0f0;
27304 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
27306 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27309 case BFD_RELOC_ARM_T32_OFFSET_U8
:
27310 if (value
< 0 || value
> 1020 || value
% 4 != 0)
27311 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27312 _("bad immediate value for offset (%ld)"), (long) value
);
27315 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
27317 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
27320 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27321 /* This is a complicated relocation used for all varieties of Thumb32
27322 load/store instruction with immediate offset:
27324 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
27325 *4, optional writeback(W)
27326 (doubleword load/store)
27328 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
27329 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
27330 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
27331 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
27332 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
27334 Uppercase letters indicate bits that are already encoded at
27335 this point. Lowercase letters are our problem. For the
27336 second block of instructions, the secondary opcode nybble
27337 (bits 8..11) is present, and bit 23 is zero, even if this is
27338 a PC-relative operation. */
27339 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27341 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
27343 if ((newval
& 0xf0000000) == 0xe0000000)
27345 /* Doubleword load/store: 8-bit offset, scaled by 4. */
27347 newval
|= (1 << 23);
27350 if (value
% 4 != 0)
27352 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27353 _("offset not a multiple of 4"));
27359 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27360 _("offset out of range"));
27365 else if ((newval
& 0x000f0000) == 0x000f0000)
27367 /* PC-relative, 12-bit offset. */
27369 newval
|= (1 << 23);
27374 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27375 _("offset out of range"));
27380 else if ((newval
& 0x00000100) == 0x00000100)
27382 /* Writeback: 8-bit, +/- offset. */
27384 newval
|= (1 << 9);
27389 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27390 _("offset out of range"));
27395 else if ((newval
& 0x00000f00) == 0x00000e00)
27397 /* T-instruction: positive 8-bit offset. */
27398 if (value
< 0 || value
> 0xff)
27400 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27401 _("offset out of range"));
27409 /* Positive 12-bit or negative 8-bit offset. */
27413 newval
|= (1 << 23);
27423 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27424 _("offset out of range"));
27431 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
27432 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
27435 case BFD_RELOC_ARM_SHIFT_IMM
:
27436 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27437 if (((unsigned long) value
) > 32
27439 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
27441 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27442 _("shift expression is too large"));
27447 /* Shifts of zero must be done as lsl. */
27449 else if (value
== 32)
27451 newval
&= 0xfffff07f;
27452 newval
|= (value
& 0x1f) << 7;
27453 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27456 case BFD_RELOC_ARM_T32_IMMEDIATE
:
27457 case BFD_RELOC_ARM_T32_ADD_IMM
:
27458 case BFD_RELOC_ARM_T32_IMM12
:
27459 case BFD_RELOC_ARM_T32_ADD_PC12
:
27460 /* We claim that this fixup has been processed here,
27461 even if in fact we generate an error because we do
27462 not have a reloc for it, so tc_gen_reloc will reject it. */
27466 && ! S_IS_DEFINED (fixP
->fx_addsy
))
27468 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27469 _("undefined symbol %s used as an immediate value"),
27470 S_GET_NAME (fixP
->fx_addsy
));
27474 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27476 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
27479 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
27480 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
27481 Thumb2 modified immediate encoding (T2). */
27482 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
27483 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27485 newimm
= encode_thumb32_immediate (value
);
27486 if (newimm
== (unsigned int) FAIL
)
27487 newimm
= thumb32_negate_data_op (&newval
, value
);
27489 if (newimm
== (unsigned int) FAIL
)
27491 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
27493 /* Turn add/sum into addw/subw. */
27494 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27495 newval
= (newval
& 0xfeffffff) | 0x02000000;
27496 /* No flat 12-bit imm encoding for addsw/subsw. */
27497 if ((newval
& 0x00100000) == 0)
27499 /* 12 bit immediate for addw/subw. */
27503 newval
^= 0x00a00000;
27506 newimm
= (unsigned int) FAIL
;
27513 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
27514 UINT16 (T3 encoding), MOVW only accepts UINT16. When
27515 disassembling, MOV is preferred when there is no encoding
27517 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
27518 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
27519 but with the Rn field [19:16] set to 1111. */
27520 && (((newval
>> 16) & 0xf) == 0xf)
27521 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
27522 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
27523 && value
>= 0 && value
<= 0xffff)
27525 /* Toggle bit[25] to change encoding from T2 to T3. */
27527 /* Clear bits[19:16]. */
27528 newval
&= 0xfff0ffff;
27529 /* Encoding high 4bits imm. Code below will encode the
27530 remaining low 12bits. */
27531 newval
|= (value
& 0x0000f000) << 4;
27532 newimm
= value
& 0x00000fff;
27537 if (newimm
== (unsigned int)FAIL
)
27539 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27540 _("invalid constant (%lx) after fixup"),
27541 (unsigned long) value
);
27545 newval
|= (newimm
& 0x800) << 15;
27546 newval
|= (newimm
& 0x700) << 4;
27547 newval
|= (newimm
& 0x0ff);
27549 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
27550 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
27553 case BFD_RELOC_ARM_SMC
:
27554 if (((unsigned long) value
) > 0xffff)
27555 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27556 _("invalid smc expression"));
27557 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27558 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
27559 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27562 case BFD_RELOC_ARM_HVC
:
27563 if (((unsigned long) value
) > 0xffff)
27564 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27565 _("invalid hvc expression"));
27566 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27567 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
27568 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27571 case BFD_RELOC_ARM_SWI
:
27572 if (fixP
->tc_fix_data
!= 0)
27574 if (((unsigned long) value
) > 0xff)
27575 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27576 _("invalid swi expression"));
27577 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27579 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27583 if (((unsigned long) value
) > 0x00ffffff)
27584 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27585 _("invalid swi expression"));
27586 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27588 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27592 case BFD_RELOC_ARM_MULTI
:
27593 if (((unsigned long) value
) > 0xffff)
27594 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27595 _("invalid expression in load/store multiple"));
27596 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
27597 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27601 case BFD_RELOC_ARM_PCREL_CALL
:
27603 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27605 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27606 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27607 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27608 /* Flip the bl to blx. This is a simple flip
27609 bit here because we generate PCREL_CALL for
27610 unconditional bls. */
27612 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27613 newval
= newval
| 0x10000000;
27614 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27620 goto arm_branch_common
;
27622 case BFD_RELOC_ARM_PCREL_JUMP
:
27623 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27625 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27626 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27627 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27629 /* This would map to a bl<cond>, b<cond>,
27630 b<always> to a Thumb function. We
27631 need to force a relocation for this particular
27633 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27636 /* Fall through. */
27638 case BFD_RELOC_ARM_PLT32
:
27640 case BFD_RELOC_ARM_PCREL_BRANCH
:
27642 goto arm_branch_common
;
27644 case BFD_RELOC_ARM_PCREL_BLX
:
27647 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27649 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27650 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27651 && ARM_IS_FUNC (fixP
->fx_addsy
))
27653 /* Flip the blx to a bl and warn. */
27654 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
27655 newval
= 0xeb000000;
27656 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
27657 _("blx to '%s' an ARM ISA state function changed to bl"),
27659 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27665 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
27666 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
27670 /* We are going to store value (shifted right by two) in the
27671 instruction, in a 24 bit, signed field. Bits 26 through 32 either
27672 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
27675 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27676 _("misaligned branch destination"));
27677 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
27678 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
27679 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27681 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27683 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27684 newval
|= (value
>> 2) & 0x00ffffff;
27685 /* Set the H bit on BLX instructions. */
27689 newval
|= 0x01000000;
27691 newval
&= ~0x01000000;
27693 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27697 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
27698 /* CBZ can only branch forward. */
27700 /* Attempts to use CBZ to branch to the next instruction
27701 (which, strictly speaking, are prohibited) will be turned into
27704 FIXME: It may be better to remove the instruction completely and
27705 perform relaxation. */
27708 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27709 newval
= 0xbf00; /* NOP encoding T1 */
27710 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27715 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27717 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27719 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27720 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
27721 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27726 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
27727 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
27728 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27730 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27732 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27733 newval
|= (value
& 0x1ff) >> 1;
27734 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27738 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
27739 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
27740 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27742 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27744 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27745 newval
|= (value
& 0xfff) >> 1;
27746 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27750 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27752 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27753 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27754 && ARM_IS_FUNC (fixP
->fx_addsy
)
27755 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27757 /* Force a relocation for a branch 20 bits wide. */
27760 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
27761 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27762 _("conditional branch out of range"));
27764 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27767 addressT S
, J1
, J2
, lo
, hi
;
27769 S
= (value
& 0x00100000) >> 20;
27770 J2
= (value
& 0x00080000) >> 19;
27771 J1
= (value
& 0x00040000) >> 18;
27772 hi
= (value
& 0x0003f000) >> 12;
27773 lo
= (value
& 0x00000ffe) >> 1;
27775 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27776 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27777 newval
|= (S
<< 10) | hi
;
27778 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
27779 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27780 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27784 case BFD_RELOC_THUMB_PCREL_BLX
:
27785 /* If there is a blx from a thumb state function to
27786 another thumb function flip this to a bl and warn
27790 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27791 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27792 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27794 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
27795 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
27796 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
27798 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27799 newval
= newval
| 0x1000;
27800 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
27801 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
27806 goto thumb_bl_common
;
27808 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27809 /* A bl from Thumb state ISA to an internal ARM state function
27810 is converted to a blx. */
27812 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27813 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27814 && ARM_IS_FUNC (fixP
->fx_addsy
)
27815 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27817 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27818 newval
= newval
& ~0x1000;
27819 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
27820 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
27826 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
27827 /* For a BLX instruction, make sure that the relocation is rounded up
27828 to a word boundary. This follows the semantics of the instruction
27829 which specifies that bit 1 of the target address will come from bit
27830 1 of the base address. */
27831 value
= (value
+ 3) & ~ 3;
27834 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
27835 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
27836 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
27839 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
27841 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
27842 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27843 else if ((value
& ~0x1ffffff)
27844 && ((value
& ~0x1ffffff) != ~0x1ffffff))
27845 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27846 _("Thumb2 branch out of range"));
27849 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27850 encode_thumb2_b_bl_offset (buf
, value
);
27854 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27855 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
27856 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27858 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27859 encode_thumb2_b_bl_offset (buf
, value
);
27864 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27869 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27870 md_number_to_chars (buf
, value
, 2);
27874 case BFD_RELOC_ARM_TLS_CALL
:
27875 case BFD_RELOC_ARM_THM_TLS_CALL
:
27876 case BFD_RELOC_ARM_TLS_DESCSEQ
:
27877 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
27878 case BFD_RELOC_ARM_TLS_GOTDESC
:
27879 case BFD_RELOC_ARM_TLS_GD32
:
27880 case BFD_RELOC_ARM_TLS_LE32
:
27881 case BFD_RELOC_ARM_TLS_IE32
:
27882 case BFD_RELOC_ARM_TLS_LDM32
:
27883 case BFD_RELOC_ARM_TLS_LDO32
:
27884 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
27887 /* Same handling as above, but with the arm_fdpic guard. */
27888 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
27889 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
27890 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
27893 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
27897 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27898 _("Relocation supported only in FDPIC mode"));
27902 case BFD_RELOC_ARM_GOT32
:
27903 case BFD_RELOC_ARM_GOTOFF
:
27906 case BFD_RELOC_ARM_GOT_PREL
:
27907 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27908 md_number_to_chars (buf
, value
, 4);
27911 case BFD_RELOC_ARM_TARGET2
:
27912 /* TARGET2 is not partial-inplace, so we need to write the
27913 addend here for REL targets, because it won't be written out
27914 during reloc processing later. */
27915 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27916 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
27919 /* Relocations for FDPIC. */
27920 case BFD_RELOC_ARM_GOTFUNCDESC
:
27921 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
27922 case BFD_RELOC_ARM_FUNCDESC
:
27925 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27926 md_number_to_chars (buf
, 0, 4);
27930 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27931 _("Relocation supported only in FDPIC mode"));
27936 case BFD_RELOC_RVA
:
27938 case BFD_RELOC_ARM_TARGET1
:
27939 case BFD_RELOC_ARM_ROSEGREL32
:
27940 case BFD_RELOC_ARM_SBREL32
:
27941 case BFD_RELOC_32_PCREL
:
27943 case BFD_RELOC_32_SECREL
:
27945 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27947 /* For WinCE we only do this for pcrel fixups. */
27948 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
27950 md_number_to_chars (buf
, value
, 4);
27954 case BFD_RELOC_ARM_PREL31
:
27955 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27957 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
27958 if ((value
^ (value
>> 1)) & 0x40000000)
27960 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27961 _("rel31 relocation overflow"));
27963 newval
|= value
& 0x7fffffff;
27964 md_number_to_chars (buf
, newval
, 4);
27969 case BFD_RELOC_ARM_CP_OFF_IMM
:
27970 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
27971 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
27972 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
27973 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27975 newval
= get_thumb32_insn (buf
);
27976 if ((newval
& 0x0f200f00) == 0x0d000900)
27978 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
27979 has permitted values that are multiples of 2, in the range 0
27981 if (value
< -510 || value
> 510 || (value
& 1))
27982 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27983 _("co-processor offset out of range"));
27985 else if ((newval
& 0xfe001f80) == 0xec000f80)
27987 if (value
< -511 || value
> 512 || (value
& 3))
27988 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27989 _("co-processor offset out of range"));
27991 else if (value
< -1023 || value
> 1023 || (value
& 3))
27992 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27993 _("co-processor offset out of range"));
27998 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
27999 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28000 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28002 newval
= get_thumb32_insn (buf
);
28005 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28006 newval
&= 0xffffff80;
28008 newval
&= 0xffffff00;
28012 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28013 newval
&= 0xff7fff80;
28015 newval
&= 0xff7fff00;
28016 if ((newval
& 0x0f200f00) == 0x0d000900)
28018 /* This is a fp16 vstr/vldr.
28020 It requires the immediate offset in the instruction is shifted
28021 left by 1 to be a half-word offset.
28023 Here, left shift by 1 first, and later right shift by 2
28024 should get the right offset. */
28027 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
28029 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28030 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28031 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28033 put_thumb32_insn (buf
, newval
);
28036 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
28037 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
28038 if (value
< -255 || value
> 255)
28039 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28040 _("co-processor offset out of range"));
28042 goto cp_off_common
;
28044 case BFD_RELOC_ARM_THUMB_OFFSET
:
28045 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28046 /* Exactly what ranges, and where the offset is inserted depends
28047 on the type of instruction, we can establish this from the
28049 switch (newval
>> 12)
28051 case 4: /* PC load. */
28052 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
28053 forced to zero for these loads; md_pcrel_from has already
28054 compensated for this. */
28056 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28057 _("invalid offset, target not word aligned (0x%08lX)"),
28058 (((unsigned long) fixP
->fx_frag
->fr_address
28059 + (unsigned long) fixP
->fx_where
) & ~3)
28060 + (unsigned long) value
);
28062 if (value
& ~0x3fc)
28063 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28064 _("invalid offset, value too big (0x%08lX)"),
28067 newval
|= value
>> 2;
28070 case 9: /* SP load/store. */
28071 if (value
& ~0x3fc)
28072 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28073 _("invalid offset, value too big (0x%08lX)"),
28075 newval
|= value
>> 2;
28078 case 6: /* Word load/store. */
28080 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28081 _("invalid offset, value too big (0x%08lX)"),
28083 newval
|= value
<< 4; /* 6 - 2. */
28086 case 7: /* Byte load/store. */
28088 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28089 _("invalid offset, value too big (0x%08lX)"),
28091 newval
|= value
<< 6;
28094 case 8: /* Halfword load/store. */
28096 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28097 _("invalid offset, value too big (0x%08lX)"),
28099 newval
|= value
<< 5; /* 6 - 1. */
28103 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28104 "Unable to process relocation for thumb opcode: %lx",
28105 (unsigned long) newval
);
28108 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28111 case BFD_RELOC_ARM_THUMB_ADD
:
28112 /* This is a complicated relocation, since we use it for all of
28113 the following immediate relocations:
28117 9bit ADD/SUB SP word-aligned
28118 10bit ADD PC/SP word-aligned
28120 The type of instruction being processed is encoded in the
28127 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28129 int rd
= (newval
>> 4) & 0xf;
28130 int rs
= newval
& 0xf;
28131 int subtract
= !!(newval
& 0x8000);
28133 /* Check for HI regs, only very restricted cases allowed:
28134 Adjusting SP, and using PC or SP to get an address. */
28135 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
28136 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
28137 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28138 _("invalid Hi register with immediate"));
28140 /* If value is negative, choose the opposite instruction. */
28144 subtract
= !subtract
;
28146 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28147 _("immediate value out of range"));
28152 if (value
& ~0x1fc)
28153 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28154 _("invalid immediate for stack address calculation"));
28155 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
28156 newval
|= value
>> 2;
28158 else if (rs
== REG_PC
|| rs
== REG_SP
)
28160 /* PR gas/18541. If the addition is for a defined symbol
28161 within range of an ADR instruction then accept it. */
28164 && fixP
->fx_addsy
!= NULL
)
28168 if (! S_IS_DEFINED (fixP
->fx_addsy
)
28169 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
28170 || S_IS_WEAK (fixP
->fx_addsy
))
28172 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28173 _("address calculation needs a strongly defined nearby symbol"));
28177 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
28179 /* Round up to the next 4-byte boundary. */
28184 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
28188 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28189 _("symbol too far away"));
28199 if (subtract
|| value
& ~0x3fc)
28200 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28201 _("invalid immediate for address calculation (value = 0x%08lX)"),
28202 (unsigned long) (subtract
? - value
: value
));
28203 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
28205 newval
|= value
>> 2;
28210 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28211 _("immediate value out of range"));
28212 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
28213 newval
|= (rd
<< 8) | value
;
28218 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28219 _("immediate value out of range"));
28220 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
28221 newval
|= rd
| (rs
<< 3) | (value
<< 6);
28224 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28227 case BFD_RELOC_ARM_THUMB_IMM
:
28228 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28229 if (value
< 0 || value
> 255)
28230 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28231 _("invalid immediate: %ld is out of range"),
28234 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28237 case BFD_RELOC_ARM_THUMB_SHIFT
:
28238 /* 5bit shift value (0..32). LSL cannot take 32. */
28239 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
28240 temp
= newval
& 0xf800;
28241 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
28242 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28243 _("invalid shift value: %ld"), (long) value
);
28244 /* Shifts of zero must be encoded as LSL. */
28246 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
28247 /* Shifts of 32 are encoded as zero. */
28248 else if (value
== 32)
28250 newval
|= value
<< 6;
28251 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28254 case BFD_RELOC_VTABLE_INHERIT
:
28255 case BFD_RELOC_VTABLE_ENTRY
:
28259 case BFD_RELOC_ARM_MOVW
:
28260 case BFD_RELOC_ARM_MOVT
:
28261 case BFD_RELOC_ARM_THUMB_MOVW
:
28262 case BFD_RELOC_ARM_THUMB_MOVT
:
28263 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28265 /* REL format relocations are limited to a 16-bit addend. */
28266 if (!fixP
->fx_done
)
28268 if (value
< -0x8000 || value
> 0x7fff)
28269 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28270 _("offset out of range"));
28272 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
28273 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28278 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
28279 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28281 newval
= get_thumb32_insn (buf
);
28282 newval
&= 0xfbf08f00;
28283 newval
|= (value
& 0xf000) << 4;
28284 newval
|= (value
& 0x0800) << 15;
28285 newval
|= (value
& 0x0700) << 4;
28286 newval
|= (value
& 0x00ff);
28287 put_thumb32_insn (buf
, newval
);
28291 newval
= md_chars_to_number (buf
, 4);
28292 newval
&= 0xfff0f000;
28293 newval
|= value
& 0x0fff;
28294 newval
|= (value
& 0xf000) << 4;
28295 md_number_to_chars (buf
, newval
, 4);
28300 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
28301 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
28302 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
28303 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
28304 gas_assert (!fixP
->fx_done
);
28307 bfd_boolean is_mov
;
28308 bfd_vma encoded_addend
= value
;
28310 /* Check that addend can be encoded in instruction. */
28311 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
28312 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28313 _("the offset 0x%08lX is not representable"),
28314 (unsigned long) encoded_addend
);
28316 /* Extract the instruction. */
28317 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
28318 is_mov
= (insn
& 0xf800) == 0x2000;
28323 if (!seg
->use_rela_p
)
28324 insn
|= encoded_addend
;
28330 /* Extract the instruction. */
28331 /* Encoding is the following
28336 /* The following conditions must be true :
28341 rd
= (insn
>> 4) & 0xf;
28343 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
28344 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28345 _("Unable to process relocation for thumb opcode: %lx"),
28346 (unsigned long) insn
);
28348 /* Encode as ADD immediate8 thumb 1 code. */
28349 insn
= 0x3000 | (rd
<< 8);
28351 /* Place the encoded addend into the first 8 bits of the
28353 if (!seg
->use_rela_p
)
28354 insn
|= encoded_addend
;
28357 /* Update the instruction. */
28358 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
28362 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
28363 case BFD_RELOC_ARM_ALU_PC_G0
:
28364 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
28365 case BFD_RELOC_ARM_ALU_PC_G1
:
28366 case BFD_RELOC_ARM_ALU_PC_G2
:
28367 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
28368 case BFD_RELOC_ARM_ALU_SB_G0
:
28369 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
28370 case BFD_RELOC_ARM_ALU_SB_G1
:
28371 case BFD_RELOC_ARM_ALU_SB_G2
:
28372 gas_assert (!fixP
->fx_done
);
28373 if (!seg
->use_rela_p
)
28376 bfd_vma encoded_addend
;
28377 bfd_vma addend_abs
= llabs (value
);
28379 /* Check that the absolute value of the addend can be
28380 expressed as an 8-bit constant plus a rotation. */
28381 encoded_addend
= encode_arm_immediate (addend_abs
);
28382 if (encoded_addend
== (unsigned int) FAIL
)
28383 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28384 _("the offset 0x%08lX is not representable"),
28385 (unsigned long) addend_abs
);
28387 /* Extract the instruction. */
28388 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28390 /* If the addend is positive, use an ADD instruction.
28391 Otherwise use a SUB. Take care not to destroy the S bit. */
28392 insn
&= 0xff1fffff;
28398 /* Place the encoded addend into the first 12 bits of the
28400 insn
&= 0xfffff000;
28401 insn
|= encoded_addend
;
28403 /* Update the instruction. */
28404 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28408 case BFD_RELOC_ARM_LDR_PC_G0
:
28409 case BFD_RELOC_ARM_LDR_PC_G1
:
28410 case BFD_RELOC_ARM_LDR_PC_G2
:
28411 case BFD_RELOC_ARM_LDR_SB_G0
:
28412 case BFD_RELOC_ARM_LDR_SB_G1
:
28413 case BFD_RELOC_ARM_LDR_SB_G2
:
28414 gas_assert (!fixP
->fx_done
);
28415 if (!seg
->use_rela_p
)
28418 bfd_vma addend_abs
= llabs (value
);
28420 /* Check that the absolute value of the addend can be
28421 encoded in 12 bits. */
28422 if (addend_abs
>= 0x1000)
28423 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28424 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
28425 (unsigned long) addend_abs
);
28427 /* Extract the instruction. */
28428 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28430 /* If the addend is negative, clear bit 23 of the instruction.
28431 Otherwise set it. */
28433 insn
&= ~(1 << 23);
28437 /* Place the absolute value of the addend into the first 12 bits
28438 of the instruction. */
28439 insn
&= 0xfffff000;
28440 insn
|= addend_abs
;
28442 /* Update the instruction. */
28443 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28447 case BFD_RELOC_ARM_LDRS_PC_G0
:
28448 case BFD_RELOC_ARM_LDRS_PC_G1
:
28449 case BFD_RELOC_ARM_LDRS_PC_G2
:
28450 case BFD_RELOC_ARM_LDRS_SB_G0
:
28451 case BFD_RELOC_ARM_LDRS_SB_G1
:
28452 case BFD_RELOC_ARM_LDRS_SB_G2
:
28453 gas_assert (!fixP
->fx_done
);
28454 if (!seg
->use_rela_p
)
28457 bfd_vma addend_abs
= llabs (value
);
28459 /* Check that the absolute value of the addend can be
28460 encoded in 8 bits. */
28461 if (addend_abs
>= 0x100)
28462 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28463 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
28464 (unsigned long) addend_abs
);
28466 /* Extract the instruction. */
28467 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28469 /* If the addend is negative, clear bit 23 of the instruction.
28470 Otherwise set it. */
28472 insn
&= ~(1 << 23);
28476 /* Place the first four bits of the absolute value of the addend
28477 into the first 4 bits of the instruction, and the remaining
28478 four into bits 8 .. 11. */
28479 insn
&= 0xfffff0f0;
28480 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
28482 /* Update the instruction. */
28483 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28487 case BFD_RELOC_ARM_LDC_PC_G0
:
28488 case BFD_RELOC_ARM_LDC_PC_G1
:
28489 case BFD_RELOC_ARM_LDC_PC_G2
:
28490 case BFD_RELOC_ARM_LDC_SB_G0
:
28491 case BFD_RELOC_ARM_LDC_SB_G1
:
28492 case BFD_RELOC_ARM_LDC_SB_G2
:
28493 gas_assert (!fixP
->fx_done
);
28494 if (!seg
->use_rela_p
)
28497 bfd_vma addend_abs
= llabs (value
);
28499 /* Check that the absolute value of the addend is a multiple of
28500 four and, when divided by four, fits in 8 bits. */
28501 if (addend_abs
& 0x3)
28502 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28503 _("bad offset 0x%08lX (must be word-aligned)"),
28504 (unsigned long) addend_abs
);
28506 if ((addend_abs
>> 2) > 0xff)
28507 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28508 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
28509 (unsigned long) addend_abs
);
28511 /* Extract the instruction. */
28512 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28514 /* If the addend is negative, clear bit 23 of the instruction.
28515 Otherwise set it. */
28517 insn
&= ~(1 << 23);
28521 /* Place the addend (divided by four) into the first eight
28522 bits of the instruction. */
28523 insn
&= 0xfffffff0;
28524 insn
|= addend_abs
>> 2;
28526 /* Update the instruction. */
28527 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28531 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
28533 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28534 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28535 && ARM_IS_FUNC (fixP
->fx_addsy
)
28536 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28538 /* Force a relocation for a branch 5 bits wide. */
28541 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
28542 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28545 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28547 addressT boff
= value
>> 1;
28549 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28550 newval
|= (boff
<< 7);
28551 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28555 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
28557 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28558 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28559 && ARM_IS_FUNC (fixP
->fx_addsy
)
28560 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28564 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
28565 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28566 _("branch out of range"));
28568 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28570 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28572 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
28573 addressT diff
= value
- boff
;
28577 newval
|= 1 << 1; /* T bit. */
28579 else if (diff
!= 2)
28581 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28582 _("out of range label-relative fixup value"));
28584 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28588 case BFD_RELOC_ARM_THUMB_BF17
:
28590 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28591 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28592 && ARM_IS_FUNC (fixP
->fx_addsy
)
28593 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28595 /* Force a relocation for a branch 17 bits wide. */
28599 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
28600 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28603 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28606 addressT immA
, immB
, immC
;
28608 immA
= (value
& 0x0001f000) >> 12;
28609 immB
= (value
& 0x00000ffc) >> 2;
28610 immC
= (value
& 0x00000002) >> 1;
28612 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28613 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28615 newval2
|= (immC
<< 11) | (immB
<< 1);
28616 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28617 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28621 case BFD_RELOC_ARM_THUMB_BF19
:
28623 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28624 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28625 && ARM_IS_FUNC (fixP
->fx_addsy
)
28626 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28628 /* Force a relocation for a branch 19 bits wide. */
28632 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
28633 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28636 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28639 addressT immA
, immB
, immC
;
28641 immA
= (value
& 0x0007f000) >> 12;
28642 immB
= (value
& 0x00000ffc) >> 2;
28643 immC
= (value
& 0x00000002) >> 1;
28645 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28646 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28648 newval2
|= (immC
<< 11) | (immB
<< 1);
28649 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28650 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28654 case BFD_RELOC_ARM_THUMB_BF13
:
28656 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28657 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28658 && ARM_IS_FUNC (fixP
->fx_addsy
)
28659 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28661 /* Force a relocation for a branch 13 bits wide. */
28665 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
28666 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28669 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28672 addressT immA
, immB
, immC
;
28674 immA
= (value
& 0x00001000) >> 12;
28675 immB
= (value
& 0x00000ffc) >> 2;
28676 immC
= (value
& 0x00000002) >> 1;
28678 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28679 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28681 newval2
|= (immC
<< 11) | (immB
<< 1);
28682 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28683 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28687 case BFD_RELOC_ARM_THUMB_LOOP12
:
28689 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28690 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28691 && ARM_IS_FUNC (fixP
->fx_addsy
)
28692 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28694 /* Force a relocation for a branch 12 bits wide. */
28698 bfd_vma insn
= get_thumb32_insn (buf
);
28699 /* le lr, <label>, le <label> or letp lr, <label> */
28700 if (((insn
& 0xffffffff) == 0xf00fc001)
28701 || ((insn
& 0xffffffff) == 0xf02fc001)
28702 || ((insn
& 0xffffffff) == 0xf01fc001))
28705 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
28706 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28708 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28710 addressT imml
, immh
;
28712 immh
= (value
& 0x00000ffc) >> 2;
28713 imml
= (value
& 0x00000002) >> 1;
28715 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28716 newval
|= (imml
<< 11) | (immh
<< 1);
28717 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
28721 case BFD_RELOC_ARM_V4BX
:
28722 /* This will need to go in the object file. */
28726 case BFD_RELOC_UNUSED
:
28728 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28729 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
28733 /* Translate internal representation of relocation info to BFD target
28737 tc_gen_reloc (asection
*section
, fixS
*fixp
)
28740 bfd_reloc_code_real_type code
;
28742 reloc
= XNEW (arelent
);
28744 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
28745 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
28746 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
28748 if (fixp
->fx_pcrel
)
28750 if (section
->use_rela_p
)
28751 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
28753 fixp
->fx_offset
= reloc
->address
;
28755 reloc
->addend
= fixp
->fx_offset
;
28757 switch (fixp
->fx_r_type
)
28760 if (fixp
->fx_pcrel
)
28762 code
= BFD_RELOC_8_PCREL
;
28765 /* Fall through. */
28768 if (fixp
->fx_pcrel
)
28770 code
= BFD_RELOC_16_PCREL
;
28773 /* Fall through. */
28776 if (fixp
->fx_pcrel
)
28778 code
= BFD_RELOC_32_PCREL
;
28781 /* Fall through. */
28783 case BFD_RELOC_ARM_MOVW
:
28784 if (fixp
->fx_pcrel
)
28786 code
= BFD_RELOC_ARM_MOVW_PCREL
;
28789 /* Fall through. */
28791 case BFD_RELOC_ARM_MOVT
:
28792 if (fixp
->fx_pcrel
)
28794 code
= BFD_RELOC_ARM_MOVT_PCREL
;
28797 /* Fall through. */
28799 case BFD_RELOC_ARM_THUMB_MOVW
:
28800 if (fixp
->fx_pcrel
)
28802 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
28805 /* Fall through. */
28807 case BFD_RELOC_ARM_THUMB_MOVT
:
28808 if (fixp
->fx_pcrel
)
28810 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
28813 /* Fall through. */
28815 case BFD_RELOC_NONE
:
28816 case BFD_RELOC_ARM_PCREL_BRANCH
:
28817 case BFD_RELOC_ARM_PCREL_BLX
:
28818 case BFD_RELOC_RVA
:
28819 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
28820 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
28821 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
28822 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
28823 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28824 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
28825 case BFD_RELOC_VTABLE_ENTRY
:
28826 case BFD_RELOC_VTABLE_INHERIT
:
28828 case BFD_RELOC_32_SECREL
:
28830 code
= fixp
->fx_r_type
;
28833 case BFD_RELOC_THUMB_PCREL_BLX
:
28835 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
28836 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28839 code
= BFD_RELOC_THUMB_PCREL_BLX
;
28842 case BFD_RELOC_ARM_LITERAL
:
28843 case BFD_RELOC_ARM_HWLITERAL
:
28844 /* If this is called then the a literal has
28845 been referenced across a section boundary. */
28846 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28847 _("literal referenced across section boundary"));
28851 case BFD_RELOC_ARM_TLS_CALL
:
28852 case BFD_RELOC_ARM_THM_TLS_CALL
:
28853 case BFD_RELOC_ARM_TLS_DESCSEQ
:
28854 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
28855 case BFD_RELOC_ARM_GOT32
:
28856 case BFD_RELOC_ARM_GOTOFF
:
28857 case BFD_RELOC_ARM_GOT_PREL
:
28858 case BFD_RELOC_ARM_PLT32
:
28859 case BFD_RELOC_ARM_TARGET1
:
28860 case BFD_RELOC_ARM_ROSEGREL32
:
28861 case BFD_RELOC_ARM_SBREL32
:
28862 case BFD_RELOC_ARM_PREL31
:
28863 case BFD_RELOC_ARM_TARGET2
:
28864 case BFD_RELOC_ARM_TLS_LDO32
:
28865 case BFD_RELOC_ARM_PCREL_CALL
:
28866 case BFD_RELOC_ARM_PCREL_JUMP
:
28867 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
28868 case BFD_RELOC_ARM_ALU_PC_G0
:
28869 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
28870 case BFD_RELOC_ARM_ALU_PC_G1
:
28871 case BFD_RELOC_ARM_ALU_PC_G2
:
28872 case BFD_RELOC_ARM_LDR_PC_G0
:
28873 case BFD_RELOC_ARM_LDR_PC_G1
:
28874 case BFD_RELOC_ARM_LDR_PC_G2
:
28875 case BFD_RELOC_ARM_LDRS_PC_G0
:
28876 case BFD_RELOC_ARM_LDRS_PC_G1
:
28877 case BFD_RELOC_ARM_LDRS_PC_G2
:
28878 case BFD_RELOC_ARM_LDC_PC_G0
:
28879 case BFD_RELOC_ARM_LDC_PC_G1
:
28880 case BFD_RELOC_ARM_LDC_PC_G2
:
28881 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
28882 case BFD_RELOC_ARM_ALU_SB_G0
:
28883 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
28884 case BFD_RELOC_ARM_ALU_SB_G1
:
28885 case BFD_RELOC_ARM_ALU_SB_G2
:
28886 case BFD_RELOC_ARM_LDR_SB_G0
:
28887 case BFD_RELOC_ARM_LDR_SB_G1
:
28888 case BFD_RELOC_ARM_LDR_SB_G2
:
28889 case BFD_RELOC_ARM_LDRS_SB_G0
:
28890 case BFD_RELOC_ARM_LDRS_SB_G1
:
28891 case BFD_RELOC_ARM_LDRS_SB_G2
:
28892 case BFD_RELOC_ARM_LDC_SB_G0
:
28893 case BFD_RELOC_ARM_LDC_SB_G1
:
28894 case BFD_RELOC_ARM_LDC_SB_G2
:
28895 case BFD_RELOC_ARM_V4BX
:
28896 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
28897 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
28898 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
28899 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
28900 case BFD_RELOC_ARM_GOTFUNCDESC
:
28901 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
28902 case BFD_RELOC_ARM_FUNCDESC
:
28903 case BFD_RELOC_ARM_THUMB_BF17
:
28904 case BFD_RELOC_ARM_THUMB_BF19
:
28905 case BFD_RELOC_ARM_THUMB_BF13
:
28906 code
= fixp
->fx_r_type
;
28909 case BFD_RELOC_ARM_TLS_GOTDESC
:
28910 case BFD_RELOC_ARM_TLS_GD32
:
28911 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
28912 case BFD_RELOC_ARM_TLS_LE32
:
28913 case BFD_RELOC_ARM_TLS_IE32
:
28914 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
28915 case BFD_RELOC_ARM_TLS_LDM32
:
28916 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
28917 /* BFD will include the symbol's address in the addend.
28918 But we don't want that, so subtract it out again here. */
28919 if (!S_IS_COMMON (fixp
->fx_addsy
))
28920 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
28921 code
= fixp
->fx_r_type
;
28925 case BFD_RELOC_ARM_IMMEDIATE
:
28926 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28927 _("internal relocation (type: IMMEDIATE) not fixed up"));
28930 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
28931 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28932 _("ADRL used for a symbol not defined in the same file"));
28935 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
28936 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
28937 case BFD_RELOC_ARM_THUMB_LOOP12
:
28938 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28939 _("%s used for a symbol not defined in the same file"),
28940 bfd_get_reloc_code_name (fixp
->fx_r_type
));
28943 case BFD_RELOC_ARM_OFFSET_IMM
:
28944 if (section
->use_rela_p
)
28946 code
= fixp
->fx_r_type
;
28950 if (fixp
->fx_addsy
!= NULL
28951 && !S_IS_DEFINED (fixp
->fx_addsy
)
28952 && S_IS_LOCAL (fixp
->fx_addsy
))
28954 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28955 _("undefined local label `%s'"),
28956 S_GET_NAME (fixp
->fx_addsy
));
28960 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28961 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
28968 switch (fixp
->fx_r_type
)
28970 case BFD_RELOC_NONE
: type
= "NONE"; break;
28971 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
28972 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
28973 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
28974 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
28975 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
28976 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
28977 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
28978 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
28979 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
28980 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
28981 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
28982 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
28983 default: type
= _("<unknown>"); break;
28985 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
28986 _("cannot represent %s relocation in this object file format"),
28993 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
28995 && fixp
->fx_addsy
== GOT_symbol
)
28997 code
= BFD_RELOC_ARM_GOTPC
;
28998 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
29002 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
29004 if (reloc
->howto
== NULL
)
29006 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29007 _("cannot represent %s relocation in this object file format"),
29008 bfd_get_reloc_code_name (code
));
29012 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
29013 vtable entry to be used in the relocation's section offset. */
29014 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29015 reloc
->address
= fixp
->fx_offset
;
29020 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
29023 cons_fix_new_arm (fragS
* frag
,
29027 bfd_reloc_code_real_type reloc
)
29032 FIXME: @@ Should look at CPU word size. */
29036 reloc
= BFD_RELOC_8
;
29039 reloc
= BFD_RELOC_16
;
29043 reloc
= BFD_RELOC_32
;
29046 reloc
= BFD_RELOC_64
;
29051 if (exp
->X_op
== O_secrel
)
29053 exp
->X_op
= O_symbol
;
29054 reloc
= BFD_RELOC_32_SECREL
;
29058 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
29061 #if defined (OBJ_COFF)
29063 arm_validate_fix (fixS
* fixP
)
29065 /* If the destination of the branch is a defined symbol which does not have
29066 the THUMB_FUNC attribute, then we must be calling a function which has
29067 the (interfacearm) attribute. We look for the Thumb entry point to that
29068 function and change the branch to refer to that function instead. */
29069 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
29070 && fixP
->fx_addsy
!= NULL
29071 && S_IS_DEFINED (fixP
->fx_addsy
)
29072 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
29074 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
29081 arm_force_relocation (struct fix
* fixp
)
29083 #if defined (OBJ_COFF) && defined (TE_PE)
29084 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
29088 /* In case we have a call or a branch to a function in ARM ISA mode from
29089 a thumb function or vice-versa force the relocation. These relocations
29090 are cleared off for some cores that might have blx and simple transformations
29094 switch (fixp
->fx_r_type
)
29096 case BFD_RELOC_ARM_PCREL_JUMP
:
29097 case BFD_RELOC_ARM_PCREL_CALL
:
29098 case BFD_RELOC_THUMB_PCREL_BLX
:
29099 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
29103 case BFD_RELOC_ARM_PCREL_BLX
:
29104 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29105 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29106 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29107 if (ARM_IS_FUNC (fixp
->fx_addsy
))
29116 /* Resolve these relocations even if the symbol is extern or weak.
29117 Technically this is probably wrong due to symbol preemption.
29118 In practice these relocations do not have enough range to be useful
29119 at dynamic link time, and some code (e.g. in the Linux kernel)
29120 expects these references to be resolved. */
29121 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
29122 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
29123 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
29124 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
29125 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29126 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
29127 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
29128 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
29129 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
29130 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
29131 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
29132 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
29133 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
29134 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
29137 /* Always leave these relocations for the linker. */
29138 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29139 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29140 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29143 /* Always generate relocations against function symbols. */
29144 if (fixp
->fx_r_type
== BFD_RELOC_32
29146 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
29149 return generic_force_reloc (fixp
);
29152 #if defined (OBJ_ELF) || defined (OBJ_COFF)
29153 /* Relocations against function names must be left unadjusted,
29154 so that the linker can use this information to generate interworking
29155 stubs. The MIPS version of this function
29156 also prevents relocations that are mips-16 specific, but I do not
29157 know why it does this.
29160 There is one other problem that ought to be addressed here, but
29161 which currently is not: Taking the address of a label (rather
29162 than a function) and then later jumping to that address. Such
29163 addresses also ought to have their bottom bit set (assuming that
29164 they reside in Thumb code), but at the moment they will not. */
29167 arm_fix_adjustable (fixS
* fixP
)
29169 if (fixP
->fx_addsy
== NULL
)
29172 /* Preserve relocations against symbols with function type. */
29173 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
29176 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
29177 && fixP
->fx_subsy
== NULL
)
29180 /* We need the symbol name for the VTABLE entries. */
29181 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
29182 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29185 /* Don't allow symbols to be discarded on GOT related relocs. */
29186 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
29187 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
29188 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
29189 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
29190 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
29191 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
29192 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
29193 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
29194 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
29195 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
29196 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
29197 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
29198 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
29199 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
29200 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
29201 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
29202 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
29205 /* Similarly for group relocations. */
29206 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29207 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29208 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29211 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
29212 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
29213 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
29214 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
29215 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
29216 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
29217 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
29218 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
29219 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
29222 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
29223 offsets, so keep these symbols. */
29224 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
29225 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
29230 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
29234 elf32_arm_target_format (void)
29237 return (target_big_endian
29238 ? "elf32-bigarm-symbian"
29239 : "elf32-littlearm-symbian");
29240 #elif defined (TE_VXWORKS)
29241 return (target_big_endian
29242 ? "elf32-bigarm-vxworks"
29243 : "elf32-littlearm-vxworks");
29244 #elif defined (TE_NACL)
29245 return (target_big_endian
29246 ? "elf32-bigarm-nacl"
29247 : "elf32-littlearm-nacl");
29251 if (target_big_endian
)
29252 return "elf32-bigarm-fdpic";
29254 return "elf32-littlearm-fdpic";
29258 if (target_big_endian
)
29259 return "elf32-bigarm";
29261 return "elf32-littlearm";
29267 armelf_frob_symbol (symbolS
* symp
,
29270 elf_frob_symbol (symp
, puntp
);
29274 /* MD interface: Finalization. */
29279 literal_pool
* pool
;
29281 /* Ensure that all the predication blocks are properly closed. */
29282 check_pred_blocks_finished ();
29284 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
29286 /* Put it at the end of the relevant section. */
29287 subseg_set (pool
->section
, pool
->sub_section
);
29289 arm_elf_change_section ();
29296 /* Remove any excess mapping symbols generated for alignment frags in
29297 SEC. We may have created a mapping symbol before a zero byte
29298 alignment; remove it if there's a mapping symbol after the
29301 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
29302 void *dummy ATTRIBUTE_UNUSED
)
29304 segment_info_type
*seginfo
= seg_info (sec
);
29307 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
29310 for (fragp
= seginfo
->frchainP
->frch_root
;
29312 fragp
= fragp
->fr_next
)
29314 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
29315 fragS
*next
= fragp
->fr_next
;
29317 /* Variable-sized frags have been converted to fixed size by
29318 this point. But if this was variable-sized to start with,
29319 there will be a fixed-size frag after it. So don't handle
29321 if (sym
== NULL
|| next
== NULL
)
29324 if (S_GET_VALUE (sym
) < next
->fr_address
)
29325 /* Not at the end of this frag. */
29327 know (S_GET_VALUE (sym
) == next
->fr_address
);
29331 if (next
->tc_frag_data
.first_map
!= NULL
)
29333 /* Next frag starts with a mapping symbol. Discard this
29335 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29339 if (next
->fr_next
== NULL
)
29341 /* This mapping symbol is at the end of the section. Discard
29343 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
29344 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29348 /* As long as we have empty frags without any mapping symbols,
29350 /* If the next frag is non-empty and does not start with a
29351 mapping symbol, then this mapping symbol is required. */
29352 if (next
->fr_address
!= next
->fr_next
->fr_address
)
29355 next
= next
->fr_next
;
29357 while (next
!= NULL
);
29362 /* Adjust the symbol table. This marks Thumb symbols as distinct from
29366 arm_adjust_symtab (void)
29371 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29373 if (ARM_IS_THUMB (sym
))
29375 if (THUMB_IS_FUNC (sym
))
29377 /* Mark the symbol as a Thumb function. */
29378 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
29379 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
29380 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
29382 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
29383 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
29385 as_bad (_("%s: unexpected function type: %d"),
29386 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
29388 else switch (S_GET_STORAGE_CLASS (sym
))
29391 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
29394 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
29397 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
29405 if (ARM_IS_INTERWORK (sym
))
29406 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
29413 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29415 if (ARM_IS_THUMB (sym
))
29417 elf_symbol_type
* elf_sym
;
29419 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
29420 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
29422 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
29423 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
29425 /* If it's a .thumb_func, declare it as so,
29426 otherwise tag label as .code 16. */
29427 if (THUMB_IS_FUNC (sym
))
29428 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
29429 ST_BRANCH_TO_THUMB
);
29430 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
29431 elf_sym
->internal_elf_sym
.st_info
=
29432 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
29437 /* Remove any overlapping mapping symbols generated by alignment frags. */
29438 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
29439 /* Now do generic ELF adjustments. */
29440 elf_adjust_symtab ();
29444 /* MD interface: Initialization. */
29447 set_constant_flonums (void)
29451 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
29452 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
29456 /* Auto-select Thumb mode if it's the only available instruction set for the
29457 given architecture. */
29460 autoselect_thumb_from_cpu_variant (void)
29462 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
29463 opcode_select (16);
29472 if ( (arm_ops_hsh
= hash_new ()) == NULL
29473 || (arm_cond_hsh
= hash_new ()) == NULL
29474 || (arm_vcond_hsh
= hash_new ()) == NULL
29475 || (arm_shift_hsh
= hash_new ()) == NULL
29476 || (arm_psr_hsh
= hash_new ()) == NULL
29477 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
29478 || (arm_reg_hsh
= hash_new ()) == NULL
29479 || (arm_reloc_hsh
= hash_new ()) == NULL
29480 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
29481 as_fatal (_("virtual memory exhausted"));
29483 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
29484 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
29485 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
29486 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
29487 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
29488 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
29489 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
29490 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
29491 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
29492 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
29493 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
29494 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
29495 (void *) (v7m_psrs
+ i
));
29496 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
29497 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
29499 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
29501 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
29502 (void *) (barrier_opt_names
+ i
));
29504 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
29506 struct reloc_entry
* entry
= reloc_names
+ i
;
29508 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
29509 /* This makes encode_branch() use the EABI versions of this relocation. */
29510 entry
->reloc
= BFD_RELOC_UNUSED
;
29512 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
29516 set_constant_flonums ();
29518 /* Set the cpu variant based on the command-line options. We prefer
29519 -mcpu= over -march= if both are set (as for GCC); and we prefer
29520 -mfpu= over any other way of setting the floating point unit.
29521 Use of legacy options with new options are faulted. */
29524 if (mcpu_cpu_opt
|| march_cpu_opt
)
29525 as_bad (_("use of old and new-style options to set CPU type"));
29527 selected_arch
= *legacy_cpu
;
29529 else if (mcpu_cpu_opt
)
29531 selected_arch
= *mcpu_cpu_opt
;
29532 selected_ext
= *mcpu_ext_opt
;
29534 else if (march_cpu_opt
)
29536 selected_arch
= *march_cpu_opt
;
29537 selected_ext
= *march_ext_opt
;
29539 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
29544 as_bad (_("use of old and new-style options to set FPU type"));
29546 selected_fpu
= *legacy_fpu
;
29549 selected_fpu
= *mfpu_opt
;
29552 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
29553 || defined (TE_NetBSD) || defined (TE_VXWORKS))
29554 /* Some environments specify a default FPU. If they don't, infer it
29555 from the processor. */
29557 selected_fpu
= *mcpu_fpu_opt
;
29558 else if (march_fpu_opt
)
29559 selected_fpu
= *march_fpu_opt
;
29561 selected_fpu
= fpu_default
;
29565 if (ARM_FEATURE_ZERO (selected_fpu
))
29567 if (!no_cpu_selected ())
29568 selected_fpu
= fpu_default
;
29570 selected_fpu
= fpu_arch_fpa
;
29574 if (ARM_FEATURE_ZERO (selected_arch
))
29576 selected_arch
= cpu_default
;
29577 selected_cpu
= selected_arch
;
29579 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29581 /* Autodection of feature mode: allow all features in cpu_variant but leave
29582 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
29583 after all instruction have been processed and we can decide what CPU
29584 should be selected. */
29585 if (ARM_FEATURE_ZERO (selected_arch
))
29586 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
29588 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29591 autoselect_thumb_from_cpu_variant ();
29593 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
29595 #if defined OBJ_COFF || defined OBJ_ELF
29597 unsigned int flags
= 0;
29599 #if defined OBJ_ELF
29600 flags
= meabi_flags
;
29602 switch (meabi_flags
)
29604 case EF_ARM_EABI_UNKNOWN
:
29606 /* Set the flags in the private structure. */
29607 if (uses_apcs_26
) flags
|= F_APCS26
;
29608 if (support_interwork
) flags
|= F_INTERWORK
;
29609 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
29610 if (pic_code
) flags
|= F_PIC
;
29611 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
29612 flags
|= F_SOFT_FLOAT
;
29614 switch (mfloat_abi_opt
)
29616 case ARM_FLOAT_ABI_SOFT
:
29617 case ARM_FLOAT_ABI_SOFTFP
:
29618 flags
|= F_SOFT_FLOAT
;
29621 case ARM_FLOAT_ABI_HARD
:
29622 if (flags
& F_SOFT_FLOAT
)
29623 as_bad (_("hard-float conflicts with specified fpu"));
29627 /* Using pure-endian doubles (even if soft-float). */
29628 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
29629 flags
|= F_VFP_FLOAT
;
29631 #if defined OBJ_ELF
29632 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
29633 flags
|= EF_ARM_MAVERICK_FLOAT
;
29636 case EF_ARM_EABI_VER4
:
29637 case EF_ARM_EABI_VER5
:
29638 /* No additional flags to set. */
29645 bfd_set_private_flags (stdoutput
, flags
);
29647 /* We have run out flags in the COFF header to encode the
29648 status of ATPCS support, so instead we create a dummy,
29649 empty, debug section called .arm.atpcs. */
29654 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
29658 bfd_set_section_flags
29659 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
29660 bfd_set_section_size (stdoutput
, sec
, 0);
29661 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
29667 /* Record the CPU type as well. */
29668 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
29669 mach
= bfd_mach_arm_iWMMXt2
;
29670 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
29671 mach
= bfd_mach_arm_iWMMXt
;
29672 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
29673 mach
= bfd_mach_arm_XScale
;
29674 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
29675 mach
= bfd_mach_arm_ep9312
;
29676 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
29677 mach
= bfd_mach_arm_5TE
;
29678 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
29680 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
29681 mach
= bfd_mach_arm_5T
;
29683 mach
= bfd_mach_arm_5
;
29685 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
29687 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
29688 mach
= bfd_mach_arm_4T
;
29690 mach
= bfd_mach_arm_4
;
29692 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
29693 mach
= bfd_mach_arm_3M
;
29694 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
29695 mach
= bfd_mach_arm_3
;
29696 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
29697 mach
= bfd_mach_arm_2a
;
29698 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
29699 mach
= bfd_mach_arm_2
;
29701 mach
= bfd_mach_arm_unknown
;
29703 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
29706 /* Command line processing. */
29709 Invocation line includes a switch not recognized by the base assembler.
29710 See if it's a processor-specific option.
29712 This routine is somewhat complicated by the need for backwards
29713 compatibility (since older releases of gcc can't be changed).
29714 The new options try to make the interface as compatible as
29717 New options (supported) are:
29719 -mcpu=<cpu name> Assemble for selected processor
29720 -march=<architecture name> Assemble for selected architecture
29721 -mfpu=<fpu architecture> Assemble for selected FPU.
29722 -EB/-mbig-endian Big-endian
29723 -EL/-mlittle-endian Little-endian
29724 -k Generate PIC code
29725 -mthumb Start in Thumb mode
29726 -mthumb-interwork Code supports ARM/Thumb interworking
29728 -m[no-]warn-deprecated Warn about deprecated features
29729 -m[no-]warn-syms Warn when symbols match instructions
29731 For now we will also provide support for:
29733 -mapcs-32 32-bit Program counter
29734 -mapcs-26 26-bit Program counter
29735 -macps-float Floats passed in FP registers
29736 -mapcs-reentrant Reentrant code
29738 (sometime these will probably be replaced with -mapcs=<list of options>
29739 and -matpcs=<list of options>)
29741 The remaining options are only supported for back-wards compatibility.
29742 Cpu variants, the arm part is optional:
29743 -m[arm]1 Currently not supported.
29744 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
29745 -m[arm]3 Arm 3 processor
29746 -m[arm]6[xx], Arm 6 processors
29747 -m[arm]7[xx][t][[d]m] Arm 7 processors
29748 -m[arm]8[10] Arm 8 processors
29749 -m[arm]9[20][tdmi] Arm 9 processors
29750 -mstrongarm[110[0]] StrongARM processors
29751 -mxscale XScale processors
29752 -m[arm]v[2345[t[e]]] Arm architectures
29753 -mall All (except the ARM1)
29755 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
29756 -mfpe-old (No float load/store multiples)
29757 -mvfpxd VFP Single precision
29759 -mno-fpu Disable all floating point instructions
29761 The following CPU names are recognized:
29762 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
29763 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
29764 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
29765 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
29766 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
29767 arm10t arm10e, arm1020t, arm1020e, arm10200e,
29768 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
29772 const char * md_shortopts
= "m:k";
29774 #ifdef ARM_BI_ENDIAN
29775 #define OPTION_EB (OPTION_MD_BASE + 0)
29776 #define OPTION_EL (OPTION_MD_BASE + 1)
29778 #if TARGET_BYTES_BIG_ENDIAN
29779 #define OPTION_EB (OPTION_MD_BASE + 0)
29781 #define OPTION_EL (OPTION_MD_BASE + 1)
29784 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
29785 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
29787 struct option md_longopts
[] =
29790 {"EB", no_argument
, NULL
, OPTION_EB
},
29793 {"EL", no_argument
, NULL
, OPTION_EL
},
29795 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
29797 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
29799 {NULL
, no_argument
, NULL
, 0}
29802 size_t md_longopts_size
= sizeof (md_longopts
);
29804 struct arm_option_table
29806 const char * option
; /* Option name to match. */
29807 const char * help
; /* Help information. */
29808 int * var
; /* Variable to change. */
29809 int value
; /* What to change it to. */
29810 const char * deprecated
; /* If non-null, print this message. */
29813 struct arm_option_table arm_opts
[] =
29815 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
29816 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
29817 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
29818 &support_interwork
, 1, NULL
},
29819 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
29820 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
29821 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
29823 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
29824 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
29825 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
29826 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
29829 /* These are recognized by the assembler, but have no affect on code. */
29830 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
29831 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
29833 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
29834 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
29835 &warn_on_deprecated
, 0, NULL
},
29836 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
29837 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
29838 {NULL
, NULL
, NULL
, 0, NULL
}
29841 struct arm_legacy_option_table
29843 const char * option
; /* Option name to match. */
29844 const arm_feature_set
** var
; /* Variable to change. */
29845 const arm_feature_set value
; /* What to change it to. */
29846 const char * deprecated
; /* If non-null, print this message. */
29849 const struct arm_legacy_option_table arm_legacy_opts
[] =
29851 /* DON'T add any new processors to this list -- we want the whole list
29852 to go away... Add them to the processors table instead. */
29853 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
29854 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
29855 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
29856 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
29857 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
29858 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
29859 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
29860 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
29861 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
29862 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
29863 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
29864 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
29865 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
29866 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
29867 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
29868 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
29869 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
29870 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
29871 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
29872 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
29873 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
29874 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
29875 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
29876 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
29877 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
29878 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
29879 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
29880 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
29881 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
29882 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
29883 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
29884 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
29885 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
29886 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
29887 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
29888 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
29889 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
29890 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
29891 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
29892 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
29893 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
29894 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
29895 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
29896 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
29897 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
29898 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
29899 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29900 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29901 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29902 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
29903 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
29904 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
29905 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
29906 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
29907 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
29908 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
29909 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
29910 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
29911 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
29912 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
29913 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
29914 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
29915 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
29916 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
29917 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
29918 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
29919 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
29920 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
29921 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
29922 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
29923 N_("use -mcpu=strongarm110")},
29924 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
29925 N_("use -mcpu=strongarm1100")},
29926 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
29927 N_("use -mcpu=strongarm1110")},
29928 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
29929 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
29930 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
29932 /* Architecture variants -- don't add any more to this list either. */
29933 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
29934 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
29935 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
29936 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
29937 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
29938 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
29939 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
29940 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
29941 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
29942 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
29943 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
29944 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
29945 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
29946 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
29947 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
29948 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
29949 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
29950 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
29952 /* Floating point variants -- don't add any more to this list either. */
29953 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
29954 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
29955 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
29956 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
29957 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
29959 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
29962 struct arm_cpu_option_table
29966 const arm_feature_set value
;
29967 const arm_feature_set ext
;
29968 /* For some CPUs we assume an FPU unless the user explicitly sets
29970 const arm_feature_set default_fpu
;
29971 /* The canonical name of the CPU, or NULL to use NAME converted to upper
29973 const char * canonical_name
;
29976 /* This list should, at a minimum, contain all the cpu names
29977 recognized by GCC. */
29978 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
29980 static const struct arm_cpu_option_table arm_cpus
[] =
29982 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
29985 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
29988 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
29991 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
29994 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
29997 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
30000 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
30003 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
30006 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
30009 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
30012 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
30015 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
30018 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
30021 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
30024 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
30027 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
30030 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
30033 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
30036 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
30039 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
30042 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
30045 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
30048 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
30051 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
30054 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
30057 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
30060 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
30063 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
30066 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
30069 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
30072 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
30075 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
30078 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
30081 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
30084 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
30087 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
30090 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
30093 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
30096 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
30099 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
30102 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
30105 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
30108 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
30111 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
30114 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
30117 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
30121 /* For V5 or later processors we default to using VFP; but the user
30122 should really set the FPU type explicitly. */
30123 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
30126 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
30129 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30132 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30135 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
30138 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
30141 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
30144 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
30147 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
30150 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
30153 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
30156 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
30159 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
30162 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
30165 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
30168 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
30171 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
30174 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
30177 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
30180 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
30183 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
30186 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
30189 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
30192 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
30195 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
30198 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
30201 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
30204 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
30207 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
30210 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
30213 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
30216 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
30219 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
30222 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
30225 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
30228 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
30231 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
30232 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30234 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
30236 FPU_ARCH_NEON_VFP_V4
),
30237 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
30238 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30239 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30240 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
30241 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30242 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30243 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
30245 FPU_ARCH_NEON_VFP_V4
),
30246 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
30248 FPU_ARCH_NEON_VFP_V4
),
30249 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
30251 FPU_ARCH_NEON_VFP_V4
),
30252 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
30253 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30254 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30255 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
30256 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30257 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30258 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
30259 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30260 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30261 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
30262 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30263 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30264 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
30265 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30266 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30267 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
30268 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30269 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30270 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
30271 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30272 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30273 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
30274 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30275 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30276 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
30277 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30278 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30279 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
30280 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30281 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30282 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
30285 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
30287 FPU_ARCH_VFP_V3D16
),
30288 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
30289 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30291 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
30292 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30293 FPU_ARCH_VFP_V3D16
),
30294 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
30295 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30296 FPU_ARCH_VFP_V3D16
),
30297 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
30298 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30299 FPU_ARCH_NEON_VFP_ARMV8
),
30300 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
30301 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30303 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
30306 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
30309 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
30312 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
30315 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
30318 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
30321 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
30324 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
30325 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30326 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30327 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
30328 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30329 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30330 /* ??? XSCALE is really an architecture. */
30331 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
30335 /* ??? iwmmxt is not a processor. */
30336 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
30339 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
30342 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
30347 ARM_CPU_OPT ("ep9312", "ARM920T",
30348 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
30349 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
30351 /* Marvell processors. */
30352 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
30353 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30354 FPU_ARCH_VFP_V3D16
),
30355 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
30356 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30357 FPU_ARCH_NEON_VFP_V4
),
30359 /* APM X-Gene family. */
30360 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
30362 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30363 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
30364 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30365 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30367 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30371 struct arm_ext_table
30375 const arm_feature_set merge
;
30376 const arm_feature_set clear
;
30379 struct arm_arch_option_table
30383 const arm_feature_set value
;
30384 const arm_feature_set default_fpu
;
30385 const struct arm_ext_table
* ext_table
;
30388 /* Used to add support for +E and +noE extension. */
30389 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
30390 /* Used to add support for a +E extension. */
30391 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
30392 /* Used to add support for a +noE extension. */
30393 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
30395 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
30396 ~0 & ~FPU_ENDIAN_PURE)
30398 static const struct arm_ext_table armv5te_ext_table
[] =
30400 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
30401 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30404 static const struct arm_ext_table armv7_ext_table
[] =
30406 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30407 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30410 static const struct arm_ext_table armv7ve_ext_table
[] =
30412 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
30413 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
30414 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30415 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30416 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30417 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
30418 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30420 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
30421 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30423 /* Aliases for +simd. */
30424 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30426 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30427 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30428 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30430 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30433 static const struct arm_ext_table armv7a_ext_table
[] =
30435 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30436 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30437 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30438 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30439 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30440 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
30441 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30443 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
30444 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30446 /* Aliases for +simd. */
30447 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30448 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30450 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30451 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30453 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
30454 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
30455 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30458 static const struct arm_ext_table armv7r_ext_table
[] =
30460 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
30461 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
30462 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30463 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30464 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
30465 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30466 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30467 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
30468 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30471 static const struct arm_ext_table armv7em_ext_table
[] =
30473 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
30474 /* Alias for +fp, used to be known as fpv4-sp-d16. */
30475 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
30476 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
30477 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30478 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
30479 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30482 static const struct arm_ext_table armv8a_ext_table
[] =
30484 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30485 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30486 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30487 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30489 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30490 should use the +simd option to turn on FP. */
30491 ARM_REMOVE ("fp", ALL_FP
),
30492 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30493 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30494 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30498 static const struct arm_ext_table armv81a_ext_table
[] =
30500 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30501 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30502 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30504 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30505 should use the +simd option to turn on FP. */
30506 ARM_REMOVE ("fp", ALL_FP
),
30507 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30508 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30509 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30512 static const struct arm_ext_table armv82a_ext_table
[] =
30514 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30515 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
30516 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
30517 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30518 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30519 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30521 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30522 should use the +simd option to turn on FP. */
30523 ARM_REMOVE ("fp", ALL_FP
),
30524 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30525 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30526 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30529 static const struct arm_ext_table armv84a_ext_table
[] =
30531 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30532 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30533 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30534 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30536 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30537 should use the +simd option to turn on FP. */
30538 ARM_REMOVE ("fp", ALL_FP
),
30539 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30540 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30541 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30544 static const struct arm_ext_table armv85a_ext_table
[] =
30546 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30547 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30548 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30549 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30551 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30552 should use the +simd option to turn on FP. */
30553 ARM_REMOVE ("fp", ALL_FP
),
30554 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30557 static const struct arm_ext_table armv8m_main_ext_table
[] =
30559 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30560 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30561 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
30562 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30563 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30566 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
30568 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30569 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30571 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30572 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
30575 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30576 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30577 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE
),
30578 ARM_FEATURE_COPROC (FPU_MVE
| FPU_MVE_FP
)),
30580 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30581 FPU_MVE
| FPU_MVE_FP
| FPU_VFP_V5_SP_D16
|
30582 FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30583 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30586 static const struct arm_ext_table armv8r_ext_table
[] =
30588 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30589 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30590 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30591 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30592 ARM_REMOVE ("fp", ALL_FP
),
30593 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
30594 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30597 /* This list should, at a minimum, contain all the architecture names
30598 recognized by GCC. */
30599 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
30600 #define ARM_ARCH_OPT2(N, V, DF, ext) \
30601 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
30603 static const struct arm_arch_option_table arm_archs
[] =
30605 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
30606 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
30607 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
30608 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30609 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30610 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
30611 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
30612 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
30613 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
30614 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
30615 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
30616 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
30617 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
30618 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
30619 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
30620 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
30621 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
30622 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30623 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30624 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
30625 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
30626 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
30627 kept to preserve existing behaviour. */
30628 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
30629 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
30630 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
30631 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
30632 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
30633 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
30634 kept to preserve existing behaviour. */
30635 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
30636 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
30637 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
30638 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
30639 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
30640 /* The official spelling of the ARMv7 profile variants is the dashed form.
30641 Accept the non-dashed form for compatibility with old toolchains. */
30642 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
30643 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
30644 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
30645 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
30646 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
30647 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
30648 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
30649 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
30650 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
30651 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
30653 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
30655 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
30656 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
30657 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
30658 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
30659 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
30660 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
30661 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
30662 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
30663 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
30664 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
30665 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30667 #undef ARM_ARCH_OPT
30669 /* ISA extensions in the co-processor and main instruction set space. */
30671 struct arm_option_extension_value_table
30675 const arm_feature_set merge_value
;
30676 const arm_feature_set clear_value
;
30677 /* List of architectures for which an extension is available. ARM_ARCH_NONE
30678 indicates that an extension is available for all architectures while
30679 ARM_ANY marks an empty entry. */
30680 const arm_feature_set allowed_archs
[2];
30683 /* The following table must be in alphabetical order with a NULL last entry. */
30685 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
30686 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
30688 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
30689 use the context sensitive approach using arm_ext_table's. */
30690 static const struct arm_option_extension_value_table arm_extensions
[] =
30692 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30693 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30694 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30695 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
30696 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30697 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
30698 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
30700 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30701 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30702 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
30703 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
30704 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30705 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30706 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30708 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30709 | ARM_EXT2_FP16_FML
),
30710 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30711 | ARM_EXT2_FP16_FML
),
30713 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30714 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30715 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
30716 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
30717 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
30718 Thumb divide instruction. Due to this having the same name as the
30719 previous entry, this will be ignored when doing command-line parsing and
30720 only considered by build attribute selection code. */
30721 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
30722 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
30723 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
30724 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
30725 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
30726 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
30727 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
30728 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
30729 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
30730 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
30731 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
30732 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
30733 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
30734 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
30735 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
30736 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
30737 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
30738 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
30739 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30740 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
30741 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
30743 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
30744 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
30745 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30746 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
30747 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
30748 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
30749 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
30750 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
30752 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30753 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30754 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
30755 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
30756 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
30757 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
30758 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30759 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
30761 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
30762 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
30763 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
30764 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
30765 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
30769 /* ISA floating-point and Advanced SIMD extensions. */
30770 struct arm_option_fpu_value_table
30773 const arm_feature_set value
;
30776 /* This list should, at a minimum, contain all the fpu names
30777 recognized by GCC. */
30778 static const struct arm_option_fpu_value_table arm_fpus
[] =
30780 {"softfpa", FPU_NONE
},
30781 {"fpe", FPU_ARCH_FPE
},
30782 {"fpe2", FPU_ARCH_FPE
},
30783 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
30784 {"fpa", FPU_ARCH_FPA
},
30785 {"fpa10", FPU_ARCH_FPA
},
30786 {"fpa11", FPU_ARCH_FPA
},
30787 {"arm7500fe", FPU_ARCH_FPA
},
30788 {"softvfp", FPU_ARCH_VFP
},
30789 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
30790 {"vfp", FPU_ARCH_VFP_V2
},
30791 {"vfp9", FPU_ARCH_VFP_V2
},
30792 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
30793 {"vfp10", FPU_ARCH_VFP_V2
},
30794 {"vfp10-r0", FPU_ARCH_VFP_V1
},
30795 {"vfpxd", FPU_ARCH_VFP_V1xD
},
30796 {"vfpv2", FPU_ARCH_VFP_V2
},
30797 {"vfpv3", FPU_ARCH_VFP_V3
},
30798 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
30799 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
30800 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
30801 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
30802 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
30803 {"arm1020t", FPU_ARCH_VFP_V1
},
30804 {"arm1020e", FPU_ARCH_VFP_V2
},
30805 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
30806 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
30807 {"maverick", FPU_ARCH_MAVERICK
},
30808 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
30809 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
30810 {"neon-fp16", FPU_ARCH_NEON_FP16
},
30811 {"vfpv4", FPU_ARCH_VFP_V4
},
30812 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
30813 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
30814 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
30815 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
30816 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
30817 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
30818 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
30819 {"crypto-neon-fp-armv8",
30820 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
30821 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
30822 {"crypto-neon-fp-armv8.1",
30823 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
30824 {NULL
, ARM_ARCH_NONE
}
30827 struct arm_option_value_table
30833 static const struct arm_option_value_table arm_float_abis
[] =
30835 {"hard", ARM_FLOAT_ABI_HARD
},
30836 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
30837 {"soft", ARM_FLOAT_ABI_SOFT
},
30842 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
30843 static const struct arm_option_value_table arm_eabis
[] =
30845 {"gnu", EF_ARM_EABI_UNKNOWN
},
30846 {"4", EF_ARM_EABI_VER4
},
30847 {"5", EF_ARM_EABI_VER5
},
30852 struct arm_long_option_table
30854 const char * option
; /* Substring to match. */
30855 const char * help
; /* Help information. */
30856 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
30857 const char * deprecated
; /* If non-null, print this message. */
30861 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
30862 arm_feature_set
*ext_set
,
30863 const struct arm_ext_table
*ext_table
)
30865 /* We insist on extensions being specified in alphabetical order, and with
30866 extensions being added before being removed. We achieve this by having
30867 the global ARM_EXTENSIONS table in alphabetical order, and using the
30868 ADDING_VALUE variable to indicate whether we are adding an extension (1)
30869 or removing it (0) and only allowing it to change in the order
30871 const struct arm_option_extension_value_table
* opt
= NULL
;
30872 const arm_feature_set arm_any
= ARM_ANY
;
30873 int adding_value
= -1;
30875 while (str
!= NULL
&& *str
!= 0)
30882 as_bad (_("invalid architectural extension"));
30887 ext
= strchr (str
, '+');
30892 len
= strlen (str
);
30894 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
30896 if (adding_value
!= 0)
30899 opt
= arm_extensions
;
30907 if (adding_value
== -1)
30910 opt
= arm_extensions
;
30912 else if (adding_value
!= 1)
30914 as_bad (_("must specify extensions to add before specifying "
30915 "those to remove"));
30922 as_bad (_("missing architectural extension"));
30926 gas_assert (adding_value
!= -1);
30927 gas_assert (opt
!= NULL
);
30929 if (ext_table
!= NULL
)
30931 const struct arm_ext_table
* ext_opt
= ext_table
;
30932 bfd_boolean found
= FALSE
;
30933 for (; ext_opt
->name
!= NULL
; ext_opt
++)
30934 if (ext_opt
->name_len
== len
30935 && strncmp (ext_opt
->name
, str
, len
) == 0)
30939 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
30940 /* TODO: Option not supported. When we remove the
30941 legacy table this case should error out. */
30944 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
30948 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
30949 /* TODO: Option not supported. When we remove the
30950 legacy table this case should error out. */
30952 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
30964 /* Scan over the options table trying to find an exact match. */
30965 for (; opt
->name
!= NULL
; opt
++)
30966 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
30968 int i
, nb_allowed_archs
=
30969 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
30970 /* Check we can apply the extension to this architecture. */
30971 for (i
= 0; i
< nb_allowed_archs
; i
++)
30974 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
30976 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
30979 if (i
== nb_allowed_archs
)
30981 as_bad (_("extension does not apply to the base architecture"));
30985 /* Add or remove the extension. */
30987 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
30989 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
30991 /* Allowing Thumb division instructions for ARMv7 in autodetection
30992 rely on this break so that duplicate extensions (extensions
30993 with the same name as a previous extension in the list) are not
30994 considered for command-line parsing. */
30998 if (opt
->name
== NULL
)
31000 /* Did we fail to find an extension because it wasn't specified in
31001 alphabetical order, or because it does not exist? */
31003 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31004 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31007 if (opt
->name
== NULL
)
31008 as_bad (_("unknown architectural extension `%s'"), str
);
31010 as_bad (_("architectural extensions must be specified in "
31011 "alphabetical order"));
31017 /* We should skip the extension we've just matched the next time
31029 arm_parse_cpu (const char *str
)
31031 const struct arm_cpu_option_table
*opt
;
31032 const char *ext
= strchr (str
, '+');
31038 len
= strlen (str
);
31042 as_bad (_("missing cpu name `%s'"), str
);
31046 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
31047 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31049 mcpu_cpu_opt
= &opt
->value
;
31050 if (mcpu_ext_opt
== NULL
)
31051 mcpu_ext_opt
= XNEW (arm_feature_set
);
31052 *mcpu_ext_opt
= opt
->ext
;
31053 mcpu_fpu_opt
= &opt
->default_fpu
;
31054 if (opt
->canonical_name
)
31056 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
31057 strcpy (selected_cpu_name
, opt
->canonical_name
);
31063 if (len
>= sizeof selected_cpu_name
)
31064 len
= (sizeof selected_cpu_name
) - 1;
31066 for (i
= 0; i
< len
; i
++)
31067 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
31068 selected_cpu_name
[i
] = 0;
31072 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
31077 as_bad (_("unknown cpu `%s'"), str
);
31082 arm_parse_arch (const char *str
)
31084 const struct arm_arch_option_table
*opt
;
31085 const char *ext
= strchr (str
, '+');
31091 len
= strlen (str
);
31095 as_bad (_("missing architecture name `%s'"), str
);
31099 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
31100 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31102 march_cpu_opt
= &opt
->value
;
31103 if (march_ext_opt
== NULL
)
31104 march_ext_opt
= XNEW (arm_feature_set
);
31105 *march_ext_opt
= arm_arch_none
;
31106 march_fpu_opt
= &opt
->default_fpu
;
31107 strcpy (selected_cpu_name
, opt
->name
);
31110 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
31116 as_bad (_("unknown architecture `%s'\n"), str
);
31121 arm_parse_fpu (const char * str
)
31123 const struct arm_option_fpu_value_table
* opt
;
31125 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
31126 if (streq (opt
->name
, str
))
31128 mfpu_opt
= &opt
->value
;
31132 as_bad (_("unknown floating point format `%s'\n"), str
);
31137 arm_parse_float_abi (const char * str
)
31139 const struct arm_option_value_table
* opt
;
31141 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
31142 if (streq (opt
->name
, str
))
31144 mfloat_abi_opt
= opt
->value
;
31148 as_bad (_("unknown floating point abi `%s'\n"), str
);
31154 arm_parse_eabi (const char * str
)
31156 const struct arm_option_value_table
*opt
;
31158 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
31159 if (streq (opt
->name
, str
))
31161 meabi_flags
= opt
->value
;
31164 as_bad (_("unknown EABI `%s'\n"), str
);
31170 arm_parse_it_mode (const char * str
)
31172 bfd_boolean ret
= TRUE
;
31174 if (streq ("arm", str
))
31175 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
31176 else if (streq ("thumb", str
))
31177 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
31178 else if (streq ("always", str
))
31179 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
31180 else if (streq ("never", str
))
31181 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
31184 as_bad (_("unknown implicit IT mode `%s', should be "\
31185 "arm, thumb, always, or never."), str
);
31193 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
31195 codecomposer_syntax
= TRUE
;
31196 arm_comment_chars
[0] = ';';
31197 arm_line_separator_chars
[0] = 0;
31201 struct arm_long_option_table arm_long_opts
[] =
31203 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
31204 arm_parse_cpu
, NULL
},
31205 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
31206 arm_parse_arch
, NULL
},
31207 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
31208 arm_parse_fpu
, NULL
},
31209 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
31210 arm_parse_float_abi
, NULL
},
31212 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
31213 arm_parse_eabi
, NULL
},
31215 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
31216 arm_parse_it_mode
, NULL
},
31217 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
31218 arm_ccs_mode
, NULL
},
31219 {NULL
, NULL
, 0, NULL
}
31223 md_parse_option (int c
, const char * arg
)
31225 struct arm_option_table
*opt
;
31226 const struct arm_legacy_option_table
*fopt
;
31227 struct arm_long_option_table
*lopt
;
31233 target_big_endian
= 1;
31239 target_big_endian
= 0;
31243 case OPTION_FIX_V4BX
:
31251 #endif /* OBJ_ELF */
31254 /* Listing option. Just ignore these, we don't support additional
31259 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31261 if (c
== opt
->option
[0]
31262 && ((arg
== NULL
&& opt
->option
[1] == 0)
31263 || streq (arg
, opt
->option
+ 1)))
31265 /* If the option is deprecated, tell the user. */
31266 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
31267 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31268 arg
? arg
: "", _(opt
->deprecated
));
31270 if (opt
->var
!= NULL
)
31271 *opt
->var
= opt
->value
;
31277 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
31279 if (c
== fopt
->option
[0]
31280 && ((arg
== NULL
&& fopt
->option
[1] == 0)
31281 || streq (arg
, fopt
->option
+ 1)))
31283 /* If the option is deprecated, tell the user. */
31284 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
31285 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31286 arg
? arg
: "", _(fopt
->deprecated
));
31288 if (fopt
->var
!= NULL
)
31289 *fopt
->var
= &fopt
->value
;
31295 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31297 /* These options are expected to have an argument. */
31298 if (c
== lopt
->option
[0]
31300 && strncmp (arg
, lopt
->option
+ 1,
31301 strlen (lopt
->option
+ 1)) == 0)
31303 /* If the option is deprecated, tell the user. */
31304 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
31305 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
31306 _(lopt
->deprecated
));
31308 /* Call the sup-option parser. */
31309 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
31320 md_show_usage (FILE * fp
)
31322 struct arm_option_table
*opt
;
31323 struct arm_long_option_table
*lopt
;
31325 fprintf (fp
, _(" ARM-specific assembler options:\n"));
31327 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31328 if (opt
->help
!= NULL
)
31329 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
31331 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31332 if (lopt
->help
!= NULL
)
31333 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
31337 -EB assemble code for a big-endian cpu\n"));
31342 -EL assemble code for a little-endian cpu\n"));
31346 --fix-v4bx Allow BX in ARMv4 code\n"));
31350 --fdpic generate an FDPIC object file\n"));
31351 #endif /* OBJ_ELF */
31359 arm_feature_set flags
;
31360 } cpu_arch_ver_table
;
31362 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
31363 chronologically for architectures, with an exception for ARMv6-M and
31364 ARMv6S-M due to legacy reasons. No new architecture should have a
31365 special case. This allows for build attribute selection results to be
31366 stable when new architectures are added. */
31367 static const cpu_arch_ver_table cpu_arch_ver
[] =
31369 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
31370 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
31371 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
31372 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
31373 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
31374 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
31375 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
31376 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
31377 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
31378 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
31379 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
31380 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
31381 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
31382 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
31383 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
31384 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
31385 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
31386 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
31387 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
31388 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
31389 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
31390 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
31391 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
31392 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
31394 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
31395 always selected build attributes to match those of ARMv6-M
31396 (resp. ARMv6S-M). However, due to these architectures being a strict
31397 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
31398 would be selected when fully respecting chronology of architectures.
31399 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
31400 move them before ARMv7 architectures. */
31401 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
31402 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
31404 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
31405 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
31406 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
31407 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
31408 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
31409 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
31410 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
31411 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
31412 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
31413 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
31414 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
31415 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
31416 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
31417 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
31418 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
31419 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
31420 {-1, ARM_ARCH_NONE
}
31423 /* Set an attribute if it has not already been set by the user. */
31426 aeabi_set_attribute_int (int tag
, int value
)
31429 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31430 || !attributes_set_explicitly
[tag
])
31431 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
31435 aeabi_set_attribute_string (int tag
, const char *value
)
31438 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31439 || !attributes_set_explicitly
[tag
])
31440 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
31443 /* Return whether features in the *NEEDED feature set are available via
31444 extensions for the architecture whose feature set is *ARCH_FSET. */
31447 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
31448 const arm_feature_set
*needed
)
31450 int i
, nb_allowed_archs
;
31451 arm_feature_set ext_fset
;
31452 const struct arm_option_extension_value_table
*opt
;
31454 ext_fset
= arm_arch_none
;
31455 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31457 /* Extension does not provide any feature we need. */
31458 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
31462 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31463 for (i
= 0; i
< nb_allowed_archs
; i
++)
31466 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
31469 /* Extension is available, add it. */
31470 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
31471 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
31475 /* Can we enable all features in *needed? */
31476 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
31479 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
31480 a given architecture feature set *ARCH_EXT_FSET including extension feature
31481 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
31482 - if true, check for an exact match of the architecture modulo extensions;
31483 - otherwise, select build attribute value of the first superset
31484 architecture released so that results remains stable when new architectures
31486 For -march/-mcpu=all the build attribute value of the most featureful
31487 architecture is returned. Tag_CPU_arch_profile result is returned in
31491 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
31492 const arm_feature_set
*ext_fset
,
31493 char *profile
, int exact_match
)
31495 arm_feature_set arch_fset
;
31496 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
31498 /* Select most featureful architecture with all its extensions if building
31499 for -march=all as the feature sets used to set build attributes. */
31500 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
31502 /* Force revisiting of decision for each new architecture. */
31503 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
31505 return TAG_CPU_ARCH_V8
;
31508 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
31510 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
31512 arm_feature_set known_arch_fset
;
31514 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
31517 /* Base architecture match user-specified architecture and
31518 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
31519 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
31524 /* Base architecture match user-specified architecture only
31525 (eg. ARMv6-M in the same case as above). Record it in case we
31526 find a match with above condition. */
31527 else if (p_ver_ret
== NULL
31528 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
31534 /* Architecture has all features wanted. */
31535 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
31537 arm_feature_set added_fset
;
31539 /* Compute features added by this architecture over the one
31540 recorded in p_ver_ret. */
31541 if (p_ver_ret
!= NULL
)
31542 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
31544 /* First architecture that match incl. with extensions, or the
31545 only difference in features over the recorded match is
31546 features that were optional and are now mandatory. */
31547 if (p_ver_ret
== NULL
31548 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
31554 else if (p_ver_ret
== NULL
)
31556 arm_feature_set needed_ext_fset
;
31558 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
31560 /* Architecture has all features needed when using some
31561 extensions. Record it and continue searching in case there
31562 exist an architecture providing all needed features without
31563 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
31565 if (have_ext_for_needed_feat_p (&known_arch_fset
,
31572 if (p_ver_ret
== NULL
)
31576 /* Tag_CPU_arch_profile. */
31577 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
31578 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
31579 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
31580 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
31582 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
31584 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
31588 return p_ver_ret
->val
;
31591 /* Set the public EABI object attributes. */
31594 aeabi_set_public_attributes (void)
31596 char profile
= '\0';
31599 int fp16_optional
= 0;
31600 int skip_exact_match
= 0;
31601 arm_feature_set flags
, flags_arch
, flags_ext
;
31603 /* Autodetection mode, choose the architecture based the instructions
31605 if (no_cpu_selected ())
31607 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
31609 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
31610 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
31612 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
31613 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
31615 /* Code run during relaxation relies on selected_cpu being set. */
31616 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
31617 flags_ext
= arm_arch_none
;
31618 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
31619 selected_ext
= flags_ext
;
31620 selected_cpu
= flags
;
31622 /* Otherwise, choose the architecture based on the capabilities of the
31626 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
31627 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
31628 flags_ext
= selected_ext
;
31629 flags
= selected_cpu
;
31631 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
31633 /* Allow the user to override the reported architecture. */
31634 if (!ARM_FEATURE_ZERO (selected_object_arch
))
31636 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
31637 flags_ext
= arm_arch_none
;
31640 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
31642 /* When this function is run again after relaxation has happened there is no
31643 way to determine whether an architecture or CPU was specified by the user:
31644 - selected_cpu is set above for relaxation to work;
31645 - march_cpu_opt is not set if only -mcpu or .cpu is used;
31646 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
31647 Therefore, if not in -march=all case we first try an exact match and fall
31648 back to autodetection. */
31649 if (!skip_exact_match
)
31650 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
31652 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
31654 as_bad (_("no architecture contains all the instructions used\n"));
31656 /* Tag_CPU_name. */
31657 if (selected_cpu_name
[0])
31661 q
= selected_cpu_name
;
31662 if (strncmp (q
, "armv", 4) == 0)
31667 for (i
= 0; q
[i
]; i
++)
31668 q
[i
] = TOUPPER (q
[i
]);
31670 aeabi_set_attribute_string (Tag_CPU_name
, q
);
31673 /* Tag_CPU_arch. */
31674 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
31676 /* Tag_CPU_arch_profile. */
31677 if (profile
!= '\0')
31678 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
31680 /* Tag_DSP_extension. */
31681 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
31682 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
31684 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
31685 /* Tag_ARM_ISA_use. */
31686 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
31687 || ARM_FEATURE_ZERO (flags_arch
))
31688 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
31690 /* Tag_THUMB_ISA_use. */
31691 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
31692 || ARM_FEATURE_ZERO (flags_arch
))
31696 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
31697 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
31699 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
31703 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
31706 /* Tag_VFP_arch. */
31707 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
31708 aeabi_set_attribute_int (Tag_VFP_arch
,
31709 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
31711 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
31712 aeabi_set_attribute_int (Tag_VFP_arch
,
31713 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
31715 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
31718 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
31720 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
31722 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
31725 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
31726 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
31727 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
31728 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
31729 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
31731 /* Tag_ABI_HardFP_use. */
31732 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
31733 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
31734 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
31736 /* Tag_WMMX_arch. */
31737 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
31738 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
31739 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
31740 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
31742 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
31743 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
31744 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
31745 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
31746 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
31747 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
31749 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
31751 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
31755 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
31760 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
31761 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
31762 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
31763 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
31765 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
31766 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
31767 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
31771 We set Tag_DIV_use to two when integer divide instructions have been used
31772 in ARM state, or when Thumb integer divide instructions have been used,
31773 but we have no architecture profile set, nor have we any ARM instructions.
31775 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
31776 by the base architecture.
31778 For new architectures we will have to check these tests. */
31779 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
31780 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
31781 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
31782 aeabi_set_attribute_int (Tag_DIV_use
, 0);
31783 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
31784 || (profile
== '\0'
31785 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
31786 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
31787 aeabi_set_attribute_int (Tag_DIV_use
, 2);
31789 /* Tag_MP_extension_use. */
31790 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
31791 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
31793 /* Tag Virtualization_use. */
31794 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
31796 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
31799 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
31802 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
31803 finished and free extension feature bits which will not be used anymore. */
31806 arm_md_post_relax (void)
31808 aeabi_set_public_attributes ();
31809 XDELETE (mcpu_ext_opt
);
31810 mcpu_ext_opt
= NULL
;
31811 XDELETE (march_ext_opt
);
31812 march_ext_opt
= NULL
;
31815 /* Add the default contents for the .ARM.attributes section. */
31820 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
31823 aeabi_set_public_attributes ();
31825 #endif /* OBJ_ELF */
31827 /* Parse a .cpu directive. */
31830 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
31832 const struct arm_cpu_option_table
*opt
;
31836 name
= input_line_pointer
;
31837 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31838 input_line_pointer
++;
31839 saved_char
= *input_line_pointer
;
31840 *input_line_pointer
= 0;
31842 /* Skip the first "all" entry. */
31843 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
31844 if (streq (opt
->name
, name
))
31846 selected_arch
= opt
->value
;
31847 selected_ext
= opt
->ext
;
31848 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
31849 if (opt
->canonical_name
)
31850 strcpy (selected_cpu_name
, opt
->canonical_name
);
31854 for (i
= 0; opt
->name
[i
]; i
++)
31855 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
31857 selected_cpu_name
[i
] = 0;
31859 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31861 *input_line_pointer
= saved_char
;
31862 demand_empty_rest_of_line ();
31865 as_bad (_("unknown cpu `%s'"), name
);
31866 *input_line_pointer
= saved_char
;
31867 ignore_rest_of_line ();
31870 /* Parse a .arch directive. */
31873 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
31875 const struct arm_arch_option_table
*opt
;
31879 name
= input_line_pointer
;
31880 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31881 input_line_pointer
++;
31882 saved_char
= *input_line_pointer
;
31883 *input_line_pointer
= 0;
31885 /* Skip the first "all" entry. */
31886 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
31887 if (streq (opt
->name
, name
))
31889 selected_arch
= opt
->value
;
31890 selected_ext
= arm_arch_none
;
31891 selected_cpu
= selected_arch
;
31892 strcpy (selected_cpu_name
, opt
->name
);
31893 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31894 *input_line_pointer
= saved_char
;
31895 demand_empty_rest_of_line ();
31899 as_bad (_("unknown architecture `%s'\n"), name
);
31900 *input_line_pointer
= saved_char
;
31901 ignore_rest_of_line ();
31904 /* Parse a .object_arch directive. */
31907 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
31909 const struct arm_arch_option_table
*opt
;
31913 name
= input_line_pointer
;
31914 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31915 input_line_pointer
++;
31916 saved_char
= *input_line_pointer
;
31917 *input_line_pointer
= 0;
31919 /* Skip the first "all" entry. */
31920 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
31921 if (streq (opt
->name
, name
))
31923 selected_object_arch
= opt
->value
;
31924 *input_line_pointer
= saved_char
;
31925 demand_empty_rest_of_line ();
31929 as_bad (_("unknown architecture `%s'\n"), name
);
31930 *input_line_pointer
= saved_char
;
31931 ignore_rest_of_line ();
31934 /* Parse a .arch_extension directive. */
31937 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
31939 const struct arm_option_extension_value_table
*opt
;
31942 int adding_value
= 1;
31944 name
= input_line_pointer
;
31945 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
31946 input_line_pointer
++;
31947 saved_char
= *input_line_pointer
;
31948 *input_line_pointer
= 0;
31950 if (strlen (name
) >= 2
31951 && strncmp (name
, "no", 2) == 0)
31957 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31958 if (streq (opt
->name
, name
))
31960 int i
, nb_allowed_archs
=
31961 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
31962 for (i
= 0; i
< nb_allowed_archs
; i
++)
31965 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
31967 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
31971 if (i
== nb_allowed_archs
)
31973 as_bad (_("architectural extension `%s' is not allowed for the "
31974 "current base architecture"), name
);
31979 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
31982 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
31984 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
31985 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
31986 *input_line_pointer
= saved_char
;
31987 demand_empty_rest_of_line ();
31988 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
31989 on this return so that duplicate extensions (extensions with the
31990 same name as a previous extension in the list) are not considered
31991 for command-line parsing. */
31995 if (opt
->name
== NULL
)
31996 as_bad (_("unknown architecture extension `%s'\n"), name
);
31998 *input_line_pointer
= saved_char
;
31999 ignore_rest_of_line ();
32002 /* Parse a .fpu directive. */
32005 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
32007 const struct arm_option_fpu_value_table
*opt
;
32011 name
= input_line_pointer
;
32012 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32013 input_line_pointer
++;
32014 saved_char
= *input_line_pointer
;
32015 *input_line_pointer
= 0;
32017 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
32018 if (streq (opt
->name
, name
))
32020 selected_fpu
= opt
->value
;
32021 #ifndef CPU_DEFAULT
32022 if (no_cpu_selected ())
32023 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
32026 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32027 *input_line_pointer
= saved_char
;
32028 demand_empty_rest_of_line ();
32032 as_bad (_("unknown floating point format `%s'\n"), name
);
32033 *input_line_pointer
= saved_char
;
32034 ignore_rest_of_line ();
32037 /* Copy symbol information. */
32040 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
32042 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
32046 /* Given a symbolic attribute NAME, return the proper integer value.
32047 Returns -1 if the attribute is not known. */
32050 arm_convert_symbolic_attribute (const char *name
)
32052 static const struct
32057 attribute_table
[] =
32059 /* When you modify this table you should
32060 also modify the list in doc/c-arm.texi. */
32061 #define T(tag) {#tag, tag}
32062 T (Tag_CPU_raw_name
),
32065 T (Tag_CPU_arch_profile
),
32066 T (Tag_ARM_ISA_use
),
32067 T (Tag_THUMB_ISA_use
),
32071 T (Tag_Advanced_SIMD_arch
),
32072 T (Tag_PCS_config
),
32073 T (Tag_ABI_PCS_R9_use
),
32074 T (Tag_ABI_PCS_RW_data
),
32075 T (Tag_ABI_PCS_RO_data
),
32076 T (Tag_ABI_PCS_GOT_use
),
32077 T (Tag_ABI_PCS_wchar_t
),
32078 T (Tag_ABI_FP_rounding
),
32079 T (Tag_ABI_FP_denormal
),
32080 T (Tag_ABI_FP_exceptions
),
32081 T (Tag_ABI_FP_user_exceptions
),
32082 T (Tag_ABI_FP_number_model
),
32083 T (Tag_ABI_align_needed
),
32084 T (Tag_ABI_align8_needed
),
32085 T (Tag_ABI_align_preserved
),
32086 T (Tag_ABI_align8_preserved
),
32087 T (Tag_ABI_enum_size
),
32088 T (Tag_ABI_HardFP_use
),
32089 T (Tag_ABI_VFP_args
),
32090 T (Tag_ABI_WMMX_args
),
32091 T (Tag_ABI_optimization_goals
),
32092 T (Tag_ABI_FP_optimization_goals
),
32093 T (Tag_compatibility
),
32094 T (Tag_CPU_unaligned_access
),
32095 T (Tag_FP_HP_extension
),
32096 T (Tag_VFP_HP_extension
),
32097 T (Tag_ABI_FP_16bit_format
),
32098 T (Tag_MPextension_use
),
32100 T (Tag_nodefaults
),
32101 T (Tag_also_compatible_with
),
32102 T (Tag_conformance
),
32104 T (Tag_Virtualization_use
),
32105 T (Tag_DSP_extension
),
32107 /* We deliberately do not include Tag_MPextension_use_legacy. */
32115 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
32116 if (streq (name
, attribute_table
[i
].name
))
32117 return attribute_table
[i
].tag
;
32122 /* Apply sym value for relocations only in the case that they are for
32123 local symbols in the same segment as the fixup and you have the
32124 respective architectural feature for blx and simple switches. */
32127 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
32130 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
32131 /* PR 17444: If the local symbol is in a different section then a reloc
32132 will always be generated for it, so applying the symbol value now
32133 will result in a double offset being stored in the relocation. */
32134 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
32135 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
32137 switch (fixP
->fx_r_type
)
32139 case BFD_RELOC_ARM_PCREL_BLX
:
32140 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
32141 if (ARM_IS_FUNC (fixP
->fx_addsy
))
32145 case BFD_RELOC_ARM_PCREL_CALL
:
32146 case BFD_RELOC_THUMB_PCREL_BLX
:
32147 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
32158 #endif /* OBJ_ELF */