1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
39 #include "dw2gencfi.h"
42 #include "dwarf2dbg.h"
45 /* Must be at least the size of the largest unwind opcode (currently two). */
46 #define ARM_OPCODE_CHUNK_SIZE 8
48 /* This structure holds the unwinding state. */
53 symbolS
* table_entry
;
54 symbolS
* personality_routine
;
55 int personality_index
;
56 /* The segment containing the function. */
59 /* Opcodes generated from this function. */
60 unsigned char * opcodes
;
63 /* The number of bytes pushed to the stack. */
65 /* We don't add stack adjustment opcodes immediately so that we can merge
66 multiple adjustments. We can also omit the final adjustment
67 when using a frame pointer. */
68 offsetT pending_offset
;
69 /* These two fields are set by both unwind_movsp and unwind_setfp. They
70 hold the reg+offset to use when restoring sp from a frame pointer. */
73 /* Nonzero if an unwind_setfp directive has been seen. */
75 /* Nonzero if the last opcode restores sp from fp_reg. */
76 unsigned sp_restored
:1;
79 /* Whether --fdpic was given. */
84 /* Results from operand parsing worker functions. */
88 PARSE_OPERAND_SUCCESS
,
90 PARSE_OPERAND_FAIL_NO_BACKTRACK
91 } parse_operand_result
;
100 /* Types of processor to assemble for. */
102 /* The code that was here used to select a default CPU depending on compiler
103 pre-defines which were only present when doing native builds, thus
104 changing gas' default behaviour depending upon the build host.
106 If you have a target that requires a default CPU option then the you
107 should define CPU_DEFAULT here. */
110 /* Perform range checks on positive and negative overflows by checking if the
111 VALUE given fits within the range of an BITS sized immediate. */
112 static bfd_boolean
out_of_range_p (offsetT value
, offsetT bits
)
114 gas_assert (bits
< (offsetT
)(sizeof (value
) * 8));
115 return (value
& ~((1 << bits
)-1))
116 && ((value
& ~((1 << bits
)-1)) != ~((1 << bits
)-1));
121 # define FPU_DEFAULT FPU_ARCH_FPA
122 # elif defined (TE_NetBSD)
124 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
126 /* Legacy a.out format. */
127 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
129 # elif defined (TE_VXWORKS)
130 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
132 /* For backwards compatibility, default to FPA. */
133 # define FPU_DEFAULT FPU_ARCH_FPA
135 #endif /* ifndef FPU_DEFAULT */
137 #define streq(a, b) (strcmp (a, b) == 0)
139 /* Current set of feature bits available (CPU+FPU). Different from
140 selected_cpu + selected_fpu in case of autodetection since the CPU
141 feature bits are then all set. */
142 static arm_feature_set cpu_variant
;
143 /* Feature bits used in each execution state. Used to set build attribute
144 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
145 static arm_feature_set arm_arch_used
;
146 static arm_feature_set thumb_arch_used
;
148 /* Flags stored in private area of BFD structure. */
149 static int uses_apcs_26
= FALSE
;
150 static int atpcs
= FALSE
;
151 static int support_interwork
= FALSE
;
152 static int uses_apcs_float
= FALSE
;
153 static int pic_code
= FALSE
;
154 static int fix_v4bx
= FALSE
;
155 /* Warn on using deprecated features. */
156 static int warn_on_deprecated
= TRUE
;
157 static int warn_on_restrict_it
= FALSE
;
159 /* Understand CodeComposer Studio assembly syntax. */
160 bfd_boolean codecomposer_syntax
= FALSE
;
162 /* Variables that we set while parsing command-line options. Once all
163 options have been read we re-process these values to set the real
166 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
167 instead of -mcpu=arm1). */
168 static const arm_feature_set
*legacy_cpu
= NULL
;
169 static const arm_feature_set
*legacy_fpu
= NULL
;
171 /* CPU, extension and FPU feature bits selected by -mcpu. */
172 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
173 static arm_feature_set
*mcpu_ext_opt
= NULL
;
174 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
176 /* CPU, extension and FPU feature bits selected by -march. */
177 static const arm_feature_set
*march_cpu_opt
= NULL
;
178 static arm_feature_set
*march_ext_opt
= NULL
;
179 static const arm_feature_set
*march_fpu_opt
= NULL
;
181 /* Feature bits selected by -mfpu. */
182 static const arm_feature_set
*mfpu_opt
= NULL
;
184 /* Constants for known architecture features. */
185 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
186 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
187 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
188 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
189 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
190 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
191 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
193 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
195 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
198 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
201 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
202 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
203 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
204 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
205 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
206 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
207 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
208 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
209 static const arm_feature_set arm_ext_v4t_5
=
210 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
211 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
212 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
213 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
214 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
215 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
216 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
217 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
218 /* Only for compatability of hint instructions. */
219 static const arm_feature_set arm_ext_v6k_v6t2
=
220 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
221 static const arm_feature_set arm_ext_v6_notm
=
222 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
223 static const arm_feature_set arm_ext_v6_dsp
=
224 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
225 static const arm_feature_set arm_ext_barrier
=
226 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
227 static const arm_feature_set arm_ext_msr
=
228 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
229 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
230 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
231 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
232 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
233 static const arm_feature_set arm_ext_v8r
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R
);
235 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
237 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
238 static const arm_feature_set arm_ext_m
=
239 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
240 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
241 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
242 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
243 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
244 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
245 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
246 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
247 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
248 static const arm_feature_set arm_ext_v8m_main
=
249 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
250 static const arm_feature_set arm_ext_v8_1m_main
=
251 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
252 /* Instructions in ARMv8-M only found in M profile architectures. */
253 static const arm_feature_set arm_ext_v8m_m_only
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
255 static const arm_feature_set arm_ext_v6t2_v8m
=
256 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
257 /* Instructions shared between ARMv8-A and ARMv8-M. */
258 static const arm_feature_set arm_ext_atomics
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
261 /* DSP instructions Tag_DSP_extension refers to. */
262 static const arm_feature_set arm_ext_dsp
=
263 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
265 static const arm_feature_set arm_ext_ras
=
266 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
267 /* FP16 instructions. */
268 static const arm_feature_set arm_ext_fp16
=
269 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
270 static const arm_feature_set arm_ext_fp16_fml
=
271 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
272 static const arm_feature_set arm_ext_v8_2
=
273 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
274 static const arm_feature_set arm_ext_v8_3
=
275 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
276 static const arm_feature_set arm_ext_sb
=
277 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
278 static const arm_feature_set arm_ext_predres
=
279 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
280 static const arm_feature_set arm_ext_bf16
=
281 ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
);
282 static const arm_feature_set arm_ext_i8mm
=
283 ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
);
284 static const arm_feature_set arm_ext_crc
=
285 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
);
286 static const arm_feature_set arm_ext_cde
=
287 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
);
288 static const arm_feature_set arm_ext_cde0
=
289 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE0
);
290 static const arm_feature_set arm_ext_cde1
=
291 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE1
);
292 static const arm_feature_set arm_ext_cde2
=
293 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE2
);
294 static const arm_feature_set arm_ext_cde3
=
295 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE3
);
296 static const arm_feature_set arm_ext_cde4
=
297 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE4
);
298 static const arm_feature_set arm_ext_cde5
=
299 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE5
);
300 static const arm_feature_set arm_ext_cde6
=
301 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE6
);
302 static const arm_feature_set arm_ext_cde7
=
303 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE7
);
305 static const arm_feature_set arm_arch_any
= ARM_ANY
;
306 static const arm_feature_set fpu_any
= FPU_ANY
;
307 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
308 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
309 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
311 static const arm_feature_set arm_cext_iwmmxt2
=
312 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
313 static const arm_feature_set arm_cext_iwmmxt
=
314 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
315 static const arm_feature_set arm_cext_xscale
=
316 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
317 static const arm_feature_set arm_cext_maverick
=
318 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
319 static const arm_feature_set fpu_fpa_ext_v1
=
320 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
321 static const arm_feature_set fpu_fpa_ext_v2
=
322 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
323 static const arm_feature_set fpu_vfp_ext_v1xd
=
324 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
325 static const arm_feature_set fpu_vfp_ext_v1
=
326 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
327 static const arm_feature_set fpu_vfp_ext_v2
=
328 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
329 static const arm_feature_set fpu_vfp_ext_v3xd
=
330 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
331 static const arm_feature_set fpu_vfp_ext_v3
=
332 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
333 static const arm_feature_set fpu_vfp_ext_d32
=
334 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
335 static const arm_feature_set fpu_neon_ext_v1
=
336 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
337 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
338 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
339 static const arm_feature_set mve_ext
=
340 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
);
341 static const arm_feature_set mve_fp_ext
=
342 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
);
343 /* Note: This has more than one bit set, which means using it with
344 mark_feature_used (which returns if *any* of the bits are set in the current
345 cpu variant) can give surprising results. */
346 static const arm_feature_set armv8m_fp
=
347 ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16
);
349 static const arm_feature_set fpu_vfp_fp16
=
350 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
351 static const arm_feature_set fpu_neon_ext_fma
=
352 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
354 static const arm_feature_set fpu_vfp_ext_fma
=
355 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
356 static const arm_feature_set fpu_vfp_ext_armv8
=
357 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
358 static const arm_feature_set fpu_vfp_ext_armv8xd
=
359 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
360 static const arm_feature_set fpu_neon_ext_armv8
=
361 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
362 static const arm_feature_set fpu_crypto_ext_armv8
=
363 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
364 static const arm_feature_set fpu_neon_ext_v8_1
=
365 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
366 static const arm_feature_set fpu_neon_ext_dotprod
=
367 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
369 static int mfloat_abi_opt
= -1;
370 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
372 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
373 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
375 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
376 /* Feature bits selected by the last -mcpu/-march or by the combination of the
377 last .cpu/.arch directive .arch_extension directives since that
379 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
380 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
381 static arm_feature_set selected_fpu
= FPU_NONE
;
382 /* Feature bits selected by the last .object_arch directive. */
383 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
384 /* Must be long enough to hold any of the names in arm_cpus. */
385 static const struct arm_ext_table
* selected_ctx_ext_table
= NULL
;
386 static char selected_cpu_name
[20];
388 extern FLONUM_TYPE generic_floating_point_number
;
390 /* Return if no cpu was selected on command-line. */
392 no_cpu_selected (void)
394 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
399 static int meabi_flags
= EABI_DEFAULT
;
401 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
404 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
409 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
414 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
415 symbolS
* GOT_symbol
;
418 /* 0: assemble for ARM,
419 1: assemble for Thumb,
420 2: assemble for Thumb even though target CPU does not support thumb
422 static int thumb_mode
= 0;
423 /* A value distinct from the possible values for thumb_mode that we
424 can use to record whether thumb_mode has been copied into the
425 tc_frag_data field of a frag. */
426 #define MODE_RECORDED (1 << 4)
428 /* Specifies the intrinsic IT insn behavior mode. */
429 enum implicit_it_mode
431 IMPLICIT_IT_MODE_NEVER
= 0x00,
432 IMPLICIT_IT_MODE_ARM
= 0x01,
433 IMPLICIT_IT_MODE_THUMB
= 0x02,
434 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
436 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
438 /* If unified_syntax is true, we are processing the new unified
439 ARM/Thumb syntax. Important differences from the old ARM mode:
441 - Immediate operands do not require a # prefix.
442 - Conditional affixes always appear at the end of the
443 instruction. (For backward compatibility, those instructions
444 that formerly had them in the middle, continue to accept them
446 - The IT instruction may appear, and if it does is validated
447 against subsequent conditional affixes. It does not generate
450 Important differences from the old Thumb mode:
452 - Immediate operands do not require a # prefix.
453 - Most of the V6T2 instructions are only available in unified mode.
454 - The .N and .W suffixes are recognized and honored (it is an error
455 if they cannot be honored).
456 - All instructions set the flags if and only if they have an 's' affix.
457 - Conditional affixes may be used. They are validated against
458 preceding IT instructions. Unlike ARM mode, you cannot use a
459 conditional affix except in the scope of an IT instruction. */
461 static bfd_boolean unified_syntax
= FALSE
;
463 /* An immediate operand can start with #, and ld*, st*, pld operands
464 can contain [ and ]. We need to tell APP not to elide whitespace
465 before a [, which can appear as the first operand for pld.
466 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
467 const char arm_symbol_chars
[] = "#[]{}";
483 enum neon_el_type type
;
487 #define NEON_MAX_TYPE_ELS 5
491 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
495 enum pred_instruction_type
501 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
502 if inside, should be the last one. */
503 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
504 i.e. BKPT and NOP. */
505 IT_INSN
, /* The IT insn has been parsed. */
506 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
507 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
508 a predication code. */
509 MVE_UNPREDICABLE_INSN
, /* MVE instruction that is non-predicable. */
512 /* The maximum number of operands we need. */
513 #define ARM_IT_MAX_OPERANDS 6
514 #define ARM_IT_MAX_RELOCS 3
519 unsigned long instruction
;
521 unsigned int size_req
;
523 /* "uncond_value" is set to the value in place of the conditional field in
524 unconditional versions of the instruction, or -1u if nothing is
526 unsigned int uncond_value
;
527 struct neon_type vectype
;
528 /* This does not indicate an actual NEON instruction, only that
529 the mnemonic accepts neon-style type suffixes. */
531 /* Set to the opcode if the instruction needs relaxation.
532 Zero if the instruction is not relaxed. */
536 bfd_reloc_code_real_type type
;
539 } relocs
[ARM_IT_MAX_RELOCS
];
541 enum pred_instruction_type pred_insn_type
;
547 struct neon_type_el vectype
;
548 unsigned present
: 1; /* Operand present. */
549 unsigned isreg
: 1; /* Operand was a register. */
550 unsigned immisreg
: 2; /* .imm field is a second register.
551 0: imm, 1: gpr, 2: MVE Q-register. */
552 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
556 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
557 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
558 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
559 instructions. This allows us to disambiguate ARM <-> vector insns. */
560 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
561 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
562 unsigned isquad
: 1; /* Operand is SIMD quad register. */
563 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
564 unsigned iszr
: 1; /* Operand is ZR register. */
565 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
566 unsigned writeback
: 1; /* Operand has trailing ! */
567 unsigned preind
: 1; /* Preindexed address. */
568 unsigned postind
: 1; /* Postindexed address. */
569 unsigned negative
: 1; /* Index register was negated. */
570 unsigned shifted
: 1; /* Shift applied to operation. */
571 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
572 } operands
[ARM_IT_MAX_OPERANDS
];
575 static struct arm_it inst
;
577 #define NUM_FLOAT_VALS 8
579 const char * fp_const
[] =
581 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
584 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
594 #define CP_T_X 0x00008000
595 #define CP_T_Y 0x00400000
597 #define CONDS_BIT 0x00100000
598 #define LOAD_BIT 0x00100000
600 #define DOUBLE_LOAD_FLAG 0x00000001
604 const char * template_name
;
608 #define COND_ALWAYS 0xE
612 const char * template_name
;
616 struct asm_barrier_opt
618 const char * template_name
;
620 const arm_feature_set arch
;
623 /* The bit that distinguishes CPSR and SPSR. */
624 #define SPSR_BIT (1 << 22)
626 /* The individual PSR flag bits. */
627 #define PSR_c (1 << 16)
628 #define PSR_x (1 << 17)
629 #define PSR_s (1 << 18)
630 #define PSR_f (1 << 19)
635 bfd_reloc_code_real_type reloc
;
640 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
641 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
646 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
649 /* Bits for DEFINED field in neon_typed_alias. */
650 #define NTA_HASTYPE 1
651 #define NTA_HASINDEX 2
653 struct neon_typed_alias
655 unsigned char defined
;
657 struct neon_type_el eltype
;
660 /* ARM register categories. This includes coprocessor numbers and various
661 architecture extensions' registers. Each entry should have an error message
662 in reg_expected_msgs below. */
692 /* Structure for a hash table entry for a register.
693 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
694 information which states whether a vector type or index is specified (for a
695 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
701 unsigned char builtin
;
702 struct neon_typed_alias
* neon
;
705 /* Diagnostics used when we don't get a register of the expected type. */
706 const char * const reg_expected_msgs
[] =
708 [REG_TYPE_RN
] = N_("ARM register expected"),
709 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
710 [REG_TYPE_CN
] = N_("co-processor register expected"),
711 [REG_TYPE_FN
] = N_("FPA register expected"),
712 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
713 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
714 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
715 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
716 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
717 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
718 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
720 [REG_TYPE_VFC
] = N_("VFP system register expected"),
721 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
722 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
723 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
724 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
725 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
726 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
727 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
728 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
729 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
730 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
731 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
735 /* Some well known registers that we refer to directly elsewhere. */
741 /* ARM instructions take 4bytes in the object file, Thumb instructions
747 /* Basic string to match. */
748 const char * template_name
;
750 /* Parameters to instruction. */
751 unsigned int operands
[8];
753 /* Conditional tag - see opcode_lookup. */
754 unsigned int tag
: 4;
756 /* Basic instruction code. */
759 /* Thumb-format instruction code. */
762 /* Which architecture variant provides this instruction. */
763 const arm_feature_set
* avariant
;
764 const arm_feature_set
* tvariant
;
766 /* Function to call to encode instruction in ARM format. */
767 void (* aencode
) (void);
769 /* Function to call to encode instruction in Thumb format. */
770 void (* tencode
) (void);
772 /* Indicates whether this instruction may be vector predicated. */
773 unsigned int mayBeVecPred
: 1;
776 /* Defines for various bits that we will want to toggle. */
777 #define INST_IMMEDIATE 0x02000000
778 #define OFFSET_REG 0x02000000
779 #define HWOFFSET_IMM 0x00400000
780 #define SHIFT_BY_REG 0x00000010
781 #define PRE_INDEX 0x01000000
782 #define INDEX_UP 0x00800000
783 #define WRITE_BACK 0x00200000
784 #define LDM_TYPE_2_OR_3 0x00400000
785 #define CPSI_MMOD 0x00020000
787 #define LITERAL_MASK 0xf000f000
788 #define OPCODE_MASK 0xfe1fffff
789 #define V4_STR_BIT 0x00000020
790 #define VLDR_VMOV_SAME 0x0040f000
792 #define T2_SUBS_PC_LR 0xf3de8f00
794 #define DATA_OP_SHIFT 21
795 #define SBIT_SHIFT 20
797 #define T2_OPCODE_MASK 0xfe1fffff
798 #define T2_DATA_OP_SHIFT 21
799 #define T2_SBIT_SHIFT 20
801 #define A_COND_MASK 0xf0000000
802 #define A_PUSH_POP_OP_MASK 0x0fff0000
804 /* Opcodes for pushing/poping registers to/from the stack. */
805 #define A1_OPCODE_PUSH 0x092d0000
806 #define A2_OPCODE_PUSH 0x052d0004
807 #define A2_OPCODE_POP 0x049d0004
809 /* Codes to distinguish the arithmetic instructions. */
820 #define OPCODE_CMP 10
821 #define OPCODE_CMN 11
822 #define OPCODE_ORR 12
823 #define OPCODE_MOV 13
824 #define OPCODE_BIC 14
825 #define OPCODE_MVN 15
827 #define T2_OPCODE_AND 0
828 #define T2_OPCODE_BIC 1
829 #define T2_OPCODE_ORR 2
830 #define T2_OPCODE_ORN 3
831 #define T2_OPCODE_EOR 4
832 #define T2_OPCODE_ADD 8
833 #define T2_OPCODE_ADC 10
834 #define T2_OPCODE_SBC 11
835 #define T2_OPCODE_SUB 13
836 #define T2_OPCODE_RSB 14
838 #define T_OPCODE_MUL 0x4340
839 #define T_OPCODE_TST 0x4200
840 #define T_OPCODE_CMN 0x42c0
841 #define T_OPCODE_NEG 0x4240
842 #define T_OPCODE_MVN 0x43c0
844 #define T_OPCODE_ADD_R3 0x1800
845 #define T_OPCODE_SUB_R3 0x1a00
846 #define T_OPCODE_ADD_HI 0x4400
847 #define T_OPCODE_ADD_ST 0xb000
848 #define T_OPCODE_SUB_ST 0xb080
849 #define T_OPCODE_ADD_SP 0xa800
850 #define T_OPCODE_ADD_PC 0xa000
851 #define T_OPCODE_ADD_I8 0x3000
852 #define T_OPCODE_SUB_I8 0x3800
853 #define T_OPCODE_ADD_I3 0x1c00
854 #define T_OPCODE_SUB_I3 0x1e00
856 #define T_OPCODE_ASR_R 0x4100
857 #define T_OPCODE_LSL_R 0x4080
858 #define T_OPCODE_LSR_R 0x40c0
859 #define T_OPCODE_ROR_R 0x41c0
860 #define T_OPCODE_ASR_I 0x1000
861 #define T_OPCODE_LSL_I 0x0000
862 #define T_OPCODE_LSR_I 0x0800
864 #define T_OPCODE_MOV_I8 0x2000
865 #define T_OPCODE_CMP_I8 0x2800
866 #define T_OPCODE_CMP_LR 0x4280
867 #define T_OPCODE_MOV_HR 0x4600
868 #define T_OPCODE_CMP_HR 0x4500
870 #define T_OPCODE_LDR_PC 0x4800
871 #define T_OPCODE_LDR_SP 0x9800
872 #define T_OPCODE_STR_SP 0x9000
873 #define T_OPCODE_LDR_IW 0x6800
874 #define T_OPCODE_STR_IW 0x6000
875 #define T_OPCODE_LDR_IH 0x8800
876 #define T_OPCODE_STR_IH 0x8000
877 #define T_OPCODE_LDR_IB 0x7800
878 #define T_OPCODE_STR_IB 0x7000
879 #define T_OPCODE_LDR_RW 0x5800
880 #define T_OPCODE_STR_RW 0x5000
881 #define T_OPCODE_LDR_RH 0x5a00
882 #define T_OPCODE_STR_RH 0x5200
883 #define T_OPCODE_LDR_RB 0x5c00
884 #define T_OPCODE_STR_RB 0x5400
886 #define T_OPCODE_PUSH 0xb400
887 #define T_OPCODE_POP 0xbc00
889 #define T_OPCODE_BRANCH 0xe000
891 #define THUMB_SIZE 2 /* Size of thumb instruction. */
892 #define THUMB_PP_PC_LR 0x0100
893 #define THUMB_LOAD_BIT 0x0800
894 #define THUMB2_LOAD_BIT 0x00100000
896 #define BAD_SYNTAX _("syntax error")
897 #define BAD_ARGS _("bad arguments to instruction")
898 #define BAD_SP _("r13 not allowed here")
899 #define BAD_PC _("r15 not allowed here")
900 #define BAD_ODD _("Odd register not allowed here")
901 #define BAD_EVEN _("Even register not allowed here")
902 #define BAD_COND _("instruction cannot be conditional")
903 #define BAD_OVERLAP _("registers may not be the same")
904 #define BAD_HIREG _("lo register required")
905 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
906 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
907 #define BAD_BRANCH _("branch must be last instruction in IT block")
908 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
909 #define BAD_NO_VPT _("instruction not allowed in VPT block")
910 #define BAD_NOT_IT _("instruction not allowed in IT block")
911 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
912 #define BAD_FPU _("selected FPU does not support instruction")
913 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
914 #define BAD_OUT_VPT \
915 _("vector predicated instruction should be in VPT/VPST block")
916 #define BAD_IT_COND _("incorrect condition in IT block")
917 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
918 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
919 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
920 #define BAD_PC_ADDRESSING \
921 _("cannot use register index with PC-relative addressing")
922 #define BAD_PC_WRITEBACK \
923 _("cannot use writeback with PC-relative addressing")
924 #define BAD_RANGE _("branch out of range")
925 #define BAD_FP16 _("selected processor does not support fp16 instruction")
926 #define BAD_BF16 _("selected processor does not support bf16 instruction")
927 #define BAD_CDE _("selected processor does not support cde instruction")
928 #define BAD_CDE_COPROC _("coprocessor for insn is not enabled for cde")
929 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
930 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
931 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
933 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
935 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
937 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
939 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
940 #define BAD_MVE_AUTO \
941 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
942 " use a valid -march or -mcpu option.")
943 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
944 "and source operands makes instruction UNPREDICTABLE")
945 #define BAD_EL_TYPE _("bad element type for instruction")
946 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
948 static htab_t arm_ops_hsh
;
949 static htab_t arm_cond_hsh
;
950 static htab_t arm_vcond_hsh
;
951 static htab_t arm_shift_hsh
;
952 static htab_t arm_psr_hsh
;
953 static htab_t arm_v7m_psr_hsh
;
954 static htab_t arm_reg_hsh
;
955 static htab_t arm_reloc_hsh
;
956 static htab_t arm_barrier_opt_hsh
;
958 /* Stuff needed to resolve the label ambiguity
967 symbolS
* last_label_seen
;
968 static int label_is_thumb_function_name
= FALSE
;
970 /* Literal pool structure. Held on a per-section
971 and per-sub-section basis. */
973 #define MAX_LITERAL_POOL_SIZE 1024
974 typedef struct literal_pool
976 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
977 unsigned int next_free_entry
;
983 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
985 struct literal_pool
* next
;
986 unsigned int alignment
;
989 /* Pointer to a linked list of literal pools. */
990 literal_pool
* list_of_pools
= NULL
;
992 typedef enum asmfunc_states
995 WAITING_ASMFUNC_NAME
,
999 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
1002 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
1004 static struct current_pred now_pred
;
1008 now_pred_compatible (int cond
)
1010 return (cond
& ~1) == (now_pred
.cc
& ~1);
1014 conditional_insn (void)
1016 return inst
.cond
!= COND_ALWAYS
;
1019 static int in_pred_block (void);
1021 static int handle_pred_state (void);
1023 static void force_automatic_it_block_close (void);
1025 static void it_fsm_post_encode (void);
1027 #define set_pred_insn_type(type) \
1030 inst.pred_insn_type = type; \
1031 if (handle_pred_state () == FAIL) \
1036 #define set_pred_insn_type_nonvoid(type, failret) \
1039 inst.pred_insn_type = type; \
1040 if (handle_pred_state () == FAIL) \
1045 #define set_pred_insn_type_last() \
1048 if (inst.cond == COND_ALWAYS) \
1049 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1051 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1055 /* Toggle value[pos]. */
1056 #define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1060 /* This array holds the chars that always start a comment. If the
1061 pre-processor is disabled, these aren't very useful. */
1062 char arm_comment_chars
[] = "@";
1064 /* This array holds the chars that only start a comment at the beginning of
1065 a line. If the line seems to have the form '# 123 filename'
1066 .line and .file directives will appear in the pre-processed output. */
1067 /* Note that input_file.c hand checks for '#' at the beginning of the
1068 first line of the input file. This is because the compiler outputs
1069 #NO_APP at the beginning of its output. */
1070 /* Also note that comments like this one will always work. */
1071 const char line_comment_chars
[] = "#";
1073 char arm_line_separator_chars
[] = ";";
1075 /* Chars that can be used to separate mant
1076 from exp in floating point numbers. */
1077 const char EXP_CHARS
[] = "eE";
1079 /* Chars that mean this number is a floating point constant. */
1080 /* As in 0f12.456 */
1081 /* or 0d1.2345e12 */
1083 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPHh";
1085 /* Prefix characters that indicate the start of an immediate
1087 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1089 /* Separator character handling. */
1091 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1093 enum fp_16bit_format
1095 ARM_FP16_FORMAT_IEEE
= 0x1,
1096 ARM_FP16_FORMAT_ALTERNATIVE
= 0x2,
1097 ARM_FP16_FORMAT_DEFAULT
= 0x3
1100 static enum fp_16bit_format fp16_format
= ARM_FP16_FORMAT_DEFAULT
;
1104 skip_past_char (char ** str
, char c
)
1106 /* PR gas/14987: Allow for whitespace before the expected character. */
1107 skip_whitespace (*str
);
1118 #define skip_past_comma(str) skip_past_char (str, ',')
1120 /* Arithmetic expressions (possibly involving symbols). */
1122 /* Return TRUE if anything in the expression is a bignum. */
1125 walk_no_bignums (symbolS
* sp
)
1127 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1130 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1132 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1133 || (symbol_get_value_expression (sp
)->X_op_symbol
1134 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1140 static bfd_boolean in_my_get_expression
= FALSE
;
1142 /* Third argument to my_get_expression. */
1143 #define GE_NO_PREFIX 0
1144 #define GE_IMM_PREFIX 1
1145 #define GE_OPT_PREFIX 2
1146 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1147 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1148 #define GE_OPT_PREFIX_BIG 3
1151 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1155 /* In unified syntax, all prefixes are optional. */
1157 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1160 switch (prefix_mode
)
1162 case GE_NO_PREFIX
: break;
1164 if (!is_immediate_prefix (**str
))
1166 inst
.error
= _("immediate expression requires a # prefix");
1172 case GE_OPT_PREFIX_BIG
:
1173 if (is_immediate_prefix (**str
))
1180 memset (ep
, 0, sizeof (expressionS
));
1182 save_in
= input_line_pointer
;
1183 input_line_pointer
= *str
;
1184 in_my_get_expression
= TRUE
;
1186 in_my_get_expression
= FALSE
;
1188 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1190 /* We found a bad or missing expression in md_operand(). */
1191 *str
= input_line_pointer
;
1192 input_line_pointer
= save_in
;
1193 if (inst
.error
== NULL
)
1194 inst
.error
= (ep
->X_op
== O_absent
1195 ? _("missing expression") :_("bad expression"));
1199 /* Get rid of any bignums now, so that we don't generate an error for which
1200 we can't establish a line number later on. Big numbers are never valid
1201 in instructions, which is where this routine is always called. */
1202 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1203 && (ep
->X_op
== O_big
1204 || (ep
->X_add_symbol
1205 && (walk_no_bignums (ep
->X_add_symbol
)
1207 && walk_no_bignums (ep
->X_op_symbol
))))))
1209 inst
.error
= _("invalid constant");
1210 *str
= input_line_pointer
;
1211 input_line_pointer
= save_in
;
1215 *str
= input_line_pointer
;
1216 input_line_pointer
= save_in
;
1220 /* Turn a string in input_line_pointer into a floating point constant
1221 of type TYPE, and store the appropriate bytes in *LITP. The number
1222 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1223 returned, or NULL on OK.
1225 Note that fp constants aren't represent in the normal way on the ARM.
1226 In big endian mode, things are as expected. However, in little endian
1227 mode fp constants are big-endian word-wise, and little-endian byte-wise
1228 within the words. For example, (double) 1.1 in big endian mode is
1229 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1230 the byte sequence 99 99 f1 3f 9a 99 99 99.
1232 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1235 md_atof (int type
, char * litP
, int * sizeP
)
1238 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1249 /* If this is a bfloat16, then parse it slightly differently, as it
1250 does not follow the IEEE specification for floating point numbers
1254 FLONUM_TYPE generic_float
;
1256 t
= atof_ieee_detail (input_line_pointer
, 1, 8, words
, &generic_float
);
1259 input_line_pointer
= t
;
1261 return _("invalid floating point number");
1263 switch (generic_float
.sign
)
1276 /* bfloat16 has two types of NaN - quiet and signalling.
1277 Quiet NaN has bit[6] == 1 && faction != 0, whereas
1278 signalling NaN's have bit[0] == 0 && fraction != 0.
1279 Chosen this specific encoding as it is the same form
1280 as used by other IEEE 754 encodings in GAS. */
1291 md_number_to_chars (litP
, (valueT
) words
[0], sizeof (LITTLENUM_TYPE
));
1321 return _("Unrecognized or unsupported floating point constant");
1324 t
= atof_ieee (input_line_pointer
, type
, words
);
1326 input_line_pointer
= t
;
1327 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1329 if (target_big_endian
|| prec
== 1)
1330 for (i
= 0; i
< prec
; i
++)
1332 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1333 litP
+= sizeof (LITTLENUM_TYPE
);
1335 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1336 for (i
= prec
- 1; i
>= 0; i
--)
1338 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1339 litP
+= sizeof (LITTLENUM_TYPE
);
1342 /* For a 4 byte float the order of elements in `words' is 1 0.
1343 For an 8 byte float the order is 1 0 3 2. */
1344 for (i
= 0; i
< prec
; i
+= 2)
1346 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1347 sizeof (LITTLENUM_TYPE
));
1348 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1349 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1350 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1356 /* We handle all bad expressions here, so that we can report the faulty
1357 instruction in the error message. */
1360 md_operand (expressionS
* exp
)
1362 if (in_my_get_expression
)
1363 exp
->X_op
= O_illegal
;
1366 /* Immediate values. */
1369 /* Generic immediate-value read function for use in directives.
1370 Accepts anything that 'expression' can fold to a constant.
1371 *val receives the number. */
1374 immediate_for_directive (int *val
)
1377 exp
.X_op
= O_illegal
;
1379 if (is_immediate_prefix (*input_line_pointer
))
1381 input_line_pointer
++;
1385 if (exp
.X_op
!= O_constant
)
1387 as_bad (_("expected #constant"));
1388 ignore_rest_of_line ();
1391 *val
= exp
.X_add_number
;
1396 /* Register parsing. */
1398 /* Generic register parser. CCP points to what should be the
1399 beginning of a register name. If it is indeed a valid register
1400 name, advance CCP over it and return the reg_entry structure;
1401 otherwise return NULL. Does not issue diagnostics. */
1403 static struct reg_entry
*
1404 arm_reg_parse_multi (char **ccp
)
1408 struct reg_entry
*reg
;
1410 skip_whitespace (start
);
1412 #ifdef REGISTER_PREFIX
1413 if (*start
!= REGISTER_PREFIX
)
1417 #ifdef OPTIONAL_REGISTER_PREFIX
1418 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1423 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1428 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1430 reg
= (struct reg_entry
*) str_hash_find_n (arm_reg_hsh
, start
, p
- start
);
1440 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1441 enum arm_reg_type type
)
1443 /* Alternative syntaxes are accepted for a few register classes. */
1450 /* Generic coprocessor register names are allowed for these. */
1451 if (reg
&& reg
->type
== REG_TYPE_CN
)
1456 /* For backward compatibility, a bare number is valid here. */
1458 unsigned long processor
= strtoul (start
, ccp
, 10);
1459 if (*ccp
!= start
&& processor
<= 15)
1464 case REG_TYPE_MMXWC
:
1465 /* WC includes WCG. ??? I'm not sure this is true for all
1466 instructions that take WC registers. */
1467 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1478 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1479 return value is the register number or FAIL. */
1482 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1485 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1488 /* Do not allow a scalar (reg+index) to parse as a register. */
1489 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1492 if (reg
&& reg
->type
== type
)
1495 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1502 /* Parse a Neon type specifier. *STR should point at the leading '.'
1503 character. Does no verification at this stage that the type fits the opcode
1510 Can all be legally parsed by this function.
1512 Fills in neon_type struct pointer with parsed information, and updates STR
1513 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1514 type, FAIL if not. */
1517 parse_neon_type (struct neon_type
*type
, char **str
)
1524 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1526 enum neon_el_type thistype
= NT_untyped
;
1527 unsigned thissize
= -1u;
1534 /* Just a size without an explicit type. */
1538 switch (TOLOWER (*ptr
))
1540 case 'i': thistype
= NT_integer
; break;
1541 case 'f': thistype
= NT_float
; break;
1542 case 'p': thistype
= NT_poly
; break;
1543 case 's': thistype
= NT_signed
; break;
1544 case 'u': thistype
= NT_unsigned
; break;
1546 thistype
= NT_float
;
1551 thistype
= NT_bfloat
;
1552 switch (TOLOWER (*(++ptr
)))
1556 thissize
= strtoul (ptr
, &ptr
, 10);
1559 as_bad (_("bad size %d in type specifier"), thissize
);
1563 case '0': case '1': case '2': case '3': case '4':
1564 case '5': case '6': case '7': case '8': case '9':
1566 as_bad (_("unexpected type character `b' -- did you mean `bf'?"));
1573 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1579 /* .f is an abbreviation for .f32. */
1580 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1585 thissize
= strtoul (ptr
, &ptr
, 10);
1587 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1590 as_bad (_("bad size %d in type specifier"), thissize
);
1598 type
->el
[type
->elems
].type
= thistype
;
1599 type
->el
[type
->elems
].size
= thissize
;
1604 /* Empty/missing type is not a successful parse. */
1605 if (type
->elems
== 0)
1613 /* Errors may be set multiple times during parsing or bit encoding
1614 (particularly in the Neon bits), but usually the earliest error which is set
1615 will be the most meaningful. Avoid overwriting it with later (cascading)
1616 errors by calling this function. */
1619 first_error (const char *err
)
1625 /* Parse a single type, e.g. ".s32", leading period included. */
1627 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1630 struct neon_type optype
;
1634 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1636 if (optype
.elems
== 1)
1637 *vectype
= optype
.el
[0];
1640 first_error (_("only one type should be specified for operand"));
1646 first_error (_("vector type expected"));
1658 /* Special meanings for indices (which have a range of 0-7), which will fit into
1661 #define NEON_ALL_LANES 15
1662 #define NEON_INTERLEAVE_LANES 14
1664 /* Record a use of the given feature. */
1666 record_feature_use (const arm_feature_set
*feature
)
1669 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1671 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1674 /* If the given feature available in the selected CPU, mark it as used.
1675 Returns TRUE iff feature is available. */
1677 mark_feature_used (const arm_feature_set
*feature
)
1680 /* Do not support the use of MVE only instructions when in auto-detection or
1682 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1683 && ARM_CPU_IS_ANY (cpu_variant
))
1685 first_error (BAD_MVE_AUTO
);
1688 /* Ensure the option is valid on the current architecture. */
1689 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1692 /* Add the appropriate architecture feature for the barrier option used.
1694 record_feature_use (feature
);
1699 /* Parse either a register or a scalar, with an optional type. Return the
1700 register number, and optionally fill in the actual type of the register
1701 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1702 type/index information in *TYPEINFO. */
1705 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1706 enum arm_reg_type
*rtype
,
1707 struct neon_typed_alias
*typeinfo
)
1710 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1711 struct neon_typed_alias atype
;
1712 struct neon_type_el parsetype
;
1716 atype
.eltype
.type
= NT_invtype
;
1717 atype
.eltype
.size
= -1;
1719 /* Try alternate syntax for some types of register. Note these are mutually
1720 exclusive with the Neon syntax extensions. */
1723 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1731 /* Undo polymorphism when a set of register types may be accepted. */
1732 if ((type
== REG_TYPE_NDQ
1733 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1734 || (type
== REG_TYPE_VFSD
1735 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1736 || (type
== REG_TYPE_NSDQ
1737 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1738 || reg
->type
== REG_TYPE_NQ
))
1739 || (type
== REG_TYPE_NSD
1740 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1741 || (type
== REG_TYPE_MMXWC
1742 && (reg
->type
== REG_TYPE_MMXWCG
)))
1743 type
= (enum arm_reg_type
) reg
->type
;
1745 if (type
== REG_TYPE_MQ
)
1747 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1750 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1753 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1755 first_error (_("expected MVE register [q0..q7]"));
1760 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1761 && (type
== REG_TYPE_NQ
))
1765 if (type
!= reg
->type
)
1771 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1773 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1775 first_error (_("can't redefine type for operand"));
1778 atype
.defined
|= NTA_HASTYPE
;
1779 atype
.eltype
= parsetype
;
1782 if (skip_past_char (&str
, '[') == SUCCESS
)
1784 if (type
!= REG_TYPE_VFD
1785 && !(type
== REG_TYPE_VFS
1786 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1787 && !(type
== REG_TYPE_NQ
1788 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1790 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1791 first_error (_("only D and Q registers may be indexed"));
1793 first_error (_("only D registers may be indexed"));
1797 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1799 first_error (_("can't change index for operand"));
1803 atype
.defined
|= NTA_HASINDEX
;
1805 if (skip_past_char (&str
, ']') == SUCCESS
)
1806 atype
.index
= NEON_ALL_LANES
;
1811 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1813 if (exp
.X_op
!= O_constant
)
1815 first_error (_("constant expression required"));
1819 if (skip_past_char (&str
, ']') == FAIL
)
1822 atype
.index
= exp
.X_add_number
;
1837 /* Like arm_reg_parse, but also allow the following extra features:
1838 - If RTYPE is non-zero, return the (possibly restricted) type of the
1839 register (e.g. Neon double or quad reg when either has been requested).
1840 - If this is a Neon vector type with additional type information, fill
1841 in the struct pointed to by VECTYPE (if non-NULL).
1842 This function will fault on encountering a scalar. */
1845 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1846 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1848 struct neon_typed_alias atype
;
1850 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1855 /* Do not allow regname(... to parse as a register. */
1859 /* Do not allow a scalar (reg+index) to parse as a register. */
1860 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1862 first_error (_("register operand expected, but got scalar"));
1867 *vectype
= atype
.eltype
;
1874 #define NEON_SCALAR_REG(X) ((X) >> 4)
1875 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1877 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1878 have enough information to be able to do a good job bounds-checking. So, we
1879 just do easy checks here, and do further checks later. */
1882 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1883 arm_reg_type reg_type
)
1887 struct neon_typed_alias atype
;
1890 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1908 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1911 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1913 first_error (_("scalar must have an index"));
1916 else if (atype
.index
>= reg_size
/ elsize
)
1918 first_error (_("scalar index out of range"));
1923 *type
= atype
.eltype
;
1927 return reg
* 16 + atype
.index
;
1930 /* Types of registers in a list. */
1943 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1946 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1952 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1954 /* We come back here if we get ranges concatenated by '+' or '|'. */
1957 skip_whitespace (str
);
1970 const char apsr_str
[] = "apsr";
1971 int apsr_str_len
= strlen (apsr_str
);
1973 reg
= arm_reg_parse (&str
, REG_TYPE_RN
);
1974 if (etype
== REGLIST_CLRM
)
1976 if (reg
== REG_SP
|| reg
== REG_PC
)
1978 else if (reg
== FAIL
1979 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1980 && !ISALPHA (*(str
+ apsr_str_len
)))
1983 str
+= apsr_str_len
;
1988 first_error (_("r0-r12, lr or APSR expected"));
1992 else /* etype == REGLIST_RN. */
1996 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
2007 first_error (_("bad range in register list"));
2011 for (i
= cur_reg
+ 1; i
< reg
; i
++)
2013 if (range
& (1 << i
))
2015 (_("Warning: duplicated register (r%d) in register list"),
2023 if (range
& (1 << reg
))
2024 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
2026 else if (reg
<= cur_reg
)
2027 as_tsktsk (_("Warning: register range not in ascending order"));
2032 while (skip_past_comma (&str
) != FAIL
2033 || (in_range
= 1, *str
++ == '-'));
2036 if (skip_past_char (&str
, '}') == FAIL
)
2038 first_error (_("missing `}'"));
2042 else if (etype
== REGLIST_RN
)
2046 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
2049 if (exp
.X_op
== O_constant
)
2051 if (exp
.X_add_number
2052 != (exp
.X_add_number
& 0x0000ffff))
2054 inst
.error
= _("invalid register mask");
2058 if ((range
& exp
.X_add_number
) != 0)
2060 int regno
= range
& exp
.X_add_number
;
2063 regno
= (1 << regno
) - 1;
2065 (_("Warning: duplicated register (r%d) in register list"),
2069 range
|= exp
.X_add_number
;
2073 if (inst
.relocs
[0].type
!= 0)
2075 inst
.error
= _("expression too complex");
2079 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
2080 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
2081 inst
.relocs
[0].pc_rel
= 0;
2085 if (*str
== '|' || *str
== '+')
2091 while (another_range
);
2097 /* Parse a VFP register list. If the string is invalid return FAIL.
2098 Otherwise return the number of registers, and set PBASE to the first
2099 register. Parses registers of type ETYPE.
2100 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
2101 - Q registers can be used to specify pairs of D registers
2102 - { } can be omitted from around a singleton register list
2103 FIXME: This is not implemented, as it would require backtracking in
2106 This could be done (the meaning isn't really ambiguous), but doesn't
2107 fit in well with the current parsing framework.
2108 - 32 D registers may be used (also true for VFPv3).
2109 FIXME: Types are ignored in these register lists, which is probably a
2113 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
2114 bfd_boolean
*partial_match
)
2119 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
2123 unsigned long mask
= 0;
2125 bfd_boolean vpr_seen
= FALSE
;
2126 bfd_boolean expect_vpr
=
2127 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2129 if (skip_past_char (&str
, '{') == FAIL
)
2131 inst
.error
= _("expecting {");
2138 case REGLIST_VFP_S_VPR
:
2139 regtype
= REG_TYPE_VFS
;
2144 case REGLIST_VFP_D_VPR
:
2145 regtype
= REG_TYPE_VFD
;
2148 case REGLIST_NEON_D
:
2149 regtype
= REG_TYPE_NDQ
;
2156 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2158 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2159 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2163 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2166 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2173 base_reg
= max_regs
;
2174 *partial_match
= FALSE
;
2178 unsigned int setmask
= 1, addregs
= 1;
2179 const char vpr_str
[] = "vpr";
2180 size_t vpr_str_len
= strlen (vpr_str
);
2182 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2186 if (new_base
== FAIL
2187 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2188 && !ISALPHA (*(str
+ vpr_str_len
))
2194 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2198 first_error (_("VPR expected last"));
2201 else if (new_base
== FAIL
)
2203 if (regtype
== REG_TYPE_VFS
)
2204 first_error (_("VFP single precision register or VPR "
2206 else /* regtype == REG_TYPE_VFD. */
2207 first_error (_("VFP/Neon double precision register or VPR "
2212 else if (new_base
== FAIL
)
2214 first_error (_(reg_expected_msgs
[regtype
]));
2218 *partial_match
= TRUE
;
2222 if (new_base
>= max_regs
)
2224 first_error (_("register out of range in list"));
2228 /* Note: a value of 2 * n is returned for the register Q<n>. */
2229 if (regtype
== REG_TYPE_NQ
)
2235 if (new_base
< base_reg
)
2236 base_reg
= new_base
;
2238 if (mask
& (setmask
<< new_base
))
2240 first_error (_("invalid register list"));
2244 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2246 as_tsktsk (_("register list not in ascending order"));
2250 mask
|= setmask
<< new_base
;
2253 if (*str
== '-') /* We have the start of a range expression */
2259 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2262 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2266 if (high_range
>= max_regs
)
2268 first_error (_("register out of range in list"));
2272 if (regtype
== REG_TYPE_NQ
)
2273 high_range
= high_range
+ 1;
2275 if (high_range
<= new_base
)
2277 inst
.error
= _("register range not in ascending order");
2281 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2283 if (mask
& (setmask
<< new_base
))
2285 inst
.error
= _("invalid register list");
2289 mask
|= setmask
<< new_base
;
2294 while (skip_past_comma (&str
) != FAIL
);
2298 /* Sanity check -- should have raised a parse error above. */
2299 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2304 if (expect_vpr
&& !vpr_seen
)
2306 first_error (_("VPR expected last"));
2310 /* Final test -- the registers must be consecutive. */
2312 for (i
= 0; i
< count
; i
++)
2314 if ((mask
& (1u << i
)) == 0)
2316 inst
.error
= _("non-contiguous register range");
2326 /* True if two alias types are the same. */
2329 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2337 if (a
->defined
!= b
->defined
)
2340 if ((a
->defined
& NTA_HASTYPE
) != 0
2341 && (a
->eltype
.type
!= b
->eltype
.type
2342 || a
->eltype
.size
!= b
->eltype
.size
))
2345 if ((a
->defined
& NTA_HASINDEX
) != 0
2346 && (a
->index
!= b
->index
))
2352 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2353 The base register is put in *PBASE.
2354 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2356 The register stride (minus one) is put in bit 4 of the return value.
2357 Bits [6:5] encode the list length (minus one).
2358 The type of the list elements is put in *ELTYPE, if non-NULL. */
2360 #define NEON_LANE(X) ((X) & 0xf)
2361 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2362 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2365 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2367 struct neon_type_el
*eltype
)
2374 int leading_brace
= 0;
2375 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2376 const char *const incr_error
= mve
? _("register stride must be 1") :
2377 _("register stride must be 1 or 2");
2378 const char *const type_error
= _("mismatched element/structure types in list");
2379 struct neon_typed_alias firsttype
;
2380 firsttype
.defined
= 0;
2381 firsttype
.eltype
.type
= NT_invtype
;
2382 firsttype
.eltype
.size
= -1;
2383 firsttype
.index
= -1;
2385 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2390 struct neon_typed_alias atype
;
2392 rtype
= REG_TYPE_MQ
;
2393 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2397 first_error (_(reg_expected_msgs
[rtype
]));
2404 if (rtype
== REG_TYPE_NQ
)
2410 else if (reg_incr
== -1)
2412 reg_incr
= getreg
- base_reg
;
2413 if (reg_incr
< 1 || reg_incr
> 2)
2415 first_error (_(incr_error
));
2419 else if (getreg
!= base_reg
+ reg_incr
* count
)
2421 first_error (_(incr_error
));
2425 if (! neon_alias_types_same (&atype
, &firsttype
))
2427 first_error (_(type_error
));
2431 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2435 struct neon_typed_alias htype
;
2436 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2438 lane
= NEON_INTERLEAVE_LANES
;
2439 else if (lane
!= NEON_INTERLEAVE_LANES
)
2441 first_error (_(type_error
));
2446 else if (reg_incr
!= 1)
2448 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2452 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2455 first_error (_(reg_expected_msgs
[rtype
]));
2458 if (! neon_alias_types_same (&htype
, &firsttype
))
2460 first_error (_(type_error
));
2463 count
+= hireg
+ dregs
- getreg
;
2467 /* If we're using Q registers, we can't use [] or [n] syntax. */
2468 if (rtype
== REG_TYPE_NQ
)
2474 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2478 else if (lane
!= atype
.index
)
2480 first_error (_(type_error
));
2484 else if (lane
== -1)
2485 lane
= NEON_INTERLEAVE_LANES
;
2486 else if (lane
!= NEON_INTERLEAVE_LANES
)
2488 first_error (_(type_error
));
2493 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2495 /* No lane set by [x]. We must be interleaving structures. */
2497 lane
= NEON_INTERLEAVE_LANES
;
2500 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2501 || (count
> 1 && reg_incr
== -1))
2503 first_error (_("error parsing element/structure list"));
2507 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2509 first_error (_("expected }"));
2517 *eltype
= firsttype
.eltype
;
2522 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2525 /* Parse an explicit relocation suffix on an expression. This is
2526 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2527 arm_reloc_hsh contains no entries, so this function can only
2528 succeed if there is no () after the word. Returns -1 on error,
2529 BFD_RELOC_UNUSED if there wasn't any suffix. */
2532 parse_reloc (char **str
)
2534 struct reloc_entry
*r
;
2538 return BFD_RELOC_UNUSED
;
2543 while (*q
&& *q
!= ')' && *q
!= ',')
2548 if ((r
= (struct reloc_entry
*)
2549 str_hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2556 /* Directives: register aliases. */
2558 static struct reg_entry
*
2559 insert_reg_alias (char *str
, unsigned number
, int type
)
2561 struct reg_entry
*new_reg
;
2564 if ((new_reg
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, str
)) != 0)
2566 if (new_reg
->builtin
)
2567 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2569 /* Only warn about a redefinition if it's not defined as the
2571 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2572 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2577 name
= xstrdup (str
);
2578 new_reg
= XNEW (struct reg_entry
);
2580 new_reg
->name
= name
;
2581 new_reg
->number
= number
;
2582 new_reg
->type
= type
;
2583 new_reg
->builtin
= FALSE
;
2584 new_reg
->neon
= NULL
;
2586 str_hash_insert (arm_reg_hsh
, name
, new_reg
, 0);
2592 insert_neon_reg_alias (char *str
, int number
, int type
,
2593 struct neon_typed_alias
*atype
)
2595 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2599 first_error (_("attempt to redefine typed alias"));
2605 reg
->neon
= XNEW (struct neon_typed_alias
);
2606 *reg
->neon
= *atype
;
2610 /* Look for the .req directive. This is of the form:
2612 new_register_name .req existing_register_name
2614 If we find one, or if it looks sufficiently like one that we want to
2615 handle any error here, return TRUE. Otherwise return FALSE. */
2618 create_register_alias (char * newname
, char *p
)
2620 struct reg_entry
*old
;
2621 char *oldname
, *nbuf
;
2624 /* The input scrubber ensures that whitespace after the mnemonic is
2625 collapsed to single spaces. */
2627 if (strncmp (oldname
, " .req ", 6) != 0)
2631 if (*oldname
== '\0')
2634 old
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, oldname
);
2637 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2641 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2642 the desired alias name, and p points to its end. If not, then
2643 the desired alias name is in the global original_case_string. */
2644 #ifdef TC_CASE_SENSITIVE
2647 newname
= original_case_string
;
2648 nlen
= strlen (newname
);
2651 nbuf
= xmemdup0 (newname
, nlen
);
2653 /* Create aliases under the new name as stated; an all-lowercase
2654 version of the new name; and an all-uppercase version of the new
2656 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2658 for (p
= nbuf
; *p
; p
++)
2661 if (strncmp (nbuf
, newname
, nlen
))
2663 /* If this attempt to create an additional alias fails, do not bother
2664 trying to create the all-lower case alias. We will fail and issue
2665 a second, duplicate error message. This situation arises when the
2666 programmer does something like:
2669 The second .req creates the "Foo" alias but then fails to create
2670 the artificial FOO alias because it has already been created by the
2672 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2679 for (p
= nbuf
; *p
; p
++)
2682 if (strncmp (nbuf
, newname
, nlen
))
2683 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2690 /* Create a Neon typed/indexed register alias using directives, e.g.:
2695 These typed registers can be used instead of the types specified after the
2696 Neon mnemonic, so long as all operands given have types. Types can also be
2697 specified directly, e.g.:
2698 vadd d0.s32, d1.s32, d2.s32 */
2701 create_neon_reg_alias (char *newname
, char *p
)
2703 enum arm_reg_type basetype
;
2704 struct reg_entry
*basereg
;
2705 struct reg_entry mybasereg
;
2706 struct neon_type ntype
;
2707 struct neon_typed_alias typeinfo
;
2708 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2711 typeinfo
.defined
= 0;
2712 typeinfo
.eltype
.type
= NT_invtype
;
2713 typeinfo
.eltype
.size
= -1;
2714 typeinfo
.index
= -1;
2718 if (strncmp (p
, " .dn ", 5) == 0)
2719 basetype
= REG_TYPE_VFD
;
2720 else if (strncmp (p
, " .qn ", 5) == 0)
2721 basetype
= REG_TYPE_NQ
;
2730 basereg
= arm_reg_parse_multi (&p
);
2732 if (basereg
&& basereg
->type
!= basetype
)
2734 as_bad (_("bad type for register"));
2738 if (basereg
== NULL
)
2741 /* Try parsing as an integer. */
2742 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2743 if (exp
.X_op
!= O_constant
)
2745 as_bad (_("expression must be constant"));
2748 basereg
= &mybasereg
;
2749 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2755 typeinfo
= *basereg
->neon
;
2757 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2759 /* We got a type. */
2760 if (typeinfo
.defined
& NTA_HASTYPE
)
2762 as_bad (_("can't redefine the type of a register alias"));
2766 typeinfo
.defined
|= NTA_HASTYPE
;
2767 if (ntype
.elems
!= 1)
2769 as_bad (_("you must specify a single type only"));
2772 typeinfo
.eltype
= ntype
.el
[0];
2775 if (skip_past_char (&p
, '[') == SUCCESS
)
2778 /* We got a scalar index. */
2780 if (typeinfo
.defined
& NTA_HASINDEX
)
2782 as_bad (_("can't redefine the index of a scalar alias"));
2786 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2788 if (exp
.X_op
!= O_constant
)
2790 as_bad (_("scalar index must be constant"));
2794 typeinfo
.defined
|= NTA_HASINDEX
;
2795 typeinfo
.index
= exp
.X_add_number
;
2797 if (skip_past_char (&p
, ']') == FAIL
)
2799 as_bad (_("expecting ]"));
2804 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2805 the desired alias name, and p points to its end. If not, then
2806 the desired alias name is in the global original_case_string. */
2807 #ifdef TC_CASE_SENSITIVE
2808 namelen
= nameend
- newname
;
2810 newname
= original_case_string
;
2811 namelen
= strlen (newname
);
2814 namebuf
= xmemdup0 (newname
, namelen
);
2816 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2817 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2819 /* Insert name in all uppercase. */
2820 for (p
= namebuf
; *p
; p
++)
2823 if (strncmp (namebuf
, newname
, namelen
))
2824 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2825 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2827 /* Insert name in all lowercase. */
2828 for (p
= namebuf
; *p
; p
++)
2831 if (strncmp (namebuf
, newname
, namelen
))
2832 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2833 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2839 /* Should never be called, as .req goes between the alias and the
2840 register name, not at the beginning of the line. */
2843 s_req (int a ATTRIBUTE_UNUSED
)
2845 as_bad (_("invalid syntax for .req directive"));
2849 s_dn (int a ATTRIBUTE_UNUSED
)
2851 as_bad (_("invalid syntax for .dn directive"));
2855 s_qn (int a ATTRIBUTE_UNUSED
)
2857 as_bad (_("invalid syntax for .qn directive"));
2860 /* The .unreq directive deletes an alias which was previously defined
2861 by .req. For example:
2867 s_unreq (int a ATTRIBUTE_UNUSED
)
2872 name
= input_line_pointer
;
2874 while (*input_line_pointer
!= 0
2875 && *input_line_pointer
!= ' '
2876 && *input_line_pointer
!= '\n')
2877 ++input_line_pointer
;
2879 saved_char
= *input_line_pointer
;
2880 *input_line_pointer
= 0;
2883 as_bad (_("invalid syntax for .unreq directive"));
2886 struct reg_entry
*reg
2887 = (struct reg_entry
*) str_hash_find (arm_reg_hsh
, name
);
2890 as_bad (_("unknown register alias '%s'"), name
);
2891 else if (reg
->builtin
)
2892 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2899 str_hash_delete (arm_reg_hsh
, name
);
2900 free ((char *) reg
->name
);
2904 /* Also locate the all upper case and all lower case versions.
2905 Do not complain if we cannot find one or the other as it
2906 was probably deleted above. */
2908 nbuf
= strdup (name
);
2909 for (p
= nbuf
; *p
; p
++)
2911 reg
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, nbuf
);
2914 str_hash_delete (arm_reg_hsh
, nbuf
);
2915 free ((char *) reg
->name
);
2920 for (p
= nbuf
; *p
; p
++)
2922 reg
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, nbuf
);
2925 str_hash_delete (arm_reg_hsh
, nbuf
);
2926 free ((char *) reg
->name
);
2935 *input_line_pointer
= saved_char
;
2936 demand_empty_rest_of_line ();
2939 /* Directives: Instruction set selection. */
2942 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2943 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2944 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2945 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2947 /* Create a new mapping symbol for the transition to STATE. */
2950 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2953 const char * symname
;
2960 type
= BSF_NO_FLAGS
;
2964 type
= BSF_NO_FLAGS
;
2968 type
= BSF_NO_FLAGS
;
2974 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
2975 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2980 THUMB_SET_FUNC (symbolP
, 0);
2981 ARM_SET_THUMB (symbolP
, 0);
2982 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2986 THUMB_SET_FUNC (symbolP
, 1);
2987 ARM_SET_THUMB (symbolP
, 1);
2988 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2996 /* Save the mapping symbols for future reference. Also check that
2997 we do not place two mapping symbols at the same offset within a
2998 frag. We'll handle overlap between frags in
2999 check_mapping_symbols.
3001 If .fill or other data filling directive generates zero sized data,
3002 the mapping symbol for the following code will have the same value
3003 as the one generated for the data filling directive. In this case,
3004 we replace the old symbol with the new one at the same address. */
3007 if (frag
->tc_frag_data
.first_map
!= NULL
)
3009 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
3010 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
3012 frag
->tc_frag_data
.first_map
= symbolP
;
3014 if (frag
->tc_frag_data
.last_map
!= NULL
)
3016 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
3017 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
3018 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
3020 frag
->tc_frag_data
.last_map
= symbolP
;
3023 /* We must sometimes convert a region marked as code to data during
3024 code alignment, if an odd number of bytes have to be padded. The
3025 code mapping symbol is pushed to an aligned address. */
3028 insert_data_mapping_symbol (enum mstate state
,
3029 valueT value
, fragS
*frag
, offsetT bytes
)
3031 /* If there was already a mapping symbol, remove it. */
3032 if (frag
->tc_frag_data
.last_map
!= NULL
3033 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
3035 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
3039 know (frag
->tc_frag_data
.first_map
== symp
);
3040 frag
->tc_frag_data
.first_map
= NULL
;
3042 frag
->tc_frag_data
.last_map
= NULL
;
3043 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
3046 make_mapping_symbol (MAP_DATA
, value
, frag
);
3047 make_mapping_symbol (state
, value
+ bytes
, frag
);
3050 static void mapping_state_2 (enum mstate state
, int max_chars
);
3052 /* Set the mapping state to STATE. Only call this when about to
3053 emit some STATE bytes to the file. */
3055 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
3057 mapping_state (enum mstate state
)
3059 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
3061 if (mapstate
== state
)
3062 /* The mapping symbol has already been emitted.
3063 There is nothing else to do. */
3066 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
3068 All ARM instructions require 4-byte alignment.
3069 (Almost) all Thumb instructions require 2-byte alignment.
3071 When emitting instructions into any section, mark the section
3074 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
3075 but themselves require 2-byte alignment; this applies to some
3076 PC- relative forms. However, these cases will involve implicit
3077 literal pool generation or an explicit .align >=2, both of
3078 which will cause the section to me marked with sufficient
3079 alignment. Thus, we don't handle those cases here. */
3080 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
3082 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
3083 /* This case will be evaluated later. */
3086 mapping_state_2 (state
, 0);
3089 /* Same as mapping_state, but MAX_CHARS bytes have already been
3090 allocated. Put the mapping symbol that far back. */
3093 mapping_state_2 (enum mstate state
, int max_chars
)
3095 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
3097 if (!SEG_NORMAL (now_seg
))
3100 if (mapstate
== state
)
3101 /* The mapping symbol has already been emitted.
3102 There is nothing else to do. */
3105 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
3106 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
3108 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
3109 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
3112 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
3115 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
3116 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3120 #define mapping_state(x) ((void)0)
3121 #define mapping_state_2(x, y) ((void)0)
3124 /* Find the real, Thumb encoded start of a Thumb function. */
3128 find_real_start (symbolS
* symbolP
)
3131 const char * name
= S_GET_NAME (symbolP
);
3132 symbolS
* new_target
;
3134 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3135 #define STUB_NAME ".real_start_of"
3140 /* The compiler may generate BL instructions to local labels because
3141 it needs to perform a branch to a far away location. These labels
3142 do not have a corresponding ".real_start_of" label. We check
3143 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3144 the ".real_start_of" convention for nonlocal branches. */
3145 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3148 real_start
= concat (STUB_NAME
, name
, NULL
);
3149 new_target
= symbol_find (real_start
);
3152 if (new_target
== NULL
)
3154 as_warn (_("Failed to find real start of function: %s\n"), name
);
3155 new_target
= symbolP
;
3163 opcode_select (int width
)
3170 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3171 as_bad (_("selected processor does not support THUMB opcodes"));
3174 /* No need to force the alignment, since we will have been
3175 coming from ARM mode, which is word-aligned. */
3176 record_alignment (now_seg
, 1);
3183 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3184 as_bad (_("selected processor does not support ARM opcodes"));
3189 frag_align (2, 0, 0);
3191 record_alignment (now_seg
, 1);
3196 as_bad (_("invalid instruction size selected (%d)"), width
);
3201 s_arm (int ignore ATTRIBUTE_UNUSED
)
3204 demand_empty_rest_of_line ();
3208 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3211 demand_empty_rest_of_line ();
3215 s_code (int unused ATTRIBUTE_UNUSED
)
3219 temp
= get_absolute_expression ();
3224 opcode_select (temp
);
3228 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3233 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3235 /* If we are not already in thumb mode go into it, EVEN if
3236 the target processor does not support thumb instructions.
3237 This is used by gcc/config/arm/lib1funcs.asm for example
3238 to compile interworking support functions even if the
3239 target processor should not support interworking. */
3243 record_alignment (now_seg
, 1);
3246 demand_empty_rest_of_line ();
3250 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3254 /* The following label is the name/address of the start of a Thumb function.
3255 We need to know this for the interworking support. */
3256 label_is_thumb_function_name
= TRUE
;
3259 /* Perform a .set directive, but also mark the alias as
3260 being a thumb function. */
3263 s_thumb_set (int equiv
)
3265 /* XXX the following is a duplicate of the code for s_set() in read.c
3266 We cannot just call that code as we need to get at the symbol that
3273 /* Especial apologies for the random logic:
3274 This just grew, and could be parsed much more simply!
3276 delim
= get_symbol_name (& name
);
3277 end_name
= input_line_pointer
;
3278 (void) restore_line_pointer (delim
);
3280 if (*input_line_pointer
!= ',')
3283 as_bad (_("expected comma after name \"%s\""), name
);
3285 ignore_rest_of_line ();
3289 input_line_pointer
++;
3292 if (name
[0] == '.' && name
[1] == '\0')
3294 /* XXX - this should not happen to .thumb_set. */
3298 if ((symbolP
= symbol_find (name
)) == NULL
3299 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3302 /* When doing symbol listings, play games with dummy fragments living
3303 outside the normal fragment chain to record the file and line info
3305 if (listing
& LISTING_SYMBOLS
)
3307 extern struct list_info_struct
* listing_tail
;
3308 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3310 memset (dummy_frag
, 0, sizeof (fragS
));
3311 dummy_frag
->fr_type
= rs_fill
;
3312 dummy_frag
->line
= listing_tail
;
3313 symbolP
= symbol_new (name
, undefined_section
, dummy_frag
, 0);
3314 dummy_frag
->fr_symbol
= symbolP
;
3318 symbolP
= symbol_new (name
, undefined_section
, &zero_address_frag
, 0);
3321 /* "set" symbols are local unless otherwise specified. */
3322 SF_SET_LOCAL (symbolP
);
3323 #endif /* OBJ_COFF */
3324 } /* Make a new symbol. */
3326 symbol_table_insert (symbolP
);
3331 && S_IS_DEFINED (symbolP
)
3332 && S_GET_SEGMENT (symbolP
) != reg_section
)
3333 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3335 pseudo_set (symbolP
);
3337 demand_empty_rest_of_line ();
3339 /* XXX Now we come to the Thumb specific bit of code. */
3341 THUMB_SET_FUNC (symbolP
, 1);
3342 ARM_SET_THUMB (symbolP
, 1);
3343 #if defined OBJ_ELF || defined OBJ_COFF
3344 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3348 /* Directives: Mode selection. */
3350 /* .syntax [unified|divided] - choose the new unified syntax
3351 (same for Arm and Thumb encoding, modulo slight differences in what
3352 can be represented) or the old divergent syntax for each mode. */
3354 s_syntax (int unused ATTRIBUTE_UNUSED
)
3358 delim
= get_symbol_name (& name
);
3360 if (!strcasecmp (name
, "unified"))
3361 unified_syntax
= TRUE
;
3362 else if (!strcasecmp (name
, "divided"))
3363 unified_syntax
= FALSE
;
3366 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3369 (void) restore_line_pointer (delim
);
3370 demand_empty_rest_of_line ();
3373 /* Directives: sectioning and alignment. */
3376 s_bss (int ignore ATTRIBUTE_UNUSED
)
3378 /* We don't support putting frags in the BSS segment, we fake it by
3379 marking in_bss, then looking at s_skip for clues. */
3380 subseg_set (bss_section
, 0);
3381 demand_empty_rest_of_line ();
3383 #ifdef md_elf_section_change_hook
3384 md_elf_section_change_hook ();
3389 s_even (int ignore ATTRIBUTE_UNUSED
)
3391 /* Never make frag if expect extra pass. */
3393 frag_align (1, 0, 0);
3395 record_alignment (now_seg
, 1);
3397 demand_empty_rest_of_line ();
3400 /* Directives: CodeComposer Studio. */
3402 /* .ref (for CodeComposer Studio syntax only). */
3404 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3406 if (codecomposer_syntax
)
3407 ignore_rest_of_line ();
3409 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3412 /* If name is not NULL, then it is used for marking the beginning of a
3413 function, whereas if it is NULL then it means the function end. */
3415 asmfunc_debug (const char * name
)
3417 static const char * last_name
= NULL
;
3421 gas_assert (last_name
== NULL
);
3424 if (debug_type
== DEBUG_STABS
)
3425 stabs_generate_asm_func (name
, name
);
3429 gas_assert (last_name
!= NULL
);
3431 if (debug_type
== DEBUG_STABS
)
3432 stabs_generate_asm_endfunc (last_name
, last_name
);
3439 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3441 if (codecomposer_syntax
)
3443 switch (asmfunc_state
)
3445 case OUTSIDE_ASMFUNC
:
3446 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3449 case WAITING_ASMFUNC_NAME
:
3450 as_bad (_(".asmfunc repeated."));
3453 case WAITING_ENDASMFUNC
:
3454 as_bad (_(".asmfunc without function."));
3457 demand_empty_rest_of_line ();
3460 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3464 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3466 if (codecomposer_syntax
)
3468 switch (asmfunc_state
)
3470 case OUTSIDE_ASMFUNC
:
3471 as_bad (_(".endasmfunc without a .asmfunc."));
3474 case WAITING_ASMFUNC_NAME
:
3475 as_bad (_(".endasmfunc without function."));
3478 case WAITING_ENDASMFUNC
:
3479 asmfunc_state
= OUTSIDE_ASMFUNC
;
3480 asmfunc_debug (NULL
);
3483 demand_empty_rest_of_line ();
3486 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3490 s_ccs_def (int name
)
3492 if (codecomposer_syntax
)
3495 as_bad (_(".def pseudo-op only available with -mccs flag."));
3498 /* Directives: Literal pools. */
3500 static literal_pool
*
3501 find_literal_pool (void)
3503 literal_pool
* pool
;
3505 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3507 if (pool
->section
== now_seg
3508 && pool
->sub_section
== now_subseg
)
3515 static literal_pool
*
3516 find_or_make_literal_pool (void)
3518 /* Next literal pool ID number. */
3519 static unsigned int latest_pool_num
= 1;
3520 literal_pool
* pool
;
3522 pool
= find_literal_pool ();
3526 /* Create a new pool. */
3527 pool
= XNEW (literal_pool
);
3531 pool
->next_free_entry
= 0;
3532 pool
->section
= now_seg
;
3533 pool
->sub_section
= now_subseg
;
3534 pool
->next
= list_of_pools
;
3535 pool
->symbol
= NULL
;
3536 pool
->alignment
= 2;
3538 /* Add it to the list. */
3539 list_of_pools
= pool
;
3542 /* New pools, and emptied pools, will have a NULL symbol. */
3543 if (pool
->symbol
== NULL
)
3545 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3546 &zero_address_frag
, 0);
3547 pool
->id
= latest_pool_num
++;
3554 /* Add the literal in the global 'inst'
3555 structure to the relevant literal pool. */
3558 add_to_lit_pool (unsigned int nbytes
)
3560 #define PADDING_SLOT 0x1
3561 #define LIT_ENTRY_SIZE_MASK 0xFF
3562 literal_pool
* pool
;
3563 unsigned int entry
, pool_size
= 0;
3564 bfd_boolean padding_slot_p
= FALSE
;
3570 imm1
= inst
.operands
[1].imm
;
3571 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3572 : inst
.relocs
[0].exp
.X_unsigned
? 0
3573 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3574 if (target_big_endian
)
3577 imm2
= inst
.operands
[1].imm
;
3581 pool
= find_or_make_literal_pool ();
3583 /* Check if this literal value is already in the pool. */
3584 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3588 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3589 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3590 && (pool
->literals
[entry
].X_add_number
3591 == inst
.relocs
[0].exp
.X_add_number
)
3592 && (pool
->literals
[entry
].X_md
== nbytes
)
3593 && (pool
->literals
[entry
].X_unsigned
3594 == inst
.relocs
[0].exp
.X_unsigned
))
3597 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3598 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3599 && (pool
->literals
[entry
].X_add_number
3600 == inst
.relocs
[0].exp
.X_add_number
)
3601 && (pool
->literals
[entry
].X_add_symbol
3602 == inst
.relocs
[0].exp
.X_add_symbol
)
3603 && (pool
->literals
[entry
].X_op_symbol
3604 == inst
.relocs
[0].exp
.X_op_symbol
)
3605 && (pool
->literals
[entry
].X_md
== nbytes
))
3608 else if ((nbytes
== 8)
3609 && !(pool_size
& 0x7)
3610 && ((entry
+ 1) != pool
->next_free_entry
)
3611 && (pool
->literals
[entry
].X_op
== O_constant
)
3612 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3613 && (pool
->literals
[entry
].X_unsigned
3614 == inst
.relocs
[0].exp
.X_unsigned
)
3615 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3616 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3617 && (pool
->literals
[entry
+ 1].X_unsigned
3618 == inst
.relocs
[0].exp
.X_unsigned
))
3621 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3622 if (padding_slot_p
&& (nbytes
== 4))
3628 /* Do we need to create a new entry? */
3629 if (entry
== pool
->next_free_entry
)
3631 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3633 inst
.error
= _("literal pool overflow");
3639 /* For 8-byte entries, we align to an 8-byte boundary,
3640 and split it into two 4-byte entries, because on 32-bit
3641 host, 8-byte constants are treated as big num, thus
3642 saved in "generic_bignum" which will be overwritten
3643 by later assignments.
3645 We also need to make sure there is enough space for
3648 We also check to make sure the literal operand is a
3650 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3651 || inst
.relocs
[0].exp
.X_op
== O_big
))
3653 inst
.error
= _("invalid type for literal pool");
3656 else if (pool_size
& 0x7)
3658 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3660 inst
.error
= _("literal pool overflow");
3664 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3665 pool
->literals
[entry
].X_op
= O_constant
;
3666 pool
->literals
[entry
].X_add_number
= 0;
3667 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3668 pool
->next_free_entry
+= 1;
3671 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3673 inst
.error
= _("literal pool overflow");
3677 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3678 pool
->literals
[entry
].X_op
= O_constant
;
3679 pool
->literals
[entry
].X_add_number
= imm1
;
3680 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3681 pool
->literals
[entry
++].X_md
= 4;
3682 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3683 pool
->literals
[entry
].X_op
= O_constant
;
3684 pool
->literals
[entry
].X_add_number
= imm2
;
3685 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3686 pool
->literals
[entry
].X_md
= 4;
3687 pool
->alignment
= 3;
3688 pool
->next_free_entry
+= 1;
3692 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3693 pool
->literals
[entry
].X_md
= 4;
3697 /* PR ld/12974: Record the location of the first source line to reference
3698 this entry in the literal pool. If it turns out during linking that the
3699 symbol does not exist we will be able to give an accurate line number for
3700 the (first use of the) missing reference. */
3701 if (debug_type
== DEBUG_DWARF2
)
3702 dwarf2_where (pool
->locs
+ entry
);
3704 pool
->next_free_entry
+= 1;
3706 else if (padding_slot_p
)
3708 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3709 pool
->literals
[entry
].X_md
= nbytes
;
3712 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3713 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3714 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3720 tc_start_label_without_colon (void)
3722 bfd_boolean ret
= TRUE
;
3724 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3726 const char *label
= input_line_pointer
;
3728 while (!is_end_of_line
[(int) label
[-1]])
3733 as_bad (_("Invalid label '%s'"), label
);
3737 asmfunc_debug (label
);
3739 asmfunc_state
= WAITING_ENDASMFUNC
;
3745 /* Can't use symbol_new here, so have to create a symbol and then at
3746 a later date assign it a value. That's what these functions do. */
3749 symbol_locate (symbolS
* symbolP
,
3750 const char * name
, /* It is copied, the caller can modify. */
3751 segT segment
, /* Segment identifier (SEG_<something>). */
3752 valueT valu
, /* Symbol value. */
3753 fragS
* frag
) /* Associated fragment. */
3756 char * preserved_copy_of_name
;
3758 name_length
= strlen (name
) + 1; /* +1 for \0. */
3759 obstack_grow (¬es
, name
, name_length
);
3760 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3762 #ifdef tc_canonicalize_symbol_name
3763 preserved_copy_of_name
=
3764 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3767 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3769 S_SET_SEGMENT (symbolP
, segment
);
3770 S_SET_VALUE (symbolP
, valu
);
3771 symbol_clear_list_pointers (symbolP
);
3773 symbol_set_frag (symbolP
, frag
);
3775 /* Link to end of symbol chain. */
3777 extern int symbol_table_frozen
;
3779 if (symbol_table_frozen
)
3783 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3785 obj_symbol_new_hook (symbolP
);
3787 #ifdef tc_symbol_new_hook
3788 tc_symbol_new_hook (symbolP
);
3792 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3793 #endif /* DEBUG_SYMS */
3797 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3800 literal_pool
* pool
;
3803 pool
= find_literal_pool ();
3805 || pool
->symbol
== NULL
3806 || pool
->next_free_entry
== 0)
3809 /* Align pool as you have word accesses.
3810 Only make a frag if we have to. */
3812 frag_align (pool
->alignment
, 0, 0);
3814 record_alignment (now_seg
, 2);
3817 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3818 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3820 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3822 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3823 (valueT
) frag_now_fix (), frag_now
);
3824 symbol_table_insert (pool
->symbol
);
3826 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3828 #if defined OBJ_COFF || defined OBJ_ELF
3829 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3832 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3835 if (debug_type
== DEBUG_DWARF2
)
3836 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3838 /* First output the expression in the instruction to the pool. */
3839 emit_expr (&(pool
->literals
[entry
]),
3840 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3843 /* Mark the pool as empty. */
3844 pool
->next_free_entry
= 0;
3845 pool
->symbol
= NULL
;
3849 /* Forward declarations for functions below, in the MD interface
3851 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3852 static valueT
create_unwind_entry (int);
3853 static void start_unwind_section (const segT
, int);
3854 static void add_unwind_opcode (valueT
, int);
3855 static void flush_pending_unwind (void);
3857 /* Directives: Data. */
3860 s_arm_elf_cons (int nbytes
)
3864 #ifdef md_flush_pending_output
3865 md_flush_pending_output ();
3868 if (is_it_end_of_statement ())
3870 demand_empty_rest_of_line ();
3874 #ifdef md_cons_align
3875 md_cons_align (nbytes
);
3878 mapping_state (MAP_DATA
);
3882 char *base
= input_line_pointer
;
3886 if (exp
.X_op
!= O_symbol
)
3887 emit_expr (&exp
, (unsigned int) nbytes
);
3890 char *before_reloc
= input_line_pointer
;
3891 reloc
= parse_reloc (&input_line_pointer
);
3894 as_bad (_("unrecognized relocation suffix"));
3895 ignore_rest_of_line ();
3898 else if (reloc
== BFD_RELOC_UNUSED
)
3899 emit_expr (&exp
, (unsigned int) nbytes
);
3902 reloc_howto_type
*howto
= (reloc_howto_type
*)
3903 bfd_reloc_type_lookup (stdoutput
,
3904 (bfd_reloc_code_real_type
) reloc
);
3905 int size
= bfd_get_reloc_size (howto
);
3907 if (reloc
== BFD_RELOC_ARM_PLT32
)
3909 as_bad (_("(plt) is only valid on branch targets"));
3910 reloc
= BFD_RELOC_UNUSED
;
3915 as_bad (ngettext ("%s relocations do not fit in %d byte",
3916 "%s relocations do not fit in %d bytes",
3918 howto
->name
, nbytes
);
3921 /* We've parsed an expression stopping at O_symbol.
3922 But there may be more expression left now that we
3923 have parsed the relocation marker. Parse it again.
3924 XXX Surely there is a cleaner way to do this. */
3925 char *p
= input_line_pointer
;
3927 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3929 memcpy (save_buf
, base
, input_line_pointer
- base
);
3930 memmove (base
+ (input_line_pointer
- before_reloc
),
3931 base
, before_reloc
- base
);
3933 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3935 memcpy (base
, save_buf
, p
- base
);
3937 offset
= nbytes
- size
;
3938 p
= frag_more (nbytes
);
3939 memset (p
, 0, nbytes
);
3940 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3941 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3947 while (*input_line_pointer
++ == ',');
3949 /* Put terminator back into stream. */
3950 input_line_pointer
--;
3951 demand_empty_rest_of_line ();
3954 /* Emit an expression containing a 32-bit thumb instruction.
3955 Implementation based on put_thumb32_insn. */
3958 emit_thumb32_expr (expressionS
* exp
)
3960 expressionS exp_high
= *exp
;
3962 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3963 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3964 exp
->X_add_number
&= 0xffff;
3965 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3968 /* Guess the instruction size based on the opcode. */
3971 thumb_insn_size (int opcode
)
3973 if ((unsigned int) opcode
< 0xe800u
)
3975 else if ((unsigned int) opcode
>= 0xe8000000u
)
3982 emit_insn (expressionS
*exp
, int nbytes
)
3986 if (exp
->X_op
== O_constant
)
3991 size
= thumb_insn_size (exp
->X_add_number
);
3995 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3997 as_bad (_(".inst.n operand too big. "\
3998 "Use .inst.w instead"));
4003 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
4004 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
4006 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
4008 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
4009 emit_thumb32_expr (exp
);
4011 emit_expr (exp
, (unsigned int) size
);
4013 it_fsm_post_encode ();
4017 as_bad (_("cannot determine Thumb instruction size. " \
4018 "Use .inst.n/.inst.w instead"));
4021 as_bad (_("constant expression required"));
4026 /* Like s_arm_elf_cons but do not use md_cons_align and
4027 set the mapping state to MAP_ARM/MAP_THUMB. */
4030 s_arm_elf_inst (int nbytes
)
4032 if (is_it_end_of_statement ())
4034 demand_empty_rest_of_line ();
4038 /* Calling mapping_state () here will not change ARM/THUMB,
4039 but will ensure not to be in DATA state. */
4042 mapping_state (MAP_THUMB
);
4047 as_bad (_("width suffixes are invalid in ARM mode"));
4048 ignore_rest_of_line ();
4054 mapping_state (MAP_ARM
);
4063 if (! emit_insn (& exp
, nbytes
))
4065 ignore_rest_of_line ();
4069 while (*input_line_pointer
++ == ',');
4071 /* Put terminator back into stream. */
4072 input_line_pointer
--;
4073 demand_empty_rest_of_line ();
4076 /* Parse a .rel31 directive. */
4079 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
4086 if (*input_line_pointer
== '1')
4087 highbit
= 0x80000000;
4088 else if (*input_line_pointer
!= '0')
4089 as_bad (_("expected 0 or 1"));
4091 input_line_pointer
++;
4092 if (*input_line_pointer
!= ',')
4093 as_bad (_("missing comma"));
4094 input_line_pointer
++;
4096 #ifdef md_flush_pending_output
4097 md_flush_pending_output ();
4100 #ifdef md_cons_align
4104 mapping_state (MAP_DATA
);
4109 md_number_to_chars (p
, highbit
, 4);
4110 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
4111 BFD_RELOC_ARM_PREL31
);
4113 demand_empty_rest_of_line ();
4116 /* Directives: AEABI stack-unwind tables. */
4118 /* Parse an unwind_fnstart directive. Simply records the current location. */
4121 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4123 demand_empty_rest_of_line ();
4124 if (unwind
.proc_start
)
4126 as_bad (_("duplicate .fnstart directive"));
4130 /* Mark the start of the function. */
4131 unwind
.proc_start
= expr_build_dot ();
4133 /* Reset the rest of the unwind info. */
4134 unwind
.opcode_count
= 0;
4135 unwind
.table_entry
= NULL
;
4136 unwind
.personality_routine
= NULL
;
4137 unwind
.personality_index
= -1;
4138 unwind
.frame_size
= 0;
4139 unwind
.fp_offset
= 0;
4140 unwind
.fp_reg
= REG_SP
;
4142 unwind
.sp_restored
= 0;
4146 /* Parse a handlerdata directive. Creates the exception handling table entry
4147 for the function. */
4150 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4152 demand_empty_rest_of_line ();
4153 if (!unwind
.proc_start
)
4154 as_bad (MISSING_FNSTART
);
4156 if (unwind
.table_entry
)
4157 as_bad (_("duplicate .handlerdata directive"));
4159 create_unwind_entry (1);
4162 /* Parse an unwind_fnend directive. Generates the index table entry. */
4165 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4170 unsigned int marked_pr_dependency
;
4172 demand_empty_rest_of_line ();
4174 if (!unwind
.proc_start
)
4176 as_bad (_(".fnend directive without .fnstart"));
4180 /* Add eh table entry. */
4181 if (unwind
.table_entry
== NULL
)
4182 val
= create_unwind_entry (0);
4186 /* Add index table entry. This is two words. */
4187 start_unwind_section (unwind
.saved_seg
, 1);
4188 frag_align (2, 0, 0);
4189 record_alignment (now_seg
, 2);
4191 ptr
= frag_more (8);
4193 where
= frag_now_fix () - 8;
4195 /* Self relative offset of the function start. */
4196 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4197 BFD_RELOC_ARM_PREL31
);
4199 /* Indicate dependency on EHABI-defined personality routines to the
4200 linker, if it hasn't been done already. */
4201 marked_pr_dependency
4202 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4203 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4204 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4206 static const char *const name
[] =
4208 "__aeabi_unwind_cpp_pr0",
4209 "__aeabi_unwind_cpp_pr1",
4210 "__aeabi_unwind_cpp_pr2"
4212 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4213 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4214 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4215 |= 1 << unwind
.personality_index
;
4219 /* Inline exception table entry. */
4220 md_number_to_chars (ptr
+ 4, val
, 4);
4222 /* Self relative offset of the table entry. */
4223 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4224 BFD_RELOC_ARM_PREL31
);
4226 /* Restore the original section. */
4227 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4229 unwind
.proc_start
= NULL
;
4233 /* Parse an unwind_cantunwind directive. */
4236 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4238 demand_empty_rest_of_line ();
4239 if (!unwind
.proc_start
)
4240 as_bad (MISSING_FNSTART
);
4242 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4243 as_bad (_("personality routine specified for cantunwind frame"));
4245 unwind
.personality_index
= -2;
4249 /* Parse a personalityindex directive. */
4252 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4256 if (!unwind
.proc_start
)
4257 as_bad (MISSING_FNSTART
);
4259 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4260 as_bad (_("duplicate .personalityindex directive"));
4264 if (exp
.X_op
!= O_constant
4265 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4267 as_bad (_("bad personality routine number"));
4268 ignore_rest_of_line ();
4272 unwind
.personality_index
= exp
.X_add_number
;
4274 demand_empty_rest_of_line ();
4278 /* Parse a personality directive. */
4281 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4285 if (!unwind
.proc_start
)
4286 as_bad (MISSING_FNSTART
);
4288 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4289 as_bad (_("duplicate .personality directive"));
4291 c
= get_symbol_name (& name
);
4292 p
= input_line_pointer
;
4294 ++ input_line_pointer
;
4295 unwind
.personality_routine
= symbol_find_or_make (name
);
4297 demand_empty_rest_of_line ();
4301 /* Parse a directive saving core registers. */
4304 s_arm_unwind_save_core (void)
4310 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4313 as_bad (_("expected register list"));
4314 ignore_rest_of_line ();
4318 demand_empty_rest_of_line ();
4320 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4321 into .unwind_save {..., sp...}. We aren't bothered about the value of
4322 ip because it is clobbered by calls. */
4323 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4324 && (range
& 0x3000) == 0x1000)
4326 unwind
.opcode_count
--;
4327 unwind
.sp_restored
= 0;
4328 range
= (range
| 0x2000) & ~0x1000;
4329 unwind
.pending_offset
= 0;
4335 /* See if we can use the short opcodes. These pop a block of up to 8
4336 registers starting with r4, plus maybe r14. */
4337 for (n
= 0; n
< 8; n
++)
4339 /* Break at the first non-saved register. */
4340 if ((range
& (1 << (n
+ 4))) == 0)
4343 /* See if there are any other bits set. */
4344 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4346 /* Use the long form. */
4347 op
= 0x8000 | ((range
>> 4) & 0xfff);
4348 add_unwind_opcode (op
, 2);
4352 /* Use the short form. */
4354 op
= 0xa8; /* Pop r14. */
4356 op
= 0xa0; /* Do not pop r14. */
4358 add_unwind_opcode (op
, 1);
4365 op
= 0xb100 | (range
& 0xf);
4366 add_unwind_opcode (op
, 2);
4369 /* Record the number of bytes pushed. */
4370 for (n
= 0; n
< 16; n
++)
4372 if (range
& (1 << n
))
4373 unwind
.frame_size
+= 4;
4378 /* Parse a directive saving FPA registers. */
4381 s_arm_unwind_save_fpa (int reg
)
4387 /* Get Number of registers to transfer. */
4388 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4391 exp
.X_op
= O_illegal
;
4393 if (exp
.X_op
!= O_constant
)
4395 as_bad (_("expected , <constant>"));
4396 ignore_rest_of_line ();
4400 num_regs
= exp
.X_add_number
;
4402 if (num_regs
< 1 || num_regs
> 4)
4404 as_bad (_("number of registers must be in the range [1:4]"));
4405 ignore_rest_of_line ();
4409 demand_empty_rest_of_line ();
4414 op
= 0xb4 | (num_regs
- 1);
4415 add_unwind_opcode (op
, 1);
4420 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4421 add_unwind_opcode (op
, 2);
4423 unwind
.frame_size
+= num_regs
* 12;
4427 /* Parse a directive saving VFP registers for ARMv6 and above. */
4430 s_arm_unwind_save_vfp_armv6 (void)
4435 int num_vfpv3_regs
= 0;
4436 int num_regs_below_16
;
4437 bfd_boolean partial_match
;
4439 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4443 as_bad (_("expected register list"));
4444 ignore_rest_of_line ();
4448 demand_empty_rest_of_line ();
4450 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4451 than FSTMX/FLDMX-style ones). */
4453 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4455 num_vfpv3_regs
= count
;
4456 else if (start
+ count
> 16)
4457 num_vfpv3_regs
= start
+ count
- 16;
4459 if (num_vfpv3_regs
> 0)
4461 int start_offset
= start
> 16 ? start
- 16 : 0;
4462 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4463 add_unwind_opcode (op
, 2);
4466 /* Generate opcode for registers numbered in the range 0 .. 15. */
4467 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4468 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4469 if (num_regs_below_16
> 0)
4471 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4472 add_unwind_opcode (op
, 2);
4475 unwind
.frame_size
+= count
* 8;
4479 /* Parse a directive saving VFP registers for pre-ARMv6. */
4482 s_arm_unwind_save_vfp (void)
4487 bfd_boolean partial_match
;
4489 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4493 as_bad (_("expected register list"));
4494 ignore_rest_of_line ();
4498 demand_empty_rest_of_line ();
4503 op
= 0xb8 | (count
- 1);
4504 add_unwind_opcode (op
, 1);
4509 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4510 add_unwind_opcode (op
, 2);
4512 unwind
.frame_size
+= count
* 8 + 4;
4516 /* Parse a directive saving iWMMXt data registers. */
4519 s_arm_unwind_save_mmxwr (void)
4527 if (*input_line_pointer
== '{')
4528 input_line_pointer
++;
4532 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4536 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4541 as_tsktsk (_("register list not in ascending order"));
4544 if (*input_line_pointer
== '-')
4546 input_line_pointer
++;
4547 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4550 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4553 else if (reg
>= hi_reg
)
4555 as_bad (_("bad register range"));
4558 for (; reg
< hi_reg
; reg
++)
4562 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4564 skip_past_char (&input_line_pointer
, '}');
4566 demand_empty_rest_of_line ();
4568 /* Generate any deferred opcodes because we're going to be looking at
4570 flush_pending_unwind ();
4572 for (i
= 0; i
< 16; i
++)
4574 if (mask
& (1 << i
))
4575 unwind
.frame_size
+= 8;
4578 /* Attempt to combine with a previous opcode. We do this because gcc
4579 likes to output separate unwind directives for a single block of
4581 if (unwind
.opcode_count
> 0)
4583 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4584 if ((i
& 0xf8) == 0xc0)
4587 /* Only merge if the blocks are contiguous. */
4590 if ((mask
& 0xfe00) == (1 << 9))
4592 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4593 unwind
.opcode_count
--;
4596 else if (i
== 6 && unwind
.opcode_count
>= 2)
4598 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4602 op
= 0xffff << (reg
- 1);
4604 && ((mask
& op
) == (1u << (reg
- 1))))
4606 op
= (1 << (reg
+ i
+ 1)) - 1;
4607 op
&= ~((1 << reg
) - 1);
4609 unwind
.opcode_count
-= 2;
4616 /* We want to generate opcodes in the order the registers have been
4617 saved, ie. descending order. */
4618 for (reg
= 15; reg
>= -1; reg
--)
4620 /* Save registers in blocks. */
4622 || !(mask
& (1 << reg
)))
4624 /* We found an unsaved reg. Generate opcodes to save the
4631 op
= 0xc0 | (hi_reg
- 10);
4632 add_unwind_opcode (op
, 1);
4637 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4638 add_unwind_opcode (op
, 2);
4647 ignore_rest_of_line ();
4651 s_arm_unwind_save_mmxwcg (void)
4658 if (*input_line_pointer
== '{')
4659 input_line_pointer
++;
4661 skip_whitespace (input_line_pointer
);
4665 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4669 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4675 as_tsktsk (_("register list not in ascending order"));
4678 if (*input_line_pointer
== '-')
4680 input_line_pointer
++;
4681 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4684 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4687 else if (reg
>= hi_reg
)
4689 as_bad (_("bad register range"));
4692 for (; reg
< hi_reg
; reg
++)
4696 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4698 skip_past_char (&input_line_pointer
, '}');
4700 demand_empty_rest_of_line ();
4702 /* Generate any deferred opcodes because we're going to be looking at
4704 flush_pending_unwind ();
4706 for (reg
= 0; reg
< 16; reg
++)
4708 if (mask
& (1 << reg
))
4709 unwind
.frame_size
+= 4;
4712 add_unwind_opcode (op
, 2);
4715 ignore_rest_of_line ();
4719 /* Parse an unwind_save directive.
4720 If the argument is non-zero, this is a .vsave directive. */
4723 s_arm_unwind_save (int arch_v6
)
4726 struct reg_entry
*reg
;
4727 bfd_boolean had_brace
= FALSE
;
4729 if (!unwind
.proc_start
)
4730 as_bad (MISSING_FNSTART
);
4732 /* Figure out what sort of save we have. */
4733 peek
= input_line_pointer
;
4741 reg
= arm_reg_parse_multi (&peek
);
4745 as_bad (_("register expected"));
4746 ignore_rest_of_line ();
4755 as_bad (_("FPA .unwind_save does not take a register list"));
4756 ignore_rest_of_line ();
4759 input_line_pointer
= peek
;
4760 s_arm_unwind_save_fpa (reg
->number
);
4764 s_arm_unwind_save_core ();
4769 s_arm_unwind_save_vfp_armv6 ();
4771 s_arm_unwind_save_vfp ();
4774 case REG_TYPE_MMXWR
:
4775 s_arm_unwind_save_mmxwr ();
4778 case REG_TYPE_MMXWCG
:
4779 s_arm_unwind_save_mmxwcg ();
4783 as_bad (_(".unwind_save does not support this kind of register"));
4784 ignore_rest_of_line ();
4789 /* Parse an unwind_movsp directive. */
4792 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4798 if (!unwind
.proc_start
)
4799 as_bad (MISSING_FNSTART
);
4801 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4804 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4805 ignore_rest_of_line ();
4809 /* Optional constant. */
4810 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4812 if (immediate_for_directive (&offset
) == FAIL
)
4818 demand_empty_rest_of_line ();
4820 if (reg
== REG_SP
|| reg
== REG_PC
)
4822 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4826 if (unwind
.fp_reg
!= REG_SP
)
4827 as_bad (_("unexpected .unwind_movsp directive"));
4829 /* Generate opcode to restore the value. */
4831 add_unwind_opcode (op
, 1);
4833 /* Record the information for later. */
4834 unwind
.fp_reg
= reg
;
4835 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4836 unwind
.sp_restored
= 1;
4839 /* Parse an unwind_pad directive. */
4842 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4846 if (!unwind
.proc_start
)
4847 as_bad (MISSING_FNSTART
);
4849 if (immediate_for_directive (&offset
) == FAIL
)
4854 as_bad (_("stack increment must be multiple of 4"));
4855 ignore_rest_of_line ();
4859 /* Don't generate any opcodes, just record the details for later. */
4860 unwind
.frame_size
+= offset
;
4861 unwind
.pending_offset
+= offset
;
4863 demand_empty_rest_of_line ();
4866 /* Parse an unwind_setfp directive. */
4869 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4875 if (!unwind
.proc_start
)
4876 as_bad (MISSING_FNSTART
);
4878 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4879 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4882 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4884 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4886 as_bad (_("expected <reg>, <reg>"));
4887 ignore_rest_of_line ();
4891 /* Optional constant. */
4892 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4894 if (immediate_for_directive (&offset
) == FAIL
)
4900 demand_empty_rest_of_line ();
4902 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4904 as_bad (_("register must be either sp or set by a previous"
4905 "unwind_movsp directive"));
4909 /* Don't generate any opcodes, just record the information for later. */
4910 unwind
.fp_reg
= fp_reg
;
4912 if (sp_reg
== REG_SP
)
4913 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4915 unwind
.fp_offset
-= offset
;
4918 /* Parse an unwind_raw directive. */
4921 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4924 /* This is an arbitrary limit. */
4925 unsigned char op
[16];
4928 if (!unwind
.proc_start
)
4929 as_bad (MISSING_FNSTART
);
4932 if (exp
.X_op
== O_constant
4933 && skip_past_comma (&input_line_pointer
) != FAIL
)
4935 unwind
.frame_size
+= exp
.X_add_number
;
4939 exp
.X_op
= O_illegal
;
4941 if (exp
.X_op
!= O_constant
)
4943 as_bad (_("expected <offset>, <opcode>"));
4944 ignore_rest_of_line ();
4950 /* Parse the opcode. */
4955 as_bad (_("unwind opcode too long"));
4956 ignore_rest_of_line ();
4958 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4960 as_bad (_("invalid unwind opcode"));
4961 ignore_rest_of_line ();
4964 op
[count
++] = exp
.X_add_number
;
4966 /* Parse the next byte. */
4967 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4973 /* Add the opcode bytes in reverse order. */
4975 add_unwind_opcode (op
[count
], 1);
4977 demand_empty_rest_of_line ();
4981 /* Parse a .eabi_attribute directive. */
4984 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4986 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4988 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4989 attributes_set_explicitly
[tag
] = 1;
4992 /* Emit a tls fix for the symbol. */
4995 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4999 #ifdef md_flush_pending_output
5000 md_flush_pending_output ();
5003 #ifdef md_cons_align
5007 /* Since we're just labelling the code, there's no need to define a
5010 p
= obstack_next_free (&frchain_now
->frch_obstack
);
5011 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
5012 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
5013 : BFD_RELOC_ARM_TLS_DESCSEQ
);
5015 #endif /* OBJ_ELF */
5017 static void s_arm_arch (int);
5018 static void s_arm_object_arch (int);
5019 static void s_arm_cpu (int);
5020 static void s_arm_fpu (int);
5021 static void s_arm_arch_extension (int);
5026 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
5033 if (exp
.X_op
== O_symbol
)
5034 exp
.X_op
= O_secrel
;
5036 emit_expr (&exp
, 4);
5038 while (*input_line_pointer
++ == ',');
5040 input_line_pointer
--;
5041 demand_empty_rest_of_line ();
5046 arm_is_largest_exponent_ok (int precision
)
5048 /* precision == 1 ensures that this will only return
5049 true for 16 bit floats. */
5050 return (precision
== 1) && (fp16_format
== ARM_FP16_FORMAT_ALTERNATIVE
);
5054 set_fp16_format (int dummy ATTRIBUTE_UNUSED
)
5058 enum fp_16bit_format new_format
;
5060 new_format
= ARM_FP16_FORMAT_DEFAULT
;
5062 name
= input_line_pointer
;
5063 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
5064 input_line_pointer
++;
5066 saved_char
= *input_line_pointer
;
5067 *input_line_pointer
= 0;
5069 if (strcasecmp (name
, "ieee") == 0)
5070 new_format
= ARM_FP16_FORMAT_IEEE
;
5071 else if (strcasecmp (name
, "alternative") == 0)
5072 new_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
5075 as_bad (_("unrecognised float16 format \"%s\""), name
);
5079 /* Only set fp16_format if it is still the default (aka not already
5081 if (fp16_format
== ARM_FP16_FORMAT_DEFAULT
)
5082 fp16_format
= new_format
;
5085 if (new_format
!= fp16_format
)
5086 as_warn (_("float16 format cannot be set more than once, ignoring."));
5090 *input_line_pointer
= saved_char
;
5091 ignore_rest_of_line ();
5094 /* This table describes all the machine specific pseudo-ops the assembler
5095 has to support. The fields are:
5096 pseudo-op name without dot
5097 function to call to execute this pseudo-op
5098 Integer arg to pass to the function. */
5100 const pseudo_typeS md_pseudo_table
[] =
5102 /* Never called because '.req' does not start a line. */
5103 { "req", s_req
, 0 },
5104 /* Following two are likewise never called. */
5107 { "unreq", s_unreq
, 0 },
5108 { "bss", s_bss
, 0 },
5109 { "align", s_align_ptwo
, 2 },
5110 { "arm", s_arm
, 0 },
5111 { "thumb", s_thumb
, 0 },
5112 { "code", s_code
, 0 },
5113 { "force_thumb", s_force_thumb
, 0 },
5114 { "thumb_func", s_thumb_func
, 0 },
5115 { "thumb_set", s_thumb_set
, 0 },
5116 { "even", s_even
, 0 },
5117 { "ltorg", s_ltorg
, 0 },
5118 { "pool", s_ltorg
, 0 },
5119 { "syntax", s_syntax
, 0 },
5120 { "cpu", s_arm_cpu
, 0 },
5121 { "arch", s_arm_arch
, 0 },
5122 { "object_arch", s_arm_object_arch
, 0 },
5123 { "fpu", s_arm_fpu
, 0 },
5124 { "arch_extension", s_arm_arch_extension
, 0 },
5126 { "word", s_arm_elf_cons
, 4 },
5127 { "long", s_arm_elf_cons
, 4 },
5128 { "inst.n", s_arm_elf_inst
, 2 },
5129 { "inst.w", s_arm_elf_inst
, 4 },
5130 { "inst", s_arm_elf_inst
, 0 },
5131 { "rel31", s_arm_rel31
, 0 },
5132 { "fnstart", s_arm_unwind_fnstart
, 0 },
5133 { "fnend", s_arm_unwind_fnend
, 0 },
5134 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
5135 { "personality", s_arm_unwind_personality
, 0 },
5136 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
5137 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
5138 { "save", s_arm_unwind_save
, 0 },
5139 { "vsave", s_arm_unwind_save
, 1 },
5140 { "movsp", s_arm_unwind_movsp
, 0 },
5141 { "pad", s_arm_unwind_pad
, 0 },
5142 { "setfp", s_arm_unwind_setfp
, 0 },
5143 { "unwind_raw", s_arm_unwind_raw
, 0 },
5144 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
5145 { "tlsdescseq", s_arm_tls_descseq
, 0 },
5149 /* These are used for dwarf. */
5153 /* These are used for dwarf2. */
5154 { "file", dwarf2_directive_file
, 0 },
5155 { "loc", dwarf2_directive_loc
, 0 },
5156 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
5158 { "extend", float_cons
, 'x' },
5159 { "ldouble", float_cons
, 'x' },
5160 { "packed", float_cons
, 'p' },
5161 { "bfloat16", float_cons
, 'b' },
5163 {"secrel32", pe_directive_secrel
, 0},
5166 /* These are for compatibility with CodeComposer Studio. */
5167 {"ref", s_ccs_ref
, 0},
5168 {"def", s_ccs_def
, 0},
5169 {"asmfunc", s_ccs_asmfunc
, 0},
5170 {"endasmfunc", s_ccs_endasmfunc
, 0},
5172 {"float16", float_cons
, 'h' },
5173 {"float16_format", set_fp16_format
, 0 },
5178 /* Parser functions used exclusively in instruction operands. */
5180 /* Generic immediate-value read function for use in insn parsing.
5181 STR points to the beginning of the immediate (the leading #);
5182 VAL receives the value; if the value is outside [MIN, MAX]
5183 issue an error. PREFIX_OPT is true if the immediate prefix is
5187 parse_immediate (char **str
, int *val
, int min
, int max
,
5188 bfd_boolean prefix_opt
)
5192 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5193 if (exp
.X_op
!= O_constant
)
5195 inst
.error
= _("constant expression required");
5199 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5201 inst
.error
= _("immediate value out of range");
5205 *val
= exp
.X_add_number
;
5209 /* Less-generic immediate-value read function with the possibility of loading a
5210 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5211 instructions. Puts the result directly in inst.operands[i]. */
5214 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5215 bfd_boolean allow_symbol_p
)
5218 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5221 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5223 if (exp_p
->X_op
== O_constant
)
5225 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5226 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5227 O_constant. We have to be careful not to break compilation for
5228 32-bit X_add_number, though. */
5229 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5231 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5232 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5234 inst
.operands
[i
].regisimm
= 1;
5237 else if (exp_p
->X_op
== O_big
5238 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5240 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5242 /* Bignums have their least significant bits in
5243 generic_bignum[0]. Make sure we put 32 bits in imm and
5244 32 bits in reg, in a (hopefully) portable way. */
5245 gas_assert (parts
!= 0);
5247 /* Make sure that the number is not too big.
5248 PR 11972: Bignums can now be sign-extended to the
5249 size of a .octa so check that the out of range bits
5250 are all zero or all one. */
5251 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5253 LITTLENUM_TYPE m
= -1;
5255 if (generic_bignum
[parts
* 2] != 0
5256 && generic_bignum
[parts
* 2] != m
)
5259 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5260 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5264 inst
.operands
[i
].imm
= 0;
5265 for (j
= 0; j
< parts
; j
++, idx
++)
5266 inst
.operands
[i
].imm
|= ((unsigned) generic_bignum
[idx
]
5267 << (LITTLENUM_NUMBER_OF_BITS
* j
));
5268 inst
.operands
[i
].reg
= 0;
5269 for (j
= 0; j
< parts
; j
++, idx
++)
5270 inst
.operands
[i
].reg
|= ((unsigned) generic_bignum
[idx
]
5271 << (LITTLENUM_NUMBER_OF_BITS
* j
));
5272 inst
.operands
[i
].regisimm
= 1;
5274 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5282 /* Returns the pseudo-register number of an FPA immediate constant,
5283 or FAIL if there isn't a valid constant here. */
5286 parse_fpa_immediate (char ** str
)
5288 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5294 /* First try and match exact strings, this is to guarantee
5295 that some formats will work even for cross assembly. */
5297 for (i
= 0; fp_const
[i
]; i
++)
5299 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5303 *str
+= strlen (fp_const
[i
]);
5304 if (is_end_of_line
[(unsigned char) **str
])
5310 /* Just because we didn't get a match doesn't mean that the constant
5311 isn't valid, just that it is in a format that we don't
5312 automatically recognize. Try parsing it with the standard
5313 expression routines. */
5315 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5317 /* Look for a raw floating point number. */
5318 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5319 && is_end_of_line
[(unsigned char) *save_in
])
5321 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5323 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5325 if (words
[j
] != fp_values
[i
][j
])
5329 if (j
== MAX_LITTLENUMS
)
5337 /* Try and parse a more complex expression, this will probably fail
5338 unless the code uses a floating point prefix (eg "0f"). */
5339 save_in
= input_line_pointer
;
5340 input_line_pointer
= *str
;
5341 if (expression (&exp
) == absolute_section
5342 && exp
.X_op
== O_big
5343 && exp
.X_add_number
< 0)
5345 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5347 #define X_PRECISION 5
5348 #define E_PRECISION 15L
5349 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5351 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5353 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5355 if (words
[j
] != fp_values
[i
][j
])
5359 if (j
== MAX_LITTLENUMS
)
5361 *str
= input_line_pointer
;
5362 input_line_pointer
= save_in
;
5369 *str
= input_line_pointer
;
5370 input_line_pointer
= save_in
;
5371 inst
.error
= _("invalid FPA immediate expression");
5375 /* Returns 1 if a number has "quarter-precision" float format
5376 0baBbbbbbc defgh000 00000000 00000000. */
5379 is_quarter_float (unsigned imm
)
5381 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5382 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5386 /* Detect the presence of a floating point or integer zero constant,
5390 parse_ifimm_zero (char **in
)
5394 if (!is_immediate_prefix (**in
))
5396 /* In unified syntax, all prefixes are optional. */
5397 if (!unified_syntax
)
5403 /* Accept #0x0 as a synonym for #0. */
5404 if (strncmp (*in
, "0x", 2) == 0)
5407 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5412 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5413 &generic_floating_point_number
);
5416 && generic_floating_point_number
.sign
== '+'
5417 && (generic_floating_point_number
.low
5418 > generic_floating_point_number
.leader
))
5424 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5425 0baBbbbbbc defgh000 00000000 00000000.
5426 The zero and minus-zero cases need special handling, since they can't be
5427 encoded in the "quarter-precision" float format, but can nonetheless be
5428 loaded as integer constants. */
5431 parse_qfloat_immediate (char **ccp
, int *immed
)
5435 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5436 int found_fpchar
= 0;
5438 skip_past_char (&str
, '#');
5440 /* We must not accidentally parse an integer as a floating-point number. Make
5441 sure that the value we parse is not an integer by checking for special
5442 characters '.' or 'e'.
5443 FIXME: This is a horrible hack, but doing better is tricky because type
5444 information isn't in a very usable state at parse time. */
5446 skip_whitespace (fpnum
);
5448 if (strncmp (fpnum
, "0x", 2) == 0)
5452 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5453 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5463 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5465 unsigned fpword
= 0;
5468 /* Our FP word must be 32 bits (single-precision FP). */
5469 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5471 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5475 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5488 /* Shift operands. */
5491 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5494 struct asm_shift_name
5497 enum shift_kind kind
;
5500 /* Third argument to parse_shift. */
5501 enum parse_shift_mode
5503 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5504 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5505 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5506 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5507 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5508 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5511 /* Parse a <shift> specifier on an ARM data processing instruction.
5512 This has three forms:
5514 (LSL|LSR|ASL|ASR|ROR) Rs
5515 (LSL|LSR|ASL|ASR|ROR) #imm
5518 Note that ASL is assimilated to LSL in the instruction encoding, and
5519 RRX to ROR #0 (which cannot be written as such). */
5522 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5524 const struct asm_shift_name
*shift_name
;
5525 enum shift_kind shift
;
5530 for (p
= *str
; ISALPHA (*p
); p
++)
5535 inst
.error
= _("shift expression expected");
5540 = (const struct asm_shift_name
*) str_hash_find_n (arm_shift_hsh
, *str
,
5543 if (shift_name
== NULL
)
5545 inst
.error
= _("shift expression expected");
5549 shift
= shift_name
->kind
;
5553 case NO_SHIFT_RESTRICT
:
5554 case SHIFT_IMMEDIATE
:
5555 if (shift
== SHIFT_UXTW
)
5557 inst
.error
= _("'UXTW' not allowed here");
5562 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5563 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5565 inst
.error
= _("'LSL' or 'ASR' required");
5570 case SHIFT_LSL_IMMEDIATE
:
5571 if (shift
!= SHIFT_LSL
)
5573 inst
.error
= _("'LSL' required");
5578 case SHIFT_ASR_IMMEDIATE
:
5579 if (shift
!= SHIFT_ASR
)
5581 inst
.error
= _("'ASR' required");
5585 case SHIFT_UXTW_IMMEDIATE
:
5586 if (shift
!= SHIFT_UXTW
)
5588 inst
.error
= _("'UXTW' required");
5596 if (shift
!= SHIFT_RRX
)
5598 /* Whitespace can appear here if the next thing is a bare digit. */
5599 skip_whitespace (p
);
5601 if (mode
== NO_SHIFT_RESTRICT
5602 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5604 inst
.operands
[i
].imm
= reg
;
5605 inst
.operands
[i
].immisreg
= 1;
5607 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5610 inst
.operands
[i
].shift_kind
= shift
;
5611 inst
.operands
[i
].shifted
= 1;
5616 /* Parse a <shifter_operand> for an ARM data processing instruction:
5619 #<immediate>, <rotate>
5623 where <shift> is defined by parse_shift above, and <rotate> is a
5624 multiple of 2 between 0 and 30. Validation of immediate operands
5625 is deferred to md_apply_fix. */
5628 parse_shifter_operand (char **str
, int i
)
5633 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5635 inst
.operands
[i
].reg
= value
;
5636 inst
.operands
[i
].isreg
= 1;
5638 /* parse_shift will override this if appropriate */
5639 inst
.relocs
[0].exp
.X_op
= O_constant
;
5640 inst
.relocs
[0].exp
.X_add_number
= 0;
5642 if (skip_past_comma (str
) == FAIL
)
5645 /* Shift operation on register. */
5646 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5649 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5652 if (skip_past_comma (str
) == SUCCESS
)
5654 /* #x, y -- ie explicit rotation by Y. */
5655 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5658 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5660 inst
.error
= _("constant expression expected");
5664 value
= exp
.X_add_number
;
5665 if (value
< 0 || value
> 30 || value
% 2 != 0)
5667 inst
.error
= _("invalid rotation");
5670 if (inst
.relocs
[0].exp
.X_add_number
< 0
5671 || inst
.relocs
[0].exp
.X_add_number
> 255)
5673 inst
.error
= _("invalid constant");
5677 /* Encode as specified. */
5678 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5682 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5683 inst
.relocs
[0].pc_rel
= 0;
5687 /* Group relocation information. Each entry in the table contains the
5688 textual name of the relocation as may appear in assembler source
5689 and must end with a colon.
5690 Along with this textual name are the relocation codes to be used if
5691 the corresponding instruction is an ALU instruction (ADD or SUB only),
5692 an LDR, an LDRS, or an LDC. */
5694 struct group_reloc_table_entry
5705 /* Varieties of non-ALU group relocation. */
5713 static struct group_reloc_table_entry group_reloc_table
[] =
5714 { /* Program counter relative: */
5716 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5721 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5722 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5723 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5724 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5726 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5731 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5732 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5733 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5734 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5736 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5737 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5738 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5739 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5740 /* Section base relative */
5742 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5747 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5748 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5749 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5750 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5752 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5757 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5758 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5759 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5760 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5762 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5763 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5764 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5765 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5766 /* Absolute thumb alu relocations. */
5768 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5773 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5778 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5783 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5788 /* Given the address of a pointer pointing to the textual name of a group
5789 relocation as may appear in assembler source, attempt to find its details
5790 in group_reloc_table. The pointer will be updated to the character after
5791 the trailing colon. On failure, FAIL will be returned; SUCCESS
5792 otherwise. On success, *entry will be updated to point at the relevant
5793 group_reloc_table entry. */
5796 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5799 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5801 int length
= strlen (group_reloc_table
[i
].name
);
5803 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5804 && (*str
)[length
] == ':')
5806 *out
= &group_reloc_table
[i
];
5807 *str
+= (length
+ 1);
5815 /* Parse a <shifter_operand> for an ARM data processing instruction
5816 (as for parse_shifter_operand) where group relocations are allowed:
5819 #<immediate>, <rotate>
5820 #:<group_reloc>:<expression>
5824 where <group_reloc> is one of the strings defined in group_reloc_table.
5825 The hashes are optional.
5827 Everything else is as for parse_shifter_operand. */
5829 static parse_operand_result
5830 parse_shifter_operand_group_reloc (char **str
, int i
)
5832 /* Determine if we have the sequence of characters #: or just :
5833 coming next. If we do, then we check for a group relocation.
5834 If we don't, punt the whole lot to parse_shifter_operand. */
5836 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5837 || (*str
)[0] == ':')
5839 struct group_reloc_table_entry
*entry
;
5841 if ((*str
)[0] == '#')
5846 /* Try to parse a group relocation. Anything else is an error. */
5847 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5849 inst
.error
= _("unknown group relocation");
5850 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5853 /* We now have the group relocation table entry corresponding to
5854 the name in the assembler source. Next, we parse the expression. */
5855 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5856 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5858 /* Record the relocation type (always the ALU variant here). */
5859 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5860 gas_assert (inst
.relocs
[0].type
!= 0);
5862 return PARSE_OPERAND_SUCCESS
;
5865 return parse_shifter_operand (str
, i
) == SUCCESS
5866 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5868 /* Never reached. */
5871 /* Parse a Neon alignment expression. Information is written to
5872 inst.operands[i]. We assume the initial ':' has been skipped.
5874 align .imm = align << 8, .immisalign=1, .preind=0 */
5875 static parse_operand_result
5876 parse_neon_alignment (char **str
, int i
)
5881 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5883 if (exp
.X_op
!= O_constant
)
5885 inst
.error
= _("alignment must be constant");
5886 return PARSE_OPERAND_FAIL
;
5889 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5890 inst
.operands
[i
].immisalign
= 1;
5891 /* Alignments are not pre-indexes. */
5892 inst
.operands
[i
].preind
= 0;
5895 return PARSE_OPERAND_SUCCESS
;
5898 /* Parse all forms of an ARM address expression. Information is written
5899 to inst.operands[i] and/or inst.relocs[0].
5901 Preindexed addressing (.preind=1):
5903 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5904 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5905 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5906 .shift_kind=shift .relocs[0].exp=shift_imm
5908 These three may have a trailing ! which causes .writeback to be set also.
5910 Postindexed addressing (.postind=1, .writeback=1):
5912 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5913 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5914 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5915 .shift_kind=shift .relocs[0].exp=shift_imm
5917 Unindexed addressing (.preind=0, .postind=0):
5919 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5923 [Rn]{!} shorthand for [Rn,#0]{!}
5924 =immediate .isreg=0 .relocs[0].exp=immediate
5925 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5927 It is the caller's responsibility to check for addressing modes not
5928 supported by the instruction, and to set inst.relocs[0].type. */
5930 static parse_operand_result
5931 parse_address_main (char **str
, int i
, int group_relocations
,
5932 group_reloc_type group_type
)
5937 if (skip_past_char (&p
, '[') == FAIL
)
5939 if (skip_past_char (&p
, '=') == FAIL
)
5941 /* Bare address - translate to PC-relative offset. */
5942 inst
.relocs
[0].pc_rel
= 1;
5943 inst
.operands
[i
].reg
= REG_PC
;
5944 inst
.operands
[i
].isreg
= 1;
5945 inst
.operands
[i
].preind
= 1;
5947 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5948 return PARSE_OPERAND_FAIL
;
5950 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5951 /*allow_symbol_p=*/TRUE
))
5952 return PARSE_OPERAND_FAIL
;
5955 return PARSE_OPERAND_SUCCESS
;
5958 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5959 skip_whitespace (p
);
5961 if (group_type
== GROUP_MVE
)
5963 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5964 struct neon_type_el et
;
5965 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5967 inst
.operands
[i
].isquad
= 1;
5969 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5971 inst
.error
= BAD_ADDR_MODE
;
5972 return PARSE_OPERAND_FAIL
;
5975 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5977 if (group_type
== GROUP_MVE
)
5978 inst
.error
= BAD_ADDR_MODE
;
5980 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5981 return PARSE_OPERAND_FAIL
;
5983 inst
.operands
[i
].reg
= reg
;
5984 inst
.operands
[i
].isreg
= 1;
5986 if (skip_past_comma (&p
) == SUCCESS
)
5988 inst
.operands
[i
].preind
= 1;
5991 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5993 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5994 struct neon_type_el et
;
5995 if (group_type
== GROUP_MVE
5996 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5998 inst
.operands
[i
].immisreg
= 2;
5999 inst
.operands
[i
].imm
= reg
;
6001 if (skip_past_comma (&p
) == SUCCESS
)
6003 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
6005 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
6006 inst
.relocs
[0].exp
.X_add_number
= 0;
6009 return PARSE_OPERAND_FAIL
;
6012 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6014 inst
.operands
[i
].imm
= reg
;
6015 inst
.operands
[i
].immisreg
= 1;
6017 if (skip_past_comma (&p
) == SUCCESS
)
6018 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6019 return PARSE_OPERAND_FAIL
;
6021 else if (skip_past_char (&p
, ':') == SUCCESS
)
6023 /* FIXME: '@' should be used here, but it's filtered out by generic
6024 code before we get to see it here. This may be subject to
6026 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6028 if (result
!= PARSE_OPERAND_SUCCESS
)
6033 if (inst
.operands
[i
].negative
)
6035 inst
.operands
[i
].negative
= 0;
6039 if (group_relocations
6040 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
6042 struct group_reloc_table_entry
*entry
;
6044 /* Skip over the #: or : sequence. */
6050 /* Try to parse a group relocation. Anything else is an
6052 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
6054 inst
.error
= _("unknown group relocation");
6055 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6058 /* We now have the group relocation table entry corresponding to
6059 the name in the assembler source. Next, we parse the
6061 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6062 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6064 /* Record the relocation type. */
6069 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
6074 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
6079 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
6086 if (inst
.relocs
[0].type
== 0)
6088 inst
.error
= _("this group relocation is not allowed on this instruction");
6089 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6096 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6097 return PARSE_OPERAND_FAIL
;
6098 /* If the offset is 0, find out if it's a +0 or -0. */
6099 if (inst
.relocs
[0].exp
.X_op
== O_constant
6100 && inst
.relocs
[0].exp
.X_add_number
== 0)
6102 skip_whitespace (q
);
6106 skip_whitespace (q
);
6109 inst
.operands
[i
].negative
= 1;
6114 else if (skip_past_char (&p
, ':') == SUCCESS
)
6116 /* FIXME: '@' should be used here, but it's filtered out by generic code
6117 before we get to see it here. This may be subject to change. */
6118 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6120 if (result
!= PARSE_OPERAND_SUCCESS
)
6124 if (skip_past_char (&p
, ']') == FAIL
)
6126 inst
.error
= _("']' expected");
6127 return PARSE_OPERAND_FAIL
;
6130 if (skip_past_char (&p
, '!') == SUCCESS
)
6131 inst
.operands
[i
].writeback
= 1;
6133 else if (skip_past_comma (&p
) == SUCCESS
)
6135 if (skip_past_char (&p
, '{') == SUCCESS
)
6137 /* [Rn], {expr} - unindexed, with option */
6138 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
6139 0, 255, TRUE
) == FAIL
)
6140 return PARSE_OPERAND_FAIL
;
6142 if (skip_past_char (&p
, '}') == FAIL
)
6144 inst
.error
= _("'}' expected at end of 'option' field");
6145 return PARSE_OPERAND_FAIL
;
6147 if (inst
.operands
[i
].preind
)
6149 inst
.error
= _("cannot combine index with option");
6150 return PARSE_OPERAND_FAIL
;
6153 return PARSE_OPERAND_SUCCESS
;
6157 inst
.operands
[i
].postind
= 1;
6158 inst
.operands
[i
].writeback
= 1;
6160 if (inst
.operands
[i
].preind
)
6162 inst
.error
= _("cannot combine pre- and post-indexing");
6163 return PARSE_OPERAND_FAIL
;
6167 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
6169 enum arm_reg_type rtype
= REG_TYPE_MQ
;
6170 struct neon_type_el et
;
6171 if (group_type
== GROUP_MVE
6172 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6174 inst
.operands
[i
].immisreg
= 2;
6175 inst
.operands
[i
].imm
= reg
;
6177 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6179 /* We might be using the immediate for alignment already. If we
6180 are, OR the register number into the low-order bits. */
6181 if (inst
.operands
[i
].immisalign
)
6182 inst
.operands
[i
].imm
|= reg
;
6184 inst
.operands
[i
].imm
= reg
;
6185 inst
.operands
[i
].immisreg
= 1;
6187 if (skip_past_comma (&p
) == SUCCESS
)
6188 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6189 return PARSE_OPERAND_FAIL
;
6195 if (inst
.operands
[i
].negative
)
6197 inst
.operands
[i
].negative
= 0;
6200 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6201 return PARSE_OPERAND_FAIL
;
6202 /* If the offset is 0, find out if it's a +0 or -0. */
6203 if (inst
.relocs
[0].exp
.X_op
== O_constant
6204 && inst
.relocs
[0].exp
.X_add_number
== 0)
6206 skip_whitespace (q
);
6210 skip_whitespace (q
);
6213 inst
.operands
[i
].negative
= 1;
6219 /* If at this point neither .preind nor .postind is set, we have a
6220 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6221 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6223 inst
.operands
[i
].preind
= 1;
6224 inst
.relocs
[0].exp
.X_op
= O_constant
;
6225 inst
.relocs
[0].exp
.X_add_number
= 0;
6228 return PARSE_OPERAND_SUCCESS
;
6232 parse_address (char **str
, int i
)
6234 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6238 static parse_operand_result
6239 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6241 return parse_address_main (str
, i
, 1, type
);
6244 /* Parse an operand for a MOVW or MOVT instruction. */
6246 parse_half (char **str
)
6251 skip_past_char (&p
, '#');
6252 if (strncasecmp (p
, ":lower16:", 9) == 0)
6253 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6254 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6255 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6257 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6260 skip_whitespace (p
);
6263 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6266 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6268 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6270 inst
.error
= _("constant expression expected");
6273 if (inst
.relocs
[0].exp
.X_add_number
< 0
6274 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6276 inst
.error
= _("immediate value out of range");
6284 /* Miscellaneous. */
6286 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6287 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6289 parse_psr (char **str
, bfd_boolean lhs
)
6292 unsigned long psr_field
;
6293 const struct asm_psr
*psr
;
6295 bfd_boolean is_apsr
= FALSE
;
6296 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6298 /* PR gas/12698: If the user has specified -march=all then m_profile will
6299 be TRUE, but we want to ignore it in this case as we are building for any
6300 CPU type, including non-m variants. */
6301 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6304 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6305 feature for ease of use and backwards compatibility. */
6307 if (strncasecmp (p
, "SPSR", 4) == 0)
6310 goto unsupported_psr
;
6312 psr_field
= SPSR_BIT
;
6314 else if (strncasecmp (p
, "CPSR", 4) == 0)
6317 goto unsupported_psr
;
6321 else if (strncasecmp (p
, "APSR", 4) == 0)
6323 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6324 and ARMv7-R architecture CPUs. */
6333 while (ISALNUM (*p
) || *p
== '_');
6335 if (strncasecmp (start
, "iapsr", 5) == 0
6336 || strncasecmp (start
, "eapsr", 5) == 0
6337 || strncasecmp (start
, "xpsr", 4) == 0
6338 || strncasecmp (start
, "psr", 3) == 0)
6339 p
= start
+ strcspn (start
, "rR") + 1;
6341 psr
= (const struct asm_psr
*) str_hash_find_n (arm_v7m_psr_hsh
, start
,
6347 /* If APSR is being written, a bitfield may be specified. Note that
6348 APSR itself is handled above. */
6349 if (psr
->field
<= 3)
6351 psr_field
= psr
->field
;
6357 /* M-profile MSR instructions have the mask field set to "10", except
6358 *PSR variants which modify APSR, which may use a different mask (and
6359 have been handled already). Do that by setting the PSR_f field
6361 return psr
->field
| (lhs
? PSR_f
: 0);
6364 goto unsupported_psr
;
6370 /* A suffix follows. */
6376 while (ISALNUM (*p
) || *p
== '_');
6380 /* APSR uses a notation for bits, rather than fields. */
6381 unsigned int nzcvq_bits
= 0;
6382 unsigned int g_bit
= 0;
6385 for (bit
= start
; bit
!= p
; bit
++)
6387 switch (TOLOWER (*bit
))
6390 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6394 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6398 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6402 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6406 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6410 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6414 inst
.error
= _("unexpected bit specified after APSR");
6419 if (nzcvq_bits
== 0x1f)
6424 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6426 inst
.error
= _("selected processor does not "
6427 "support DSP extension");
6434 if ((nzcvq_bits
& 0x20) != 0
6435 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6436 || (g_bit
& 0x2) != 0)
6438 inst
.error
= _("bad bitmask specified after APSR");
6444 psr
= (const struct asm_psr
*) str_hash_find_n (arm_psr_hsh
, start
,
6449 psr_field
|= psr
->field
;
6455 goto error
; /* Garbage after "[CS]PSR". */
6457 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6458 is deprecated, but allow it anyway. */
6462 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6465 else if (!m_profile
)
6466 /* These bits are never right for M-profile devices: don't set them
6467 (only code paths which read/write APSR reach here). */
6468 psr_field
|= (PSR_c
| PSR_f
);
6474 inst
.error
= _("selected processor does not support requested special "
6475 "purpose register");
6479 inst
.error
= _("flag for {c}psr instruction expected");
6484 parse_sys_vldr_vstr (char **str
)
6493 {"FPSCR", 0x1, 0x0},
6494 {"FPSCR_nzcvqc", 0x2, 0x0},
6497 {"FPCXTNS", 0x6, 0x1},
6498 {"FPCXTS", 0x7, 0x1}
6500 char *op_end
= strchr (*str
, ',');
6501 size_t op_strlen
= op_end
- *str
;
6503 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6505 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6507 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6516 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6517 value suitable for splatting into the AIF field of the instruction. */
6520 parse_cps_flags (char **str
)
6529 case '\0': case ',':
6532 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6533 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6534 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6537 inst
.error
= _("unrecognized CPS flag");
6542 if (saw_a_flag
== 0)
6544 inst
.error
= _("missing CPS flags");
6552 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6553 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6556 parse_endian_specifier (char **str
)
6561 if (strncasecmp (s
, "BE", 2))
6563 else if (strncasecmp (s
, "LE", 2))
6567 inst
.error
= _("valid endian specifiers are be or le");
6571 if (ISALNUM (s
[2]) || s
[2] == '_')
6573 inst
.error
= _("valid endian specifiers are be or le");
6578 return little_endian
;
6581 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6582 value suitable for poking into the rotate field of an sxt or sxta
6583 instruction, or FAIL on error. */
6586 parse_ror (char **str
)
6591 if (strncasecmp (s
, "ROR", 3) == 0)
6595 inst
.error
= _("missing rotation field after comma");
6599 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6604 case 0: *str
= s
; return 0x0;
6605 case 8: *str
= s
; return 0x1;
6606 case 16: *str
= s
; return 0x2;
6607 case 24: *str
= s
; return 0x3;
6610 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6615 /* Parse a conditional code (from conds[] below). The value returned is in the
6616 range 0 .. 14, or FAIL. */
6618 parse_cond (char **str
)
6621 const struct asm_cond
*c
;
6623 /* Condition codes are always 2 characters, so matching up to
6624 3 characters is sufficient. */
6629 while (ISALPHA (*q
) && n
< 3)
6631 cond
[n
] = TOLOWER (*q
);
6636 c
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, cond
, n
);
6639 inst
.error
= _("condition required");
6647 /* Parse an option for a barrier instruction. Returns the encoding for the
6650 parse_barrier (char **str
)
6653 const struct asm_barrier_opt
*o
;
6656 while (ISALPHA (*q
))
6659 o
= (const struct asm_barrier_opt
*) str_hash_find_n (arm_barrier_opt_hsh
, p
,
6664 if (!mark_feature_used (&o
->arch
))
6671 /* Parse the operands of a table branch instruction. Similar to a memory
6674 parse_tb (char **str
)
6679 if (skip_past_char (&p
, '[') == FAIL
)
6681 inst
.error
= _("'[' expected");
6685 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6687 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6690 inst
.operands
[0].reg
= reg
;
6692 if (skip_past_comma (&p
) == FAIL
)
6694 inst
.error
= _("',' expected");
6698 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6700 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6703 inst
.operands
[0].imm
= reg
;
6705 if (skip_past_comma (&p
) == SUCCESS
)
6707 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6709 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6711 inst
.error
= _("invalid shift");
6714 inst
.operands
[0].shifted
= 1;
6717 if (skip_past_char (&p
, ']') == FAIL
)
6719 inst
.error
= _("']' expected");
6726 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6727 information on the types the operands can take and how they are encoded.
6728 Up to four operands may be read; this function handles setting the
6729 ".present" field for each read operand itself.
6730 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6731 else returns FAIL. */
6734 parse_neon_mov (char **str
, int *which_operand
)
6736 int i
= *which_operand
, val
;
6737 enum arm_reg_type rtype
;
6739 struct neon_type_el optype
;
6741 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6743 /* Cases 17 or 19. */
6744 inst
.operands
[i
].reg
= val
;
6745 inst
.operands
[i
].isvec
= 1;
6746 inst
.operands
[i
].isscalar
= 2;
6747 inst
.operands
[i
].vectype
= optype
;
6748 inst
.operands
[i
++].present
= 1;
6750 if (skip_past_comma (&ptr
) == FAIL
)
6753 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6755 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6756 inst
.operands
[i
].reg
= val
;
6757 inst
.operands
[i
].isreg
= 1;
6758 inst
.operands
[i
].present
= 1;
6760 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6762 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6763 inst
.operands
[i
].reg
= val
;
6764 inst
.operands
[i
].isvec
= 1;
6765 inst
.operands
[i
].isscalar
= 2;
6766 inst
.operands
[i
].vectype
= optype
;
6767 inst
.operands
[i
++].present
= 1;
6769 if (skip_past_comma (&ptr
) == FAIL
)
6772 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6775 inst
.operands
[i
].reg
= val
;
6776 inst
.operands
[i
].isreg
= 1;
6777 inst
.operands
[i
++].present
= 1;
6779 if (skip_past_comma (&ptr
) == FAIL
)
6782 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6785 inst
.operands
[i
].reg
= val
;
6786 inst
.operands
[i
].isreg
= 1;
6787 inst
.operands
[i
].present
= 1;
6791 first_error (_("expected ARM or MVE vector register"));
6795 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6797 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6798 inst
.operands
[i
].reg
= val
;
6799 inst
.operands
[i
].isscalar
= 1;
6800 inst
.operands
[i
].vectype
= optype
;
6801 inst
.operands
[i
++].present
= 1;
6803 if (skip_past_comma (&ptr
) == FAIL
)
6806 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6809 inst
.operands
[i
].reg
= val
;
6810 inst
.operands
[i
].isreg
= 1;
6811 inst
.operands
[i
].present
= 1;
6813 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6815 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6818 /* Cases 0, 1, 2, 3, 5 (D only). */
6819 if (skip_past_comma (&ptr
) == FAIL
)
6822 inst
.operands
[i
].reg
= val
;
6823 inst
.operands
[i
].isreg
= 1;
6824 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6825 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6826 inst
.operands
[i
].isvec
= 1;
6827 inst
.operands
[i
].vectype
= optype
;
6828 inst
.operands
[i
++].present
= 1;
6830 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6832 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6833 Case 13: VMOV <Sd>, <Rm> */
6834 inst
.operands
[i
].reg
= val
;
6835 inst
.operands
[i
].isreg
= 1;
6836 inst
.operands
[i
].present
= 1;
6838 if (rtype
== REG_TYPE_NQ
)
6840 first_error (_("can't use Neon quad register here"));
6843 else if (rtype
!= REG_TYPE_VFS
)
6846 if (skip_past_comma (&ptr
) == FAIL
)
6848 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6850 inst
.operands
[i
].reg
= val
;
6851 inst
.operands
[i
].isreg
= 1;
6852 inst
.operands
[i
].present
= 1;
6855 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6857 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
,
6860 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6861 Case 1: VMOV<c><q> <Dd>, <Dm>
6862 Case 8: VMOV.F32 <Sd>, <Sm>
6863 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6865 inst
.operands
[i
].reg
= val
;
6866 inst
.operands
[i
].isreg
= 1;
6867 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6868 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6869 inst
.operands
[i
].isvec
= 1;
6870 inst
.operands
[i
].vectype
= optype
;
6871 inst
.operands
[i
].present
= 1;
6873 if (skip_past_comma (&ptr
) == SUCCESS
)
6878 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6881 inst
.operands
[i
].reg
= val
;
6882 inst
.operands
[i
].isreg
= 1;
6883 inst
.operands
[i
++].present
= 1;
6885 if (skip_past_comma (&ptr
) == FAIL
)
6888 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6891 inst
.operands
[i
].reg
= val
;
6892 inst
.operands
[i
].isreg
= 1;
6893 inst
.operands
[i
].present
= 1;
6896 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6897 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6898 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6899 Case 10: VMOV.F32 <Sd>, #<imm>
6900 Case 11: VMOV.F64 <Dd>, #<imm> */
6901 inst
.operands
[i
].immisfloat
= 1;
6902 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6904 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6905 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6909 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6913 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6915 /* Cases 6, 7, 16, 18. */
6916 inst
.operands
[i
].reg
= val
;
6917 inst
.operands
[i
].isreg
= 1;
6918 inst
.operands
[i
++].present
= 1;
6920 if (skip_past_comma (&ptr
) == FAIL
)
6923 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6925 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6926 inst
.operands
[i
].reg
= val
;
6927 inst
.operands
[i
].isscalar
= 2;
6928 inst
.operands
[i
].present
= 1;
6929 inst
.operands
[i
].vectype
= optype
;
6931 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6933 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6934 inst
.operands
[i
].reg
= val
;
6935 inst
.operands
[i
].isscalar
= 1;
6936 inst
.operands
[i
].present
= 1;
6937 inst
.operands
[i
].vectype
= optype
;
6939 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6941 inst
.operands
[i
].reg
= val
;
6942 inst
.operands
[i
].isreg
= 1;
6943 inst
.operands
[i
++].present
= 1;
6945 if (skip_past_comma (&ptr
) == FAIL
)
6948 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6951 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6953 inst
.operands
[i
].reg
= val
;
6954 inst
.operands
[i
].isreg
= 1;
6955 inst
.operands
[i
].isvec
= 1;
6956 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6957 inst
.operands
[i
].vectype
= optype
;
6958 inst
.operands
[i
].present
= 1;
6960 if (rtype
== REG_TYPE_VFS
)
6964 if (skip_past_comma (&ptr
) == FAIL
)
6966 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6969 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6972 inst
.operands
[i
].reg
= val
;
6973 inst
.operands
[i
].isreg
= 1;
6974 inst
.operands
[i
].isvec
= 1;
6975 inst
.operands
[i
].issingle
= 1;
6976 inst
.operands
[i
].vectype
= optype
;
6977 inst
.operands
[i
].present
= 1;
6982 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6985 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6986 inst
.operands
[i
].reg
= val
;
6987 inst
.operands
[i
].isvec
= 1;
6988 inst
.operands
[i
].isscalar
= 2;
6989 inst
.operands
[i
].vectype
= optype
;
6990 inst
.operands
[i
++].present
= 1;
6992 if (skip_past_comma (&ptr
) == FAIL
)
6995 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6998 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
7001 inst
.operands
[i
].reg
= val
;
7002 inst
.operands
[i
].isvec
= 1;
7003 inst
.operands
[i
].isscalar
= 2;
7004 inst
.operands
[i
].vectype
= optype
;
7005 inst
.operands
[i
].present
= 1;
7009 first_error (_("VFP single, double or MVE vector register"
7015 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
7019 inst
.operands
[i
].reg
= val
;
7020 inst
.operands
[i
].isreg
= 1;
7021 inst
.operands
[i
].isvec
= 1;
7022 inst
.operands
[i
].issingle
= 1;
7023 inst
.operands
[i
].vectype
= optype
;
7024 inst
.operands
[i
].present
= 1;
7029 first_error (_("parse error"));
7033 /* Successfully parsed the operands. Update args. */
7039 first_error (_("expected comma"));
7043 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
7047 /* Use this macro when the operand constraints are different
7048 for ARM and THUMB (e.g. ldrd). */
7049 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
7050 ((arm_operand) | ((thumb_operand) << 16))
7052 /* Matcher codes for parse_operands. */
7053 enum operand_parse_code
7055 OP_stop
, /* end of line */
7057 OP_RR
, /* ARM register */
7058 OP_RRnpc
, /* ARM register, not r15 */
7059 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
7060 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
7061 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
7062 optional trailing ! */
7063 OP_RRw
, /* ARM register, not r15, optional trailing ! */
7064 OP_RCP
, /* Coprocessor number */
7065 OP_RCN
, /* Coprocessor register */
7066 OP_RF
, /* FPA register */
7067 OP_RVS
, /* VFP single precision register */
7068 OP_RVD
, /* VFP double precision register (0..15) */
7069 OP_RND
, /* Neon double precision register (0..31) */
7070 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
7071 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
7073 OP_RNSDMQR
, /* Neon single or double precision, MVE vector or ARM register.
7075 OP_RNQ
, /* Neon quad precision register */
7076 OP_RNQMQ
, /* Neon quad or MVE vector register. */
7077 OP_RVSD
, /* VFP single or double precision register */
7078 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
7079 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
7080 OP_RNSD
, /* Neon single or double precision register */
7081 OP_RNDQ
, /* Neon double or quad precision register */
7082 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
7083 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
7084 OP_RNSDQ
, /* Neon single, double or quad precision register */
7085 OP_RNSC
, /* Neon scalar D[X] */
7086 OP_RVC
, /* VFP control register */
7087 OP_RMF
, /* Maverick F register */
7088 OP_RMD
, /* Maverick D register */
7089 OP_RMFX
, /* Maverick FX register */
7090 OP_RMDX
, /* Maverick DX register */
7091 OP_RMAX
, /* Maverick AX register */
7092 OP_RMDS
, /* Maverick DSPSC register */
7093 OP_RIWR
, /* iWMMXt wR register */
7094 OP_RIWC
, /* iWMMXt wC register */
7095 OP_RIWG
, /* iWMMXt wCG register */
7096 OP_RXA
, /* XScale accumulator register */
7098 OP_RNSDMQ
, /* Neon single, double or MVE vector register */
7099 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
7101 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
7103 OP_RMQ
, /* MVE vector register. */
7104 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
7105 OP_RMQRR
, /* MVE vector or ARM register. */
7107 /* New operands for Armv8.1-M Mainline. */
7108 OP_LR
, /* ARM LR register */
7109 OP_RRe
, /* ARM register, only even numbered. */
7110 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
7111 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
7112 OP_RR_ZR
, /* ARM register or ZR but no PC */
7114 OP_REGLST
, /* ARM register list */
7115 OP_CLRMLST
, /* CLRM register list */
7116 OP_VRSLST
, /* VFP single-precision register list */
7117 OP_VRDLST
, /* VFP double-precision register list */
7118 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
7119 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
7120 OP_NSTRLST
, /* Neon element/structure list */
7121 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
7122 OP_MSTRLST2
, /* MVE vector list with two elements. */
7123 OP_MSTRLST4
, /* MVE vector list with four elements. */
7125 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
7126 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
7127 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
7128 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
7130 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
7131 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
7132 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
7133 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
7135 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
7136 scalar, or ARM register. */
7137 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
7138 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
7139 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
7141 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
7142 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
7143 OP_VMOV
, /* Neon VMOV operands. */
7144 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
7145 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
7147 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
7148 OP_RNDQMQ_I63b_RR
, /* Neon D or Q reg, immediate for shift, MVE vector or
7150 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
7151 OP_VLDR
, /* VLDR operand. */
7153 OP_I0
, /* immediate zero */
7154 OP_I7
, /* immediate value 0 .. 7 */
7155 OP_I15
, /* 0 .. 15 */
7156 OP_I16
, /* 1 .. 16 */
7157 OP_I16z
, /* 0 .. 16 */
7158 OP_I31
, /* 0 .. 31 */
7159 OP_I31w
, /* 0 .. 31, optional trailing ! */
7160 OP_I32
, /* 1 .. 32 */
7161 OP_I32z
, /* 0 .. 32 */
7162 OP_I48_I64
, /* 48 or 64 */
7163 OP_I63
, /* 0 .. 63 */
7164 OP_I63s
, /* -64 .. 63 */
7165 OP_I64
, /* 1 .. 64 */
7166 OP_I64z
, /* 0 .. 64 */
7167 OP_I127
, /* 0 .. 127 */
7168 OP_I255
, /* 0 .. 255 */
7169 OP_I511
, /* 0 .. 511 */
7170 OP_I4095
, /* 0 .. 4095 */
7171 OP_I8191
, /* 0 .. 8191 */
7172 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
7173 OP_I7b
, /* 0 .. 7 */
7174 OP_I15b
, /* 0 .. 15 */
7175 OP_I31b
, /* 0 .. 31 */
7177 OP_SH
, /* shifter operand */
7178 OP_SHG
, /* shifter operand with possible group relocation */
7179 OP_ADDR
, /* Memory address expression (any mode) */
7180 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
7181 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
7182 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
7183 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
7184 OP_EXP
, /* arbitrary expression */
7185 OP_EXPi
, /* same, with optional immediate prefix */
7186 OP_EXPr
, /* same, with optional relocation suffix */
7187 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7188 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7189 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7190 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7192 OP_CPSF
, /* CPS flags */
7193 OP_ENDI
, /* Endianness specifier */
7194 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7195 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7196 OP_COND
, /* conditional code */
7197 OP_TB
, /* Table branch. */
7199 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7201 OP_RRnpc_I0
, /* ARM register or literal 0 */
7202 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7203 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7204 OP_RF_IF
, /* FPA register or immediate */
7205 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7206 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7208 /* Optional operands. */
7209 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7210 OP_oI31b
, /* 0 .. 31 */
7211 OP_oI32b
, /* 1 .. 32 */
7212 OP_oI32z
, /* 0 .. 32 */
7213 OP_oIffffb
, /* 0 .. 65535 */
7214 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7216 OP_oRR
, /* ARM register */
7217 OP_oLR
, /* ARM LR register */
7218 OP_oRRnpc
, /* ARM register, not the PC */
7219 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7220 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7221 OP_oRND
, /* Optional Neon double precision register */
7222 OP_oRNQ
, /* Optional Neon quad precision register */
7223 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7224 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7225 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7226 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7228 OP_oRNSDMQ
, /* Optional single, double register or MVE vector
7230 OP_oSHll
, /* LSL immediate */
7231 OP_oSHar
, /* ASR immediate */
7232 OP_oSHllar
, /* LSL or ASR immediate */
7233 OP_oROR
, /* ROR 0/8/16/24 */
7234 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7236 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7238 /* Some pre-defined mixed (ARM/THUMB) operands. */
7239 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7240 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7241 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7243 OP_FIRST_OPTIONAL
= OP_oI7b
7246 /* Generic instruction operand parser. This does no encoding and no
7247 semantic validation; it merely squirrels values away in the inst
7248 structure. Returns SUCCESS or FAIL depending on whether the
7249 specified grammar matched. */
7251 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7253 unsigned const int *upat
= pattern
;
7254 char *backtrack_pos
= 0;
7255 const char *backtrack_error
= 0;
7256 int i
, val
= 0, backtrack_index
= 0;
7257 enum arm_reg_type rtype
;
7258 parse_operand_result result
;
7259 unsigned int op_parse_code
;
7260 bfd_boolean partial_match
;
7262 #define po_char_or_fail(chr) \
7265 if (skip_past_char (&str, chr) == FAIL) \
7270 #define po_reg_or_fail(regtype) \
7273 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7274 & inst.operands[i].vectype); \
7277 first_error (_(reg_expected_msgs[regtype])); \
7280 inst.operands[i].reg = val; \
7281 inst.operands[i].isreg = 1; \
7282 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7283 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7284 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7285 || rtype == REG_TYPE_VFD \
7286 || rtype == REG_TYPE_NQ); \
7287 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7291 #define po_reg_or_goto(regtype, label) \
7294 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7295 & inst.operands[i].vectype); \
7299 inst.operands[i].reg = val; \
7300 inst.operands[i].isreg = 1; \
7301 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7302 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7303 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7304 || rtype == REG_TYPE_VFD \
7305 || rtype == REG_TYPE_NQ); \
7306 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7310 #define po_imm_or_fail(min, max, popt) \
7313 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7315 inst.operands[i].imm = val; \
7319 #define po_imm1_or_imm2_or_fail(imm1, imm2, popt) \
7323 my_get_expression (&exp, &str, popt); \
7324 if (exp.X_op != O_constant) \
7326 inst.error = _("constant expression required"); \
7329 if (exp.X_add_number != imm1 && exp.X_add_number != imm2) \
7331 inst.error = _("immediate value 48 or 64 expected"); \
7334 inst.operands[i].imm = exp.X_add_number; \
7338 #define po_scalar_or_goto(elsz, label, reg_type) \
7341 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7345 inst.operands[i].reg = val; \
7346 inst.operands[i].isscalar = 1; \
7350 #define po_misc_or_fail(expr) \
7358 #define po_misc_or_fail_no_backtrack(expr) \
7362 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7363 backtrack_pos = 0; \
7364 if (result != PARSE_OPERAND_SUCCESS) \
7369 #define po_barrier_or_imm(str) \
7372 val = parse_barrier (&str); \
7373 if (val == FAIL && ! ISALPHA (*str)) \
7376 /* ISB can only take SY as an option. */ \
7377 || ((inst.instruction & 0xf0) == 0x60 \
7380 inst.error = _("invalid barrier type"); \
7381 backtrack_pos = 0; \
7387 skip_whitespace (str
);
7389 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7391 op_parse_code
= upat
[i
];
7392 if (op_parse_code
>= 1<<16)
7393 op_parse_code
= thumb
? (op_parse_code
>> 16)
7394 : (op_parse_code
& ((1<<16)-1));
7396 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7398 /* Remember where we are in case we need to backtrack. */
7399 backtrack_pos
= str
;
7400 backtrack_error
= inst
.error
;
7401 backtrack_index
= i
;
7404 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7405 po_char_or_fail (',');
7407 switch (op_parse_code
)
7419 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7420 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7421 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7422 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7423 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7424 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7427 po_reg_or_goto (REG_TYPE_VFS
, try_rndmqr
);
7431 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7435 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7438 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7440 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7442 /* Also accept generic coprocessor regs for unknown registers. */
7444 po_reg_or_goto (REG_TYPE_CN
, vpr_po
);
7446 /* Also accept P0 or p0 for VPR.P0. Since P0 is already an
7447 existing register with a value of 0, this seems like the
7448 best way to parse P0. */
7450 if (strncasecmp (str
, "P0", 2) == 0)
7453 inst
.operands
[i
].isreg
= 1;
7454 inst
.operands
[i
].reg
= 13;
7459 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7460 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7461 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7462 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7463 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7464 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7465 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7466 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7467 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7468 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7471 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7474 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7475 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7477 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7482 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7486 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7488 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7491 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7493 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7497 po_reg_or_goto (REG_TYPE_NSD
, try_mq2
);
7500 po_reg_or_fail (REG_TYPE_MQ
);
7503 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7505 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7510 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7513 po_reg_or_fail (REG_TYPE_NSDQ
);
7517 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7521 po_reg_or_fail (REG_TYPE_MQ
);
7523 /* Neon scalar. Using an element size of 8 means that some invalid
7524 scalars are accepted here, so deal with those in later code. */
7525 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7529 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7532 po_imm_or_fail (0, 0, TRUE
);
7537 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7541 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7546 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7549 if (parse_ifimm_zero (&str
))
7550 inst
.operands
[i
].imm
= 0;
7554 = _("only floating point zero is allowed as immediate value");
7562 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7565 po_reg_or_fail (REG_TYPE_RN
);
7569 case OP_RNSDQ_RNSC_MQ_RR
:
7570 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7573 case OP_RNSDQ_RNSC_MQ
:
7574 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7579 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7583 po_reg_or_fail (REG_TYPE_NSDQ
);
7590 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7593 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7596 po_reg_or_fail (REG_TYPE_NSD
);
7600 case OP_RNDQMQ_RNSC_RR
:
7601 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7604 case OP_RNDQ_RNSC_RR
:
7605 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7607 case OP_RNDQMQ_RNSC
:
7608 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7613 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7616 po_reg_or_fail (REG_TYPE_NDQ
);
7622 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7625 po_reg_or_fail (REG_TYPE_VFD
);
7630 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7631 not careful then bad things might happen. */
7632 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7635 case OP_RNDQMQ_Ibig
:
7636 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7641 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7644 /* There's a possibility of getting a 64-bit immediate here, so
7645 we need special handling. */
7646 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7649 inst
.error
= _("immediate value is out of range");
7655 case OP_RNDQMQ_I63b_RR
:
7656 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_i63b_rr
);
7659 po_reg_or_goto (REG_TYPE_RN
, try_rndq_i63b
);
7664 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7667 po_imm_or_fail (0, 63, TRUE
);
7672 po_char_or_fail ('[');
7673 po_reg_or_fail (REG_TYPE_RN
);
7674 po_char_or_fail (']');
7680 po_reg_or_fail (REG_TYPE_RN
);
7681 if (skip_past_char (&str
, '!') == SUCCESS
)
7682 inst
.operands
[i
].writeback
= 1;
7686 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7687 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7688 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7689 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7690 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7691 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7692 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7693 case OP_I48_I64
: po_imm1_or_imm2_or_fail (48, 64, FALSE
); break;
7694 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7695 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7696 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7697 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7698 case OP_I127
: po_imm_or_fail ( 0, 127, FALSE
); break;
7699 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7700 case OP_I511
: po_imm_or_fail ( 0, 511, FALSE
); break;
7701 case OP_I4095
: po_imm_or_fail ( 0, 4095, FALSE
); break;
7702 case OP_I8191
: po_imm_or_fail ( 0, 8191, FALSE
); break;
7703 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7705 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7706 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7708 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7709 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7710 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7711 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7713 /* Immediate variants */
7715 po_char_or_fail ('{');
7716 po_imm_or_fail (0, 255, TRUE
);
7717 po_char_or_fail ('}');
7721 /* The expression parser chokes on a trailing !, so we have
7722 to find it first and zap it. */
7725 while (*s
&& *s
!= ',')
7730 inst
.operands
[i
].writeback
= 1;
7732 po_imm_or_fail (0, 31, TRUE
);
7740 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7745 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7750 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7752 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7754 val
= parse_reloc (&str
);
7757 inst
.error
= _("unrecognized relocation suffix");
7760 else if (val
!= BFD_RELOC_UNUSED
)
7762 inst
.operands
[i
].imm
= val
;
7763 inst
.operands
[i
].hasreloc
= 1;
7769 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7771 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7773 inst
.operands
[i
].hasreloc
= 1;
7775 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7777 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7778 inst
.operands
[i
].hasreloc
= 0;
7782 /* Operand for MOVW or MOVT. */
7784 po_misc_or_fail (parse_half (&str
));
7787 /* Register or expression. */
7788 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7789 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7791 /* Register or immediate. */
7792 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7793 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7795 case OP_RRnpcsp_I32
: po_reg_or_goto (REG_TYPE_RN
, I32
); break;
7796 I32
: po_imm_or_fail (1, 32, FALSE
); break;
7798 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7800 if (!is_immediate_prefix (*str
))
7803 val
= parse_fpa_immediate (&str
);
7806 /* FPA immediates are encoded as registers 8-15.
7807 parse_fpa_immediate has already applied the offset. */
7808 inst
.operands
[i
].reg
= val
;
7809 inst
.operands
[i
].isreg
= 1;
7812 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7813 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7815 /* Two kinds of register. */
7818 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7820 || (rege
->type
!= REG_TYPE_MMXWR
7821 && rege
->type
!= REG_TYPE_MMXWC
7822 && rege
->type
!= REG_TYPE_MMXWCG
))
7824 inst
.error
= _("iWMMXt data or control register expected");
7827 inst
.operands
[i
].reg
= rege
->number
;
7828 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7834 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7836 || (rege
->type
!= REG_TYPE_MMXWC
7837 && rege
->type
!= REG_TYPE_MMXWCG
))
7839 inst
.error
= _("iWMMXt control register expected");
7842 inst
.operands
[i
].reg
= rege
->number
;
7843 inst
.operands
[i
].isreg
= 1;
7848 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7849 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7850 case OP_oROR
: val
= parse_ror (&str
); break;
7852 case OP_COND
: val
= parse_cond (&str
); break;
7853 case OP_oBARRIER_I15
:
7854 po_barrier_or_imm (str
); break;
7856 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7862 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7863 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7865 inst
.error
= _("Banked registers are not available with this "
7871 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7875 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7878 val
= parse_sys_vldr_vstr (&str
);
7882 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7885 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7887 if (strncasecmp (str
, "APSR_", 5) == 0)
7894 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7895 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7896 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7897 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7898 default: found
= 16;
7902 inst
.operands
[i
].isvec
= 1;
7903 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7904 inst
.operands
[i
].reg
= REG_PC
;
7911 po_misc_or_fail (parse_tb (&str
));
7914 /* Register lists. */
7916 val
= parse_reg_list (&str
, REGLIST_RN
);
7919 inst
.operands
[i
].writeback
= 1;
7925 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7929 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7934 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7939 /* Allow Q registers too. */
7940 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7941 REGLIST_NEON_D
, &partial_match
);
7945 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7946 REGLIST_VFP_S
, &partial_match
);
7947 inst
.operands
[i
].issingle
= 1;
7952 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7953 REGLIST_VFP_D_VPR
, &partial_match
);
7954 if (val
== FAIL
&& !partial_match
)
7957 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7958 REGLIST_VFP_S_VPR
, &partial_match
);
7959 inst
.operands
[i
].issingle
= 1;
7964 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7965 REGLIST_NEON_D
, &partial_match
);
7970 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7971 1, &inst
.operands
[i
].vectype
);
7972 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7976 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7977 0, &inst
.operands
[i
].vectype
);
7980 /* Addressing modes */
7982 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7986 po_misc_or_fail (parse_address (&str
, i
));
7990 po_misc_or_fail_no_backtrack (
7991 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7995 po_misc_or_fail_no_backtrack (
7996 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
8000 po_misc_or_fail_no_backtrack (
8001 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
8005 po_misc_or_fail (parse_shifter_operand (&str
, i
));
8009 po_misc_or_fail_no_backtrack (
8010 parse_shifter_operand_group_reloc (&str
, i
));
8014 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
8018 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
8022 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
8027 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
8032 po_reg_or_goto (REG_TYPE_RN
, ZR
);
8035 po_reg_or_fail (REG_TYPE_ZR
);
8039 as_fatal (_("unhandled operand code %d"), op_parse_code
);
8042 /* Various value-based sanity checks and shared operations. We
8043 do not signal immediate failures for the register constraints;
8044 this allows a syntax error to take precedence. */
8045 switch (op_parse_code
)
8053 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
8054 inst
.error
= BAD_PC
;
8059 case OP_RRnpcsp_I32
:
8060 if (inst
.operands
[i
].isreg
)
8062 if (inst
.operands
[i
].reg
== REG_PC
)
8063 inst
.error
= BAD_PC
;
8064 else if (inst
.operands
[i
].reg
== REG_SP
8065 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
8066 relaxed since ARMv8-A. */
8067 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8070 inst
.error
= BAD_SP
;
8076 if (inst
.operands
[i
].isreg
8077 && inst
.operands
[i
].reg
== REG_PC
8078 && (inst
.operands
[i
].writeback
|| thumb
))
8079 inst
.error
= BAD_PC
;
8084 if (inst
.operands
[i
].isreg
)
8094 case OP_oBARRIER_I15
:
8107 inst
.operands
[i
].imm
= val
;
8112 if (inst
.operands
[i
].reg
!= REG_LR
)
8113 inst
.error
= _("operand must be LR register");
8119 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
8120 inst
.error
= BAD_PC
;
8124 if (inst
.operands
[i
].isreg
8125 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
8126 inst
.error
= BAD_ODD
;
8130 if (inst
.operands
[i
].isreg
)
8132 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
8133 inst
.error
= BAD_EVEN
;
8134 else if (inst
.operands
[i
].reg
== REG_SP
)
8135 as_tsktsk (MVE_BAD_SP
);
8136 else if (inst
.operands
[i
].reg
== REG_PC
)
8137 inst
.error
= BAD_PC
;
8145 /* If we get here, this operand was successfully parsed. */
8146 inst
.operands
[i
].present
= 1;
8150 inst
.error
= BAD_ARGS
;
8155 /* The parse routine should already have set inst.error, but set a
8156 default here just in case. */
8158 inst
.error
= BAD_SYNTAX
;
8162 /* Do not backtrack over a trailing optional argument that
8163 absorbed some text. We will only fail again, with the
8164 'garbage following instruction' error message, which is
8165 probably less helpful than the current one. */
8166 if (backtrack_index
== i
&& backtrack_pos
!= str
8167 && upat
[i
+1] == OP_stop
)
8170 inst
.error
= BAD_SYNTAX
;
8174 /* Try again, skipping the optional argument at backtrack_pos. */
8175 str
= backtrack_pos
;
8176 inst
.error
= backtrack_error
;
8177 inst
.operands
[backtrack_index
].present
= 0;
8178 i
= backtrack_index
;
8182 /* Check that we have parsed all the arguments. */
8183 if (*str
!= '\0' && !inst
.error
)
8184 inst
.error
= _("garbage following instruction");
8186 return inst
.error
? FAIL
: SUCCESS
;
8189 #undef po_char_or_fail
8190 #undef po_reg_or_fail
8191 #undef po_reg_or_goto
8192 #undef po_imm_or_fail
8193 #undef po_scalar_or_fail
8194 #undef po_barrier_or_imm
8196 /* Shorthand macro for instruction encoding functions issuing errors. */
8197 #define constraint(expr, err) \
8208 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
8209 instructions are unpredictable if these registers are used. This
8210 is the BadReg predicate in ARM's Thumb-2 documentation.
8212 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
8213 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
8214 #define reject_bad_reg(reg) \
8216 if (reg == REG_PC) \
8218 inst.error = BAD_PC; \
8221 else if (reg == REG_SP \
8222 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
8224 inst.error = BAD_SP; \
8229 /* If REG is R13 (the stack pointer), warn that its use is
8231 #define warn_deprecated_sp(reg) \
8233 if (warn_on_deprecated && reg == REG_SP) \
8234 as_tsktsk (_("use of r13 is deprecated")); \
8237 /* Functions for operand encoding. ARM, then Thumb. */
8239 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8241 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8243 The only binary encoding difference is the Coprocessor number. Coprocessor
8244 9 is used for half-precision calculations or conversions. The format of the
8245 instruction is the same as the equivalent Coprocessor 10 instruction that
8246 exists for Single-Precision operation. */
8249 do_scalar_fp16_v82_encode (void)
8251 if (inst
.cond
< COND_ALWAYS
)
8252 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8253 " the behaviour is UNPREDICTABLE"));
8254 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8257 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8258 mark_feature_used (&arm_ext_fp16
);
8261 /* If VAL can be encoded in the immediate field of an ARM instruction,
8262 return the encoded form. Otherwise, return FAIL. */
8265 encode_arm_immediate (unsigned int val
)
8272 for (i
= 2; i
< 32; i
+= 2)
8273 if ((a
= rotate_left (val
, i
)) <= 0xff)
8274 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8279 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8280 return the encoded form. Otherwise, return FAIL. */
8282 encode_thumb32_immediate (unsigned int val
)
8289 for (i
= 1; i
<= 24; i
++)
8292 if ((val
& ~(0xffU
<< i
)) == 0)
8293 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8297 if (val
== ((a
<< 16) | a
))
8299 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8303 if (val
== ((a
<< 16) | a
))
8304 return 0x200 | (a
>> 8);
8308 /* Encode a VFP SP or DP register number into inst.instruction. */
8311 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8313 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8316 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8319 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8322 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8327 first_error (_("D register out of range for selected VFP version"));
8335 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8339 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8343 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8347 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8351 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8355 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8363 /* Encode a <shift> in an ARM-format instruction. The immediate,
8364 if any, is handled by md_apply_fix. */
8366 encode_arm_shift (int i
)
8368 /* register-shifted register. */
8369 if (inst
.operands
[i
].immisreg
)
8372 for (op_index
= 0; op_index
<= i
; ++op_index
)
8374 /* Check the operand only when it's presented. In pre-UAL syntax,
8375 if the destination register is the same as the first operand, two
8376 register form of the instruction can be used. */
8377 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8378 && inst
.operands
[op_index
].reg
== REG_PC
)
8379 as_warn (UNPRED_REG ("r15"));
8382 if (inst
.operands
[i
].imm
== REG_PC
)
8383 as_warn (UNPRED_REG ("r15"));
8386 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8387 inst
.instruction
|= SHIFT_ROR
<< 5;
8390 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8391 if (inst
.operands
[i
].immisreg
)
8393 inst
.instruction
|= SHIFT_BY_REG
;
8394 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8397 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8402 encode_arm_shifter_operand (int i
)
8404 if (inst
.operands
[i
].isreg
)
8406 inst
.instruction
|= inst
.operands
[i
].reg
;
8407 encode_arm_shift (i
);
8411 inst
.instruction
|= INST_IMMEDIATE
;
8412 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8413 inst
.instruction
|= inst
.operands
[i
].imm
;
8417 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8419 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8422 Generate an error if the operand is not a register. */
8423 constraint (!inst
.operands
[i
].isreg
,
8424 _("Instruction does not support =N addresses"));
8426 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8428 if (inst
.operands
[i
].preind
)
8432 inst
.error
= _("instruction does not accept preindexed addressing");
8435 inst
.instruction
|= PRE_INDEX
;
8436 if (inst
.operands
[i
].writeback
)
8437 inst
.instruction
|= WRITE_BACK
;
8440 else if (inst
.operands
[i
].postind
)
8442 gas_assert (inst
.operands
[i
].writeback
);
8444 inst
.instruction
|= WRITE_BACK
;
8446 else /* unindexed - only for coprocessor */
8448 inst
.error
= _("instruction does not accept unindexed addressing");
8452 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8453 && (((inst
.instruction
& 0x000f0000) >> 16)
8454 == ((inst
.instruction
& 0x0000f000) >> 12)))
8455 as_warn ((inst
.instruction
& LOAD_BIT
)
8456 ? _("destination register same as write-back base")
8457 : _("source register same as write-back base"));
8460 /* inst.operands[i] was set up by parse_address. Encode it into an
8461 ARM-format mode 2 load or store instruction. If is_t is true,
8462 reject forms that cannot be used with a T instruction (i.e. not
8465 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8467 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8469 encode_arm_addr_mode_common (i
, is_t
);
8471 if (inst
.operands
[i
].immisreg
)
8473 constraint ((inst
.operands
[i
].imm
== REG_PC
8474 || (is_pc
&& inst
.operands
[i
].writeback
)),
8476 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8477 inst
.instruction
|= inst
.operands
[i
].imm
;
8478 if (!inst
.operands
[i
].negative
)
8479 inst
.instruction
|= INDEX_UP
;
8480 if (inst
.operands
[i
].shifted
)
8482 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8483 inst
.instruction
|= SHIFT_ROR
<< 5;
8486 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8487 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8491 else /* immediate offset in inst.relocs[0] */
8493 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8495 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8497 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8498 cannot use PC in addressing.
8499 PC cannot be used in writeback addressing, either. */
8500 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8503 /* Use of PC in str is deprecated for ARMv7. */
8504 if (warn_on_deprecated
8506 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8507 as_tsktsk (_("use of PC in this instruction is deprecated"));
8510 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8512 /* Prefer + for zero encoded value. */
8513 if (!inst
.operands
[i
].negative
)
8514 inst
.instruction
|= INDEX_UP
;
8515 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8520 /* inst.operands[i] was set up by parse_address. Encode it into an
8521 ARM-format mode 3 load or store instruction. Reject forms that
8522 cannot be used with such instructions. If is_t is true, reject
8523 forms that cannot be used with a T instruction (i.e. not
8526 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8528 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8530 inst
.error
= _("instruction does not accept scaled register index");
8534 encode_arm_addr_mode_common (i
, is_t
);
8536 if (inst
.operands
[i
].immisreg
)
8538 constraint ((inst
.operands
[i
].imm
== REG_PC
8539 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8541 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8543 inst
.instruction
|= inst
.operands
[i
].imm
;
8544 if (!inst
.operands
[i
].negative
)
8545 inst
.instruction
|= INDEX_UP
;
8547 else /* immediate offset in inst.relocs[0] */
8549 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8550 && inst
.operands
[i
].writeback
),
8552 inst
.instruction
|= HWOFFSET_IMM
;
8553 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8555 /* Prefer + for zero encoded value. */
8556 if (!inst
.operands
[i
].negative
)
8557 inst
.instruction
|= INDEX_UP
;
8559 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8564 /* Write immediate bits [7:0] to the following locations:
8566 |28/24|23 19|18 16|15 4|3 0|
8567 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8569 This function is used by VMOV/VMVN/VORR/VBIC. */
8572 neon_write_immbits (unsigned immbits
)
8574 inst
.instruction
|= immbits
& 0xf;
8575 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8576 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8579 /* Invert low-order SIZE bits of XHI:XLO. */
8582 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8584 unsigned immlo
= xlo
? *xlo
: 0;
8585 unsigned immhi
= xhi
? *xhi
: 0;
8590 immlo
= (~immlo
) & 0xff;
8594 immlo
= (~immlo
) & 0xffff;
8598 immhi
= (~immhi
) & 0xffffffff;
8602 immlo
= (~immlo
) & 0xffffffff;
8616 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8620 neon_bits_same_in_bytes (unsigned imm
)
8622 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8623 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8624 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8625 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8628 /* For immediate of above form, return 0bABCD. */
8631 neon_squash_bits (unsigned imm
)
8633 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8634 | ((imm
& 0x01000000) >> 21);
8637 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8640 neon_qfloat_bits (unsigned imm
)
8642 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8645 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8646 the instruction. *OP is passed as the initial value of the op field, and
8647 may be set to a different value depending on the constant (i.e.
8648 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8649 MVN). If the immediate looks like a repeated pattern then also
8650 try smaller element sizes. */
8653 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8654 unsigned *immbits
, int *op
, int size
,
8655 enum neon_el_type type
)
8657 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8659 if (type
== NT_float
&& !float_p
)
8662 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8664 if (size
!= 32 || *op
== 1)
8666 *immbits
= neon_qfloat_bits (immlo
);
8672 if (neon_bits_same_in_bytes (immhi
)
8673 && neon_bits_same_in_bytes (immlo
))
8677 *immbits
= (neon_squash_bits (immhi
) << 4)
8678 | neon_squash_bits (immlo
);
8689 if (immlo
== (immlo
& 0x000000ff))
8694 else if (immlo
== (immlo
& 0x0000ff00))
8696 *immbits
= immlo
>> 8;
8699 else if (immlo
== (immlo
& 0x00ff0000))
8701 *immbits
= immlo
>> 16;
8704 else if (immlo
== (immlo
& 0xff000000))
8706 *immbits
= immlo
>> 24;
8709 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8711 *immbits
= (immlo
>> 8) & 0xff;
8714 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8716 *immbits
= (immlo
>> 16) & 0xff;
8720 if ((immlo
& 0xffff) != (immlo
>> 16))
8727 if (immlo
== (immlo
& 0x000000ff))
8732 else if (immlo
== (immlo
& 0x0000ff00))
8734 *immbits
= immlo
>> 8;
8738 if ((immlo
& 0xff) != (immlo
>> 8))
8743 if (immlo
== (immlo
& 0x000000ff))
8745 /* Don't allow MVN with 8-bit immediate. */
8755 #if defined BFD_HOST_64_BIT
8756 /* Returns TRUE if double precision value V may be cast
8757 to single precision without loss of accuracy. */
8760 is_double_a_single (bfd_uint64_t v
)
8762 int exp
= (v
>> 52) & 0x7FF;
8763 bfd_uint64_t mantissa
= v
& 0xFFFFFFFFFFFFFULL
;
8765 return ((exp
== 0 || exp
== 0x7FF
8766 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8767 && (mantissa
& 0x1FFFFFFFL
) == 0);
8770 /* Returns a double precision value casted to single precision
8771 (ignoring the least significant bits in exponent and mantissa). */
8774 double_to_single (bfd_uint64_t v
)
8776 unsigned int sign
= (v
>> 63) & 1;
8777 int exp
= (v
>> 52) & 0x7FF;
8778 bfd_uint64_t mantissa
= v
& 0xFFFFFFFFFFFFFULL
;
8784 exp
= exp
- 1023 + 127;
8793 /* No denormalized numbers. */
8799 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8801 #endif /* BFD_HOST_64_BIT */
8810 static void do_vfp_nsyn_opcode (const char *);
8812 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8813 Determine whether it can be performed with a move instruction; if
8814 it can, convert inst.instruction to that move instruction and
8815 return TRUE; if it can't, convert inst.instruction to a literal-pool
8816 load and return FALSE. If this is not a valid thing to do in the
8817 current context, set inst.error and return TRUE.
8819 inst.operands[i] describes the destination register. */
8822 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8825 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8826 bfd_boolean arm_p
= (t
== CONST_ARM
);
8829 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8833 if ((inst
.instruction
& tbit
) == 0)
8835 inst
.error
= _("invalid pseudo operation");
8839 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8840 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8841 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8843 inst
.error
= _("constant expression expected");
8847 if (inst
.relocs
[0].exp
.X_op
== O_constant
8848 || inst
.relocs
[0].exp
.X_op
== O_big
)
8850 #if defined BFD_HOST_64_BIT
8855 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8857 LITTLENUM_TYPE w
[X_PRECISION
];
8860 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8862 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8864 /* FIXME: Should we check words w[2..5] ? */
8869 #if defined BFD_HOST_64_BIT
8870 v
= l
[3] & LITTLENUM_MASK
;
8871 v
<<= LITTLENUM_NUMBER_OF_BITS
;
8872 v
|= l
[2] & LITTLENUM_MASK
;
8873 v
<<= LITTLENUM_NUMBER_OF_BITS
;
8874 v
|= l
[1] & LITTLENUM_MASK
;
8875 v
<<= LITTLENUM_NUMBER_OF_BITS
;
8876 v
|= l
[0] & LITTLENUM_MASK
;
8878 v
= l
[1] & LITTLENUM_MASK
;
8879 v
<<= LITTLENUM_NUMBER_OF_BITS
;
8880 v
|= l
[0] & LITTLENUM_MASK
;
8884 v
= inst
.relocs
[0].exp
.X_add_number
;
8886 if (!inst
.operands
[i
].issingle
)
8890 /* LDR should not use lead in a flag-setting instruction being
8891 chosen so we do not check whether movs can be used. */
8893 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8894 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8895 && inst
.operands
[i
].reg
!= 13
8896 && inst
.operands
[i
].reg
!= 15)
8898 /* Check if on thumb2 it can be done with a mov.w, mvn or
8899 movw instruction. */
8900 unsigned int newimm
;
8901 bfd_boolean isNegated
= FALSE
;
8903 newimm
= encode_thumb32_immediate (v
);
8904 if (newimm
== (unsigned int) FAIL
)
8906 newimm
= encode_thumb32_immediate (~v
);
8910 /* The number can be loaded with a mov.w or mvn
8912 if (newimm
!= (unsigned int) FAIL
8913 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8915 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8916 | (inst
.operands
[i
].reg
<< 8));
8917 /* Change to MOVN. */
8918 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8919 inst
.instruction
|= (newimm
& 0x800) << 15;
8920 inst
.instruction
|= (newimm
& 0x700) << 4;
8921 inst
.instruction
|= (newimm
& 0x0ff);
8924 /* The number can be loaded with a movw instruction. */
8925 else if ((v
& ~0xFFFF) == 0
8926 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8928 int imm
= v
& 0xFFFF;
8930 inst
.instruction
= 0xf2400000; /* MOVW. */
8931 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8932 inst
.instruction
|= (imm
& 0xf000) << 4;
8933 inst
.instruction
|= (imm
& 0x0800) << 15;
8934 inst
.instruction
|= (imm
& 0x0700) << 4;
8935 inst
.instruction
|= (imm
& 0x00ff);
8936 /* In case this replacement is being done on Armv8-M
8937 Baseline we need to make sure to disable the
8938 instruction size check, as otherwise GAS will reject
8939 the use of this T32 instruction. */
8947 int value
= encode_arm_immediate (v
);
8951 /* This can be done with a mov instruction. */
8952 inst
.instruction
&= LITERAL_MASK
;
8953 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8954 inst
.instruction
|= value
& 0xfff;
8958 value
= encode_arm_immediate (~ v
);
8961 /* This can be done with a mvn instruction. */
8962 inst
.instruction
&= LITERAL_MASK
;
8963 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8964 inst
.instruction
|= value
& 0xfff;
8968 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8971 unsigned immbits
= 0;
8972 unsigned immlo
= inst
.operands
[1].imm
;
8973 unsigned immhi
= inst
.operands
[1].regisimm
8974 ? inst
.operands
[1].reg
8975 : inst
.relocs
[0].exp
.X_unsigned
8977 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8978 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8979 &op
, 64, NT_invtype
);
8983 neon_invert_size (&immlo
, &immhi
, 64);
8985 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8986 &op
, 64, NT_invtype
);
8991 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8997 /* Fill other bits in vmov encoding for both thumb and arm. */
8999 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
9001 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
9002 neon_write_immbits (immbits
);
9010 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
9011 if (inst
.operands
[i
].issingle
9012 && is_quarter_float (inst
.operands
[1].imm
)
9013 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
9015 inst
.operands
[1].imm
=
9016 neon_qfloat_bits (v
);
9017 do_vfp_nsyn_opcode ("fconsts");
9021 /* If our host does not support a 64-bit type then we cannot perform
9022 the following optimization. This mean that there will be a
9023 discrepancy between the output produced by an assembler built for
9024 a 32-bit-only host and the output produced from a 64-bit host, but
9025 this cannot be helped. */
9026 #if defined BFD_HOST_64_BIT
9027 else if (!inst
.operands
[1].issingle
9028 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
9030 if (is_double_a_single (v
)
9031 && is_quarter_float (double_to_single (v
)))
9033 inst
.operands
[1].imm
=
9034 neon_qfloat_bits (double_to_single (v
));
9035 do_vfp_nsyn_opcode ("fconstd");
9043 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
9044 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
9047 inst
.operands
[1].reg
= REG_PC
;
9048 inst
.operands
[1].isreg
= 1;
9049 inst
.operands
[1].preind
= 1;
9050 inst
.relocs
[0].pc_rel
= 1;
9051 inst
.relocs
[0].type
= (thumb_p
9052 ? BFD_RELOC_ARM_THUMB_OFFSET
9054 ? BFD_RELOC_ARM_HWLITERAL
9055 : BFD_RELOC_ARM_LITERAL
));
9059 /* inst.operands[i] was set up by parse_address. Encode it into an
9060 ARM-format instruction. Reject all forms which cannot be encoded
9061 into a coprocessor load/store instruction. If wb_ok is false,
9062 reject use of writeback; if unind_ok is false, reject use of
9063 unindexed addressing. If reloc_override is not 0, use it instead
9064 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
9065 (in which case it is preserved). */
9068 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
9070 if (!inst
.operands
[i
].isreg
)
9073 if (! inst
.operands
[0].isvec
)
9075 inst
.error
= _("invalid co-processor operand");
9078 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
9082 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9084 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
9086 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
9088 gas_assert (!inst
.operands
[i
].writeback
);
9091 inst
.error
= _("instruction does not support unindexed addressing");
9094 inst
.instruction
|= inst
.operands
[i
].imm
;
9095 inst
.instruction
|= INDEX_UP
;
9099 if (inst
.operands
[i
].preind
)
9100 inst
.instruction
|= PRE_INDEX
;
9102 if (inst
.operands
[i
].writeback
)
9104 if (inst
.operands
[i
].reg
== REG_PC
)
9106 inst
.error
= _("pc may not be used with write-back");
9111 inst
.error
= _("instruction does not support writeback");
9114 inst
.instruction
|= WRITE_BACK
;
9118 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
9119 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
9120 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
9121 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
9124 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
9126 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
9129 /* Prefer + for zero encoded value. */
9130 if (!inst
.operands
[i
].negative
)
9131 inst
.instruction
|= INDEX_UP
;
9136 /* Functions for instruction encoding, sorted by sub-architecture.
9137 First some generics; their names are taken from the conventional
9138 bit positions for register arguments in ARM format instructions. */
9148 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9154 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9160 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9161 inst
.instruction
|= inst
.operands
[1].reg
;
9167 inst
.instruction
|= inst
.operands
[0].reg
;
9168 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9174 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9175 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9181 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9182 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9188 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9189 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9193 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
9195 if (ARM_CPU_IS_ANY (cpu_variant
))
9197 as_tsktsk ("%s", msg
);
9200 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
9212 unsigned Rn
= inst
.operands
[2].reg
;
9213 /* Enforce restrictions on SWP instruction. */
9214 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
9216 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
9217 _("Rn must not overlap other operands"));
9219 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
9221 if (!check_obsolete (&arm_ext_v8
,
9222 _("swp{b} use is obsoleted for ARMv8 and later"))
9223 && warn_on_deprecated
9224 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
9225 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
9228 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9229 inst
.instruction
|= inst
.operands
[1].reg
;
9230 inst
.instruction
|= Rn
<< 16;
9236 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9237 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9238 inst
.instruction
|= inst
.operands
[2].reg
;
9244 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
9245 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
9246 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
9247 || inst
.relocs
[0].exp
.X_add_number
!= 0),
9249 inst
.instruction
|= inst
.operands
[0].reg
;
9250 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9251 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9257 inst
.instruction
|= inst
.operands
[0].imm
;
9263 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9264 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9267 /* ARM instructions, in alphabetical order by function name (except
9268 that wrapper functions appear immediately after the function they
9271 /* This is a pseudo-op of the form "adr rd, label" to be converted
9272 into a relative address of the form "add rd, pc, #label-.-8". */
9277 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9279 /* Frag hacking will turn this into a sub instruction if the offset turns
9280 out to be negative. */
9281 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9282 inst
.relocs
[0].pc_rel
= 1;
9283 inst
.relocs
[0].exp
.X_add_number
-= 8;
9285 if (support_interwork
9286 && inst
.relocs
[0].exp
.X_op
== O_symbol
9287 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9288 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9289 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9290 inst
.relocs
[0].exp
.X_add_number
|= 1;
9293 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9294 into a relative address of the form:
9295 add rd, pc, #low(label-.-8)"
9296 add rd, rd, #high(label-.-8)" */
9301 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9303 /* Frag hacking will turn this into a sub instruction if the offset turns
9304 out to be negative. */
9305 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9306 inst
.relocs
[0].pc_rel
= 1;
9307 inst
.size
= INSN_SIZE
* 2;
9308 inst
.relocs
[0].exp
.X_add_number
-= 8;
9310 if (support_interwork
9311 && inst
.relocs
[0].exp
.X_op
== O_symbol
9312 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9313 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9314 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9315 inst
.relocs
[0].exp
.X_add_number
|= 1;
9321 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9322 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9324 if (!inst
.operands
[1].present
)
9325 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9326 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9327 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9328 encode_arm_shifter_operand (2);
9334 if (inst
.operands
[0].present
)
9335 inst
.instruction
|= inst
.operands
[0].imm
;
9337 inst
.instruction
|= 0xf;
9343 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9344 constraint (msb
> 32, _("bit-field extends past end of register"));
9345 /* The instruction encoding stores the LSB and MSB,
9346 not the LSB and width. */
9347 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9348 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9349 inst
.instruction
|= (msb
- 1) << 16;
9357 /* #0 in second position is alternative syntax for bfc, which is
9358 the same instruction but with REG_PC in the Rm field. */
9359 if (!inst
.operands
[1].isreg
)
9360 inst
.operands
[1].reg
= REG_PC
;
9362 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9363 constraint (msb
> 32, _("bit-field extends past end of register"));
9364 /* The instruction encoding stores the LSB and MSB,
9365 not the LSB and width. */
9366 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9367 inst
.instruction
|= inst
.operands
[1].reg
;
9368 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9369 inst
.instruction
|= (msb
- 1) << 16;
9375 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9376 _("bit-field extends past end of register"));
9377 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9378 inst
.instruction
|= inst
.operands
[1].reg
;
9379 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9380 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9383 /* ARM V5 breakpoint instruction (argument parse)
9384 BKPT <16 bit unsigned immediate>
9385 Instruction is not conditional.
9386 The bit pattern given in insns[] has the COND_ALWAYS condition,
9387 and it is an error if the caller tried to override that. */
9392 /* Top 12 of 16 bits to bits 19:8. */
9393 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9395 /* Bottom 4 of 16 bits to bits 3:0. */
9396 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9400 encode_branch (int default_reloc
)
9402 if (inst
.operands
[0].hasreloc
)
9404 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9405 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9406 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9407 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9408 ? BFD_RELOC_ARM_PLT32
9409 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9412 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9413 inst
.relocs
[0].pc_rel
= 1;
9420 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9421 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9424 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9431 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9433 if (inst
.cond
== COND_ALWAYS
)
9434 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9436 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9440 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9443 /* ARM V5 branch-link-exchange instruction (argument parse)
9444 BLX <target_addr> ie BLX(1)
9445 BLX{<condition>} <Rm> ie BLX(2)
9446 Unfortunately, there are two different opcodes for this mnemonic.
9447 So, the insns[].value is not used, and the code here zaps values
9448 into inst.instruction.
9449 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9454 if (inst
.operands
[0].isreg
)
9456 /* Arg is a register; the opcode provided by insns[] is correct.
9457 It is not illegal to do "blx pc", just useless. */
9458 if (inst
.operands
[0].reg
== REG_PC
)
9459 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9461 inst
.instruction
|= inst
.operands
[0].reg
;
9465 /* Arg is an address; this instruction cannot be executed
9466 conditionally, and the opcode must be adjusted.
9467 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9468 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9469 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9470 inst
.instruction
= 0xfa000000;
9471 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9478 bfd_boolean want_reloc
;
9480 if (inst
.operands
[0].reg
== REG_PC
)
9481 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9483 inst
.instruction
|= inst
.operands
[0].reg
;
9484 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9485 it is for ARMv4t or earlier. */
9486 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9487 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9488 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9492 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9497 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9501 /* ARM v5TEJ. Jump to Jazelle code. */
9506 if (inst
.operands
[0].reg
== REG_PC
)
9507 as_tsktsk (_("use of r15 in bxj is not really useful"));
9509 inst
.instruction
|= inst
.operands
[0].reg
;
9512 /* Co-processor data operation:
9513 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9514 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9518 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9519 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9520 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9521 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9522 inst
.instruction
|= inst
.operands
[4].reg
;
9523 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9529 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9530 encode_arm_shifter_operand (1);
9533 /* Transfer between coprocessor and ARM registers.
9534 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9539 No special properties. */
9541 struct deprecated_coproc_regs_s
9548 arm_feature_set deprecated
;
9549 arm_feature_set obsoleted
;
9550 const char *dep_msg
;
9551 const char *obs_msg
;
9554 #define DEPR_ACCESS_V8 \
9555 N_("This coprocessor register access is deprecated in ARMv8")
9557 /* Table of all deprecated coprocessor registers. */
9558 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9560 {15, 0, 7, 10, 5, /* CP15DMB. */
9561 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9562 DEPR_ACCESS_V8
, NULL
},
9563 {15, 0, 7, 10, 4, /* CP15DSB. */
9564 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9565 DEPR_ACCESS_V8
, NULL
},
9566 {15, 0, 7, 5, 4, /* CP15ISB. */
9567 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9568 DEPR_ACCESS_V8
, NULL
},
9569 {14, 6, 1, 0, 0, /* TEEHBR. */
9570 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9571 DEPR_ACCESS_V8
, NULL
},
9572 {14, 6, 0, 0, 0, /* TEECR. */
9573 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9574 DEPR_ACCESS_V8
, NULL
},
9577 #undef DEPR_ACCESS_V8
9579 static const size_t deprecated_coproc_reg_count
=
9580 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9588 Rd
= inst
.operands
[2].reg
;
9591 if (inst
.instruction
== 0xee000010
9592 || inst
.instruction
== 0xfe000010)
9594 reject_bad_reg (Rd
);
9595 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9597 constraint (Rd
== REG_SP
, BAD_SP
);
9602 if (inst
.instruction
== 0xe000010)
9603 constraint (Rd
== REG_PC
, BAD_PC
);
9606 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9608 const struct deprecated_coproc_regs_s
*r
=
9609 deprecated_coproc_regs
+ i
;
9611 if (inst
.operands
[0].reg
== r
->cp
9612 && inst
.operands
[1].imm
== r
->opc1
9613 && inst
.operands
[3].reg
== r
->crn
9614 && inst
.operands
[4].reg
== r
->crm
9615 && inst
.operands
[5].imm
== r
->opc2
)
9617 if (! ARM_CPU_IS_ANY (cpu_variant
)
9618 && warn_on_deprecated
9619 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9620 as_tsktsk ("%s", r
->dep_msg
);
9624 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9625 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9626 inst
.instruction
|= Rd
<< 12;
9627 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9628 inst
.instruction
|= inst
.operands
[4].reg
;
9629 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9632 /* Transfer between coprocessor register and pair of ARM registers.
9633 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9638 Two XScale instructions are special cases of these:
9640 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9641 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9643 Result unpredictable if Rd or Rn is R15. */
9650 Rd
= inst
.operands
[2].reg
;
9651 Rn
= inst
.operands
[3].reg
;
9655 reject_bad_reg (Rd
);
9656 reject_bad_reg (Rn
);
9660 constraint (Rd
== REG_PC
, BAD_PC
);
9661 constraint (Rn
== REG_PC
, BAD_PC
);
9664 /* Only check the MRRC{2} variants. */
9665 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9667 /* If Rd == Rn, error that the operation is
9668 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9669 constraint (Rd
== Rn
, BAD_OVERLAP
);
9672 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9673 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9674 inst
.instruction
|= Rd
<< 12;
9675 inst
.instruction
|= Rn
<< 16;
9676 inst
.instruction
|= inst
.operands
[4].reg
;
9682 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9683 if (inst
.operands
[1].present
)
9685 inst
.instruction
|= CPSI_MMOD
;
9686 inst
.instruction
|= inst
.operands
[1].imm
;
9693 inst
.instruction
|= inst
.operands
[0].imm
;
9699 unsigned Rd
, Rn
, Rm
;
9701 Rd
= inst
.operands
[0].reg
;
9702 Rn
= (inst
.operands
[1].present
9703 ? inst
.operands
[1].reg
: Rd
);
9704 Rm
= inst
.operands
[2].reg
;
9706 constraint ((Rd
== REG_PC
), BAD_PC
);
9707 constraint ((Rn
== REG_PC
), BAD_PC
);
9708 constraint ((Rm
== REG_PC
), BAD_PC
);
9710 inst
.instruction
|= Rd
<< 16;
9711 inst
.instruction
|= Rn
<< 0;
9712 inst
.instruction
|= Rm
<< 8;
9718 /* There is no IT instruction in ARM mode. We
9719 process it to do the validation as if in
9720 thumb mode, just in case the code gets
9721 assembled for thumb using the unified syntax. */
9726 set_pred_insn_type (IT_INSN
);
9727 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9728 now_pred
.cc
= inst
.operands
[0].imm
;
9732 /* If there is only one register in the register list,
9733 then return its register number. Otherwise return -1. */
9735 only_one_reg_in_list (int range
)
9737 int i
= ffs (range
) - 1;
9738 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9742 encode_ldmstm(int from_push_pop_mnem
)
9744 int base_reg
= inst
.operands
[0].reg
;
9745 int range
= inst
.operands
[1].imm
;
9748 inst
.instruction
|= base_reg
<< 16;
9749 inst
.instruction
|= range
;
9751 if (inst
.operands
[1].writeback
)
9752 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9754 if (inst
.operands
[0].writeback
)
9756 inst
.instruction
|= WRITE_BACK
;
9757 /* Check for unpredictable uses of writeback. */
9758 if (inst
.instruction
& LOAD_BIT
)
9760 /* Not allowed in LDM type 2. */
9761 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9762 && ((range
& (1 << REG_PC
)) == 0))
9763 as_warn (_("writeback of base register is UNPREDICTABLE"));
9764 /* Only allowed if base reg not in list for other types. */
9765 else if (range
& (1 << base_reg
))
9766 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9770 /* Not allowed for type 2. */
9771 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9772 as_warn (_("writeback of base register is UNPREDICTABLE"));
9773 /* Only allowed if base reg not in list, or first in list. */
9774 else if ((range
& (1 << base_reg
))
9775 && (range
& ((1 << base_reg
) - 1)))
9776 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9780 /* If PUSH/POP has only one register, then use the A2 encoding. */
9781 one_reg
= only_one_reg_in_list (range
);
9782 if (from_push_pop_mnem
&& one_reg
>= 0)
9784 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9786 if (is_push
&& one_reg
== 13 /* SP */)
9787 /* PR 22483: The A2 encoding cannot be used when
9788 pushing the stack pointer as this is UNPREDICTABLE. */
9791 inst
.instruction
&= A_COND_MASK
;
9792 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9793 inst
.instruction
|= one_reg
<< 12;
9800 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9803 /* ARMv5TE load-consecutive (argument parse)
9812 constraint (inst
.operands
[0].reg
% 2 != 0,
9813 _("first transfer register must be even"));
9814 constraint (inst
.operands
[1].present
9815 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9816 _("can only transfer two consecutive registers"));
9817 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9818 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9820 if (!inst
.operands
[1].present
)
9821 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9823 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9824 register and the first register written; we have to diagnose
9825 overlap between the base and the second register written here. */
9827 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9828 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9829 as_warn (_("base register written back, and overlaps "
9830 "second transfer register"));
9832 if (!(inst
.instruction
& V4_STR_BIT
))
9834 /* For an index-register load, the index register must not overlap the
9835 destination (even if not write-back). */
9836 if (inst
.operands
[2].immisreg
9837 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9838 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9839 as_warn (_("index register overlaps transfer register"));
9841 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9842 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9848 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9849 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9850 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9851 || inst
.operands
[1].negative
9852 /* This can arise if the programmer has written
9854 or if they have mistakenly used a register name as the last
9857 It is very difficult to distinguish between these two cases
9858 because "rX" might actually be a label. ie the register
9859 name has been occluded by a symbol of the same name. So we
9860 just generate a general 'bad addressing mode' type error
9861 message and leave it up to the programmer to discover the
9862 true cause and fix their mistake. */
9863 || (inst
.operands
[1].reg
== REG_PC
),
9866 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9867 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9868 _("offset must be zero in ARM encoding"));
9870 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9872 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9873 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9874 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9880 constraint (inst
.operands
[0].reg
% 2 != 0,
9881 _("even register required"));
9882 constraint (inst
.operands
[1].present
9883 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9884 _("can only load two consecutive registers"));
9885 /* If op 1 were present and equal to PC, this function wouldn't
9886 have been called in the first place. */
9887 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9889 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9890 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9893 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9894 which is not a multiple of four is UNPREDICTABLE. */
9896 check_ldr_r15_aligned (void)
9898 constraint (!(inst
.operands
[1].immisreg
)
9899 && (inst
.operands
[0].reg
== REG_PC
9900 && inst
.operands
[1].reg
== REG_PC
9901 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9902 _("ldr to register 15 must be 4-byte aligned"));
9908 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9909 if (!inst
.operands
[1].isreg
)
9910 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9912 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9913 check_ldr_r15_aligned ();
9919 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9921 if (inst
.operands
[1].preind
)
9923 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9924 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9925 _("this instruction requires a post-indexed address"));
9927 inst
.operands
[1].preind
= 0;
9928 inst
.operands
[1].postind
= 1;
9929 inst
.operands
[1].writeback
= 1;
9931 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9932 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9935 /* Halfword and signed-byte load/store operations. */
9940 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9941 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9942 if (!inst
.operands
[1].isreg
)
9943 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9945 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9951 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9953 if (inst
.operands
[1].preind
)
9955 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9956 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9957 _("this instruction requires a post-indexed address"));
9959 inst
.operands
[1].preind
= 0;
9960 inst
.operands
[1].postind
= 1;
9961 inst
.operands
[1].writeback
= 1;
9963 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9964 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9967 /* Co-processor register load/store.
9968 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9972 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9973 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9974 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9980 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9981 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9982 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9983 && !(inst
.instruction
& 0x00400000))
9984 as_tsktsk (_("Rd and Rm should be different in mla"));
9986 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9987 inst
.instruction
|= inst
.operands
[1].reg
;
9988 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9989 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9995 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9996 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9998 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9999 encode_arm_shifter_operand (1);
10002 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
10009 top
= (inst
.instruction
& 0x00400000) != 0;
10010 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
10011 _(":lower16: not allowed in this instruction"));
10012 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
10013 _(":upper16: not allowed in this instruction"));
10014 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10015 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
10017 imm
= inst
.relocs
[0].exp
.X_add_number
;
10018 /* The value is in two pieces: 0:11, 16:19. */
10019 inst
.instruction
|= (imm
& 0x00000fff);
10020 inst
.instruction
|= (imm
& 0x0000f000) << 4;
10025 do_vfp_nsyn_mrs (void)
10027 if (inst
.operands
[0].isvec
)
10029 if (inst
.operands
[1].reg
!= 1)
10030 first_error (_("operand 1 must be FPSCR"));
10031 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
10032 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
10033 do_vfp_nsyn_opcode ("fmstat");
10035 else if (inst
.operands
[1].isvec
)
10036 do_vfp_nsyn_opcode ("fmrx");
10044 do_vfp_nsyn_msr (void)
10046 if (inst
.operands
[0].isvec
)
10047 do_vfp_nsyn_opcode ("fmxr");
10057 unsigned Rt
= inst
.operands
[0].reg
;
10059 if (thumb_mode
&& Rt
== REG_SP
)
10061 inst
.error
= BAD_SP
;
10065 switch (inst
.operands
[1].reg
)
10067 /* MVFR2 is only valid for Armv8-A. */
10069 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10073 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10074 case 1: /* fpscr. */
10075 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10076 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10080 case 14: /* fpcxt_ns. */
10081 case 15: /* fpcxt_s. */
10082 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10083 _("selected processor does not support instruction"));
10086 case 2: /* fpscr_nzcvqc. */
10087 case 12: /* vpr. */
10089 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10090 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10091 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10092 _("selected processor does not support instruction"));
10093 if (inst
.operands
[0].reg
!= 2
10094 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10095 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10102 /* APSR_ sets isvec. All other refs to PC are illegal. */
10103 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
10105 inst
.error
= BAD_PC
;
10109 /* If we get through parsing the register name, we just insert the number
10110 generated into the instruction without further validation. */
10111 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
10112 inst
.instruction
|= (Rt
<< 12);
10118 unsigned Rt
= inst
.operands
[1].reg
;
10121 reject_bad_reg (Rt
);
10122 else if (Rt
== REG_PC
)
10124 inst
.error
= BAD_PC
;
10128 switch (inst
.operands
[0].reg
)
10130 /* MVFR2 is only valid for Armv8-A. */
10132 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10136 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10137 case 1: /* fpcr. */
10138 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10139 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10143 case 14: /* fpcxt_ns. */
10144 case 15: /* fpcxt_s. */
10145 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10146 _("selected processor does not support instruction"));
10149 case 2: /* fpscr_nzcvqc. */
10150 case 12: /* vpr. */
10152 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10153 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10154 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10155 _("selected processor does not support instruction"));
10156 if (inst
.operands
[0].reg
!= 2
10157 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10158 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10165 /* If we get through parsing the register name, we just insert the number
10166 generated into the instruction without further validation. */
10167 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
10168 inst
.instruction
|= (Rt
<< 12);
10176 if (do_vfp_nsyn_mrs () == SUCCESS
)
10179 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10180 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10182 if (inst
.operands
[1].isreg
)
10184 br
= inst
.operands
[1].reg
;
10185 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
10186 as_bad (_("bad register for mrs"));
10190 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10191 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
10193 _("'APSR', 'CPSR' or 'SPSR' expected"));
10194 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
10197 inst
.instruction
|= br
;
10200 /* Two possible forms:
10201 "{C|S}PSR_<field>, Rm",
10202 "{C|S}PSR_f, #expression". */
10207 if (do_vfp_nsyn_msr () == SUCCESS
)
10210 inst
.instruction
|= inst
.operands
[0].imm
;
10211 if (inst
.operands
[1].isreg
)
10212 inst
.instruction
|= inst
.operands
[1].reg
;
10215 inst
.instruction
|= INST_IMMEDIATE
;
10216 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
10217 inst
.relocs
[0].pc_rel
= 0;
10224 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
10226 if (!inst
.operands
[2].present
)
10227 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10228 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10229 inst
.instruction
|= inst
.operands
[1].reg
;
10230 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10232 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
10233 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10234 as_tsktsk (_("Rd and Rm should be different in mul"));
10237 /* Long Multiply Parser
10238 UMULL RdLo, RdHi, Rm, Rs
10239 SMULL RdLo, RdHi, Rm, Rs
10240 UMLAL RdLo, RdHi, Rm, Rs
10241 SMLAL RdLo, RdHi, Rm, Rs. */
10246 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10247 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10248 inst
.instruction
|= inst
.operands
[2].reg
;
10249 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10251 /* rdhi and rdlo must be different. */
10252 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10253 as_tsktsk (_("rdhi and rdlo must be different"));
10255 /* rdhi, rdlo and rm must all be different before armv6. */
10256 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
10257 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
10258 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10259 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10265 if (inst
.operands
[0].present
10266 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
10268 /* Architectural NOP hints are CPSR sets with no bits selected. */
10269 inst
.instruction
&= 0xf0000000;
10270 inst
.instruction
|= 0x0320f000;
10271 if (inst
.operands
[0].present
)
10272 inst
.instruction
|= inst
.operands
[0].imm
;
10276 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
10277 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10278 Condition defaults to COND_ALWAYS.
10279 Error if Rd, Rn or Rm are R15. */
10284 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10285 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10286 inst
.instruction
|= inst
.operands
[2].reg
;
10287 if (inst
.operands
[3].present
)
10288 encode_arm_shift (3);
10291 /* ARM V6 PKHTB (Argument Parse). */
10296 if (!inst
.operands
[3].present
)
10298 /* If the shift specifier is omitted, turn the instruction
10299 into pkhbt rd, rm, rn. */
10300 inst
.instruction
&= 0xfff00010;
10301 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10302 inst
.instruction
|= inst
.operands
[1].reg
;
10303 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10307 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10308 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10309 inst
.instruction
|= inst
.operands
[2].reg
;
10310 encode_arm_shift (3);
10314 /* ARMv5TE: Preload-Cache
10315 MP Extensions: Preload for write
10319 Syntactically, like LDR with B=1, W=0, L=1. */
10324 constraint (!inst
.operands
[0].isreg
,
10325 _("'[' expected after PLD mnemonic"));
10326 constraint (inst
.operands
[0].postind
,
10327 _("post-indexed expression used in preload instruction"));
10328 constraint (inst
.operands
[0].writeback
,
10329 _("writeback used in preload instruction"));
10330 constraint (!inst
.operands
[0].preind
,
10331 _("unindexed addressing used in preload instruction"));
10332 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10335 /* ARMv7: PLI <addr_mode> */
10339 constraint (!inst
.operands
[0].isreg
,
10340 _("'[' expected after PLI mnemonic"));
10341 constraint (inst
.operands
[0].postind
,
10342 _("post-indexed expression used in preload instruction"));
10343 constraint (inst
.operands
[0].writeback
,
10344 _("writeback used in preload instruction"));
10345 constraint (!inst
.operands
[0].preind
,
10346 _("unindexed addressing used in preload instruction"));
10347 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10348 inst
.instruction
&= ~PRE_INDEX
;
10354 constraint (inst
.operands
[0].writeback
,
10355 _("push/pop do not support {reglist}^"));
10356 inst
.operands
[1] = inst
.operands
[0];
10357 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10358 inst
.operands
[0].isreg
= 1;
10359 inst
.operands
[0].writeback
= 1;
10360 inst
.operands
[0].reg
= REG_SP
;
10361 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10364 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10365 word at the specified address and the following word
10367 Unconditionally executed.
10368 Error if Rn is R15. */
10373 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10374 if (inst
.operands
[0].writeback
)
10375 inst
.instruction
|= WRITE_BACK
;
10378 /* ARM V6 ssat (argument parse). */
10383 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10384 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10385 inst
.instruction
|= inst
.operands
[2].reg
;
10387 if (inst
.operands
[3].present
)
10388 encode_arm_shift (3);
10391 /* ARM V6 usat (argument parse). */
10396 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10397 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10398 inst
.instruction
|= inst
.operands
[2].reg
;
10400 if (inst
.operands
[3].present
)
10401 encode_arm_shift (3);
10404 /* ARM V6 ssat16 (argument parse). */
10409 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10410 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10411 inst
.instruction
|= inst
.operands
[2].reg
;
10417 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10418 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10419 inst
.instruction
|= inst
.operands
[2].reg
;
10422 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10423 preserving the other bits.
10425 setend <endian_specifier>, where <endian_specifier> is either
10431 if (warn_on_deprecated
10432 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10433 as_tsktsk (_("setend use is deprecated for ARMv8"));
10435 if (inst
.operands
[0].imm
)
10436 inst
.instruction
|= 0x200;
10442 unsigned int Rm
= (inst
.operands
[1].present
10443 ? inst
.operands
[1].reg
10444 : inst
.operands
[0].reg
);
10446 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10447 inst
.instruction
|= Rm
;
10448 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10450 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10451 inst
.instruction
|= SHIFT_BY_REG
;
10452 /* PR 12854: Error on extraneous shifts. */
10453 constraint (inst
.operands
[2].shifted
,
10454 _("extraneous shift as part of operand to shift insn"));
10457 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10463 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10464 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
10466 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10467 inst
.relocs
[0].pc_rel
= 0;
10473 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10474 inst
.relocs
[0].pc_rel
= 0;
10480 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10481 inst
.relocs
[0].pc_rel
= 0;
10487 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10488 _("selected processor does not support SETPAN instruction"));
10490 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10496 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10497 _("selected processor does not support SETPAN instruction"));
10499 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10502 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10503 SMLAxy{cond} Rd,Rm,Rs,Rn
10504 SMLAWy{cond} Rd,Rm,Rs,Rn
10505 Error if any register is R15. */
10510 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10511 inst
.instruction
|= inst
.operands
[1].reg
;
10512 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10513 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10516 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10517 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10518 Error if any register is R15.
10519 Warning if Rdlo == Rdhi. */
10524 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10525 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10526 inst
.instruction
|= inst
.operands
[2].reg
;
10527 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10529 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10530 as_tsktsk (_("rdhi and rdlo must be different"));
10533 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10534 SMULxy{cond} Rd,Rm,Rs
10535 Error if any register is R15. */
10540 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10541 inst
.instruction
|= inst
.operands
[1].reg
;
10542 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10545 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10546 the same for both ARM and Thumb-2. */
10553 if (inst
.operands
[0].present
)
10555 reg
= inst
.operands
[0].reg
;
10556 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10561 inst
.instruction
|= reg
<< 16;
10562 inst
.instruction
|= inst
.operands
[1].imm
;
10563 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10564 inst
.instruction
|= WRITE_BACK
;
10567 /* ARM V6 strex (argument parse). */
10572 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10573 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10574 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10575 || inst
.operands
[2].negative
10576 /* See comment in do_ldrex(). */
10577 || (inst
.operands
[2].reg
== REG_PC
),
10580 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10581 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10583 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10584 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10585 _("offset must be zero in ARM encoding"));
10587 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10588 inst
.instruction
|= inst
.operands
[1].reg
;
10589 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10590 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10594 do_t_strexbh (void)
10596 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10597 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10598 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10599 || inst
.operands
[2].negative
,
10602 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10603 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10611 constraint (inst
.operands
[1].reg
% 2 != 0,
10612 _("even register required"));
10613 constraint (inst
.operands
[2].present
10614 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10615 _("can only store two consecutive registers"));
10616 /* If op 2 were present and equal to PC, this function wouldn't
10617 have been called in the first place. */
10618 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10620 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10621 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10622 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10625 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10626 inst
.instruction
|= inst
.operands
[1].reg
;
10627 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10634 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10635 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10643 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10644 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10649 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10650 extends it to 32-bits, and adds the result to a value in another
10651 register. You can specify a rotation by 0, 8, 16, or 24 bits
10652 before extracting the 16-bit value.
10653 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10654 Condition defaults to COND_ALWAYS.
10655 Error if any register uses R15. */
10660 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10661 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10662 inst
.instruction
|= inst
.operands
[2].reg
;
10663 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10668 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10669 Condition defaults to COND_ALWAYS.
10670 Error if any register uses R15. */
10675 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10676 inst
.instruction
|= inst
.operands
[1].reg
;
10677 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10680 /* VFP instructions. In a logical order: SP variant first, monad
10681 before dyad, arithmetic then move then load/store. */
10684 do_vfp_sp_monadic (void)
10686 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10687 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10690 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10691 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10695 do_vfp_sp_dyadic (void)
10697 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10698 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10699 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10703 do_vfp_sp_compare_z (void)
10705 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10709 do_vfp_dp_sp_cvt (void)
10711 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10712 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10716 do_vfp_sp_dp_cvt (void)
10718 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10719 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10723 do_vfp_reg_from_sp (void)
10725 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10726 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10729 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10730 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10734 do_vfp_reg2_from_sp2 (void)
10736 constraint (inst
.operands
[2].imm
!= 2,
10737 _("only two consecutive VFP SP registers allowed here"));
10738 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10739 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10740 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10744 do_vfp_sp_from_reg (void)
10746 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10747 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10750 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10751 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10755 do_vfp_sp2_from_reg2 (void)
10757 constraint (inst
.operands
[0].imm
!= 2,
10758 _("only two consecutive VFP SP registers allowed here"));
10759 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10760 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10761 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10765 do_vfp_sp_ldst (void)
10767 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10768 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10772 do_vfp_dp_ldst (void)
10774 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10775 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10780 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10782 if (inst
.operands
[0].writeback
)
10783 inst
.instruction
|= WRITE_BACK
;
10785 constraint (ldstm_type
!= VFP_LDSTMIA
,
10786 _("this addressing mode requires base-register writeback"));
10787 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10788 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10789 inst
.instruction
|= inst
.operands
[1].imm
;
10793 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10797 if (inst
.operands
[0].writeback
)
10798 inst
.instruction
|= WRITE_BACK
;
10800 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10801 _("this addressing mode requires base-register writeback"));
10803 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10804 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10806 count
= inst
.operands
[1].imm
<< 1;
10807 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10810 inst
.instruction
|= count
;
10814 do_vfp_sp_ldstmia (void)
10816 vfp_sp_ldstm (VFP_LDSTMIA
);
10820 do_vfp_sp_ldstmdb (void)
10822 vfp_sp_ldstm (VFP_LDSTMDB
);
10826 do_vfp_dp_ldstmia (void)
10828 vfp_dp_ldstm (VFP_LDSTMIA
);
10832 do_vfp_dp_ldstmdb (void)
10834 vfp_dp_ldstm (VFP_LDSTMDB
);
10838 do_vfp_xp_ldstmia (void)
10840 vfp_dp_ldstm (VFP_LDSTMIAX
);
10844 do_vfp_xp_ldstmdb (void)
10846 vfp_dp_ldstm (VFP_LDSTMDBX
);
10850 do_vfp_dp_rd_rm (void)
10852 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10853 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10856 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10857 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10861 do_vfp_dp_rn_rd (void)
10863 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10864 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10868 do_vfp_dp_rd_rn (void)
10870 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10871 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10875 do_vfp_dp_rd_rn_rm (void)
10877 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10878 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10881 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10882 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10883 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10887 do_vfp_dp_rd (void)
10889 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10893 do_vfp_dp_rm_rd_rn (void)
10895 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10896 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10899 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10900 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10901 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10904 /* VFPv3 instructions. */
10906 do_vfp_sp_const (void)
10908 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10909 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10910 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10914 do_vfp_dp_const (void)
10916 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10917 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10918 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10922 vfp_conv (int srcsize
)
10924 int immbits
= srcsize
- inst
.operands
[1].imm
;
10926 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10928 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10929 i.e. immbits must be in range 0 - 16. */
10930 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10933 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10935 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10936 i.e. immbits must be in range 0 - 31. */
10937 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10941 inst
.instruction
|= (immbits
& 1) << 5;
10942 inst
.instruction
|= (immbits
>> 1);
10946 do_vfp_sp_conv_16 (void)
10948 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10953 do_vfp_dp_conv_16 (void)
10955 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10960 do_vfp_sp_conv_32 (void)
10962 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10967 do_vfp_dp_conv_32 (void)
10969 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10973 /* FPA instructions. Also in a logical order. */
10978 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10979 inst
.instruction
|= inst
.operands
[1].reg
;
10983 do_fpa_ldmstm (void)
10985 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10986 switch (inst
.operands
[1].imm
)
10988 case 1: inst
.instruction
|= CP_T_X
; break;
10989 case 2: inst
.instruction
|= CP_T_Y
; break;
10990 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10995 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10997 /* The instruction specified "ea" or "fd", so we can only accept
10998 [Rn]{!}. The instruction does not really support stacking or
10999 unstacking, so we have to emulate these by setting appropriate
11000 bits and offsets. */
11001 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
11002 || inst
.relocs
[0].exp
.X_add_number
!= 0,
11003 _("this instruction does not support indexing"));
11005 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
11006 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
11008 if (!(inst
.instruction
& INDEX_UP
))
11009 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
11011 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
11013 inst
.operands
[2].preind
= 0;
11014 inst
.operands
[2].postind
= 1;
11018 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
11021 /* iWMMXt instructions: strictly in alphabetical order. */
11024 do_iwmmxt_tandorc (void)
11026 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
11030 do_iwmmxt_textrc (void)
11032 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11033 inst
.instruction
|= inst
.operands
[1].imm
;
11037 do_iwmmxt_textrm (void)
11039 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11040 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11041 inst
.instruction
|= inst
.operands
[2].imm
;
11045 do_iwmmxt_tinsr (void)
11047 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11048 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11049 inst
.instruction
|= inst
.operands
[2].imm
;
11053 do_iwmmxt_tmia (void)
11055 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11056 inst
.instruction
|= inst
.operands
[1].reg
;
11057 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11061 do_iwmmxt_waligni (void)
11063 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11064 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11065 inst
.instruction
|= inst
.operands
[2].reg
;
11066 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
11070 do_iwmmxt_wmerge (void)
11072 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11073 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11074 inst
.instruction
|= inst
.operands
[2].reg
;
11075 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
11079 do_iwmmxt_wmov (void)
11081 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
11082 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11083 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11084 inst
.instruction
|= inst
.operands
[1].reg
;
11088 do_iwmmxt_wldstbh (void)
11091 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11093 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
11095 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
11096 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
11100 do_iwmmxt_wldstw (void)
11102 /* RIWR_RIWC clears .isreg for a control register. */
11103 if (!inst
.operands
[0].isreg
)
11105 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
11106 inst
.instruction
|= 0xf0000000;
11109 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11110 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
11114 do_iwmmxt_wldstd (void)
11116 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11117 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
11118 && inst
.operands
[1].immisreg
)
11120 inst
.instruction
&= ~0x1a000ff;
11121 inst
.instruction
|= (0xfU
<< 28);
11122 if (inst
.operands
[1].preind
)
11123 inst
.instruction
|= PRE_INDEX
;
11124 if (!inst
.operands
[1].negative
)
11125 inst
.instruction
|= INDEX_UP
;
11126 if (inst
.operands
[1].writeback
)
11127 inst
.instruction
|= WRITE_BACK
;
11128 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11129 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11130 inst
.instruction
|= inst
.operands
[1].imm
;
11133 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
11137 do_iwmmxt_wshufh (void)
11139 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11140 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11141 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
11142 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
11146 do_iwmmxt_wzero (void)
11148 /* WZERO reg is an alias for WANDN reg, reg, reg. */
11149 inst
.instruction
|= inst
.operands
[0].reg
;
11150 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11151 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11155 do_iwmmxt_wrwrwr_or_imm5 (void)
11157 if (inst
.operands
[2].isreg
)
11160 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
11161 _("immediate operand requires iWMMXt2"));
11163 if (inst
.operands
[2].imm
== 0)
11165 switch ((inst
.instruction
>> 20) & 0xf)
11171 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
11172 inst
.operands
[2].imm
= 16;
11173 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
11179 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
11180 inst
.operands
[2].imm
= 32;
11181 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
11188 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
11190 wrn
= (inst
.instruction
>> 16) & 0xf;
11191 inst
.instruction
&= 0xff0fff0f;
11192 inst
.instruction
|= wrn
;
11193 /* Bail out here; the instruction is now assembled. */
11198 /* Map 32 -> 0, etc. */
11199 inst
.operands
[2].imm
&= 0x1f;
11200 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
11204 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
11205 operations first, then control, shift, and load/store. */
11207 /* Insns like "foo X,Y,Z". */
11210 do_mav_triple (void)
11212 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11213 inst
.instruction
|= inst
.operands
[1].reg
;
11214 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11217 /* Insns like "foo W,X,Y,Z".
11218 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
11223 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11224 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11225 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11226 inst
.instruction
|= inst
.operands
[3].reg
;
11229 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
11231 do_mav_dspsc (void)
11233 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11236 /* Maverick shift immediate instructions.
11237 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
11238 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
11241 do_mav_shift (void)
11243 int imm
= inst
.operands
[2].imm
;
11245 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11246 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11248 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
11249 Bits 5-7 of the insn should have bits 4-6 of the immediate.
11250 Bit 4 should be 0. */
11251 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
11253 inst
.instruction
|= imm
;
11256 /* XScale instructions. Also sorted arithmetic before move. */
11258 /* Xscale multiply-accumulate (argument parse)
11261 MIAxycc acc0,Rm,Rs. */
11266 inst
.instruction
|= inst
.operands
[1].reg
;
11267 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11270 /* Xscale move-accumulator-register (argument parse)
11272 MARcc acc0,RdLo,RdHi. */
11277 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11278 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11281 /* Xscale move-register-accumulator (argument parse)
11283 MRAcc RdLo,RdHi,acc0. */
11288 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
11289 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11290 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11293 /* Encoding functions relevant only to Thumb. */
11295 /* inst.operands[i] is a shifted-register operand; encode
11296 it into inst.instruction in the format used by Thumb32. */
11299 encode_thumb32_shifted_operand (int i
)
11301 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11302 unsigned int shift
= inst
.operands
[i
].shift_kind
;
11304 constraint (inst
.operands
[i
].immisreg
,
11305 _("shift by register not allowed in thumb mode"));
11306 inst
.instruction
|= inst
.operands
[i
].reg
;
11307 if (shift
== SHIFT_RRX
)
11308 inst
.instruction
|= SHIFT_ROR
<< 4;
11311 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11312 _("expression too complex"));
11314 constraint (value
> 32
11315 || (value
== 32 && (shift
== SHIFT_LSL
11316 || shift
== SHIFT_ROR
)),
11317 _("shift expression is too large"));
11321 else if (value
== 32)
11324 inst
.instruction
|= shift
<< 4;
11325 inst
.instruction
|= (value
& 0x1c) << 10;
11326 inst
.instruction
|= (value
& 0x03) << 6;
11331 /* inst.operands[i] was set up by parse_address. Encode it into a
11332 Thumb32 format load or store instruction. Reject forms that cannot
11333 be used with such instructions. If is_t is true, reject forms that
11334 cannot be used with a T instruction; if is_d is true, reject forms
11335 that cannot be used with a D instruction. If it is a store insn,
11336 reject PC in Rn. */
11339 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11341 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11343 constraint (!inst
.operands
[i
].isreg
,
11344 _("Instruction does not support =N addresses"));
11346 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11347 if (inst
.operands
[i
].immisreg
)
11349 constraint (is_pc
, BAD_PC_ADDRESSING
);
11350 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11351 constraint (inst
.operands
[i
].negative
,
11352 _("Thumb does not support negative register indexing"));
11353 constraint (inst
.operands
[i
].postind
,
11354 _("Thumb does not support register post-indexing"));
11355 constraint (inst
.operands
[i
].writeback
,
11356 _("Thumb does not support register indexing with writeback"));
11357 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11358 _("Thumb supports only LSL in shifted register indexing"));
11360 inst
.instruction
|= inst
.operands
[i
].imm
;
11361 if (inst
.operands
[i
].shifted
)
11363 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11364 _("expression too complex"));
11365 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11366 || inst
.relocs
[0].exp
.X_add_number
> 3,
11367 _("shift out of range"));
11368 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11370 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11372 else if (inst
.operands
[i
].preind
)
11374 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11375 constraint (is_t
&& inst
.operands
[i
].writeback
,
11376 _("cannot use writeback with this instruction"));
11377 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11378 BAD_PC_ADDRESSING
);
11382 inst
.instruction
|= 0x01000000;
11383 if (inst
.operands
[i
].writeback
)
11384 inst
.instruction
|= 0x00200000;
11388 inst
.instruction
|= 0x00000c00;
11389 if (inst
.operands
[i
].writeback
)
11390 inst
.instruction
|= 0x00000100;
11392 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11394 else if (inst
.operands
[i
].postind
)
11396 gas_assert (inst
.operands
[i
].writeback
);
11397 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11398 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11401 inst
.instruction
|= 0x00200000;
11403 inst
.instruction
|= 0x00000900;
11404 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11406 else /* unindexed - only for coprocessor */
11407 inst
.error
= _("instruction does not accept unindexed addressing");
11410 /* Table of Thumb instructions which exist in 16- and/or 32-bit
11411 encodings (the latter only in post-V6T2 cores). The index is the
11412 value used in the insns table below. When there is more than one
11413 possible 16-bit encoding for the instruction, this table always
11415 Also contains several pseudo-instructions used during relaxation. */
11416 #define T16_32_TAB \
11417 X(_adc, 4140, eb400000), \
11418 X(_adcs, 4140, eb500000), \
11419 X(_add, 1c00, eb000000), \
11420 X(_adds, 1c00, eb100000), \
11421 X(_addi, 0000, f1000000), \
11422 X(_addis, 0000, f1100000), \
11423 X(_add_pc,000f, f20f0000), \
11424 X(_add_sp,000d, f10d0000), \
11425 X(_adr, 000f, f20f0000), \
11426 X(_and, 4000, ea000000), \
11427 X(_ands, 4000, ea100000), \
11428 X(_asr, 1000, fa40f000), \
11429 X(_asrs, 1000, fa50f000), \
11430 X(_b, e000, f000b000), \
11431 X(_bcond, d000, f0008000), \
11432 X(_bf, 0000, f040e001), \
11433 X(_bfcsel,0000, f000e001), \
11434 X(_bfx, 0000, f060e001), \
11435 X(_bfl, 0000, f000c001), \
11436 X(_bflx, 0000, f070e001), \
11437 X(_bic, 4380, ea200000), \
11438 X(_bics, 4380, ea300000), \
11439 X(_cinc, 0000, ea509000), \
11440 X(_cinv, 0000, ea50a000), \
11441 X(_cmn, 42c0, eb100f00), \
11442 X(_cmp, 2800, ebb00f00), \
11443 X(_cneg, 0000, ea50b000), \
11444 X(_cpsie, b660, f3af8400), \
11445 X(_cpsid, b670, f3af8600), \
11446 X(_cpy, 4600, ea4f0000), \
11447 X(_csel, 0000, ea508000), \
11448 X(_cset, 0000, ea5f900f), \
11449 X(_csetm, 0000, ea5fa00f), \
11450 X(_csinc, 0000, ea509000), \
11451 X(_csinv, 0000, ea50a000), \
11452 X(_csneg, 0000, ea50b000), \
11453 X(_dec_sp,80dd, f1ad0d00), \
11454 X(_dls, 0000, f040e001), \
11455 X(_dlstp, 0000, f000e001), \
11456 X(_eor, 4040, ea800000), \
11457 X(_eors, 4040, ea900000), \
11458 X(_inc_sp,00dd, f10d0d00), \
11459 X(_lctp, 0000, f00fe001), \
11460 X(_ldmia, c800, e8900000), \
11461 X(_ldr, 6800, f8500000), \
11462 X(_ldrb, 7800, f8100000), \
11463 X(_ldrh, 8800, f8300000), \
11464 X(_ldrsb, 5600, f9100000), \
11465 X(_ldrsh, 5e00, f9300000), \
11466 X(_ldr_pc,4800, f85f0000), \
11467 X(_ldr_pc2,4800, f85f0000), \
11468 X(_ldr_sp,9800, f85d0000), \
11469 X(_le, 0000, f00fc001), \
11470 X(_letp, 0000, f01fc001), \
11471 X(_lsl, 0000, fa00f000), \
11472 X(_lsls, 0000, fa10f000), \
11473 X(_lsr, 0800, fa20f000), \
11474 X(_lsrs, 0800, fa30f000), \
11475 X(_mov, 2000, ea4f0000), \
11476 X(_movs, 2000, ea5f0000), \
11477 X(_mul, 4340, fb00f000), \
11478 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11479 X(_mvn, 43c0, ea6f0000), \
11480 X(_mvns, 43c0, ea7f0000), \
11481 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11482 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11483 X(_orr, 4300, ea400000), \
11484 X(_orrs, 4300, ea500000), \
11485 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11486 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11487 X(_rev, ba00, fa90f080), \
11488 X(_rev16, ba40, fa90f090), \
11489 X(_revsh, bac0, fa90f0b0), \
11490 X(_ror, 41c0, fa60f000), \
11491 X(_rors, 41c0, fa70f000), \
11492 X(_sbc, 4180, eb600000), \
11493 X(_sbcs, 4180, eb700000), \
11494 X(_stmia, c000, e8800000), \
11495 X(_str, 6000, f8400000), \
11496 X(_strb, 7000, f8000000), \
11497 X(_strh, 8000, f8200000), \
11498 X(_str_sp,9000, f84d0000), \
11499 X(_sub, 1e00, eba00000), \
11500 X(_subs, 1e00, ebb00000), \
11501 X(_subi, 8000, f1a00000), \
11502 X(_subis, 8000, f1b00000), \
11503 X(_sxtb, b240, fa4ff080), \
11504 X(_sxth, b200, fa0ff080), \
11505 X(_tst, 4200, ea100f00), \
11506 X(_uxtb, b2c0, fa5ff080), \
11507 X(_uxth, b280, fa1ff080), \
11508 X(_nop, bf00, f3af8000), \
11509 X(_yield, bf10, f3af8001), \
11510 X(_wfe, bf20, f3af8002), \
11511 X(_wfi, bf30, f3af8003), \
11512 X(_wls, 0000, f040c001), \
11513 X(_wlstp, 0000, f000c001), \
11514 X(_sev, bf40, f3af8004), \
11515 X(_sevl, bf50, f3af8005), \
11516 X(_udf, de00, f7f0a000)
11518 /* To catch errors in encoding functions, the codes are all offset by
11519 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11520 as 16-bit instructions. */
11521 #define X(a,b,c) T_MNEM##a
11522 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11525 #define X(a,b,c) 0x##b
11526 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11527 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11530 #define X(a,b,c) 0x##c
11531 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11532 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11533 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11537 /* Thumb instruction encoders, in alphabetical order. */
11539 /* ADDW or SUBW. */
11542 do_t_add_sub_w (void)
11546 Rd
= inst
.operands
[0].reg
;
11547 Rn
= inst
.operands
[1].reg
;
11549 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11550 is the SP-{plus,minus}-immediate form of the instruction. */
11552 constraint (Rd
== REG_PC
, BAD_PC
);
11554 reject_bad_reg (Rd
);
11556 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11557 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11560 /* Parse an add or subtract instruction. We get here with inst.instruction
11561 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11564 do_t_add_sub (void)
11568 Rd
= inst
.operands
[0].reg
;
11569 Rs
= (inst
.operands
[1].present
11570 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11571 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11574 set_pred_insn_type_last ();
11576 if (unified_syntax
)
11579 bfd_boolean narrow
;
11582 flags
= (inst
.instruction
== T_MNEM_adds
11583 || inst
.instruction
== T_MNEM_subs
);
11585 narrow
= !in_pred_block ();
11587 narrow
= in_pred_block ();
11588 if (!inst
.operands
[2].isreg
)
11592 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11593 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11595 add
= (inst
.instruction
== T_MNEM_add
11596 || inst
.instruction
== T_MNEM_adds
);
11598 if (inst
.size_req
!= 4)
11600 /* Attempt to use a narrow opcode, with relaxation if
11602 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11603 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11604 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11605 opcode
= T_MNEM_add_sp
;
11606 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11607 opcode
= T_MNEM_add_pc
;
11608 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11611 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11613 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11617 inst
.instruction
= THUMB_OP16(opcode
);
11618 inst
.instruction
|= (Rd
<< 4) | Rs
;
11619 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11620 || (inst
.relocs
[0].type
11621 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11623 if (inst
.size_req
== 2)
11624 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11626 inst
.relax
= opcode
;
11630 constraint (inst
.size_req
== 2, BAD_HIREG
);
11632 if (inst
.size_req
== 4
11633 || (inst
.size_req
!= 2 && !opcode
))
11635 constraint ((inst
.relocs
[0].type
11636 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11637 && (inst
.relocs
[0].type
11638 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11639 THUMB1_RELOC_ONLY
);
11642 constraint (add
, BAD_PC
);
11643 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11644 _("only SUBS PC, LR, #const allowed"));
11645 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11646 _("expression too complex"));
11647 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11648 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11649 _("immediate value out of range"));
11650 inst
.instruction
= T2_SUBS_PC_LR
11651 | inst
.relocs
[0].exp
.X_add_number
;
11652 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11655 else if (Rs
== REG_PC
)
11657 /* Always use addw/subw. */
11658 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11659 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11663 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11664 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11667 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11669 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11671 inst
.instruction
|= Rd
<< 8;
11672 inst
.instruction
|= Rs
<< 16;
11677 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11678 unsigned int shift
= inst
.operands
[2].shift_kind
;
11680 Rn
= inst
.operands
[2].reg
;
11681 /* See if we can do this with a 16-bit instruction. */
11682 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11684 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11689 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11690 || inst
.instruction
== T_MNEM_add
)
11692 : T_OPCODE_SUB_R3
);
11693 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11697 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11699 /* Thumb-1 cores (except v6-M) require at least one high
11700 register in a narrow non flag setting add. */
11701 if (Rd
> 7 || Rn
> 7
11702 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11703 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11710 inst
.instruction
= T_OPCODE_ADD_HI
;
11711 inst
.instruction
|= (Rd
& 8) << 4;
11712 inst
.instruction
|= (Rd
& 7);
11713 inst
.instruction
|= Rn
<< 3;
11719 constraint (Rd
== REG_PC
, BAD_PC
);
11720 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11721 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11722 constraint (Rs
== REG_PC
, BAD_PC
);
11723 reject_bad_reg (Rn
);
11725 /* If we get here, it can't be done in 16 bits. */
11726 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11727 _("shift must be constant"));
11728 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11729 inst
.instruction
|= Rd
<< 8;
11730 inst
.instruction
|= Rs
<< 16;
11731 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11732 _("shift value over 3 not allowed in thumb mode"));
11733 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11734 _("only LSL shift allowed in thumb mode"));
11735 encode_thumb32_shifted_operand (2);
11740 constraint (inst
.instruction
== T_MNEM_adds
11741 || inst
.instruction
== T_MNEM_subs
,
11744 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11746 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11747 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11750 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11751 ? 0x0000 : 0x8000);
11752 inst
.instruction
|= (Rd
<< 4) | Rs
;
11753 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11757 Rn
= inst
.operands
[2].reg
;
11758 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11760 /* We now have Rd, Rs, and Rn set to registers. */
11761 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11763 /* Can't do this for SUB. */
11764 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11765 inst
.instruction
= T_OPCODE_ADD_HI
;
11766 inst
.instruction
|= (Rd
& 8) << 4;
11767 inst
.instruction
|= (Rd
& 7);
11769 inst
.instruction
|= Rn
<< 3;
11771 inst
.instruction
|= Rs
<< 3;
11773 constraint (1, _("dest must overlap one source register"));
11777 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11778 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11779 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11789 Rd
= inst
.operands
[0].reg
;
11790 reject_bad_reg (Rd
);
11792 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11794 /* Defer to section relaxation. */
11795 inst
.relax
= inst
.instruction
;
11796 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11797 inst
.instruction
|= Rd
<< 4;
11799 else if (unified_syntax
&& inst
.size_req
!= 2)
11801 /* Generate a 32-bit opcode. */
11802 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11803 inst
.instruction
|= Rd
<< 8;
11804 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11805 inst
.relocs
[0].pc_rel
= 1;
11809 /* Generate a 16-bit opcode. */
11810 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11811 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11812 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11813 inst
.relocs
[0].pc_rel
= 1;
11814 inst
.instruction
|= Rd
<< 4;
11817 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11818 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11819 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11820 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11821 inst
.relocs
[0].exp
.X_add_number
+= 1;
11824 /* Arithmetic instructions for which there is just one 16-bit
11825 instruction encoding, and it allows only two low registers.
11826 For maximal compatibility with ARM syntax, we allow three register
11827 operands even when Thumb-32 instructions are not available, as long
11828 as the first two are identical. For instance, both "sbc r0,r1" and
11829 "sbc r0,r0,r1" are allowed. */
11835 Rd
= inst
.operands
[0].reg
;
11836 Rs
= (inst
.operands
[1].present
11837 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11838 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11839 Rn
= inst
.operands
[2].reg
;
11841 reject_bad_reg (Rd
);
11842 reject_bad_reg (Rs
);
11843 if (inst
.operands
[2].isreg
)
11844 reject_bad_reg (Rn
);
11846 if (unified_syntax
)
11848 if (!inst
.operands
[2].isreg
)
11850 /* For an immediate, we always generate a 32-bit opcode;
11851 section relaxation will shrink it later if possible. */
11852 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11853 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11854 inst
.instruction
|= Rd
<< 8;
11855 inst
.instruction
|= Rs
<< 16;
11856 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11860 bfd_boolean narrow
;
11862 /* See if we can do this with a 16-bit instruction. */
11863 if (THUMB_SETS_FLAGS (inst
.instruction
))
11864 narrow
= !in_pred_block ();
11866 narrow
= in_pred_block ();
11868 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11870 if (inst
.operands
[2].shifted
)
11872 if (inst
.size_req
== 4)
11878 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11879 inst
.instruction
|= Rd
;
11880 inst
.instruction
|= Rn
<< 3;
11884 /* If we get here, it can't be done in 16 bits. */
11885 constraint (inst
.operands
[2].shifted
11886 && inst
.operands
[2].immisreg
,
11887 _("shift must be constant"));
11888 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11889 inst
.instruction
|= Rd
<< 8;
11890 inst
.instruction
|= Rs
<< 16;
11891 encode_thumb32_shifted_operand (2);
11896 /* On its face this is a lie - the instruction does set the
11897 flags. However, the only supported mnemonic in this mode
11898 says it doesn't. */
11899 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11901 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11902 _("unshifted register required"));
11903 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11904 constraint (Rd
!= Rs
,
11905 _("dest and source1 must be the same register"));
11907 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11908 inst
.instruction
|= Rd
;
11909 inst
.instruction
|= Rn
<< 3;
11913 /* Similarly, but for instructions where the arithmetic operation is
11914 commutative, so we can allow either of them to be different from
11915 the destination operand in a 16-bit instruction. For instance, all
11916 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11923 Rd
= inst
.operands
[0].reg
;
11924 Rs
= (inst
.operands
[1].present
11925 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11926 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11927 Rn
= inst
.operands
[2].reg
;
11929 reject_bad_reg (Rd
);
11930 reject_bad_reg (Rs
);
11931 if (inst
.operands
[2].isreg
)
11932 reject_bad_reg (Rn
);
11934 if (unified_syntax
)
11936 if (!inst
.operands
[2].isreg
)
11938 /* For an immediate, we always generate a 32-bit opcode;
11939 section relaxation will shrink it later if possible. */
11940 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11941 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11942 inst
.instruction
|= Rd
<< 8;
11943 inst
.instruction
|= Rs
<< 16;
11944 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11948 bfd_boolean narrow
;
11950 /* See if we can do this with a 16-bit instruction. */
11951 if (THUMB_SETS_FLAGS (inst
.instruction
))
11952 narrow
= !in_pred_block ();
11954 narrow
= in_pred_block ();
11956 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11958 if (inst
.operands
[2].shifted
)
11960 if (inst
.size_req
== 4)
11967 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11968 inst
.instruction
|= Rd
;
11969 inst
.instruction
|= Rn
<< 3;
11974 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11975 inst
.instruction
|= Rd
;
11976 inst
.instruction
|= Rs
<< 3;
11981 /* If we get here, it can't be done in 16 bits. */
11982 constraint (inst
.operands
[2].shifted
11983 && inst
.operands
[2].immisreg
,
11984 _("shift must be constant"));
11985 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11986 inst
.instruction
|= Rd
<< 8;
11987 inst
.instruction
|= Rs
<< 16;
11988 encode_thumb32_shifted_operand (2);
11993 /* On its face this is a lie - the instruction does set the
11994 flags. However, the only supported mnemonic in this mode
11995 says it doesn't. */
11996 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11998 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11999 _("unshifted register required"));
12000 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
12002 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12003 inst
.instruction
|= Rd
;
12006 inst
.instruction
|= Rn
<< 3;
12008 inst
.instruction
|= Rs
<< 3;
12010 constraint (1, _("dest must overlap one source register"));
12018 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
12019 constraint (msb
> 32, _("bit-field extends past end of register"));
12020 /* The instruction encoding stores the LSB and MSB,
12021 not the LSB and width. */
12022 Rd
= inst
.operands
[0].reg
;
12023 reject_bad_reg (Rd
);
12024 inst
.instruction
|= Rd
<< 8;
12025 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
12026 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
12027 inst
.instruction
|= msb
- 1;
12036 Rd
= inst
.operands
[0].reg
;
12037 reject_bad_reg (Rd
);
12039 /* #0 in second position is alternative syntax for bfc, which is
12040 the same instruction but with REG_PC in the Rm field. */
12041 if (!inst
.operands
[1].isreg
)
12045 Rn
= inst
.operands
[1].reg
;
12046 reject_bad_reg (Rn
);
12049 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
12050 constraint (msb
> 32, _("bit-field extends past end of register"));
12051 /* The instruction encoding stores the LSB and MSB,
12052 not the LSB and width. */
12053 inst
.instruction
|= Rd
<< 8;
12054 inst
.instruction
|= Rn
<< 16;
12055 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
12056 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
12057 inst
.instruction
|= msb
- 1;
12065 Rd
= inst
.operands
[0].reg
;
12066 Rn
= inst
.operands
[1].reg
;
12068 reject_bad_reg (Rd
);
12069 reject_bad_reg (Rn
);
12071 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
12072 _("bit-field extends past end of register"));
12073 inst
.instruction
|= Rd
<< 8;
12074 inst
.instruction
|= Rn
<< 16;
12075 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
12076 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
12077 inst
.instruction
|= inst
.operands
[3].imm
- 1;
12080 /* ARM V5 Thumb BLX (argument parse)
12081 BLX <target_addr> which is BLX(1)
12082 BLX <Rm> which is BLX(2)
12083 Unfortunately, there are two different opcodes for this mnemonic.
12084 So, the insns[].value is not used, and the code here zaps values
12085 into inst.instruction.
12087 ??? How to take advantage of the additional two bits of displacement
12088 available in Thumb32 mode? Need new relocation? */
12093 set_pred_insn_type_last ();
12095 if (inst
.operands
[0].isreg
)
12097 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
12098 /* We have a register, so this is BLX(2). */
12099 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12103 /* No register. This must be BLX(1). */
12104 inst
.instruction
= 0xf000e800;
12105 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
12114 bfd_reloc_code_real_type reloc
;
12117 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
12119 if (in_pred_block ())
12121 /* Conditional branches inside IT blocks are encoded as unconditional
12123 cond
= COND_ALWAYS
;
12128 if (cond
!= COND_ALWAYS
)
12129 opcode
= T_MNEM_bcond
;
12131 opcode
= inst
.instruction
;
12134 && (inst
.size_req
== 4
12135 || (inst
.size_req
!= 2
12136 && (inst
.operands
[0].hasreloc
12137 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
12139 inst
.instruction
= THUMB_OP32(opcode
);
12140 if (cond
== COND_ALWAYS
)
12141 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
12144 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
12145 _("selected architecture does not support "
12146 "wide conditional branch instruction"));
12148 gas_assert (cond
!= 0xF);
12149 inst
.instruction
|= cond
<< 22;
12150 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
12155 inst
.instruction
= THUMB_OP16(opcode
);
12156 if (cond
== COND_ALWAYS
)
12157 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
12160 inst
.instruction
|= cond
<< 8;
12161 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
12163 /* Allow section relaxation. */
12164 if (unified_syntax
&& inst
.size_req
!= 2)
12165 inst
.relax
= opcode
;
12167 inst
.relocs
[0].type
= reloc
;
12168 inst
.relocs
[0].pc_rel
= 1;
12171 /* Actually do the work for Thumb state bkpt and hlt. The only difference
12172 between the two is the maximum immediate allowed - which is passed in
12175 do_t_bkpt_hlt1 (int range
)
12177 constraint (inst
.cond
!= COND_ALWAYS
,
12178 _("instruction is always unconditional"));
12179 if (inst
.operands
[0].present
)
12181 constraint (inst
.operands
[0].imm
> range
,
12182 _("immediate value out of range"));
12183 inst
.instruction
|= inst
.operands
[0].imm
;
12186 set_pred_insn_type (NEUTRAL_IT_INSN
);
12192 do_t_bkpt_hlt1 (63);
12198 do_t_bkpt_hlt1 (255);
12202 do_t_branch23 (void)
12204 set_pred_insn_type_last ();
12205 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
12207 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
12208 this file. We used to simply ignore the PLT reloc type here --
12209 the branch encoding is now needed to deal with TLSCALL relocs.
12210 So if we see a PLT reloc now, put it back to how it used to be to
12211 keep the preexisting behaviour. */
12212 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
12213 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
12215 #if defined(OBJ_COFF)
12216 /* If the destination of the branch is a defined symbol which does not have
12217 the THUMB_FUNC attribute, then we must be calling a function which has
12218 the (interfacearm) attribute. We look for the Thumb entry point to that
12219 function and change the branch to refer to that function instead. */
12220 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
12221 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
12222 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
12223 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
12224 inst
.relocs
[0].exp
.X_add_symbol
12225 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
12232 set_pred_insn_type_last ();
12233 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12234 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
12235 should cause the alignment to be checked once it is known. This is
12236 because BX PC only works if the instruction is word aligned. */
12244 set_pred_insn_type_last ();
12245 Rm
= inst
.operands
[0].reg
;
12246 reject_bad_reg (Rm
);
12247 inst
.instruction
|= Rm
<< 16;
12256 Rd
= inst
.operands
[0].reg
;
12257 Rm
= inst
.operands
[1].reg
;
12259 reject_bad_reg (Rd
);
12260 reject_bad_reg (Rm
);
12262 inst
.instruction
|= Rd
<< 8;
12263 inst
.instruction
|= Rm
<< 16;
12264 inst
.instruction
|= Rm
;
12267 /* For the Armv8.1-M conditional instructions. */
12271 unsigned Rd
, Rn
, Rm
;
12274 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
12276 Rd
= inst
.operands
[0].reg
;
12277 switch (inst
.instruction
)
12283 Rn
= inst
.operands
[1].reg
;
12284 Rm
= inst
.operands
[2].reg
;
12285 cond
= inst
.operands
[3].imm
;
12286 constraint (Rn
== REG_SP
, BAD_SP
);
12287 constraint (Rm
== REG_SP
, BAD_SP
);
12293 Rn
= inst
.operands
[1].reg
;
12294 cond
= inst
.operands
[2].imm
;
12295 /* Invert the last bit to invert the cond. */
12296 cond
= TOGGLE_BIT (cond
, 0);
12297 constraint (Rn
== REG_SP
, BAD_SP
);
12303 cond
= inst
.operands
[1].imm
;
12304 /* Invert the last bit to invert the cond. */
12305 cond
= TOGGLE_BIT (cond
, 0);
12313 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12314 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12315 inst
.instruction
|= Rd
<< 8;
12316 inst
.instruction
|= Rn
<< 16;
12317 inst
.instruction
|= Rm
;
12318 inst
.instruction
|= cond
<< 4;
12324 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12330 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12331 inst
.instruction
|= inst
.operands
[0].imm
;
12337 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12339 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
12340 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
12342 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
12343 inst
.instruction
= 0xf3af8000;
12344 inst
.instruction
|= imod
<< 9;
12345 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
12346 if (inst
.operands
[1].present
)
12347 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
12351 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
12352 && (inst
.operands
[0].imm
& 4),
12353 _("selected processor does not support 'A' form "
12354 "of this instruction"));
12355 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
12356 _("Thumb does not support the 2-argument "
12357 "form of this instruction"));
12358 inst
.instruction
|= inst
.operands
[0].imm
;
12362 /* THUMB CPY instruction (argument parse). */
12367 if (inst
.size_req
== 4)
12369 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
12370 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12371 inst
.instruction
|= inst
.operands
[1].reg
;
12375 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
12376 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
12377 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12384 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12385 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12386 inst
.instruction
|= inst
.operands
[0].reg
;
12387 inst
.relocs
[0].pc_rel
= 1;
12388 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12394 inst
.instruction
|= inst
.operands
[0].imm
;
12400 unsigned Rd
, Rn
, Rm
;
12402 Rd
= inst
.operands
[0].reg
;
12403 Rn
= (inst
.operands
[1].present
12404 ? inst
.operands
[1].reg
: Rd
);
12405 Rm
= inst
.operands
[2].reg
;
12407 reject_bad_reg (Rd
);
12408 reject_bad_reg (Rn
);
12409 reject_bad_reg (Rm
);
12411 inst
.instruction
|= Rd
<< 8;
12412 inst
.instruction
|= Rn
<< 16;
12413 inst
.instruction
|= Rm
;
12419 if (unified_syntax
&& inst
.size_req
== 4)
12420 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12422 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12428 unsigned int cond
= inst
.operands
[0].imm
;
12430 set_pred_insn_type (IT_INSN
);
12431 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12432 now_pred
.cc
= cond
;
12433 now_pred
.warn_deprecated
= FALSE
;
12434 now_pred
.type
= SCALAR_PRED
;
12436 /* If the condition is a negative condition, invert the mask. */
12437 if ((cond
& 0x1) == 0x0)
12439 unsigned int mask
= inst
.instruction
& 0x000f;
12441 if ((mask
& 0x7) == 0)
12443 /* No conversion needed. */
12444 now_pred
.block_length
= 1;
12446 else if ((mask
& 0x3) == 0)
12449 now_pred
.block_length
= 2;
12451 else if ((mask
& 0x1) == 0)
12454 now_pred
.block_length
= 3;
12459 now_pred
.block_length
= 4;
12462 inst
.instruction
&= 0xfff0;
12463 inst
.instruction
|= mask
;
12466 inst
.instruction
|= cond
<< 4;
12469 /* Helper function used for both push/pop and ldm/stm. */
12471 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12472 bfd_boolean writeback
)
12474 bfd_boolean load
, store
;
12476 gas_assert (base
!= -1 || !do_io
);
12477 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12478 store
= do_io
&& !load
;
12480 if (mask
& (1 << 13))
12481 inst
.error
= _("SP not allowed in register list");
12483 if (do_io
&& (mask
& (1 << base
)) != 0
12485 inst
.error
= _("having the base register in the register list when "
12486 "using write back is UNPREDICTABLE");
12490 if (mask
& (1 << 15))
12492 if (mask
& (1 << 14))
12493 inst
.error
= _("LR and PC should not both be in register list");
12495 set_pred_insn_type_last ();
12500 if (mask
& (1 << 15))
12501 inst
.error
= _("PC not allowed in register list");
12504 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12506 /* Single register transfers implemented as str/ldr. */
12509 if (inst
.instruction
& (1 << 23))
12510 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12512 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12516 if (inst
.instruction
& (1 << 23))
12517 inst
.instruction
= 0x00800000; /* ia -> [base] */
12519 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12522 inst
.instruction
|= 0xf8400000;
12524 inst
.instruction
|= 0x00100000;
12526 mask
= ffs (mask
) - 1;
12529 else if (writeback
)
12530 inst
.instruction
|= WRITE_BACK
;
12532 inst
.instruction
|= mask
;
12534 inst
.instruction
|= base
<< 16;
12540 /* This really doesn't seem worth it. */
12541 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12542 _("expression too complex"));
12543 constraint (inst
.operands
[1].writeback
,
12544 _("Thumb load/store multiple does not support {reglist}^"));
12546 if (unified_syntax
)
12548 bfd_boolean narrow
;
12552 /* See if we can use a 16-bit instruction. */
12553 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12554 && inst
.size_req
!= 4
12555 && !(inst
.operands
[1].imm
& ~0xff))
12557 mask
= 1 << inst
.operands
[0].reg
;
12559 if (inst
.operands
[0].reg
<= 7)
12561 if (inst
.instruction
== T_MNEM_stmia
12562 ? inst
.operands
[0].writeback
12563 : (inst
.operands
[0].writeback
12564 == !(inst
.operands
[1].imm
& mask
)))
12566 if (inst
.instruction
== T_MNEM_stmia
12567 && (inst
.operands
[1].imm
& mask
)
12568 && (inst
.operands
[1].imm
& (mask
- 1)))
12569 as_warn (_("value stored for r%d is UNKNOWN"),
12570 inst
.operands
[0].reg
);
12572 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12573 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12574 inst
.instruction
|= inst
.operands
[1].imm
;
12577 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12579 /* This means 1 register in reg list one of 3 situations:
12580 1. Instruction is stmia, but without writeback.
12581 2. lmdia without writeback, but with Rn not in
12583 3. ldmia with writeback, but with Rn in reglist.
12584 Case 3 is UNPREDICTABLE behaviour, so we handle
12585 case 1 and 2 which can be converted into a 16-bit
12586 str or ldr. The SP cases are handled below. */
12587 unsigned long opcode
;
12588 /* First, record an error for Case 3. */
12589 if (inst
.operands
[1].imm
& mask
12590 && inst
.operands
[0].writeback
)
12592 _("having the base register in the register list when "
12593 "using write back is UNPREDICTABLE");
12595 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12597 inst
.instruction
= THUMB_OP16 (opcode
);
12598 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12599 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12603 else if (inst
.operands
[0] .reg
== REG_SP
)
12605 if (inst
.operands
[0].writeback
)
12608 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12609 ? T_MNEM_push
: T_MNEM_pop
);
12610 inst
.instruction
|= inst
.operands
[1].imm
;
12613 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12616 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12617 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12618 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12626 if (inst
.instruction
< 0xffff)
12627 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12629 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12630 inst
.operands
[1].imm
,
12631 inst
.operands
[0].writeback
);
12636 constraint (inst
.operands
[0].reg
> 7
12637 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12638 constraint (inst
.instruction
!= T_MNEM_ldmia
12639 && inst
.instruction
!= T_MNEM_stmia
,
12640 _("Thumb-2 instruction only valid in unified syntax"));
12641 if (inst
.instruction
== T_MNEM_stmia
)
12643 if (!inst
.operands
[0].writeback
)
12644 as_warn (_("this instruction will write back the base register"));
12645 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12646 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12647 as_warn (_("value stored for r%d is UNKNOWN"),
12648 inst
.operands
[0].reg
);
12652 if (!inst
.operands
[0].writeback
12653 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12654 as_warn (_("this instruction will write back the base register"));
12655 else if (inst
.operands
[0].writeback
12656 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12657 as_warn (_("this instruction will not write back the base register"));
12660 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12661 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12662 inst
.instruction
|= inst
.operands
[1].imm
;
12669 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12670 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12671 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12672 || inst
.operands
[1].negative
,
12675 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12677 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12678 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12679 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12685 if (!inst
.operands
[1].present
)
12687 constraint (inst
.operands
[0].reg
== REG_LR
,
12688 _("r14 not allowed as first register "
12689 "when second register is omitted"));
12690 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12692 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12695 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12696 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12697 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12703 unsigned long opcode
;
12706 if (inst
.operands
[0].isreg
12707 && !inst
.operands
[0].preind
12708 && inst
.operands
[0].reg
== REG_PC
)
12709 set_pred_insn_type_last ();
12711 opcode
= inst
.instruction
;
12712 if (unified_syntax
)
12714 if (!inst
.operands
[1].isreg
)
12716 if (opcode
<= 0xffff)
12717 inst
.instruction
= THUMB_OP32 (opcode
);
12718 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12721 if (inst
.operands
[1].isreg
12722 && !inst
.operands
[1].writeback
12723 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12724 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12725 && opcode
<= 0xffff
12726 && inst
.size_req
!= 4)
12728 /* Insn may have a 16-bit form. */
12729 Rn
= inst
.operands
[1].reg
;
12730 if (inst
.operands
[1].immisreg
)
12732 inst
.instruction
= THUMB_OP16 (opcode
);
12734 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12736 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12737 reject_bad_reg (inst
.operands
[1].imm
);
12739 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12740 && opcode
!= T_MNEM_ldrsb
)
12741 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12742 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12749 if (inst
.relocs
[0].pc_rel
)
12750 opcode
= T_MNEM_ldr_pc2
;
12752 opcode
= T_MNEM_ldr_pc
;
12756 if (opcode
== T_MNEM_ldr
)
12757 opcode
= T_MNEM_ldr_sp
;
12759 opcode
= T_MNEM_str_sp
;
12761 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12765 inst
.instruction
= inst
.operands
[0].reg
;
12766 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12768 inst
.instruction
|= THUMB_OP16 (opcode
);
12769 if (inst
.size_req
== 2)
12770 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12772 inst
.relax
= opcode
;
12776 /* Definitely a 32-bit variant. */
12778 /* Warning for Erratum 752419. */
12779 if (opcode
== T_MNEM_ldr
12780 && inst
.operands
[0].reg
== REG_SP
12781 && inst
.operands
[1].writeback
== 1
12782 && !inst
.operands
[1].immisreg
)
12784 if (no_cpu_selected ()
12785 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12786 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12787 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12788 as_warn (_("This instruction may be unpredictable "
12789 "if executed on M-profile cores "
12790 "with interrupts enabled."));
12793 /* Do some validations regarding addressing modes. */
12794 if (inst
.operands
[1].immisreg
)
12795 reject_bad_reg (inst
.operands
[1].imm
);
12797 constraint (inst
.operands
[1].writeback
== 1
12798 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12801 inst
.instruction
= THUMB_OP32 (opcode
);
12802 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12803 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12804 check_ldr_r15_aligned ();
12808 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12810 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12812 /* Only [Rn,Rm] is acceptable. */
12813 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12814 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12815 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12816 || inst
.operands
[1].negative
,
12817 _("Thumb does not support this addressing mode"));
12818 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12822 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12823 if (!inst
.operands
[1].isreg
)
12824 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12827 constraint (!inst
.operands
[1].preind
12828 || inst
.operands
[1].shifted
12829 || inst
.operands
[1].writeback
,
12830 _("Thumb does not support this addressing mode"));
12831 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12833 constraint (inst
.instruction
& 0x0600,
12834 _("byte or halfword not valid for base register"));
12835 constraint (inst
.operands
[1].reg
== REG_PC
12836 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12837 _("r15 based store not allowed"));
12838 constraint (inst
.operands
[1].immisreg
,
12839 _("invalid base register for register offset"));
12841 if (inst
.operands
[1].reg
== REG_PC
)
12842 inst
.instruction
= T_OPCODE_LDR_PC
;
12843 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12844 inst
.instruction
= T_OPCODE_LDR_SP
;
12846 inst
.instruction
= T_OPCODE_STR_SP
;
12848 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12849 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12853 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12854 if (!inst
.operands
[1].immisreg
)
12856 /* Immediate offset. */
12857 inst
.instruction
|= inst
.operands
[0].reg
;
12858 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12859 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12863 /* Register offset. */
12864 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12865 constraint (inst
.operands
[1].negative
,
12866 _("Thumb does not support this addressing mode"));
12869 switch (inst
.instruction
)
12871 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12872 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12873 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12874 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12875 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12876 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12877 case 0x5600 /* ldrsb */:
12878 case 0x5e00 /* ldrsh */: break;
12882 inst
.instruction
|= inst
.operands
[0].reg
;
12883 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12884 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12890 if (!inst
.operands
[1].present
)
12892 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12893 constraint (inst
.operands
[0].reg
== REG_LR
,
12894 _("r14 not allowed here"));
12895 constraint (inst
.operands
[0].reg
== REG_R12
,
12896 _("r12 not allowed here"));
12899 if (inst
.operands
[2].writeback
12900 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12901 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12902 as_warn (_("base register written back, and overlaps "
12903 "one of transfer registers"));
12905 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12906 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12907 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12913 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12914 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12920 unsigned Rd
, Rn
, Rm
, Ra
;
12922 Rd
= inst
.operands
[0].reg
;
12923 Rn
= inst
.operands
[1].reg
;
12924 Rm
= inst
.operands
[2].reg
;
12925 Ra
= inst
.operands
[3].reg
;
12927 reject_bad_reg (Rd
);
12928 reject_bad_reg (Rn
);
12929 reject_bad_reg (Rm
);
12930 reject_bad_reg (Ra
);
12932 inst
.instruction
|= Rd
<< 8;
12933 inst
.instruction
|= Rn
<< 16;
12934 inst
.instruction
|= Rm
;
12935 inst
.instruction
|= Ra
<< 12;
12941 unsigned RdLo
, RdHi
, Rn
, Rm
;
12943 RdLo
= inst
.operands
[0].reg
;
12944 RdHi
= inst
.operands
[1].reg
;
12945 Rn
= inst
.operands
[2].reg
;
12946 Rm
= inst
.operands
[3].reg
;
12948 reject_bad_reg (RdLo
);
12949 reject_bad_reg (RdHi
);
12950 reject_bad_reg (Rn
);
12951 reject_bad_reg (Rm
);
12953 inst
.instruction
|= RdLo
<< 12;
12954 inst
.instruction
|= RdHi
<< 8;
12955 inst
.instruction
|= Rn
<< 16;
12956 inst
.instruction
|= Rm
;
12960 do_t_mov_cmp (void)
12964 Rn
= inst
.operands
[0].reg
;
12965 Rm
= inst
.operands
[1].reg
;
12968 set_pred_insn_type_last ();
12970 if (unified_syntax
)
12972 int r0off
= (inst
.instruction
== T_MNEM_mov
12973 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12974 unsigned long opcode
;
12975 bfd_boolean narrow
;
12976 bfd_boolean low_regs
;
12978 low_regs
= (Rn
<= 7 && Rm
<= 7);
12979 opcode
= inst
.instruction
;
12980 if (in_pred_block ())
12981 narrow
= opcode
!= T_MNEM_movs
;
12983 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12984 if (inst
.size_req
== 4
12985 || inst
.operands
[1].shifted
)
12988 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12989 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12990 && !inst
.operands
[1].shifted
12994 inst
.instruction
= T2_SUBS_PC_LR
;
12998 if (opcode
== T_MNEM_cmp
)
13000 constraint (Rn
== REG_PC
, BAD_PC
);
13003 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
13005 warn_deprecated_sp (Rm
);
13006 /* R15 was documented as a valid choice for Rm in ARMv6,
13007 but as UNPREDICTABLE in ARMv7. ARM's proprietary
13008 tools reject R15, so we do too. */
13009 constraint (Rm
== REG_PC
, BAD_PC
);
13012 reject_bad_reg (Rm
);
13014 else if (opcode
== T_MNEM_mov
13015 || opcode
== T_MNEM_movs
)
13017 if (inst
.operands
[1].isreg
)
13019 if (opcode
== T_MNEM_movs
)
13021 reject_bad_reg (Rn
);
13022 reject_bad_reg (Rm
);
13026 /* This is mov.n. */
13027 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
13028 && (Rm
== REG_SP
|| Rm
== REG_PC
))
13030 as_tsktsk (_("Use of r%u as a source register is "
13031 "deprecated when r%u is the destination "
13032 "register."), Rm
, Rn
);
13037 /* This is mov.w. */
13038 constraint (Rn
== REG_PC
, BAD_PC
);
13039 constraint (Rm
== REG_PC
, BAD_PC
);
13040 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13041 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
13045 reject_bad_reg (Rn
);
13048 if (!inst
.operands
[1].isreg
)
13050 /* Immediate operand. */
13051 if (!in_pred_block () && opcode
== T_MNEM_mov
)
13053 if (low_regs
&& narrow
)
13055 inst
.instruction
= THUMB_OP16 (opcode
);
13056 inst
.instruction
|= Rn
<< 8;
13057 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
13058 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
13060 if (inst
.size_req
== 2)
13061 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13063 inst
.relax
= opcode
;
13068 constraint ((inst
.relocs
[0].type
13069 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
13070 && (inst
.relocs
[0].type
13071 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
13072 THUMB1_RELOC_ONLY
);
13074 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13075 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13076 inst
.instruction
|= Rn
<< r0off
;
13077 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13080 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
13081 && (inst
.instruction
== T_MNEM_mov
13082 || inst
.instruction
== T_MNEM_movs
))
13084 /* Register shifts are encoded as separate shift instructions. */
13085 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
13087 if (in_pred_block ())
13092 if (inst
.size_req
== 4)
13095 if (!low_regs
|| inst
.operands
[1].imm
> 7)
13101 switch (inst
.operands
[1].shift_kind
)
13104 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
13107 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
13110 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
13113 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
13119 inst
.instruction
= opcode
;
13122 inst
.instruction
|= Rn
;
13123 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
13128 inst
.instruction
|= CONDS_BIT
;
13130 inst
.instruction
|= Rn
<< 8;
13131 inst
.instruction
|= Rm
<< 16;
13132 inst
.instruction
|= inst
.operands
[1].imm
;
13137 /* Some mov with immediate shift have narrow variants.
13138 Register shifts are handled above. */
13139 if (low_regs
&& inst
.operands
[1].shifted
13140 && (inst
.instruction
== T_MNEM_mov
13141 || inst
.instruction
== T_MNEM_movs
))
13143 if (in_pred_block ())
13144 narrow
= (inst
.instruction
== T_MNEM_mov
);
13146 narrow
= (inst
.instruction
== T_MNEM_movs
);
13151 switch (inst
.operands
[1].shift_kind
)
13153 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13154 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13155 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13156 default: narrow
= FALSE
; break;
13162 inst
.instruction
|= Rn
;
13163 inst
.instruction
|= Rm
<< 3;
13164 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13168 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13169 inst
.instruction
|= Rn
<< r0off
;
13170 encode_thumb32_shifted_operand (1);
13174 switch (inst
.instruction
)
13177 /* In v4t or v5t a move of two lowregs produces unpredictable
13178 results. Don't allow this. */
13181 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
13182 "MOV Rd, Rs with two low registers is not "
13183 "permitted on this architecture");
13184 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13188 inst
.instruction
= T_OPCODE_MOV_HR
;
13189 inst
.instruction
|= (Rn
& 0x8) << 4;
13190 inst
.instruction
|= (Rn
& 0x7);
13191 inst
.instruction
|= Rm
<< 3;
13195 /* We know we have low registers at this point.
13196 Generate LSLS Rd, Rs, #0. */
13197 inst
.instruction
= T_OPCODE_LSL_I
;
13198 inst
.instruction
|= Rn
;
13199 inst
.instruction
|= Rm
<< 3;
13205 inst
.instruction
= T_OPCODE_CMP_LR
;
13206 inst
.instruction
|= Rn
;
13207 inst
.instruction
|= Rm
<< 3;
13211 inst
.instruction
= T_OPCODE_CMP_HR
;
13212 inst
.instruction
|= (Rn
& 0x8) << 4;
13213 inst
.instruction
|= (Rn
& 0x7);
13214 inst
.instruction
|= Rm
<< 3;
13221 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13223 /* PR 10443: Do not silently ignore shifted operands. */
13224 constraint (inst
.operands
[1].shifted
,
13225 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
13227 if (inst
.operands
[1].isreg
)
13229 if (Rn
< 8 && Rm
< 8)
13231 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
13232 since a MOV instruction produces unpredictable results. */
13233 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13234 inst
.instruction
= T_OPCODE_ADD_I3
;
13236 inst
.instruction
= T_OPCODE_CMP_LR
;
13238 inst
.instruction
|= Rn
;
13239 inst
.instruction
|= Rm
<< 3;
13243 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13244 inst
.instruction
= T_OPCODE_MOV_HR
;
13246 inst
.instruction
= T_OPCODE_CMP_HR
;
13252 constraint (Rn
> 7,
13253 _("only lo regs allowed with immediate"));
13254 inst
.instruction
|= Rn
<< 8;
13255 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13266 top
= (inst
.instruction
& 0x00800000) != 0;
13267 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
13269 constraint (top
, _(":lower16: not allowed in this instruction"));
13270 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
13272 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
13274 constraint (!top
, _(":upper16: not allowed in this instruction"));
13275 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
13278 Rd
= inst
.operands
[0].reg
;
13279 reject_bad_reg (Rd
);
13281 inst
.instruction
|= Rd
<< 8;
13282 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
13284 imm
= inst
.relocs
[0].exp
.X_add_number
;
13285 inst
.instruction
|= (imm
& 0xf000) << 4;
13286 inst
.instruction
|= (imm
& 0x0800) << 15;
13287 inst
.instruction
|= (imm
& 0x0700) << 4;
13288 inst
.instruction
|= (imm
& 0x00ff);
13293 do_t_mvn_tst (void)
13297 Rn
= inst
.operands
[0].reg
;
13298 Rm
= inst
.operands
[1].reg
;
13300 if (inst
.instruction
== T_MNEM_cmp
13301 || inst
.instruction
== T_MNEM_cmn
)
13302 constraint (Rn
== REG_PC
, BAD_PC
);
13304 reject_bad_reg (Rn
);
13305 reject_bad_reg (Rm
);
13307 if (unified_syntax
)
13309 int r0off
= (inst
.instruction
== T_MNEM_mvn
13310 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
13311 bfd_boolean narrow
;
13313 if (inst
.size_req
== 4
13314 || inst
.instruction
> 0xffff
13315 || inst
.operands
[1].shifted
13316 || Rn
> 7 || Rm
> 7)
13318 else if (inst
.instruction
== T_MNEM_cmn
13319 || inst
.instruction
== T_MNEM_tst
)
13321 else if (THUMB_SETS_FLAGS (inst
.instruction
))
13322 narrow
= !in_pred_block ();
13324 narrow
= in_pred_block ();
13326 if (!inst
.operands
[1].isreg
)
13328 /* For an immediate, we always generate a 32-bit opcode;
13329 section relaxation will shrink it later if possible. */
13330 if (inst
.instruction
< 0xffff)
13331 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13332 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13333 inst
.instruction
|= Rn
<< r0off
;
13334 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13338 /* See if we can do this with a 16-bit instruction. */
13341 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13342 inst
.instruction
|= Rn
;
13343 inst
.instruction
|= Rm
<< 3;
13347 constraint (inst
.operands
[1].shifted
13348 && inst
.operands
[1].immisreg
,
13349 _("shift must be constant"));
13350 if (inst
.instruction
< 0xffff)
13351 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13352 inst
.instruction
|= Rn
<< r0off
;
13353 encode_thumb32_shifted_operand (1);
13359 constraint (inst
.instruction
> 0xffff
13360 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
13361 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
13362 _("unshifted register required"));
13363 constraint (Rn
> 7 || Rm
> 7,
13366 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13367 inst
.instruction
|= Rn
;
13368 inst
.instruction
|= Rm
<< 3;
13377 if (do_vfp_nsyn_mrs () == SUCCESS
)
13380 Rd
= inst
.operands
[0].reg
;
13381 reject_bad_reg (Rd
);
13382 inst
.instruction
|= Rd
<< 8;
13384 if (inst
.operands
[1].isreg
)
13386 unsigned br
= inst
.operands
[1].reg
;
13387 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13388 as_bad (_("bad register for mrs"));
13390 inst
.instruction
|= br
& (0xf << 16);
13391 inst
.instruction
|= (br
& 0x300) >> 4;
13392 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13396 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13398 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13400 /* PR gas/12698: The constraint is only applied for m_profile.
13401 If the user has specified -march=all, we want to ignore it as
13402 we are building for any CPU type, including non-m variants. */
13403 bfd_boolean m_profile
=
13404 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13405 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13406 "not support requested special purpose register"));
13409 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13411 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13412 _("'APSR', 'CPSR' or 'SPSR' expected"));
13414 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13415 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13416 inst
.instruction
|= 0xf0000;
13426 if (do_vfp_nsyn_msr () == SUCCESS
)
13429 constraint (!inst
.operands
[1].isreg
,
13430 _("Thumb encoding does not support an immediate here"));
13432 if (inst
.operands
[0].isreg
)
13433 flags
= (int)(inst
.operands
[0].reg
);
13435 flags
= inst
.operands
[0].imm
;
13437 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13439 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13441 /* PR gas/12698: The constraint is only applied for m_profile.
13442 If the user has specified -march=all, we want to ignore it as
13443 we are building for any CPU type, including non-m variants. */
13444 bfd_boolean m_profile
=
13445 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13446 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13447 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13448 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13449 && bits
!= PSR_f
)) && m_profile
,
13450 _("selected processor does not support requested special "
13451 "purpose register"));
13454 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13455 "requested special purpose register"));
13457 Rn
= inst
.operands
[1].reg
;
13458 reject_bad_reg (Rn
);
13460 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13461 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13462 inst
.instruction
|= (flags
& 0x300) >> 4;
13463 inst
.instruction
|= (flags
& 0xff);
13464 inst
.instruction
|= Rn
<< 16;
13470 bfd_boolean narrow
;
13471 unsigned Rd
, Rn
, Rm
;
13473 if (!inst
.operands
[2].present
)
13474 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13476 Rd
= inst
.operands
[0].reg
;
13477 Rn
= inst
.operands
[1].reg
;
13478 Rm
= inst
.operands
[2].reg
;
13480 if (unified_syntax
)
13482 if (inst
.size_req
== 4
13488 else if (inst
.instruction
== T_MNEM_muls
)
13489 narrow
= !in_pred_block ();
13491 narrow
= in_pred_block ();
13495 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13496 constraint (Rn
> 7 || Rm
> 7,
13503 /* 16-bit MULS/Conditional MUL. */
13504 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13505 inst
.instruction
|= Rd
;
13508 inst
.instruction
|= Rm
<< 3;
13510 inst
.instruction
|= Rn
<< 3;
13512 constraint (1, _("dest must overlap one source register"));
13516 constraint (inst
.instruction
!= T_MNEM_mul
,
13517 _("Thumb-2 MUL must not set flags"));
13519 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13520 inst
.instruction
|= Rd
<< 8;
13521 inst
.instruction
|= Rn
<< 16;
13522 inst
.instruction
|= Rm
<< 0;
13524 reject_bad_reg (Rd
);
13525 reject_bad_reg (Rn
);
13526 reject_bad_reg (Rm
);
13533 unsigned RdLo
, RdHi
, Rn
, Rm
;
13535 RdLo
= inst
.operands
[0].reg
;
13536 RdHi
= inst
.operands
[1].reg
;
13537 Rn
= inst
.operands
[2].reg
;
13538 Rm
= inst
.operands
[3].reg
;
13540 reject_bad_reg (RdLo
);
13541 reject_bad_reg (RdHi
);
13542 reject_bad_reg (Rn
);
13543 reject_bad_reg (Rm
);
13545 inst
.instruction
|= RdLo
<< 12;
13546 inst
.instruction
|= RdHi
<< 8;
13547 inst
.instruction
|= Rn
<< 16;
13548 inst
.instruction
|= Rm
;
13551 as_tsktsk (_("rdhi and rdlo must be different"));
13557 set_pred_insn_type (NEUTRAL_IT_INSN
);
13559 if (unified_syntax
)
13561 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13563 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13564 inst
.instruction
|= inst
.operands
[0].imm
;
13568 /* PR9722: Check for Thumb2 availability before
13569 generating a thumb2 nop instruction. */
13570 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13572 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13573 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13576 inst
.instruction
= 0x46c0;
13581 constraint (inst
.operands
[0].present
,
13582 _("Thumb does not support NOP with hints"));
13583 inst
.instruction
= 0x46c0;
13590 if (unified_syntax
)
13592 bfd_boolean narrow
;
13594 if (THUMB_SETS_FLAGS (inst
.instruction
))
13595 narrow
= !in_pred_block ();
13597 narrow
= in_pred_block ();
13598 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13600 if (inst
.size_req
== 4)
13605 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13606 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13607 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13611 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13612 inst
.instruction
|= inst
.operands
[0].reg
;
13613 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13618 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13620 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13622 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13623 inst
.instruction
|= inst
.operands
[0].reg
;
13624 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13633 Rd
= inst
.operands
[0].reg
;
13634 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13636 reject_bad_reg (Rd
);
13637 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13638 reject_bad_reg (Rn
);
13640 inst
.instruction
|= Rd
<< 8;
13641 inst
.instruction
|= Rn
<< 16;
13643 if (!inst
.operands
[2].isreg
)
13645 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13646 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13652 Rm
= inst
.operands
[2].reg
;
13653 reject_bad_reg (Rm
);
13655 constraint (inst
.operands
[2].shifted
13656 && inst
.operands
[2].immisreg
,
13657 _("shift must be constant"));
13658 encode_thumb32_shifted_operand (2);
13665 unsigned Rd
, Rn
, Rm
;
13667 Rd
= inst
.operands
[0].reg
;
13668 Rn
= inst
.operands
[1].reg
;
13669 Rm
= inst
.operands
[2].reg
;
13671 reject_bad_reg (Rd
);
13672 reject_bad_reg (Rn
);
13673 reject_bad_reg (Rm
);
13675 inst
.instruction
|= Rd
<< 8;
13676 inst
.instruction
|= Rn
<< 16;
13677 inst
.instruction
|= Rm
;
13678 if (inst
.operands
[3].present
)
13680 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13681 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13682 _("expression too complex"));
13683 inst
.instruction
|= (val
& 0x1c) << 10;
13684 inst
.instruction
|= (val
& 0x03) << 6;
13691 if (!inst
.operands
[3].present
)
13695 inst
.instruction
&= ~0x00000020;
13697 /* PR 10168. Swap the Rm and Rn registers. */
13698 Rtmp
= inst
.operands
[1].reg
;
13699 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13700 inst
.operands
[2].reg
= Rtmp
;
13708 if (inst
.operands
[0].immisreg
)
13709 reject_bad_reg (inst
.operands
[0].imm
);
13711 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13715 do_t_push_pop (void)
13719 constraint (inst
.operands
[0].writeback
,
13720 _("push/pop do not support {reglist}^"));
13721 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13722 _("expression too complex"));
13724 mask
= inst
.operands
[0].imm
;
13725 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13726 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13727 else if (inst
.size_req
!= 4
13728 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13729 ? REG_LR
: REG_PC
)))
13731 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13732 inst
.instruction
|= THUMB_PP_PC_LR
;
13733 inst
.instruction
|= mask
& 0xff;
13735 else if (unified_syntax
)
13737 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13738 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13742 inst
.error
= _("invalid register list to push/pop instruction");
13750 if (unified_syntax
)
13751 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13754 inst
.error
= _("invalid register list to push/pop instruction");
13760 do_t_vscclrm (void)
13762 if (inst
.operands
[0].issingle
)
13764 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13765 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13766 inst
.instruction
|= inst
.operands
[0].imm
;
13770 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13771 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13772 inst
.instruction
|= 1 << 8;
13773 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13782 Rd
= inst
.operands
[0].reg
;
13783 Rm
= inst
.operands
[1].reg
;
13785 reject_bad_reg (Rd
);
13786 reject_bad_reg (Rm
);
13788 inst
.instruction
|= Rd
<< 8;
13789 inst
.instruction
|= Rm
<< 16;
13790 inst
.instruction
|= Rm
;
13798 Rd
= inst
.operands
[0].reg
;
13799 Rm
= inst
.operands
[1].reg
;
13801 reject_bad_reg (Rd
);
13802 reject_bad_reg (Rm
);
13804 if (Rd
<= 7 && Rm
<= 7
13805 && inst
.size_req
!= 4)
13807 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13808 inst
.instruction
|= Rd
;
13809 inst
.instruction
|= Rm
<< 3;
13811 else if (unified_syntax
)
13813 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13814 inst
.instruction
|= Rd
<< 8;
13815 inst
.instruction
|= Rm
<< 16;
13816 inst
.instruction
|= Rm
;
13819 inst
.error
= BAD_HIREG
;
13827 Rd
= inst
.operands
[0].reg
;
13828 Rm
= inst
.operands
[1].reg
;
13830 reject_bad_reg (Rd
);
13831 reject_bad_reg (Rm
);
13833 inst
.instruction
|= Rd
<< 8;
13834 inst
.instruction
|= Rm
;
13842 Rd
= inst
.operands
[0].reg
;
13843 Rs
= (inst
.operands
[1].present
13844 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13845 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13847 reject_bad_reg (Rd
);
13848 reject_bad_reg (Rs
);
13849 if (inst
.operands
[2].isreg
)
13850 reject_bad_reg (inst
.operands
[2].reg
);
13852 inst
.instruction
|= Rd
<< 8;
13853 inst
.instruction
|= Rs
<< 16;
13854 if (!inst
.operands
[2].isreg
)
13856 bfd_boolean narrow
;
13858 if ((inst
.instruction
& 0x00100000) != 0)
13859 narrow
= !in_pred_block ();
13861 narrow
= in_pred_block ();
13863 if (Rd
> 7 || Rs
> 7)
13866 if (inst
.size_req
== 4 || !unified_syntax
)
13869 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13870 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13873 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13874 relaxation, but it doesn't seem worth the hassle. */
13877 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13878 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13879 inst
.instruction
|= Rs
<< 3;
13880 inst
.instruction
|= Rd
;
13884 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13885 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13889 encode_thumb32_shifted_operand (2);
13895 if (warn_on_deprecated
13896 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13897 as_tsktsk (_("setend use is deprecated for ARMv8"));
13899 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13900 if (inst
.operands
[0].imm
)
13901 inst
.instruction
|= 0x8;
13907 if (!inst
.operands
[1].present
)
13908 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13910 if (unified_syntax
)
13912 bfd_boolean narrow
;
13915 switch (inst
.instruction
)
13918 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13920 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13922 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13924 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13928 if (THUMB_SETS_FLAGS (inst
.instruction
))
13929 narrow
= !in_pred_block ();
13931 narrow
= in_pred_block ();
13932 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13934 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13936 if (inst
.operands
[2].isreg
13937 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13938 || inst
.operands
[2].reg
> 7))
13940 if (inst
.size_req
== 4)
13943 reject_bad_reg (inst
.operands
[0].reg
);
13944 reject_bad_reg (inst
.operands
[1].reg
);
13948 if (inst
.operands
[2].isreg
)
13950 reject_bad_reg (inst
.operands
[2].reg
);
13951 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13952 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13953 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13954 inst
.instruction
|= inst
.operands
[2].reg
;
13956 /* PR 12854: Error on extraneous shifts. */
13957 constraint (inst
.operands
[2].shifted
,
13958 _("extraneous shift as part of operand to shift insn"));
13962 inst
.operands
[1].shifted
= 1;
13963 inst
.operands
[1].shift_kind
= shift_kind
;
13964 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13965 ? T_MNEM_movs
: T_MNEM_mov
);
13966 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13967 encode_thumb32_shifted_operand (1);
13968 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13969 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13974 if (inst
.operands
[2].isreg
)
13976 switch (shift_kind
)
13978 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13979 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13980 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13981 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13985 inst
.instruction
|= inst
.operands
[0].reg
;
13986 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13988 /* PR 12854: Error on extraneous shifts. */
13989 constraint (inst
.operands
[2].shifted
,
13990 _("extraneous shift as part of operand to shift insn"));
13994 switch (shift_kind
)
13996 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13997 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13998 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
14001 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
14002 inst
.instruction
|= inst
.operands
[0].reg
;
14003 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
14009 constraint (inst
.operands
[0].reg
> 7
14010 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
14011 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
14013 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
14015 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
14016 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14017 _("source1 and dest must be same register"));
14019 switch (inst
.instruction
)
14021 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
14022 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
14023 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
14024 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
14028 inst
.instruction
|= inst
.operands
[0].reg
;
14029 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
14031 /* PR 12854: Error on extraneous shifts. */
14032 constraint (inst
.operands
[2].shifted
,
14033 _("extraneous shift as part of operand to shift insn"));
14037 switch (inst
.instruction
)
14039 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
14040 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
14041 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
14042 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
14045 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
14046 inst
.instruction
|= inst
.operands
[0].reg
;
14047 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
14055 unsigned Rd
, Rn
, Rm
;
14057 Rd
= inst
.operands
[0].reg
;
14058 Rn
= inst
.operands
[1].reg
;
14059 Rm
= inst
.operands
[2].reg
;
14061 reject_bad_reg (Rd
);
14062 reject_bad_reg (Rn
);
14063 reject_bad_reg (Rm
);
14065 inst
.instruction
|= Rd
<< 8;
14066 inst
.instruction
|= Rn
<< 16;
14067 inst
.instruction
|= Rm
;
14073 unsigned Rd
, Rn
, Rm
;
14075 Rd
= inst
.operands
[0].reg
;
14076 Rm
= inst
.operands
[1].reg
;
14077 Rn
= inst
.operands
[2].reg
;
14079 reject_bad_reg (Rd
);
14080 reject_bad_reg (Rn
);
14081 reject_bad_reg (Rm
);
14083 inst
.instruction
|= Rd
<< 8;
14084 inst
.instruction
|= Rn
<< 16;
14085 inst
.instruction
|= Rm
;
14091 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
14092 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
14093 _("SMC is not permitted on this architecture"));
14094 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14095 _("expression too complex"));
14096 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
14098 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14099 inst
.instruction
|= (value
& 0x000f) << 16;
14101 /* PR gas/15623: SMC instructions must be last in an IT block. */
14102 set_pred_insn_type_last ();
14108 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
14110 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14111 inst
.instruction
|= (value
& 0x0fff);
14112 inst
.instruction
|= (value
& 0xf000) << 4;
14116 do_t_ssat_usat (int bias
)
14120 Rd
= inst
.operands
[0].reg
;
14121 Rn
= inst
.operands
[2].reg
;
14123 reject_bad_reg (Rd
);
14124 reject_bad_reg (Rn
);
14126 inst
.instruction
|= Rd
<< 8;
14127 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
14128 inst
.instruction
|= Rn
<< 16;
14130 if (inst
.operands
[3].present
)
14132 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
14134 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14136 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14137 _("expression too complex"));
14139 if (shift_amount
!= 0)
14141 constraint (shift_amount
> 31,
14142 _("shift expression is too large"));
14144 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
14145 inst
.instruction
|= 0x00200000; /* sh bit. */
14147 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
14148 inst
.instruction
|= (shift_amount
& 0x03) << 6;
14156 do_t_ssat_usat (1);
14164 Rd
= inst
.operands
[0].reg
;
14165 Rn
= inst
.operands
[2].reg
;
14167 reject_bad_reg (Rd
);
14168 reject_bad_reg (Rn
);
14170 inst
.instruction
|= Rd
<< 8;
14171 inst
.instruction
|= inst
.operands
[1].imm
- 1;
14172 inst
.instruction
|= Rn
<< 16;
14178 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
14179 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
14180 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
14181 || inst
.operands
[2].negative
,
14184 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
14186 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
14187 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14188 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14189 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
14195 if (!inst
.operands
[2].present
)
14196 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
14198 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
14199 || inst
.operands
[0].reg
== inst
.operands
[2].reg
14200 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
14203 inst
.instruction
|= inst
.operands
[0].reg
;
14204 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14205 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
14206 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
14212 unsigned Rd
, Rn
, Rm
;
14214 Rd
= inst
.operands
[0].reg
;
14215 Rn
= inst
.operands
[1].reg
;
14216 Rm
= inst
.operands
[2].reg
;
14218 reject_bad_reg (Rd
);
14219 reject_bad_reg (Rn
);
14220 reject_bad_reg (Rm
);
14222 inst
.instruction
|= Rd
<< 8;
14223 inst
.instruction
|= Rn
<< 16;
14224 inst
.instruction
|= Rm
;
14225 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
14233 Rd
= inst
.operands
[0].reg
;
14234 Rm
= inst
.operands
[1].reg
;
14236 reject_bad_reg (Rd
);
14237 reject_bad_reg (Rm
);
14239 if (inst
.instruction
<= 0xffff
14240 && inst
.size_req
!= 4
14241 && Rd
<= 7 && Rm
<= 7
14242 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
14244 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14245 inst
.instruction
|= Rd
;
14246 inst
.instruction
|= Rm
<< 3;
14248 else if (unified_syntax
)
14250 if (inst
.instruction
<= 0xffff)
14251 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14252 inst
.instruction
|= Rd
<< 8;
14253 inst
.instruction
|= Rm
;
14254 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
14258 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
14259 _("Thumb encoding does not support rotation"));
14260 constraint (1, BAD_HIREG
);
14267 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
14276 half
= (inst
.instruction
& 0x10) != 0;
14277 set_pred_insn_type_last ();
14278 constraint (inst
.operands
[0].immisreg
,
14279 _("instruction requires register index"));
14281 Rn
= inst
.operands
[0].reg
;
14282 Rm
= inst
.operands
[0].imm
;
14284 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
14285 constraint (Rn
== REG_SP
, BAD_SP
);
14286 reject_bad_reg (Rm
);
14288 constraint (!half
&& inst
.operands
[0].shifted
,
14289 _("instruction does not allow shifted index"));
14290 inst
.instruction
|= (Rn
<< 16) | Rm
;
14296 if (!inst
.operands
[0].present
)
14297 inst
.operands
[0].imm
= 0;
14299 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
14301 constraint (inst
.size_req
== 2,
14302 _("immediate value out of range"));
14303 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14304 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
14305 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
14309 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14310 inst
.instruction
|= inst
.operands
[0].imm
;
14313 set_pred_insn_type (NEUTRAL_IT_INSN
);
14320 do_t_ssat_usat (0);
14328 Rd
= inst
.operands
[0].reg
;
14329 Rn
= inst
.operands
[2].reg
;
14331 reject_bad_reg (Rd
);
14332 reject_bad_reg (Rn
);
14334 inst
.instruction
|= Rd
<< 8;
14335 inst
.instruction
|= inst
.operands
[1].imm
;
14336 inst
.instruction
|= Rn
<< 16;
14339 /* Checking the range of the branch offset (VAL) with NBITS bits
14340 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14342 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
14344 gas_assert (nbits
> 0 && nbits
<= 32);
14347 int cmp
= (1 << (nbits
- 1));
14348 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
14353 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
14359 /* For branches in Armv8.1-M Mainline. */
14361 do_t_branch_future (void)
14363 unsigned long insn
= inst
.instruction
;
14365 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14366 if (inst
.operands
[0].hasreloc
== 0)
14368 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
14369 as_bad (BAD_BRANCH_OFF
);
14371 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
14375 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
14376 inst
.relocs
[0].pc_rel
= 1;
14382 if (inst
.operands
[1].hasreloc
== 0)
14384 int val
= inst
.operands
[1].imm
;
14385 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
14386 as_bad (BAD_BRANCH_OFF
);
14388 int immA
= (val
& 0x0001f000) >> 12;
14389 int immB
= (val
& 0x00000ffc) >> 2;
14390 int immC
= (val
& 0x00000002) >> 1;
14391 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14395 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14396 inst
.relocs
[1].pc_rel
= 1;
14401 if (inst
.operands
[1].hasreloc
== 0)
14403 int val
= inst
.operands
[1].imm
;
14404 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14405 as_bad (BAD_BRANCH_OFF
);
14407 int immA
= (val
& 0x0007f000) >> 12;
14408 int immB
= (val
& 0x00000ffc) >> 2;
14409 int immC
= (val
& 0x00000002) >> 1;
14410 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14414 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14415 inst
.relocs
[1].pc_rel
= 1;
14419 case T_MNEM_bfcsel
:
14421 if (inst
.operands
[1].hasreloc
== 0)
14423 int val
= inst
.operands
[1].imm
;
14424 int immA
= (val
& 0x00001000) >> 12;
14425 int immB
= (val
& 0x00000ffc) >> 2;
14426 int immC
= (val
& 0x00000002) >> 1;
14427 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14431 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14432 inst
.relocs
[1].pc_rel
= 1;
14436 if (inst
.operands
[2].hasreloc
== 0)
14438 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14439 int val2
= inst
.operands
[2].imm
;
14440 int val0
= inst
.operands
[0].imm
& 0x1f;
14441 int diff
= val2
- val0
;
14443 inst
.instruction
|= 1 << 17; /* T bit. */
14444 else if (diff
!= 2)
14445 as_bad (_("out of range label-relative fixup value"));
14449 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14450 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14451 inst
.relocs
[2].pc_rel
= 1;
14455 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14456 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14461 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14468 /* Helper function for do_t_loloop to handle relocations. */
14470 v8_1_loop_reloc (int is_le
)
14472 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14474 int value
= inst
.relocs
[0].exp
.X_add_number
;
14475 value
= (is_le
) ? -value
: value
;
14477 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14478 as_bad (BAD_BRANCH_OFF
);
14482 immh
= (value
& 0x00000ffc) >> 2;
14483 imml
= (value
& 0x00000002) >> 1;
14485 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14489 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14490 inst
.relocs
[0].pc_rel
= 1;
14494 /* For shifts with four operands in MVE. */
14496 do_mve_scalar_shift1 (void)
14498 unsigned int value
= inst
.operands
[2].imm
;
14500 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14501 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14503 /* Setting the bit for saturation. */
14504 inst
.instruction
|= ((value
== 64) ? 0: 1) << 7;
14506 /* Assuming Rm is already checked not to be 11x1. */
14507 constraint (inst
.operands
[3].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14508 constraint (inst
.operands
[3].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14509 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
14512 /* For shifts in MVE. */
14514 do_mve_scalar_shift (void)
14516 if (!inst
.operands
[2].present
)
14518 inst
.operands
[2] = inst
.operands
[1];
14519 inst
.operands
[1].reg
= 0xf;
14522 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14523 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14525 if (inst
.operands
[2].isreg
)
14527 /* Assuming Rm is already checked not to be 11x1. */
14528 constraint (inst
.operands
[2].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14529 constraint (inst
.operands
[2].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14530 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
14534 /* Assuming imm is already checked as [1,32]. */
14535 unsigned int value
= inst
.operands
[2].imm
;
14536 inst
.instruction
|= (value
& 0x1c) << 10;
14537 inst
.instruction
|= (value
& 0x03) << 6;
14538 /* Change last 4 bits from 0xd to 0xf. */
14539 inst
.instruction
|= 0x2;
14543 /* MVE instruction encoder helpers. */
14544 #define M_MNEM_vabav 0xee800f01
14545 #define M_MNEM_vmladav 0xeef00e00
14546 #define M_MNEM_vmladava 0xeef00e20
14547 #define M_MNEM_vmladavx 0xeef01e00
14548 #define M_MNEM_vmladavax 0xeef01e20
14549 #define M_MNEM_vmlsdav 0xeef00e01
14550 #define M_MNEM_vmlsdava 0xeef00e21
14551 #define M_MNEM_vmlsdavx 0xeef01e01
14552 #define M_MNEM_vmlsdavax 0xeef01e21
14553 #define M_MNEM_vmullt 0xee011e00
14554 #define M_MNEM_vmullb 0xee010e00
14555 #define M_MNEM_vctp 0xf000e801
14556 #define M_MNEM_vst20 0xfc801e00
14557 #define M_MNEM_vst21 0xfc801e20
14558 #define M_MNEM_vst40 0xfc801e01
14559 #define M_MNEM_vst41 0xfc801e21
14560 #define M_MNEM_vst42 0xfc801e41
14561 #define M_MNEM_vst43 0xfc801e61
14562 #define M_MNEM_vld20 0xfc901e00
14563 #define M_MNEM_vld21 0xfc901e20
14564 #define M_MNEM_vld40 0xfc901e01
14565 #define M_MNEM_vld41 0xfc901e21
14566 #define M_MNEM_vld42 0xfc901e41
14567 #define M_MNEM_vld43 0xfc901e61
14568 #define M_MNEM_vstrb 0xec000e00
14569 #define M_MNEM_vstrh 0xec000e10
14570 #define M_MNEM_vstrw 0xec000e40
14571 #define M_MNEM_vstrd 0xec000e50
14572 #define M_MNEM_vldrb 0xec100e00
14573 #define M_MNEM_vldrh 0xec100e10
14574 #define M_MNEM_vldrw 0xec100e40
14575 #define M_MNEM_vldrd 0xec100e50
14576 #define M_MNEM_vmovlt 0xeea01f40
14577 #define M_MNEM_vmovlb 0xeea00f40
14578 #define M_MNEM_vmovnt 0xfe311e81
14579 #define M_MNEM_vmovnb 0xfe310e81
14580 #define M_MNEM_vadc 0xee300f00
14581 #define M_MNEM_vadci 0xee301f00
14582 #define M_MNEM_vbrsr 0xfe011e60
14583 #define M_MNEM_vaddlv 0xee890f00
14584 #define M_MNEM_vaddlva 0xee890f20
14585 #define M_MNEM_vaddv 0xeef10f00
14586 #define M_MNEM_vaddva 0xeef10f20
14587 #define M_MNEM_vddup 0xee011f6e
14588 #define M_MNEM_vdwdup 0xee011f60
14589 #define M_MNEM_vidup 0xee010f6e
14590 #define M_MNEM_viwdup 0xee010f60
14591 #define M_MNEM_vmaxv 0xeee20f00
14592 #define M_MNEM_vmaxav 0xeee00f00
14593 #define M_MNEM_vminv 0xeee20f80
14594 #define M_MNEM_vminav 0xeee00f80
14595 #define M_MNEM_vmlaldav 0xee800e00
14596 #define M_MNEM_vmlaldava 0xee800e20
14597 #define M_MNEM_vmlaldavx 0xee801e00
14598 #define M_MNEM_vmlaldavax 0xee801e20
14599 #define M_MNEM_vmlsldav 0xee800e01
14600 #define M_MNEM_vmlsldava 0xee800e21
14601 #define M_MNEM_vmlsldavx 0xee801e01
14602 #define M_MNEM_vmlsldavax 0xee801e21
14603 #define M_MNEM_vrmlaldavhx 0xee801f00
14604 #define M_MNEM_vrmlaldavhax 0xee801f20
14605 #define M_MNEM_vrmlsldavh 0xfe800e01
14606 #define M_MNEM_vrmlsldavha 0xfe800e21
14607 #define M_MNEM_vrmlsldavhx 0xfe801e01
14608 #define M_MNEM_vrmlsldavhax 0xfe801e21
14609 #define M_MNEM_vqmovnt 0xee331e01
14610 #define M_MNEM_vqmovnb 0xee330e01
14611 #define M_MNEM_vqmovunt 0xee311e81
14612 #define M_MNEM_vqmovunb 0xee310e81
14613 #define M_MNEM_vshrnt 0xee801fc1
14614 #define M_MNEM_vshrnb 0xee800fc1
14615 #define M_MNEM_vrshrnt 0xfe801fc1
14616 #define M_MNEM_vqshrnt 0xee801f40
14617 #define M_MNEM_vqshrnb 0xee800f40
14618 #define M_MNEM_vqshrunt 0xee801fc0
14619 #define M_MNEM_vqshrunb 0xee800fc0
14620 #define M_MNEM_vrshrnb 0xfe800fc1
14621 #define M_MNEM_vqrshrnt 0xee801f41
14622 #define M_MNEM_vqrshrnb 0xee800f41
14623 #define M_MNEM_vqrshrunt 0xfe801fc0
14624 #define M_MNEM_vqrshrunb 0xfe800fc0
14626 /* Bfloat16 instruction encoder helpers. */
14627 #define B_MNEM_vfmat 0xfc300850
14628 #define B_MNEM_vfmab 0xfc300810
14630 /* Neon instruction encoder helpers. */
14632 /* Encodings for the different types for various Neon opcodes. */
14634 /* An "invalid" code for the following tables. */
14637 struct neon_tab_entry
14640 unsigned float_or_poly
;
14641 unsigned scalar_or_imm
;
14644 /* Map overloaded Neon opcodes to their respective encodings. */
14645 #define NEON_ENC_TAB \
14646 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14647 X(vabdl, 0x0800700, N_INV, N_INV), \
14648 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14649 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14650 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14651 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14652 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14653 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14654 X(vaddl, 0x0800000, N_INV, N_INV), \
14655 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14656 X(vsubl, 0x0800200, N_INV, N_INV), \
14657 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14658 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14659 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14660 /* Register variants of the following two instructions are encoded as
14661 vcge / vcgt with the operands reversed. */ \
14662 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14663 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14664 X(vfma, N_INV, 0x0000c10, N_INV), \
14665 X(vfms, N_INV, 0x0200c10, N_INV), \
14666 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14667 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14668 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14669 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14670 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14671 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14672 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14673 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14674 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14675 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14676 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14677 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14678 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14679 X(vshl, 0x0000400, N_INV, 0x0800510), \
14680 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14681 X(vand, 0x0000110, N_INV, 0x0800030), \
14682 X(vbic, 0x0100110, N_INV, 0x0800030), \
14683 X(veor, 0x1000110, N_INV, N_INV), \
14684 X(vorn, 0x0300110, N_INV, 0x0800010), \
14685 X(vorr, 0x0200110, N_INV, 0x0800010), \
14686 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14687 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14688 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14689 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14690 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14691 X(vst1, 0x0000000, 0x0800000, N_INV), \
14692 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14693 X(vst2, 0x0000100, 0x0800100, N_INV), \
14694 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14695 X(vst3, 0x0000200, 0x0800200, N_INV), \
14696 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14697 X(vst4, 0x0000300, 0x0800300, N_INV), \
14698 X(vmovn, 0x1b20200, N_INV, N_INV), \
14699 X(vtrn, 0x1b20080, N_INV, N_INV), \
14700 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14701 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14702 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14703 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14704 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14705 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14706 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14707 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14708 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14709 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14710 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14711 X(vseleq, 0xe000a00, N_INV, N_INV), \
14712 X(vselvs, 0xe100a00, N_INV, N_INV), \
14713 X(vselge, 0xe200a00, N_INV, N_INV), \
14714 X(vselgt, 0xe300a00, N_INV, N_INV), \
14715 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14716 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14717 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14718 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14719 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14720 X(aes, 0x3b00300, N_INV, N_INV), \
14721 X(sha3op, 0x2000c00, N_INV, N_INV), \
14722 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14723 X(sha2op, 0x3ba0380, N_INV, N_INV)
14727 #define X(OPC,I,F,S) N_MNEM_##OPC
14732 static const struct neon_tab_entry neon_enc_tab
[] =
14734 #define X(OPC,I,F,S) { (I), (F), (S) }
14739 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14740 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14741 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14742 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14743 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14744 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14745 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14746 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14747 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14748 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14749 #define NEON_ENC_SINGLE_(X) \
14750 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14751 #define NEON_ENC_DOUBLE_(X) \
14752 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14753 #define NEON_ENC_FPV8_(X) \
14754 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14756 #define NEON_ENCODE(type, inst) \
14759 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14760 inst.is_neon = 1; \
14764 #define check_neon_suffixes \
14767 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14769 as_bad (_("invalid neon suffix for non neon instruction")); \
14775 /* Define shapes for instruction operands. The following mnemonic characters
14776 are used in this table:
14778 F - VFP S<n> register
14779 D - Neon D<n> register
14780 Q - Neon Q<n> register
14784 L - D<n> register list
14786 This table is used to generate various data:
14787 - enumerations of the form NS_DDR to be used as arguments to
14789 - a table classifying shapes into single, double, quad, mixed.
14790 - a table used to drive neon_select_shape. */
14792 #define NEON_SHAPE_DEF \
14793 X(4, (R, R, Q, Q), QUAD), \
14794 X(4, (Q, R, R, I), QUAD), \
14795 X(4, (R, R, S, S), QUAD), \
14796 X(4, (S, S, R, R), QUAD), \
14797 X(3, (Q, R, I), QUAD), \
14798 X(3, (I, Q, Q), QUAD), \
14799 X(3, (I, Q, R), QUAD), \
14800 X(3, (R, Q, Q), QUAD), \
14801 X(3, (D, D, D), DOUBLE), \
14802 X(3, (Q, Q, Q), QUAD), \
14803 X(3, (D, D, I), DOUBLE), \
14804 X(3, (Q, Q, I), QUAD), \
14805 X(3, (D, D, S), DOUBLE), \
14806 X(3, (Q, Q, S), QUAD), \
14807 X(3, (Q, Q, R), QUAD), \
14808 X(3, (R, R, Q), QUAD), \
14809 X(2, (R, Q), QUAD), \
14810 X(2, (D, D), DOUBLE), \
14811 X(2, (Q, Q), QUAD), \
14812 X(2, (D, S), DOUBLE), \
14813 X(2, (Q, S), QUAD), \
14814 X(2, (D, R), DOUBLE), \
14815 X(2, (Q, R), QUAD), \
14816 X(2, (D, I), DOUBLE), \
14817 X(2, (Q, I), QUAD), \
14818 X(3, (P, F, I), SINGLE), \
14819 X(3, (P, D, I), DOUBLE), \
14820 X(3, (P, Q, I), QUAD), \
14821 X(4, (P, F, F, I), SINGLE), \
14822 X(4, (P, D, D, I), DOUBLE), \
14823 X(4, (P, Q, Q, I), QUAD), \
14824 X(5, (P, F, F, F, I), SINGLE), \
14825 X(5, (P, D, D, D, I), DOUBLE), \
14826 X(5, (P, Q, Q, Q, I), QUAD), \
14827 X(3, (D, L, D), DOUBLE), \
14828 X(2, (D, Q), MIXED), \
14829 X(2, (Q, D), MIXED), \
14830 X(3, (D, Q, I), MIXED), \
14831 X(3, (Q, D, I), MIXED), \
14832 X(3, (Q, D, D), MIXED), \
14833 X(3, (D, Q, Q), MIXED), \
14834 X(3, (Q, Q, D), MIXED), \
14835 X(3, (Q, D, S), MIXED), \
14836 X(3, (D, Q, S), MIXED), \
14837 X(4, (D, D, D, I), DOUBLE), \
14838 X(4, (Q, Q, Q, I), QUAD), \
14839 X(4, (D, D, S, I), DOUBLE), \
14840 X(4, (Q, Q, S, I), QUAD), \
14841 X(2, (F, F), SINGLE), \
14842 X(3, (F, F, F), SINGLE), \
14843 X(2, (F, I), SINGLE), \
14844 X(2, (F, D), MIXED), \
14845 X(2, (D, F), MIXED), \
14846 X(3, (F, F, I), MIXED), \
14847 X(4, (R, R, F, F), SINGLE), \
14848 X(4, (F, F, R, R), SINGLE), \
14849 X(3, (D, R, R), DOUBLE), \
14850 X(3, (R, R, D), DOUBLE), \
14851 X(2, (S, R), SINGLE), \
14852 X(2, (R, S), SINGLE), \
14853 X(2, (F, R), SINGLE), \
14854 X(2, (R, F), SINGLE), \
14855 /* Used for MVE tail predicated loop instructions. */\
14856 X(2, (R, R), QUAD), \
14857 /* Half float shape supported so far. */\
14858 X (2, (H, D), MIXED), \
14859 X (2, (D, H), MIXED), \
14860 X (2, (H, F), MIXED), \
14861 X (2, (F, H), MIXED), \
14862 X (2, (H, H), HALF), \
14863 X (2, (H, R), HALF), \
14864 X (2, (R, H), HALF), \
14865 X (2, (H, I), HALF), \
14866 X (3, (H, H, H), HALF), \
14867 X (3, (H, F, I), MIXED), \
14868 X (3, (F, H, I), MIXED), \
14869 X (3, (D, H, H), MIXED), \
14870 X (3, (D, H, S), MIXED)
14872 #define S2(A,B) NS_##A##B
14873 #define S3(A,B,C) NS_##A##B##C
14874 #define S4(A,B,C,D) NS_##A##B##C##D
14875 #define S5(A,B,C,D,E) NS_##A##B##C##D##E
14877 #define X(N, L, C) S##N L
14891 enum neon_shape_class
14900 #define X(N, L, C) SC_##C
14902 static enum neon_shape_class neon_shape_class
[] =
14922 /* Register widths of above. */
14923 static unsigned neon_shape_el_size
[] =
14936 struct neon_shape_info
14939 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14942 #define S2(A,B) { SE_##A, SE_##B }
14943 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14944 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14945 #define S5(A,B,C,D,E) { SE_##A, SE_##B, SE_##C, SE_##D, SE_##E }
14947 #define X(N, L, C) { N, S##N L }
14949 static struct neon_shape_info neon_shape_tab
[] =
14960 /* Bit masks used in type checking given instructions.
14961 'N_EQK' means the type must be the same as (or based on in some way) the key
14962 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14963 set, various other bits can be set as well in order to modify the meaning of
14964 the type constraint. */
14966 enum neon_type_mask
14990 N_BF16
= 0x0400000,
14991 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14992 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14993 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14994 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14995 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14996 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14997 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14998 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14999 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
15000 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
15001 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
15003 N_MAX_NONSPECIAL
= N_P64
15006 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
15008 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
15009 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
15010 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
15011 #define N_S_32 (N_S8 | N_S16 | N_S32)
15012 #define N_F_16_32 (N_F16 | N_F32)
15013 #define N_SUF_32 (N_SU_32 | N_F_16_32)
15014 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
15015 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
15016 #define N_F_ALL (N_F16 | N_F32 | N_F64)
15017 #define N_I_MVE (N_I8 | N_I16 | N_I32)
15018 #define N_F_MVE (N_F16 | N_F32)
15019 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
15021 /* Pass this as the first type argument to neon_check_type to ignore types
15023 #define N_IGNORE_TYPE (N_KEY | N_EQK)
15025 /* Select a "shape" for the current instruction (describing register types or
15026 sizes) from a list of alternatives. Return NS_NULL if the current instruction
15027 doesn't fit. For non-polymorphic shapes, checking is usually done as a
15028 function of operand parsing, so this function doesn't need to be called.
15029 Shapes should be listed in order of decreasing length. */
15031 static enum neon_shape
15032 neon_select_shape (enum neon_shape shape
, ...)
15035 enum neon_shape first_shape
= shape
;
15037 /* Fix missing optional operands. FIXME: we don't know at this point how
15038 many arguments we should have, so this makes the assumption that we have
15039 > 1. This is true of all current Neon opcodes, I think, but may not be
15040 true in the future. */
15041 if (!inst
.operands
[1].present
)
15042 inst
.operands
[1] = inst
.operands
[0];
15044 va_start (ap
, shape
);
15046 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
15051 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
15053 if (!inst
.operands
[j
].present
)
15059 switch (neon_shape_tab
[shape
].el
[j
])
15061 /* If a .f16, .16, .u16, .s16 type specifier is given over
15062 a VFP single precision register operand, it's essentially
15063 means only half of the register is used.
15065 If the type specifier is given after the mnemonics, the
15066 information is stored in inst.vectype. If the type specifier
15067 is given after register operand, the information is stored
15068 in inst.operands[].vectype.
15070 When there is only one type specifier, and all the register
15071 operands are the same type of hardware register, the type
15072 specifier applies to all register operands.
15074 If no type specifier is given, the shape is inferred from
15075 operand information.
15078 vadd.f16 s0, s1, s2: NS_HHH
15079 vabs.f16 s0, s1: NS_HH
15080 vmov.f16 s0, r1: NS_HR
15081 vmov.f16 r0, s1: NS_RH
15082 vcvt.f16 r0, s1: NS_RH
15083 vcvt.f16.s32 s2, s2, #29: NS_HFI
15084 vcvt.f16.s32 s2, s2: NS_HF
15087 if (!(inst
.operands
[j
].isreg
15088 && inst
.operands
[j
].isvec
15089 && inst
.operands
[j
].issingle
15090 && !inst
.operands
[j
].isquad
15091 && ((inst
.vectype
.elems
== 1
15092 && inst
.vectype
.el
[0].size
== 16)
15093 || (inst
.vectype
.elems
> 1
15094 && inst
.vectype
.el
[j
].size
== 16)
15095 || (inst
.vectype
.elems
== 0
15096 && inst
.operands
[j
].vectype
.type
!= NT_invtype
15097 && inst
.operands
[j
].vectype
.size
== 16))))
15102 if (!(inst
.operands
[j
].isreg
15103 && inst
.operands
[j
].isvec
15104 && inst
.operands
[j
].issingle
15105 && !inst
.operands
[j
].isquad
15106 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
15107 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
15108 || (inst
.vectype
.elems
== 0
15109 && (inst
.operands
[j
].vectype
.size
== 32
15110 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
15115 if (!(inst
.operands
[j
].isreg
15116 && inst
.operands
[j
].isvec
15117 && !inst
.operands
[j
].isquad
15118 && !inst
.operands
[j
].issingle
))
15123 if (!(inst
.operands
[j
].isreg
15124 && !inst
.operands
[j
].isvec
))
15129 if (!(inst
.operands
[j
].isreg
15130 && inst
.operands
[j
].isvec
15131 && inst
.operands
[j
].isquad
15132 && !inst
.operands
[j
].issingle
))
15137 if (!(!inst
.operands
[j
].isreg
15138 && !inst
.operands
[j
].isscalar
))
15143 if (!(!inst
.operands
[j
].isreg
15144 && inst
.operands
[j
].isscalar
))
15155 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
15156 /* We've matched all the entries in the shape table, and we don't
15157 have any left over operands which have not been matched. */
15163 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
15164 first_error (_("invalid instruction shape"));
15169 /* True if SHAPE is predominantly a quadword operation (most of the time, this
15170 means the Q bit should be set). */
15173 neon_quad (enum neon_shape shape
)
15175 return neon_shape_class
[shape
] == SC_QUAD
;
15179 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
15182 /* Allow modification to be made to types which are constrained to be
15183 based on the key element, based on bits set alongside N_EQK. */
15184 if ((typebits
& N_EQK
) != 0)
15186 if ((typebits
& N_HLF
) != 0)
15188 else if ((typebits
& N_DBL
) != 0)
15190 if ((typebits
& N_SGN
) != 0)
15191 *g_type
= NT_signed
;
15192 else if ((typebits
& N_UNS
) != 0)
15193 *g_type
= NT_unsigned
;
15194 else if ((typebits
& N_INT
) != 0)
15195 *g_type
= NT_integer
;
15196 else if ((typebits
& N_FLT
) != 0)
15197 *g_type
= NT_float
;
15198 else if ((typebits
& N_SIZ
) != 0)
15199 *g_type
= NT_untyped
;
15203 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
15204 operand type, i.e. the single type specified in a Neon instruction when it
15205 is the only one given. */
15207 static struct neon_type_el
15208 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
15210 struct neon_type_el dest
= *key
;
15212 gas_assert ((thisarg
& N_EQK
) != 0);
15214 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
15219 /* Convert Neon type and size into compact bitmask representation. */
15221 static enum neon_type_mask
15222 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
15229 case 8: return N_8
;
15230 case 16: return N_16
;
15231 case 32: return N_32
;
15232 case 64: return N_64
;
15240 case 8: return N_I8
;
15241 case 16: return N_I16
;
15242 case 32: return N_I32
;
15243 case 64: return N_I64
;
15251 case 16: return N_F16
;
15252 case 32: return N_F32
;
15253 case 64: return N_F64
;
15261 case 8: return N_P8
;
15262 case 16: return N_P16
;
15263 case 64: return N_P64
;
15271 case 8: return N_S8
;
15272 case 16: return N_S16
;
15273 case 32: return N_S32
;
15274 case 64: return N_S64
;
15282 case 8: return N_U8
;
15283 case 16: return N_U16
;
15284 case 32: return N_U32
;
15285 case 64: return N_U64
;
15291 if (size
== 16) return N_BF16
;
15300 /* Convert compact Neon bitmask type representation to a type and size. Only
15301 handles the case where a single bit is set in the mask. */
15304 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
15305 enum neon_type_mask mask
)
15307 if ((mask
& N_EQK
) != 0)
15310 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
15312 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
| N_BF16
))
15315 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
15317 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
15322 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
15324 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
15325 *type
= NT_unsigned
;
15326 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
15327 *type
= NT_integer
;
15328 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
15329 *type
= NT_untyped
;
15330 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
15332 else if ((mask
& (N_F_ALL
)) != 0)
15334 else if ((mask
& (N_BF16
)) != 0)
15342 /* Modify a bitmask of allowed types. This is only needed for type
15346 modify_types_allowed (unsigned allowed
, unsigned mods
)
15349 enum neon_el_type type
;
15355 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
15357 if (el_type_of_type_chk (&type
, &size
,
15358 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
15360 neon_modify_type_size (mods
, &type
, &size
);
15361 destmask
|= type_chk_of_el_type (type
, size
);
15368 /* Check type and return type classification.
15369 The manual states (paraphrase): If one datatype is given, it indicates the
15371 - the second operand, if there is one
15372 - the operand, if there is no second operand
15373 - the result, if there are no operands.
15374 This isn't quite good enough though, so we use a concept of a "key" datatype
15375 which is set on a per-instruction basis, which is the one which matters when
15376 only one data type is written.
15377 Note: this function has side-effects (e.g. filling in missing operands). All
15378 Neon instructions should call it before performing bit encoding. */
15380 static struct neon_type_el
15381 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
15384 unsigned i
, pass
, key_el
= 0;
15385 unsigned types
[NEON_MAX_TYPE_ELS
];
15386 enum neon_el_type k_type
= NT_invtype
;
15387 unsigned k_size
= -1u;
15388 struct neon_type_el badtype
= {NT_invtype
, -1};
15389 unsigned key_allowed
= 0;
15391 /* Optional registers in Neon instructions are always (not) in operand 1.
15392 Fill in the missing operand here, if it was omitted. */
15393 if (els
> 1 && !inst
.operands
[1].present
)
15394 inst
.operands
[1] = inst
.operands
[0];
15396 /* Suck up all the varargs. */
15398 for (i
= 0; i
< els
; i
++)
15400 unsigned thisarg
= va_arg (ap
, unsigned);
15401 if (thisarg
== N_IGNORE_TYPE
)
15406 types
[i
] = thisarg
;
15407 if ((thisarg
& N_KEY
) != 0)
15412 if (inst
.vectype
.elems
> 0)
15413 for (i
= 0; i
< els
; i
++)
15414 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
15416 first_error (_("types specified in both the mnemonic and operands"));
15420 /* Duplicate inst.vectype elements here as necessary.
15421 FIXME: No idea if this is exactly the same as the ARM assembler,
15422 particularly when an insn takes one register and one non-register
15424 if (inst
.vectype
.elems
== 1 && els
> 1)
15427 inst
.vectype
.elems
= els
;
15428 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
15429 for (j
= 0; j
< els
; j
++)
15431 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15434 else if (inst
.vectype
.elems
== 0 && els
> 0)
15437 /* No types were given after the mnemonic, so look for types specified
15438 after each operand. We allow some flexibility here; as long as the
15439 "key" operand has a type, we can infer the others. */
15440 for (j
= 0; j
< els
; j
++)
15441 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
15442 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
15444 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
15446 for (j
= 0; j
< els
; j
++)
15447 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
15448 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15453 first_error (_("operand types can't be inferred"));
15457 else if (inst
.vectype
.elems
!= els
)
15459 first_error (_("type specifier has the wrong number of parts"));
15463 for (pass
= 0; pass
< 2; pass
++)
15465 for (i
= 0; i
< els
; i
++)
15467 unsigned thisarg
= types
[i
];
15468 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15469 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15470 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15471 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15473 /* Decay more-specific signed & unsigned types to sign-insensitive
15474 integer types if sign-specific variants are unavailable. */
15475 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15476 && (types_allowed
& N_SU_ALL
) == 0)
15477 g_type
= NT_integer
;
15479 /* If only untyped args are allowed, decay any more specific types to
15480 them. Some instructions only care about signs for some element
15481 sizes, so handle that properly. */
15482 if (((types_allowed
& N_UNT
) == 0)
15483 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15484 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15485 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15486 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15487 g_type
= NT_untyped
;
15491 if ((thisarg
& N_KEY
) != 0)
15495 key_allowed
= thisarg
& ~N_KEY
;
15497 /* Check architecture constraint on FP16 extension. */
15499 && k_type
== NT_float
15500 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15502 inst
.error
= _(BAD_FP16
);
15509 if ((thisarg
& N_VFP
) != 0)
15511 enum neon_shape_el regshape
;
15512 unsigned regwidth
, match
;
15514 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15517 first_error (_("invalid instruction shape"));
15520 regshape
= neon_shape_tab
[ns
].el
[i
];
15521 regwidth
= neon_shape_el_size
[regshape
];
15523 /* In VFP mode, operands must match register widths. If we
15524 have a key operand, use its width, else use the width of
15525 the current operand. */
15531 /* FP16 will use a single precision register. */
15532 if (regwidth
== 32 && match
== 16)
15534 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15538 inst
.error
= _(BAD_FP16
);
15543 if (regwidth
!= match
)
15545 first_error (_("operand size must match register width"));
15550 if ((thisarg
& N_EQK
) == 0)
15552 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15554 if ((given_type
& types_allowed
) == 0)
15556 first_error (BAD_SIMD_TYPE
);
15562 enum neon_el_type mod_k_type
= k_type
;
15563 unsigned mod_k_size
= k_size
;
15564 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15565 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15567 first_error (_("inconsistent types in Neon instruction"));
15575 return inst
.vectype
.el
[key_el
];
15578 /* Neon-style VFP instruction forwarding. */
15580 /* Thumb VFP instructions have 0xE in the condition field. */
15583 do_vfp_cond_or_thumb (void)
15588 inst
.instruction
|= 0xe0000000;
15590 inst
.instruction
|= inst
.cond
<< 28;
15593 /* Look up and encode a simple mnemonic, for use as a helper function for the
15594 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15595 etc. It is assumed that operand parsing has already been done, and that the
15596 operands are in the form expected by the given opcode (this isn't necessarily
15597 the same as the form in which they were parsed, hence some massaging must
15598 take place before this function is called).
15599 Checks current arch version against that in the looked-up opcode. */
15602 do_vfp_nsyn_opcode (const char *opname
)
15604 const struct asm_opcode
*opcode
;
15606 opcode
= (const struct asm_opcode
*) str_hash_find (arm_ops_hsh
, opname
);
15611 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15612 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15619 inst
.instruction
= opcode
->tvalue
;
15620 opcode
->tencode ();
15624 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15625 opcode
->aencode ();
15630 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15632 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15634 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15637 do_vfp_nsyn_opcode ("fadds");
15639 do_vfp_nsyn_opcode ("fsubs");
15641 /* ARMv8.2 fp16 instruction. */
15643 do_scalar_fp16_v82_encode ();
15648 do_vfp_nsyn_opcode ("faddd");
15650 do_vfp_nsyn_opcode ("fsubd");
15654 /* Check operand types to see if this is a VFP instruction, and if so call
15658 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15660 enum neon_shape rs
;
15661 struct neon_type_el et
;
15666 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15667 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15671 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15672 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15673 N_F_ALL
| N_KEY
| N_VFP
);
15680 if (et
.type
!= NT_invtype
)
15691 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15693 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15695 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15698 do_vfp_nsyn_opcode ("fmacs");
15700 do_vfp_nsyn_opcode ("fnmacs");
15702 /* ARMv8.2 fp16 instruction. */
15704 do_scalar_fp16_v82_encode ();
15709 do_vfp_nsyn_opcode ("fmacd");
15711 do_vfp_nsyn_opcode ("fnmacd");
15716 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15718 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15720 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15723 do_vfp_nsyn_opcode ("ffmas");
15725 do_vfp_nsyn_opcode ("ffnmas");
15727 /* ARMv8.2 fp16 instruction. */
15729 do_scalar_fp16_v82_encode ();
15734 do_vfp_nsyn_opcode ("ffmad");
15736 do_vfp_nsyn_opcode ("ffnmad");
15741 do_vfp_nsyn_mul (enum neon_shape rs
)
15743 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15745 do_vfp_nsyn_opcode ("fmuls");
15747 /* ARMv8.2 fp16 instruction. */
15749 do_scalar_fp16_v82_encode ();
15752 do_vfp_nsyn_opcode ("fmuld");
15756 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15758 int is_neg
= (inst
.instruction
& 0x80) != 0;
15759 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15761 if (rs
== NS_FF
|| rs
== NS_HH
)
15764 do_vfp_nsyn_opcode ("fnegs");
15766 do_vfp_nsyn_opcode ("fabss");
15768 /* ARMv8.2 fp16 instruction. */
15770 do_scalar_fp16_v82_encode ();
15775 do_vfp_nsyn_opcode ("fnegd");
15777 do_vfp_nsyn_opcode ("fabsd");
15781 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15782 insns belong to Neon, and are handled elsewhere. */
15785 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15787 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15791 do_vfp_nsyn_opcode ("fldmdbs");
15793 do_vfp_nsyn_opcode ("fldmias");
15798 do_vfp_nsyn_opcode ("fstmdbs");
15800 do_vfp_nsyn_opcode ("fstmias");
15805 do_vfp_nsyn_sqrt (void)
15807 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15808 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15810 if (rs
== NS_FF
|| rs
== NS_HH
)
15812 do_vfp_nsyn_opcode ("fsqrts");
15814 /* ARMv8.2 fp16 instruction. */
15816 do_scalar_fp16_v82_encode ();
15819 do_vfp_nsyn_opcode ("fsqrtd");
15823 do_vfp_nsyn_div (void)
15825 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15826 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15827 N_F_ALL
| N_KEY
| N_VFP
);
15829 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15831 do_vfp_nsyn_opcode ("fdivs");
15833 /* ARMv8.2 fp16 instruction. */
15835 do_scalar_fp16_v82_encode ();
15838 do_vfp_nsyn_opcode ("fdivd");
15842 do_vfp_nsyn_nmul (void)
15844 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15845 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15846 N_F_ALL
| N_KEY
| N_VFP
);
15848 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15850 NEON_ENCODE (SINGLE
, inst
);
15851 do_vfp_sp_dyadic ();
15853 /* ARMv8.2 fp16 instruction. */
15855 do_scalar_fp16_v82_encode ();
15859 NEON_ENCODE (DOUBLE
, inst
);
15860 do_vfp_dp_rd_rn_rm ();
15862 do_vfp_cond_or_thumb ();
15866 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15870 neon_logbits (unsigned x
)
15872 return ffs (x
) - 4;
15875 #define LOW4(R) ((R) & 0xf)
15876 #define HI1(R) (((R) >> 4) & 1)
15877 #define LOW1(R) ((R) & 0x1)
15878 #define HI4(R) (((R) >> 1) & 0xf)
15881 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15886 first_error (BAD_EL_TYPE
);
15889 switch (inst
.operands
[0].imm
)
15892 first_error (_("invalid condition"));
15914 /* only accept eq and ne. */
15915 if (inst
.operands
[0].imm
> 1)
15917 first_error (_("invalid condition"));
15920 return inst
.operands
[0].imm
;
15922 if (inst
.operands
[0].imm
== 0x2)
15924 else if (inst
.operands
[0].imm
== 0x8)
15928 first_error (_("invalid condition"));
15932 switch (inst
.operands
[0].imm
)
15935 first_error (_("invalid condition"));
15951 /* Should be unreachable. */
15955 /* For VCTP (create vector tail predicate) in MVE. */
15960 unsigned size
= 0x0;
15962 if (inst
.cond
> COND_ALWAYS
)
15963 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15965 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15967 /* This is a typical MVE instruction which has no type but have size 8, 16,
15968 32 and 64. For instructions with no type, inst.vectype.el[j].type is set
15969 to NT_untyped and size is updated in inst.vectype.el[j].size. */
15970 if ((inst
.operands
[0].present
) && (inst
.vectype
.el
[0].type
== NT_untyped
))
15971 dt
= inst
.vectype
.el
[0].size
;
15973 /* Setting this does not indicate an actual NEON instruction, but only
15974 indicates that the mnemonic accepts neon-style type suffixes. */
15988 first_error (_("Type is not allowed for this instruction"));
15990 inst
.instruction
|= size
<< 20;
15991 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15997 /* We are dealing with a vector predicated block. */
15998 if (inst
.operands
[0].present
)
16000 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
16001 struct neon_type_el et
16002 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
16005 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
16007 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16009 if (et
.type
== NT_invtype
)
16012 if (et
.type
== NT_float
)
16014 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
16016 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
16017 inst
.instruction
|= (et
.size
== 16) << 28;
16018 inst
.instruction
|= 0x3 << 20;
16022 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
16024 inst
.instruction
|= 1 << 28;
16025 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16028 if (inst
.operands
[2].isquad
)
16030 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16031 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16032 inst
.instruction
|= (fcond
& 0x2) >> 1;
16036 if (inst
.operands
[2].reg
== REG_SP
)
16037 as_tsktsk (MVE_BAD_SP
);
16038 inst
.instruction
|= 1 << 6;
16039 inst
.instruction
|= (fcond
& 0x2) << 4;
16040 inst
.instruction
|= inst
.operands
[2].reg
;
16042 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16043 inst
.instruction
|= (fcond
& 0x4) << 10;
16044 inst
.instruction
|= (fcond
& 0x1) << 7;
16047 set_pred_insn_type (VPT_INSN
);
16049 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
16050 | ((inst
.instruction
& 0xe000) >> 13);
16051 now_pred
.warn_deprecated
= FALSE
;
16052 now_pred
.type
= VECTOR_PRED
;
16059 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
16060 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
16061 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
16062 if (!inst
.operands
[2].present
)
16063 first_error (_("MVE vector or ARM register expected"));
16064 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16066 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
16067 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
16068 && inst
.operands
[1].isquad
)
16070 inst
.instruction
= N_MNEM_vcmp
;
16074 if (inst
.cond
> COND_ALWAYS
)
16075 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16077 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16079 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
16080 struct neon_type_el et
16081 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
16084 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
16085 && !inst
.operands
[2].iszr
, BAD_PC
);
16087 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
16089 inst
.instruction
= 0xee010f00;
16090 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16091 inst
.instruction
|= (fcond
& 0x4) << 10;
16092 inst
.instruction
|= (fcond
& 0x1) << 7;
16093 if (et
.type
== NT_float
)
16095 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
16097 inst
.instruction
|= (et
.size
== 16) << 28;
16098 inst
.instruction
|= 0x3 << 20;
16102 inst
.instruction
|= 1 << 28;
16103 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16105 if (inst
.operands
[2].isquad
)
16107 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16108 inst
.instruction
|= (fcond
& 0x2) >> 1;
16109 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16113 if (inst
.operands
[2].reg
== REG_SP
)
16114 as_tsktsk (MVE_BAD_SP
);
16115 inst
.instruction
|= 1 << 6;
16116 inst
.instruction
|= (fcond
& 0x2) << 4;
16117 inst
.instruction
|= inst
.operands
[2].reg
;
16125 do_mve_vmaxa_vmina (void)
16127 if (inst
.cond
> COND_ALWAYS
)
16128 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16130 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16132 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16133 struct neon_type_el et
16134 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
16136 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16137 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16138 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16139 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16140 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16145 do_mve_vfmas (void)
16147 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16148 struct neon_type_el et
16149 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
16151 if (inst
.cond
> COND_ALWAYS
)
16152 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16154 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16156 if (inst
.operands
[2].reg
== REG_SP
)
16157 as_tsktsk (MVE_BAD_SP
);
16158 else if (inst
.operands
[2].reg
== REG_PC
)
16159 as_tsktsk (MVE_BAD_PC
);
16161 inst
.instruction
|= (et
.size
== 16) << 28;
16162 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16163 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16164 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16165 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16166 inst
.instruction
|= inst
.operands
[2].reg
;
16171 do_mve_viddup (void)
16173 if (inst
.cond
> COND_ALWAYS
)
16174 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16176 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16178 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
16179 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
16180 _("immediate must be either 1, 2, 4 or 8"));
16182 enum neon_shape rs
;
16183 struct neon_type_el et
;
16185 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
16187 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
16188 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
16193 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
16194 if (inst
.operands
[2].reg
== REG_SP
)
16195 as_tsktsk (MVE_BAD_SP
);
16196 else if (inst
.operands
[2].reg
== REG_PC
)
16197 first_error (BAD_PC
);
16199 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
16200 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
16201 Rm
= inst
.operands
[2].reg
>> 1;
16203 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16204 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16205 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16206 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16207 inst
.instruction
|= (imm
> 2) << 7;
16208 inst
.instruction
|= Rm
<< 1;
16209 inst
.instruction
|= (imm
== 2 || imm
== 8);
16214 do_mve_vmlas (void)
16216 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16217 struct neon_type_el et
16218 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16220 if (inst
.operands
[2].reg
== REG_PC
)
16221 as_tsktsk (MVE_BAD_PC
);
16222 else if (inst
.operands
[2].reg
== REG_SP
)
16223 as_tsktsk (MVE_BAD_SP
);
16225 if (inst
.cond
> COND_ALWAYS
)
16226 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16228 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16230 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16231 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16232 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16233 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16234 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16235 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16236 inst
.instruction
|= inst
.operands
[2].reg
;
16241 do_mve_vshll (void)
16243 struct neon_type_el et
16244 = neon_check_type (2, NS_QQI
, N_EQK
, N_S8
| N_U8
| N_S16
| N_U16
| N_KEY
);
16246 if (inst
.cond
> COND_ALWAYS
)
16247 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16249 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16251 int imm
= inst
.operands
[2].imm
;
16252 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16253 _("immediate value out of range"));
16255 if ((unsigned)imm
== et
.size
)
16257 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16258 inst
.instruction
|= 0x110001;
16262 inst
.instruction
|= (et
.size
+ imm
) << 16;
16263 inst
.instruction
|= 0x800140;
16266 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16267 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16268 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16269 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16270 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16275 do_mve_vshlc (void)
16277 if (inst
.cond
> COND_ALWAYS
)
16278 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16280 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16282 if (inst
.operands
[1].reg
== REG_PC
)
16283 as_tsktsk (MVE_BAD_PC
);
16284 else if (inst
.operands
[1].reg
== REG_SP
)
16285 as_tsktsk (MVE_BAD_SP
);
16287 int imm
= inst
.operands
[2].imm
;
16288 constraint (imm
< 1 || imm
> 32, _("immediate value out of range"));
16290 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16291 inst
.instruction
|= (imm
& 0x1f) << 16;
16292 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16293 inst
.instruction
|= inst
.operands
[1].reg
;
16298 do_mve_vshrn (void)
16301 switch (inst
.instruction
)
16303 case M_MNEM_vshrnt
:
16304 case M_MNEM_vshrnb
:
16305 case M_MNEM_vrshrnt
:
16306 case M_MNEM_vrshrnb
:
16307 types
= N_I16
| N_I32
;
16309 case M_MNEM_vqshrnt
:
16310 case M_MNEM_vqshrnb
:
16311 case M_MNEM_vqrshrnt
:
16312 case M_MNEM_vqrshrnb
:
16313 types
= N_U16
| N_U32
| N_S16
| N_S32
;
16315 case M_MNEM_vqshrunt
:
16316 case M_MNEM_vqshrunb
:
16317 case M_MNEM_vqrshrunt
:
16318 case M_MNEM_vqrshrunb
:
16319 types
= N_S16
| N_S32
;
16325 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
16327 if (inst
.cond
> COND_ALWAYS
)
16328 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16330 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16332 unsigned Qd
= inst
.operands
[0].reg
;
16333 unsigned Qm
= inst
.operands
[1].reg
;
16334 unsigned imm
= inst
.operands
[2].imm
;
16335 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
16337 ? _("immediate operand expected in the range [1,8]")
16338 : _("immediate operand expected in the range [1,16]"));
16340 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16341 inst
.instruction
|= HI1 (Qd
) << 22;
16342 inst
.instruction
|= (et
.size
- imm
) << 16;
16343 inst
.instruction
|= LOW4 (Qd
) << 12;
16344 inst
.instruction
|= HI1 (Qm
) << 5;
16345 inst
.instruction
|= LOW4 (Qm
);
16350 do_mve_vqmovn (void)
16352 struct neon_type_el et
;
16353 if (inst
.instruction
== M_MNEM_vqmovnt
16354 || inst
.instruction
== M_MNEM_vqmovnb
)
16355 et
= neon_check_type (2, NS_QQ
, N_EQK
,
16356 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
16358 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16360 if (inst
.cond
> COND_ALWAYS
)
16361 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16363 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16365 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16366 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16367 inst
.instruction
|= (et
.size
== 32) << 18;
16368 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16369 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16370 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16375 do_mve_vpsel (void)
16377 neon_select_shape (NS_QQQ
, NS_NULL
);
16379 if (inst
.cond
> COND_ALWAYS
)
16380 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16382 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16384 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16385 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16386 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16387 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16388 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16389 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16394 do_mve_vpnot (void)
16396 if (inst
.cond
> COND_ALWAYS
)
16397 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16399 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16403 do_mve_vmaxnma_vminnma (void)
16405 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16406 struct neon_type_el et
16407 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
16409 if (inst
.cond
> COND_ALWAYS
)
16410 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16412 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16414 inst
.instruction
|= (et
.size
== 16) << 28;
16415 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16416 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16417 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16418 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16423 do_mve_vcmul (void)
16425 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
16426 struct neon_type_el et
16427 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
16429 if (inst
.cond
> COND_ALWAYS
)
16430 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16432 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16434 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
16435 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
16436 _("immediate out of range"));
16438 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
16439 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
16440 as_tsktsk (BAD_MVE_SRCDEST
);
16442 inst
.instruction
|= (et
.size
== 32) << 28;
16443 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16444 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16445 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16446 inst
.instruction
|= (rot
> 90) << 12;
16447 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16448 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16449 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16450 inst
.instruction
|= (rot
== 90 || rot
== 270);
16454 /* To handle the Low Overhead Loop instructions
16455 in Armv8.1-M Mainline and MVE. */
16459 unsigned long insn
= inst
.instruction
;
16461 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
16463 if (insn
== T_MNEM_lctp
)
16466 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN
);
16468 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16470 struct neon_type_el et
16471 = neon_check_type (2, NS_RR
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16472 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16479 constraint (!inst
.operands
[0].present
,
16481 /* fall through. */
16484 if (!inst
.operands
[0].present
)
16485 inst
.instruction
|= 1 << 21;
16487 v8_1_loop_reloc (TRUE
);
16492 v8_1_loop_reloc (FALSE
);
16493 /* fall through. */
16496 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
16498 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16499 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16500 else if (inst
.operands
[1].reg
== REG_PC
)
16501 as_tsktsk (MVE_BAD_PC
);
16502 if (inst
.operands
[1].reg
== REG_SP
)
16503 as_tsktsk (MVE_BAD_SP
);
16505 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
16515 do_vfp_nsyn_cmp (void)
16517 enum neon_shape rs
;
16518 if (!inst
.operands
[0].isreg
)
16525 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
16526 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
16530 if (inst
.operands
[1].isreg
)
16532 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
16533 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
16535 if (rs
== NS_FF
|| rs
== NS_HH
)
16537 NEON_ENCODE (SINGLE
, inst
);
16538 do_vfp_sp_monadic ();
16542 NEON_ENCODE (DOUBLE
, inst
);
16543 do_vfp_dp_rd_rm ();
16548 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
16549 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
16551 switch (inst
.instruction
& 0x0fffffff)
16554 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
16557 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
16563 if (rs
== NS_FI
|| rs
== NS_HI
)
16565 NEON_ENCODE (SINGLE
, inst
);
16566 do_vfp_sp_compare_z ();
16570 NEON_ENCODE (DOUBLE
, inst
);
16574 do_vfp_cond_or_thumb ();
16576 /* ARMv8.2 fp16 instruction. */
16577 if (rs
== NS_HI
|| rs
== NS_HH
)
16578 do_scalar_fp16_v82_encode ();
16582 nsyn_insert_sp (void)
16584 inst
.operands
[1] = inst
.operands
[0];
16585 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
16586 inst
.operands
[0].reg
= REG_SP
;
16587 inst
.operands
[0].isreg
= 1;
16588 inst
.operands
[0].writeback
= 1;
16589 inst
.operands
[0].present
= 1;
16592 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16593 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16596 neon_dp_fixup (struct arm_it
* insn
)
16598 unsigned int i
= insn
->instruction
;
16603 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16614 insn
->instruction
= i
;
16618 mve_encode_qqr (int size
, int U
, int fp
)
16620 if (inst
.operands
[2].reg
== REG_SP
)
16621 as_tsktsk (MVE_BAD_SP
);
16622 else if (inst
.operands
[2].reg
== REG_PC
)
16623 as_tsktsk (MVE_BAD_PC
);
16628 if (((unsigned)inst
.instruction
) == 0xd00)
16629 inst
.instruction
= 0xee300f40;
16631 else if (((unsigned)inst
.instruction
) == 0x200d00)
16632 inst
.instruction
= 0xee301f40;
16634 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16635 inst
.instruction
= 0xee310e60;
16637 /* Setting size which is 1 for F16 and 0 for F32. */
16638 inst
.instruction
|= (size
== 16) << 28;
16643 if (((unsigned)inst
.instruction
) == 0x800)
16644 inst
.instruction
= 0xee010f40;
16646 else if (((unsigned)inst
.instruction
) == 0x1000800)
16647 inst
.instruction
= 0xee011f40;
16649 else if (((unsigned)inst
.instruction
) == 0)
16650 inst
.instruction
= 0xee000f40;
16652 else if (((unsigned)inst
.instruction
) == 0x200)
16653 inst
.instruction
= 0xee001f40;
16655 else if (((unsigned)inst
.instruction
) == 0x900)
16656 inst
.instruction
= 0xee010e40;
16658 else if (((unsigned)inst
.instruction
) == 0x910)
16659 inst
.instruction
= 0xee011e60;
16661 else if (((unsigned)inst
.instruction
) == 0x10)
16662 inst
.instruction
= 0xee000f60;
16664 else if (((unsigned)inst
.instruction
) == 0x210)
16665 inst
.instruction
= 0xee001f60;
16667 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16668 inst
.instruction
= 0xee000e40;
16670 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16671 inst
.instruction
= 0xee010e60;
16673 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16674 inst
.instruction
= 0xfe010e60;
16677 inst
.instruction
|= U
<< 28;
16679 /* Setting bits for size. */
16680 inst
.instruction
|= neon_logbits (size
) << 20;
16682 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16683 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16684 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16685 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16686 inst
.instruction
|= inst
.operands
[2].reg
;
16691 mve_encode_rqq (unsigned bit28
, unsigned size
)
16693 inst
.instruction
|= bit28
<< 28;
16694 inst
.instruction
|= neon_logbits (size
) << 20;
16695 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16696 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16697 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16698 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16699 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16704 mve_encode_qqq (int ubit
, int size
)
16707 inst
.instruction
|= (ubit
!= 0) << 28;
16708 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16709 inst
.instruction
|= neon_logbits (size
) << 20;
16710 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16711 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16712 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16713 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16714 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16720 mve_encode_rq (unsigned bit28
, unsigned size
)
16722 inst
.instruction
|= bit28
<< 28;
16723 inst
.instruction
|= neon_logbits (size
) << 18;
16724 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16725 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16730 mve_encode_rrqq (unsigned U
, unsigned size
)
16732 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16734 inst
.instruction
|= U
<< 28;
16735 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16736 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16737 inst
.instruction
|= (size
== 32) << 16;
16738 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16739 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16740 inst
.instruction
|= inst
.operands
[3].reg
;
16744 /* Helper function for neon_three_same handling the operands. */
16746 neon_three_args (int isquad
)
16748 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16749 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16750 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16751 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16752 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16753 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16754 inst
.instruction
|= (isquad
!= 0) << 6;
16758 /* Encode insns with bit pattern:
16760 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16761 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16763 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16764 different meaning for some instruction. */
16767 neon_three_same (int isquad
, int ubit
, int size
)
16769 neon_three_args (isquad
);
16770 inst
.instruction
|= (ubit
!= 0) << 24;
16772 inst
.instruction
|= neon_logbits (size
) << 20;
16774 neon_dp_fixup (&inst
);
16777 /* Encode instructions of the form:
16779 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16780 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16782 Don't write size if SIZE == -1. */
16785 neon_two_same (int qbit
, int ubit
, int size
)
16787 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16788 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16789 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16790 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16791 inst
.instruction
|= (qbit
!= 0) << 6;
16792 inst
.instruction
|= (ubit
!= 0) << 24;
16795 inst
.instruction
|= neon_logbits (size
) << 18;
16797 neon_dp_fixup (&inst
);
16800 enum vfp_or_neon_is_neon_bits
16803 NEON_CHECK_ARCH
= 2,
16804 NEON_CHECK_ARCH8
= 4
16807 /* Call this function if an instruction which may have belonged to the VFP or
16808 Neon instruction sets, but turned out to be a Neon instruction (due to the
16809 operand types involved, etc.). We have to check and/or fix-up a couple of
16812 - Make sure the user hasn't attempted to make a Neon instruction
16814 - Alter the value in the condition code field if necessary.
16815 - Make sure that the arch supports Neon instructions.
16817 Which of these operations take place depends on bits from enum
16818 vfp_or_neon_is_neon_bits.
16820 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16821 current instruction's condition is COND_ALWAYS, the condition field is
16822 changed to inst.uncond_value. This is necessary because instructions shared
16823 between VFP and Neon may be conditional for the VFP variants only, and the
16824 unconditional Neon version must have, e.g., 0xF in the condition field. */
16827 vfp_or_neon_is_neon (unsigned check
)
16829 /* Conditions are always legal in Thumb mode (IT blocks). */
16830 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16832 if (inst
.cond
!= COND_ALWAYS
)
16834 first_error (_(BAD_COND
));
16837 if (inst
.uncond_value
!= -1u)
16838 inst
.instruction
|= inst
.uncond_value
<< 28;
16842 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16843 || ((check
& NEON_CHECK_ARCH8
)
16844 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16846 first_error (_(BAD_FPU
));
16854 /* Return TRUE if the SIMD instruction is available for the current
16855 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16856 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16857 vfp_or_neon_is_neon for the NEON specific checks. */
16860 check_simd_pred_availability (int fp
, unsigned check
)
16862 if (inst
.cond
> COND_ALWAYS
)
16864 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16866 inst
.error
= BAD_FPU
;
16869 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16871 else if (inst
.cond
< COND_ALWAYS
)
16873 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16874 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16875 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16880 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16881 && vfp_or_neon_is_neon (check
) == FAIL
)
16884 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16885 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16890 /* Neon instruction encoders, in approximate order of appearance. */
16893 do_neon_dyadic_i_su (void)
16895 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16898 enum neon_shape rs
;
16899 struct neon_type_el et
;
16900 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16901 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16903 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16905 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16909 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16911 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16915 do_neon_dyadic_i64_su (void)
16917 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16919 enum neon_shape rs
;
16920 struct neon_type_el et
;
16921 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16923 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16924 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16928 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16929 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16932 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16934 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16938 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16941 unsigned size
= et
.size
>> 3;
16942 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16943 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16944 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16945 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16946 inst
.instruction
|= (isquad
!= 0) << 6;
16947 inst
.instruction
|= immbits
<< 16;
16948 inst
.instruction
|= (size
>> 3) << 7;
16949 inst
.instruction
|= (size
& 0x7) << 19;
16951 inst
.instruction
|= (uval
!= 0) << 24;
16953 neon_dp_fixup (&inst
);
16959 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16962 if (!inst
.operands
[2].isreg
)
16964 enum neon_shape rs
;
16965 struct neon_type_el et
;
16966 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16968 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16969 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_MVE
);
16973 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16974 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16976 int imm
= inst
.operands
[2].imm
;
16978 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16979 _("immediate out of range for shift"));
16980 NEON_ENCODE (IMMED
, inst
);
16981 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16985 enum neon_shape rs
;
16986 struct neon_type_el et
;
16987 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16989 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16990 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16994 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16995 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
17001 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17002 _("invalid instruction shape"));
17003 if (inst
.operands
[2].reg
== REG_SP
)
17004 as_tsktsk (MVE_BAD_SP
);
17005 else if (inst
.operands
[2].reg
== REG_PC
)
17006 as_tsktsk (MVE_BAD_PC
);
17008 inst
.instruction
= 0xee311e60;
17009 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17010 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17011 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17012 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17013 inst
.instruction
|= inst
.operands
[2].reg
;
17020 /* VSHL/VQSHL 3-register variants have syntax such as:
17022 whereas other 3-register operations encoded by neon_three_same have
17025 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
17026 operands[2].reg here. */
17027 tmp
= inst
.operands
[2].reg
;
17028 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17029 inst
.operands
[1].reg
= tmp
;
17030 NEON_ENCODE (INTEGER
, inst
);
17031 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17037 do_neon_qshl (void)
17039 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17042 if (!inst
.operands
[2].isreg
)
17044 enum neon_shape rs
;
17045 struct neon_type_el et
;
17046 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17048 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
17049 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_SU_MVE
);
17053 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17054 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
17056 int imm
= inst
.operands
[2].imm
;
17058 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
17059 _("immediate out of range for shift"));
17060 NEON_ENCODE (IMMED
, inst
);
17061 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
17065 enum neon_shape rs
;
17066 struct neon_type_el et
;
17068 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17070 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17071 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
17075 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17076 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
17081 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17082 _("invalid instruction shape"));
17083 if (inst
.operands
[2].reg
== REG_SP
)
17084 as_tsktsk (MVE_BAD_SP
);
17085 else if (inst
.operands
[2].reg
== REG_PC
)
17086 as_tsktsk (MVE_BAD_PC
);
17088 inst
.instruction
= 0xee311ee0;
17089 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17090 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17091 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17092 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17093 inst
.instruction
|= inst
.operands
[2].reg
;
17100 /* See note in do_neon_shl. */
17101 tmp
= inst
.operands
[2].reg
;
17102 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17103 inst
.operands
[1].reg
= tmp
;
17104 NEON_ENCODE (INTEGER
, inst
);
17105 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17111 do_neon_rshl (void)
17113 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17116 enum neon_shape rs
;
17117 struct neon_type_el et
;
17118 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17120 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17121 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17125 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17126 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
17133 if (inst
.operands
[2].reg
== REG_PC
)
17134 as_tsktsk (MVE_BAD_PC
);
17135 else if (inst
.operands
[2].reg
== REG_SP
)
17136 as_tsktsk (MVE_BAD_SP
);
17138 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17139 _("invalid instruction shape"));
17141 if (inst
.instruction
== 0x0000510)
17142 /* We are dealing with vqrshl. */
17143 inst
.instruction
= 0xee331ee0;
17145 /* We are dealing with vrshl. */
17146 inst
.instruction
= 0xee331e60;
17148 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17149 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17150 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17151 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17152 inst
.instruction
|= inst
.operands
[2].reg
;
17157 tmp
= inst
.operands
[2].reg
;
17158 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17159 inst
.operands
[1].reg
= tmp
;
17160 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17165 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
17167 /* Handle .I8 pseudo-instructions. */
17170 /* Unfortunately, this will make everything apart from zero out-of-range.
17171 FIXME is this the intended semantics? There doesn't seem much point in
17172 accepting .I8 if so. */
17173 immediate
|= immediate
<< 8;
17179 if (immediate
== (immediate
& 0x000000ff))
17181 *immbits
= immediate
;
17184 else if (immediate
== (immediate
& 0x0000ff00))
17186 *immbits
= immediate
>> 8;
17189 else if (immediate
== (immediate
& 0x00ff0000))
17191 *immbits
= immediate
>> 16;
17194 else if (immediate
== (immediate
& 0xff000000))
17196 *immbits
= immediate
>> 24;
17199 if ((immediate
& 0xffff) != (immediate
>> 16))
17200 goto bad_immediate
;
17201 immediate
&= 0xffff;
17204 if (immediate
== (immediate
& 0x000000ff))
17206 *immbits
= immediate
;
17209 else if (immediate
== (immediate
& 0x0000ff00))
17211 *immbits
= immediate
>> 8;
17216 first_error (_("immediate value out of range"));
17221 do_neon_logic (void)
17223 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
17225 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17227 && !check_simd_pred_availability (FALSE
,
17228 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17230 else if (rs
!= NS_QQQ
17231 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17232 first_error (BAD_FPU
);
17234 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17235 /* U bit and size field were set as part of the bitmask. */
17236 NEON_ENCODE (INTEGER
, inst
);
17237 neon_three_same (neon_quad (rs
), 0, -1);
17241 const int three_ops_form
= (inst
.operands
[2].present
17242 && !inst
.operands
[2].isreg
);
17243 const int immoperand
= (three_ops_form
? 2 : 1);
17244 enum neon_shape rs
= (three_ops_form
17245 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
17246 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
17247 /* Because neon_select_shape makes the second operand a copy of the first
17248 if the second operand is not present. */
17250 && !check_simd_pred_availability (FALSE
,
17251 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17253 else if (rs
!= NS_QQI
17254 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17255 first_error (BAD_FPU
);
17257 struct neon_type_el et
;
17258 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17259 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
17261 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
17264 if (et
.type
== NT_invtype
)
17266 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
17271 if (three_ops_form
)
17272 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17273 _("first and second operands shall be the same register"));
17275 NEON_ENCODE (IMMED
, inst
);
17277 immbits
= inst
.operands
[immoperand
].imm
;
17280 /* .i64 is a pseudo-op, so the immediate must be a repeating
17282 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
17283 inst
.operands
[immoperand
].reg
: 0))
17285 /* Set immbits to an invalid constant. */
17286 immbits
= 0xdeadbeef;
17293 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17297 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17301 /* Pseudo-instruction for VBIC. */
17302 neon_invert_size (&immbits
, 0, et
.size
);
17303 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17307 /* Pseudo-instruction for VORR. */
17308 neon_invert_size (&immbits
, 0, et
.size
);
17309 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17319 inst
.instruction
|= neon_quad (rs
) << 6;
17320 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17321 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17322 inst
.instruction
|= cmode
<< 8;
17323 neon_write_immbits (immbits
);
17325 neon_dp_fixup (&inst
);
17330 do_neon_bitfield (void)
17332 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17333 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17334 neon_three_same (neon_quad (rs
), 0, -1);
17338 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
17341 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17342 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
17344 if (et
.type
== NT_float
)
17346 NEON_ENCODE (FLOAT
, inst
);
17348 mve_encode_qqr (et
.size
, 0, 1);
17350 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
17354 NEON_ENCODE (INTEGER
, inst
);
17356 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
17358 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
17364 do_neon_dyadic_if_su_d (void)
17366 /* This version only allow D registers, but that constraint is enforced during
17367 operand parsing so we don't need to do anything extra here. */
17368 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17372 do_neon_dyadic_if_i_d (void)
17374 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17375 affected if we specify unsigned args. */
17376 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17380 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
17382 constraint (size
< 32, BAD_ADDR_MODE
);
17383 constraint (size
!= elsize
, BAD_EL_TYPE
);
17384 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17385 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
17386 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
17387 _("destination register and offset register may not be the"
17390 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17397 constraint ((imm
% (size
/ 8) != 0)
17398 || imm
> (0x7f << neon_logbits (size
)),
17399 (size
== 32) ? _("immediate must be a multiple of 4 in the"
17400 " range of +/-[0,508]")
17401 : _("immediate must be a multiple of 8 in the"
17402 " range of +/-[0,1016]"));
17403 inst
.instruction
|= 0x11 << 24;
17404 inst
.instruction
|= add
<< 23;
17405 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17406 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17407 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17408 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17409 inst
.instruction
|= 1 << 12;
17410 inst
.instruction
|= (size
== 64) << 8;
17411 inst
.instruction
&= 0xffffff00;
17412 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17413 inst
.instruction
|= imm
>> neon_logbits (size
);
17417 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
17419 unsigned os
= inst
.operands
[1].imm
>> 5;
17420 unsigned type
= inst
.vectype
.el
[0].type
;
17421 constraint (os
!= 0 && size
== 8,
17422 _("can not shift offsets when accessing less than half-word"));
17423 constraint (os
&& os
!= neon_logbits (size
),
17424 _("shift immediate must be 1, 2 or 3 for half-word, word"
17425 " or double-word accesses respectively"));
17426 if (inst
.operands
[1].reg
== REG_PC
)
17427 as_tsktsk (MVE_BAD_PC
);
17432 constraint (elsize
>= 64, BAD_EL_TYPE
);
17435 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17439 constraint (elsize
!= size
, BAD_EL_TYPE
);
17444 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
17448 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
17449 _("destination register and offset register may not be"
17451 constraint (size
== elsize
&& type
== NT_signed
, BAD_EL_TYPE
);
17452 constraint (size
!= elsize
&& type
!= NT_unsigned
&& type
!= NT_signed
,
17454 inst
.instruction
|= ((size
== elsize
) || (type
== NT_unsigned
)) << 28;
17458 constraint (type
!= NT_untyped
, BAD_EL_TYPE
);
17461 inst
.instruction
|= 1 << 23;
17462 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17463 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17464 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17465 inst
.instruction
|= neon_logbits (elsize
) << 7;
17466 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
17467 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
17468 inst
.instruction
|= !!os
;
17472 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
17474 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
17476 constraint (size
>= 64, BAD_ADDR_MODE
);
17480 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17483 constraint (elsize
!= size
, BAD_EL_TYPE
);
17490 constraint (elsize
!= size
&& type
!= NT_unsigned
17491 && type
!= NT_signed
, BAD_EL_TYPE
);
17495 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
17498 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17506 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
17511 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17514 constraint (1, _("immediate must be a multiple of 2 in the"
17515 " range of +/-[0,254]"));
17518 constraint (1, _("immediate must be a multiple of 4 in the"
17519 " range of +/-[0,508]"));
17524 if (size
!= elsize
)
17526 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
17527 constraint (inst
.operands
[0].reg
> 14,
17528 _("MVE vector register in the range [Q0..Q7] expected"));
17529 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
17530 inst
.instruction
|= (size
== 16) << 19;
17531 inst
.instruction
|= neon_logbits (elsize
) << 7;
17535 if (inst
.operands
[1].reg
== REG_PC
)
17536 as_tsktsk (MVE_BAD_PC
);
17537 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17538 as_tsktsk (MVE_BAD_SP
);
17539 inst
.instruction
|= 1 << 12;
17540 inst
.instruction
|= neon_logbits (size
) << 7;
17542 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
17543 inst
.instruction
|= add
<< 23;
17544 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17545 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17546 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17547 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17548 inst
.instruction
&= 0xffffff80;
17549 inst
.instruction
|= imm
>> neon_logbits (size
);
17554 do_mve_vstr_vldr (void)
17559 if (inst
.cond
> COND_ALWAYS
)
17560 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17562 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17564 switch (inst
.instruction
)
17571 /* fall through. */
17577 /* fall through. */
17583 /* fall through. */
17589 /* fall through. */
17594 unsigned elsize
= inst
.vectype
.el
[0].size
;
17596 if (inst
.operands
[1].isquad
)
17598 /* We are dealing with [Q, imm]{!} cases. */
17599 do_mve_vstr_vldr_QI (size
, elsize
, load
);
17603 if (inst
.operands
[1].immisreg
== 2)
17605 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17606 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
17608 else if (!inst
.operands
[1].immisreg
)
17610 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17611 do_mve_vstr_vldr_RI (size
, elsize
, load
);
17614 constraint (1, BAD_ADDR_MODE
);
17621 do_mve_vst_vld (void)
17623 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17626 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
17627 || inst
.relocs
[0].exp
.X_add_number
!= 0
17628 || inst
.operands
[1].immisreg
!= 0,
17630 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
17631 if (inst
.operands
[1].reg
== REG_PC
)
17632 as_tsktsk (MVE_BAD_PC
);
17633 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17634 as_tsktsk (MVE_BAD_SP
);
17637 /* These instructions are one of the "exceptions" mentioned in
17638 handle_pred_state. They are MVE instructions that are not VPT compatible
17639 and do not accept a VPT code, thus appending such a code is a syntax
17641 if (inst
.cond
> COND_ALWAYS
)
17642 first_error (BAD_SYNTAX
);
17643 /* If we append a scalar condition code we can set this to
17644 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17645 else if (inst
.cond
< COND_ALWAYS
)
17646 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17648 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
17650 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17651 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17652 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17653 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17654 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
17659 do_mve_vaddlv (void)
17661 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
17662 struct neon_type_el et
17663 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17665 if (et
.type
== NT_invtype
)
17666 first_error (BAD_EL_TYPE
);
17668 if (inst
.cond
> COND_ALWAYS
)
17669 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17671 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17673 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17675 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17676 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17677 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17678 inst
.instruction
|= inst
.operands
[2].reg
;
17683 do_neon_dyadic_if_su (void)
17685 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17686 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17689 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17690 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17691 && et
.type
== NT_float
17692 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17694 if (!check_simd_pred_availability (et
.type
== NT_float
,
17695 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17698 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17702 do_neon_addsub_if_i (void)
17704 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17705 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17708 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17709 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17710 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17712 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17713 /* If we are parsing Q registers and the element types match MVE, which NEON
17714 also supports, then we must check whether this is an instruction that can
17715 be used by both MVE/NEON. This distinction can be made based on whether
17716 they are predicated or not. */
17717 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17719 if (!check_simd_pred_availability (et
.type
== NT_float
,
17720 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17725 /* If they are either in a D register or are using an unsupported. */
17727 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17731 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17732 affected if we specify unsigned args. */
17733 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17736 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17738 V<op> A,B (A is operand 0, B is operand 2)
17743 so handle that case specially. */
17746 neon_exchange_operands (void)
17748 if (inst
.operands
[1].present
)
17750 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17752 /* Swap operands[1] and operands[2]. */
17753 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17754 inst
.operands
[1] = inst
.operands
[2];
17755 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17760 inst
.operands
[1] = inst
.operands
[2];
17761 inst
.operands
[2] = inst
.operands
[0];
17766 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17768 if (inst
.operands
[2].isreg
)
17771 neon_exchange_operands ();
17772 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17776 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17777 struct neon_type_el et
= neon_check_type (2, rs
,
17778 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17780 NEON_ENCODE (IMMED
, inst
);
17781 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17782 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17783 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17784 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17785 inst
.instruction
|= neon_quad (rs
) << 6;
17786 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17787 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17789 neon_dp_fixup (&inst
);
17796 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
17800 do_neon_cmp_inv (void)
17802 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
17808 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
17811 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17812 scalars, which are encoded in 5 bits, M : Rm.
17813 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17814 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17817 Dot Product instructions are similar to multiply instructions except elsize
17818 should always be 32.
17820 This function translates SCALAR, which is GAS's internal encoding of indexed
17821 scalar register, to raw encoding. There is also register and index range
17822 check based on ELSIZE. */
17825 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17827 unsigned regno
= NEON_SCALAR_REG (scalar
);
17828 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17833 if (regno
> 7 || elno
> 3)
17835 return regno
| (elno
<< 3);
17838 if (regno
> 15 || elno
> 1)
17840 return regno
| (elno
<< 4);
17844 first_error (_("scalar out of range for multiply instruction"));
17850 /* Encode multiply / multiply-accumulate scalar instructions. */
17853 neon_mul_mac (struct neon_type_el et
, int ubit
)
17857 /* Give a more helpful error message if we have an invalid type. */
17858 if (et
.type
== NT_invtype
)
17861 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17862 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17863 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17864 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17865 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17866 inst
.instruction
|= LOW4 (scalar
);
17867 inst
.instruction
|= HI1 (scalar
) << 5;
17868 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17869 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17870 inst
.instruction
|= (ubit
!= 0) << 24;
17872 neon_dp_fixup (&inst
);
17876 do_neon_mac_maybe_scalar (void)
17878 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17881 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17884 if (inst
.operands
[2].isscalar
)
17886 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17887 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17888 struct neon_type_el et
= neon_check_type (3, rs
,
17889 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17890 NEON_ENCODE (SCALAR
, inst
);
17891 neon_mul_mac (et
, neon_quad (rs
));
17893 else if (!inst
.operands
[2].isvec
)
17895 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17897 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17898 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17900 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17904 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17905 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17906 affected if we specify unsigned args. */
17907 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17912 do_bfloat_vfma (void)
17914 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
17915 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
17916 enum neon_shape rs
;
17919 if (inst
.instruction
!= B_MNEM_vfmab
)
17922 inst
.instruction
= B_MNEM_vfmat
;
17925 if (inst
.operands
[2].isscalar
)
17927 rs
= neon_select_shape (NS_QQS
, NS_NULL
);
17928 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
17930 inst
.instruction
|= (1 << 25);
17931 int index
= inst
.operands
[2].reg
& 0xf;
17932 constraint (!(index
< 4), _("index must be in the range 0 to 3"));
17933 inst
.operands
[2].reg
>>= 4;
17934 constraint (!(inst
.operands
[2].reg
< 8),
17935 _("indexed register must be less than 8"));
17936 neon_three_args (t_bit
);
17937 inst
.instruction
|= ((index
& 1) << 3);
17938 inst
.instruction
|= ((index
& 2) << 4);
17942 rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17943 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
17944 neon_three_args (t_bit
);
17950 do_neon_fmac (void)
17952 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17953 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17956 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17959 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17961 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17962 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17968 if (inst
.operands
[2].reg
== REG_SP
)
17969 as_tsktsk (MVE_BAD_SP
);
17970 else if (inst
.operands
[2].reg
== REG_PC
)
17971 as_tsktsk (MVE_BAD_PC
);
17973 inst
.instruction
= 0xee310e40;
17974 inst
.instruction
|= (et
.size
== 16) << 28;
17975 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17976 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17977 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17978 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17979 inst
.instruction
|= inst
.operands
[2].reg
;
17986 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17989 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17995 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_bf16
) &&
17996 inst
.cond
== COND_ALWAYS
)
17998 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17999 inst
.instruction
= N_MNEM_vfma
;
18000 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18002 return do_neon_fmac();
18013 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18014 struct neon_type_el et
= neon_check_type (3, rs
,
18015 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18016 neon_three_same (neon_quad (rs
), 0, et
.size
);
18019 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
18020 same types as the MAC equivalents. The polynomial type for this instruction
18021 is encoded the same as the integer type. */
18026 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
18029 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18032 if (inst
.operands
[2].isscalar
)
18034 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18035 do_neon_mac_maybe_scalar ();
18039 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18041 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
18042 struct neon_type_el et
18043 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
18044 if (et
.type
== NT_float
)
18045 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
18048 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
18052 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
18053 neon_dyadic_misc (NT_poly
,
18054 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
18060 do_neon_qdmulh (void)
18062 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18065 if (inst
.operands
[2].isscalar
)
18067 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18068 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18069 struct neon_type_el et
= neon_check_type (3, rs
,
18070 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18071 NEON_ENCODE (SCALAR
, inst
);
18072 neon_mul_mac (et
, neon_quad (rs
));
18076 enum neon_shape rs
;
18077 struct neon_type_el et
;
18078 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18080 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
18081 et
= neon_check_type (3, rs
,
18082 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18086 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18087 et
= neon_check_type (3, rs
,
18088 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18091 NEON_ENCODE (INTEGER
, inst
);
18093 mve_encode_qqr (et
.size
, 0, 0);
18095 /* The U bit (rounding) comes from bit mask. */
18096 neon_three_same (neon_quad (rs
), 0, et
.size
);
18101 do_mve_vaddv (void)
18103 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18104 struct neon_type_el et
18105 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
18107 if (et
.type
== NT_invtype
)
18108 first_error (BAD_EL_TYPE
);
18110 if (inst
.cond
> COND_ALWAYS
)
18111 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18113 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18115 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
18117 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18121 do_mve_vhcadd (void)
18123 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
18124 struct neon_type_el et
18125 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18127 if (inst
.cond
> COND_ALWAYS
)
18128 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18130 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18132 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
18133 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
18135 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
18136 as_tsktsk (_("Warning: 32-bit element size and same first and third "
18137 "operand makes instruction UNPREDICTABLE"));
18139 mve_encode_qqq (0, et
.size
);
18140 inst
.instruction
|= (rot
== 270) << 12;
18145 do_mve_vqdmull (void)
18147 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
18148 struct neon_type_el et
18149 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18152 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18153 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
18154 as_tsktsk (BAD_MVE_SRCDEST
);
18156 if (inst
.cond
> COND_ALWAYS
)
18157 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18159 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18163 mve_encode_qqq (et
.size
== 32, 64);
18164 inst
.instruction
|= 1;
18168 mve_encode_qqr (64, et
.size
== 32, 0);
18169 inst
.instruction
|= 0x3 << 5;
18176 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18177 struct neon_type_el et
18178 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
18180 if (et
.type
== NT_invtype
)
18181 first_error (BAD_EL_TYPE
);
18183 if (inst
.cond
> COND_ALWAYS
)
18184 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18186 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18188 mve_encode_qqq (0, 64);
18192 do_mve_vbrsr (void)
18194 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18195 struct neon_type_el et
18196 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18198 if (inst
.cond
> COND_ALWAYS
)
18199 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18201 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18203 mve_encode_qqr (et
.size
, 0, 0);
18209 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
18211 if (inst
.cond
> COND_ALWAYS
)
18212 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18214 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18216 mve_encode_qqq (1, 64);
18220 do_mve_vmulh (void)
18222 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18223 struct neon_type_el et
18224 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18226 if (inst
.cond
> COND_ALWAYS
)
18227 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18229 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18231 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18235 do_mve_vqdmlah (void)
18237 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18238 struct neon_type_el et
18239 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18241 if (inst
.cond
> COND_ALWAYS
)
18242 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18244 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18246 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18250 do_mve_vqdmladh (void)
18252 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18253 struct neon_type_el et
18254 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18256 if (inst
.cond
> COND_ALWAYS
)
18257 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18259 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18261 mve_encode_qqq (0, et
.size
);
18266 do_mve_vmull (void)
18269 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
18270 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
18271 if (inst
.cond
== COND_ALWAYS
18272 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
18277 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18284 constraint (rs
!= NS_QQQ
, BAD_FPU
);
18285 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18286 N_SU_32
| N_P8
| N_P16
| N_KEY
);
18288 /* We are dealing with MVE's vmullt. */
18290 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18291 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
18292 as_tsktsk (BAD_MVE_SRCDEST
);
18294 if (inst
.cond
> COND_ALWAYS
)
18295 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18297 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18299 if (et
.type
== NT_poly
)
18300 mve_encode_qqq (neon_logbits (et
.size
), 64);
18302 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18307 inst
.instruction
= N_MNEM_vmul
;
18310 inst
.pred_insn_type
= INSIDE_IT_INSN
;
18315 do_mve_vabav (void)
18317 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18322 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18325 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
18326 | N_S16
| N_S32
| N_U8
| N_U16
18329 if (inst
.cond
> COND_ALWAYS
)
18330 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18332 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18334 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
18338 do_mve_vmladav (void)
18340 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18341 struct neon_type_el et
= neon_check_type (3, rs
,
18342 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18344 if (et
.type
== NT_unsigned
18345 && (inst
.instruction
== M_MNEM_vmladavx
18346 || inst
.instruction
== M_MNEM_vmladavax
18347 || inst
.instruction
== M_MNEM_vmlsdav
18348 || inst
.instruction
== M_MNEM_vmlsdava
18349 || inst
.instruction
== M_MNEM_vmlsdavx
18350 || inst
.instruction
== M_MNEM_vmlsdavax
))
18351 first_error (BAD_SIMD_TYPE
);
18353 constraint (inst
.operands
[2].reg
> 14,
18354 _("MVE vector register in the range [Q0..Q7] expected"));
18356 if (inst
.cond
> COND_ALWAYS
)
18357 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18359 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18361 if (inst
.instruction
== M_MNEM_vmlsdav
18362 || inst
.instruction
== M_MNEM_vmlsdava
18363 || inst
.instruction
== M_MNEM_vmlsdavx
18364 || inst
.instruction
== M_MNEM_vmlsdavax
)
18365 inst
.instruction
|= (et
.size
== 8) << 28;
18367 inst
.instruction
|= (et
.size
== 8) << 8;
18369 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
18370 inst
.instruction
|= (et
.size
== 32) << 16;
18374 do_mve_vmlaldav (void)
18376 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
18377 struct neon_type_el et
18378 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
18379 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
18381 if (et
.type
== NT_unsigned
18382 && (inst
.instruction
== M_MNEM_vmlsldav
18383 || inst
.instruction
== M_MNEM_vmlsldava
18384 || inst
.instruction
== M_MNEM_vmlsldavx
18385 || inst
.instruction
== M_MNEM_vmlsldavax
))
18386 first_error (BAD_SIMD_TYPE
);
18388 if (inst
.cond
> COND_ALWAYS
)
18389 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18391 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18393 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
18397 do_mve_vrmlaldavh (void)
18399 struct neon_type_el et
;
18400 if (inst
.instruction
== M_MNEM_vrmlsldavh
18401 || inst
.instruction
== M_MNEM_vrmlsldavha
18402 || inst
.instruction
== M_MNEM_vrmlsldavhx
18403 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
18405 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18406 if (inst
.operands
[1].reg
== REG_SP
)
18407 as_tsktsk (MVE_BAD_SP
);
18411 if (inst
.instruction
== M_MNEM_vrmlaldavhx
18412 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
18413 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18415 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
18416 N_U32
| N_S32
| N_KEY
);
18417 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18418 with vmax/min instructions, making the use of SP in assembly really
18419 nonsensical, so instead of issuing a warning like we do for other uses
18420 of SP for the odd register operand we error out. */
18421 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
18424 /* Make sure we still check the second operand is an odd one and that PC is
18425 disallowed. This because we are parsing for any GPR operand, to be able
18426 to distinguish between giving a warning or an error for SP as described
18428 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
18429 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
18431 if (inst
.cond
> COND_ALWAYS
)
18432 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18434 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18436 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
18441 do_mve_vmaxnmv (void)
18443 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18444 struct neon_type_el et
18445 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
18447 if (inst
.cond
> COND_ALWAYS
)
18448 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18450 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18452 if (inst
.operands
[0].reg
== REG_SP
)
18453 as_tsktsk (MVE_BAD_SP
);
18454 else if (inst
.operands
[0].reg
== REG_PC
)
18455 as_tsktsk (MVE_BAD_PC
);
18457 mve_encode_rq (et
.size
== 16, 64);
18461 do_mve_vmaxv (void)
18463 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18464 struct neon_type_el et
;
18466 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
18467 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
18469 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18471 if (inst
.cond
> COND_ALWAYS
)
18472 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18474 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18476 if (inst
.operands
[0].reg
== REG_SP
)
18477 as_tsktsk (MVE_BAD_SP
);
18478 else if (inst
.operands
[0].reg
== REG_PC
)
18479 as_tsktsk (MVE_BAD_PC
);
18481 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18486 do_neon_qrdmlah (void)
18488 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18490 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18492 /* Check we're on the correct architecture. */
18493 if (!mark_feature_used (&fpu_neon_ext_armv8
))
18495 = _("instruction form not available on this architecture.");
18496 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
18498 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18499 record_feature_use (&fpu_neon_ext_v8_1
);
18501 if (inst
.operands
[2].isscalar
)
18503 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18504 struct neon_type_el et
= neon_check_type (3, rs
,
18505 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18506 NEON_ENCODE (SCALAR
, inst
);
18507 neon_mul_mac (et
, neon_quad (rs
));
18511 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18512 struct neon_type_el et
= neon_check_type (3, rs
,
18513 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18514 NEON_ENCODE (INTEGER
, inst
);
18515 /* The U bit (rounding) comes from bit mask. */
18516 neon_three_same (neon_quad (rs
), 0, et
.size
);
18521 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18522 struct neon_type_el et
18523 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18525 NEON_ENCODE (INTEGER
, inst
);
18526 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18531 do_neon_fcmp_absolute (void)
18533 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18534 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18535 N_F_16_32
| N_KEY
);
18536 /* Size field comes from bit mask. */
18537 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
18541 do_neon_fcmp_absolute_inv (void)
18543 neon_exchange_operands ();
18544 do_neon_fcmp_absolute ();
18548 do_neon_step (void)
18550 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18551 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18552 N_F_16_32
| N_KEY
);
18553 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
18557 do_neon_abs_neg (void)
18559 enum neon_shape rs
;
18560 struct neon_type_el et
;
18562 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
18565 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18566 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
18568 if (!check_simd_pred_availability (et
.type
== NT_float
,
18569 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18572 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18573 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18574 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18575 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18576 inst
.instruction
|= neon_quad (rs
) << 6;
18577 inst
.instruction
|= (et
.type
== NT_float
) << 10;
18578 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18580 neon_dp_fixup (&inst
);
18586 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18589 enum neon_shape rs
;
18590 struct neon_type_el et
;
18591 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18593 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18594 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18598 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18599 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18603 int imm
= inst
.operands
[2].imm
;
18604 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18605 _("immediate out of range for insert"));
18606 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18612 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18615 enum neon_shape rs
;
18616 struct neon_type_el et
;
18617 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18619 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18620 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18624 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18625 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18628 int imm
= inst
.operands
[2].imm
;
18629 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18630 _("immediate out of range for insert"));
18631 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
18635 do_neon_qshlu_imm (void)
18637 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18640 enum neon_shape rs
;
18641 struct neon_type_el et
;
18642 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18644 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18645 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18649 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18650 et
= neon_check_type (2, rs
, N_EQK
| N_UNS
,
18651 N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
18654 int imm
= inst
.operands
[2].imm
;
18655 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18656 _("immediate out of range for shift"));
18657 /* Only encodes the 'U present' variant of the instruction.
18658 In this case, signed types have OP (bit 8) set to 0.
18659 Unsigned types have OP set to 1. */
18660 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
18661 /* The rest of the bits are the same as other immediate shifts. */
18662 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18666 do_neon_qmovn (void)
18668 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18669 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18670 /* Saturating move where operands can be signed or unsigned, and the
18671 destination has the same signedness. */
18672 NEON_ENCODE (INTEGER
, inst
);
18673 if (et
.type
== NT_unsigned
)
18674 inst
.instruction
|= 0xc0;
18676 inst
.instruction
|= 0x80;
18677 neon_two_same (0, 1, et
.size
/ 2);
18681 do_neon_qmovun (void)
18683 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18684 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18685 /* Saturating move with unsigned results. Operands must be signed. */
18686 NEON_ENCODE (INTEGER
, inst
);
18687 neon_two_same (0, 1, et
.size
/ 2);
18691 do_neon_rshift_sat_narrow (void)
18693 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18694 or unsigned. If operands are unsigned, results must also be unsigned. */
18695 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18696 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18697 int imm
= inst
.operands
[2].imm
;
18698 /* This gets the bounds check, size encoding and immediate bits calculation
18702 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18703 VQMOVN.I<size> <Dd>, <Qm>. */
18706 inst
.operands
[2].present
= 0;
18707 inst
.instruction
= N_MNEM_vqmovn
;
18712 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18713 _("immediate out of range"));
18714 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
18718 do_neon_rshift_sat_narrow_u (void)
18720 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18721 or unsigned. If operands are unsigned, results must also be unsigned. */
18722 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18723 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18724 int imm
= inst
.operands
[2].imm
;
18725 /* This gets the bounds check, size encoding and immediate bits calculation
18729 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18730 VQMOVUN.I<size> <Dd>, <Qm>. */
18733 inst
.operands
[2].present
= 0;
18734 inst
.instruction
= N_MNEM_vqmovun
;
18739 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18740 _("immediate out of range"));
18741 /* FIXME: The manual is kind of unclear about what value U should have in
18742 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18744 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
18748 do_neon_movn (void)
18750 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18751 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18752 NEON_ENCODE (INTEGER
, inst
);
18753 neon_two_same (0, 1, et
.size
/ 2);
18757 do_neon_rshift_narrow (void)
18759 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18760 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18761 int imm
= inst
.operands
[2].imm
;
18762 /* This gets the bounds check, size encoding and immediate bits calculation
18766 /* If immediate is zero then we are a pseudo-instruction for
18767 VMOVN.I<size> <Dd>, <Qm> */
18770 inst
.operands
[2].present
= 0;
18771 inst
.instruction
= N_MNEM_vmovn
;
18776 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18777 _("immediate out of range for narrowing operation"));
18778 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
18782 do_neon_shll (void)
18784 /* FIXME: Type checking when lengthening. */
18785 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18786 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18787 unsigned imm
= inst
.operands
[2].imm
;
18789 if (imm
== et
.size
)
18791 /* Maximum shift variant. */
18792 NEON_ENCODE (INTEGER
, inst
);
18793 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18794 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18795 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18796 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18797 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18799 neon_dp_fixup (&inst
);
18803 /* A more-specific type check for non-max versions. */
18804 et
= neon_check_type (2, NS_QDI
,
18805 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18806 NEON_ENCODE (IMMED
, inst
);
18807 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
18811 /* Check the various types for the VCVT instruction, and return which version
18812 the current instruction is. */
18814 #define CVT_FLAVOUR_VAR \
18815 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18816 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18817 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18818 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18819 /* Half-precision conversions. */ \
18820 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18821 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18822 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18823 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18824 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18825 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18826 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18827 Compared with single/double precision variants, only the co-processor \
18828 field is different, so the encoding flow is reused here. */ \
18829 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18830 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18831 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18832 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18833 CVT_VAR (bf16_f32, N_BF16, N_F32, whole_reg, NULL, NULL, NULL) \
18834 /* VFP instructions. */ \
18835 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18836 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18837 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18838 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18839 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18840 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18841 /* VFP instructions with bitshift. */ \
18842 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18843 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18844 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18845 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18846 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18847 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18848 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18849 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18851 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18852 neon_cvt_flavour_##C,
18854 /* The different types of conversions we can do. */
18855 enum neon_cvt_flavour
18858 neon_cvt_flavour_invalid
,
18859 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18864 static enum neon_cvt_flavour
18865 get_neon_cvt_flavour (enum neon_shape rs
)
18867 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18868 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18869 if (et.type != NT_invtype) \
18871 inst.error = NULL; \
18872 return (neon_cvt_flavour_##C); \
18875 struct neon_type_el et
;
18876 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18877 || rs
== NS_FF
) ? N_VFP
: 0;
18878 /* The instruction versions which take an immediate take one register
18879 argument, which is extended to the width of the full register. Thus the
18880 "source" and "destination" registers must have the same width. Hack that
18881 here by making the size equal to the key (wider, in this case) operand. */
18882 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18886 return neon_cvt_flavour_invalid
;
18901 /* Neon-syntax VFP conversions. */
18904 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18906 const char *opname
= 0;
18908 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18909 || rs
== NS_FHI
|| rs
== NS_HFI
)
18911 /* Conversions with immediate bitshift. */
18912 const char *enc
[] =
18914 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18920 if (flavour
< (int) ARRAY_SIZE (enc
))
18922 opname
= enc
[flavour
];
18923 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18924 _("operands 0 and 1 must be the same register"));
18925 inst
.operands
[1] = inst
.operands
[2];
18926 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18931 /* Conversions without bitshift. */
18932 const char *enc
[] =
18934 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18940 if (flavour
< (int) ARRAY_SIZE (enc
))
18941 opname
= enc
[flavour
];
18945 do_vfp_nsyn_opcode (opname
);
18947 /* ARMv8.2 fp16 VCVT instruction. */
18948 if (flavour
== neon_cvt_flavour_s32_f16
18949 || flavour
== neon_cvt_flavour_u32_f16
18950 || flavour
== neon_cvt_flavour_f16_u32
18951 || flavour
== neon_cvt_flavour_f16_s32
)
18952 do_scalar_fp16_v82_encode ();
18956 do_vfp_nsyn_cvtz (void)
18958 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18959 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18960 const char *enc
[] =
18962 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18968 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18969 do_vfp_nsyn_opcode (enc
[flavour
]);
18973 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18974 enum neon_cvt_mode mode
)
18979 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18980 D register operands. */
18981 if (flavour
== neon_cvt_flavour_s32_f64
18982 || flavour
== neon_cvt_flavour_u32_f64
)
18983 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18986 if (flavour
== neon_cvt_flavour_s32_f16
18987 || flavour
== neon_cvt_flavour_u32_f16
)
18988 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18991 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18995 case neon_cvt_flavour_s32_f64
:
18999 case neon_cvt_flavour_s32_f32
:
19003 case neon_cvt_flavour_s32_f16
:
19007 case neon_cvt_flavour_u32_f64
:
19011 case neon_cvt_flavour_u32_f32
:
19015 case neon_cvt_flavour_u32_f16
:
19020 first_error (_("invalid instruction shape"));
19026 case neon_cvt_mode_a
: rm
= 0; break;
19027 case neon_cvt_mode_n
: rm
= 1; break;
19028 case neon_cvt_mode_p
: rm
= 2; break;
19029 case neon_cvt_mode_m
: rm
= 3; break;
19030 default: first_error (_("invalid rounding mode")); return;
19033 NEON_ENCODE (FPV8
, inst
);
19034 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
19035 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
19036 inst
.instruction
|= sz
<< 8;
19038 /* ARMv8.2 fp16 VCVT instruction. */
19039 if (flavour
== neon_cvt_flavour_s32_f16
19040 ||flavour
== neon_cvt_flavour_u32_f16
)
19041 do_scalar_fp16_v82_encode ();
19042 inst
.instruction
|= op
<< 7;
19043 inst
.instruction
|= rm
<< 16;
19044 inst
.instruction
|= 0xf0000000;
19045 inst
.is_neon
= TRUE
;
19049 do_neon_cvt_1 (enum neon_cvt_mode mode
)
19051 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
19052 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
19053 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
19055 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19057 if (flavour
== neon_cvt_flavour_invalid
)
19060 /* PR11109: Handle round-to-zero for VCVT conversions. */
19061 if (mode
== neon_cvt_mode_z
19062 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
19063 && (flavour
== neon_cvt_flavour_s16_f16
19064 || flavour
== neon_cvt_flavour_u16_f16
19065 || flavour
== neon_cvt_flavour_s32_f32
19066 || flavour
== neon_cvt_flavour_u32_f32
19067 || flavour
== neon_cvt_flavour_s32_f64
19068 || flavour
== neon_cvt_flavour_u32_f64
)
19069 && (rs
== NS_FD
|| rs
== NS_FF
))
19071 do_vfp_nsyn_cvtz ();
19075 /* ARMv8.2 fp16 VCVT conversions. */
19076 if (mode
== neon_cvt_mode_z
19077 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
19078 && (flavour
== neon_cvt_flavour_s32_f16
19079 || flavour
== neon_cvt_flavour_u32_f16
)
19082 do_vfp_nsyn_cvtz ();
19083 do_scalar_fp16_v82_encode ();
19087 if ((rs
== NS_FD
|| rs
== NS_QQI
) && mode
== neon_cvt_mode_n
19088 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19090 /* We are dealing with vcvt with the 'ne' condition. */
19092 inst
.instruction
= N_MNEM_vcvt
;
19093 do_neon_cvt_1 (neon_cvt_mode_z
);
19097 /* VFP rather than Neon conversions. */
19098 if (flavour
>= neon_cvt_flavour_first_fp
)
19100 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19101 do_vfp_nsyn_cvt (rs
, flavour
);
19103 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19111 if (mode
== neon_cvt_mode_z
19112 && (flavour
== neon_cvt_flavour_f16_s16
19113 || flavour
== neon_cvt_flavour_f16_u16
19114 || flavour
== neon_cvt_flavour_s16_f16
19115 || flavour
== neon_cvt_flavour_u16_f16
19116 || flavour
== neon_cvt_flavour_f32_u32
19117 || flavour
== neon_cvt_flavour_f32_s32
19118 || flavour
== neon_cvt_flavour_s32_f32
19119 || flavour
== neon_cvt_flavour_u32_f32
))
19121 if (!check_simd_pred_availability (TRUE
,
19122 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19125 /* fall through. */
19129 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
19130 0x0000100, 0x1000100, 0x0, 0x1000000};
19132 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19133 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19136 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19138 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
19139 _("immediate value out of range"));
19142 case neon_cvt_flavour_f16_s16
:
19143 case neon_cvt_flavour_f16_u16
:
19144 case neon_cvt_flavour_s16_f16
:
19145 case neon_cvt_flavour_u16_f16
:
19146 constraint (inst
.operands
[2].imm
> 16,
19147 _("immediate value out of range"));
19149 case neon_cvt_flavour_f32_u32
:
19150 case neon_cvt_flavour_f32_s32
:
19151 case neon_cvt_flavour_s32_f32
:
19152 case neon_cvt_flavour_u32_f32
:
19153 constraint (inst
.operands
[2].imm
> 32,
19154 _("immediate value out of range"));
19157 inst
.error
= BAD_FPU
;
19162 /* Fixed-point conversion with #0 immediate is encoded as an
19163 integer conversion. */
19164 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
19166 NEON_ENCODE (IMMED
, inst
);
19167 if (flavour
!= neon_cvt_flavour_invalid
)
19168 inst
.instruction
|= enctab
[flavour
];
19169 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19170 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19171 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19172 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19173 inst
.instruction
|= neon_quad (rs
) << 6;
19174 inst
.instruction
|= 1 << 21;
19175 if (flavour
< neon_cvt_flavour_s16_f16
)
19177 inst
.instruction
|= 1 << 21;
19178 immbits
= 32 - inst
.operands
[2].imm
;
19179 inst
.instruction
|= immbits
<< 16;
19183 inst
.instruction
|= 3 << 20;
19184 immbits
= 16 - inst
.operands
[2].imm
;
19185 inst
.instruction
|= immbits
<< 16;
19186 inst
.instruction
&= ~(1 << 9);
19189 neon_dp_fixup (&inst
);
19194 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
19195 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
19196 && (flavour
== neon_cvt_flavour_s16_f16
19197 || flavour
== neon_cvt_flavour_u16_f16
19198 || flavour
== neon_cvt_flavour_s32_f32
19199 || flavour
== neon_cvt_flavour_u32_f32
))
19201 if (!check_simd_pred_availability (TRUE
,
19202 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19205 else if (mode
== neon_cvt_mode_z
19206 && (flavour
== neon_cvt_flavour_f16_s16
19207 || flavour
== neon_cvt_flavour_f16_u16
19208 || flavour
== neon_cvt_flavour_s16_f16
19209 || flavour
== neon_cvt_flavour_u16_f16
19210 || flavour
== neon_cvt_flavour_f32_u32
19211 || flavour
== neon_cvt_flavour_f32_s32
19212 || flavour
== neon_cvt_flavour_s32_f32
19213 || flavour
== neon_cvt_flavour_u32_f32
))
19215 if (!check_simd_pred_availability (TRUE
,
19216 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19219 /* fall through. */
19221 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
19224 NEON_ENCODE (FLOAT
, inst
);
19225 if (!check_simd_pred_availability (TRUE
,
19226 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19229 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19230 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19231 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19232 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19233 inst
.instruction
|= neon_quad (rs
) << 6;
19234 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
19235 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
19236 inst
.instruction
|= mode
<< 8;
19237 if (flavour
== neon_cvt_flavour_u16_f16
19238 || flavour
== neon_cvt_flavour_s16_f16
)
19239 /* Mask off the original size bits and reencode them. */
19240 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
19243 inst
.instruction
|= 0xfc000000;
19245 inst
.instruction
|= 0xf0000000;
19251 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
19252 0x100, 0x180, 0x0, 0x080};
19254 NEON_ENCODE (INTEGER
, inst
);
19256 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19258 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19262 if (flavour
!= neon_cvt_flavour_invalid
)
19263 inst
.instruction
|= enctab
[flavour
];
19265 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19266 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19267 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19268 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19269 inst
.instruction
|= neon_quad (rs
) << 6;
19270 if (flavour
>= neon_cvt_flavour_s16_f16
19271 && flavour
<= neon_cvt_flavour_f16_u16
)
19272 /* Half precision. */
19273 inst
.instruction
|= 1 << 18;
19275 inst
.instruction
|= 2 << 18;
19277 neon_dp_fixup (&inst
);
19282 /* Half-precision conversions for Advanced SIMD -- neon. */
19285 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19289 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
19291 as_bad (_("operand size must match register width"));
19296 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
19298 as_bad (_("operand size must match register width"));
19304 if (flavour
== neon_cvt_flavour_bf16_f32
)
19306 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH8
) == FAIL
)
19308 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
19309 /* VCVT.bf16.f32. */
19310 inst
.instruction
= 0x11b60640;
19313 /* VCVT.f16.f32. */
19314 inst
.instruction
= 0x3b60600;
19317 /* VCVT.f32.f16. */
19318 inst
.instruction
= 0x3b60700;
19320 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19321 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19322 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19323 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19324 neon_dp_fixup (&inst
);
19328 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
19329 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19330 do_vfp_nsyn_cvt (rs
, flavour
);
19332 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19337 do_neon_cvtr (void)
19339 do_neon_cvt_1 (neon_cvt_mode_x
);
19345 do_neon_cvt_1 (neon_cvt_mode_z
);
19349 do_neon_cvta (void)
19351 do_neon_cvt_1 (neon_cvt_mode_a
);
19355 do_neon_cvtn (void)
19357 do_neon_cvt_1 (neon_cvt_mode_n
);
19361 do_neon_cvtp (void)
19363 do_neon_cvt_1 (neon_cvt_mode_p
);
19367 do_neon_cvtm (void)
19369 do_neon_cvt_1 (neon_cvt_mode_m
);
19373 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
19376 mark_feature_used (&fpu_vfp_ext_armv8
);
19378 encode_arm_vfp_reg (inst
.operands
[0].reg
,
19379 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
19380 encode_arm_vfp_reg (inst
.operands
[1].reg
,
19381 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
19382 inst
.instruction
|= to
? 0x10000 : 0;
19383 inst
.instruction
|= t
? 0x80 : 0;
19384 inst
.instruction
|= is_double
? 0x100 : 0;
19385 do_vfp_cond_or_thumb ();
19389 do_neon_cvttb_1 (bfd_boolean t
)
19391 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
19392 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
19396 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
19398 int single_to_half
= 0;
19399 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_ARCH
))
19402 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19404 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19405 && (flavour
== neon_cvt_flavour_u16_f16
19406 || flavour
== neon_cvt_flavour_s16_f16
19407 || flavour
== neon_cvt_flavour_f16_s16
19408 || flavour
== neon_cvt_flavour_f16_u16
19409 || flavour
== neon_cvt_flavour_u32_f32
19410 || flavour
== neon_cvt_flavour_s32_f32
19411 || flavour
== neon_cvt_flavour_f32_s32
19412 || flavour
== neon_cvt_flavour_f32_u32
))
19415 inst
.instruction
= N_MNEM_vcvt
;
19416 set_pred_insn_type (INSIDE_VPT_INSN
);
19417 do_neon_cvt_1 (neon_cvt_mode_z
);
19420 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
19421 single_to_half
= 1;
19422 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
19424 first_error (BAD_FPU
);
19428 inst
.instruction
= 0xee3f0e01;
19429 inst
.instruction
|= single_to_half
<< 28;
19430 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19431 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
19432 inst
.instruction
|= t
<< 12;
19433 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19434 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
19437 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
19440 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19442 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
19445 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
19447 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
19449 /* The VCVTB and VCVTT instructions with D-register operands
19450 don't work for SP only targets. */
19451 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19455 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
19457 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
19459 /* The VCVTB and VCVTT instructions with D-register operands
19460 don't work for SP only targets. */
19461 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19465 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
19467 else if (neon_check_type (2, rs
, N_BF16
| N_VFP
, N_F32
).type
!= NT_invtype
)
19469 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
19471 inst
.instruction
|= (1 << 8);
19472 inst
.instruction
&= ~(1 << 9);
19473 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19480 do_neon_cvtb (void)
19482 do_neon_cvttb_1 (FALSE
);
19487 do_neon_cvtt (void)
19489 do_neon_cvttb_1 (TRUE
);
19493 neon_move_immediate (void)
19495 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
19496 struct neon_type_el et
= neon_check_type (2, rs
,
19497 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
19498 unsigned immlo
, immhi
= 0, immbits
;
19499 int op
, cmode
, float_p
;
19501 constraint (et
.type
== NT_invtype
,
19502 _("operand size must be specified for immediate VMOV"));
19504 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19505 op
= (inst
.instruction
& (1 << 5)) != 0;
19507 immlo
= inst
.operands
[1].imm
;
19508 if (inst
.operands
[1].regisimm
)
19509 immhi
= inst
.operands
[1].reg
;
19511 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
19512 _("immediate has bits set outside the operand size"));
19514 float_p
= inst
.operands
[1].immisfloat
;
19516 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
19517 et
.size
, et
.type
)) == FAIL
)
19519 /* Invert relevant bits only. */
19520 neon_invert_size (&immlo
, &immhi
, et
.size
);
19521 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
19522 with one or the other; those cases are caught by
19523 neon_cmode_for_move_imm. */
19525 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
19526 &op
, et
.size
, et
.type
)) == FAIL
)
19528 first_error (_("immediate out of range"));
19533 inst
.instruction
&= ~(1 << 5);
19534 inst
.instruction
|= op
<< 5;
19536 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19537 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19538 inst
.instruction
|= neon_quad (rs
) << 6;
19539 inst
.instruction
|= cmode
<< 8;
19541 neon_write_immbits (immbits
);
19547 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19550 if (inst
.operands
[1].isreg
)
19552 enum neon_shape rs
;
19553 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19554 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19556 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19561 NEON_ENCODE (INTEGER
, inst
);
19562 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19563 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19564 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19565 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19566 inst
.instruction
|= neon_quad (rs
) << 6;
19570 NEON_ENCODE (IMMED
, inst
);
19571 neon_move_immediate ();
19574 neon_dp_fixup (&inst
);
19576 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19578 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
19582 /* Encode instructions of form:
19584 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19585 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19588 neon_mixed_length (struct neon_type_el et
, unsigned size
)
19590 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19591 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19592 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19593 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19594 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19595 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19596 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
19597 inst
.instruction
|= neon_logbits (size
) << 20;
19599 neon_dp_fixup (&inst
);
19603 do_neon_dyadic_long (void)
19605 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
19608 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
19611 NEON_ENCODE (INTEGER
, inst
);
19612 /* FIXME: Type checking for lengthening op. */
19613 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19614 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19615 neon_mixed_length (et
, et
.size
);
19617 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19618 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
19620 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19621 in an IT block with le/lt conditions. */
19623 if (inst
.cond
== 0xf)
19625 else if (inst
.cond
== 0x10)
19628 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19630 if (inst
.instruction
== N_MNEM_vaddl
)
19632 inst
.instruction
= N_MNEM_vadd
;
19633 do_neon_addsub_if_i ();
19635 else if (inst
.instruction
== N_MNEM_vsubl
)
19637 inst
.instruction
= N_MNEM_vsub
;
19638 do_neon_addsub_if_i ();
19640 else if (inst
.instruction
== N_MNEM_vabdl
)
19642 inst
.instruction
= N_MNEM_vabd
;
19643 do_neon_dyadic_if_su ();
19647 first_error (BAD_FPU
);
19651 do_neon_abal (void)
19653 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19654 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19655 neon_mixed_length (et
, et
.size
);
19659 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
19661 if (inst
.operands
[2].isscalar
)
19663 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
19664 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
19665 NEON_ENCODE (SCALAR
, inst
);
19666 neon_mul_mac (et
, et
.type
== NT_unsigned
);
19670 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19671 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
19672 NEON_ENCODE (INTEGER
, inst
);
19673 neon_mixed_length (et
, et
.size
);
19678 do_neon_mac_maybe_scalar_long (void)
19680 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
19683 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19684 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19687 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
19689 unsigned regno
= NEON_SCALAR_REG (scalar
);
19690 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
19694 if (regno
> 7 || elno
> 3)
19697 return ((regno
& 0x7)
19698 | ((elno
& 0x1) << 3)
19699 | (((elno
>> 1) & 0x1) << 5));
19703 if (regno
> 15 || elno
> 1)
19706 return (((regno
& 0x1) << 5)
19707 | ((regno
>> 1) & 0x7)
19708 | ((elno
& 0x1) << 3));
19712 first_error (_("scalar out of range for multiply instruction"));
19717 do_neon_fmac_maybe_scalar_long (int subtype
)
19719 enum neon_shape rs
;
19721 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19722 field (bits[21:20]) has different meaning. For scalar index variant, it's
19723 used to differentiate add and subtract, otherwise it's with fixed value
19727 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19728 be a scalar index register. */
19729 if (inst
.operands
[2].isscalar
)
19731 high8
= 0xfe000000;
19734 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
19738 high8
= 0xfc000000;
19741 inst
.instruction
|= (0x1 << 23);
19742 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19746 if (inst
.cond
!= COND_ALWAYS
)
19747 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19748 "behaviour is UNPREDICTABLE"));
19750 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
19753 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19756 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19757 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19758 so we simply pass -1 as size. */
19759 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19760 neon_three_same (quad_p
, 0, size
);
19762 /* Undo neon_dp_fixup. Redo the high eight bits. */
19763 inst
.instruction
&= 0x00ffffff;
19764 inst
.instruction
|= high8
;
19766 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19767 whether the instruction is in Q form and whether Vm is a scalar indexed
19769 if (inst
.operands
[2].isscalar
)
19772 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19773 inst
.instruction
&= 0xffffffd0;
19774 inst
.instruction
|= rm
;
19778 /* Redo Rn as well. */
19779 inst
.instruction
&= 0xfff0ff7f;
19780 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19781 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19786 /* Redo Rn and Rm. */
19787 inst
.instruction
&= 0xfff0ff50;
19788 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19789 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19790 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19791 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19796 do_neon_vfmal (void)
19798 return do_neon_fmac_maybe_scalar_long (0);
19802 do_neon_vfmsl (void)
19804 return do_neon_fmac_maybe_scalar_long (1);
19808 do_neon_dyadic_wide (void)
19810 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19811 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19812 neon_mixed_length (et
, et
.size
);
19816 do_neon_dyadic_narrow (void)
19818 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19819 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19820 /* Operand sign is unimportant, and the U bit is part of the opcode,
19821 so force the operand type to integer. */
19822 et
.type
= NT_integer
;
19823 neon_mixed_length (et
, et
.size
/ 2);
19827 do_neon_mul_sat_scalar_long (void)
19829 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19833 do_neon_vmull (void)
19835 if (inst
.operands
[2].isscalar
)
19836 do_neon_mac_maybe_scalar_long ();
19839 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19840 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19842 if (et
.type
== NT_poly
)
19843 NEON_ENCODE (POLY
, inst
);
19845 NEON_ENCODE (INTEGER
, inst
);
19847 /* For polynomial encoding the U bit must be zero, and the size must
19848 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19849 obviously, as 0b10). */
19852 /* Check we're on the correct architecture. */
19853 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19855 _("Instruction form not available on this architecture.");
19860 neon_mixed_length (et
, et
.size
);
19867 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19868 struct neon_type_el et
= neon_check_type (3, rs
,
19869 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19870 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19872 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19873 _("shift out of range"));
19874 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19875 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19876 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19877 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19878 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19879 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19880 inst
.instruction
|= neon_quad (rs
) << 6;
19881 inst
.instruction
|= imm
<< 8;
19883 neon_dp_fixup (&inst
);
19889 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19892 enum neon_shape rs
;
19893 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19894 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19896 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19898 struct neon_type_el et
= neon_check_type (2, rs
,
19899 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19901 unsigned op
= (inst
.instruction
>> 7) & 3;
19902 /* N (width of reversed regions) is encoded as part of the bitmask. We
19903 extract it here to check the elements to be reversed are smaller.
19904 Otherwise we'd get a reserved instruction. */
19905 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19907 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19908 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19909 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19910 " operands makes instruction UNPREDICTABLE"));
19912 gas_assert (elsize
!= 0);
19913 constraint (et
.size
>= elsize
,
19914 _("elements must be smaller than reversal region"));
19915 neon_two_same (neon_quad (rs
), 1, et
.size
);
19921 if (inst
.operands
[1].isscalar
)
19923 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19925 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19926 struct neon_type_el et
= neon_check_type (2, rs
,
19927 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19928 unsigned sizebits
= et
.size
>> 3;
19929 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19930 int logsize
= neon_logbits (et
.size
);
19931 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19933 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19936 NEON_ENCODE (SCALAR
, inst
);
19937 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19938 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19939 inst
.instruction
|= LOW4 (dm
);
19940 inst
.instruction
|= HI1 (dm
) << 5;
19941 inst
.instruction
|= neon_quad (rs
) << 6;
19942 inst
.instruction
|= x
<< 17;
19943 inst
.instruction
|= sizebits
<< 16;
19945 neon_dp_fixup (&inst
);
19949 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19950 struct neon_type_el et
= neon_check_type (2, rs
,
19951 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19954 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
))
19958 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19961 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19963 if (inst
.operands
[1].reg
== REG_SP
)
19964 as_tsktsk (MVE_BAD_SP
);
19965 else if (inst
.operands
[1].reg
== REG_PC
)
19966 as_tsktsk (MVE_BAD_PC
);
19969 /* Duplicate ARM register to lanes of vector. */
19970 NEON_ENCODE (ARMREG
, inst
);
19973 case 8: inst
.instruction
|= 0x400000; break;
19974 case 16: inst
.instruction
|= 0x000020; break;
19975 case 32: inst
.instruction
|= 0x000000; break;
19978 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19979 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19980 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19981 inst
.instruction
|= neon_quad (rs
) << 21;
19982 /* The encoding for this instruction is identical for the ARM and Thumb
19983 variants, except for the condition field. */
19984 do_vfp_cond_or_thumb ();
19989 do_mve_mov (int toQ
)
19991 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19993 if (inst
.cond
> COND_ALWAYS
)
19994 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
19996 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
20005 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
20006 _("Index one must be [2,3] and index two must be two less than"
20008 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
20009 _("General purpose registers may not be the same"));
20010 constraint (inst
.operands
[Rt
].reg
== REG_SP
20011 || inst
.operands
[Rt2
].reg
== REG_SP
,
20013 constraint (inst
.operands
[Rt
].reg
== REG_PC
20014 || inst
.operands
[Rt2
].reg
== REG_PC
,
20017 inst
.instruction
= 0xec000f00;
20018 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
20019 inst
.instruction
|= !!toQ
<< 20;
20020 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
20021 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
20022 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
20023 inst
.instruction
|= inst
.operands
[Rt
].reg
;
20029 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20032 if (inst
.cond
> COND_ALWAYS
)
20033 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20035 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
20037 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
20040 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20041 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
20042 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20043 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20044 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20049 /* VMOV has particularly many variations. It can be one of:
20050 0. VMOV<c><q> <Qd>, <Qm>
20051 1. VMOV<c><q> <Dd>, <Dm>
20052 (Register operations, which are VORR with Rm = Rn.)
20053 2. VMOV<c><q>.<dt> <Qd>, #<imm>
20054 3. VMOV<c><q>.<dt> <Dd>, #<imm>
20056 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
20057 (ARM register to scalar.)
20058 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
20059 (Two ARM registers to vector.)
20060 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
20061 (Scalar to ARM register.)
20062 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
20063 (Vector to two ARM registers.)
20064 8. VMOV.F32 <Sd>, <Sm>
20065 9. VMOV.F64 <Dd>, <Dm>
20066 (VFP register moves.)
20067 10. VMOV.F32 <Sd>, #imm
20068 11. VMOV.F64 <Dd>, #imm
20069 (VFP float immediate load.)
20070 12. VMOV <Rd>, <Sm>
20071 (VFP single to ARM reg.)
20072 13. VMOV <Sd>, <Rm>
20073 (ARM reg to VFP single.)
20074 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
20075 (Two ARM regs to two VFP singles.)
20076 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
20077 (Two VFP singles to two ARM regs.)
20078 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
20079 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
20080 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
20081 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
20083 These cases can be disambiguated using neon_select_shape, except cases 1/9
20084 and 3/11 which depend on the operand type too.
20086 All the encoded bits are hardcoded by this function.
20088 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
20089 Cases 5, 7 may be used with VFPv2 and above.
20091 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
20092 can specify a type where it doesn't make sense to, and is ignored). */
20097 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
20098 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
20099 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
20100 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
20102 struct neon_type_el et
;
20103 const char *ldconst
= 0;
20107 case NS_DD
: /* case 1/9. */
20108 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
20109 /* It is not an error here if no type is given. */
20112 /* In MVE we interpret the following instructions as same, so ignoring
20113 the following type (float) and size (64) checks.
20114 a: VMOV<c><q> <Dd>, <Dm>
20115 b: VMOV<c><q>.F64 <Dd>, <Dm>. */
20116 if ((et
.type
== NT_float
&& et
.size
== 64)
20117 || (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
20119 do_vfp_nsyn_opcode ("fcpyd");
20122 /* fall through. */
20124 case NS_QQ
: /* case 0/1. */
20126 if (!check_simd_pred_availability (FALSE
,
20127 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20129 /* The architecture manual I have doesn't explicitly state which
20130 value the U bit should have for register->register moves, but
20131 the equivalent VORR instruction has U = 0, so do that. */
20132 inst
.instruction
= 0x0200110;
20133 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20134 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20135 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20136 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20137 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20138 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20139 inst
.instruction
|= neon_quad (rs
) << 6;
20141 neon_dp_fixup (&inst
);
20145 case NS_DI
: /* case 3/11. */
20146 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
20148 if (et
.type
== NT_float
&& et
.size
== 64)
20150 /* case 11 (fconstd). */
20151 ldconst
= "fconstd";
20152 goto encode_fconstd
;
20154 /* fall through. */
20156 case NS_QI
: /* case 2/3. */
20157 if (!check_simd_pred_availability (FALSE
,
20158 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20160 inst
.instruction
= 0x0800010;
20161 neon_move_immediate ();
20162 neon_dp_fixup (&inst
);
20165 case NS_SR
: /* case 4. */
20167 unsigned bcdebits
= 0;
20169 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
20170 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
20172 /* .<size> is optional here, defaulting to .32. */
20173 if (inst
.vectype
.elems
== 0
20174 && inst
.operands
[0].vectype
.type
== NT_invtype
20175 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20177 inst
.vectype
.el
[0].type
= NT_untyped
;
20178 inst
.vectype
.el
[0].size
= 32;
20179 inst
.vectype
.elems
= 1;
20182 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
20183 logsize
= neon_logbits (et
.size
);
20187 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20188 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
20193 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20194 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20198 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20200 if (inst
.operands
[1].reg
== REG_SP
)
20201 as_tsktsk (MVE_BAD_SP
);
20202 else if (inst
.operands
[1].reg
== REG_PC
)
20203 as_tsktsk (MVE_BAD_PC
);
20205 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
20207 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20208 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20213 case 8: bcdebits
= 0x8; break;
20214 case 16: bcdebits
= 0x1; break;
20215 case 32: bcdebits
= 0x0; break;
20219 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20221 inst
.instruction
= 0xe000b10;
20222 do_vfp_cond_or_thumb ();
20223 inst
.instruction
|= LOW4 (dn
) << 16;
20224 inst
.instruction
|= HI1 (dn
) << 7;
20225 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20226 inst
.instruction
|= (bcdebits
& 3) << 5;
20227 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
20228 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20232 case NS_DRR
: /* case 5 (fmdrr). */
20233 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20234 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20237 inst
.instruction
= 0xc400b10;
20238 do_vfp_cond_or_thumb ();
20239 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
20240 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
20241 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20242 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
20245 case NS_RS
: /* case 6. */
20248 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
20249 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
20250 unsigned abcdebits
= 0;
20252 /* .<dt> is optional here, defaulting to .32. */
20253 if (inst
.vectype
.elems
== 0
20254 && inst
.operands
[0].vectype
.type
== NT_invtype
20255 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20257 inst
.vectype
.el
[0].type
= NT_untyped
;
20258 inst
.vectype
.el
[0].size
= 32;
20259 inst
.vectype
.elems
= 1;
20262 et
= neon_check_type (2, NS_NULL
,
20263 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
20264 logsize
= neon_logbits (et
.size
);
20268 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20269 && vfp_or_neon_is_neon (NEON_CHECK_CC
20270 | NEON_CHECK_ARCH
) == FAIL
)
20275 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20276 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20280 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20282 if (inst
.operands
[0].reg
== REG_SP
)
20283 as_tsktsk (MVE_BAD_SP
);
20284 else if (inst
.operands
[0].reg
== REG_PC
)
20285 as_tsktsk (MVE_BAD_PC
);
20288 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
20290 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20291 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20295 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
20296 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
20297 case 32: abcdebits
= 0x00; break;
20301 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20302 inst
.instruction
= 0xe100b10;
20303 do_vfp_cond_or_thumb ();
20304 inst
.instruction
|= LOW4 (dn
) << 16;
20305 inst
.instruction
|= HI1 (dn
) << 7;
20306 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20307 inst
.instruction
|= (abcdebits
& 3) << 5;
20308 inst
.instruction
|= (abcdebits
>> 2) << 21;
20309 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20313 case NS_RRD
: /* case 7 (fmrrd). */
20314 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20315 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20318 inst
.instruction
= 0xc500b10;
20319 do_vfp_cond_or_thumb ();
20320 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20321 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20322 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20323 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20326 case NS_FF
: /* case 8 (fcpys). */
20327 do_vfp_nsyn_opcode ("fcpys");
20331 case NS_FI
: /* case 10 (fconsts). */
20332 ldconst
= "fconsts";
20334 if (!inst
.operands
[1].immisfloat
)
20337 /* Immediate has to fit in 8 bits so float is enough. */
20338 float imm
= (float) inst
.operands
[1].imm
;
20339 memcpy (&new_imm
, &imm
, sizeof (float));
20340 /* But the assembly may have been written to provide an integer
20341 bit pattern that equates to a float, so check that the
20342 conversion has worked. */
20343 if (is_quarter_float (new_imm
))
20345 if (is_quarter_float (inst
.operands
[1].imm
))
20346 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
20348 inst
.operands
[1].imm
= new_imm
;
20349 inst
.operands
[1].immisfloat
= 1;
20353 if (is_quarter_float (inst
.operands
[1].imm
))
20355 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
20356 do_vfp_nsyn_opcode (ldconst
);
20358 /* ARMv8.2 fp16 vmov.f16 instruction. */
20360 do_scalar_fp16_v82_encode ();
20363 first_error (_("immediate out of range"));
20367 case NS_RF
: /* case 12 (fmrs). */
20368 do_vfp_nsyn_opcode ("fmrs");
20369 /* ARMv8.2 fp16 vmov.f16 instruction. */
20371 do_scalar_fp16_v82_encode ();
20375 case NS_FR
: /* case 13 (fmsr). */
20376 do_vfp_nsyn_opcode ("fmsr");
20377 /* ARMv8.2 fp16 vmov.f16 instruction. */
20379 do_scalar_fp16_v82_encode ();
20389 /* The encoders for the fmrrs and fmsrr instructions expect three operands
20390 (one of which is a list), but we have parsed four. Do some fiddling to
20391 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
20393 case NS_RRFF
: /* case 14 (fmrrs). */
20394 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20395 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20397 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
20398 _("VFP registers must be adjacent"));
20399 inst
.operands
[2].imm
= 2;
20400 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20401 do_vfp_nsyn_opcode ("fmrrs");
20404 case NS_FFRR
: /* case 15 (fmsrr). */
20405 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20406 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20408 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
20409 _("VFP registers must be adjacent"));
20410 inst
.operands
[1] = inst
.operands
[2];
20411 inst
.operands
[2] = inst
.operands
[3];
20412 inst
.operands
[0].imm
= 2;
20413 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20414 do_vfp_nsyn_opcode ("fmsrr");
20418 /* neon_select_shape has determined that the instruction
20419 shape is wrong and has already set the error message. */
20430 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
20431 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
20432 && !inst
.operands
[2].present
))
20434 inst
.instruction
= 0;
20437 set_pred_insn_type (INSIDE_IT_INSN
);
20442 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20445 if (inst
.cond
!= COND_ALWAYS
)
20446 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20448 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
20449 | N_S16
| N_U16
| N_KEY
);
20451 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
20452 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20453 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
20454 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20455 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20456 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20461 do_neon_rshift_round_imm (void)
20463 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20466 enum neon_shape rs
;
20467 struct neon_type_el et
;
20469 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20471 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
20472 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
20476 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
20477 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
20479 int imm
= inst
.operands
[2].imm
;
20481 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20484 inst
.operands
[2].present
= 0;
20489 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
20490 _("immediate out of range for shift"));
20491 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
20496 do_neon_movhf (void)
20498 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
20499 constraint (rs
!= NS_HH
, _("invalid suffix"));
20501 if (inst
.cond
!= COND_ALWAYS
)
20505 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20506 " the behaviour is UNPREDICTABLE"));
20510 inst
.error
= BAD_COND
;
20515 do_vfp_sp_monadic ();
20518 inst
.instruction
|= 0xf0000000;
20522 do_neon_movl (void)
20524 struct neon_type_el et
= neon_check_type (2, NS_QD
,
20525 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
20526 unsigned sizebits
= et
.size
>> 3;
20527 inst
.instruction
|= sizebits
<< 19;
20528 neon_two_same (0, et
.type
== NT_unsigned
, -1);
20534 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20535 struct neon_type_el et
= neon_check_type (2, rs
,
20536 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20537 NEON_ENCODE (INTEGER
, inst
);
20538 neon_two_same (neon_quad (rs
), 1, et
.size
);
20542 do_neon_zip_uzp (void)
20544 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20545 struct neon_type_el et
= neon_check_type (2, rs
,
20546 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20547 if (rs
== NS_DD
&& et
.size
== 32)
20549 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20550 inst
.instruction
= N_MNEM_vtrn
;
20554 neon_two_same (neon_quad (rs
), 1, et
.size
);
20558 do_neon_sat_abs_neg (void)
20560 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20563 enum neon_shape rs
;
20564 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20565 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20567 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20568 struct neon_type_el et
= neon_check_type (2, rs
,
20569 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20570 neon_two_same (neon_quad (rs
), 1, et
.size
);
20574 do_neon_pair_long (void)
20576 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20577 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
20578 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20579 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
20580 neon_two_same (neon_quad (rs
), 1, et
.size
);
20584 do_neon_recip_est (void)
20586 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20587 struct neon_type_el et
= neon_check_type (2, rs
,
20588 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
20589 inst
.instruction
|= (et
.type
== NT_float
) << 8;
20590 neon_two_same (neon_quad (rs
), 1, et
.size
);
20596 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20599 enum neon_shape rs
;
20600 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20601 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20603 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20605 struct neon_type_el et
= neon_check_type (2, rs
,
20606 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20607 neon_two_same (neon_quad (rs
), 1, et
.size
);
20613 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20616 enum neon_shape rs
;
20617 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20618 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20620 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20622 struct neon_type_el et
= neon_check_type (2, rs
,
20623 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
20624 neon_two_same (neon_quad (rs
), 1, et
.size
);
20630 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20631 struct neon_type_el et
= neon_check_type (2, rs
,
20632 N_EQK
| N_INT
, N_8
| N_KEY
);
20633 neon_two_same (neon_quad (rs
), 1, et
.size
);
20639 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20642 neon_two_same (neon_quad (rs
), 1, -1);
20646 do_neon_tbl_tbx (void)
20648 unsigned listlenbits
;
20649 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
20651 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
20653 first_error (_("bad list length for table lookup"));
20657 listlenbits
= inst
.operands
[1].imm
- 1;
20658 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20659 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20660 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20661 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20662 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20663 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20664 inst
.instruction
|= listlenbits
<< 8;
20666 neon_dp_fixup (&inst
);
20670 do_neon_ldm_stm (void)
20672 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
20673 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20675 /* P, U and L bits are part of bitmask. */
20676 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
20677 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
20679 if (inst
.operands
[1].issingle
)
20681 do_vfp_nsyn_ldm_stm (is_dbmode
);
20685 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
20686 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20688 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20689 _("register list must contain at least 1 and at most 16 "
20692 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
20693 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
20694 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
20695 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
20697 inst
.instruction
|= offsetbits
;
20699 do_vfp_cond_or_thumb ();
20703 do_vfp_nsyn_pop (void)
20706 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)) {
20707 return do_vfp_nsyn_opcode ("vldm");
20710 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
20713 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20714 _("register list must contain at least 1 and at most 16 "
20717 if (inst
.operands
[1].issingle
)
20718 do_vfp_nsyn_opcode ("fldmias");
20720 do_vfp_nsyn_opcode ("fldmiad");
20724 do_vfp_nsyn_push (void)
20727 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)) {
20728 return do_vfp_nsyn_opcode ("vstmdb");
20731 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
20734 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20735 _("register list must contain at least 1 and at most 16 "
20738 if (inst
.operands
[1].issingle
)
20739 do_vfp_nsyn_opcode ("fstmdbs");
20741 do_vfp_nsyn_opcode ("fstmdbd");
20746 do_neon_ldr_str (void)
20748 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
20750 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20751 And is UNPREDICTABLE in thumb mode. */
20753 && inst
.operands
[1].reg
== REG_PC
20754 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
20757 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20758 else if (warn_on_deprecated
)
20759 as_tsktsk (_("Use of PC here is deprecated"));
20762 if (inst
.operands
[0].issingle
)
20765 do_vfp_nsyn_opcode ("flds");
20767 do_vfp_nsyn_opcode ("fsts");
20769 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20770 if (inst
.vectype
.el
[0].size
== 16)
20771 do_scalar_fp16_v82_encode ();
20776 do_vfp_nsyn_opcode ("fldd");
20778 do_vfp_nsyn_opcode ("fstd");
20783 do_t_vldr_vstr_sysreg (void)
20785 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
20786 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
20788 /* Use of PC is UNPREDICTABLE. */
20789 if (inst
.operands
[1].reg
== REG_PC
)
20790 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20792 if (inst
.operands
[1].immisreg
)
20793 inst
.error
= _("instruction does not accept register index");
20795 if (!inst
.operands
[1].isreg
)
20796 inst
.error
= _("instruction does not accept PC-relative addressing");
20798 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
20799 inst
.error
= _("immediate value out of range");
20801 inst
.instruction
= 0xec000f80;
20803 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20804 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20805 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20806 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20810 do_vldr_vstr (void)
20812 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
20814 /* VLDR/VSTR (System Register). */
20817 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20818 as_bad (_("Instruction not permitted on this architecture"));
20820 do_t_vldr_vstr_sysreg ();
20825 if (!mark_feature_used (&fpu_vfp_ext_v1xd
)
20826 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20827 as_bad (_("Instruction not permitted on this architecture"));
20828 do_neon_ldr_str ();
20832 /* "interleave" version also handles non-interleaving register VLD1/VST1
20836 do_neon_ld_st_interleave (void)
20838 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20839 N_8
| N_16
| N_32
| N_64
);
20840 unsigned alignbits
= 0;
20842 /* The bits in this table go:
20843 0: register stride of one (0) or two (1)
20844 1,2: register list length, minus one (1, 2, 3, 4).
20845 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20846 We use -1 for invalid entries. */
20847 const int typetable
[] =
20849 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20850 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20851 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20852 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20856 if (et
.type
== NT_invtype
)
20859 if (inst
.operands
[1].immisalign
)
20860 switch (inst
.operands
[1].imm
>> 8)
20862 case 64: alignbits
= 1; break;
20864 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20865 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20866 goto bad_alignment
;
20870 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20871 goto bad_alignment
;
20876 first_error (_("bad alignment"));
20880 inst
.instruction
|= alignbits
<< 4;
20881 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20883 /* Bits [4:6] of the immediate in a list specifier encode register stride
20884 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20885 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20886 up the right value for "type" in a table based on this value and the given
20887 list style, then stick it back. */
20888 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20889 | (((inst
.instruction
>> 8) & 3) << 3);
20891 typebits
= typetable
[idx
];
20893 constraint (typebits
== -1, _("bad list type for instruction"));
20894 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20897 inst
.instruction
&= ~0xf00;
20898 inst
.instruction
|= typebits
<< 8;
20901 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20902 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20903 otherwise. The variable arguments are a list of pairs of legal (size, align)
20904 values, terminated with -1. */
20907 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20910 int result
= FAIL
, thissize
, thisalign
;
20912 if (!inst
.operands
[1].immisalign
)
20918 va_start (ap
, do_alignment
);
20922 thissize
= va_arg (ap
, int);
20923 if (thissize
== -1)
20925 thisalign
= va_arg (ap
, int);
20927 if (size
== thissize
&& align
== thisalign
)
20930 while (result
!= SUCCESS
);
20934 if (result
== SUCCESS
)
20937 first_error (_("unsupported alignment for instruction"));
20943 do_neon_ld_st_lane (void)
20945 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20946 int align_good
, do_alignment
= 0;
20947 int logsize
= neon_logbits (et
.size
);
20948 int align
= inst
.operands
[1].imm
>> 8;
20949 int n
= (inst
.instruction
>> 8) & 3;
20950 int max_el
= 64 / et
.size
;
20952 if (et
.type
== NT_invtype
)
20955 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20956 _("bad list length"));
20957 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20958 _("scalar index out of range"));
20959 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20961 _("stride of 2 unavailable when element size is 8"));
20965 case 0: /* VLD1 / VST1. */
20966 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20968 if (align_good
== FAIL
)
20972 unsigned alignbits
= 0;
20975 case 16: alignbits
= 0x1; break;
20976 case 32: alignbits
= 0x3; break;
20979 inst
.instruction
|= alignbits
<< 4;
20983 case 1: /* VLD2 / VST2. */
20984 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20985 16, 32, 32, 64, -1);
20986 if (align_good
== FAIL
)
20989 inst
.instruction
|= 1 << 4;
20992 case 2: /* VLD3 / VST3. */
20993 constraint (inst
.operands
[1].immisalign
,
20994 _("can't use alignment with this instruction"));
20997 case 3: /* VLD4 / VST4. */
20998 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20999 16, 64, 32, 64, 32, 128, -1);
21000 if (align_good
== FAIL
)
21004 unsigned alignbits
= 0;
21007 case 8: alignbits
= 0x1; break;
21008 case 16: alignbits
= 0x1; break;
21009 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
21012 inst
.instruction
|= alignbits
<< 4;
21019 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
21020 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21021 inst
.instruction
|= 1 << (4 + logsize
);
21023 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
21024 inst
.instruction
|= logsize
<< 10;
21027 /* Encode single n-element structure to all lanes VLD<n> instructions. */
21030 do_neon_ld_dup (void)
21032 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
21033 int align_good
, do_alignment
= 0;
21035 if (et
.type
== NT_invtype
)
21038 switch ((inst
.instruction
>> 8) & 3)
21040 case 0: /* VLD1. */
21041 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
21042 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
21043 &do_alignment
, 16, 16, 32, 32, -1);
21044 if (align_good
== FAIL
)
21046 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
21049 case 2: inst
.instruction
|= 1 << 5; break;
21050 default: first_error (_("bad list length")); return;
21052 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21055 case 1: /* VLD2. */
21056 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
21057 &do_alignment
, 8, 16, 16, 32, 32, 64,
21059 if (align_good
== FAIL
)
21061 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
21062 _("bad list length"));
21063 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21064 inst
.instruction
|= 1 << 5;
21065 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21068 case 2: /* VLD3. */
21069 constraint (inst
.operands
[1].immisalign
,
21070 _("can't use alignment with this instruction"));
21071 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
21072 _("bad list length"));
21073 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21074 inst
.instruction
|= 1 << 5;
21075 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21078 case 3: /* VLD4. */
21080 int align
= inst
.operands
[1].imm
>> 8;
21081 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
21082 16, 64, 32, 64, 32, 128, -1);
21083 if (align_good
== FAIL
)
21085 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
21086 _("bad list length"));
21087 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21088 inst
.instruction
|= 1 << 5;
21089 if (et
.size
== 32 && align
== 128)
21090 inst
.instruction
|= 0x3 << 6;
21092 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21099 inst
.instruction
|= do_alignment
<< 4;
21102 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
21103 apart from bits [11:4]. */
21106 do_neon_ldx_stx (void)
21108 if (inst
.operands
[1].isreg
)
21109 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
21111 switch (NEON_LANE (inst
.operands
[0].imm
))
21113 case NEON_INTERLEAVE_LANES
:
21114 NEON_ENCODE (INTERLV
, inst
);
21115 do_neon_ld_st_interleave ();
21118 case NEON_ALL_LANES
:
21119 NEON_ENCODE (DUP
, inst
);
21120 if (inst
.instruction
== N_INV
)
21122 first_error ("only loads support such operands");
21129 NEON_ENCODE (LANE
, inst
);
21130 do_neon_ld_st_lane ();
21133 /* L bit comes from bit mask. */
21134 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21135 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21136 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
21138 if (inst
.operands
[1].postind
)
21140 int postreg
= inst
.operands
[1].imm
& 0xf;
21141 constraint (!inst
.operands
[1].immisreg
,
21142 _("post-index must be a register"));
21143 constraint (postreg
== 0xd || postreg
== 0xf,
21144 _("bad register for post-index"));
21145 inst
.instruction
|= postreg
;
21149 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
21150 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
21151 || inst
.relocs
[0].exp
.X_add_number
!= 0,
21154 if (inst
.operands
[1].writeback
)
21156 inst
.instruction
|= 0xd;
21159 inst
.instruction
|= 0xf;
21163 inst
.instruction
|= 0xf9000000;
21165 inst
.instruction
|= 0xf4000000;
21170 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
21172 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21173 D register operands. */
21174 if (neon_shape_class
[rs
] == SC_DOUBLE
)
21175 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21178 NEON_ENCODE (FPV8
, inst
);
21180 if (rs
== NS_FFF
|| rs
== NS_HHH
)
21182 do_vfp_sp_dyadic ();
21184 /* ARMv8.2 fp16 instruction. */
21186 do_scalar_fp16_v82_encode ();
21189 do_vfp_dp_rd_rn_rm ();
21192 inst
.instruction
|= 0x100;
21194 inst
.instruction
|= 0xf0000000;
21200 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21202 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
21203 first_error (_("invalid instruction shape"));
21209 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21210 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21212 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
21215 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21218 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
21222 do_vrint_1 (enum neon_cvt_mode mode
)
21224 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
21225 struct neon_type_el et
;
21230 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21231 D register operands. */
21232 if (neon_shape_class
[rs
] == SC_DOUBLE
)
21233 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21236 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
21238 if (et
.type
!= NT_invtype
)
21240 /* VFP encodings. */
21241 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
21242 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
21243 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21245 NEON_ENCODE (FPV8
, inst
);
21246 if (rs
== NS_FF
|| rs
== NS_HH
)
21247 do_vfp_sp_monadic ();
21249 do_vfp_dp_rd_rm ();
21253 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
21254 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
21255 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
21256 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
21257 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
21258 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
21259 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
21263 inst
.instruction
|= (rs
== NS_DD
) << 8;
21264 do_vfp_cond_or_thumb ();
21266 /* ARMv8.2 fp16 vrint instruction. */
21268 do_scalar_fp16_v82_encode ();
21272 /* Neon encodings (or something broken...). */
21274 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
21276 if (et
.type
== NT_invtype
)
21279 if (!check_simd_pred_availability (TRUE
,
21280 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21283 NEON_ENCODE (FLOAT
, inst
);
21285 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21286 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21287 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21288 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21289 inst
.instruction
|= neon_quad (rs
) << 6;
21290 /* Mask off the original size bits and reencode them. */
21291 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
21292 | neon_logbits (et
.size
) << 18);
21296 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
21297 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
21298 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
21299 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
21300 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
21301 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
21302 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
21307 inst
.instruction
|= 0xfc000000;
21309 inst
.instruction
|= 0xf0000000;
21316 do_vrint_1 (neon_cvt_mode_x
);
21322 do_vrint_1 (neon_cvt_mode_z
);
21328 do_vrint_1 (neon_cvt_mode_r
);
21334 do_vrint_1 (neon_cvt_mode_a
);
21340 do_vrint_1 (neon_cvt_mode_n
);
21346 do_vrint_1 (neon_cvt_mode_p
);
21352 do_vrint_1 (neon_cvt_mode_m
);
21356 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
21358 unsigned regno
= NEON_SCALAR_REG (opnd
);
21359 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
21361 if (elsize
== 16 && elno
< 2 && regno
< 16)
21362 return regno
| (elno
<< 4);
21363 else if (elsize
== 32 && elno
== 0)
21366 first_error (_("scalar out of range"));
21373 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
21374 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21375 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21376 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21377 _("expression too complex"));
21378 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21379 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
21380 _("immediate out of range"));
21383 if (!check_simd_pred_availability (TRUE
,
21384 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21387 if (inst
.operands
[2].isscalar
)
21389 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21390 first_error (_("invalid instruction shape"));
21391 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
21392 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21393 N_KEY
| N_F16
| N_F32
).size
;
21394 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
21396 inst
.instruction
= 0xfe000800;
21397 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21398 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21399 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21400 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21401 inst
.instruction
|= LOW4 (m
);
21402 inst
.instruction
|= HI1 (m
) << 5;
21403 inst
.instruction
|= neon_quad (rs
) << 6;
21404 inst
.instruction
|= rot
<< 20;
21405 inst
.instruction
|= (size
== 32) << 23;
21409 enum neon_shape rs
;
21410 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21411 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21413 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21415 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21416 N_KEY
| N_F16
| N_F32
).size
;
21417 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
21418 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
21419 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
21420 as_tsktsk (BAD_MVE_SRCDEST
);
21422 neon_three_same (neon_quad (rs
), 0, -1);
21423 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21424 inst
.instruction
|= 0xfc200800;
21425 inst
.instruction
|= rot
<< 23;
21426 inst
.instruction
|= (size
== 32) << 20;
21433 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
21434 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21435 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21436 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21437 _("expression too complex"));
21439 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21440 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
21441 enum neon_shape rs
;
21442 struct neon_type_el et
;
21443 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21445 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21446 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
21450 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21451 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
21453 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
21454 as_tsktsk (_("Warning: 32-bit element size and same first and third "
21455 "operand makes instruction UNPREDICTABLE"));
21458 if (et
.type
== NT_invtype
)
21461 if (!check_simd_pred_availability (et
.type
== NT_float
,
21462 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21465 if (et
.type
== NT_float
)
21467 neon_three_same (neon_quad (rs
), 0, -1);
21468 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21469 inst
.instruction
|= 0xfc800800;
21470 inst
.instruction
|= (rot
== 270) << 24;
21471 inst
.instruction
|= (et
.size
== 32) << 20;
21475 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
21476 inst
.instruction
= 0xfe000f00;
21477 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21478 inst
.instruction
|= neon_logbits (et
.size
) << 20;
21479 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21480 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21481 inst
.instruction
|= (rot
== 270) << 12;
21482 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21483 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
21484 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
21489 /* Dot Product instructions encoding support. */
21492 do_neon_dotproduct (int unsigned_p
)
21494 enum neon_shape rs
;
21495 unsigned scalar_oprd2
= 0;
21498 if (inst
.cond
!= COND_ALWAYS
)
21499 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21500 "is UNPREDICTABLE"));
21502 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
21505 /* Dot Product instructions are in three-same D/Q register format or the third
21506 operand can be a scalar index register. */
21507 if (inst
.operands
[2].isscalar
)
21509 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
21510 high8
= 0xfe000000;
21511 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21515 high8
= 0xfc000000;
21516 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21520 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
21522 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
21524 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21525 Product instruction, so we pass 0 as the "ubit" parameter. And the
21526 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21527 neon_three_same (neon_quad (rs
), 0, 32);
21529 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21530 different NEON three-same encoding. */
21531 inst
.instruction
&= 0x00ffffff;
21532 inst
.instruction
|= high8
;
21533 /* Encode 'U' bit which indicates signedness. */
21534 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
21535 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21536 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21537 the instruction encoding. */
21538 if (inst
.operands
[2].isscalar
)
21540 inst
.instruction
&= 0xffffffd0;
21541 inst
.instruction
|= LOW4 (scalar_oprd2
);
21542 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
21546 /* Dot Product instructions for signed integer. */
21549 do_neon_dotproduct_s (void)
21551 return do_neon_dotproduct (0);
21554 /* Dot Product instructions for unsigned integer. */
21557 do_neon_dotproduct_u (void)
21559 return do_neon_dotproduct (1);
21565 enum neon_shape rs
;
21566 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21567 if (inst
.operands
[2].isscalar
)
21569 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21570 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21572 inst
.instruction
|= (1 << 25);
21573 int index
= inst
.operands
[2].reg
& 0xf;
21574 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
21575 inst
.operands
[2].reg
>>= 4;
21576 constraint (!(inst
.operands
[2].reg
< 16),
21577 _("indexed register must be less than 16"));
21578 neon_three_args (rs
== NS_QQS
);
21579 inst
.instruction
|= (index
<< 5);
21583 inst
.instruction
|= (1 << 21);
21584 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21585 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21586 neon_three_args (rs
== NS_QQQ
);
21593 enum neon_shape rs
;
21594 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21595 if (inst
.operands
[2].isscalar
)
21597 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21598 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_U8
| N_KEY
);
21600 inst
.instruction
|= (1 << 25);
21601 int index
= inst
.operands
[2].reg
& 0xf;
21602 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
21603 inst
.operands
[2].reg
>>= 4;
21604 constraint (!(inst
.operands
[2].reg
< 16),
21605 _("indexed register must be less than 16"));
21606 neon_three_args (rs
== NS_QQS
);
21607 inst
.instruction
|= (index
<< 5);
21614 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21615 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21617 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21619 neon_three_args (1);
21626 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21627 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_U8
| N_KEY
);
21629 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21631 neon_three_args (1);
21636 check_cde_operand (size_t index
, int is_dual
)
21638 unsigned Rx
= inst
.operands
[index
].reg
;
21639 bfd_boolean isvec
= inst
.operands
[index
].isvec
;
21640 if (is_dual
== 0 && thumb_mode
)
21642 !((Rx
<= 14 && Rx
!= 13) || (Rx
== REG_PC
&& isvec
)),
21643 _("Register must be r0-r14 except r13, or APSR_nzcv."));
21645 constraint ( !((Rx
<= 10 && Rx
% 2 == 0 )),
21646 _("Register must be an even register between r0-r10."));
21650 cde_coproc_enabled (unsigned coproc
)
21654 case 0: return mark_feature_used (&arm_ext_cde0
);
21655 case 1: return mark_feature_used (&arm_ext_cde1
);
21656 case 2: return mark_feature_used (&arm_ext_cde2
);
21657 case 3: return mark_feature_used (&arm_ext_cde3
);
21658 case 4: return mark_feature_used (&arm_ext_cde4
);
21659 case 5: return mark_feature_used (&arm_ext_cde5
);
21660 case 6: return mark_feature_used (&arm_ext_cde6
);
21661 case 7: return mark_feature_used (&arm_ext_cde7
);
21662 default: return FALSE
;
21666 #define cde_coproc_pos 8
21668 cde_handle_coproc (void)
21670 unsigned coproc
= inst
.operands
[0].reg
;
21671 constraint (coproc
> 7, _("CDE Coprocessor must be in range 0-7"));
21672 constraint (!(cde_coproc_enabled (coproc
)), BAD_CDE_COPROC
);
21673 inst
.instruction
|= coproc
<< cde_coproc_pos
;
21675 #undef cde_coproc_pos
21678 cxn_handle_predication (bfd_boolean is_accum
)
21680 if (is_accum
&& conditional_insn ())
21681 set_pred_insn_type (INSIDE_IT_INSN
);
21682 else if (conditional_insn ())
21683 /* conditional_insn essentially checks for a suffix, not whether the
21684 instruction is inside an IT block or not.
21685 The non-accumulator versions should not have suffixes. */
21686 inst
.error
= BAD_SYNTAX
;
21688 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21692 do_custom_instruction_1 (int is_dual
, bfd_boolean is_accum
)
21695 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21699 Rd
= inst
.operands
[1].reg
;
21700 check_cde_operand (1, is_dual
);
21704 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21705 _("cx1d requires consecutive destination registers."));
21706 imm
= inst
.operands
[3].imm
;
21708 else if (is_dual
== 0)
21709 imm
= inst
.operands
[2].imm
;
21713 inst
.instruction
|= Rd
<< 12;
21714 inst
.instruction
|= (imm
& 0x1F80) << 9;
21715 inst
.instruction
|= (imm
& 0x0040) << 1;
21716 inst
.instruction
|= (imm
& 0x003f);
21718 cde_handle_coproc ();
21719 cxn_handle_predication (is_accum
);
21723 do_custom_instruction_2 (int is_dual
, bfd_boolean is_accum
)
21726 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21728 unsigned imm
, Rd
, Rn
;
21730 Rd
= inst
.operands
[1].reg
;
21734 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21735 _("cx2d requires consecutive destination registers."));
21736 imm
= inst
.operands
[4].imm
;
21737 Rn
= inst
.operands
[3].reg
;
21739 else if (is_dual
== 0)
21741 imm
= inst
.operands
[3].imm
;
21742 Rn
= inst
.operands
[2].reg
;
21747 check_cde_operand (2 + is_dual
, /* is_dual = */0);
21748 check_cde_operand (1, is_dual
);
21750 inst
.instruction
|= Rd
<< 12;
21751 inst
.instruction
|= Rn
<< 16;
21753 inst
.instruction
|= (imm
& 0x0380) << 13;
21754 inst
.instruction
|= (imm
& 0x0040) << 1;
21755 inst
.instruction
|= (imm
& 0x003f);
21757 cde_handle_coproc ();
21758 cxn_handle_predication (is_accum
);
21762 do_custom_instruction_3 (int is_dual
, bfd_boolean is_accum
)
21765 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21767 unsigned imm
, Rd
, Rn
, Rm
;
21769 Rd
= inst
.operands
[1].reg
;
21773 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21774 _("cx3d requires consecutive destination registers."));
21775 imm
= inst
.operands
[5].imm
;
21776 Rn
= inst
.operands
[3].reg
;
21777 Rm
= inst
.operands
[4].reg
;
21779 else if (is_dual
== 0)
21781 imm
= inst
.operands
[4].imm
;
21782 Rn
= inst
.operands
[2].reg
;
21783 Rm
= inst
.operands
[3].reg
;
21788 check_cde_operand (1, is_dual
);
21789 check_cde_operand (2 + is_dual
, /* is_dual = */0);
21790 check_cde_operand (3 + is_dual
, /* is_dual = */0);
21792 inst
.instruction
|= Rd
;
21793 inst
.instruction
|= Rn
<< 16;
21794 inst
.instruction
|= Rm
<< 12;
21796 inst
.instruction
|= (imm
& 0x0038) << 17;
21797 inst
.instruction
|= (imm
& 0x0004) << 5;
21798 inst
.instruction
|= (imm
& 0x0003) << 4;
21800 cde_handle_coproc ();
21801 cxn_handle_predication (is_accum
);
21807 return do_custom_instruction_1 (0, 0);
21813 return do_custom_instruction_1 (0, 1);
21819 return do_custom_instruction_1 (1, 0);
21825 return do_custom_instruction_1 (1, 1);
21831 return do_custom_instruction_2 (0, 0);
21837 return do_custom_instruction_2 (0, 1);
21843 return do_custom_instruction_2 (1, 0);
21849 return do_custom_instruction_2 (1, 1);
21855 return do_custom_instruction_3 (0, 0);
21861 return do_custom_instruction_3 (0, 1);
21867 return do_custom_instruction_3 (1, 0);
21873 return do_custom_instruction_3 (1, 1);
21877 vcx_assign_vec_d (unsigned regnum
)
21879 inst
.instruction
|= HI4 (regnum
) << 12;
21880 inst
.instruction
|= LOW1 (regnum
) << 22;
21884 vcx_assign_vec_m (unsigned regnum
)
21886 inst
.instruction
|= HI4 (regnum
);
21887 inst
.instruction
|= LOW1 (regnum
) << 5;
21891 vcx_assign_vec_n (unsigned regnum
)
21893 inst
.instruction
|= HI4 (regnum
) << 16;
21894 inst
.instruction
|= LOW1 (regnum
) << 7;
21897 enum vcx_reg_type
{
21903 static enum vcx_reg_type
21904 vcx_get_reg_type (enum neon_shape ns
)
21906 gas_assert (ns
== NS_PQI
21914 || ns
== NS_PFFFI
);
21915 if (ns
== NS_PQI
|| ns
== NS_PQQI
|| ns
== NS_PQQQI
)
21917 if (ns
== NS_PDI
|| ns
== NS_PDDI
|| ns
== NS_PDDDI
)
21922 #define vcx_size_pos 24
21923 #define vcx_vec_pos 6
21925 vcx_handle_shape (enum vcx_reg_type reg_type
)
21928 if (reg_type
== q_reg
)
21929 inst
.instruction
|= 1 << vcx_vec_pos
;
21930 else if (reg_type
== d_reg
)
21931 inst
.instruction
|= 1 << vcx_size_pos
;
21935 The documentation says that the Q registers are encoded as 2*N in the D:Vd
21936 bits (or equivalent for N and M registers).
21937 Similarly the D registers are encoded as N in D:Vd bits.
21938 While the S registers are encoded as N in the Vd:D bits.
21940 Taking into account the maximum values of these registers we can see a
21941 nicer pattern for calculation:
21942 Q -> 7, D -> 15, S -> 31
21944 If we say that everything is encoded in the Vd:D bits, then we can say
21945 that Q is encoded as 4*N, and D is encoded as 2*N.
21946 This way the bits will end up the same, and calculation is simpler.
21947 (calculation is now:
21948 1. Multiply by a number determined by the register letter.
21949 2. Encode resulting number in Vd:D bits.)
21951 This is made a little more complicated by automatic handling of 'Q'
21952 registers elsewhere, which means the register number is already 2*N where
21953 N is the number the user wrote after the register letter.
21958 #undef vcx_size_pos
21961 vcx_ensure_register_in_range (unsigned R
, enum vcx_reg_type reg_type
)
21963 if (reg_type
== q_reg
)
21965 gas_assert (R
% 2 == 0);
21966 constraint (R
>= 16, _("'q' register must be in range 0-7"));
21968 else if (reg_type
== d_reg
)
21969 constraint (R
>= 16, _("'d' register must be in range 0-15"));
21971 constraint (R
>= 32, _("'s' register must be in range 0-31"));
21974 static void (*vcx_assign_vec
[3]) (unsigned) = {
21981 vcx_handle_register_arguments (unsigned num_registers
,
21982 enum vcx_reg_type reg_type
)
21985 unsigned reg_mult
= vcx_handle_shape (reg_type
);
21986 for (i
= 0; i
< num_registers
; i
++)
21988 R
= inst
.operands
[i
+1].reg
;
21989 vcx_ensure_register_in_range (R
, reg_type
);
21990 if (num_registers
== 3 && i
> 0)
21993 vcx_assign_vec
[1] (R
* reg_mult
);
21995 vcx_assign_vec
[2] (R
* reg_mult
);
21998 vcx_assign_vec
[i
](R
* reg_mult
);
22003 vcx_handle_insn_block (enum vcx_reg_type reg_type
)
22005 if (reg_type
== q_reg
)
22006 if (inst
.cond
> COND_ALWAYS
)
22007 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
22009 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
22010 else if (inst
.cond
== COND_ALWAYS
)
22011 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22013 inst
.error
= BAD_NOT_IT
;
22017 vcx_handle_common_checks (unsigned num_args
, enum neon_shape rs
)
22019 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
22020 cde_handle_coproc ();
22021 enum vcx_reg_type reg_type
= vcx_get_reg_type (rs
);
22022 vcx_handle_register_arguments (num_args
, reg_type
);
22023 vcx_handle_insn_block (reg_type
);
22024 if (reg_type
== q_reg
)
22025 constraint (!mark_feature_used (&mve_ext
),
22026 _("vcx instructions with Q registers require MVE"));
22028 constraint (!(ARM_FSET_CPU_SUBSET (armv8m_fp
, cpu_variant
)
22029 && mark_feature_used (&armv8m_fp
))
22030 && !mark_feature_used (&mve_ext
),
22031 _("vcx instructions with S or D registers require either MVE"
22032 " or Armv8-M floating point extension."));
22038 enum neon_shape rs
= neon_select_shape (NS_PQI
, NS_PDI
, NS_PFI
, NS_NULL
);
22039 vcx_handle_common_checks (1, rs
);
22041 unsigned imm
= inst
.operands
[2].imm
;
22042 inst
.instruction
|= (imm
& 0x03f);
22043 inst
.instruction
|= (imm
& 0x040) << 1;
22044 inst
.instruction
|= (imm
& 0x780) << 9;
22046 constraint (imm
>= 2048,
22047 _("vcx1 with S or D registers takes immediate within 0-2047"));
22048 inst
.instruction
|= (imm
& 0x800) << 13;
22054 enum neon_shape rs
= neon_select_shape (NS_PQQI
, NS_PDDI
, NS_PFFI
, NS_NULL
);
22055 vcx_handle_common_checks (2, rs
);
22057 unsigned imm
= inst
.operands
[3].imm
;
22058 inst
.instruction
|= (imm
& 0x01) << 4;
22059 inst
.instruction
|= (imm
& 0x02) << 6;
22060 inst
.instruction
|= (imm
& 0x3c) << 14;
22062 constraint (imm
>= 64,
22063 _("vcx2 with S or D registers takes immediate within 0-63"));
22064 inst
.instruction
|= (imm
& 0x40) << 18;
22070 enum neon_shape rs
= neon_select_shape (NS_PQQQI
, NS_PDDDI
, NS_PFFFI
, NS_NULL
);
22071 vcx_handle_common_checks (3, rs
);
22073 unsigned imm
= inst
.operands
[4].imm
;
22074 inst
.instruction
|= (imm
& 0x1) << 4;
22075 inst
.instruction
|= (imm
& 0x6) << 19;
22076 if (rs
!= NS_PQQQI
)
22077 constraint (imm
>= 8,
22078 _("vcx2 with S or D registers takes immediate within 0-7"));
22079 inst
.instruction
|= (imm
& 0x8) << 21;
22082 /* Crypto v1 instructions. */
22084 do_crypto_2op_1 (unsigned elttype
, int op
)
22086 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22088 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
22094 NEON_ENCODE (INTEGER
, inst
);
22095 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
22096 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
22097 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
22098 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
22100 inst
.instruction
|= op
<< 6;
22103 inst
.instruction
|= 0xfc000000;
22105 inst
.instruction
|= 0xf0000000;
22109 do_crypto_3op_1 (int u
, int op
)
22111 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22113 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
22114 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
22119 NEON_ENCODE (INTEGER
, inst
);
22120 neon_three_same (1, u
, 8 << op
);
22126 do_crypto_2op_1 (N_8
, 0);
22132 do_crypto_2op_1 (N_8
, 1);
22138 do_crypto_2op_1 (N_8
, 2);
22144 do_crypto_2op_1 (N_8
, 3);
22150 do_crypto_3op_1 (0, 0);
22156 do_crypto_3op_1 (0, 1);
22162 do_crypto_3op_1 (0, 2);
22168 do_crypto_3op_1 (0, 3);
22174 do_crypto_3op_1 (1, 0);
22180 do_crypto_3op_1 (1, 1);
22184 do_sha256su1 (void)
22186 do_crypto_3op_1 (1, 2);
22192 do_crypto_2op_1 (N_32
, -1);
22198 do_crypto_2op_1 (N_32
, 0);
22202 do_sha256su0 (void)
22204 do_crypto_2op_1 (N_32
, 1);
22208 do_crc32_1 (unsigned int poly
, unsigned int sz
)
22210 unsigned int Rd
= inst
.operands
[0].reg
;
22211 unsigned int Rn
= inst
.operands
[1].reg
;
22212 unsigned int Rm
= inst
.operands
[2].reg
;
22214 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22215 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
22216 inst
.instruction
|= LOW4 (Rn
) << 16;
22217 inst
.instruction
|= LOW4 (Rm
);
22218 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
22219 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
22221 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
22222 as_warn (UNPRED_REG ("r15"));
22264 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
22266 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
22267 do_vfp_sp_dp_cvt ();
22268 do_vfp_cond_or_thumb ();
22274 enum neon_shape rs
;
22275 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
22276 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22277 if (inst
.operands
[2].isscalar
)
22279 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
22280 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22282 inst
.instruction
|= (1 << 25);
22283 int index
= inst
.operands
[2].reg
& 0xf;
22284 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
22285 inst
.operands
[2].reg
>>= 4;
22286 constraint (!(inst
.operands
[2].reg
< 16),
22287 _("indexed register must be less than 16"));
22288 neon_three_args (rs
== NS_QQS
);
22289 inst
.instruction
|= (index
<< 5);
22293 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
22294 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22295 neon_three_args (rs
== NS_QQQ
);
22302 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
22303 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22305 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
22306 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22308 neon_three_args (1);
22312 /* Overall per-instruction processing. */
22314 /* We need to be able to fix up arbitrary expressions in some statements.
22315 This is so that we can handle symbols that are an arbitrary distance from
22316 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
22317 which returns part of an address in a form which will be valid for
22318 a data instruction. We do this by pushing the expression into a symbol
22319 in the expr_section, and creating a fix for that. */
22322 fix_new_arm (fragS
* frag
,
22336 /* Create an absolute valued symbol, so we have something to
22337 refer to in the object file. Unfortunately for us, gas's
22338 generic expression parsing will already have folded out
22339 any use of .set foo/.type foo %function that may have
22340 been used to set type information of the target location,
22341 that's being specified symbolically. We have to presume
22342 the user knows what they are doing. */
22346 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
22348 symbol
= symbol_find_or_make (name
);
22349 S_SET_SEGMENT (symbol
, absolute_section
);
22350 symbol_set_frag (symbol
, &zero_address_frag
);
22351 S_SET_VALUE (symbol
, exp
->X_add_number
);
22352 exp
->X_op
= O_symbol
;
22353 exp
->X_add_symbol
= symbol
;
22354 exp
->X_add_number
= 0;
22360 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
22361 (enum bfd_reloc_code_real
) reloc
);
22365 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
22366 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
22370 /* Mark whether the fix is to a THUMB instruction, or an ARM
22372 new_fix
->tc_fix_data
= thumb_mode
;
22375 /* Create a frg for an instruction requiring relaxation. */
22377 output_relax_insn (void)
22383 /* The size of the instruction is unknown, so tie the debug info to the
22384 start of the instruction. */
22385 dwarf2_emit_insn (0);
22387 switch (inst
.relocs
[0].exp
.X_op
)
22390 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
22391 offset
= inst
.relocs
[0].exp
.X_add_number
;
22395 offset
= inst
.relocs
[0].exp
.X_add_number
;
22398 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
22402 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
22403 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
22404 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
22407 /* Write a 32-bit thumb instruction to buf. */
22409 put_thumb32_insn (char * buf
, unsigned long insn
)
22411 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
22412 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
22416 output_inst (const char * str
)
22422 as_bad ("%s -- `%s'", inst
.error
, str
);
22427 output_relax_insn ();
22430 if (inst
.size
== 0)
22433 to
= frag_more (inst
.size
);
22434 /* PR 9814: Record the thumb mode into the current frag so that we know
22435 what type of NOP padding to use, if necessary. We override any previous
22436 setting so that if the mode has changed then the NOPS that we use will
22437 match the encoding of the last instruction in the frag. */
22438 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22440 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
22442 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
22443 put_thumb32_insn (to
, inst
.instruction
);
22445 else if (inst
.size
> INSN_SIZE
)
22447 gas_assert (inst
.size
== (2 * INSN_SIZE
));
22448 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
22449 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
22452 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
22455 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22457 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
22458 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
22459 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
22460 inst
.relocs
[r
].type
);
22463 dwarf2_emit_insn (inst
.size
);
22467 output_it_inst (int cond
, int mask
, char * to
)
22469 unsigned long instruction
= 0xbf00;
22472 instruction
|= mask
;
22473 instruction
|= cond
<< 4;
22477 to
= frag_more (2);
22479 dwarf2_emit_insn (2);
22483 md_number_to_chars (to
, instruction
, 2);
22488 /* Tag values used in struct asm_opcode's tag field. */
22491 OT_unconditional
, /* Instruction cannot be conditionalized.
22492 The ARM condition field is still 0xE. */
22493 OT_unconditionalF
, /* Instruction cannot be conditionalized
22494 and carries 0xF in its ARM condition field. */
22495 OT_csuffix
, /* Instruction takes a conditional suffix. */
22496 OT_csuffixF
, /* Some forms of the instruction take a scalar
22497 conditional suffix, others place 0xF where the
22498 condition field would be, others take a vector
22499 conditional suffix. */
22500 OT_cinfix3
, /* Instruction takes a conditional infix,
22501 beginning at character index 3. (In
22502 unified mode, it becomes a suffix.) */
22503 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
22504 tsts, cmps, cmns, and teqs. */
22505 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
22506 character index 3, even in unified mode. Used for
22507 legacy instructions where suffix and infix forms
22508 may be ambiguous. */
22509 OT_csuf_or_in3
, /* Instruction takes either a conditional
22510 suffix or an infix at character index 3. */
22511 OT_odd_infix_unc
, /* This is the unconditional variant of an
22512 instruction that takes a conditional infix
22513 at an unusual position. In unified mode,
22514 this variant will accept a suffix. */
22515 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
22516 are the conditional variants of instructions that
22517 take conditional infixes in unusual positions.
22518 The infix appears at character index
22519 (tag - OT_odd_infix_0). These are not accepted
22520 in unified mode. */
22523 /* Subroutine of md_assemble, responsible for looking up the primary
22524 opcode from the mnemonic the user wrote. STR points to the
22525 beginning of the mnemonic.
22527 This is not simply a hash table lookup, because of conditional
22528 variants. Most instructions have conditional variants, which are
22529 expressed with a _conditional affix_ to the mnemonic. If we were
22530 to encode each conditional variant as a literal string in the opcode
22531 table, it would have approximately 20,000 entries.
22533 Most mnemonics take this affix as a suffix, and in unified syntax,
22534 'most' is upgraded to 'all'. However, in the divided syntax, some
22535 instructions take the affix as an infix, notably the s-variants of
22536 the arithmetic instructions. Of those instructions, all but six
22537 have the infix appear after the third character of the mnemonic.
22539 Accordingly, the algorithm for looking up primary opcodes given
22542 1. Look up the identifier in the opcode table.
22543 If we find a match, go to step U.
22545 2. Look up the last two characters of the identifier in the
22546 conditions table. If we find a match, look up the first N-2
22547 characters of the identifier in the opcode table. If we
22548 find a match, go to step CE.
22550 3. Look up the fourth and fifth characters of the identifier in
22551 the conditions table. If we find a match, extract those
22552 characters from the identifier, and look up the remaining
22553 characters in the opcode table. If we find a match, go
22558 U. Examine the tag field of the opcode structure, in case this is
22559 one of the six instructions with its conditional infix in an
22560 unusual place. If it is, the tag tells us where to find the
22561 infix; look it up in the conditions table and set inst.cond
22562 accordingly. Otherwise, this is an unconditional instruction.
22563 Again set inst.cond accordingly. Return the opcode structure.
22565 CE. Examine the tag field to make sure this is an instruction that
22566 should receive a conditional suffix. If it is not, fail.
22567 Otherwise, set inst.cond from the suffix we already looked up,
22568 and return the opcode structure.
22570 CM. Examine the tag field to make sure this is an instruction that
22571 should receive a conditional infix after the third character.
22572 If it is not, fail. Otherwise, undo the edits to the current
22573 line of input and proceed as for case CE. */
22575 static const struct asm_opcode
*
22576 opcode_lookup (char **str
)
22580 const struct asm_opcode
*opcode
;
22581 const struct asm_cond
*cond
;
22584 /* Scan up to the end of the mnemonic, which must end in white space,
22585 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
22586 for (base
= end
= *str
; *end
!= '\0'; end
++)
22587 if (*end
== ' ' || *end
== '.')
22593 /* Handle a possible width suffix and/or Neon type suffix. */
22598 /* The .w and .n suffixes are only valid if the unified syntax is in
22600 if (unified_syntax
&& end
[1] == 'w')
22602 else if (unified_syntax
&& end
[1] == 'n')
22607 inst
.vectype
.elems
= 0;
22609 *str
= end
+ offset
;
22611 if (end
[offset
] == '.')
22613 /* See if we have a Neon type suffix (possible in either unified or
22614 non-unified ARM syntax mode). */
22615 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
22618 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
22624 /* Look for unaffixed or special-case affixed mnemonic. */
22625 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22631 if (opcode
->tag
< OT_odd_infix_0
)
22633 inst
.cond
= COND_ALWAYS
;
22637 if (warn_on_deprecated
&& unified_syntax
)
22638 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22639 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
22640 cond
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, affix
, 2);
22643 inst
.cond
= cond
->value
;
22646 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
22648 /* Cannot have a conditional suffix on a mnemonic of less than a character.
22650 if (end
- base
< 2)
22653 cond
= (const struct asm_cond
*) str_hash_find_n (arm_vcond_hsh
, affix
, 1);
22654 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22656 /* If this opcode can not be vector predicated then don't accept it with a
22657 vector predication code. */
22658 if (opcode
&& !opcode
->mayBeVecPred
)
22661 if (!opcode
|| !cond
)
22663 /* Cannot have a conditional suffix on a mnemonic of less than two
22665 if (end
- base
< 3)
22668 /* Look for suffixed mnemonic. */
22670 cond
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, affix
, 2);
22671 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22675 if (opcode
&& cond
)
22678 switch (opcode
->tag
)
22680 case OT_cinfix3_legacy
:
22681 /* Ignore conditional suffixes matched on infix only mnemonics. */
22685 case OT_cinfix3_deprecated
:
22686 case OT_odd_infix_unc
:
22687 if (!unified_syntax
)
22689 /* Fall through. */
22693 case OT_csuf_or_in3
:
22694 inst
.cond
= cond
->value
;
22697 case OT_unconditional
:
22698 case OT_unconditionalF
:
22700 inst
.cond
= cond
->value
;
22703 /* Delayed diagnostic. */
22704 inst
.error
= BAD_COND
;
22705 inst
.cond
= COND_ALWAYS
;
22714 /* Cannot have a usual-position infix on a mnemonic of less than
22715 six characters (five would be a suffix). */
22716 if (end
- base
< 6)
22719 /* Look for infixed mnemonic in the usual position. */
22721 cond
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, affix
, 2);
22725 memcpy (save
, affix
, 2);
22726 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
22727 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22729 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
22730 memcpy (affix
, save
, 2);
22733 && (opcode
->tag
== OT_cinfix3
22734 || opcode
->tag
== OT_cinfix3_deprecated
22735 || opcode
->tag
== OT_csuf_or_in3
22736 || opcode
->tag
== OT_cinfix3_legacy
))
22739 if (warn_on_deprecated
&& unified_syntax
22740 && (opcode
->tag
== OT_cinfix3
22741 || opcode
->tag
== OT_cinfix3_deprecated
))
22742 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22744 inst
.cond
= cond
->value
;
22751 /* This function generates an initial IT instruction, leaving its block
22752 virtually open for the new instructions. Eventually,
22753 the mask will be updated by now_pred_add_mask () each time
22754 a new instruction needs to be included in the IT block.
22755 Finally, the block is closed with close_automatic_it_block ().
22756 The block closure can be requested either from md_assemble (),
22757 a tencode (), or due to a label hook. */
22760 new_automatic_it_block (int cond
)
22762 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
22763 now_pred
.mask
= 0x18;
22764 now_pred
.cc
= cond
;
22765 now_pred
.block_length
= 1;
22766 mapping_state (MAP_THUMB
);
22767 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
22768 now_pred
.warn_deprecated
= FALSE
;
22769 now_pred
.insn_cond
= TRUE
;
22772 /* Close an automatic IT block.
22773 See comments in new_automatic_it_block (). */
22776 close_automatic_it_block (void)
22778 now_pred
.mask
= 0x10;
22779 now_pred
.block_length
= 0;
22782 /* Update the mask of the current automatically-generated IT
22783 instruction. See comments in new_automatic_it_block (). */
22786 now_pred_add_mask (int cond
)
22788 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
22789 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
22790 | ((bitvalue) << (nbit)))
22791 const int resulting_bit
= (cond
& 1);
22793 now_pred
.mask
&= 0xf;
22794 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
22796 (5 - now_pred
.block_length
));
22797 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
22799 ((5 - now_pred
.block_length
) - 1));
22800 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
22803 #undef SET_BIT_VALUE
22806 /* The IT blocks handling machinery is accessed through the these functions:
22807 it_fsm_pre_encode () from md_assemble ()
22808 set_pred_insn_type () optional, from the tencode functions
22809 set_pred_insn_type_last () ditto
22810 in_pred_block () ditto
22811 it_fsm_post_encode () from md_assemble ()
22812 force_automatic_it_block_close () from label handling functions
22815 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
22816 initializing the IT insn type with a generic initial value depending
22817 on the inst.condition.
22818 2) During the tencode function, two things may happen:
22819 a) The tencode function overrides the IT insn type by
22820 calling either set_pred_insn_type (type) or
22821 set_pred_insn_type_last ().
22822 b) The tencode function queries the IT block state by
22823 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
22825 Both set_pred_insn_type and in_pred_block run the internal FSM state
22826 handling function (handle_pred_state), because: a) setting the IT insn
22827 type may incur in an invalid state (exiting the function),
22828 and b) querying the state requires the FSM to be updated.
22829 Specifically we want to avoid creating an IT block for conditional
22830 branches, so it_fsm_pre_encode is actually a guess and we can't
22831 determine whether an IT block is required until the tencode () routine
22832 has decided what type of instruction this actually it.
22833 Because of this, if set_pred_insn_type and in_pred_block have to be
22834 used, set_pred_insn_type has to be called first.
22836 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
22837 that determines the insn IT type depending on the inst.cond code.
22838 When a tencode () routine encodes an instruction that can be
22839 either outside an IT block, or, in the case of being inside, has to be
22840 the last one, set_pred_insn_type_last () will determine the proper
22841 IT instruction type based on the inst.cond code. Otherwise,
22842 set_pred_insn_type can be called for overriding that logic or
22843 for covering other cases.
22845 Calling handle_pred_state () may not transition the IT block state to
22846 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
22847 still queried. Instead, if the FSM determines that the state should
22848 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
22849 after the tencode () function: that's what it_fsm_post_encode () does.
22851 Since in_pred_block () calls the state handling function to get an
22852 updated state, an error may occur (due to invalid insns combination).
22853 In that case, inst.error is set.
22854 Therefore, inst.error has to be checked after the execution of
22855 the tencode () routine.
22857 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
22858 any pending state change (if any) that didn't take place in
22859 handle_pred_state () as explained above. */
22862 it_fsm_pre_encode (void)
22864 if (inst
.cond
!= COND_ALWAYS
)
22865 inst
.pred_insn_type
= INSIDE_IT_INSN
;
22867 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22869 now_pred
.state_handled
= 0;
22872 /* IT state FSM handling function. */
22873 /* MVE instructions and non-MVE instructions are handled differently because of
22874 the introduction of VPT blocks.
22875 Specifications say that any non-MVE instruction inside a VPT block is
22876 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
22877 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
22878 few exceptions we have MVE_UNPREDICABLE_INSN.
22879 The error messages provided depending on the different combinations possible
22880 are described in the cases below:
22881 For 'most' MVE instructions:
22882 1) In an IT block, with an IT code: syntax error
22883 2) In an IT block, with a VPT code: error: must be in a VPT block
22884 3) In an IT block, with no code: warning: UNPREDICTABLE
22885 4) In a VPT block, with an IT code: syntax error
22886 5) In a VPT block, with a VPT code: OK!
22887 6) In a VPT block, with no code: error: missing code
22888 7) Outside a pred block, with an IT code: error: syntax error
22889 8) Outside a pred block, with a VPT code: error: should be in a VPT block
22890 9) Outside a pred block, with no code: OK!
22891 For non-MVE instructions:
22892 10) In an IT block, with an IT code: OK!
22893 11) In an IT block, with a VPT code: syntax error
22894 12) In an IT block, with no code: error: missing code
22895 13) In a VPT block, with an IT code: error: should be in an IT block
22896 14) In a VPT block, with a VPT code: syntax error
22897 15) In a VPT block, with no code: UNPREDICTABLE
22898 16) Outside a pred block, with an IT code: error: should be in an IT block
22899 17) Outside a pred block, with a VPT code: syntax error
22900 18) Outside a pred block, with no code: OK!
22905 handle_pred_state (void)
22907 now_pred
.state_handled
= 1;
22908 now_pred
.insn_cond
= FALSE
;
22910 switch (now_pred
.state
)
22912 case OUTSIDE_PRED_BLOCK
:
22913 switch (inst
.pred_insn_type
)
22915 case MVE_UNPREDICABLE_INSN
:
22916 case MVE_OUTSIDE_PRED_INSN
:
22917 if (inst
.cond
< COND_ALWAYS
)
22919 /* Case 7: Outside a pred block, with an IT code: error: syntax
22921 inst
.error
= BAD_SYNTAX
;
22924 /* Case 9: Outside a pred block, with no code: OK! */
22926 case OUTSIDE_PRED_INSN
:
22927 if (inst
.cond
> COND_ALWAYS
)
22929 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22931 inst
.error
= BAD_SYNTAX
;
22934 /* Case 18: Outside a pred block, with no code: OK! */
22937 case INSIDE_VPT_INSN
:
22938 /* Case 8: Outside a pred block, with a VPT code: error: should be in
22940 inst
.error
= BAD_OUT_VPT
;
22943 case INSIDE_IT_INSN
:
22944 case INSIDE_IT_LAST_INSN
:
22945 if (inst
.cond
< COND_ALWAYS
)
22947 /* Case 16: Outside a pred block, with an IT code: error: should
22948 be in an IT block. */
22949 if (thumb_mode
== 0)
22952 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
22953 as_tsktsk (_("Warning: conditional outside an IT block"\
22958 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
22959 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
22961 /* Automatically generate the IT instruction. */
22962 new_automatic_it_block (inst
.cond
);
22963 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
22964 close_automatic_it_block ();
22968 inst
.error
= BAD_OUT_IT
;
22974 else if (inst
.cond
> COND_ALWAYS
)
22976 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22978 inst
.error
= BAD_SYNTAX
;
22983 case IF_INSIDE_IT_LAST_INSN
:
22984 case NEUTRAL_IT_INSN
:
22988 if (inst
.cond
!= COND_ALWAYS
)
22989 first_error (BAD_SYNTAX
);
22990 now_pred
.state
= MANUAL_PRED_BLOCK
;
22991 now_pred
.block_length
= 0;
22992 now_pred
.type
= VECTOR_PRED
;
22996 now_pred
.state
= MANUAL_PRED_BLOCK
;
22997 now_pred
.block_length
= 0;
22998 now_pred
.type
= SCALAR_PRED
;
23003 case AUTOMATIC_PRED_BLOCK
:
23004 /* Three things may happen now:
23005 a) We should increment current it block size;
23006 b) We should close current it block (closing insn or 4 insns);
23007 c) We should close current it block and start a new one (due
23008 to incompatible conditions or
23009 4 insns-length block reached). */
23011 switch (inst
.pred_insn_type
)
23013 case INSIDE_VPT_INSN
:
23015 case MVE_UNPREDICABLE_INSN
:
23016 case MVE_OUTSIDE_PRED_INSN
:
23018 case OUTSIDE_PRED_INSN
:
23019 /* The closure of the block shall happen immediately,
23020 so any in_pred_block () call reports the block as closed. */
23021 force_automatic_it_block_close ();
23024 case INSIDE_IT_INSN
:
23025 case INSIDE_IT_LAST_INSN
:
23026 case IF_INSIDE_IT_LAST_INSN
:
23027 now_pred
.block_length
++;
23029 if (now_pred
.block_length
> 4
23030 || !now_pred_compatible (inst
.cond
))
23032 force_automatic_it_block_close ();
23033 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
23034 new_automatic_it_block (inst
.cond
);
23038 now_pred
.insn_cond
= TRUE
;
23039 now_pred_add_mask (inst
.cond
);
23042 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
23043 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
23044 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
23045 close_automatic_it_block ();
23049 case NEUTRAL_IT_INSN
:
23050 now_pred
.block_length
++;
23051 now_pred
.insn_cond
= TRUE
;
23053 if (now_pred
.block_length
> 4)
23054 force_automatic_it_block_close ();
23056 now_pred_add_mask (now_pred
.cc
& 1);
23060 close_automatic_it_block ();
23061 now_pred
.state
= MANUAL_PRED_BLOCK
;
23066 case MANUAL_PRED_BLOCK
:
23070 if (now_pred
.type
== SCALAR_PRED
)
23072 /* Check conditional suffixes. */
23073 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
23074 now_pred
.mask
<<= 1;
23075 now_pred
.mask
&= 0x1f;
23076 is_last
= (now_pred
.mask
== 0x10);
23080 now_pred
.cc
^= (now_pred
.mask
>> 4);
23081 cond
= now_pred
.cc
+ 0xf;
23082 now_pred
.mask
<<= 1;
23083 now_pred
.mask
&= 0x1f;
23084 is_last
= now_pred
.mask
== 0x10;
23086 now_pred
.insn_cond
= TRUE
;
23088 switch (inst
.pred_insn_type
)
23090 case OUTSIDE_PRED_INSN
:
23091 if (now_pred
.type
== SCALAR_PRED
)
23093 if (inst
.cond
== COND_ALWAYS
)
23095 /* Case 12: In an IT block, with no code: error: missing
23097 inst
.error
= BAD_NOT_IT
;
23100 else if (inst
.cond
> COND_ALWAYS
)
23102 /* Case 11: In an IT block, with a VPT code: syntax error.
23104 inst
.error
= BAD_SYNTAX
;
23107 else if (thumb_mode
)
23109 /* This is for some special cases where a non-MVE
23110 instruction is not allowed in an IT block, such as cbz,
23111 but are put into one with a condition code.
23112 You could argue this should be a syntax error, but we
23113 gave the 'not allowed in IT block' diagnostic in the
23114 past so we will keep doing so. */
23115 inst
.error
= BAD_NOT_IT
;
23122 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
23123 as_tsktsk (MVE_NOT_VPT
);
23126 case MVE_OUTSIDE_PRED_INSN
:
23127 if (now_pred
.type
== SCALAR_PRED
)
23129 if (inst
.cond
== COND_ALWAYS
)
23131 /* Case 3: In an IT block, with no code: warning:
23133 as_tsktsk (MVE_NOT_IT
);
23136 else if (inst
.cond
< COND_ALWAYS
)
23138 /* Case 1: In an IT block, with an IT code: syntax error.
23140 inst
.error
= BAD_SYNTAX
;
23148 if (inst
.cond
< COND_ALWAYS
)
23150 /* Case 4: In a VPT block, with an IT code: syntax error.
23152 inst
.error
= BAD_SYNTAX
;
23155 else if (inst
.cond
== COND_ALWAYS
)
23157 /* Case 6: In a VPT block, with no code: error: missing
23159 inst
.error
= BAD_NOT_VPT
;
23167 case MVE_UNPREDICABLE_INSN
:
23168 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
23170 case INSIDE_IT_INSN
:
23171 if (inst
.cond
> COND_ALWAYS
)
23173 /* Case 11: In an IT block, with a VPT code: syntax error. */
23174 /* Case 14: In a VPT block, with a VPT code: syntax error. */
23175 inst
.error
= BAD_SYNTAX
;
23178 else if (now_pred
.type
== SCALAR_PRED
)
23180 /* Case 10: In an IT block, with an IT code: OK! */
23181 if (cond
!= inst
.cond
)
23183 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
23190 /* Case 13: In a VPT block, with an IT code: error: should be
23192 inst
.error
= BAD_OUT_IT
;
23197 case INSIDE_VPT_INSN
:
23198 if (now_pred
.type
== SCALAR_PRED
)
23200 /* Case 2: In an IT block, with a VPT code: error: must be in a
23202 inst
.error
= BAD_OUT_VPT
;
23205 /* Case 5: In a VPT block, with a VPT code: OK! */
23206 else if (cond
!= inst
.cond
)
23208 inst
.error
= BAD_VPT_COND
;
23212 case INSIDE_IT_LAST_INSN
:
23213 case IF_INSIDE_IT_LAST_INSN
:
23214 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
23216 /* Case 4: In a VPT block, with an IT code: syntax error. */
23217 /* Case 11: In an IT block, with a VPT code: syntax error. */
23218 inst
.error
= BAD_SYNTAX
;
23221 else if (cond
!= inst
.cond
)
23223 inst
.error
= BAD_IT_COND
;
23228 inst
.error
= BAD_BRANCH
;
23233 case NEUTRAL_IT_INSN
:
23234 /* The BKPT instruction is unconditional even in a IT or VPT
23239 if (now_pred
.type
== SCALAR_PRED
)
23241 inst
.error
= BAD_IT_IT
;
23244 /* fall through. */
23246 if (inst
.cond
== COND_ALWAYS
)
23248 /* Executing a VPT/VPST instruction inside an IT block or a
23249 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
23251 if (now_pred
.type
== SCALAR_PRED
)
23252 as_tsktsk (MVE_NOT_IT
);
23254 as_tsktsk (MVE_NOT_VPT
);
23259 /* VPT/VPST do not accept condition codes. */
23260 inst
.error
= BAD_SYNTAX
;
23271 struct depr_insn_mask
23273 unsigned long pattern
;
23274 unsigned long mask
;
23275 const char* description
;
23278 /* List of 16-bit instruction patterns deprecated in an IT block in
23280 static const struct depr_insn_mask depr_it_insns
[] = {
23281 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
23282 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
23283 { 0xa000, 0xb800, N_("ADR") },
23284 { 0x4800, 0xf800, N_("Literal loads") },
23285 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
23286 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
23287 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
23288 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
23289 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
23294 it_fsm_post_encode (void)
23298 if (!now_pred
.state_handled
)
23299 handle_pred_state ();
23301 if (now_pred
.insn_cond
23302 && warn_on_restrict_it
23303 && !now_pred
.warn_deprecated
23304 && warn_on_deprecated
23305 && (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
23306 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8r
))
23307 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
23309 if (inst
.instruction
>= 0x10000)
23311 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
23312 "performance deprecated in ARMv8-A and ARMv8-R"));
23313 now_pred
.warn_deprecated
= TRUE
;
23317 const struct depr_insn_mask
*p
= depr_it_insns
;
23319 while (p
->mask
!= 0)
23321 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
23323 as_tsktsk (_("IT blocks containing 16-bit Thumb "
23324 "instructions of the following class are "
23325 "performance deprecated in ARMv8-A and "
23326 "ARMv8-R: %s"), p
->description
);
23327 now_pred
.warn_deprecated
= TRUE
;
23335 if (now_pred
.block_length
> 1)
23337 as_tsktsk (_("IT blocks containing more than one conditional "
23338 "instruction are performance deprecated in ARMv8-A and "
23340 now_pred
.warn_deprecated
= TRUE
;
23344 is_last
= (now_pred
.mask
== 0x10);
23347 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
23353 force_automatic_it_block_close (void)
23355 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
23357 close_automatic_it_block ();
23358 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
23364 in_pred_block (void)
23366 if (!now_pred
.state_handled
)
23367 handle_pred_state ();
23369 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
23372 /* Whether OPCODE only has T32 encoding. Since this function is only used by
23373 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
23374 here, hence the "known" in the function name. */
23377 known_t32_only_insn (const struct asm_opcode
*opcode
)
23379 /* Original Thumb-1 wide instruction. */
23380 if (opcode
->tencode
== do_t_blx
23381 || opcode
->tencode
== do_t_branch23
23382 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
23383 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
23386 /* Wide-only instruction added to ARMv8-M Baseline. */
23387 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
23388 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
23389 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
23390 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
23396 /* Whether wide instruction variant can be used if available for a valid OPCODE
23400 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
23402 if (known_t32_only_insn (opcode
))
23405 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
23406 of variant T3 of B.W is checked in do_t_branch. */
23407 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
23408 && opcode
->tencode
== do_t_branch
)
23411 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
23412 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
23413 && opcode
->tencode
== do_t_mov_cmp
23414 /* Make sure CMP instruction is not affected. */
23415 && opcode
->aencode
== do_mov
)
23418 /* Wide instruction variants of all instructions with narrow *and* wide
23419 variants become available with ARMv6t2. Other opcodes are either
23420 narrow-only or wide-only and are thus available if OPCODE is valid. */
23421 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
23424 /* OPCODE with narrow only instruction variant or wide variant not
23430 md_assemble (char *str
)
23433 const struct asm_opcode
* opcode
;
23435 /* Align the previous label if needed. */
23436 if (last_label_seen
!= NULL
)
23438 symbol_set_frag (last_label_seen
, frag_now
);
23439 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
23440 S_SET_SEGMENT (last_label_seen
, now_seg
);
23443 memset (&inst
, '\0', sizeof (inst
));
23445 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
23446 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
23448 opcode
= opcode_lookup (&p
);
23451 /* It wasn't an instruction, but it might be a register alias of
23452 the form alias .req reg, or a Neon .dn/.qn directive. */
23453 if (! create_register_alias (str
, p
)
23454 && ! create_neon_reg_alias (str
, p
))
23455 as_bad (_("bad instruction `%s'"), str
);
23460 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
23461 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
23463 /* The value which unconditional instructions should have in place of the
23464 condition field. */
23465 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1u;
23469 arm_feature_set variant
;
23471 variant
= cpu_variant
;
23472 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
23473 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
23474 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
23475 /* Check that this instruction is supported for this CPU. */
23476 if (!opcode
->tvariant
23477 || (thumb_mode
== 1
23478 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
23480 if (opcode
->tencode
== do_t_swi
)
23481 as_bad (_("SVC is not permitted on this architecture"));
23483 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
23486 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
23487 && opcode
->tencode
!= do_t_branch
)
23489 as_bad (_("Thumb does not support conditional execution"));
23493 /* Two things are addressed here:
23494 1) Implicit require narrow instructions on Thumb-1.
23495 This avoids relaxation accidentally introducing Thumb-2
23497 2) Reject wide instructions in non Thumb-2 cores.
23499 Only instructions with narrow and wide variants need to be handled
23500 but selecting all non wide-only instructions is easier. */
23501 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
23502 && !t32_insn_ok (variant
, opcode
))
23504 if (inst
.size_req
== 0)
23506 else if (inst
.size_req
== 4)
23508 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
23509 as_bad (_("selected processor does not support 32bit wide "
23510 "variant of instruction `%s'"), str
);
23512 as_bad (_("selected processor does not support `%s' in "
23513 "Thumb-2 mode"), str
);
23518 inst
.instruction
= opcode
->tvalue
;
23520 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
23522 /* Prepare the pred_insn_type for those encodings that don't set
23524 it_fsm_pre_encode ();
23526 opcode
->tencode ();
23528 it_fsm_post_encode ();
23531 if (!(inst
.error
|| inst
.relax
))
23533 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
23534 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
23535 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
23537 as_bad (_("cannot honor width suffix -- `%s'"), str
);
23542 /* Something has gone badly wrong if we try to relax a fixed size
23544 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
23546 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
23547 *opcode
->tvariant
);
23548 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
23549 set those bits when Thumb-2 32-bit instructions are seen. The impact
23550 of relaxable instructions will be considered later after we finish all
23552 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
23553 variant
= arm_arch_none
;
23555 variant
= cpu_variant
;
23556 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
23557 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
23560 check_neon_suffixes
;
23564 mapping_state (MAP_THUMB
);
23567 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
23571 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
23572 is_bx
= (opcode
->aencode
== do_bx
);
23574 /* Check that this instruction is supported for this CPU. */
23575 if (!(is_bx
&& fix_v4bx
)
23576 && !(opcode
->avariant
&&
23577 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
23579 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
23584 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
23588 inst
.instruction
= opcode
->avalue
;
23589 if (opcode
->tag
== OT_unconditionalF
)
23590 inst
.instruction
|= 0xFU
<< 28;
23592 inst
.instruction
|= inst
.cond
<< 28;
23593 inst
.size
= INSN_SIZE
;
23594 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
23596 it_fsm_pre_encode ();
23597 opcode
->aencode ();
23598 it_fsm_post_encode ();
23600 /* Arm mode bx is marked as both v4T and v5 because it's still required
23601 on a hypothetical non-thumb v5 core. */
23603 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
23605 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
23606 *opcode
->avariant
);
23608 check_neon_suffixes
;
23612 mapping_state (MAP_ARM
);
23617 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
23625 check_pred_blocks_finished (void)
23630 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
23631 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
23632 == MANUAL_PRED_BLOCK
)
23634 if (now_pred
.type
== SCALAR_PRED
)
23635 as_warn (_("section '%s' finished with an open IT block."),
23638 as_warn (_("section '%s' finished with an open VPT/VPST block."),
23642 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
23644 if (now_pred
.type
== SCALAR_PRED
)
23645 as_warn (_("file finished with an open IT block."));
23647 as_warn (_("file finished with an open VPT/VPST block."));
23652 /* Various frobbings of labels and their addresses. */
23655 arm_start_line_hook (void)
23657 last_label_seen
= NULL
;
23661 arm_frob_label (symbolS
* sym
)
23663 last_label_seen
= sym
;
23665 ARM_SET_THUMB (sym
, thumb_mode
);
23667 #if defined OBJ_COFF || defined OBJ_ELF
23668 ARM_SET_INTERWORK (sym
, support_interwork
);
23671 force_automatic_it_block_close ();
23673 /* Note - do not allow local symbols (.Lxxx) to be labelled
23674 as Thumb functions. This is because these labels, whilst
23675 they exist inside Thumb code, are not the entry points for
23676 possible ARM->Thumb calls. Also, these labels can be used
23677 as part of a computed goto or switch statement. eg gcc
23678 can generate code that looks like this:
23680 ldr r2, [pc, .Laaa]
23690 The first instruction loads the address of the jump table.
23691 The second instruction converts a table index into a byte offset.
23692 The third instruction gets the jump address out of the table.
23693 The fourth instruction performs the jump.
23695 If the address stored at .Laaa is that of a symbol which has the
23696 Thumb_Func bit set, then the linker will arrange for this address
23697 to have the bottom bit set, which in turn would mean that the
23698 address computation performed by the third instruction would end
23699 up with the bottom bit set. Since the ARM is capable of unaligned
23700 word loads, the instruction would then load the incorrect address
23701 out of the jump table, and chaos would ensue. */
23702 if (label_is_thumb_function_name
23703 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
23704 && (bfd_section_flags (now_seg
) & SEC_CODE
) != 0)
23706 /* When the address of a Thumb function is taken the bottom
23707 bit of that address should be set. This will allow
23708 interworking between Arm and Thumb functions to work
23711 THUMB_SET_FUNC (sym
, 1);
23713 label_is_thumb_function_name
= FALSE
;
23716 dwarf2_emit_label (sym
);
23720 arm_data_in_code (void)
23722 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
23724 *input_line_pointer
= '/';
23725 input_line_pointer
+= 5;
23726 *input_line_pointer
= 0;
23734 arm_canonicalize_symbol_name (char * name
)
23738 if (thumb_mode
&& (len
= strlen (name
)) > 5
23739 && streq (name
+ len
- 5, "/data"))
23740 *(name
+ len
- 5) = 0;
23745 /* Table of all register names defined by default. The user can
23746 define additional names with .req. Note that all register names
23747 should appear in both upper and lowercase variants. Some registers
23748 also have mixed-case names. */
23750 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
23751 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
23752 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
23753 #define REGSET(p,t) \
23754 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
23755 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
23756 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
23757 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
23758 #define REGSETH(p,t) \
23759 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
23760 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
23761 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
23762 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
23763 #define REGSET2(p,t) \
23764 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
23765 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
23766 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
23767 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
23768 #define SPLRBANK(base,bank,t) \
23769 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
23770 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
23771 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
23772 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
23773 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
23774 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
23776 static const struct reg_entry reg_names
[] =
23778 /* ARM integer registers. */
23779 REGSET(r
, RN
), REGSET(R
, RN
),
23781 /* ATPCS synonyms. */
23782 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
23783 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
23784 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
23786 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
23787 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
23788 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
23790 /* Well-known aliases. */
23791 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
23792 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
23794 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
23795 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
23797 /* Defining the new Zero register from ARMv8.1-M. */
23801 /* Coprocessor numbers. */
23802 REGSET(p
, CP
), REGSET(P
, CP
),
23804 /* Coprocessor register numbers. The "cr" variants are for backward
23806 REGSET(c
, CN
), REGSET(C
, CN
),
23807 REGSET(cr
, CN
), REGSET(CR
, CN
),
23809 /* ARM banked registers. */
23810 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
23811 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
23812 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
23813 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
23814 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
23815 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
23816 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
23818 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
23819 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
23820 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
23821 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
23822 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
23823 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
23824 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
23825 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
23827 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
23828 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
23829 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
23830 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
23831 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
23832 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
23833 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
23834 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23835 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23837 /* FPA registers. */
23838 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
23839 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
23841 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
23842 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
23844 /* VFP SP registers. */
23845 REGSET(s
,VFS
), REGSET(S
,VFS
),
23846 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
23848 /* VFP DP Registers. */
23849 REGSET(d
,VFD
), REGSET(D
,VFD
),
23850 /* Extra Neon DP registers. */
23851 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
23853 /* Neon QP registers. */
23854 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
23856 /* VFP control registers. */
23857 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
23858 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
23859 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
23860 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
23861 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
23862 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
23863 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
23864 REGDEF(fpscr_nzcvqc
,2,VFC
), REGDEF(FPSCR_nzcvqc
,2,VFC
),
23865 REGDEF(vpr
,12,VFC
), REGDEF(VPR
,12,VFC
),
23866 REGDEF(fpcxt_ns
,14,VFC
), REGDEF(FPCXT_NS
,14,VFC
),
23867 REGDEF(fpcxt_s
,15,VFC
), REGDEF(FPCXT_S
,15,VFC
),
23869 /* Maverick DSP coprocessor registers. */
23870 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
23871 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
23873 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
23874 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
23875 REGDEF(dspsc
,0,DSPSC
),
23877 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
23878 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
23879 REGDEF(DSPSC
,0,DSPSC
),
23881 /* iWMMXt data registers - p0, c0-15. */
23882 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
23884 /* iWMMXt control registers - p1, c0-3. */
23885 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
23886 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
23887 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
23888 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
23890 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
23891 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
23892 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
23893 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
23894 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
23896 /* XScale accumulator registers. */
23897 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
23903 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
23904 within psr_required_here. */
23905 static const struct asm_psr psrs
[] =
23907 /* Backward compatibility notation. Note that "all" is no longer
23908 truly all possible PSR bits. */
23909 {"all", PSR_c
| PSR_f
},
23913 /* Individual flags. */
23919 /* Combinations of flags. */
23920 {"fs", PSR_f
| PSR_s
},
23921 {"fx", PSR_f
| PSR_x
},
23922 {"fc", PSR_f
| PSR_c
},
23923 {"sf", PSR_s
| PSR_f
},
23924 {"sx", PSR_s
| PSR_x
},
23925 {"sc", PSR_s
| PSR_c
},
23926 {"xf", PSR_x
| PSR_f
},
23927 {"xs", PSR_x
| PSR_s
},
23928 {"xc", PSR_x
| PSR_c
},
23929 {"cf", PSR_c
| PSR_f
},
23930 {"cs", PSR_c
| PSR_s
},
23931 {"cx", PSR_c
| PSR_x
},
23932 {"fsx", PSR_f
| PSR_s
| PSR_x
},
23933 {"fsc", PSR_f
| PSR_s
| PSR_c
},
23934 {"fxs", PSR_f
| PSR_x
| PSR_s
},
23935 {"fxc", PSR_f
| PSR_x
| PSR_c
},
23936 {"fcs", PSR_f
| PSR_c
| PSR_s
},
23937 {"fcx", PSR_f
| PSR_c
| PSR_x
},
23938 {"sfx", PSR_s
| PSR_f
| PSR_x
},
23939 {"sfc", PSR_s
| PSR_f
| PSR_c
},
23940 {"sxf", PSR_s
| PSR_x
| PSR_f
},
23941 {"sxc", PSR_s
| PSR_x
| PSR_c
},
23942 {"scf", PSR_s
| PSR_c
| PSR_f
},
23943 {"scx", PSR_s
| PSR_c
| PSR_x
},
23944 {"xfs", PSR_x
| PSR_f
| PSR_s
},
23945 {"xfc", PSR_x
| PSR_f
| PSR_c
},
23946 {"xsf", PSR_x
| PSR_s
| PSR_f
},
23947 {"xsc", PSR_x
| PSR_s
| PSR_c
},
23948 {"xcf", PSR_x
| PSR_c
| PSR_f
},
23949 {"xcs", PSR_x
| PSR_c
| PSR_s
},
23950 {"cfs", PSR_c
| PSR_f
| PSR_s
},
23951 {"cfx", PSR_c
| PSR_f
| PSR_x
},
23952 {"csf", PSR_c
| PSR_s
| PSR_f
},
23953 {"csx", PSR_c
| PSR_s
| PSR_x
},
23954 {"cxf", PSR_c
| PSR_x
| PSR_f
},
23955 {"cxs", PSR_c
| PSR_x
| PSR_s
},
23956 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
23957 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
23958 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
23959 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
23960 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
23961 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
23962 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
23963 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
23964 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
23965 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
23966 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
23967 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
23968 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
23969 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
23970 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
23971 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
23972 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
23973 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
23974 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
23975 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
23976 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
23977 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
23978 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
23979 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
23982 /* Table of V7M psr names. */
23983 static const struct asm_psr v7m_psrs
[] =
23985 {"apsr", 0x0 }, {"APSR", 0x0 },
23986 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
23987 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
23988 {"psr", 0x3 }, {"PSR", 0x3 },
23989 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
23990 {"ipsr", 0x5 }, {"IPSR", 0x5 },
23991 {"epsr", 0x6 }, {"EPSR", 0x6 },
23992 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
23993 {"msp", 0x8 }, {"MSP", 0x8 },
23994 {"psp", 0x9 }, {"PSP", 0x9 },
23995 {"msplim", 0xa }, {"MSPLIM", 0xa },
23996 {"psplim", 0xb }, {"PSPLIM", 0xb },
23997 {"primask", 0x10}, {"PRIMASK", 0x10},
23998 {"basepri", 0x11}, {"BASEPRI", 0x11},
23999 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
24000 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
24001 {"control", 0x14}, {"CONTROL", 0x14},
24002 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
24003 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
24004 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
24005 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
24006 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
24007 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
24008 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
24009 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
24010 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
24013 /* Table of all shift-in-operand names. */
24014 static const struct asm_shift_name shift_names
[] =
24016 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
24017 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
24018 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
24019 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
24020 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
24021 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
24022 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
24025 /* Table of all explicit relocation names. */
24027 static struct reloc_entry reloc_names
[] =
24029 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
24030 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
24031 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
24032 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
24033 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
24034 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
24035 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
24036 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
24037 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
24038 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
24039 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
24040 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
24041 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
24042 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
24043 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
24044 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
24045 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
24046 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
24047 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
24048 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
24049 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
24050 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
24051 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
24052 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
24053 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
24054 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
24055 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
24059 /* Table of all conditional affixes. */
24060 static const struct asm_cond conds
[] =
24064 {"cs", 0x2}, {"hs", 0x2},
24065 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
24078 static const struct asm_cond vconds
[] =
24084 #define UL_BARRIER(L,U,CODE,FEAT) \
24085 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
24086 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
24088 static struct asm_barrier_opt barrier_opt_names
[] =
24090 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
24091 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
24092 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
24093 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
24094 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
24095 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
24096 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
24097 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
24098 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
24099 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
24100 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
24101 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
24102 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
24103 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
24104 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
24105 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
24110 /* Table of ARM-format instructions. */
24112 /* Macros for gluing together operand strings. N.B. In all cases
24113 other than OPS0, the trailing OP_stop comes from default
24114 zero-initialization of the unspecified elements of the array. */
24115 #define OPS0() { OP_stop, }
24116 #define OPS1(a) { OP_##a, }
24117 #define OPS2(a,b) { OP_##a,OP_##b, }
24118 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
24119 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
24120 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
24121 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
24123 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
24124 This is useful when mixing operands for ARM and THUMB, i.e. using the
24125 MIX_ARM_THUMB_OPERANDS macro.
24126 In order to use these macros, prefix the number of operands with _
24128 #define OPS_1(a) { a, }
24129 #define OPS_2(a,b) { a,b, }
24130 #define OPS_3(a,b,c) { a,b,c, }
24131 #define OPS_4(a,b,c,d) { a,b,c,d, }
24132 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
24133 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
24135 /* These macros abstract out the exact format of the mnemonic table and
24136 save some repeated characters. */
24138 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
24139 #define TxCE(mnem, op, top, nops, ops, ae, te) \
24140 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
24141 THUMB_VARIANT, do_##ae, do_##te, 0 }
24143 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
24144 a T_MNEM_xyz enumerator. */
24145 #define TCE(mnem, aop, top, nops, ops, ae, te) \
24146 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
24147 #define tCE(mnem, aop, top, nops, ops, ae, te) \
24148 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24150 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
24151 infix after the third character. */
24152 #define TxC3(mnem, op, top, nops, ops, ae, te) \
24153 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
24154 THUMB_VARIANT, do_##ae, do_##te, 0 }
24155 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
24156 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
24157 THUMB_VARIANT, do_##ae, do_##te, 0 }
24158 #define TC3(mnem, aop, top, nops, ops, ae, te) \
24159 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
24160 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
24161 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
24162 #define tC3(mnem, aop, top, nops, ops, ae, te) \
24163 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24164 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
24165 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24167 /* Mnemonic that cannot be conditionalized. The ARM condition-code
24168 field is still 0xE. Many of the Thumb variants can be executed
24169 conditionally, so this is checked separately. */
24170 #define TUE(mnem, op, top, nops, ops, ae, te) \
24171 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
24172 THUMB_VARIANT, do_##ae, do_##te, 0 }
24174 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
24175 Used by mnemonics that have very minimal differences in the encoding for
24176 ARM and Thumb variants and can be handled in a common function. */
24177 #define TUEc(mnem, op, top, nops, ops, en) \
24178 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
24179 THUMB_VARIANT, do_##en, do_##en, 0 }
24181 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
24182 condition code field. */
24183 #define TUF(mnem, op, top, nops, ops, ae, te) \
24184 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
24185 THUMB_VARIANT, do_##ae, do_##te, 0 }
24187 /* ARM-only variants of all the above. */
24188 #define CE(mnem, op, nops, ops, ae) \
24189 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24191 #define C3(mnem, op, nops, ops, ae) \
24192 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24194 /* Thumb-only variants of TCE and TUE. */
24195 #define ToC(mnem, top, nops, ops, te) \
24196 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
24199 #define ToU(mnem, top, nops, ops, te) \
24200 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
24203 /* T_MNEM_xyz enumerator variants of ToC. */
24204 #define toC(mnem, top, nops, ops, te) \
24205 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
24208 /* T_MNEM_xyz enumerator variants of ToU. */
24209 #define toU(mnem, top, nops, ops, te) \
24210 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
24213 /* Legacy mnemonics that always have conditional infix after the third
24215 #define CL(mnem, op, nops, ops, ae) \
24216 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
24217 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24219 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
24220 #define cCE(mnem, op, nops, ops, ae) \
24221 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24223 /* mov instructions that are shared between coprocessor and MVE. */
24224 #define mcCE(mnem, op, nops, ops, ae) \
24225 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
24227 /* Legacy coprocessor instructions where conditional infix and conditional
24228 suffix are ambiguous. For consistency this includes all FPA instructions,
24229 not just the potentially ambiguous ones. */
24230 #define cCL(mnem, op, nops, ops, ae) \
24231 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
24232 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24234 /* Coprocessor, takes either a suffix or a position-3 infix
24235 (for an FPA corner case). */
24236 #define C3E(mnem, op, nops, ops, ae) \
24237 { mnem, OPS##nops ops, OT_csuf_or_in3, \
24238 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24240 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
24241 { m1 #m2 m3, OPS##nops ops, \
24242 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
24243 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24245 #define CM(m1, m2, op, nops, ops, ae) \
24246 xCM_ (m1, , m2, op, nops, ops, ae), \
24247 xCM_ (m1, eq, m2, op, nops, ops, ae), \
24248 xCM_ (m1, ne, m2, op, nops, ops, ae), \
24249 xCM_ (m1, cs, m2, op, nops, ops, ae), \
24250 xCM_ (m1, hs, m2, op, nops, ops, ae), \
24251 xCM_ (m1, cc, m2, op, nops, ops, ae), \
24252 xCM_ (m1, ul, m2, op, nops, ops, ae), \
24253 xCM_ (m1, lo, m2, op, nops, ops, ae), \
24254 xCM_ (m1, mi, m2, op, nops, ops, ae), \
24255 xCM_ (m1, pl, m2, op, nops, ops, ae), \
24256 xCM_ (m1, vs, m2, op, nops, ops, ae), \
24257 xCM_ (m1, vc, m2, op, nops, ops, ae), \
24258 xCM_ (m1, hi, m2, op, nops, ops, ae), \
24259 xCM_ (m1, ls, m2, op, nops, ops, ae), \
24260 xCM_ (m1, ge, m2, op, nops, ops, ae), \
24261 xCM_ (m1, lt, m2, op, nops, ops, ae), \
24262 xCM_ (m1, gt, m2, op, nops, ops, ae), \
24263 xCM_ (m1, le, m2, op, nops, ops, ae), \
24264 xCM_ (m1, al, m2, op, nops, ops, ae)
24266 #define UE(mnem, op, nops, ops, ae) \
24267 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24269 #define UF(mnem, op, nops, ops, ae) \
24270 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24272 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
24273 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
24274 use the same encoding function for each. */
24275 #define NUF(mnem, op, nops, ops, enc) \
24276 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
24277 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
24279 /* Neon data processing, version which indirects through neon_enc_tab for
24280 the various overloaded versions of opcodes. */
24281 #define nUF(mnem, op, nops, ops, enc) \
24282 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
24283 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
24285 /* Neon insn with conditional suffix for the ARM version, non-overloaded
24287 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
24288 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
24289 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
24291 #define NCE(mnem, op, nops, ops, enc) \
24292 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
24294 #define NCEF(mnem, op, nops, ops, enc) \
24295 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
24297 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
24298 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
24299 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
24300 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
24302 #define nCE(mnem, op, nops, ops, enc) \
24303 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
24305 #define nCEF(mnem, op, nops, ops, enc) \
24306 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
24309 #define mCEF(mnem, op, nops, ops, enc) \
24310 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
24311 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24314 /* nCEF but for MVE predicated instructions. */
24315 #define mnCEF(mnem, op, nops, ops, enc) \
24316 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
24318 /* nCE but for MVE predicated instructions. */
24319 #define mnCE(mnem, op, nops, ops, enc) \
24320 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
24322 /* NUF but for potentially MVE predicated instructions. */
24323 #define MNUF(mnem, op, nops, ops, enc) \
24324 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
24325 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24327 /* nUF but for potentially MVE predicated instructions. */
24328 #define mnUF(mnem, op, nops, ops, enc) \
24329 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
24330 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24332 /* ToC but for potentially MVE predicated instructions. */
24333 #define mToC(mnem, top, nops, ops, te) \
24334 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
24337 /* NCE but for MVE predicated instructions. */
24338 #define MNCE(mnem, op, nops, ops, enc) \
24339 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
24341 /* NCEF but for MVE predicated instructions. */
24342 #define MNCEF(mnem, op, nops, ops, enc) \
24343 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
24346 static const struct asm_opcode insns
[] =
24348 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
24349 #define THUMB_VARIANT & arm_ext_v4t
24350 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24351 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24352 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24353 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24354 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
24355 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
24356 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
24357 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
24358 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24359 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24360 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24361 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24362 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24363 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24364 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24365 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24367 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
24368 for setting PSR flag bits. They are obsolete in V6 and do not
24369 have Thumb equivalents. */
24370 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24371 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24372 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
24373 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
24374 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
24375 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
24376 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24377 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24378 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
24380 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
24381 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
24382 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
24383 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
24385 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
24386 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
24387 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
24389 OP_ADDRGLDR
),ldst
, t_ldst
),
24390 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
24392 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24393 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24394 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24395 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24396 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24397 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24399 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
24400 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
24403 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
24404 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
24405 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
24406 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
24408 /* Thumb-compatibility pseudo ops. */
24409 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24410 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24411 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24412 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24413 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24414 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24415 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24416 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24417 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
24418 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
24419 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
24420 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
24422 /* These may simplify to neg. */
24423 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
24424 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
24426 #undef THUMB_VARIANT
24427 #define THUMB_VARIANT & arm_ext_os
24429 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
24430 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
24432 #undef THUMB_VARIANT
24433 #define THUMB_VARIANT & arm_ext_v6
24435 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
24437 /* V1 instructions with no Thumb analogue prior to V6T2. */
24438 #undef THUMB_VARIANT
24439 #define THUMB_VARIANT & arm_ext_v6t2
24441 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24442 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24443 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
24445 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24446 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24447 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
24448 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24450 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24451 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24453 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24454 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24456 /* V1 instructions with no Thumb analogue at all. */
24457 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
24458 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
24460 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
24461 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
24462 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
24463 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
24464 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
24465 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
24466 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
24467 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
24470 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
24471 #undef THUMB_VARIANT
24472 #define THUMB_VARIANT & arm_ext_v4t
24474 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
24475 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
24477 #undef THUMB_VARIANT
24478 #define THUMB_VARIANT & arm_ext_v6t2
24480 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
24481 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
24483 /* Generic coprocessor instructions. */
24484 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
24485 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24486 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24487 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24488 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24489 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24490 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24493 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
24495 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
24496 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
24499 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
24500 #undef THUMB_VARIANT
24501 #define THUMB_VARIANT & arm_ext_msr
24503 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
24504 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
24507 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
24508 #undef THUMB_VARIANT
24509 #define THUMB_VARIANT & arm_ext_v6t2
24511 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24512 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24513 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24514 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24515 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24516 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24517 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24518 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24521 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
24522 #undef THUMB_VARIANT
24523 #define THUMB_VARIANT & arm_ext_v4t
24525 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24526 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24527 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24528 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24529 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24530 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24533 #define ARM_VARIANT & arm_ext_v4t_5
24535 /* ARM Architecture 4T. */
24536 /* Note: bx (and blx) are required on V5, even if the processor does
24537 not support Thumb. */
24538 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
24541 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
24542 #undef THUMB_VARIANT
24543 #define THUMB_VARIANT & arm_ext_v5t
24545 /* Note: blx has 2 variants; the .value coded here is for
24546 BLX(2). Only this variant has conditional execution. */
24547 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
24548 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
24550 #undef THUMB_VARIANT
24551 #define THUMB_VARIANT & arm_ext_v6t2
24553 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
24554 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24555 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24556 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24557 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24558 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
24559 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24560 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24563 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
24564 #undef THUMB_VARIANT
24565 #define THUMB_VARIANT & arm_ext_v5exp
24567 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24568 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24569 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24570 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24572 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24573 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24575 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24576 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24577 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24578 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24580 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24581 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24582 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24583 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24585 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24586 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24588 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24589 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24590 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24591 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24594 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
24595 #undef THUMB_VARIANT
24596 #define THUMB_VARIANT & arm_ext_v6t2
24598 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
24599 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
24601 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
24602 ADDRGLDRS
), ldrd
, t_ldstd
),
24604 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24605 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24608 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
24610 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
24613 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
24614 #undef THUMB_VARIANT
24615 #define THUMB_VARIANT & arm_ext_v6
24617 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
24618 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
24619 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24620 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24621 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24622 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24623 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24624 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24625 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24626 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
24628 #undef THUMB_VARIANT
24629 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24631 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
24632 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24634 #undef THUMB_VARIANT
24635 #define THUMB_VARIANT & arm_ext_v6t2
24637 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24638 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24640 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
24641 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
24643 /* ARM V6 not included in V7M. */
24644 #undef THUMB_VARIANT
24645 #define THUMB_VARIANT & arm_ext_v6_notm
24646 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24647 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24648 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
24649 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
24650 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
24651 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24652 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
24653 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
24654 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
24655 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24656 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24657 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24658 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
24659 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
24660 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
24661 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
24662 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
24663 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
24664 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
24666 /* ARM V6 not included in V7M (eg. integer SIMD). */
24667 #undef THUMB_VARIANT
24668 #define THUMB_VARIANT & arm_ext_v6_dsp
24669 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
24670 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
24671 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24672 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24673 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24674 /* Old name for QASX. */
24675 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24676 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24677 /* Old name for QSAX. */
24678 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24679 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24680 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24681 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24682 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24683 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24684 /* Old name for SASX. */
24685 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24686 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24687 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24688 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24689 /* Old name for SHASX. */
24690 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24691 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24692 /* Old name for SHSAX. */
24693 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24694 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24695 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24696 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24697 /* Old name for SSAX. */
24698 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24699 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24700 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24701 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24702 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24703 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24704 /* Old name for UASX. */
24705 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24706 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24707 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24708 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24709 /* Old name for UHASX. */
24710 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24711 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24712 /* Old name for UHSAX. */
24713 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24714 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24715 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24716 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24717 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24718 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24719 /* Old name for UQASX. */
24720 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24721 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24722 /* Old name for UQSAX. */
24723 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24724 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24725 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24726 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24727 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24728 /* Old name for USAX. */
24729 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24730 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24731 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24732 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24733 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24734 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24735 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24736 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24737 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24738 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24739 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24740 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24741 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24742 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24743 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24744 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24745 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24746 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24747 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24748 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24749 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24750 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24751 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24752 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24753 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24754 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24755 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24756 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24757 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24758 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
24759 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
24760 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24761 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24762 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
24765 #define ARM_VARIANT & arm_ext_v6k_v6t2
24766 #undef THUMB_VARIANT
24767 #define THUMB_VARIANT & arm_ext_v6k_v6t2
24769 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
24770 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
24771 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
24772 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
24774 #undef THUMB_VARIANT
24775 #define THUMB_VARIANT & arm_ext_v6_notm
24776 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
24778 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
24779 RRnpcb
), strexd
, t_strexd
),
24781 #undef THUMB_VARIANT
24782 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24783 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
24785 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
24787 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24789 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24791 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
24794 #define ARM_VARIANT & arm_ext_sec
24795 #undef THUMB_VARIANT
24796 #define THUMB_VARIANT & arm_ext_sec
24798 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
24801 #define ARM_VARIANT & arm_ext_virt
24802 #undef THUMB_VARIANT
24803 #define THUMB_VARIANT & arm_ext_virt
24805 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
24806 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
24809 #define ARM_VARIANT & arm_ext_pan
24810 #undef THUMB_VARIANT
24811 #define THUMB_VARIANT & arm_ext_pan
24813 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
24816 #define ARM_VARIANT & arm_ext_v6t2
24817 #undef THUMB_VARIANT
24818 #define THUMB_VARIANT & arm_ext_v6t2
24820 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
24821 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
24822 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24823 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24825 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
24826 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
24828 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24829 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24830 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24831 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24834 #define ARM_VARIANT & arm_ext_v3
24835 #undef THUMB_VARIANT
24836 #define THUMB_VARIANT & arm_ext_v6t2
24838 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
24839 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
24840 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
24843 #define ARM_VARIANT & arm_ext_v6t2
24844 #undef THUMB_VARIANT
24845 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24846 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24847 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24849 /* Thumb-only instructions. */
24851 #define ARM_VARIANT NULL
24852 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
24853 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
24855 /* ARM does not really have an IT instruction, so always allow it.
24856 The opcode is copied from Thumb in order to allow warnings in
24857 -mimplicit-it=[never | arm] modes. */
24859 #define ARM_VARIANT & arm_ext_v1
24860 #undef THUMB_VARIANT
24861 #define THUMB_VARIANT & arm_ext_v6t2
24863 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
24864 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
24865 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
24866 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
24867 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
24868 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
24869 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
24870 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
24871 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
24872 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
24873 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
24874 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
24875 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
24876 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
24877 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
24878 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
24879 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24880 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24882 /* Thumb2 only instructions. */
24884 #define ARM_VARIANT NULL
24886 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24887 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24888 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24889 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24890 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
24891 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
24893 /* Hardware division instructions. */
24895 #define ARM_VARIANT & arm_ext_adiv
24896 #undef THUMB_VARIANT
24897 #define THUMB_VARIANT & arm_ext_div
24899 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24900 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24902 /* ARM V6M/V7 instructions. */
24904 #define ARM_VARIANT & arm_ext_barrier
24905 #undef THUMB_VARIANT
24906 #define THUMB_VARIANT & arm_ext_barrier
24908 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
24909 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
24910 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
24912 /* ARM V7 instructions. */
24914 #define ARM_VARIANT & arm_ext_v7
24915 #undef THUMB_VARIANT
24916 #define THUMB_VARIANT & arm_ext_v7
24918 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
24919 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
24922 #define ARM_VARIANT & arm_ext_mp
24923 #undef THUMB_VARIANT
24924 #define THUMB_VARIANT & arm_ext_mp
24926 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
24928 /* AArchv8 instructions. */
24930 #define ARM_VARIANT & arm_ext_v8
24932 /* Instructions shared between armv8-a and armv8-m. */
24933 #undef THUMB_VARIANT
24934 #define THUMB_VARIANT & arm_ext_atomics
24936 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24937 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24938 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24939 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24940 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24941 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24942 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24943 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
24944 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24945 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24947 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24949 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24951 #undef THUMB_VARIANT
24952 #define THUMB_VARIANT & arm_ext_v8
24954 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
24955 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
24957 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
24959 #undef THUMB_VARIANT
24960 #define THUMB_VARIANT & arm_ext_v8r
24962 #define ARM_VARIANT & arm_ext_v8r
24964 /* ARMv8-R instructions. */
24965 TUF("dfb", 57ff04c
, f3bf8f4c
, 0, (), noargs
, noargs
),
24967 /* Defined in V8 but is in undefined encoding space for earlier
24968 architectures. However earlier architectures are required to treat
24969 this instuction as a semihosting trap as well. Hence while not explicitly
24970 defined as such, it is in fact correct to define the instruction for all
24972 #undef THUMB_VARIANT
24973 #define THUMB_VARIANT & arm_ext_v1
24975 #define ARM_VARIANT & arm_ext_v1
24976 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
24978 /* ARMv8 T32 only. */
24980 #define ARM_VARIANT NULL
24981 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
24982 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
24983 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
24985 /* FP for ARMv8. */
24987 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
24988 #undef THUMB_VARIANT
24989 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
24991 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24992 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24993 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24994 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24995 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
24996 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
24997 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
24998 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
24999 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
25000 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
25001 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
25003 /* Crypto v1 extensions. */
25005 #define ARM_VARIANT & fpu_crypto_ext_armv8
25006 #undef THUMB_VARIANT
25007 #define THUMB_VARIANT & fpu_crypto_ext_armv8
25009 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
25010 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
25011 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
25012 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
25013 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
25014 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
25015 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
25016 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
25017 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
25018 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
25019 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
25020 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
25021 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
25022 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
25025 #define ARM_VARIANT & arm_ext_crc
25026 #undef THUMB_VARIANT
25027 #define THUMB_VARIANT & arm_ext_crc
25028 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
25029 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
25030 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
25031 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
25032 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
25033 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
25035 /* ARMv8.2 RAS extension. */
25037 #define ARM_VARIANT & arm_ext_ras
25038 #undef THUMB_VARIANT
25039 #define THUMB_VARIANT & arm_ext_ras
25040 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
25043 #define ARM_VARIANT & arm_ext_v8_3
25044 #undef THUMB_VARIANT
25045 #define THUMB_VARIANT & arm_ext_v8_3
25046 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
25049 #define ARM_VARIANT & fpu_neon_ext_dotprod
25050 #undef THUMB_VARIANT
25051 #define THUMB_VARIANT & fpu_neon_ext_dotprod
25052 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
25053 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
25056 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
25057 #undef THUMB_VARIANT
25058 #define THUMB_VARIANT NULL
25060 cCE("wfs", e200110
, 1, (RR
), rd
),
25061 cCE("rfs", e300110
, 1, (RR
), rd
),
25062 cCE("wfc", e400110
, 1, (RR
), rd
),
25063 cCE("rfc", e500110
, 1, (RR
), rd
),
25065 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25066 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25067 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25068 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25070 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25071 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25072 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25073 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25075 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
25076 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
25077 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
25078 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
25079 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
25080 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
25081 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
25082 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
25083 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
25084 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
25085 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
25086 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
25088 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
25089 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
25090 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
25091 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
25092 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
25093 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
25094 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
25095 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
25096 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
25097 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
25098 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
25099 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
25101 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
25102 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
25103 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
25104 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
25105 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
25106 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
25107 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
25108 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
25109 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
25110 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
25111 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
25112 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
25114 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
25115 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
25116 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
25117 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
25118 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
25119 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
25120 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
25121 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
25122 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
25123 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
25124 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
25125 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
25127 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
25128 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
25129 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
25130 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
25131 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
25132 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
25133 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
25134 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
25135 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
25136 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
25137 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
25138 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
25140 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
25141 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
25142 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
25143 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
25144 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
25145 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
25146 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
25147 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
25148 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
25149 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
25150 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
25151 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
25153 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
25154 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
25155 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
25156 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
25157 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
25158 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
25159 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
25160 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
25161 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
25162 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
25163 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
25164 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
25166 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
25167 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
25168 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
25169 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
25170 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
25171 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
25172 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
25173 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
25174 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
25175 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
25176 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
25177 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
25179 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
25180 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
25181 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
25182 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
25183 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
25184 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
25185 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
25186 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
25187 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
25188 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
25189 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
25190 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
25192 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
25193 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
25194 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
25195 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
25196 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
25197 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
25198 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
25199 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
25200 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
25201 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
25202 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
25203 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
25205 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
25206 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
25207 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
25208 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
25209 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
25210 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
25211 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
25212 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
25213 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
25214 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
25215 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
25216 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
25218 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
25219 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
25220 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
25221 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
25222 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
25223 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
25224 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
25225 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
25226 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
25227 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
25228 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
25229 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
25231 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
25232 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
25233 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
25234 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
25235 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
25236 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
25237 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
25238 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
25239 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
25240 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
25241 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
25242 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
25244 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
25245 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
25246 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
25247 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
25248 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
25249 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
25250 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
25251 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
25252 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
25253 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
25254 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
25255 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
25257 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
25258 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
25259 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
25260 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
25261 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
25262 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
25263 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
25264 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
25265 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
25266 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
25267 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
25268 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
25270 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
25271 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
25272 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
25273 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
25274 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
25275 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
25276 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
25277 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
25278 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
25279 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
25280 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
25281 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
25283 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25284 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25285 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25286 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25287 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25288 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25289 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25290 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25291 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25292 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25293 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25294 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25296 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25297 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25298 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25299 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25300 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25301 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25302 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25303 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25304 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25305 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25306 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25307 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25309 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25310 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25311 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25312 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25313 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25314 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25315 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25316 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25317 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25318 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25319 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25320 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25322 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25323 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25324 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25325 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25326 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25327 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25328 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25329 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25330 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25331 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25332 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25333 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25335 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25336 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25337 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25338 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25339 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25340 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25341 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25342 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25343 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25344 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25345 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25346 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25348 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25349 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25350 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25351 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25352 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25353 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25354 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25355 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25356 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25357 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25358 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25359 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25361 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25362 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25363 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25364 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25365 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25366 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25367 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25368 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25369 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25370 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25371 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25372 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25374 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25375 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25376 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25377 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25378 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25379 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25380 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25381 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25382 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25383 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25384 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25385 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25387 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25388 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25389 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25390 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25391 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25392 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25393 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25394 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25395 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25396 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25397 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25398 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25400 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25401 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25402 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25403 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25404 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25405 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25406 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25407 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25408 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25409 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25410 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25411 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25413 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25414 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25415 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25416 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25417 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25418 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25419 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25420 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25421 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25422 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25423 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25424 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25426 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25427 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25428 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25429 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25430 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25431 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25432 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25433 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25434 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25435 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25436 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25437 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25439 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25440 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25441 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25442 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25443 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25444 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25445 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25446 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25447 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25448 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25449 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25450 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25452 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25453 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25454 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25455 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25457 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
25458 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
25459 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
25460 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
25461 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
25462 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
25463 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
25464 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
25465 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
25466 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
25467 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
25468 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
25470 /* The implementation of the FIX instruction is broken on some
25471 assemblers, in that it accepts a precision specifier as well as a
25472 rounding specifier, despite the fact that this is meaningless.
25473 To be more compatible, we accept it as well, though of course it
25474 does not set any bits. */
25475 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
25476 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
25477 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
25478 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
25479 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
25480 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
25481 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
25482 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
25483 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
25484 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
25485 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
25486 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
25487 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
25489 /* Instructions that were new with the real FPA, call them V2. */
25491 #define ARM_VARIANT & fpu_fpa_ext_v2
25493 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25494 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25495 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25496 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25497 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25498 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25501 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
25502 #undef THUMB_VARIANT
25503 #define THUMB_VARIANT & arm_ext_v6t2
25504 mcCE(vmrs
, ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
25505 mcCE(vmsr
, ee00a10
, 2, (RVC
, RR
), vmsr
),
25506 mcCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
25507 mcCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
25508 mcCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
25509 mcCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
25511 /* Memory operations. */
25512 mcCE(fldmias
, c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25513 mcCE(fldmdbs
, d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25514 mcCE(fstmias
, c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25515 mcCE(fstmdbs
, d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25516 #undef THUMB_VARIANT
25518 /* Moves and type conversions. */
25519 cCE("fmstat", ef1fa10
, 0, (), noargs
),
25520 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25521 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25522 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25523 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25524 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25525 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25526 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
25527 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
25529 /* Memory operations. */
25530 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25531 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25532 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25533 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25534 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25535 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25536 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25537 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25538 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25539 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25540 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25541 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25543 /* Monadic operations. */
25544 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25545 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25546 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25548 /* Dyadic operations. */
25549 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25550 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25551 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25552 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25553 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25554 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25555 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25556 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25557 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25560 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25561 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
25562 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25563 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
25565 /* Double precision load/store are still present on single precision
25566 implementations. */
25567 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25568 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25569 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25570 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25571 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25572 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25573 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25574 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25577 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
25579 /* Moves and type conversions. */
25580 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25581 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25582 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
25583 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
25584 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
25585 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
25586 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25587 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25588 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25589 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25590 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25591 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25593 /* Monadic operations. */
25594 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25595 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25596 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25598 /* Dyadic operations. */
25599 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25600 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25601 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25602 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25603 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25604 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25605 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25606 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25607 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25610 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25611 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
25612 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25613 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
25615 /* Instructions which may belong to either the Neon or VFP instruction sets.
25616 Individual encoder functions perform additional architecture checks. */
25618 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25619 #undef THUMB_VARIANT
25620 #define THUMB_VARIANT & arm_ext_v6t2
25622 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25623 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25624 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25625 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25626 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25627 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25629 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
25630 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
25632 #undef THUMB_VARIANT
25633 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
25635 /* These mnemonics are unique to VFP. */
25636 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
25637 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
25638 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25639 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25640 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25641 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
25643 /* Mnemonics shared by Neon and VFP. */
25644 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
25646 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
25647 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
25648 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
25649 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
25652 /* NOTE: All VMOV encoding is special-cased! */
25653 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
25655 #undef THUMB_VARIANT
25656 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
25657 by different feature bits. Since we are setting the Thumb guard, we can
25658 require Thumb-1 which makes it a nop guard and set the right feature bit in
25659 do_vldr_vstr (). */
25660 #define THUMB_VARIANT & arm_ext_v4t
25661 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
25662 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
25665 #define ARM_VARIANT & arm_ext_fp16
25666 #undef THUMB_VARIANT
25667 #define THUMB_VARIANT & arm_ext_fp16
25668 /* New instructions added from v8.2, allowing the extraction and insertion of
25669 the upper 16 bits of a 32-bit vector register. */
25670 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
25671 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
25673 /* New backported fma/fms instructions optional in v8.2. */
25674 NUF (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
25675 NUF (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
25677 #undef THUMB_VARIANT
25678 #define THUMB_VARIANT & fpu_neon_ext_v1
25680 #define ARM_VARIANT & fpu_neon_ext_v1
25682 /* Data processing with three registers of the same length. */
25683 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
25684 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
25685 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
25686 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25687 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25688 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25689 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
25690 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
25691 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
25692 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
25693 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
25694 /* If not immediate, fall back to neon_dyadic_i64_su.
25695 shl should accept I8 I16 I32 I64,
25696 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
25697 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl
),
25698 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl
),
25699 /* Logic ops, types optional & ignored. */
25700 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25701 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25702 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25703 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25704 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
25705 /* Bitfield ops, untyped. */
25706 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25707 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25708 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25709 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25710 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25711 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25712 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
25713 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25714 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25715 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25716 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
25717 back to neon_dyadic_if_su. */
25718 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
25719 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
25720 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
25721 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
25722 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
25723 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
25724 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
25725 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
25726 /* Comparison. Type I8 I16 I32 F32. */
25727 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
25728 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
25729 /* As above, D registers only. */
25730 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
25731 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
25732 /* Int and float variants, signedness unimportant. */
25733 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
25734 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
25735 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
25736 /* Add/sub take types I8 I16 I32 I64 F32. */
25737 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
25738 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
25739 /* vtst takes sizes 8, 16, 32. */
25740 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
25741 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
25742 /* VMUL takes I8 I16 I32 F32 P8. */
25743 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
25744 /* VQD{R}MULH takes S16 S32. */
25745 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
25746 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
25747 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
25748 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
25749 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
25750 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
25751 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
25752 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
25753 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
25754 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
25755 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
25756 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
25757 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
25758 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
25759 /* ARM v8.1 extension. */
25760 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
25761 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
25762 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
25764 /* Two address, int/float. Types S8 S16 S32 F32. */
25765 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
25766 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
25768 /* Data processing with two registers and a shift amount. */
25769 /* Right shifts, and variants with rounding.
25770 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
25771 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
25772 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
25773 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
25774 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
25775 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
25776 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
25777 /* Shift and insert. Sizes accepted 8 16 32 64. */
25778 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
25779 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
25780 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
25781 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
25782 /* Right shift immediate, saturating & narrowing, with rounding variants.
25783 Types accepted S16 S32 S64 U16 U32 U64. */
25784 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
25785 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
25786 /* As above, unsigned. Types accepted S16 S32 S64. */
25787 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
25788 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
25789 /* Right shift narrowing. Types accepted I16 I32 I64. */
25790 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
25791 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
25792 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
25793 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
25794 /* CVT with optional immediate for fixed-point variant. */
25795 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
25797 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
25799 /* Data processing, three registers of different lengths. */
25800 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
25801 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
25802 /* If not scalar, fall back to neon_dyadic_long.
25803 Vector types as above, scalar types S16 S32 U16 U32. */
25804 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
25805 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
25806 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
25807 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
25808 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
25809 /* Dyadic, narrowing insns. Types I16 I32 I64. */
25810 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25811 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25812 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25813 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25814 /* Saturating doubling multiplies. Types S16 S32. */
25815 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25816 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25817 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25818 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
25819 S16 S32 U16 U32. */
25820 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
25822 /* Extract. Size 8. */
25823 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
25824 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
25826 /* Two registers, miscellaneous. */
25827 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
25828 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
25829 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
25830 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
25831 /* Vector replicate. Sizes 8 16 32. */
25832 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
25833 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
25834 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
25835 /* VMOVN. Types I16 I32 I64. */
25836 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
25837 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
25838 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
25839 /* VQMOVUN. Types S16 S32 S64. */
25840 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
25841 /* VZIP / VUZP. Sizes 8 16 32. */
25842 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25843 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25844 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25845 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25846 /* VQABS / VQNEG. Types S8 S16 S32. */
25847 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25848 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25849 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
25850 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25851 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
25852 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25853 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
25854 /* Reciprocal estimates. Types U32 F16 F32. */
25855 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25856 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
25857 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25858 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
25859 /* VCLS. Types S8 S16 S32. */
25860 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
25861 /* VCLZ. Types I8 I16 I32. */
25862 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
25863 /* VCNT. Size 8. */
25864 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
25865 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
25866 /* Two address, untyped. */
25867 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
25868 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
25869 /* VTRN. Sizes 8 16 32. */
25870 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
25871 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
25873 /* Table lookup. Size 8. */
25874 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25875 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25877 #undef THUMB_VARIANT
25878 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
25880 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
25882 /* Neon element/structure load/store. */
25883 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25884 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25885 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25886 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25887 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25888 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25889 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25890 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25892 #undef THUMB_VARIANT
25893 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
25895 #define ARM_VARIANT & fpu_vfp_ext_v3xd
25896 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
25897 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25898 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25899 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25900 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25901 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25902 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25903 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25904 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25906 #undef THUMB_VARIANT
25907 #define THUMB_VARIANT & fpu_vfp_ext_v3
25909 #define ARM_VARIANT & fpu_vfp_ext_v3
25911 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
25912 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25913 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25914 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25915 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25916 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25917 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25918 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25919 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25922 #define ARM_VARIANT & fpu_vfp_ext_fma
25923 #undef THUMB_VARIANT
25924 #define THUMB_VARIANT & fpu_vfp_ext_fma
25925 /* Mnemonics shared by Neon, VFP, MVE and BF16. These are included in the
25926 VFP FMA variant; NEON and VFP FMA always includes the NEON
25927 FMA instructions. */
25928 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
25929 TUF ("vfmat", c300850
, fc300850
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), mve_vfma
, mve_vfma
),
25930 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
25932 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
25933 the v form should always be used. */
25934 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25935 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25936 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25937 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25938 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25939 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25941 #undef THUMB_VARIANT
25943 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
25945 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25946 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25947 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25948 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25949 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25950 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25951 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
25952 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
25955 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
25957 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
25958 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
25959 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
25960 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
25961 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
25962 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
25963 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
25964 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
25965 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
25966 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25967 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25968 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25969 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25970 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25971 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25972 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25973 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25974 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25975 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
25976 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
25977 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25978 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25979 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25980 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25981 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25982 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25983 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
25984 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
25985 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
25986 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
25987 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
25988 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
25989 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
25990 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
25991 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25992 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25993 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25994 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25995 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25996 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25997 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25998 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25999 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26000 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26001 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26002 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26003 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
26004 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26005 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26006 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26007 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26008 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26009 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26010 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26011 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26012 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26013 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26014 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26015 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26016 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26017 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26018 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26019 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26020 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26021 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26022 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26023 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26024 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26025 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
26026 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
26027 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26028 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26029 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26030 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26031 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26032 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26033 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26034 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26035 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26036 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26037 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26038 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26039 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26040 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26041 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26042 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26043 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26044 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26045 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
26046 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26047 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26048 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26049 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26050 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26051 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26052 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26053 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26054 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26055 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26056 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26057 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26058 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26059 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26060 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26061 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26062 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26063 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26064 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26065 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26066 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26067 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
26068 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26069 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26070 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26071 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26072 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26073 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26074 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26075 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26076 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26077 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26078 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26079 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26080 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26081 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26082 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26083 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26084 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26085 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26086 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26087 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26088 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
26089 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
26090 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26091 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26092 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26093 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26094 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26095 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26096 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26097 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26098 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26099 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26100 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26101 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26102 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26103 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26104 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26105 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26106 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26107 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26108 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26109 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26110 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26111 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26112 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26113 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26114 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26115 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26116 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26117 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26118 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
26121 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
26123 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
26124 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
26125 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
26126 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26127 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26128 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26129 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26130 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26131 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26132 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26133 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26134 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26135 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26136 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26137 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26138 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26139 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26140 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26141 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26142 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26143 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
26144 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26145 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26146 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26147 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26148 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26149 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26150 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26151 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26152 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26153 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26154 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26155 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26156 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26157 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26158 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26159 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26160 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26161 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26162 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26163 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26164 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26165 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26166 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26167 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26168 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26169 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26170 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26171 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26172 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26173 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26174 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26175 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26176 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26177 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26178 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26179 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26182 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
26184 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
26185 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
26186 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
26187 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
26188 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
26189 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
26190 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
26191 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
26192 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
26193 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
26194 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
26195 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
26196 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
26197 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
26198 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
26199 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
26200 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
26201 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
26202 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
26203 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
26204 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
26205 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
26206 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
26207 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
26208 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
26209 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
26210 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
26211 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
26212 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
26213 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
26214 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
26215 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
26216 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
26217 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
26218 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
26219 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
26220 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
26221 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
26222 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
26223 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
26224 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
26225 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
26226 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
26227 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
26228 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
26229 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
26230 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
26231 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
26232 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
26233 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
26234 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
26235 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
26236 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
26237 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
26238 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26239 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26240 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26241 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26242 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26243 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26244 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
26245 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
26246 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
26247 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
26248 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26249 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26250 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26251 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26252 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26253 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26254 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26255 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26256 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
26257 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
26258 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
26259 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
26261 /* ARMv8.5-A instructions. */
26263 #define ARM_VARIANT & arm_ext_sb
26264 #undef THUMB_VARIANT
26265 #define THUMB_VARIANT & arm_ext_sb
26266 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
26269 #define ARM_VARIANT & arm_ext_predres
26270 #undef THUMB_VARIANT
26271 #define THUMB_VARIANT & arm_ext_predres
26272 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
26273 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
26274 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
26276 /* ARMv8-M instructions. */
26278 #define ARM_VARIANT NULL
26279 #undef THUMB_VARIANT
26280 #define THUMB_VARIANT & arm_ext_v8m
26281 ToU("sg", e97fe97f
, 0, (), noargs
),
26282 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
26283 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
26284 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
26285 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
26286 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
26287 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
26289 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
26290 instructions behave as nop if no VFP is present. */
26291 #undef THUMB_VARIANT
26292 #define THUMB_VARIANT & arm_ext_v8m_main
26293 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
26294 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
26296 /* Armv8.1-M Mainline instructions. */
26297 #undef THUMB_VARIANT
26298 #define THUMB_VARIANT & arm_ext_v8_1m_main
26299 toU("cinc", _cinc
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26300 toU("cinv", _cinv
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26301 toU("cneg", _cneg
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26302 toU("csel", _csel
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26303 toU("csetm", _csetm
, 2, (RRnpcsp
, COND
), t_cond
),
26304 toU("cset", _cset
, 2, (RRnpcsp
, COND
), t_cond
),
26305 toU("csinc", _csinc
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26306 toU("csinv", _csinv
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26307 toU("csneg", _csneg
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26309 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
26310 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
26311 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
26312 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
26313 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
26315 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
26316 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
26317 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
26319 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
26320 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
26322 #undef THUMB_VARIANT
26323 #define THUMB_VARIANT & mve_ext
26324 ToC("lsll", ea50010d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
26325 ToC("lsrl", ea50011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26326 ToC("asrl", ea50012d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
26327 ToC("uqrshll", ea51010d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
26328 ToC("sqrshrl", ea51012d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
26329 ToC("uqshll", ea51010f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26330 ToC("urshrl", ea51011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26331 ToC("srshrl", ea51012f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26332 ToC("sqshll", ea51013f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26333 ToC("uqrshl", ea500f0d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
26334 ToC("sqrshr", ea500f2d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
26335 ToC("uqshl", ea500f0f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26336 ToC("urshr", ea500f1f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26337 ToC("srshr", ea500f2f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26338 ToC("sqshl", ea500f3f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26340 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26341 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26342 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26343 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26344 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26345 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26346 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26347 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26348 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26349 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26350 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26351 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26352 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26353 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26354 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26356 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
26357 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
26358 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
26359 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
26360 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
26361 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
26362 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
26363 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
26364 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
26365 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
26366 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
26367 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
26368 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
26369 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
26370 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
26372 /* MVE and MVE FP only. */
26373 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
26374 mCEF(vctp
, _vctp
, 1, (RRnpc
), mve_vctp
),
26375 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
26376 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
26377 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
26378 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
26379 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
26380 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
26381 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26382 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26383 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26384 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26385 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26386 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26387 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26388 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26389 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26390 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26392 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26393 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26394 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26395 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26396 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26397 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26398 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26399 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26400 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26401 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26402 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26403 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26404 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26405 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26406 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26407 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26408 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26409 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26410 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26411 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26413 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
26414 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
26415 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
26416 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
26417 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
26418 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
26419 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
26420 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
26421 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
26422 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
26423 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
26424 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
26425 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
26426 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
26427 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
26428 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
26429 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
26431 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26432 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26433 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26434 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26435 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26436 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26437 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26438 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26439 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26440 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26441 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26442 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26443 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26444 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26445 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26446 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26447 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26448 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26449 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26450 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26452 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
26453 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
26454 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
26455 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
26456 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
26458 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26459 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26460 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26461 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26462 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26463 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26464 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26465 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26466 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26467 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26468 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26469 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
26470 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
26471 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26472 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26473 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26474 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26476 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26477 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26478 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26479 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26480 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26481 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26482 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26483 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26484 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26485 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26486 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26487 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26489 mToC("vshlc", eea00fc0
, 3, (RMQ
, RR
, I32z
), mve_vshlc
),
26490 mToC("vshllt", ee201e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
26491 mToC("vshllb", ee200e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
26493 toU("dlstp", _dlstp
, 2, (LR
, RR
), t_loloop
),
26494 toU("wlstp", _wlstp
, 3, (LR
, RR
, EXP
), t_loloop
),
26495 toU("letp", _letp
, 2, (LR
, EXP
), t_loloop
),
26496 toU("lctp", _lctp
, 0, (), t_loloop
),
26498 #undef THUMB_VARIANT
26499 #define THUMB_VARIANT & mve_fp_ext
26500 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
26501 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
26502 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
26503 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
26504 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26505 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26506 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26507 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26510 #define ARM_VARIANT & fpu_vfp_ext_v1
26511 #undef THUMB_VARIANT
26512 #define THUMB_VARIANT & arm_ext_v6t2
26513 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
26514 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
26516 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
26519 #define ARM_VARIANT & fpu_vfp_ext_v1xd
26521 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
26522 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
26523 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
26524 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
26526 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
26527 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
26528 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
26530 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
26531 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
26533 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
26534 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
26536 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
26537 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
26540 #define ARM_VARIANT & fpu_vfp_ext_v2
26542 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
26543 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
26544 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
26545 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
26548 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
26549 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
26550 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
26551 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
26552 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
26553 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
26554 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
26557 #define ARM_VARIANT & fpu_neon_ext_v1
26558 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26559 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
26560 mnUF(vaddl
, _vaddl
, 3, (RNSDQMQ
, oRNSDMQ
, RNSDMQR
), neon_dyadic_long
),
26561 mnUF(vsubl
, _vsubl
, 3, (RNSDQMQ
, oRNSDMQ
, RNSDMQR
), neon_dyadic_long
),
26562 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26563 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26564 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26565 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26566 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
26567 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
26568 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
26569 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
26570 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
26571 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
26572 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
26573 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26574 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26575 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
26576 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
26577 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
26578 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
26579 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
26580 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
26581 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
26582 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
26583 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
26584 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
26585 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
26586 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
26587 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
26588 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
26589 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26590 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26591 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26592 mnUF(vshl
, _vshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_shl
),
26593 mnUF(vqshl
, _vqshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_qshl
),
26594 MNUF(vqshlu
, 1800610, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_qshlu_imm
),
26597 #define ARM_VARIANT & arm_ext_v8_3
26598 #undef THUMB_VARIANT
26599 #define THUMB_VARIANT & arm_ext_v6t2_v8m
26600 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
26601 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
26604 #define ARM_VARIANT &arm_ext_bf16
26605 #undef THUMB_VARIANT
26606 #define THUMB_VARIANT &arm_ext_bf16
26607 TUF ("vdot", c000d00
, fc000d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), vdot
, vdot
),
26608 TUF ("vmmla", c000c40
, fc000c40
, 3, (RNQ
, RNQ
, RNQ
), vmmla
, vmmla
),
26609 TUF ("vfmab", c300810
, fc300810
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), bfloat_vfma
, bfloat_vfma
),
26612 #define ARM_VARIANT &arm_ext_i8mm
26613 #undef THUMB_VARIANT
26614 #define THUMB_VARIANT &arm_ext_i8mm
26615 TUF ("vsmmla", c200c40
, fc200c40
, 3, (RNQ
, RNQ
, RNQ
), vsmmla
, vsmmla
),
26616 TUF ("vummla", c200c50
, fc200c50
, 3, (RNQ
, RNQ
, RNQ
), vummla
, vummla
),
26617 TUF ("vusmmla", ca00c40
, fca00c40
, 3, (RNQ
, RNQ
, RNQ
), vsmmla
, vsmmla
),
26618 TUF ("vusdot", c800d00
, fc800d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), vusdot
, vusdot
),
26619 TUF ("vsudot", c800d10
, fc800d10
, 3, (RNDQ
, RNDQ
, RNSC
), vsudot
, vsudot
),
26622 #undef THUMB_VARIANT
26623 #define THUMB_VARIANT &arm_ext_cde
26624 ToC ("cx1", ee000000
, 3, (RCP
, APSR_RR
, I8191
), cx1
),
26625 ToC ("cx1a", fe000000
, 3, (RCP
, APSR_RR
, I8191
), cx1a
),
26626 ToC ("cx1d", ee000040
, 4, (RCP
, RR
, APSR_RR
, I8191
), cx1d
),
26627 ToC ("cx1da", fe000040
, 4, (RCP
, RR
, APSR_RR
, I8191
), cx1da
),
26629 ToC ("cx2", ee400000
, 4, (RCP
, APSR_RR
, APSR_RR
, I511
), cx2
),
26630 ToC ("cx2a", fe400000
, 4, (RCP
, APSR_RR
, APSR_RR
, I511
), cx2a
),
26631 ToC ("cx2d", ee400040
, 5, (RCP
, RR
, APSR_RR
, APSR_RR
, I511
), cx2d
),
26632 ToC ("cx2da", fe400040
, 5, (RCP
, RR
, APSR_RR
, APSR_RR
, I511
), cx2da
),
26634 ToC ("cx3", ee800000
, 5, (RCP
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3
),
26635 ToC ("cx3a", fe800000
, 5, (RCP
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3a
),
26636 ToC ("cx3d", ee800040
, 6, (RCP
, RR
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3d
),
26637 ToC ("cx3da", fe800040
, 6, (RCP
, RR
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3da
),
26639 mToC ("vcx1", ec200000
, 3, (RCP
, RNSDMQ
, I4095
), vcx1
),
26640 mToC ("vcx1a", fc200000
, 3, (RCP
, RNSDMQ
, I4095
), vcx1
),
26642 mToC ("vcx2", ec300000
, 4, (RCP
, RNSDMQ
, RNSDMQ
, I127
), vcx2
),
26643 mToC ("vcx2a", fc300000
, 4, (RCP
, RNSDMQ
, RNSDMQ
, I127
), vcx2
),
26645 mToC ("vcx3", ec800000
, 5, (RCP
, RNSDMQ
, RNSDMQ
, RNSDMQ
, I15
), vcx3
),
26646 mToC ("vcx3a", fc800000
, 5, (RCP
, RNSDMQ
, RNSDMQ
, RNSDMQ
, I15
), vcx3
),
26650 #undef THUMB_VARIANT
26682 /* MD interface: bits in the object file. */
26684 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
26685 for use in the a.out file, and stores them in the array pointed to by buf.
26686 This knows about the endian-ness of the target machine and does
26687 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
26688 2 (short) and 4 (long) Floating numbers are put out as a series of
26689 LITTLENUMS (shorts, here at least). */
26692 md_number_to_chars (char * buf
, valueT val
, int n
)
26694 if (target_big_endian
)
26695 number_to_chars_bigendian (buf
, val
, n
);
26697 number_to_chars_littleendian (buf
, val
, n
);
26701 md_chars_to_number (char * buf
, int n
)
26704 unsigned char * where
= (unsigned char *) buf
;
26706 if (target_big_endian
)
26711 result
|= (*where
++ & 255);
26719 result
|= (where
[n
] & 255);
26726 /* MD interface: Sections. */
26728 /* Calculate the maximum variable size (i.e., excluding fr_fix)
26729 that an rs_machine_dependent frag may reach. */
26732 arm_frag_max_var (fragS
*fragp
)
26734 /* We only use rs_machine_dependent for variable-size Thumb instructions,
26735 which are either THUMB_SIZE (2) or INSN_SIZE (4).
26737 Note that we generate relaxable instructions even for cases that don't
26738 really need it, like an immediate that's a trivial constant. So we're
26739 overestimating the instruction size for some of those cases. Rather
26740 than putting more intelligence here, it would probably be better to
26741 avoid generating a relaxation frag in the first place when it can be
26742 determined up front that a short instruction will suffice. */
26744 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
26748 /* Estimate the size of a frag before relaxing. Assume everything fits in
26752 md_estimate_size_before_relax (fragS
* fragp
,
26753 segT segtype ATTRIBUTE_UNUSED
)
26759 /* Convert a machine dependent frag. */
26762 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
26764 unsigned long insn
;
26765 unsigned long old_op
;
26773 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
26775 old_op
= bfd_get_16(abfd
, buf
);
26776 if (fragp
->fr_symbol
)
26778 exp
.X_op
= O_symbol
;
26779 exp
.X_add_symbol
= fragp
->fr_symbol
;
26783 exp
.X_op
= O_constant
;
26785 exp
.X_add_number
= fragp
->fr_offset
;
26786 opcode
= fragp
->fr_subtype
;
26789 case T_MNEM_ldr_pc
:
26790 case T_MNEM_ldr_pc2
:
26791 case T_MNEM_ldr_sp
:
26792 case T_MNEM_str_sp
:
26799 if (fragp
->fr_var
== 4)
26801 insn
= THUMB_OP32 (opcode
);
26802 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
26804 insn
|= (old_op
& 0x700) << 4;
26808 insn
|= (old_op
& 7) << 12;
26809 insn
|= (old_op
& 0x38) << 13;
26811 insn
|= 0x00000c00;
26812 put_thumb32_insn (buf
, insn
);
26813 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
26817 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
26819 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
26822 if (fragp
->fr_var
== 4)
26824 insn
= THUMB_OP32 (opcode
);
26825 insn
|= (old_op
& 0xf0) << 4;
26826 put_thumb32_insn (buf
, insn
);
26827 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
26831 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26832 exp
.X_add_number
-= 4;
26840 if (fragp
->fr_var
== 4)
26842 int r0off
= (opcode
== T_MNEM_mov
26843 || opcode
== T_MNEM_movs
) ? 0 : 8;
26844 insn
= THUMB_OP32 (opcode
);
26845 insn
= (insn
& 0xe1ffffff) | 0x10000000;
26846 insn
|= (old_op
& 0x700) << r0off
;
26847 put_thumb32_insn (buf
, insn
);
26848 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26852 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
26857 if (fragp
->fr_var
== 4)
26859 insn
= THUMB_OP32(opcode
);
26860 put_thumb32_insn (buf
, insn
);
26861 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
26864 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
26868 if (fragp
->fr_var
== 4)
26870 insn
= THUMB_OP32(opcode
);
26871 insn
|= (old_op
& 0xf00) << 14;
26872 put_thumb32_insn (buf
, insn
);
26873 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
26876 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
26879 case T_MNEM_add_sp
:
26880 case T_MNEM_add_pc
:
26881 case T_MNEM_inc_sp
:
26882 case T_MNEM_dec_sp
:
26883 if (fragp
->fr_var
== 4)
26885 /* ??? Choose between add and addw. */
26886 insn
= THUMB_OP32 (opcode
);
26887 insn
|= (old_op
& 0xf0) << 4;
26888 put_thumb32_insn (buf
, insn
);
26889 if (opcode
== T_MNEM_add_pc
)
26890 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
26892 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26895 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26903 if (fragp
->fr_var
== 4)
26905 insn
= THUMB_OP32 (opcode
);
26906 insn
|= (old_op
& 0xf0) << 4;
26907 insn
|= (old_op
& 0xf) << 16;
26908 put_thumb32_insn (buf
, insn
);
26909 if (insn
& (1 << 20))
26910 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26912 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26915 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26921 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
26922 (enum bfd_reloc_code_real
) reloc_type
);
26923 fixp
->fx_file
= fragp
->fr_file
;
26924 fixp
->fx_line
= fragp
->fr_line
;
26925 fragp
->fr_fix
+= fragp
->fr_var
;
26927 /* Set whether we use thumb-2 ISA based on final relaxation results. */
26928 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
26929 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
26930 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
26933 /* Return the size of a relaxable immediate operand instruction.
26934 SHIFT and SIZE specify the form of the allowable immediate. */
26936 relax_immediate (fragS
*fragp
, int size
, int shift
)
26942 /* ??? Should be able to do better than this. */
26943 if (fragp
->fr_symbol
)
26946 low
= (1 << shift
) - 1;
26947 mask
= (1 << (shift
+ size
)) - (1 << shift
);
26948 offset
= fragp
->fr_offset
;
26949 /* Force misaligned offsets to 32-bit variant. */
26952 if (offset
& ~mask
)
26957 /* Get the address of a symbol during relaxation. */
26959 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
26965 sym
= fragp
->fr_symbol
;
26966 sym_frag
= symbol_get_frag (sym
);
26967 know (S_GET_SEGMENT (sym
) != absolute_section
26968 || sym_frag
== &zero_address_frag
);
26969 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
26971 /* If frag has yet to be reached on this pass, assume it will
26972 move by STRETCH just as we did. If this is not so, it will
26973 be because some frag between grows, and that will force
26977 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
26981 /* Adjust stretch for any alignment frag. Note that if have
26982 been expanding the earlier code, the symbol may be
26983 defined in what appears to be an earlier frag. FIXME:
26984 This doesn't handle the fr_subtype field, which specifies
26985 a maximum number of bytes to skip when doing an
26987 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
26989 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
26992 stretch
= - ((- stretch
)
26993 & ~ ((1 << (int) f
->fr_offset
) - 1));
26995 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
27007 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
27010 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
27015 /* Assume worst case for symbols not known to be in the same section. */
27016 if (fragp
->fr_symbol
== NULL
27017 || !S_IS_DEFINED (fragp
->fr_symbol
)
27018 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
27019 || S_IS_WEAK (fragp
->fr_symbol
))
27022 val
= relaxed_symbol_addr (fragp
, stretch
);
27023 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
27024 addr
= (addr
+ 4) & ~3;
27025 /* Force misaligned targets to 32-bit variant. */
27029 if (val
< 0 || val
> 1020)
27034 /* Return the size of a relaxable add/sub immediate instruction. */
27036 relax_addsub (fragS
*fragp
, asection
*sec
)
27041 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
27042 op
= bfd_get_16(sec
->owner
, buf
);
27043 if ((op
& 0xf) == ((op
>> 4) & 0xf))
27044 return relax_immediate (fragp
, 8, 0);
27046 return relax_immediate (fragp
, 3, 0);
27049 /* Return TRUE iff the definition of symbol S could be pre-empted
27050 (overridden) at link or load time. */
27052 symbol_preemptible (symbolS
*s
)
27054 /* Weak symbols can always be pre-empted. */
27058 /* Non-global symbols cannot be pre-empted. */
27059 if (! S_IS_EXTERNAL (s
))
27063 /* In ELF, a global symbol can be marked protected, or private. In that
27064 case it can't be pre-empted (other definitions in the same link unit
27065 would violate the ODR). */
27066 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
27070 /* Other global symbols might be pre-empted. */
27074 /* Return the size of a relaxable branch instruction. BITS is the
27075 size of the offset field in the narrow instruction. */
27078 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
27084 /* Assume worst case for symbols not known to be in the same section. */
27085 if (!S_IS_DEFINED (fragp
->fr_symbol
)
27086 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
27087 || S_IS_WEAK (fragp
->fr_symbol
))
27091 /* A branch to a function in ARM state will require interworking. */
27092 if (S_IS_DEFINED (fragp
->fr_symbol
)
27093 && ARM_IS_FUNC (fragp
->fr_symbol
))
27097 if (symbol_preemptible (fragp
->fr_symbol
))
27100 val
= relaxed_symbol_addr (fragp
, stretch
);
27101 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
27104 /* Offset is a signed value *2 */
27106 if (val
>= limit
|| val
< -limit
)
27112 /* Relax a machine dependent frag. This returns the amount by which
27113 the current size of the frag should change. */
27116 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
27121 oldsize
= fragp
->fr_var
;
27122 switch (fragp
->fr_subtype
)
27124 case T_MNEM_ldr_pc2
:
27125 newsize
= relax_adr (fragp
, sec
, stretch
);
27127 case T_MNEM_ldr_pc
:
27128 case T_MNEM_ldr_sp
:
27129 case T_MNEM_str_sp
:
27130 newsize
= relax_immediate (fragp
, 8, 2);
27134 newsize
= relax_immediate (fragp
, 5, 2);
27138 newsize
= relax_immediate (fragp
, 5, 1);
27142 newsize
= relax_immediate (fragp
, 5, 0);
27145 newsize
= relax_adr (fragp
, sec
, stretch
);
27151 newsize
= relax_immediate (fragp
, 8, 0);
27154 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
27157 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
27159 case T_MNEM_add_sp
:
27160 case T_MNEM_add_pc
:
27161 newsize
= relax_immediate (fragp
, 8, 2);
27163 case T_MNEM_inc_sp
:
27164 case T_MNEM_dec_sp
:
27165 newsize
= relax_immediate (fragp
, 7, 2);
27171 newsize
= relax_addsub (fragp
, sec
);
27177 fragp
->fr_var
= newsize
;
27178 /* Freeze wide instructions that are at or before the same location as
27179 in the previous pass. This avoids infinite loops.
27180 Don't freeze them unconditionally because targets may be artificially
27181 misaligned by the expansion of preceding frags. */
27182 if (stretch
<= 0 && newsize
> 2)
27184 md_convert_frag (sec
->owner
, sec
, fragp
);
27188 return newsize
- oldsize
;
27191 /* Round up a section size to the appropriate boundary. */
27194 md_section_align (segT segment ATTRIBUTE_UNUSED
,
27200 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
27201 of an rs_align_code fragment. */
27204 arm_handle_align (fragS
* fragP
)
27206 static unsigned char const arm_noop
[2][2][4] =
27209 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
27210 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
27213 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
27214 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
27217 static unsigned char const thumb_noop
[2][2][2] =
27220 {0xc0, 0x46}, /* LE */
27221 {0x46, 0xc0}, /* BE */
27224 {0x00, 0xbf}, /* LE */
27225 {0xbf, 0x00} /* BE */
27228 static unsigned char const wide_thumb_noop
[2][4] =
27229 { /* Wide Thumb-2 */
27230 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
27231 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
27234 unsigned bytes
, fix
, noop_size
;
27236 const unsigned char * noop
;
27237 const unsigned char *narrow_noop
= NULL
;
27242 if (fragP
->fr_type
!= rs_align_code
)
27245 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
27246 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
27249 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
27250 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
27252 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
27254 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
27256 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
27257 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
27259 narrow_noop
= thumb_noop
[1][target_big_endian
];
27260 noop
= wide_thumb_noop
[target_big_endian
];
27263 noop
= thumb_noop
[0][target_big_endian
];
27271 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
27272 ? selected_cpu
: arm_arch_none
,
27274 [target_big_endian
];
27281 fragP
->fr_var
= noop_size
;
27283 if (bytes
& (noop_size
- 1))
27285 fix
= bytes
& (noop_size
- 1);
27287 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
27289 memset (p
, 0, fix
);
27296 if (bytes
& noop_size
)
27298 /* Insert a narrow noop. */
27299 memcpy (p
, narrow_noop
, noop_size
);
27301 bytes
-= noop_size
;
27305 /* Use wide noops for the remainder */
27309 while (bytes
>= noop_size
)
27311 memcpy (p
, noop
, noop_size
);
27313 bytes
-= noop_size
;
27317 fragP
->fr_fix
+= fix
;
27320 /* Called from md_do_align. Used to create an alignment
27321 frag in a code section. */
27324 arm_frag_align_code (int n
, int max
)
27328 /* We assume that there will never be a requirement
27329 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
27330 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
27335 _("alignments greater than %d bytes not supported in .text sections."),
27336 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
27337 as_fatal ("%s", err_msg
);
27340 p
= frag_var (rs_align_code
,
27341 MAX_MEM_FOR_RS_ALIGN_CODE
,
27343 (relax_substateT
) max
,
27350 /* Perform target specific initialisation of a frag.
27351 Note - despite the name this initialisation is not done when the frag
27352 is created, but only when its type is assigned. A frag can be created
27353 and used a long time before its type is set, so beware of assuming that
27354 this initialisation is performed first. */
27358 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
27360 /* Record whether this frag is in an ARM or a THUMB area. */
27361 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
27364 #else /* OBJ_ELF is defined. */
27366 arm_init_frag (fragS
* fragP
, int max_chars
)
27368 bfd_boolean frag_thumb_mode
;
27370 /* If the current ARM vs THUMB mode has not already
27371 been recorded into this frag then do so now. */
27372 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
27373 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
27375 /* PR 21809: Do not set a mapping state for debug sections
27376 - it just confuses other tools. */
27377 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
27380 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
27382 /* Record a mapping symbol for alignment frags. We will delete this
27383 later if the alignment ends up empty. */
27384 switch (fragP
->fr_type
)
27387 case rs_align_test
:
27389 mapping_state_2 (MAP_DATA
, max_chars
);
27391 case rs_align_code
:
27392 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
27399 /* When we change sections we need to issue a new mapping symbol. */
27402 arm_elf_change_section (void)
27404 /* Link an unlinked unwind index table section to the .text section. */
27405 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
27406 && elf_linked_to_section (now_seg
) == NULL
)
27407 elf_linked_to_section (now_seg
) = text_section
;
27411 arm_elf_section_type (const char * str
, size_t len
)
27413 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
27414 return SHT_ARM_EXIDX
;
27419 /* Code to deal with unwinding tables. */
27421 static void add_unwind_adjustsp (offsetT
);
27423 /* Generate any deferred unwind frame offset. */
27426 flush_pending_unwind (void)
27430 offset
= unwind
.pending_offset
;
27431 unwind
.pending_offset
= 0;
27433 add_unwind_adjustsp (offset
);
27436 /* Add an opcode to this list for this function. Two-byte opcodes should
27437 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
27441 add_unwind_opcode (valueT op
, int length
)
27443 /* Add any deferred stack adjustment. */
27444 if (unwind
.pending_offset
)
27445 flush_pending_unwind ();
27447 unwind
.sp_restored
= 0;
27449 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
27451 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
27452 if (unwind
.opcodes
)
27453 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
27454 unwind
.opcode_alloc
);
27456 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
27461 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
27463 unwind
.opcode_count
++;
27467 /* Add unwind opcodes to adjust the stack pointer. */
27470 add_unwind_adjustsp (offsetT offset
)
27474 if (offset
> 0x200)
27476 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
27481 /* Long form: 0xb2, uleb128. */
27482 /* This might not fit in a word so add the individual bytes,
27483 remembering the list is built in reverse order. */
27484 o
= (valueT
) ((offset
- 0x204) >> 2);
27486 add_unwind_opcode (0, 1);
27488 /* Calculate the uleb128 encoding of the offset. */
27492 bytes
[n
] = o
& 0x7f;
27498 /* Add the insn. */
27500 add_unwind_opcode (bytes
[n
- 1], 1);
27501 add_unwind_opcode (0xb2, 1);
27503 else if (offset
> 0x100)
27505 /* Two short opcodes. */
27506 add_unwind_opcode (0x3f, 1);
27507 op
= (offset
- 0x104) >> 2;
27508 add_unwind_opcode (op
, 1);
27510 else if (offset
> 0)
27512 /* Short opcode. */
27513 op
= (offset
- 4) >> 2;
27514 add_unwind_opcode (op
, 1);
27516 else if (offset
< 0)
27519 while (offset
> 0x100)
27521 add_unwind_opcode (0x7f, 1);
27524 op
= ((offset
- 4) >> 2) | 0x40;
27525 add_unwind_opcode (op
, 1);
27529 /* Finish the list of unwind opcodes for this function. */
27532 finish_unwind_opcodes (void)
27536 if (unwind
.fp_used
)
27538 /* Adjust sp as necessary. */
27539 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
27540 flush_pending_unwind ();
27542 /* After restoring sp from the frame pointer. */
27543 op
= 0x90 | unwind
.fp_reg
;
27544 add_unwind_opcode (op
, 1);
27547 flush_pending_unwind ();
27551 /* Start an exception table entry. If idx is nonzero this is an index table
27555 start_unwind_section (const segT text_seg
, int idx
)
27557 const char * text_name
;
27558 const char * prefix
;
27559 const char * prefix_once
;
27560 struct elf_section_match match
;
27568 prefix
= ELF_STRING_ARM_unwind
;
27569 prefix_once
= ELF_STRING_ARM_unwind_once
;
27570 type
= SHT_ARM_EXIDX
;
27574 prefix
= ELF_STRING_ARM_unwind_info
;
27575 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
27576 type
= SHT_PROGBITS
;
27579 text_name
= segment_name (text_seg
);
27580 if (streq (text_name
, ".text"))
27583 if (strncmp (text_name
, ".gnu.linkonce.t.",
27584 strlen (".gnu.linkonce.t.")) == 0)
27586 prefix
= prefix_once
;
27587 text_name
+= strlen (".gnu.linkonce.t.");
27590 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
27594 memset (&match
, 0, sizeof (match
));
27596 /* Handle COMDAT group. */
27597 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
27599 match
.group_name
= elf_group_name (text_seg
);
27600 if (match
.group_name
== NULL
)
27602 as_bad (_("Group section `%s' has no group signature"),
27603 segment_name (text_seg
));
27604 ignore_rest_of_line ();
27607 flags
|= SHF_GROUP
;
27611 obj_elf_change_section (sec_name
, type
, flags
, 0, &match
,
27614 /* Set the section link for index tables. */
27616 elf_linked_to_section (now_seg
) = text_seg
;
27620 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
27621 personality routine data. Returns zero, or the index table value for
27622 an inline entry. */
27625 create_unwind_entry (int have_data
)
27630 /* The current word of data. */
27632 /* The number of bytes left in this word. */
27635 finish_unwind_opcodes ();
27637 /* Remember the current text section. */
27638 unwind
.saved_seg
= now_seg
;
27639 unwind
.saved_subseg
= now_subseg
;
27641 start_unwind_section (now_seg
, 0);
27643 if (unwind
.personality_routine
== NULL
)
27645 if (unwind
.personality_index
== -2)
27648 as_bad (_("handlerdata in cantunwind frame"));
27649 return 1; /* EXIDX_CANTUNWIND. */
27652 /* Use a default personality routine if none is specified. */
27653 if (unwind
.personality_index
== -1)
27655 if (unwind
.opcode_count
> 3)
27656 unwind
.personality_index
= 1;
27658 unwind
.personality_index
= 0;
27661 /* Space for the personality routine entry. */
27662 if (unwind
.personality_index
== 0)
27664 if (unwind
.opcode_count
> 3)
27665 as_bad (_("too many unwind opcodes for personality routine 0"));
27669 /* All the data is inline in the index table. */
27672 while (unwind
.opcode_count
> 0)
27674 unwind
.opcode_count
--;
27675 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
27679 /* Pad with "finish" opcodes. */
27681 data
= (data
<< 8) | 0xb0;
27688 /* We get two opcodes "free" in the first word. */
27689 size
= unwind
.opcode_count
- 2;
27693 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
27694 if (unwind
.personality_index
!= -1)
27696 as_bad (_("attempt to recreate an unwind entry"));
27700 /* An extra byte is required for the opcode count. */
27701 size
= unwind
.opcode_count
+ 1;
27704 size
= (size
+ 3) >> 2;
27706 as_bad (_("too many unwind opcodes"));
27708 frag_align (2, 0, 0);
27709 record_alignment (now_seg
, 2);
27710 unwind
.table_entry
= expr_build_dot ();
27712 /* Allocate the table entry. */
27713 ptr
= frag_more ((size
<< 2) + 4);
27714 /* PR 13449: Zero the table entries in case some of them are not used. */
27715 memset (ptr
, 0, (size
<< 2) + 4);
27716 where
= frag_now_fix () - ((size
<< 2) + 4);
27718 switch (unwind
.personality_index
)
27721 /* ??? Should this be a PLT generating relocation? */
27722 /* Custom personality routine. */
27723 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
27724 BFD_RELOC_ARM_PREL31
);
27729 /* Set the first byte to the number of additional words. */
27730 data
= size
> 0 ? size
- 1 : 0;
27734 /* ABI defined personality routines. */
27736 /* Three opcodes bytes are packed into the first word. */
27743 /* The size and first two opcode bytes go in the first word. */
27744 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
27749 /* Should never happen. */
27753 /* Pack the opcodes into words (MSB first), reversing the list at the same
27755 while (unwind
.opcode_count
> 0)
27759 md_number_to_chars (ptr
, data
, 4);
27764 unwind
.opcode_count
--;
27766 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
27769 /* Finish off the last word. */
27772 /* Pad with "finish" opcodes. */
27774 data
= (data
<< 8) | 0xb0;
27776 md_number_to_chars (ptr
, data
, 4);
27781 /* Add an empty descriptor if there is no user-specified data. */
27782 ptr
= frag_more (4);
27783 md_number_to_chars (ptr
, 0, 4);
27790 /* Initialize the DWARF-2 unwind information for this procedure. */
27793 tc_arm_frame_initial_instructions (void)
27795 cfi_add_CFA_def_cfa (REG_SP
, 0);
27797 #endif /* OBJ_ELF */
27799 /* Convert REGNAME to a DWARF-2 register number. */
27802 tc_arm_regname_to_dw2regnum (char *regname
)
27804 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
27808 /* PR 16694: Allow VFP registers as well. */
27809 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
27813 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
27822 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
27826 exp
.X_op
= O_secrel
;
27827 exp
.X_add_symbol
= symbol
;
27828 exp
.X_add_number
= 0;
27829 emit_expr (&exp
, size
);
27833 /* MD interface: Symbol and relocation handling. */
27835 /* Return the address within the segment that a PC-relative fixup is
27836 relative to. For ARM, PC-relative fixups applied to instructions
27837 are generally relative to the location of the fixup plus 8 bytes.
27838 Thumb branches are offset by 4, and Thumb loads relative to PC
27839 require special handling. */
27842 md_pcrel_from_section (fixS
* fixP
, segT seg
)
27844 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27846 /* If this is pc-relative and we are going to emit a relocation
27847 then we just want to put out any pipeline compensation that the linker
27848 will need. Otherwise we want to use the calculated base.
27849 For WinCE we skip the bias for externals as well, since this
27850 is how the MS ARM-CE assembler behaves and we want to be compatible. */
27852 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27853 || (arm_force_relocation (fixP
)
27855 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
27861 switch (fixP
->fx_r_type
)
27863 /* PC relative addressing on the Thumb is slightly odd as the
27864 bottom two bits of the PC are forced to zero for the
27865 calculation. This happens *after* application of the
27866 pipeline offset. However, Thumb adrl already adjusts for
27867 this, so we need not do it again. */
27868 case BFD_RELOC_ARM_THUMB_ADD
:
27871 case BFD_RELOC_ARM_THUMB_OFFSET
:
27872 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27873 case BFD_RELOC_ARM_T32_ADD_PC12
:
27874 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
27875 return (base
+ 4) & ~3;
27877 /* Thumb branches are simply offset by +4. */
27878 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
27879 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
27880 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
27881 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
27882 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27883 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27884 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
27885 case BFD_RELOC_ARM_THUMB_BF17
:
27886 case BFD_RELOC_ARM_THUMB_BF19
:
27887 case BFD_RELOC_ARM_THUMB_BF13
:
27888 case BFD_RELOC_ARM_THUMB_LOOP12
:
27891 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27893 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27894 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27895 && ARM_IS_FUNC (fixP
->fx_addsy
)
27896 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27897 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27900 /* BLX is like branches above, but forces the low two bits of PC to
27902 case BFD_RELOC_THUMB_PCREL_BLX
:
27904 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27905 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27906 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27907 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27908 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27909 return (base
+ 4) & ~3;
27911 /* ARM mode branches are offset by +8. However, the Windows CE
27912 loader expects the relocation not to take this into account. */
27913 case BFD_RELOC_ARM_PCREL_BLX
:
27915 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27916 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27917 && ARM_IS_FUNC (fixP
->fx_addsy
)
27918 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27919 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27922 case BFD_RELOC_ARM_PCREL_CALL
:
27924 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27925 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27926 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27927 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27928 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27931 case BFD_RELOC_ARM_PCREL_BRANCH
:
27932 case BFD_RELOC_ARM_PCREL_JUMP
:
27933 case BFD_RELOC_ARM_PLT32
:
27935 /* When handling fixups immediately, because we have already
27936 discovered the value of a symbol, or the address of the frag involved
27937 we must account for the offset by +8, as the OS loader will never see the reloc.
27938 see fixup_segment() in write.c
27939 The S_IS_EXTERNAL test handles the case of global symbols.
27940 Those need the calculated base, not just the pipe compensation the linker will need. */
27942 && fixP
->fx_addsy
!= NULL
27943 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27944 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
27952 /* ARM mode loads relative to PC are also offset by +8. Unlike
27953 branches, the Windows CE loader *does* expect the relocation
27954 to take this into account. */
27955 case BFD_RELOC_ARM_OFFSET_IMM
:
27956 case BFD_RELOC_ARM_OFFSET_IMM8
:
27957 case BFD_RELOC_ARM_HWLITERAL
:
27958 case BFD_RELOC_ARM_LITERAL
:
27959 case BFD_RELOC_ARM_CP_OFF_IMM
:
27963 /* Other PC-relative relocations are un-offset. */
27969 static bfd_boolean flag_warn_syms
= TRUE
;
27972 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
27974 /* PR 18347 - Warn if the user attempts to create a symbol with the same
27975 name as an ARM instruction. Whilst strictly speaking it is allowed, it
27976 does mean that the resulting code might be very confusing to the reader.
27977 Also this warning can be triggered if the user omits an operand before
27978 an immediate address, eg:
27982 GAS treats this as an assignment of the value of the symbol foo to a
27983 symbol LDR, and so (without this code) it will not issue any kind of
27984 warning or error message.
27986 Note - ARM instructions are case-insensitive but the strings in the hash
27987 table are all stored in lower case, so we must first ensure that name is
27989 if (flag_warn_syms
&& arm_ops_hsh
)
27991 char * nbuf
= strdup (name
);
27994 for (p
= nbuf
; *p
; p
++)
27996 if (str_hash_find (arm_ops_hsh
, nbuf
) != NULL
)
27998 static htab_t already_warned
= NULL
;
28000 if (already_warned
== NULL
)
28001 already_warned
= str_htab_create ();
28002 /* Only warn about the symbol once. To keep the code
28003 simple we let str_hash_insert do the lookup for us. */
28004 if (str_hash_find (already_warned
, nbuf
) == NULL
)
28006 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
28007 str_hash_insert (already_warned
, nbuf
, NULL
, 0);
28017 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
28018 Otherwise we have no need to default values of symbols. */
28021 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
28024 if (name
[0] == '_' && name
[1] == 'G'
28025 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
28029 if (symbol_find (name
))
28030 as_bad (_("GOT already in the symbol table"));
28032 GOT_symbol
= symbol_new (name
, undefined_section
,
28033 &zero_address_frag
, 0);
28043 /* Subroutine of md_apply_fix. Check to see if an immediate can be
28044 computed as two separate immediate values, added together. We
28045 already know that this value cannot be computed by just one ARM
28048 static unsigned int
28049 validate_immediate_twopart (unsigned int val
,
28050 unsigned int * highpart
)
28055 for (i
= 0; i
< 32; i
+= 2)
28056 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
28062 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
28064 else if (a
& 0xff0000)
28066 if (a
& 0xff000000)
28068 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
28072 gas_assert (a
& 0xff000000);
28073 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
28076 return (a
& 0xff) | (i
<< 7);
28083 validate_offset_imm (unsigned int val
, int hwse
)
28085 if ((hwse
&& val
> 255) || val
> 4095)
28090 /* Subroutine of md_apply_fix. Do those data_ops which can take a
28091 negative immediate constant by altering the instruction. A bit of
28096 by inverting the second operand, and
28099 by negating the second operand. */
28102 negate_data_op (unsigned long * instruction
,
28103 unsigned long value
)
28106 unsigned long negated
, inverted
;
28108 negated
= encode_arm_immediate (-value
);
28109 inverted
= encode_arm_immediate (~value
);
28111 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
28114 /* First negates. */
28115 case OPCODE_SUB
: /* ADD <-> SUB */
28116 new_inst
= OPCODE_ADD
;
28121 new_inst
= OPCODE_SUB
;
28125 case OPCODE_CMP
: /* CMP <-> CMN */
28126 new_inst
= OPCODE_CMN
;
28131 new_inst
= OPCODE_CMP
;
28135 /* Now Inverted ops. */
28136 case OPCODE_MOV
: /* MOV <-> MVN */
28137 new_inst
= OPCODE_MVN
;
28142 new_inst
= OPCODE_MOV
;
28146 case OPCODE_AND
: /* AND <-> BIC */
28147 new_inst
= OPCODE_BIC
;
28152 new_inst
= OPCODE_AND
;
28156 case OPCODE_ADC
: /* ADC <-> SBC */
28157 new_inst
= OPCODE_SBC
;
28162 new_inst
= OPCODE_ADC
;
28166 /* We cannot do anything. */
28171 if (value
== (unsigned) FAIL
)
28174 *instruction
&= OPCODE_MASK
;
28175 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
28179 /* Like negate_data_op, but for Thumb-2. */
28181 static unsigned int
28182 thumb32_negate_data_op (valueT
*instruction
, unsigned int value
)
28184 unsigned int op
, new_inst
;
28186 unsigned int negated
, inverted
;
28188 negated
= encode_thumb32_immediate (-value
);
28189 inverted
= encode_thumb32_immediate (~value
);
28191 rd
= (*instruction
>> 8) & 0xf;
28192 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
28195 /* ADD <-> SUB. Includes CMP <-> CMN. */
28196 case T2_OPCODE_SUB
:
28197 new_inst
= T2_OPCODE_ADD
;
28201 case T2_OPCODE_ADD
:
28202 new_inst
= T2_OPCODE_SUB
;
28206 /* ORR <-> ORN. Includes MOV <-> MVN. */
28207 case T2_OPCODE_ORR
:
28208 new_inst
= T2_OPCODE_ORN
;
28212 case T2_OPCODE_ORN
:
28213 new_inst
= T2_OPCODE_ORR
;
28217 /* AND <-> BIC. TST has no inverted equivalent. */
28218 case T2_OPCODE_AND
:
28219 new_inst
= T2_OPCODE_BIC
;
28226 case T2_OPCODE_BIC
:
28227 new_inst
= T2_OPCODE_AND
;
28232 case T2_OPCODE_ADC
:
28233 new_inst
= T2_OPCODE_SBC
;
28237 case T2_OPCODE_SBC
:
28238 new_inst
= T2_OPCODE_ADC
;
28242 /* We cannot do anything. */
28247 if (value
== (unsigned int)FAIL
)
28250 *instruction
&= T2_OPCODE_MASK
;
28251 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
28255 /* Read a 32-bit thumb instruction from buf. */
28257 static unsigned long
28258 get_thumb32_insn (char * buf
)
28260 unsigned long insn
;
28261 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
28262 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28267 /* We usually want to set the low bit on the address of thumb function
28268 symbols. In particular .word foo - . should have the low bit set.
28269 Generic code tries to fold the difference of two symbols to
28270 a constant. Prevent this and force a relocation when the first symbols
28271 is a thumb function. */
28274 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
28276 if (op
== O_subtract
28277 && l
->X_op
== O_symbol
28278 && r
->X_op
== O_symbol
28279 && THUMB_IS_FUNC (l
->X_add_symbol
))
28281 l
->X_op
= O_subtract
;
28282 l
->X_op_symbol
= r
->X_add_symbol
;
28283 l
->X_add_number
-= r
->X_add_number
;
28287 /* Process as normal. */
28291 /* Encode Thumb2 unconditional branches and calls. The encoding
28292 for the 2 are identical for the immediate values. */
28295 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
28297 #define T2I1I2MASK ((1 << 13) | (1 << 11))
28300 addressT S
, I1
, I2
, lo
, hi
;
28302 S
= (value
>> 24) & 0x01;
28303 I1
= (value
>> 23) & 0x01;
28304 I2
= (value
>> 22) & 0x01;
28305 hi
= (value
>> 12) & 0x3ff;
28306 lo
= (value
>> 1) & 0x7ff;
28307 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28308 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28309 newval
|= (S
<< 10) | hi
;
28310 newval2
&= ~T2I1I2MASK
;
28311 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
28312 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28313 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28317 md_apply_fix (fixS
* fixP
,
28321 valueT value
= * valP
;
28323 unsigned int newimm
;
28324 unsigned long temp
;
28326 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
28328 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
28330 /* Note whether this will delete the relocation. */
28332 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
28335 /* On a 64-bit host, silently truncate 'value' to 32 bits for
28336 consistency with the behaviour on 32-bit hosts. Remember value
28338 value
&= 0xffffffff;
28339 value
^= 0x80000000;
28340 value
-= 0x80000000;
28343 fixP
->fx_addnumber
= value
;
28345 /* Same treatment for fixP->fx_offset. */
28346 fixP
->fx_offset
&= 0xffffffff;
28347 fixP
->fx_offset
^= 0x80000000;
28348 fixP
->fx_offset
-= 0x80000000;
28350 switch (fixP
->fx_r_type
)
28352 case BFD_RELOC_NONE
:
28353 /* This will need to go in the object file. */
28357 case BFD_RELOC_ARM_IMMEDIATE
:
28358 /* We claim that this fixup has been processed here,
28359 even if in fact we generate an error because we do
28360 not have a reloc for it, so tc_gen_reloc will reject it. */
28363 if (fixP
->fx_addsy
)
28365 const char *msg
= 0;
28367 if (! S_IS_DEFINED (fixP
->fx_addsy
))
28368 msg
= _("undefined symbol %s used as an immediate value");
28369 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
28370 msg
= _("symbol %s is in a different section");
28371 else if (S_IS_WEAK (fixP
->fx_addsy
))
28372 msg
= _("symbol %s is weak and may be overridden later");
28376 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28377 msg
, S_GET_NAME (fixP
->fx_addsy
));
28382 temp
= md_chars_to_number (buf
, INSN_SIZE
);
28384 /* If the offset is negative, we should use encoding A2 for ADR. */
28385 if ((temp
& 0xfff0000) == 0x28f0000 && (offsetT
) value
< 0)
28386 newimm
= negate_data_op (&temp
, value
);
28389 newimm
= encode_arm_immediate (value
);
28391 /* If the instruction will fail, see if we can fix things up by
28392 changing the opcode. */
28393 if (newimm
== (unsigned int) FAIL
)
28394 newimm
= negate_data_op (&temp
, value
);
28395 /* MOV accepts both ARM modified immediate (A1 encoding) and
28396 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
28397 When disassembling, MOV is preferred when there is no encoding
28399 if (newimm
== (unsigned int) FAIL
28400 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
28401 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
28402 && !((temp
>> SBIT_SHIFT
) & 0x1)
28403 && value
<= 0xffff)
28405 /* Clear bits[23:20] to change encoding from A1 to A2. */
28406 temp
&= 0xff0fffff;
28407 /* Encoding high 4bits imm. Code below will encode the remaining
28409 temp
|= (value
& 0x0000f000) << 4;
28410 newimm
= value
& 0x00000fff;
28414 if (newimm
== (unsigned int) FAIL
)
28416 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28417 _("invalid constant (%lx) after fixup"),
28418 (unsigned long) value
);
28422 newimm
|= (temp
& 0xfffff000);
28423 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
28426 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
28428 unsigned int highpart
= 0;
28429 unsigned int newinsn
= 0xe1a00000; /* nop. */
28431 if (fixP
->fx_addsy
)
28433 const char *msg
= 0;
28435 if (! S_IS_DEFINED (fixP
->fx_addsy
))
28436 msg
= _("undefined symbol %s used as an immediate value");
28437 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
28438 msg
= _("symbol %s is in a different section");
28439 else if (S_IS_WEAK (fixP
->fx_addsy
))
28440 msg
= _("symbol %s is weak and may be overridden later");
28444 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28445 msg
, S_GET_NAME (fixP
->fx_addsy
));
28450 newimm
= encode_arm_immediate (value
);
28451 temp
= md_chars_to_number (buf
, INSN_SIZE
);
28453 /* If the instruction will fail, see if we can fix things up by
28454 changing the opcode. */
28455 if (newimm
== (unsigned int) FAIL
28456 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
28458 /* No ? OK - try using two ADD instructions to generate
28460 newimm
= validate_immediate_twopart (value
, & highpart
);
28462 /* Yes - then make sure that the second instruction is
28464 if (newimm
!= (unsigned int) FAIL
)
28466 /* Still No ? Try using a negated value. */
28467 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
28468 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
28469 /* Otherwise - give up. */
28472 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28473 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
28478 /* Replace the first operand in the 2nd instruction (which
28479 is the PC) with the destination register. We have
28480 already added in the PC in the first instruction and we
28481 do not want to do it again. */
28482 newinsn
&= ~ 0xf0000;
28483 newinsn
|= ((newinsn
& 0x0f000) << 4);
28486 newimm
|= (temp
& 0xfffff000);
28487 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
28489 highpart
|= (newinsn
& 0xfffff000);
28490 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
28494 case BFD_RELOC_ARM_OFFSET_IMM
:
28495 if (!fixP
->fx_done
&& seg
->use_rela_p
)
28497 /* Fall through. */
28499 case BFD_RELOC_ARM_LITERAL
:
28500 sign
= (offsetT
) value
> 0;
28502 if ((offsetT
) value
< 0)
28505 if (validate_offset_imm (value
, 0) == FAIL
)
28507 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
28508 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28509 _("invalid literal constant: pool needs to be closer"));
28511 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28512 _("bad immediate value for offset (%ld)"),
28517 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28519 newval
&= 0xfffff000;
28522 newval
&= 0xff7ff000;
28523 newval
|= value
| (sign
? INDEX_UP
: 0);
28525 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28528 case BFD_RELOC_ARM_OFFSET_IMM8
:
28529 case BFD_RELOC_ARM_HWLITERAL
:
28530 sign
= (offsetT
) value
> 0;
28532 if ((offsetT
) value
< 0)
28535 if (validate_offset_imm (value
, 1) == FAIL
)
28537 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
28538 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28539 _("invalid literal constant: pool needs to be closer"));
28541 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28542 _("bad immediate value for 8-bit offset (%ld)"),
28547 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28549 newval
&= 0xfffff0f0;
28552 newval
&= 0xff7ff0f0;
28553 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
28555 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28558 case BFD_RELOC_ARM_T32_OFFSET_U8
:
28559 if (value
> 1020 || value
% 4 != 0)
28560 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28561 _("bad immediate value for offset (%ld)"), (long) value
);
28564 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
28566 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
28569 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
28570 /* This is a complicated relocation used for all varieties of Thumb32
28571 load/store instruction with immediate offset:
28573 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
28574 *4, optional writeback(W)
28575 (doubleword load/store)
28577 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
28578 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
28579 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
28580 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
28581 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
28583 Uppercase letters indicate bits that are already encoded at
28584 this point. Lowercase letters are our problem. For the
28585 second block of instructions, the secondary opcode nybble
28586 (bits 8..11) is present, and bit 23 is zero, even if this is
28587 a PC-relative operation. */
28588 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28590 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
28592 if ((newval
& 0xf0000000) == 0xe0000000)
28594 /* Doubleword load/store: 8-bit offset, scaled by 4. */
28595 if ((offsetT
) value
>= 0)
28596 newval
|= (1 << 23);
28599 if (value
% 4 != 0)
28601 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28602 _("offset not a multiple of 4"));
28608 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28609 _("offset out of range"));
28614 else if ((newval
& 0x000f0000) == 0x000f0000)
28616 /* PC-relative, 12-bit offset. */
28617 if ((offsetT
) value
>= 0)
28618 newval
|= (1 << 23);
28623 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28624 _("offset out of range"));
28629 else if ((newval
& 0x00000100) == 0x00000100)
28631 /* Writeback: 8-bit, +/- offset. */
28632 if ((offsetT
) value
>= 0)
28633 newval
|= (1 << 9);
28638 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28639 _("offset out of range"));
28644 else if ((newval
& 0x00000f00) == 0x00000e00)
28646 /* T-instruction: positive 8-bit offset. */
28649 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28650 _("offset out of range"));
28658 /* Positive 12-bit or negative 8-bit offset. */
28659 unsigned int limit
;
28660 if ((offsetT
) value
>= 0)
28662 newval
|= (1 << 23);
28672 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28673 _("offset out of range"));
28680 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
28681 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
28684 case BFD_RELOC_ARM_SHIFT_IMM
:
28685 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28688 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
28690 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28691 _("shift expression is too large"));
28696 /* Shifts of zero must be done as lsl. */
28698 else if (value
== 32)
28700 newval
&= 0xfffff07f;
28701 newval
|= (value
& 0x1f) << 7;
28702 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28705 case BFD_RELOC_ARM_T32_IMMEDIATE
:
28706 case BFD_RELOC_ARM_T32_ADD_IMM
:
28707 case BFD_RELOC_ARM_T32_IMM12
:
28708 case BFD_RELOC_ARM_T32_ADD_PC12
:
28709 /* We claim that this fixup has been processed here,
28710 even if in fact we generate an error because we do
28711 not have a reloc for it, so tc_gen_reloc will reject it. */
28715 && ! S_IS_DEFINED (fixP
->fx_addsy
))
28717 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28718 _("undefined symbol %s used as an immediate value"),
28719 S_GET_NAME (fixP
->fx_addsy
));
28723 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28725 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
28728 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
28729 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
28730 Thumb2 modified immediate encoding (T2). */
28731 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
28732 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
28734 newimm
= encode_thumb32_immediate (value
);
28735 if (newimm
== (unsigned int) FAIL
)
28736 newimm
= thumb32_negate_data_op (&newval
, value
);
28738 if (newimm
== (unsigned int) FAIL
)
28740 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
28742 /* Turn add/sum into addw/subw. */
28743 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
28744 newval
= (newval
& 0xfeffffff) | 0x02000000;
28745 /* No flat 12-bit imm encoding for addsw/subsw. */
28746 if ((newval
& 0x00100000) == 0)
28748 /* 12 bit immediate for addw/subw. */
28749 if ((offsetT
) value
< 0)
28752 newval
^= 0x00a00000;
28755 newimm
= (unsigned int) FAIL
;
28762 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
28763 UINT16 (T3 encoding), MOVW only accepts UINT16. When
28764 disassembling, MOV is preferred when there is no encoding
28766 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
28767 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
28768 but with the Rn field [19:16] set to 1111. */
28769 && (((newval
>> 16) & 0xf) == 0xf)
28770 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
28771 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
28772 && value
<= 0xffff)
28774 /* Toggle bit[25] to change encoding from T2 to T3. */
28776 /* Clear bits[19:16]. */
28777 newval
&= 0xfff0ffff;
28778 /* Encoding high 4bits imm. Code below will encode the
28779 remaining low 12bits. */
28780 newval
|= (value
& 0x0000f000) << 4;
28781 newimm
= value
& 0x00000fff;
28786 if (newimm
== (unsigned int)FAIL
)
28788 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28789 _("invalid constant (%lx) after fixup"),
28790 (unsigned long) value
);
28794 newval
|= (newimm
& 0x800) << 15;
28795 newval
|= (newimm
& 0x700) << 4;
28796 newval
|= (newimm
& 0x0ff);
28798 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
28799 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
28802 case BFD_RELOC_ARM_SMC
:
28804 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28805 _("invalid smc expression"));
28807 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28808 newval
|= (value
& 0xf);
28809 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28812 case BFD_RELOC_ARM_HVC
:
28813 if (value
> 0xffff)
28814 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28815 _("invalid hvc expression"));
28816 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28817 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
28818 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28821 case BFD_RELOC_ARM_SWI
:
28822 if (fixP
->tc_fix_data
!= 0)
28825 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28826 _("invalid swi expression"));
28827 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28829 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28833 if (value
> 0x00ffffff)
28834 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28835 _("invalid swi expression"));
28836 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28838 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28842 case BFD_RELOC_ARM_MULTI
:
28843 if (value
> 0xffff)
28844 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28845 _("invalid expression in load/store multiple"));
28846 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
28847 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28851 case BFD_RELOC_ARM_PCREL_CALL
:
28853 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28855 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28856 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28857 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28858 /* Flip the bl to blx. This is a simple flip
28859 bit here because we generate PCREL_CALL for
28860 unconditional bls. */
28862 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28863 newval
= newval
| 0x10000000;
28864 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28870 goto arm_branch_common
;
28872 case BFD_RELOC_ARM_PCREL_JUMP
:
28873 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28875 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28876 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28877 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28879 /* This would map to a bl<cond>, b<cond>,
28880 b<always> to a Thumb function. We
28881 need to force a relocation for this particular
28883 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28886 /* Fall through. */
28888 case BFD_RELOC_ARM_PLT32
:
28890 case BFD_RELOC_ARM_PCREL_BRANCH
:
28892 goto arm_branch_common
;
28894 case BFD_RELOC_ARM_PCREL_BLX
:
28897 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28899 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28900 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28901 && ARM_IS_FUNC (fixP
->fx_addsy
))
28903 /* Flip the blx to a bl and warn. */
28904 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
28905 newval
= 0xeb000000;
28906 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
28907 _("blx to '%s' an ARM ISA state function changed to bl"),
28909 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28915 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
28916 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
28920 /* We are going to store value (shifted right by two) in the
28921 instruction, in a 24 bit, signed field. Bits 26 through 32 either
28922 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
28925 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28926 _("misaligned branch destination"));
28927 if ((value
& 0xfe000000) != 0
28928 && (value
& 0xfe000000) != 0xfe000000)
28929 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28931 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28933 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28934 newval
|= (value
>> 2) & 0x00ffffff;
28935 /* Set the H bit on BLX instructions. */
28939 newval
|= 0x01000000;
28941 newval
&= ~0x01000000;
28943 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28947 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
28948 /* CBZ can only branch forward. */
28950 /* Attempts to use CBZ to branch to the next instruction
28951 (which, strictly speaking, are prohibited) will be turned into
28954 FIXME: It may be better to remove the instruction completely and
28955 perform relaxation. */
28956 if ((offsetT
) value
== -2)
28958 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28959 newval
= 0xbf00; /* NOP encoding T1 */
28960 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28965 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28967 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28969 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28970 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
28971 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28976 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
28977 if (out_of_range_p (value
, 8))
28978 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28980 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28982 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28983 newval
|= (value
& 0x1ff) >> 1;
28984 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28988 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
28989 if (out_of_range_p (value
, 11))
28990 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28992 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28994 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28995 newval
|= (value
& 0xfff) >> 1;
28996 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29000 /* This relocation is misnamed, it should be BRANCH21. */
29001 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29003 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29004 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29005 && ARM_IS_FUNC (fixP
->fx_addsy
)
29006 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
29008 /* Force a relocation for a branch 20 bits wide. */
29011 if (out_of_range_p (value
, 20))
29012 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29013 _("conditional branch out of range"));
29015 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29018 addressT S
, J1
, J2
, lo
, hi
;
29020 S
= (value
& 0x00100000) >> 20;
29021 J2
= (value
& 0x00080000) >> 19;
29022 J1
= (value
& 0x00040000) >> 18;
29023 hi
= (value
& 0x0003f000) >> 12;
29024 lo
= (value
& 0x00000ffe) >> 1;
29026 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29027 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29028 newval
|= (S
<< 10) | hi
;
29029 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
29030 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29031 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29035 case BFD_RELOC_THUMB_PCREL_BLX
:
29036 /* If there is a blx from a thumb state function to
29037 another thumb function flip this to a bl and warn
29041 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29042 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29043 && THUMB_IS_FUNC (fixP
->fx_addsy
))
29045 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
29046 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
29047 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
29049 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29050 newval
= newval
| 0x1000;
29051 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
29052 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29057 goto thumb_bl_common
;
29059 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29060 /* A bl from Thumb state ISA to an internal ARM state function
29061 is converted to a blx. */
29063 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29064 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29065 && ARM_IS_FUNC (fixP
->fx_addsy
)
29066 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
29068 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29069 newval
= newval
& ~0x1000;
29070 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
29071 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
29077 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
29078 /* For a BLX instruction, make sure that the relocation is rounded up
29079 to a word boundary. This follows the semantics of the instruction
29080 which specifies that bit 1 of the target address will come from bit
29081 1 of the base address. */
29082 value
= (value
+ 3) & ~ 3;
29085 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
29086 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
29087 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29090 if (out_of_range_p (value
, 22))
29092 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
29093 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
29094 else if (out_of_range_p (value
, 24))
29095 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29096 _("Thumb2 branch out of range"));
29099 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29100 encode_thumb2_b_bl_offset (buf
, value
);
29104 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29105 if (out_of_range_p (value
, 24))
29106 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
29108 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29109 encode_thumb2_b_bl_offset (buf
, value
);
29114 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29119 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29120 md_number_to_chars (buf
, value
, 2);
29124 case BFD_RELOC_ARM_TLS_CALL
:
29125 case BFD_RELOC_ARM_THM_TLS_CALL
:
29126 case BFD_RELOC_ARM_TLS_DESCSEQ
:
29127 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
29128 case BFD_RELOC_ARM_TLS_GOTDESC
:
29129 case BFD_RELOC_ARM_TLS_GD32
:
29130 case BFD_RELOC_ARM_TLS_LE32
:
29131 case BFD_RELOC_ARM_TLS_IE32
:
29132 case BFD_RELOC_ARM_TLS_LDM32
:
29133 case BFD_RELOC_ARM_TLS_LDO32
:
29134 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
29137 /* Same handling as above, but with the arm_fdpic guard. */
29138 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
29139 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
29140 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
29143 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
29147 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29148 _("Relocation supported only in FDPIC mode"));
29152 case BFD_RELOC_ARM_GOT32
:
29153 case BFD_RELOC_ARM_GOTOFF
:
29156 case BFD_RELOC_ARM_GOT_PREL
:
29157 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29158 md_number_to_chars (buf
, value
, 4);
29161 case BFD_RELOC_ARM_TARGET2
:
29162 /* TARGET2 is not partial-inplace, so we need to write the
29163 addend here for REL targets, because it won't be written out
29164 during reloc processing later. */
29165 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29166 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
29169 /* Relocations for FDPIC. */
29170 case BFD_RELOC_ARM_GOTFUNCDESC
:
29171 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
29172 case BFD_RELOC_ARM_FUNCDESC
:
29175 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29176 md_number_to_chars (buf
, 0, 4);
29180 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29181 _("Relocation supported only in FDPIC mode"));
29186 case BFD_RELOC_RVA
:
29188 case BFD_RELOC_ARM_TARGET1
:
29189 case BFD_RELOC_ARM_ROSEGREL32
:
29190 case BFD_RELOC_ARM_SBREL32
:
29191 case BFD_RELOC_32_PCREL
:
29193 case BFD_RELOC_32_SECREL
:
29195 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29197 /* For WinCE we only do this for pcrel fixups. */
29198 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
29200 md_number_to_chars (buf
, value
, 4);
29204 case BFD_RELOC_ARM_PREL31
:
29205 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29207 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
29208 if ((value
^ (value
>> 1)) & 0x40000000)
29210 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29211 _("rel31 relocation overflow"));
29213 newval
|= value
& 0x7fffffff;
29214 md_number_to_chars (buf
, newval
, 4);
29219 case BFD_RELOC_ARM_CP_OFF_IMM
:
29220 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
29221 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
29222 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
29223 newval
= md_chars_to_number (buf
, INSN_SIZE
);
29225 newval
= get_thumb32_insn (buf
);
29226 if ((newval
& 0x0f200f00) == 0x0d000900)
29228 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
29229 has permitted values that are multiples of 2, in the range -510
29231 if (value
+ 510 > 510 + 510 || (value
& 1))
29232 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29233 _("co-processor offset out of range"));
29235 else if ((newval
& 0xfe001f80) == 0xec000f80)
29237 if (value
+ 511 > 512 + 511 || (value
& 3))
29238 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29239 _("co-processor offset out of range"));
29241 else if (value
+ 1023 > 1023 + 1023 || (value
& 3))
29242 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29243 _("co-processor offset out of range"));
29245 sign
= (offsetT
) value
> 0;
29246 if ((offsetT
) value
< 0)
29248 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29249 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
29250 newval
= md_chars_to_number (buf
, INSN_SIZE
);
29252 newval
= get_thumb32_insn (buf
);
29255 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
29256 newval
&= 0xffffff80;
29258 newval
&= 0xffffff00;
29262 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
29263 newval
&= 0xff7fff80;
29265 newval
&= 0xff7fff00;
29266 if ((newval
& 0x0f200f00) == 0x0d000900)
29268 /* This is a fp16 vstr/vldr.
29270 It requires the immediate offset in the instruction is shifted
29271 left by 1 to be a half-word offset.
29273 Here, left shift by 1 first, and later right shift by 2
29274 should get the right offset. */
29277 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
29279 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29280 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
29281 md_number_to_chars (buf
, newval
, INSN_SIZE
);
29283 put_thumb32_insn (buf
, newval
);
29286 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
29287 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
29288 if (value
+ 255 > 255 + 255)
29289 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29290 _("co-processor offset out of range"));
29292 goto cp_off_common
;
29294 case BFD_RELOC_ARM_THUMB_OFFSET
:
29295 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29296 /* Exactly what ranges, and where the offset is inserted depends
29297 on the type of instruction, we can establish this from the
29299 switch (newval
>> 12)
29301 case 4: /* PC load. */
29302 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
29303 forced to zero for these loads; md_pcrel_from has already
29304 compensated for this. */
29306 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29307 _("invalid offset, target not word aligned (0x%08lX)"),
29308 (((unsigned long) fixP
->fx_frag
->fr_address
29309 + (unsigned long) fixP
->fx_where
) & ~3)
29310 + (unsigned long) value
);
29311 else if (get_recorded_alignment (seg
) < 2)
29312 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
29313 _("section does not have enough alignment to ensure safe PC-relative loads"));
29315 if (value
& ~0x3fc)
29316 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29317 _("invalid offset, value too big (0x%08lX)"),
29320 newval
|= value
>> 2;
29323 case 9: /* SP load/store. */
29324 if (value
& ~0x3fc)
29325 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29326 _("invalid offset, value too big (0x%08lX)"),
29328 newval
|= value
>> 2;
29331 case 6: /* Word load/store. */
29333 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29334 _("invalid offset, value too big (0x%08lX)"),
29336 newval
|= value
<< 4; /* 6 - 2. */
29339 case 7: /* Byte load/store. */
29341 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29342 _("invalid offset, value too big (0x%08lX)"),
29344 newval
|= value
<< 6;
29347 case 8: /* Halfword load/store. */
29349 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29350 _("invalid offset, value too big (0x%08lX)"),
29352 newval
|= value
<< 5; /* 6 - 1. */
29356 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29357 "Unable to process relocation for thumb opcode: %lx",
29358 (unsigned long) newval
);
29361 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29364 case BFD_RELOC_ARM_THUMB_ADD
:
29365 /* This is a complicated relocation, since we use it for all of
29366 the following immediate relocations:
29370 9bit ADD/SUB SP word-aligned
29371 10bit ADD PC/SP word-aligned
29373 The type of instruction being processed is encoded in the
29380 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29382 int rd
= (newval
>> 4) & 0xf;
29383 int rs
= newval
& 0xf;
29384 int subtract
= !!(newval
& 0x8000);
29386 /* Check for HI regs, only very restricted cases allowed:
29387 Adjusting SP, and using PC or SP to get an address. */
29388 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
29389 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
29390 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29391 _("invalid Hi register with immediate"));
29393 /* If value is negative, choose the opposite instruction. */
29394 if ((offsetT
) value
< 0)
29397 subtract
= !subtract
;
29398 if ((offsetT
) value
< 0)
29399 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29400 _("immediate value out of range"));
29405 if (value
& ~0x1fc)
29406 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29407 _("invalid immediate for stack address calculation"));
29408 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
29409 newval
|= value
>> 2;
29411 else if (rs
== REG_PC
|| rs
== REG_SP
)
29413 /* PR gas/18541. If the addition is for a defined symbol
29414 within range of an ADR instruction then accept it. */
29417 && fixP
->fx_addsy
!= NULL
)
29421 if (! S_IS_DEFINED (fixP
->fx_addsy
)
29422 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
29423 || S_IS_WEAK (fixP
->fx_addsy
))
29425 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29426 _("address calculation needs a strongly defined nearby symbol"));
29430 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
29432 /* Round up to the next 4-byte boundary. */
29437 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
29441 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29442 _("symbol too far away"));
29452 if (subtract
|| value
& ~0x3fc)
29453 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29454 _("invalid immediate for address calculation (value = 0x%08lX)"),
29455 (unsigned long) (subtract
? - value
: value
));
29456 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
29458 newval
|= value
>> 2;
29463 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29464 _("immediate value out of range"));
29465 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
29466 newval
|= (rd
<< 8) | value
;
29471 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29472 _("immediate value out of range"));
29473 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
29474 newval
|= rd
| (rs
<< 3) | (value
<< 6);
29477 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29480 case BFD_RELOC_ARM_THUMB_IMM
:
29481 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29483 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29484 _("invalid immediate: %ld is out of range"),
29487 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29490 case BFD_RELOC_ARM_THUMB_SHIFT
:
29491 /* 5bit shift value (0..32). LSL cannot take 32. */
29492 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
29493 temp
= newval
& 0xf800;
29494 if (value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
29495 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29496 _("invalid shift value: %ld"), (long) value
);
29497 /* Shifts of zero must be encoded as LSL. */
29499 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
29500 /* Shifts of 32 are encoded as zero. */
29501 else if (value
== 32)
29503 newval
|= value
<< 6;
29504 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29507 case BFD_RELOC_VTABLE_INHERIT
:
29508 case BFD_RELOC_VTABLE_ENTRY
:
29512 case BFD_RELOC_ARM_MOVW
:
29513 case BFD_RELOC_ARM_MOVT
:
29514 case BFD_RELOC_ARM_THUMB_MOVW
:
29515 case BFD_RELOC_ARM_THUMB_MOVT
:
29516 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29518 /* REL format relocations are limited to a 16-bit addend. */
29519 if (!fixP
->fx_done
)
29521 if (value
+ 0x8000 > 0x7fff + 0x8000)
29522 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29523 _("offset out of range"));
29525 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
29526 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
29531 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
29532 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
29534 newval
= get_thumb32_insn (buf
);
29535 newval
&= 0xfbf08f00;
29536 newval
|= (value
& 0xf000) << 4;
29537 newval
|= (value
& 0x0800) << 15;
29538 newval
|= (value
& 0x0700) << 4;
29539 newval
|= (value
& 0x00ff);
29540 put_thumb32_insn (buf
, newval
);
29544 newval
= md_chars_to_number (buf
, 4);
29545 newval
&= 0xfff0f000;
29546 newval
|= value
& 0x0fff;
29547 newval
|= (value
& 0xf000) << 4;
29548 md_number_to_chars (buf
, newval
, 4);
29553 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
29554 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
29555 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
29556 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
29557 gas_assert (!fixP
->fx_done
);
29560 bfd_boolean is_mov
;
29561 bfd_vma encoded_addend
= value
;
29563 /* Check that addend can be encoded in instruction. */
29564 if (!seg
->use_rela_p
&& value
> 255)
29565 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29566 _("the offset 0x%08lX is not representable"),
29567 (unsigned long) encoded_addend
);
29569 /* Extract the instruction. */
29570 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
29571 is_mov
= (insn
& 0xf800) == 0x2000;
29576 if (!seg
->use_rela_p
)
29577 insn
|= encoded_addend
;
29583 /* Extract the instruction. */
29584 /* Encoding is the following
29589 /* The following conditions must be true :
29594 rd
= (insn
>> 4) & 0xf;
29596 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
29597 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29598 _("Unable to process relocation for thumb opcode: %lx"),
29599 (unsigned long) insn
);
29601 /* Encode as ADD immediate8 thumb 1 code. */
29602 insn
= 0x3000 | (rd
<< 8);
29604 /* Place the encoded addend into the first 8 bits of the
29606 if (!seg
->use_rela_p
)
29607 insn
|= encoded_addend
;
29610 /* Update the instruction. */
29611 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
29615 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
29616 case BFD_RELOC_ARM_ALU_PC_G0
:
29617 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
29618 case BFD_RELOC_ARM_ALU_PC_G1
:
29619 case BFD_RELOC_ARM_ALU_PC_G2
:
29620 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
29621 case BFD_RELOC_ARM_ALU_SB_G0
:
29622 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
29623 case BFD_RELOC_ARM_ALU_SB_G1
:
29624 case BFD_RELOC_ARM_ALU_SB_G2
:
29625 gas_assert (!fixP
->fx_done
);
29626 if (!seg
->use_rela_p
)
29629 bfd_vma encoded_addend
;
29630 bfd_vma addend_abs
= llabs ((offsetT
) value
);
29632 /* Check that the absolute value of the addend can be
29633 expressed as an 8-bit constant plus a rotation. */
29634 encoded_addend
= encode_arm_immediate (addend_abs
);
29635 if (encoded_addend
== (unsigned int) FAIL
)
29636 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29637 _("the offset 0x%08lX is not representable"),
29638 (unsigned long) addend_abs
);
29640 /* Extract the instruction. */
29641 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29643 /* If the addend is positive, use an ADD instruction.
29644 Otherwise use a SUB. Take care not to destroy the S bit. */
29645 insn
&= 0xff1fffff;
29646 if ((offsetT
) value
< 0)
29651 /* Place the encoded addend into the first 12 bits of the
29653 insn
&= 0xfffff000;
29654 insn
|= encoded_addend
;
29656 /* Update the instruction. */
29657 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29661 case BFD_RELOC_ARM_LDR_PC_G0
:
29662 case BFD_RELOC_ARM_LDR_PC_G1
:
29663 case BFD_RELOC_ARM_LDR_PC_G2
:
29664 case BFD_RELOC_ARM_LDR_SB_G0
:
29665 case BFD_RELOC_ARM_LDR_SB_G1
:
29666 case BFD_RELOC_ARM_LDR_SB_G2
:
29667 gas_assert (!fixP
->fx_done
);
29668 if (!seg
->use_rela_p
)
29671 bfd_vma addend_abs
= llabs ((offsetT
) value
);
29673 /* Check that the absolute value of the addend can be
29674 encoded in 12 bits. */
29675 if (addend_abs
>= 0x1000)
29676 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29677 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
29678 (unsigned long) addend_abs
);
29680 /* Extract the instruction. */
29681 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29683 /* If the addend is negative, clear bit 23 of the instruction.
29684 Otherwise set it. */
29685 if ((offsetT
) value
< 0)
29686 insn
&= ~(1 << 23);
29690 /* Place the absolute value of the addend into the first 12 bits
29691 of the instruction. */
29692 insn
&= 0xfffff000;
29693 insn
|= addend_abs
;
29695 /* Update the instruction. */
29696 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29700 case BFD_RELOC_ARM_LDRS_PC_G0
:
29701 case BFD_RELOC_ARM_LDRS_PC_G1
:
29702 case BFD_RELOC_ARM_LDRS_PC_G2
:
29703 case BFD_RELOC_ARM_LDRS_SB_G0
:
29704 case BFD_RELOC_ARM_LDRS_SB_G1
:
29705 case BFD_RELOC_ARM_LDRS_SB_G2
:
29706 gas_assert (!fixP
->fx_done
);
29707 if (!seg
->use_rela_p
)
29710 bfd_vma addend_abs
= llabs ((offsetT
) value
);
29712 /* Check that the absolute value of the addend can be
29713 encoded in 8 bits. */
29714 if (addend_abs
>= 0x100)
29715 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29716 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
29717 (unsigned long) addend_abs
);
29719 /* Extract the instruction. */
29720 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29722 /* If the addend is negative, clear bit 23 of the instruction.
29723 Otherwise set it. */
29724 if ((offsetT
) value
< 0)
29725 insn
&= ~(1 << 23);
29729 /* Place the first four bits of the absolute value of the addend
29730 into the first 4 bits of the instruction, and the remaining
29731 four into bits 8 .. 11. */
29732 insn
&= 0xfffff0f0;
29733 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
29735 /* Update the instruction. */
29736 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29740 case BFD_RELOC_ARM_LDC_PC_G0
:
29741 case BFD_RELOC_ARM_LDC_PC_G1
:
29742 case BFD_RELOC_ARM_LDC_PC_G2
:
29743 case BFD_RELOC_ARM_LDC_SB_G0
:
29744 case BFD_RELOC_ARM_LDC_SB_G1
:
29745 case BFD_RELOC_ARM_LDC_SB_G2
:
29746 gas_assert (!fixP
->fx_done
);
29747 if (!seg
->use_rela_p
)
29750 bfd_vma addend_abs
= llabs ((offsetT
) value
);
29752 /* Check that the absolute value of the addend is a multiple of
29753 four and, when divided by four, fits in 8 bits. */
29754 if (addend_abs
& 0x3)
29755 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29756 _("bad offset 0x%08lX (must be word-aligned)"),
29757 (unsigned long) addend_abs
);
29759 if ((addend_abs
>> 2) > 0xff)
29760 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29761 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
29762 (unsigned long) addend_abs
);
29764 /* Extract the instruction. */
29765 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29767 /* If the addend is negative, clear bit 23 of the instruction.
29768 Otherwise set it. */
29769 if ((offsetT
) value
< 0)
29770 insn
&= ~(1 << 23);
29774 /* Place the addend (divided by four) into the first eight
29775 bits of the instruction. */
29776 insn
&= 0xfffffff0;
29777 insn
|= addend_abs
>> 2;
29779 /* Update the instruction. */
29780 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29784 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
29786 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29787 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29788 && ARM_IS_FUNC (fixP
->fx_addsy
)
29789 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29791 /* Force a relocation for a branch 5 bits wide. */
29794 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
29795 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29798 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29800 addressT boff
= value
>> 1;
29802 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29803 newval
|= (boff
<< 7);
29804 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29808 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
29810 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29811 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29812 && ARM_IS_FUNC (fixP
->fx_addsy
)
29813 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29817 if ((value
& ~0x7f) && ((value
& ~0x3f) != (valueT
) ~0x3f))
29818 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29819 _("branch out of range"));
29821 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29823 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29825 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
29826 addressT diff
= value
- boff
;
29830 newval
|= 1 << 1; /* T bit. */
29832 else if (diff
!= 2)
29834 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29835 _("out of range label-relative fixup value"));
29837 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29841 case BFD_RELOC_ARM_THUMB_BF17
:
29843 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29844 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29845 && ARM_IS_FUNC (fixP
->fx_addsy
)
29846 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29848 /* Force a relocation for a branch 17 bits wide. */
29852 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
29853 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29856 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29859 addressT immA
, immB
, immC
;
29861 immA
= (value
& 0x0001f000) >> 12;
29862 immB
= (value
& 0x00000ffc) >> 2;
29863 immC
= (value
& 0x00000002) >> 1;
29865 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29866 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29868 newval2
|= (immC
<< 11) | (immB
<< 1);
29869 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29870 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29874 case BFD_RELOC_ARM_THUMB_BF19
:
29876 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29877 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29878 && ARM_IS_FUNC (fixP
->fx_addsy
)
29879 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29881 /* Force a relocation for a branch 19 bits wide. */
29885 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
29886 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29889 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29892 addressT immA
, immB
, immC
;
29894 immA
= (value
& 0x0007f000) >> 12;
29895 immB
= (value
& 0x00000ffc) >> 2;
29896 immC
= (value
& 0x00000002) >> 1;
29898 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29899 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29901 newval2
|= (immC
<< 11) | (immB
<< 1);
29902 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29903 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29907 case BFD_RELOC_ARM_THUMB_BF13
:
29909 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29910 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29911 && ARM_IS_FUNC (fixP
->fx_addsy
)
29912 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29914 /* Force a relocation for a branch 13 bits wide. */
29918 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
29919 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29922 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29925 addressT immA
, immB
, immC
;
29927 immA
= (value
& 0x00001000) >> 12;
29928 immB
= (value
& 0x00000ffc) >> 2;
29929 immC
= (value
& 0x00000002) >> 1;
29931 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29932 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29934 newval2
|= (immC
<< 11) | (immB
<< 1);
29935 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29936 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29940 case BFD_RELOC_ARM_THUMB_LOOP12
:
29942 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29943 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29944 && ARM_IS_FUNC (fixP
->fx_addsy
)
29945 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29947 /* Force a relocation for a branch 12 bits wide. */
29951 bfd_vma insn
= get_thumb32_insn (buf
);
29952 /* le lr, <label>, le <label> or letp lr, <label> */
29953 if (((insn
& 0xffffffff) == 0xf00fc001)
29954 || ((insn
& 0xffffffff) == 0xf02fc001)
29955 || ((insn
& 0xffffffff) == 0xf01fc001))
29958 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
29959 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29961 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29963 addressT imml
, immh
;
29965 immh
= (value
& 0x00000ffc) >> 2;
29966 imml
= (value
& 0x00000002) >> 1;
29968 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29969 newval
|= (imml
<< 11) | (immh
<< 1);
29970 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
29974 case BFD_RELOC_ARM_V4BX
:
29975 /* This will need to go in the object file. */
29979 case BFD_RELOC_UNUSED
:
29981 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29982 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
29986 /* Translate internal representation of relocation info to BFD target
29990 tc_gen_reloc (asection
*section
, fixS
*fixp
)
29993 bfd_reloc_code_real_type code
;
29995 reloc
= XNEW (arelent
);
29997 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
29998 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
29999 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
30001 if (fixp
->fx_pcrel
)
30003 if (section
->use_rela_p
)
30004 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
30006 fixp
->fx_offset
= reloc
->address
;
30008 reloc
->addend
= fixp
->fx_offset
;
30010 switch (fixp
->fx_r_type
)
30013 if (fixp
->fx_pcrel
)
30015 code
= BFD_RELOC_8_PCREL
;
30018 /* Fall through. */
30021 if (fixp
->fx_pcrel
)
30023 code
= BFD_RELOC_16_PCREL
;
30026 /* Fall through. */
30029 if (fixp
->fx_pcrel
)
30031 code
= BFD_RELOC_32_PCREL
;
30034 /* Fall through. */
30036 case BFD_RELOC_ARM_MOVW
:
30037 if (fixp
->fx_pcrel
)
30039 code
= BFD_RELOC_ARM_MOVW_PCREL
;
30042 /* Fall through. */
30044 case BFD_RELOC_ARM_MOVT
:
30045 if (fixp
->fx_pcrel
)
30047 code
= BFD_RELOC_ARM_MOVT_PCREL
;
30050 /* Fall through. */
30052 case BFD_RELOC_ARM_THUMB_MOVW
:
30053 if (fixp
->fx_pcrel
)
30055 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
30058 /* Fall through. */
30060 case BFD_RELOC_ARM_THUMB_MOVT
:
30061 if (fixp
->fx_pcrel
)
30063 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
30066 /* Fall through. */
30068 case BFD_RELOC_NONE
:
30069 case BFD_RELOC_ARM_PCREL_BRANCH
:
30070 case BFD_RELOC_ARM_PCREL_BLX
:
30071 case BFD_RELOC_RVA
:
30072 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
30073 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
30074 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
30075 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
30076 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
30077 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
30078 case BFD_RELOC_VTABLE_ENTRY
:
30079 case BFD_RELOC_VTABLE_INHERIT
:
30081 case BFD_RELOC_32_SECREL
:
30083 code
= fixp
->fx_r_type
;
30086 case BFD_RELOC_THUMB_PCREL_BLX
:
30088 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
30089 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
30092 code
= BFD_RELOC_THUMB_PCREL_BLX
;
30095 case BFD_RELOC_ARM_LITERAL
:
30096 case BFD_RELOC_ARM_HWLITERAL
:
30097 /* If this is called then the a literal has
30098 been referenced across a section boundary. */
30099 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30100 _("literal referenced across section boundary"));
30104 case BFD_RELOC_ARM_TLS_CALL
:
30105 case BFD_RELOC_ARM_THM_TLS_CALL
:
30106 case BFD_RELOC_ARM_TLS_DESCSEQ
:
30107 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
30108 case BFD_RELOC_ARM_GOT32
:
30109 case BFD_RELOC_ARM_GOTOFF
:
30110 case BFD_RELOC_ARM_GOT_PREL
:
30111 case BFD_RELOC_ARM_PLT32
:
30112 case BFD_RELOC_ARM_TARGET1
:
30113 case BFD_RELOC_ARM_ROSEGREL32
:
30114 case BFD_RELOC_ARM_SBREL32
:
30115 case BFD_RELOC_ARM_PREL31
:
30116 case BFD_RELOC_ARM_TARGET2
:
30117 case BFD_RELOC_ARM_TLS_LDO32
:
30118 case BFD_RELOC_ARM_PCREL_CALL
:
30119 case BFD_RELOC_ARM_PCREL_JUMP
:
30120 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
30121 case BFD_RELOC_ARM_ALU_PC_G0
:
30122 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
30123 case BFD_RELOC_ARM_ALU_PC_G1
:
30124 case BFD_RELOC_ARM_ALU_PC_G2
:
30125 case BFD_RELOC_ARM_LDR_PC_G0
:
30126 case BFD_RELOC_ARM_LDR_PC_G1
:
30127 case BFD_RELOC_ARM_LDR_PC_G2
:
30128 case BFD_RELOC_ARM_LDRS_PC_G0
:
30129 case BFD_RELOC_ARM_LDRS_PC_G1
:
30130 case BFD_RELOC_ARM_LDRS_PC_G2
:
30131 case BFD_RELOC_ARM_LDC_PC_G0
:
30132 case BFD_RELOC_ARM_LDC_PC_G1
:
30133 case BFD_RELOC_ARM_LDC_PC_G2
:
30134 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
30135 case BFD_RELOC_ARM_ALU_SB_G0
:
30136 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
30137 case BFD_RELOC_ARM_ALU_SB_G1
:
30138 case BFD_RELOC_ARM_ALU_SB_G2
:
30139 case BFD_RELOC_ARM_LDR_SB_G0
:
30140 case BFD_RELOC_ARM_LDR_SB_G1
:
30141 case BFD_RELOC_ARM_LDR_SB_G2
:
30142 case BFD_RELOC_ARM_LDRS_SB_G0
:
30143 case BFD_RELOC_ARM_LDRS_SB_G1
:
30144 case BFD_RELOC_ARM_LDRS_SB_G2
:
30145 case BFD_RELOC_ARM_LDC_SB_G0
:
30146 case BFD_RELOC_ARM_LDC_SB_G1
:
30147 case BFD_RELOC_ARM_LDC_SB_G2
:
30148 case BFD_RELOC_ARM_V4BX
:
30149 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
30150 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
30151 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
30152 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
30153 case BFD_RELOC_ARM_GOTFUNCDESC
:
30154 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
30155 case BFD_RELOC_ARM_FUNCDESC
:
30156 case BFD_RELOC_ARM_THUMB_BF17
:
30157 case BFD_RELOC_ARM_THUMB_BF19
:
30158 case BFD_RELOC_ARM_THUMB_BF13
:
30159 code
= fixp
->fx_r_type
;
30162 case BFD_RELOC_ARM_TLS_GOTDESC
:
30163 case BFD_RELOC_ARM_TLS_GD32
:
30164 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
30165 case BFD_RELOC_ARM_TLS_LE32
:
30166 case BFD_RELOC_ARM_TLS_IE32
:
30167 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
30168 case BFD_RELOC_ARM_TLS_LDM32
:
30169 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
30170 /* BFD will include the symbol's address in the addend.
30171 But we don't want that, so subtract it out again here. */
30172 if (!S_IS_COMMON (fixp
->fx_addsy
))
30173 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
30174 code
= fixp
->fx_r_type
;
30178 case BFD_RELOC_ARM_IMMEDIATE
:
30179 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30180 _("internal relocation (type: IMMEDIATE) not fixed up"));
30183 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
30184 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30185 _("ADRL used for a symbol not defined in the same file"));
30188 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
30189 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
30190 case BFD_RELOC_ARM_THUMB_LOOP12
:
30191 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30192 _("%s used for a symbol not defined in the same file"),
30193 bfd_get_reloc_code_name (fixp
->fx_r_type
));
30196 case BFD_RELOC_ARM_OFFSET_IMM
:
30197 if (section
->use_rela_p
)
30199 code
= fixp
->fx_r_type
;
30203 if (fixp
->fx_addsy
!= NULL
30204 && !S_IS_DEFINED (fixp
->fx_addsy
)
30205 && S_IS_LOCAL (fixp
->fx_addsy
))
30207 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30208 _("undefined local label `%s'"),
30209 S_GET_NAME (fixp
->fx_addsy
));
30213 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30214 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
30221 switch (fixp
->fx_r_type
)
30223 case BFD_RELOC_NONE
: type
= "NONE"; break;
30224 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
30225 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
30226 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
30227 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
30228 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
30229 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
30230 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
30231 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
30232 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
30233 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
30234 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
30235 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
30236 default: type
= _("<unknown>"); break;
30238 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30239 _("cannot represent %s relocation in this object file format"),
30246 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
30248 && fixp
->fx_addsy
== GOT_symbol
)
30250 code
= BFD_RELOC_ARM_GOTPC
;
30251 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
30255 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
30257 if (reloc
->howto
== NULL
)
30259 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30260 _("cannot represent %s relocation in this object file format"),
30261 bfd_get_reloc_code_name (code
));
30265 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
30266 vtable entry to be used in the relocation's section offset. */
30267 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
30268 reloc
->address
= fixp
->fx_offset
;
30273 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
30276 cons_fix_new_arm (fragS
* frag
,
30280 bfd_reloc_code_real_type reloc
)
30285 FIXME: @@ Should look at CPU word size. */
30289 reloc
= BFD_RELOC_8
;
30292 reloc
= BFD_RELOC_16
;
30296 reloc
= BFD_RELOC_32
;
30299 reloc
= BFD_RELOC_64
;
30304 if (exp
->X_op
== O_secrel
)
30306 exp
->X_op
= O_symbol
;
30307 reloc
= BFD_RELOC_32_SECREL
;
30311 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
30314 #if defined (OBJ_COFF)
30316 arm_validate_fix (fixS
* fixP
)
30318 /* If the destination of the branch is a defined symbol which does not have
30319 the THUMB_FUNC attribute, then we must be calling a function which has
30320 the (interfacearm) attribute. We look for the Thumb entry point to that
30321 function and change the branch to refer to that function instead. */
30322 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
30323 && fixP
->fx_addsy
!= NULL
30324 && S_IS_DEFINED (fixP
->fx_addsy
)
30325 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
30327 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
30334 arm_force_relocation (struct fix
* fixp
)
30336 #if defined (OBJ_COFF) && defined (TE_PE)
30337 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
30341 /* In case we have a call or a branch to a function in ARM ISA mode from
30342 a thumb function or vice-versa force the relocation. These relocations
30343 are cleared off for some cores that might have blx and simple transformations
30347 switch (fixp
->fx_r_type
)
30349 case BFD_RELOC_ARM_PCREL_JUMP
:
30350 case BFD_RELOC_ARM_PCREL_CALL
:
30351 case BFD_RELOC_THUMB_PCREL_BLX
:
30352 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
30356 case BFD_RELOC_ARM_PCREL_BLX
:
30357 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
30358 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
30359 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
30360 if (ARM_IS_FUNC (fixp
->fx_addsy
))
30369 /* Resolve these relocations even if the symbol is extern or weak.
30370 Technically this is probably wrong due to symbol preemption.
30371 In practice these relocations do not have enough range to be useful
30372 at dynamic link time, and some code (e.g. in the Linux kernel)
30373 expects these references to be resolved. */
30374 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
30375 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
30376 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
30377 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
30378 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
30379 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
30380 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
30381 || fixp
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH12
30382 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
30383 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
30384 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
30385 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
30386 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
30387 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
30388 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
30391 /* Always leave these relocations for the linker. */
30392 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
30393 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
30394 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
30397 /* Always generate relocations against function symbols. */
30398 if (fixp
->fx_r_type
== BFD_RELOC_32
30400 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
30403 return generic_force_reloc (fixp
);
30406 #if defined (OBJ_ELF) || defined (OBJ_COFF)
30407 /* Relocations against function names must be left unadjusted,
30408 so that the linker can use this information to generate interworking
30409 stubs. The MIPS version of this function
30410 also prevents relocations that are mips-16 specific, but I do not
30411 know why it does this.
30414 There is one other problem that ought to be addressed here, but
30415 which currently is not: Taking the address of a label (rather
30416 than a function) and then later jumping to that address. Such
30417 addresses also ought to have their bottom bit set (assuming that
30418 they reside in Thumb code), but at the moment they will not. */
30421 arm_fix_adjustable (fixS
* fixP
)
30423 if (fixP
->fx_addsy
== NULL
)
30426 /* Preserve relocations against symbols with function type. */
30427 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
30430 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
30431 && fixP
->fx_subsy
== NULL
)
30434 /* We need the symbol name for the VTABLE entries. */
30435 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
30436 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
30439 /* Don't allow symbols to be discarded on GOT related relocs. */
30440 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
30441 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
30442 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
30443 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
30444 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
30445 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
30446 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
30447 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
30448 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
30449 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
30450 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
30451 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
30452 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
30453 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
30454 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
30455 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
30456 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
30459 /* Similarly for group relocations. */
30460 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
30461 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
30462 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
30465 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
30466 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
30467 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
30468 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
30469 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
30470 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
30471 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
30472 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
30473 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
30476 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
30477 offsets, so keep these symbols. */
30478 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
30479 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
30484 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
30488 elf32_arm_target_format (void)
30491 return (target_big_endian
30492 ? "elf32-bigarm-symbian"
30493 : "elf32-littlearm-symbian");
30494 #elif defined (TE_VXWORKS)
30495 return (target_big_endian
30496 ? "elf32-bigarm-vxworks"
30497 : "elf32-littlearm-vxworks");
30498 #elif defined (TE_NACL)
30499 return (target_big_endian
30500 ? "elf32-bigarm-nacl"
30501 : "elf32-littlearm-nacl");
30505 if (target_big_endian
)
30506 return "elf32-bigarm-fdpic";
30508 return "elf32-littlearm-fdpic";
30512 if (target_big_endian
)
30513 return "elf32-bigarm";
30515 return "elf32-littlearm";
30521 armelf_frob_symbol (symbolS
* symp
,
30524 elf_frob_symbol (symp
, puntp
);
30528 /* MD interface: Finalization. */
30533 literal_pool
* pool
;
30535 /* Ensure that all the predication blocks are properly closed. */
30536 check_pred_blocks_finished ();
30538 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
30540 /* Put it at the end of the relevant section. */
30541 subseg_set (pool
->section
, pool
->sub_section
);
30543 arm_elf_change_section ();
30550 /* Remove any excess mapping symbols generated for alignment frags in
30551 SEC. We may have created a mapping symbol before a zero byte
30552 alignment; remove it if there's a mapping symbol after the
30555 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
30556 void *dummy ATTRIBUTE_UNUSED
)
30558 segment_info_type
*seginfo
= seg_info (sec
);
30561 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
30564 for (fragp
= seginfo
->frchainP
->frch_root
;
30566 fragp
= fragp
->fr_next
)
30568 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
30569 fragS
*next
= fragp
->fr_next
;
30571 /* Variable-sized frags have been converted to fixed size by
30572 this point. But if this was variable-sized to start with,
30573 there will be a fixed-size frag after it. So don't handle
30575 if (sym
== NULL
|| next
== NULL
)
30578 if (S_GET_VALUE (sym
) < next
->fr_address
)
30579 /* Not at the end of this frag. */
30581 know (S_GET_VALUE (sym
) == next
->fr_address
);
30585 if (next
->tc_frag_data
.first_map
!= NULL
)
30587 /* Next frag starts with a mapping symbol. Discard this
30589 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
30593 if (next
->fr_next
== NULL
)
30595 /* This mapping symbol is at the end of the section. Discard
30597 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
30598 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
30602 /* As long as we have empty frags without any mapping symbols,
30604 /* If the next frag is non-empty and does not start with a
30605 mapping symbol, then this mapping symbol is required. */
30606 if (next
->fr_address
!= next
->fr_next
->fr_address
)
30609 next
= next
->fr_next
;
30611 while (next
!= NULL
);
30616 /* Adjust the symbol table. This marks Thumb symbols as distinct from
30620 arm_adjust_symtab (void)
30625 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
30627 if (ARM_IS_THUMB (sym
))
30629 if (THUMB_IS_FUNC (sym
))
30631 /* Mark the symbol as a Thumb function. */
30632 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
30633 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
30634 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
30636 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
30637 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
30639 as_bad (_("%s: unexpected function type: %d"),
30640 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
30642 else switch (S_GET_STORAGE_CLASS (sym
))
30645 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
30648 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
30651 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
30659 if (ARM_IS_INTERWORK (sym
))
30660 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
30667 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
30669 if (ARM_IS_THUMB (sym
))
30671 elf_symbol_type
* elf_sym
;
30673 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
30674 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
30676 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
30677 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
30679 /* If it's a .thumb_func, declare it as so,
30680 otherwise tag label as .code 16. */
30681 if (THUMB_IS_FUNC (sym
))
30682 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
30683 ST_BRANCH_TO_THUMB
);
30684 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
30685 elf_sym
->internal_elf_sym
.st_info
=
30686 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
30691 /* Remove any overlapping mapping symbols generated by alignment frags. */
30692 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
30693 /* Now do generic ELF adjustments. */
30694 elf_adjust_symtab ();
30698 /* MD interface: Initialization. */
30701 set_constant_flonums (void)
30705 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
30706 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
30710 /* Auto-select Thumb mode if it's the only available instruction set for the
30711 given architecture. */
30714 autoselect_thumb_from_cpu_variant (void)
30716 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
30717 opcode_select (16);
30726 arm_ops_hsh
= str_htab_create ();
30727 arm_cond_hsh
= str_htab_create ();
30728 arm_vcond_hsh
= str_htab_create ();
30729 arm_shift_hsh
= str_htab_create ();
30730 arm_psr_hsh
= str_htab_create ();
30731 arm_v7m_psr_hsh
= str_htab_create ();
30732 arm_reg_hsh
= str_htab_create ();
30733 arm_reloc_hsh
= str_htab_create ();
30734 arm_barrier_opt_hsh
= str_htab_create ();
30736 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
30737 if (str_hash_find (arm_ops_hsh
, insns
[i
].template_name
) == NULL
)
30738 str_hash_insert (arm_ops_hsh
, insns
[i
].template_name
, insns
+ i
, 0);
30739 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
30740 str_hash_insert (arm_cond_hsh
, conds
[i
].template_name
, conds
+ i
, 0);
30741 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
30742 str_hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, vconds
+ i
, 0);
30743 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
30744 str_hash_insert (arm_shift_hsh
, shift_names
[i
].name
, shift_names
+ i
, 0);
30745 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
30746 str_hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, psrs
+ i
, 0);
30747 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
30748 str_hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
30750 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
30751 str_hash_insert (arm_reg_hsh
, reg_names
[i
].name
, reg_names
+ i
, 0);
30753 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
30755 str_hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
30756 barrier_opt_names
+ i
, 0);
30758 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
30760 struct reloc_entry
* entry
= reloc_names
+ i
;
30762 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
30763 /* This makes encode_branch() use the EABI versions of this relocation. */
30764 entry
->reloc
= BFD_RELOC_UNUSED
;
30766 str_hash_insert (arm_reloc_hsh
, entry
->name
, entry
, 0);
30770 set_constant_flonums ();
30772 /* Set the cpu variant based on the command-line options. We prefer
30773 -mcpu= over -march= if both are set (as for GCC); and we prefer
30774 -mfpu= over any other way of setting the floating point unit.
30775 Use of legacy options with new options are faulted. */
30778 if (mcpu_cpu_opt
|| march_cpu_opt
)
30779 as_bad (_("use of old and new-style options to set CPU type"));
30781 selected_arch
= *legacy_cpu
;
30783 else if (mcpu_cpu_opt
)
30785 selected_arch
= *mcpu_cpu_opt
;
30786 selected_ext
= *mcpu_ext_opt
;
30788 else if (march_cpu_opt
)
30790 selected_arch
= *march_cpu_opt
;
30791 selected_ext
= *march_ext_opt
;
30793 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
30798 as_bad (_("use of old and new-style options to set FPU type"));
30800 selected_fpu
= *legacy_fpu
;
30803 selected_fpu
= *mfpu_opt
;
30806 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
30807 || defined (TE_NetBSD) || defined (TE_VXWORKS))
30808 /* Some environments specify a default FPU. If they don't, infer it
30809 from the processor. */
30811 selected_fpu
= *mcpu_fpu_opt
;
30812 else if (march_fpu_opt
)
30813 selected_fpu
= *march_fpu_opt
;
30815 selected_fpu
= fpu_default
;
30819 if (ARM_FEATURE_ZERO (selected_fpu
))
30821 if (!no_cpu_selected ())
30822 selected_fpu
= fpu_default
;
30824 selected_fpu
= fpu_arch_fpa
;
30828 if (ARM_FEATURE_ZERO (selected_arch
))
30830 selected_arch
= cpu_default
;
30831 selected_cpu
= selected_arch
;
30833 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30835 /* Autodection of feature mode: allow all features in cpu_variant but leave
30836 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
30837 after all instruction have been processed and we can decide what CPU
30838 should be selected. */
30839 if (ARM_FEATURE_ZERO (selected_arch
))
30840 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
30842 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30845 autoselect_thumb_from_cpu_variant ();
30847 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
30849 #if defined OBJ_COFF || defined OBJ_ELF
30851 unsigned int flags
= 0;
30853 #if defined OBJ_ELF
30854 flags
= meabi_flags
;
30856 switch (meabi_flags
)
30858 case EF_ARM_EABI_UNKNOWN
:
30860 /* Set the flags in the private structure. */
30861 if (uses_apcs_26
) flags
|= F_APCS26
;
30862 if (support_interwork
) flags
|= F_INTERWORK
;
30863 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
30864 if (pic_code
) flags
|= F_PIC
;
30865 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
30866 flags
|= F_SOFT_FLOAT
;
30868 switch (mfloat_abi_opt
)
30870 case ARM_FLOAT_ABI_SOFT
:
30871 case ARM_FLOAT_ABI_SOFTFP
:
30872 flags
|= F_SOFT_FLOAT
;
30875 case ARM_FLOAT_ABI_HARD
:
30876 if (flags
& F_SOFT_FLOAT
)
30877 as_bad (_("hard-float conflicts with specified fpu"));
30881 /* Using pure-endian doubles (even if soft-float). */
30882 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
30883 flags
|= F_VFP_FLOAT
;
30885 #if defined OBJ_ELF
30886 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
30887 flags
|= EF_ARM_MAVERICK_FLOAT
;
30890 case EF_ARM_EABI_VER4
:
30891 case EF_ARM_EABI_VER5
:
30892 /* No additional flags to set. */
30899 bfd_set_private_flags (stdoutput
, flags
);
30901 /* We have run out flags in the COFF header to encode the
30902 status of ATPCS support, so instead we create a dummy,
30903 empty, debug section called .arm.atpcs. */
30908 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
30912 bfd_set_section_flags (sec
, SEC_READONLY
| SEC_DEBUGGING
);
30913 bfd_set_section_size (sec
, 0);
30914 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
30920 /* Record the CPU type as well. */
30921 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
30922 mach
= bfd_mach_arm_iWMMXt2
;
30923 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
30924 mach
= bfd_mach_arm_iWMMXt
;
30925 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
30926 mach
= bfd_mach_arm_XScale
;
30927 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
30928 mach
= bfd_mach_arm_ep9312
;
30929 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
30930 mach
= bfd_mach_arm_5TE
;
30931 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
30933 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30934 mach
= bfd_mach_arm_5T
;
30936 mach
= bfd_mach_arm_5
;
30938 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
30940 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30941 mach
= bfd_mach_arm_4T
;
30943 mach
= bfd_mach_arm_4
;
30945 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
30946 mach
= bfd_mach_arm_3M
;
30947 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
30948 mach
= bfd_mach_arm_3
;
30949 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
30950 mach
= bfd_mach_arm_2a
;
30951 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
30952 mach
= bfd_mach_arm_2
;
30954 mach
= bfd_mach_arm_unknown
;
30956 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
30959 /* Command line processing. */
30962 Invocation line includes a switch not recognized by the base assembler.
30963 See if it's a processor-specific option.
30965 This routine is somewhat complicated by the need for backwards
30966 compatibility (since older releases of gcc can't be changed).
30967 The new options try to make the interface as compatible as
30970 New options (supported) are:
30972 -mcpu=<cpu name> Assemble for selected processor
30973 -march=<architecture name> Assemble for selected architecture
30974 -mfpu=<fpu architecture> Assemble for selected FPU.
30975 -EB/-mbig-endian Big-endian
30976 -EL/-mlittle-endian Little-endian
30977 -k Generate PIC code
30978 -mthumb Start in Thumb mode
30979 -mthumb-interwork Code supports ARM/Thumb interworking
30981 -m[no-]warn-deprecated Warn about deprecated features
30982 -m[no-]warn-syms Warn when symbols match instructions
30984 For now we will also provide support for:
30986 -mapcs-32 32-bit Program counter
30987 -mapcs-26 26-bit Program counter
30988 -macps-float Floats passed in FP registers
30989 -mapcs-reentrant Reentrant code
30991 (sometime these will probably be replaced with -mapcs=<list of options>
30992 and -matpcs=<list of options>)
30994 The remaining options are only supported for back-wards compatibility.
30995 Cpu variants, the arm part is optional:
30996 -m[arm]1 Currently not supported.
30997 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
30998 -m[arm]3 Arm 3 processor
30999 -m[arm]6[xx], Arm 6 processors
31000 -m[arm]7[xx][t][[d]m] Arm 7 processors
31001 -m[arm]8[10] Arm 8 processors
31002 -m[arm]9[20][tdmi] Arm 9 processors
31003 -mstrongarm[110[0]] StrongARM processors
31004 -mxscale XScale processors
31005 -m[arm]v[2345[t[e]]] Arm architectures
31006 -mall All (except the ARM1)
31008 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
31009 -mfpe-old (No float load/store multiples)
31010 -mvfpxd VFP Single precision
31012 -mno-fpu Disable all floating point instructions
31014 The following CPU names are recognized:
31015 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
31016 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
31017 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
31018 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
31019 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
31020 arm10t arm10e, arm1020t, arm1020e, arm10200e,
31021 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
31025 const char * md_shortopts
= "m:k";
31027 #ifdef ARM_BI_ENDIAN
31028 #define OPTION_EB (OPTION_MD_BASE + 0)
31029 #define OPTION_EL (OPTION_MD_BASE + 1)
31031 #if TARGET_BYTES_BIG_ENDIAN
31032 #define OPTION_EB (OPTION_MD_BASE + 0)
31034 #define OPTION_EL (OPTION_MD_BASE + 1)
31037 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
31038 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
31040 struct option md_longopts
[] =
31043 {"EB", no_argument
, NULL
, OPTION_EB
},
31046 {"EL", no_argument
, NULL
, OPTION_EL
},
31048 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
31050 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
31052 {NULL
, no_argument
, NULL
, 0}
31055 size_t md_longopts_size
= sizeof (md_longopts
);
31057 struct arm_option_table
31059 const char * option
; /* Option name to match. */
31060 const char * help
; /* Help information. */
31061 int * var
; /* Variable to change. */
31062 int value
; /* What to change it to. */
31063 const char * deprecated
; /* If non-null, print this message. */
31066 struct arm_option_table arm_opts
[] =
31068 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
31069 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
31070 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
31071 &support_interwork
, 1, NULL
},
31072 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
31073 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
31074 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
31076 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
31077 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
31078 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
31079 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
31082 /* These are recognized by the assembler, but have no affect on code. */
31083 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
31084 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
31086 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
31087 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
31088 &warn_on_deprecated
, 0, NULL
},
31090 {"mwarn-restrict-it", N_("warn about performance deprecated IT instructions"
31091 " in ARMv8-A and ARMv8-R"), &warn_on_restrict_it
, 1, NULL
},
31092 {"mno-warn-restrict-it", NULL
, &warn_on_restrict_it
, 0, NULL
},
31094 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
31095 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
31096 {NULL
, NULL
, NULL
, 0, NULL
}
31099 struct arm_legacy_option_table
31101 const char * option
; /* Option name to match. */
31102 const arm_feature_set
** var
; /* Variable to change. */
31103 const arm_feature_set value
; /* What to change it to. */
31104 const char * deprecated
; /* If non-null, print this message. */
31107 const struct arm_legacy_option_table arm_legacy_opts
[] =
31109 /* DON'T add any new processors to this list -- we want the whole list
31110 to go away... Add them to the processors table instead. */
31111 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
31112 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
31113 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
31114 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
31115 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
31116 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
31117 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
31118 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
31119 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
31120 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
31121 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
31122 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
31123 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
31124 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
31125 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
31126 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
31127 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
31128 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
31129 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
31130 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
31131 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
31132 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
31133 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
31134 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
31135 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
31136 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
31137 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
31138 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
31139 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
31140 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
31141 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
31142 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
31143 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
31144 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
31145 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
31146 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
31147 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
31148 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
31149 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
31150 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
31151 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
31152 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
31153 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
31154 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
31155 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
31156 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
31157 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31158 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31159 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31160 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31161 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
31162 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
31163 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
31164 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
31165 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
31166 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
31167 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
31168 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
31169 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
31170 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
31171 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
31172 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
31173 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
31174 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
31175 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
31176 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
31177 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
31178 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
31179 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
31180 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
31181 N_("use -mcpu=strongarm110")},
31182 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
31183 N_("use -mcpu=strongarm1100")},
31184 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
31185 N_("use -mcpu=strongarm1110")},
31186 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
31187 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
31188 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
31190 /* Architecture variants -- don't add any more to this list either. */
31191 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
31192 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
31193 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
31194 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
31195 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
31196 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
31197 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
31198 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
31199 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
31200 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
31201 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
31202 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
31203 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
31204 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
31205 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
31206 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
31207 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
31208 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
31210 /* Floating point variants -- don't add any more to this list either. */
31211 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
31212 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
31213 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
31214 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
31215 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
31217 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
31220 struct arm_cpu_option_table
31224 const arm_feature_set value
;
31225 const arm_feature_set ext
;
31226 /* For some CPUs we assume an FPU unless the user explicitly sets
31228 const arm_feature_set default_fpu
;
31229 /* The canonical name of the CPU, or NULL to use NAME converted to upper
31231 const char * canonical_name
;
31234 /* This list should, at a minimum, contain all the cpu names
31235 recognized by GCC. */
31236 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
31238 static const struct arm_cpu_option_table arm_cpus
[] =
31240 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
31243 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
31246 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
31249 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
31252 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
31255 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
31258 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
31261 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
31264 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
31267 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
31270 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
31273 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
31276 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
31279 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
31282 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
31285 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
31288 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
31291 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
31294 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
31297 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
31300 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
31303 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
31306 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
31309 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
31312 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
31315 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
31318 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
31321 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
31324 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
31327 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
31330 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
31333 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
31336 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
31339 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
31342 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
31345 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
31348 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
31351 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
31354 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
31357 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
31360 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
31363 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
31366 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
31369 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
31372 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
31375 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
31379 /* For V5 or later processors we default to using VFP; but the user
31380 should really set the FPU type explicitly. */
31381 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
31384 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
31387 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
31390 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
31393 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
31396 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
31399 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
31402 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
31405 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
31408 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
31411 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
31414 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
31417 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
31420 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
31423 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
31426 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
31429 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
31432 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
31435 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
31438 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
31441 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
31444 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
31447 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
31450 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
31453 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
31456 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
31459 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
31462 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
31465 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
31468 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
31471 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
31474 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
31477 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
31480 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
31483 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
31486 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
31489 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
31490 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31492 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
31494 FPU_ARCH_NEON_VFP_V4
),
31495 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
31496 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31497 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
31498 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
31499 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31500 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
31501 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
31503 FPU_ARCH_NEON_VFP_V4
),
31504 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
31506 FPU_ARCH_NEON_VFP_V4
),
31507 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
31509 FPU_ARCH_NEON_VFP_V4
),
31510 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
31511 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31512 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31513 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
31514 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31515 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31516 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
31517 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31518 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31519 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
31520 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31521 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31522 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
31523 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31524 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31525 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
31526 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31527 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31528 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
31529 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31530 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31531 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
31532 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31533 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31534 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
31535 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31536 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31537 ARM_CPU_OPT ("cortex-a76ae", "Cortex-A76AE", ARM_ARCH_V8_2A
,
31538 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31539 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31540 ARM_CPU_OPT ("cortex-a77", "Cortex-A77", ARM_ARCH_V8_2A
,
31541 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31542 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31543 ARM_CPU_OPT ("cortex-a78", "Cortex-A78", ARM_ARCH_V8_2A
,
31544 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_SB
),
31545 FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31546 ARM_CPU_OPT ("cortex-a78ae", "Cortex-A78AE", ARM_ARCH_V8_2A
,
31547 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_SB
),
31548 FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31549 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
31550 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31551 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31552 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
31555 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
31557 FPU_ARCH_VFP_V3D16
),
31558 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
31559 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31561 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
31562 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31563 FPU_ARCH_VFP_V3D16
),
31564 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
31565 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31566 FPU_ARCH_VFP_V3D16
),
31567 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
31568 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31569 FPU_ARCH_NEON_VFP_ARMV8
),
31570 ARM_CPU_OPT ("cortex-m35p", "Cortex-M35P", ARM_ARCH_V8M_MAIN
,
31571 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31573 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
31574 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31576 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
31579 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
31582 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
31585 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
31588 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
31591 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
31594 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
31597 ARM_CPU_OPT ("cortex-x1", "Cortex-X1", ARM_ARCH_V8_2A
,
31598 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_SB
),
31599 FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31600 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
31601 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31602 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31603 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
31604 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31605 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31606 ARM_CPU_OPT ("neoverse-n2", "Neoverse N2", ARM_ARCH_V8_5A
,
31607 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31610 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
),
31611 ARM_CPU_OPT ("neoverse-v1", "Neoverse V1", ARM_ARCH_V8_4A
,
31612 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31615 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
),
31616 /* ??? XSCALE is really an architecture. */
31617 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
31621 /* ??? iwmmxt is not a processor. */
31622 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
31625 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
31628 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
31633 ARM_CPU_OPT ("ep9312", "ARM920T",
31634 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
31635 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
31637 /* Marvell processors. */
31638 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
31639 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31640 FPU_ARCH_VFP_V3D16
),
31641 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
31642 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31643 FPU_ARCH_NEON_VFP_V4
),
31645 /* APM X-Gene family. */
31646 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
31648 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31649 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
31650 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31651 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31653 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
31657 struct arm_ext_table
31661 const arm_feature_set merge
;
31662 const arm_feature_set clear
;
31665 struct arm_arch_option_table
31669 const arm_feature_set value
;
31670 const arm_feature_set default_fpu
;
31671 const struct arm_ext_table
* ext_table
;
31674 /* Used to add support for +E and +noE extension. */
31675 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
31676 /* Used to add support for a +E extension. */
31677 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
31678 /* Used to add support for a +noE extension. */
31679 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
31681 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
31682 ~0 & ~FPU_ENDIAN_PURE)
31684 static const struct arm_ext_table armv5te_ext_table
[] =
31686 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
31687 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31690 static const struct arm_ext_table armv7_ext_table
[] =
31692 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31693 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31696 static const struct arm_ext_table armv7ve_ext_table
[] =
31698 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
31699 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
31700 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
31701 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31702 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
31703 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
31704 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
31706 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
31707 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
31709 /* Aliases for +simd. */
31710 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
31712 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31713 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31714 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
31716 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31719 static const struct arm_ext_table armv7a_ext_table
[] =
31721 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31722 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
31723 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
31724 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31725 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
31726 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
31727 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
31729 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
31730 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
31732 /* Aliases for +simd. */
31733 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31734 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31736 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
31737 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
31739 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
31740 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
31741 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31744 static const struct arm_ext_table armv7r_ext_table
[] =
31746 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
31747 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
31748 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31749 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
31750 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
31751 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31752 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31753 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
31754 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31757 static const struct arm_ext_table armv7em_ext_table
[] =
31759 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
31760 /* Alias for +fp, used to be known as fpv4-sp-d16. */
31761 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
31762 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
31763 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
31764 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
31765 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31768 static const struct arm_ext_table armv8a_ext_table
[] =
31770 ARM_ADD ("crc", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
)),
31771 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
31772 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31773 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31775 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31776 should use the +simd option to turn on FP. */
31777 ARM_REMOVE ("fp", ALL_FP
),
31778 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31779 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31780 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31784 static const struct arm_ext_table armv81a_ext_table
[] =
31786 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
31787 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
31788 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31790 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31791 should use the +simd option to turn on FP. */
31792 ARM_REMOVE ("fp", ALL_FP
),
31793 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31794 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31795 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31798 static const struct arm_ext_table armv82a_ext_table
[] =
31800 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
31801 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
31802 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
31803 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31804 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31805 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
31806 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31807 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31809 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31810 should use the +simd option to turn on FP. */
31811 ARM_REMOVE ("fp", ALL_FP
),
31812 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31813 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31814 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31817 static const struct arm_ext_table armv84a_ext_table
[] =
31819 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31820 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
31821 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31822 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31823 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
31824 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31826 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31827 should use the +simd option to turn on FP. */
31828 ARM_REMOVE ("fp", ALL_FP
),
31829 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31830 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31831 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31834 static const struct arm_ext_table armv85a_ext_table
[] =
31836 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31837 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
31838 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31839 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31840 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
31841 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31843 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31844 should use the +simd option to turn on FP. */
31845 ARM_REMOVE ("fp", ALL_FP
),
31846 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31849 static const struct arm_ext_table armv86a_ext_table
[] =
31851 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31852 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31855 #define CDE_EXTENSIONS \
31856 ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
31857 ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
31858 ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
31859 ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
31860 ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
31861 ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
31862 ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
31863 ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
31865 static const struct arm_ext_table armv8m_main_ext_table
[] =
31867 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
),
31868 ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
)),
31869 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
31870 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
31872 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31876 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
31878 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
),
31879 ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
)),
31881 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31882 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
31885 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31886 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
31887 ARM_EXT ("mve", ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP
, ARM_EXT2_MVE
, 0),
31888 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
)),
31890 ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP
,
31891 ARM_EXT2_FP16_INST
| ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
,
31892 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
31894 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31897 #undef CDE_EXTENSIONS
31899 static const struct arm_ext_table armv8r_ext_table
[] =
31901 ARM_ADD ("crc", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
)),
31902 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
31903 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31904 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31905 ARM_REMOVE ("fp", ALL_FP
),
31906 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
31907 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31910 /* This list should, at a minimum, contain all the architecture names
31911 recognized by GCC. */
31912 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
31913 #define ARM_ARCH_OPT2(N, V, DF, ext) \
31914 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
31916 static const struct arm_arch_option_table arm_archs
[] =
31918 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
31919 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
31920 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
31921 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
31922 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
31923 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
31924 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
31925 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
31926 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
31927 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
31928 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
31929 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
31930 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
31931 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
31932 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
31933 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
31934 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
31935 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31936 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31937 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
31938 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
31939 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
31940 kept to preserve existing behaviour. */
31941 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31942 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31943 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
31944 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
31945 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
31946 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
31947 kept to preserve existing behaviour. */
31948 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31949 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31950 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
31951 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
31952 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
31953 /* The official spelling of the ARMv7 profile variants is the dashed form.
31954 Accept the non-dashed form for compatibility with old toolchains. */
31955 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31956 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
31957 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31958 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31959 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31960 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31961 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31962 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
31963 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
31964 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
31966 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
31968 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
31969 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
31970 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
31971 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
31972 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
31973 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
31974 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
31975 ARM_ARCH_OPT2 ("armv8.6-a", ARM_ARCH_V8_6A
, FPU_ARCH_VFP
, armv86a
),
31976 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
31977 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
31978 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
31979 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
31981 #undef ARM_ARCH_OPT
31983 /* ISA extensions in the co-processor and main instruction set space. */
31985 struct arm_option_extension_value_table
31989 const arm_feature_set merge_value
;
31990 const arm_feature_set clear_value
;
31991 /* List of architectures for which an extension is available. ARM_ARCH_NONE
31992 indicates that an extension is available for all architectures while
31993 ARM_ANY marks an empty entry. */
31994 const arm_feature_set allowed_archs
[2];
31997 /* The following table must be in alphabetical order with a NULL last entry. */
31999 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
32000 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
32002 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
32003 use the context sensitive approach using arm_ext_table's. */
32004 static const struct arm_option_extension_value_table arm_extensions
[] =
32006 ARM_EXT_OPT ("crc", ARM_FEATURE_CORE_HIGH(ARM_EXT2_CRC
),
32007 ARM_FEATURE_CORE_HIGH(ARM_EXT2_CRC
),
32008 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
32009 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
32010 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
32011 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
32012 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
32013 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
32015 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
32016 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
32017 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
32018 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
32019 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
32020 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
32021 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
32023 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
32024 | ARM_EXT2_FP16_FML
),
32025 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
32026 | ARM_EXT2_FP16_FML
),
32028 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
32029 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
32030 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
32031 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
32032 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
32033 Thumb divide instruction. Due to this having the same name as the
32034 previous entry, this will be ignored when doing command-line parsing and
32035 only considered by build attribute selection code. */
32036 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
32037 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
32038 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
32039 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
32040 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
32041 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
32042 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
32043 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
32044 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
32045 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
32046 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
32047 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
32048 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
32049 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
32050 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
32051 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
32052 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
32053 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
32054 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32055 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
32056 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
32058 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
32059 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
32060 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32061 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
32062 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
32063 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32064 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
32065 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
32067 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
32068 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
32069 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
32070 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
32071 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
32072 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
32073 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
32074 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
32076 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
32077 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
32078 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
32079 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
32080 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
32084 /* ISA floating-point and Advanced SIMD extensions. */
32085 struct arm_option_fpu_value_table
32088 const arm_feature_set value
;
32091 /* This list should, at a minimum, contain all the fpu names
32092 recognized by GCC. */
32093 static const struct arm_option_fpu_value_table arm_fpus
[] =
32095 {"softfpa", FPU_NONE
},
32096 {"fpe", FPU_ARCH_FPE
},
32097 {"fpe2", FPU_ARCH_FPE
},
32098 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
32099 {"fpa", FPU_ARCH_FPA
},
32100 {"fpa10", FPU_ARCH_FPA
},
32101 {"fpa11", FPU_ARCH_FPA
},
32102 {"arm7500fe", FPU_ARCH_FPA
},
32103 {"softvfp", FPU_ARCH_VFP
},
32104 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
32105 {"vfp", FPU_ARCH_VFP_V2
},
32106 {"vfp9", FPU_ARCH_VFP_V2
},
32107 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
32108 {"vfp10", FPU_ARCH_VFP_V2
},
32109 {"vfp10-r0", FPU_ARCH_VFP_V1
},
32110 {"vfpxd", FPU_ARCH_VFP_V1xD
},
32111 {"vfpv2", FPU_ARCH_VFP_V2
},
32112 {"vfpv3", FPU_ARCH_VFP_V3
},
32113 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
32114 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
32115 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
32116 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
32117 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
32118 {"arm1020t", FPU_ARCH_VFP_V1
},
32119 {"arm1020e", FPU_ARCH_VFP_V2
},
32120 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
32121 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
32122 {"maverick", FPU_ARCH_MAVERICK
},
32123 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
32124 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
32125 {"neon-fp16", FPU_ARCH_NEON_FP16
},
32126 {"vfpv4", FPU_ARCH_VFP_V4
},
32127 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
32128 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
32129 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
32130 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
32131 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
32132 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
32133 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
32134 {"crypto-neon-fp-armv8",
32135 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
32136 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
32137 {"crypto-neon-fp-armv8.1",
32138 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
32139 {NULL
, ARM_ARCH_NONE
}
32142 struct arm_option_value_table
32148 static const struct arm_option_value_table arm_float_abis
[] =
32150 {"hard", ARM_FLOAT_ABI_HARD
},
32151 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
32152 {"soft", ARM_FLOAT_ABI_SOFT
},
32157 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
32158 static const struct arm_option_value_table arm_eabis
[] =
32160 {"gnu", EF_ARM_EABI_UNKNOWN
},
32161 {"4", EF_ARM_EABI_VER4
},
32162 {"5", EF_ARM_EABI_VER5
},
32167 struct arm_long_option_table
32169 const char * option
; /* Substring to match. */
32170 const char * help
; /* Help information. */
32171 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
32172 const char * deprecated
; /* If non-null, print this message. */
32176 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
32177 arm_feature_set
*ext_set
,
32178 const struct arm_ext_table
*ext_table
)
32180 /* We insist on extensions being specified in alphabetical order, and with
32181 extensions being added before being removed. We achieve this by having
32182 the global ARM_EXTENSIONS table in alphabetical order, and using the
32183 ADDING_VALUE variable to indicate whether we are adding an extension (1)
32184 or removing it (0) and only allowing it to change in the order
32186 const struct arm_option_extension_value_table
* opt
= NULL
;
32187 const arm_feature_set arm_any
= ARM_ANY
;
32188 int adding_value
= -1;
32190 while (str
!= NULL
&& *str
!= 0)
32197 as_bad (_("invalid architectural extension"));
32202 ext
= strchr (str
, '+');
32207 len
= strlen (str
);
32209 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
32211 if (adding_value
!= 0)
32214 opt
= arm_extensions
;
32222 if (adding_value
== -1)
32225 opt
= arm_extensions
;
32227 else if (adding_value
!= 1)
32229 as_bad (_("must specify extensions to add before specifying "
32230 "those to remove"));
32237 as_bad (_("missing architectural extension"));
32241 gas_assert (adding_value
!= -1);
32242 gas_assert (opt
!= NULL
);
32244 if (ext_table
!= NULL
)
32246 const struct arm_ext_table
* ext_opt
= ext_table
;
32247 bfd_boolean found
= FALSE
;
32248 for (; ext_opt
->name
!= NULL
; ext_opt
++)
32249 if (ext_opt
->name_len
== len
32250 && strncmp (ext_opt
->name
, str
, len
) == 0)
32254 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
32255 /* TODO: Option not supported. When we remove the
32256 legacy table this case should error out. */
32259 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
32263 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
32264 /* TODO: Option not supported. When we remove the
32265 legacy table this case should error out. */
32267 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
32279 /* Scan over the options table trying to find an exact match. */
32280 for (; opt
->name
!= NULL
; opt
++)
32281 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32283 int i
, nb_allowed_archs
=
32284 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
32285 /* Check we can apply the extension to this architecture. */
32286 for (i
= 0; i
< nb_allowed_archs
; i
++)
32289 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
32291 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
32294 if (i
== nb_allowed_archs
)
32296 as_bad (_("extension does not apply to the base architecture"));
32300 /* Add or remove the extension. */
32302 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
32304 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
32306 /* Allowing Thumb division instructions for ARMv7 in autodetection
32307 rely on this break so that duplicate extensions (extensions
32308 with the same name as a previous extension in the list) are not
32309 considered for command-line parsing. */
32313 if (opt
->name
== NULL
)
32315 /* Did we fail to find an extension because it wasn't specified in
32316 alphabetical order, or because it does not exist? */
32318 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32319 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32322 if (opt
->name
== NULL
)
32323 as_bad (_("unknown architectural extension `%s'"), str
);
32325 as_bad (_("architectural extensions must be specified in "
32326 "alphabetical order"));
32332 /* We should skip the extension we've just matched the next time
32344 arm_parse_fp16_opt (const char *str
)
32346 if (strcasecmp (str
, "ieee") == 0)
32347 fp16_format
= ARM_FP16_FORMAT_IEEE
;
32348 else if (strcasecmp (str
, "alternative") == 0)
32349 fp16_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
32352 as_bad (_("unrecognised float16 format \"%s\""), str
);
32360 arm_parse_cpu (const char *str
)
32362 const struct arm_cpu_option_table
*opt
;
32363 const char *ext
= strchr (str
, '+');
32369 len
= strlen (str
);
32373 as_bad (_("missing cpu name `%s'"), str
);
32377 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
32378 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32380 mcpu_cpu_opt
= &opt
->value
;
32381 if (mcpu_ext_opt
== NULL
)
32382 mcpu_ext_opt
= XNEW (arm_feature_set
);
32383 *mcpu_ext_opt
= opt
->ext
;
32384 mcpu_fpu_opt
= &opt
->default_fpu
;
32385 if (opt
->canonical_name
)
32387 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
32388 strcpy (selected_cpu_name
, opt
->canonical_name
);
32394 if (len
>= sizeof selected_cpu_name
)
32395 len
= (sizeof selected_cpu_name
) - 1;
32397 for (i
= 0; i
< len
; i
++)
32398 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
32399 selected_cpu_name
[i
] = 0;
32403 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
32408 as_bad (_("unknown cpu `%s'"), str
);
32413 arm_parse_arch (const char *str
)
32415 const struct arm_arch_option_table
*opt
;
32416 const char *ext
= strchr (str
, '+');
32422 len
= strlen (str
);
32426 as_bad (_("missing architecture name `%s'"), str
);
32430 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
32431 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32433 march_cpu_opt
= &opt
->value
;
32434 if (march_ext_opt
== NULL
)
32435 march_ext_opt
= XNEW (arm_feature_set
);
32436 *march_ext_opt
= arm_arch_none
;
32437 march_fpu_opt
= &opt
->default_fpu
;
32438 selected_ctx_ext_table
= opt
->ext_table
;
32439 strcpy (selected_cpu_name
, opt
->name
);
32442 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
32448 as_bad (_("unknown architecture `%s'\n"), str
);
32453 arm_parse_fpu (const char * str
)
32455 const struct arm_option_fpu_value_table
* opt
;
32457 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
32458 if (streq (opt
->name
, str
))
32460 mfpu_opt
= &opt
->value
;
32464 as_bad (_("unknown floating point format `%s'\n"), str
);
32469 arm_parse_float_abi (const char * str
)
32471 const struct arm_option_value_table
* opt
;
32473 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
32474 if (streq (opt
->name
, str
))
32476 mfloat_abi_opt
= opt
->value
;
32480 as_bad (_("unknown floating point abi `%s'\n"), str
);
32486 arm_parse_eabi (const char * str
)
32488 const struct arm_option_value_table
*opt
;
32490 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
32491 if (streq (opt
->name
, str
))
32493 meabi_flags
= opt
->value
;
32496 as_bad (_("unknown EABI `%s'\n"), str
);
32502 arm_parse_it_mode (const char * str
)
32504 bfd_boolean ret
= TRUE
;
32506 if (streq ("arm", str
))
32507 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
32508 else if (streq ("thumb", str
))
32509 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
32510 else if (streq ("always", str
))
32511 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
32512 else if (streq ("never", str
))
32513 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
32516 as_bad (_("unknown implicit IT mode `%s', should be "\
32517 "arm, thumb, always, or never."), str
);
32525 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
32527 codecomposer_syntax
= TRUE
;
32528 arm_comment_chars
[0] = ';';
32529 arm_line_separator_chars
[0] = 0;
32533 struct arm_long_option_table arm_long_opts
[] =
32535 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
32536 arm_parse_cpu
, NULL
},
32537 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
32538 arm_parse_arch
, NULL
},
32539 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
32540 arm_parse_fpu
, NULL
},
32541 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
32542 arm_parse_float_abi
, NULL
},
32544 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
32545 arm_parse_eabi
, NULL
},
32547 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
32548 arm_parse_it_mode
, NULL
},
32549 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
32550 arm_ccs_mode
, NULL
},
32552 N_("[ieee|alternative]\n\
32553 set the encoding for half precision floating point "
32554 "numbers to IEEE\n\
32555 or Arm alternative format."),
32556 arm_parse_fp16_opt
, NULL
},
32557 {NULL
, NULL
, 0, NULL
}
32561 md_parse_option (int c
, const char * arg
)
32563 struct arm_option_table
*opt
;
32564 const struct arm_legacy_option_table
*fopt
;
32565 struct arm_long_option_table
*lopt
;
32571 target_big_endian
= 1;
32577 target_big_endian
= 0;
32581 case OPTION_FIX_V4BX
:
32589 #endif /* OBJ_ELF */
32592 /* Listing option. Just ignore these, we don't support additional
32597 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
32599 if (c
== opt
->option
[0]
32600 && ((arg
== NULL
&& opt
->option
[1] == 0)
32601 || streq (arg
, opt
->option
+ 1)))
32603 /* If the option is deprecated, tell the user. */
32604 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
32605 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
32606 arg
? arg
: "", _(opt
->deprecated
));
32608 if (opt
->var
!= NULL
)
32609 *opt
->var
= opt
->value
;
32615 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
32617 if (c
== fopt
->option
[0]
32618 && ((arg
== NULL
&& fopt
->option
[1] == 0)
32619 || streq (arg
, fopt
->option
+ 1)))
32621 /* If the option is deprecated, tell the user. */
32622 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
32623 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
32624 arg
? arg
: "", _(fopt
->deprecated
));
32626 if (fopt
->var
!= NULL
)
32627 *fopt
->var
= &fopt
->value
;
32633 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
32635 /* These options are expected to have an argument. */
32636 if (c
== lopt
->option
[0]
32638 && strncmp (arg
, lopt
->option
+ 1,
32639 strlen (lopt
->option
+ 1)) == 0)
32641 /* If the option is deprecated, tell the user. */
32642 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
32643 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
32644 _(lopt
->deprecated
));
32646 /* Call the sup-option parser. */
32647 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
32658 md_show_usage (FILE * fp
)
32660 struct arm_option_table
*opt
;
32661 struct arm_long_option_table
*lopt
;
32663 fprintf (fp
, _(" ARM-specific assembler options:\n"));
32665 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
32666 if (opt
->help
!= NULL
)
32667 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
32669 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
32670 if (lopt
->help
!= NULL
)
32671 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
32675 -EB assemble code for a big-endian cpu\n"));
32680 -EL assemble code for a little-endian cpu\n"));
32684 --fix-v4bx Allow BX in ARMv4 code\n"));
32688 --fdpic generate an FDPIC object file\n"));
32689 #endif /* OBJ_ELF */
32697 arm_feature_set flags
;
32698 } cpu_arch_ver_table
;
32700 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
32701 chronologically for architectures, with an exception for ARMv6-M and
32702 ARMv6S-M due to legacy reasons. No new architecture should have a
32703 special case. This allows for build attribute selection results to be
32704 stable when new architectures are added. */
32705 static const cpu_arch_ver_table cpu_arch_ver
[] =
32707 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
32708 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
32709 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
32710 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
32711 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
32712 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
32713 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
32714 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
32715 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
32716 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
32717 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
32718 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
32719 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
32720 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
32721 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
32722 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
32723 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
32724 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
32725 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
32726 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
32727 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
32728 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
32729 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
32730 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
32732 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
32733 always selected build attributes to match those of ARMv6-M
32734 (resp. ARMv6S-M). However, due to these architectures being a strict
32735 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
32736 would be selected when fully respecting chronology of architectures.
32737 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
32738 move them before ARMv7 architectures. */
32739 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
32740 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
32742 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
32743 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
32744 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
32745 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
32746 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
32747 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
32748 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
32749 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
32750 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
32751 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
32752 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
32753 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
32754 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
32755 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
32756 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
32757 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
32758 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_6A
},
32759 {-1, ARM_ARCH_NONE
}
32762 /* Set an attribute if it has not already been set by the user. */
32765 aeabi_set_attribute_int (int tag
, int value
)
32768 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
32769 || !attributes_set_explicitly
[tag
])
32770 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
32774 aeabi_set_attribute_string (int tag
, const char *value
)
32777 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
32778 || !attributes_set_explicitly
[tag
])
32779 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
32782 /* Return whether features in the *NEEDED feature set are available via
32783 extensions for the architecture whose feature set is *ARCH_FSET. */
32786 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
32787 const arm_feature_set
*needed
)
32789 int i
, nb_allowed_archs
;
32790 arm_feature_set ext_fset
;
32791 const struct arm_option_extension_value_table
*opt
;
32793 ext_fset
= arm_arch_none
;
32794 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32796 /* Extension does not provide any feature we need. */
32797 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
32801 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
32802 for (i
= 0; i
< nb_allowed_archs
; i
++)
32805 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
32808 /* Extension is available, add it. */
32809 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
32810 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
32814 /* Can we enable all features in *needed? */
32815 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
32818 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
32819 a given architecture feature set *ARCH_EXT_FSET including extension feature
32820 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
32821 - if true, check for an exact match of the architecture modulo extensions;
32822 - otherwise, select build attribute value of the first superset
32823 architecture released so that results remains stable when new architectures
32825 For -march/-mcpu=all the build attribute value of the most featureful
32826 architecture is returned. Tag_CPU_arch_profile result is returned in
32830 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
32831 const arm_feature_set
*ext_fset
,
32832 char *profile
, int exact_match
)
32834 arm_feature_set arch_fset
;
32835 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
32837 /* Select most featureful architecture with all its extensions if building
32838 for -march=all as the feature sets used to set build attributes. */
32839 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
32841 /* Force revisiting of decision for each new architecture. */
32842 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
32844 return TAG_CPU_ARCH_V8
;
32847 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
32849 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
32851 arm_feature_set known_arch_fset
;
32853 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
32856 /* Base architecture match user-specified architecture and
32857 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
32858 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
32863 /* Base architecture match user-specified architecture only
32864 (eg. ARMv6-M in the same case as above). Record it in case we
32865 find a match with above condition. */
32866 else if (p_ver_ret
== NULL
32867 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
32873 /* Architecture has all features wanted. */
32874 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
32876 arm_feature_set added_fset
;
32878 /* Compute features added by this architecture over the one
32879 recorded in p_ver_ret. */
32880 if (p_ver_ret
!= NULL
)
32881 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
32883 /* First architecture that match incl. with extensions, or the
32884 only difference in features over the recorded match is
32885 features that were optional and are now mandatory. */
32886 if (p_ver_ret
== NULL
32887 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
32893 else if (p_ver_ret
== NULL
)
32895 arm_feature_set needed_ext_fset
;
32897 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
32899 /* Architecture has all features needed when using some
32900 extensions. Record it and continue searching in case there
32901 exist an architecture providing all needed features without
32902 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
32904 if (have_ext_for_needed_feat_p (&known_arch_fset
,
32911 if (p_ver_ret
== NULL
)
32915 /* Tag_CPU_arch_profile. */
32916 if (!ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8r
)
32917 && (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
32918 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
32919 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
32920 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
))))
32922 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
)
32923 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8r
))
32925 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
32929 return p_ver_ret
->val
;
32932 /* Set the public EABI object attributes. */
32935 aeabi_set_public_attributes (void)
32937 char profile
= '\0';
32940 int fp16_optional
= 0;
32941 int skip_exact_match
= 0;
32942 arm_feature_set flags
, flags_arch
, flags_ext
;
32944 /* Autodetection mode, choose the architecture based the instructions
32946 if (no_cpu_selected ())
32948 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
32950 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
32951 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
32953 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
32954 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
32956 /* Code run during relaxation relies on selected_cpu being set. */
32957 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
32958 flags_ext
= arm_arch_none
;
32959 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
32960 selected_ext
= flags_ext
;
32961 selected_cpu
= flags
;
32963 /* Otherwise, choose the architecture based on the capabilities of the
32967 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
32968 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
32969 flags_ext
= selected_ext
;
32970 flags
= selected_cpu
;
32972 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
32974 /* Allow the user to override the reported architecture. */
32975 if (!ARM_FEATURE_ZERO (selected_object_arch
))
32977 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
32978 flags_ext
= arm_arch_none
;
32981 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
32983 /* When this function is run again after relaxation has happened there is no
32984 way to determine whether an architecture or CPU was specified by the user:
32985 - selected_cpu is set above for relaxation to work;
32986 - march_cpu_opt is not set if only -mcpu or .cpu is used;
32987 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
32988 Therefore, if not in -march=all case we first try an exact match and fall
32989 back to autodetection. */
32990 if (!skip_exact_match
)
32991 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
32993 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
32995 as_bad (_("no architecture contains all the instructions used\n"));
32997 /* Tag_CPU_name. */
32998 if (selected_cpu_name
[0])
33002 q
= selected_cpu_name
;
33003 if (strncmp (q
, "armv", 4) == 0)
33008 for (i
= 0; q
[i
]; i
++)
33009 q
[i
] = TOUPPER (q
[i
]);
33011 aeabi_set_attribute_string (Tag_CPU_name
, q
);
33014 /* Tag_CPU_arch. */
33015 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
33017 /* Tag_CPU_arch_profile. */
33018 if (profile
!= '\0')
33019 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
33021 /* Tag_DSP_extension. */
33022 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
33023 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
33025 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
33026 /* Tag_ARM_ISA_use. */
33027 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
33028 || ARM_FEATURE_ZERO (flags_arch
))
33029 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
33031 /* Tag_THUMB_ISA_use. */
33032 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
33033 || ARM_FEATURE_ZERO (flags_arch
))
33037 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
33038 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
33040 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
33044 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
33047 /* Tag_VFP_arch. */
33048 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
33049 aeabi_set_attribute_int (Tag_VFP_arch
,
33050 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
33052 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
33053 aeabi_set_attribute_int (Tag_VFP_arch
,
33054 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
33056 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
33059 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
33061 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
33063 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
33066 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
33067 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
33068 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
33069 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
33070 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
33072 /* Tag_ABI_HardFP_use. */
33073 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
33074 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
33075 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
33077 /* Tag_WMMX_arch. */
33078 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
33079 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
33080 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
33081 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
33083 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
33084 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
33085 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
33086 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
33087 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
33088 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
33090 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
33092 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
33096 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
33101 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
33102 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
33103 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
33104 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
33106 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
33107 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
33108 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
33112 We set Tag_DIV_use to two when integer divide instructions have been used
33113 in ARM state, or when Thumb integer divide instructions have been used,
33114 but we have no architecture profile set, nor have we any ARM instructions.
33116 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
33117 by the base architecture.
33119 For new architectures we will have to check these tests. */
33120 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
33121 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
33122 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
33123 aeabi_set_attribute_int (Tag_DIV_use
, 0);
33124 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
33125 || (profile
== '\0'
33126 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
33127 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
33128 aeabi_set_attribute_int (Tag_DIV_use
, 2);
33130 /* Tag_MP_extension_use. */
33131 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
33132 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
33134 /* Tag Virtualization_use. */
33135 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
33137 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
33140 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
33142 if (fp16_format
!= ARM_FP16_FORMAT_DEFAULT
)
33143 aeabi_set_attribute_int (Tag_ABI_FP_16bit_format
, fp16_format
);
33146 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
33147 finished and free extension feature bits which will not be used anymore. */
33150 arm_md_post_relax (void)
33152 aeabi_set_public_attributes ();
33153 XDELETE (mcpu_ext_opt
);
33154 mcpu_ext_opt
= NULL
;
33155 XDELETE (march_ext_opt
);
33156 march_ext_opt
= NULL
;
33159 /* Add the default contents for the .ARM.attributes section. */
33164 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
33167 aeabi_set_public_attributes ();
33169 #endif /* OBJ_ELF */
33171 /* Parse a .cpu directive. */
33174 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
33176 const struct arm_cpu_option_table
*opt
;
33180 name
= input_line_pointer
;
33181 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33182 input_line_pointer
++;
33183 saved_char
= *input_line_pointer
;
33184 *input_line_pointer
= 0;
33186 /* Skip the first "all" entry. */
33187 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
33188 if (streq (opt
->name
, name
))
33190 selected_arch
= opt
->value
;
33191 selected_ext
= opt
->ext
;
33192 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33193 if (opt
->canonical_name
)
33194 strcpy (selected_cpu_name
, opt
->canonical_name
);
33198 for (i
= 0; opt
->name
[i
]; i
++)
33199 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
33201 selected_cpu_name
[i
] = 0;
33203 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33205 *input_line_pointer
= saved_char
;
33206 demand_empty_rest_of_line ();
33209 as_bad (_("unknown cpu `%s'"), name
);
33210 *input_line_pointer
= saved_char
;
33211 ignore_rest_of_line ();
33214 /* Parse a .arch directive. */
33217 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
33219 const struct arm_arch_option_table
*opt
;
33223 name
= input_line_pointer
;
33224 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33225 input_line_pointer
++;
33226 saved_char
= *input_line_pointer
;
33227 *input_line_pointer
= 0;
33229 /* Skip the first "all" entry. */
33230 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
33231 if (streq (opt
->name
, name
))
33233 selected_arch
= opt
->value
;
33234 selected_ctx_ext_table
= opt
->ext_table
;
33235 selected_ext
= arm_arch_none
;
33236 selected_cpu
= selected_arch
;
33237 strcpy (selected_cpu_name
, opt
->name
);
33238 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33239 *input_line_pointer
= saved_char
;
33240 demand_empty_rest_of_line ();
33244 as_bad (_("unknown architecture `%s'\n"), name
);
33245 *input_line_pointer
= saved_char
;
33246 ignore_rest_of_line ();
33249 /* Parse a .object_arch directive. */
33252 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
33254 const struct arm_arch_option_table
*opt
;
33258 name
= input_line_pointer
;
33259 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33260 input_line_pointer
++;
33261 saved_char
= *input_line_pointer
;
33262 *input_line_pointer
= 0;
33264 /* Skip the first "all" entry. */
33265 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
33266 if (streq (opt
->name
, name
))
33268 selected_object_arch
= opt
->value
;
33269 *input_line_pointer
= saved_char
;
33270 demand_empty_rest_of_line ();
33274 as_bad (_("unknown architecture `%s'\n"), name
);
33275 *input_line_pointer
= saved_char
;
33276 ignore_rest_of_line ();
33279 /* Parse a .arch_extension directive. */
33282 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
33284 const struct arm_option_extension_value_table
*opt
;
33287 int adding_value
= 1;
33289 name
= input_line_pointer
;
33290 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33291 input_line_pointer
++;
33292 saved_char
= *input_line_pointer
;
33293 *input_line_pointer
= 0;
33295 if (strlen (name
) >= 2
33296 && strncmp (name
, "no", 2) == 0)
33302 /* Check the context specific extension table */
33303 if (selected_ctx_ext_table
)
33305 const struct arm_ext_table
* ext_opt
;
33306 for (ext_opt
= selected_ctx_ext_table
; ext_opt
->name
!= NULL
; ext_opt
++)
33308 if (streq (ext_opt
->name
, name
))
33312 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
33313 /* TODO: Option not supported. When we remove the
33314 legacy table this case should error out. */
33316 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
33320 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, ext_opt
->clear
);
33322 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33323 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33324 *input_line_pointer
= saved_char
;
33325 demand_empty_rest_of_line ();
33331 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
33332 if (streq (opt
->name
, name
))
33334 int i
, nb_allowed_archs
=
33335 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
33336 for (i
= 0; i
< nb_allowed_archs
; i
++)
33339 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
33341 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
33345 if (i
== nb_allowed_archs
)
33347 as_bad (_("architectural extension `%s' is not allowed for the "
33348 "current base architecture"), name
);
33353 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
33356 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
33358 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33359 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33360 *input_line_pointer
= saved_char
;
33361 demand_empty_rest_of_line ();
33362 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
33363 on this return so that duplicate extensions (extensions with the
33364 same name as a previous extension in the list) are not considered
33365 for command-line parsing. */
33369 if (opt
->name
== NULL
)
33370 as_bad (_("unknown architecture extension `%s'\n"), name
);
33372 *input_line_pointer
= saved_char
;
33373 ignore_rest_of_line ();
33376 /* Parse a .fpu directive. */
33379 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
33381 const struct arm_option_fpu_value_table
*opt
;
33385 name
= input_line_pointer
;
33386 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33387 input_line_pointer
++;
33388 saved_char
= *input_line_pointer
;
33389 *input_line_pointer
= 0;
33391 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
33392 if (streq (opt
->name
, name
))
33394 selected_fpu
= opt
->value
;
33395 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, fpu_any
);
33396 #ifndef CPU_DEFAULT
33397 if (no_cpu_selected ())
33398 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
33401 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33402 *input_line_pointer
= saved_char
;
33403 demand_empty_rest_of_line ();
33407 as_bad (_("unknown floating point format `%s'\n"), name
);
33408 *input_line_pointer
= saved_char
;
33409 ignore_rest_of_line ();
33412 /* Copy symbol information. */
33415 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
33417 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
33421 /* Given a symbolic attribute NAME, return the proper integer value.
33422 Returns -1 if the attribute is not known. */
33425 arm_convert_symbolic_attribute (const char *name
)
33427 static const struct
33432 attribute_table
[] =
33434 /* When you modify this table you should
33435 also modify the list in doc/c-arm.texi. */
33436 #define T(tag) {#tag, tag}
33437 T (Tag_CPU_raw_name
),
33440 T (Tag_CPU_arch_profile
),
33441 T (Tag_ARM_ISA_use
),
33442 T (Tag_THUMB_ISA_use
),
33446 T (Tag_Advanced_SIMD_arch
),
33447 T (Tag_PCS_config
),
33448 T (Tag_ABI_PCS_R9_use
),
33449 T (Tag_ABI_PCS_RW_data
),
33450 T (Tag_ABI_PCS_RO_data
),
33451 T (Tag_ABI_PCS_GOT_use
),
33452 T (Tag_ABI_PCS_wchar_t
),
33453 T (Tag_ABI_FP_rounding
),
33454 T (Tag_ABI_FP_denormal
),
33455 T (Tag_ABI_FP_exceptions
),
33456 T (Tag_ABI_FP_user_exceptions
),
33457 T (Tag_ABI_FP_number_model
),
33458 T (Tag_ABI_align_needed
),
33459 T (Tag_ABI_align8_needed
),
33460 T (Tag_ABI_align_preserved
),
33461 T (Tag_ABI_align8_preserved
),
33462 T (Tag_ABI_enum_size
),
33463 T (Tag_ABI_HardFP_use
),
33464 T (Tag_ABI_VFP_args
),
33465 T (Tag_ABI_WMMX_args
),
33466 T (Tag_ABI_optimization_goals
),
33467 T (Tag_ABI_FP_optimization_goals
),
33468 T (Tag_compatibility
),
33469 T (Tag_CPU_unaligned_access
),
33470 T (Tag_FP_HP_extension
),
33471 T (Tag_VFP_HP_extension
),
33472 T (Tag_ABI_FP_16bit_format
),
33473 T (Tag_MPextension_use
),
33475 T (Tag_nodefaults
),
33476 T (Tag_also_compatible_with
),
33477 T (Tag_conformance
),
33479 T (Tag_Virtualization_use
),
33480 T (Tag_DSP_extension
),
33482 /* We deliberately do not include Tag_MPextension_use_legacy. */
33490 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
33491 if (streq (name
, attribute_table
[i
].name
))
33492 return attribute_table
[i
].tag
;
33497 /* Apply sym value for relocations only in the case that they are for
33498 local symbols in the same segment as the fixup and you have the
33499 respective architectural feature for blx and simple switches. */
33502 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
33505 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
33506 /* PR 17444: If the local symbol is in a different section then a reloc
33507 will always be generated for it, so applying the symbol value now
33508 will result in a double offset being stored in the relocation. */
33509 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
33510 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
33512 switch (fixP
->fx_r_type
)
33514 case BFD_RELOC_ARM_PCREL_BLX
:
33515 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
33516 if (ARM_IS_FUNC (fixP
->fx_addsy
))
33520 case BFD_RELOC_ARM_PCREL_CALL
:
33521 case BFD_RELOC_THUMB_PCREL_BLX
:
33522 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
33533 #endif /* OBJ_ELF */