1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
189 static const arm_feature_set arm_ext_v6_notm
=
190 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
191 static const arm_feature_set arm_ext_v6_dsp
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
193 static const arm_feature_set arm_ext_barrier
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
195 static const arm_feature_set arm_ext_msr
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
197 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
198 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
199 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
200 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
201 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
202 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
203 static const arm_feature_set arm_ext_m
=
204 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, ARM_EXT2_V8M
);
205 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
206 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
207 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
208 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
209 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
210 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
211 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
212 static const arm_feature_set arm_ext_v6t2_v8m
=
213 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
214 /* Instructions shared between ARMv8-A and ARMv8-M. */
215 static const arm_feature_set arm_ext_atomics
=
216 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
217 static const arm_feature_set arm_ext_v8_2
=
218 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
219 /* FP16 instructions. */
220 static const arm_feature_set arm_ext_fp16
=
221 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
223 static const arm_feature_set arm_arch_any
= ARM_ANY
;
224 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1, -1);
225 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
226 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
227 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
229 static const arm_feature_set arm_cext_iwmmxt2
=
230 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
231 static const arm_feature_set arm_cext_iwmmxt
=
232 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
233 static const arm_feature_set arm_cext_xscale
=
234 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
235 static const arm_feature_set arm_cext_maverick
=
236 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
237 static const arm_feature_set fpu_fpa_ext_v1
=
238 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
239 static const arm_feature_set fpu_fpa_ext_v2
=
240 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
241 static const arm_feature_set fpu_vfp_ext_v1xd
=
242 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
243 static const arm_feature_set fpu_vfp_ext_v1
=
244 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
245 static const arm_feature_set fpu_vfp_ext_v2
=
246 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
247 static const arm_feature_set fpu_vfp_ext_v3xd
=
248 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
249 static const arm_feature_set fpu_vfp_ext_v3
=
250 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
251 static const arm_feature_set fpu_vfp_ext_d32
=
252 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
253 static const arm_feature_set fpu_neon_ext_v1
=
254 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
255 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
256 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
257 static const arm_feature_set fpu_vfp_fp16
=
258 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
259 static const arm_feature_set fpu_neon_ext_fma
=
260 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
261 static const arm_feature_set fpu_vfp_ext_fma
=
262 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
263 static const arm_feature_set fpu_vfp_ext_armv8
=
264 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
265 static const arm_feature_set fpu_vfp_ext_armv8xd
=
266 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
267 static const arm_feature_set fpu_neon_ext_armv8
=
268 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
269 static const arm_feature_set fpu_crypto_ext_armv8
=
270 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
271 static const arm_feature_set crc_ext_armv8
=
272 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
273 static const arm_feature_set fpu_neon_ext_v8_1
=
274 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
276 static int mfloat_abi_opt
= -1;
277 /* Record user cpu selection for object attributes. */
278 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
279 /* Must be long enough to hold any of the names in arm_cpus. */
280 static char selected_cpu_name
[20];
282 extern FLONUM_TYPE generic_floating_point_number
;
284 /* Return if no cpu was selected on command-line. */
286 no_cpu_selected (void)
288 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
293 static int meabi_flags
= EABI_DEFAULT
;
295 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
298 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
303 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
308 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
309 symbolS
* GOT_symbol
;
312 /* 0: assemble for ARM,
313 1: assemble for Thumb,
314 2: assemble for Thumb even though target CPU does not support thumb
316 static int thumb_mode
= 0;
317 /* A value distinct from the possible values for thumb_mode that we
318 can use to record whether thumb_mode has been copied into the
319 tc_frag_data field of a frag. */
320 #define MODE_RECORDED (1 << 4)
322 /* Specifies the intrinsic IT insn behavior mode. */
323 enum implicit_it_mode
325 IMPLICIT_IT_MODE_NEVER
= 0x00,
326 IMPLICIT_IT_MODE_ARM
= 0x01,
327 IMPLICIT_IT_MODE_THUMB
= 0x02,
328 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
330 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
332 /* If unified_syntax is true, we are processing the new unified
333 ARM/Thumb syntax. Important differences from the old ARM mode:
335 - Immediate operands do not require a # prefix.
336 - Conditional affixes always appear at the end of the
337 instruction. (For backward compatibility, those instructions
338 that formerly had them in the middle, continue to accept them
340 - The IT instruction may appear, and if it does is validated
341 against subsequent conditional affixes. It does not generate
344 Important differences from the old Thumb mode:
346 - Immediate operands do not require a # prefix.
347 - Most of the V6T2 instructions are only available in unified mode.
348 - The .N and .W suffixes are recognized and honored (it is an error
349 if they cannot be honored).
350 - All instructions set the flags if and only if they have an 's' affix.
351 - Conditional affixes may be used. They are validated against
352 preceding IT instructions. Unlike ARM mode, you cannot use a
353 conditional affix except in the scope of an IT instruction. */
355 static bfd_boolean unified_syntax
= FALSE
;
357 /* An immediate operand can start with #, and ld*, st*, pld operands
358 can contain [ and ]. We need to tell APP not to elide whitespace
359 before a [, which can appear as the first operand for pld.
360 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
361 const char arm_symbol_chars
[] = "#[]{}";
376 enum neon_el_type type
;
380 #define NEON_MAX_TYPE_ELS 4
384 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
388 enum it_instruction_type
393 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
394 if inside, should be the last one. */
395 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
396 i.e. BKPT and NOP. */
397 IT_INSN
/* The IT insn has been parsed. */
400 /* The maximum number of operands we need. */
401 #define ARM_IT_MAX_OPERANDS 6
406 unsigned long instruction
;
410 /* "uncond_value" is set to the value in place of the conditional field in
411 unconditional versions of the instruction, or -1 if nothing is
414 struct neon_type vectype
;
415 /* This does not indicate an actual NEON instruction, only that
416 the mnemonic accepts neon-style type suffixes. */
418 /* Set to the opcode if the instruction needs relaxation.
419 Zero if the instruction is not relaxed. */
423 bfd_reloc_code_real_type type
;
428 enum it_instruction_type it_insn_type
;
434 struct neon_type_el vectype
;
435 unsigned present
: 1; /* Operand present. */
436 unsigned isreg
: 1; /* Operand was a register. */
437 unsigned immisreg
: 1; /* .imm field is a second register. */
438 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
439 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
440 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
441 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
442 instructions. This allows us to disambiguate ARM <-> vector insns. */
443 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
444 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
445 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
446 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
447 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
448 unsigned writeback
: 1; /* Operand has trailing ! */
449 unsigned preind
: 1; /* Preindexed address. */
450 unsigned postind
: 1; /* Postindexed address. */
451 unsigned negative
: 1; /* Index register was negated. */
452 unsigned shifted
: 1; /* Shift applied to operation. */
453 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
454 } operands
[ARM_IT_MAX_OPERANDS
];
457 static struct arm_it inst
;
459 #define NUM_FLOAT_VALS 8
461 const char * fp_const
[] =
463 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
466 /* Number of littlenums required to hold an extended precision number. */
467 #define MAX_LITTLENUMS 6
469 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
479 #define CP_T_X 0x00008000
480 #define CP_T_Y 0x00400000
482 #define CONDS_BIT 0x00100000
483 #define LOAD_BIT 0x00100000
485 #define DOUBLE_LOAD_FLAG 0x00000001
489 const char * template_name
;
493 #define COND_ALWAYS 0xE
497 const char * template_name
;
501 struct asm_barrier_opt
503 const char * template_name
;
505 const arm_feature_set arch
;
508 /* The bit that distinguishes CPSR and SPSR. */
509 #define SPSR_BIT (1 << 22)
511 /* The individual PSR flag bits. */
512 #define PSR_c (1 << 16)
513 #define PSR_x (1 << 17)
514 #define PSR_s (1 << 18)
515 #define PSR_f (1 << 19)
520 bfd_reloc_code_real_type reloc
;
525 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
526 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
531 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
534 /* Bits for DEFINED field in neon_typed_alias. */
535 #define NTA_HASTYPE 1
536 #define NTA_HASINDEX 2
538 struct neon_typed_alias
540 unsigned char defined
;
542 struct neon_type_el eltype
;
545 /* ARM register categories. This includes coprocessor numbers and various
546 architecture extensions' registers. */
573 /* Structure for a hash table entry for a register.
574 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
575 information which states whether a vector type or index is specified (for a
576 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
582 unsigned char builtin
;
583 struct neon_typed_alias
* neon
;
586 /* Diagnostics used when we don't get a register of the expected type. */
587 const char * const reg_expected_msgs
[] =
589 N_("ARM register expected"),
590 N_("bad or missing co-processor number"),
591 N_("co-processor register expected"),
592 N_("FPA register expected"),
593 N_("VFP single precision register expected"),
594 N_("VFP/Neon double precision register expected"),
595 N_("Neon quad precision register expected"),
596 N_("VFP single or double precision register expected"),
597 N_("Neon double or quad precision register expected"),
598 N_("VFP single, double or Neon quad precision register expected"),
599 N_("VFP system register expected"),
600 N_("Maverick MVF register expected"),
601 N_("Maverick MVD register expected"),
602 N_("Maverick MVFX register expected"),
603 N_("Maverick MVDX register expected"),
604 N_("Maverick MVAX register expected"),
605 N_("Maverick DSPSC register expected"),
606 N_("iWMMXt data register expected"),
607 N_("iWMMXt control register expected"),
608 N_("iWMMXt scalar register expected"),
609 N_("XScale accumulator register expected"),
612 /* Some well known registers that we refer to directly elsewhere. */
618 /* ARM instructions take 4bytes in the object file, Thumb instructions
624 /* Basic string to match. */
625 const char * template_name
;
627 /* Parameters to instruction. */
628 unsigned int operands
[8];
630 /* Conditional tag - see opcode_lookup. */
631 unsigned int tag
: 4;
633 /* Basic instruction code. */
634 unsigned int avalue
: 28;
636 /* Thumb-format instruction code. */
639 /* Which architecture variant provides this instruction. */
640 const arm_feature_set
* avariant
;
641 const arm_feature_set
* tvariant
;
643 /* Function to call to encode instruction in ARM format. */
644 void (* aencode
) (void);
646 /* Function to call to encode instruction in Thumb format. */
647 void (* tencode
) (void);
650 /* Defines for various bits that we will want to toggle. */
651 #define INST_IMMEDIATE 0x02000000
652 #define OFFSET_REG 0x02000000
653 #define HWOFFSET_IMM 0x00400000
654 #define SHIFT_BY_REG 0x00000010
655 #define PRE_INDEX 0x01000000
656 #define INDEX_UP 0x00800000
657 #define WRITE_BACK 0x00200000
658 #define LDM_TYPE_2_OR_3 0x00400000
659 #define CPSI_MMOD 0x00020000
661 #define LITERAL_MASK 0xf000f000
662 #define OPCODE_MASK 0xfe1fffff
663 #define V4_STR_BIT 0x00000020
664 #define VLDR_VMOV_SAME 0x0040f000
666 #define T2_SUBS_PC_LR 0xf3de8f00
668 #define DATA_OP_SHIFT 21
670 #define T2_OPCODE_MASK 0xfe1fffff
671 #define T2_DATA_OP_SHIFT 21
673 #define A_COND_MASK 0xf0000000
674 #define A_PUSH_POP_OP_MASK 0x0fff0000
676 /* Opcodes for pushing/poping registers to/from the stack. */
677 #define A1_OPCODE_PUSH 0x092d0000
678 #define A2_OPCODE_PUSH 0x052d0004
679 #define A2_OPCODE_POP 0x049d0004
681 /* Codes to distinguish the arithmetic instructions. */
692 #define OPCODE_CMP 10
693 #define OPCODE_CMN 11
694 #define OPCODE_ORR 12
695 #define OPCODE_MOV 13
696 #define OPCODE_BIC 14
697 #define OPCODE_MVN 15
699 #define T2_OPCODE_AND 0
700 #define T2_OPCODE_BIC 1
701 #define T2_OPCODE_ORR 2
702 #define T2_OPCODE_ORN 3
703 #define T2_OPCODE_EOR 4
704 #define T2_OPCODE_ADD 8
705 #define T2_OPCODE_ADC 10
706 #define T2_OPCODE_SBC 11
707 #define T2_OPCODE_SUB 13
708 #define T2_OPCODE_RSB 14
710 #define T_OPCODE_MUL 0x4340
711 #define T_OPCODE_TST 0x4200
712 #define T_OPCODE_CMN 0x42c0
713 #define T_OPCODE_NEG 0x4240
714 #define T_OPCODE_MVN 0x43c0
716 #define T_OPCODE_ADD_R3 0x1800
717 #define T_OPCODE_SUB_R3 0x1a00
718 #define T_OPCODE_ADD_HI 0x4400
719 #define T_OPCODE_ADD_ST 0xb000
720 #define T_OPCODE_SUB_ST 0xb080
721 #define T_OPCODE_ADD_SP 0xa800
722 #define T_OPCODE_ADD_PC 0xa000
723 #define T_OPCODE_ADD_I8 0x3000
724 #define T_OPCODE_SUB_I8 0x3800
725 #define T_OPCODE_ADD_I3 0x1c00
726 #define T_OPCODE_SUB_I3 0x1e00
728 #define T_OPCODE_ASR_R 0x4100
729 #define T_OPCODE_LSL_R 0x4080
730 #define T_OPCODE_LSR_R 0x40c0
731 #define T_OPCODE_ROR_R 0x41c0
732 #define T_OPCODE_ASR_I 0x1000
733 #define T_OPCODE_LSL_I 0x0000
734 #define T_OPCODE_LSR_I 0x0800
736 #define T_OPCODE_MOV_I8 0x2000
737 #define T_OPCODE_CMP_I8 0x2800
738 #define T_OPCODE_CMP_LR 0x4280
739 #define T_OPCODE_MOV_HR 0x4600
740 #define T_OPCODE_CMP_HR 0x4500
742 #define T_OPCODE_LDR_PC 0x4800
743 #define T_OPCODE_LDR_SP 0x9800
744 #define T_OPCODE_STR_SP 0x9000
745 #define T_OPCODE_LDR_IW 0x6800
746 #define T_OPCODE_STR_IW 0x6000
747 #define T_OPCODE_LDR_IH 0x8800
748 #define T_OPCODE_STR_IH 0x8000
749 #define T_OPCODE_LDR_IB 0x7800
750 #define T_OPCODE_STR_IB 0x7000
751 #define T_OPCODE_LDR_RW 0x5800
752 #define T_OPCODE_STR_RW 0x5000
753 #define T_OPCODE_LDR_RH 0x5a00
754 #define T_OPCODE_STR_RH 0x5200
755 #define T_OPCODE_LDR_RB 0x5c00
756 #define T_OPCODE_STR_RB 0x5400
758 #define T_OPCODE_PUSH 0xb400
759 #define T_OPCODE_POP 0xbc00
761 #define T_OPCODE_BRANCH 0xe000
763 #define THUMB_SIZE 2 /* Size of thumb instruction. */
764 #define THUMB_PP_PC_LR 0x0100
765 #define THUMB_LOAD_BIT 0x0800
766 #define THUMB2_LOAD_BIT 0x00100000
768 #define BAD_ARGS _("bad arguments to instruction")
769 #define BAD_SP _("r13 not allowed here")
770 #define BAD_PC _("r15 not allowed here")
771 #define BAD_COND _("instruction cannot be conditional")
772 #define BAD_OVERLAP _("registers may not be the same")
773 #define BAD_HIREG _("lo register required")
774 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
775 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
776 #define BAD_BRANCH _("branch must be last instruction in IT block")
777 #define BAD_NOT_IT _("instruction not allowed in IT block")
778 #define BAD_FPU _("selected FPU does not support instruction")
779 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
780 #define BAD_IT_COND _("incorrect condition in IT block")
781 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
782 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
783 #define BAD_PC_ADDRESSING \
784 _("cannot use register index with PC-relative addressing")
785 #define BAD_PC_WRITEBACK \
786 _("cannot use writeback with PC-relative addressing")
787 #define BAD_RANGE _("branch out of range")
788 #define BAD_FP16 _("selected processor does not support fp16 instruction")
789 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
790 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
792 static struct hash_control
* arm_ops_hsh
;
793 static struct hash_control
* arm_cond_hsh
;
794 static struct hash_control
* arm_shift_hsh
;
795 static struct hash_control
* arm_psr_hsh
;
796 static struct hash_control
* arm_v7m_psr_hsh
;
797 static struct hash_control
* arm_reg_hsh
;
798 static struct hash_control
* arm_reloc_hsh
;
799 static struct hash_control
* arm_barrier_opt_hsh
;
801 /* Stuff needed to resolve the label ambiguity
810 symbolS
* last_label_seen
;
811 static int label_is_thumb_function_name
= FALSE
;
813 /* Literal pool structure. Held on a per-section
814 and per-sub-section basis. */
816 #define MAX_LITERAL_POOL_SIZE 1024
817 typedef struct literal_pool
819 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
820 unsigned int next_free_entry
;
826 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
828 struct literal_pool
* next
;
829 unsigned int alignment
;
832 /* Pointer to a linked list of literal pools. */
833 literal_pool
* list_of_pools
= NULL
;
835 typedef enum asmfunc_states
838 WAITING_ASMFUNC_NAME
,
842 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
845 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
847 static struct current_it now_it
;
851 now_it_compatible (int cond
)
853 return (cond
& ~1) == (now_it
.cc
& ~1);
857 conditional_insn (void)
859 return inst
.cond
!= COND_ALWAYS
;
862 static int in_it_block (void);
864 static int handle_it_state (void);
866 static void force_automatic_it_block_close (void);
868 static void it_fsm_post_encode (void);
870 #define set_it_insn_type(type) \
873 inst.it_insn_type = type; \
874 if (handle_it_state () == FAIL) \
879 #define set_it_insn_type_nonvoid(type, failret) \
882 inst.it_insn_type = type; \
883 if (handle_it_state () == FAIL) \
888 #define set_it_insn_type_last() \
891 if (inst.cond == COND_ALWAYS) \
892 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
894 set_it_insn_type (INSIDE_IT_LAST_INSN); \
900 /* This array holds the chars that always start a comment. If the
901 pre-processor is disabled, these aren't very useful. */
902 char arm_comment_chars
[] = "@";
904 /* This array holds the chars that only start a comment at the beginning of
905 a line. If the line seems to have the form '# 123 filename'
906 .line and .file directives will appear in the pre-processed output. */
907 /* Note that input_file.c hand checks for '#' at the beginning of the
908 first line of the input file. This is because the compiler outputs
909 #NO_APP at the beginning of its output. */
910 /* Also note that comments like this one will always work. */
911 const char line_comment_chars
[] = "#";
913 char arm_line_separator_chars
[] = ";";
915 /* Chars that can be used to separate mant
916 from exp in floating point numbers. */
917 const char EXP_CHARS
[] = "eE";
919 /* Chars that mean this number is a floating point constant. */
923 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
925 /* Prefix characters that indicate the start of an immediate
927 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
929 /* Separator character handling. */
931 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
934 skip_past_char (char ** str
, char c
)
936 /* PR gas/14987: Allow for whitespace before the expected character. */
937 skip_whitespace (*str
);
948 #define skip_past_comma(str) skip_past_char (str, ',')
950 /* Arithmetic expressions (possibly involving symbols). */
952 /* Return TRUE if anything in the expression is a bignum. */
955 walk_no_bignums (symbolS
* sp
)
957 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
960 if (symbol_get_value_expression (sp
)->X_add_symbol
)
962 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
963 || (symbol_get_value_expression (sp
)->X_op_symbol
964 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
970 static int in_my_get_expression
= 0;
972 /* Third argument to my_get_expression. */
973 #define GE_NO_PREFIX 0
974 #define GE_IMM_PREFIX 1
975 #define GE_OPT_PREFIX 2
976 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
977 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
978 #define GE_OPT_PREFIX_BIG 3
981 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
986 /* In unified syntax, all prefixes are optional. */
988 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
993 case GE_NO_PREFIX
: break;
995 if (!is_immediate_prefix (**str
))
997 inst
.error
= _("immediate expression requires a # prefix");
1003 case GE_OPT_PREFIX_BIG
:
1004 if (is_immediate_prefix (**str
))
1010 memset (ep
, 0, sizeof (expressionS
));
1012 save_in
= input_line_pointer
;
1013 input_line_pointer
= *str
;
1014 in_my_get_expression
= 1;
1015 seg
= expression (ep
);
1016 in_my_get_expression
= 0;
1018 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1020 /* We found a bad or missing expression in md_operand(). */
1021 *str
= input_line_pointer
;
1022 input_line_pointer
= save_in
;
1023 if (inst
.error
== NULL
)
1024 inst
.error
= (ep
->X_op
== O_absent
1025 ? _("missing expression") :_("bad expression"));
1030 if (seg
!= absolute_section
1031 && seg
!= text_section
1032 && seg
!= data_section
1033 && seg
!= bss_section
1034 && seg
!= undefined_section
)
1036 inst
.error
= _("bad segment");
1037 *str
= input_line_pointer
;
1038 input_line_pointer
= save_in
;
1045 /* Get rid of any bignums now, so that we don't generate an error for which
1046 we can't establish a line number later on. Big numbers are never valid
1047 in instructions, which is where this routine is always called. */
1048 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1049 && (ep
->X_op
== O_big
1050 || (ep
->X_add_symbol
1051 && (walk_no_bignums (ep
->X_add_symbol
)
1053 && walk_no_bignums (ep
->X_op_symbol
))))))
1055 inst
.error
= _("invalid constant");
1056 *str
= input_line_pointer
;
1057 input_line_pointer
= save_in
;
1061 *str
= input_line_pointer
;
1062 input_line_pointer
= save_in
;
1066 /* Turn a string in input_line_pointer into a floating point constant
1067 of type TYPE, and store the appropriate bytes in *LITP. The number
1068 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1069 returned, or NULL on OK.
1071 Note that fp constants aren't represent in the normal way on the ARM.
1072 In big endian mode, things are as expected. However, in little endian
1073 mode fp constants are big-endian word-wise, and little-endian byte-wise
1074 within the words. For example, (double) 1.1 in big endian mode is
1075 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1076 the byte sequence 99 99 f1 3f 9a 99 99 99.
1078 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1081 md_atof (int type
, char * litP
, int * sizeP
)
1084 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1116 return _("Unrecognized or unsupported floating point constant");
1119 t
= atof_ieee (input_line_pointer
, type
, words
);
1121 input_line_pointer
= t
;
1122 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1124 if (target_big_endian
)
1126 for (i
= 0; i
< prec
; i
++)
1128 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1129 litP
+= sizeof (LITTLENUM_TYPE
);
1134 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1135 for (i
= prec
- 1; i
>= 0; i
--)
1137 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1138 litP
+= sizeof (LITTLENUM_TYPE
);
1141 /* For a 4 byte float the order of elements in `words' is 1 0.
1142 For an 8 byte float the order is 1 0 3 2. */
1143 for (i
= 0; i
< prec
; i
+= 2)
1145 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1146 sizeof (LITTLENUM_TYPE
));
1147 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1148 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1149 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1156 /* We handle all bad expressions here, so that we can report the faulty
1157 instruction in the error message. */
1159 md_operand (expressionS
* exp
)
1161 if (in_my_get_expression
)
1162 exp
->X_op
= O_illegal
;
1165 /* Immediate values. */
1167 /* Generic immediate-value read function for use in directives.
1168 Accepts anything that 'expression' can fold to a constant.
1169 *val receives the number. */
1172 immediate_for_directive (int *val
)
1175 exp
.X_op
= O_illegal
;
1177 if (is_immediate_prefix (*input_line_pointer
))
1179 input_line_pointer
++;
1183 if (exp
.X_op
!= O_constant
)
1185 as_bad (_("expected #constant"));
1186 ignore_rest_of_line ();
1189 *val
= exp
.X_add_number
;
1194 /* Register parsing. */
1196 /* Generic register parser. CCP points to what should be the
1197 beginning of a register name. If it is indeed a valid register
1198 name, advance CCP over it and return the reg_entry structure;
1199 otherwise return NULL. Does not issue diagnostics. */
1201 static struct reg_entry
*
1202 arm_reg_parse_multi (char **ccp
)
1206 struct reg_entry
*reg
;
1208 skip_whitespace (start
);
1210 #ifdef REGISTER_PREFIX
1211 if (*start
!= REGISTER_PREFIX
)
1215 #ifdef OPTIONAL_REGISTER_PREFIX
1216 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1221 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1226 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1228 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1238 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1239 enum arm_reg_type type
)
1241 /* Alternative syntaxes are accepted for a few register classes. */
1248 /* Generic coprocessor register names are allowed for these. */
1249 if (reg
&& reg
->type
== REG_TYPE_CN
)
1254 /* For backward compatibility, a bare number is valid here. */
1256 unsigned long processor
= strtoul (start
, ccp
, 10);
1257 if (*ccp
!= start
&& processor
<= 15)
1261 case REG_TYPE_MMXWC
:
1262 /* WC includes WCG. ??? I'm not sure this is true for all
1263 instructions that take WC registers. */
1264 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1275 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1276 return value is the register number or FAIL. */
1279 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1282 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1285 /* Do not allow a scalar (reg+index) to parse as a register. */
1286 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1289 if (reg
&& reg
->type
== type
)
1292 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1299 /* Parse a Neon type specifier. *STR should point at the leading '.'
1300 character. Does no verification at this stage that the type fits the opcode
1307 Can all be legally parsed by this function.
1309 Fills in neon_type struct pointer with parsed information, and updates STR
1310 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1311 type, FAIL if not. */
1314 parse_neon_type (struct neon_type
*type
, char **str
)
1321 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1323 enum neon_el_type thistype
= NT_untyped
;
1324 unsigned thissize
= -1u;
1331 /* Just a size without an explicit type. */
1335 switch (TOLOWER (*ptr
))
1337 case 'i': thistype
= NT_integer
; break;
1338 case 'f': thistype
= NT_float
; break;
1339 case 'p': thistype
= NT_poly
; break;
1340 case 's': thistype
= NT_signed
; break;
1341 case 'u': thistype
= NT_unsigned
; break;
1343 thistype
= NT_float
;
1348 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1354 /* .f is an abbreviation for .f32. */
1355 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1360 thissize
= strtoul (ptr
, &ptr
, 10);
1362 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1365 as_bad (_("bad size %d in type specifier"), thissize
);
1373 type
->el
[type
->elems
].type
= thistype
;
1374 type
->el
[type
->elems
].size
= thissize
;
1379 /* Empty/missing type is not a successful parse. */
1380 if (type
->elems
== 0)
1388 /* Errors may be set multiple times during parsing or bit encoding
1389 (particularly in the Neon bits), but usually the earliest error which is set
1390 will be the most meaningful. Avoid overwriting it with later (cascading)
1391 errors by calling this function. */
1394 first_error (const char *err
)
1400 /* Parse a single type, e.g. ".s32", leading period included. */
1402 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1405 struct neon_type optype
;
1409 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1411 if (optype
.elems
== 1)
1412 *vectype
= optype
.el
[0];
1415 first_error (_("only one type should be specified for operand"));
1421 first_error (_("vector type expected"));
1433 /* Special meanings for indices (which have a range of 0-7), which will fit into
1436 #define NEON_ALL_LANES 15
1437 #define NEON_INTERLEAVE_LANES 14
1439 /* Parse either a register or a scalar, with an optional type. Return the
1440 register number, and optionally fill in the actual type of the register
1441 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1442 type/index information in *TYPEINFO. */
1445 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1446 enum arm_reg_type
*rtype
,
1447 struct neon_typed_alias
*typeinfo
)
1450 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1451 struct neon_typed_alias atype
;
1452 struct neon_type_el parsetype
;
1456 atype
.eltype
.type
= NT_invtype
;
1457 atype
.eltype
.size
= -1;
1459 /* Try alternate syntax for some types of register. Note these are mutually
1460 exclusive with the Neon syntax extensions. */
1463 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1471 /* Undo polymorphism when a set of register types may be accepted. */
1472 if ((type
== REG_TYPE_NDQ
1473 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1474 || (type
== REG_TYPE_VFSD
1475 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1476 || (type
== REG_TYPE_NSDQ
1477 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1478 || reg
->type
== REG_TYPE_NQ
))
1479 || (type
== REG_TYPE_MMXWC
1480 && (reg
->type
== REG_TYPE_MMXWCG
)))
1481 type
= (enum arm_reg_type
) reg
->type
;
1483 if (type
!= reg
->type
)
1489 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1491 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1493 first_error (_("can't redefine type for operand"));
1496 atype
.defined
|= NTA_HASTYPE
;
1497 atype
.eltype
= parsetype
;
1500 if (skip_past_char (&str
, '[') == SUCCESS
)
1502 if (type
!= REG_TYPE_VFD
)
1504 first_error (_("only D registers may be indexed"));
1508 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1510 first_error (_("can't change index for operand"));
1514 atype
.defined
|= NTA_HASINDEX
;
1516 if (skip_past_char (&str
, ']') == SUCCESS
)
1517 atype
.index
= NEON_ALL_LANES
;
1522 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1524 if (exp
.X_op
!= O_constant
)
1526 first_error (_("constant expression required"));
1530 if (skip_past_char (&str
, ']') == FAIL
)
1533 atype
.index
= exp
.X_add_number
;
1548 /* Like arm_reg_parse, but allow allow the following extra features:
1549 - If RTYPE is non-zero, return the (possibly restricted) type of the
1550 register (e.g. Neon double or quad reg when either has been requested).
1551 - If this is a Neon vector type with additional type information, fill
1552 in the struct pointed to by VECTYPE (if non-NULL).
1553 This function will fault on encountering a scalar. */
1556 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1557 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1559 struct neon_typed_alias atype
;
1561 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1566 /* Do not allow regname(... to parse as a register. */
1570 /* Do not allow a scalar (reg+index) to parse as a register. */
1571 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1573 first_error (_("register operand expected, but got scalar"));
1578 *vectype
= atype
.eltype
;
1585 #define NEON_SCALAR_REG(X) ((X) >> 4)
1586 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1588 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1589 have enough information to be able to do a good job bounds-checking. So, we
1590 just do easy checks here, and do further checks later. */
1593 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1597 struct neon_typed_alias atype
;
1599 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1601 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1604 if (atype
.index
== NEON_ALL_LANES
)
1606 first_error (_("scalar must have an index"));
1609 else if (atype
.index
>= 64 / elsize
)
1611 first_error (_("scalar index out of range"));
1616 *type
= atype
.eltype
;
1620 return reg
* 16 + atype
.index
;
1623 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1626 parse_reg_list (char ** strp
)
1628 char * str
= * strp
;
1632 /* We come back here if we get ranges concatenated by '+' or '|'. */
1635 skip_whitespace (str
);
1649 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1651 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1661 first_error (_("bad range in register list"));
1665 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1667 if (range
& (1 << i
))
1669 (_("Warning: duplicated register (r%d) in register list"),
1677 if (range
& (1 << reg
))
1678 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1680 else if (reg
<= cur_reg
)
1681 as_tsktsk (_("Warning: register range not in ascending order"));
1686 while (skip_past_comma (&str
) != FAIL
1687 || (in_range
= 1, *str
++ == '-'));
1690 if (skip_past_char (&str
, '}') == FAIL
)
1692 first_error (_("missing `}'"));
1700 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1703 if (exp
.X_op
== O_constant
)
1705 if (exp
.X_add_number
1706 != (exp
.X_add_number
& 0x0000ffff))
1708 inst
.error
= _("invalid register mask");
1712 if ((range
& exp
.X_add_number
) != 0)
1714 int regno
= range
& exp
.X_add_number
;
1717 regno
= (1 << regno
) - 1;
1719 (_("Warning: duplicated register (r%d) in register list"),
1723 range
|= exp
.X_add_number
;
1727 if (inst
.reloc
.type
!= 0)
1729 inst
.error
= _("expression too complex");
1733 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1734 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1735 inst
.reloc
.pc_rel
= 0;
1739 if (*str
== '|' || *str
== '+')
1745 while (another_range
);
1751 /* Types of registers in a list. */
1760 /* Parse a VFP register list. If the string is invalid return FAIL.
1761 Otherwise return the number of registers, and set PBASE to the first
1762 register. Parses registers of type ETYPE.
1763 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1764 - Q registers can be used to specify pairs of D registers
1765 - { } can be omitted from around a singleton register list
1766 FIXME: This is not implemented, as it would require backtracking in
1769 This could be done (the meaning isn't really ambiguous), but doesn't
1770 fit in well with the current parsing framework.
1771 - 32 D registers may be used (also true for VFPv3).
1772 FIXME: Types are ignored in these register lists, which is probably a
1776 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1781 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1785 unsigned long mask
= 0;
1788 if (skip_past_char (&str
, '{') == FAIL
)
1790 inst
.error
= _("expecting {");
1797 regtype
= REG_TYPE_VFS
;
1802 regtype
= REG_TYPE_VFD
;
1805 case REGLIST_NEON_D
:
1806 regtype
= REG_TYPE_NDQ
;
1810 if (etype
!= REGLIST_VFP_S
)
1812 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1813 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1817 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1820 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1827 base_reg
= max_regs
;
1831 int setmask
= 1, addregs
= 1;
1833 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1835 if (new_base
== FAIL
)
1837 first_error (_(reg_expected_msgs
[regtype
]));
1841 if (new_base
>= max_regs
)
1843 first_error (_("register out of range in list"));
1847 /* Note: a value of 2 * n is returned for the register Q<n>. */
1848 if (regtype
== REG_TYPE_NQ
)
1854 if (new_base
< base_reg
)
1855 base_reg
= new_base
;
1857 if (mask
& (setmask
<< new_base
))
1859 first_error (_("invalid register list"));
1863 if ((mask
>> new_base
) != 0 && ! warned
)
1865 as_tsktsk (_("register list not in ascending order"));
1869 mask
|= setmask
<< new_base
;
1872 if (*str
== '-') /* We have the start of a range expression */
1878 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1881 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1885 if (high_range
>= max_regs
)
1887 first_error (_("register out of range in list"));
1891 if (regtype
== REG_TYPE_NQ
)
1892 high_range
= high_range
+ 1;
1894 if (high_range
<= new_base
)
1896 inst
.error
= _("register range not in ascending order");
1900 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1902 if (mask
& (setmask
<< new_base
))
1904 inst
.error
= _("invalid register list");
1908 mask
|= setmask
<< new_base
;
1913 while (skip_past_comma (&str
) != FAIL
);
1917 /* Sanity check -- should have raised a parse error above. */
1918 if (count
== 0 || count
> max_regs
)
1923 /* Final test -- the registers must be consecutive. */
1925 for (i
= 0; i
< count
; i
++)
1927 if ((mask
& (1u << i
)) == 0)
1929 inst
.error
= _("non-contiguous register range");
1939 /* True if two alias types are the same. */
1942 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1950 if (a
->defined
!= b
->defined
)
1953 if ((a
->defined
& NTA_HASTYPE
) != 0
1954 && (a
->eltype
.type
!= b
->eltype
.type
1955 || a
->eltype
.size
!= b
->eltype
.size
))
1958 if ((a
->defined
& NTA_HASINDEX
) != 0
1959 && (a
->index
!= b
->index
))
1965 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1966 The base register is put in *PBASE.
1967 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1969 The register stride (minus one) is put in bit 4 of the return value.
1970 Bits [6:5] encode the list length (minus one).
1971 The type of the list elements is put in *ELTYPE, if non-NULL. */
1973 #define NEON_LANE(X) ((X) & 0xf)
1974 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1975 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1978 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1979 struct neon_type_el
*eltype
)
1986 int leading_brace
= 0;
1987 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1988 const char *const incr_error
= _("register stride must be 1 or 2");
1989 const char *const type_error
= _("mismatched element/structure types in list");
1990 struct neon_typed_alias firsttype
;
1992 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1997 struct neon_typed_alias atype
;
1998 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2002 first_error (_(reg_expected_msgs
[rtype
]));
2009 if (rtype
== REG_TYPE_NQ
)
2015 else if (reg_incr
== -1)
2017 reg_incr
= getreg
- base_reg
;
2018 if (reg_incr
< 1 || reg_incr
> 2)
2020 first_error (_(incr_error
));
2024 else if (getreg
!= base_reg
+ reg_incr
* count
)
2026 first_error (_(incr_error
));
2030 if (! neon_alias_types_same (&atype
, &firsttype
))
2032 first_error (_(type_error
));
2036 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2040 struct neon_typed_alias htype
;
2041 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2043 lane
= NEON_INTERLEAVE_LANES
;
2044 else if (lane
!= NEON_INTERLEAVE_LANES
)
2046 first_error (_(type_error
));
2051 else if (reg_incr
!= 1)
2053 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2057 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2060 first_error (_(reg_expected_msgs
[rtype
]));
2063 if (! neon_alias_types_same (&htype
, &firsttype
))
2065 first_error (_(type_error
));
2068 count
+= hireg
+ dregs
- getreg
;
2072 /* If we're using Q registers, we can't use [] or [n] syntax. */
2073 if (rtype
== REG_TYPE_NQ
)
2079 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2083 else if (lane
!= atype
.index
)
2085 first_error (_(type_error
));
2089 else if (lane
== -1)
2090 lane
= NEON_INTERLEAVE_LANES
;
2091 else if (lane
!= NEON_INTERLEAVE_LANES
)
2093 first_error (_(type_error
));
2098 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2100 /* No lane set by [x]. We must be interleaving structures. */
2102 lane
= NEON_INTERLEAVE_LANES
;
2105 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2106 || (count
> 1 && reg_incr
== -1))
2108 first_error (_("error parsing element/structure list"));
2112 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2114 first_error (_("expected }"));
2122 *eltype
= firsttype
.eltype
;
2127 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2130 /* Parse an explicit relocation suffix on an expression. This is
2131 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2132 arm_reloc_hsh contains no entries, so this function can only
2133 succeed if there is no () after the word. Returns -1 on error,
2134 BFD_RELOC_UNUSED if there wasn't any suffix. */
2137 parse_reloc (char **str
)
2139 struct reloc_entry
*r
;
2143 return BFD_RELOC_UNUSED
;
2148 while (*q
&& *q
!= ')' && *q
!= ',')
2153 if ((r
= (struct reloc_entry
*)
2154 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2161 /* Directives: register aliases. */
2163 static struct reg_entry
*
2164 insert_reg_alias (char *str
, unsigned number
, int type
)
2166 struct reg_entry
*new_reg
;
2169 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2171 if (new_reg
->builtin
)
2172 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2174 /* Only warn about a redefinition if it's not defined as the
2176 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2177 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2182 name
= xstrdup (str
);
2183 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2185 new_reg
->name
= name
;
2186 new_reg
->number
= number
;
2187 new_reg
->type
= type
;
2188 new_reg
->builtin
= FALSE
;
2189 new_reg
->neon
= NULL
;
2191 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2198 insert_neon_reg_alias (char *str
, int number
, int type
,
2199 struct neon_typed_alias
*atype
)
2201 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2205 first_error (_("attempt to redefine typed alias"));
2211 reg
->neon
= (struct neon_typed_alias
*)
2212 xmalloc (sizeof (struct neon_typed_alias
));
2213 *reg
->neon
= *atype
;
2217 /* Look for the .req directive. This is of the form:
2219 new_register_name .req existing_register_name
2221 If we find one, or if it looks sufficiently like one that we want to
2222 handle any error here, return TRUE. Otherwise return FALSE. */
2225 create_register_alias (char * newname
, char *p
)
2227 struct reg_entry
*old
;
2228 char *oldname
, *nbuf
;
2231 /* The input scrubber ensures that whitespace after the mnemonic is
2232 collapsed to single spaces. */
2234 if (strncmp (oldname
, " .req ", 6) != 0)
2238 if (*oldname
== '\0')
2241 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2244 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2248 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2249 the desired alias name, and p points to its end. If not, then
2250 the desired alias name is in the global original_case_string. */
2251 #ifdef TC_CASE_SENSITIVE
2254 newname
= original_case_string
;
2255 nlen
= strlen (newname
);
2258 nbuf
= (char *) alloca (nlen
+ 1);
2259 memcpy (nbuf
, newname
, nlen
);
2262 /* Create aliases under the new name as stated; an all-lowercase
2263 version of the new name; and an all-uppercase version of the new
2265 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2267 for (p
= nbuf
; *p
; p
++)
2270 if (strncmp (nbuf
, newname
, nlen
))
2272 /* If this attempt to create an additional alias fails, do not bother
2273 trying to create the all-lower case alias. We will fail and issue
2274 a second, duplicate error message. This situation arises when the
2275 programmer does something like:
2278 The second .req creates the "Foo" alias but then fails to create
2279 the artificial FOO alias because it has already been created by the
2281 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2285 for (p
= nbuf
; *p
; p
++)
2288 if (strncmp (nbuf
, newname
, nlen
))
2289 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2295 /* Create a Neon typed/indexed register alias using directives, e.g.:
2300 These typed registers can be used instead of the types specified after the
2301 Neon mnemonic, so long as all operands given have types. Types can also be
2302 specified directly, e.g.:
2303 vadd d0.s32, d1.s32, d2.s32 */
2306 create_neon_reg_alias (char *newname
, char *p
)
2308 enum arm_reg_type basetype
;
2309 struct reg_entry
*basereg
;
2310 struct reg_entry mybasereg
;
2311 struct neon_type ntype
;
2312 struct neon_typed_alias typeinfo
;
2313 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2316 typeinfo
.defined
= 0;
2317 typeinfo
.eltype
.type
= NT_invtype
;
2318 typeinfo
.eltype
.size
= -1;
2319 typeinfo
.index
= -1;
2323 if (strncmp (p
, " .dn ", 5) == 0)
2324 basetype
= REG_TYPE_VFD
;
2325 else if (strncmp (p
, " .qn ", 5) == 0)
2326 basetype
= REG_TYPE_NQ
;
2335 basereg
= arm_reg_parse_multi (&p
);
2337 if (basereg
&& basereg
->type
!= basetype
)
2339 as_bad (_("bad type for register"));
2343 if (basereg
== NULL
)
2346 /* Try parsing as an integer. */
2347 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2348 if (exp
.X_op
!= O_constant
)
2350 as_bad (_("expression must be constant"));
2353 basereg
= &mybasereg
;
2354 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2360 typeinfo
= *basereg
->neon
;
2362 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2364 /* We got a type. */
2365 if (typeinfo
.defined
& NTA_HASTYPE
)
2367 as_bad (_("can't redefine the type of a register alias"));
2371 typeinfo
.defined
|= NTA_HASTYPE
;
2372 if (ntype
.elems
!= 1)
2374 as_bad (_("you must specify a single type only"));
2377 typeinfo
.eltype
= ntype
.el
[0];
2380 if (skip_past_char (&p
, '[') == SUCCESS
)
2383 /* We got a scalar index. */
2385 if (typeinfo
.defined
& NTA_HASINDEX
)
2387 as_bad (_("can't redefine the index of a scalar alias"));
2391 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2393 if (exp
.X_op
!= O_constant
)
2395 as_bad (_("scalar index must be constant"));
2399 typeinfo
.defined
|= NTA_HASINDEX
;
2400 typeinfo
.index
= exp
.X_add_number
;
2402 if (skip_past_char (&p
, ']') == FAIL
)
2404 as_bad (_("expecting ]"));
2409 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2410 the desired alias name, and p points to its end. If not, then
2411 the desired alias name is in the global original_case_string. */
2412 #ifdef TC_CASE_SENSITIVE
2413 namelen
= nameend
- newname
;
2415 newname
= original_case_string
;
2416 namelen
= strlen (newname
);
2419 namebuf
= (char *) alloca (namelen
+ 1);
2420 strncpy (namebuf
, newname
, namelen
);
2421 namebuf
[namelen
] = '\0';
2423 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2424 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2426 /* Insert name in all uppercase. */
2427 for (p
= namebuf
; *p
; p
++)
2430 if (strncmp (namebuf
, newname
, namelen
))
2431 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2432 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2434 /* Insert name in all lowercase. */
2435 for (p
= namebuf
; *p
; p
++)
2438 if (strncmp (namebuf
, newname
, namelen
))
2439 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2440 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2445 /* Should never be called, as .req goes between the alias and the
2446 register name, not at the beginning of the line. */
2449 s_req (int a ATTRIBUTE_UNUSED
)
2451 as_bad (_("invalid syntax for .req directive"));
2455 s_dn (int a ATTRIBUTE_UNUSED
)
2457 as_bad (_("invalid syntax for .dn directive"));
2461 s_qn (int a ATTRIBUTE_UNUSED
)
2463 as_bad (_("invalid syntax for .qn directive"));
2466 /* The .unreq directive deletes an alias which was previously defined
2467 by .req. For example:
2473 s_unreq (int a ATTRIBUTE_UNUSED
)
2478 name
= input_line_pointer
;
2480 while (*input_line_pointer
!= 0
2481 && *input_line_pointer
!= ' '
2482 && *input_line_pointer
!= '\n')
2483 ++input_line_pointer
;
2485 saved_char
= *input_line_pointer
;
2486 *input_line_pointer
= 0;
2489 as_bad (_("invalid syntax for .unreq directive"));
2492 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2496 as_bad (_("unknown register alias '%s'"), name
);
2497 else if (reg
->builtin
)
2498 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2505 hash_delete (arm_reg_hsh
, name
, FALSE
);
2506 free ((char *) reg
->name
);
2511 /* Also locate the all upper case and all lower case versions.
2512 Do not complain if we cannot find one or the other as it
2513 was probably deleted above. */
2515 nbuf
= strdup (name
);
2516 for (p
= nbuf
; *p
; p
++)
2518 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2521 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2522 free ((char *) reg
->name
);
2528 for (p
= nbuf
; *p
; p
++)
2530 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2533 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2534 free ((char *) reg
->name
);
2544 *input_line_pointer
= saved_char
;
2545 demand_empty_rest_of_line ();
2548 /* Directives: Instruction set selection. */
2551 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2552 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2553 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2554 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2556 /* Create a new mapping symbol for the transition to STATE. */
2559 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2562 const char * symname
;
2569 type
= BSF_NO_FLAGS
;
2573 type
= BSF_NO_FLAGS
;
2577 type
= BSF_NO_FLAGS
;
2583 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2584 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2589 THUMB_SET_FUNC (symbolP
, 0);
2590 ARM_SET_THUMB (symbolP
, 0);
2591 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2595 THUMB_SET_FUNC (symbolP
, 1);
2596 ARM_SET_THUMB (symbolP
, 1);
2597 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2605 /* Save the mapping symbols for future reference. Also check that
2606 we do not place two mapping symbols at the same offset within a
2607 frag. We'll handle overlap between frags in
2608 check_mapping_symbols.
2610 If .fill or other data filling directive generates zero sized data,
2611 the mapping symbol for the following code will have the same value
2612 as the one generated for the data filling directive. In this case,
2613 we replace the old symbol with the new one at the same address. */
2616 if (frag
->tc_frag_data
.first_map
!= NULL
)
2618 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2619 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2621 frag
->tc_frag_data
.first_map
= symbolP
;
2623 if (frag
->tc_frag_data
.last_map
!= NULL
)
2625 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2626 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2627 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2629 frag
->tc_frag_data
.last_map
= symbolP
;
2632 /* We must sometimes convert a region marked as code to data during
2633 code alignment, if an odd number of bytes have to be padded. The
2634 code mapping symbol is pushed to an aligned address. */
2637 insert_data_mapping_symbol (enum mstate state
,
2638 valueT value
, fragS
*frag
, offsetT bytes
)
2640 /* If there was already a mapping symbol, remove it. */
2641 if (frag
->tc_frag_data
.last_map
!= NULL
2642 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2644 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2648 know (frag
->tc_frag_data
.first_map
== symp
);
2649 frag
->tc_frag_data
.first_map
= NULL
;
2651 frag
->tc_frag_data
.last_map
= NULL
;
2652 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2655 make_mapping_symbol (MAP_DATA
, value
, frag
);
2656 make_mapping_symbol (state
, value
+ bytes
, frag
);
2659 static void mapping_state_2 (enum mstate state
, int max_chars
);
2661 /* Set the mapping state to STATE. Only call this when about to
2662 emit some STATE bytes to the file. */
2664 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2666 mapping_state (enum mstate state
)
2668 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2670 if (mapstate
== state
)
2671 /* The mapping symbol has already been emitted.
2672 There is nothing else to do. */
2675 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2677 All ARM instructions require 4-byte alignment.
2678 (Almost) all Thumb instructions require 2-byte alignment.
2680 When emitting instructions into any section, mark the section
2683 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2684 but themselves require 2-byte alignment; this applies to some
2685 PC- relative forms. However, these cases will invovle implicit
2686 literal pool generation or an explicit .align >=2, both of
2687 which will cause the section to me marked with sufficient
2688 alignment. Thus, we don't handle those cases here. */
2689 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2691 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2692 /* This case will be evaluated later. */
2695 mapping_state_2 (state
, 0);
2698 /* Same as mapping_state, but MAX_CHARS bytes have already been
2699 allocated. Put the mapping symbol that far back. */
2702 mapping_state_2 (enum mstate state
, int max_chars
)
2704 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2706 if (!SEG_NORMAL (now_seg
))
2709 if (mapstate
== state
)
2710 /* The mapping symbol has already been emitted.
2711 There is nothing else to do. */
2714 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2715 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2717 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2718 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2721 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2724 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2725 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2729 #define mapping_state(x) ((void)0)
2730 #define mapping_state_2(x, y) ((void)0)
2733 /* Find the real, Thumb encoded start of a Thumb function. */
2737 find_real_start (symbolS
* symbolP
)
2740 const char * name
= S_GET_NAME (symbolP
);
2741 symbolS
* new_target
;
2743 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2744 #define STUB_NAME ".real_start_of"
2749 /* The compiler may generate BL instructions to local labels because
2750 it needs to perform a branch to a far away location. These labels
2751 do not have a corresponding ".real_start_of" label. We check
2752 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2753 the ".real_start_of" convention for nonlocal branches. */
2754 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2757 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2758 new_target
= symbol_find (real_start
);
2760 if (new_target
== NULL
)
2762 as_warn (_("Failed to find real start of function: %s\n"), name
);
2763 new_target
= symbolP
;
2771 opcode_select (int width
)
2778 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2779 as_bad (_("selected processor does not support THUMB opcodes"));
2782 /* No need to force the alignment, since we will have been
2783 coming from ARM mode, which is word-aligned. */
2784 record_alignment (now_seg
, 1);
2791 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2792 as_bad (_("selected processor does not support ARM opcodes"));
2797 frag_align (2, 0, 0);
2799 record_alignment (now_seg
, 1);
2804 as_bad (_("invalid instruction size selected (%d)"), width
);
2809 s_arm (int ignore ATTRIBUTE_UNUSED
)
2812 demand_empty_rest_of_line ();
2816 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2819 demand_empty_rest_of_line ();
2823 s_code (int unused ATTRIBUTE_UNUSED
)
2827 temp
= get_absolute_expression ();
2832 opcode_select (temp
);
2836 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2841 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2843 /* If we are not already in thumb mode go into it, EVEN if
2844 the target processor does not support thumb instructions.
2845 This is used by gcc/config/arm/lib1funcs.asm for example
2846 to compile interworking support functions even if the
2847 target processor should not support interworking. */
2851 record_alignment (now_seg
, 1);
2854 demand_empty_rest_of_line ();
2858 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2862 /* The following label is the name/address of the start of a Thumb function.
2863 We need to know this for the interworking support. */
2864 label_is_thumb_function_name
= TRUE
;
2867 /* Perform a .set directive, but also mark the alias as
2868 being a thumb function. */
2871 s_thumb_set (int equiv
)
2873 /* XXX the following is a duplicate of the code for s_set() in read.c
2874 We cannot just call that code as we need to get at the symbol that
2881 /* Especial apologies for the random logic:
2882 This just grew, and could be parsed much more simply!
2884 delim
= get_symbol_name (& name
);
2885 end_name
= input_line_pointer
;
2886 (void) restore_line_pointer (delim
);
2888 if (*input_line_pointer
!= ',')
2891 as_bad (_("expected comma after name \"%s\""), name
);
2893 ignore_rest_of_line ();
2897 input_line_pointer
++;
2900 if (name
[0] == '.' && name
[1] == '\0')
2902 /* XXX - this should not happen to .thumb_set. */
2906 if ((symbolP
= symbol_find (name
)) == NULL
2907 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2910 /* When doing symbol listings, play games with dummy fragments living
2911 outside the normal fragment chain to record the file and line info
2913 if (listing
& LISTING_SYMBOLS
)
2915 extern struct list_info_struct
* listing_tail
;
2916 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2918 memset (dummy_frag
, 0, sizeof (fragS
));
2919 dummy_frag
->fr_type
= rs_fill
;
2920 dummy_frag
->line
= listing_tail
;
2921 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2922 dummy_frag
->fr_symbol
= symbolP
;
2926 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2929 /* "set" symbols are local unless otherwise specified. */
2930 SF_SET_LOCAL (symbolP
);
2931 #endif /* OBJ_COFF */
2932 } /* Make a new symbol. */
2934 symbol_table_insert (symbolP
);
2939 && S_IS_DEFINED (symbolP
)
2940 && S_GET_SEGMENT (symbolP
) != reg_section
)
2941 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2943 pseudo_set (symbolP
);
2945 demand_empty_rest_of_line ();
2947 /* XXX Now we come to the Thumb specific bit of code. */
2949 THUMB_SET_FUNC (symbolP
, 1);
2950 ARM_SET_THUMB (symbolP
, 1);
2951 #if defined OBJ_ELF || defined OBJ_COFF
2952 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2956 /* Directives: Mode selection. */
2958 /* .syntax [unified|divided] - choose the new unified syntax
2959 (same for Arm and Thumb encoding, modulo slight differences in what
2960 can be represented) or the old divergent syntax for each mode. */
2962 s_syntax (int unused ATTRIBUTE_UNUSED
)
2966 delim
= get_symbol_name (& name
);
2968 if (!strcasecmp (name
, "unified"))
2969 unified_syntax
= TRUE
;
2970 else if (!strcasecmp (name
, "divided"))
2971 unified_syntax
= FALSE
;
2974 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2977 (void) restore_line_pointer (delim
);
2978 demand_empty_rest_of_line ();
2981 /* Directives: sectioning and alignment. */
2984 s_bss (int ignore ATTRIBUTE_UNUSED
)
2986 /* We don't support putting frags in the BSS segment, we fake it by
2987 marking in_bss, then looking at s_skip for clues. */
2988 subseg_set (bss_section
, 0);
2989 demand_empty_rest_of_line ();
2991 #ifdef md_elf_section_change_hook
2992 md_elf_section_change_hook ();
2997 s_even (int ignore ATTRIBUTE_UNUSED
)
2999 /* Never make frag if expect extra pass. */
3001 frag_align (1, 0, 0);
3003 record_alignment (now_seg
, 1);
3005 demand_empty_rest_of_line ();
3008 /* Directives: CodeComposer Studio. */
3010 /* .ref (for CodeComposer Studio syntax only). */
3012 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3014 if (codecomposer_syntax
)
3015 ignore_rest_of_line ();
3017 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3020 /* If name is not NULL, then it is used for marking the beginning of a
3021 function, wherease if it is NULL then it means the function end. */
3023 asmfunc_debug (const char * name
)
3025 static const char * last_name
= NULL
;
3029 gas_assert (last_name
== NULL
);
3032 if (debug_type
== DEBUG_STABS
)
3033 stabs_generate_asm_func (name
, name
);
3037 gas_assert (last_name
!= NULL
);
3039 if (debug_type
== DEBUG_STABS
)
3040 stabs_generate_asm_endfunc (last_name
, last_name
);
3047 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3049 if (codecomposer_syntax
)
3051 switch (asmfunc_state
)
3053 case OUTSIDE_ASMFUNC
:
3054 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3057 case WAITING_ASMFUNC_NAME
:
3058 as_bad (_(".asmfunc repeated."));
3061 case WAITING_ENDASMFUNC
:
3062 as_bad (_(".asmfunc without function."));
3065 demand_empty_rest_of_line ();
3068 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3072 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3074 if (codecomposer_syntax
)
3076 switch (asmfunc_state
)
3078 case OUTSIDE_ASMFUNC
:
3079 as_bad (_(".endasmfunc without a .asmfunc."));
3082 case WAITING_ASMFUNC_NAME
:
3083 as_bad (_(".endasmfunc without function."));
3086 case WAITING_ENDASMFUNC
:
3087 asmfunc_state
= OUTSIDE_ASMFUNC
;
3088 asmfunc_debug (NULL
);
3091 demand_empty_rest_of_line ();
3094 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3098 s_ccs_def (int name
)
3100 if (codecomposer_syntax
)
3103 as_bad (_(".def pseudo-op only available with -mccs flag."));
3106 /* Directives: Literal pools. */
3108 static literal_pool
*
3109 find_literal_pool (void)
3111 literal_pool
* pool
;
3113 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3115 if (pool
->section
== now_seg
3116 && pool
->sub_section
== now_subseg
)
3123 static literal_pool
*
3124 find_or_make_literal_pool (void)
3126 /* Next literal pool ID number. */
3127 static unsigned int latest_pool_num
= 1;
3128 literal_pool
* pool
;
3130 pool
= find_literal_pool ();
3134 /* Create a new pool. */
3135 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
3139 pool
->next_free_entry
= 0;
3140 pool
->section
= now_seg
;
3141 pool
->sub_section
= now_subseg
;
3142 pool
->next
= list_of_pools
;
3143 pool
->symbol
= NULL
;
3144 pool
->alignment
= 2;
3146 /* Add it to the list. */
3147 list_of_pools
= pool
;
3150 /* New pools, and emptied pools, will have a NULL symbol. */
3151 if (pool
->symbol
== NULL
)
3153 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3154 (valueT
) 0, &zero_address_frag
);
3155 pool
->id
= latest_pool_num
++;
3162 /* Add the literal in the global 'inst'
3163 structure to the relevant literal pool. */
3166 add_to_lit_pool (unsigned int nbytes
)
3168 #define PADDING_SLOT 0x1
3169 #define LIT_ENTRY_SIZE_MASK 0xFF
3170 literal_pool
* pool
;
3171 unsigned int entry
, pool_size
= 0;
3172 bfd_boolean padding_slot_p
= FALSE
;
3178 imm1
= inst
.operands
[1].imm
;
3179 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3180 : inst
.reloc
.exp
.X_unsigned
? 0
3181 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3182 if (target_big_endian
)
3185 imm2
= inst
.operands
[1].imm
;
3189 pool
= find_or_make_literal_pool ();
3191 /* Check if this literal value is already in the pool. */
3192 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3196 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3197 && (inst
.reloc
.exp
.X_op
== O_constant
)
3198 && (pool
->literals
[entry
].X_add_number
3199 == inst
.reloc
.exp
.X_add_number
)
3200 && (pool
->literals
[entry
].X_md
== nbytes
)
3201 && (pool
->literals
[entry
].X_unsigned
3202 == inst
.reloc
.exp
.X_unsigned
))
3205 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3206 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3207 && (pool
->literals
[entry
].X_add_number
3208 == inst
.reloc
.exp
.X_add_number
)
3209 && (pool
->literals
[entry
].X_add_symbol
3210 == inst
.reloc
.exp
.X_add_symbol
)
3211 && (pool
->literals
[entry
].X_op_symbol
3212 == inst
.reloc
.exp
.X_op_symbol
)
3213 && (pool
->literals
[entry
].X_md
== nbytes
))
3216 else if ((nbytes
== 8)
3217 && !(pool_size
& 0x7)
3218 && ((entry
+ 1) != pool
->next_free_entry
)
3219 && (pool
->literals
[entry
].X_op
== O_constant
)
3220 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3221 && (pool
->literals
[entry
].X_unsigned
3222 == inst
.reloc
.exp
.X_unsigned
)
3223 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3224 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3225 && (pool
->literals
[entry
+ 1].X_unsigned
3226 == inst
.reloc
.exp
.X_unsigned
))
3229 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3230 if (padding_slot_p
&& (nbytes
== 4))
3236 /* Do we need to create a new entry? */
3237 if (entry
== pool
->next_free_entry
)
3239 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3241 inst
.error
= _("literal pool overflow");
3247 /* For 8-byte entries, we align to an 8-byte boundary,
3248 and split it into two 4-byte entries, because on 32-bit
3249 host, 8-byte constants are treated as big num, thus
3250 saved in "generic_bignum" which will be overwritten
3251 by later assignments.
3253 We also need to make sure there is enough space for
3256 We also check to make sure the literal operand is a
3258 if (!(inst
.reloc
.exp
.X_op
== O_constant
3259 || inst
.reloc
.exp
.X_op
== O_big
))
3261 inst
.error
= _("invalid type for literal pool");
3264 else if (pool_size
& 0x7)
3266 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3268 inst
.error
= _("literal pool overflow");
3272 pool
->literals
[entry
] = inst
.reloc
.exp
;
3273 pool
->literals
[entry
].X_add_number
= 0;
3274 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3275 pool
->next_free_entry
+= 1;
3278 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3280 inst
.error
= _("literal pool overflow");
3284 pool
->literals
[entry
] = inst
.reloc
.exp
;
3285 pool
->literals
[entry
].X_op
= O_constant
;
3286 pool
->literals
[entry
].X_add_number
= imm1
;
3287 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3288 pool
->literals
[entry
++].X_md
= 4;
3289 pool
->literals
[entry
] = inst
.reloc
.exp
;
3290 pool
->literals
[entry
].X_op
= O_constant
;
3291 pool
->literals
[entry
].X_add_number
= imm2
;
3292 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3293 pool
->literals
[entry
].X_md
= 4;
3294 pool
->alignment
= 3;
3295 pool
->next_free_entry
+= 1;
3299 pool
->literals
[entry
] = inst
.reloc
.exp
;
3300 pool
->literals
[entry
].X_md
= 4;
3304 /* PR ld/12974: Record the location of the first source line to reference
3305 this entry in the literal pool. If it turns out during linking that the
3306 symbol does not exist we will be able to give an accurate line number for
3307 the (first use of the) missing reference. */
3308 if (debug_type
== DEBUG_DWARF2
)
3309 dwarf2_where (pool
->locs
+ entry
);
3311 pool
->next_free_entry
+= 1;
3313 else if (padding_slot_p
)
3315 pool
->literals
[entry
] = inst
.reloc
.exp
;
3316 pool
->literals
[entry
].X_md
= nbytes
;
3319 inst
.reloc
.exp
.X_op
= O_symbol
;
3320 inst
.reloc
.exp
.X_add_number
= pool_size
;
3321 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3327 tc_start_label_without_colon (void)
3329 bfd_boolean ret
= TRUE
;
3331 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3333 const char *label
= input_line_pointer
;
3335 while (!is_end_of_line
[(int) label
[-1]])
3340 as_bad (_("Invalid label '%s'"), label
);
3344 asmfunc_debug (label
);
3346 asmfunc_state
= WAITING_ENDASMFUNC
;
3352 /* Can't use symbol_new here, so have to create a symbol and then at
3353 a later date assign it a value. Thats what these functions do. */
3356 symbol_locate (symbolS
* symbolP
,
3357 const char * name
, /* It is copied, the caller can modify. */
3358 segT segment
, /* Segment identifier (SEG_<something>). */
3359 valueT valu
, /* Symbol value. */
3360 fragS
* frag
) /* Associated fragment. */
3363 char * preserved_copy_of_name
;
3365 name_length
= strlen (name
) + 1; /* +1 for \0. */
3366 obstack_grow (¬es
, name
, name_length
);
3367 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3369 #ifdef tc_canonicalize_symbol_name
3370 preserved_copy_of_name
=
3371 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3374 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3376 S_SET_SEGMENT (symbolP
, segment
);
3377 S_SET_VALUE (symbolP
, valu
);
3378 symbol_clear_list_pointers (symbolP
);
3380 symbol_set_frag (symbolP
, frag
);
3382 /* Link to end of symbol chain. */
3384 extern int symbol_table_frozen
;
3386 if (symbol_table_frozen
)
3390 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3392 obj_symbol_new_hook (symbolP
);
3394 #ifdef tc_symbol_new_hook
3395 tc_symbol_new_hook (symbolP
);
3399 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3400 #endif /* DEBUG_SYMS */
3404 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3407 literal_pool
* pool
;
3410 pool
= find_literal_pool ();
3412 || pool
->symbol
== NULL
3413 || pool
->next_free_entry
== 0)
3416 /* Align pool as you have word accesses.
3417 Only make a frag if we have to. */
3419 frag_align (pool
->alignment
, 0, 0);
3421 record_alignment (now_seg
, 2);
3424 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3425 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3427 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3429 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3430 (valueT
) frag_now_fix (), frag_now
);
3431 symbol_table_insert (pool
->symbol
);
3433 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3435 #if defined OBJ_COFF || defined OBJ_ELF
3436 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3439 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3442 if (debug_type
== DEBUG_DWARF2
)
3443 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3445 /* First output the expression in the instruction to the pool. */
3446 emit_expr (&(pool
->literals
[entry
]),
3447 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3450 /* Mark the pool as empty. */
3451 pool
->next_free_entry
= 0;
3452 pool
->symbol
= NULL
;
3456 /* Forward declarations for functions below, in the MD interface
3458 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3459 static valueT
create_unwind_entry (int);
3460 static void start_unwind_section (const segT
, int);
3461 static void add_unwind_opcode (valueT
, int);
3462 static void flush_pending_unwind (void);
3464 /* Directives: Data. */
3467 s_arm_elf_cons (int nbytes
)
3471 #ifdef md_flush_pending_output
3472 md_flush_pending_output ();
3475 if (is_it_end_of_statement ())
3477 demand_empty_rest_of_line ();
3481 #ifdef md_cons_align
3482 md_cons_align (nbytes
);
3485 mapping_state (MAP_DATA
);
3489 char *base
= input_line_pointer
;
3493 if (exp
.X_op
!= O_symbol
)
3494 emit_expr (&exp
, (unsigned int) nbytes
);
3497 char *before_reloc
= input_line_pointer
;
3498 reloc
= parse_reloc (&input_line_pointer
);
3501 as_bad (_("unrecognized relocation suffix"));
3502 ignore_rest_of_line ();
3505 else if (reloc
== BFD_RELOC_UNUSED
)
3506 emit_expr (&exp
, (unsigned int) nbytes
);
3509 reloc_howto_type
*howto
= (reloc_howto_type
*)
3510 bfd_reloc_type_lookup (stdoutput
,
3511 (bfd_reloc_code_real_type
) reloc
);
3512 int size
= bfd_get_reloc_size (howto
);
3514 if (reloc
== BFD_RELOC_ARM_PLT32
)
3516 as_bad (_("(plt) is only valid on branch targets"));
3517 reloc
= BFD_RELOC_UNUSED
;
3522 as_bad (_("%s relocations do not fit in %d bytes"),
3523 howto
->name
, nbytes
);
3526 /* We've parsed an expression stopping at O_symbol.
3527 But there may be more expression left now that we
3528 have parsed the relocation marker. Parse it again.
3529 XXX Surely there is a cleaner way to do this. */
3530 char *p
= input_line_pointer
;
3532 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3533 memcpy (save_buf
, base
, input_line_pointer
- base
);
3534 memmove (base
+ (input_line_pointer
- before_reloc
),
3535 base
, before_reloc
- base
);
3537 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3539 memcpy (base
, save_buf
, p
- base
);
3541 offset
= nbytes
- size
;
3542 p
= frag_more (nbytes
);
3543 memset (p
, 0, nbytes
);
3544 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3545 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3550 while (*input_line_pointer
++ == ',');
3552 /* Put terminator back into stream. */
3553 input_line_pointer
--;
3554 demand_empty_rest_of_line ();
3557 /* Emit an expression containing a 32-bit thumb instruction.
3558 Implementation based on put_thumb32_insn. */
3561 emit_thumb32_expr (expressionS
* exp
)
3563 expressionS exp_high
= *exp
;
3565 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3566 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3567 exp
->X_add_number
&= 0xffff;
3568 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3571 /* Guess the instruction size based on the opcode. */
3574 thumb_insn_size (int opcode
)
3576 if ((unsigned int) opcode
< 0xe800u
)
3578 else if ((unsigned int) opcode
>= 0xe8000000u
)
3585 emit_insn (expressionS
*exp
, int nbytes
)
3589 if (exp
->X_op
== O_constant
)
3594 size
= thumb_insn_size (exp
->X_add_number
);
3598 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3600 as_bad (_(".inst.n operand too big. "\
3601 "Use .inst.w instead"));
3606 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3607 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3609 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3611 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3612 emit_thumb32_expr (exp
);
3614 emit_expr (exp
, (unsigned int) size
);
3616 it_fsm_post_encode ();
3620 as_bad (_("cannot determine Thumb instruction size. " \
3621 "Use .inst.n/.inst.w instead"));
3624 as_bad (_("constant expression required"));
3629 /* Like s_arm_elf_cons but do not use md_cons_align and
3630 set the mapping state to MAP_ARM/MAP_THUMB. */
3633 s_arm_elf_inst (int nbytes
)
3635 if (is_it_end_of_statement ())
3637 demand_empty_rest_of_line ();
3641 /* Calling mapping_state () here will not change ARM/THUMB,
3642 but will ensure not to be in DATA state. */
3645 mapping_state (MAP_THUMB
);
3650 as_bad (_("width suffixes are invalid in ARM mode"));
3651 ignore_rest_of_line ();
3657 mapping_state (MAP_ARM
);
3666 if (! emit_insn (& exp
, nbytes
))
3668 ignore_rest_of_line ();
3672 while (*input_line_pointer
++ == ',');
3674 /* Put terminator back into stream. */
3675 input_line_pointer
--;
3676 demand_empty_rest_of_line ();
3679 /* Parse a .rel31 directive. */
3682 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3689 if (*input_line_pointer
== '1')
3690 highbit
= 0x80000000;
3691 else if (*input_line_pointer
!= '0')
3692 as_bad (_("expected 0 or 1"));
3694 input_line_pointer
++;
3695 if (*input_line_pointer
!= ',')
3696 as_bad (_("missing comma"));
3697 input_line_pointer
++;
3699 #ifdef md_flush_pending_output
3700 md_flush_pending_output ();
3703 #ifdef md_cons_align
3707 mapping_state (MAP_DATA
);
3712 md_number_to_chars (p
, highbit
, 4);
3713 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3714 BFD_RELOC_ARM_PREL31
);
3716 demand_empty_rest_of_line ();
3719 /* Directives: AEABI stack-unwind tables. */
3721 /* Parse an unwind_fnstart directive. Simply records the current location. */
3724 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3726 demand_empty_rest_of_line ();
3727 if (unwind
.proc_start
)
3729 as_bad (_("duplicate .fnstart directive"));
3733 /* Mark the start of the function. */
3734 unwind
.proc_start
= expr_build_dot ();
3736 /* Reset the rest of the unwind info. */
3737 unwind
.opcode_count
= 0;
3738 unwind
.table_entry
= NULL
;
3739 unwind
.personality_routine
= NULL
;
3740 unwind
.personality_index
= -1;
3741 unwind
.frame_size
= 0;
3742 unwind
.fp_offset
= 0;
3743 unwind
.fp_reg
= REG_SP
;
3745 unwind
.sp_restored
= 0;
3749 /* Parse a handlerdata directive. Creates the exception handling table entry
3750 for the function. */
3753 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3755 demand_empty_rest_of_line ();
3756 if (!unwind
.proc_start
)
3757 as_bad (MISSING_FNSTART
);
3759 if (unwind
.table_entry
)
3760 as_bad (_("duplicate .handlerdata directive"));
3762 create_unwind_entry (1);
3765 /* Parse an unwind_fnend directive. Generates the index table entry. */
3768 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3773 unsigned int marked_pr_dependency
;
3775 demand_empty_rest_of_line ();
3777 if (!unwind
.proc_start
)
3779 as_bad (_(".fnend directive without .fnstart"));
3783 /* Add eh table entry. */
3784 if (unwind
.table_entry
== NULL
)
3785 val
= create_unwind_entry (0);
3789 /* Add index table entry. This is two words. */
3790 start_unwind_section (unwind
.saved_seg
, 1);
3791 frag_align (2, 0, 0);
3792 record_alignment (now_seg
, 2);
3794 ptr
= frag_more (8);
3796 where
= frag_now_fix () - 8;
3798 /* Self relative offset of the function start. */
3799 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3800 BFD_RELOC_ARM_PREL31
);
3802 /* Indicate dependency on EHABI-defined personality routines to the
3803 linker, if it hasn't been done already. */
3804 marked_pr_dependency
3805 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3806 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3807 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3809 static const char *const name
[] =
3811 "__aeabi_unwind_cpp_pr0",
3812 "__aeabi_unwind_cpp_pr1",
3813 "__aeabi_unwind_cpp_pr2"
3815 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3816 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3817 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3818 |= 1 << unwind
.personality_index
;
3822 /* Inline exception table entry. */
3823 md_number_to_chars (ptr
+ 4, val
, 4);
3825 /* Self relative offset of the table entry. */
3826 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3827 BFD_RELOC_ARM_PREL31
);
3829 /* Restore the original section. */
3830 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3832 unwind
.proc_start
= NULL
;
3836 /* Parse an unwind_cantunwind directive. */
3839 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3841 demand_empty_rest_of_line ();
3842 if (!unwind
.proc_start
)
3843 as_bad (MISSING_FNSTART
);
3845 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3846 as_bad (_("personality routine specified for cantunwind frame"));
3848 unwind
.personality_index
= -2;
3852 /* Parse a personalityindex directive. */
3855 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3859 if (!unwind
.proc_start
)
3860 as_bad (MISSING_FNSTART
);
3862 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3863 as_bad (_("duplicate .personalityindex directive"));
3867 if (exp
.X_op
!= O_constant
3868 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3870 as_bad (_("bad personality routine number"));
3871 ignore_rest_of_line ();
3875 unwind
.personality_index
= exp
.X_add_number
;
3877 demand_empty_rest_of_line ();
3881 /* Parse a personality directive. */
3884 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3888 if (!unwind
.proc_start
)
3889 as_bad (MISSING_FNSTART
);
3891 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3892 as_bad (_("duplicate .personality directive"));
3894 c
= get_symbol_name (& name
);
3895 p
= input_line_pointer
;
3897 ++ input_line_pointer
;
3898 unwind
.personality_routine
= symbol_find_or_make (name
);
3900 demand_empty_rest_of_line ();
3904 /* Parse a directive saving core registers. */
3907 s_arm_unwind_save_core (void)
3913 range
= parse_reg_list (&input_line_pointer
);
3916 as_bad (_("expected register list"));
3917 ignore_rest_of_line ();
3921 demand_empty_rest_of_line ();
3923 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3924 into .unwind_save {..., sp...}. We aren't bothered about the value of
3925 ip because it is clobbered by calls. */
3926 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3927 && (range
& 0x3000) == 0x1000)
3929 unwind
.opcode_count
--;
3930 unwind
.sp_restored
= 0;
3931 range
= (range
| 0x2000) & ~0x1000;
3932 unwind
.pending_offset
= 0;
3938 /* See if we can use the short opcodes. These pop a block of up to 8
3939 registers starting with r4, plus maybe r14. */
3940 for (n
= 0; n
< 8; n
++)
3942 /* Break at the first non-saved register. */
3943 if ((range
& (1 << (n
+ 4))) == 0)
3946 /* See if there are any other bits set. */
3947 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3949 /* Use the long form. */
3950 op
= 0x8000 | ((range
>> 4) & 0xfff);
3951 add_unwind_opcode (op
, 2);
3955 /* Use the short form. */
3957 op
= 0xa8; /* Pop r14. */
3959 op
= 0xa0; /* Do not pop r14. */
3961 add_unwind_opcode (op
, 1);
3968 op
= 0xb100 | (range
& 0xf);
3969 add_unwind_opcode (op
, 2);
3972 /* Record the number of bytes pushed. */
3973 for (n
= 0; n
< 16; n
++)
3975 if (range
& (1 << n
))
3976 unwind
.frame_size
+= 4;
3981 /* Parse a directive saving FPA registers. */
3984 s_arm_unwind_save_fpa (int reg
)
3990 /* Get Number of registers to transfer. */
3991 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3994 exp
.X_op
= O_illegal
;
3996 if (exp
.X_op
!= O_constant
)
3998 as_bad (_("expected , <constant>"));
3999 ignore_rest_of_line ();
4003 num_regs
= exp
.X_add_number
;
4005 if (num_regs
< 1 || num_regs
> 4)
4007 as_bad (_("number of registers must be in the range [1:4]"));
4008 ignore_rest_of_line ();
4012 demand_empty_rest_of_line ();
4017 op
= 0xb4 | (num_regs
- 1);
4018 add_unwind_opcode (op
, 1);
4023 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4024 add_unwind_opcode (op
, 2);
4026 unwind
.frame_size
+= num_regs
* 12;
4030 /* Parse a directive saving VFP registers for ARMv6 and above. */
4033 s_arm_unwind_save_vfp_armv6 (void)
4038 int num_vfpv3_regs
= 0;
4039 int num_regs_below_16
;
4041 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4044 as_bad (_("expected register list"));
4045 ignore_rest_of_line ();
4049 demand_empty_rest_of_line ();
4051 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4052 than FSTMX/FLDMX-style ones). */
4054 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4056 num_vfpv3_regs
= count
;
4057 else if (start
+ count
> 16)
4058 num_vfpv3_regs
= start
+ count
- 16;
4060 if (num_vfpv3_regs
> 0)
4062 int start_offset
= start
> 16 ? start
- 16 : 0;
4063 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4064 add_unwind_opcode (op
, 2);
4067 /* Generate opcode for registers numbered in the range 0 .. 15. */
4068 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4069 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4070 if (num_regs_below_16
> 0)
4072 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4073 add_unwind_opcode (op
, 2);
4076 unwind
.frame_size
+= count
* 8;
4080 /* Parse a directive saving VFP registers for pre-ARMv6. */
4083 s_arm_unwind_save_vfp (void)
4089 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4092 as_bad (_("expected register list"));
4093 ignore_rest_of_line ();
4097 demand_empty_rest_of_line ();
4102 op
= 0xb8 | (count
- 1);
4103 add_unwind_opcode (op
, 1);
4108 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4109 add_unwind_opcode (op
, 2);
4111 unwind
.frame_size
+= count
* 8 + 4;
4115 /* Parse a directive saving iWMMXt data registers. */
4118 s_arm_unwind_save_mmxwr (void)
4126 if (*input_line_pointer
== '{')
4127 input_line_pointer
++;
4131 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4135 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4140 as_tsktsk (_("register list not in ascending order"));
4143 if (*input_line_pointer
== '-')
4145 input_line_pointer
++;
4146 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4149 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4152 else if (reg
>= hi_reg
)
4154 as_bad (_("bad register range"));
4157 for (; reg
< hi_reg
; reg
++)
4161 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4163 skip_past_char (&input_line_pointer
, '}');
4165 demand_empty_rest_of_line ();
4167 /* Generate any deferred opcodes because we're going to be looking at
4169 flush_pending_unwind ();
4171 for (i
= 0; i
< 16; i
++)
4173 if (mask
& (1 << i
))
4174 unwind
.frame_size
+= 8;
4177 /* Attempt to combine with a previous opcode. We do this because gcc
4178 likes to output separate unwind directives for a single block of
4180 if (unwind
.opcode_count
> 0)
4182 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4183 if ((i
& 0xf8) == 0xc0)
4186 /* Only merge if the blocks are contiguous. */
4189 if ((mask
& 0xfe00) == (1 << 9))
4191 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4192 unwind
.opcode_count
--;
4195 else if (i
== 6 && unwind
.opcode_count
>= 2)
4197 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4201 op
= 0xffff << (reg
- 1);
4203 && ((mask
& op
) == (1u << (reg
- 1))))
4205 op
= (1 << (reg
+ i
+ 1)) - 1;
4206 op
&= ~((1 << reg
) - 1);
4208 unwind
.opcode_count
-= 2;
4215 /* We want to generate opcodes in the order the registers have been
4216 saved, ie. descending order. */
4217 for (reg
= 15; reg
>= -1; reg
--)
4219 /* Save registers in blocks. */
4221 || !(mask
& (1 << reg
)))
4223 /* We found an unsaved reg. Generate opcodes to save the
4230 op
= 0xc0 | (hi_reg
- 10);
4231 add_unwind_opcode (op
, 1);
4236 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4237 add_unwind_opcode (op
, 2);
4246 ignore_rest_of_line ();
4250 s_arm_unwind_save_mmxwcg (void)
4257 if (*input_line_pointer
== '{')
4258 input_line_pointer
++;
4260 skip_whitespace (input_line_pointer
);
4264 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4268 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4274 as_tsktsk (_("register list not in ascending order"));
4277 if (*input_line_pointer
== '-')
4279 input_line_pointer
++;
4280 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4283 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4286 else if (reg
>= hi_reg
)
4288 as_bad (_("bad register range"));
4291 for (; reg
< hi_reg
; reg
++)
4295 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4297 skip_past_char (&input_line_pointer
, '}');
4299 demand_empty_rest_of_line ();
4301 /* Generate any deferred opcodes because we're going to be looking at
4303 flush_pending_unwind ();
4305 for (reg
= 0; reg
< 16; reg
++)
4307 if (mask
& (1 << reg
))
4308 unwind
.frame_size
+= 4;
4311 add_unwind_opcode (op
, 2);
4314 ignore_rest_of_line ();
4318 /* Parse an unwind_save directive.
4319 If the argument is non-zero, this is a .vsave directive. */
4322 s_arm_unwind_save (int arch_v6
)
4325 struct reg_entry
*reg
;
4326 bfd_boolean had_brace
= FALSE
;
4328 if (!unwind
.proc_start
)
4329 as_bad (MISSING_FNSTART
);
4331 /* Figure out what sort of save we have. */
4332 peek
= input_line_pointer
;
4340 reg
= arm_reg_parse_multi (&peek
);
4344 as_bad (_("register expected"));
4345 ignore_rest_of_line ();
4354 as_bad (_("FPA .unwind_save does not take a register list"));
4355 ignore_rest_of_line ();
4358 input_line_pointer
= peek
;
4359 s_arm_unwind_save_fpa (reg
->number
);
4363 s_arm_unwind_save_core ();
4368 s_arm_unwind_save_vfp_armv6 ();
4370 s_arm_unwind_save_vfp ();
4373 case REG_TYPE_MMXWR
:
4374 s_arm_unwind_save_mmxwr ();
4377 case REG_TYPE_MMXWCG
:
4378 s_arm_unwind_save_mmxwcg ();
4382 as_bad (_(".unwind_save does not support this kind of register"));
4383 ignore_rest_of_line ();
4388 /* Parse an unwind_movsp directive. */
4391 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4397 if (!unwind
.proc_start
)
4398 as_bad (MISSING_FNSTART
);
4400 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4403 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4404 ignore_rest_of_line ();
4408 /* Optional constant. */
4409 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4411 if (immediate_for_directive (&offset
) == FAIL
)
4417 demand_empty_rest_of_line ();
4419 if (reg
== REG_SP
|| reg
== REG_PC
)
4421 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4425 if (unwind
.fp_reg
!= REG_SP
)
4426 as_bad (_("unexpected .unwind_movsp directive"));
4428 /* Generate opcode to restore the value. */
4430 add_unwind_opcode (op
, 1);
4432 /* Record the information for later. */
4433 unwind
.fp_reg
= reg
;
4434 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4435 unwind
.sp_restored
= 1;
4438 /* Parse an unwind_pad directive. */
4441 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4445 if (!unwind
.proc_start
)
4446 as_bad (MISSING_FNSTART
);
4448 if (immediate_for_directive (&offset
) == FAIL
)
4453 as_bad (_("stack increment must be multiple of 4"));
4454 ignore_rest_of_line ();
4458 /* Don't generate any opcodes, just record the details for later. */
4459 unwind
.frame_size
+= offset
;
4460 unwind
.pending_offset
+= offset
;
4462 demand_empty_rest_of_line ();
4465 /* Parse an unwind_setfp directive. */
4468 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4474 if (!unwind
.proc_start
)
4475 as_bad (MISSING_FNSTART
);
4477 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4478 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4481 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4483 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4485 as_bad (_("expected <reg>, <reg>"));
4486 ignore_rest_of_line ();
4490 /* Optional constant. */
4491 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4493 if (immediate_for_directive (&offset
) == FAIL
)
4499 demand_empty_rest_of_line ();
4501 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4503 as_bad (_("register must be either sp or set by a previous"
4504 "unwind_movsp directive"));
4508 /* Don't generate any opcodes, just record the information for later. */
4509 unwind
.fp_reg
= fp_reg
;
4511 if (sp_reg
== REG_SP
)
4512 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4514 unwind
.fp_offset
-= offset
;
4517 /* Parse an unwind_raw directive. */
4520 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4523 /* This is an arbitrary limit. */
4524 unsigned char op
[16];
4527 if (!unwind
.proc_start
)
4528 as_bad (MISSING_FNSTART
);
4531 if (exp
.X_op
== O_constant
4532 && skip_past_comma (&input_line_pointer
) != FAIL
)
4534 unwind
.frame_size
+= exp
.X_add_number
;
4538 exp
.X_op
= O_illegal
;
4540 if (exp
.X_op
!= O_constant
)
4542 as_bad (_("expected <offset>, <opcode>"));
4543 ignore_rest_of_line ();
4549 /* Parse the opcode. */
4554 as_bad (_("unwind opcode too long"));
4555 ignore_rest_of_line ();
4557 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4559 as_bad (_("invalid unwind opcode"));
4560 ignore_rest_of_line ();
4563 op
[count
++] = exp
.X_add_number
;
4565 /* Parse the next byte. */
4566 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4572 /* Add the opcode bytes in reverse order. */
4574 add_unwind_opcode (op
[count
], 1);
4576 demand_empty_rest_of_line ();
4580 /* Parse a .eabi_attribute directive. */
4583 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4585 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4587 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4588 attributes_set_explicitly
[tag
] = 1;
4591 /* Emit a tls fix for the symbol. */
4594 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4598 #ifdef md_flush_pending_output
4599 md_flush_pending_output ();
4602 #ifdef md_cons_align
4606 /* Since we're just labelling the code, there's no need to define a
4609 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4610 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4611 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4612 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4614 #endif /* OBJ_ELF */
4616 static void s_arm_arch (int);
4617 static void s_arm_object_arch (int);
4618 static void s_arm_cpu (int);
4619 static void s_arm_fpu (int);
4620 static void s_arm_arch_extension (int);
4625 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4632 if (exp
.X_op
== O_symbol
)
4633 exp
.X_op
= O_secrel
;
4635 emit_expr (&exp
, 4);
4637 while (*input_line_pointer
++ == ',');
4639 input_line_pointer
--;
4640 demand_empty_rest_of_line ();
4644 /* This table describes all the machine specific pseudo-ops the assembler
4645 has to support. The fields are:
4646 pseudo-op name without dot
4647 function to call to execute this pseudo-op
4648 Integer arg to pass to the function. */
4650 const pseudo_typeS md_pseudo_table
[] =
4652 /* Never called because '.req' does not start a line. */
4653 { "req", s_req
, 0 },
4654 /* Following two are likewise never called. */
4657 { "unreq", s_unreq
, 0 },
4658 { "bss", s_bss
, 0 },
4659 { "align", s_align_ptwo
, 2 },
4660 { "arm", s_arm
, 0 },
4661 { "thumb", s_thumb
, 0 },
4662 { "code", s_code
, 0 },
4663 { "force_thumb", s_force_thumb
, 0 },
4664 { "thumb_func", s_thumb_func
, 0 },
4665 { "thumb_set", s_thumb_set
, 0 },
4666 { "even", s_even
, 0 },
4667 { "ltorg", s_ltorg
, 0 },
4668 { "pool", s_ltorg
, 0 },
4669 { "syntax", s_syntax
, 0 },
4670 { "cpu", s_arm_cpu
, 0 },
4671 { "arch", s_arm_arch
, 0 },
4672 { "object_arch", s_arm_object_arch
, 0 },
4673 { "fpu", s_arm_fpu
, 0 },
4674 { "arch_extension", s_arm_arch_extension
, 0 },
4676 { "word", s_arm_elf_cons
, 4 },
4677 { "long", s_arm_elf_cons
, 4 },
4678 { "inst.n", s_arm_elf_inst
, 2 },
4679 { "inst.w", s_arm_elf_inst
, 4 },
4680 { "inst", s_arm_elf_inst
, 0 },
4681 { "rel31", s_arm_rel31
, 0 },
4682 { "fnstart", s_arm_unwind_fnstart
, 0 },
4683 { "fnend", s_arm_unwind_fnend
, 0 },
4684 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4685 { "personality", s_arm_unwind_personality
, 0 },
4686 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4687 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4688 { "save", s_arm_unwind_save
, 0 },
4689 { "vsave", s_arm_unwind_save
, 1 },
4690 { "movsp", s_arm_unwind_movsp
, 0 },
4691 { "pad", s_arm_unwind_pad
, 0 },
4692 { "setfp", s_arm_unwind_setfp
, 0 },
4693 { "unwind_raw", s_arm_unwind_raw
, 0 },
4694 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4695 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4699 /* These are used for dwarf. */
4703 /* These are used for dwarf2. */
4704 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4705 { "loc", dwarf2_directive_loc
, 0 },
4706 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4708 { "extend", float_cons
, 'x' },
4709 { "ldouble", float_cons
, 'x' },
4710 { "packed", float_cons
, 'p' },
4712 {"secrel32", pe_directive_secrel
, 0},
4715 /* These are for compatibility with CodeComposer Studio. */
4716 {"ref", s_ccs_ref
, 0},
4717 {"def", s_ccs_def
, 0},
4718 {"asmfunc", s_ccs_asmfunc
, 0},
4719 {"endasmfunc", s_ccs_endasmfunc
, 0},
4724 /* Parser functions used exclusively in instruction operands. */
4726 /* Generic immediate-value read function for use in insn parsing.
4727 STR points to the beginning of the immediate (the leading #);
4728 VAL receives the value; if the value is outside [MIN, MAX]
4729 issue an error. PREFIX_OPT is true if the immediate prefix is
4733 parse_immediate (char **str
, int *val
, int min
, int max
,
4734 bfd_boolean prefix_opt
)
4737 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4738 if (exp
.X_op
!= O_constant
)
4740 inst
.error
= _("constant expression required");
4744 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4746 inst
.error
= _("immediate value out of range");
4750 *val
= exp
.X_add_number
;
4754 /* Less-generic immediate-value read function with the possibility of loading a
4755 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4756 instructions. Puts the result directly in inst.operands[i]. */
4759 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4760 bfd_boolean allow_symbol_p
)
4763 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4766 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4768 if (exp_p
->X_op
== O_constant
)
4770 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4771 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4772 O_constant. We have to be careful not to break compilation for
4773 32-bit X_add_number, though. */
4774 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4776 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4777 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4779 inst
.operands
[i
].regisimm
= 1;
4782 else if (exp_p
->X_op
== O_big
4783 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4785 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4787 /* Bignums have their least significant bits in
4788 generic_bignum[0]. Make sure we put 32 bits in imm and
4789 32 bits in reg, in a (hopefully) portable way. */
4790 gas_assert (parts
!= 0);
4792 /* Make sure that the number is not too big.
4793 PR 11972: Bignums can now be sign-extended to the
4794 size of a .octa so check that the out of range bits
4795 are all zero or all one. */
4796 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4798 LITTLENUM_TYPE m
= -1;
4800 if (generic_bignum
[parts
* 2] != 0
4801 && generic_bignum
[parts
* 2] != m
)
4804 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4805 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4809 inst
.operands
[i
].imm
= 0;
4810 for (j
= 0; j
< parts
; j
++, idx
++)
4811 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4812 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4813 inst
.operands
[i
].reg
= 0;
4814 for (j
= 0; j
< parts
; j
++, idx
++)
4815 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4816 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4817 inst
.operands
[i
].regisimm
= 1;
4819 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4827 /* Returns the pseudo-register number of an FPA immediate constant,
4828 or FAIL if there isn't a valid constant here. */
4831 parse_fpa_immediate (char ** str
)
4833 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4839 /* First try and match exact strings, this is to guarantee
4840 that some formats will work even for cross assembly. */
4842 for (i
= 0; fp_const
[i
]; i
++)
4844 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4848 *str
+= strlen (fp_const
[i
]);
4849 if (is_end_of_line
[(unsigned char) **str
])
4855 /* Just because we didn't get a match doesn't mean that the constant
4856 isn't valid, just that it is in a format that we don't
4857 automatically recognize. Try parsing it with the standard
4858 expression routines. */
4860 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4862 /* Look for a raw floating point number. */
4863 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4864 && is_end_of_line
[(unsigned char) *save_in
])
4866 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4868 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4870 if (words
[j
] != fp_values
[i
][j
])
4874 if (j
== MAX_LITTLENUMS
)
4882 /* Try and parse a more complex expression, this will probably fail
4883 unless the code uses a floating point prefix (eg "0f"). */
4884 save_in
= input_line_pointer
;
4885 input_line_pointer
= *str
;
4886 if (expression (&exp
) == absolute_section
4887 && exp
.X_op
== O_big
4888 && exp
.X_add_number
< 0)
4890 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4892 #define X_PRECISION 5
4893 #define E_PRECISION 15L
4894 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4896 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4898 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4900 if (words
[j
] != fp_values
[i
][j
])
4904 if (j
== MAX_LITTLENUMS
)
4906 *str
= input_line_pointer
;
4907 input_line_pointer
= save_in
;
4914 *str
= input_line_pointer
;
4915 input_line_pointer
= save_in
;
4916 inst
.error
= _("invalid FPA immediate expression");
4920 /* Returns 1 if a number has "quarter-precision" float format
4921 0baBbbbbbc defgh000 00000000 00000000. */
4924 is_quarter_float (unsigned imm
)
4926 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4927 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4931 /* Detect the presence of a floating point or integer zero constant,
4935 parse_ifimm_zero (char **in
)
4939 if (!is_immediate_prefix (**in
))
4944 /* Accept #0x0 as a synonym for #0. */
4945 if (strncmp (*in
, "0x", 2) == 0)
4948 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4953 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4954 &generic_floating_point_number
);
4957 && generic_floating_point_number
.sign
== '+'
4958 && (generic_floating_point_number
.low
4959 > generic_floating_point_number
.leader
))
4965 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4966 0baBbbbbbc defgh000 00000000 00000000.
4967 The zero and minus-zero cases need special handling, since they can't be
4968 encoded in the "quarter-precision" float format, but can nonetheless be
4969 loaded as integer constants. */
4972 parse_qfloat_immediate (char **ccp
, int *immed
)
4976 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4977 int found_fpchar
= 0;
4979 skip_past_char (&str
, '#');
4981 /* We must not accidentally parse an integer as a floating-point number. Make
4982 sure that the value we parse is not an integer by checking for special
4983 characters '.' or 'e'.
4984 FIXME: This is a horrible hack, but doing better is tricky because type
4985 information isn't in a very usable state at parse time. */
4987 skip_whitespace (fpnum
);
4989 if (strncmp (fpnum
, "0x", 2) == 0)
4993 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4994 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5004 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5006 unsigned fpword
= 0;
5009 /* Our FP word must be 32 bits (single-precision FP). */
5010 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5012 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5016 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5029 /* Shift operands. */
5032 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5035 struct asm_shift_name
5038 enum shift_kind kind
;
5041 /* Third argument to parse_shift. */
5042 enum parse_shift_mode
5044 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5045 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5046 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5047 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5048 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5051 /* Parse a <shift> specifier on an ARM data processing instruction.
5052 This has three forms:
5054 (LSL|LSR|ASL|ASR|ROR) Rs
5055 (LSL|LSR|ASL|ASR|ROR) #imm
5058 Note that ASL is assimilated to LSL in the instruction encoding, and
5059 RRX to ROR #0 (which cannot be written as such). */
5062 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5064 const struct asm_shift_name
*shift_name
;
5065 enum shift_kind shift
;
5070 for (p
= *str
; ISALPHA (*p
); p
++)
5075 inst
.error
= _("shift expression expected");
5079 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5082 if (shift_name
== NULL
)
5084 inst
.error
= _("shift expression expected");
5088 shift
= shift_name
->kind
;
5092 case NO_SHIFT_RESTRICT
:
5093 case SHIFT_IMMEDIATE
: break;
5095 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5096 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5098 inst
.error
= _("'LSL' or 'ASR' required");
5103 case SHIFT_LSL_IMMEDIATE
:
5104 if (shift
!= SHIFT_LSL
)
5106 inst
.error
= _("'LSL' required");
5111 case SHIFT_ASR_IMMEDIATE
:
5112 if (shift
!= SHIFT_ASR
)
5114 inst
.error
= _("'ASR' required");
5122 if (shift
!= SHIFT_RRX
)
5124 /* Whitespace can appear here if the next thing is a bare digit. */
5125 skip_whitespace (p
);
5127 if (mode
== NO_SHIFT_RESTRICT
5128 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5130 inst
.operands
[i
].imm
= reg
;
5131 inst
.operands
[i
].immisreg
= 1;
5133 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5136 inst
.operands
[i
].shift_kind
= shift
;
5137 inst
.operands
[i
].shifted
= 1;
5142 /* Parse a <shifter_operand> for an ARM data processing instruction:
5145 #<immediate>, <rotate>
5149 where <shift> is defined by parse_shift above, and <rotate> is a
5150 multiple of 2 between 0 and 30. Validation of immediate operands
5151 is deferred to md_apply_fix. */
5154 parse_shifter_operand (char **str
, int i
)
5159 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5161 inst
.operands
[i
].reg
= value
;
5162 inst
.operands
[i
].isreg
= 1;
5164 /* parse_shift will override this if appropriate */
5165 inst
.reloc
.exp
.X_op
= O_constant
;
5166 inst
.reloc
.exp
.X_add_number
= 0;
5168 if (skip_past_comma (str
) == FAIL
)
5171 /* Shift operation on register. */
5172 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5175 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5178 if (skip_past_comma (str
) == SUCCESS
)
5180 /* #x, y -- ie explicit rotation by Y. */
5181 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5184 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5186 inst
.error
= _("constant expression expected");
5190 value
= exp
.X_add_number
;
5191 if (value
< 0 || value
> 30 || value
% 2 != 0)
5193 inst
.error
= _("invalid rotation");
5196 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5198 inst
.error
= _("invalid constant");
5202 /* Encode as specified. */
5203 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5207 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5208 inst
.reloc
.pc_rel
= 0;
5212 /* Group relocation information. Each entry in the table contains the
5213 textual name of the relocation as may appear in assembler source
5214 and must end with a colon.
5215 Along with this textual name are the relocation codes to be used if
5216 the corresponding instruction is an ALU instruction (ADD or SUB only),
5217 an LDR, an LDRS, or an LDC. */
5219 struct group_reloc_table_entry
5230 /* Varieties of non-ALU group relocation. */
5237 static struct group_reloc_table_entry group_reloc_table
[] =
5238 { /* Program counter relative: */
5240 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5245 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5246 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5247 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5248 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5250 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5255 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5256 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5257 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5258 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5260 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5261 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5262 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5263 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5264 /* Section base relative */
5266 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5271 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5272 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5273 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5274 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5276 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5281 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5282 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5283 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5284 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5286 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5287 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5288 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5289 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5290 /* Absolute thumb alu relocations. */
5292 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5297 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5302 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5307 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5312 /* Given the address of a pointer pointing to the textual name of a group
5313 relocation as may appear in assembler source, attempt to find its details
5314 in group_reloc_table. The pointer will be updated to the character after
5315 the trailing colon. On failure, FAIL will be returned; SUCCESS
5316 otherwise. On success, *entry will be updated to point at the relevant
5317 group_reloc_table entry. */
5320 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5323 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5325 int length
= strlen (group_reloc_table
[i
].name
);
5327 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5328 && (*str
)[length
] == ':')
5330 *out
= &group_reloc_table
[i
];
5331 *str
+= (length
+ 1);
5339 /* Parse a <shifter_operand> for an ARM data processing instruction
5340 (as for parse_shifter_operand) where group relocations are allowed:
5343 #<immediate>, <rotate>
5344 #:<group_reloc>:<expression>
5348 where <group_reloc> is one of the strings defined in group_reloc_table.
5349 The hashes are optional.
5351 Everything else is as for parse_shifter_operand. */
5353 static parse_operand_result
5354 parse_shifter_operand_group_reloc (char **str
, int i
)
5356 /* Determine if we have the sequence of characters #: or just :
5357 coming next. If we do, then we check for a group relocation.
5358 If we don't, punt the whole lot to parse_shifter_operand. */
5360 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5361 || (*str
)[0] == ':')
5363 struct group_reloc_table_entry
*entry
;
5365 if ((*str
)[0] == '#')
5370 /* Try to parse a group relocation. Anything else is an error. */
5371 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5373 inst
.error
= _("unknown group relocation");
5374 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5377 /* We now have the group relocation table entry corresponding to
5378 the name in the assembler source. Next, we parse the expression. */
5379 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5380 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5382 /* Record the relocation type (always the ALU variant here). */
5383 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5384 gas_assert (inst
.reloc
.type
!= 0);
5386 return PARSE_OPERAND_SUCCESS
;
5389 return parse_shifter_operand (str
, i
) == SUCCESS
5390 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5392 /* Never reached. */
5395 /* Parse a Neon alignment expression. Information is written to
5396 inst.operands[i]. We assume the initial ':' has been skipped.
5398 align .imm = align << 8, .immisalign=1, .preind=0 */
5399 static parse_operand_result
5400 parse_neon_alignment (char **str
, int i
)
5405 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5407 if (exp
.X_op
!= O_constant
)
5409 inst
.error
= _("alignment must be constant");
5410 return PARSE_OPERAND_FAIL
;
5413 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5414 inst
.operands
[i
].immisalign
= 1;
5415 /* Alignments are not pre-indexes. */
5416 inst
.operands
[i
].preind
= 0;
5419 return PARSE_OPERAND_SUCCESS
;
5422 /* Parse all forms of an ARM address expression. Information is written
5423 to inst.operands[i] and/or inst.reloc.
5425 Preindexed addressing (.preind=1):
5427 [Rn, #offset] .reg=Rn .reloc.exp=offset
5428 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5429 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5430 .shift_kind=shift .reloc.exp=shift_imm
5432 These three may have a trailing ! which causes .writeback to be set also.
5434 Postindexed addressing (.postind=1, .writeback=1):
5436 [Rn], #offset .reg=Rn .reloc.exp=offset
5437 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5438 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5439 .shift_kind=shift .reloc.exp=shift_imm
5441 Unindexed addressing (.preind=0, .postind=0):
5443 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5447 [Rn]{!} shorthand for [Rn,#0]{!}
5448 =immediate .isreg=0 .reloc.exp=immediate
5449 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5451 It is the caller's responsibility to check for addressing modes not
5452 supported by the instruction, and to set inst.reloc.type. */
5454 static parse_operand_result
5455 parse_address_main (char **str
, int i
, int group_relocations
,
5456 group_reloc_type group_type
)
5461 if (skip_past_char (&p
, '[') == FAIL
)
5463 if (skip_past_char (&p
, '=') == FAIL
)
5465 /* Bare address - translate to PC-relative offset. */
5466 inst
.reloc
.pc_rel
= 1;
5467 inst
.operands
[i
].reg
= REG_PC
;
5468 inst
.operands
[i
].isreg
= 1;
5469 inst
.operands
[i
].preind
= 1;
5471 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5472 return PARSE_OPERAND_FAIL
;
5474 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5475 /*allow_symbol_p=*/TRUE
))
5476 return PARSE_OPERAND_FAIL
;
5479 return PARSE_OPERAND_SUCCESS
;
5482 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5483 skip_whitespace (p
);
5485 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5487 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5488 return PARSE_OPERAND_FAIL
;
5490 inst
.operands
[i
].reg
= reg
;
5491 inst
.operands
[i
].isreg
= 1;
5493 if (skip_past_comma (&p
) == SUCCESS
)
5495 inst
.operands
[i
].preind
= 1;
5498 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5500 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5502 inst
.operands
[i
].imm
= reg
;
5503 inst
.operands
[i
].immisreg
= 1;
5505 if (skip_past_comma (&p
) == SUCCESS
)
5506 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5507 return PARSE_OPERAND_FAIL
;
5509 else if (skip_past_char (&p
, ':') == SUCCESS
)
5511 /* FIXME: '@' should be used here, but it's filtered out by generic
5512 code before we get to see it here. This may be subject to
5514 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5516 if (result
!= PARSE_OPERAND_SUCCESS
)
5521 if (inst
.operands
[i
].negative
)
5523 inst
.operands
[i
].negative
= 0;
5527 if (group_relocations
5528 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5530 struct group_reloc_table_entry
*entry
;
5532 /* Skip over the #: or : sequence. */
5538 /* Try to parse a group relocation. Anything else is an
5540 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5542 inst
.error
= _("unknown group relocation");
5543 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5546 /* We now have the group relocation table entry corresponding to
5547 the name in the assembler source. Next, we parse the
5549 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5550 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5552 /* Record the relocation type. */
5556 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5560 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5564 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5571 if (inst
.reloc
.type
== 0)
5573 inst
.error
= _("this group relocation is not allowed on this instruction");
5574 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5580 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5581 return PARSE_OPERAND_FAIL
;
5582 /* If the offset is 0, find out if it's a +0 or -0. */
5583 if (inst
.reloc
.exp
.X_op
== O_constant
5584 && inst
.reloc
.exp
.X_add_number
== 0)
5586 skip_whitespace (q
);
5590 skip_whitespace (q
);
5593 inst
.operands
[i
].negative
= 1;
5598 else if (skip_past_char (&p
, ':') == SUCCESS
)
5600 /* FIXME: '@' should be used here, but it's filtered out by generic code
5601 before we get to see it here. This may be subject to change. */
5602 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5604 if (result
!= PARSE_OPERAND_SUCCESS
)
5608 if (skip_past_char (&p
, ']') == FAIL
)
5610 inst
.error
= _("']' expected");
5611 return PARSE_OPERAND_FAIL
;
5614 if (skip_past_char (&p
, '!') == SUCCESS
)
5615 inst
.operands
[i
].writeback
= 1;
5617 else if (skip_past_comma (&p
) == SUCCESS
)
5619 if (skip_past_char (&p
, '{') == SUCCESS
)
5621 /* [Rn], {expr} - unindexed, with option */
5622 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5623 0, 255, TRUE
) == FAIL
)
5624 return PARSE_OPERAND_FAIL
;
5626 if (skip_past_char (&p
, '}') == FAIL
)
5628 inst
.error
= _("'}' expected at end of 'option' field");
5629 return PARSE_OPERAND_FAIL
;
5631 if (inst
.operands
[i
].preind
)
5633 inst
.error
= _("cannot combine index with option");
5634 return PARSE_OPERAND_FAIL
;
5637 return PARSE_OPERAND_SUCCESS
;
5641 inst
.operands
[i
].postind
= 1;
5642 inst
.operands
[i
].writeback
= 1;
5644 if (inst
.operands
[i
].preind
)
5646 inst
.error
= _("cannot combine pre- and post-indexing");
5647 return PARSE_OPERAND_FAIL
;
5651 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5653 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5655 /* We might be using the immediate for alignment already. If we
5656 are, OR the register number into the low-order bits. */
5657 if (inst
.operands
[i
].immisalign
)
5658 inst
.operands
[i
].imm
|= reg
;
5660 inst
.operands
[i
].imm
= reg
;
5661 inst
.operands
[i
].immisreg
= 1;
5663 if (skip_past_comma (&p
) == SUCCESS
)
5664 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5665 return PARSE_OPERAND_FAIL
;
5670 if (inst
.operands
[i
].negative
)
5672 inst
.operands
[i
].negative
= 0;
5675 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5676 return PARSE_OPERAND_FAIL
;
5677 /* If the offset is 0, find out if it's a +0 or -0. */
5678 if (inst
.reloc
.exp
.X_op
== O_constant
5679 && inst
.reloc
.exp
.X_add_number
== 0)
5681 skip_whitespace (q
);
5685 skip_whitespace (q
);
5688 inst
.operands
[i
].negative
= 1;
5694 /* If at this point neither .preind nor .postind is set, we have a
5695 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5696 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5698 inst
.operands
[i
].preind
= 1;
5699 inst
.reloc
.exp
.X_op
= O_constant
;
5700 inst
.reloc
.exp
.X_add_number
= 0;
5703 return PARSE_OPERAND_SUCCESS
;
5707 parse_address (char **str
, int i
)
5709 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5713 static parse_operand_result
5714 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5716 return parse_address_main (str
, i
, 1, type
);
5719 /* Parse an operand for a MOVW or MOVT instruction. */
5721 parse_half (char **str
)
5726 skip_past_char (&p
, '#');
5727 if (strncasecmp (p
, ":lower16:", 9) == 0)
5728 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5729 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5730 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5732 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5735 skip_whitespace (p
);
5738 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5741 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5743 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5745 inst
.error
= _("constant expression expected");
5748 if (inst
.reloc
.exp
.X_add_number
< 0
5749 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5751 inst
.error
= _("immediate value out of range");
5759 /* Miscellaneous. */
5761 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5762 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5764 parse_psr (char **str
, bfd_boolean lhs
)
5767 unsigned long psr_field
;
5768 const struct asm_psr
*psr
;
5770 bfd_boolean is_apsr
= FALSE
;
5771 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5773 /* PR gas/12698: If the user has specified -march=all then m_profile will
5774 be TRUE, but we want to ignore it in this case as we are building for any
5775 CPU type, including non-m variants. */
5776 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5779 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5780 feature for ease of use and backwards compatibility. */
5782 if (strncasecmp (p
, "SPSR", 4) == 0)
5785 goto unsupported_psr
;
5787 psr_field
= SPSR_BIT
;
5789 else if (strncasecmp (p
, "CPSR", 4) == 0)
5792 goto unsupported_psr
;
5796 else if (strncasecmp (p
, "APSR", 4) == 0)
5798 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5799 and ARMv7-R architecture CPUs. */
5808 while (ISALNUM (*p
) || *p
== '_');
5810 if (strncasecmp (start
, "iapsr", 5) == 0
5811 || strncasecmp (start
, "eapsr", 5) == 0
5812 || strncasecmp (start
, "xpsr", 4) == 0
5813 || strncasecmp (start
, "psr", 3) == 0)
5814 p
= start
+ strcspn (start
, "rR") + 1;
5816 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5822 /* If APSR is being written, a bitfield may be specified. Note that
5823 APSR itself is handled above. */
5824 if (psr
->field
<= 3)
5826 psr_field
= psr
->field
;
5832 /* M-profile MSR instructions have the mask field set to "10", except
5833 *PSR variants which modify APSR, which may use a different mask (and
5834 have been handled already). Do that by setting the PSR_f field
5836 return psr
->field
| (lhs
? PSR_f
: 0);
5839 goto unsupported_psr
;
5845 /* A suffix follows. */
5851 while (ISALNUM (*p
) || *p
== '_');
5855 /* APSR uses a notation for bits, rather than fields. */
5856 unsigned int nzcvq_bits
= 0;
5857 unsigned int g_bit
= 0;
5860 for (bit
= start
; bit
!= p
; bit
++)
5862 switch (TOLOWER (*bit
))
5865 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5869 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5873 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5877 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5881 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5885 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5889 inst
.error
= _("unexpected bit specified after APSR");
5894 if (nzcvq_bits
== 0x1f)
5899 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5901 inst
.error
= _("selected processor does not "
5902 "support DSP extension");
5909 if ((nzcvq_bits
& 0x20) != 0
5910 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5911 || (g_bit
& 0x2) != 0)
5913 inst
.error
= _("bad bitmask specified after APSR");
5919 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5924 psr_field
|= psr
->field
;
5930 goto error
; /* Garbage after "[CS]PSR". */
5932 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5933 is deprecated, but allow it anyway. */
5937 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5940 else if (!m_profile
)
5941 /* These bits are never right for M-profile devices: don't set them
5942 (only code paths which read/write APSR reach here). */
5943 psr_field
|= (PSR_c
| PSR_f
);
5949 inst
.error
= _("selected processor does not support requested special "
5950 "purpose register");
5954 inst
.error
= _("flag for {c}psr instruction expected");
5958 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5959 value suitable for splatting into the AIF field of the instruction. */
5962 parse_cps_flags (char **str
)
5971 case '\0': case ',':
5974 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5975 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5976 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5979 inst
.error
= _("unrecognized CPS flag");
5984 if (saw_a_flag
== 0)
5986 inst
.error
= _("missing CPS flags");
5994 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5995 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5998 parse_endian_specifier (char **str
)
6003 if (strncasecmp (s
, "BE", 2))
6005 else if (strncasecmp (s
, "LE", 2))
6009 inst
.error
= _("valid endian specifiers are be or le");
6013 if (ISALNUM (s
[2]) || s
[2] == '_')
6015 inst
.error
= _("valid endian specifiers are be or le");
6020 return little_endian
;
6023 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6024 value suitable for poking into the rotate field of an sxt or sxta
6025 instruction, or FAIL on error. */
6028 parse_ror (char **str
)
6033 if (strncasecmp (s
, "ROR", 3) == 0)
6037 inst
.error
= _("missing rotation field after comma");
6041 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6046 case 0: *str
= s
; return 0x0;
6047 case 8: *str
= s
; return 0x1;
6048 case 16: *str
= s
; return 0x2;
6049 case 24: *str
= s
; return 0x3;
6052 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6057 /* Parse a conditional code (from conds[] below). The value returned is in the
6058 range 0 .. 14, or FAIL. */
6060 parse_cond (char **str
)
6063 const struct asm_cond
*c
;
6065 /* Condition codes are always 2 characters, so matching up to
6066 3 characters is sufficient. */
6071 while (ISALPHA (*q
) && n
< 3)
6073 cond
[n
] = TOLOWER (*q
);
6078 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6081 inst
.error
= _("condition required");
6089 /* Record a use of the given feature. */
6091 record_feature_use (const arm_feature_set
*feature
)
6094 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6096 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6099 /* If the given feature available in the selected CPU, mark it as used.
6100 Returns TRUE iff feature is available. */
6102 mark_feature_used (const arm_feature_set
*feature
)
6104 /* Ensure the option is valid on the current architecture. */
6105 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6108 /* Add the appropriate architecture feature for the barrier option used.
6110 record_feature_use (feature
);
6115 /* Parse an option for a barrier instruction. Returns the encoding for the
6118 parse_barrier (char **str
)
6121 const struct asm_barrier_opt
*o
;
6124 while (ISALPHA (*q
))
6127 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6132 if (!mark_feature_used (&o
->arch
))
6139 /* Parse the operands of a table branch instruction. Similar to a memory
6142 parse_tb (char **str
)
6147 if (skip_past_char (&p
, '[') == FAIL
)
6149 inst
.error
= _("'[' expected");
6153 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6155 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6158 inst
.operands
[0].reg
= reg
;
6160 if (skip_past_comma (&p
) == FAIL
)
6162 inst
.error
= _("',' expected");
6166 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6168 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6171 inst
.operands
[0].imm
= reg
;
6173 if (skip_past_comma (&p
) == SUCCESS
)
6175 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6177 if (inst
.reloc
.exp
.X_add_number
!= 1)
6179 inst
.error
= _("invalid shift");
6182 inst
.operands
[0].shifted
= 1;
6185 if (skip_past_char (&p
, ']') == FAIL
)
6187 inst
.error
= _("']' expected");
6194 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6195 information on the types the operands can take and how they are encoded.
6196 Up to four operands may be read; this function handles setting the
6197 ".present" field for each read operand itself.
6198 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6199 else returns FAIL. */
6202 parse_neon_mov (char **str
, int *which_operand
)
6204 int i
= *which_operand
, val
;
6205 enum arm_reg_type rtype
;
6207 struct neon_type_el optype
;
6209 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6211 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6212 inst
.operands
[i
].reg
= val
;
6213 inst
.operands
[i
].isscalar
= 1;
6214 inst
.operands
[i
].vectype
= optype
;
6215 inst
.operands
[i
++].present
= 1;
6217 if (skip_past_comma (&ptr
) == FAIL
)
6220 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6223 inst
.operands
[i
].reg
= val
;
6224 inst
.operands
[i
].isreg
= 1;
6225 inst
.operands
[i
].present
= 1;
6227 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6230 /* Cases 0, 1, 2, 3, 5 (D only). */
6231 if (skip_past_comma (&ptr
) == FAIL
)
6234 inst
.operands
[i
].reg
= val
;
6235 inst
.operands
[i
].isreg
= 1;
6236 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6237 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6238 inst
.operands
[i
].isvec
= 1;
6239 inst
.operands
[i
].vectype
= optype
;
6240 inst
.operands
[i
++].present
= 1;
6242 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6244 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6245 Case 13: VMOV <Sd>, <Rm> */
6246 inst
.operands
[i
].reg
= val
;
6247 inst
.operands
[i
].isreg
= 1;
6248 inst
.operands
[i
].present
= 1;
6250 if (rtype
== REG_TYPE_NQ
)
6252 first_error (_("can't use Neon quad register here"));
6255 else if (rtype
!= REG_TYPE_VFS
)
6258 if (skip_past_comma (&ptr
) == FAIL
)
6260 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6262 inst
.operands
[i
].reg
= val
;
6263 inst
.operands
[i
].isreg
= 1;
6264 inst
.operands
[i
].present
= 1;
6267 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6270 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6271 Case 1: VMOV<c><q> <Dd>, <Dm>
6272 Case 8: VMOV.F32 <Sd>, <Sm>
6273 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6275 inst
.operands
[i
].reg
= val
;
6276 inst
.operands
[i
].isreg
= 1;
6277 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6278 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6279 inst
.operands
[i
].isvec
= 1;
6280 inst
.operands
[i
].vectype
= optype
;
6281 inst
.operands
[i
].present
= 1;
6283 if (skip_past_comma (&ptr
) == SUCCESS
)
6288 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6291 inst
.operands
[i
].reg
= val
;
6292 inst
.operands
[i
].isreg
= 1;
6293 inst
.operands
[i
++].present
= 1;
6295 if (skip_past_comma (&ptr
) == FAIL
)
6298 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6301 inst
.operands
[i
].reg
= val
;
6302 inst
.operands
[i
].isreg
= 1;
6303 inst
.operands
[i
].present
= 1;
6306 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6307 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6308 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6309 Case 10: VMOV.F32 <Sd>, #<imm>
6310 Case 11: VMOV.F64 <Dd>, #<imm> */
6311 inst
.operands
[i
].immisfloat
= 1;
6312 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6314 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6315 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6319 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6323 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6326 inst
.operands
[i
].reg
= val
;
6327 inst
.operands
[i
].isreg
= 1;
6328 inst
.operands
[i
++].present
= 1;
6330 if (skip_past_comma (&ptr
) == FAIL
)
6333 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6335 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6336 inst
.operands
[i
].reg
= val
;
6337 inst
.operands
[i
].isscalar
= 1;
6338 inst
.operands
[i
].present
= 1;
6339 inst
.operands
[i
].vectype
= optype
;
6341 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6343 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6344 inst
.operands
[i
].reg
= val
;
6345 inst
.operands
[i
].isreg
= 1;
6346 inst
.operands
[i
++].present
= 1;
6348 if (skip_past_comma (&ptr
) == FAIL
)
6351 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6354 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6358 inst
.operands
[i
].reg
= val
;
6359 inst
.operands
[i
].isreg
= 1;
6360 inst
.operands
[i
].isvec
= 1;
6361 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6362 inst
.operands
[i
].vectype
= optype
;
6363 inst
.operands
[i
].present
= 1;
6365 if (rtype
== REG_TYPE_VFS
)
6369 if (skip_past_comma (&ptr
) == FAIL
)
6371 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6374 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6377 inst
.operands
[i
].reg
= val
;
6378 inst
.operands
[i
].isreg
= 1;
6379 inst
.operands
[i
].isvec
= 1;
6380 inst
.operands
[i
].issingle
= 1;
6381 inst
.operands
[i
].vectype
= optype
;
6382 inst
.operands
[i
].present
= 1;
6385 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6389 inst
.operands
[i
].reg
= val
;
6390 inst
.operands
[i
].isreg
= 1;
6391 inst
.operands
[i
].isvec
= 1;
6392 inst
.operands
[i
].issingle
= 1;
6393 inst
.operands
[i
].vectype
= optype
;
6394 inst
.operands
[i
].present
= 1;
6399 first_error (_("parse error"));
6403 /* Successfully parsed the operands. Update args. */
6409 first_error (_("expected comma"));
6413 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6417 /* Use this macro when the operand constraints are different
6418 for ARM and THUMB (e.g. ldrd). */
6419 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6420 ((arm_operand) | ((thumb_operand) << 16))
6422 /* Matcher codes for parse_operands. */
6423 enum operand_parse_code
6425 OP_stop
, /* end of line */
6427 OP_RR
, /* ARM register */
6428 OP_RRnpc
, /* ARM register, not r15 */
6429 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6430 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6431 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6432 optional trailing ! */
6433 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6434 OP_RCP
, /* Coprocessor number */
6435 OP_RCN
, /* Coprocessor register */
6436 OP_RF
, /* FPA register */
6437 OP_RVS
, /* VFP single precision register */
6438 OP_RVD
, /* VFP double precision register (0..15) */
6439 OP_RND
, /* Neon double precision register (0..31) */
6440 OP_RNQ
, /* Neon quad precision register */
6441 OP_RVSD
, /* VFP single or double precision register */
6442 OP_RNDQ
, /* Neon double or quad precision register */
6443 OP_RNSDQ
, /* Neon single, double or quad precision register */
6444 OP_RNSC
, /* Neon scalar D[X] */
6445 OP_RVC
, /* VFP control register */
6446 OP_RMF
, /* Maverick F register */
6447 OP_RMD
, /* Maverick D register */
6448 OP_RMFX
, /* Maverick FX register */
6449 OP_RMDX
, /* Maverick DX register */
6450 OP_RMAX
, /* Maverick AX register */
6451 OP_RMDS
, /* Maverick DSPSC register */
6452 OP_RIWR
, /* iWMMXt wR register */
6453 OP_RIWC
, /* iWMMXt wC register */
6454 OP_RIWG
, /* iWMMXt wCG register */
6455 OP_RXA
, /* XScale accumulator register */
6457 OP_REGLST
, /* ARM register list */
6458 OP_VRSLST
, /* VFP single-precision register list */
6459 OP_VRDLST
, /* VFP double-precision register list */
6460 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6461 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6462 OP_NSTRLST
, /* Neon element/structure list */
6464 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6465 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6466 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6467 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6468 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6469 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6470 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6471 OP_VMOV
, /* Neon VMOV operands. */
6472 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6473 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6474 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6476 OP_I0
, /* immediate zero */
6477 OP_I7
, /* immediate value 0 .. 7 */
6478 OP_I15
, /* 0 .. 15 */
6479 OP_I16
, /* 1 .. 16 */
6480 OP_I16z
, /* 0 .. 16 */
6481 OP_I31
, /* 0 .. 31 */
6482 OP_I31w
, /* 0 .. 31, optional trailing ! */
6483 OP_I32
, /* 1 .. 32 */
6484 OP_I32z
, /* 0 .. 32 */
6485 OP_I63
, /* 0 .. 63 */
6486 OP_I63s
, /* -64 .. 63 */
6487 OP_I64
, /* 1 .. 64 */
6488 OP_I64z
, /* 0 .. 64 */
6489 OP_I255
, /* 0 .. 255 */
6491 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6492 OP_I7b
, /* 0 .. 7 */
6493 OP_I15b
, /* 0 .. 15 */
6494 OP_I31b
, /* 0 .. 31 */
6496 OP_SH
, /* shifter operand */
6497 OP_SHG
, /* shifter operand with possible group relocation */
6498 OP_ADDR
, /* Memory address expression (any mode) */
6499 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6500 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6501 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6502 OP_EXP
, /* arbitrary expression */
6503 OP_EXPi
, /* same, with optional immediate prefix */
6504 OP_EXPr
, /* same, with optional relocation suffix */
6505 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6507 OP_CPSF
, /* CPS flags */
6508 OP_ENDI
, /* Endianness specifier */
6509 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6510 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6511 OP_COND
, /* conditional code */
6512 OP_TB
, /* Table branch. */
6514 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6516 OP_RRnpc_I0
, /* ARM register or literal 0 */
6517 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6518 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6519 OP_RF_IF
, /* FPA register or immediate */
6520 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6521 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6523 /* Optional operands. */
6524 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6525 OP_oI31b
, /* 0 .. 31 */
6526 OP_oI32b
, /* 1 .. 32 */
6527 OP_oI32z
, /* 0 .. 32 */
6528 OP_oIffffb
, /* 0 .. 65535 */
6529 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6531 OP_oRR
, /* ARM register */
6532 OP_oRRnpc
, /* ARM register, not the PC */
6533 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6534 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6535 OP_oRND
, /* Optional Neon double precision register */
6536 OP_oRNQ
, /* Optional Neon quad precision register */
6537 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6538 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6539 OP_oSHll
, /* LSL immediate */
6540 OP_oSHar
, /* ASR immediate */
6541 OP_oSHllar
, /* LSL or ASR immediate */
6542 OP_oROR
, /* ROR 0/8/16/24 */
6543 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6545 /* Some pre-defined mixed (ARM/THUMB) operands. */
6546 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6547 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6548 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6550 OP_FIRST_OPTIONAL
= OP_oI7b
6553 /* Generic instruction operand parser. This does no encoding and no
6554 semantic validation; it merely squirrels values away in the inst
6555 structure. Returns SUCCESS or FAIL depending on whether the
6556 specified grammar matched. */
6558 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6560 unsigned const int *upat
= pattern
;
6561 char *backtrack_pos
= 0;
6562 const char *backtrack_error
= 0;
6563 int i
, val
= 0, backtrack_index
= 0;
6564 enum arm_reg_type rtype
;
6565 parse_operand_result result
;
6566 unsigned int op_parse_code
;
6568 #define po_char_or_fail(chr) \
6571 if (skip_past_char (&str, chr) == FAIL) \
6576 #define po_reg_or_fail(regtype) \
6579 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6580 & inst.operands[i].vectype); \
6583 first_error (_(reg_expected_msgs[regtype])); \
6586 inst.operands[i].reg = val; \
6587 inst.operands[i].isreg = 1; \
6588 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6589 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6590 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6591 || rtype == REG_TYPE_VFD \
6592 || rtype == REG_TYPE_NQ); \
6596 #define po_reg_or_goto(regtype, label) \
6599 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6600 & inst.operands[i].vectype); \
6604 inst.operands[i].reg = val; \
6605 inst.operands[i].isreg = 1; \
6606 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6607 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6608 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6609 || rtype == REG_TYPE_VFD \
6610 || rtype == REG_TYPE_NQ); \
6614 #define po_imm_or_fail(min, max, popt) \
6617 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6619 inst.operands[i].imm = val; \
6623 #define po_scalar_or_goto(elsz, label) \
6626 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6629 inst.operands[i].reg = val; \
6630 inst.operands[i].isscalar = 1; \
6634 #define po_misc_or_fail(expr) \
6642 #define po_misc_or_fail_no_backtrack(expr) \
6646 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6647 backtrack_pos = 0; \
6648 if (result != PARSE_OPERAND_SUCCESS) \
6653 #define po_barrier_or_imm(str) \
6656 val = parse_barrier (&str); \
6657 if (val == FAIL && ! ISALPHA (*str)) \
6660 /* ISB can only take SY as an option. */ \
6661 || ((inst.instruction & 0xf0) == 0x60 \
6664 inst.error = _("invalid barrier type"); \
6665 backtrack_pos = 0; \
6671 skip_whitespace (str
);
6673 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6675 op_parse_code
= upat
[i
];
6676 if (op_parse_code
>= 1<<16)
6677 op_parse_code
= thumb
? (op_parse_code
>> 16)
6678 : (op_parse_code
& ((1<<16)-1));
6680 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6682 /* Remember where we are in case we need to backtrack. */
6683 gas_assert (!backtrack_pos
);
6684 backtrack_pos
= str
;
6685 backtrack_error
= inst
.error
;
6686 backtrack_index
= i
;
6689 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6690 po_char_or_fail (',');
6692 switch (op_parse_code
)
6700 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6701 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6702 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6703 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6704 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6705 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6707 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6709 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6711 /* Also accept generic coprocessor regs for unknown registers. */
6713 po_reg_or_fail (REG_TYPE_CN
);
6715 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6716 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6717 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6718 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6719 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6720 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6721 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6722 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6723 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6724 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6726 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6728 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6729 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6731 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6733 /* Neon scalar. Using an element size of 8 means that some invalid
6734 scalars are accepted here, so deal with those in later code. */
6735 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6739 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6742 po_imm_or_fail (0, 0, TRUE
);
6747 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6752 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6755 if (parse_ifimm_zero (&str
))
6756 inst
.operands
[i
].imm
= 0;
6760 = _("only floating point zero is allowed as immediate value");
6768 po_scalar_or_goto (8, try_rr
);
6771 po_reg_or_fail (REG_TYPE_RN
);
6777 po_scalar_or_goto (8, try_nsdq
);
6780 po_reg_or_fail (REG_TYPE_NSDQ
);
6786 po_scalar_or_goto (8, try_ndq
);
6789 po_reg_or_fail (REG_TYPE_NDQ
);
6795 po_scalar_or_goto (8, try_vfd
);
6798 po_reg_or_fail (REG_TYPE_VFD
);
6803 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6804 not careful then bad things might happen. */
6805 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6810 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6813 /* There's a possibility of getting a 64-bit immediate here, so
6814 we need special handling. */
6815 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6818 inst
.error
= _("immediate value is out of range");
6826 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6829 po_imm_or_fail (0, 63, TRUE
);
6834 po_char_or_fail ('[');
6835 po_reg_or_fail (REG_TYPE_RN
);
6836 po_char_or_fail (']');
6842 po_reg_or_fail (REG_TYPE_RN
);
6843 if (skip_past_char (&str
, '!') == SUCCESS
)
6844 inst
.operands
[i
].writeback
= 1;
6848 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6849 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6850 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6851 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6852 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6853 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6854 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6855 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6856 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6857 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6858 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6859 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6861 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6863 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6864 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6866 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6867 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6868 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6869 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6871 /* Immediate variants */
6873 po_char_or_fail ('{');
6874 po_imm_or_fail (0, 255, TRUE
);
6875 po_char_or_fail ('}');
6879 /* The expression parser chokes on a trailing !, so we have
6880 to find it first and zap it. */
6883 while (*s
&& *s
!= ',')
6888 inst
.operands
[i
].writeback
= 1;
6890 po_imm_or_fail (0, 31, TRUE
);
6898 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6903 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6908 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6910 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6912 val
= parse_reloc (&str
);
6915 inst
.error
= _("unrecognized relocation suffix");
6918 else if (val
!= BFD_RELOC_UNUSED
)
6920 inst
.operands
[i
].imm
= val
;
6921 inst
.operands
[i
].hasreloc
= 1;
6926 /* Operand for MOVW or MOVT. */
6928 po_misc_or_fail (parse_half (&str
));
6931 /* Register or expression. */
6932 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6933 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6935 /* Register or immediate. */
6936 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6937 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6939 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6941 if (!is_immediate_prefix (*str
))
6944 val
= parse_fpa_immediate (&str
);
6947 /* FPA immediates are encoded as registers 8-15.
6948 parse_fpa_immediate has already applied the offset. */
6949 inst
.operands
[i
].reg
= val
;
6950 inst
.operands
[i
].isreg
= 1;
6953 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6954 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6956 /* Two kinds of register. */
6959 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6961 || (rege
->type
!= REG_TYPE_MMXWR
6962 && rege
->type
!= REG_TYPE_MMXWC
6963 && rege
->type
!= REG_TYPE_MMXWCG
))
6965 inst
.error
= _("iWMMXt data or control register expected");
6968 inst
.operands
[i
].reg
= rege
->number
;
6969 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6975 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6977 || (rege
->type
!= REG_TYPE_MMXWC
6978 && rege
->type
!= REG_TYPE_MMXWCG
))
6980 inst
.error
= _("iWMMXt control register expected");
6983 inst
.operands
[i
].reg
= rege
->number
;
6984 inst
.operands
[i
].isreg
= 1;
6989 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6990 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6991 case OP_oROR
: val
= parse_ror (&str
); break;
6992 case OP_COND
: val
= parse_cond (&str
); break;
6993 case OP_oBARRIER_I15
:
6994 po_barrier_or_imm (str
); break;
6996 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7002 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7003 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7005 inst
.error
= _("Banked registers are not available with this "
7011 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7015 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7018 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7020 if (strncasecmp (str
, "APSR_", 5) == 0)
7027 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7028 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7029 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7030 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7031 default: found
= 16;
7035 inst
.operands
[i
].isvec
= 1;
7036 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7037 inst
.operands
[i
].reg
= REG_PC
;
7044 po_misc_or_fail (parse_tb (&str
));
7047 /* Register lists. */
7049 val
= parse_reg_list (&str
);
7052 inst
.operands
[i
].writeback
= 1;
7058 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7062 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7066 /* Allow Q registers too. */
7067 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7072 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7074 inst
.operands
[i
].issingle
= 1;
7079 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7084 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7085 &inst
.operands
[i
].vectype
);
7088 /* Addressing modes */
7090 po_misc_or_fail (parse_address (&str
, i
));
7094 po_misc_or_fail_no_backtrack (
7095 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7099 po_misc_or_fail_no_backtrack (
7100 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7104 po_misc_or_fail_no_backtrack (
7105 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7109 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7113 po_misc_or_fail_no_backtrack (
7114 parse_shifter_operand_group_reloc (&str
, i
));
7118 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7122 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7126 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7130 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7133 /* Various value-based sanity checks and shared operations. We
7134 do not signal immediate failures for the register constraints;
7135 this allows a syntax error to take precedence. */
7136 switch (op_parse_code
)
7144 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7145 inst
.error
= BAD_PC
;
7150 if (inst
.operands
[i
].isreg
)
7152 if (inst
.operands
[i
].reg
== REG_PC
)
7153 inst
.error
= BAD_PC
;
7154 else if (inst
.operands
[i
].reg
== REG_SP
)
7155 inst
.error
= BAD_SP
;
7160 if (inst
.operands
[i
].isreg
7161 && inst
.operands
[i
].reg
== REG_PC
7162 && (inst
.operands
[i
].writeback
|| thumb
))
7163 inst
.error
= BAD_PC
;
7172 case OP_oBARRIER_I15
:
7181 inst
.operands
[i
].imm
= val
;
7188 /* If we get here, this operand was successfully parsed. */
7189 inst
.operands
[i
].present
= 1;
7193 inst
.error
= BAD_ARGS
;
7198 /* The parse routine should already have set inst.error, but set a
7199 default here just in case. */
7201 inst
.error
= _("syntax error");
7205 /* Do not backtrack over a trailing optional argument that
7206 absorbed some text. We will only fail again, with the
7207 'garbage following instruction' error message, which is
7208 probably less helpful than the current one. */
7209 if (backtrack_index
== i
&& backtrack_pos
!= str
7210 && upat
[i
+1] == OP_stop
)
7213 inst
.error
= _("syntax error");
7217 /* Try again, skipping the optional argument at backtrack_pos. */
7218 str
= backtrack_pos
;
7219 inst
.error
= backtrack_error
;
7220 inst
.operands
[backtrack_index
].present
= 0;
7221 i
= backtrack_index
;
7225 /* Check that we have parsed all the arguments. */
7226 if (*str
!= '\0' && !inst
.error
)
7227 inst
.error
= _("garbage following instruction");
7229 return inst
.error
? FAIL
: SUCCESS
;
7232 #undef po_char_or_fail
7233 #undef po_reg_or_fail
7234 #undef po_reg_or_goto
7235 #undef po_imm_or_fail
7236 #undef po_scalar_or_fail
7237 #undef po_barrier_or_imm
7239 /* Shorthand macro for instruction encoding functions issuing errors. */
7240 #define constraint(expr, err) \
7251 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7252 instructions are unpredictable if these registers are used. This
7253 is the BadReg predicate in ARM's Thumb-2 documentation. */
7254 #define reject_bad_reg(reg) \
7256 if (reg == REG_SP || reg == REG_PC) \
7258 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7263 /* If REG is R13 (the stack pointer), warn that its use is
7265 #define warn_deprecated_sp(reg) \
7267 if (warn_on_deprecated && reg == REG_SP) \
7268 as_tsktsk (_("use of r13 is deprecated")); \
7271 /* Functions for operand encoding. ARM, then Thumb. */
7273 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7275 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7277 The only binary encoding difference is the Coprocessor number. Coprocessor
7278 9 is used for half-precision calculations or conversions. The format of the
7279 instruction is the same as the equivalent Coprocessor 10 instuction that
7280 exists for Single-Precision operation. */
7283 do_scalar_fp16_v82_encode (void)
7285 if (inst
.cond
!= COND_ALWAYS
)
7286 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7287 " the behaviour is UNPREDICTABLE"));
7288 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7291 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7292 mark_feature_used (&arm_ext_fp16
);
7295 /* If VAL can be encoded in the immediate field of an ARM instruction,
7296 return the encoded form. Otherwise, return FAIL. */
7299 encode_arm_immediate (unsigned int val
)
7306 for (i
= 2; i
< 32; i
+= 2)
7307 if ((a
= rotate_left (val
, i
)) <= 0xff)
7308 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7313 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7314 return the encoded form. Otherwise, return FAIL. */
7316 encode_thumb32_immediate (unsigned int val
)
7323 for (i
= 1; i
<= 24; i
++)
7326 if ((val
& ~(0xff << i
)) == 0)
7327 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7331 if (val
== ((a
<< 16) | a
))
7333 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7337 if (val
== ((a
<< 16) | a
))
7338 return 0x200 | (a
>> 8);
7342 /* Encode a VFP SP or DP register number into inst.instruction. */
7345 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7347 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7350 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7353 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7356 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7361 first_error (_("D register out of range for selected VFP version"));
7369 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7373 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7377 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7381 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7385 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7389 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7397 /* Encode a <shift> in an ARM-format instruction. The immediate,
7398 if any, is handled by md_apply_fix. */
7400 encode_arm_shift (int i
)
7402 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7403 inst
.instruction
|= SHIFT_ROR
<< 5;
7406 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7407 if (inst
.operands
[i
].immisreg
)
7409 inst
.instruction
|= SHIFT_BY_REG
;
7410 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7413 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7418 encode_arm_shifter_operand (int i
)
7420 if (inst
.operands
[i
].isreg
)
7422 inst
.instruction
|= inst
.operands
[i
].reg
;
7423 encode_arm_shift (i
);
7427 inst
.instruction
|= INST_IMMEDIATE
;
7428 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7429 inst
.instruction
|= inst
.operands
[i
].imm
;
7433 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7435 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7438 Generate an error if the operand is not a register. */
7439 constraint (!inst
.operands
[i
].isreg
,
7440 _("Instruction does not support =N addresses"));
7442 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7444 if (inst
.operands
[i
].preind
)
7448 inst
.error
= _("instruction does not accept preindexed addressing");
7451 inst
.instruction
|= PRE_INDEX
;
7452 if (inst
.operands
[i
].writeback
)
7453 inst
.instruction
|= WRITE_BACK
;
7456 else if (inst
.operands
[i
].postind
)
7458 gas_assert (inst
.operands
[i
].writeback
);
7460 inst
.instruction
|= WRITE_BACK
;
7462 else /* unindexed - only for coprocessor */
7464 inst
.error
= _("instruction does not accept unindexed addressing");
7468 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7469 && (((inst
.instruction
& 0x000f0000) >> 16)
7470 == ((inst
.instruction
& 0x0000f000) >> 12)))
7471 as_warn ((inst
.instruction
& LOAD_BIT
)
7472 ? _("destination register same as write-back base")
7473 : _("source register same as write-back base"));
7476 /* inst.operands[i] was set up by parse_address. Encode it into an
7477 ARM-format mode 2 load or store instruction. If is_t is true,
7478 reject forms that cannot be used with a T instruction (i.e. not
7481 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7483 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7485 encode_arm_addr_mode_common (i
, is_t
);
7487 if (inst
.operands
[i
].immisreg
)
7489 constraint ((inst
.operands
[i
].imm
== REG_PC
7490 || (is_pc
&& inst
.operands
[i
].writeback
)),
7492 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7493 inst
.instruction
|= inst
.operands
[i
].imm
;
7494 if (!inst
.operands
[i
].negative
)
7495 inst
.instruction
|= INDEX_UP
;
7496 if (inst
.operands
[i
].shifted
)
7498 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7499 inst
.instruction
|= SHIFT_ROR
<< 5;
7502 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7503 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7507 else /* immediate offset in inst.reloc */
7509 if (is_pc
&& !inst
.reloc
.pc_rel
)
7511 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7513 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7514 cannot use PC in addressing.
7515 PC cannot be used in writeback addressing, either. */
7516 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7519 /* Use of PC in str is deprecated for ARMv7. */
7520 if (warn_on_deprecated
7522 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7523 as_tsktsk (_("use of PC in this instruction is deprecated"));
7526 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7528 /* Prefer + for zero encoded value. */
7529 if (!inst
.operands
[i
].negative
)
7530 inst
.instruction
|= INDEX_UP
;
7531 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7536 /* inst.operands[i] was set up by parse_address. Encode it into an
7537 ARM-format mode 3 load or store instruction. Reject forms that
7538 cannot be used with such instructions. If is_t is true, reject
7539 forms that cannot be used with a T instruction (i.e. not
7542 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7544 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7546 inst
.error
= _("instruction does not accept scaled register index");
7550 encode_arm_addr_mode_common (i
, is_t
);
7552 if (inst
.operands
[i
].immisreg
)
7554 constraint ((inst
.operands
[i
].imm
== REG_PC
7555 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7557 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7559 inst
.instruction
|= inst
.operands
[i
].imm
;
7560 if (!inst
.operands
[i
].negative
)
7561 inst
.instruction
|= INDEX_UP
;
7563 else /* immediate offset in inst.reloc */
7565 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7566 && inst
.operands
[i
].writeback
),
7568 inst
.instruction
|= HWOFFSET_IMM
;
7569 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7571 /* Prefer + for zero encoded value. */
7572 if (!inst
.operands
[i
].negative
)
7573 inst
.instruction
|= INDEX_UP
;
7575 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7580 /* Write immediate bits [7:0] to the following locations:
7582 |28/24|23 19|18 16|15 4|3 0|
7583 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7585 This function is used by VMOV/VMVN/VORR/VBIC. */
7588 neon_write_immbits (unsigned immbits
)
7590 inst
.instruction
|= immbits
& 0xf;
7591 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7592 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7595 /* Invert low-order SIZE bits of XHI:XLO. */
7598 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7600 unsigned immlo
= xlo
? *xlo
: 0;
7601 unsigned immhi
= xhi
? *xhi
: 0;
7606 immlo
= (~immlo
) & 0xff;
7610 immlo
= (~immlo
) & 0xffff;
7614 immhi
= (~immhi
) & 0xffffffff;
7618 immlo
= (~immlo
) & 0xffffffff;
7632 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7636 neon_bits_same_in_bytes (unsigned imm
)
7638 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7639 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7640 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7641 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7644 /* For immediate of above form, return 0bABCD. */
7647 neon_squash_bits (unsigned imm
)
7649 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7650 | ((imm
& 0x01000000) >> 21);
7653 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7656 neon_qfloat_bits (unsigned imm
)
7658 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7661 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7662 the instruction. *OP is passed as the initial value of the op field, and
7663 may be set to a different value depending on the constant (i.e.
7664 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7665 MVN). If the immediate looks like a repeated pattern then also
7666 try smaller element sizes. */
7669 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7670 unsigned *immbits
, int *op
, int size
,
7671 enum neon_el_type type
)
7673 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7675 if (type
== NT_float
&& !float_p
)
7678 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7680 if (size
!= 32 || *op
== 1)
7682 *immbits
= neon_qfloat_bits (immlo
);
7688 if (neon_bits_same_in_bytes (immhi
)
7689 && neon_bits_same_in_bytes (immlo
))
7693 *immbits
= (neon_squash_bits (immhi
) << 4)
7694 | neon_squash_bits (immlo
);
7705 if (immlo
== (immlo
& 0x000000ff))
7710 else if (immlo
== (immlo
& 0x0000ff00))
7712 *immbits
= immlo
>> 8;
7715 else if (immlo
== (immlo
& 0x00ff0000))
7717 *immbits
= immlo
>> 16;
7720 else if (immlo
== (immlo
& 0xff000000))
7722 *immbits
= immlo
>> 24;
7725 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7727 *immbits
= (immlo
>> 8) & 0xff;
7730 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7732 *immbits
= (immlo
>> 16) & 0xff;
7736 if ((immlo
& 0xffff) != (immlo
>> 16))
7743 if (immlo
== (immlo
& 0x000000ff))
7748 else if (immlo
== (immlo
& 0x0000ff00))
7750 *immbits
= immlo
>> 8;
7754 if ((immlo
& 0xff) != (immlo
>> 8))
7759 if (immlo
== (immlo
& 0x000000ff))
7761 /* Don't allow MVN with 8-bit immediate. */
7771 #if defined BFD_HOST_64_BIT
7772 /* Returns TRUE if double precision value V may be cast
7773 to single precision without loss of accuracy. */
7776 is_double_a_single (bfd_int64_t v
)
7778 int exp
= (int)((v
>> 52) & 0x7FF);
7779 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7781 return (exp
== 0 || exp
== 0x7FF
7782 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7783 && (mantissa
& 0x1FFFFFFFl
) == 0;
7786 /* Returns a double precision value casted to single precision
7787 (ignoring the least significant bits in exponent and mantissa). */
7790 double_to_single (bfd_int64_t v
)
7792 int sign
= (int) ((v
>> 63) & 1l);
7793 int exp
= (int) ((v
>> 52) & 0x7FF);
7794 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7800 exp
= exp
- 1023 + 127;
7809 /* No denormalized numbers. */
7815 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7817 #endif /* BFD_HOST_64_BIT */
7826 static void do_vfp_nsyn_opcode (const char *);
7828 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7829 Determine whether it can be performed with a move instruction; if
7830 it can, convert inst.instruction to that move instruction and
7831 return TRUE; if it can't, convert inst.instruction to a literal-pool
7832 load and return FALSE. If this is not a valid thing to do in the
7833 current context, set inst.error and return TRUE.
7835 inst.operands[i] describes the destination register. */
7838 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7841 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7842 bfd_boolean arm_p
= (t
== CONST_ARM
);
7845 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7849 if ((inst
.instruction
& tbit
) == 0)
7851 inst
.error
= _("invalid pseudo operation");
7855 if (inst
.reloc
.exp
.X_op
!= O_constant
7856 && inst
.reloc
.exp
.X_op
!= O_symbol
7857 && inst
.reloc
.exp
.X_op
!= O_big
)
7859 inst
.error
= _("constant expression expected");
7863 if (inst
.reloc
.exp
.X_op
== O_constant
7864 || inst
.reloc
.exp
.X_op
== O_big
)
7866 #if defined BFD_HOST_64_BIT
7871 if (inst
.reloc
.exp
.X_op
== O_big
)
7873 LITTLENUM_TYPE w
[X_PRECISION
];
7876 if (inst
.reloc
.exp
.X_add_number
== -1)
7878 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7880 /* FIXME: Should we check words w[2..5] ? */
7885 #if defined BFD_HOST_64_BIT
7887 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7888 << LITTLENUM_NUMBER_OF_BITS
)
7889 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7890 << LITTLENUM_NUMBER_OF_BITS
)
7891 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7892 << LITTLENUM_NUMBER_OF_BITS
)
7893 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7895 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7896 | (l
[0] & LITTLENUM_MASK
);
7900 v
= inst
.reloc
.exp
.X_add_number
;
7902 if (!inst
.operands
[i
].issingle
)
7906 /* This can be encoded only for a low register. */
7907 if ((v
& ~0xFF) == 0 && (inst
.operands
[i
].reg
< 8))
7909 /* This can be done with a mov(1) instruction. */
7910 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7911 inst
.instruction
|= v
;
7915 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
7916 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7918 /* Check if on thumb2 it can be done with a mov.w, mvn or
7919 movw instruction. */
7920 unsigned int newimm
;
7921 bfd_boolean isNegated
;
7923 newimm
= encode_thumb32_immediate (v
);
7924 if (newimm
!= (unsigned int) FAIL
)
7928 newimm
= encode_thumb32_immediate (~v
);
7929 if (newimm
!= (unsigned int) FAIL
)
7933 /* The number can be loaded with a mov.w or mvn
7935 if (newimm
!= (unsigned int) FAIL
7936 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
7938 inst
.instruction
= (0xf04f0000 /* MOV.W. */
7939 | (inst
.operands
[i
].reg
<< 8));
7940 /* Change to MOVN. */
7941 inst
.instruction
|= (isNegated
? 0x200000 : 0);
7942 inst
.instruction
|= (newimm
& 0x800) << 15;
7943 inst
.instruction
|= (newimm
& 0x700) << 4;
7944 inst
.instruction
|= (newimm
& 0x0ff);
7947 /* The number can be loaded with a movw instruction. */
7948 else if ((v
& ~0xFFFF) == 0
7949 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7951 int imm
= v
& 0xFFFF;
7953 inst
.instruction
= 0xf2400000; /* MOVW. */
7954 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
7955 inst
.instruction
|= (imm
& 0xf000) << 4;
7956 inst
.instruction
|= (imm
& 0x0800) << 15;
7957 inst
.instruction
|= (imm
& 0x0700) << 4;
7958 inst
.instruction
|= (imm
& 0x00ff);
7965 int value
= encode_arm_immediate (v
);
7969 /* This can be done with a mov instruction. */
7970 inst
.instruction
&= LITERAL_MASK
;
7971 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7972 inst
.instruction
|= value
& 0xfff;
7976 value
= encode_arm_immediate (~ v
);
7979 /* This can be done with a mvn instruction. */
7980 inst
.instruction
&= LITERAL_MASK
;
7981 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7982 inst
.instruction
|= value
& 0xfff;
7986 else if (t
== CONST_VEC
)
7989 unsigned immbits
= 0;
7990 unsigned immlo
= inst
.operands
[1].imm
;
7991 unsigned immhi
= inst
.operands
[1].regisimm
7992 ? inst
.operands
[1].reg
7993 : inst
.reloc
.exp
.X_unsigned
7995 : ((bfd_int64_t
)((int) immlo
)) >> 32;
7996 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7997 &op
, 64, NT_invtype
);
8001 neon_invert_size (&immlo
, &immhi
, 64);
8003 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8004 &op
, 64, NT_invtype
);
8009 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8015 /* Fill other bits in vmov encoding for both thumb and arm. */
8017 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8019 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8020 neon_write_immbits (immbits
);
8028 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8029 if (inst
.operands
[i
].issingle
8030 && is_quarter_float (inst
.operands
[1].imm
)
8031 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8033 inst
.operands
[1].imm
=
8034 neon_qfloat_bits (v
);
8035 do_vfp_nsyn_opcode ("fconsts");
8039 /* If our host does not support a 64-bit type then we cannot perform
8040 the following optimization. This mean that there will be a
8041 discrepancy between the output produced by an assembler built for
8042 a 32-bit-only host and the output produced from a 64-bit host, but
8043 this cannot be helped. */
8044 #if defined BFD_HOST_64_BIT
8045 else if (!inst
.operands
[1].issingle
8046 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8048 if (is_double_a_single (v
)
8049 && is_quarter_float (double_to_single (v
)))
8051 inst
.operands
[1].imm
=
8052 neon_qfloat_bits (double_to_single (v
));
8053 do_vfp_nsyn_opcode ("fconstd");
8061 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8062 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8065 inst
.operands
[1].reg
= REG_PC
;
8066 inst
.operands
[1].isreg
= 1;
8067 inst
.operands
[1].preind
= 1;
8068 inst
.reloc
.pc_rel
= 1;
8069 inst
.reloc
.type
= (thumb_p
8070 ? BFD_RELOC_ARM_THUMB_OFFSET
8072 ? BFD_RELOC_ARM_HWLITERAL
8073 : BFD_RELOC_ARM_LITERAL
));
8077 /* inst.operands[i] was set up by parse_address. Encode it into an
8078 ARM-format instruction. Reject all forms which cannot be encoded
8079 into a coprocessor load/store instruction. If wb_ok is false,
8080 reject use of writeback; if unind_ok is false, reject use of
8081 unindexed addressing. If reloc_override is not 0, use it instead
8082 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8083 (in which case it is preserved). */
8086 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8088 if (!inst
.operands
[i
].isreg
)
8091 if (! inst
.operands
[0].isvec
)
8093 inst
.error
= _("invalid co-processor operand");
8096 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8100 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8102 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8104 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8106 gas_assert (!inst
.operands
[i
].writeback
);
8109 inst
.error
= _("instruction does not support unindexed addressing");
8112 inst
.instruction
|= inst
.operands
[i
].imm
;
8113 inst
.instruction
|= INDEX_UP
;
8117 if (inst
.operands
[i
].preind
)
8118 inst
.instruction
|= PRE_INDEX
;
8120 if (inst
.operands
[i
].writeback
)
8122 if (inst
.operands
[i
].reg
== REG_PC
)
8124 inst
.error
= _("pc may not be used with write-back");
8129 inst
.error
= _("instruction does not support writeback");
8132 inst
.instruction
|= WRITE_BACK
;
8136 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8137 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8138 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8139 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8142 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8144 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8147 /* Prefer + for zero encoded value. */
8148 if (!inst
.operands
[i
].negative
)
8149 inst
.instruction
|= INDEX_UP
;
8154 /* Functions for instruction encoding, sorted by sub-architecture.
8155 First some generics; their names are taken from the conventional
8156 bit positions for register arguments in ARM format instructions. */
8166 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8172 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8173 inst
.instruction
|= inst
.operands
[1].reg
;
8179 inst
.instruction
|= inst
.operands
[0].reg
;
8180 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8186 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8187 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8193 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8194 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8200 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8201 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8205 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8207 if (ARM_CPU_IS_ANY (cpu_variant
))
8209 as_tsktsk ("%s", msg
);
8212 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8224 unsigned Rn
= inst
.operands
[2].reg
;
8225 /* Enforce restrictions on SWP instruction. */
8226 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8228 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8229 _("Rn must not overlap other operands"));
8231 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8233 if (!check_obsolete (&arm_ext_v8
,
8234 _("swp{b} use is obsoleted for ARMv8 and later"))
8235 && warn_on_deprecated
8236 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8237 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8240 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8241 inst
.instruction
|= inst
.operands
[1].reg
;
8242 inst
.instruction
|= Rn
<< 16;
8248 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8249 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8250 inst
.instruction
|= inst
.operands
[2].reg
;
8256 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8257 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8258 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8259 || inst
.reloc
.exp
.X_add_number
!= 0),
8261 inst
.instruction
|= inst
.operands
[0].reg
;
8262 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8263 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8269 inst
.instruction
|= inst
.operands
[0].imm
;
8275 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8276 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8279 /* ARM instructions, in alphabetical order by function name (except
8280 that wrapper functions appear immediately after the function they
8283 /* This is a pseudo-op of the form "adr rd, label" to be converted
8284 into a relative address of the form "add rd, pc, #label-.-8". */
8289 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8291 /* Frag hacking will turn this into a sub instruction if the offset turns
8292 out to be negative. */
8293 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8294 inst
.reloc
.pc_rel
= 1;
8295 inst
.reloc
.exp
.X_add_number
-= 8;
8298 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8299 into a relative address of the form:
8300 add rd, pc, #low(label-.-8)"
8301 add rd, rd, #high(label-.-8)" */
8306 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8308 /* Frag hacking will turn this into a sub instruction if the offset turns
8309 out to be negative. */
8310 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8311 inst
.reloc
.pc_rel
= 1;
8312 inst
.size
= INSN_SIZE
* 2;
8313 inst
.reloc
.exp
.X_add_number
-= 8;
8319 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8320 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8322 if (!inst
.operands
[1].present
)
8323 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8324 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8325 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8326 encode_arm_shifter_operand (2);
8332 if (inst
.operands
[0].present
)
8333 inst
.instruction
|= inst
.operands
[0].imm
;
8335 inst
.instruction
|= 0xf;
8341 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8342 constraint (msb
> 32, _("bit-field extends past end of register"));
8343 /* The instruction encoding stores the LSB and MSB,
8344 not the LSB and width. */
8345 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8346 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8347 inst
.instruction
|= (msb
- 1) << 16;
8355 /* #0 in second position is alternative syntax for bfc, which is
8356 the same instruction but with REG_PC in the Rm field. */
8357 if (!inst
.operands
[1].isreg
)
8358 inst
.operands
[1].reg
= REG_PC
;
8360 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8361 constraint (msb
> 32, _("bit-field extends past end of register"));
8362 /* The instruction encoding stores the LSB and MSB,
8363 not the LSB and width. */
8364 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8365 inst
.instruction
|= inst
.operands
[1].reg
;
8366 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8367 inst
.instruction
|= (msb
- 1) << 16;
8373 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8374 _("bit-field extends past end of register"));
8375 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8376 inst
.instruction
|= inst
.operands
[1].reg
;
8377 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8378 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8381 /* ARM V5 breakpoint instruction (argument parse)
8382 BKPT <16 bit unsigned immediate>
8383 Instruction is not conditional.
8384 The bit pattern given in insns[] has the COND_ALWAYS condition,
8385 and it is an error if the caller tried to override that. */
8390 /* Top 12 of 16 bits to bits 19:8. */
8391 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8393 /* Bottom 4 of 16 bits to bits 3:0. */
8394 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8398 encode_branch (int default_reloc
)
8400 if (inst
.operands
[0].hasreloc
)
8402 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8403 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8404 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8405 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8406 ? BFD_RELOC_ARM_PLT32
8407 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8410 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8411 inst
.reloc
.pc_rel
= 1;
8418 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8419 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8422 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8429 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8431 if (inst
.cond
== COND_ALWAYS
)
8432 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8434 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8438 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8441 /* ARM V5 branch-link-exchange instruction (argument parse)
8442 BLX <target_addr> ie BLX(1)
8443 BLX{<condition>} <Rm> ie BLX(2)
8444 Unfortunately, there are two different opcodes for this mnemonic.
8445 So, the insns[].value is not used, and the code here zaps values
8446 into inst.instruction.
8447 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8452 if (inst
.operands
[0].isreg
)
8454 /* Arg is a register; the opcode provided by insns[] is correct.
8455 It is not illegal to do "blx pc", just useless. */
8456 if (inst
.operands
[0].reg
== REG_PC
)
8457 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8459 inst
.instruction
|= inst
.operands
[0].reg
;
8463 /* Arg is an address; this instruction cannot be executed
8464 conditionally, and the opcode must be adjusted.
8465 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8466 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8467 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8468 inst
.instruction
= 0xfa000000;
8469 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8476 bfd_boolean want_reloc
;
8478 if (inst
.operands
[0].reg
== REG_PC
)
8479 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8481 inst
.instruction
|= inst
.operands
[0].reg
;
8482 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8483 it is for ARMv4t or earlier. */
8484 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8485 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8489 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8494 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8498 /* ARM v5TEJ. Jump to Jazelle code. */
8503 if (inst
.operands
[0].reg
== REG_PC
)
8504 as_tsktsk (_("use of r15 in bxj is not really useful"));
8506 inst
.instruction
|= inst
.operands
[0].reg
;
8509 /* Co-processor data operation:
8510 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8511 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8515 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8516 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8517 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8518 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8519 inst
.instruction
|= inst
.operands
[4].reg
;
8520 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8526 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8527 encode_arm_shifter_operand (1);
8530 /* Transfer between coprocessor and ARM registers.
8531 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8536 No special properties. */
8538 struct deprecated_coproc_regs_s
8545 arm_feature_set deprecated
;
8546 arm_feature_set obsoleted
;
8547 const char *dep_msg
;
8548 const char *obs_msg
;
8551 #define DEPR_ACCESS_V8 \
8552 N_("This coprocessor register access is deprecated in ARMv8")
8554 /* Table of all deprecated coprocessor registers. */
8555 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8557 {15, 0, 7, 10, 5, /* CP15DMB. */
8558 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8559 DEPR_ACCESS_V8
, NULL
},
8560 {15, 0, 7, 10, 4, /* CP15DSB. */
8561 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8562 DEPR_ACCESS_V8
, NULL
},
8563 {15, 0, 7, 5, 4, /* CP15ISB. */
8564 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8565 DEPR_ACCESS_V8
, NULL
},
8566 {14, 6, 1, 0, 0, /* TEEHBR. */
8567 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8568 DEPR_ACCESS_V8
, NULL
},
8569 {14, 6, 0, 0, 0, /* TEECR. */
8570 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8571 DEPR_ACCESS_V8
, NULL
},
8574 #undef DEPR_ACCESS_V8
8576 static const size_t deprecated_coproc_reg_count
=
8577 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8585 Rd
= inst
.operands
[2].reg
;
8588 if (inst
.instruction
== 0xee000010
8589 || inst
.instruction
== 0xfe000010)
8591 reject_bad_reg (Rd
);
8594 constraint (Rd
== REG_SP
, BAD_SP
);
8599 if (inst
.instruction
== 0xe000010)
8600 constraint (Rd
== REG_PC
, BAD_PC
);
8603 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8605 const struct deprecated_coproc_regs_s
*r
=
8606 deprecated_coproc_regs
+ i
;
8608 if (inst
.operands
[0].reg
== r
->cp
8609 && inst
.operands
[1].imm
== r
->opc1
8610 && inst
.operands
[3].reg
== r
->crn
8611 && inst
.operands
[4].reg
== r
->crm
8612 && inst
.operands
[5].imm
== r
->opc2
)
8614 if (! ARM_CPU_IS_ANY (cpu_variant
)
8615 && warn_on_deprecated
8616 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8617 as_tsktsk ("%s", r
->dep_msg
);
8621 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8622 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8623 inst
.instruction
|= Rd
<< 12;
8624 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8625 inst
.instruction
|= inst
.operands
[4].reg
;
8626 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8629 /* Transfer between coprocessor register and pair of ARM registers.
8630 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8635 Two XScale instructions are special cases of these:
8637 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8638 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8640 Result unpredictable if Rd or Rn is R15. */
8647 Rd
= inst
.operands
[2].reg
;
8648 Rn
= inst
.operands
[3].reg
;
8652 reject_bad_reg (Rd
);
8653 reject_bad_reg (Rn
);
8657 constraint (Rd
== REG_PC
, BAD_PC
);
8658 constraint (Rn
== REG_PC
, BAD_PC
);
8661 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8662 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8663 inst
.instruction
|= Rd
<< 12;
8664 inst
.instruction
|= Rn
<< 16;
8665 inst
.instruction
|= inst
.operands
[4].reg
;
8671 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8672 if (inst
.operands
[1].present
)
8674 inst
.instruction
|= CPSI_MMOD
;
8675 inst
.instruction
|= inst
.operands
[1].imm
;
8682 inst
.instruction
|= inst
.operands
[0].imm
;
8688 unsigned Rd
, Rn
, Rm
;
8690 Rd
= inst
.operands
[0].reg
;
8691 Rn
= (inst
.operands
[1].present
8692 ? inst
.operands
[1].reg
: Rd
);
8693 Rm
= inst
.operands
[2].reg
;
8695 constraint ((Rd
== REG_PC
), BAD_PC
);
8696 constraint ((Rn
== REG_PC
), BAD_PC
);
8697 constraint ((Rm
== REG_PC
), BAD_PC
);
8699 inst
.instruction
|= Rd
<< 16;
8700 inst
.instruction
|= Rn
<< 0;
8701 inst
.instruction
|= Rm
<< 8;
8707 /* There is no IT instruction in ARM mode. We
8708 process it to do the validation as if in
8709 thumb mode, just in case the code gets
8710 assembled for thumb using the unified syntax. */
8715 set_it_insn_type (IT_INSN
);
8716 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8717 now_it
.cc
= inst
.operands
[0].imm
;
8721 /* If there is only one register in the register list,
8722 then return its register number. Otherwise return -1. */
8724 only_one_reg_in_list (int range
)
8726 int i
= ffs (range
) - 1;
8727 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8731 encode_ldmstm(int from_push_pop_mnem
)
8733 int base_reg
= inst
.operands
[0].reg
;
8734 int range
= inst
.operands
[1].imm
;
8737 inst
.instruction
|= base_reg
<< 16;
8738 inst
.instruction
|= range
;
8740 if (inst
.operands
[1].writeback
)
8741 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8743 if (inst
.operands
[0].writeback
)
8745 inst
.instruction
|= WRITE_BACK
;
8746 /* Check for unpredictable uses of writeback. */
8747 if (inst
.instruction
& LOAD_BIT
)
8749 /* Not allowed in LDM type 2. */
8750 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8751 && ((range
& (1 << REG_PC
)) == 0))
8752 as_warn (_("writeback of base register is UNPREDICTABLE"));
8753 /* Only allowed if base reg not in list for other types. */
8754 else if (range
& (1 << base_reg
))
8755 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8759 /* Not allowed for type 2. */
8760 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8761 as_warn (_("writeback of base register is UNPREDICTABLE"));
8762 /* Only allowed if base reg not in list, or first in list. */
8763 else if ((range
& (1 << base_reg
))
8764 && (range
& ((1 << base_reg
) - 1)))
8765 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8769 /* If PUSH/POP has only one register, then use the A2 encoding. */
8770 one_reg
= only_one_reg_in_list (range
);
8771 if (from_push_pop_mnem
&& one_reg
>= 0)
8773 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8775 inst
.instruction
&= A_COND_MASK
;
8776 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8777 inst
.instruction
|= one_reg
<< 12;
8784 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8787 /* ARMv5TE load-consecutive (argument parse)
8796 constraint (inst
.operands
[0].reg
% 2 != 0,
8797 _("first transfer register must be even"));
8798 constraint (inst
.operands
[1].present
8799 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8800 _("can only transfer two consecutive registers"));
8801 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8802 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8804 if (!inst
.operands
[1].present
)
8805 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8807 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8808 register and the first register written; we have to diagnose
8809 overlap between the base and the second register written here. */
8811 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8812 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8813 as_warn (_("base register written back, and overlaps "
8814 "second transfer register"));
8816 if (!(inst
.instruction
& V4_STR_BIT
))
8818 /* For an index-register load, the index register must not overlap the
8819 destination (even if not write-back). */
8820 if (inst
.operands
[2].immisreg
8821 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8822 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8823 as_warn (_("index register overlaps transfer register"));
8825 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8826 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8832 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8833 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8834 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8835 || inst
.operands
[1].negative
8836 /* This can arise if the programmer has written
8838 or if they have mistakenly used a register name as the last
8841 It is very difficult to distinguish between these two cases
8842 because "rX" might actually be a label. ie the register
8843 name has been occluded by a symbol of the same name. So we
8844 just generate a general 'bad addressing mode' type error
8845 message and leave it up to the programmer to discover the
8846 true cause and fix their mistake. */
8847 || (inst
.operands
[1].reg
== REG_PC
),
8850 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8851 || inst
.reloc
.exp
.X_add_number
!= 0,
8852 _("offset must be zero in ARM encoding"));
8854 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8856 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8857 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8858 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8864 constraint (inst
.operands
[0].reg
% 2 != 0,
8865 _("even register required"));
8866 constraint (inst
.operands
[1].present
8867 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8868 _("can only load two consecutive registers"));
8869 /* If op 1 were present and equal to PC, this function wouldn't
8870 have been called in the first place. */
8871 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8873 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8874 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8877 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8878 which is not a multiple of four is UNPREDICTABLE. */
8880 check_ldr_r15_aligned (void)
8882 constraint (!(inst
.operands
[1].immisreg
)
8883 && (inst
.operands
[0].reg
== REG_PC
8884 && inst
.operands
[1].reg
== REG_PC
8885 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8886 _("ldr to register 15 must be 4-byte alligned"));
8892 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8893 if (!inst
.operands
[1].isreg
)
8894 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8896 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8897 check_ldr_r15_aligned ();
8903 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8905 if (inst
.operands
[1].preind
)
8907 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8908 || inst
.reloc
.exp
.X_add_number
!= 0,
8909 _("this instruction requires a post-indexed address"));
8911 inst
.operands
[1].preind
= 0;
8912 inst
.operands
[1].postind
= 1;
8913 inst
.operands
[1].writeback
= 1;
8915 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8916 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8919 /* Halfword and signed-byte load/store operations. */
8924 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8925 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8926 if (!inst
.operands
[1].isreg
)
8927 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8929 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8935 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8937 if (inst
.operands
[1].preind
)
8939 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8940 || inst
.reloc
.exp
.X_add_number
!= 0,
8941 _("this instruction requires a post-indexed address"));
8943 inst
.operands
[1].preind
= 0;
8944 inst
.operands
[1].postind
= 1;
8945 inst
.operands
[1].writeback
= 1;
8947 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8948 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8951 /* Co-processor register load/store.
8952 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8956 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8957 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8958 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8964 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8965 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8966 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8967 && !(inst
.instruction
& 0x00400000))
8968 as_tsktsk (_("Rd and Rm should be different in mla"));
8970 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8971 inst
.instruction
|= inst
.operands
[1].reg
;
8972 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8973 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8979 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8980 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8982 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8983 encode_arm_shifter_operand (1);
8986 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8993 top
= (inst
.instruction
& 0x00400000) != 0;
8994 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
8995 _(":lower16: not allowed this instruction"));
8996 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
8997 _(":upper16: not allowed instruction"));
8998 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8999 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9001 imm
= inst
.reloc
.exp
.X_add_number
;
9002 /* The value is in two pieces: 0:11, 16:19. */
9003 inst
.instruction
|= (imm
& 0x00000fff);
9004 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9009 do_vfp_nsyn_mrs (void)
9011 if (inst
.operands
[0].isvec
)
9013 if (inst
.operands
[1].reg
!= 1)
9014 first_error (_("operand 1 must be FPSCR"));
9015 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9016 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9017 do_vfp_nsyn_opcode ("fmstat");
9019 else if (inst
.operands
[1].isvec
)
9020 do_vfp_nsyn_opcode ("fmrx");
9028 do_vfp_nsyn_msr (void)
9030 if (inst
.operands
[0].isvec
)
9031 do_vfp_nsyn_opcode ("fmxr");
9041 unsigned Rt
= inst
.operands
[0].reg
;
9043 if (thumb_mode
&& Rt
== REG_SP
)
9045 inst
.error
= BAD_SP
;
9049 /* APSR_ sets isvec. All other refs to PC are illegal. */
9050 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9052 inst
.error
= BAD_PC
;
9056 /* If we get through parsing the register name, we just insert the number
9057 generated into the instruction without further validation. */
9058 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9059 inst
.instruction
|= (Rt
<< 12);
9065 unsigned Rt
= inst
.operands
[1].reg
;
9068 reject_bad_reg (Rt
);
9069 else if (Rt
== REG_PC
)
9071 inst
.error
= BAD_PC
;
9075 /* If we get through parsing the register name, we just insert the number
9076 generated into the instruction without further validation. */
9077 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9078 inst
.instruction
|= (Rt
<< 12);
9086 if (do_vfp_nsyn_mrs () == SUCCESS
)
9089 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9090 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9092 if (inst
.operands
[1].isreg
)
9094 br
= inst
.operands
[1].reg
;
9095 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9096 as_bad (_("bad register for mrs"));
9100 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9101 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9103 _("'APSR', 'CPSR' or 'SPSR' expected"));
9104 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9107 inst
.instruction
|= br
;
9110 /* Two possible forms:
9111 "{C|S}PSR_<field>, Rm",
9112 "{C|S}PSR_f, #expression". */
9117 if (do_vfp_nsyn_msr () == SUCCESS
)
9120 inst
.instruction
|= inst
.operands
[0].imm
;
9121 if (inst
.operands
[1].isreg
)
9122 inst
.instruction
|= inst
.operands
[1].reg
;
9125 inst
.instruction
|= INST_IMMEDIATE
;
9126 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9127 inst
.reloc
.pc_rel
= 0;
9134 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9136 if (!inst
.operands
[2].present
)
9137 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9138 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9139 inst
.instruction
|= inst
.operands
[1].reg
;
9140 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9142 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9143 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9144 as_tsktsk (_("Rd and Rm should be different in mul"));
9147 /* Long Multiply Parser
9148 UMULL RdLo, RdHi, Rm, Rs
9149 SMULL RdLo, RdHi, Rm, Rs
9150 UMLAL RdLo, RdHi, Rm, Rs
9151 SMLAL RdLo, RdHi, Rm, Rs. */
9156 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9157 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9158 inst
.instruction
|= inst
.operands
[2].reg
;
9159 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9161 /* rdhi and rdlo must be different. */
9162 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9163 as_tsktsk (_("rdhi and rdlo must be different"));
9165 /* rdhi, rdlo and rm must all be different before armv6. */
9166 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9167 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9168 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9169 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9175 if (inst
.operands
[0].present
9176 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9178 /* Architectural NOP hints are CPSR sets with no bits selected. */
9179 inst
.instruction
&= 0xf0000000;
9180 inst
.instruction
|= 0x0320f000;
9181 if (inst
.operands
[0].present
)
9182 inst
.instruction
|= inst
.operands
[0].imm
;
9186 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9187 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9188 Condition defaults to COND_ALWAYS.
9189 Error if Rd, Rn or Rm are R15. */
9194 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9195 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9196 inst
.instruction
|= inst
.operands
[2].reg
;
9197 if (inst
.operands
[3].present
)
9198 encode_arm_shift (3);
9201 /* ARM V6 PKHTB (Argument Parse). */
9206 if (!inst
.operands
[3].present
)
9208 /* If the shift specifier is omitted, turn the instruction
9209 into pkhbt rd, rm, rn. */
9210 inst
.instruction
&= 0xfff00010;
9211 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9212 inst
.instruction
|= inst
.operands
[1].reg
;
9213 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9217 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9218 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9219 inst
.instruction
|= inst
.operands
[2].reg
;
9220 encode_arm_shift (3);
9224 /* ARMv5TE: Preload-Cache
9225 MP Extensions: Preload for write
9229 Syntactically, like LDR with B=1, W=0, L=1. */
9234 constraint (!inst
.operands
[0].isreg
,
9235 _("'[' expected after PLD mnemonic"));
9236 constraint (inst
.operands
[0].postind
,
9237 _("post-indexed expression used in preload instruction"));
9238 constraint (inst
.operands
[0].writeback
,
9239 _("writeback used in preload instruction"));
9240 constraint (!inst
.operands
[0].preind
,
9241 _("unindexed addressing used in preload instruction"));
9242 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9245 /* ARMv7: PLI <addr_mode> */
9249 constraint (!inst
.operands
[0].isreg
,
9250 _("'[' expected after PLI mnemonic"));
9251 constraint (inst
.operands
[0].postind
,
9252 _("post-indexed expression used in preload instruction"));
9253 constraint (inst
.operands
[0].writeback
,
9254 _("writeback used in preload instruction"));
9255 constraint (!inst
.operands
[0].preind
,
9256 _("unindexed addressing used in preload instruction"));
9257 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9258 inst
.instruction
&= ~PRE_INDEX
;
9264 constraint (inst
.operands
[0].writeback
,
9265 _("push/pop do not support {reglist}^"));
9266 inst
.operands
[1] = inst
.operands
[0];
9267 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9268 inst
.operands
[0].isreg
= 1;
9269 inst
.operands
[0].writeback
= 1;
9270 inst
.operands
[0].reg
= REG_SP
;
9271 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9274 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9275 word at the specified address and the following word
9277 Unconditionally executed.
9278 Error if Rn is R15. */
9283 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9284 if (inst
.operands
[0].writeback
)
9285 inst
.instruction
|= WRITE_BACK
;
9288 /* ARM V6 ssat (argument parse). */
9293 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9294 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9295 inst
.instruction
|= inst
.operands
[2].reg
;
9297 if (inst
.operands
[3].present
)
9298 encode_arm_shift (3);
9301 /* ARM V6 usat (argument parse). */
9306 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9307 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9308 inst
.instruction
|= inst
.operands
[2].reg
;
9310 if (inst
.operands
[3].present
)
9311 encode_arm_shift (3);
9314 /* ARM V6 ssat16 (argument parse). */
9319 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9320 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9321 inst
.instruction
|= inst
.operands
[2].reg
;
9327 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9328 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9329 inst
.instruction
|= inst
.operands
[2].reg
;
9332 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9333 preserving the other bits.
9335 setend <endian_specifier>, where <endian_specifier> is either
9341 if (warn_on_deprecated
9342 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9343 as_tsktsk (_("setend use is deprecated for ARMv8"));
9345 if (inst
.operands
[0].imm
)
9346 inst
.instruction
|= 0x200;
9352 unsigned int Rm
= (inst
.operands
[1].present
9353 ? inst
.operands
[1].reg
9354 : inst
.operands
[0].reg
);
9356 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9357 inst
.instruction
|= Rm
;
9358 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9360 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9361 inst
.instruction
|= SHIFT_BY_REG
;
9362 /* PR 12854: Error on extraneous shifts. */
9363 constraint (inst
.operands
[2].shifted
,
9364 _("extraneous shift as part of operand to shift insn"));
9367 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9373 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9374 inst
.reloc
.pc_rel
= 0;
9380 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9381 inst
.reloc
.pc_rel
= 0;
9387 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9388 inst
.reloc
.pc_rel
= 0;
9394 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9395 _("selected processor does not support SETPAN instruction"));
9397 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9403 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9404 _("selected processor does not support SETPAN instruction"));
9406 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9409 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9410 SMLAxy{cond} Rd,Rm,Rs,Rn
9411 SMLAWy{cond} Rd,Rm,Rs,Rn
9412 Error if any register is R15. */
9417 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9418 inst
.instruction
|= inst
.operands
[1].reg
;
9419 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9420 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9423 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9424 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9425 Error if any register is R15.
9426 Warning if Rdlo == Rdhi. */
9431 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9432 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9433 inst
.instruction
|= inst
.operands
[2].reg
;
9434 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9436 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9437 as_tsktsk (_("rdhi and rdlo must be different"));
9440 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9441 SMULxy{cond} Rd,Rm,Rs
9442 Error if any register is R15. */
9447 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9448 inst
.instruction
|= inst
.operands
[1].reg
;
9449 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9452 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9453 the same for both ARM and Thumb-2. */
9460 if (inst
.operands
[0].present
)
9462 reg
= inst
.operands
[0].reg
;
9463 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9468 inst
.instruction
|= reg
<< 16;
9469 inst
.instruction
|= inst
.operands
[1].imm
;
9470 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9471 inst
.instruction
|= WRITE_BACK
;
9474 /* ARM V6 strex (argument parse). */
9479 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9480 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9481 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9482 || inst
.operands
[2].negative
9483 /* See comment in do_ldrex(). */
9484 || (inst
.operands
[2].reg
== REG_PC
),
9487 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9488 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9490 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9491 || inst
.reloc
.exp
.X_add_number
!= 0,
9492 _("offset must be zero in ARM encoding"));
9494 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9495 inst
.instruction
|= inst
.operands
[1].reg
;
9496 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9497 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9503 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9504 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9505 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9506 || inst
.operands
[2].negative
,
9509 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9510 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9518 constraint (inst
.operands
[1].reg
% 2 != 0,
9519 _("even register required"));
9520 constraint (inst
.operands
[2].present
9521 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9522 _("can only store two consecutive registers"));
9523 /* If op 2 were present and equal to PC, this function wouldn't
9524 have been called in the first place. */
9525 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9527 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9528 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9529 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9532 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9533 inst
.instruction
|= inst
.operands
[1].reg
;
9534 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9541 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9542 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9550 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9551 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9556 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9557 extends it to 32-bits, and adds the result to a value in another
9558 register. You can specify a rotation by 0, 8, 16, or 24 bits
9559 before extracting the 16-bit value.
9560 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9561 Condition defaults to COND_ALWAYS.
9562 Error if any register uses R15. */
9567 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9568 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9569 inst
.instruction
|= inst
.operands
[2].reg
;
9570 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9575 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9576 Condition defaults to COND_ALWAYS.
9577 Error if any register uses R15. */
9582 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9583 inst
.instruction
|= inst
.operands
[1].reg
;
9584 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9587 /* VFP instructions. In a logical order: SP variant first, monad
9588 before dyad, arithmetic then move then load/store. */
9591 do_vfp_sp_monadic (void)
9593 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9594 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9598 do_vfp_sp_dyadic (void)
9600 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9601 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9602 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9606 do_vfp_sp_compare_z (void)
9608 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9612 do_vfp_dp_sp_cvt (void)
9614 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9615 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9619 do_vfp_sp_dp_cvt (void)
9621 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9622 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9626 do_vfp_reg_from_sp (void)
9628 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9629 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9633 do_vfp_reg2_from_sp2 (void)
9635 constraint (inst
.operands
[2].imm
!= 2,
9636 _("only two consecutive VFP SP registers allowed here"));
9637 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9638 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9639 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9643 do_vfp_sp_from_reg (void)
9645 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9646 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9650 do_vfp_sp2_from_reg2 (void)
9652 constraint (inst
.operands
[0].imm
!= 2,
9653 _("only two consecutive VFP SP registers allowed here"));
9654 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9655 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9656 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9660 do_vfp_sp_ldst (void)
9662 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9663 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9667 do_vfp_dp_ldst (void)
9669 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9670 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9675 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9677 if (inst
.operands
[0].writeback
)
9678 inst
.instruction
|= WRITE_BACK
;
9680 constraint (ldstm_type
!= VFP_LDSTMIA
,
9681 _("this addressing mode requires base-register writeback"));
9682 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9683 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9684 inst
.instruction
|= inst
.operands
[1].imm
;
9688 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9692 if (inst
.operands
[0].writeback
)
9693 inst
.instruction
|= WRITE_BACK
;
9695 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9696 _("this addressing mode requires base-register writeback"));
9698 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9699 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9701 count
= inst
.operands
[1].imm
<< 1;
9702 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9705 inst
.instruction
|= count
;
9709 do_vfp_sp_ldstmia (void)
9711 vfp_sp_ldstm (VFP_LDSTMIA
);
9715 do_vfp_sp_ldstmdb (void)
9717 vfp_sp_ldstm (VFP_LDSTMDB
);
9721 do_vfp_dp_ldstmia (void)
9723 vfp_dp_ldstm (VFP_LDSTMIA
);
9727 do_vfp_dp_ldstmdb (void)
9729 vfp_dp_ldstm (VFP_LDSTMDB
);
9733 do_vfp_xp_ldstmia (void)
9735 vfp_dp_ldstm (VFP_LDSTMIAX
);
9739 do_vfp_xp_ldstmdb (void)
9741 vfp_dp_ldstm (VFP_LDSTMDBX
);
9745 do_vfp_dp_rd_rm (void)
9747 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9748 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9752 do_vfp_dp_rn_rd (void)
9754 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9755 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9759 do_vfp_dp_rd_rn (void)
9761 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9762 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9766 do_vfp_dp_rd_rn_rm (void)
9768 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9769 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9770 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9776 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9780 do_vfp_dp_rm_rd_rn (void)
9782 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9783 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9784 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9787 /* VFPv3 instructions. */
9789 do_vfp_sp_const (void)
9791 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9792 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9793 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9797 do_vfp_dp_const (void)
9799 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9800 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9801 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9805 vfp_conv (int srcsize
)
9807 int immbits
= srcsize
- inst
.operands
[1].imm
;
9809 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9811 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9812 i.e. immbits must be in range 0 - 16. */
9813 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9816 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9818 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9819 i.e. immbits must be in range 0 - 31. */
9820 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9824 inst
.instruction
|= (immbits
& 1) << 5;
9825 inst
.instruction
|= (immbits
>> 1);
9829 do_vfp_sp_conv_16 (void)
9831 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9836 do_vfp_dp_conv_16 (void)
9838 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9843 do_vfp_sp_conv_32 (void)
9845 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9850 do_vfp_dp_conv_32 (void)
9852 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9856 /* FPA instructions. Also in a logical order. */
9861 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9862 inst
.instruction
|= inst
.operands
[1].reg
;
9866 do_fpa_ldmstm (void)
9868 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9869 switch (inst
.operands
[1].imm
)
9871 case 1: inst
.instruction
|= CP_T_X
; break;
9872 case 2: inst
.instruction
|= CP_T_Y
; break;
9873 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9878 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9880 /* The instruction specified "ea" or "fd", so we can only accept
9881 [Rn]{!}. The instruction does not really support stacking or
9882 unstacking, so we have to emulate these by setting appropriate
9883 bits and offsets. */
9884 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9885 || inst
.reloc
.exp
.X_add_number
!= 0,
9886 _("this instruction does not support indexing"));
9888 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9889 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9891 if (!(inst
.instruction
& INDEX_UP
))
9892 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9894 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9896 inst
.operands
[2].preind
= 0;
9897 inst
.operands
[2].postind
= 1;
9901 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9904 /* iWMMXt instructions: strictly in alphabetical order. */
9907 do_iwmmxt_tandorc (void)
9909 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9913 do_iwmmxt_textrc (void)
9915 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9916 inst
.instruction
|= inst
.operands
[1].imm
;
9920 do_iwmmxt_textrm (void)
9922 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9923 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9924 inst
.instruction
|= inst
.operands
[2].imm
;
9928 do_iwmmxt_tinsr (void)
9930 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9931 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9932 inst
.instruction
|= inst
.operands
[2].imm
;
9936 do_iwmmxt_tmia (void)
9938 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9939 inst
.instruction
|= inst
.operands
[1].reg
;
9940 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9944 do_iwmmxt_waligni (void)
9946 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9947 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9948 inst
.instruction
|= inst
.operands
[2].reg
;
9949 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9953 do_iwmmxt_wmerge (void)
9955 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9956 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9957 inst
.instruction
|= inst
.operands
[2].reg
;
9958 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9962 do_iwmmxt_wmov (void)
9964 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9965 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9966 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9967 inst
.instruction
|= inst
.operands
[1].reg
;
9971 do_iwmmxt_wldstbh (void)
9974 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9976 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
9978 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
9979 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
9983 do_iwmmxt_wldstw (void)
9985 /* RIWR_RIWC clears .isreg for a control register. */
9986 if (!inst
.operands
[0].isreg
)
9988 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9989 inst
.instruction
|= 0xf0000000;
9992 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9993 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9997 do_iwmmxt_wldstd (void)
9999 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10000 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10001 && inst
.operands
[1].immisreg
)
10003 inst
.instruction
&= ~0x1a000ff;
10004 inst
.instruction
|= (0xfU
<< 28);
10005 if (inst
.operands
[1].preind
)
10006 inst
.instruction
|= PRE_INDEX
;
10007 if (!inst
.operands
[1].negative
)
10008 inst
.instruction
|= INDEX_UP
;
10009 if (inst
.operands
[1].writeback
)
10010 inst
.instruction
|= WRITE_BACK
;
10011 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10012 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10013 inst
.instruction
|= inst
.operands
[1].imm
;
10016 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10020 do_iwmmxt_wshufh (void)
10022 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10023 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10024 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10025 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10029 do_iwmmxt_wzero (void)
10031 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10032 inst
.instruction
|= inst
.operands
[0].reg
;
10033 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10034 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10038 do_iwmmxt_wrwrwr_or_imm5 (void)
10040 if (inst
.operands
[2].isreg
)
10043 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10044 _("immediate operand requires iWMMXt2"));
10046 if (inst
.operands
[2].imm
== 0)
10048 switch ((inst
.instruction
>> 20) & 0xf)
10054 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10055 inst
.operands
[2].imm
= 16;
10056 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10062 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10063 inst
.operands
[2].imm
= 32;
10064 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10071 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10073 wrn
= (inst
.instruction
>> 16) & 0xf;
10074 inst
.instruction
&= 0xff0fff0f;
10075 inst
.instruction
|= wrn
;
10076 /* Bail out here; the instruction is now assembled. */
10081 /* Map 32 -> 0, etc. */
10082 inst
.operands
[2].imm
&= 0x1f;
10083 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10087 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10088 operations first, then control, shift, and load/store. */
10090 /* Insns like "foo X,Y,Z". */
10093 do_mav_triple (void)
10095 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10096 inst
.instruction
|= inst
.operands
[1].reg
;
10097 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10100 /* Insns like "foo W,X,Y,Z".
10101 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10106 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10107 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10108 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10109 inst
.instruction
|= inst
.operands
[3].reg
;
10112 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10114 do_mav_dspsc (void)
10116 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10119 /* Maverick shift immediate instructions.
10120 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10121 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10124 do_mav_shift (void)
10126 int imm
= inst
.operands
[2].imm
;
10128 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10129 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10131 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10132 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10133 Bit 4 should be 0. */
10134 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10136 inst
.instruction
|= imm
;
10139 /* XScale instructions. Also sorted arithmetic before move. */
10141 /* Xscale multiply-accumulate (argument parse)
10144 MIAxycc acc0,Rm,Rs. */
10149 inst
.instruction
|= inst
.operands
[1].reg
;
10150 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10153 /* Xscale move-accumulator-register (argument parse)
10155 MARcc acc0,RdLo,RdHi. */
10160 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10161 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10164 /* Xscale move-register-accumulator (argument parse)
10166 MRAcc RdLo,RdHi,acc0. */
10171 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10172 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10173 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10176 /* Encoding functions relevant only to Thumb. */
10178 /* inst.operands[i] is a shifted-register operand; encode
10179 it into inst.instruction in the format used by Thumb32. */
10182 encode_thumb32_shifted_operand (int i
)
10184 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10185 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10187 constraint (inst
.operands
[i
].immisreg
,
10188 _("shift by register not allowed in thumb mode"));
10189 inst
.instruction
|= inst
.operands
[i
].reg
;
10190 if (shift
== SHIFT_RRX
)
10191 inst
.instruction
|= SHIFT_ROR
<< 4;
10194 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10195 _("expression too complex"));
10197 constraint (value
> 32
10198 || (value
== 32 && (shift
== SHIFT_LSL
10199 || shift
== SHIFT_ROR
)),
10200 _("shift expression is too large"));
10204 else if (value
== 32)
10207 inst
.instruction
|= shift
<< 4;
10208 inst
.instruction
|= (value
& 0x1c) << 10;
10209 inst
.instruction
|= (value
& 0x03) << 6;
10214 /* inst.operands[i] was set up by parse_address. Encode it into a
10215 Thumb32 format load or store instruction. Reject forms that cannot
10216 be used with such instructions. If is_t is true, reject forms that
10217 cannot be used with a T instruction; if is_d is true, reject forms
10218 that cannot be used with a D instruction. If it is a store insn,
10219 reject PC in Rn. */
10222 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10224 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10226 constraint (!inst
.operands
[i
].isreg
,
10227 _("Instruction does not support =N addresses"));
10229 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10230 if (inst
.operands
[i
].immisreg
)
10232 constraint (is_pc
, BAD_PC_ADDRESSING
);
10233 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10234 constraint (inst
.operands
[i
].negative
,
10235 _("Thumb does not support negative register indexing"));
10236 constraint (inst
.operands
[i
].postind
,
10237 _("Thumb does not support register post-indexing"));
10238 constraint (inst
.operands
[i
].writeback
,
10239 _("Thumb does not support register indexing with writeback"));
10240 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10241 _("Thumb supports only LSL in shifted register indexing"));
10243 inst
.instruction
|= inst
.operands
[i
].imm
;
10244 if (inst
.operands
[i
].shifted
)
10246 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10247 _("expression too complex"));
10248 constraint (inst
.reloc
.exp
.X_add_number
< 0
10249 || inst
.reloc
.exp
.X_add_number
> 3,
10250 _("shift out of range"));
10251 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10253 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10255 else if (inst
.operands
[i
].preind
)
10257 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10258 constraint (is_t
&& inst
.operands
[i
].writeback
,
10259 _("cannot use writeback with this instruction"));
10260 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10261 BAD_PC_ADDRESSING
);
10265 inst
.instruction
|= 0x01000000;
10266 if (inst
.operands
[i
].writeback
)
10267 inst
.instruction
|= 0x00200000;
10271 inst
.instruction
|= 0x00000c00;
10272 if (inst
.operands
[i
].writeback
)
10273 inst
.instruction
|= 0x00000100;
10275 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10277 else if (inst
.operands
[i
].postind
)
10279 gas_assert (inst
.operands
[i
].writeback
);
10280 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10281 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10284 inst
.instruction
|= 0x00200000;
10286 inst
.instruction
|= 0x00000900;
10287 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10289 else /* unindexed - only for coprocessor */
10290 inst
.error
= _("instruction does not accept unindexed addressing");
10293 /* Table of Thumb instructions which exist in both 16- and 32-bit
10294 encodings (the latter only in post-V6T2 cores). The index is the
10295 value used in the insns table below. When there is more than one
10296 possible 16-bit encoding for the instruction, this table always
10298 Also contains several pseudo-instructions used during relaxation. */
10299 #define T16_32_TAB \
10300 X(_adc, 4140, eb400000), \
10301 X(_adcs, 4140, eb500000), \
10302 X(_add, 1c00, eb000000), \
10303 X(_adds, 1c00, eb100000), \
10304 X(_addi, 0000, f1000000), \
10305 X(_addis, 0000, f1100000), \
10306 X(_add_pc,000f, f20f0000), \
10307 X(_add_sp,000d, f10d0000), \
10308 X(_adr, 000f, f20f0000), \
10309 X(_and, 4000, ea000000), \
10310 X(_ands, 4000, ea100000), \
10311 X(_asr, 1000, fa40f000), \
10312 X(_asrs, 1000, fa50f000), \
10313 X(_b, e000, f000b000), \
10314 X(_bcond, d000, f0008000), \
10315 X(_bic, 4380, ea200000), \
10316 X(_bics, 4380, ea300000), \
10317 X(_cmn, 42c0, eb100f00), \
10318 X(_cmp, 2800, ebb00f00), \
10319 X(_cpsie, b660, f3af8400), \
10320 X(_cpsid, b670, f3af8600), \
10321 X(_cpy, 4600, ea4f0000), \
10322 X(_dec_sp,80dd, f1ad0d00), \
10323 X(_eor, 4040, ea800000), \
10324 X(_eors, 4040, ea900000), \
10325 X(_inc_sp,00dd, f10d0d00), \
10326 X(_ldmia, c800, e8900000), \
10327 X(_ldr, 6800, f8500000), \
10328 X(_ldrb, 7800, f8100000), \
10329 X(_ldrh, 8800, f8300000), \
10330 X(_ldrsb, 5600, f9100000), \
10331 X(_ldrsh, 5e00, f9300000), \
10332 X(_ldr_pc,4800, f85f0000), \
10333 X(_ldr_pc2,4800, f85f0000), \
10334 X(_ldr_sp,9800, f85d0000), \
10335 X(_lsl, 0000, fa00f000), \
10336 X(_lsls, 0000, fa10f000), \
10337 X(_lsr, 0800, fa20f000), \
10338 X(_lsrs, 0800, fa30f000), \
10339 X(_mov, 2000, ea4f0000), \
10340 X(_movs, 2000, ea5f0000), \
10341 X(_mul, 4340, fb00f000), \
10342 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10343 X(_mvn, 43c0, ea6f0000), \
10344 X(_mvns, 43c0, ea7f0000), \
10345 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10346 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10347 X(_orr, 4300, ea400000), \
10348 X(_orrs, 4300, ea500000), \
10349 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10350 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10351 X(_rev, ba00, fa90f080), \
10352 X(_rev16, ba40, fa90f090), \
10353 X(_revsh, bac0, fa90f0b0), \
10354 X(_ror, 41c0, fa60f000), \
10355 X(_rors, 41c0, fa70f000), \
10356 X(_sbc, 4180, eb600000), \
10357 X(_sbcs, 4180, eb700000), \
10358 X(_stmia, c000, e8800000), \
10359 X(_str, 6000, f8400000), \
10360 X(_strb, 7000, f8000000), \
10361 X(_strh, 8000, f8200000), \
10362 X(_str_sp,9000, f84d0000), \
10363 X(_sub, 1e00, eba00000), \
10364 X(_subs, 1e00, ebb00000), \
10365 X(_subi, 8000, f1a00000), \
10366 X(_subis, 8000, f1b00000), \
10367 X(_sxtb, b240, fa4ff080), \
10368 X(_sxth, b200, fa0ff080), \
10369 X(_tst, 4200, ea100f00), \
10370 X(_uxtb, b2c0, fa5ff080), \
10371 X(_uxth, b280, fa1ff080), \
10372 X(_nop, bf00, f3af8000), \
10373 X(_yield, bf10, f3af8001), \
10374 X(_wfe, bf20, f3af8002), \
10375 X(_wfi, bf30, f3af8003), \
10376 X(_sev, bf40, f3af8004), \
10377 X(_sevl, bf50, f3af8005), \
10378 X(_udf, de00, f7f0a000)
10380 /* To catch errors in encoding functions, the codes are all offset by
10381 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10382 as 16-bit instructions. */
10383 #define X(a,b,c) T_MNEM##a
10384 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10387 #define X(a,b,c) 0x##b
10388 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10389 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10392 #define X(a,b,c) 0x##c
10393 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10394 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10395 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10399 /* Thumb instruction encoders, in alphabetical order. */
10401 /* ADDW or SUBW. */
10404 do_t_add_sub_w (void)
10408 Rd
= inst
.operands
[0].reg
;
10409 Rn
= inst
.operands
[1].reg
;
10411 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10412 is the SP-{plus,minus}-immediate form of the instruction. */
10414 constraint (Rd
== REG_PC
, BAD_PC
);
10416 reject_bad_reg (Rd
);
10418 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10419 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10422 /* Parse an add or subtract instruction. We get here with inst.instruction
10423 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10426 do_t_add_sub (void)
10430 Rd
= inst
.operands
[0].reg
;
10431 Rs
= (inst
.operands
[1].present
10432 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10433 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10436 set_it_insn_type_last ();
10438 if (unified_syntax
)
10441 bfd_boolean narrow
;
10444 flags
= (inst
.instruction
== T_MNEM_adds
10445 || inst
.instruction
== T_MNEM_subs
);
10447 narrow
= !in_it_block ();
10449 narrow
= in_it_block ();
10450 if (!inst
.operands
[2].isreg
)
10454 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10456 add
= (inst
.instruction
== T_MNEM_add
10457 || inst
.instruction
== T_MNEM_adds
);
10459 if (inst
.size_req
!= 4)
10461 /* Attempt to use a narrow opcode, with relaxation if
10463 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10464 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10465 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10466 opcode
= T_MNEM_add_sp
;
10467 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10468 opcode
= T_MNEM_add_pc
;
10469 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10472 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10474 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10478 inst
.instruction
= THUMB_OP16(opcode
);
10479 inst
.instruction
|= (Rd
<< 4) | Rs
;
10480 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10481 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10483 if (inst
.size_req
== 2)
10484 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10486 inst
.relax
= opcode
;
10490 constraint (inst
.size_req
== 2, BAD_HIREG
);
10492 if (inst
.size_req
== 4
10493 || (inst
.size_req
!= 2 && !opcode
))
10495 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10496 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10497 THUMB1_RELOC_ONLY
);
10500 constraint (add
, BAD_PC
);
10501 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10502 _("only SUBS PC, LR, #const allowed"));
10503 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10504 _("expression too complex"));
10505 constraint (inst
.reloc
.exp
.X_add_number
< 0
10506 || inst
.reloc
.exp
.X_add_number
> 0xff,
10507 _("immediate value out of range"));
10508 inst
.instruction
= T2_SUBS_PC_LR
10509 | inst
.reloc
.exp
.X_add_number
;
10510 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10513 else if (Rs
== REG_PC
)
10515 /* Always use addw/subw. */
10516 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10517 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10521 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10522 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10525 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10527 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10529 inst
.instruction
|= Rd
<< 8;
10530 inst
.instruction
|= Rs
<< 16;
10535 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10536 unsigned int shift
= inst
.operands
[2].shift_kind
;
10538 Rn
= inst
.operands
[2].reg
;
10539 /* See if we can do this with a 16-bit instruction. */
10540 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10542 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10547 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10548 || inst
.instruction
== T_MNEM_add
)
10550 : T_OPCODE_SUB_R3
);
10551 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10555 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10557 /* Thumb-1 cores (except v6-M) require at least one high
10558 register in a narrow non flag setting add. */
10559 if (Rd
> 7 || Rn
> 7
10560 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10561 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10568 inst
.instruction
= T_OPCODE_ADD_HI
;
10569 inst
.instruction
|= (Rd
& 8) << 4;
10570 inst
.instruction
|= (Rd
& 7);
10571 inst
.instruction
|= Rn
<< 3;
10577 constraint (Rd
== REG_PC
, BAD_PC
);
10578 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10579 constraint (Rs
== REG_PC
, BAD_PC
);
10580 reject_bad_reg (Rn
);
10582 /* If we get here, it can't be done in 16 bits. */
10583 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10584 _("shift must be constant"));
10585 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10586 inst
.instruction
|= Rd
<< 8;
10587 inst
.instruction
|= Rs
<< 16;
10588 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10589 _("shift value over 3 not allowed in thumb mode"));
10590 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10591 _("only LSL shift allowed in thumb mode"));
10592 encode_thumb32_shifted_operand (2);
10597 constraint (inst
.instruction
== T_MNEM_adds
10598 || inst
.instruction
== T_MNEM_subs
,
10601 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10603 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10604 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10607 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10608 ? 0x0000 : 0x8000);
10609 inst
.instruction
|= (Rd
<< 4) | Rs
;
10610 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10614 Rn
= inst
.operands
[2].reg
;
10615 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10617 /* We now have Rd, Rs, and Rn set to registers. */
10618 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10620 /* Can't do this for SUB. */
10621 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10622 inst
.instruction
= T_OPCODE_ADD_HI
;
10623 inst
.instruction
|= (Rd
& 8) << 4;
10624 inst
.instruction
|= (Rd
& 7);
10626 inst
.instruction
|= Rn
<< 3;
10628 inst
.instruction
|= Rs
<< 3;
10630 constraint (1, _("dest must overlap one source register"));
10634 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10635 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10636 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10646 Rd
= inst
.operands
[0].reg
;
10647 reject_bad_reg (Rd
);
10649 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10651 /* Defer to section relaxation. */
10652 inst
.relax
= inst
.instruction
;
10653 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10654 inst
.instruction
|= Rd
<< 4;
10656 else if (unified_syntax
&& inst
.size_req
!= 2)
10658 /* Generate a 32-bit opcode. */
10659 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10660 inst
.instruction
|= Rd
<< 8;
10661 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10662 inst
.reloc
.pc_rel
= 1;
10666 /* Generate a 16-bit opcode. */
10667 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10668 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10669 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10670 inst
.reloc
.pc_rel
= 1;
10672 inst
.instruction
|= Rd
<< 4;
10676 /* Arithmetic instructions for which there is just one 16-bit
10677 instruction encoding, and it allows only two low registers.
10678 For maximal compatibility with ARM syntax, we allow three register
10679 operands even when Thumb-32 instructions are not available, as long
10680 as the first two are identical. For instance, both "sbc r0,r1" and
10681 "sbc r0,r0,r1" are allowed. */
10687 Rd
= inst
.operands
[0].reg
;
10688 Rs
= (inst
.operands
[1].present
10689 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10690 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10691 Rn
= inst
.operands
[2].reg
;
10693 reject_bad_reg (Rd
);
10694 reject_bad_reg (Rs
);
10695 if (inst
.operands
[2].isreg
)
10696 reject_bad_reg (Rn
);
10698 if (unified_syntax
)
10700 if (!inst
.operands
[2].isreg
)
10702 /* For an immediate, we always generate a 32-bit opcode;
10703 section relaxation will shrink it later if possible. */
10704 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10705 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10706 inst
.instruction
|= Rd
<< 8;
10707 inst
.instruction
|= Rs
<< 16;
10708 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10712 bfd_boolean narrow
;
10714 /* See if we can do this with a 16-bit instruction. */
10715 if (THUMB_SETS_FLAGS (inst
.instruction
))
10716 narrow
= !in_it_block ();
10718 narrow
= in_it_block ();
10720 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10722 if (inst
.operands
[2].shifted
)
10724 if (inst
.size_req
== 4)
10730 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10731 inst
.instruction
|= Rd
;
10732 inst
.instruction
|= Rn
<< 3;
10736 /* If we get here, it can't be done in 16 bits. */
10737 constraint (inst
.operands
[2].shifted
10738 && inst
.operands
[2].immisreg
,
10739 _("shift must be constant"));
10740 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10741 inst
.instruction
|= Rd
<< 8;
10742 inst
.instruction
|= Rs
<< 16;
10743 encode_thumb32_shifted_operand (2);
10748 /* On its face this is a lie - the instruction does set the
10749 flags. However, the only supported mnemonic in this mode
10750 says it doesn't. */
10751 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10753 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10754 _("unshifted register required"));
10755 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10756 constraint (Rd
!= Rs
,
10757 _("dest and source1 must be the same register"));
10759 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10760 inst
.instruction
|= Rd
;
10761 inst
.instruction
|= Rn
<< 3;
10765 /* Similarly, but for instructions where the arithmetic operation is
10766 commutative, so we can allow either of them to be different from
10767 the destination operand in a 16-bit instruction. For instance, all
10768 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10775 Rd
= inst
.operands
[0].reg
;
10776 Rs
= (inst
.operands
[1].present
10777 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10778 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10779 Rn
= inst
.operands
[2].reg
;
10781 reject_bad_reg (Rd
);
10782 reject_bad_reg (Rs
);
10783 if (inst
.operands
[2].isreg
)
10784 reject_bad_reg (Rn
);
10786 if (unified_syntax
)
10788 if (!inst
.operands
[2].isreg
)
10790 /* For an immediate, we always generate a 32-bit opcode;
10791 section relaxation will shrink it later if possible. */
10792 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10793 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10794 inst
.instruction
|= Rd
<< 8;
10795 inst
.instruction
|= Rs
<< 16;
10796 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10800 bfd_boolean narrow
;
10802 /* See if we can do this with a 16-bit instruction. */
10803 if (THUMB_SETS_FLAGS (inst
.instruction
))
10804 narrow
= !in_it_block ();
10806 narrow
= in_it_block ();
10808 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10810 if (inst
.operands
[2].shifted
)
10812 if (inst
.size_req
== 4)
10819 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10820 inst
.instruction
|= Rd
;
10821 inst
.instruction
|= Rn
<< 3;
10826 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10827 inst
.instruction
|= Rd
;
10828 inst
.instruction
|= Rs
<< 3;
10833 /* If we get here, it can't be done in 16 bits. */
10834 constraint (inst
.operands
[2].shifted
10835 && inst
.operands
[2].immisreg
,
10836 _("shift must be constant"));
10837 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10838 inst
.instruction
|= Rd
<< 8;
10839 inst
.instruction
|= Rs
<< 16;
10840 encode_thumb32_shifted_operand (2);
10845 /* On its face this is a lie - the instruction does set the
10846 flags. However, the only supported mnemonic in this mode
10847 says it doesn't. */
10848 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10850 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10851 _("unshifted register required"));
10852 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10854 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10855 inst
.instruction
|= Rd
;
10858 inst
.instruction
|= Rn
<< 3;
10860 inst
.instruction
|= Rs
<< 3;
10862 constraint (1, _("dest must overlap one source register"));
10870 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10871 constraint (msb
> 32, _("bit-field extends past end of register"));
10872 /* The instruction encoding stores the LSB and MSB,
10873 not the LSB and width. */
10874 Rd
= inst
.operands
[0].reg
;
10875 reject_bad_reg (Rd
);
10876 inst
.instruction
|= Rd
<< 8;
10877 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10878 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10879 inst
.instruction
|= msb
- 1;
10888 Rd
= inst
.operands
[0].reg
;
10889 reject_bad_reg (Rd
);
10891 /* #0 in second position is alternative syntax for bfc, which is
10892 the same instruction but with REG_PC in the Rm field. */
10893 if (!inst
.operands
[1].isreg
)
10897 Rn
= inst
.operands
[1].reg
;
10898 reject_bad_reg (Rn
);
10901 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10902 constraint (msb
> 32, _("bit-field extends past end of register"));
10903 /* The instruction encoding stores the LSB and MSB,
10904 not the LSB and width. */
10905 inst
.instruction
|= Rd
<< 8;
10906 inst
.instruction
|= Rn
<< 16;
10907 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10908 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10909 inst
.instruction
|= msb
- 1;
10917 Rd
= inst
.operands
[0].reg
;
10918 Rn
= inst
.operands
[1].reg
;
10920 reject_bad_reg (Rd
);
10921 reject_bad_reg (Rn
);
10923 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10924 _("bit-field extends past end of register"));
10925 inst
.instruction
|= Rd
<< 8;
10926 inst
.instruction
|= Rn
<< 16;
10927 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10928 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10929 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10932 /* ARM V5 Thumb BLX (argument parse)
10933 BLX <target_addr> which is BLX(1)
10934 BLX <Rm> which is BLX(2)
10935 Unfortunately, there are two different opcodes for this mnemonic.
10936 So, the insns[].value is not used, and the code here zaps values
10937 into inst.instruction.
10939 ??? How to take advantage of the additional two bits of displacement
10940 available in Thumb32 mode? Need new relocation? */
10945 set_it_insn_type_last ();
10947 if (inst
.operands
[0].isreg
)
10949 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10950 /* We have a register, so this is BLX(2). */
10951 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10955 /* No register. This must be BLX(1). */
10956 inst
.instruction
= 0xf000e800;
10957 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10969 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10971 if (in_it_block ())
10973 /* Conditional branches inside IT blocks are encoded as unconditional
10975 cond
= COND_ALWAYS
;
10980 if (cond
!= COND_ALWAYS
)
10981 opcode
= T_MNEM_bcond
;
10983 opcode
= inst
.instruction
;
10986 && (inst
.size_req
== 4
10987 || (inst
.size_req
!= 2
10988 && (inst
.operands
[0].hasreloc
10989 || inst
.reloc
.exp
.X_op
== O_constant
))))
10991 inst
.instruction
= THUMB_OP32(opcode
);
10992 if (cond
== COND_ALWAYS
)
10993 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
10996 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
10997 _("selected architecture does not support "
10998 "wide conditional branch instruction"));
11000 gas_assert (cond
!= 0xF);
11001 inst
.instruction
|= cond
<< 22;
11002 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11007 inst
.instruction
= THUMB_OP16(opcode
);
11008 if (cond
== COND_ALWAYS
)
11009 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11012 inst
.instruction
|= cond
<< 8;
11013 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11015 /* Allow section relaxation. */
11016 if (unified_syntax
&& inst
.size_req
!= 2)
11017 inst
.relax
= opcode
;
11019 inst
.reloc
.type
= reloc
;
11020 inst
.reloc
.pc_rel
= 1;
11023 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11024 between the two is the maximum immediate allowed - which is passed in
11027 do_t_bkpt_hlt1 (int range
)
11029 constraint (inst
.cond
!= COND_ALWAYS
,
11030 _("instruction is always unconditional"));
11031 if (inst
.operands
[0].present
)
11033 constraint (inst
.operands
[0].imm
> range
,
11034 _("immediate value out of range"));
11035 inst
.instruction
|= inst
.operands
[0].imm
;
11038 set_it_insn_type (NEUTRAL_IT_INSN
);
11044 do_t_bkpt_hlt1 (63);
11050 do_t_bkpt_hlt1 (255);
11054 do_t_branch23 (void)
11056 set_it_insn_type_last ();
11057 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11059 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11060 this file. We used to simply ignore the PLT reloc type here --
11061 the branch encoding is now needed to deal with TLSCALL relocs.
11062 So if we see a PLT reloc now, put it back to how it used to be to
11063 keep the preexisting behaviour. */
11064 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11065 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11067 #if defined(OBJ_COFF)
11068 /* If the destination of the branch is a defined symbol which does not have
11069 the THUMB_FUNC attribute, then we must be calling a function which has
11070 the (interfacearm) attribute. We look for the Thumb entry point to that
11071 function and change the branch to refer to that function instead. */
11072 if ( inst
.reloc
.exp
.X_op
== O_symbol
11073 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11074 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11075 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11076 inst
.reloc
.exp
.X_add_symbol
=
11077 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11084 set_it_insn_type_last ();
11085 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11086 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11087 should cause the alignment to be checked once it is known. This is
11088 because BX PC only works if the instruction is word aligned. */
11096 set_it_insn_type_last ();
11097 Rm
= inst
.operands
[0].reg
;
11098 reject_bad_reg (Rm
);
11099 inst
.instruction
|= Rm
<< 16;
11108 Rd
= inst
.operands
[0].reg
;
11109 Rm
= inst
.operands
[1].reg
;
11111 reject_bad_reg (Rd
);
11112 reject_bad_reg (Rm
);
11114 inst
.instruction
|= Rd
<< 8;
11115 inst
.instruction
|= Rm
<< 16;
11116 inst
.instruction
|= Rm
;
11122 set_it_insn_type (OUTSIDE_IT_INSN
);
11123 inst
.instruction
|= inst
.operands
[0].imm
;
11129 set_it_insn_type (OUTSIDE_IT_INSN
);
11131 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11132 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11134 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11135 inst
.instruction
= 0xf3af8000;
11136 inst
.instruction
|= imod
<< 9;
11137 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11138 if (inst
.operands
[1].present
)
11139 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11143 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11144 && (inst
.operands
[0].imm
& 4),
11145 _("selected processor does not support 'A' form "
11146 "of this instruction"));
11147 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11148 _("Thumb does not support the 2-argument "
11149 "form of this instruction"));
11150 inst
.instruction
|= inst
.operands
[0].imm
;
11154 /* THUMB CPY instruction (argument parse). */
11159 if (inst
.size_req
== 4)
11161 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11162 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11163 inst
.instruction
|= inst
.operands
[1].reg
;
11167 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11168 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11169 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11176 set_it_insn_type (OUTSIDE_IT_INSN
);
11177 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11178 inst
.instruction
|= inst
.operands
[0].reg
;
11179 inst
.reloc
.pc_rel
= 1;
11180 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11186 inst
.instruction
|= inst
.operands
[0].imm
;
11192 unsigned Rd
, Rn
, Rm
;
11194 Rd
= inst
.operands
[0].reg
;
11195 Rn
= (inst
.operands
[1].present
11196 ? inst
.operands
[1].reg
: Rd
);
11197 Rm
= inst
.operands
[2].reg
;
11199 reject_bad_reg (Rd
);
11200 reject_bad_reg (Rn
);
11201 reject_bad_reg (Rm
);
11203 inst
.instruction
|= Rd
<< 8;
11204 inst
.instruction
|= Rn
<< 16;
11205 inst
.instruction
|= Rm
;
11211 if (unified_syntax
&& inst
.size_req
== 4)
11212 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11214 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11220 unsigned int cond
= inst
.operands
[0].imm
;
11222 set_it_insn_type (IT_INSN
);
11223 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11225 now_it
.warn_deprecated
= FALSE
;
11227 /* If the condition is a negative condition, invert the mask. */
11228 if ((cond
& 0x1) == 0x0)
11230 unsigned int mask
= inst
.instruction
& 0x000f;
11232 if ((mask
& 0x7) == 0)
11234 /* No conversion needed. */
11235 now_it
.block_length
= 1;
11237 else if ((mask
& 0x3) == 0)
11240 now_it
.block_length
= 2;
11242 else if ((mask
& 0x1) == 0)
11245 now_it
.block_length
= 3;
11250 now_it
.block_length
= 4;
11253 inst
.instruction
&= 0xfff0;
11254 inst
.instruction
|= mask
;
11257 inst
.instruction
|= cond
<< 4;
11260 /* Helper function used for both push/pop and ldm/stm. */
11262 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11266 load
= (inst
.instruction
& (1 << 20)) != 0;
11268 if (mask
& (1 << 13))
11269 inst
.error
= _("SP not allowed in register list");
11271 if ((mask
& (1 << base
)) != 0
11273 inst
.error
= _("having the base register in the register list when "
11274 "using write back is UNPREDICTABLE");
11278 if (mask
& (1 << 15))
11280 if (mask
& (1 << 14))
11281 inst
.error
= _("LR and PC should not both be in register list");
11283 set_it_insn_type_last ();
11288 if (mask
& (1 << 15))
11289 inst
.error
= _("PC not allowed in register list");
11292 if ((mask
& (mask
- 1)) == 0)
11294 /* Single register transfers implemented as str/ldr. */
11297 if (inst
.instruction
& (1 << 23))
11298 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11300 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11304 if (inst
.instruction
& (1 << 23))
11305 inst
.instruction
= 0x00800000; /* ia -> [base] */
11307 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11310 inst
.instruction
|= 0xf8400000;
11312 inst
.instruction
|= 0x00100000;
11314 mask
= ffs (mask
) - 1;
11317 else if (writeback
)
11318 inst
.instruction
|= WRITE_BACK
;
11320 inst
.instruction
|= mask
;
11321 inst
.instruction
|= base
<< 16;
11327 /* This really doesn't seem worth it. */
11328 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11329 _("expression too complex"));
11330 constraint (inst
.operands
[1].writeback
,
11331 _("Thumb load/store multiple does not support {reglist}^"));
11333 if (unified_syntax
)
11335 bfd_boolean narrow
;
11339 /* See if we can use a 16-bit instruction. */
11340 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11341 && inst
.size_req
!= 4
11342 && !(inst
.operands
[1].imm
& ~0xff))
11344 mask
= 1 << inst
.operands
[0].reg
;
11346 if (inst
.operands
[0].reg
<= 7)
11348 if (inst
.instruction
== T_MNEM_stmia
11349 ? inst
.operands
[0].writeback
11350 : (inst
.operands
[0].writeback
11351 == !(inst
.operands
[1].imm
& mask
)))
11353 if (inst
.instruction
== T_MNEM_stmia
11354 && (inst
.operands
[1].imm
& mask
)
11355 && (inst
.operands
[1].imm
& (mask
- 1)))
11356 as_warn (_("value stored for r%d is UNKNOWN"),
11357 inst
.operands
[0].reg
);
11359 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11360 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11361 inst
.instruction
|= inst
.operands
[1].imm
;
11364 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11366 /* This means 1 register in reg list one of 3 situations:
11367 1. Instruction is stmia, but without writeback.
11368 2. lmdia without writeback, but with Rn not in
11370 3. ldmia with writeback, but with Rn in reglist.
11371 Case 3 is UNPREDICTABLE behaviour, so we handle
11372 case 1 and 2 which can be converted into a 16-bit
11373 str or ldr. The SP cases are handled below. */
11374 unsigned long opcode
;
11375 /* First, record an error for Case 3. */
11376 if (inst
.operands
[1].imm
& mask
11377 && inst
.operands
[0].writeback
)
11379 _("having the base register in the register list when "
11380 "using write back is UNPREDICTABLE");
11382 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11384 inst
.instruction
= THUMB_OP16 (opcode
);
11385 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11386 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11390 else if (inst
.operands
[0] .reg
== REG_SP
)
11392 if (inst
.operands
[0].writeback
)
11395 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11396 ? T_MNEM_push
: T_MNEM_pop
);
11397 inst
.instruction
|= inst
.operands
[1].imm
;
11400 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11403 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11404 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11405 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11413 if (inst
.instruction
< 0xffff)
11414 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11416 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11417 inst
.operands
[0].writeback
);
11422 constraint (inst
.operands
[0].reg
> 7
11423 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11424 constraint (inst
.instruction
!= T_MNEM_ldmia
11425 && inst
.instruction
!= T_MNEM_stmia
,
11426 _("Thumb-2 instruction only valid in unified syntax"));
11427 if (inst
.instruction
== T_MNEM_stmia
)
11429 if (!inst
.operands
[0].writeback
)
11430 as_warn (_("this instruction will write back the base register"));
11431 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11432 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11433 as_warn (_("value stored for r%d is UNKNOWN"),
11434 inst
.operands
[0].reg
);
11438 if (!inst
.operands
[0].writeback
11439 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11440 as_warn (_("this instruction will write back the base register"));
11441 else if (inst
.operands
[0].writeback
11442 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11443 as_warn (_("this instruction will not write back the base register"));
11446 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11447 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11448 inst
.instruction
|= inst
.operands
[1].imm
;
11455 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11456 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11457 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11458 || inst
.operands
[1].negative
,
11461 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11463 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11464 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11465 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11471 if (!inst
.operands
[1].present
)
11473 constraint (inst
.operands
[0].reg
== REG_LR
,
11474 _("r14 not allowed as first register "
11475 "when second register is omitted"));
11476 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11478 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11481 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11482 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11483 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11489 unsigned long opcode
;
11492 if (inst
.operands
[0].isreg
11493 && !inst
.operands
[0].preind
11494 && inst
.operands
[0].reg
== REG_PC
)
11495 set_it_insn_type_last ();
11497 opcode
= inst
.instruction
;
11498 if (unified_syntax
)
11500 if (!inst
.operands
[1].isreg
)
11502 if (opcode
<= 0xffff)
11503 inst
.instruction
= THUMB_OP32 (opcode
);
11504 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11507 if (inst
.operands
[1].isreg
11508 && !inst
.operands
[1].writeback
11509 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11510 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11511 && opcode
<= 0xffff
11512 && inst
.size_req
!= 4)
11514 /* Insn may have a 16-bit form. */
11515 Rn
= inst
.operands
[1].reg
;
11516 if (inst
.operands
[1].immisreg
)
11518 inst
.instruction
= THUMB_OP16 (opcode
);
11520 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11522 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11523 reject_bad_reg (inst
.operands
[1].imm
);
11525 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11526 && opcode
!= T_MNEM_ldrsb
)
11527 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11528 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11535 if (inst
.reloc
.pc_rel
)
11536 opcode
= T_MNEM_ldr_pc2
;
11538 opcode
= T_MNEM_ldr_pc
;
11542 if (opcode
== T_MNEM_ldr
)
11543 opcode
= T_MNEM_ldr_sp
;
11545 opcode
= T_MNEM_str_sp
;
11547 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11551 inst
.instruction
= inst
.operands
[0].reg
;
11552 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11554 inst
.instruction
|= THUMB_OP16 (opcode
);
11555 if (inst
.size_req
== 2)
11556 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11558 inst
.relax
= opcode
;
11562 /* Definitely a 32-bit variant. */
11564 /* Warning for Erratum 752419. */
11565 if (opcode
== T_MNEM_ldr
11566 && inst
.operands
[0].reg
== REG_SP
11567 && inst
.operands
[1].writeback
== 1
11568 && !inst
.operands
[1].immisreg
)
11570 if (no_cpu_selected ()
11571 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11572 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11573 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11574 as_warn (_("This instruction may be unpredictable "
11575 "if executed on M-profile cores "
11576 "with interrupts enabled."));
11579 /* Do some validations regarding addressing modes. */
11580 if (inst
.operands
[1].immisreg
)
11581 reject_bad_reg (inst
.operands
[1].imm
);
11583 constraint (inst
.operands
[1].writeback
== 1
11584 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11587 inst
.instruction
= THUMB_OP32 (opcode
);
11588 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11589 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11590 check_ldr_r15_aligned ();
11594 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11596 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11598 /* Only [Rn,Rm] is acceptable. */
11599 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11600 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11601 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11602 || inst
.operands
[1].negative
,
11603 _("Thumb does not support this addressing mode"));
11604 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11608 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11609 if (!inst
.operands
[1].isreg
)
11610 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11613 constraint (!inst
.operands
[1].preind
11614 || inst
.operands
[1].shifted
11615 || inst
.operands
[1].writeback
,
11616 _("Thumb does not support this addressing mode"));
11617 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11619 constraint (inst
.instruction
& 0x0600,
11620 _("byte or halfword not valid for base register"));
11621 constraint (inst
.operands
[1].reg
== REG_PC
11622 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11623 _("r15 based store not allowed"));
11624 constraint (inst
.operands
[1].immisreg
,
11625 _("invalid base register for register offset"));
11627 if (inst
.operands
[1].reg
== REG_PC
)
11628 inst
.instruction
= T_OPCODE_LDR_PC
;
11629 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11630 inst
.instruction
= T_OPCODE_LDR_SP
;
11632 inst
.instruction
= T_OPCODE_STR_SP
;
11634 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11635 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11639 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11640 if (!inst
.operands
[1].immisreg
)
11642 /* Immediate offset. */
11643 inst
.instruction
|= inst
.operands
[0].reg
;
11644 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11645 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11649 /* Register offset. */
11650 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11651 constraint (inst
.operands
[1].negative
,
11652 _("Thumb does not support this addressing mode"));
11655 switch (inst
.instruction
)
11657 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11658 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11659 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11660 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11661 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11662 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11663 case 0x5600 /* ldrsb */:
11664 case 0x5e00 /* ldrsh */: break;
11668 inst
.instruction
|= inst
.operands
[0].reg
;
11669 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11670 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11676 if (!inst
.operands
[1].present
)
11678 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11679 constraint (inst
.operands
[0].reg
== REG_LR
,
11680 _("r14 not allowed here"));
11681 constraint (inst
.operands
[0].reg
== REG_R12
,
11682 _("r12 not allowed here"));
11685 if (inst
.operands
[2].writeback
11686 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11687 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11688 as_warn (_("base register written back, and overlaps "
11689 "one of transfer registers"));
11691 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11692 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11693 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11699 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11700 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11706 unsigned Rd
, Rn
, Rm
, Ra
;
11708 Rd
= inst
.operands
[0].reg
;
11709 Rn
= inst
.operands
[1].reg
;
11710 Rm
= inst
.operands
[2].reg
;
11711 Ra
= inst
.operands
[3].reg
;
11713 reject_bad_reg (Rd
);
11714 reject_bad_reg (Rn
);
11715 reject_bad_reg (Rm
);
11716 reject_bad_reg (Ra
);
11718 inst
.instruction
|= Rd
<< 8;
11719 inst
.instruction
|= Rn
<< 16;
11720 inst
.instruction
|= Rm
;
11721 inst
.instruction
|= Ra
<< 12;
11727 unsigned RdLo
, RdHi
, Rn
, Rm
;
11729 RdLo
= inst
.operands
[0].reg
;
11730 RdHi
= inst
.operands
[1].reg
;
11731 Rn
= inst
.operands
[2].reg
;
11732 Rm
= inst
.operands
[3].reg
;
11734 reject_bad_reg (RdLo
);
11735 reject_bad_reg (RdHi
);
11736 reject_bad_reg (Rn
);
11737 reject_bad_reg (Rm
);
11739 inst
.instruction
|= RdLo
<< 12;
11740 inst
.instruction
|= RdHi
<< 8;
11741 inst
.instruction
|= Rn
<< 16;
11742 inst
.instruction
|= Rm
;
11746 do_t_mov_cmp (void)
11750 Rn
= inst
.operands
[0].reg
;
11751 Rm
= inst
.operands
[1].reg
;
11754 set_it_insn_type_last ();
11756 if (unified_syntax
)
11758 int r0off
= (inst
.instruction
== T_MNEM_mov
11759 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11760 unsigned long opcode
;
11761 bfd_boolean narrow
;
11762 bfd_boolean low_regs
;
11764 low_regs
= (Rn
<= 7 && Rm
<= 7);
11765 opcode
= inst
.instruction
;
11766 if (in_it_block ())
11767 narrow
= opcode
!= T_MNEM_movs
;
11769 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11770 if (inst
.size_req
== 4
11771 || inst
.operands
[1].shifted
)
11774 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11775 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11776 && !inst
.operands
[1].shifted
11780 inst
.instruction
= T2_SUBS_PC_LR
;
11784 if (opcode
== T_MNEM_cmp
)
11786 constraint (Rn
== REG_PC
, BAD_PC
);
11789 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11791 warn_deprecated_sp (Rm
);
11792 /* R15 was documented as a valid choice for Rm in ARMv6,
11793 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11794 tools reject R15, so we do too. */
11795 constraint (Rm
== REG_PC
, BAD_PC
);
11798 reject_bad_reg (Rm
);
11800 else if (opcode
== T_MNEM_mov
11801 || opcode
== T_MNEM_movs
)
11803 if (inst
.operands
[1].isreg
)
11805 if (opcode
== T_MNEM_movs
)
11807 reject_bad_reg (Rn
);
11808 reject_bad_reg (Rm
);
11812 /* This is mov.n. */
11813 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11814 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11816 as_tsktsk (_("Use of r%u as a source register is "
11817 "deprecated when r%u is the destination "
11818 "register."), Rm
, Rn
);
11823 /* This is mov.w. */
11824 constraint (Rn
== REG_PC
, BAD_PC
);
11825 constraint (Rm
== REG_PC
, BAD_PC
);
11826 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11830 reject_bad_reg (Rn
);
11833 if (!inst
.operands
[1].isreg
)
11835 /* Immediate operand. */
11836 if (!in_it_block () && opcode
== T_MNEM_mov
)
11838 if (low_regs
&& narrow
)
11840 inst
.instruction
= THUMB_OP16 (opcode
);
11841 inst
.instruction
|= Rn
<< 8;
11842 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11843 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11845 if (inst
.size_req
== 2)
11846 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11848 inst
.relax
= opcode
;
11853 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11854 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
11855 THUMB1_RELOC_ONLY
);
11857 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11858 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11859 inst
.instruction
|= Rn
<< r0off
;
11860 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11863 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11864 && (inst
.instruction
== T_MNEM_mov
11865 || inst
.instruction
== T_MNEM_movs
))
11867 /* Register shifts are encoded as separate shift instructions. */
11868 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11870 if (in_it_block ())
11875 if (inst
.size_req
== 4)
11878 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11884 switch (inst
.operands
[1].shift_kind
)
11887 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11890 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11893 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11896 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11902 inst
.instruction
= opcode
;
11905 inst
.instruction
|= Rn
;
11906 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11911 inst
.instruction
|= CONDS_BIT
;
11913 inst
.instruction
|= Rn
<< 8;
11914 inst
.instruction
|= Rm
<< 16;
11915 inst
.instruction
|= inst
.operands
[1].imm
;
11920 /* Some mov with immediate shift have narrow variants.
11921 Register shifts are handled above. */
11922 if (low_regs
&& inst
.operands
[1].shifted
11923 && (inst
.instruction
== T_MNEM_mov
11924 || inst
.instruction
== T_MNEM_movs
))
11926 if (in_it_block ())
11927 narrow
= (inst
.instruction
== T_MNEM_mov
);
11929 narrow
= (inst
.instruction
== T_MNEM_movs
);
11934 switch (inst
.operands
[1].shift_kind
)
11936 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11937 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11938 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11939 default: narrow
= FALSE
; break;
11945 inst
.instruction
|= Rn
;
11946 inst
.instruction
|= Rm
<< 3;
11947 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11951 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11952 inst
.instruction
|= Rn
<< r0off
;
11953 encode_thumb32_shifted_operand (1);
11957 switch (inst
.instruction
)
11960 /* In v4t or v5t a move of two lowregs produces unpredictable
11961 results. Don't allow this. */
11964 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11965 "MOV Rd, Rs with two low registers is not "
11966 "permitted on this architecture");
11967 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11971 inst
.instruction
= T_OPCODE_MOV_HR
;
11972 inst
.instruction
|= (Rn
& 0x8) << 4;
11973 inst
.instruction
|= (Rn
& 0x7);
11974 inst
.instruction
|= Rm
<< 3;
11978 /* We know we have low registers at this point.
11979 Generate LSLS Rd, Rs, #0. */
11980 inst
.instruction
= T_OPCODE_LSL_I
;
11981 inst
.instruction
|= Rn
;
11982 inst
.instruction
|= Rm
<< 3;
11988 inst
.instruction
= T_OPCODE_CMP_LR
;
11989 inst
.instruction
|= Rn
;
11990 inst
.instruction
|= Rm
<< 3;
11994 inst
.instruction
= T_OPCODE_CMP_HR
;
11995 inst
.instruction
|= (Rn
& 0x8) << 4;
11996 inst
.instruction
|= (Rn
& 0x7);
11997 inst
.instruction
|= Rm
<< 3;
12004 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12006 /* PR 10443: Do not silently ignore shifted operands. */
12007 constraint (inst
.operands
[1].shifted
,
12008 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12010 if (inst
.operands
[1].isreg
)
12012 if (Rn
< 8 && Rm
< 8)
12014 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12015 since a MOV instruction produces unpredictable results. */
12016 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12017 inst
.instruction
= T_OPCODE_ADD_I3
;
12019 inst
.instruction
= T_OPCODE_CMP_LR
;
12021 inst
.instruction
|= Rn
;
12022 inst
.instruction
|= Rm
<< 3;
12026 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12027 inst
.instruction
= T_OPCODE_MOV_HR
;
12029 inst
.instruction
= T_OPCODE_CMP_HR
;
12035 constraint (Rn
> 7,
12036 _("only lo regs allowed with immediate"));
12037 inst
.instruction
|= Rn
<< 8;
12038 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12049 top
= (inst
.instruction
& 0x00800000) != 0;
12050 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12052 constraint (top
, _(":lower16: not allowed this instruction"));
12053 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12055 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12057 constraint (!top
, _(":upper16: not allowed this instruction"));
12058 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12061 Rd
= inst
.operands
[0].reg
;
12062 reject_bad_reg (Rd
);
12064 inst
.instruction
|= Rd
<< 8;
12065 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12067 imm
= inst
.reloc
.exp
.X_add_number
;
12068 inst
.instruction
|= (imm
& 0xf000) << 4;
12069 inst
.instruction
|= (imm
& 0x0800) << 15;
12070 inst
.instruction
|= (imm
& 0x0700) << 4;
12071 inst
.instruction
|= (imm
& 0x00ff);
12076 do_t_mvn_tst (void)
12080 Rn
= inst
.operands
[0].reg
;
12081 Rm
= inst
.operands
[1].reg
;
12083 if (inst
.instruction
== T_MNEM_cmp
12084 || inst
.instruction
== T_MNEM_cmn
)
12085 constraint (Rn
== REG_PC
, BAD_PC
);
12087 reject_bad_reg (Rn
);
12088 reject_bad_reg (Rm
);
12090 if (unified_syntax
)
12092 int r0off
= (inst
.instruction
== T_MNEM_mvn
12093 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12094 bfd_boolean narrow
;
12096 if (inst
.size_req
== 4
12097 || inst
.instruction
> 0xffff
12098 || inst
.operands
[1].shifted
12099 || Rn
> 7 || Rm
> 7)
12101 else if (inst
.instruction
== T_MNEM_cmn
12102 || inst
.instruction
== T_MNEM_tst
)
12104 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12105 narrow
= !in_it_block ();
12107 narrow
= in_it_block ();
12109 if (!inst
.operands
[1].isreg
)
12111 /* For an immediate, we always generate a 32-bit opcode;
12112 section relaxation will shrink it later if possible. */
12113 if (inst
.instruction
< 0xffff)
12114 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12115 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12116 inst
.instruction
|= Rn
<< r0off
;
12117 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12121 /* See if we can do this with a 16-bit instruction. */
12124 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12125 inst
.instruction
|= Rn
;
12126 inst
.instruction
|= Rm
<< 3;
12130 constraint (inst
.operands
[1].shifted
12131 && inst
.operands
[1].immisreg
,
12132 _("shift must be constant"));
12133 if (inst
.instruction
< 0xffff)
12134 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12135 inst
.instruction
|= Rn
<< r0off
;
12136 encode_thumb32_shifted_operand (1);
12142 constraint (inst
.instruction
> 0xffff
12143 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12144 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12145 _("unshifted register required"));
12146 constraint (Rn
> 7 || Rm
> 7,
12149 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12150 inst
.instruction
|= Rn
;
12151 inst
.instruction
|= Rm
<< 3;
12160 if (do_vfp_nsyn_mrs () == SUCCESS
)
12163 Rd
= inst
.operands
[0].reg
;
12164 reject_bad_reg (Rd
);
12165 inst
.instruction
|= Rd
<< 8;
12167 if (inst
.operands
[1].isreg
)
12169 unsigned br
= inst
.operands
[1].reg
;
12170 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12171 as_bad (_("bad register for mrs"));
12173 inst
.instruction
|= br
& (0xf << 16);
12174 inst
.instruction
|= (br
& 0x300) >> 4;
12175 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12179 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12181 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12183 /* PR gas/12698: The constraint is only applied for m_profile.
12184 If the user has specified -march=all, we want to ignore it as
12185 we are building for any CPU type, including non-m variants. */
12186 bfd_boolean m_profile
=
12187 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12188 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12189 "not support requested special purpose register"));
12192 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12194 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12195 _("'APSR', 'CPSR' or 'SPSR' expected"));
12197 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12198 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12199 inst
.instruction
|= 0xf0000;
12209 if (do_vfp_nsyn_msr () == SUCCESS
)
12212 constraint (!inst
.operands
[1].isreg
,
12213 _("Thumb encoding does not support an immediate here"));
12215 if (inst
.operands
[0].isreg
)
12216 flags
= (int)(inst
.operands
[0].reg
);
12218 flags
= inst
.operands
[0].imm
;
12220 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12222 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12224 /* PR gas/12698: The constraint is only applied for m_profile.
12225 If the user has specified -march=all, we want to ignore it as
12226 we are building for any CPU type, including non-m variants. */
12227 bfd_boolean m_profile
=
12228 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12229 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12230 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12231 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12232 && bits
!= PSR_f
)) && m_profile
,
12233 _("selected processor does not support requested special "
12234 "purpose register"));
12237 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12238 "requested special purpose register"));
12240 Rn
= inst
.operands
[1].reg
;
12241 reject_bad_reg (Rn
);
12243 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12244 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12245 inst
.instruction
|= (flags
& 0x300) >> 4;
12246 inst
.instruction
|= (flags
& 0xff);
12247 inst
.instruction
|= Rn
<< 16;
12253 bfd_boolean narrow
;
12254 unsigned Rd
, Rn
, Rm
;
12256 if (!inst
.operands
[2].present
)
12257 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12259 Rd
= inst
.operands
[0].reg
;
12260 Rn
= inst
.operands
[1].reg
;
12261 Rm
= inst
.operands
[2].reg
;
12263 if (unified_syntax
)
12265 if (inst
.size_req
== 4
12271 else if (inst
.instruction
== T_MNEM_muls
)
12272 narrow
= !in_it_block ();
12274 narrow
= in_it_block ();
12278 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12279 constraint (Rn
> 7 || Rm
> 7,
12286 /* 16-bit MULS/Conditional MUL. */
12287 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12288 inst
.instruction
|= Rd
;
12291 inst
.instruction
|= Rm
<< 3;
12293 inst
.instruction
|= Rn
<< 3;
12295 constraint (1, _("dest must overlap one source register"));
12299 constraint (inst
.instruction
!= T_MNEM_mul
,
12300 _("Thumb-2 MUL must not set flags"));
12302 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12303 inst
.instruction
|= Rd
<< 8;
12304 inst
.instruction
|= Rn
<< 16;
12305 inst
.instruction
|= Rm
<< 0;
12307 reject_bad_reg (Rd
);
12308 reject_bad_reg (Rn
);
12309 reject_bad_reg (Rm
);
12316 unsigned RdLo
, RdHi
, Rn
, Rm
;
12318 RdLo
= inst
.operands
[0].reg
;
12319 RdHi
= inst
.operands
[1].reg
;
12320 Rn
= inst
.operands
[2].reg
;
12321 Rm
= inst
.operands
[3].reg
;
12323 reject_bad_reg (RdLo
);
12324 reject_bad_reg (RdHi
);
12325 reject_bad_reg (Rn
);
12326 reject_bad_reg (Rm
);
12328 inst
.instruction
|= RdLo
<< 12;
12329 inst
.instruction
|= RdHi
<< 8;
12330 inst
.instruction
|= Rn
<< 16;
12331 inst
.instruction
|= Rm
;
12334 as_tsktsk (_("rdhi and rdlo must be different"));
12340 set_it_insn_type (NEUTRAL_IT_INSN
);
12342 if (unified_syntax
)
12344 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12346 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12347 inst
.instruction
|= inst
.operands
[0].imm
;
12351 /* PR9722: Check for Thumb2 availability before
12352 generating a thumb2 nop instruction. */
12353 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12355 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12356 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12359 inst
.instruction
= 0x46c0;
12364 constraint (inst
.operands
[0].present
,
12365 _("Thumb does not support NOP with hints"));
12366 inst
.instruction
= 0x46c0;
12373 if (unified_syntax
)
12375 bfd_boolean narrow
;
12377 if (THUMB_SETS_FLAGS (inst
.instruction
))
12378 narrow
= !in_it_block ();
12380 narrow
= in_it_block ();
12381 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12383 if (inst
.size_req
== 4)
12388 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12389 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12390 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12394 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12395 inst
.instruction
|= inst
.operands
[0].reg
;
12396 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12401 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12403 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12405 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12406 inst
.instruction
|= inst
.operands
[0].reg
;
12407 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12416 Rd
= inst
.operands
[0].reg
;
12417 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12419 reject_bad_reg (Rd
);
12420 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12421 reject_bad_reg (Rn
);
12423 inst
.instruction
|= Rd
<< 8;
12424 inst
.instruction
|= Rn
<< 16;
12426 if (!inst
.operands
[2].isreg
)
12428 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12429 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12435 Rm
= inst
.operands
[2].reg
;
12436 reject_bad_reg (Rm
);
12438 constraint (inst
.operands
[2].shifted
12439 && inst
.operands
[2].immisreg
,
12440 _("shift must be constant"));
12441 encode_thumb32_shifted_operand (2);
12448 unsigned Rd
, Rn
, Rm
;
12450 Rd
= inst
.operands
[0].reg
;
12451 Rn
= inst
.operands
[1].reg
;
12452 Rm
= inst
.operands
[2].reg
;
12454 reject_bad_reg (Rd
);
12455 reject_bad_reg (Rn
);
12456 reject_bad_reg (Rm
);
12458 inst
.instruction
|= Rd
<< 8;
12459 inst
.instruction
|= Rn
<< 16;
12460 inst
.instruction
|= Rm
;
12461 if (inst
.operands
[3].present
)
12463 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12464 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12465 _("expression too complex"));
12466 inst
.instruction
|= (val
& 0x1c) << 10;
12467 inst
.instruction
|= (val
& 0x03) << 6;
12474 if (!inst
.operands
[3].present
)
12478 inst
.instruction
&= ~0x00000020;
12480 /* PR 10168. Swap the Rm and Rn registers. */
12481 Rtmp
= inst
.operands
[1].reg
;
12482 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12483 inst
.operands
[2].reg
= Rtmp
;
12491 if (inst
.operands
[0].immisreg
)
12492 reject_bad_reg (inst
.operands
[0].imm
);
12494 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12498 do_t_push_pop (void)
12502 constraint (inst
.operands
[0].writeback
,
12503 _("push/pop do not support {reglist}^"));
12504 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12505 _("expression too complex"));
12507 mask
= inst
.operands
[0].imm
;
12508 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12509 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12510 else if (inst
.size_req
!= 4
12511 && (mask
& ~0xff) == (1 << (inst
.instruction
== T_MNEM_push
12512 ? REG_LR
: REG_PC
)))
12514 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12515 inst
.instruction
|= THUMB_PP_PC_LR
;
12516 inst
.instruction
|= mask
& 0xff;
12518 else if (unified_syntax
)
12520 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12521 encode_thumb2_ldmstm (13, mask
, TRUE
);
12525 inst
.error
= _("invalid register list to push/pop instruction");
12535 Rd
= inst
.operands
[0].reg
;
12536 Rm
= inst
.operands
[1].reg
;
12538 reject_bad_reg (Rd
);
12539 reject_bad_reg (Rm
);
12541 inst
.instruction
|= Rd
<< 8;
12542 inst
.instruction
|= Rm
<< 16;
12543 inst
.instruction
|= Rm
;
12551 Rd
= inst
.operands
[0].reg
;
12552 Rm
= inst
.operands
[1].reg
;
12554 reject_bad_reg (Rd
);
12555 reject_bad_reg (Rm
);
12557 if (Rd
<= 7 && Rm
<= 7
12558 && inst
.size_req
!= 4)
12560 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12561 inst
.instruction
|= Rd
;
12562 inst
.instruction
|= Rm
<< 3;
12564 else if (unified_syntax
)
12566 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12567 inst
.instruction
|= Rd
<< 8;
12568 inst
.instruction
|= Rm
<< 16;
12569 inst
.instruction
|= Rm
;
12572 inst
.error
= BAD_HIREG
;
12580 Rd
= inst
.operands
[0].reg
;
12581 Rm
= inst
.operands
[1].reg
;
12583 reject_bad_reg (Rd
);
12584 reject_bad_reg (Rm
);
12586 inst
.instruction
|= Rd
<< 8;
12587 inst
.instruction
|= Rm
;
12595 Rd
= inst
.operands
[0].reg
;
12596 Rs
= (inst
.operands
[1].present
12597 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12598 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12600 reject_bad_reg (Rd
);
12601 reject_bad_reg (Rs
);
12602 if (inst
.operands
[2].isreg
)
12603 reject_bad_reg (inst
.operands
[2].reg
);
12605 inst
.instruction
|= Rd
<< 8;
12606 inst
.instruction
|= Rs
<< 16;
12607 if (!inst
.operands
[2].isreg
)
12609 bfd_boolean narrow
;
12611 if ((inst
.instruction
& 0x00100000) != 0)
12612 narrow
= !in_it_block ();
12614 narrow
= in_it_block ();
12616 if (Rd
> 7 || Rs
> 7)
12619 if (inst
.size_req
== 4 || !unified_syntax
)
12622 if (inst
.reloc
.exp
.X_op
!= O_constant
12623 || inst
.reloc
.exp
.X_add_number
!= 0)
12626 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12627 relaxation, but it doesn't seem worth the hassle. */
12630 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12631 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12632 inst
.instruction
|= Rs
<< 3;
12633 inst
.instruction
|= Rd
;
12637 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12638 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12642 encode_thumb32_shifted_operand (2);
12648 if (warn_on_deprecated
12649 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12650 as_tsktsk (_("setend use is deprecated for ARMv8"));
12652 set_it_insn_type (OUTSIDE_IT_INSN
);
12653 if (inst
.operands
[0].imm
)
12654 inst
.instruction
|= 0x8;
12660 if (!inst
.operands
[1].present
)
12661 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12663 if (unified_syntax
)
12665 bfd_boolean narrow
;
12668 switch (inst
.instruction
)
12671 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12673 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12675 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12677 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12681 if (THUMB_SETS_FLAGS (inst
.instruction
))
12682 narrow
= !in_it_block ();
12684 narrow
= in_it_block ();
12685 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12687 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12689 if (inst
.operands
[2].isreg
12690 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12691 || inst
.operands
[2].reg
> 7))
12693 if (inst
.size_req
== 4)
12696 reject_bad_reg (inst
.operands
[0].reg
);
12697 reject_bad_reg (inst
.operands
[1].reg
);
12701 if (inst
.operands
[2].isreg
)
12703 reject_bad_reg (inst
.operands
[2].reg
);
12704 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12705 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12706 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12707 inst
.instruction
|= inst
.operands
[2].reg
;
12709 /* PR 12854: Error on extraneous shifts. */
12710 constraint (inst
.operands
[2].shifted
,
12711 _("extraneous shift as part of operand to shift insn"));
12715 inst
.operands
[1].shifted
= 1;
12716 inst
.operands
[1].shift_kind
= shift_kind
;
12717 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12718 ? T_MNEM_movs
: T_MNEM_mov
);
12719 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12720 encode_thumb32_shifted_operand (1);
12721 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12722 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12727 if (inst
.operands
[2].isreg
)
12729 switch (shift_kind
)
12731 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12732 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12733 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12734 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12738 inst
.instruction
|= inst
.operands
[0].reg
;
12739 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12741 /* PR 12854: Error on extraneous shifts. */
12742 constraint (inst
.operands
[2].shifted
,
12743 _("extraneous shift as part of operand to shift insn"));
12747 switch (shift_kind
)
12749 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12750 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12751 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12754 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12755 inst
.instruction
|= inst
.operands
[0].reg
;
12756 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12762 constraint (inst
.operands
[0].reg
> 7
12763 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12764 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12766 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12768 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12769 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12770 _("source1 and dest must be same register"));
12772 switch (inst
.instruction
)
12774 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12775 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12776 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12777 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12781 inst
.instruction
|= inst
.operands
[0].reg
;
12782 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12784 /* PR 12854: Error on extraneous shifts. */
12785 constraint (inst
.operands
[2].shifted
,
12786 _("extraneous shift as part of operand to shift insn"));
12790 switch (inst
.instruction
)
12792 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12793 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12794 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12795 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12798 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12799 inst
.instruction
|= inst
.operands
[0].reg
;
12800 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12808 unsigned Rd
, Rn
, Rm
;
12810 Rd
= inst
.operands
[0].reg
;
12811 Rn
= inst
.operands
[1].reg
;
12812 Rm
= inst
.operands
[2].reg
;
12814 reject_bad_reg (Rd
);
12815 reject_bad_reg (Rn
);
12816 reject_bad_reg (Rm
);
12818 inst
.instruction
|= Rd
<< 8;
12819 inst
.instruction
|= Rn
<< 16;
12820 inst
.instruction
|= Rm
;
12826 unsigned Rd
, Rn
, Rm
;
12828 Rd
= inst
.operands
[0].reg
;
12829 Rm
= inst
.operands
[1].reg
;
12830 Rn
= inst
.operands
[2].reg
;
12832 reject_bad_reg (Rd
);
12833 reject_bad_reg (Rn
);
12834 reject_bad_reg (Rm
);
12836 inst
.instruction
|= Rd
<< 8;
12837 inst
.instruction
|= Rn
<< 16;
12838 inst
.instruction
|= Rm
;
12844 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12845 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12846 _("SMC is not permitted on this architecture"));
12847 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12848 _("expression too complex"));
12849 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12850 inst
.instruction
|= (value
& 0xf000) >> 12;
12851 inst
.instruction
|= (value
& 0x0ff0);
12852 inst
.instruction
|= (value
& 0x000f) << 16;
12853 /* PR gas/15623: SMC instructions must be last in an IT block. */
12854 set_it_insn_type_last ();
12860 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12862 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12863 inst
.instruction
|= (value
& 0x0fff);
12864 inst
.instruction
|= (value
& 0xf000) << 4;
12868 do_t_ssat_usat (int bias
)
12872 Rd
= inst
.operands
[0].reg
;
12873 Rn
= inst
.operands
[2].reg
;
12875 reject_bad_reg (Rd
);
12876 reject_bad_reg (Rn
);
12878 inst
.instruction
|= Rd
<< 8;
12879 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12880 inst
.instruction
|= Rn
<< 16;
12882 if (inst
.operands
[3].present
)
12884 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12886 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12888 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12889 _("expression too complex"));
12891 if (shift_amount
!= 0)
12893 constraint (shift_amount
> 31,
12894 _("shift expression is too large"));
12896 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12897 inst
.instruction
|= 0x00200000; /* sh bit. */
12899 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12900 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12908 do_t_ssat_usat (1);
12916 Rd
= inst
.operands
[0].reg
;
12917 Rn
= inst
.operands
[2].reg
;
12919 reject_bad_reg (Rd
);
12920 reject_bad_reg (Rn
);
12922 inst
.instruction
|= Rd
<< 8;
12923 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12924 inst
.instruction
|= Rn
<< 16;
12930 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12931 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12932 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12933 || inst
.operands
[2].negative
,
12936 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12938 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12939 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12940 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12941 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12947 if (!inst
.operands
[2].present
)
12948 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12950 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12951 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12952 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12955 inst
.instruction
|= inst
.operands
[0].reg
;
12956 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12957 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12958 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12964 unsigned Rd
, Rn
, Rm
;
12966 Rd
= inst
.operands
[0].reg
;
12967 Rn
= inst
.operands
[1].reg
;
12968 Rm
= inst
.operands
[2].reg
;
12970 reject_bad_reg (Rd
);
12971 reject_bad_reg (Rn
);
12972 reject_bad_reg (Rm
);
12974 inst
.instruction
|= Rd
<< 8;
12975 inst
.instruction
|= Rn
<< 16;
12976 inst
.instruction
|= Rm
;
12977 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
12985 Rd
= inst
.operands
[0].reg
;
12986 Rm
= inst
.operands
[1].reg
;
12988 reject_bad_reg (Rd
);
12989 reject_bad_reg (Rm
);
12991 if (inst
.instruction
<= 0xffff
12992 && inst
.size_req
!= 4
12993 && Rd
<= 7 && Rm
<= 7
12994 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
12996 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12997 inst
.instruction
|= Rd
;
12998 inst
.instruction
|= Rm
<< 3;
13000 else if (unified_syntax
)
13002 if (inst
.instruction
<= 0xffff)
13003 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13004 inst
.instruction
|= Rd
<< 8;
13005 inst
.instruction
|= Rm
;
13006 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13010 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13011 _("Thumb encoding does not support rotation"));
13012 constraint (1, BAD_HIREG
);
13019 /* We have to do the following check manually as ARM_EXT_OS only applies
13021 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
13023 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
13024 /* This only applies to the v6m howver, not later architectures. */
13025 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
13026 as_bad (_("SVC is not permitted on this architecture"));
13027 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
13030 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13039 half
= (inst
.instruction
& 0x10) != 0;
13040 set_it_insn_type_last ();
13041 constraint (inst
.operands
[0].immisreg
,
13042 _("instruction requires register index"));
13044 Rn
= inst
.operands
[0].reg
;
13045 Rm
= inst
.operands
[0].imm
;
13047 constraint (Rn
== REG_SP
, BAD_SP
);
13048 reject_bad_reg (Rm
);
13050 constraint (!half
&& inst
.operands
[0].shifted
,
13051 _("instruction does not allow shifted index"));
13052 inst
.instruction
|= (Rn
<< 16) | Rm
;
13058 if (!inst
.operands
[0].present
)
13059 inst
.operands
[0].imm
= 0;
13061 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13063 constraint (inst
.size_req
== 2,
13064 _("immediate value out of range"));
13065 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13066 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13067 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13071 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13072 inst
.instruction
|= inst
.operands
[0].imm
;
13075 set_it_insn_type (NEUTRAL_IT_INSN
);
13082 do_t_ssat_usat (0);
13090 Rd
= inst
.operands
[0].reg
;
13091 Rn
= inst
.operands
[2].reg
;
13093 reject_bad_reg (Rd
);
13094 reject_bad_reg (Rn
);
13096 inst
.instruction
|= Rd
<< 8;
13097 inst
.instruction
|= inst
.operands
[1].imm
;
13098 inst
.instruction
|= Rn
<< 16;
13101 /* Neon instruction encoder helpers. */
13103 /* Encodings for the different types for various Neon opcodes. */
13105 /* An "invalid" code for the following tables. */
13108 struct neon_tab_entry
13111 unsigned float_or_poly
;
13112 unsigned scalar_or_imm
;
13115 /* Map overloaded Neon opcodes to their respective encodings. */
13116 #define NEON_ENC_TAB \
13117 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13118 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13119 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13120 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13121 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13122 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13123 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13124 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13125 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13126 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13127 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13128 /* Register variants of the following two instructions are encoded as
13129 vcge / vcgt with the operands reversed. */ \
13130 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13131 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13132 X(vfma, N_INV, 0x0000c10, N_INV), \
13133 X(vfms, N_INV, 0x0200c10, N_INV), \
13134 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13135 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13136 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13137 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13138 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13139 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13140 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13141 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13142 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13143 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13144 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13145 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13146 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13147 X(vshl, 0x0000400, N_INV, 0x0800510), \
13148 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13149 X(vand, 0x0000110, N_INV, 0x0800030), \
13150 X(vbic, 0x0100110, N_INV, 0x0800030), \
13151 X(veor, 0x1000110, N_INV, N_INV), \
13152 X(vorn, 0x0300110, N_INV, 0x0800010), \
13153 X(vorr, 0x0200110, N_INV, 0x0800010), \
13154 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13155 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13156 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13157 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13158 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13159 X(vst1, 0x0000000, 0x0800000, N_INV), \
13160 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13161 X(vst2, 0x0000100, 0x0800100, N_INV), \
13162 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13163 X(vst3, 0x0000200, 0x0800200, N_INV), \
13164 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13165 X(vst4, 0x0000300, 0x0800300, N_INV), \
13166 X(vmovn, 0x1b20200, N_INV, N_INV), \
13167 X(vtrn, 0x1b20080, N_INV, N_INV), \
13168 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13169 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13170 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13171 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13172 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13173 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13174 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13175 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13176 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13177 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13178 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13179 X(vseleq, 0xe000a00, N_INV, N_INV), \
13180 X(vselvs, 0xe100a00, N_INV, N_INV), \
13181 X(vselge, 0xe200a00, N_INV, N_INV), \
13182 X(vselgt, 0xe300a00, N_INV, N_INV), \
13183 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13184 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13185 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13186 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13187 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13188 X(aes, 0x3b00300, N_INV, N_INV), \
13189 X(sha3op, 0x2000c00, N_INV, N_INV), \
13190 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13191 X(sha2op, 0x3ba0380, N_INV, N_INV)
13195 #define X(OPC,I,F,S) N_MNEM_##OPC
13200 static const struct neon_tab_entry neon_enc_tab
[] =
13202 #define X(OPC,I,F,S) { (I), (F), (S) }
13207 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13208 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13209 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13210 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13211 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13212 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13213 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13214 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13215 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13216 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13217 #define NEON_ENC_SINGLE_(X) \
13218 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13219 #define NEON_ENC_DOUBLE_(X) \
13220 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13221 #define NEON_ENC_FPV8_(X) \
13222 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13224 #define NEON_ENCODE(type, inst) \
13227 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13228 inst.is_neon = 1; \
13232 #define check_neon_suffixes \
13235 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13237 as_bad (_("invalid neon suffix for non neon instruction")); \
13243 /* Define shapes for instruction operands. The following mnemonic characters
13244 are used in this table:
13246 F - VFP S<n> register
13247 D - Neon D<n> register
13248 Q - Neon Q<n> register
13252 L - D<n> register list
13254 This table is used to generate various data:
13255 - enumerations of the form NS_DDR to be used as arguments to
13257 - a table classifying shapes into single, double, quad, mixed.
13258 - a table used to drive neon_select_shape. */
13260 #define NEON_SHAPE_DEF \
13261 X(3, (D, D, D), DOUBLE), \
13262 X(3, (Q, Q, Q), QUAD), \
13263 X(3, (D, D, I), DOUBLE), \
13264 X(3, (Q, Q, I), QUAD), \
13265 X(3, (D, D, S), DOUBLE), \
13266 X(3, (Q, Q, S), QUAD), \
13267 X(2, (D, D), DOUBLE), \
13268 X(2, (Q, Q), QUAD), \
13269 X(2, (D, S), DOUBLE), \
13270 X(2, (Q, S), QUAD), \
13271 X(2, (D, R), DOUBLE), \
13272 X(2, (Q, R), QUAD), \
13273 X(2, (D, I), DOUBLE), \
13274 X(2, (Q, I), QUAD), \
13275 X(3, (D, L, D), DOUBLE), \
13276 X(2, (D, Q), MIXED), \
13277 X(2, (Q, D), MIXED), \
13278 X(3, (D, Q, I), MIXED), \
13279 X(3, (Q, D, I), MIXED), \
13280 X(3, (Q, D, D), MIXED), \
13281 X(3, (D, Q, Q), MIXED), \
13282 X(3, (Q, Q, D), MIXED), \
13283 X(3, (Q, D, S), MIXED), \
13284 X(3, (D, Q, S), MIXED), \
13285 X(4, (D, D, D, I), DOUBLE), \
13286 X(4, (Q, Q, Q, I), QUAD), \
13287 X(2, (F, F), SINGLE), \
13288 X(3, (F, F, F), SINGLE), \
13289 X(2, (F, I), SINGLE), \
13290 X(2, (F, D), MIXED), \
13291 X(2, (D, F), MIXED), \
13292 X(3, (F, F, I), MIXED), \
13293 X(4, (R, R, F, F), SINGLE), \
13294 X(4, (F, F, R, R), SINGLE), \
13295 X(3, (D, R, R), DOUBLE), \
13296 X(3, (R, R, D), DOUBLE), \
13297 X(2, (S, R), SINGLE), \
13298 X(2, (R, S), SINGLE), \
13299 X(2, (F, R), SINGLE), \
13300 X(2, (R, F), SINGLE), \
13301 /* Half float shape supported so far. */\
13302 X (2, (H, D), MIXED), \
13303 X (2, (D, H), MIXED), \
13304 X (2, (H, F), MIXED), \
13305 X (2, (F, H), MIXED), \
13306 X (2, (H, H), HALF), \
13307 X (2, (H, R), HALF), \
13308 X (2, (R, H), HALF), \
13309 X (2, (H, I), HALF), \
13310 X (3, (H, H, H), HALF), \
13311 X (3, (H, F, I), MIXED), \
13312 X (3, (F, H, I), MIXED)
13314 #define S2(A,B) NS_##A##B
13315 #define S3(A,B,C) NS_##A##B##C
13316 #define S4(A,B,C,D) NS_##A##B##C##D
13318 #define X(N, L, C) S##N L
13331 enum neon_shape_class
13340 #define X(N, L, C) SC_##C
13342 static enum neon_shape_class neon_shape_class
[] =
13361 /* Register widths of above. */
13362 static unsigned neon_shape_el_size
[] =
13374 struct neon_shape_info
13377 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13380 #define S2(A,B) { SE_##A, SE_##B }
13381 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13382 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13384 #define X(N, L, C) { N, S##N L }
13386 static struct neon_shape_info neon_shape_tab
[] =
13396 /* Bit masks used in type checking given instructions.
13397 'N_EQK' means the type must be the same as (or based on in some way) the key
13398 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13399 set, various other bits can be set as well in order to modify the meaning of
13400 the type constraint. */
13402 enum neon_type_mask
13426 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13427 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13428 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13429 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13430 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13431 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13432 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13433 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13434 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13435 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13436 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13438 N_MAX_NONSPECIAL
= N_P64
13441 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13443 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13444 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13445 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13446 #define N_SUF_32 (N_SU_32 | N_F32)
13447 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13448 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
13449 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13451 /* Pass this as the first type argument to neon_check_type to ignore types
13453 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13455 /* Select a "shape" for the current instruction (describing register types or
13456 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13457 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13458 function of operand parsing, so this function doesn't need to be called.
13459 Shapes should be listed in order of decreasing length. */
13461 static enum neon_shape
13462 neon_select_shape (enum neon_shape shape
, ...)
13465 enum neon_shape first_shape
= shape
;
13467 /* Fix missing optional operands. FIXME: we don't know at this point how
13468 many arguments we should have, so this makes the assumption that we have
13469 > 1. This is true of all current Neon opcodes, I think, but may not be
13470 true in the future. */
13471 if (!inst
.operands
[1].present
)
13472 inst
.operands
[1] = inst
.operands
[0];
13474 va_start (ap
, shape
);
13476 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13481 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13483 if (!inst
.operands
[j
].present
)
13489 switch (neon_shape_tab
[shape
].el
[j
])
13491 /* If a .f16, .16, .u16, .s16 type specifier is given over
13492 a VFP single precision register operand, it's essentially
13493 means only half of the register is used.
13495 If the type specifier is given after the mnemonics, the
13496 information is stored in inst.vectype. If the type specifier
13497 is given after register operand, the information is stored
13498 in inst.operands[].vectype.
13500 When there is only one type specifier, and all the register
13501 operands are the same type of hardware register, the type
13502 specifier applies to all register operands.
13504 If no type specifier is given, the shape is inferred from
13505 operand information.
13508 vadd.f16 s0, s1, s2: NS_HHH
13509 vabs.f16 s0, s1: NS_HH
13510 vmov.f16 s0, r1: NS_HR
13511 vmov.f16 r0, s1: NS_RH
13512 vcvt.f16 r0, s1: NS_RH
13513 vcvt.f16.s32 s2, s2, #29: NS_HFI
13514 vcvt.f16.s32 s2, s2: NS_HF
13517 if (!(inst
.operands
[j
].isreg
13518 && inst
.operands
[j
].isvec
13519 && inst
.operands
[j
].issingle
13520 && !inst
.operands
[j
].isquad
13521 && ((inst
.vectype
.elems
== 1
13522 && inst
.vectype
.el
[0].size
== 16)
13523 || (inst
.vectype
.elems
> 1
13524 && inst
.vectype
.el
[j
].size
== 16)
13525 || (inst
.vectype
.elems
== 0
13526 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13527 && inst
.operands
[j
].vectype
.size
== 16))))
13532 if (!(inst
.operands
[j
].isreg
13533 && inst
.operands
[j
].isvec
13534 && inst
.operands
[j
].issingle
13535 && !inst
.operands
[j
].isquad
13536 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13537 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13538 || (inst
.vectype
.elems
== 0
13539 && (inst
.operands
[j
].vectype
.size
== 32
13540 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13545 if (!(inst
.operands
[j
].isreg
13546 && inst
.operands
[j
].isvec
13547 && !inst
.operands
[j
].isquad
13548 && !inst
.operands
[j
].issingle
))
13553 if (!(inst
.operands
[j
].isreg
13554 && !inst
.operands
[j
].isvec
))
13559 if (!(inst
.operands
[j
].isreg
13560 && inst
.operands
[j
].isvec
13561 && inst
.operands
[j
].isquad
13562 && !inst
.operands
[j
].issingle
))
13567 if (!(!inst
.operands
[j
].isreg
13568 && !inst
.operands
[j
].isscalar
))
13573 if (!(!inst
.operands
[j
].isreg
13574 && inst
.operands
[j
].isscalar
))
13584 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13585 /* We've matched all the entries in the shape table, and we don't
13586 have any left over operands which have not been matched. */
13592 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13593 first_error (_("invalid instruction shape"));
13598 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13599 means the Q bit should be set). */
13602 neon_quad (enum neon_shape shape
)
13604 return neon_shape_class
[shape
] == SC_QUAD
;
13608 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13611 /* Allow modification to be made to types which are constrained to be
13612 based on the key element, based on bits set alongside N_EQK. */
13613 if ((typebits
& N_EQK
) != 0)
13615 if ((typebits
& N_HLF
) != 0)
13617 else if ((typebits
& N_DBL
) != 0)
13619 if ((typebits
& N_SGN
) != 0)
13620 *g_type
= NT_signed
;
13621 else if ((typebits
& N_UNS
) != 0)
13622 *g_type
= NT_unsigned
;
13623 else if ((typebits
& N_INT
) != 0)
13624 *g_type
= NT_integer
;
13625 else if ((typebits
& N_FLT
) != 0)
13626 *g_type
= NT_float
;
13627 else if ((typebits
& N_SIZ
) != 0)
13628 *g_type
= NT_untyped
;
13632 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13633 operand type, i.e. the single type specified in a Neon instruction when it
13634 is the only one given. */
13636 static struct neon_type_el
13637 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13639 struct neon_type_el dest
= *key
;
13641 gas_assert ((thisarg
& N_EQK
) != 0);
13643 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13648 /* Convert Neon type and size into compact bitmask representation. */
13650 static enum neon_type_mask
13651 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13658 case 8: return N_8
;
13659 case 16: return N_16
;
13660 case 32: return N_32
;
13661 case 64: return N_64
;
13669 case 8: return N_I8
;
13670 case 16: return N_I16
;
13671 case 32: return N_I32
;
13672 case 64: return N_I64
;
13680 case 16: return N_F16
;
13681 case 32: return N_F32
;
13682 case 64: return N_F64
;
13690 case 8: return N_P8
;
13691 case 16: return N_P16
;
13692 case 64: return N_P64
;
13700 case 8: return N_S8
;
13701 case 16: return N_S16
;
13702 case 32: return N_S32
;
13703 case 64: return N_S64
;
13711 case 8: return N_U8
;
13712 case 16: return N_U16
;
13713 case 32: return N_U32
;
13714 case 64: return N_U64
;
13725 /* Convert compact Neon bitmask type representation to a type and size. Only
13726 handles the case where a single bit is set in the mask. */
13729 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13730 enum neon_type_mask mask
)
13732 if ((mask
& N_EQK
) != 0)
13735 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13737 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13739 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13741 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13746 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13748 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13749 *type
= NT_unsigned
;
13750 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13751 *type
= NT_integer
;
13752 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13753 *type
= NT_untyped
;
13754 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13756 else if ((mask
& (N_F_ALL
)) != 0)
13764 /* Modify a bitmask of allowed types. This is only needed for type
13768 modify_types_allowed (unsigned allowed
, unsigned mods
)
13771 enum neon_el_type type
;
13777 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13779 if (el_type_of_type_chk (&type
, &size
,
13780 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13782 neon_modify_type_size (mods
, &type
, &size
);
13783 destmask
|= type_chk_of_el_type (type
, size
);
13790 /* Check type and return type classification.
13791 The manual states (paraphrase): If one datatype is given, it indicates the
13793 - the second operand, if there is one
13794 - the operand, if there is no second operand
13795 - the result, if there are no operands.
13796 This isn't quite good enough though, so we use a concept of a "key" datatype
13797 which is set on a per-instruction basis, which is the one which matters when
13798 only one data type is written.
13799 Note: this function has side-effects (e.g. filling in missing operands). All
13800 Neon instructions should call it before performing bit encoding. */
13802 static struct neon_type_el
13803 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13806 unsigned i
, pass
, key_el
= 0;
13807 unsigned types
[NEON_MAX_TYPE_ELS
];
13808 enum neon_el_type k_type
= NT_invtype
;
13809 unsigned k_size
= -1u;
13810 struct neon_type_el badtype
= {NT_invtype
, -1};
13811 unsigned key_allowed
= 0;
13813 /* Optional registers in Neon instructions are always (not) in operand 1.
13814 Fill in the missing operand here, if it was omitted. */
13815 if (els
> 1 && !inst
.operands
[1].present
)
13816 inst
.operands
[1] = inst
.operands
[0];
13818 /* Suck up all the varargs. */
13820 for (i
= 0; i
< els
; i
++)
13822 unsigned thisarg
= va_arg (ap
, unsigned);
13823 if (thisarg
== N_IGNORE_TYPE
)
13828 types
[i
] = thisarg
;
13829 if ((thisarg
& N_KEY
) != 0)
13834 if (inst
.vectype
.elems
> 0)
13835 for (i
= 0; i
< els
; i
++)
13836 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13838 first_error (_("types specified in both the mnemonic and operands"));
13842 /* Duplicate inst.vectype elements here as necessary.
13843 FIXME: No idea if this is exactly the same as the ARM assembler,
13844 particularly when an insn takes one register and one non-register
13846 if (inst
.vectype
.elems
== 1 && els
> 1)
13849 inst
.vectype
.elems
= els
;
13850 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13851 for (j
= 0; j
< els
; j
++)
13853 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13856 else if (inst
.vectype
.elems
== 0 && els
> 0)
13859 /* No types were given after the mnemonic, so look for types specified
13860 after each operand. We allow some flexibility here; as long as the
13861 "key" operand has a type, we can infer the others. */
13862 for (j
= 0; j
< els
; j
++)
13863 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13864 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13866 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13868 for (j
= 0; j
< els
; j
++)
13869 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13870 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13875 first_error (_("operand types can't be inferred"));
13879 else if (inst
.vectype
.elems
!= els
)
13881 first_error (_("type specifier has the wrong number of parts"));
13885 for (pass
= 0; pass
< 2; pass
++)
13887 for (i
= 0; i
< els
; i
++)
13889 unsigned thisarg
= types
[i
];
13890 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13891 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13892 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13893 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13895 /* Decay more-specific signed & unsigned types to sign-insensitive
13896 integer types if sign-specific variants are unavailable. */
13897 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13898 && (types_allowed
& N_SU_ALL
) == 0)
13899 g_type
= NT_integer
;
13901 /* If only untyped args are allowed, decay any more specific types to
13902 them. Some instructions only care about signs for some element
13903 sizes, so handle that properly. */
13904 if (((types_allowed
& N_UNT
) == 0)
13905 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13906 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13907 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13908 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13909 g_type
= NT_untyped
;
13913 if ((thisarg
& N_KEY
) != 0)
13917 key_allowed
= thisarg
& ~N_KEY
;
13922 if ((thisarg
& N_VFP
) != 0)
13924 enum neon_shape_el regshape
;
13925 unsigned regwidth
, match
;
13927 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13930 first_error (_("invalid instruction shape"));
13933 regshape
= neon_shape_tab
[ns
].el
[i
];
13934 regwidth
= neon_shape_el_size
[regshape
];
13936 /* In VFP mode, operands must match register widths. If we
13937 have a key operand, use its width, else use the width of
13938 the current operand. */
13944 /* FP16 will use a single precision register. */
13945 if (regwidth
== 32 && match
== 16)
13947 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
13951 inst
.error
= _(BAD_FP16
);
13956 if (regwidth
!= match
)
13958 first_error (_("operand size must match register width"));
13963 if ((thisarg
& N_EQK
) == 0)
13965 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
13967 if ((given_type
& types_allowed
) == 0)
13969 first_error (_("bad type in Neon instruction"));
13975 enum neon_el_type mod_k_type
= k_type
;
13976 unsigned mod_k_size
= k_size
;
13977 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
13978 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
13980 first_error (_("inconsistent types in Neon instruction"));
13988 return inst
.vectype
.el
[key_el
];
13991 /* Neon-style VFP instruction forwarding. */
13993 /* Thumb VFP instructions have 0xE in the condition field. */
13996 do_vfp_cond_or_thumb (void)
14001 inst
.instruction
|= 0xe0000000;
14003 inst
.instruction
|= inst
.cond
<< 28;
14006 /* Look up and encode a simple mnemonic, for use as a helper function for the
14007 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14008 etc. It is assumed that operand parsing has already been done, and that the
14009 operands are in the form expected by the given opcode (this isn't necessarily
14010 the same as the form in which they were parsed, hence some massaging must
14011 take place before this function is called).
14012 Checks current arch version against that in the looked-up opcode. */
14015 do_vfp_nsyn_opcode (const char *opname
)
14017 const struct asm_opcode
*opcode
;
14019 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14024 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14025 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14032 inst
.instruction
= opcode
->tvalue
;
14033 opcode
->tencode ();
14037 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14038 opcode
->aencode ();
14043 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14045 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14047 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14050 do_vfp_nsyn_opcode ("fadds");
14052 do_vfp_nsyn_opcode ("fsubs");
14054 /* ARMv8.2 fp16 instruction. */
14056 do_scalar_fp16_v82_encode ();
14061 do_vfp_nsyn_opcode ("faddd");
14063 do_vfp_nsyn_opcode ("fsubd");
14067 /* Check operand types to see if this is a VFP instruction, and if so call
14071 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14073 enum neon_shape rs
;
14074 struct neon_type_el et
;
14079 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14080 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14084 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14085 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14086 N_F_ALL
| N_KEY
| N_VFP
);
14093 if (et
.type
!= NT_invtype
)
14104 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14106 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14108 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14111 do_vfp_nsyn_opcode ("fmacs");
14113 do_vfp_nsyn_opcode ("fnmacs");
14115 /* ARMv8.2 fp16 instruction. */
14117 do_scalar_fp16_v82_encode ();
14122 do_vfp_nsyn_opcode ("fmacd");
14124 do_vfp_nsyn_opcode ("fnmacd");
14129 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14131 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14133 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14136 do_vfp_nsyn_opcode ("ffmas");
14138 do_vfp_nsyn_opcode ("ffnmas");
14140 /* ARMv8.2 fp16 instruction. */
14142 do_scalar_fp16_v82_encode ();
14147 do_vfp_nsyn_opcode ("ffmad");
14149 do_vfp_nsyn_opcode ("ffnmad");
14154 do_vfp_nsyn_mul (enum neon_shape rs
)
14156 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14158 do_vfp_nsyn_opcode ("fmuls");
14160 /* ARMv8.2 fp16 instruction. */
14162 do_scalar_fp16_v82_encode ();
14165 do_vfp_nsyn_opcode ("fmuld");
14169 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14171 int is_neg
= (inst
.instruction
& 0x80) != 0;
14172 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14174 if (rs
== NS_FF
|| rs
== NS_HH
)
14177 do_vfp_nsyn_opcode ("fnegs");
14179 do_vfp_nsyn_opcode ("fabss");
14181 /* ARMv8.2 fp16 instruction. */
14183 do_scalar_fp16_v82_encode ();
14188 do_vfp_nsyn_opcode ("fnegd");
14190 do_vfp_nsyn_opcode ("fabsd");
14194 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14195 insns belong to Neon, and are handled elsewhere. */
14198 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14200 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14204 do_vfp_nsyn_opcode ("fldmdbs");
14206 do_vfp_nsyn_opcode ("fldmias");
14211 do_vfp_nsyn_opcode ("fstmdbs");
14213 do_vfp_nsyn_opcode ("fstmias");
14218 do_vfp_nsyn_sqrt (void)
14220 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14221 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14223 if (rs
== NS_FF
|| rs
== NS_HH
)
14225 do_vfp_nsyn_opcode ("fsqrts");
14227 /* ARMv8.2 fp16 instruction. */
14229 do_scalar_fp16_v82_encode ();
14232 do_vfp_nsyn_opcode ("fsqrtd");
14236 do_vfp_nsyn_div (void)
14238 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14239 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14240 N_F_ALL
| N_KEY
| N_VFP
);
14242 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14244 do_vfp_nsyn_opcode ("fdivs");
14246 /* ARMv8.2 fp16 instruction. */
14248 do_scalar_fp16_v82_encode ();
14251 do_vfp_nsyn_opcode ("fdivd");
14255 do_vfp_nsyn_nmul (void)
14257 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14258 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14259 N_F_ALL
| N_KEY
| N_VFP
);
14261 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14263 NEON_ENCODE (SINGLE
, inst
);
14264 do_vfp_sp_dyadic ();
14266 /* ARMv8.2 fp16 instruction. */
14268 do_scalar_fp16_v82_encode ();
14272 NEON_ENCODE (DOUBLE
, inst
);
14273 do_vfp_dp_rd_rn_rm ();
14275 do_vfp_cond_or_thumb ();
14280 do_vfp_nsyn_cmp (void)
14282 enum neon_shape rs
;
14283 if (inst
.operands
[1].isreg
)
14285 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14286 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14288 if (rs
== NS_FF
|| rs
== NS_HH
)
14290 NEON_ENCODE (SINGLE
, inst
);
14291 do_vfp_sp_monadic ();
14295 NEON_ENCODE (DOUBLE
, inst
);
14296 do_vfp_dp_rd_rm ();
14301 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14302 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14304 switch (inst
.instruction
& 0x0fffffff)
14307 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14310 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14316 if (rs
== NS_FI
|| rs
== NS_HI
)
14318 NEON_ENCODE (SINGLE
, inst
);
14319 do_vfp_sp_compare_z ();
14323 NEON_ENCODE (DOUBLE
, inst
);
14327 do_vfp_cond_or_thumb ();
14329 /* ARMv8.2 fp16 instruction. */
14330 if (rs
== NS_HI
|| rs
== NS_HH
)
14331 do_scalar_fp16_v82_encode ();
14335 nsyn_insert_sp (void)
14337 inst
.operands
[1] = inst
.operands
[0];
14338 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14339 inst
.operands
[0].reg
= REG_SP
;
14340 inst
.operands
[0].isreg
= 1;
14341 inst
.operands
[0].writeback
= 1;
14342 inst
.operands
[0].present
= 1;
14346 do_vfp_nsyn_push (void)
14349 if (inst
.operands
[1].issingle
)
14350 do_vfp_nsyn_opcode ("fstmdbs");
14352 do_vfp_nsyn_opcode ("fstmdbd");
14356 do_vfp_nsyn_pop (void)
14359 if (inst
.operands
[1].issingle
)
14360 do_vfp_nsyn_opcode ("fldmias");
14362 do_vfp_nsyn_opcode ("fldmiad");
14365 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14366 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14369 neon_dp_fixup (struct arm_it
* insn
)
14371 unsigned int i
= insn
->instruction
;
14376 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14387 insn
->instruction
= i
;
14390 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14394 neon_logbits (unsigned x
)
14396 return ffs (x
) - 4;
14399 #define LOW4(R) ((R) & 0xf)
14400 #define HI1(R) (((R) >> 4) & 1)
14402 /* Encode insns with bit pattern:
14404 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14405 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14407 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14408 different meaning for some instruction. */
14411 neon_three_same (int isquad
, int ubit
, int size
)
14413 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14414 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14415 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14416 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14417 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14418 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14419 inst
.instruction
|= (isquad
!= 0) << 6;
14420 inst
.instruction
|= (ubit
!= 0) << 24;
14422 inst
.instruction
|= neon_logbits (size
) << 20;
14424 neon_dp_fixup (&inst
);
14427 /* Encode instructions of the form:
14429 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14430 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14432 Don't write size if SIZE == -1. */
14435 neon_two_same (int qbit
, int ubit
, int size
)
14437 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14438 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14439 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14440 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14441 inst
.instruction
|= (qbit
!= 0) << 6;
14442 inst
.instruction
|= (ubit
!= 0) << 24;
14445 inst
.instruction
|= neon_logbits (size
) << 18;
14447 neon_dp_fixup (&inst
);
14450 /* Neon instruction encoders, in approximate order of appearance. */
14453 do_neon_dyadic_i_su (void)
14455 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14456 struct neon_type_el et
= neon_check_type (3, rs
,
14457 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14458 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14462 do_neon_dyadic_i64_su (void)
14464 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14465 struct neon_type_el et
= neon_check_type (3, rs
,
14466 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14467 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14471 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14474 unsigned size
= et
.size
>> 3;
14475 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14476 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14477 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14478 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14479 inst
.instruction
|= (isquad
!= 0) << 6;
14480 inst
.instruction
|= immbits
<< 16;
14481 inst
.instruction
|= (size
>> 3) << 7;
14482 inst
.instruction
|= (size
& 0x7) << 19;
14484 inst
.instruction
|= (uval
!= 0) << 24;
14486 neon_dp_fixup (&inst
);
14490 do_neon_shl_imm (void)
14492 if (!inst
.operands
[2].isreg
)
14494 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14495 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14496 int imm
= inst
.operands
[2].imm
;
14498 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14499 _("immediate out of range for shift"));
14500 NEON_ENCODE (IMMED
, inst
);
14501 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14505 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14506 struct neon_type_el et
= neon_check_type (3, rs
,
14507 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14510 /* VSHL/VQSHL 3-register variants have syntax such as:
14512 whereas other 3-register operations encoded by neon_three_same have
14515 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14517 tmp
= inst
.operands
[2].reg
;
14518 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14519 inst
.operands
[1].reg
= tmp
;
14520 NEON_ENCODE (INTEGER
, inst
);
14521 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14526 do_neon_qshl_imm (void)
14528 if (!inst
.operands
[2].isreg
)
14530 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14531 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14532 int imm
= inst
.operands
[2].imm
;
14534 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14535 _("immediate out of range for shift"));
14536 NEON_ENCODE (IMMED
, inst
);
14537 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14541 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14542 struct neon_type_el et
= neon_check_type (3, rs
,
14543 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14546 /* See note in do_neon_shl_imm. */
14547 tmp
= inst
.operands
[2].reg
;
14548 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14549 inst
.operands
[1].reg
= tmp
;
14550 NEON_ENCODE (INTEGER
, inst
);
14551 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14556 do_neon_rshl (void)
14558 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14559 struct neon_type_el et
= neon_check_type (3, rs
,
14560 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14563 tmp
= inst
.operands
[2].reg
;
14564 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14565 inst
.operands
[1].reg
= tmp
;
14566 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14570 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14572 /* Handle .I8 pseudo-instructions. */
14575 /* Unfortunately, this will make everything apart from zero out-of-range.
14576 FIXME is this the intended semantics? There doesn't seem much point in
14577 accepting .I8 if so. */
14578 immediate
|= immediate
<< 8;
14584 if (immediate
== (immediate
& 0x000000ff))
14586 *immbits
= immediate
;
14589 else if (immediate
== (immediate
& 0x0000ff00))
14591 *immbits
= immediate
>> 8;
14594 else if (immediate
== (immediate
& 0x00ff0000))
14596 *immbits
= immediate
>> 16;
14599 else if (immediate
== (immediate
& 0xff000000))
14601 *immbits
= immediate
>> 24;
14604 if ((immediate
& 0xffff) != (immediate
>> 16))
14605 goto bad_immediate
;
14606 immediate
&= 0xffff;
14609 if (immediate
== (immediate
& 0x000000ff))
14611 *immbits
= immediate
;
14614 else if (immediate
== (immediate
& 0x0000ff00))
14616 *immbits
= immediate
>> 8;
14621 first_error (_("immediate value out of range"));
14626 do_neon_logic (void)
14628 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14630 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14631 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14632 /* U bit and size field were set as part of the bitmask. */
14633 NEON_ENCODE (INTEGER
, inst
);
14634 neon_three_same (neon_quad (rs
), 0, -1);
14638 const int three_ops_form
= (inst
.operands
[2].present
14639 && !inst
.operands
[2].isreg
);
14640 const int immoperand
= (three_ops_form
? 2 : 1);
14641 enum neon_shape rs
= (three_ops_form
14642 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14643 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14644 struct neon_type_el et
= neon_check_type (2, rs
,
14645 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14646 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14650 if (et
.type
== NT_invtype
)
14653 if (three_ops_form
)
14654 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14655 _("first and second operands shall be the same register"));
14657 NEON_ENCODE (IMMED
, inst
);
14659 immbits
= inst
.operands
[immoperand
].imm
;
14662 /* .i64 is a pseudo-op, so the immediate must be a repeating
14664 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14665 inst
.operands
[immoperand
].reg
: 0))
14667 /* Set immbits to an invalid constant. */
14668 immbits
= 0xdeadbeef;
14675 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14679 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14683 /* Pseudo-instruction for VBIC. */
14684 neon_invert_size (&immbits
, 0, et
.size
);
14685 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14689 /* Pseudo-instruction for VORR. */
14690 neon_invert_size (&immbits
, 0, et
.size
);
14691 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14701 inst
.instruction
|= neon_quad (rs
) << 6;
14702 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14703 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14704 inst
.instruction
|= cmode
<< 8;
14705 neon_write_immbits (immbits
);
14707 neon_dp_fixup (&inst
);
14712 do_neon_bitfield (void)
14714 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14715 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14716 neon_three_same (neon_quad (rs
), 0, -1);
14720 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14723 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14724 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14726 if (et
.type
== NT_float
)
14728 NEON_ENCODE (FLOAT
, inst
);
14729 neon_three_same (neon_quad (rs
), 0, -1);
14733 NEON_ENCODE (INTEGER
, inst
);
14734 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14739 do_neon_dyadic_if_su (void)
14741 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14745 do_neon_dyadic_if_su_d (void)
14747 /* This version only allow D registers, but that constraint is enforced during
14748 operand parsing so we don't need to do anything extra here. */
14749 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14753 do_neon_dyadic_if_i_d (void)
14755 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14756 affected if we specify unsigned args. */
14757 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14760 enum vfp_or_neon_is_neon_bits
14763 NEON_CHECK_ARCH
= 2,
14764 NEON_CHECK_ARCH8
= 4
14767 /* Call this function if an instruction which may have belonged to the VFP or
14768 Neon instruction sets, but turned out to be a Neon instruction (due to the
14769 operand types involved, etc.). We have to check and/or fix-up a couple of
14772 - Make sure the user hasn't attempted to make a Neon instruction
14774 - Alter the value in the condition code field if necessary.
14775 - Make sure that the arch supports Neon instructions.
14777 Which of these operations take place depends on bits from enum
14778 vfp_or_neon_is_neon_bits.
14780 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14781 current instruction's condition is COND_ALWAYS, the condition field is
14782 changed to inst.uncond_value. This is necessary because instructions shared
14783 between VFP and Neon may be conditional for the VFP variants only, and the
14784 unconditional Neon version must have, e.g., 0xF in the condition field. */
14787 vfp_or_neon_is_neon (unsigned check
)
14789 /* Conditions are always legal in Thumb mode (IT blocks). */
14790 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14792 if (inst
.cond
!= COND_ALWAYS
)
14794 first_error (_(BAD_COND
));
14797 if (inst
.uncond_value
!= -1)
14798 inst
.instruction
|= inst
.uncond_value
<< 28;
14801 if ((check
& NEON_CHECK_ARCH
)
14802 && !mark_feature_used (&fpu_neon_ext_v1
))
14804 first_error (_(BAD_FPU
));
14808 if ((check
& NEON_CHECK_ARCH8
)
14809 && !mark_feature_used (&fpu_neon_ext_armv8
))
14811 first_error (_(BAD_FPU
));
14819 do_neon_addsub_if_i (void)
14821 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14824 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14827 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14828 affected if we specify unsigned args. */
14829 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14832 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14834 V<op> A,B (A is operand 0, B is operand 2)
14839 so handle that case specially. */
14842 neon_exchange_operands (void)
14844 void *scratch
= alloca (sizeof (inst
.operands
[0]));
14845 if (inst
.operands
[1].present
)
14847 /* Swap operands[1] and operands[2]. */
14848 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14849 inst
.operands
[1] = inst
.operands
[2];
14850 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14854 inst
.operands
[1] = inst
.operands
[2];
14855 inst
.operands
[2] = inst
.operands
[0];
14860 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14862 if (inst
.operands
[2].isreg
)
14865 neon_exchange_operands ();
14866 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14870 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14871 struct neon_type_el et
= neon_check_type (2, rs
,
14872 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14874 NEON_ENCODE (IMMED
, inst
);
14875 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14876 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14877 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14878 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14879 inst
.instruction
|= neon_quad (rs
) << 6;
14880 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14881 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14883 neon_dp_fixup (&inst
);
14890 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
14894 do_neon_cmp_inv (void)
14896 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
14902 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14905 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14906 scalars, which are encoded in 5 bits, M : Rm.
14907 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14908 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14912 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14914 unsigned regno
= NEON_SCALAR_REG (scalar
);
14915 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14920 if (regno
> 7 || elno
> 3)
14922 return regno
| (elno
<< 3);
14925 if (regno
> 15 || elno
> 1)
14927 return regno
| (elno
<< 4);
14931 first_error (_("scalar out of range for multiply instruction"));
14937 /* Encode multiply / multiply-accumulate scalar instructions. */
14940 neon_mul_mac (struct neon_type_el et
, int ubit
)
14944 /* Give a more helpful error message if we have an invalid type. */
14945 if (et
.type
== NT_invtype
)
14948 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14949 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14950 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14951 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14952 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14953 inst
.instruction
|= LOW4 (scalar
);
14954 inst
.instruction
|= HI1 (scalar
) << 5;
14955 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14956 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14957 inst
.instruction
|= (ubit
!= 0) << 24;
14959 neon_dp_fixup (&inst
);
14963 do_neon_mac_maybe_scalar (void)
14965 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
14968 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14971 if (inst
.operands
[2].isscalar
)
14973 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14974 struct neon_type_el et
= neon_check_type (3, rs
,
14975 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
14976 NEON_ENCODE (SCALAR
, inst
);
14977 neon_mul_mac (et
, neon_quad (rs
));
14981 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14982 affected if we specify unsigned args. */
14983 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14988 do_neon_fmac (void)
14990 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
14993 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14996 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15002 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15003 struct neon_type_el et
= neon_check_type (3, rs
,
15004 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15005 neon_three_same (neon_quad (rs
), 0, et
.size
);
15008 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15009 same types as the MAC equivalents. The polynomial type for this instruction
15010 is encoded the same as the integer type. */
15015 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15018 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15021 if (inst
.operands
[2].isscalar
)
15022 do_neon_mac_maybe_scalar ();
15024 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
15028 do_neon_qdmulh (void)
15030 if (inst
.operands
[2].isscalar
)
15032 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15033 struct neon_type_el et
= neon_check_type (3, rs
,
15034 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15035 NEON_ENCODE (SCALAR
, inst
);
15036 neon_mul_mac (et
, neon_quad (rs
));
15040 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15041 struct neon_type_el et
= neon_check_type (3, rs
,
15042 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15043 NEON_ENCODE (INTEGER
, inst
);
15044 /* The U bit (rounding) comes from bit mask. */
15045 neon_three_same (neon_quad (rs
), 0, et
.size
);
15050 do_neon_qrdmlah (void)
15052 /* Check we're on the correct architecture. */
15053 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15055 _("instruction form not available on this architecture.");
15056 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15058 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15059 record_feature_use (&fpu_neon_ext_v8_1
);
15062 if (inst
.operands
[2].isscalar
)
15064 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15065 struct neon_type_el et
= neon_check_type (3, rs
,
15066 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15067 NEON_ENCODE (SCALAR
, inst
);
15068 neon_mul_mac (et
, neon_quad (rs
));
15072 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15073 struct neon_type_el et
= neon_check_type (3, rs
,
15074 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15075 NEON_ENCODE (INTEGER
, inst
);
15076 /* The U bit (rounding) comes from bit mask. */
15077 neon_three_same (neon_quad (rs
), 0, et
.size
);
15082 do_neon_fcmp_absolute (void)
15084 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15085 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
15086 /* Size field comes from bit mask. */
15087 neon_three_same (neon_quad (rs
), 1, -1);
15091 do_neon_fcmp_absolute_inv (void)
15093 neon_exchange_operands ();
15094 do_neon_fcmp_absolute ();
15098 do_neon_step (void)
15100 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15101 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
15102 neon_three_same (neon_quad (rs
), 0, -1);
15106 do_neon_abs_neg (void)
15108 enum neon_shape rs
;
15109 struct neon_type_el et
;
15111 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15114 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15117 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15118 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
15120 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15121 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15122 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15123 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15124 inst
.instruction
|= neon_quad (rs
) << 6;
15125 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15126 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15128 neon_dp_fixup (&inst
);
15134 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15135 struct neon_type_el et
= neon_check_type (2, rs
,
15136 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15137 int imm
= inst
.operands
[2].imm
;
15138 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15139 _("immediate out of range for insert"));
15140 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15146 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15147 struct neon_type_el et
= neon_check_type (2, rs
,
15148 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15149 int imm
= inst
.operands
[2].imm
;
15150 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15151 _("immediate out of range for insert"));
15152 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15156 do_neon_qshlu_imm (void)
15158 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15159 struct neon_type_el et
= neon_check_type (2, rs
,
15160 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15161 int imm
= inst
.operands
[2].imm
;
15162 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15163 _("immediate out of range for shift"));
15164 /* Only encodes the 'U present' variant of the instruction.
15165 In this case, signed types have OP (bit 8) set to 0.
15166 Unsigned types have OP set to 1. */
15167 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15168 /* The rest of the bits are the same as other immediate shifts. */
15169 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15173 do_neon_qmovn (void)
15175 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15176 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15177 /* Saturating move where operands can be signed or unsigned, and the
15178 destination has the same signedness. */
15179 NEON_ENCODE (INTEGER
, inst
);
15180 if (et
.type
== NT_unsigned
)
15181 inst
.instruction
|= 0xc0;
15183 inst
.instruction
|= 0x80;
15184 neon_two_same (0, 1, et
.size
/ 2);
15188 do_neon_qmovun (void)
15190 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15191 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15192 /* Saturating move with unsigned results. Operands must be signed. */
15193 NEON_ENCODE (INTEGER
, inst
);
15194 neon_two_same (0, 1, et
.size
/ 2);
15198 do_neon_rshift_sat_narrow (void)
15200 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15201 or unsigned. If operands are unsigned, results must also be unsigned. */
15202 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15203 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15204 int imm
= inst
.operands
[2].imm
;
15205 /* This gets the bounds check, size encoding and immediate bits calculation
15209 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15210 VQMOVN.I<size> <Dd>, <Qm>. */
15213 inst
.operands
[2].present
= 0;
15214 inst
.instruction
= N_MNEM_vqmovn
;
15219 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15220 _("immediate out of range"));
15221 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15225 do_neon_rshift_sat_narrow_u (void)
15227 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15228 or unsigned. If operands are unsigned, results must also be unsigned. */
15229 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15230 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15231 int imm
= inst
.operands
[2].imm
;
15232 /* This gets the bounds check, size encoding and immediate bits calculation
15236 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15237 VQMOVUN.I<size> <Dd>, <Qm>. */
15240 inst
.operands
[2].present
= 0;
15241 inst
.instruction
= N_MNEM_vqmovun
;
15246 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15247 _("immediate out of range"));
15248 /* FIXME: The manual is kind of unclear about what value U should have in
15249 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15251 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15255 do_neon_movn (void)
15257 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15258 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15259 NEON_ENCODE (INTEGER
, inst
);
15260 neon_two_same (0, 1, et
.size
/ 2);
15264 do_neon_rshift_narrow (void)
15266 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15267 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15268 int imm
= inst
.operands
[2].imm
;
15269 /* This gets the bounds check, size encoding and immediate bits calculation
15273 /* If immediate is zero then we are a pseudo-instruction for
15274 VMOVN.I<size> <Dd>, <Qm> */
15277 inst
.operands
[2].present
= 0;
15278 inst
.instruction
= N_MNEM_vmovn
;
15283 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15284 _("immediate out of range for narrowing operation"));
15285 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15289 do_neon_shll (void)
15291 /* FIXME: Type checking when lengthening. */
15292 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15293 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15294 unsigned imm
= inst
.operands
[2].imm
;
15296 if (imm
== et
.size
)
15298 /* Maximum shift variant. */
15299 NEON_ENCODE (INTEGER
, inst
);
15300 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15301 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15302 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15303 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15304 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15306 neon_dp_fixup (&inst
);
15310 /* A more-specific type check for non-max versions. */
15311 et
= neon_check_type (2, NS_QDI
,
15312 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15313 NEON_ENCODE (IMMED
, inst
);
15314 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15318 /* Check the various types for the VCVT instruction, and return which version
15319 the current instruction is. */
15321 #define CVT_FLAVOUR_VAR \
15322 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15323 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15324 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15325 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15326 /* Half-precision conversions. */ \
15327 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15328 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15329 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15330 Compared with single/double precision variants, only the co-processor \
15331 field is different, so the encoding flow is reused here. */ \
15332 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15333 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15334 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15335 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15336 /* VFP instructions. */ \
15337 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15338 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15339 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15340 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15341 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15342 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15343 /* VFP instructions with bitshift. */ \
15344 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15345 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15346 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15347 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15348 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15349 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15350 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15351 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15353 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15354 neon_cvt_flavour_##C,
15356 /* The different types of conversions we can do. */
15357 enum neon_cvt_flavour
15360 neon_cvt_flavour_invalid
,
15361 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15366 static enum neon_cvt_flavour
15367 get_neon_cvt_flavour (enum neon_shape rs
)
15369 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15370 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15371 if (et.type != NT_invtype) \
15373 inst.error = NULL; \
15374 return (neon_cvt_flavour_##C); \
15377 struct neon_type_el et
;
15378 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15379 || rs
== NS_FF
) ? N_VFP
: 0;
15380 /* The instruction versions which take an immediate take one register
15381 argument, which is extended to the width of the full register. Thus the
15382 "source" and "destination" registers must have the same width. Hack that
15383 here by making the size equal to the key (wider, in this case) operand. */
15384 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15388 return neon_cvt_flavour_invalid
;
15403 /* Neon-syntax VFP conversions. */
15406 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15408 const char *opname
= 0;
15410 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15411 || rs
== NS_FHI
|| rs
== NS_HFI
)
15413 /* Conversions with immediate bitshift. */
15414 const char *enc
[] =
15416 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15422 if (flavour
< (int) ARRAY_SIZE (enc
))
15424 opname
= enc
[flavour
];
15425 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15426 _("operands 0 and 1 must be the same register"));
15427 inst
.operands
[1] = inst
.operands
[2];
15428 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15433 /* Conversions without bitshift. */
15434 const char *enc
[] =
15436 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15442 if (flavour
< (int) ARRAY_SIZE (enc
))
15443 opname
= enc
[flavour
];
15447 do_vfp_nsyn_opcode (opname
);
15449 /* ARMv8.2 fp16 VCVT instruction. */
15450 if (flavour
== neon_cvt_flavour_s32_f16
15451 || flavour
== neon_cvt_flavour_u32_f16
15452 || flavour
== neon_cvt_flavour_f16_u32
15453 || flavour
== neon_cvt_flavour_f16_s32
)
15454 do_scalar_fp16_v82_encode ();
15458 do_vfp_nsyn_cvtz (void)
15460 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15461 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15462 const char *enc
[] =
15464 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15470 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15471 do_vfp_nsyn_opcode (enc
[flavour
]);
15475 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15476 enum neon_cvt_mode mode
)
15481 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15482 D register operands. */
15483 if (flavour
== neon_cvt_flavour_s32_f64
15484 || flavour
== neon_cvt_flavour_u32_f64
)
15485 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15488 if (flavour
== neon_cvt_flavour_s32_f16
15489 || flavour
== neon_cvt_flavour_u32_f16
)
15490 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15493 set_it_insn_type (OUTSIDE_IT_INSN
);
15497 case neon_cvt_flavour_s32_f64
:
15501 case neon_cvt_flavour_s32_f32
:
15505 case neon_cvt_flavour_s32_f16
:
15509 case neon_cvt_flavour_u32_f64
:
15513 case neon_cvt_flavour_u32_f32
:
15517 case neon_cvt_flavour_u32_f16
:
15522 first_error (_("invalid instruction shape"));
15528 case neon_cvt_mode_a
: rm
= 0; break;
15529 case neon_cvt_mode_n
: rm
= 1; break;
15530 case neon_cvt_mode_p
: rm
= 2; break;
15531 case neon_cvt_mode_m
: rm
= 3; break;
15532 default: first_error (_("invalid rounding mode")); return;
15535 NEON_ENCODE (FPV8
, inst
);
15536 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15537 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15538 inst
.instruction
|= sz
<< 8;
15540 /* ARMv8.2 fp16 VCVT instruction. */
15541 if (flavour
== neon_cvt_flavour_s32_f16
15542 ||flavour
== neon_cvt_flavour_u32_f16
)
15543 do_scalar_fp16_v82_encode ();
15544 inst
.instruction
|= op
<< 7;
15545 inst
.instruction
|= rm
<< 16;
15546 inst
.instruction
|= 0xf0000000;
15547 inst
.is_neon
= TRUE
;
15551 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15553 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15554 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15555 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15557 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15559 /* PR11109: Handle round-to-zero for VCVT conversions. */
15560 if (mode
== neon_cvt_mode_z
15561 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15562 && (flavour
== neon_cvt_flavour_s32_f32
15563 || flavour
== neon_cvt_flavour_u32_f32
15564 || flavour
== neon_cvt_flavour_s32_f64
15565 || flavour
== neon_cvt_flavour_u32_f64
)
15566 && (rs
== NS_FD
|| rs
== NS_FF
))
15568 do_vfp_nsyn_cvtz ();
15572 /* ARMv8.2 fp16 VCVT conversions. */
15573 if (mode
== neon_cvt_mode_z
15574 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15575 && (flavour
== neon_cvt_flavour_s32_f16
15576 || flavour
== neon_cvt_flavour_u32_f16
)
15579 do_vfp_nsyn_cvtz ();
15580 do_scalar_fp16_v82_encode ();
15584 /* VFP rather than Neon conversions. */
15585 if (flavour
>= neon_cvt_flavour_first_fp
)
15587 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15588 do_vfp_nsyn_cvt (rs
, flavour
);
15590 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15601 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
15603 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15606 /* Fixed-point conversion with #0 immediate is encoded as an
15607 integer conversion. */
15608 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15610 immbits
= 32 - inst
.operands
[2].imm
;
15611 NEON_ENCODE (IMMED
, inst
);
15612 if (flavour
!= neon_cvt_flavour_invalid
)
15613 inst
.instruction
|= enctab
[flavour
];
15614 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15615 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15616 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15617 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15618 inst
.instruction
|= neon_quad (rs
) << 6;
15619 inst
.instruction
|= 1 << 21;
15620 inst
.instruction
|= immbits
<< 16;
15622 neon_dp_fixup (&inst
);
15628 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15630 NEON_ENCODE (FLOAT
, inst
);
15631 set_it_insn_type (OUTSIDE_IT_INSN
);
15633 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15636 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15637 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15638 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15639 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15640 inst
.instruction
|= neon_quad (rs
) << 6;
15641 inst
.instruction
|= (flavour
== neon_cvt_flavour_u32_f32
) << 7;
15642 inst
.instruction
|= mode
<< 8;
15644 inst
.instruction
|= 0xfc000000;
15646 inst
.instruction
|= 0xf0000000;
15652 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
15654 NEON_ENCODE (INTEGER
, inst
);
15656 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15659 if (flavour
!= neon_cvt_flavour_invalid
)
15660 inst
.instruction
|= enctab
[flavour
];
15662 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15663 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15664 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15665 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15666 inst
.instruction
|= neon_quad (rs
) << 6;
15667 inst
.instruction
|= 2 << 18;
15669 neon_dp_fixup (&inst
);
15674 /* Half-precision conversions for Advanced SIMD -- neon. */
15679 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15681 as_bad (_("operand size must match register width"));
15686 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15688 as_bad (_("operand size must match register width"));
15693 inst
.instruction
= 0x3b60600;
15695 inst
.instruction
= 0x3b60700;
15697 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15698 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15699 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15700 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15701 neon_dp_fixup (&inst
);
15705 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15706 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15707 do_vfp_nsyn_cvt (rs
, flavour
);
15709 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15714 do_neon_cvtr (void)
15716 do_neon_cvt_1 (neon_cvt_mode_x
);
15722 do_neon_cvt_1 (neon_cvt_mode_z
);
15726 do_neon_cvta (void)
15728 do_neon_cvt_1 (neon_cvt_mode_a
);
15732 do_neon_cvtn (void)
15734 do_neon_cvt_1 (neon_cvt_mode_n
);
15738 do_neon_cvtp (void)
15740 do_neon_cvt_1 (neon_cvt_mode_p
);
15744 do_neon_cvtm (void)
15746 do_neon_cvt_1 (neon_cvt_mode_m
);
15750 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15753 mark_feature_used (&fpu_vfp_ext_armv8
);
15755 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15756 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15757 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15758 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15759 inst
.instruction
|= to
? 0x10000 : 0;
15760 inst
.instruction
|= t
? 0x80 : 0;
15761 inst
.instruction
|= is_double
? 0x100 : 0;
15762 do_vfp_cond_or_thumb ();
15766 do_neon_cvttb_1 (bfd_boolean t
)
15768 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
15769 NS_DF
, NS_DH
, NS_NULL
);
15773 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15776 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15778 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15781 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15783 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15785 /* The VCVTB and VCVTT instructions with D-register operands
15786 don't work for SP only targets. */
15787 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15791 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15793 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15795 /* The VCVTB and VCVTT instructions with D-register operands
15796 don't work for SP only targets. */
15797 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15801 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15808 do_neon_cvtb (void)
15810 do_neon_cvttb_1 (FALSE
);
15815 do_neon_cvtt (void)
15817 do_neon_cvttb_1 (TRUE
);
15821 neon_move_immediate (void)
15823 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15824 struct neon_type_el et
= neon_check_type (2, rs
,
15825 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15826 unsigned immlo
, immhi
= 0, immbits
;
15827 int op
, cmode
, float_p
;
15829 constraint (et
.type
== NT_invtype
,
15830 _("operand size must be specified for immediate VMOV"));
15832 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15833 op
= (inst
.instruction
& (1 << 5)) != 0;
15835 immlo
= inst
.operands
[1].imm
;
15836 if (inst
.operands
[1].regisimm
)
15837 immhi
= inst
.operands
[1].reg
;
15839 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15840 _("immediate has bits set outside the operand size"));
15842 float_p
= inst
.operands
[1].immisfloat
;
15844 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15845 et
.size
, et
.type
)) == FAIL
)
15847 /* Invert relevant bits only. */
15848 neon_invert_size (&immlo
, &immhi
, et
.size
);
15849 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15850 with one or the other; those cases are caught by
15851 neon_cmode_for_move_imm. */
15853 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15854 &op
, et
.size
, et
.type
)) == FAIL
)
15856 first_error (_("immediate out of range"));
15861 inst
.instruction
&= ~(1 << 5);
15862 inst
.instruction
|= op
<< 5;
15864 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15865 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15866 inst
.instruction
|= neon_quad (rs
) << 6;
15867 inst
.instruction
|= cmode
<< 8;
15869 neon_write_immbits (immbits
);
15875 if (inst
.operands
[1].isreg
)
15877 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15879 NEON_ENCODE (INTEGER
, inst
);
15880 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15881 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15882 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15883 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15884 inst
.instruction
|= neon_quad (rs
) << 6;
15888 NEON_ENCODE (IMMED
, inst
);
15889 neon_move_immediate ();
15892 neon_dp_fixup (&inst
);
15895 /* Encode instructions of form:
15897 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15898 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15901 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15903 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15904 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15905 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15906 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15907 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15908 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15909 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15910 inst
.instruction
|= neon_logbits (size
) << 20;
15912 neon_dp_fixup (&inst
);
15916 do_neon_dyadic_long (void)
15918 /* FIXME: Type checking for lengthening op. */
15919 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15920 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15921 neon_mixed_length (et
, et
.size
);
15925 do_neon_abal (void)
15927 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15928 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15929 neon_mixed_length (et
, et
.size
);
15933 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
15935 if (inst
.operands
[2].isscalar
)
15937 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
15938 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
15939 NEON_ENCODE (SCALAR
, inst
);
15940 neon_mul_mac (et
, et
.type
== NT_unsigned
);
15944 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15945 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
15946 NEON_ENCODE (INTEGER
, inst
);
15947 neon_mixed_length (et
, et
.size
);
15952 do_neon_mac_maybe_scalar_long (void)
15954 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
15958 do_neon_dyadic_wide (void)
15960 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
15961 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15962 neon_mixed_length (et
, et
.size
);
15966 do_neon_dyadic_narrow (void)
15968 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15969 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
15970 /* Operand sign is unimportant, and the U bit is part of the opcode,
15971 so force the operand type to integer. */
15972 et
.type
= NT_integer
;
15973 neon_mixed_length (et
, et
.size
/ 2);
15977 do_neon_mul_sat_scalar_long (void)
15979 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
15983 do_neon_vmull (void)
15985 if (inst
.operands
[2].isscalar
)
15986 do_neon_mac_maybe_scalar_long ();
15989 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15990 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
15992 if (et
.type
== NT_poly
)
15993 NEON_ENCODE (POLY
, inst
);
15995 NEON_ENCODE (INTEGER
, inst
);
15997 /* For polynomial encoding the U bit must be zero, and the size must
15998 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15999 obviously, as 0b10). */
16002 /* Check we're on the correct architecture. */
16003 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16005 _("Instruction form not available on this architecture.");
16010 neon_mixed_length (et
, et
.size
);
16017 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16018 struct neon_type_el et
= neon_check_type (3, rs
,
16019 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16020 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16022 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16023 _("shift out of range"));
16024 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16025 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16026 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16027 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16028 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16029 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16030 inst
.instruction
|= neon_quad (rs
) << 6;
16031 inst
.instruction
|= imm
<< 8;
16033 neon_dp_fixup (&inst
);
16039 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16040 struct neon_type_el et
= neon_check_type (2, rs
,
16041 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16042 unsigned op
= (inst
.instruction
>> 7) & 3;
16043 /* N (width of reversed regions) is encoded as part of the bitmask. We
16044 extract it here to check the elements to be reversed are smaller.
16045 Otherwise we'd get a reserved instruction. */
16046 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16047 gas_assert (elsize
!= 0);
16048 constraint (et
.size
>= elsize
,
16049 _("elements must be smaller than reversal region"));
16050 neon_two_same (neon_quad (rs
), 1, et
.size
);
16056 if (inst
.operands
[1].isscalar
)
16058 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16059 struct neon_type_el et
= neon_check_type (2, rs
,
16060 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16061 unsigned sizebits
= et
.size
>> 3;
16062 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16063 int logsize
= neon_logbits (et
.size
);
16064 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16066 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16069 NEON_ENCODE (SCALAR
, inst
);
16070 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16071 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16072 inst
.instruction
|= LOW4 (dm
);
16073 inst
.instruction
|= HI1 (dm
) << 5;
16074 inst
.instruction
|= neon_quad (rs
) << 6;
16075 inst
.instruction
|= x
<< 17;
16076 inst
.instruction
|= sizebits
<< 16;
16078 neon_dp_fixup (&inst
);
16082 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16083 struct neon_type_el et
= neon_check_type (2, rs
,
16084 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16085 /* Duplicate ARM register to lanes of vector. */
16086 NEON_ENCODE (ARMREG
, inst
);
16089 case 8: inst
.instruction
|= 0x400000; break;
16090 case 16: inst
.instruction
|= 0x000020; break;
16091 case 32: inst
.instruction
|= 0x000000; break;
16094 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16095 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16096 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16097 inst
.instruction
|= neon_quad (rs
) << 21;
16098 /* The encoding for this instruction is identical for the ARM and Thumb
16099 variants, except for the condition field. */
16100 do_vfp_cond_or_thumb ();
16104 /* VMOV has particularly many variations. It can be one of:
16105 0. VMOV<c><q> <Qd>, <Qm>
16106 1. VMOV<c><q> <Dd>, <Dm>
16107 (Register operations, which are VORR with Rm = Rn.)
16108 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16109 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16111 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16112 (ARM register to scalar.)
16113 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16114 (Two ARM registers to vector.)
16115 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16116 (Scalar to ARM register.)
16117 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16118 (Vector to two ARM registers.)
16119 8. VMOV.F32 <Sd>, <Sm>
16120 9. VMOV.F64 <Dd>, <Dm>
16121 (VFP register moves.)
16122 10. VMOV.F32 <Sd>, #imm
16123 11. VMOV.F64 <Dd>, #imm
16124 (VFP float immediate load.)
16125 12. VMOV <Rd>, <Sm>
16126 (VFP single to ARM reg.)
16127 13. VMOV <Sd>, <Rm>
16128 (ARM reg to VFP single.)
16129 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16130 (Two ARM regs to two VFP singles.)
16131 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16132 (Two VFP singles to two ARM regs.)
16134 These cases can be disambiguated using neon_select_shape, except cases 1/9
16135 and 3/11 which depend on the operand type too.
16137 All the encoded bits are hardcoded by this function.
16139 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16140 Cases 5, 7 may be used with VFPv2 and above.
16142 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16143 can specify a type where it doesn't make sense to, and is ignored). */
16148 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16149 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16150 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16151 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16152 struct neon_type_el et
;
16153 const char *ldconst
= 0;
16157 case NS_DD
: /* case 1/9. */
16158 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16159 /* It is not an error here if no type is given. */
16161 if (et
.type
== NT_float
&& et
.size
== 64)
16163 do_vfp_nsyn_opcode ("fcpyd");
16166 /* fall through. */
16168 case NS_QQ
: /* case 0/1. */
16170 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16172 /* The architecture manual I have doesn't explicitly state which
16173 value the U bit should have for register->register moves, but
16174 the equivalent VORR instruction has U = 0, so do that. */
16175 inst
.instruction
= 0x0200110;
16176 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16177 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16178 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16179 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16180 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16181 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16182 inst
.instruction
|= neon_quad (rs
) << 6;
16184 neon_dp_fixup (&inst
);
16188 case NS_DI
: /* case 3/11. */
16189 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16191 if (et
.type
== NT_float
&& et
.size
== 64)
16193 /* case 11 (fconstd). */
16194 ldconst
= "fconstd";
16195 goto encode_fconstd
;
16197 /* fall through. */
16199 case NS_QI
: /* case 2/3. */
16200 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16202 inst
.instruction
= 0x0800010;
16203 neon_move_immediate ();
16204 neon_dp_fixup (&inst
);
16207 case NS_SR
: /* case 4. */
16209 unsigned bcdebits
= 0;
16211 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16212 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16214 /* .<size> is optional here, defaulting to .32. */
16215 if (inst
.vectype
.elems
== 0
16216 && inst
.operands
[0].vectype
.type
== NT_invtype
16217 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16219 inst
.vectype
.el
[0].type
= NT_untyped
;
16220 inst
.vectype
.el
[0].size
= 32;
16221 inst
.vectype
.elems
= 1;
16224 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16225 logsize
= neon_logbits (et
.size
);
16227 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16229 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16230 && et
.size
!= 32, _(BAD_FPU
));
16231 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16232 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16236 case 8: bcdebits
= 0x8; break;
16237 case 16: bcdebits
= 0x1; break;
16238 case 32: bcdebits
= 0x0; break;
16242 bcdebits
|= x
<< logsize
;
16244 inst
.instruction
= 0xe000b10;
16245 do_vfp_cond_or_thumb ();
16246 inst
.instruction
|= LOW4 (dn
) << 16;
16247 inst
.instruction
|= HI1 (dn
) << 7;
16248 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16249 inst
.instruction
|= (bcdebits
& 3) << 5;
16250 inst
.instruction
|= (bcdebits
>> 2) << 21;
16254 case NS_DRR
: /* case 5 (fmdrr). */
16255 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16258 inst
.instruction
= 0xc400b10;
16259 do_vfp_cond_or_thumb ();
16260 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16261 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16262 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16263 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16266 case NS_RS
: /* case 6. */
16269 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16270 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16271 unsigned abcdebits
= 0;
16273 /* .<dt> is optional here, defaulting to .32. */
16274 if (inst
.vectype
.elems
== 0
16275 && inst
.operands
[0].vectype
.type
== NT_invtype
16276 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16278 inst
.vectype
.el
[0].type
= NT_untyped
;
16279 inst
.vectype
.el
[0].size
= 32;
16280 inst
.vectype
.elems
= 1;
16283 et
= neon_check_type (2, NS_NULL
,
16284 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16285 logsize
= neon_logbits (et
.size
);
16287 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16289 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16290 && et
.size
!= 32, _(BAD_FPU
));
16291 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16292 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16296 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16297 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16298 case 32: abcdebits
= 0x00; break;
16302 abcdebits
|= x
<< logsize
;
16303 inst
.instruction
= 0xe100b10;
16304 do_vfp_cond_or_thumb ();
16305 inst
.instruction
|= LOW4 (dn
) << 16;
16306 inst
.instruction
|= HI1 (dn
) << 7;
16307 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16308 inst
.instruction
|= (abcdebits
& 3) << 5;
16309 inst
.instruction
|= (abcdebits
>> 2) << 21;
16313 case NS_RRD
: /* case 7 (fmrrd). */
16314 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16317 inst
.instruction
= 0xc500b10;
16318 do_vfp_cond_or_thumb ();
16319 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16320 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16321 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16322 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16325 case NS_FF
: /* case 8 (fcpys). */
16326 do_vfp_nsyn_opcode ("fcpys");
16330 case NS_FI
: /* case 10 (fconsts). */
16331 ldconst
= "fconsts";
16333 if (is_quarter_float (inst
.operands
[1].imm
))
16335 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16336 do_vfp_nsyn_opcode (ldconst
);
16338 /* ARMv8.2 fp16 vmov.f16 instruction. */
16340 do_scalar_fp16_v82_encode ();
16343 first_error (_("immediate out of range"));
16347 case NS_RF
: /* case 12 (fmrs). */
16348 do_vfp_nsyn_opcode ("fmrs");
16349 /* ARMv8.2 fp16 vmov.f16 instruction. */
16351 do_scalar_fp16_v82_encode ();
16355 case NS_FR
: /* case 13 (fmsr). */
16356 do_vfp_nsyn_opcode ("fmsr");
16357 /* ARMv8.2 fp16 vmov.f16 instruction. */
16359 do_scalar_fp16_v82_encode ();
16362 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16363 (one of which is a list), but we have parsed four. Do some fiddling to
16364 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16366 case NS_RRFF
: /* case 14 (fmrrs). */
16367 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16368 _("VFP registers must be adjacent"));
16369 inst
.operands
[2].imm
= 2;
16370 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16371 do_vfp_nsyn_opcode ("fmrrs");
16374 case NS_FFRR
: /* case 15 (fmsrr). */
16375 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16376 _("VFP registers must be adjacent"));
16377 inst
.operands
[1] = inst
.operands
[2];
16378 inst
.operands
[2] = inst
.operands
[3];
16379 inst
.operands
[0].imm
= 2;
16380 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16381 do_vfp_nsyn_opcode ("fmsrr");
16385 /* neon_select_shape has determined that the instruction
16386 shape is wrong and has already set the error message. */
16395 do_neon_rshift_round_imm (void)
16397 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16398 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16399 int imm
= inst
.operands
[2].imm
;
16401 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16404 inst
.operands
[2].present
= 0;
16409 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16410 _("immediate out of range for shift"));
16411 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16416 do_neon_movhf (void)
16418 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16419 constraint (rs
!= NS_HH
, _("invalid suffix"));
16421 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16424 do_vfp_sp_monadic ();
16427 inst
.instruction
|= 0xf0000000;
16431 do_neon_movl (void)
16433 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16434 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16435 unsigned sizebits
= et
.size
>> 3;
16436 inst
.instruction
|= sizebits
<< 19;
16437 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16443 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16444 struct neon_type_el et
= neon_check_type (2, rs
,
16445 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16446 NEON_ENCODE (INTEGER
, inst
);
16447 neon_two_same (neon_quad (rs
), 1, et
.size
);
16451 do_neon_zip_uzp (void)
16453 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16454 struct neon_type_el et
= neon_check_type (2, rs
,
16455 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16456 if (rs
== NS_DD
&& et
.size
== 32)
16458 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16459 inst
.instruction
= N_MNEM_vtrn
;
16463 neon_two_same (neon_quad (rs
), 1, et
.size
);
16467 do_neon_sat_abs_neg (void)
16469 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16470 struct neon_type_el et
= neon_check_type (2, rs
,
16471 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16472 neon_two_same (neon_quad (rs
), 1, et
.size
);
16476 do_neon_pair_long (void)
16478 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16479 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16480 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16481 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16482 neon_two_same (neon_quad (rs
), 1, et
.size
);
16486 do_neon_recip_est (void)
16488 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16489 struct neon_type_el et
= neon_check_type (2, rs
,
16490 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
16491 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16492 neon_two_same (neon_quad (rs
), 1, et
.size
);
16498 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16499 struct neon_type_el et
= neon_check_type (2, rs
,
16500 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16501 neon_two_same (neon_quad (rs
), 1, et
.size
);
16507 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16508 struct neon_type_el et
= neon_check_type (2, rs
,
16509 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16510 neon_two_same (neon_quad (rs
), 1, et
.size
);
16516 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16517 struct neon_type_el et
= neon_check_type (2, rs
,
16518 N_EQK
| N_INT
, N_8
| N_KEY
);
16519 neon_two_same (neon_quad (rs
), 1, et
.size
);
16525 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16526 neon_two_same (neon_quad (rs
), 1, -1);
16530 do_neon_tbl_tbx (void)
16532 unsigned listlenbits
;
16533 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16535 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16537 first_error (_("bad list length for table lookup"));
16541 listlenbits
= inst
.operands
[1].imm
- 1;
16542 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16543 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16544 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16545 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16546 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16547 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16548 inst
.instruction
|= listlenbits
<< 8;
16550 neon_dp_fixup (&inst
);
16554 do_neon_ldm_stm (void)
16556 /* P, U and L bits are part of bitmask. */
16557 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16558 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16560 if (inst
.operands
[1].issingle
)
16562 do_vfp_nsyn_ldm_stm (is_dbmode
);
16566 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16567 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16569 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16570 _("register list must contain at least 1 and at most 16 "
16573 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16574 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16575 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16576 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16578 inst
.instruction
|= offsetbits
;
16580 do_vfp_cond_or_thumb ();
16584 do_neon_ldr_str (void)
16586 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16588 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16589 And is UNPREDICTABLE in thumb mode. */
16591 && inst
.operands
[1].reg
== REG_PC
16592 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16595 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16596 else if (warn_on_deprecated
)
16597 as_tsktsk (_("Use of PC here is deprecated"));
16600 if (inst
.operands
[0].issingle
)
16603 do_vfp_nsyn_opcode ("flds");
16605 do_vfp_nsyn_opcode ("fsts");
16607 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16608 if (inst
.vectype
.el
[0].size
== 16)
16609 do_scalar_fp16_v82_encode ();
16614 do_vfp_nsyn_opcode ("fldd");
16616 do_vfp_nsyn_opcode ("fstd");
16620 /* "interleave" version also handles non-interleaving register VLD1/VST1
16624 do_neon_ld_st_interleave (void)
16626 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16627 N_8
| N_16
| N_32
| N_64
);
16628 unsigned alignbits
= 0;
16630 /* The bits in this table go:
16631 0: register stride of one (0) or two (1)
16632 1,2: register list length, minus one (1, 2, 3, 4).
16633 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16634 We use -1 for invalid entries. */
16635 const int typetable
[] =
16637 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16638 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16639 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16640 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16644 if (et
.type
== NT_invtype
)
16647 if (inst
.operands
[1].immisalign
)
16648 switch (inst
.operands
[1].imm
>> 8)
16650 case 64: alignbits
= 1; break;
16652 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16653 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16654 goto bad_alignment
;
16658 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16659 goto bad_alignment
;
16664 first_error (_("bad alignment"));
16668 inst
.instruction
|= alignbits
<< 4;
16669 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16671 /* Bits [4:6] of the immediate in a list specifier encode register stride
16672 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16673 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16674 up the right value for "type" in a table based on this value and the given
16675 list style, then stick it back. */
16676 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16677 | (((inst
.instruction
>> 8) & 3) << 3);
16679 typebits
= typetable
[idx
];
16681 constraint (typebits
== -1, _("bad list type for instruction"));
16682 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16683 _("bad element type for instruction"));
16685 inst
.instruction
&= ~0xf00;
16686 inst
.instruction
|= typebits
<< 8;
16689 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16690 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16691 otherwise. The variable arguments are a list of pairs of legal (size, align)
16692 values, terminated with -1. */
16695 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
16698 int result
= FAIL
, thissize
, thisalign
;
16700 if (!inst
.operands
[1].immisalign
)
16706 va_start (ap
, do_alignment
);
16710 thissize
= va_arg (ap
, int);
16711 if (thissize
== -1)
16713 thisalign
= va_arg (ap
, int);
16715 if (size
== thissize
&& align
== thisalign
)
16718 while (result
!= SUCCESS
);
16722 if (result
== SUCCESS
)
16725 first_error (_("unsupported alignment for instruction"));
16731 do_neon_ld_st_lane (void)
16733 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16734 int align_good
, do_alignment
= 0;
16735 int logsize
= neon_logbits (et
.size
);
16736 int align
= inst
.operands
[1].imm
>> 8;
16737 int n
= (inst
.instruction
>> 8) & 3;
16738 int max_el
= 64 / et
.size
;
16740 if (et
.type
== NT_invtype
)
16743 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16744 _("bad list length"));
16745 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16746 _("scalar index out of range"));
16747 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16749 _("stride of 2 unavailable when element size is 8"));
16753 case 0: /* VLD1 / VST1. */
16754 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
16756 if (align_good
== FAIL
)
16760 unsigned alignbits
= 0;
16763 case 16: alignbits
= 0x1; break;
16764 case 32: alignbits
= 0x3; break;
16767 inst
.instruction
|= alignbits
<< 4;
16771 case 1: /* VLD2 / VST2. */
16772 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
16773 16, 32, 32, 64, -1);
16774 if (align_good
== FAIL
)
16777 inst
.instruction
|= 1 << 4;
16780 case 2: /* VLD3 / VST3. */
16781 constraint (inst
.operands
[1].immisalign
,
16782 _("can't use alignment with this instruction"));
16785 case 3: /* VLD4 / VST4. */
16786 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16787 16, 64, 32, 64, 32, 128, -1);
16788 if (align_good
== FAIL
)
16792 unsigned alignbits
= 0;
16795 case 8: alignbits
= 0x1; break;
16796 case 16: alignbits
= 0x1; break;
16797 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16800 inst
.instruction
|= alignbits
<< 4;
16807 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16808 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16809 inst
.instruction
|= 1 << (4 + logsize
);
16811 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16812 inst
.instruction
|= logsize
<< 10;
16815 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16818 do_neon_ld_dup (void)
16820 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16821 int align_good
, do_alignment
= 0;
16823 if (et
.type
== NT_invtype
)
16826 switch ((inst
.instruction
>> 8) & 3)
16828 case 0: /* VLD1. */
16829 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16830 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16831 &do_alignment
, 16, 16, 32, 32, -1);
16832 if (align_good
== FAIL
)
16834 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16837 case 2: inst
.instruction
|= 1 << 5; break;
16838 default: first_error (_("bad list length")); return;
16840 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16843 case 1: /* VLD2. */
16844 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16845 &do_alignment
, 8, 16, 16, 32, 32, 64,
16847 if (align_good
== FAIL
)
16849 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16850 _("bad list length"));
16851 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16852 inst
.instruction
|= 1 << 5;
16853 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16856 case 2: /* VLD3. */
16857 constraint (inst
.operands
[1].immisalign
,
16858 _("can't use alignment with this instruction"));
16859 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16860 _("bad list length"));
16861 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16862 inst
.instruction
|= 1 << 5;
16863 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16866 case 3: /* VLD4. */
16868 int align
= inst
.operands
[1].imm
>> 8;
16869 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16870 16, 64, 32, 64, 32, 128, -1);
16871 if (align_good
== FAIL
)
16873 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16874 _("bad list length"));
16875 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16876 inst
.instruction
|= 1 << 5;
16877 if (et
.size
== 32 && align
== 128)
16878 inst
.instruction
|= 0x3 << 6;
16880 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16887 inst
.instruction
|= do_alignment
<< 4;
16890 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16891 apart from bits [11:4]. */
16894 do_neon_ldx_stx (void)
16896 if (inst
.operands
[1].isreg
)
16897 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16899 switch (NEON_LANE (inst
.operands
[0].imm
))
16901 case NEON_INTERLEAVE_LANES
:
16902 NEON_ENCODE (INTERLV
, inst
);
16903 do_neon_ld_st_interleave ();
16906 case NEON_ALL_LANES
:
16907 NEON_ENCODE (DUP
, inst
);
16908 if (inst
.instruction
== N_INV
)
16910 first_error ("only loads support such operands");
16917 NEON_ENCODE (LANE
, inst
);
16918 do_neon_ld_st_lane ();
16921 /* L bit comes from bit mask. */
16922 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16923 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16924 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16926 if (inst
.operands
[1].postind
)
16928 int postreg
= inst
.operands
[1].imm
& 0xf;
16929 constraint (!inst
.operands
[1].immisreg
,
16930 _("post-index must be a register"));
16931 constraint (postreg
== 0xd || postreg
== 0xf,
16932 _("bad register for post-index"));
16933 inst
.instruction
|= postreg
;
16937 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16938 constraint (inst
.reloc
.exp
.X_op
!= O_constant
16939 || inst
.reloc
.exp
.X_add_number
!= 0,
16942 if (inst
.operands
[1].writeback
)
16944 inst
.instruction
|= 0xd;
16947 inst
.instruction
|= 0xf;
16951 inst
.instruction
|= 0xf9000000;
16953 inst
.instruction
|= 0xf4000000;
16958 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
16960 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16961 D register operands. */
16962 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16963 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16966 NEON_ENCODE (FPV8
, inst
);
16968 if (rs
== NS_FFF
|| rs
== NS_HHH
)
16970 do_vfp_sp_dyadic ();
16972 /* ARMv8.2 fp16 instruction. */
16974 do_scalar_fp16_v82_encode ();
16977 do_vfp_dp_rd_rn_rm ();
16980 inst
.instruction
|= 0x100;
16982 inst
.instruction
|= 0xf0000000;
16988 set_it_insn_type (OUTSIDE_IT_INSN
);
16990 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
16991 first_error (_("invalid instruction shape"));
16997 set_it_insn_type (OUTSIDE_IT_INSN
);
16999 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17002 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17005 neon_dyadic_misc (NT_untyped
, N_F32
, 0);
17009 do_vrint_1 (enum neon_cvt_mode mode
)
17011 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17012 struct neon_type_el et
;
17017 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17018 D register operands. */
17019 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17020 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17023 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17025 if (et
.type
!= NT_invtype
)
17027 /* VFP encodings. */
17028 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17029 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17030 set_it_insn_type (OUTSIDE_IT_INSN
);
17032 NEON_ENCODE (FPV8
, inst
);
17033 if (rs
== NS_FF
|| rs
== NS_HH
)
17034 do_vfp_sp_monadic ();
17036 do_vfp_dp_rd_rm ();
17040 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17041 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17042 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17043 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17044 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17045 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17046 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17050 inst
.instruction
|= (rs
== NS_DD
) << 8;
17051 do_vfp_cond_or_thumb ();
17053 /* ARMv8.2 fp16 vrint instruction. */
17055 do_scalar_fp16_v82_encode ();
17059 /* Neon encodings (or something broken...). */
17061 et
= neon_check_type (2, rs
, N_EQK
, N_F32
| N_KEY
);
17063 if (et
.type
== NT_invtype
)
17066 set_it_insn_type (OUTSIDE_IT_INSN
);
17067 NEON_ENCODE (FLOAT
, inst
);
17069 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17072 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17073 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17074 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17075 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17076 inst
.instruction
|= neon_quad (rs
) << 6;
17079 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17080 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17081 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17082 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17083 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17084 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17085 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17090 inst
.instruction
|= 0xfc000000;
17092 inst
.instruction
|= 0xf0000000;
17099 do_vrint_1 (neon_cvt_mode_x
);
17105 do_vrint_1 (neon_cvt_mode_z
);
17111 do_vrint_1 (neon_cvt_mode_r
);
17117 do_vrint_1 (neon_cvt_mode_a
);
17123 do_vrint_1 (neon_cvt_mode_n
);
17129 do_vrint_1 (neon_cvt_mode_p
);
17135 do_vrint_1 (neon_cvt_mode_m
);
17138 /* Crypto v1 instructions. */
17140 do_crypto_2op_1 (unsigned elttype
, int op
)
17142 set_it_insn_type (OUTSIDE_IT_INSN
);
17144 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17150 NEON_ENCODE (INTEGER
, inst
);
17151 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17152 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17153 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17154 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17156 inst
.instruction
|= op
<< 6;
17159 inst
.instruction
|= 0xfc000000;
17161 inst
.instruction
|= 0xf0000000;
17165 do_crypto_3op_1 (int u
, int op
)
17167 set_it_insn_type (OUTSIDE_IT_INSN
);
17169 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17170 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17175 NEON_ENCODE (INTEGER
, inst
);
17176 neon_three_same (1, u
, 8 << op
);
17182 do_crypto_2op_1 (N_8
, 0);
17188 do_crypto_2op_1 (N_8
, 1);
17194 do_crypto_2op_1 (N_8
, 2);
17200 do_crypto_2op_1 (N_8
, 3);
17206 do_crypto_3op_1 (0, 0);
17212 do_crypto_3op_1 (0, 1);
17218 do_crypto_3op_1 (0, 2);
17224 do_crypto_3op_1 (0, 3);
17230 do_crypto_3op_1 (1, 0);
17236 do_crypto_3op_1 (1, 1);
17240 do_sha256su1 (void)
17242 do_crypto_3op_1 (1, 2);
17248 do_crypto_2op_1 (N_32
, -1);
17254 do_crypto_2op_1 (N_32
, 0);
17258 do_sha256su0 (void)
17260 do_crypto_2op_1 (N_32
, 1);
17264 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17266 unsigned int Rd
= inst
.operands
[0].reg
;
17267 unsigned int Rn
= inst
.operands
[1].reg
;
17268 unsigned int Rm
= inst
.operands
[2].reg
;
17270 set_it_insn_type (OUTSIDE_IT_INSN
);
17271 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17272 inst
.instruction
|= LOW4 (Rn
) << 16;
17273 inst
.instruction
|= LOW4 (Rm
);
17274 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17275 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17277 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17278 as_warn (UNPRED_REG ("r15"));
17279 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
17280 as_warn (UNPRED_REG ("r13"));
17320 /* Overall per-instruction processing. */
17322 /* We need to be able to fix up arbitrary expressions in some statements.
17323 This is so that we can handle symbols that are an arbitrary distance from
17324 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17325 which returns part of an address in a form which will be valid for
17326 a data instruction. We do this by pushing the expression into a symbol
17327 in the expr_section, and creating a fix for that. */
17330 fix_new_arm (fragS
* frag
,
17344 /* Create an absolute valued symbol, so we have something to
17345 refer to in the object file. Unfortunately for us, gas's
17346 generic expression parsing will already have folded out
17347 any use of .set foo/.type foo %function that may have
17348 been used to set type information of the target location,
17349 that's being specified symbolically. We have to presume
17350 the user knows what they are doing. */
17354 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17356 symbol
= symbol_find_or_make (name
);
17357 S_SET_SEGMENT (symbol
, absolute_section
);
17358 symbol_set_frag (symbol
, &zero_address_frag
);
17359 S_SET_VALUE (symbol
, exp
->X_add_number
);
17360 exp
->X_op
= O_symbol
;
17361 exp
->X_add_symbol
= symbol
;
17362 exp
->X_add_number
= 0;
17368 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17369 (enum bfd_reloc_code_real
) reloc
);
17373 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17374 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17378 /* Mark whether the fix is to a THUMB instruction, or an ARM
17380 new_fix
->tc_fix_data
= thumb_mode
;
17383 /* Create a frg for an instruction requiring relaxation. */
17385 output_relax_insn (void)
17391 /* The size of the instruction is unknown, so tie the debug info to the
17392 start of the instruction. */
17393 dwarf2_emit_insn (0);
17395 switch (inst
.reloc
.exp
.X_op
)
17398 sym
= inst
.reloc
.exp
.X_add_symbol
;
17399 offset
= inst
.reloc
.exp
.X_add_number
;
17403 offset
= inst
.reloc
.exp
.X_add_number
;
17406 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17410 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17411 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17412 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17415 /* Write a 32-bit thumb instruction to buf. */
17417 put_thumb32_insn (char * buf
, unsigned long insn
)
17419 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17420 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17424 output_inst (const char * str
)
17430 as_bad ("%s -- `%s'", inst
.error
, str
);
17435 output_relax_insn ();
17438 if (inst
.size
== 0)
17441 to
= frag_more (inst
.size
);
17442 /* PR 9814: Record the thumb mode into the current frag so that we know
17443 what type of NOP padding to use, if necessary. We override any previous
17444 setting so that if the mode has changed then the NOPS that we use will
17445 match the encoding of the last instruction in the frag. */
17446 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17448 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17450 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17451 put_thumb32_insn (to
, inst
.instruction
);
17453 else if (inst
.size
> INSN_SIZE
)
17455 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17456 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17457 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17460 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17462 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17463 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17464 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17467 dwarf2_emit_insn (inst
.size
);
17471 output_it_inst (int cond
, int mask
, char * to
)
17473 unsigned long instruction
= 0xbf00;
17476 instruction
|= mask
;
17477 instruction
|= cond
<< 4;
17481 to
= frag_more (2);
17483 dwarf2_emit_insn (2);
17487 md_number_to_chars (to
, instruction
, 2);
17492 /* Tag values used in struct asm_opcode's tag field. */
17495 OT_unconditional
, /* Instruction cannot be conditionalized.
17496 The ARM condition field is still 0xE. */
17497 OT_unconditionalF
, /* Instruction cannot be conditionalized
17498 and carries 0xF in its ARM condition field. */
17499 OT_csuffix
, /* Instruction takes a conditional suffix. */
17500 OT_csuffixF
, /* Some forms of the instruction take a conditional
17501 suffix, others place 0xF where the condition field
17503 OT_cinfix3
, /* Instruction takes a conditional infix,
17504 beginning at character index 3. (In
17505 unified mode, it becomes a suffix.) */
17506 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17507 tsts, cmps, cmns, and teqs. */
17508 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17509 character index 3, even in unified mode. Used for
17510 legacy instructions where suffix and infix forms
17511 may be ambiguous. */
17512 OT_csuf_or_in3
, /* Instruction takes either a conditional
17513 suffix or an infix at character index 3. */
17514 OT_odd_infix_unc
, /* This is the unconditional variant of an
17515 instruction that takes a conditional infix
17516 at an unusual position. In unified mode,
17517 this variant will accept a suffix. */
17518 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17519 are the conditional variants of instructions that
17520 take conditional infixes in unusual positions.
17521 The infix appears at character index
17522 (tag - OT_odd_infix_0). These are not accepted
17523 in unified mode. */
17526 /* Subroutine of md_assemble, responsible for looking up the primary
17527 opcode from the mnemonic the user wrote. STR points to the
17528 beginning of the mnemonic.
17530 This is not simply a hash table lookup, because of conditional
17531 variants. Most instructions have conditional variants, which are
17532 expressed with a _conditional affix_ to the mnemonic. If we were
17533 to encode each conditional variant as a literal string in the opcode
17534 table, it would have approximately 20,000 entries.
17536 Most mnemonics take this affix as a suffix, and in unified syntax,
17537 'most' is upgraded to 'all'. However, in the divided syntax, some
17538 instructions take the affix as an infix, notably the s-variants of
17539 the arithmetic instructions. Of those instructions, all but six
17540 have the infix appear after the third character of the mnemonic.
17542 Accordingly, the algorithm for looking up primary opcodes given
17545 1. Look up the identifier in the opcode table.
17546 If we find a match, go to step U.
17548 2. Look up the last two characters of the identifier in the
17549 conditions table. If we find a match, look up the first N-2
17550 characters of the identifier in the opcode table. If we
17551 find a match, go to step CE.
17553 3. Look up the fourth and fifth characters of the identifier in
17554 the conditions table. If we find a match, extract those
17555 characters from the identifier, and look up the remaining
17556 characters in the opcode table. If we find a match, go
17561 U. Examine the tag field of the opcode structure, in case this is
17562 one of the six instructions with its conditional infix in an
17563 unusual place. If it is, the tag tells us where to find the
17564 infix; look it up in the conditions table and set inst.cond
17565 accordingly. Otherwise, this is an unconditional instruction.
17566 Again set inst.cond accordingly. Return the opcode structure.
17568 CE. Examine the tag field to make sure this is an instruction that
17569 should receive a conditional suffix. If it is not, fail.
17570 Otherwise, set inst.cond from the suffix we already looked up,
17571 and return the opcode structure.
17573 CM. Examine the tag field to make sure this is an instruction that
17574 should receive a conditional infix after the third character.
17575 If it is not, fail. Otherwise, undo the edits to the current
17576 line of input and proceed as for case CE. */
17578 static const struct asm_opcode
*
17579 opcode_lookup (char **str
)
17583 const struct asm_opcode
*opcode
;
17584 const struct asm_cond
*cond
;
17587 /* Scan up to the end of the mnemonic, which must end in white space,
17588 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17589 for (base
= end
= *str
; *end
!= '\0'; end
++)
17590 if (*end
== ' ' || *end
== '.')
17596 /* Handle a possible width suffix and/or Neon type suffix. */
17601 /* The .w and .n suffixes are only valid if the unified syntax is in
17603 if (unified_syntax
&& end
[1] == 'w')
17605 else if (unified_syntax
&& end
[1] == 'n')
17610 inst
.vectype
.elems
= 0;
17612 *str
= end
+ offset
;
17614 if (end
[offset
] == '.')
17616 /* See if we have a Neon type suffix (possible in either unified or
17617 non-unified ARM syntax mode). */
17618 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17621 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17627 /* Look for unaffixed or special-case affixed mnemonic. */
17628 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17633 if (opcode
->tag
< OT_odd_infix_0
)
17635 inst
.cond
= COND_ALWAYS
;
17639 if (warn_on_deprecated
&& unified_syntax
)
17640 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17641 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17642 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17645 inst
.cond
= cond
->value
;
17649 /* Cannot have a conditional suffix on a mnemonic of less than two
17651 if (end
- base
< 3)
17654 /* Look for suffixed mnemonic. */
17656 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17657 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17659 if (opcode
&& cond
)
17662 switch (opcode
->tag
)
17664 case OT_cinfix3_legacy
:
17665 /* Ignore conditional suffixes matched on infix only mnemonics. */
17669 case OT_cinfix3_deprecated
:
17670 case OT_odd_infix_unc
:
17671 if (!unified_syntax
)
17673 /* else fall through */
17677 case OT_csuf_or_in3
:
17678 inst
.cond
= cond
->value
;
17681 case OT_unconditional
:
17682 case OT_unconditionalF
:
17684 inst
.cond
= cond
->value
;
17687 /* Delayed diagnostic. */
17688 inst
.error
= BAD_COND
;
17689 inst
.cond
= COND_ALWAYS
;
17698 /* Cannot have a usual-position infix on a mnemonic of less than
17699 six characters (five would be a suffix). */
17700 if (end
- base
< 6)
17703 /* Look for infixed mnemonic in the usual position. */
17705 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17709 memcpy (save
, affix
, 2);
17710 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17711 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17713 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17714 memcpy (affix
, save
, 2);
17717 && (opcode
->tag
== OT_cinfix3
17718 || opcode
->tag
== OT_cinfix3_deprecated
17719 || opcode
->tag
== OT_csuf_or_in3
17720 || opcode
->tag
== OT_cinfix3_legacy
))
17723 if (warn_on_deprecated
&& unified_syntax
17724 && (opcode
->tag
== OT_cinfix3
17725 || opcode
->tag
== OT_cinfix3_deprecated
))
17726 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17728 inst
.cond
= cond
->value
;
17735 /* This function generates an initial IT instruction, leaving its block
17736 virtually open for the new instructions. Eventually,
17737 the mask will be updated by now_it_add_mask () each time
17738 a new instruction needs to be included in the IT block.
17739 Finally, the block is closed with close_automatic_it_block ().
17740 The block closure can be requested either from md_assemble (),
17741 a tencode (), or due to a label hook. */
17744 new_automatic_it_block (int cond
)
17746 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17747 now_it
.mask
= 0x18;
17749 now_it
.block_length
= 1;
17750 mapping_state (MAP_THUMB
);
17751 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17752 now_it
.warn_deprecated
= FALSE
;
17753 now_it
.insn_cond
= TRUE
;
17756 /* Close an automatic IT block.
17757 See comments in new_automatic_it_block (). */
17760 close_automatic_it_block (void)
17762 now_it
.mask
= 0x10;
17763 now_it
.block_length
= 0;
17766 /* Update the mask of the current automatically-generated IT
17767 instruction. See comments in new_automatic_it_block (). */
17770 now_it_add_mask (int cond
)
17772 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17773 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17774 | ((bitvalue) << (nbit)))
17775 const int resulting_bit
= (cond
& 1);
17777 now_it
.mask
&= 0xf;
17778 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17780 (5 - now_it
.block_length
));
17781 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17783 ((5 - now_it
.block_length
) - 1) );
17784 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17787 #undef SET_BIT_VALUE
17790 /* The IT blocks handling machinery is accessed through the these functions:
17791 it_fsm_pre_encode () from md_assemble ()
17792 set_it_insn_type () optional, from the tencode functions
17793 set_it_insn_type_last () ditto
17794 in_it_block () ditto
17795 it_fsm_post_encode () from md_assemble ()
17796 force_automatic_it_block_close () from label habdling functions
17799 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17800 initializing the IT insn type with a generic initial value depending
17801 on the inst.condition.
17802 2) During the tencode function, two things may happen:
17803 a) The tencode function overrides the IT insn type by
17804 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17805 b) The tencode function queries the IT block state by
17806 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17808 Both set_it_insn_type and in_it_block run the internal FSM state
17809 handling function (handle_it_state), because: a) setting the IT insn
17810 type may incur in an invalid state (exiting the function),
17811 and b) querying the state requires the FSM to be updated.
17812 Specifically we want to avoid creating an IT block for conditional
17813 branches, so it_fsm_pre_encode is actually a guess and we can't
17814 determine whether an IT block is required until the tencode () routine
17815 has decided what type of instruction this actually it.
17816 Because of this, if set_it_insn_type and in_it_block have to be used,
17817 set_it_insn_type has to be called first.
17819 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17820 determines the insn IT type depending on the inst.cond code.
17821 When a tencode () routine encodes an instruction that can be
17822 either outside an IT block, or, in the case of being inside, has to be
17823 the last one, set_it_insn_type_last () will determine the proper
17824 IT instruction type based on the inst.cond code. Otherwise,
17825 set_it_insn_type can be called for overriding that logic or
17826 for covering other cases.
17828 Calling handle_it_state () may not transition the IT block state to
17829 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17830 still queried. Instead, if the FSM determines that the state should
17831 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17832 after the tencode () function: that's what it_fsm_post_encode () does.
17834 Since in_it_block () calls the state handling function to get an
17835 updated state, an error may occur (due to invalid insns combination).
17836 In that case, inst.error is set.
17837 Therefore, inst.error has to be checked after the execution of
17838 the tencode () routine.
17840 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17841 any pending state change (if any) that didn't take place in
17842 handle_it_state () as explained above. */
17845 it_fsm_pre_encode (void)
17847 if (inst
.cond
!= COND_ALWAYS
)
17848 inst
.it_insn_type
= INSIDE_IT_INSN
;
17850 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17852 now_it
.state_handled
= 0;
17855 /* IT state FSM handling function. */
17858 handle_it_state (void)
17860 now_it
.state_handled
= 1;
17861 now_it
.insn_cond
= FALSE
;
17863 switch (now_it
.state
)
17865 case OUTSIDE_IT_BLOCK
:
17866 switch (inst
.it_insn_type
)
17868 case OUTSIDE_IT_INSN
:
17871 case INSIDE_IT_INSN
:
17872 case INSIDE_IT_LAST_INSN
:
17873 if (thumb_mode
== 0)
17876 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17877 as_tsktsk (_("Warning: conditional outside an IT block"\
17882 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17883 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
17885 /* Automatically generate the IT instruction. */
17886 new_automatic_it_block (inst
.cond
);
17887 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17888 close_automatic_it_block ();
17892 inst
.error
= BAD_OUT_IT
;
17898 case IF_INSIDE_IT_LAST_INSN
:
17899 case NEUTRAL_IT_INSN
:
17903 now_it
.state
= MANUAL_IT_BLOCK
;
17904 now_it
.block_length
= 0;
17909 case AUTOMATIC_IT_BLOCK
:
17910 /* Three things may happen now:
17911 a) We should increment current it block size;
17912 b) We should close current it block (closing insn or 4 insns);
17913 c) We should close current it block and start a new one (due
17914 to incompatible conditions or
17915 4 insns-length block reached). */
17917 switch (inst
.it_insn_type
)
17919 case OUTSIDE_IT_INSN
:
17920 /* The closure of the block shall happen immediatelly,
17921 so any in_it_block () call reports the block as closed. */
17922 force_automatic_it_block_close ();
17925 case INSIDE_IT_INSN
:
17926 case INSIDE_IT_LAST_INSN
:
17927 case IF_INSIDE_IT_LAST_INSN
:
17928 now_it
.block_length
++;
17930 if (now_it
.block_length
> 4
17931 || !now_it_compatible (inst
.cond
))
17933 force_automatic_it_block_close ();
17934 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
17935 new_automatic_it_block (inst
.cond
);
17939 now_it
.insn_cond
= TRUE
;
17940 now_it_add_mask (inst
.cond
);
17943 if (now_it
.state
== AUTOMATIC_IT_BLOCK
17944 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
17945 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
17946 close_automatic_it_block ();
17949 case NEUTRAL_IT_INSN
:
17950 now_it
.block_length
++;
17951 now_it
.insn_cond
= TRUE
;
17953 if (now_it
.block_length
> 4)
17954 force_automatic_it_block_close ();
17956 now_it_add_mask (now_it
.cc
& 1);
17960 close_automatic_it_block ();
17961 now_it
.state
= MANUAL_IT_BLOCK
;
17966 case MANUAL_IT_BLOCK
:
17968 /* Check conditional suffixes. */
17969 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
17972 now_it
.mask
&= 0x1f;
17973 is_last
= (now_it
.mask
== 0x10);
17974 now_it
.insn_cond
= TRUE
;
17976 switch (inst
.it_insn_type
)
17978 case OUTSIDE_IT_INSN
:
17979 inst
.error
= BAD_NOT_IT
;
17982 case INSIDE_IT_INSN
:
17983 if (cond
!= inst
.cond
)
17985 inst
.error
= BAD_IT_COND
;
17990 case INSIDE_IT_LAST_INSN
:
17991 case IF_INSIDE_IT_LAST_INSN
:
17992 if (cond
!= inst
.cond
)
17994 inst
.error
= BAD_IT_COND
;
17999 inst
.error
= BAD_BRANCH
;
18004 case NEUTRAL_IT_INSN
:
18005 /* The BKPT instruction is unconditional even in an IT block. */
18009 inst
.error
= BAD_IT_IT
;
18019 struct depr_insn_mask
18021 unsigned long pattern
;
18022 unsigned long mask
;
18023 const char* description
;
18026 /* List of 16-bit instruction patterns deprecated in an IT block in
18028 static const struct depr_insn_mask depr_it_insns
[] = {
18029 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18030 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18031 { 0xa000, 0xb800, N_("ADR") },
18032 { 0x4800, 0xf800, N_("Literal loads") },
18033 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18034 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18035 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18036 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18037 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18042 it_fsm_post_encode (void)
18046 if (!now_it
.state_handled
)
18047 handle_it_state ();
18049 if (now_it
.insn_cond
18050 && !now_it
.warn_deprecated
18051 && warn_on_deprecated
18052 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
18054 if (inst
.instruction
>= 0x10000)
18056 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18057 "deprecated in ARMv8"));
18058 now_it
.warn_deprecated
= TRUE
;
18062 const struct depr_insn_mask
*p
= depr_it_insns
;
18064 while (p
->mask
!= 0)
18066 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18068 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18069 "of the following class are deprecated in ARMv8: "
18070 "%s"), p
->description
);
18071 now_it
.warn_deprecated
= TRUE
;
18079 if (now_it
.block_length
> 1)
18081 as_tsktsk (_("IT blocks containing more than one conditional "
18082 "instruction are deprecated in ARMv8"));
18083 now_it
.warn_deprecated
= TRUE
;
18087 is_last
= (now_it
.mask
== 0x10);
18090 now_it
.state
= OUTSIDE_IT_BLOCK
;
18096 force_automatic_it_block_close (void)
18098 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18100 close_automatic_it_block ();
18101 now_it
.state
= OUTSIDE_IT_BLOCK
;
18109 if (!now_it
.state_handled
)
18110 handle_it_state ();
18112 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18115 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18116 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18117 here, hence the "known" in the function name. */
18120 known_t32_only_insn (const struct asm_opcode
*opcode
)
18122 /* Original Thumb-1 wide instruction. */
18123 if (opcode
->tencode
== do_t_blx
18124 || opcode
->tencode
== do_t_branch23
18125 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18126 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18129 /* Wide-only instruction added to ARMv8-M. */
18130 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m
)
18131 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18132 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18133 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18139 /* Whether wide instruction variant can be used if available for a valid OPCODE
18143 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18145 if (known_t32_only_insn (opcode
))
18148 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18149 of variant T3 of B.W is checked in do_t_branch. */
18150 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18151 && opcode
->tencode
== do_t_branch
)
18154 /* Wide instruction variants of all instructions with narrow *and* wide
18155 variants become available with ARMv6t2. Other opcodes are either
18156 narrow-only or wide-only and are thus available if OPCODE is valid. */
18157 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18160 /* OPCODE with narrow only instruction variant or wide variant not
18166 md_assemble (char *str
)
18169 const struct asm_opcode
* opcode
;
18171 /* Align the previous label if needed. */
18172 if (last_label_seen
!= NULL
)
18174 symbol_set_frag (last_label_seen
, frag_now
);
18175 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18176 S_SET_SEGMENT (last_label_seen
, now_seg
);
18179 memset (&inst
, '\0', sizeof (inst
));
18180 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18182 opcode
= opcode_lookup (&p
);
18185 /* It wasn't an instruction, but it might be a register alias of
18186 the form alias .req reg, or a Neon .dn/.qn directive. */
18187 if (! create_register_alias (str
, p
)
18188 && ! create_neon_reg_alias (str
, p
))
18189 as_bad (_("bad instruction `%s'"), str
);
18194 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18195 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18197 /* The value which unconditional instructions should have in place of the
18198 condition field. */
18199 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18203 arm_feature_set variant
;
18205 variant
= cpu_variant
;
18206 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18207 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18208 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18209 /* Check that this instruction is supported for this CPU. */
18210 if (!opcode
->tvariant
18211 || (thumb_mode
== 1
18212 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18214 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18217 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18218 && opcode
->tencode
!= do_t_branch
)
18220 as_bad (_("Thumb does not support conditional execution"));
18224 /* Two things are addressed here:
18225 1) Implicit require narrow instructions on Thumb-1.
18226 This avoids relaxation accidentally introducing Thumb-2
18228 2) Reject wide instructions in non Thumb-2 cores.
18230 Only instructions with narrow and wide variants need to be handled
18231 but selecting all non wide-only instructions is easier. */
18232 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18233 && !t32_insn_ok (variant
, opcode
))
18235 if (inst
.size_req
== 0)
18237 else if (inst
.size_req
== 4)
18239 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18240 as_bad (_("selected processor does not support 32bit wide "
18241 "variant of instruction `%s'"), str
);
18243 as_bad (_("selected processor does not support `%s' in "
18244 "Thumb-2 mode"), str
);
18249 inst
.instruction
= opcode
->tvalue
;
18251 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18253 /* Prepare the it_insn_type for those encodings that don't set
18255 it_fsm_pre_encode ();
18257 opcode
->tencode ();
18259 it_fsm_post_encode ();
18262 if (!(inst
.error
|| inst
.relax
))
18264 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18265 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18266 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18268 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18273 /* Something has gone badly wrong if we try to relax a fixed size
18275 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18277 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18278 *opcode
->tvariant
);
18279 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18280 set those bits when Thumb-2 32-bit instructions are seen. The impact
18281 of relaxable instructions will be considered later after we finish all
18283 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18284 variant
= arm_arch_none
;
18286 variant
= cpu_variant
;
18287 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18288 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18291 check_neon_suffixes
;
18295 mapping_state (MAP_THUMB
);
18298 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18302 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18303 is_bx
= (opcode
->aencode
== do_bx
);
18305 /* Check that this instruction is supported for this CPU. */
18306 if (!(is_bx
&& fix_v4bx
)
18307 && !(opcode
->avariant
&&
18308 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18310 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18315 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18319 inst
.instruction
= opcode
->avalue
;
18320 if (opcode
->tag
== OT_unconditionalF
)
18321 inst
.instruction
|= 0xFU
<< 28;
18323 inst
.instruction
|= inst
.cond
<< 28;
18324 inst
.size
= INSN_SIZE
;
18325 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18327 it_fsm_pre_encode ();
18328 opcode
->aencode ();
18329 it_fsm_post_encode ();
18331 /* Arm mode bx is marked as both v4T and v5 because it's still required
18332 on a hypothetical non-thumb v5 core. */
18334 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18336 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18337 *opcode
->avariant
);
18339 check_neon_suffixes
;
18343 mapping_state (MAP_ARM
);
18348 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18356 check_it_blocks_finished (void)
18361 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18362 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18363 == MANUAL_IT_BLOCK
)
18365 as_warn (_("section '%s' finished with an open IT block."),
18369 if (now_it
.state
== MANUAL_IT_BLOCK
)
18370 as_warn (_("file finished with an open IT block."));
18374 /* Various frobbings of labels and their addresses. */
18377 arm_start_line_hook (void)
18379 last_label_seen
= NULL
;
18383 arm_frob_label (symbolS
* sym
)
18385 last_label_seen
= sym
;
18387 ARM_SET_THUMB (sym
, thumb_mode
);
18389 #if defined OBJ_COFF || defined OBJ_ELF
18390 ARM_SET_INTERWORK (sym
, support_interwork
);
18393 force_automatic_it_block_close ();
18395 /* Note - do not allow local symbols (.Lxxx) to be labelled
18396 as Thumb functions. This is because these labels, whilst
18397 they exist inside Thumb code, are not the entry points for
18398 possible ARM->Thumb calls. Also, these labels can be used
18399 as part of a computed goto or switch statement. eg gcc
18400 can generate code that looks like this:
18402 ldr r2, [pc, .Laaa]
18412 The first instruction loads the address of the jump table.
18413 The second instruction converts a table index into a byte offset.
18414 The third instruction gets the jump address out of the table.
18415 The fourth instruction performs the jump.
18417 If the address stored at .Laaa is that of a symbol which has the
18418 Thumb_Func bit set, then the linker will arrange for this address
18419 to have the bottom bit set, which in turn would mean that the
18420 address computation performed by the third instruction would end
18421 up with the bottom bit set. Since the ARM is capable of unaligned
18422 word loads, the instruction would then load the incorrect address
18423 out of the jump table, and chaos would ensue. */
18424 if (label_is_thumb_function_name
18425 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18426 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18428 /* When the address of a Thumb function is taken the bottom
18429 bit of that address should be set. This will allow
18430 interworking between Arm and Thumb functions to work
18433 THUMB_SET_FUNC (sym
, 1);
18435 label_is_thumb_function_name
= FALSE
;
18438 dwarf2_emit_label (sym
);
18442 arm_data_in_code (void)
18444 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18446 *input_line_pointer
= '/';
18447 input_line_pointer
+= 5;
18448 *input_line_pointer
= 0;
18456 arm_canonicalize_symbol_name (char * name
)
18460 if (thumb_mode
&& (len
= strlen (name
)) > 5
18461 && streq (name
+ len
- 5, "/data"))
18462 *(name
+ len
- 5) = 0;
18467 /* Table of all register names defined by default. The user can
18468 define additional names with .req. Note that all register names
18469 should appear in both upper and lowercase variants. Some registers
18470 also have mixed-case names. */
18472 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18473 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18474 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18475 #define REGSET(p,t) \
18476 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18477 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18478 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18479 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18480 #define REGSETH(p,t) \
18481 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18482 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18483 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18484 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18485 #define REGSET2(p,t) \
18486 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18487 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18488 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18489 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18490 #define SPLRBANK(base,bank,t) \
18491 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18492 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18493 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18494 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18495 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18496 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18498 static const struct reg_entry reg_names
[] =
18500 /* ARM integer registers. */
18501 REGSET(r
, RN
), REGSET(R
, RN
),
18503 /* ATPCS synonyms. */
18504 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18505 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18506 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18508 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18509 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18510 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18512 /* Well-known aliases. */
18513 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18514 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18516 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18517 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18519 /* Coprocessor numbers. */
18520 REGSET(p
, CP
), REGSET(P
, CP
),
18522 /* Coprocessor register numbers. The "cr" variants are for backward
18524 REGSET(c
, CN
), REGSET(C
, CN
),
18525 REGSET(cr
, CN
), REGSET(CR
, CN
),
18527 /* ARM banked registers. */
18528 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18529 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18530 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18531 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18532 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18533 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18534 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18536 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18537 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18538 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18539 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18540 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18541 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18542 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18543 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18545 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18546 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18547 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18548 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18549 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18550 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18551 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18552 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18553 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18555 /* FPA registers. */
18556 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18557 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18559 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18560 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18562 /* VFP SP registers. */
18563 REGSET(s
,VFS
), REGSET(S
,VFS
),
18564 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18566 /* VFP DP Registers. */
18567 REGSET(d
,VFD
), REGSET(D
,VFD
),
18568 /* Extra Neon DP registers. */
18569 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18571 /* Neon QP registers. */
18572 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18574 /* VFP control registers. */
18575 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18576 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18577 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18578 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18579 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18580 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18582 /* Maverick DSP coprocessor registers. */
18583 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18584 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18586 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18587 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18588 REGDEF(dspsc
,0,DSPSC
),
18590 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18591 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18592 REGDEF(DSPSC
,0,DSPSC
),
18594 /* iWMMXt data registers - p0, c0-15. */
18595 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18597 /* iWMMXt control registers - p1, c0-3. */
18598 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18599 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18600 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18601 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18603 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18604 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18605 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18606 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18607 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18609 /* XScale accumulator registers. */
18610 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18616 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18617 within psr_required_here. */
18618 static const struct asm_psr psrs
[] =
18620 /* Backward compatibility notation. Note that "all" is no longer
18621 truly all possible PSR bits. */
18622 {"all", PSR_c
| PSR_f
},
18626 /* Individual flags. */
18632 /* Combinations of flags. */
18633 {"fs", PSR_f
| PSR_s
},
18634 {"fx", PSR_f
| PSR_x
},
18635 {"fc", PSR_f
| PSR_c
},
18636 {"sf", PSR_s
| PSR_f
},
18637 {"sx", PSR_s
| PSR_x
},
18638 {"sc", PSR_s
| PSR_c
},
18639 {"xf", PSR_x
| PSR_f
},
18640 {"xs", PSR_x
| PSR_s
},
18641 {"xc", PSR_x
| PSR_c
},
18642 {"cf", PSR_c
| PSR_f
},
18643 {"cs", PSR_c
| PSR_s
},
18644 {"cx", PSR_c
| PSR_x
},
18645 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18646 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18647 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18648 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18649 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18650 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18651 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18652 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18653 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18654 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18655 {"scf", PSR_s
| PSR_c
| PSR_f
},
18656 {"scx", PSR_s
| PSR_c
| PSR_x
},
18657 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18658 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18659 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18660 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18661 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18662 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18663 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18664 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18665 {"csf", PSR_c
| PSR_s
| PSR_f
},
18666 {"csx", PSR_c
| PSR_s
| PSR_x
},
18667 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18668 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18669 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18670 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18671 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18672 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18673 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18674 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18675 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18676 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18677 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18678 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18679 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18680 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18681 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18682 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18683 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18684 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18685 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18686 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18687 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18688 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18689 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18690 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18691 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18692 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18695 /* Table of V7M psr names. */
18696 static const struct asm_psr v7m_psrs
[] =
18698 {"apsr", 0 }, {"APSR", 0 },
18699 {"iapsr", 1 }, {"IAPSR", 1 },
18700 {"eapsr", 2 }, {"EAPSR", 2 },
18701 {"psr", 3 }, {"PSR", 3 },
18702 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18703 {"ipsr", 5 }, {"IPSR", 5 },
18704 {"epsr", 6 }, {"EPSR", 6 },
18705 {"iepsr", 7 }, {"IEPSR", 7 },
18706 {"msp", 8 }, {"MSP", 8 },
18707 {"psp", 9 }, {"PSP", 9 },
18708 {"primask", 16}, {"PRIMASK", 16},
18709 {"basepri", 17}, {"BASEPRI", 17},
18710 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18711 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
18712 {"faultmask", 19}, {"FAULTMASK", 19},
18713 {"control", 20}, {"CONTROL", 20}
18716 /* Table of all shift-in-operand names. */
18717 static const struct asm_shift_name shift_names
[] =
18719 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18720 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18721 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18722 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18723 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18724 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18727 /* Table of all explicit relocation names. */
18729 static struct reloc_entry reloc_names
[] =
18731 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18732 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18733 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18734 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18735 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18736 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18737 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18738 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18739 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18740 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18741 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18742 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18743 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18744 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18745 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18746 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18747 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18748 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18752 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18753 static const struct asm_cond conds
[] =
18757 {"cs", 0x2}, {"hs", 0x2},
18758 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18772 #define UL_BARRIER(L,U,CODE,FEAT) \
18773 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18774 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18776 static struct asm_barrier_opt barrier_opt_names
[] =
18778 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
18779 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
18780 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
18781 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
18782 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
18783 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
18784 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
18785 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
18786 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
18787 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
18788 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
18789 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
18790 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
18791 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
18792 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
18793 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
18798 /* Table of ARM-format instructions. */
18800 /* Macros for gluing together operand strings. N.B. In all cases
18801 other than OPS0, the trailing OP_stop comes from default
18802 zero-initialization of the unspecified elements of the array. */
18803 #define OPS0() { OP_stop, }
18804 #define OPS1(a) { OP_##a, }
18805 #define OPS2(a,b) { OP_##a,OP_##b, }
18806 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18807 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18808 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18809 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18811 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18812 This is useful when mixing operands for ARM and THUMB, i.e. using the
18813 MIX_ARM_THUMB_OPERANDS macro.
18814 In order to use these macros, prefix the number of operands with _
18816 #define OPS_1(a) { a, }
18817 #define OPS_2(a,b) { a,b, }
18818 #define OPS_3(a,b,c) { a,b,c, }
18819 #define OPS_4(a,b,c,d) { a,b,c,d, }
18820 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18821 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18823 /* These macros abstract out the exact format of the mnemonic table and
18824 save some repeated characters. */
18826 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18827 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18828 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18829 THUMB_VARIANT, do_##ae, do_##te }
18831 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18832 a T_MNEM_xyz enumerator. */
18833 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18834 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18835 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18836 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18838 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18839 infix after the third character. */
18840 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18841 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18842 THUMB_VARIANT, do_##ae, do_##te }
18843 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18844 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18845 THUMB_VARIANT, do_##ae, do_##te }
18846 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18847 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18848 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18849 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18850 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18851 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18852 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18853 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18855 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18856 field is still 0xE. Many of the Thumb variants can be executed
18857 conditionally, so this is checked separately. */
18858 #define TUE(mnem, op, top, nops, ops, ae, te) \
18859 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18860 THUMB_VARIANT, do_##ae, do_##te }
18862 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18863 Used by mnemonics that have very minimal differences in the encoding for
18864 ARM and Thumb variants and can be handled in a common function. */
18865 #define TUEc(mnem, op, top, nops, ops, en) \
18866 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18867 THUMB_VARIANT, do_##en, do_##en }
18869 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18870 condition code field. */
18871 #define TUF(mnem, op, top, nops, ops, ae, te) \
18872 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18873 THUMB_VARIANT, do_##ae, do_##te }
18875 /* ARM-only variants of all the above. */
18876 #define CE(mnem, op, nops, ops, ae) \
18877 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18879 #define C3(mnem, op, nops, ops, ae) \
18880 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18882 /* Legacy mnemonics that always have conditional infix after the third
18884 #define CL(mnem, op, nops, ops, ae) \
18885 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18886 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18888 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18889 #define cCE(mnem, op, nops, ops, ae) \
18890 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18892 /* Legacy coprocessor instructions where conditional infix and conditional
18893 suffix are ambiguous. For consistency this includes all FPA instructions,
18894 not just the potentially ambiguous ones. */
18895 #define cCL(mnem, op, nops, ops, ae) \
18896 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18897 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18899 /* Coprocessor, takes either a suffix or a position-3 infix
18900 (for an FPA corner case). */
18901 #define C3E(mnem, op, nops, ops, ae) \
18902 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18903 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18905 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18906 { m1 #m2 m3, OPS##nops ops, \
18907 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18908 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18910 #define CM(m1, m2, op, nops, ops, ae) \
18911 xCM_ (m1, , m2, op, nops, ops, ae), \
18912 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18913 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18914 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18915 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18916 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18917 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18918 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18919 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18920 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18921 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18922 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18923 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18924 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18925 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18926 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18927 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18928 xCM_ (m1, le, m2, op, nops, ops, ae), \
18929 xCM_ (m1, al, m2, op, nops, ops, ae)
18931 #define UE(mnem, op, nops, ops, ae) \
18932 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18934 #define UF(mnem, op, nops, ops, ae) \
18935 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18937 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
18938 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
18939 use the same encoding function for each. */
18940 #define NUF(mnem, op, nops, ops, enc) \
18941 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
18942 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18944 /* Neon data processing, version which indirects through neon_enc_tab for
18945 the various overloaded versions of opcodes. */
18946 #define nUF(mnem, op, nops, ops, enc) \
18947 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
18948 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18950 /* Neon insn with conditional suffix for the ARM version, non-overloaded
18952 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
18953 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
18954 THUMB_VARIANT, do_##enc, do_##enc }
18956 #define NCE(mnem, op, nops, ops, enc) \
18957 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18959 #define NCEF(mnem, op, nops, ops, enc) \
18960 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18962 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
18963 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
18964 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
18965 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18967 #define nCE(mnem, op, nops, ops, enc) \
18968 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18970 #define nCEF(mnem, op, nops, ops, enc) \
18971 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18975 static const struct asm_opcode insns
[] =
18977 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
18978 #define THUMB_VARIANT & arm_ext_v4t
18979 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18980 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18981 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18982 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18983 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18984 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18985 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18986 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18987 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18988 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18989 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18990 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18991 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18992 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18993 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18994 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18996 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18997 for setting PSR flag bits. They are obsolete in V6 and do not
18998 have Thumb equivalents. */
18999 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19000 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19001 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19002 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19003 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19004 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19005 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19006 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19007 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19009 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19010 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19011 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19012 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19014 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19015 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19016 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19018 OP_ADDRGLDR
),ldst
, t_ldst
),
19019 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19021 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19022 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19023 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19024 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19025 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19026 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19028 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19029 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19030 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19031 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19034 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19035 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19036 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19037 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19039 /* Thumb-compatibility pseudo ops. */
19040 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19041 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19042 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19043 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19044 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19045 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19046 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19047 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19048 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19049 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19050 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19051 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19053 /* These may simplify to neg. */
19054 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19055 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19057 #undef THUMB_VARIANT
19058 #define THUMB_VARIANT & arm_ext_v6
19060 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19062 /* V1 instructions with no Thumb analogue prior to V6T2. */
19063 #undef THUMB_VARIANT
19064 #define THUMB_VARIANT & arm_ext_v6t2
19066 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19067 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19068 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19070 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19071 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19072 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19073 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19075 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19076 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19078 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19079 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19081 /* V1 instructions with no Thumb analogue at all. */
19082 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19083 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19085 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19086 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19087 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19088 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19089 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19090 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19091 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19092 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19095 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19096 #undef THUMB_VARIANT
19097 #define THUMB_VARIANT & arm_ext_v4t
19099 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19100 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19102 #undef THUMB_VARIANT
19103 #define THUMB_VARIANT & arm_ext_v6t2
19105 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19106 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19108 /* Generic coprocessor instructions. */
19109 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19110 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19111 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19112 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19113 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19114 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19115 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19118 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19120 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19121 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19124 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19125 #undef THUMB_VARIANT
19126 #define THUMB_VARIANT & arm_ext_msr
19128 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19129 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19132 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19133 #undef THUMB_VARIANT
19134 #define THUMB_VARIANT & arm_ext_v6t2
19136 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19137 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19138 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19139 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19140 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19141 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19142 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19143 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19146 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19147 #undef THUMB_VARIANT
19148 #define THUMB_VARIANT & arm_ext_v4t
19150 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19151 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19152 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19153 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19154 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19155 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19158 #define ARM_VARIANT & arm_ext_v4t_5
19160 /* ARM Architecture 4T. */
19161 /* Note: bx (and blx) are required on V5, even if the processor does
19162 not support Thumb. */
19163 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19166 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19167 #undef THUMB_VARIANT
19168 #define THUMB_VARIANT & arm_ext_v5t
19170 /* Note: blx has 2 variants; the .value coded here is for
19171 BLX(2). Only this variant has conditional execution. */
19172 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19173 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19175 #undef THUMB_VARIANT
19176 #define THUMB_VARIANT & arm_ext_v6t2
19178 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19179 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19180 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19181 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19182 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19183 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19184 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19185 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19188 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19189 #undef THUMB_VARIANT
19190 #define THUMB_VARIANT & arm_ext_v5exp
19192 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19193 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19194 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19195 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19197 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19198 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19200 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19201 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19202 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19203 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19205 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19206 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19207 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19208 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19210 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19211 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19213 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19214 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19215 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19216 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19219 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19220 #undef THUMB_VARIANT
19221 #define THUMB_VARIANT & arm_ext_v6t2
19223 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19224 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19226 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19227 ADDRGLDRS
), ldrd
, t_ldstd
),
19229 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19230 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19233 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19235 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19238 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19239 #undef THUMB_VARIANT
19240 #define THUMB_VARIANT & arm_ext_v6
19242 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19243 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19244 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19245 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19246 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19247 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19248 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19249 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19250 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19251 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19253 #undef THUMB_VARIANT
19254 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19256 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19257 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19259 #undef THUMB_VARIANT
19260 #define THUMB_VARIANT & arm_ext_v6t2
19262 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19263 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19265 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19266 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19268 /* ARM V6 not included in V7M. */
19269 #undef THUMB_VARIANT
19270 #define THUMB_VARIANT & arm_ext_v6_notm
19271 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19272 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19273 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19274 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19275 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19276 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19277 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19278 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19279 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19280 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19281 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19282 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19283 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19284 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19285 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19286 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19287 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19288 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19289 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19291 /* ARM V6 not included in V7M (eg. integer SIMD). */
19292 #undef THUMB_VARIANT
19293 #define THUMB_VARIANT & arm_ext_v6_dsp
19294 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19295 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19296 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19297 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19298 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19299 /* Old name for QASX. */
19300 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19301 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19302 /* Old name for QSAX. */
19303 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19304 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19305 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19306 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19307 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19308 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19309 /* Old name for SASX. */
19310 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19311 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19312 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19313 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19314 /* Old name for SHASX. */
19315 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19316 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19317 /* Old name for SHSAX. */
19318 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19319 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19320 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19321 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19322 /* Old name for SSAX. */
19323 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19324 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19325 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19326 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19327 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19328 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19329 /* Old name for UASX. */
19330 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19331 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19332 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19333 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19334 /* Old name for UHASX. */
19335 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19336 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19337 /* Old name for UHSAX. */
19338 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19339 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19340 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19341 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19342 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19343 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19344 /* Old name for UQASX. */
19345 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19346 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19347 /* Old name for UQSAX. */
19348 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19349 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19350 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19351 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19352 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19353 /* Old name for USAX. */
19354 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19355 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19356 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19357 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19358 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19359 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19360 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19361 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19362 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19363 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19364 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19365 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19366 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19367 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19368 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19369 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19370 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19371 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19372 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19373 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19374 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19375 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19376 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19377 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19378 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19379 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19380 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19381 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19382 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19383 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19384 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19385 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19386 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19387 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19390 #define ARM_VARIANT & arm_ext_v6k
19391 #undef THUMB_VARIANT
19392 #define THUMB_VARIANT & arm_ext_v6k
19394 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19395 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19396 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19397 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19399 #undef THUMB_VARIANT
19400 #define THUMB_VARIANT & arm_ext_v6_notm
19401 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19403 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19404 RRnpcb
), strexd
, t_strexd
),
19406 #undef THUMB_VARIANT
19407 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19408 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19410 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19412 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19414 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19416 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19419 #define ARM_VARIANT & arm_ext_sec
19420 #undef THUMB_VARIANT
19421 #define THUMB_VARIANT & arm_ext_sec
19423 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19426 #define ARM_VARIANT & arm_ext_virt
19427 #undef THUMB_VARIANT
19428 #define THUMB_VARIANT & arm_ext_virt
19430 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19431 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19434 #define ARM_VARIANT & arm_ext_pan
19435 #undef THUMB_VARIANT
19436 #define THUMB_VARIANT & arm_ext_pan
19438 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19441 #define ARM_VARIANT & arm_ext_v6t2
19442 #undef THUMB_VARIANT
19443 #define THUMB_VARIANT & arm_ext_v6t2
19445 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19446 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19447 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19448 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19450 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19451 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19453 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19454 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19455 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19456 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19458 #undef THUMB_VARIANT
19459 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19460 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19461 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19463 /* Thumb-only instructions. */
19465 #define ARM_VARIANT NULL
19466 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19467 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19469 /* ARM does not really have an IT instruction, so always allow it.
19470 The opcode is copied from Thumb in order to allow warnings in
19471 -mimplicit-it=[never | arm] modes. */
19473 #define ARM_VARIANT & arm_ext_v1
19474 #undef THUMB_VARIANT
19475 #define THUMB_VARIANT & arm_ext_v6t2
19477 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19478 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19479 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19480 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19481 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19482 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19483 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19484 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19485 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19486 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19487 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19488 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19489 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19490 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19491 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19492 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19493 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19494 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19496 /* Thumb2 only instructions. */
19498 #define ARM_VARIANT NULL
19500 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19501 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19502 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19503 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19504 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19505 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19507 /* Hardware division instructions. */
19509 #define ARM_VARIANT & arm_ext_adiv
19510 #undef THUMB_VARIANT
19511 #define THUMB_VARIANT & arm_ext_div
19513 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19514 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19516 /* ARM V6M/V7 instructions. */
19518 #define ARM_VARIANT & arm_ext_barrier
19519 #undef THUMB_VARIANT
19520 #define THUMB_VARIANT & arm_ext_barrier
19522 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19523 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19524 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19526 /* ARM V7 instructions. */
19528 #define ARM_VARIANT & arm_ext_v7
19529 #undef THUMB_VARIANT
19530 #define THUMB_VARIANT & arm_ext_v7
19532 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19533 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19536 #define ARM_VARIANT & arm_ext_mp
19537 #undef THUMB_VARIANT
19538 #define THUMB_VARIANT & arm_ext_mp
19540 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19542 /* AArchv8 instructions. */
19544 #define ARM_VARIANT & arm_ext_v8
19546 /* Instructions shared between armv8-a and armv8-m. */
19547 #undef THUMB_VARIANT
19548 #define THUMB_VARIANT & arm_ext_atomics
19550 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19551 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19552 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19553 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19554 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19555 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19556 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19557 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19558 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19559 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19561 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19563 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19565 #undef THUMB_VARIANT
19566 #define THUMB_VARIANT & arm_ext_v8
19568 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19569 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19570 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19572 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19574 /* ARMv8 T32 only. */
19576 #define ARM_VARIANT NULL
19577 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19578 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19579 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19581 /* FP for ARMv8. */
19583 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19584 #undef THUMB_VARIANT
19585 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19587 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19588 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19589 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19590 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19591 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19592 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19593 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19594 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19595 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19596 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19597 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19598 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19599 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19600 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19601 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19602 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19603 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19605 /* Crypto v1 extensions. */
19607 #define ARM_VARIANT & fpu_crypto_ext_armv8
19608 #undef THUMB_VARIANT
19609 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19611 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19612 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19613 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19614 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19615 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19616 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19617 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19618 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19619 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19620 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19621 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19622 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19623 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19624 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19627 #define ARM_VARIANT & crc_ext_armv8
19628 #undef THUMB_VARIANT
19629 #define THUMB_VARIANT & crc_ext_armv8
19630 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19631 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19632 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19633 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19634 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19635 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19637 /* ARMv8.2 RAS extension. */
19639 #define ARM_VARIANT & arm_ext_v8_2
19640 #undef THUMB_VARIANT
19641 #define THUMB_VARIANT & arm_ext_v8_2
19642 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
19645 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19646 #undef THUMB_VARIANT
19647 #define THUMB_VARIANT NULL
19649 cCE("wfs", e200110
, 1, (RR
), rd
),
19650 cCE("rfs", e300110
, 1, (RR
), rd
),
19651 cCE("wfc", e400110
, 1, (RR
), rd
),
19652 cCE("rfc", e500110
, 1, (RR
), rd
),
19654 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19655 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19656 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19657 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19659 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19660 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19661 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19662 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19664 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19665 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19666 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19667 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19668 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19669 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19670 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19671 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19672 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19673 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19674 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19675 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19677 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19678 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19679 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19680 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19681 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19682 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19683 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19684 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19685 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19686 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19687 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19688 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19690 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19691 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19692 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19693 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19694 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19695 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19696 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19697 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19698 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19699 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19700 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19701 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19703 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19704 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19705 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19706 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19707 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19708 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19709 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19710 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19711 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19712 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19713 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19714 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19716 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19717 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19718 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19719 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19720 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19721 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19722 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19723 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19724 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19725 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19726 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19727 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19729 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19730 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19731 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19732 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19733 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19734 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19735 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19736 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19737 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19738 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19739 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19740 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19742 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19743 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19744 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19745 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19746 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19747 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19748 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19749 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19750 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19751 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19752 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19753 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19755 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19756 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19757 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19758 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19759 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19760 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
19761 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
19762 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
19763 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
19764 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
19765 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
19766 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
19768 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
19769 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
19770 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
19771 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
19772 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
19773 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
19774 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
19775 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
19776 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
19777 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
19778 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
19779 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
19781 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
19782 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
19783 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
19784 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
19785 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
19786 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
19787 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
19788 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
19789 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
19790 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
19791 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
19792 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
19794 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
19795 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
19796 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
19797 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
19798 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
19799 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
19800 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
19801 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
19802 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
19803 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
19804 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
19805 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
19807 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
19808 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
19809 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
19810 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
19811 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
19812 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
19813 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
19814 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
19815 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
19816 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
19817 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
19818 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
19820 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
19821 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
19822 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
19823 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
19824 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
19825 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
19826 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
19827 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
19828 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
19829 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
19830 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
19831 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
19833 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
19834 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
19835 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
19836 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
19837 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
19838 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
19839 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
19840 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
19841 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
19842 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
19843 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
19844 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
19846 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
19847 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
19848 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
19849 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
19850 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
19851 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19852 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19853 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19854 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19855 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19856 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19857 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19859 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19860 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19861 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19862 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19863 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19864 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19865 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19866 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19867 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19868 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19869 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19870 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19872 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19873 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19874 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19875 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19876 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19877 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19878 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19879 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19880 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19881 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19882 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19883 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19885 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19886 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19887 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19888 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19889 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19890 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19891 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19892 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19893 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19894 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19895 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19896 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19898 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19899 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19900 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19901 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19902 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19903 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19904 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19905 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19906 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19907 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19908 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19909 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19911 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19912 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19913 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19914 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19915 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19916 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19917 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19918 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19919 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19920 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19921 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19922 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19924 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19925 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19926 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19927 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19928 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19929 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19930 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19931 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19932 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19933 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19934 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19935 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19937 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19938 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19939 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19940 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19941 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19942 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19943 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19944 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19945 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19946 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19947 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19948 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19950 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19951 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19952 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19953 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19954 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19955 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19956 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19957 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19958 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19959 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19960 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19961 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19963 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19964 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19965 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19966 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19967 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19968 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19969 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19970 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19971 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19972 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19973 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19974 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19976 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19977 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19978 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19979 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19980 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19981 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19982 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19983 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19984 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19985 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19986 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19987 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19989 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19990 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19991 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19992 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19993 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19994 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19995 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19996 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19997 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19998 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19999 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20000 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20002 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20003 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20004 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20005 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20006 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20007 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20008 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20009 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20010 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20011 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20012 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20013 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20015 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20016 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20017 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20018 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20019 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20020 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20021 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20022 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20023 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20024 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20025 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20026 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20028 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20029 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20030 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20031 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20032 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20033 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20034 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20035 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20036 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20037 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20038 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20039 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20041 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20042 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20043 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20044 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20046 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20047 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20048 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20049 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20050 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20051 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20052 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20053 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20054 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20055 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20056 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20057 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20059 /* The implementation of the FIX instruction is broken on some
20060 assemblers, in that it accepts a precision specifier as well as a
20061 rounding specifier, despite the fact that this is meaningless.
20062 To be more compatible, we accept it as well, though of course it
20063 does not set any bits. */
20064 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20065 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20066 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20067 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20068 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20069 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20070 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20071 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20072 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20073 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20074 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20075 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20076 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20078 /* Instructions that were new with the real FPA, call them V2. */
20080 #define ARM_VARIANT & fpu_fpa_ext_v2
20082 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20083 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20084 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20085 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20086 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20087 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20090 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20092 /* Moves and type conversions. */
20093 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20094 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20095 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20096 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20097 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20098 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20099 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20100 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20101 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20102 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20103 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20104 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20105 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20106 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20108 /* Memory operations. */
20109 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20110 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20111 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20112 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20113 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20114 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20115 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20116 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20117 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20118 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20119 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20120 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20121 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20122 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20123 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20124 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20125 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20126 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20128 /* Monadic operations. */
20129 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20130 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20131 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20133 /* Dyadic operations. */
20134 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20135 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20136 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20137 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20138 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20139 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20140 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20141 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20142 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20145 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20146 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20147 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20148 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20150 /* Double precision load/store are still present on single precision
20151 implementations. */
20152 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20153 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20154 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20155 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20156 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20157 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20158 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20159 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20160 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20161 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20164 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20166 /* Moves and type conversions. */
20167 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20168 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20169 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20170 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20171 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20172 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20173 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20174 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20175 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20176 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20177 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20178 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20179 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20181 /* Monadic operations. */
20182 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20183 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20184 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20186 /* Dyadic operations. */
20187 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20188 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20189 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20190 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20191 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20192 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20193 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20194 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20195 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20198 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20199 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20200 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20201 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20204 #define ARM_VARIANT & fpu_vfp_ext_v2
20206 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20207 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20208 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20209 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20211 /* Instructions which may belong to either the Neon or VFP instruction sets.
20212 Individual encoder functions perform additional architecture checks. */
20214 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20215 #undef THUMB_VARIANT
20216 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20218 /* These mnemonics are unique to VFP. */
20219 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20220 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20221 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20222 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20223 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20224 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20225 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20226 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20227 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20228 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20230 /* Mnemonics shared by Neon and VFP. */
20231 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20232 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20233 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20235 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20236 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20238 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20239 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20241 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20242 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20243 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20244 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20245 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20246 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20247 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20248 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20250 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20251 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20252 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20253 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20256 /* NOTE: All VMOV encoding is special-cased! */
20257 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20258 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20261 #define ARM_VARIANT & arm_ext_fp16
20262 #undef THUMB_VARIANT
20263 #define THUMB_VARIANT & arm_ext_fp16
20264 /* New instructions added from v8.2, allowing the extraction and insertion of
20265 the upper 16 bits of a 32-bit vector register. */
20266 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20267 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20269 #undef THUMB_VARIANT
20270 #define THUMB_VARIANT & fpu_neon_ext_v1
20272 #define ARM_VARIANT & fpu_neon_ext_v1
20274 /* Data processing with three registers of the same length. */
20275 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20276 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20277 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20278 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20279 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20280 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20281 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20282 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20283 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20284 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20285 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20286 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20287 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20288 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20289 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20290 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20291 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20292 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20293 /* If not immediate, fall back to neon_dyadic_i64_su.
20294 shl_imm should accept I8 I16 I32 I64,
20295 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20296 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20297 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20298 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20299 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20300 /* Logic ops, types optional & ignored. */
20301 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20302 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20303 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20304 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20305 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20306 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20307 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20308 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20309 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20310 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20311 /* Bitfield ops, untyped. */
20312 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20313 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20314 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20315 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20316 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20317 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20318 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
20319 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20320 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20321 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20322 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20323 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20324 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20325 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20326 back to neon_dyadic_if_su. */
20327 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20328 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20329 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20330 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20331 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20332 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20333 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20334 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20335 /* Comparison. Type I8 I16 I32 F32. */
20336 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20337 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20338 /* As above, D registers only. */
20339 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20340 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20341 /* Int and float variants, signedness unimportant. */
20342 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20343 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20344 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20345 /* Add/sub take types I8 I16 I32 I64 F32. */
20346 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20347 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20348 /* vtst takes sizes 8, 16, 32. */
20349 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20350 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20351 /* VMUL takes I8 I16 I32 F32 P8. */
20352 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20353 /* VQD{R}MULH takes S16 S32. */
20354 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20355 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20356 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20357 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20358 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20359 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20360 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20361 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20362 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20363 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20364 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20365 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20366 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20367 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20368 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20369 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20370 /* ARM v8.1 extension. */
20371 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20372 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20373 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20374 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20376 /* Two address, int/float. Types S8 S16 S32 F32. */
20377 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20378 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20380 /* Data processing with two registers and a shift amount. */
20381 /* Right shifts, and variants with rounding.
20382 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20383 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20384 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20385 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20386 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20387 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20388 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20389 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20390 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20391 /* Shift and insert. Sizes accepted 8 16 32 64. */
20392 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20393 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20394 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20395 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20396 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20397 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20398 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20399 /* Right shift immediate, saturating & narrowing, with rounding variants.
20400 Types accepted S16 S32 S64 U16 U32 U64. */
20401 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20402 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20403 /* As above, unsigned. Types accepted S16 S32 S64. */
20404 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20405 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20406 /* Right shift narrowing. Types accepted I16 I32 I64. */
20407 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20408 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20409 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20410 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20411 /* CVT with optional immediate for fixed-point variant. */
20412 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20414 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20415 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20417 /* Data processing, three registers of different lengths. */
20418 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20419 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20420 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20421 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20422 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20423 /* If not scalar, fall back to neon_dyadic_long.
20424 Vector types as above, scalar types S16 S32 U16 U32. */
20425 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20426 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20427 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20428 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20429 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20430 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20431 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20432 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20433 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20434 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20435 /* Saturating doubling multiplies. Types S16 S32. */
20436 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20437 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20438 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20439 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20440 S16 S32 U16 U32. */
20441 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20443 /* Extract. Size 8. */
20444 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20445 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20447 /* Two registers, miscellaneous. */
20448 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20449 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20450 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20451 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20452 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20453 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20454 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20455 /* Vector replicate. Sizes 8 16 32. */
20456 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20457 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20458 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20459 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20460 /* VMOVN. Types I16 I32 I64. */
20461 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20462 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20463 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20464 /* VQMOVUN. Types S16 S32 S64. */
20465 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20466 /* VZIP / VUZP. Sizes 8 16 32. */
20467 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20468 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20469 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20470 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20471 /* VQABS / VQNEG. Types S8 S16 S32. */
20472 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20473 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20474 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20475 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20476 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20477 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20478 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20479 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20480 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20481 /* Reciprocal estimates. Types U32 F32. */
20482 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20483 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20484 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20485 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20486 /* VCLS. Types S8 S16 S32. */
20487 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20488 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20489 /* VCLZ. Types I8 I16 I32. */
20490 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20491 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20492 /* VCNT. Size 8. */
20493 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20494 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20495 /* Two address, untyped. */
20496 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20497 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20498 /* VTRN. Sizes 8 16 32. */
20499 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20500 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20502 /* Table lookup. Size 8. */
20503 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20504 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20506 #undef THUMB_VARIANT
20507 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20509 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20511 /* Neon element/structure load/store. */
20512 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20513 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20514 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20515 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20516 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20517 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20518 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20519 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20521 #undef THUMB_VARIANT
20522 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20524 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20525 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20526 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20527 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20528 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20529 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20530 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20531 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20532 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20533 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20535 #undef THUMB_VARIANT
20536 #define THUMB_VARIANT & fpu_vfp_ext_v3
20538 #define ARM_VARIANT & fpu_vfp_ext_v3
20540 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20541 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20542 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20543 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20544 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20545 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20546 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20547 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20548 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20551 #define ARM_VARIANT & fpu_vfp_ext_fma
20552 #undef THUMB_VARIANT
20553 #define THUMB_VARIANT & fpu_vfp_ext_fma
20554 /* Mnemonics shared by Neon and VFP. These are included in the
20555 VFP FMA variant; NEON and VFP FMA always includes the NEON
20556 FMA instructions. */
20557 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20558 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20559 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20560 the v form should always be used. */
20561 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20562 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20563 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20564 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20565 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20566 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20568 #undef THUMB_VARIANT
20570 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20572 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20573 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20574 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20575 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20576 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20577 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20578 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20579 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20582 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20584 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20585 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20586 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20587 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20588 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20589 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20590 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20591 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20592 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20593 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20594 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20595 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20596 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20597 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20598 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20599 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20600 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20601 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20602 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20603 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20604 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20605 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20606 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20607 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20608 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20609 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20610 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20611 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20612 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20613 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20614 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20615 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20616 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20617 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20618 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20619 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20620 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20621 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20622 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20623 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20624 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20625 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20626 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20627 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20628 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20629 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20630 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20631 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20632 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20633 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20634 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20635 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20636 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20637 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20638 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20639 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20640 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20641 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20642 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20643 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20644 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20645 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20646 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20647 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20648 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20649 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20650 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20651 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20652 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20653 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20654 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20655 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20656 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20657 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20658 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20659 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20660 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20661 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20662 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20663 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20664 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20665 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20666 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20667 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20668 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20669 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20670 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20671 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20672 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20673 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20674 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20675 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20676 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20677 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20678 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20679 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20680 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20681 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20682 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20683 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20684 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20685 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20686 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20687 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20688 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20689 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20690 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20691 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20692 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20693 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20694 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20695 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20696 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20697 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20698 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20699 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20700 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20701 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20702 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20703 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20704 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20705 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20706 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20707 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20708 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20709 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20710 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20711 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20712 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20713 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20714 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20715 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20716 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20717 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20718 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20719 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20720 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20721 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20722 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20723 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20724 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20725 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20726 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20727 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20728 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20729 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20730 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20731 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20732 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20733 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20734 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20735 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20736 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20737 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20738 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20739 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20740 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20741 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20742 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20743 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20744 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20745 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20748 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20750 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20751 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20752 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20753 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20754 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20755 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20756 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20757 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20758 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20759 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20760 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20761 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20762 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20763 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20764 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20765 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20766 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20767 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20768 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20769 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20770 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
20771 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20772 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20773 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20774 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20775 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20776 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20777 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20778 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20779 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20780 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20781 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20782 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20783 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20784 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20785 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20786 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20787 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20788 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20789 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20790 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20791 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20792 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20793 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20794 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20795 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20796 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20797 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20798 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20799 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20800 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20801 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20802 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20803 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20804 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20805 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20806 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20809 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20811 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20812 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20813 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20814 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20815 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20816 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20817 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20818 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20819 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
20820 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
20821 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
20822 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
20823 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
20824 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
20825 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
20826 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
20827 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
20828 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
20829 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
20830 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
20831 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
20832 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
20833 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
20834 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
20835 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
20836 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
20837 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
20838 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
20839 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
20840 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
20841 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
20842 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
20843 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
20844 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
20845 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
20846 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
20847 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
20848 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
20849 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
20850 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
20851 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
20852 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
20853 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
20854 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
20855 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
20856 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
20857 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
20858 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
20859 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
20860 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
20861 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
20862 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
20863 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
20864 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
20865 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20866 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20867 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20868 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20869 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20870 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20871 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20872 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20873 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20874 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20875 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20876 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20877 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20878 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20879 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20880 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20881 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20882 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20883 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20884 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20885 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20886 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20889 #define ARM_VARIANT NULL
20890 #undef THUMB_VARIANT
20891 #define THUMB_VARIANT & arm_ext_v8m
20892 TUE("tt", 0, e840f000
, 2, (RRnpc
, RRnpc
), 0, tt
),
20893 TUE("ttt", 0, e840f040
, 2, (RRnpc
, RRnpc
), 0, tt
),
20896 #undef THUMB_VARIANT
20922 /* MD interface: bits in the object file. */
20924 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20925 for use in the a.out file, and stores them in the array pointed to by buf.
20926 This knows about the endian-ness of the target machine and does
20927 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20928 2 (short) and 4 (long) Floating numbers are put out as a series of
20929 LITTLENUMS (shorts, here at least). */
20932 md_number_to_chars (char * buf
, valueT val
, int n
)
20934 if (target_big_endian
)
20935 number_to_chars_bigendian (buf
, val
, n
);
20937 number_to_chars_littleendian (buf
, val
, n
);
20941 md_chars_to_number (char * buf
, int n
)
20944 unsigned char * where
= (unsigned char *) buf
;
20946 if (target_big_endian
)
20951 result
|= (*where
++ & 255);
20959 result
|= (where
[n
] & 255);
20966 /* MD interface: Sections. */
20968 /* Calculate the maximum variable size (i.e., excluding fr_fix)
20969 that an rs_machine_dependent frag may reach. */
20972 arm_frag_max_var (fragS
*fragp
)
20974 /* We only use rs_machine_dependent for variable-size Thumb instructions,
20975 which are either THUMB_SIZE (2) or INSN_SIZE (4).
20977 Note that we generate relaxable instructions even for cases that don't
20978 really need it, like an immediate that's a trivial constant. So we're
20979 overestimating the instruction size for some of those cases. Rather
20980 than putting more intelligence here, it would probably be better to
20981 avoid generating a relaxation frag in the first place when it can be
20982 determined up front that a short instruction will suffice. */
20984 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
20988 /* Estimate the size of a frag before relaxing. Assume everything fits in
20992 md_estimate_size_before_relax (fragS
* fragp
,
20993 segT segtype ATTRIBUTE_UNUSED
)
20999 /* Convert a machine dependent frag. */
21002 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21004 unsigned long insn
;
21005 unsigned long old_op
;
21013 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21015 old_op
= bfd_get_16(abfd
, buf
);
21016 if (fragp
->fr_symbol
)
21018 exp
.X_op
= O_symbol
;
21019 exp
.X_add_symbol
= fragp
->fr_symbol
;
21023 exp
.X_op
= O_constant
;
21025 exp
.X_add_number
= fragp
->fr_offset
;
21026 opcode
= fragp
->fr_subtype
;
21029 case T_MNEM_ldr_pc
:
21030 case T_MNEM_ldr_pc2
:
21031 case T_MNEM_ldr_sp
:
21032 case T_MNEM_str_sp
:
21039 if (fragp
->fr_var
== 4)
21041 insn
= THUMB_OP32 (opcode
);
21042 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21044 insn
|= (old_op
& 0x700) << 4;
21048 insn
|= (old_op
& 7) << 12;
21049 insn
|= (old_op
& 0x38) << 13;
21051 insn
|= 0x00000c00;
21052 put_thumb32_insn (buf
, insn
);
21053 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21057 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21059 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21062 if (fragp
->fr_var
== 4)
21064 insn
= THUMB_OP32 (opcode
);
21065 insn
|= (old_op
& 0xf0) << 4;
21066 put_thumb32_insn (buf
, insn
);
21067 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21071 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21072 exp
.X_add_number
-= 4;
21080 if (fragp
->fr_var
== 4)
21082 int r0off
= (opcode
== T_MNEM_mov
21083 || opcode
== T_MNEM_movs
) ? 0 : 8;
21084 insn
= THUMB_OP32 (opcode
);
21085 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21086 insn
|= (old_op
& 0x700) << r0off
;
21087 put_thumb32_insn (buf
, insn
);
21088 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21092 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21097 if (fragp
->fr_var
== 4)
21099 insn
= THUMB_OP32(opcode
);
21100 put_thumb32_insn (buf
, insn
);
21101 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21104 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21108 if (fragp
->fr_var
== 4)
21110 insn
= THUMB_OP32(opcode
);
21111 insn
|= (old_op
& 0xf00) << 14;
21112 put_thumb32_insn (buf
, insn
);
21113 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21116 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21119 case T_MNEM_add_sp
:
21120 case T_MNEM_add_pc
:
21121 case T_MNEM_inc_sp
:
21122 case T_MNEM_dec_sp
:
21123 if (fragp
->fr_var
== 4)
21125 /* ??? Choose between add and addw. */
21126 insn
= THUMB_OP32 (opcode
);
21127 insn
|= (old_op
& 0xf0) << 4;
21128 put_thumb32_insn (buf
, insn
);
21129 if (opcode
== T_MNEM_add_pc
)
21130 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21132 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21135 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21143 if (fragp
->fr_var
== 4)
21145 insn
= THUMB_OP32 (opcode
);
21146 insn
|= (old_op
& 0xf0) << 4;
21147 insn
|= (old_op
& 0xf) << 16;
21148 put_thumb32_insn (buf
, insn
);
21149 if (insn
& (1 << 20))
21150 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21152 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21155 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21161 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21162 (enum bfd_reloc_code_real
) reloc_type
);
21163 fixp
->fx_file
= fragp
->fr_file
;
21164 fixp
->fx_line
= fragp
->fr_line
;
21165 fragp
->fr_fix
+= fragp
->fr_var
;
21167 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21168 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21169 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21170 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21173 /* Return the size of a relaxable immediate operand instruction.
21174 SHIFT and SIZE specify the form of the allowable immediate. */
21176 relax_immediate (fragS
*fragp
, int size
, int shift
)
21182 /* ??? Should be able to do better than this. */
21183 if (fragp
->fr_symbol
)
21186 low
= (1 << shift
) - 1;
21187 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21188 offset
= fragp
->fr_offset
;
21189 /* Force misaligned offsets to 32-bit variant. */
21192 if (offset
& ~mask
)
21197 /* Get the address of a symbol during relaxation. */
21199 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21205 sym
= fragp
->fr_symbol
;
21206 sym_frag
= symbol_get_frag (sym
);
21207 know (S_GET_SEGMENT (sym
) != absolute_section
21208 || sym_frag
== &zero_address_frag
);
21209 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21211 /* If frag has yet to be reached on this pass, assume it will
21212 move by STRETCH just as we did. If this is not so, it will
21213 be because some frag between grows, and that will force
21217 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21221 /* Adjust stretch for any alignment frag. Note that if have
21222 been expanding the earlier code, the symbol may be
21223 defined in what appears to be an earlier frag. FIXME:
21224 This doesn't handle the fr_subtype field, which specifies
21225 a maximum number of bytes to skip when doing an
21227 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21229 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21232 stretch
= - ((- stretch
)
21233 & ~ ((1 << (int) f
->fr_offset
) - 1));
21235 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21247 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21250 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21255 /* Assume worst case for symbols not known to be in the same section. */
21256 if (fragp
->fr_symbol
== NULL
21257 || !S_IS_DEFINED (fragp
->fr_symbol
)
21258 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21259 || S_IS_WEAK (fragp
->fr_symbol
))
21262 val
= relaxed_symbol_addr (fragp
, stretch
);
21263 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21264 addr
= (addr
+ 4) & ~3;
21265 /* Force misaligned targets to 32-bit variant. */
21269 if (val
< 0 || val
> 1020)
21274 /* Return the size of a relaxable add/sub immediate instruction. */
21276 relax_addsub (fragS
*fragp
, asection
*sec
)
21281 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21282 op
= bfd_get_16(sec
->owner
, buf
);
21283 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21284 return relax_immediate (fragp
, 8, 0);
21286 return relax_immediate (fragp
, 3, 0);
21289 /* Return TRUE iff the definition of symbol S could be pre-empted
21290 (overridden) at link or load time. */
21292 symbol_preemptible (symbolS
*s
)
21294 /* Weak symbols can always be pre-empted. */
21298 /* Non-global symbols cannot be pre-empted. */
21299 if (! S_IS_EXTERNAL (s
))
21303 /* In ELF, a global symbol can be marked protected, or private. In that
21304 case it can't be pre-empted (other definitions in the same link unit
21305 would violate the ODR). */
21306 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21310 /* Other global symbols might be pre-empted. */
21314 /* Return the size of a relaxable branch instruction. BITS is the
21315 size of the offset field in the narrow instruction. */
21318 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21324 /* Assume worst case for symbols not known to be in the same section. */
21325 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21326 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21327 || S_IS_WEAK (fragp
->fr_symbol
))
21331 /* A branch to a function in ARM state will require interworking. */
21332 if (S_IS_DEFINED (fragp
->fr_symbol
)
21333 && ARM_IS_FUNC (fragp
->fr_symbol
))
21337 if (symbol_preemptible (fragp
->fr_symbol
))
21340 val
= relaxed_symbol_addr (fragp
, stretch
);
21341 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21344 /* Offset is a signed value *2 */
21346 if (val
>= limit
|| val
< -limit
)
21352 /* Relax a machine dependent frag. This returns the amount by which
21353 the current size of the frag should change. */
21356 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21361 oldsize
= fragp
->fr_var
;
21362 switch (fragp
->fr_subtype
)
21364 case T_MNEM_ldr_pc2
:
21365 newsize
= relax_adr (fragp
, sec
, stretch
);
21367 case T_MNEM_ldr_pc
:
21368 case T_MNEM_ldr_sp
:
21369 case T_MNEM_str_sp
:
21370 newsize
= relax_immediate (fragp
, 8, 2);
21374 newsize
= relax_immediate (fragp
, 5, 2);
21378 newsize
= relax_immediate (fragp
, 5, 1);
21382 newsize
= relax_immediate (fragp
, 5, 0);
21385 newsize
= relax_adr (fragp
, sec
, stretch
);
21391 newsize
= relax_immediate (fragp
, 8, 0);
21394 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21397 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21399 case T_MNEM_add_sp
:
21400 case T_MNEM_add_pc
:
21401 newsize
= relax_immediate (fragp
, 8, 2);
21403 case T_MNEM_inc_sp
:
21404 case T_MNEM_dec_sp
:
21405 newsize
= relax_immediate (fragp
, 7, 2);
21411 newsize
= relax_addsub (fragp
, sec
);
21417 fragp
->fr_var
= newsize
;
21418 /* Freeze wide instructions that are at or before the same location as
21419 in the previous pass. This avoids infinite loops.
21420 Don't freeze them unconditionally because targets may be artificially
21421 misaligned by the expansion of preceding frags. */
21422 if (stretch
<= 0 && newsize
> 2)
21424 md_convert_frag (sec
->owner
, sec
, fragp
);
21428 return newsize
- oldsize
;
21431 /* Round up a section size to the appropriate boundary. */
21434 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21437 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21438 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21440 /* For a.out, force the section size to be aligned. If we don't do
21441 this, BFD will align it for us, but it will not write out the
21442 final bytes of the section. This may be a bug in BFD, but it is
21443 easier to fix it here since that is how the other a.out targets
21447 align
= bfd_get_section_alignment (stdoutput
, segment
);
21448 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21455 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21456 of an rs_align_code fragment. */
21459 arm_handle_align (fragS
* fragP
)
21461 static char const arm_noop
[2][2][4] =
21464 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21465 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21468 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21469 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21472 static char const thumb_noop
[2][2][2] =
21475 {0xc0, 0x46}, /* LE */
21476 {0x46, 0xc0}, /* BE */
21479 {0x00, 0xbf}, /* LE */
21480 {0xbf, 0x00} /* BE */
21483 static char const wide_thumb_noop
[2][4] =
21484 { /* Wide Thumb-2 */
21485 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21486 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21489 unsigned bytes
, fix
, noop_size
;
21492 const char *narrow_noop
= NULL
;
21497 if (fragP
->fr_type
!= rs_align_code
)
21500 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21501 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21504 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21505 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21507 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21509 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21511 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21512 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21514 narrow_noop
= thumb_noop
[1][target_big_endian
];
21515 noop
= wide_thumb_noop
[target_big_endian
];
21518 noop
= thumb_noop
[0][target_big_endian
];
21526 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21527 ? selected_cpu
: arm_arch_none
,
21529 [target_big_endian
];
21536 fragP
->fr_var
= noop_size
;
21538 if (bytes
& (noop_size
- 1))
21540 fix
= bytes
& (noop_size
- 1);
21542 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21544 memset (p
, 0, fix
);
21551 if (bytes
& noop_size
)
21553 /* Insert a narrow noop. */
21554 memcpy (p
, narrow_noop
, noop_size
);
21556 bytes
-= noop_size
;
21560 /* Use wide noops for the remainder */
21564 while (bytes
>= noop_size
)
21566 memcpy (p
, noop
, noop_size
);
21568 bytes
-= noop_size
;
21572 fragP
->fr_fix
+= fix
;
21575 /* Called from md_do_align. Used to create an alignment
21576 frag in a code section. */
21579 arm_frag_align_code (int n
, int max
)
21583 /* We assume that there will never be a requirement
21584 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21585 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21590 _("alignments greater than %d bytes not supported in .text sections."),
21591 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21592 as_fatal ("%s", err_msg
);
21595 p
= frag_var (rs_align_code
,
21596 MAX_MEM_FOR_RS_ALIGN_CODE
,
21598 (relax_substateT
) max
,
21605 /* Perform target specific initialisation of a frag.
21606 Note - despite the name this initialisation is not done when the frag
21607 is created, but only when its type is assigned. A frag can be created
21608 and used a long time before its type is set, so beware of assuming that
21609 this initialisationis performed first. */
21613 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21615 /* Record whether this frag is in an ARM or a THUMB area. */
21616 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21619 #else /* OBJ_ELF is defined. */
21621 arm_init_frag (fragS
* fragP
, int max_chars
)
21623 int frag_thumb_mode
;
21625 /* If the current ARM vs THUMB mode has not already
21626 been recorded into this frag then do so now. */
21627 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21628 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21630 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21632 /* Record a mapping symbol for alignment frags. We will delete this
21633 later if the alignment ends up empty. */
21634 switch (fragP
->fr_type
)
21637 case rs_align_test
:
21639 mapping_state_2 (MAP_DATA
, max_chars
);
21641 case rs_align_code
:
21642 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21649 /* When we change sections we need to issue a new mapping symbol. */
21652 arm_elf_change_section (void)
21654 /* Link an unlinked unwind index table section to the .text section. */
21655 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21656 && elf_linked_to_section (now_seg
) == NULL
)
21657 elf_linked_to_section (now_seg
) = text_section
;
21661 arm_elf_section_type (const char * str
, size_t len
)
21663 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21664 return SHT_ARM_EXIDX
;
21669 /* Code to deal with unwinding tables. */
21671 static void add_unwind_adjustsp (offsetT
);
21673 /* Generate any deferred unwind frame offset. */
21676 flush_pending_unwind (void)
21680 offset
= unwind
.pending_offset
;
21681 unwind
.pending_offset
= 0;
21683 add_unwind_adjustsp (offset
);
21686 /* Add an opcode to this list for this function. Two-byte opcodes should
21687 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21691 add_unwind_opcode (valueT op
, int length
)
21693 /* Add any deferred stack adjustment. */
21694 if (unwind
.pending_offset
)
21695 flush_pending_unwind ();
21697 unwind
.sp_restored
= 0;
21699 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21701 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21702 if (unwind
.opcodes
)
21703 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
21704 unwind
.opcode_alloc
);
21706 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
21711 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21713 unwind
.opcode_count
++;
21717 /* Add unwind opcodes to adjust the stack pointer. */
21720 add_unwind_adjustsp (offsetT offset
)
21724 if (offset
> 0x200)
21726 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21731 /* Long form: 0xb2, uleb128. */
21732 /* This might not fit in a word so add the individual bytes,
21733 remembering the list is built in reverse order. */
21734 o
= (valueT
) ((offset
- 0x204) >> 2);
21736 add_unwind_opcode (0, 1);
21738 /* Calculate the uleb128 encoding of the offset. */
21742 bytes
[n
] = o
& 0x7f;
21748 /* Add the insn. */
21750 add_unwind_opcode (bytes
[n
- 1], 1);
21751 add_unwind_opcode (0xb2, 1);
21753 else if (offset
> 0x100)
21755 /* Two short opcodes. */
21756 add_unwind_opcode (0x3f, 1);
21757 op
= (offset
- 0x104) >> 2;
21758 add_unwind_opcode (op
, 1);
21760 else if (offset
> 0)
21762 /* Short opcode. */
21763 op
= (offset
- 4) >> 2;
21764 add_unwind_opcode (op
, 1);
21766 else if (offset
< 0)
21769 while (offset
> 0x100)
21771 add_unwind_opcode (0x7f, 1);
21774 op
= ((offset
- 4) >> 2) | 0x40;
21775 add_unwind_opcode (op
, 1);
21779 /* Finish the list of unwind opcodes for this function. */
21781 finish_unwind_opcodes (void)
21785 if (unwind
.fp_used
)
21787 /* Adjust sp as necessary. */
21788 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
21789 flush_pending_unwind ();
21791 /* After restoring sp from the frame pointer. */
21792 op
= 0x90 | unwind
.fp_reg
;
21793 add_unwind_opcode (op
, 1);
21796 flush_pending_unwind ();
21800 /* Start an exception table entry. If idx is nonzero this is an index table
21804 start_unwind_section (const segT text_seg
, int idx
)
21806 const char * text_name
;
21807 const char * prefix
;
21808 const char * prefix_once
;
21809 const char * group_name
;
21813 size_t sec_name_len
;
21820 prefix
= ELF_STRING_ARM_unwind
;
21821 prefix_once
= ELF_STRING_ARM_unwind_once
;
21822 type
= SHT_ARM_EXIDX
;
21826 prefix
= ELF_STRING_ARM_unwind_info
;
21827 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
21828 type
= SHT_PROGBITS
;
21831 text_name
= segment_name (text_seg
);
21832 if (streq (text_name
, ".text"))
21835 if (strncmp (text_name
, ".gnu.linkonce.t.",
21836 strlen (".gnu.linkonce.t.")) == 0)
21838 prefix
= prefix_once
;
21839 text_name
+= strlen (".gnu.linkonce.t.");
21842 prefix_len
= strlen (prefix
);
21843 text_len
= strlen (text_name
);
21844 sec_name_len
= prefix_len
+ text_len
;
21845 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
21846 memcpy (sec_name
, prefix
, prefix_len
);
21847 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
21848 sec_name
[prefix_len
+ text_len
] = '\0';
21854 /* Handle COMDAT group. */
21855 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
21857 group_name
= elf_group_name (text_seg
);
21858 if (group_name
== NULL
)
21860 as_bad (_("Group section `%s' has no group signature"),
21861 segment_name (text_seg
));
21862 ignore_rest_of_line ();
21865 flags
|= SHF_GROUP
;
21869 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
21871 /* Set the section link for index tables. */
21873 elf_linked_to_section (now_seg
) = text_seg
;
21877 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21878 personality routine data. Returns zero, or the index table value for
21879 an inline entry. */
21882 create_unwind_entry (int have_data
)
21887 /* The current word of data. */
21889 /* The number of bytes left in this word. */
21892 finish_unwind_opcodes ();
21894 /* Remember the current text section. */
21895 unwind
.saved_seg
= now_seg
;
21896 unwind
.saved_subseg
= now_subseg
;
21898 start_unwind_section (now_seg
, 0);
21900 if (unwind
.personality_routine
== NULL
)
21902 if (unwind
.personality_index
== -2)
21905 as_bad (_("handlerdata in cantunwind frame"));
21906 return 1; /* EXIDX_CANTUNWIND. */
21909 /* Use a default personality routine if none is specified. */
21910 if (unwind
.personality_index
== -1)
21912 if (unwind
.opcode_count
> 3)
21913 unwind
.personality_index
= 1;
21915 unwind
.personality_index
= 0;
21918 /* Space for the personality routine entry. */
21919 if (unwind
.personality_index
== 0)
21921 if (unwind
.opcode_count
> 3)
21922 as_bad (_("too many unwind opcodes for personality routine 0"));
21926 /* All the data is inline in the index table. */
21929 while (unwind
.opcode_count
> 0)
21931 unwind
.opcode_count
--;
21932 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21936 /* Pad with "finish" opcodes. */
21938 data
= (data
<< 8) | 0xb0;
21945 /* We get two opcodes "free" in the first word. */
21946 size
= unwind
.opcode_count
- 2;
21950 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
21951 if (unwind
.personality_index
!= -1)
21953 as_bad (_("attempt to recreate an unwind entry"));
21957 /* An extra byte is required for the opcode count. */
21958 size
= unwind
.opcode_count
+ 1;
21961 size
= (size
+ 3) >> 2;
21963 as_bad (_("too many unwind opcodes"));
21965 frag_align (2, 0, 0);
21966 record_alignment (now_seg
, 2);
21967 unwind
.table_entry
= expr_build_dot ();
21969 /* Allocate the table entry. */
21970 ptr
= frag_more ((size
<< 2) + 4);
21971 /* PR 13449: Zero the table entries in case some of them are not used. */
21972 memset (ptr
, 0, (size
<< 2) + 4);
21973 where
= frag_now_fix () - ((size
<< 2) + 4);
21975 switch (unwind
.personality_index
)
21978 /* ??? Should this be a PLT generating relocation? */
21979 /* Custom personality routine. */
21980 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
21981 BFD_RELOC_ARM_PREL31
);
21986 /* Set the first byte to the number of additional words. */
21987 data
= size
> 0 ? size
- 1 : 0;
21991 /* ABI defined personality routines. */
21993 /* Three opcodes bytes are packed into the first word. */
22000 /* The size and first two opcode bytes go in the first word. */
22001 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22006 /* Should never happen. */
22010 /* Pack the opcodes into words (MSB first), reversing the list at the same
22012 while (unwind
.opcode_count
> 0)
22016 md_number_to_chars (ptr
, data
, 4);
22021 unwind
.opcode_count
--;
22023 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22026 /* Finish off the last word. */
22029 /* Pad with "finish" opcodes. */
22031 data
= (data
<< 8) | 0xb0;
22033 md_number_to_chars (ptr
, data
, 4);
22038 /* Add an empty descriptor if there is no user-specified data. */
22039 ptr
= frag_more (4);
22040 md_number_to_chars (ptr
, 0, 4);
22047 /* Initialize the DWARF-2 unwind information for this procedure. */
22050 tc_arm_frame_initial_instructions (void)
22052 cfi_add_CFA_def_cfa (REG_SP
, 0);
22054 #endif /* OBJ_ELF */
22056 /* Convert REGNAME to a DWARF-2 register number. */
22059 tc_arm_regname_to_dw2regnum (char *regname
)
22061 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22065 /* PR 16694: Allow VFP registers as well. */
22066 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22070 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22079 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22083 exp
.X_op
= O_secrel
;
22084 exp
.X_add_symbol
= symbol
;
22085 exp
.X_add_number
= 0;
22086 emit_expr (&exp
, size
);
22090 /* MD interface: Symbol and relocation handling. */
22092 /* Return the address within the segment that a PC-relative fixup is
22093 relative to. For ARM, PC-relative fixups applied to instructions
22094 are generally relative to the location of the fixup plus 8 bytes.
22095 Thumb branches are offset by 4, and Thumb loads relative to PC
22096 require special handling. */
22099 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22101 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22103 /* If this is pc-relative and we are going to emit a relocation
22104 then we just want to put out any pipeline compensation that the linker
22105 will need. Otherwise we want to use the calculated base.
22106 For WinCE we skip the bias for externals as well, since this
22107 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22109 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22110 || (arm_force_relocation (fixP
)
22112 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22118 switch (fixP
->fx_r_type
)
22120 /* PC relative addressing on the Thumb is slightly odd as the
22121 bottom two bits of the PC are forced to zero for the
22122 calculation. This happens *after* application of the
22123 pipeline offset. However, Thumb adrl already adjusts for
22124 this, so we need not do it again. */
22125 case BFD_RELOC_ARM_THUMB_ADD
:
22128 case BFD_RELOC_ARM_THUMB_OFFSET
:
22129 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22130 case BFD_RELOC_ARM_T32_ADD_PC12
:
22131 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22132 return (base
+ 4) & ~3;
22134 /* Thumb branches are simply offset by +4. */
22135 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22136 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22137 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22138 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22139 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22142 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22144 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22145 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22146 && ARM_IS_FUNC (fixP
->fx_addsy
)
22147 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22148 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22151 /* BLX is like branches above, but forces the low two bits of PC to
22153 case BFD_RELOC_THUMB_PCREL_BLX
:
22155 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22156 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22157 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22158 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22159 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22160 return (base
+ 4) & ~3;
22162 /* ARM mode branches are offset by +8. However, the Windows CE
22163 loader expects the relocation not to take this into account. */
22164 case BFD_RELOC_ARM_PCREL_BLX
:
22166 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22167 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22168 && ARM_IS_FUNC (fixP
->fx_addsy
)
22169 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22170 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22173 case BFD_RELOC_ARM_PCREL_CALL
:
22175 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22176 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22177 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22178 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22179 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22182 case BFD_RELOC_ARM_PCREL_BRANCH
:
22183 case BFD_RELOC_ARM_PCREL_JUMP
:
22184 case BFD_RELOC_ARM_PLT32
:
22186 /* When handling fixups immediately, because we have already
22187 discovered the value of a symbol, or the address of the frag involved
22188 we must account for the offset by +8, as the OS loader will never see the reloc.
22189 see fixup_segment() in write.c
22190 The S_IS_EXTERNAL test handles the case of global symbols.
22191 Those need the calculated base, not just the pipe compensation the linker will need. */
22193 && fixP
->fx_addsy
!= NULL
22194 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22195 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22203 /* ARM mode loads relative to PC are also offset by +8. Unlike
22204 branches, the Windows CE loader *does* expect the relocation
22205 to take this into account. */
22206 case BFD_RELOC_ARM_OFFSET_IMM
:
22207 case BFD_RELOC_ARM_OFFSET_IMM8
:
22208 case BFD_RELOC_ARM_HWLITERAL
:
22209 case BFD_RELOC_ARM_LITERAL
:
22210 case BFD_RELOC_ARM_CP_OFF_IMM
:
22214 /* Other PC-relative relocations are un-offset. */
22220 static bfd_boolean flag_warn_syms
= TRUE
;
22223 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22225 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22226 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22227 does mean that the resulting code might be very confusing to the reader.
22228 Also this warning can be triggered if the user omits an operand before
22229 an immediate address, eg:
22233 GAS treats this as an assignment of the value of the symbol foo to a
22234 symbol LDR, and so (without this code) it will not issue any kind of
22235 warning or error message.
22237 Note - ARM instructions are case-insensitive but the strings in the hash
22238 table are all stored in lower case, so we must first ensure that name is
22240 if (flag_warn_syms
&& arm_ops_hsh
)
22242 char * nbuf
= strdup (name
);
22245 for (p
= nbuf
; *p
; p
++)
22247 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22249 static struct hash_control
* already_warned
= NULL
;
22251 if (already_warned
== NULL
)
22252 already_warned
= hash_new ();
22253 /* Only warn about the symbol once. To keep the code
22254 simple we let hash_insert do the lookup for us. */
22255 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22256 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22265 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22266 Otherwise we have no need to default values of symbols. */
22269 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22272 if (name
[0] == '_' && name
[1] == 'G'
22273 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22277 if (symbol_find (name
))
22278 as_bad (_("GOT already in the symbol table"));
22280 GOT_symbol
= symbol_new (name
, undefined_section
,
22281 (valueT
) 0, & zero_address_frag
);
22291 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22292 computed as two separate immediate values, added together. We
22293 already know that this value cannot be computed by just one ARM
22296 static unsigned int
22297 validate_immediate_twopart (unsigned int val
,
22298 unsigned int * highpart
)
22303 for (i
= 0; i
< 32; i
+= 2)
22304 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22310 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22312 else if (a
& 0xff0000)
22314 if (a
& 0xff000000)
22316 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22320 gas_assert (a
& 0xff000000);
22321 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22324 return (a
& 0xff) | (i
<< 7);
22331 validate_offset_imm (unsigned int val
, int hwse
)
22333 if ((hwse
&& val
> 255) || val
> 4095)
22338 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22339 negative immediate constant by altering the instruction. A bit of
22344 by inverting the second operand, and
22347 by negating the second operand. */
22350 negate_data_op (unsigned long * instruction
,
22351 unsigned long value
)
22354 unsigned long negated
, inverted
;
22356 negated
= encode_arm_immediate (-value
);
22357 inverted
= encode_arm_immediate (~value
);
22359 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22362 /* First negates. */
22363 case OPCODE_SUB
: /* ADD <-> SUB */
22364 new_inst
= OPCODE_ADD
;
22369 new_inst
= OPCODE_SUB
;
22373 case OPCODE_CMP
: /* CMP <-> CMN */
22374 new_inst
= OPCODE_CMN
;
22379 new_inst
= OPCODE_CMP
;
22383 /* Now Inverted ops. */
22384 case OPCODE_MOV
: /* MOV <-> MVN */
22385 new_inst
= OPCODE_MVN
;
22390 new_inst
= OPCODE_MOV
;
22394 case OPCODE_AND
: /* AND <-> BIC */
22395 new_inst
= OPCODE_BIC
;
22400 new_inst
= OPCODE_AND
;
22404 case OPCODE_ADC
: /* ADC <-> SBC */
22405 new_inst
= OPCODE_SBC
;
22410 new_inst
= OPCODE_ADC
;
22414 /* We cannot do anything. */
22419 if (value
== (unsigned) FAIL
)
22422 *instruction
&= OPCODE_MASK
;
22423 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22427 /* Like negate_data_op, but for Thumb-2. */
22429 static unsigned int
22430 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22434 unsigned int negated
, inverted
;
22436 negated
= encode_thumb32_immediate (-value
);
22437 inverted
= encode_thumb32_immediate (~value
);
22439 rd
= (*instruction
>> 8) & 0xf;
22440 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22443 /* ADD <-> SUB. Includes CMP <-> CMN. */
22444 case T2_OPCODE_SUB
:
22445 new_inst
= T2_OPCODE_ADD
;
22449 case T2_OPCODE_ADD
:
22450 new_inst
= T2_OPCODE_SUB
;
22454 /* ORR <-> ORN. Includes MOV <-> MVN. */
22455 case T2_OPCODE_ORR
:
22456 new_inst
= T2_OPCODE_ORN
;
22460 case T2_OPCODE_ORN
:
22461 new_inst
= T2_OPCODE_ORR
;
22465 /* AND <-> BIC. TST has no inverted equivalent. */
22466 case T2_OPCODE_AND
:
22467 new_inst
= T2_OPCODE_BIC
;
22474 case T2_OPCODE_BIC
:
22475 new_inst
= T2_OPCODE_AND
;
22480 case T2_OPCODE_ADC
:
22481 new_inst
= T2_OPCODE_SBC
;
22485 case T2_OPCODE_SBC
:
22486 new_inst
= T2_OPCODE_ADC
;
22490 /* We cannot do anything. */
22495 if (value
== (unsigned int)FAIL
)
22498 *instruction
&= T2_OPCODE_MASK
;
22499 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22503 /* Read a 32-bit thumb instruction from buf. */
22504 static unsigned long
22505 get_thumb32_insn (char * buf
)
22507 unsigned long insn
;
22508 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22509 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22515 /* We usually want to set the low bit on the address of thumb function
22516 symbols. In particular .word foo - . should have the low bit set.
22517 Generic code tries to fold the difference of two symbols to
22518 a constant. Prevent this and force a relocation when the first symbols
22519 is a thumb function. */
22522 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22524 if (op
== O_subtract
22525 && l
->X_op
== O_symbol
22526 && r
->X_op
== O_symbol
22527 && THUMB_IS_FUNC (l
->X_add_symbol
))
22529 l
->X_op
= O_subtract
;
22530 l
->X_op_symbol
= r
->X_add_symbol
;
22531 l
->X_add_number
-= r
->X_add_number
;
22535 /* Process as normal. */
22539 /* Encode Thumb2 unconditional branches and calls. The encoding
22540 for the 2 are identical for the immediate values. */
22543 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22545 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22548 addressT S
, I1
, I2
, lo
, hi
;
22550 S
= (value
>> 24) & 0x01;
22551 I1
= (value
>> 23) & 0x01;
22552 I2
= (value
>> 22) & 0x01;
22553 hi
= (value
>> 12) & 0x3ff;
22554 lo
= (value
>> 1) & 0x7ff;
22555 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22556 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22557 newval
|= (S
<< 10) | hi
;
22558 newval2
&= ~T2I1I2MASK
;
22559 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22560 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22561 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22565 md_apply_fix (fixS
* fixP
,
22569 offsetT value
= * valP
;
22571 unsigned int newimm
;
22572 unsigned long temp
;
22574 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22576 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22578 /* Note whether this will delete the relocation. */
22580 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22583 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22584 consistency with the behaviour on 32-bit hosts. Remember value
22586 value
&= 0xffffffff;
22587 value
^= 0x80000000;
22588 value
-= 0x80000000;
22591 fixP
->fx_addnumber
= value
;
22593 /* Same treatment for fixP->fx_offset. */
22594 fixP
->fx_offset
&= 0xffffffff;
22595 fixP
->fx_offset
^= 0x80000000;
22596 fixP
->fx_offset
-= 0x80000000;
22598 switch (fixP
->fx_r_type
)
22600 case BFD_RELOC_NONE
:
22601 /* This will need to go in the object file. */
22605 case BFD_RELOC_ARM_IMMEDIATE
:
22606 /* We claim that this fixup has been processed here,
22607 even if in fact we generate an error because we do
22608 not have a reloc for it, so tc_gen_reloc will reject it. */
22611 if (fixP
->fx_addsy
)
22613 const char *msg
= 0;
22615 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22616 msg
= _("undefined symbol %s used as an immediate value");
22617 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22618 msg
= _("symbol %s is in a different section");
22619 else if (S_IS_WEAK (fixP
->fx_addsy
))
22620 msg
= _("symbol %s is weak and may be overridden later");
22624 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22625 msg
, S_GET_NAME (fixP
->fx_addsy
));
22630 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22632 /* If the offset is negative, we should use encoding A2 for ADR. */
22633 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22634 newimm
= negate_data_op (&temp
, value
);
22637 newimm
= encode_arm_immediate (value
);
22639 /* If the instruction will fail, see if we can fix things up by
22640 changing the opcode. */
22641 if (newimm
== (unsigned int) FAIL
)
22642 newimm
= negate_data_op (&temp
, value
);
22645 if (newimm
== (unsigned int) FAIL
)
22647 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22648 _("invalid constant (%lx) after fixup"),
22649 (unsigned long) value
);
22653 newimm
|= (temp
& 0xfffff000);
22654 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22657 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22659 unsigned int highpart
= 0;
22660 unsigned int newinsn
= 0xe1a00000; /* nop. */
22662 if (fixP
->fx_addsy
)
22664 const char *msg
= 0;
22666 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22667 msg
= _("undefined symbol %s used as an immediate value");
22668 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22669 msg
= _("symbol %s is in a different section");
22670 else if (S_IS_WEAK (fixP
->fx_addsy
))
22671 msg
= _("symbol %s is weak and may be overridden later");
22675 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22676 msg
, S_GET_NAME (fixP
->fx_addsy
));
22681 newimm
= encode_arm_immediate (value
);
22682 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22684 /* If the instruction will fail, see if we can fix things up by
22685 changing the opcode. */
22686 if (newimm
== (unsigned int) FAIL
22687 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22689 /* No ? OK - try using two ADD instructions to generate
22691 newimm
= validate_immediate_twopart (value
, & highpart
);
22693 /* Yes - then make sure that the second instruction is
22695 if (newimm
!= (unsigned int) FAIL
)
22697 /* Still No ? Try using a negated value. */
22698 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22699 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22700 /* Otherwise - give up. */
22703 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22704 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22709 /* Replace the first operand in the 2nd instruction (which
22710 is the PC) with the destination register. We have
22711 already added in the PC in the first instruction and we
22712 do not want to do it again. */
22713 newinsn
&= ~ 0xf0000;
22714 newinsn
|= ((newinsn
& 0x0f000) << 4);
22717 newimm
|= (temp
& 0xfffff000);
22718 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22720 highpart
|= (newinsn
& 0xfffff000);
22721 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22725 case BFD_RELOC_ARM_OFFSET_IMM
:
22726 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22729 case BFD_RELOC_ARM_LITERAL
:
22735 if (validate_offset_imm (value
, 0) == FAIL
)
22737 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22738 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22739 _("invalid literal constant: pool needs to be closer"));
22741 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22742 _("bad immediate value for offset (%ld)"),
22747 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22749 newval
&= 0xfffff000;
22752 newval
&= 0xff7ff000;
22753 newval
|= value
| (sign
? INDEX_UP
: 0);
22755 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22758 case BFD_RELOC_ARM_OFFSET_IMM8
:
22759 case BFD_RELOC_ARM_HWLITERAL
:
22765 if (validate_offset_imm (value
, 1) == FAIL
)
22767 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
22768 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22769 _("invalid literal constant: pool needs to be closer"));
22771 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22772 _("bad immediate value for 8-bit offset (%ld)"),
22777 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22779 newval
&= 0xfffff0f0;
22782 newval
&= 0xff7ff0f0;
22783 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
22785 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22788 case BFD_RELOC_ARM_T32_OFFSET_U8
:
22789 if (value
< 0 || value
> 1020 || value
% 4 != 0)
22790 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22791 _("bad immediate value for offset (%ld)"), (long) value
);
22794 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
22796 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
22799 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22800 /* This is a complicated relocation used for all varieties of Thumb32
22801 load/store instruction with immediate offset:
22803 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22804 *4, optional writeback(W)
22805 (doubleword load/store)
22807 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22808 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22809 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22810 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22811 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22813 Uppercase letters indicate bits that are already encoded at
22814 this point. Lowercase letters are our problem. For the
22815 second block of instructions, the secondary opcode nybble
22816 (bits 8..11) is present, and bit 23 is zero, even if this is
22817 a PC-relative operation. */
22818 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22820 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
22822 if ((newval
& 0xf0000000) == 0xe0000000)
22824 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22826 newval
|= (1 << 23);
22829 if (value
% 4 != 0)
22831 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22832 _("offset not a multiple of 4"));
22838 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22839 _("offset out of range"));
22844 else if ((newval
& 0x000f0000) == 0x000f0000)
22846 /* PC-relative, 12-bit offset. */
22848 newval
|= (1 << 23);
22853 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22854 _("offset out of range"));
22859 else if ((newval
& 0x00000100) == 0x00000100)
22861 /* Writeback: 8-bit, +/- offset. */
22863 newval
|= (1 << 9);
22868 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22869 _("offset out of range"));
22874 else if ((newval
& 0x00000f00) == 0x00000e00)
22876 /* T-instruction: positive 8-bit offset. */
22877 if (value
< 0 || value
> 0xff)
22879 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22880 _("offset out of range"));
22888 /* Positive 12-bit or negative 8-bit offset. */
22892 newval
|= (1 << 23);
22902 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22903 _("offset out of range"));
22910 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
22911 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
22914 case BFD_RELOC_ARM_SHIFT_IMM
:
22915 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22916 if (((unsigned long) value
) > 32
22918 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
22920 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22921 _("shift expression is too large"));
22926 /* Shifts of zero must be done as lsl. */
22928 else if (value
== 32)
22930 newval
&= 0xfffff07f;
22931 newval
|= (value
& 0x1f) << 7;
22932 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22935 case BFD_RELOC_ARM_T32_IMMEDIATE
:
22936 case BFD_RELOC_ARM_T32_ADD_IMM
:
22937 case BFD_RELOC_ARM_T32_IMM12
:
22938 case BFD_RELOC_ARM_T32_ADD_PC12
:
22939 /* We claim that this fixup has been processed here,
22940 even if in fact we generate an error because we do
22941 not have a reloc for it, so tc_gen_reloc will reject it. */
22945 && ! S_IS_DEFINED (fixP
->fx_addsy
))
22947 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22948 _("undefined symbol %s used as an immediate value"),
22949 S_GET_NAME (fixP
->fx_addsy
));
22953 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22955 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
22958 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
22959 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22961 newimm
= encode_thumb32_immediate (value
);
22962 if (newimm
== (unsigned int) FAIL
)
22963 newimm
= thumb32_negate_data_op (&newval
, value
);
22965 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
22966 && newimm
== (unsigned int) FAIL
)
22968 /* Turn add/sum into addw/subw. */
22969 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22970 newval
= (newval
& 0xfeffffff) | 0x02000000;
22971 /* No flat 12-bit imm encoding for addsw/subsw. */
22972 if ((newval
& 0x00100000) == 0)
22974 /* 12 bit immediate for addw/subw. */
22978 newval
^= 0x00a00000;
22981 newimm
= (unsigned int) FAIL
;
22987 if (newimm
== (unsigned int)FAIL
)
22989 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22990 _("invalid constant (%lx) after fixup"),
22991 (unsigned long) value
);
22995 newval
|= (newimm
& 0x800) << 15;
22996 newval
|= (newimm
& 0x700) << 4;
22997 newval
|= (newimm
& 0x0ff);
22999 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23000 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23003 case BFD_RELOC_ARM_SMC
:
23004 if (((unsigned long) value
) > 0xffff)
23005 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23006 _("invalid smc expression"));
23007 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23008 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23009 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23012 case BFD_RELOC_ARM_HVC
:
23013 if (((unsigned long) value
) > 0xffff)
23014 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23015 _("invalid hvc expression"));
23016 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23017 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23018 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23021 case BFD_RELOC_ARM_SWI
:
23022 if (fixP
->tc_fix_data
!= 0)
23024 if (((unsigned long) value
) > 0xff)
23025 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23026 _("invalid swi expression"));
23027 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23029 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23033 if (((unsigned long) value
) > 0x00ffffff)
23034 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23035 _("invalid swi expression"));
23036 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23038 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23042 case BFD_RELOC_ARM_MULTI
:
23043 if (((unsigned long) value
) > 0xffff)
23044 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23045 _("invalid expression in load/store multiple"));
23046 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23047 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23051 case BFD_RELOC_ARM_PCREL_CALL
:
23053 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23055 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23056 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23057 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23058 /* Flip the bl to blx. This is a simple flip
23059 bit here because we generate PCREL_CALL for
23060 unconditional bls. */
23062 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23063 newval
= newval
| 0x10000000;
23064 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23070 goto arm_branch_common
;
23072 case BFD_RELOC_ARM_PCREL_JUMP
:
23073 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23075 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23076 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23077 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23079 /* This would map to a bl<cond>, b<cond>,
23080 b<always> to a Thumb function. We
23081 need to force a relocation for this particular
23083 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23087 case BFD_RELOC_ARM_PLT32
:
23089 case BFD_RELOC_ARM_PCREL_BRANCH
:
23091 goto arm_branch_common
;
23093 case BFD_RELOC_ARM_PCREL_BLX
:
23096 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23098 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23099 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23100 && ARM_IS_FUNC (fixP
->fx_addsy
))
23102 /* Flip the blx to a bl and warn. */
23103 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23104 newval
= 0xeb000000;
23105 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23106 _("blx to '%s' an ARM ISA state function changed to bl"),
23108 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23114 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23115 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23119 /* We are going to store value (shifted right by two) in the
23120 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23121 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23122 also be be clear. */
23124 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23125 _("misaligned branch destination"));
23126 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23127 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23128 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23130 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23132 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23133 newval
|= (value
>> 2) & 0x00ffffff;
23134 /* Set the H bit on BLX instructions. */
23138 newval
|= 0x01000000;
23140 newval
&= ~0x01000000;
23142 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23146 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23147 /* CBZ can only branch forward. */
23149 /* Attempts to use CBZ to branch to the next instruction
23150 (which, strictly speaking, are prohibited) will be turned into
23153 FIXME: It may be better to remove the instruction completely and
23154 perform relaxation. */
23157 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23158 newval
= 0xbf00; /* NOP encoding T1 */
23159 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23164 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23166 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23168 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23169 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23170 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23175 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23176 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23177 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23179 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23181 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23182 newval
|= (value
& 0x1ff) >> 1;
23183 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23187 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23188 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23189 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23191 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23193 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23194 newval
|= (value
& 0xfff) >> 1;
23195 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23199 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23201 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23202 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23203 && ARM_IS_FUNC (fixP
->fx_addsy
)
23204 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23206 /* Force a relocation for a branch 20 bits wide. */
23209 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23210 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23211 _("conditional branch out of range"));
23213 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23216 addressT S
, J1
, J2
, lo
, hi
;
23218 S
= (value
& 0x00100000) >> 20;
23219 J2
= (value
& 0x00080000) >> 19;
23220 J1
= (value
& 0x00040000) >> 18;
23221 hi
= (value
& 0x0003f000) >> 12;
23222 lo
= (value
& 0x00000ffe) >> 1;
23224 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23225 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23226 newval
|= (S
<< 10) | hi
;
23227 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23228 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23229 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23233 case BFD_RELOC_THUMB_PCREL_BLX
:
23234 /* If there is a blx from a thumb state function to
23235 another thumb function flip this to a bl and warn
23239 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23240 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23241 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23243 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23244 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23245 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23247 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23248 newval
= newval
| 0x1000;
23249 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23250 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23255 goto thumb_bl_common
;
23257 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23258 /* A bl from Thumb state ISA to an internal ARM state function
23259 is converted to a blx. */
23261 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23262 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23263 && ARM_IS_FUNC (fixP
->fx_addsy
)
23264 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23266 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23267 newval
= newval
& ~0x1000;
23268 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23269 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23275 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23276 /* For a BLX instruction, make sure that the relocation is rounded up
23277 to a word boundary. This follows the semantics of the instruction
23278 which specifies that bit 1 of the target address will come from bit
23279 1 of the base address. */
23280 value
= (value
+ 3) & ~ 3;
23283 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23284 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23285 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23288 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23290 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23291 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23292 else if ((value
& ~0x1ffffff)
23293 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23294 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23295 _("Thumb2 branch out of range"));
23298 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23299 encode_thumb2_b_bl_offset (buf
, value
);
23303 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23304 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23305 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23307 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23308 encode_thumb2_b_bl_offset (buf
, value
);
23313 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23318 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23319 md_number_to_chars (buf
, value
, 2);
23323 case BFD_RELOC_ARM_TLS_CALL
:
23324 case BFD_RELOC_ARM_THM_TLS_CALL
:
23325 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23326 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23327 case BFD_RELOC_ARM_TLS_GOTDESC
:
23328 case BFD_RELOC_ARM_TLS_GD32
:
23329 case BFD_RELOC_ARM_TLS_LE32
:
23330 case BFD_RELOC_ARM_TLS_IE32
:
23331 case BFD_RELOC_ARM_TLS_LDM32
:
23332 case BFD_RELOC_ARM_TLS_LDO32
:
23333 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23336 case BFD_RELOC_ARM_GOT32
:
23337 case BFD_RELOC_ARM_GOTOFF
:
23340 case BFD_RELOC_ARM_GOT_PREL
:
23341 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23342 md_number_to_chars (buf
, value
, 4);
23345 case BFD_RELOC_ARM_TARGET2
:
23346 /* TARGET2 is not partial-inplace, so we need to write the
23347 addend here for REL targets, because it won't be written out
23348 during reloc processing later. */
23349 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23350 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
23354 case BFD_RELOC_RVA
:
23356 case BFD_RELOC_ARM_TARGET1
:
23357 case BFD_RELOC_ARM_ROSEGREL32
:
23358 case BFD_RELOC_ARM_SBREL32
:
23359 case BFD_RELOC_32_PCREL
:
23361 case BFD_RELOC_32_SECREL
:
23363 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23365 /* For WinCE we only do this for pcrel fixups. */
23366 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
23368 md_number_to_chars (buf
, value
, 4);
23372 case BFD_RELOC_ARM_PREL31
:
23373 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23375 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
23376 if ((value
^ (value
>> 1)) & 0x40000000)
23378 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23379 _("rel31 relocation overflow"));
23381 newval
|= value
& 0x7fffffff;
23382 md_number_to_chars (buf
, newval
, 4);
23387 case BFD_RELOC_ARM_CP_OFF_IMM
:
23388 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23389 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
23390 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23392 newval
= get_thumb32_insn (buf
);
23393 if ((newval
& 0x0f200f00) == 0x0d000900)
23395 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23396 has permitted values that are multiples of 2, in the range 0
23398 if (value
< -510 || value
> 510 || (value
& 1))
23399 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23400 _("co-processor offset out of range"));
23402 else if (value
< -1023 || value
> 1023 || (value
& 3))
23403 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23404 _("co-processor offset out of range"));
23409 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23410 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23411 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23413 newval
= get_thumb32_insn (buf
);
23415 newval
&= 0xffffff00;
23418 newval
&= 0xff7fff00;
23419 if ((newval
& 0x0f200f00) == 0x0d000900)
23421 /* This is a fp16 vstr/vldr.
23423 It requires the immediate offset in the instruction is shifted
23424 left by 1 to be a half-word offset.
23426 Here, left shift by 1 first, and later right shift by 2
23427 should get the right offset. */
23430 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23432 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23433 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23434 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23436 put_thumb32_insn (buf
, newval
);
23439 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23440 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23441 if (value
< -255 || value
> 255)
23442 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23443 _("co-processor offset out of range"));
23445 goto cp_off_common
;
23447 case BFD_RELOC_ARM_THUMB_OFFSET
:
23448 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23449 /* Exactly what ranges, and where the offset is inserted depends
23450 on the type of instruction, we can establish this from the
23452 switch (newval
>> 12)
23454 case 4: /* PC load. */
23455 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23456 forced to zero for these loads; md_pcrel_from has already
23457 compensated for this. */
23459 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23460 _("invalid offset, target not word aligned (0x%08lX)"),
23461 (((unsigned long) fixP
->fx_frag
->fr_address
23462 + (unsigned long) fixP
->fx_where
) & ~3)
23463 + (unsigned long) value
);
23465 if (value
& ~0x3fc)
23466 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23467 _("invalid offset, value too big (0x%08lX)"),
23470 newval
|= value
>> 2;
23473 case 9: /* SP load/store. */
23474 if (value
& ~0x3fc)
23475 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23476 _("invalid offset, value too big (0x%08lX)"),
23478 newval
|= value
>> 2;
23481 case 6: /* Word load/store. */
23483 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23484 _("invalid offset, value too big (0x%08lX)"),
23486 newval
|= value
<< 4; /* 6 - 2. */
23489 case 7: /* Byte load/store. */
23491 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23492 _("invalid offset, value too big (0x%08lX)"),
23494 newval
|= value
<< 6;
23497 case 8: /* Halfword load/store. */
23499 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23500 _("invalid offset, value too big (0x%08lX)"),
23502 newval
|= value
<< 5; /* 6 - 1. */
23506 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23507 "Unable to process relocation for thumb opcode: %lx",
23508 (unsigned long) newval
);
23511 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23514 case BFD_RELOC_ARM_THUMB_ADD
:
23515 /* This is a complicated relocation, since we use it for all of
23516 the following immediate relocations:
23520 9bit ADD/SUB SP word-aligned
23521 10bit ADD PC/SP word-aligned
23523 The type of instruction being processed is encoded in the
23530 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23532 int rd
= (newval
>> 4) & 0xf;
23533 int rs
= newval
& 0xf;
23534 int subtract
= !!(newval
& 0x8000);
23536 /* Check for HI regs, only very restricted cases allowed:
23537 Adjusting SP, and using PC or SP to get an address. */
23538 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23539 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23540 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23541 _("invalid Hi register with immediate"));
23543 /* If value is negative, choose the opposite instruction. */
23547 subtract
= !subtract
;
23549 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23550 _("immediate value out of range"));
23555 if (value
& ~0x1fc)
23556 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23557 _("invalid immediate for stack address calculation"));
23558 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23559 newval
|= value
>> 2;
23561 else if (rs
== REG_PC
|| rs
== REG_SP
)
23563 /* PR gas/18541. If the addition is for a defined symbol
23564 within range of an ADR instruction then accept it. */
23567 && fixP
->fx_addsy
!= NULL
)
23571 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23572 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23573 || S_IS_WEAK (fixP
->fx_addsy
))
23575 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23576 _("address calculation needs a strongly defined nearby symbol"));
23580 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23582 /* Round up to the next 4-byte boundary. */
23587 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23591 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23592 _("symbol too far away"));
23602 if (subtract
|| value
& ~0x3fc)
23603 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23604 _("invalid immediate for address calculation (value = 0x%08lX)"),
23605 (unsigned long) (subtract
? - value
: value
));
23606 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23608 newval
|= value
>> 2;
23613 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23614 _("immediate value out of range"));
23615 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23616 newval
|= (rd
<< 8) | value
;
23621 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23622 _("immediate value out of range"));
23623 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23624 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23627 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23630 case BFD_RELOC_ARM_THUMB_IMM
:
23631 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23632 if (value
< 0 || value
> 255)
23633 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23634 _("invalid immediate: %ld is out of range"),
23637 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23640 case BFD_RELOC_ARM_THUMB_SHIFT
:
23641 /* 5bit shift value (0..32). LSL cannot take 32. */
23642 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23643 temp
= newval
& 0xf800;
23644 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23645 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23646 _("invalid shift value: %ld"), (long) value
);
23647 /* Shifts of zero must be encoded as LSL. */
23649 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23650 /* Shifts of 32 are encoded as zero. */
23651 else if (value
== 32)
23653 newval
|= value
<< 6;
23654 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23657 case BFD_RELOC_VTABLE_INHERIT
:
23658 case BFD_RELOC_VTABLE_ENTRY
:
23662 case BFD_RELOC_ARM_MOVW
:
23663 case BFD_RELOC_ARM_MOVT
:
23664 case BFD_RELOC_ARM_THUMB_MOVW
:
23665 case BFD_RELOC_ARM_THUMB_MOVT
:
23666 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23668 /* REL format relocations are limited to a 16-bit addend. */
23669 if (!fixP
->fx_done
)
23671 if (value
< -0x8000 || value
> 0x7fff)
23672 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23673 _("offset out of range"));
23675 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23676 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23681 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23682 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23684 newval
= get_thumb32_insn (buf
);
23685 newval
&= 0xfbf08f00;
23686 newval
|= (value
& 0xf000) << 4;
23687 newval
|= (value
& 0x0800) << 15;
23688 newval
|= (value
& 0x0700) << 4;
23689 newval
|= (value
& 0x00ff);
23690 put_thumb32_insn (buf
, newval
);
23694 newval
= md_chars_to_number (buf
, 4);
23695 newval
&= 0xfff0f000;
23696 newval
|= value
& 0x0fff;
23697 newval
|= (value
& 0xf000) << 4;
23698 md_number_to_chars (buf
, newval
, 4);
23703 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
23704 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
23705 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
23706 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
23707 gas_assert (!fixP
->fx_done
);
23710 bfd_boolean is_mov
;
23711 bfd_vma encoded_addend
= value
;
23713 /* Check that addend can be encoded in instruction. */
23714 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
23715 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23716 _("the offset 0x%08lX is not representable"),
23717 (unsigned long) encoded_addend
);
23719 /* Extract the instruction. */
23720 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
23721 is_mov
= (insn
& 0xf800) == 0x2000;
23726 if (!seg
->use_rela_p
)
23727 insn
|= encoded_addend
;
23733 /* Extract the instruction. */
23734 /* Encoding is the following
23739 /* The following conditions must be true :
23744 rd
= (insn
>> 4) & 0xf;
23746 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
23747 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23748 _("Unable to process relocation for thumb opcode: %lx"),
23749 (unsigned long) insn
);
23751 /* Encode as ADD immediate8 thumb 1 code. */
23752 insn
= 0x3000 | (rd
<< 8);
23754 /* Place the encoded addend into the first 8 bits of the
23756 if (!seg
->use_rela_p
)
23757 insn
|= encoded_addend
;
23760 /* Update the instruction. */
23761 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
23765 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23766 case BFD_RELOC_ARM_ALU_PC_G0
:
23767 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23768 case BFD_RELOC_ARM_ALU_PC_G1
:
23769 case BFD_RELOC_ARM_ALU_PC_G2
:
23770 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23771 case BFD_RELOC_ARM_ALU_SB_G0
:
23772 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23773 case BFD_RELOC_ARM_ALU_SB_G1
:
23774 case BFD_RELOC_ARM_ALU_SB_G2
:
23775 gas_assert (!fixP
->fx_done
);
23776 if (!seg
->use_rela_p
)
23779 bfd_vma encoded_addend
;
23780 bfd_vma addend_abs
= abs (value
);
23782 /* Check that the absolute value of the addend can be
23783 expressed as an 8-bit constant plus a rotation. */
23784 encoded_addend
= encode_arm_immediate (addend_abs
);
23785 if (encoded_addend
== (unsigned int) FAIL
)
23786 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23787 _("the offset 0x%08lX is not representable"),
23788 (unsigned long) addend_abs
);
23790 /* Extract the instruction. */
23791 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23793 /* If the addend is positive, use an ADD instruction.
23794 Otherwise use a SUB. Take care not to destroy the S bit. */
23795 insn
&= 0xff1fffff;
23801 /* Place the encoded addend into the first 12 bits of the
23803 insn
&= 0xfffff000;
23804 insn
|= encoded_addend
;
23806 /* Update the instruction. */
23807 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23811 case BFD_RELOC_ARM_LDR_PC_G0
:
23812 case BFD_RELOC_ARM_LDR_PC_G1
:
23813 case BFD_RELOC_ARM_LDR_PC_G2
:
23814 case BFD_RELOC_ARM_LDR_SB_G0
:
23815 case BFD_RELOC_ARM_LDR_SB_G1
:
23816 case BFD_RELOC_ARM_LDR_SB_G2
:
23817 gas_assert (!fixP
->fx_done
);
23818 if (!seg
->use_rela_p
)
23821 bfd_vma addend_abs
= abs (value
);
23823 /* Check that the absolute value of the addend can be
23824 encoded in 12 bits. */
23825 if (addend_abs
>= 0x1000)
23826 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23827 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23828 (unsigned long) addend_abs
);
23830 /* Extract the instruction. */
23831 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23833 /* If the addend is negative, clear bit 23 of the instruction.
23834 Otherwise set it. */
23836 insn
&= ~(1 << 23);
23840 /* Place the absolute value of the addend into the first 12 bits
23841 of the instruction. */
23842 insn
&= 0xfffff000;
23843 insn
|= addend_abs
;
23845 /* Update the instruction. */
23846 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23850 case BFD_RELOC_ARM_LDRS_PC_G0
:
23851 case BFD_RELOC_ARM_LDRS_PC_G1
:
23852 case BFD_RELOC_ARM_LDRS_PC_G2
:
23853 case BFD_RELOC_ARM_LDRS_SB_G0
:
23854 case BFD_RELOC_ARM_LDRS_SB_G1
:
23855 case BFD_RELOC_ARM_LDRS_SB_G2
:
23856 gas_assert (!fixP
->fx_done
);
23857 if (!seg
->use_rela_p
)
23860 bfd_vma addend_abs
= abs (value
);
23862 /* Check that the absolute value of the addend can be
23863 encoded in 8 bits. */
23864 if (addend_abs
>= 0x100)
23865 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23866 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23867 (unsigned long) addend_abs
);
23869 /* Extract the instruction. */
23870 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23872 /* If the addend is negative, clear bit 23 of the instruction.
23873 Otherwise set it. */
23875 insn
&= ~(1 << 23);
23879 /* Place the first four bits of the absolute value of the addend
23880 into the first 4 bits of the instruction, and the remaining
23881 four into bits 8 .. 11. */
23882 insn
&= 0xfffff0f0;
23883 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
23885 /* Update the instruction. */
23886 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23890 case BFD_RELOC_ARM_LDC_PC_G0
:
23891 case BFD_RELOC_ARM_LDC_PC_G1
:
23892 case BFD_RELOC_ARM_LDC_PC_G2
:
23893 case BFD_RELOC_ARM_LDC_SB_G0
:
23894 case BFD_RELOC_ARM_LDC_SB_G1
:
23895 case BFD_RELOC_ARM_LDC_SB_G2
:
23896 gas_assert (!fixP
->fx_done
);
23897 if (!seg
->use_rela_p
)
23900 bfd_vma addend_abs
= abs (value
);
23902 /* Check that the absolute value of the addend is a multiple of
23903 four and, when divided by four, fits in 8 bits. */
23904 if (addend_abs
& 0x3)
23905 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23906 _("bad offset 0x%08lX (must be word-aligned)"),
23907 (unsigned long) addend_abs
);
23909 if ((addend_abs
>> 2) > 0xff)
23910 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23911 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
23912 (unsigned long) addend_abs
);
23914 /* Extract the instruction. */
23915 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23917 /* If the addend is negative, clear bit 23 of the instruction.
23918 Otherwise set it. */
23920 insn
&= ~(1 << 23);
23924 /* Place the addend (divided by four) into the first eight
23925 bits of the instruction. */
23926 insn
&= 0xfffffff0;
23927 insn
|= addend_abs
>> 2;
23929 /* Update the instruction. */
23930 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23934 case BFD_RELOC_ARM_V4BX
:
23935 /* This will need to go in the object file. */
23939 case BFD_RELOC_UNUSED
:
23941 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23942 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
23946 /* Translate internal representation of relocation info to BFD target
23950 tc_gen_reloc (asection
*section
, fixS
*fixp
)
23953 bfd_reloc_code_real_type code
;
23955 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
23957 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
23958 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
23959 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
23961 if (fixp
->fx_pcrel
)
23963 if (section
->use_rela_p
)
23964 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
23966 fixp
->fx_offset
= reloc
->address
;
23968 reloc
->addend
= fixp
->fx_offset
;
23970 switch (fixp
->fx_r_type
)
23973 if (fixp
->fx_pcrel
)
23975 code
= BFD_RELOC_8_PCREL
;
23980 if (fixp
->fx_pcrel
)
23982 code
= BFD_RELOC_16_PCREL
;
23987 if (fixp
->fx_pcrel
)
23989 code
= BFD_RELOC_32_PCREL
;
23993 case BFD_RELOC_ARM_MOVW
:
23994 if (fixp
->fx_pcrel
)
23996 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24000 case BFD_RELOC_ARM_MOVT
:
24001 if (fixp
->fx_pcrel
)
24003 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24007 case BFD_RELOC_ARM_THUMB_MOVW
:
24008 if (fixp
->fx_pcrel
)
24010 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24014 case BFD_RELOC_ARM_THUMB_MOVT
:
24015 if (fixp
->fx_pcrel
)
24017 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24021 case BFD_RELOC_NONE
:
24022 case BFD_RELOC_ARM_PCREL_BRANCH
:
24023 case BFD_RELOC_ARM_PCREL_BLX
:
24024 case BFD_RELOC_RVA
:
24025 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24026 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24027 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24028 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24029 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24030 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24031 case BFD_RELOC_VTABLE_ENTRY
:
24032 case BFD_RELOC_VTABLE_INHERIT
:
24034 case BFD_RELOC_32_SECREL
:
24036 code
= fixp
->fx_r_type
;
24039 case BFD_RELOC_THUMB_PCREL_BLX
:
24041 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24042 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24045 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24048 case BFD_RELOC_ARM_LITERAL
:
24049 case BFD_RELOC_ARM_HWLITERAL
:
24050 /* If this is called then the a literal has
24051 been referenced across a section boundary. */
24052 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24053 _("literal referenced across section boundary"));
24057 case BFD_RELOC_ARM_TLS_CALL
:
24058 case BFD_RELOC_ARM_THM_TLS_CALL
:
24059 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24060 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24061 case BFD_RELOC_ARM_GOT32
:
24062 case BFD_RELOC_ARM_GOTOFF
:
24063 case BFD_RELOC_ARM_GOT_PREL
:
24064 case BFD_RELOC_ARM_PLT32
:
24065 case BFD_RELOC_ARM_TARGET1
:
24066 case BFD_RELOC_ARM_ROSEGREL32
:
24067 case BFD_RELOC_ARM_SBREL32
:
24068 case BFD_RELOC_ARM_PREL31
:
24069 case BFD_RELOC_ARM_TARGET2
:
24070 case BFD_RELOC_ARM_TLS_LDO32
:
24071 case BFD_RELOC_ARM_PCREL_CALL
:
24072 case BFD_RELOC_ARM_PCREL_JUMP
:
24073 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24074 case BFD_RELOC_ARM_ALU_PC_G0
:
24075 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24076 case BFD_RELOC_ARM_ALU_PC_G1
:
24077 case BFD_RELOC_ARM_ALU_PC_G2
:
24078 case BFD_RELOC_ARM_LDR_PC_G0
:
24079 case BFD_RELOC_ARM_LDR_PC_G1
:
24080 case BFD_RELOC_ARM_LDR_PC_G2
:
24081 case BFD_RELOC_ARM_LDRS_PC_G0
:
24082 case BFD_RELOC_ARM_LDRS_PC_G1
:
24083 case BFD_RELOC_ARM_LDRS_PC_G2
:
24084 case BFD_RELOC_ARM_LDC_PC_G0
:
24085 case BFD_RELOC_ARM_LDC_PC_G1
:
24086 case BFD_RELOC_ARM_LDC_PC_G2
:
24087 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24088 case BFD_RELOC_ARM_ALU_SB_G0
:
24089 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24090 case BFD_RELOC_ARM_ALU_SB_G1
:
24091 case BFD_RELOC_ARM_ALU_SB_G2
:
24092 case BFD_RELOC_ARM_LDR_SB_G0
:
24093 case BFD_RELOC_ARM_LDR_SB_G1
:
24094 case BFD_RELOC_ARM_LDR_SB_G2
:
24095 case BFD_RELOC_ARM_LDRS_SB_G0
:
24096 case BFD_RELOC_ARM_LDRS_SB_G1
:
24097 case BFD_RELOC_ARM_LDRS_SB_G2
:
24098 case BFD_RELOC_ARM_LDC_SB_G0
:
24099 case BFD_RELOC_ARM_LDC_SB_G1
:
24100 case BFD_RELOC_ARM_LDC_SB_G2
:
24101 case BFD_RELOC_ARM_V4BX
:
24102 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24103 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24104 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24105 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24106 code
= fixp
->fx_r_type
;
24109 case BFD_RELOC_ARM_TLS_GOTDESC
:
24110 case BFD_RELOC_ARM_TLS_GD32
:
24111 case BFD_RELOC_ARM_TLS_LE32
:
24112 case BFD_RELOC_ARM_TLS_IE32
:
24113 case BFD_RELOC_ARM_TLS_LDM32
:
24114 /* BFD will include the symbol's address in the addend.
24115 But we don't want that, so subtract it out again here. */
24116 if (!S_IS_COMMON (fixp
->fx_addsy
))
24117 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24118 code
= fixp
->fx_r_type
;
24122 case BFD_RELOC_ARM_IMMEDIATE
:
24123 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24124 _("internal relocation (type: IMMEDIATE) not fixed up"));
24127 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24128 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24129 _("ADRL used for a symbol not defined in the same file"));
24132 case BFD_RELOC_ARM_OFFSET_IMM
:
24133 if (section
->use_rela_p
)
24135 code
= fixp
->fx_r_type
;
24139 if (fixp
->fx_addsy
!= NULL
24140 && !S_IS_DEFINED (fixp
->fx_addsy
)
24141 && S_IS_LOCAL (fixp
->fx_addsy
))
24143 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24144 _("undefined local label `%s'"),
24145 S_GET_NAME (fixp
->fx_addsy
));
24149 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24150 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24157 switch (fixp
->fx_r_type
)
24159 case BFD_RELOC_NONE
: type
= "NONE"; break;
24160 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24161 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24162 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24163 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24164 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24165 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24166 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24167 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24168 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24169 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24170 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24171 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24172 default: type
= _("<unknown>"); break;
24174 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24175 _("cannot represent %s relocation in this object file format"),
24182 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24184 && fixp
->fx_addsy
== GOT_symbol
)
24186 code
= BFD_RELOC_ARM_GOTPC
;
24187 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24191 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24193 if (reloc
->howto
== NULL
)
24195 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24196 _("cannot represent %s relocation in this object file format"),
24197 bfd_get_reloc_code_name (code
));
24201 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24202 vtable entry to be used in the relocation's section offset. */
24203 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24204 reloc
->address
= fixp
->fx_offset
;
24209 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24212 cons_fix_new_arm (fragS
* frag
,
24216 bfd_reloc_code_real_type reloc
)
24221 FIXME: @@ Should look at CPU word size. */
24225 reloc
= BFD_RELOC_8
;
24228 reloc
= BFD_RELOC_16
;
24232 reloc
= BFD_RELOC_32
;
24235 reloc
= BFD_RELOC_64
;
24240 if (exp
->X_op
== O_secrel
)
24242 exp
->X_op
= O_symbol
;
24243 reloc
= BFD_RELOC_32_SECREL
;
24247 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24250 #if defined (OBJ_COFF)
24252 arm_validate_fix (fixS
* fixP
)
24254 /* If the destination of the branch is a defined symbol which does not have
24255 the THUMB_FUNC attribute, then we must be calling a function which has
24256 the (interfacearm) attribute. We look for the Thumb entry point to that
24257 function and change the branch to refer to that function instead. */
24258 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24259 && fixP
->fx_addsy
!= NULL
24260 && S_IS_DEFINED (fixP
->fx_addsy
)
24261 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24263 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24270 arm_force_relocation (struct fix
* fixp
)
24272 #if defined (OBJ_COFF) && defined (TE_PE)
24273 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24277 /* In case we have a call or a branch to a function in ARM ISA mode from
24278 a thumb function or vice-versa force the relocation. These relocations
24279 are cleared off for some cores that might have blx and simple transformations
24283 switch (fixp
->fx_r_type
)
24285 case BFD_RELOC_ARM_PCREL_JUMP
:
24286 case BFD_RELOC_ARM_PCREL_CALL
:
24287 case BFD_RELOC_THUMB_PCREL_BLX
:
24288 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24292 case BFD_RELOC_ARM_PCREL_BLX
:
24293 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24294 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24295 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24296 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24305 /* Resolve these relocations even if the symbol is extern or weak.
24306 Technically this is probably wrong due to symbol preemption.
24307 In practice these relocations do not have enough range to be useful
24308 at dynamic link time, and some code (e.g. in the Linux kernel)
24309 expects these references to be resolved. */
24310 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24311 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24312 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24313 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24314 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24315 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24316 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24317 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24318 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24319 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24320 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
24321 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
24322 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
24323 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
24326 /* Always leave these relocations for the linker. */
24327 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24328 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24329 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24332 /* Always generate relocations against function symbols. */
24333 if (fixp
->fx_r_type
== BFD_RELOC_32
24335 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
24338 return generic_force_reloc (fixp
);
24341 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24342 /* Relocations against function names must be left unadjusted,
24343 so that the linker can use this information to generate interworking
24344 stubs. The MIPS version of this function
24345 also prevents relocations that are mips-16 specific, but I do not
24346 know why it does this.
24349 There is one other problem that ought to be addressed here, but
24350 which currently is not: Taking the address of a label (rather
24351 than a function) and then later jumping to that address. Such
24352 addresses also ought to have their bottom bit set (assuming that
24353 they reside in Thumb code), but at the moment they will not. */
24356 arm_fix_adjustable (fixS
* fixP
)
24358 if (fixP
->fx_addsy
== NULL
)
24361 /* Preserve relocations against symbols with function type. */
24362 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
24365 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
24366 && fixP
->fx_subsy
== NULL
)
24369 /* We need the symbol name for the VTABLE entries. */
24370 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
24371 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24374 /* Don't allow symbols to be discarded on GOT related relocs. */
24375 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
24376 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
24377 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
24378 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
24379 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
24380 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
24381 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
24382 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
24383 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
24384 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
24385 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
24386 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
24387 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
24388 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
24391 /* Similarly for group relocations. */
24392 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24393 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24394 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24397 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
24398 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
24399 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24400 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
24401 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
24402 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24403 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
24404 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
24405 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
24408 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
24409 offsets, so keep these symbols. */
24410 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
24411 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
24416 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
24420 elf32_arm_target_format (void)
24423 return (target_big_endian
24424 ? "elf32-bigarm-symbian"
24425 : "elf32-littlearm-symbian");
24426 #elif defined (TE_VXWORKS)
24427 return (target_big_endian
24428 ? "elf32-bigarm-vxworks"
24429 : "elf32-littlearm-vxworks");
24430 #elif defined (TE_NACL)
24431 return (target_big_endian
24432 ? "elf32-bigarm-nacl"
24433 : "elf32-littlearm-nacl");
24435 if (target_big_endian
)
24436 return "elf32-bigarm";
24438 return "elf32-littlearm";
24443 armelf_frob_symbol (symbolS
* symp
,
24446 elf_frob_symbol (symp
, puntp
);
24450 /* MD interface: Finalization. */
24455 literal_pool
* pool
;
24457 /* Ensure that all the IT blocks are properly closed. */
24458 check_it_blocks_finished ();
24460 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
24462 /* Put it at the end of the relevant section. */
24463 subseg_set (pool
->section
, pool
->sub_section
);
24465 arm_elf_change_section ();
24472 /* Remove any excess mapping symbols generated for alignment frags in
24473 SEC. We may have created a mapping symbol before a zero byte
24474 alignment; remove it if there's a mapping symbol after the
24477 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
24478 void *dummy ATTRIBUTE_UNUSED
)
24480 segment_info_type
*seginfo
= seg_info (sec
);
24483 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
24486 for (fragp
= seginfo
->frchainP
->frch_root
;
24488 fragp
= fragp
->fr_next
)
24490 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
24491 fragS
*next
= fragp
->fr_next
;
24493 /* Variable-sized frags have been converted to fixed size by
24494 this point. But if this was variable-sized to start with,
24495 there will be a fixed-size frag after it. So don't handle
24497 if (sym
== NULL
|| next
== NULL
)
24500 if (S_GET_VALUE (sym
) < next
->fr_address
)
24501 /* Not at the end of this frag. */
24503 know (S_GET_VALUE (sym
) == next
->fr_address
);
24507 if (next
->tc_frag_data
.first_map
!= NULL
)
24509 /* Next frag starts with a mapping symbol. Discard this
24511 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24515 if (next
->fr_next
== NULL
)
24517 /* This mapping symbol is at the end of the section. Discard
24519 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24520 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24524 /* As long as we have empty frags without any mapping symbols,
24526 /* If the next frag is non-empty and does not start with a
24527 mapping symbol, then this mapping symbol is required. */
24528 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24531 next
= next
->fr_next
;
24533 while (next
!= NULL
);
24538 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24542 arm_adjust_symtab (void)
24547 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24549 if (ARM_IS_THUMB (sym
))
24551 if (THUMB_IS_FUNC (sym
))
24553 /* Mark the symbol as a Thumb function. */
24554 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24555 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24556 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24558 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24559 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24561 as_bad (_("%s: unexpected function type: %d"),
24562 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24564 else switch (S_GET_STORAGE_CLASS (sym
))
24567 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24570 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24573 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24581 if (ARM_IS_INTERWORK (sym
))
24582 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24589 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24591 if (ARM_IS_THUMB (sym
))
24593 elf_symbol_type
* elf_sym
;
24595 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24596 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24598 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24599 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24601 /* If it's a .thumb_func, declare it as so,
24602 otherwise tag label as .code 16. */
24603 if (THUMB_IS_FUNC (sym
))
24604 elf_sym
->internal_elf_sym
.st_target_internal
24605 = ST_BRANCH_TO_THUMB
;
24606 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24607 elf_sym
->internal_elf_sym
.st_info
=
24608 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24613 /* Remove any overlapping mapping symbols generated by alignment frags. */
24614 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24615 /* Now do generic ELF adjustments. */
24616 elf_adjust_symtab ();
24620 /* MD interface: Initialization. */
24623 set_constant_flonums (void)
24627 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24628 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24632 /* Auto-select Thumb mode if it's the only available instruction set for the
24633 given architecture. */
24636 autoselect_thumb_from_cpu_variant (void)
24638 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24639 opcode_select (16);
24648 if ( (arm_ops_hsh
= hash_new ()) == NULL
24649 || (arm_cond_hsh
= hash_new ()) == NULL
24650 || (arm_shift_hsh
= hash_new ()) == NULL
24651 || (arm_psr_hsh
= hash_new ()) == NULL
24652 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24653 || (arm_reg_hsh
= hash_new ()) == NULL
24654 || (arm_reloc_hsh
= hash_new ()) == NULL
24655 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24656 as_fatal (_("virtual memory exhausted"));
24658 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24659 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24660 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24661 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24662 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24663 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24664 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24665 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24666 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24667 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24668 (void *) (v7m_psrs
+ i
));
24669 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24670 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
24672 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
24674 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
24675 (void *) (barrier_opt_names
+ i
));
24677 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
24679 struct reloc_entry
* entry
= reloc_names
+ i
;
24681 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
24682 /* This makes encode_branch() use the EABI versions of this relocation. */
24683 entry
->reloc
= BFD_RELOC_UNUSED
;
24685 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
24689 set_constant_flonums ();
24691 /* Set the cpu variant based on the command-line options. We prefer
24692 -mcpu= over -march= if both are set (as for GCC); and we prefer
24693 -mfpu= over any other way of setting the floating point unit.
24694 Use of legacy options with new options are faulted. */
24697 if (mcpu_cpu_opt
|| march_cpu_opt
)
24698 as_bad (_("use of old and new-style options to set CPU type"));
24700 mcpu_cpu_opt
= legacy_cpu
;
24702 else if (!mcpu_cpu_opt
)
24703 mcpu_cpu_opt
= march_cpu_opt
;
24708 as_bad (_("use of old and new-style options to set FPU type"));
24710 mfpu_opt
= legacy_fpu
;
24712 else if (!mfpu_opt
)
24714 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24715 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24716 /* Some environments specify a default FPU. If they don't, infer it
24717 from the processor. */
24719 mfpu_opt
= mcpu_fpu_opt
;
24721 mfpu_opt
= march_fpu_opt
;
24723 mfpu_opt
= &fpu_default
;
24729 if (mcpu_cpu_opt
!= NULL
)
24730 mfpu_opt
= &fpu_default
;
24731 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
24732 mfpu_opt
= &fpu_arch_vfp_v2
;
24734 mfpu_opt
= &fpu_arch_fpa
;
24740 mcpu_cpu_opt
= &cpu_default
;
24741 selected_cpu
= cpu_default
;
24743 else if (no_cpu_selected ())
24744 selected_cpu
= cpu_default
;
24747 selected_cpu
= *mcpu_cpu_opt
;
24749 mcpu_cpu_opt
= &arm_arch_any
;
24752 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24754 autoselect_thumb_from_cpu_variant ();
24756 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
24758 #if defined OBJ_COFF || defined OBJ_ELF
24760 unsigned int flags
= 0;
24762 #if defined OBJ_ELF
24763 flags
= meabi_flags
;
24765 switch (meabi_flags
)
24767 case EF_ARM_EABI_UNKNOWN
:
24769 /* Set the flags in the private structure. */
24770 if (uses_apcs_26
) flags
|= F_APCS26
;
24771 if (support_interwork
) flags
|= F_INTERWORK
;
24772 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
24773 if (pic_code
) flags
|= F_PIC
;
24774 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
24775 flags
|= F_SOFT_FLOAT
;
24777 switch (mfloat_abi_opt
)
24779 case ARM_FLOAT_ABI_SOFT
:
24780 case ARM_FLOAT_ABI_SOFTFP
:
24781 flags
|= F_SOFT_FLOAT
;
24784 case ARM_FLOAT_ABI_HARD
:
24785 if (flags
& F_SOFT_FLOAT
)
24786 as_bad (_("hard-float conflicts with specified fpu"));
24790 /* Using pure-endian doubles (even if soft-float). */
24791 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
24792 flags
|= F_VFP_FLOAT
;
24794 #if defined OBJ_ELF
24795 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
24796 flags
|= EF_ARM_MAVERICK_FLOAT
;
24799 case EF_ARM_EABI_VER4
:
24800 case EF_ARM_EABI_VER5
:
24801 /* No additional flags to set. */
24808 bfd_set_private_flags (stdoutput
, flags
);
24810 /* We have run out flags in the COFF header to encode the
24811 status of ATPCS support, so instead we create a dummy,
24812 empty, debug section called .arm.atpcs. */
24817 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
24821 bfd_set_section_flags
24822 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
24823 bfd_set_section_size (stdoutput
, sec
, 0);
24824 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
24830 /* Record the CPU type as well. */
24831 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
24832 mach
= bfd_mach_arm_iWMMXt2
;
24833 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
24834 mach
= bfd_mach_arm_iWMMXt
;
24835 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
24836 mach
= bfd_mach_arm_XScale
;
24837 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
24838 mach
= bfd_mach_arm_ep9312
;
24839 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
24840 mach
= bfd_mach_arm_5TE
;
24841 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
24843 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24844 mach
= bfd_mach_arm_5T
;
24846 mach
= bfd_mach_arm_5
;
24848 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
24850 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24851 mach
= bfd_mach_arm_4T
;
24853 mach
= bfd_mach_arm_4
;
24855 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
24856 mach
= bfd_mach_arm_3M
;
24857 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
24858 mach
= bfd_mach_arm_3
;
24859 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
24860 mach
= bfd_mach_arm_2a
;
24861 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
24862 mach
= bfd_mach_arm_2
;
24864 mach
= bfd_mach_arm_unknown
;
24866 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
24869 /* Command line processing. */
24872 Invocation line includes a switch not recognized by the base assembler.
24873 See if it's a processor-specific option.
24875 This routine is somewhat complicated by the need for backwards
24876 compatibility (since older releases of gcc can't be changed).
24877 The new options try to make the interface as compatible as
24880 New options (supported) are:
24882 -mcpu=<cpu name> Assemble for selected processor
24883 -march=<architecture name> Assemble for selected architecture
24884 -mfpu=<fpu architecture> Assemble for selected FPU.
24885 -EB/-mbig-endian Big-endian
24886 -EL/-mlittle-endian Little-endian
24887 -k Generate PIC code
24888 -mthumb Start in Thumb mode
24889 -mthumb-interwork Code supports ARM/Thumb interworking
24891 -m[no-]warn-deprecated Warn about deprecated features
24892 -m[no-]warn-syms Warn when symbols match instructions
24894 For now we will also provide support for:
24896 -mapcs-32 32-bit Program counter
24897 -mapcs-26 26-bit Program counter
24898 -macps-float Floats passed in FP registers
24899 -mapcs-reentrant Reentrant code
24901 (sometime these will probably be replaced with -mapcs=<list of options>
24902 and -matpcs=<list of options>)
24904 The remaining options are only supported for back-wards compatibility.
24905 Cpu variants, the arm part is optional:
24906 -m[arm]1 Currently not supported.
24907 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
24908 -m[arm]3 Arm 3 processor
24909 -m[arm]6[xx], Arm 6 processors
24910 -m[arm]7[xx][t][[d]m] Arm 7 processors
24911 -m[arm]8[10] Arm 8 processors
24912 -m[arm]9[20][tdmi] Arm 9 processors
24913 -mstrongarm[110[0]] StrongARM processors
24914 -mxscale XScale processors
24915 -m[arm]v[2345[t[e]]] Arm architectures
24916 -mall All (except the ARM1)
24918 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
24919 -mfpe-old (No float load/store multiples)
24920 -mvfpxd VFP Single precision
24922 -mno-fpu Disable all floating point instructions
24924 The following CPU names are recognized:
24925 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
24926 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
24927 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
24928 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
24929 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
24930 arm10t arm10e, arm1020t, arm1020e, arm10200e,
24931 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
24935 const char * md_shortopts
= "m:k";
24937 #ifdef ARM_BI_ENDIAN
24938 #define OPTION_EB (OPTION_MD_BASE + 0)
24939 #define OPTION_EL (OPTION_MD_BASE + 1)
24941 #if TARGET_BYTES_BIG_ENDIAN
24942 #define OPTION_EB (OPTION_MD_BASE + 0)
24944 #define OPTION_EL (OPTION_MD_BASE + 1)
24947 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
24949 struct option md_longopts
[] =
24952 {"EB", no_argument
, NULL
, OPTION_EB
},
24955 {"EL", no_argument
, NULL
, OPTION_EL
},
24957 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
24958 {NULL
, no_argument
, NULL
, 0}
24962 size_t md_longopts_size
= sizeof (md_longopts
);
24964 struct arm_option_table
24966 const char *option
; /* Option name to match. */
24967 const char *help
; /* Help information. */
24968 int *var
; /* Variable to change. */
24969 int value
; /* What to change it to. */
24970 const char *deprecated
; /* If non-null, print this message. */
24973 struct arm_option_table arm_opts
[] =
24975 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
24976 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
24977 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
24978 &support_interwork
, 1, NULL
},
24979 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
24980 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
24981 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
24983 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
24984 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
24985 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
24986 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
24989 /* These are recognized by the assembler, but have no affect on code. */
24990 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
24991 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
24993 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
24994 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
24995 &warn_on_deprecated
, 0, NULL
},
24996 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
24997 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
24998 {NULL
, NULL
, NULL
, 0, NULL
}
25001 struct arm_legacy_option_table
25003 const char *option
; /* Option name to match. */
25004 const arm_feature_set
**var
; /* Variable to change. */
25005 const arm_feature_set value
; /* What to change it to. */
25006 const char *deprecated
; /* If non-null, print this message. */
25009 const struct arm_legacy_option_table arm_legacy_opts
[] =
25011 /* DON'T add any new processors to this list -- we want the whole list
25012 to go away... Add them to the processors table instead. */
25013 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25014 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25015 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25016 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25017 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25018 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25019 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25020 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25021 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25022 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25023 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25024 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25025 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25026 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25027 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25028 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25029 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25030 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25031 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25032 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25033 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25034 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25035 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25036 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25037 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25038 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25039 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25040 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25041 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25042 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25043 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25044 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25045 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25046 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25047 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25048 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25049 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25050 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25051 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25052 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25053 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25054 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25055 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25056 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25057 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25058 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25059 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25060 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25061 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25062 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25063 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25064 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25065 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25066 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25067 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25068 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25069 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25070 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25071 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25072 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25073 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25074 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25075 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25076 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25077 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25078 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25079 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25080 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25081 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25082 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25083 N_("use -mcpu=strongarm110")},
25084 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25085 N_("use -mcpu=strongarm1100")},
25086 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25087 N_("use -mcpu=strongarm1110")},
25088 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25089 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25090 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25092 /* Architecture variants -- don't add any more to this list either. */
25093 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25094 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25095 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25096 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25097 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25098 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25099 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25100 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25101 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25102 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25103 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25104 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25105 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25106 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25107 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25108 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25109 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25110 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25112 /* Floating point variants -- don't add any more to this list either. */
25113 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25114 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25115 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25116 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25117 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25119 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25122 struct arm_cpu_option_table
25126 const arm_feature_set value
;
25127 /* For some CPUs we assume an FPU unless the user explicitly sets
25129 const arm_feature_set default_fpu
;
25130 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25132 const char *canonical_name
;
25135 /* This list should, at a minimum, contain all the cpu names
25136 recognized by GCC. */
25137 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
25138 static const struct arm_cpu_option_table arm_cpus
[] =
25140 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
25141 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
25142 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
25143 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25144 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25145 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25146 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25147 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25148 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25149 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25150 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25151 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25152 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25153 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25154 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25155 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25156 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25157 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25158 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25159 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25160 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25161 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25162 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25163 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25164 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25165 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25166 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25167 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25168 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25169 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25170 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25171 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25172 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25173 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25174 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25175 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25176 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25177 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25178 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25179 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
25180 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25181 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25182 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25183 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25184 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25185 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25186 /* For V5 or later processors we default to using VFP; but the user
25187 should really set the FPU type explicitly. */
25188 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25189 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25190 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25191 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25192 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25193 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25194 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
25195 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25196 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25197 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
25198 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25199 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25200 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25201 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25202 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25203 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
25204 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25205 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25206 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25207 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
25209 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25210 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25211 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25212 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25213 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25214 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25215 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
25216 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
25217 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
25219 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
25220 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
25221 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
25222 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
25223 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
25224 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ
, FPU_NONE
, NULL
),
25225 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ
, FPU_ARCH_VFP_V2
, NULL
),
25226 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
25227 FPU_NONE
, "Cortex-A5"),
25228 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25230 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
25231 ARM_FEATURE_COPROC (FPU_VFP_V3
25232 | FPU_NEON_EXT_V1
),
25234 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
25235 ARM_FEATURE_COPROC (FPU_VFP_V3
25236 | FPU_NEON_EXT_V1
),
25238 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25240 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25242 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25244 ARM_CPU_OPT ("cortex-a32", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25246 ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25248 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25250 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25252 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25254 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
25255 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
25257 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
25258 FPU_NONE
, "Cortex-R5"),
25259 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
25260 FPU_ARCH_VFP_V3D16
,
25262 ARM_CPU_OPT ("cortex-r8", ARM_ARCH_V7R_IDIV
,
25263 FPU_ARCH_VFP_V3D16
,
25265 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
25266 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
25267 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
25268 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
25269 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
25270 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
25271 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25274 ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25278 /* ??? XSCALE is really an architecture. */
25279 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25280 /* ??? iwmmxt is not a processor. */
25281 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
25282 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
25283 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25285 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
25286 FPU_ARCH_MAVERICK
, "ARM920T"),
25287 /* Marvell processors. */
25288 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25290 ARM_EXT2_V6T2_V8M
),
25291 FPU_ARCH_VFP_V3D16
, NULL
),
25292 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25294 ARM_EXT2_V6T2_V8M
),
25295 FPU_ARCH_NEON_VFP_V4
, NULL
),
25296 /* APM X-Gene family. */
25297 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25299 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25302 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
25306 struct arm_arch_option_table
25310 const arm_feature_set value
;
25311 const arm_feature_set default_fpu
;
25314 /* This list should, at a minimum, contain all the architecture names
25315 recognized by GCC. */
25316 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
25317 static const struct arm_arch_option_table arm_archs
[] =
25319 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
25320 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
25321 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
25322 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25323 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25324 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
25325 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
25326 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
25327 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
25328 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
25329 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
25330 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
25331 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
25332 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
25333 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
25334 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
25335 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
25336 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25337 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25338 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
25339 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
25340 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
25341 kept to preserve existing behaviour. */
25342 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25343 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25344 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
25345 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
25346 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
25347 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
25348 kept to preserve existing behaviour. */
25349 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25350 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25351 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
25352 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
25353 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
25354 /* The official spelling of the ARMv7 profile variants is the dashed form.
25355 Accept the non-dashed form for compatibility with old toolchains. */
25356 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25357 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
25358 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25359 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25360 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25361 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25362 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25363 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
25364 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
25365 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
25366 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
25367 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
25368 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
25369 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
25370 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
25371 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
25372 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25374 #undef ARM_ARCH_OPT
25376 /* ISA extensions in the co-processor and main instruction set space. */
25377 struct arm_option_extension_value_table
25381 const arm_feature_set merge_value
;
25382 const arm_feature_set clear_value
;
25383 const arm_feature_set allowed_archs
;
25386 /* The following table must be in alphabetical order with a NULL last entry.
25388 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA }
25389 static const struct arm_option_extension_value_table arm_extensions
[] =
25391 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25392 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25393 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25394 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
25395 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25396 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
25397 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25398 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25399 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25401 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25402 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25403 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
25404 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
25405 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ANY
),
25406 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
25407 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ANY
),
25408 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
25409 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ANY
),
25410 ARM_EXT_OPT ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25411 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25412 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
25413 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25414 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25415 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
25416 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
25417 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
25418 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25419 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
25420 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
25421 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25422 ARM_EXT_OPT ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25423 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25424 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V7A
)),
25425 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
25426 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
25427 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25428 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
25430 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
25431 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25432 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
25433 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ANY
),
25434 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25438 /* ISA floating-point and Advanced SIMD extensions. */
25439 struct arm_option_fpu_value_table
25442 const arm_feature_set value
;
25445 /* This list should, at a minimum, contain all the fpu names
25446 recognized by GCC. */
25447 static const struct arm_option_fpu_value_table arm_fpus
[] =
25449 {"softfpa", FPU_NONE
},
25450 {"fpe", FPU_ARCH_FPE
},
25451 {"fpe2", FPU_ARCH_FPE
},
25452 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
25453 {"fpa", FPU_ARCH_FPA
},
25454 {"fpa10", FPU_ARCH_FPA
},
25455 {"fpa11", FPU_ARCH_FPA
},
25456 {"arm7500fe", FPU_ARCH_FPA
},
25457 {"softvfp", FPU_ARCH_VFP
},
25458 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
25459 {"vfp", FPU_ARCH_VFP_V2
},
25460 {"vfp9", FPU_ARCH_VFP_V2
},
25461 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
25462 {"vfp10", FPU_ARCH_VFP_V2
},
25463 {"vfp10-r0", FPU_ARCH_VFP_V1
},
25464 {"vfpxd", FPU_ARCH_VFP_V1xD
},
25465 {"vfpv2", FPU_ARCH_VFP_V2
},
25466 {"vfpv3", FPU_ARCH_VFP_V3
},
25467 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
25468 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
25469 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
25470 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
25471 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
25472 {"arm1020t", FPU_ARCH_VFP_V1
},
25473 {"arm1020e", FPU_ARCH_VFP_V2
},
25474 {"arm1136jfs", FPU_ARCH_VFP_V2
},
25475 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
25476 {"maverick", FPU_ARCH_MAVERICK
},
25477 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
25478 {"neon-fp16", FPU_ARCH_NEON_FP16
},
25479 {"vfpv4", FPU_ARCH_VFP_V4
},
25480 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
25481 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
25482 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
25483 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
25484 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
25485 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
25486 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
25487 {"crypto-neon-fp-armv8",
25488 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
25489 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
25490 {"crypto-neon-fp-armv8.1",
25491 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
25492 {NULL
, ARM_ARCH_NONE
}
25495 struct arm_option_value_table
25501 static const struct arm_option_value_table arm_float_abis
[] =
25503 {"hard", ARM_FLOAT_ABI_HARD
},
25504 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
25505 {"soft", ARM_FLOAT_ABI_SOFT
},
25510 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
25511 static const struct arm_option_value_table arm_eabis
[] =
25513 {"gnu", EF_ARM_EABI_UNKNOWN
},
25514 {"4", EF_ARM_EABI_VER4
},
25515 {"5", EF_ARM_EABI_VER5
},
25520 struct arm_long_option_table
25522 const char * option
; /* Substring to match. */
25523 const char * help
; /* Help information. */
25524 int (* func
) (char * subopt
); /* Function to decode sub-option. */
25525 const char * deprecated
; /* If non-null, print this message. */
25529 arm_parse_extension (char *str
, const arm_feature_set
**opt_p
)
25531 arm_feature_set
*ext_set
= (arm_feature_set
*)
25532 xmalloc (sizeof (arm_feature_set
));
25534 /* We insist on extensions being specified in alphabetical order, and with
25535 extensions being added before being removed. We achieve this by having
25536 the global ARM_EXTENSIONS table in alphabetical order, and using the
25537 ADDING_VALUE variable to indicate whether we are adding an extension (1)
25538 or removing it (0) and only allowing it to change in the order
25540 const struct arm_option_extension_value_table
* opt
= NULL
;
25541 int adding_value
= -1;
25543 /* Copy the feature set, so that we can modify it. */
25544 *ext_set
= **opt_p
;
25547 while (str
!= NULL
&& *str
!= 0)
25554 as_bad (_("invalid architectural extension"));
25559 ext
= strchr (str
, '+');
25564 len
= strlen (str
);
25566 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
25568 if (adding_value
!= 0)
25571 opt
= arm_extensions
;
25579 if (adding_value
== -1)
25582 opt
= arm_extensions
;
25584 else if (adding_value
!= 1)
25586 as_bad (_("must specify extensions to add before specifying "
25587 "those to remove"));
25594 as_bad (_("missing architectural extension"));
25598 gas_assert (adding_value
!= -1);
25599 gas_assert (opt
!= NULL
);
25601 /* Scan over the options table trying to find an exact match. */
25602 for (; opt
->name
!= NULL
; opt
++)
25603 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25605 /* Check we can apply the extension to this architecture. */
25606 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
25608 as_bad (_("extension does not apply to the base architecture"));
25612 /* Add or remove the extension. */
25614 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
25616 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
25621 if (opt
->name
== NULL
)
25623 /* Did we fail to find an extension because it wasn't specified in
25624 alphabetical order, or because it does not exist? */
25626 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25627 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25630 if (opt
->name
== NULL
)
25631 as_bad (_("unknown architectural extension `%s'"), str
);
25633 as_bad (_("architectural extensions must be specified in "
25634 "alphabetical order"));
25640 /* We should skip the extension we've just matched the next time
25652 arm_parse_cpu (char *str
)
25654 const struct arm_cpu_option_table
*opt
;
25655 char *ext
= strchr (str
, '+');
25661 len
= strlen (str
);
25665 as_bad (_("missing cpu name `%s'"), str
);
25669 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
25670 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25672 mcpu_cpu_opt
= &opt
->value
;
25673 mcpu_fpu_opt
= &opt
->default_fpu
;
25674 if (opt
->canonical_name
)
25676 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
25677 strcpy (selected_cpu_name
, opt
->canonical_name
);
25683 if (len
>= sizeof selected_cpu_name
)
25684 len
= (sizeof selected_cpu_name
) - 1;
25686 for (i
= 0; i
< len
; i
++)
25687 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25688 selected_cpu_name
[i
] = 0;
25692 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
25697 as_bad (_("unknown cpu `%s'"), str
);
25702 arm_parse_arch (char *str
)
25704 const struct arm_arch_option_table
*opt
;
25705 char *ext
= strchr (str
, '+');
25711 len
= strlen (str
);
25715 as_bad (_("missing architecture name `%s'"), str
);
25719 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
25720 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25722 march_cpu_opt
= &opt
->value
;
25723 march_fpu_opt
= &opt
->default_fpu
;
25724 strcpy (selected_cpu_name
, opt
->name
);
25727 return arm_parse_extension (ext
, &march_cpu_opt
);
25732 as_bad (_("unknown architecture `%s'\n"), str
);
25737 arm_parse_fpu (char * str
)
25739 const struct arm_option_fpu_value_table
* opt
;
25741 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25742 if (streq (opt
->name
, str
))
25744 mfpu_opt
= &opt
->value
;
25748 as_bad (_("unknown floating point format `%s'\n"), str
);
25753 arm_parse_float_abi (char * str
)
25755 const struct arm_option_value_table
* opt
;
25757 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
25758 if (streq (opt
->name
, str
))
25760 mfloat_abi_opt
= opt
->value
;
25764 as_bad (_("unknown floating point abi `%s'\n"), str
);
25770 arm_parse_eabi (char * str
)
25772 const struct arm_option_value_table
*opt
;
25774 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
25775 if (streq (opt
->name
, str
))
25777 meabi_flags
= opt
->value
;
25780 as_bad (_("unknown EABI `%s'\n"), str
);
25786 arm_parse_it_mode (char * str
)
25788 bfd_boolean ret
= TRUE
;
25790 if (streq ("arm", str
))
25791 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
25792 else if (streq ("thumb", str
))
25793 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
25794 else if (streq ("always", str
))
25795 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
25796 else if (streq ("never", str
))
25797 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
25800 as_bad (_("unknown implicit IT mode `%s', should be "\
25801 "arm, thumb, always, or never."), str
);
25809 arm_ccs_mode (char * unused ATTRIBUTE_UNUSED
)
25811 codecomposer_syntax
= TRUE
;
25812 arm_comment_chars
[0] = ';';
25813 arm_line_separator_chars
[0] = 0;
25817 struct arm_long_option_table arm_long_opts
[] =
25819 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
25820 arm_parse_cpu
, NULL
},
25821 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
25822 arm_parse_arch
, NULL
},
25823 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
25824 arm_parse_fpu
, NULL
},
25825 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
25826 arm_parse_float_abi
, NULL
},
25828 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
25829 arm_parse_eabi
, NULL
},
25831 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
25832 arm_parse_it_mode
, NULL
},
25833 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
25834 arm_ccs_mode
, NULL
},
25835 {NULL
, NULL
, 0, NULL
}
25839 md_parse_option (int c
, char * arg
)
25841 struct arm_option_table
*opt
;
25842 const struct arm_legacy_option_table
*fopt
;
25843 struct arm_long_option_table
*lopt
;
25849 target_big_endian
= 1;
25855 target_big_endian
= 0;
25859 case OPTION_FIX_V4BX
:
25864 /* Listing option. Just ignore these, we don't support additional
25869 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25871 if (c
== opt
->option
[0]
25872 && ((arg
== NULL
&& opt
->option
[1] == 0)
25873 || streq (arg
, opt
->option
+ 1)))
25875 /* If the option is deprecated, tell the user. */
25876 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
25877 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25878 arg
? arg
: "", _(opt
->deprecated
));
25880 if (opt
->var
!= NULL
)
25881 *opt
->var
= opt
->value
;
25887 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
25889 if (c
== fopt
->option
[0]
25890 && ((arg
== NULL
&& fopt
->option
[1] == 0)
25891 || streq (arg
, fopt
->option
+ 1)))
25893 /* If the option is deprecated, tell the user. */
25894 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
25895 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25896 arg
? arg
: "", _(fopt
->deprecated
));
25898 if (fopt
->var
!= NULL
)
25899 *fopt
->var
= &fopt
->value
;
25905 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25907 /* These options are expected to have an argument. */
25908 if (c
== lopt
->option
[0]
25910 && strncmp (arg
, lopt
->option
+ 1,
25911 strlen (lopt
->option
+ 1)) == 0)
25913 /* If the option is deprecated, tell the user. */
25914 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
25915 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
25916 _(lopt
->deprecated
));
25918 /* Call the sup-option parser. */
25919 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
25930 md_show_usage (FILE * fp
)
25932 struct arm_option_table
*opt
;
25933 struct arm_long_option_table
*lopt
;
25935 fprintf (fp
, _(" ARM-specific assembler options:\n"));
25937 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25938 if (opt
->help
!= NULL
)
25939 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
25941 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25942 if (lopt
->help
!= NULL
)
25943 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
25947 -EB assemble code for a big-endian cpu\n"));
25952 -EL assemble code for a little-endian cpu\n"));
25956 --fix-v4bx Allow BX in ARMv4 code\n"));
25964 arm_feature_set flags
;
25965 } cpu_arch_ver_table
;
25967 /* Mapping from CPU features to EABI CPU arch values. As a general rule, table
25968 must be sorted least features first but some reordering is needed, eg. for
25969 Thumb-2 instructions to be detected as coming from ARMv6T2. */
25970 static const cpu_arch_ver_table cpu_arch_ver
[] =
25976 {4, ARM_ARCH_V5TE
},
25977 {5, ARM_ARCH_V5TEJ
},
25981 {11, ARM_ARCH_V6M
},
25982 {12, ARM_ARCH_V6SM
},
25983 {8, ARM_ARCH_V6T2
},
25984 {10, ARM_ARCH_V7VE
},
25985 {10, ARM_ARCH_V7R
},
25986 {10, ARM_ARCH_V7M
},
25987 {14, ARM_ARCH_V8A
},
25988 {16, ARM_ARCH_V8M_BASE
},
25989 {17, ARM_ARCH_V8M_MAIN
},
25993 /* Set an attribute if it has not already been set by the user. */
25995 aeabi_set_attribute_int (int tag
, int value
)
25998 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25999 || !attributes_set_explicitly
[tag
])
26000 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
26004 aeabi_set_attribute_string (int tag
, const char *value
)
26007 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26008 || !attributes_set_explicitly
[tag
])
26009 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
26012 /* Set the public EABI object attributes. */
26014 aeabi_set_public_attributes (void)
26019 int fp16_optional
= 0;
26020 arm_feature_set flags
;
26021 arm_feature_set tmp
;
26022 arm_feature_set arm_arch_v8m_base
= ARM_ARCH_V8M_BASE
;
26023 const cpu_arch_ver_table
*p
;
26025 /* Choose the architecture based on the capabilities of the requested cpu
26026 (if any) and/or the instructions actually used. */
26027 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
26028 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
26029 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
26031 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
26032 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
26034 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
26035 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
26037 selected_cpu
= flags
;
26039 /* Allow the user to override the reported architecture. */
26042 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
26043 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
26046 /* We need to make sure that the attributes do not identify us as v6S-M
26047 when the only v6S-M feature in use is the Operating System Extensions. */
26048 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
26049 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
26050 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
26054 for (p
= cpu_arch_ver
; p
->val
; p
++)
26056 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
26059 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
26063 /* The table lookup above finds the last architecture to contribute
26064 a new feature. Unfortunately, Tag13 is a subset of the union of
26065 v6T2 and v7-M, so it is never seen as contributing a new feature.
26066 We can not search for the last entry which is entirely used,
26067 because if no CPU is specified we build up only those flags
26068 actually used. Perhaps we should separate out the specified
26069 and implicit cases. Avoid taking this path for -march=all by
26070 checking for contradictory v7-A / v7-M features. */
26071 if (arch
== TAG_CPU_ARCH_V7
26072 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26073 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
26074 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
26075 arch
= TAG_CPU_ARCH_V7E_M
;
26077 ARM_CLEAR_FEATURE (tmp
, flags
, arm_arch_v8m_base
);
26078 if (arch
== TAG_CPU_ARCH_V8M_BASE
&& ARM_CPU_HAS_FEATURE (tmp
, arm_arch_any
))
26079 arch
= TAG_CPU_ARCH_V8M_MAIN
;
26081 /* In cpu_arch_ver ARMv8-A is before ARMv8-M for atomics to be detected as
26082 coming from ARMv8-A. However, since ARMv8-A has more instructions than
26083 ARMv8-M, -march=all must be detected as ARMv8-A. */
26084 if (arch
== TAG_CPU_ARCH_V8M_MAIN
26085 && ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
26086 arch
= TAG_CPU_ARCH_V8
;
26088 /* Tag_CPU_name. */
26089 if (selected_cpu_name
[0])
26093 q
= selected_cpu_name
;
26094 if (strncmp (q
, "armv", 4) == 0)
26099 for (i
= 0; q
[i
]; i
++)
26100 q
[i
] = TOUPPER (q
[i
]);
26102 aeabi_set_attribute_string (Tag_CPU_name
, q
);
26105 /* Tag_CPU_arch. */
26106 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
26108 /* Tag_CPU_arch_profile. */
26109 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26110 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26111 || (ARM_CPU_HAS_FEATURE (flags
, arm_ext_atomics
)
26112 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
)))
26114 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
26116 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
26121 if (profile
!= '\0')
26122 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
26124 /* Tag_ARM_ISA_use. */
26125 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
26127 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
26129 /* Tag_THUMB_ISA_use. */
26130 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
26135 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26136 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
26138 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
26142 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
26145 /* Tag_VFP_arch. */
26146 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
26147 aeabi_set_attribute_int (Tag_VFP_arch
,
26148 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26150 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
26151 aeabi_set_attribute_int (Tag_VFP_arch
,
26152 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26154 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
26157 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
26159 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
26161 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
26164 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
26165 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
26166 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
26167 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
26168 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
26170 /* Tag_ABI_HardFP_use. */
26171 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
26172 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
26173 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
26175 /* Tag_WMMX_arch. */
26176 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
26177 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
26178 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
26179 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
26181 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
26182 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
26183 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
26184 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
26185 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
26186 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
26188 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
26190 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
26194 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
26199 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
26200 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
26201 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
26205 We set Tag_DIV_use to two when integer divide instructions have been used
26206 in ARM state, or when Thumb integer divide instructions have been used,
26207 but we have no architecture profile set, nor have we any ARM instructions.
26209 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
26210 by the base architecture.
26212 For new architectures we will have to check these tests. */
26213 gas_assert (arch
<= TAG_CPU_ARCH_V8
26214 || (arch
>= TAG_CPU_ARCH_V8M_BASE
26215 && arch
<= TAG_CPU_ARCH_V8M_MAIN
));
26216 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26217 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
26218 aeabi_set_attribute_int (Tag_DIV_use
, 0);
26219 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
26220 || (profile
== '\0'
26221 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
26222 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
26223 aeabi_set_attribute_int (Tag_DIV_use
, 2);
26225 /* Tag_MP_extension_use. */
26226 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
26227 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
26229 /* Tag Virtualization_use. */
26230 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
26232 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
26235 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
26238 /* Add the default contents for the .ARM.attributes section. */
26242 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
26245 aeabi_set_public_attributes ();
26247 #endif /* OBJ_ELF */
26250 /* Parse a .cpu directive. */
26253 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
26255 const struct arm_cpu_option_table
*opt
;
26259 name
= input_line_pointer
;
26260 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26261 input_line_pointer
++;
26262 saved_char
= *input_line_pointer
;
26263 *input_line_pointer
= 0;
26265 /* Skip the first "all" entry. */
26266 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
26267 if (streq (opt
->name
, name
))
26269 mcpu_cpu_opt
= &opt
->value
;
26270 selected_cpu
= opt
->value
;
26271 if (opt
->canonical_name
)
26272 strcpy (selected_cpu_name
, opt
->canonical_name
);
26276 for (i
= 0; opt
->name
[i
]; i
++)
26277 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26279 selected_cpu_name
[i
] = 0;
26281 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26282 *input_line_pointer
= saved_char
;
26283 demand_empty_rest_of_line ();
26286 as_bad (_("unknown cpu `%s'"), name
);
26287 *input_line_pointer
= saved_char
;
26288 ignore_rest_of_line ();
26292 /* Parse a .arch directive. */
26295 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
26297 const struct arm_arch_option_table
*opt
;
26301 name
= input_line_pointer
;
26302 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26303 input_line_pointer
++;
26304 saved_char
= *input_line_pointer
;
26305 *input_line_pointer
= 0;
26307 /* Skip the first "all" entry. */
26308 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26309 if (streq (opt
->name
, name
))
26311 mcpu_cpu_opt
= &opt
->value
;
26312 selected_cpu
= opt
->value
;
26313 strcpy (selected_cpu_name
, opt
->name
);
26314 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26315 *input_line_pointer
= saved_char
;
26316 demand_empty_rest_of_line ();
26320 as_bad (_("unknown architecture `%s'\n"), name
);
26321 *input_line_pointer
= saved_char
;
26322 ignore_rest_of_line ();
26326 /* Parse a .object_arch directive. */
26329 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
26331 const struct arm_arch_option_table
*opt
;
26335 name
= input_line_pointer
;
26336 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26337 input_line_pointer
++;
26338 saved_char
= *input_line_pointer
;
26339 *input_line_pointer
= 0;
26341 /* Skip the first "all" entry. */
26342 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26343 if (streq (opt
->name
, name
))
26345 object_arch
= &opt
->value
;
26346 *input_line_pointer
= saved_char
;
26347 demand_empty_rest_of_line ();
26351 as_bad (_("unknown architecture `%s'\n"), name
);
26352 *input_line_pointer
= saved_char
;
26353 ignore_rest_of_line ();
26356 /* Parse a .arch_extension directive. */
26359 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
26361 const struct arm_option_extension_value_table
*opt
;
26364 int adding_value
= 1;
26366 name
= input_line_pointer
;
26367 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26368 input_line_pointer
++;
26369 saved_char
= *input_line_pointer
;
26370 *input_line_pointer
= 0;
26372 if (strlen (name
) >= 2
26373 && strncmp (name
, "no", 2) == 0)
26379 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26380 if (streq (opt
->name
, name
))
26382 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
26384 as_bad (_("architectural extension `%s' is not allowed for the "
26385 "current base architecture"), name
);
26390 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
26393 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
26395 mcpu_cpu_opt
= &selected_cpu
;
26396 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26397 *input_line_pointer
= saved_char
;
26398 demand_empty_rest_of_line ();
26402 if (opt
->name
== NULL
)
26403 as_bad (_("unknown architecture extension `%s'\n"), name
);
26405 *input_line_pointer
= saved_char
;
26406 ignore_rest_of_line ();
26409 /* Parse a .fpu directive. */
26412 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
26414 const struct arm_option_fpu_value_table
*opt
;
26418 name
= input_line_pointer
;
26419 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26420 input_line_pointer
++;
26421 saved_char
= *input_line_pointer
;
26422 *input_line_pointer
= 0;
26424 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26425 if (streq (opt
->name
, name
))
26427 mfpu_opt
= &opt
->value
;
26428 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26429 *input_line_pointer
= saved_char
;
26430 demand_empty_rest_of_line ();
26434 as_bad (_("unknown floating point format `%s'\n"), name
);
26435 *input_line_pointer
= saved_char
;
26436 ignore_rest_of_line ();
26439 /* Copy symbol information. */
26442 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
26444 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
26448 /* Given a symbolic attribute NAME, return the proper integer value.
26449 Returns -1 if the attribute is not known. */
26452 arm_convert_symbolic_attribute (const char *name
)
26454 static const struct
26459 attribute_table
[] =
26461 /* When you modify this table you should
26462 also modify the list in doc/c-arm.texi. */
26463 #define T(tag) {#tag, tag}
26464 T (Tag_CPU_raw_name
),
26467 T (Tag_CPU_arch_profile
),
26468 T (Tag_ARM_ISA_use
),
26469 T (Tag_THUMB_ISA_use
),
26473 T (Tag_Advanced_SIMD_arch
),
26474 T (Tag_PCS_config
),
26475 T (Tag_ABI_PCS_R9_use
),
26476 T (Tag_ABI_PCS_RW_data
),
26477 T (Tag_ABI_PCS_RO_data
),
26478 T (Tag_ABI_PCS_GOT_use
),
26479 T (Tag_ABI_PCS_wchar_t
),
26480 T (Tag_ABI_FP_rounding
),
26481 T (Tag_ABI_FP_denormal
),
26482 T (Tag_ABI_FP_exceptions
),
26483 T (Tag_ABI_FP_user_exceptions
),
26484 T (Tag_ABI_FP_number_model
),
26485 T (Tag_ABI_align_needed
),
26486 T (Tag_ABI_align8_needed
),
26487 T (Tag_ABI_align_preserved
),
26488 T (Tag_ABI_align8_preserved
),
26489 T (Tag_ABI_enum_size
),
26490 T (Tag_ABI_HardFP_use
),
26491 T (Tag_ABI_VFP_args
),
26492 T (Tag_ABI_WMMX_args
),
26493 T (Tag_ABI_optimization_goals
),
26494 T (Tag_ABI_FP_optimization_goals
),
26495 T (Tag_compatibility
),
26496 T (Tag_CPU_unaligned_access
),
26497 T (Tag_FP_HP_extension
),
26498 T (Tag_VFP_HP_extension
),
26499 T (Tag_ABI_FP_16bit_format
),
26500 T (Tag_MPextension_use
),
26502 T (Tag_nodefaults
),
26503 T (Tag_also_compatible_with
),
26504 T (Tag_conformance
),
26506 T (Tag_Virtualization_use
),
26507 /* We deliberately do not include Tag_MPextension_use_legacy. */
26515 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
26516 if (streq (name
, attribute_table
[i
].name
))
26517 return attribute_table
[i
].tag
;
26523 /* Apply sym value for relocations only in the case that they are for
26524 local symbols in the same segment as the fixup and you have the
26525 respective architectural feature for blx and simple switches. */
26527 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
26530 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26531 /* PR 17444: If the local symbol is in a different section then a reloc
26532 will always be generated for it, so applying the symbol value now
26533 will result in a double offset being stored in the relocation. */
26534 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
26535 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
26537 switch (fixP
->fx_r_type
)
26539 case BFD_RELOC_ARM_PCREL_BLX
:
26540 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26541 if (ARM_IS_FUNC (fixP
->fx_addsy
))
26545 case BFD_RELOC_ARM_PCREL_CALL
:
26546 case BFD_RELOC_THUMB_PCREL_BLX
:
26547 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
26558 #endif /* OBJ_ELF */