1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
* legacy_cpu
= NULL
;
147 static const arm_feature_set
* legacy_fpu
= NULL
;
149 static const arm_feature_set
* mcpu_cpu_opt
= NULL
;
150 static arm_feature_set
* dyn_mcpu_ext_opt
= NULL
;
151 static const arm_feature_set
* mcpu_fpu_opt
= NULL
;
152 static const arm_feature_set
* march_cpu_opt
= NULL
;
153 static arm_feature_set
* dyn_march_ext_opt
= NULL
;
154 static const arm_feature_set
* march_fpu_opt
= NULL
;
155 static const arm_feature_set
* mfpu_opt
= NULL
;
156 static const arm_feature_set
* object_arch
= NULL
;
158 /* Constants for known architecture features. */
159 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
160 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
161 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
162 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
163 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
164 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
165 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
167 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
169 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
172 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
175 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
176 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
177 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
178 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
179 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
180 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
181 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
182 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
183 static const arm_feature_set arm_ext_v4t_5
=
184 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
185 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
186 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
187 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
188 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
189 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
190 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
191 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
192 static const arm_feature_set arm_ext_v6_notm
=
193 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
194 static const arm_feature_set arm_ext_v6_dsp
=
195 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
196 static const arm_feature_set arm_ext_barrier
=
197 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
198 static const arm_feature_set arm_ext_msr
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
200 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
201 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
202 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
203 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
205 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
207 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
208 static const arm_feature_set arm_ext_m
=
209 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
210 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
211 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
212 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
213 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
214 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
215 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
216 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
217 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
218 static const arm_feature_set arm_ext_v8m_main
=
219 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
220 /* Instructions in ARMv8-M only found in M profile architectures. */
221 static const arm_feature_set arm_ext_v8m_m_only
=
222 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
223 static const arm_feature_set arm_ext_v6t2_v8m
=
224 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
225 /* Instructions shared between ARMv8-A and ARMv8-M. */
226 static const arm_feature_set arm_ext_atomics
=
227 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
229 /* DSP instructions Tag_DSP_extension refers to. */
230 static const arm_feature_set arm_ext_dsp
=
231 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
233 static const arm_feature_set arm_ext_ras
=
234 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
235 /* FP16 instructions. */
236 static const arm_feature_set arm_ext_fp16
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
238 static const arm_feature_set arm_ext_v8_2
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
240 static const arm_feature_set arm_ext_v8_3
=
241 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
243 static const arm_feature_set arm_arch_any
= ARM_ANY
;
245 static const arm_feature_set fpu_any
= FPU_ANY
;
247 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
248 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
249 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
251 static const arm_feature_set arm_cext_iwmmxt2
=
252 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
253 static const arm_feature_set arm_cext_iwmmxt
=
254 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
255 static const arm_feature_set arm_cext_xscale
=
256 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
257 static const arm_feature_set arm_cext_maverick
=
258 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
259 static const arm_feature_set fpu_fpa_ext_v1
=
260 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
261 static const arm_feature_set fpu_fpa_ext_v2
=
262 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
263 static const arm_feature_set fpu_vfp_ext_v1xd
=
264 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
265 static const arm_feature_set fpu_vfp_ext_v1
=
266 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
267 static const arm_feature_set fpu_vfp_ext_v2
=
268 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
269 static const arm_feature_set fpu_vfp_ext_v3xd
=
270 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
271 static const arm_feature_set fpu_vfp_ext_v3
=
272 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
273 static const arm_feature_set fpu_vfp_ext_d32
=
274 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
275 static const arm_feature_set fpu_neon_ext_v1
=
276 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
277 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
278 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
280 static const arm_feature_set fpu_vfp_fp16
=
281 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
282 static const arm_feature_set fpu_neon_ext_fma
=
283 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
285 static const arm_feature_set fpu_vfp_ext_fma
=
286 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
287 static const arm_feature_set fpu_vfp_ext_armv8
=
288 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
289 static const arm_feature_set fpu_vfp_ext_armv8xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
291 static const arm_feature_set fpu_neon_ext_armv8
=
292 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
293 static const arm_feature_set fpu_crypto_ext_armv8
=
294 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
295 static const arm_feature_set crc_ext_armv8
=
296 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
297 static const arm_feature_set fpu_neon_ext_v8_1
=
298 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
299 static const arm_feature_set fpu_neon_ext_dotprod
=
300 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
302 static int mfloat_abi_opt
= -1;
303 /* Record user cpu selection for object attributes. */
304 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
305 /* Must be long enough to hold any of the names in arm_cpus. */
306 static char selected_cpu_name
[20];
308 extern FLONUM_TYPE generic_floating_point_number
;
310 /* Return if no cpu was selected on command-line. */
312 no_cpu_selected (void)
314 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
319 static int meabi_flags
= EABI_DEFAULT
;
321 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
324 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
329 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
334 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
335 symbolS
* GOT_symbol
;
338 /* 0: assemble for ARM,
339 1: assemble for Thumb,
340 2: assemble for Thumb even though target CPU does not support thumb
342 static int thumb_mode
= 0;
343 /* A value distinct from the possible values for thumb_mode that we
344 can use to record whether thumb_mode has been copied into the
345 tc_frag_data field of a frag. */
346 #define MODE_RECORDED (1 << 4)
348 /* Specifies the intrinsic IT insn behavior mode. */
349 enum implicit_it_mode
351 IMPLICIT_IT_MODE_NEVER
= 0x00,
352 IMPLICIT_IT_MODE_ARM
= 0x01,
353 IMPLICIT_IT_MODE_THUMB
= 0x02,
354 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
356 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
358 /* If unified_syntax is true, we are processing the new unified
359 ARM/Thumb syntax. Important differences from the old ARM mode:
361 - Immediate operands do not require a # prefix.
362 - Conditional affixes always appear at the end of the
363 instruction. (For backward compatibility, those instructions
364 that formerly had them in the middle, continue to accept them
366 - The IT instruction may appear, and if it does is validated
367 against subsequent conditional affixes. It does not generate
370 Important differences from the old Thumb mode:
372 - Immediate operands do not require a # prefix.
373 - Most of the V6T2 instructions are only available in unified mode.
374 - The .N and .W suffixes are recognized and honored (it is an error
375 if they cannot be honored).
376 - All instructions set the flags if and only if they have an 's' affix.
377 - Conditional affixes may be used. They are validated against
378 preceding IT instructions. Unlike ARM mode, you cannot use a
379 conditional affix except in the scope of an IT instruction. */
381 static bfd_boolean unified_syntax
= FALSE
;
383 /* An immediate operand can start with #, and ld*, st*, pld operands
384 can contain [ and ]. We need to tell APP not to elide whitespace
385 before a [, which can appear as the first operand for pld.
386 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
387 const char arm_symbol_chars
[] = "#[]{}";
402 enum neon_el_type type
;
406 #define NEON_MAX_TYPE_ELS 4
410 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
414 enum it_instruction_type
419 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
420 if inside, should be the last one. */
421 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
422 i.e. BKPT and NOP. */
423 IT_INSN
/* The IT insn has been parsed. */
426 /* The maximum number of operands we need. */
427 #define ARM_IT_MAX_OPERANDS 6
432 unsigned long instruction
;
436 /* "uncond_value" is set to the value in place of the conditional field in
437 unconditional versions of the instruction, or -1 if nothing is
440 struct neon_type vectype
;
441 /* This does not indicate an actual NEON instruction, only that
442 the mnemonic accepts neon-style type suffixes. */
444 /* Set to the opcode if the instruction needs relaxation.
445 Zero if the instruction is not relaxed. */
449 bfd_reloc_code_real_type type
;
454 enum it_instruction_type it_insn_type
;
460 struct neon_type_el vectype
;
461 unsigned present
: 1; /* Operand present. */
462 unsigned isreg
: 1; /* Operand was a register. */
463 unsigned immisreg
: 1; /* .imm field is a second register. */
464 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
465 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
466 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
467 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
468 instructions. This allows us to disambiguate ARM <-> vector insns. */
469 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
470 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
471 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
472 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
473 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
474 unsigned writeback
: 1; /* Operand has trailing ! */
475 unsigned preind
: 1; /* Preindexed address. */
476 unsigned postind
: 1; /* Postindexed address. */
477 unsigned negative
: 1; /* Index register was negated. */
478 unsigned shifted
: 1; /* Shift applied to operation. */
479 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
480 } operands
[ARM_IT_MAX_OPERANDS
];
483 static struct arm_it inst
;
485 #define NUM_FLOAT_VALS 8
487 const char * fp_const
[] =
489 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
492 /* Number of littlenums required to hold an extended precision number. */
493 #define MAX_LITTLENUMS 6
495 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
505 #define CP_T_X 0x00008000
506 #define CP_T_Y 0x00400000
508 #define CONDS_BIT 0x00100000
509 #define LOAD_BIT 0x00100000
511 #define DOUBLE_LOAD_FLAG 0x00000001
515 const char * template_name
;
519 #define COND_ALWAYS 0xE
523 const char * template_name
;
527 struct asm_barrier_opt
529 const char * template_name
;
531 const arm_feature_set arch
;
534 /* The bit that distinguishes CPSR and SPSR. */
535 #define SPSR_BIT (1 << 22)
537 /* The individual PSR flag bits. */
538 #define PSR_c (1 << 16)
539 #define PSR_x (1 << 17)
540 #define PSR_s (1 << 18)
541 #define PSR_f (1 << 19)
546 bfd_reloc_code_real_type reloc
;
551 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
552 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
557 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
560 /* Bits for DEFINED field in neon_typed_alias. */
561 #define NTA_HASTYPE 1
562 #define NTA_HASINDEX 2
564 struct neon_typed_alias
566 unsigned char defined
;
568 struct neon_type_el eltype
;
571 /* ARM register categories. This includes coprocessor numbers and various
572 architecture extensions' registers. */
600 /* Structure for a hash table entry for a register.
601 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
602 information which states whether a vector type or index is specified (for a
603 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
609 unsigned char builtin
;
610 struct neon_typed_alias
* neon
;
613 /* Diagnostics used when we don't get a register of the expected type. */
614 const char * const reg_expected_msgs
[] =
616 N_("ARM register expected"),
617 N_("bad or missing co-processor number"),
618 N_("co-processor register expected"),
619 N_("FPA register expected"),
620 N_("VFP single precision register expected"),
621 N_("VFP/Neon double precision register expected"),
622 N_("Neon quad precision register expected"),
623 N_("VFP single or double precision register expected"),
624 N_("Neon double or quad precision register expected"),
625 N_("Neon single or double precision register expected"),
626 N_("VFP single, double or Neon quad precision register expected"),
627 N_("VFP system register expected"),
628 N_("Maverick MVF register expected"),
629 N_("Maverick MVD register expected"),
630 N_("Maverick MVFX register expected"),
631 N_("Maverick MVDX register expected"),
632 N_("Maverick MVAX register expected"),
633 N_("Maverick DSPSC register expected"),
634 N_("iWMMXt data register expected"),
635 N_("iWMMXt control register expected"),
636 N_("iWMMXt scalar register expected"),
637 N_("XScale accumulator register expected"),
640 /* Some well known registers that we refer to directly elsewhere. */
646 /* ARM instructions take 4bytes in the object file, Thumb instructions
652 /* Basic string to match. */
653 const char * template_name
;
655 /* Parameters to instruction. */
656 unsigned int operands
[8];
658 /* Conditional tag - see opcode_lookup. */
659 unsigned int tag
: 4;
661 /* Basic instruction code. */
662 unsigned int avalue
: 28;
664 /* Thumb-format instruction code. */
667 /* Which architecture variant provides this instruction. */
668 const arm_feature_set
* avariant
;
669 const arm_feature_set
* tvariant
;
671 /* Function to call to encode instruction in ARM format. */
672 void (* aencode
) (void);
674 /* Function to call to encode instruction in Thumb format. */
675 void (* tencode
) (void);
678 /* Defines for various bits that we will want to toggle. */
679 #define INST_IMMEDIATE 0x02000000
680 #define OFFSET_REG 0x02000000
681 #define HWOFFSET_IMM 0x00400000
682 #define SHIFT_BY_REG 0x00000010
683 #define PRE_INDEX 0x01000000
684 #define INDEX_UP 0x00800000
685 #define WRITE_BACK 0x00200000
686 #define LDM_TYPE_2_OR_3 0x00400000
687 #define CPSI_MMOD 0x00020000
689 #define LITERAL_MASK 0xf000f000
690 #define OPCODE_MASK 0xfe1fffff
691 #define V4_STR_BIT 0x00000020
692 #define VLDR_VMOV_SAME 0x0040f000
694 #define T2_SUBS_PC_LR 0xf3de8f00
696 #define DATA_OP_SHIFT 21
697 #define SBIT_SHIFT 20
699 #define T2_OPCODE_MASK 0xfe1fffff
700 #define T2_DATA_OP_SHIFT 21
701 #define T2_SBIT_SHIFT 20
703 #define A_COND_MASK 0xf0000000
704 #define A_PUSH_POP_OP_MASK 0x0fff0000
706 /* Opcodes for pushing/poping registers to/from the stack. */
707 #define A1_OPCODE_PUSH 0x092d0000
708 #define A2_OPCODE_PUSH 0x052d0004
709 #define A2_OPCODE_POP 0x049d0004
711 /* Codes to distinguish the arithmetic instructions. */
722 #define OPCODE_CMP 10
723 #define OPCODE_CMN 11
724 #define OPCODE_ORR 12
725 #define OPCODE_MOV 13
726 #define OPCODE_BIC 14
727 #define OPCODE_MVN 15
729 #define T2_OPCODE_AND 0
730 #define T2_OPCODE_BIC 1
731 #define T2_OPCODE_ORR 2
732 #define T2_OPCODE_ORN 3
733 #define T2_OPCODE_EOR 4
734 #define T2_OPCODE_ADD 8
735 #define T2_OPCODE_ADC 10
736 #define T2_OPCODE_SBC 11
737 #define T2_OPCODE_SUB 13
738 #define T2_OPCODE_RSB 14
740 #define T_OPCODE_MUL 0x4340
741 #define T_OPCODE_TST 0x4200
742 #define T_OPCODE_CMN 0x42c0
743 #define T_OPCODE_NEG 0x4240
744 #define T_OPCODE_MVN 0x43c0
746 #define T_OPCODE_ADD_R3 0x1800
747 #define T_OPCODE_SUB_R3 0x1a00
748 #define T_OPCODE_ADD_HI 0x4400
749 #define T_OPCODE_ADD_ST 0xb000
750 #define T_OPCODE_SUB_ST 0xb080
751 #define T_OPCODE_ADD_SP 0xa800
752 #define T_OPCODE_ADD_PC 0xa000
753 #define T_OPCODE_ADD_I8 0x3000
754 #define T_OPCODE_SUB_I8 0x3800
755 #define T_OPCODE_ADD_I3 0x1c00
756 #define T_OPCODE_SUB_I3 0x1e00
758 #define T_OPCODE_ASR_R 0x4100
759 #define T_OPCODE_LSL_R 0x4080
760 #define T_OPCODE_LSR_R 0x40c0
761 #define T_OPCODE_ROR_R 0x41c0
762 #define T_OPCODE_ASR_I 0x1000
763 #define T_OPCODE_LSL_I 0x0000
764 #define T_OPCODE_LSR_I 0x0800
766 #define T_OPCODE_MOV_I8 0x2000
767 #define T_OPCODE_CMP_I8 0x2800
768 #define T_OPCODE_CMP_LR 0x4280
769 #define T_OPCODE_MOV_HR 0x4600
770 #define T_OPCODE_CMP_HR 0x4500
772 #define T_OPCODE_LDR_PC 0x4800
773 #define T_OPCODE_LDR_SP 0x9800
774 #define T_OPCODE_STR_SP 0x9000
775 #define T_OPCODE_LDR_IW 0x6800
776 #define T_OPCODE_STR_IW 0x6000
777 #define T_OPCODE_LDR_IH 0x8800
778 #define T_OPCODE_STR_IH 0x8000
779 #define T_OPCODE_LDR_IB 0x7800
780 #define T_OPCODE_STR_IB 0x7000
781 #define T_OPCODE_LDR_RW 0x5800
782 #define T_OPCODE_STR_RW 0x5000
783 #define T_OPCODE_LDR_RH 0x5a00
784 #define T_OPCODE_STR_RH 0x5200
785 #define T_OPCODE_LDR_RB 0x5c00
786 #define T_OPCODE_STR_RB 0x5400
788 #define T_OPCODE_PUSH 0xb400
789 #define T_OPCODE_POP 0xbc00
791 #define T_OPCODE_BRANCH 0xe000
793 #define THUMB_SIZE 2 /* Size of thumb instruction. */
794 #define THUMB_PP_PC_LR 0x0100
795 #define THUMB_LOAD_BIT 0x0800
796 #define THUMB2_LOAD_BIT 0x00100000
798 #define BAD_ARGS _("bad arguments to instruction")
799 #define BAD_SP _("r13 not allowed here")
800 #define BAD_PC _("r15 not allowed here")
801 #define BAD_COND _("instruction cannot be conditional")
802 #define BAD_OVERLAP _("registers may not be the same")
803 #define BAD_HIREG _("lo register required")
804 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
805 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
806 #define BAD_BRANCH _("branch must be last instruction in IT block")
807 #define BAD_NOT_IT _("instruction not allowed in IT block")
808 #define BAD_FPU _("selected FPU does not support instruction")
809 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
810 #define BAD_IT_COND _("incorrect condition in IT block")
811 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
812 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
813 #define BAD_PC_ADDRESSING \
814 _("cannot use register index with PC-relative addressing")
815 #define BAD_PC_WRITEBACK \
816 _("cannot use writeback with PC-relative addressing")
817 #define BAD_RANGE _("branch out of range")
818 #define BAD_FP16 _("selected processor does not support fp16 instruction")
819 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
820 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
822 static struct hash_control
* arm_ops_hsh
;
823 static struct hash_control
* arm_cond_hsh
;
824 static struct hash_control
* arm_shift_hsh
;
825 static struct hash_control
* arm_psr_hsh
;
826 static struct hash_control
* arm_v7m_psr_hsh
;
827 static struct hash_control
* arm_reg_hsh
;
828 static struct hash_control
* arm_reloc_hsh
;
829 static struct hash_control
* arm_barrier_opt_hsh
;
831 /* Stuff needed to resolve the label ambiguity
840 symbolS
* last_label_seen
;
841 static int label_is_thumb_function_name
= FALSE
;
843 /* Literal pool structure. Held on a per-section
844 and per-sub-section basis. */
846 #define MAX_LITERAL_POOL_SIZE 1024
847 typedef struct literal_pool
849 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
850 unsigned int next_free_entry
;
856 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
858 struct literal_pool
* next
;
859 unsigned int alignment
;
862 /* Pointer to a linked list of literal pools. */
863 literal_pool
* list_of_pools
= NULL
;
865 typedef enum asmfunc_states
868 WAITING_ASMFUNC_NAME
,
872 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
875 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
877 static struct current_it now_it
;
881 now_it_compatible (int cond
)
883 return (cond
& ~1) == (now_it
.cc
& ~1);
887 conditional_insn (void)
889 return inst
.cond
!= COND_ALWAYS
;
892 static int in_it_block (void);
894 static int handle_it_state (void);
896 static void force_automatic_it_block_close (void);
898 static void it_fsm_post_encode (void);
900 #define set_it_insn_type(type) \
903 inst.it_insn_type = type; \
904 if (handle_it_state () == FAIL) \
909 #define set_it_insn_type_nonvoid(type, failret) \
912 inst.it_insn_type = type; \
913 if (handle_it_state () == FAIL) \
918 #define set_it_insn_type_last() \
921 if (inst.cond == COND_ALWAYS) \
922 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
924 set_it_insn_type (INSIDE_IT_LAST_INSN); \
930 /* This array holds the chars that always start a comment. If the
931 pre-processor is disabled, these aren't very useful. */
932 char arm_comment_chars
[] = "@";
934 /* This array holds the chars that only start a comment at the beginning of
935 a line. If the line seems to have the form '# 123 filename'
936 .line and .file directives will appear in the pre-processed output. */
937 /* Note that input_file.c hand checks for '#' at the beginning of the
938 first line of the input file. This is because the compiler outputs
939 #NO_APP at the beginning of its output. */
940 /* Also note that comments like this one will always work. */
941 const char line_comment_chars
[] = "#";
943 char arm_line_separator_chars
[] = ";";
945 /* Chars that can be used to separate mant
946 from exp in floating point numbers. */
947 const char EXP_CHARS
[] = "eE";
949 /* Chars that mean this number is a floating point constant. */
953 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
955 /* Prefix characters that indicate the start of an immediate
957 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
959 /* Separator character handling. */
961 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
964 skip_past_char (char ** str
, char c
)
966 /* PR gas/14987: Allow for whitespace before the expected character. */
967 skip_whitespace (*str
);
978 #define skip_past_comma(str) skip_past_char (str, ',')
980 /* Arithmetic expressions (possibly involving symbols). */
982 /* Return TRUE if anything in the expression is a bignum. */
985 walk_no_bignums (symbolS
* sp
)
987 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
990 if (symbol_get_value_expression (sp
)->X_add_symbol
)
992 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
993 || (symbol_get_value_expression (sp
)->X_op_symbol
994 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1000 static bfd_boolean in_my_get_expression
= FALSE
;
1002 /* Third argument to my_get_expression. */
1003 #define GE_NO_PREFIX 0
1004 #define GE_IMM_PREFIX 1
1005 #define GE_OPT_PREFIX 2
1006 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1007 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1008 #define GE_OPT_PREFIX_BIG 3
1011 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1016 /* In unified syntax, all prefixes are optional. */
1018 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1021 switch (prefix_mode
)
1023 case GE_NO_PREFIX
: break;
1025 if (!is_immediate_prefix (**str
))
1027 inst
.error
= _("immediate expression requires a # prefix");
1033 case GE_OPT_PREFIX_BIG
:
1034 if (is_immediate_prefix (**str
))
1041 memset (ep
, 0, sizeof (expressionS
));
1043 save_in
= input_line_pointer
;
1044 input_line_pointer
= *str
;
1045 in_my_get_expression
= TRUE
;
1046 seg
= expression (ep
);
1047 in_my_get_expression
= FALSE
;
1049 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1051 /* We found a bad or missing expression in md_operand(). */
1052 *str
= input_line_pointer
;
1053 input_line_pointer
= save_in
;
1054 if (inst
.error
== NULL
)
1055 inst
.error
= (ep
->X_op
== O_absent
1056 ? _("missing expression") :_("bad expression"));
1061 if (seg
!= absolute_section
1062 && seg
!= text_section
1063 && seg
!= data_section
1064 && seg
!= bss_section
1065 && seg
!= undefined_section
)
1067 inst
.error
= _("bad segment");
1068 *str
= input_line_pointer
;
1069 input_line_pointer
= save_in
;
1076 /* Get rid of any bignums now, so that we don't generate an error for which
1077 we can't establish a line number later on. Big numbers are never valid
1078 in instructions, which is where this routine is always called. */
1079 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1080 && (ep
->X_op
== O_big
1081 || (ep
->X_add_symbol
1082 && (walk_no_bignums (ep
->X_add_symbol
)
1084 && walk_no_bignums (ep
->X_op_symbol
))))))
1086 inst
.error
= _("invalid constant");
1087 *str
= input_line_pointer
;
1088 input_line_pointer
= save_in
;
1092 *str
= input_line_pointer
;
1093 input_line_pointer
= save_in
;
1097 /* Turn a string in input_line_pointer into a floating point constant
1098 of type TYPE, and store the appropriate bytes in *LITP. The number
1099 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1100 returned, or NULL on OK.
1102 Note that fp constants aren't represent in the normal way on the ARM.
1103 In big endian mode, things are as expected. However, in little endian
1104 mode fp constants are big-endian word-wise, and little-endian byte-wise
1105 within the words. For example, (double) 1.1 in big endian mode is
1106 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1107 the byte sequence 99 99 f1 3f 9a 99 99 99.
1109 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1112 md_atof (int type
, char * litP
, int * sizeP
)
1115 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1147 return _("Unrecognized or unsupported floating point constant");
1150 t
= atof_ieee (input_line_pointer
, type
, words
);
1152 input_line_pointer
= t
;
1153 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1155 if (target_big_endian
)
1157 for (i
= 0; i
< prec
; i
++)
1159 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1160 litP
+= sizeof (LITTLENUM_TYPE
);
1165 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1166 for (i
= prec
- 1; i
>= 0; i
--)
1168 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1169 litP
+= sizeof (LITTLENUM_TYPE
);
1172 /* For a 4 byte float the order of elements in `words' is 1 0.
1173 For an 8 byte float the order is 1 0 3 2. */
1174 for (i
= 0; i
< prec
; i
+= 2)
1176 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1177 sizeof (LITTLENUM_TYPE
));
1178 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1179 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1180 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1187 /* We handle all bad expressions here, so that we can report the faulty
1188 instruction in the error message. */
1191 md_operand (expressionS
* exp
)
1193 if (in_my_get_expression
)
1194 exp
->X_op
= O_illegal
;
1197 /* Immediate values. */
1200 /* Generic immediate-value read function for use in directives.
1201 Accepts anything that 'expression' can fold to a constant.
1202 *val receives the number. */
1205 immediate_for_directive (int *val
)
1208 exp
.X_op
= O_illegal
;
1210 if (is_immediate_prefix (*input_line_pointer
))
1212 input_line_pointer
++;
1216 if (exp
.X_op
!= O_constant
)
1218 as_bad (_("expected #constant"));
1219 ignore_rest_of_line ();
1222 *val
= exp
.X_add_number
;
1227 /* Register parsing. */
1229 /* Generic register parser. CCP points to what should be the
1230 beginning of a register name. If it is indeed a valid register
1231 name, advance CCP over it and return the reg_entry structure;
1232 otherwise return NULL. Does not issue diagnostics. */
1234 static struct reg_entry
*
1235 arm_reg_parse_multi (char **ccp
)
1239 struct reg_entry
*reg
;
1241 skip_whitespace (start
);
1243 #ifdef REGISTER_PREFIX
1244 if (*start
!= REGISTER_PREFIX
)
1248 #ifdef OPTIONAL_REGISTER_PREFIX
1249 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1254 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1259 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1261 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1271 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1272 enum arm_reg_type type
)
1274 /* Alternative syntaxes are accepted for a few register classes. */
1281 /* Generic coprocessor register names are allowed for these. */
1282 if (reg
&& reg
->type
== REG_TYPE_CN
)
1287 /* For backward compatibility, a bare number is valid here. */
1289 unsigned long processor
= strtoul (start
, ccp
, 10);
1290 if (*ccp
!= start
&& processor
<= 15)
1295 case REG_TYPE_MMXWC
:
1296 /* WC includes WCG. ??? I'm not sure this is true for all
1297 instructions that take WC registers. */
1298 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1309 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1310 return value is the register number or FAIL. */
1313 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1316 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1319 /* Do not allow a scalar (reg+index) to parse as a register. */
1320 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1323 if (reg
&& reg
->type
== type
)
1326 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1333 /* Parse a Neon type specifier. *STR should point at the leading '.'
1334 character. Does no verification at this stage that the type fits the opcode
1341 Can all be legally parsed by this function.
1343 Fills in neon_type struct pointer with parsed information, and updates STR
1344 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1345 type, FAIL if not. */
1348 parse_neon_type (struct neon_type
*type
, char **str
)
1355 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1357 enum neon_el_type thistype
= NT_untyped
;
1358 unsigned thissize
= -1u;
1365 /* Just a size without an explicit type. */
1369 switch (TOLOWER (*ptr
))
1371 case 'i': thistype
= NT_integer
; break;
1372 case 'f': thistype
= NT_float
; break;
1373 case 'p': thistype
= NT_poly
; break;
1374 case 's': thistype
= NT_signed
; break;
1375 case 'u': thistype
= NT_unsigned
; break;
1377 thistype
= NT_float
;
1382 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1388 /* .f is an abbreviation for .f32. */
1389 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1394 thissize
= strtoul (ptr
, &ptr
, 10);
1396 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1399 as_bad (_("bad size %d in type specifier"), thissize
);
1407 type
->el
[type
->elems
].type
= thistype
;
1408 type
->el
[type
->elems
].size
= thissize
;
1413 /* Empty/missing type is not a successful parse. */
1414 if (type
->elems
== 0)
1422 /* Errors may be set multiple times during parsing or bit encoding
1423 (particularly in the Neon bits), but usually the earliest error which is set
1424 will be the most meaningful. Avoid overwriting it with later (cascading)
1425 errors by calling this function. */
1428 first_error (const char *err
)
1434 /* Parse a single type, e.g. ".s32", leading period included. */
1436 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1439 struct neon_type optype
;
1443 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1445 if (optype
.elems
== 1)
1446 *vectype
= optype
.el
[0];
1449 first_error (_("only one type should be specified for operand"));
1455 first_error (_("vector type expected"));
1467 /* Special meanings for indices (which have a range of 0-7), which will fit into
1470 #define NEON_ALL_LANES 15
1471 #define NEON_INTERLEAVE_LANES 14
1473 /* Parse either a register or a scalar, with an optional type. Return the
1474 register number, and optionally fill in the actual type of the register
1475 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1476 type/index information in *TYPEINFO. */
1479 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1480 enum arm_reg_type
*rtype
,
1481 struct neon_typed_alias
*typeinfo
)
1484 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1485 struct neon_typed_alias atype
;
1486 struct neon_type_el parsetype
;
1490 atype
.eltype
.type
= NT_invtype
;
1491 atype
.eltype
.size
= -1;
1493 /* Try alternate syntax for some types of register. Note these are mutually
1494 exclusive with the Neon syntax extensions. */
1497 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1505 /* Undo polymorphism when a set of register types may be accepted. */
1506 if ((type
== REG_TYPE_NDQ
1507 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1508 || (type
== REG_TYPE_VFSD
1509 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1510 || (type
== REG_TYPE_NSDQ
1511 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1512 || reg
->type
== REG_TYPE_NQ
))
1513 || (type
== REG_TYPE_NSD
1514 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1515 || (type
== REG_TYPE_MMXWC
1516 && (reg
->type
== REG_TYPE_MMXWCG
)))
1517 type
= (enum arm_reg_type
) reg
->type
;
1519 if (type
!= reg
->type
)
1525 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1527 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1529 first_error (_("can't redefine type for operand"));
1532 atype
.defined
|= NTA_HASTYPE
;
1533 atype
.eltype
= parsetype
;
1536 if (skip_past_char (&str
, '[') == SUCCESS
)
1538 if (type
!= REG_TYPE_VFD
1539 && !(type
== REG_TYPE_VFS
1540 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
)))
1542 first_error (_("only D registers may be indexed"));
1546 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1548 first_error (_("can't change index for operand"));
1552 atype
.defined
|= NTA_HASINDEX
;
1554 if (skip_past_char (&str
, ']') == SUCCESS
)
1555 atype
.index
= NEON_ALL_LANES
;
1560 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1562 if (exp
.X_op
!= O_constant
)
1564 first_error (_("constant expression required"));
1568 if (skip_past_char (&str
, ']') == FAIL
)
1571 atype
.index
= exp
.X_add_number
;
1586 /* Like arm_reg_parse, but allow allow the following extra features:
1587 - If RTYPE is non-zero, return the (possibly restricted) type of the
1588 register (e.g. Neon double or quad reg when either has been requested).
1589 - If this is a Neon vector type with additional type information, fill
1590 in the struct pointed to by VECTYPE (if non-NULL).
1591 This function will fault on encountering a scalar. */
1594 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1595 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1597 struct neon_typed_alias atype
;
1599 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1604 /* Do not allow regname(... to parse as a register. */
1608 /* Do not allow a scalar (reg+index) to parse as a register. */
1609 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1611 first_error (_("register operand expected, but got scalar"));
1616 *vectype
= atype
.eltype
;
1623 #define NEON_SCALAR_REG(X) ((X) >> 4)
1624 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1626 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1627 have enough information to be able to do a good job bounds-checking. So, we
1628 just do easy checks here, and do further checks later. */
1631 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1635 struct neon_typed_alias atype
;
1636 enum arm_reg_type reg_type
= REG_TYPE_VFD
;
1639 reg_type
= REG_TYPE_VFS
;
1641 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1643 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1646 if (atype
.index
== NEON_ALL_LANES
)
1648 first_error (_("scalar must have an index"));
1651 else if (atype
.index
>= 64 / elsize
)
1653 first_error (_("scalar index out of range"));
1658 *type
= atype
.eltype
;
1662 return reg
* 16 + atype
.index
;
1665 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1668 parse_reg_list (char ** strp
)
1670 char * str
= * strp
;
1674 /* We come back here if we get ranges concatenated by '+' or '|'. */
1677 skip_whitespace (str
);
1691 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1693 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1703 first_error (_("bad range in register list"));
1707 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1709 if (range
& (1 << i
))
1711 (_("Warning: duplicated register (r%d) in register list"),
1719 if (range
& (1 << reg
))
1720 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1722 else if (reg
<= cur_reg
)
1723 as_tsktsk (_("Warning: register range not in ascending order"));
1728 while (skip_past_comma (&str
) != FAIL
1729 || (in_range
= 1, *str
++ == '-'));
1732 if (skip_past_char (&str
, '}') == FAIL
)
1734 first_error (_("missing `}'"));
1742 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1745 if (exp
.X_op
== O_constant
)
1747 if (exp
.X_add_number
1748 != (exp
.X_add_number
& 0x0000ffff))
1750 inst
.error
= _("invalid register mask");
1754 if ((range
& exp
.X_add_number
) != 0)
1756 int regno
= range
& exp
.X_add_number
;
1759 regno
= (1 << regno
) - 1;
1761 (_("Warning: duplicated register (r%d) in register list"),
1765 range
|= exp
.X_add_number
;
1769 if (inst
.reloc
.type
!= 0)
1771 inst
.error
= _("expression too complex");
1775 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1776 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1777 inst
.reloc
.pc_rel
= 0;
1781 if (*str
== '|' || *str
== '+')
1787 while (another_range
);
1793 /* Types of registers in a list. */
1802 /* Parse a VFP register list. If the string is invalid return FAIL.
1803 Otherwise return the number of registers, and set PBASE to the first
1804 register. Parses registers of type ETYPE.
1805 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1806 - Q registers can be used to specify pairs of D registers
1807 - { } can be omitted from around a singleton register list
1808 FIXME: This is not implemented, as it would require backtracking in
1811 This could be done (the meaning isn't really ambiguous), but doesn't
1812 fit in well with the current parsing framework.
1813 - 32 D registers may be used (also true for VFPv3).
1814 FIXME: Types are ignored in these register lists, which is probably a
1818 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1823 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1827 unsigned long mask
= 0;
1830 if (skip_past_char (&str
, '{') == FAIL
)
1832 inst
.error
= _("expecting {");
1839 regtype
= REG_TYPE_VFS
;
1844 regtype
= REG_TYPE_VFD
;
1847 case REGLIST_NEON_D
:
1848 regtype
= REG_TYPE_NDQ
;
1852 if (etype
!= REGLIST_VFP_S
)
1854 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1855 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1859 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1862 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1869 base_reg
= max_regs
;
1873 int setmask
= 1, addregs
= 1;
1875 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1877 if (new_base
== FAIL
)
1879 first_error (_(reg_expected_msgs
[regtype
]));
1883 if (new_base
>= max_regs
)
1885 first_error (_("register out of range in list"));
1889 /* Note: a value of 2 * n is returned for the register Q<n>. */
1890 if (regtype
== REG_TYPE_NQ
)
1896 if (new_base
< base_reg
)
1897 base_reg
= new_base
;
1899 if (mask
& (setmask
<< new_base
))
1901 first_error (_("invalid register list"));
1905 if ((mask
>> new_base
) != 0 && ! warned
)
1907 as_tsktsk (_("register list not in ascending order"));
1911 mask
|= setmask
<< new_base
;
1914 if (*str
== '-') /* We have the start of a range expression */
1920 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1923 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1927 if (high_range
>= max_regs
)
1929 first_error (_("register out of range in list"));
1933 if (regtype
== REG_TYPE_NQ
)
1934 high_range
= high_range
+ 1;
1936 if (high_range
<= new_base
)
1938 inst
.error
= _("register range not in ascending order");
1942 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1944 if (mask
& (setmask
<< new_base
))
1946 inst
.error
= _("invalid register list");
1950 mask
|= setmask
<< new_base
;
1955 while (skip_past_comma (&str
) != FAIL
);
1959 /* Sanity check -- should have raised a parse error above. */
1960 if (count
== 0 || count
> max_regs
)
1965 /* Final test -- the registers must be consecutive. */
1967 for (i
= 0; i
< count
; i
++)
1969 if ((mask
& (1u << i
)) == 0)
1971 inst
.error
= _("non-contiguous register range");
1981 /* True if two alias types are the same. */
1984 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1992 if (a
->defined
!= b
->defined
)
1995 if ((a
->defined
& NTA_HASTYPE
) != 0
1996 && (a
->eltype
.type
!= b
->eltype
.type
1997 || a
->eltype
.size
!= b
->eltype
.size
))
2000 if ((a
->defined
& NTA_HASINDEX
) != 0
2001 && (a
->index
!= b
->index
))
2007 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2008 The base register is put in *PBASE.
2009 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2011 The register stride (minus one) is put in bit 4 of the return value.
2012 Bits [6:5] encode the list length (minus one).
2013 The type of the list elements is put in *ELTYPE, if non-NULL. */
2015 #define NEON_LANE(X) ((X) & 0xf)
2016 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2017 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2020 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2021 struct neon_type_el
*eltype
)
2028 int leading_brace
= 0;
2029 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2030 const char *const incr_error
= _("register stride must be 1 or 2");
2031 const char *const type_error
= _("mismatched element/structure types in list");
2032 struct neon_typed_alias firsttype
;
2033 firsttype
.defined
= 0;
2034 firsttype
.eltype
.type
= NT_invtype
;
2035 firsttype
.eltype
.size
= -1;
2036 firsttype
.index
= -1;
2038 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2043 struct neon_typed_alias atype
;
2044 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2048 first_error (_(reg_expected_msgs
[rtype
]));
2055 if (rtype
== REG_TYPE_NQ
)
2061 else if (reg_incr
== -1)
2063 reg_incr
= getreg
- base_reg
;
2064 if (reg_incr
< 1 || reg_incr
> 2)
2066 first_error (_(incr_error
));
2070 else if (getreg
!= base_reg
+ reg_incr
* count
)
2072 first_error (_(incr_error
));
2076 if (! neon_alias_types_same (&atype
, &firsttype
))
2078 first_error (_(type_error
));
2082 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2086 struct neon_typed_alias htype
;
2087 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2089 lane
= NEON_INTERLEAVE_LANES
;
2090 else if (lane
!= NEON_INTERLEAVE_LANES
)
2092 first_error (_(type_error
));
2097 else if (reg_incr
!= 1)
2099 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2103 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2106 first_error (_(reg_expected_msgs
[rtype
]));
2109 if (! neon_alias_types_same (&htype
, &firsttype
))
2111 first_error (_(type_error
));
2114 count
+= hireg
+ dregs
- getreg
;
2118 /* If we're using Q registers, we can't use [] or [n] syntax. */
2119 if (rtype
== REG_TYPE_NQ
)
2125 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2129 else if (lane
!= atype
.index
)
2131 first_error (_(type_error
));
2135 else if (lane
== -1)
2136 lane
= NEON_INTERLEAVE_LANES
;
2137 else if (lane
!= NEON_INTERLEAVE_LANES
)
2139 first_error (_(type_error
));
2144 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2146 /* No lane set by [x]. We must be interleaving structures. */
2148 lane
= NEON_INTERLEAVE_LANES
;
2151 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2152 || (count
> 1 && reg_incr
== -1))
2154 first_error (_("error parsing element/structure list"));
2158 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2160 first_error (_("expected }"));
2168 *eltype
= firsttype
.eltype
;
2173 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2176 /* Parse an explicit relocation suffix on an expression. This is
2177 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2178 arm_reloc_hsh contains no entries, so this function can only
2179 succeed if there is no () after the word. Returns -1 on error,
2180 BFD_RELOC_UNUSED if there wasn't any suffix. */
2183 parse_reloc (char **str
)
2185 struct reloc_entry
*r
;
2189 return BFD_RELOC_UNUSED
;
2194 while (*q
&& *q
!= ')' && *q
!= ',')
2199 if ((r
= (struct reloc_entry
*)
2200 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2207 /* Directives: register aliases. */
2209 static struct reg_entry
*
2210 insert_reg_alias (char *str
, unsigned number
, int type
)
2212 struct reg_entry
*new_reg
;
2215 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2217 if (new_reg
->builtin
)
2218 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2220 /* Only warn about a redefinition if it's not defined as the
2222 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2223 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2228 name
= xstrdup (str
);
2229 new_reg
= XNEW (struct reg_entry
);
2231 new_reg
->name
= name
;
2232 new_reg
->number
= number
;
2233 new_reg
->type
= type
;
2234 new_reg
->builtin
= FALSE
;
2235 new_reg
->neon
= NULL
;
2237 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2244 insert_neon_reg_alias (char *str
, int number
, int type
,
2245 struct neon_typed_alias
*atype
)
2247 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2251 first_error (_("attempt to redefine typed alias"));
2257 reg
->neon
= XNEW (struct neon_typed_alias
);
2258 *reg
->neon
= *atype
;
2262 /* Look for the .req directive. This is of the form:
2264 new_register_name .req existing_register_name
2266 If we find one, or if it looks sufficiently like one that we want to
2267 handle any error here, return TRUE. Otherwise return FALSE. */
2270 create_register_alias (char * newname
, char *p
)
2272 struct reg_entry
*old
;
2273 char *oldname
, *nbuf
;
2276 /* The input scrubber ensures that whitespace after the mnemonic is
2277 collapsed to single spaces. */
2279 if (strncmp (oldname
, " .req ", 6) != 0)
2283 if (*oldname
== '\0')
2286 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2289 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2293 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2294 the desired alias name, and p points to its end. If not, then
2295 the desired alias name is in the global original_case_string. */
2296 #ifdef TC_CASE_SENSITIVE
2299 newname
= original_case_string
;
2300 nlen
= strlen (newname
);
2303 nbuf
= xmemdup0 (newname
, nlen
);
2305 /* Create aliases under the new name as stated; an all-lowercase
2306 version of the new name; and an all-uppercase version of the new
2308 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2310 for (p
= nbuf
; *p
; p
++)
2313 if (strncmp (nbuf
, newname
, nlen
))
2315 /* If this attempt to create an additional alias fails, do not bother
2316 trying to create the all-lower case alias. We will fail and issue
2317 a second, duplicate error message. This situation arises when the
2318 programmer does something like:
2321 The second .req creates the "Foo" alias but then fails to create
2322 the artificial FOO alias because it has already been created by the
2324 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2331 for (p
= nbuf
; *p
; p
++)
2334 if (strncmp (nbuf
, newname
, nlen
))
2335 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2342 /* Create a Neon typed/indexed register alias using directives, e.g.:
2347 These typed registers can be used instead of the types specified after the
2348 Neon mnemonic, so long as all operands given have types. Types can also be
2349 specified directly, e.g.:
2350 vadd d0.s32, d1.s32, d2.s32 */
2353 create_neon_reg_alias (char *newname
, char *p
)
2355 enum arm_reg_type basetype
;
2356 struct reg_entry
*basereg
;
2357 struct reg_entry mybasereg
;
2358 struct neon_type ntype
;
2359 struct neon_typed_alias typeinfo
;
2360 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2363 typeinfo
.defined
= 0;
2364 typeinfo
.eltype
.type
= NT_invtype
;
2365 typeinfo
.eltype
.size
= -1;
2366 typeinfo
.index
= -1;
2370 if (strncmp (p
, " .dn ", 5) == 0)
2371 basetype
= REG_TYPE_VFD
;
2372 else if (strncmp (p
, " .qn ", 5) == 0)
2373 basetype
= REG_TYPE_NQ
;
2382 basereg
= arm_reg_parse_multi (&p
);
2384 if (basereg
&& basereg
->type
!= basetype
)
2386 as_bad (_("bad type for register"));
2390 if (basereg
== NULL
)
2393 /* Try parsing as an integer. */
2394 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2395 if (exp
.X_op
!= O_constant
)
2397 as_bad (_("expression must be constant"));
2400 basereg
= &mybasereg
;
2401 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2407 typeinfo
= *basereg
->neon
;
2409 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2411 /* We got a type. */
2412 if (typeinfo
.defined
& NTA_HASTYPE
)
2414 as_bad (_("can't redefine the type of a register alias"));
2418 typeinfo
.defined
|= NTA_HASTYPE
;
2419 if (ntype
.elems
!= 1)
2421 as_bad (_("you must specify a single type only"));
2424 typeinfo
.eltype
= ntype
.el
[0];
2427 if (skip_past_char (&p
, '[') == SUCCESS
)
2430 /* We got a scalar index. */
2432 if (typeinfo
.defined
& NTA_HASINDEX
)
2434 as_bad (_("can't redefine the index of a scalar alias"));
2438 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2440 if (exp
.X_op
!= O_constant
)
2442 as_bad (_("scalar index must be constant"));
2446 typeinfo
.defined
|= NTA_HASINDEX
;
2447 typeinfo
.index
= exp
.X_add_number
;
2449 if (skip_past_char (&p
, ']') == FAIL
)
2451 as_bad (_("expecting ]"));
2456 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2457 the desired alias name, and p points to its end. If not, then
2458 the desired alias name is in the global original_case_string. */
2459 #ifdef TC_CASE_SENSITIVE
2460 namelen
= nameend
- newname
;
2462 newname
= original_case_string
;
2463 namelen
= strlen (newname
);
2466 namebuf
= xmemdup0 (newname
, namelen
);
2468 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2469 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2471 /* Insert name in all uppercase. */
2472 for (p
= namebuf
; *p
; p
++)
2475 if (strncmp (namebuf
, newname
, namelen
))
2476 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2477 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2479 /* Insert name in all lowercase. */
2480 for (p
= namebuf
; *p
; p
++)
2483 if (strncmp (namebuf
, newname
, namelen
))
2484 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2485 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2491 /* Should never be called, as .req goes between the alias and the
2492 register name, not at the beginning of the line. */
2495 s_req (int a ATTRIBUTE_UNUSED
)
2497 as_bad (_("invalid syntax for .req directive"));
2501 s_dn (int a ATTRIBUTE_UNUSED
)
2503 as_bad (_("invalid syntax for .dn directive"));
2507 s_qn (int a ATTRIBUTE_UNUSED
)
2509 as_bad (_("invalid syntax for .qn directive"));
2512 /* The .unreq directive deletes an alias which was previously defined
2513 by .req. For example:
2519 s_unreq (int a ATTRIBUTE_UNUSED
)
2524 name
= input_line_pointer
;
2526 while (*input_line_pointer
!= 0
2527 && *input_line_pointer
!= ' '
2528 && *input_line_pointer
!= '\n')
2529 ++input_line_pointer
;
2531 saved_char
= *input_line_pointer
;
2532 *input_line_pointer
= 0;
2535 as_bad (_("invalid syntax for .unreq directive"));
2538 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2542 as_bad (_("unknown register alias '%s'"), name
);
2543 else if (reg
->builtin
)
2544 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2551 hash_delete (arm_reg_hsh
, name
, FALSE
);
2552 free ((char *) reg
->name
);
2557 /* Also locate the all upper case and all lower case versions.
2558 Do not complain if we cannot find one or the other as it
2559 was probably deleted above. */
2561 nbuf
= strdup (name
);
2562 for (p
= nbuf
; *p
; p
++)
2564 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2567 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2568 free ((char *) reg
->name
);
2574 for (p
= nbuf
; *p
; p
++)
2576 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2579 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2580 free ((char *) reg
->name
);
2590 *input_line_pointer
= saved_char
;
2591 demand_empty_rest_of_line ();
2594 /* Directives: Instruction set selection. */
2597 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2598 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2599 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2600 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2602 /* Create a new mapping symbol for the transition to STATE. */
2605 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2608 const char * symname
;
2615 type
= BSF_NO_FLAGS
;
2619 type
= BSF_NO_FLAGS
;
2623 type
= BSF_NO_FLAGS
;
2629 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2630 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2635 THUMB_SET_FUNC (symbolP
, 0);
2636 ARM_SET_THUMB (symbolP
, 0);
2637 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2641 THUMB_SET_FUNC (symbolP
, 1);
2642 ARM_SET_THUMB (symbolP
, 1);
2643 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2651 /* Save the mapping symbols for future reference. Also check that
2652 we do not place two mapping symbols at the same offset within a
2653 frag. We'll handle overlap between frags in
2654 check_mapping_symbols.
2656 If .fill or other data filling directive generates zero sized data,
2657 the mapping symbol for the following code will have the same value
2658 as the one generated for the data filling directive. In this case,
2659 we replace the old symbol with the new one at the same address. */
2662 if (frag
->tc_frag_data
.first_map
!= NULL
)
2664 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2665 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2667 frag
->tc_frag_data
.first_map
= symbolP
;
2669 if (frag
->tc_frag_data
.last_map
!= NULL
)
2671 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2672 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2673 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2675 frag
->tc_frag_data
.last_map
= symbolP
;
2678 /* We must sometimes convert a region marked as code to data during
2679 code alignment, if an odd number of bytes have to be padded. The
2680 code mapping symbol is pushed to an aligned address. */
2683 insert_data_mapping_symbol (enum mstate state
,
2684 valueT value
, fragS
*frag
, offsetT bytes
)
2686 /* If there was already a mapping symbol, remove it. */
2687 if (frag
->tc_frag_data
.last_map
!= NULL
2688 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2690 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2694 know (frag
->tc_frag_data
.first_map
== symp
);
2695 frag
->tc_frag_data
.first_map
= NULL
;
2697 frag
->tc_frag_data
.last_map
= NULL
;
2698 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2701 make_mapping_symbol (MAP_DATA
, value
, frag
);
2702 make_mapping_symbol (state
, value
+ bytes
, frag
);
2705 static void mapping_state_2 (enum mstate state
, int max_chars
);
2707 /* Set the mapping state to STATE. Only call this when about to
2708 emit some STATE bytes to the file. */
2710 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2712 mapping_state (enum mstate state
)
2714 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2716 if (mapstate
== state
)
2717 /* The mapping symbol has already been emitted.
2718 There is nothing else to do. */
2721 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2723 All ARM instructions require 4-byte alignment.
2724 (Almost) all Thumb instructions require 2-byte alignment.
2726 When emitting instructions into any section, mark the section
2729 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2730 but themselves require 2-byte alignment; this applies to some
2731 PC- relative forms. However, these cases will involve implicit
2732 literal pool generation or an explicit .align >=2, both of
2733 which will cause the section to me marked with sufficient
2734 alignment. Thus, we don't handle those cases here. */
2735 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2737 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2738 /* This case will be evaluated later. */
2741 mapping_state_2 (state
, 0);
2744 /* Same as mapping_state, but MAX_CHARS bytes have already been
2745 allocated. Put the mapping symbol that far back. */
2748 mapping_state_2 (enum mstate state
, int max_chars
)
2750 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2752 if (!SEG_NORMAL (now_seg
))
2755 if (mapstate
== state
)
2756 /* The mapping symbol has already been emitted.
2757 There is nothing else to do. */
2760 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2761 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2763 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2764 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2767 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2770 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2771 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2775 #define mapping_state(x) ((void)0)
2776 #define mapping_state_2(x, y) ((void)0)
2779 /* Find the real, Thumb encoded start of a Thumb function. */
2783 find_real_start (symbolS
* symbolP
)
2786 const char * name
= S_GET_NAME (symbolP
);
2787 symbolS
* new_target
;
2789 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2790 #define STUB_NAME ".real_start_of"
2795 /* The compiler may generate BL instructions to local labels because
2796 it needs to perform a branch to a far away location. These labels
2797 do not have a corresponding ".real_start_of" label. We check
2798 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2799 the ".real_start_of" convention for nonlocal branches. */
2800 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2803 real_start
= concat (STUB_NAME
, name
, NULL
);
2804 new_target
= symbol_find (real_start
);
2807 if (new_target
== NULL
)
2809 as_warn (_("Failed to find real start of function: %s\n"), name
);
2810 new_target
= symbolP
;
2818 opcode_select (int width
)
2825 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2826 as_bad (_("selected processor does not support THUMB opcodes"));
2829 /* No need to force the alignment, since we will have been
2830 coming from ARM mode, which is word-aligned. */
2831 record_alignment (now_seg
, 1);
2838 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2839 as_bad (_("selected processor does not support ARM opcodes"));
2844 frag_align (2, 0, 0);
2846 record_alignment (now_seg
, 1);
2851 as_bad (_("invalid instruction size selected (%d)"), width
);
2856 s_arm (int ignore ATTRIBUTE_UNUSED
)
2859 demand_empty_rest_of_line ();
2863 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2866 demand_empty_rest_of_line ();
2870 s_code (int unused ATTRIBUTE_UNUSED
)
2874 temp
= get_absolute_expression ();
2879 opcode_select (temp
);
2883 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2888 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2890 /* If we are not already in thumb mode go into it, EVEN if
2891 the target processor does not support thumb instructions.
2892 This is used by gcc/config/arm/lib1funcs.asm for example
2893 to compile interworking support functions even if the
2894 target processor should not support interworking. */
2898 record_alignment (now_seg
, 1);
2901 demand_empty_rest_of_line ();
2905 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2909 /* The following label is the name/address of the start of a Thumb function.
2910 We need to know this for the interworking support. */
2911 label_is_thumb_function_name
= TRUE
;
2914 /* Perform a .set directive, but also mark the alias as
2915 being a thumb function. */
2918 s_thumb_set (int equiv
)
2920 /* XXX the following is a duplicate of the code for s_set() in read.c
2921 We cannot just call that code as we need to get at the symbol that
2928 /* Especial apologies for the random logic:
2929 This just grew, and could be parsed much more simply!
2931 delim
= get_symbol_name (& name
);
2932 end_name
= input_line_pointer
;
2933 (void) restore_line_pointer (delim
);
2935 if (*input_line_pointer
!= ',')
2938 as_bad (_("expected comma after name \"%s\""), name
);
2940 ignore_rest_of_line ();
2944 input_line_pointer
++;
2947 if (name
[0] == '.' && name
[1] == '\0')
2949 /* XXX - this should not happen to .thumb_set. */
2953 if ((symbolP
= symbol_find (name
)) == NULL
2954 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2957 /* When doing symbol listings, play games with dummy fragments living
2958 outside the normal fragment chain to record the file and line info
2960 if (listing
& LISTING_SYMBOLS
)
2962 extern struct list_info_struct
* listing_tail
;
2963 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2965 memset (dummy_frag
, 0, sizeof (fragS
));
2966 dummy_frag
->fr_type
= rs_fill
;
2967 dummy_frag
->line
= listing_tail
;
2968 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2969 dummy_frag
->fr_symbol
= symbolP
;
2973 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2976 /* "set" symbols are local unless otherwise specified. */
2977 SF_SET_LOCAL (symbolP
);
2978 #endif /* OBJ_COFF */
2979 } /* Make a new symbol. */
2981 symbol_table_insert (symbolP
);
2986 && S_IS_DEFINED (symbolP
)
2987 && S_GET_SEGMENT (symbolP
) != reg_section
)
2988 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2990 pseudo_set (symbolP
);
2992 demand_empty_rest_of_line ();
2994 /* XXX Now we come to the Thumb specific bit of code. */
2996 THUMB_SET_FUNC (symbolP
, 1);
2997 ARM_SET_THUMB (symbolP
, 1);
2998 #if defined OBJ_ELF || defined OBJ_COFF
2999 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3003 /* Directives: Mode selection. */
3005 /* .syntax [unified|divided] - choose the new unified syntax
3006 (same for Arm and Thumb encoding, modulo slight differences in what
3007 can be represented) or the old divergent syntax for each mode. */
3009 s_syntax (int unused ATTRIBUTE_UNUSED
)
3013 delim
= get_symbol_name (& name
);
3015 if (!strcasecmp (name
, "unified"))
3016 unified_syntax
= TRUE
;
3017 else if (!strcasecmp (name
, "divided"))
3018 unified_syntax
= FALSE
;
3021 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3024 (void) restore_line_pointer (delim
);
3025 demand_empty_rest_of_line ();
3028 /* Directives: sectioning and alignment. */
3031 s_bss (int ignore ATTRIBUTE_UNUSED
)
3033 /* We don't support putting frags in the BSS segment, we fake it by
3034 marking in_bss, then looking at s_skip for clues. */
3035 subseg_set (bss_section
, 0);
3036 demand_empty_rest_of_line ();
3038 #ifdef md_elf_section_change_hook
3039 md_elf_section_change_hook ();
3044 s_even (int ignore ATTRIBUTE_UNUSED
)
3046 /* Never make frag if expect extra pass. */
3048 frag_align (1, 0, 0);
3050 record_alignment (now_seg
, 1);
3052 demand_empty_rest_of_line ();
3055 /* Directives: CodeComposer Studio. */
3057 /* .ref (for CodeComposer Studio syntax only). */
3059 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3061 if (codecomposer_syntax
)
3062 ignore_rest_of_line ();
3064 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3067 /* If name is not NULL, then it is used for marking the beginning of a
3068 function, whereas if it is NULL then it means the function end. */
3070 asmfunc_debug (const char * name
)
3072 static const char * last_name
= NULL
;
3076 gas_assert (last_name
== NULL
);
3079 if (debug_type
== DEBUG_STABS
)
3080 stabs_generate_asm_func (name
, name
);
3084 gas_assert (last_name
!= NULL
);
3086 if (debug_type
== DEBUG_STABS
)
3087 stabs_generate_asm_endfunc (last_name
, last_name
);
3094 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3096 if (codecomposer_syntax
)
3098 switch (asmfunc_state
)
3100 case OUTSIDE_ASMFUNC
:
3101 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3104 case WAITING_ASMFUNC_NAME
:
3105 as_bad (_(".asmfunc repeated."));
3108 case WAITING_ENDASMFUNC
:
3109 as_bad (_(".asmfunc without function."));
3112 demand_empty_rest_of_line ();
3115 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3119 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3121 if (codecomposer_syntax
)
3123 switch (asmfunc_state
)
3125 case OUTSIDE_ASMFUNC
:
3126 as_bad (_(".endasmfunc without a .asmfunc."));
3129 case WAITING_ASMFUNC_NAME
:
3130 as_bad (_(".endasmfunc without function."));
3133 case WAITING_ENDASMFUNC
:
3134 asmfunc_state
= OUTSIDE_ASMFUNC
;
3135 asmfunc_debug (NULL
);
3138 demand_empty_rest_of_line ();
3141 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3145 s_ccs_def (int name
)
3147 if (codecomposer_syntax
)
3150 as_bad (_(".def pseudo-op only available with -mccs flag."));
3153 /* Directives: Literal pools. */
3155 static literal_pool
*
3156 find_literal_pool (void)
3158 literal_pool
* pool
;
3160 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3162 if (pool
->section
== now_seg
3163 && pool
->sub_section
== now_subseg
)
3170 static literal_pool
*
3171 find_or_make_literal_pool (void)
3173 /* Next literal pool ID number. */
3174 static unsigned int latest_pool_num
= 1;
3175 literal_pool
* pool
;
3177 pool
= find_literal_pool ();
3181 /* Create a new pool. */
3182 pool
= XNEW (literal_pool
);
3186 pool
->next_free_entry
= 0;
3187 pool
->section
= now_seg
;
3188 pool
->sub_section
= now_subseg
;
3189 pool
->next
= list_of_pools
;
3190 pool
->symbol
= NULL
;
3191 pool
->alignment
= 2;
3193 /* Add it to the list. */
3194 list_of_pools
= pool
;
3197 /* New pools, and emptied pools, will have a NULL symbol. */
3198 if (pool
->symbol
== NULL
)
3200 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3201 (valueT
) 0, &zero_address_frag
);
3202 pool
->id
= latest_pool_num
++;
3209 /* Add the literal in the global 'inst'
3210 structure to the relevant literal pool. */
3213 add_to_lit_pool (unsigned int nbytes
)
3215 #define PADDING_SLOT 0x1
3216 #define LIT_ENTRY_SIZE_MASK 0xFF
3217 literal_pool
* pool
;
3218 unsigned int entry
, pool_size
= 0;
3219 bfd_boolean padding_slot_p
= FALSE
;
3225 imm1
= inst
.operands
[1].imm
;
3226 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3227 : inst
.reloc
.exp
.X_unsigned
? 0
3228 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3229 if (target_big_endian
)
3232 imm2
= inst
.operands
[1].imm
;
3236 pool
= find_or_make_literal_pool ();
3238 /* Check if this literal value is already in the pool. */
3239 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3243 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3244 && (inst
.reloc
.exp
.X_op
== O_constant
)
3245 && (pool
->literals
[entry
].X_add_number
3246 == inst
.reloc
.exp
.X_add_number
)
3247 && (pool
->literals
[entry
].X_md
== nbytes
)
3248 && (pool
->literals
[entry
].X_unsigned
3249 == inst
.reloc
.exp
.X_unsigned
))
3252 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3253 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3254 && (pool
->literals
[entry
].X_add_number
3255 == inst
.reloc
.exp
.X_add_number
)
3256 && (pool
->literals
[entry
].X_add_symbol
3257 == inst
.reloc
.exp
.X_add_symbol
)
3258 && (pool
->literals
[entry
].X_op_symbol
3259 == inst
.reloc
.exp
.X_op_symbol
)
3260 && (pool
->literals
[entry
].X_md
== nbytes
))
3263 else if ((nbytes
== 8)
3264 && !(pool_size
& 0x7)
3265 && ((entry
+ 1) != pool
->next_free_entry
)
3266 && (pool
->literals
[entry
].X_op
== O_constant
)
3267 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3268 && (pool
->literals
[entry
].X_unsigned
3269 == inst
.reloc
.exp
.X_unsigned
)
3270 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3271 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3272 && (pool
->literals
[entry
+ 1].X_unsigned
3273 == inst
.reloc
.exp
.X_unsigned
))
3276 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3277 if (padding_slot_p
&& (nbytes
== 4))
3283 /* Do we need to create a new entry? */
3284 if (entry
== pool
->next_free_entry
)
3286 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3288 inst
.error
= _("literal pool overflow");
3294 /* For 8-byte entries, we align to an 8-byte boundary,
3295 and split it into two 4-byte entries, because on 32-bit
3296 host, 8-byte constants are treated as big num, thus
3297 saved in "generic_bignum" which will be overwritten
3298 by later assignments.
3300 We also need to make sure there is enough space for
3303 We also check to make sure the literal operand is a
3305 if (!(inst
.reloc
.exp
.X_op
== O_constant
3306 || inst
.reloc
.exp
.X_op
== O_big
))
3308 inst
.error
= _("invalid type for literal pool");
3311 else if (pool_size
& 0x7)
3313 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3315 inst
.error
= _("literal pool overflow");
3319 pool
->literals
[entry
] = inst
.reloc
.exp
;
3320 pool
->literals
[entry
].X_op
= O_constant
;
3321 pool
->literals
[entry
].X_add_number
= 0;
3322 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3323 pool
->next_free_entry
+= 1;
3326 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3328 inst
.error
= _("literal pool overflow");
3332 pool
->literals
[entry
] = inst
.reloc
.exp
;
3333 pool
->literals
[entry
].X_op
= O_constant
;
3334 pool
->literals
[entry
].X_add_number
= imm1
;
3335 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3336 pool
->literals
[entry
++].X_md
= 4;
3337 pool
->literals
[entry
] = inst
.reloc
.exp
;
3338 pool
->literals
[entry
].X_op
= O_constant
;
3339 pool
->literals
[entry
].X_add_number
= imm2
;
3340 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3341 pool
->literals
[entry
].X_md
= 4;
3342 pool
->alignment
= 3;
3343 pool
->next_free_entry
+= 1;
3347 pool
->literals
[entry
] = inst
.reloc
.exp
;
3348 pool
->literals
[entry
].X_md
= 4;
3352 /* PR ld/12974: Record the location of the first source line to reference
3353 this entry in the literal pool. If it turns out during linking that the
3354 symbol does not exist we will be able to give an accurate line number for
3355 the (first use of the) missing reference. */
3356 if (debug_type
== DEBUG_DWARF2
)
3357 dwarf2_where (pool
->locs
+ entry
);
3359 pool
->next_free_entry
+= 1;
3361 else if (padding_slot_p
)
3363 pool
->literals
[entry
] = inst
.reloc
.exp
;
3364 pool
->literals
[entry
].X_md
= nbytes
;
3367 inst
.reloc
.exp
.X_op
= O_symbol
;
3368 inst
.reloc
.exp
.X_add_number
= pool_size
;
3369 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3375 tc_start_label_without_colon (void)
3377 bfd_boolean ret
= TRUE
;
3379 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3381 const char *label
= input_line_pointer
;
3383 while (!is_end_of_line
[(int) label
[-1]])
3388 as_bad (_("Invalid label '%s'"), label
);
3392 asmfunc_debug (label
);
3394 asmfunc_state
= WAITING_ENDASMFUNC
;
3400 /* Can't use symbol_new here, so have to create a symbol and then at
3401 a later date assign it a value. That's what these functions do. */
3404 symbol_locate (symbolS
* symbolP
,
3405 const char * name
, /* It is copied, the caller can modify. */
3406 segT segment
, /* Segment identifier (SEG_<something>). */
3407 valueT valu
, /* Symbol value. */
3408 fragS
* frag
) /* Associated fragment. */
3411 char * preserved_copy_of_name
;
3413 name_length
= strlen (name
) + 1; /* +1 for \0. */
3414 obstack_grow (¬es
, name
, name_length
);
3415 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3417 #ifdef tc_canonicalize_symbol_name
3418 preserved_copy_of_name
=
3419 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3422 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3424 S_SET_SEGMENT (symbolP
, segment
);
3425 S_SET_VALUE (symbolP
, valu
);
3426 symbol_clear_list_pointers (symbolP
);
3428 symbol_set_frag (symbolP
, frag
);
3430 /* Link to end of symbol chain. */
3432 extern int symbol_table_frozen
;
3434 if (symbol_table_frozen
)
3438 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3440 obj_symbol_new_hook (symbolP
);
3442 #ifdef tc_symbol_new_hook
3443 tc_symbol_new_hook (symbolP
);
3447 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3448 #endif /* DEBUG_SYMS */
3452 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3455 literal_pool
* pool
;
3458 pool
= find_literal_pool ();
3460 || pool
->symbol
== NULL
3461 || pool
->next_free_entry
== 0)
3464 /* Align pool as you have word accesses.
3465 Only make a frag if we have to. */
3467 frag_align (pool
->alignment
, 0, 0);
3469 record_alignment (now_seg
, 2);
3472 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3473 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3475 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3477 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3478 (valueT
) frag_now_fix (), frag_now
);
3479 symbol_table_insert (pool
->symbol
);
3481 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3483 #if defined OBJ_COFF || defined OBJ_ELF
3484 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3487 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3490 if (debug_type
== DEBUG_DWARF2
)
3491 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3493 /* First output the expression in the instruction to the pool. */
3494 emit_expr (&(pool
->literals
[entry
]),
3495 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3498 /* Mark the pool as empty. */
3499 pool
->next_free_entry
= 0;
3500 pool
->symbol
= NULL
;
3504 /* Forward declarations for functions below, in the MD interface
3506 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3507 static valueT
create_unwind_entry (int);
3508 static void start_unwind_section (const segT
, int);
3509 static void add_unwind_opcode (valueT
, int);
3510 static void flush_pending_unwind (void);
3512 /* Directives: Data. */
3515 s_arm_elf_cons (int nbytes
)
3519 #ifdef md_flush_pending_output
3520 md_flush_pending_output ();
3523 if (is_it_end_of_statement ())
3525 demand_empty_rest_of_line ();
3529 #ifdef md_cons_align
3530 md_cons_align (nbytes
);
3533 mapping_state (MAP_DATA
);
3537 char *base
= input_line_pointer
;
3541 if (exp
.X_op
!= O_symbol
)
3542 emit_expr (&exp
, (unsigned int) nbytes
);
3545 char *before_reloc
= input_line_pointer
;
3546 reloc
= parse_reloc (&input_line_pointer
);
3549 as_bad (_("unrecognized relocation suffix"));
3550 ignore_rest_of_line ();
3553 else if (reloc
== BFD_RELOC_UNUSED
)
3554 emit_expr (&exp
, (unsigned int) nbytes
);
3557 reloc_howto_type
*howto
= (reloc_howto_type
*)
3558 bfd_reloc_type_lookup (stdoutput
,
3559 (bfd_reloc_code_real_type
) reloc
);
3560 int size
= bfd_get_reloc_size (howto
);
3562 if (reloc
== BFD_RELOC_ARM_PLT32
)
3564 as_bad (_("(plt) is only valid on branch targets"));
3565 reloc
= BFD_RELOC_UNUSED
;
3570 as_bad (ngettext ("%s relocations do not fit in %d byte",
3571 "%s relocations do not fit in %d bytes",
3573 howto
->name
, nbytes
);
3576 /* We've parsed an expression stopping at O_symbol.
3577 But there may be more expression left now that we
3578 have parsed the relocation marker. Parse it again.
3579 XXX Surely there is a cleaner way to do this. */
3580 char *p
= input_line_pointer
;
3582 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3584 memcpy (save_buf
, base
, input_line_pointer
- base
);
3585 memmove (base
+ (input_line_pointer
- before_reloc
),
3586 base
, before_reloc
- base
);
3588 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3590 memcpy (base
, save_buf
, p
- base
);
3592 offset
= nbytes
- size
;
3593 p
= frag_more (nbytes
);
3594 memset (p
, 0, nbytes
);
3595 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3596 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3602 while (*input_line_pointer
++ == ',');
3604 /* Put terminator back into stream. */
3605 input_line_pointer
--;
3606 demand_empty_rest_of_line ();
3609 /* Emit an expression containing a 32-bit thumb instruction.
3610 Implementation based on put_thumb32_insn. */
3613 emit_thumb32_expr (expressionS
* exp
)
3615 expressionS exp_high
= *exp
;
3617 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3618 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3619 exp
->X_add_number
&= 0xffff;
3620 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3623 /* Guess the instruction size based on the opcode. */
3626 thumb_insn_size (int opcode
)
3628 if ((unsigned int) opcode
< 0xe800u
)
3630 else if ((unsigned int) opcode
>= 0xe8000000u
)
3637 emit_insn (expressionS
*exp
, int nbytes
)
3641 if (exp
->X_op
== O_constant
)
3646 size
= thumb_insn_size (exp
->X_add_number
);
3650 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3652 as_bad (_(".inst.n operand too big. "\
3653 "Use .inst.w instead"));
3658 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3659 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3661 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3663 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3664 emit_thumb32_expr (exp
);
3666 emit_expr (exp
, (unsigned int) size
);
3668 it_fsm_post_encode ();
3672 as_bad (_("cannot determine Thumb instruction size. " \
3673 "Use .inst.n/.inst.w instead"));
3676 as_bad (_("constant expression required"));
3681 /* Like s_arm_elf_cons but do not use md_cons_align and
3682 set the mapping state to MAP_ARM/MAP_THUMB. */
3685 s_arm_elf_inst (int nbytes
)
3687 if (is_it_end_of_statement ())
3689 demand_empty_rest_of_line ();
3693 /* Calling mapping_state () here will not change ARM/THUMB,
3694 but will ensure not to be in DATA state. */
3697 mapping_state (MAP_THUMB
);
3702 as_bad (_("width suffixes are invalid in ARM mode"));
3703 ignore_rest_of_line ();
3709 mapping_state (MAP_ARM
);
3718 if (! emit_insn (& exp
, nbytes
))
3720 ignore_rest_of_line ();
3724 while (*input_line_pointer
++ == ',');
3726 /* Put terminator back into stream. */
3727 input_line_pointer
--;
3728 demand_empty_rest_of_line ();
3731 /* Parse a .rel31 directive. */
3734 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3741 if (*input_line_pointer
== '1')
3742 highbit
= 0x80000000;
3743 else if (*input_line_pointer
!= '0')
3744 as_bad (_("expected 0 or 1"));
3746 input_line_pointer
++;
3747 if (*input_line_pointer
!= ',')
3748 as_bad (_("missing comma"));
3749 input_line_pointer
++;
3751 #ifdef md_flush_pending_output
3752 md_flush_pending_output ();
3755 #ifdef md_cons_align
3759 mapping_state (MAP_DATA
);
3764 md_number_to_chars (p
, highbit
, 4);
3765 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3766 BFD_RELOC_ARM_PREL31
);
3768 demand_empty_rest_of_line ();
3771 /* Directives: AEABI stack-unwind tables. */
3773 /* Parse an unwind_fnstart directive. Simply records the current location. */
3776 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3778 demand_empty_rest_of_line ();
3779 if (unwind
.proc_start
)
3781 as_bad (_("duplicate .fnstart directive"));
3785 /* Mark the start of the function. */
3786 unwind
.proc_start
= expr_build_dot ();
3788 /* Reset the rest of the unwind info. */
3789 unwind
.opcode_count
= 0;
3790 unwind
.table_entry
= NULL
;
3791 unwind
.personality_routine
= NULL
;
3792 unwind
.personality_index
= -1;
3793 unwind
.frame_size
= 0;
3794 unwind
.fp_offset
= 0;
3795 unwind
.fp_reg
= REG_SP
;
3797 unwind
.sp_restored
= 0;
3801 /* Parse a handlerdata directive. Creates the exception handling table entry
3802 for the function. */
3805 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3807 demand_empty_rest_of_line ();
3808 if (!unwind
.proc_start
)
3809 as_bad (MISSING_FNSTART
);
3811 if (unwind
.table_entry
)
3812 as_bad (_("duplicate .handlerdata directive"));
3814 create_unwind_entry (1);
3817 /* Parse an unwind_fnend directive. Generates the index table entry. */
3820 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3825 unsigned int marked_pr_dependency
;
3827 demand_empty_rest_of_line ();
3829 if (!unwind
.proc_start
)
3831 as_bad (_(".fnend directive without .fnstart"));
3835 /* Add eh table entry. */
3836 if (unwind
.table_entry
== NULL
)
3837 val
= create_unwind_entry (0);
3841 /* Add index table entry. This is two words. */
3842 start_unwind_section (unwind
.saved_seg
, 1);
3843 frag_align (2, 0, 0);
3844 record_alignment (now_seg
, 2);
3846 ptr
= frag_more (8);
3848 where
= frag_now_fix () - 8;
3850 /* Self relative offset of the function start. */
3851 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3852 BFD_RELOC_ARM_PREL31
);
3854 /* Indicate dependency on EHABI-defined personality routines to the
3855 linker, if it hasn't been done already. */
3856 marked_pr_dependency
3857 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3858 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3859 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3861 static const char *const name
[] =
3863 "__aeabi_unwind_cpp_pr0",
3864 "__aeabi_unwind_cpp_pr1",
3865 "__aeabi_unwind_cpp_pr2"
3867 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3868 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3869 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3870 |= 1 << unwind
.personality_index
;
3874 /* Inline exception table entry. */
3875 md_number_to_chars (ptr
+ 4, val
, 4);
3877 /* Self relative offset of the table entry. */
3878 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3879 BFD_RELOC_ARM_PREL31
);
3881 /* Restore the original section. */
3882 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3884 unwind
.proc_start
= NULL
;
3888 /* Parse an unwind_cantunwind directive. */
3891 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3893 demand_empty_rest_of_line ();
3894 if (!unwind
.proc_start
)
3895 as_bad (MISSING_FNSTART
);
3897 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3898 as_bad (_("personality routine specified for cantunwind frame"));
3900 unwind
.personality_index
= -2;
3904 /* Parse a personalityindex directive. */
3907 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3911 if (!unwind
.proc_start
)
3912 as_bad (MISSING_FNSTART
);
3914 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3915 as_bad (_("duplicate .personalityindex directive"));
3919 if (exp
.X_op
!= O_constant
3920 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3922 as_bad (_("bad personality routine number"));
3923 ignore_rest_of_line ();
3927 unwind
.personality_index
= exp
.X_add_number
;
3929 demand_empty_rest_of_line ();
3933 /* Parse a personality directive. */
3936 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3940 if (!unwind
.proc_start
)
3941 as_bad (MISSING_FNSTART
);
3943 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3944 as_bad (_("duplicate .personality directive"));
3946 c
= get_symbol_name (& name
);
3947 p
= input_line_pointer
;
3949 ++ input_line_pointer
;
3950 unwind
.personality_routine
= symbol_find_or_make (name
);
3952 demand_empty_rest_of_line ();
3956 /* Parse a directive saving core registers. */
3959 s_arm_unwind_save_core (void)
3965 range
= parse_reg_list (&input_line_pointer
);
3968 as_bad (_("expected register list"));
3969 ignore_rest_of_line ();
3973 demand_empty_rest_of_line ();
3975 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3976 into .unwind_save {..., sp...}. We aren't bothered about the value of
3977 ip because it is clobbered by calls. */
3978 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3979 && (range
& 0x3000) == 0x1000)
3981 unwind
.opcode_count
--;
3982 unwind
.sp_restored
= 0;
3983 range
= (range
| 0x2000) & ~0x1000;
3984 unwind
.pending_offset
= 0;
3990 /* See if we can use the short opcodes. These pop a block of up to 8
3991 registers starting with r4, plus maybe r14. */
3992 for (n
= 0; n
< 8; n
++)
3994 /* Break at the first non-saved register. */
3995 if ((range
& (1 << (n
+ 4))) == 0)
3998 /* See if there are any other bits set. */
3999 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4001 /* Use the long form. */
4002 op
= 0x8000 | ((range
>> 4) & 0xfff);
4003 add_unwind_opcode (op
, 2);
4007 /* Use the short form. */
4009 op
= 0xa8; /* Pop r14. */
4011 op
= 0xa0; /* Do not pop r14. */
4013 add_unwind_opcode (op
, 1);
4020 op
= 0xb100 | (range
& 0xf);
4021 add_unwind_opcode (op
, 2);
4024 /* Record the number of bytes pushed. */
4025 for (n
= 0; n
< 16; n
++)
4027 if (range
& (1 << n
))
4028 unwind
.frame_size
+= 4;
4033 /* Parse a directive saving FPA registers. */
4036 s_arm_unwind_save_fpa (int reg
)
4042 /* Get Number of registers to transfer. */
4043 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4046 exp
.X_op
= O_illegal
;
4048 if (exp
.X_op
!= O_constant
)
4050 as_bad (_("expected , <constant>"));
4051 ignore_rest_of_line ();
4055 num_regs
= exp
.X_add_number
;
4057 if (num_regs
< 1 || num_regs
> 4)
4059 as_bad (_("number of registers must be in the range [1:4]"));
4060 ignore_rest_of_line ();
4064 demand_empty_rest_of_line ();
4069 op
= 0xb4 | (num_regs
- 1);
4070 add_unwind_opcode (op
, 1);
4075 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4076 add_unwind_opcode (op
, 2);
4078 unwind
.frame_size
+= num_regs
* 12;
4082 /* Parse a directive saving VFP registers for ARMv6 and above. */
4085 s_arm_unwind_save_vfp_armv6 (void)
4090 int num_vfpv3_regs
= 0;
4091 int num_regs_below_16
;
4093 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4096 as_bad (_("expected register list"));
4097 ignore_rest_of_line ();
4101 demand_empty_rest_of_line ();
4103 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4104 than FSTMX/FLDMX-style ones). */
4106 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4108 num_vfpv3_regs
= count
;
4109 else if (start
+ count
> 16)
4110 num_vfpv3_regs
= start
+ count
- 16;
4112 if (num_vfpv3_regs
> 0)
4114 int start_offset
= start
> 16 ? start
- 16 : 0;
4115 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4116 add_unwind_opcode (op
, 2);
4119 /* Generate opcode for registers numbered in the range 0 .. 15. */
4120 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4121 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4122 if (num_regs_below_16
> 0)
4124 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4125 add_unwind_opcode (op
, 2);
4128 unwind
.frame_size
+= count
* 8;
4132 /* Parse a directive saving VFP registers for pre-ARMv6. */
4135 s_arm_unwind_save_vfp (void)
4141 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4144 as_bad (_("expected register list"));
4145 ignore_rest_of_line ();
4149 demand_empty_rest_of_line ();
4154 op
= 0xb8 | (count
- 1);
4155 add_unwind_opcode (op
, 1);
4160 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4161 add_unwind_opcode (op
, 2);
4163 unwind
.frame_size
+= count
* 8 + 4;
4167 /* Parse a directive saving iWMMXt data registers. */
4170 s_arm_unwind_save_mmxwr (void)
4178 if (*input_line_pointer
== '{')
4179 input_line_pointer
++;
4183 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4187 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4192 as_tsktsk (_("register list not in ascending order"));
4195 if (*input_line_pointer
== '-')
4197 input_line_pointer
++;
4198 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4201 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4204 else if (reg
>= hi_reg
)
4206 as_bad (_("bad register range"));
4209 for (; reg
< hi_reg
; reg
++)
4213 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4215 skip_past_char (&input_line_pointer
, '}');
4217 demand_empty_rest_of_line ();
4219 /* Generate any deferred opcodes because we're going to be looking at
4221 flush_pending_unwind ();
4223 for (i
= 0; i
< 16; i
++)
4225 if (mask
& (1 << i
))
4226 unwind
.frame_size
+= 8;
4229 /* Attempt to combine with a previous opcode. We do this because gcc
4230 likes to output separate unwind directives for a single block of
4232 if (unwind
.opcode_count
> 0)
4234 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4235 if ((i
& 0xf8) == 0xc0)
4238 /* Only merge if the blocks are contiguous. */
4241 if ((mask
& 0xfe00) == (1 << 9))
4243 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4244 unwind
.opcode_count
--;
4247 else if (i
== 6 && unwind
.opcode_count
>= 2)
4249 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4253 op
= 0xffff << (reg
- 1);
4255 && ((mask
& op
) == (1u << (reg
- 1))))
4257 op
= (1 << (reg
+ i
+ 1)) - 1;
4258 op
&= ~((1 << reg
) - 1);
4260 unwind
.opcode_count
-= 2;
4267 /* We want to generate opcodes in the order the registers have been
4268 saved, ie. descending order. */
4269 for (reg
= 15; reg
>= -1; reg
--)
4271 /* Save registers in blocks. */
4273 || !(mask
& (1 << reg
)))
4275 /* We found an unsaved reg. Generate opcodes to save the
4282 op
= 0xc0 | (hi_reg
- 10);
4283 add_unwind_opcode (op
, 1);
4288 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4289 add_unwind_opcode (op
, 2);
4298 ignore_rest_of_line ();
4302 s_arm_unwind_save_mmxwcg (void)
4309 if (*input_line_pointer
== '{')
4310 input_line_pointer
++;
4312 skip_whitespace (input_line_pointer
);
4316 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4320 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4326 as_tsktsk (_("register list not in ascending order"));
4329 if (*input_line_pointer
== '-')
4331 input_line_pointer
++;
4332 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4335 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4338 else if (reg
>= hi_reg
)
4340 as_bad (_("bad register range"));
4343 for (; reg
< hi_reg
; reg
++)
4347 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4349 skip_past_char (&input_line_pointer
, '}');
4351 demand_empty_rest_of_line ();
4353 /* Generate any deferred opcodes because we're going to be looking at
4355 flush_pending_unwind ();
4357 for (reg
= 0; reg
< 16; reg
++)
4359 if (mask
& (1 << reg
))
4360 unwind
.frame_size
+= 4;
4363 add_unwind_opcode (op
, 2);
4366 ignore_rest_of_line ();
4370 /* Parse an unwind_save directive.
4371 If the argument is non-zero, this is a .vsave directive. */
4374 s_arm_unwind_save (int arch_v6
)
4377 struct reg_entry
*reg
;
4378 bfd_boolean had_brace
= FALSE
;
4380 if (!unwind
.proc_start
)
4381 as_bad (MISSING_FNSTART
);
4383 /* Figure out what sort of save we have. */
4384 peek
= input_line_pointer
;
4392 reg
= arm_reg_parse_multi (&peek
);
4396 as_bad (_("register expected"));
4397 ignore_rest_of_line ();
4406 as_bad (_("FPA .unwind_save does not take a register list"));
4407 ignore_rest_of_line ();
4410 input_line_pointer
= peek
;
4411 s_arm_unwind_save_fpa (reg
->number
);
4415 s_arm_unwind_save_core ();
4420 s_arm_unwind_save_vfp_armv6 ();
4422 s_arm_unwind_save_vfp ();
4425 case REG_TYPE_MMXWR
:
4426 s_arm_unwind_save_mmxwr ();
4429 case REG_TYPE_MMXWCG
:
4430 s_arm_unwind_save_mmxwcg ();
4434 as_bad (_(".unwind_save does not support this kind of register"));
4435 ignore_rest_of_line ();
4440 /* Parse an unwind_movsp directive. */
4443 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4449 if (!unwind
.proc_start
)
4450 as_bad (MISSING_FNSTART
);
4452 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4455 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4456 ignore_rest_of_line ();
4460 /* Optional constant. */
4461 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4463 if (immediate_for_directive (&offset
) == FAIL
)
4469 demand_empty_rest_of_line ();
4471 if (reg
== REG_SP
|| reg
== REG_PC
)
4473 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4477 if (unwind
.fp_reg
!= REG_SP
)
4478 as_bad (_("unexpected .unwind_movsp directive"));
4480 /* Generate opcode to restore the value. */
4482 add_unwind_opcode (op
, 1);
4484 /* Record the information for later. */
4485 unwind
.fp_reg
= reg
;
4486 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4487 unwind
.sp_restored
= 1;
4490 /* Parse an unwind_pad directive. */
4493 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4497 if (!unwind
.proc_start
)
4498 as_bad (MISSING_FNSTART
);
4500 if (immediate_for_directive (&offset
) == FAIL
)
4505 as_bad (_("stack increment must be multiple of 4"));
4506 ignore_rest_of_line ();
4510 /* Don't generate any opcodes, just record the details for later. */
4511 unwind
.frame_size
+= offset
;
4512 unwind
.pending_offset
+= offset
;
4514 demand_empty_rest_of_line ();
4517 /* Parse an unwind_setfp directive. */
4520 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4526 if (!unwind
.proc_start
)
4527 as_bad (MISSING_FNSTART
);
4529 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4530 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4533 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4535 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4537 as_bad (_("expected <reg>, <reg>"));
4538 ignore_rest_of_line ();
4542 /* Optional constant. */
4543 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4545 if (immediate_for_directive (&offset
) == FAIL
)
4551 demand_empty_rest_of_line ();
4553 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4555 as_bad (_("register must be either sp or set by a previous"
4556 "unwind_movsp directive"));
4560 /* Don't generate any opcodes, just record the information for later. */
4561 unwind
.fp_reg
= fp_reg
;
4563 if (sp_reg
== REG_SP
)
4564 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4566 unwind
.fp_offset
-= offset
;
4569 /* Parse an unwind_raw directive. */
4572 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4575 /* This is an arbitrary limit. */
4576 unsigned char op
[16];
4579 if (!unwind
.proc_start
)
4580 as_bad (MISSING_FNSTART
);
4583 if (exp
.X_op
== O_constant
4584 && skip_past_comma (&input_line_pointer
) != FAIL
)
4586 unwind
.frame_size
+= exp
.X_add_number
;
4590 exp
.X_op
= O_illegal
;
4592 if (exp
.X_op
!= O_constant
)
4594 as_bad (_("expected <offset>, <opcode>"));
4595 ignore_rest_of_line ();
4601 /* Parse the opcode. */
4606 as_bad (_("unwind opcode too long"));
4607 ignore_rest_of_line ();
4609 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4611 as_bad (_("invalid unwind opcode"));
4612 ignore_rest_of_line ();
4615 op
[count
++] = exp
.X_add_number
;
4617 /* Parse the next byte. */
4618 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4624 /* Add the opcode bytes in reverse order. */
4626 add_unwind_opcode (op
[count
], 1);
4628 demand_empty_rest_of_line ();
4632 /* Parse a .eabi_attribute directive. */
4635 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4637 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4639 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4640 attributes_set_explicitly
[tag
] = 1;
4643 /* Emit a tls fix for the symbol. */
4646 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4650 #ifdef md_flush_pending_output
4651 md_flush_pending_output ();
4654 #ifdef md_cons_align
4658 /* Since we're just labelling the code, there's no need to define a
4661 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4662 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4663 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4664 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4666 #endif /* OBJ_ELF */
4668 static void s_arm_arch (int);
4669 static void s_arm_object_arch (int);
4670 static void s_arm_cpu (int);
4671 static void s_arm_fpu (int);
4672 static void s_arm_arch_extension (int);
4677 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4684 if (exp
.X_op
== O_symbol
)
4685 exp
.X_op
= O_secrel
;
4687 emit_expr (&exp
, 4);
4689 while (*input_line_pointer
++ == ',');
4691 input_line_pointer
--;
4692 demand_empty_rest_of_line ();
4696 /* This table describes all the machine specific pseudo-ops the assembler
4697 has to support. The fields are:
4698 pseudo-op name without dot
4699 function to call to execute this pseudo-op
4700 Integer arg to pass to the function. */
4702 const pseudo_typeS md_pseudo_table
[] =
4704 /* Never called because '.req' does not start a line. */
4705 { "req", s_req
, 0 },
4706 /* Following two are likewise never called. */
4709 { "unreq", s_unreq
, 0 },
4710 { "bss", s_bss
, 0 },
4711 { "align", s_align_ptwo
, 2 },
4712 { "arm", s_arm
, 0 },
4713 { "thumb", s_thumb
, 0 },
4714 { "code", s_code
, 0 },
4715 { "force_thumb", s_force_thumb
, 0 },
4716 { "thumb_func", s_thumb_func
, 0 },
4717 { "thumb_set", s_thumb_set
, 0 },
4718 { "even", s_even
, 0 },
4719 { "ltorg", s_ltorg
, 0 },
4720 { "pool", s_ltorg
, 0 },
4721 { "syntax", s_syntax
, 0 },
4722 { "cpu", s_arm_cpu
, 0 },
4723 { "arch", s_arm_arch
, 0 },
4724 { "object_arch", s_arm_object_arch
, 0 },
4725 { "fpu", s_arm_fpu
, 0 },
4726 { "arch_extension", s_arm_arch_extension
, 0 },
4728 { "word", s_arm_elf_cons
, 4 },
4729 { "long", s_arm_elf_cons
, 4 },
4730 { "inst.n", s_arm_elf_inst
, 2 },
4731 { "inst.w", s_arm_elf_inst
, 4 },
4732 { "inst", s_arm_elf_inst
, 0 },
4733 { "rel31", s_arm_rel31
, 0 },
4734 { "fnstart", s_arm_unwind_fnstart
, 0 },
4735 { "fnend", s_arm_unwind_fnend
, 0 },
4736 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4737 { "personality", s_arm_unwind_personality
, 0 },
4738 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4739 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4740 { "save", s_arm_unwind_save
, 0 },
4741 { "vsave", s_arm_unwind_save
, 1 },
4742 { "movsp", s_arm_unwind_movsp
, 0 },
4743 { "pad", s_arm_unwind_pad
, 0 },
4744 { "setfp", s_arm_unwind_setfp
, 0 },
4745 { "unwind_raw", s_arm_unwind_raw
, 0 },
4746 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4747 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4751 /* These are used for dwarf. */
4755 /* These are used for dwarf2. */
4756 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4757 { "loc", dwarf2_directive_loc
, 0 },
4758 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4760 { "extend", float_cons
, 'x' },
4761 { "ldouble", float_cons
, 'x' },
4762 { "packed", float_cons
, 'p' },
4764 {"secrel32", pe_directive_secrel
, 0},
4767 /* These are for compatibility with CodeComposer Studio. */
4768 {"ref", s_ccs_ref
, 0},
4769 {"def", s_ccs_def
, 0},
4770 {"asmfunc", s_ccs_asmfunc
, 0},
4771 {"endasmfunc", s_ccs_endasmfunc
, 0},
4776 /* Parser functions used exclusively in instruction operands. */
4778 /* Generic immediate-value read function for use in insn parsing.
4779 STR points to the beginning of the immediate (the leading #);
4780 VAL receives the value; if the value is outside [MIN, MAX]
4781 issue an error. PREFIX_OPT is true if the immediate prefix is
4785 parse_immediate (char **str
, int *val
, int min
, int max
,
4786 bfd_boolean prefix_opt
)
4790 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4791 if (exp
.X_op
!= O_constant
)
4793 inst
.error
= _("constant expression required");
4797 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4799 inst
.error
= _("immediate value out of range");
4803 *val
= exp
.X_add_number
;
4807 /* Less-generic immediate-value read function with the possibility of loading a
4808 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4809 instructions. Puts the result directly in inst.operands[i]. */
4812 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4813 bfd_boolean allow_symbol_p
)
4816 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4819 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4821 if (exp_p
->X_op
== O_constant
)
4823 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4824 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4825 O_constant. We have to be careful not to break compilation for
4826 32-bit X_add_number, though. */
4827 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4829 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4830 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4832 inst
.operands
[i
].regisimm
= 1;
4835 else if (exp_p
->X_op
== O_big
4836 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4838 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4840 /* Bignums have their least significant bits in
4841 generic_bignum[0]. Make sure we put 32 bits in imm and
4842 32 bits in reg, in a (hopefully) portable way. */
4843 gas_assert (parts
!= 0);
4845 /* Make sure that the number is not too big.
4846 PR 11972: Bignums can now be sign-extended to the
4847 size of a .octa so check that the out of range bits
4848 are all zero or all one. */
4849 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4851 LITTLENUM_TYPE m
= -1;
4853 if (generic_bignum
[parts
* 2] != 0
4854 && generic_bignum
[parts
* 2] != m
)
4857 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4858 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4862 inst
.operands
[i
].imm
= 0;
4863 for (j
= 0; j
< parts
; j
++, idx
++)
4864 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4865 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4866 inst
.operands
[i
].reg
= 0;
4867 for (j
= 0; j
< parts
; j
++, idx
++)
4868 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4869 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4870 inst
.operands
[i
].regisimm
= 1;
4872 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4880 /* Returns the pseudo-register number of an FPA immediate constant,
4881 or FAIL if there isn't a valid constant here. */
4884 parse_fpa_immediate (char ** str
)
4886 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4892 /* First try and match exact strings, this is to guarantee
4893 that some formats will work even for cross assembly. */
4895 for (i
= 0; fp_const
[i
]; i
++)
4897 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4901 *str
+= strlen (fp_const
[i
]);
4902 if (is_end_of_line
[(unsigned char) **str
])
4908 /* Just because we didn't get a match doesn't mean that the constant
4909 isn't valid, just that it is in a format that we don't
4910 automatically recognize. Try parsing it with the standard
4911 expression routines. */
4913 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4915 /* Look for a raw floating point number. */
4916 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4917 && is_end_of_line
[(unsigned char) *save_in
])
4919 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4921 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4923 if (words
[j
] != fp_values
[i
][j
])
4927 if (j
== MAX_LITTLENUMS
)
4935 /* Try and parse a more complex expression, this will probably fail
4936 unless the code uses a floating point prefix (eg "0f"). */
4937 save_in
= input_line_pointer
;
4938 input_line_pointer
= *str
;
4939 if (expression (&exp
) == absolute_section
4940 && exp
.X_op
== O_big
4941 && exp
.X_add_number
< 0)
4943 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4945 #define X_PRECISION 5
4946 #define E_PRECISION 15L
4947 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4949 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4951 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4953 if (words
[j
] != fp_values
[i
][j
])
4957 if (j
== MAX_LITTLENUMS
)
4959 *str
= input_line_pointer
;
4960 input_line_pointer
= save_in
;
4967 *str
= input_line_pointer
;
4968 input_line_pointer
= save_in
;
4969 inst
.error
= _("invalid FPA immediate expression");
4973 /* Returns 1 if a number has "quarter-precision" float format
4974 0baBbbbbbc defgh000 00000000 00000000. */
4977 is_quarter_float (unsigned imm
)
4979 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4980 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4984 /* Detect the presence of a floating point or integer zero constant,
4988 parse_ifimm_zero (char **in
)
4992 if (!is_immediate_prefix (**in
))
4994 /* In unified syntax, all prefixes are optional. */
4995 if (!unified_syntax
)
5001 /* Accept #0x0 as a synonym for #0. */
5002 if (strncmp (*in
, "0x", 2) == 0)
5005 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5010 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5011 &generic_floating_point_number
);
5014 && generic_floating_point_number
.sign
== '+'
5015 && (generic_floating_point_number
.low
5016 > generic_floating_point_number
.leader
))
5022 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5023 0baBbbbbbc defgh000 00000000 00000000.
5024 The zero and minus-zero cases need special handling, since they can't be
5025 encoded in the "quarter-precision" float format, but can nonetheless be
5026 loaded as integer constants. */
5029 parse_qfloat_immediate (char **ccp
, int *immed
)
5033 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5034 int found_fpchar
= 0;
5036 skip_past_char (&str
, '#');
5038 /* We must not accidentally parse an integer as a floating-point number. Make
5039 sure that the value we parse is not an integer by checking for special
5040 characters '.' or 'e'.
5041 FIXME: This is a horrible hack, but doing better is tricky because type
5042 information isn't in a very usable state at parse time. */
5044 skip_whitespace (fpnum
);
5046 if (strncmp (fpnum
, "0x", 2) == 0)
5050 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5051 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5061 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5063 unsigned fpword
= 0;
5066 /* Our FP word must be 32 bits (single-precision FP). */
5067 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5069 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5073 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5086 /* Shift operands. */
5089 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5092 struct asm_shift_name
5095 enum shift_kind kind
;
5098 /* Third argument to parse_shift. */
5099 enum parse_shift_mode
5101 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5102 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5103 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5104 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5105 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5108 /* Parse a <shift> specifier on an ARM data processing instruction.
5109 This has three forms:
5111 (LSL|LSR|ASL|ASR|ROR) Rs
5112 (LSL|LSR|ASL|ASR|ROR) #imm
5115 Note that ASL is assimilated to LSL in the instruction encoding, and
5116 RRX to ROR #0 (which cannot be written as such). */
5119 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5121 const struct asm_shift_name
*shift_name
;
5122 enum shift_kind shift
;
5127 for (p
= *str
; ISALPHA (*p
); p
++)
5132 inst
.error
= _("shift expression expected");
5136 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5139 if (shift_name
== NULL
)
5141 inst
.error
= _("shift expression expected");
5145 shift
= shift_name
->kind
;
5149 case NO_SHIFT_RESTRICT
:
5150 case SHIFT_IMMEDIATE
: break;
5152 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5153 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5155 inst
.error
= _("'LSL' or 'ASR' required");
5160 case SHIFT_LSL_IMMEDIATE
:
5161 if (shift
!= SHIFT_LSL
)
5163 inst
.error
= _("'LSL' required");
5168 case SHIFT_ASR_IMMEDIATE
:
5169 if (shift
!= SHIFT_ASR
)
5171 inst
.error
= _("'ASR' required");
5179 if (shift
!= SHIFT_RRX
)
5181 /* Whitespace can appear here if the next thing is a bare digit. */
5182 skip_whitespace (p
);
5184 if (mode
== NO_SHIFT_RESTRICT
5185 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5187 inst
.operands
[i
].imm
= reg
;
5188 inst
.operands
[i
].immisreg
= 1;
5190 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5193 inst
.operands
[i
].shift_kind
= shift
;
5194 inst
.operands
[i
].shifted
= 1;
5199 /* Parse a <shifter_operand> for an ARM data processing instruction:
5202 #<immediate>, <rotate>
5206 where <shift> is defined by parse_shift above, and <rotate> is a
5207 multiple of 2 between 0 and 30. Validation of immediate operands
5208 is deferred to md_apply_fix. */
5211 parse_shifter_operand (char **str
, int i
)
5216 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5218 inst
.operands
[i
].reg
= value
;
5219 inst
.operands
[i
].isreg
= 1;
5221 /* parse_shift will override this if appropriate */
5222 inst
.reloc
.exp
.X_op
= O_constant
;
5223 inst
.reloc
.exp
.X_add_number
= 0;
5225 if (skip_past_comma (str
) == FAIL
)
5228 /* Shift operation on register. */
5229 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5232 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5235 if (skip_past_comma (str
) == SUCCESS
)
5237 /* #x, y -- ie explicit rotation by Y. */
5238 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5241 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5243 inst
.error
= _("constant expression expected");
5247 value
= exp
.X_add_number
;
5248 if (value
< 0 || value
> 30 || value
% 2 != 0)
5250 inst
.error
= _("invalid rotation");
5253 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5255 inst
.error
= _("invalid constant");
5259 /* Encode as specified. */
5260 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5264 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5265 inst
.reloc
.pc_rel
= 0;
5269 /* Group relocation information. Each entry in the table contains the
5270 textual name of the relocation as may appear in assembler source
5271 and must end with a colon.
5272 Along with this textual name are the relocation codes to be used if
5273 the corresponding instruction is an ALU instruction (ADD or SUB only),
5274 an LDR, an LDRS, or an LDC. */
5276 struct group_reloc_table_entry
5287 /* Varieties of non-ALU group relocation. */
5294 static struct group_reloc_table_entry group_reloc_table
[] =
5295 { /* Program counter relative: */
5297 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5302 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5303 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5304 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5305 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5307 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5312 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5313 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5314 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5315 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5317 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5318 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5319 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5320 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5321 /* Section base relative */
5323 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5328 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5329 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5330 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5331 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5333 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5338 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5339 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5340 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5341 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5343 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5344 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5345 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5346 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5347 /* Absolute thumb alu relocations. */
5349 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5354 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5359 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5364 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5369 /* Given the address of a pointer pointing to the textual name of a group
5370 relocation as may appear in assembler source, attempt to find its details
5371 in group_reloc_table. The pointer will be updated to the character after
5372 the trailing colon. On failure, FAIL will be returned; SUCCESS
5373 otherwise. On success, *entry will be updated to point at the relevant
5374 group_reloc_table entry. */
5377 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5380 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5382 int length
= strlen (group_reloc_table
[i
].name
);
5384 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5385 && (*str
)[length
] == ':')
5387 *out
= &group_reloc_table
[i
];
5388 *str
+= (length
+ 1);
5396 /* Parse a <shifter_operand> for an ARM data processing instruction
5397 (as for parse_shifter_operand) where group relocations are allowed:
5400 #<immediate>, <rotate>
5401 #:<group_reloc>:<expression>
5405 where <group_reloc> is one of the strings defined in group_reloc_table.
5406 The hashes are optional.
5408 Everything else is as for parse_shifter_operand. */
5410 static parse_operand_result
5411 parse_shifter_operand_group_reloc (char **str
, int i
)
5413 /* Determine if we have the sequence of characters #: or just :
5414 coming next. If we do, then we check for a group relocation.
5415 If we don't, punt the whole lot to parse_shifter_operand. */
5417 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5418 || (*str
)[0] == ':')
5420 struct group_reloc_table_entry
*entry
;
5422 if ((*str
)[0] == '#')
5427 /* Try to parse a group relocation. Anything else is an error. */
5428 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5430 inst
.error
= _("unknown group relocation");
5431 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5434 /* We now have the group relocation table entry corresponding to
5435 the name in the assembler source. Next, we parse the expression. */
5436 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5437 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5439 /* Record the relocation type (always the ALU variant here). */
5440 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5441 gas_assert (inst
.reloc
.type
!= 0);
5443 return PARSE_OPERAND_SUCCESS
;
5446 return parse_shifter_operand (str
, i
) == SUCCESS
5447 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5449 /* Never reached. */
5452 /* Parse a Neon alignment expression. Information is written to
5453 inst.operands[i]. We assume the initial ':' has been skipped.
5455 align .imm = align << 8, .immisalign=1, .preind=0 */
5456 static parse_operand_result
5457 parse_neon_alignment (char **str
, int i
)
5462 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5464 if (exp
.X_op
!= O_constant
)
5466 inst
.error
= _("alignment must be constant");
5467 return PARSE_OPERAND_FAIL
;
5470 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5471 inst
.operands
[i
].immisalign
= 1;
5472 /* Alignments are not pre-indexes. */
5473 inst
.operands
[i
].preind
= 0;
5476 return PARSE_OPERAND_SUCCESS
;
5479 /* Parse all forms of an ARM address expression. Information is written
5480 to inst.operands[i] and/or inst.reloc.
5482 Preindexed addressing (.preind=1):
5484 [Rn, #offset] .reg=Rn .reloc.exp=offset
5485 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5486 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5487 .shift_kind=shift .reloc.exp=shift_imm
5489 These three may have a trailing ! which causes .writeback to be set also.
5491 Postindexed addressing (.postind=1, .writeback=1):
5493 [Rn], #offset .reg=Rn .reloc.exp=offset
5494 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5495 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5496 .shift_kind=shift .reloc.exp=shift_imm
5498 Unindexed addressing (.preind=0, .postind=0):
5500 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5504 [Rn]{!} shorthand for [Rn,#0]{!}
5505 =immediate .isreg=0 .reloc.exp=immediate
5506 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5508 It is the caller's responsibility to check for addressing modes not
5509 supported by the instruction, and to set inst.reloc.type. */
5511 static parse_operand_result
5512 parse_address_main (char **str
, int i
, int group_relocations
,
5513 group_reloc_type group_type
)
5518 if (skip_past_char (&p
, '[') == FAIL
)
5520 if (skip_past_char (&p
, '=') == FAIL
)
5522 /* Bare address - translate to PC-relative offset. */
5523 inst
.reloc
.pc_rel
= 1;
5524 inst
.operands
[i
].reg
= REG_PC
;
5525 inst
.operands
[i
].isreg
= 1;
5526 inst
.operands
[i
].preind
= 1;
5528 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5529 return PARSE_OPERAND_FAIL
;
5531 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5532 /*allow_symbol_p=*/TRUE
))
5533 return PARSE_OPERAND_FAIL
;
5536 return PARSE_OPERAND_SUCCESS
;
5539 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5540 skip_whitespace (p
);
5542 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5544 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5545 return PARSE_OPERAND_FAIL
;
5547 inst
.operands
[i
].reg
= reg
;
5548 inst
.operands
[i
].isreg
= 1;
5550 if (skip_past_comma (&p
) == SUCCESS
)
5552 inst
.operands
[i
].preind
= 1;
5555 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5557 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5559 inst
.operands
[i
].imm
= reg
;
5560 inst
.operands
[i
].immisreg
= 1;
5562 if (skip_past_comma (&p
) == SUCCESS
)
5563 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5564 return PARSE_OPERAND_FAIL
;
5566 else if (skip_past_char (&p
, ':') == SUCCESS
)
5568 /* FIXME: '@' should be used here, but it's filtered out by generic
5569 code before we get to see it here. This may be subject to
5571 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5573 if (result
!= PARSE_OPERAND_SUCCESS
)
5578 if (inst
.operands
[i
].negative
)
5580 inst
.operands
[i
].negative
= 0;
5584 if (group_relocations
5585 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5587 struct group_reloc_table_entry
*entry
;
5589 /* Skip over the #: or : sequence. */
5595 /* Try to parse a group relocation. Anything else is an
5597 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5599 inst
.error
= _("unknown group relocation");
5600 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5603 /* We now have the group relocation table entry corresponding to
5604 the name in the assembler source. Next, we parse the
5606 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5607 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5609 /* Record the relocation type. */
5613 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5617 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5621 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5628 if (inst
.reloc
.type
== 0)
5630 inst
.error
= _("this group relocation is not allowed on this instruction");
5631 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5638 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5639 return PARSE_OPERAND_FAIL
;
5640 /* If the offset is 0, find out if it's a +0 or -0. */
5641 if (inst
.reloc
.exp
.X_op
== O_constant
5642 && inst
.reloc
.exp
.X_add_number
== 0)
5644 skip_whitespace (q
);
5648 skip_whitespace (q
);
5651 inst
.operands
[i
].negative
= 1;
5656 else if (skip_past_char (&p
, ':') == SUCCESS
)
5658 /* FIXME: '@' should be used here, but it's filtered out by generic code
5659 before we get to see it here. This may be subject to change. */
5660 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5662 if (result
!= PARSE_OPERAND_SUCCESS
)
5666 if (skip_past_char (&p
, ']') == FAIL
)
5668 inst
.error
= _("']' expected");
5669 return PARSE_OPERAND_FAIL
;
5672 if (skip_past_char (&p
, '!') == SUCCESS
)
5673 inst
.operands
[i
].writeback
= 1;
5675 else if (skip_past_comma (&p
) == SUCCESS
)
5677 if (skip_past_char (&p
, '{') == SUCCESS
)
5679 /* [Rn], {expr} - unindexed, with option */
5680 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5681 0, 255, TRUE
) == FAIL
)
5682 return PARSE_OPERAND_FAIL
;
5684 if (skip_past_char (&p
, '}') == FAIL
)
5686 inst
.error
= _("'}' expected at end of 'option' field");
5687 return PARSE_OPERAND_FAIL
;
5689 if (inst
.operands
[i
].preind
)
5691 inst
.error
= _("cannot combine index with option");
5692 return PARSE_OPERAND_FAIL
;
5695 return PARSE_OPERAND_SUCCESS
;
5699 inst
.operands
[i
].postind
= 1;
5700 inst
.operands
[i
].writeback
= 1;
5702 if (inst
.operands
[i
].preind
)
5704 inst
.error
= _("cannot combine pre- and post-indexing");
5705 return PARSE_OPERAND_FAIL
;
5709 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5711 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5713 /* We might be using the immediate for alignment already. If we
5714 are, OR the register number into the low-order bits. */
5715 if (inst
.operands
[i
].immisalign
)
5716 inst
.operands
[i
].imm
|= reg
;
5718 inst
.operands
[i
].imm
= reg
;
5719 inst
.operands
[i
].immisreg
= 1;
5721 if (skip_past_comma (&p
) == SUCCESS
)
5722 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5723 return PARSE_OPERAND_FAIL
;
5729 if (inst
.operands
[i
].negative
)
5731 inst
.operands
[i
].negative
= 0;
5734 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5735 return PARSE_OPERAND_FAIL
;
5736 /* If the offset is 0, find out if it's a +0 or -0. */
5737 if (inst
.reloc
.exp
.X_op
== O_constant
5738 && inst
.reloc
.exp
.X_add_number
== 0)
5740 skip_whitespace (q
);
5744 skip_whitespace (q
);
5747 inst
.operands
[i
].negative
= 1;
5753 /* If at this point neither .preind nor .postind is set, we have a
5754 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5755 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5757 inst
.operands
[i
].preind
= 1;
5758 inst
.reloc
.exp
.X_op
= O_constant
;
5759 inst
.reloc
.exp
.X_add_number
= 0;
5762 return PARSE_OPERAND_SUCCESS
;
5766 parse_address (char **str
, int i
)
5768 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5772 static parse_operand_result
5773 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5775 return parse_address_main (str
, i
, 1, type
);
5778 /* Parse an operand for a MOVW or MOVT instruction. */
5780 parse_half (char **str
)
5785 skip_past_char (&p
, '#');
5786 if (strncasecmp (p
, ":lower16:", 9) == 0)
5787 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5788 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5789 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5791 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5794 skip_whitespace (p
);
5797 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5800 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5802 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5804 inst
.error
= _("constant expression expected");
5807 if (inst
.reloc
.exp
.X_add_number
< 0
5808 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5810 inst
.error
= _("immediate value out of range");
5818 /* Miscellaneous. */
5820 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5821 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5823 parse_psr (char **str
, bfd_boolean lhs
)
5826 unsigned long psr_field
;
5827 const struct asm_psr
*psr
;
5829 bfd_boolean is_apsr
= FALSE
;
5830 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5832 /* PR gas/12698: If the user has specified -march=all then m_profile will
5833 be TRUE, but we want to ignore it in this case as we are building for any
5834 CPU type, including non-m variants. */
5835 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5838 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5839 feature for ease of use and backwards compatibility. */
5841 if (strncasecmp (p
, "SPSR", 4) == 0)
5844 goto unsupported_psr
;
5846 psr_field
= SPSR_BIT
;
5848 else if (strncasecmp (p
, "CPSR", 4) == 0)
5851 goto unsupported_psr
;
5855 else if (strncasecmp (p
, "APSR", 4) == 0)
5857 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5858 and ARMv7-R architecture CPUs. */
5867 while (ISALNUM (*p
) || *p
== '_');
5869 if (strncasecmp (start
, "iapsr", 5) == 0
5870 || strncasecmp (start
, "eapsr", 5) == 0
5871 || strncasecmp (start
, "xpsr", 4) == 0
5872 || strncasecmp (start
, "psr", 3) == 0)
5873 p
= start
+ strcspn (start
, "rR") + 1;
5875 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5881 /* If APSR is being written, a bitfield may be specified. Note that
5882 APSR itself is handled above. */
5883 if (psr
->field
<= 3)
5885 psr_field
= psr
->field
;
5891 /* M-profile MSR instructions have the mask field set to "10", except
5892 *PSR variants which modify APSR, which may use a different mask (and
5893 have been handled already). Do that by setting the PSR_f field
5895 return psr
->field
| (lhs
? PSR_f
: 0);
5898 goto unsupported_psr
;
5904 /* A suffix follows. */
5910 while (ISALNUM (*p
) || *p
== '_');
5914 /* APSR uses a notation for bits, rather than fields. */
5915 unsigned int nzcvq_bits
= 0;
5916 unsigned int g_bit
= 0;
5919 for (bit
= start
; bit
!= p
; bit
++)
5921 switch (TOLOWER (*bit
))
5924 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5928 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5932 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5936 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5940 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5944 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5948 inst
.error
= _("unexpected bit specified after APSR");
5953 if (nzcvq_bits
== 0x1f)
5958 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5960 inst
.error
= _("selected processor does not "
5961 "support DSP extension");
5968 if ((nzcvq_bits
& 0x20) != 0
5969 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5970 || (g_bit
& 0x2) != 0)
5972 inst
.error
= _("bad bitmask specified after APSR");
5978 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5983 psr_field
|= psr
->field
;
5989 goto error
; /* Garbage after "[CS]PSR". */
5991 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5992 is deprecated, but allow it anyway. */
5996 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5999 else if (!m_profile
)
6000 /* These bits are never right for M-profile devices: don't set them
6001 (only code paths which read/write APSR reach here). */
6002 psr_field
|= (PSR_c
| PSR_f
);
6008 inst
.error
= _("selected processor does not support requested special "
6009 "purpose register");
6013 inst
.error
= _("flag for {c}psr instruction expected");
6017 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6018 value suitable for splatting into the AIF field of the instruction. */
6021 parse_cps_flags (char **str
)
6030 case '\0': case ',':
6033 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6034 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6035 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6038 inst
.error
= _("unrecognized CPS flag");
6043 if (saw_a_flag
== 0)
6045 inst
.error
= _("missing CPS flags");
6053 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6054 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6057 parse_endian_specifier (char **str
)
6062 if (strncasecmp (s
, "BE", 2))
6064 else if (strncasecmp (s
, "LE", 2))
6068 inst
.error
= _("valid endian specifiers are be or le");
6072 if (ISALNUM (s
[2]) || s
[2] == '_')
6074 inst
.error
= _("valid endian specifiers are be or le");
6079 return little_endian
;
6082 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6083 value suitable for poking into the rotate field of an sxt or sxta
6084 instruction, or FAIL on error. */
6087 parse_ror (char **str
)
6092 if (strncasecmp (s
, "ROR", 3) == 0)
6096 inst
.error
= _("missing rotation field after comma");
6100 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6105 case 0: *str
= s
; return 0x0;
6106 case 8: *str
= s
; return 0x1;
6107 case 16: *str
= s
; return 0x2;
6108 case 24: *str
= s
; return 0x3;
6111 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6116 /* Parse a conditional code (from conds[] below). The value returned is in the
6117 range 0 .. 14, or FAIL. */
6119 parse_cond (char **str
)
6122 const struct asm_cond
*c
;
6124 /* Condition codes are always 2 characters, so matching up to
6125 3 characters is sufficient. */
6130 while (ISALPHA (*q
) && n
< 3)
6132 cond
[n
] = TOLOWER (*q
);
6137 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6140 inst
.error
= _("condition required");
6148 /* Record a use of the given feature. */
6150 record_feature_use (const arm_feature_set
*feature
)
6153 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6155 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6158 /* If the given feature available in the selected CPU, mark it as used.
6159 Returns TRUE iff feature is available. */
6161 mark_feature_used (const arm_feature_set
*feature
)
6163 /* Ensure the option is valid on the current architecture. */
6164 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6167 /* Add the appropriate architecture feature for the barrier option used.
6169 record_feature_use (feature
);
6174 /* Parse an option for a barrier instruction. Returns the encoding for the
6177 parse_barrier (char **str
)
6180 const struct asm_barrier_opt
*o
;
6183 while (ISALPHA (*q
))
6186 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6191 if (!mark_feature_used (&o
->arch
))
6198 /* Parse the operands of a table branch instruction. Similar to a memory
6201 parse_tb (char **str
)
6206 if (skip_past_char (&p
, '[') == FAIL
)
6208 inst
.error
= _("'[' expected");
6212 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6214 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6217 inst
.operands
[0].reg
= reg
;
6219 if (skip_past_comma (&p
) == FAIL
)
6221 inst
.error
= _("',' expected");
6225 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6227 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6230 inst
.operands
[0].imm
= reg
;
6232 if (skip_past_comma (&p
) == SUCCESS
)
6234 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6236 if (inst
.reloc
.exp
.X_add_number
!= 1)
6238 inst
.error
= _("invalid shift");
6241 inst
.operands
[0].shifted
= 1;
6244 if (skip_past_char (&p
, ']') == FAIL
)
6246 inst
.error
= _("']' expected");
6253 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6254 information on the types the operands can take and how they are encoded.
6255 Up to four operands may be read; this function handles setting the
6256 ".present" field for each read operand itself.
6257 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6258 else returns FAIL. */
6261 parse_neon_mov (char **str
, int *which_operand
)
6263 int i
= *which_operand
, val
;
6264 enum arm_reg_type rtype
;
6266 struct neon_type_el optype
;
6268 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6270 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6271 inst
.operands
[i
].reg
= val
;
6272 inst
.operands
[i
].isscalar
= 1;
6273 inst
.operands
[i
].vectype
= optype
;
6274 inst
.operands
[i
++].present
= 1;
6276 if (skip_past_comma (&ptr
) == FAIL
)
6279 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6282 inst
.operands
[i
].reg
= val
;
6283 inst
.operands
[i
].isreg
= 1;
6284 inst
.operands
[i
].present
= 1;
6286 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6289 /* Cases 0, 1, 2, 3, 5 (D only). */
6290 if (skip_past_comma (&ptr
) == FAIL
)
6293 inst
.operands
[i
].reg
= val
;
6294 inst
.operands
[i
].isreg
= 1;
6295 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6296 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6297 inst
.operands
[i
].isvec
= 1;
6298 inst
.operands
[i
].vectype
= optype
;
6299 inst
.operands
[i
++].present
= 1;
6301 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6303 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6304 Case 13: VMOV <Sd>, <Rm> */
6305 inst
.operands
[i
].reg
= val
;
6306 inst
.operands
[i
].isreg
= 1;
6307 inst
.operands
[i
].present
= 1;
6309 if (rtype
== REG_TYPE_NQ
)
6311 first_error (_("can't use Neon quad register here"));
6314 else if (rtype
!= REG_TYPE_VFS
)
6317 if (skip_past_comma (&ptr
) == FAIL
)
6319 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6321 inst
.operands
[i
].reg
= val
;
6322 inst
.operands
[i
].isreg
= 1;
6323 inst
.operands
[i
].present
= 1;
6326 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6329 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6330 Case 1: VMOV<c><q> <Dd>, <Dm>
6331 Case 8: VMOV.F32 <Sd>, <Sm>
6332 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6334 inst
.operands
[i
].reg
= val
;
6335 inst
.operands
[i
].isreg
= 1;
6336 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6337 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6338 inst
.operands
[i
].isvec
= 1;
6339 inst
.operands
[i
].vectype
= optype
;
6340 inst
.operands
[i
].present
= 1;
6342 if (skip_past_comma (&ptr
) == SUCCESS
)
6347 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6350 inst
.operands
[i
].reg
= val
;
6351 inst
.operands
[i
].isreg
= 1;
6352 inst
.operands
[i
++].present
= 1;
6354 if (skip_past_comma (&ptr
) == FAIL
)
6357 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6360 inst
.operands
[i
].reg
= val
;
6361 inst
.operands
[i
].isreg
= 1;
6362 inst
.operands
[i
].present
= 1;
6365 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6366 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6367 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6368 Case 10: VMOV.F32 <Sd>, #<imm>
6369 Case 11: VMOV.F64 <Dd>, #<imm> */
6370 inst
.operands
[i
].immisfloat
= 1;
6371 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6373 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6374 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6378 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6382 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6385 inst
.operands
[i
].reg
= val
;
6386 inst
.operands
[i
].isreg
= 1;
6387 inst
.operands
[i
++].present
= 1;
6389 if (skip_past_comma (&ptr
) == FAIL
)
6392 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6394 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6395 inst
.operands
[i
].reg
= val
;
6396 inst
.operands
[i
].isscalar
= 1;
6397 inst
.operands
[i
].present
= 1;
6398 inst
.operands
[i
].vectype
= optype
;
6400 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6402 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6403 inst
.operands
[i
].reg
= val
;
6404 inst
.operands
[i
].isreg
= 1;
6405 inst
.operands
[i
++].present
= 1;
6407 if (skip_past_comma (&ptr
) == FAIL
)
6410 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6413 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6417 inst
.operands
[i
].reg
= val
;
6418 inst
.operands
[i
].isreg
= 1;
6419 inst
.operands
[i
].isvec
= 1;
6420 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6421 inst
.operands
[i
].vectype
= optype
;
6422 inst
.operands
[i
].present
= 1;
6424 if (rtype
== REG_TYPE_VFS
)
6428 if (skip_past_comma (&ptr
) == FAIL
)
6430 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6433 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6436 inst
.operands
[i
].reg
= val
;
6437 inst
.operands
[i
].isreg
= 1;
6438 inst
.operands
[i
].isvec
= 1;
6439 inst
.operands
[i
].issingle
= 1;
6440 inst
.operands
[i
].vectype
= optype
;
6441 inst
.operands
[i
].present
= 1;
6444 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6448 inst
.operands
[i
].reg
= val
;
6449 inst
.operands
[i
].isreg
= 1;
6450 inst
.operands
[i
].isvec
= 1;
6451 inst
.operands
[i
].issingle
= 1;
6452 inst
.operands
[i
].vectype
= optype
;
6453 inst
.operands
[i
].present
= 1;
6458 first_error (_("parse error"));
6462 /* Successfully parsed the operands. Update args. */
6468 first_error (_("expected comma"));
6472 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6476 /* Use this macro when the operand constraints are different
6477 for ARM and THUMB (e.g. ldrd). */
6478 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6479 ((arm_operand) | ((thumb_operand) << 16))
6481 /* Matcher codes for parse_operands. */
6482 enum operand_parse_code
6484 OP_stop
, /* end of line */
6486 OP_RR
, /* ARM register */
6487 OP_RRnpc
, /* ARM register, not r15 */
6488 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6489 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6490 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6491 optional trailing ! */
6492 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6493 OP_RCP
, /* Coprocessor number */
6494 OP_RCN
, /* Coprocessor register */
6495 OP_RF
, /* FPA register */
6496 OP_RVS
, /* VFP single precision register */
6497 OP_RVD
, /* VFP double precision register (0..15) */
6498 OP_RND
, /* Neon double precision register (0..31) */
6499 OP_RNQ
, /* Neon quad precision register */
6500 OP_RVSD
, /* VFP single or double precision register */
6501 OP_RNSD
, /* Neon single or double precision register */
6502 OP_RNDQ
, /* Neon double or quad precision register */
6503 OP_RNSDQ
, /* Neon single, double or quad precision register */
6504 OP_RNSC
, /* Neon scalar D[X] */
6505 OP_RVC
, /* VFP control register */
6506 OP_RMF
, /* Maverick F register */
6507 OP_RMD
, /* Maverick D register */
6508 OP_RMFX
, /* Maverick FX register */
6509 OP_RMDX
, /* Maverick DX register */
6510 OP_RMAX
, /* Maverick AX register */
6511 OP_RMDS
, /* Maverick DSPSC register */
6512 OP_RIWR
, /* iWMMXt wR register */
6513 OP_RIWC
, /* iWMMXt wC register */
6514 OP_RIWG
, /* iWMMXt wCG register */
6515 OP_RXA
, /* XScale accumulator register */
6517 OP_REGLST
, /* ARM register list */
6518 OP_VRSLST
, /* VFP single-precision register list */
6519 OP_VRDLST
, /* VFP double-precision register list */
6520 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6521 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6522 OP_NSTRLST
, /* Neon element/structure list */
6524 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6525 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6526 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6527 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6528 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6529 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6530 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6531 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6532 OP_VMOV
, /* Neon VMOV operands. */
6533 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6534 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6535 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6537 OP_I0
, /* immediate zero */
6538 OP_I7
, /* immediate value 0 .. 7 */
6539 OP_I15
, /* 0 .. 15 */
6540 OP_I16
, /* 1 .. 16 */
6541 OP_I16z
, /* 0 .. 16 */
6542 OP_I31
, /* 0 .. 31 */
6543 OP_I31w
, /* 0 .. 31, optional trailing ! */
6544 OP_I32
, /* 1 .. 32 */
6545 OP_I32z
, /* 0 .. 32 */
6546 OP_I63
, /* 0 .. 63 */
6547 OP_I63s
, /* -64 .. 63 */
6548 OP_I64
, /* 1 .. 64 */
6549 OP_I64z
, /* 0 .. 64 */
6550 OP_I255
, /* 0 .. 255 */
6552 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6553 OP_I7b
, /* 0 .. 7 */
6554 OP_I15b
, /* 0 .. 15 */
6555 OP_I31b
, /* 0 .. 31 */
6557 OP_SH
, /* shifter operand */
6558 OP_SHG
, /* shifter operand with possible group relocation */
6559 OP_ADDR
, /* Memory address expression (any mode) */
6560 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6561 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6562 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6563 OP_EXP
, /* arbitrary expression */
6564 OP_EXPi
, /* same, with optional immediate prefix */
6565 OP_EXPr
, /* same, with optional relocation suffix */
6566 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6567 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6568 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6570 OP_CPSF
, /* CPS flags */
6571 OP_ENDI
, /* Endianness specifier */
6572 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6573 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6574 OP_COND
, /* conditional code */
6575 OP_TB
, /* Table branch. */
6577 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6579 OP_RRnpc_I0
, /* ARM register or literal 0 */
6580 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
6581 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6582 OP_RF_IF
, /* FPA register or immediate */
6583 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6584 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6586 /* Optional operands. */
6587 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6588 OP_oI31b
, /* 0 .. 31 */
6589 OP_oI32b
, /* 1 .. 32 */
6590 OP_oI32z
, /* 0 .. 32 */
6591 OP_oIffffb
, /* 0 .. 65535 */
6592 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6594 OP_oRR
, /* ARM register */
6595 OP_oRRnpc
, /* ARM register, not the PC */
6596 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6597 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6598 OP_oRND
, /* Optional Neon double precision register */
6599 OP_oRNQ
, /* Optional Neon quad precision register */
6600 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6601 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6602 OP_oSHll
, /* LSL immediate */
6603 OP_oSHar
, /* ASR immediate */
6604 OP_oSHllar
, /* LSL or ASR immediate */
6605 OP_oROR
, /* ROR 0/8/16/24 */
6606 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6608 /* Some pre-defined mixed (ARM/THUMB) operands. */
6609 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6610 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6611 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6613 OP_FIRST_OPTIONAL
= OP_oI7b
6616 /* Generic instruction operand parser. This does no encoding and no
6617 semantic validation; it merely squirrels values away in the inst
6618 structure. Returns SUCCESS or FAIL depending on whether the
6619 specified grammar matched. */
6621 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6623 unsigned const int *upat
= pattern
;
6624 char *backtrack_pos
= 0;
6625 const char *backtrack_error
= 0;
6626 int i
, val
= 0, backtrack_index
= 0;
6627 enum arm_reg_type rtype
;
6628 parse_operand_result result
;
6629 unsigned int op_parse_code
;
6631 #define po_char_or_fail(chr) \
6634 if (skip_past_char (&str, chr) == FAIL) \
6639 #define po_reg_or_fail(regtype) \
6642 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6643 & inst.operands[i].vectype); \
6646 first_error (_(reg_expected_msgs[regtype])); \
6649 inst.operands[i].reg = val; \
6650 inst.operands[i].isreg = 1; \
6651 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6652 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6653 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6654 || rtype == REG_TYPE_VFD \
6655 || rtype == REG_TYPE_NQ); \
6659 #define po_reg_or_goto(regtype, label) \
6662 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6663 & inst.operands[i].vectype); \
6667 inst.operands[i].reg = val; \
6668 inst.operands[i].isreg = 1; \
6669 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6670 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6671 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6672 || rtype == REG_TYPE_VFD \
6673 || rtype == REG_TYPE_NQ); \
6677 #define po_imm_or_fail(min, max, popt) \
6680 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6682 inst.operands[i].imm = val; \
6686 #define po_scalar_or_goto(elsz, label) \
6689 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6692 inst.operands[i].reg = val; \
6693 inst.operands[i].isscalar = 1; \
6697 #define po_misc_or_fail(expr) \
6705 #define po_misc_or_fail_no_backtrack(expr) \
6709 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6710 backtrack_pos = 0; \
6711 if (result != PARSE_OPERAND_SUCCESS) \
6716 #define po_barrier_or_imm(str) \
6719 val = parse_barrier (&str); \
6720 if (val == FAIL && ! ISALPHA (*str)) \
6723 /* ISB can only take SY as an option. */ \
6724 || ((inst.instruction & 0xf0) == 0x60 \
6727 inst.error = _("invalid barrier type"); \
6728 backtrack_pos = 0; \
6734 skip_whitespace (str
);
6736 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6738 op_parse_code
= upat
[i
];
6739 if (op_parse_code
>= 1<<16)
6740 op_parse_code
= thumb
? (op_parse_code
>> 16)
6741 : (op_parse_code
& ((1<<16)-1));
6743 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6745 /* Remember where we are in case we need to backtrack. */
6746 gas_assert (!backtrack_pos
);
6747 backtrack_pos
= str
;
6748 backtrack_error
= inst
.error
;
6749 backtrack_index
= i
;
6752 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6753 po_char_or_fail (',');
6755 switch (op_parse_code
)
6763 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6764 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6765 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6766 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6767 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6768 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6770 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6772 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6774 /* Also accept generic coprocessor regs for unknown registers. */
6776 po_reg_or_fail (REG_TYPE_CN
);
6778 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6779 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6780 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6781 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6782 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6783 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6784 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6785 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6786 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6787 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6789 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6790 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
6792 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6793 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6795 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6797 /* Neon scalar. Using an element size of 8 means that some invalid
6798 scalars are accepted here, so deal with those in later code. */
6799 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6803 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6806 po_imm_or_fail (0, 0, TRUE
);
6811 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6816 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6819 if (parse_ifimm_zero (&str
))
6820 inst
.operands
[i
].imm
= 0;
6824 = _("only floating point zero is allowed as immediate value");
6832 po_scalar_or_goto (8, try_rr
);
6835 po_reg_or_fail (REG_TYPE_RN
);
6841 po_scalar_or_goto (8, try_nsdq
);
6844 po_reg_or_fail (REG_TYPE_NSDQ
);
6850 po_scalar_or_goto (8, try_s_scalar
);
6853 po_scalar_or_goto (4, try_nsd
);
6856 po_reg_or_fail (REG_TYPE_NSD
);
6862 po_scalar_or_goto (8, try_ndq
);
6865 po_reg_or_fail (REG_TYPE_NDQ
);
6871 po_scalar_or_goto (8, try_vfd
);
6874 po_reg_or_fail (REG_TYPE_VFD
);
6879 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6880 not careful then bad things might happen. */
6881 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6886 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6889 /* There's a possibility of getting a 64-bit immediate here, so
6890 we need special handling. */
6891 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6894 inst
.error
= _("immediate value is out of range");
6902 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6905 po_imm_or_fail (0, 63, TRUE
);
6910 po_char_or_fail ('[');
6911 po_reg_or_fail (REG_TYPE_RN
);
6912 po_char_or_fail (']');
6918 po_reg_or_fail (REG_TYPE_RN
);
6919 if (skip_past_char (&str
, '!') == SUCCESS
)
6920 inst
.operands
[i
].writeback
= 1;
6924 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6925 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6926 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6927 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6928 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6929 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6930 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6931 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6932 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6933 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6934 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6935 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6937 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6939 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6940 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6942 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6943 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6944 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6945 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6947 /* Immediate variants */
6949 po_char_or_fail ('{');
6950 po_imm_or_fail (0, 255, TRUE
);
6951 po_char_or_fail ('}');
6955 /* The expression parser chokes on a trailing !, so we have
6956 to find it first and zap it. */
6959 while (*s
&& *s
!= ',')
6964 inst
.operands
[i
].writeback
= 1;
6966 po_imm_or_fail (0, 31, TRUE
);
6974 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6979 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6984 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6986 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6988 val
= parse_reloc (&str
);
6991 inst
.error
= _("unrecognized relocation suffix");
6994 else if (val
!= BFD_RELOC_UNUSED
)
6996 inst
.operands
[i
].imm
= val
;
6997 inst
.operands
[i
].hasreloc
= 1;
7002 /* Operand for MOVW or MOVT. */
7004 po_misc_or_fail (parse_half (&str
));
7007 /* Register or expression. */
7008 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7009 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7011 /* Register or immediate. */
7012 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7013 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7015 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7017 if (!is_immediate_prefix (*str
))
7020 val
= parse_fpa_immediate (&str
);
7023 /* FPA immediates are encoded as registers 8-15.
7024 parse_fpa_immediate has already applied the offset. */
7025 inst
.operands
[i
].reg
= val
;
7026 inst
.operands
[i
].isreg
= 1;
7029 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7030 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7032 /* Two kinds of register. */
7035 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7037 || (rege
->type
!= REG_TYPE_MMXWR
7038 && rege
->type
!= REG_TYPE_MMXWC
7039 && rege
->type
!= REG_TYPE_MMXWCG
))
7041 inst
.error
= _("iWMMXt data or control register expected");
7044 inst
.operands
[i
].reg
= rege
->number
;
7045 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7051 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7053 || (rege
->type
!= REG_TYPE_MMXWC
7054 && rege
->type
!= REG_TYPE_MMXWCG
))
7056 inst
.error
= _("iWMMXt control register expected");
7059 inst
.operands
[i
].reg
= rege
->number
;
7060 inst
.operands
[i
].isreg
= 1;
7065 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7066 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7067 case OP_oROR
: val
= parse_ror (&str
); break;
7068 case OP_COND
: val
= parse_cond (&str
); break;
7069 case OP_oBARRIER_I15
:
7070 po_barrier_or_imm (str
); break;
7072 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7078 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7079 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7081 inst
.error
= _("Banked registers are not available with this "
7087 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7091 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7094 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7096 if (strncasecmp (str
, "APSR_", 5) == 0)
7103 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7104 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7105 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7106 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7107 default: found
= 16;
7111 inst
.operands
[i
].isvec
= 1;
7112 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7113 inst
.operands
[i
].reg
= REG_PC
;
7120 po_misc_or_fail (parse_tb (&str
));
7123 /* Register lists. */
7125 val
= parse_reg_list (&str
);
7128 inst
.operands
[i
].writeback
= 1;
7134 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7138 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7142 /* Allow Q registers too. */
7143 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7148 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7150 inst
.operands
[i
].issingle
= 1;
7155 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7160 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7161 &inst
.operands
[i
].vectype
);
7164 /* Addressing modes */
7166 po_misc_or_fail (parse_address (&str
, i
));
7170 po_misc_or_fail_no_backtrack (
7171 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7175 po_misc_or_fail_no_backtrack (
7176 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7180 po_misc_or_fail_no_backtrack (
7181 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7185 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7189 po_misc_or_fail_no_backtrack (
7190 parse_shifter_operand_group_reloc (&str
, i
));
7194 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7198 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7202 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7206 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7209 /* Various value-based sanity checks and shared operations. We
7210 do not signal immediate failures for the register constraints;
7211 this allows a syntax error to take precedence. */
7212 switch (op_parse_code
)
7220 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7221 inst
.error
= BAD_PC
;
7226 if (inst
.operands
[i
].isreg
)
7228 if (inst
.operands
[i
].reg
== REG_PC
)
7229 inst
.error
= BAD_PC
;
7230 else if (inst
.operands
[i
].reg
== REG_SP
7231 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7232 relaxed since ARMv8-A. */
7233 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7236 inst
.error
= BAD_SP
;
7242 if (inst
.operands
[i
].isreg
7243 && inst
.operands
[i
].reg
== REG_PC
7244 && (inst
.operands
[i
].writeback
|| thumb
))
7245 inst
.error
= BAD_PC
;
7254 case OP_oBARRIER_I15
:
7263 inst
.operands
[i
].imm
= val
;
7270 /* If we get here, this operand was successfully parsed. */
7271 inst
.operands
[i
].present
= 1;
7275 inst
.error
= BAD_ARGS
;
7280 /* The parse routine should already have set inst.error, but set a
7281 default here just in case. */
7283 inst
.error
= _("syntax error");
7287 /* Do not backtrack over a trailing optional argument that
7288 absorbed some text. We will only fail again, with the
7289 'garbage following instruction' error message, which is
7290 probably less helpful than the current one. */
7291 if (backtrack_index
== i
&& backtrack_pos
!= str
7292 && upat
[i
+1] == OP_stop
)
7295 inst
.error
= _("syntax error");
7299 /* Try again, skipping the optional argument at backtrack_pos. */
7300 str
= backtrack_pos
;
7301 inst
.error
= backtrack_error
;
7302 inst
.operands
[backtrack_index
].present
= 0;
7303 i
= backtrack_index
;
7307 /* Check that we have parsed all the arguments. */
7308 if (*str
!= '\0' && !inst
.error
)
7309 inst
.error
= _("garbage following instruction");
7311 return inst
.error
? FAIL
: SUCCESS
;
7314 #undef po_char_or_fail
7315 #undef po_reg_or_fail
7316 #undef po_reg_or_goto
7317 #undef po_imm_or_fail
7318 #undef po_scalar_or_fail
7319 #undef po_barrier_or_imm
7321 /* Shorthand macro for instruction encoding functions issuing errors. */
7322 #define constraint(expr, err) \
7333 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7334 instructions are unpredictable if these registers are used. This
7335 is the BadReg predicate in ARM's Thumb-2 documentation.
7337 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7338 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7339 #define reject_bad_reg(reg) \
7341 if (reg == REG_PC) \
7343 inst.error = BAD_PC; \
7346 else if (reg == REG_SP \
7347 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7349 inst.error = BAD_SP; \
7354 /* If REG is R13 (the stack pointer), warn that its use is
7356 #define warn_deprecated_sp(reg) \
7358 if (warn_on_deprecated && reg == REG_SP) \
7359 as_tsktsk (_("use of r13 is deprecated")); \
7362 /* Functions for operand encoding. ARM, then Thumb. */
7364 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7366 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7368 The only binary encoding difference is the Coprocessor number. Coprocessor
7369 9 is used for half-precision calculations or conversions. The format of the
7370 instruction is the same as the equivalent Coprocessor 10 instruction that
7371 exists for Single-Precision operation. */
7374 do_scalar_fp16_v82_encode (void)
7376 if (inst
.cond
!= COND_ALWAYS
)
7377 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7378 " the behaviour is UNPREDICTABLE"));
7379 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7382 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7383 mark_feature_used (&arm_ext_fp16
);
7386 /* If VAL can be encoded in the immediate field of an ARM instruction,
7387 return the encoded form. Otherwise, return FAIL. */
7390 encode_arm_immediate (unsigned int val
)
7397 for (i
= 2; i
< 32; i
+= 2)
7398 if ((a
= rotate_left (val
, i
)) <= 0xff)
7399 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7404 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7405 return the encoded form. Otherwise, return FAIL. */
7407 encode_thumb32_immediate (unsigned int val
)
7414 for (i
= 1; i
<= 24; i
++)
7417 if ((val
& ~(0xff << i
)) == 0)
7418 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7422 if (val
== ((a
<< 16) | a
))
7424 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7428 if (val
== ((a
<< 16) | a
))
7429 return 0x200 | (a
>> 8);
7433 /* Encode a VFP SP or DP register number into inst.instruction. */
7436 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7438 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7441 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7444 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7447 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7452 first_error (_("D register out of range for selected VFP version"));
7460 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7464 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7468 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7472 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7476 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7480 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7488 /* Encode a <shift> in an ARM-format instruction. The immediate,
7489 if any, is handled by md_apply_fix. */
7491 encode_arm_shift (int i
)
7493 /* register-shifted register. */
7494 if (inst
.operands
[i
].immisreg
)
7497 for (op_index
= 0; op_index
<= i
; ++op_index
)
7499 /* Check the operand only when it's presented. In pre-UAL syntax,
7500 if the destination register is the same as the first operand, two
7501 register form of the instruction can be used. */
7502 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
7503 && inst
.operands
[op_index
].reg
== REG_PC
)
7504 as_warn (UNPRED_REG ("r15"));
7507 if (inst
.operands
[i
].imm
== REG_PC
)
7508 as_warn (UNPRED_REG ("r15"));
7511 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7512 inst
.instruction
|= SHIFT_ROR
<< 5;
7515 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7516 if (inst
.operands
[i
].immisreg
)
7518 inst
.instruction
|= SHIFT_BY_REG
;
7519 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7522 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7527 encode_arm_shifter_operand (int i
)
7529 if (inst
.operands
[i
].isreg
)
7531 inst
.instruction
|= inst
.operands
[i
].reg
;
7532 encode_arm_shift (i
);
7536 inst
.instruction
|= INST_IMMEDIATE
;
7537 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7538 inst
.instruction
|= inst
.operands
[i
].imm
;
7542 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7544 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7547 Generate an error if the operand is not a register. */
7548 constraint (!inst
.operands
[i
].isreg
,
7549 _("Instruction does not support =N addresses"));
7551 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7553 if (inst
.operands
[i
].preind
)
7557 inst
.error
= _("instruction does not accept preindexed addressing");
7560 inst
.instruction
|= PRE_INDEX
;
7561 if (inst
.operands
[i
].writeback
)
7562 inst
.instruction
|= WRITE_BACK
;
7565 else if (inst
.operands
[i
].postind
)
7567 gas_assert (inst
.operands
[i
].writeback
);
7569 inst
.instruction
|= WRITE_BACK
;
7571 else /* unindexed - only for coprocessor */
7573 inst
.error
= _("instruction does not accept unindexed addressing");
7577 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7578 && (((inst
.instruction
& 0x000f0000) >> 16)
7579 == ((inst
.instruction
& 0x0000f000) >> 12)))
7580 as_warn ((inst
.instruction
& LOAD_BIT
)
7581 ? _("destination register same as write-back base")
7582 : _("source register same as write-back base"));
7585 /* inst.operands[i] was set up by parse_address. Encode it into an
7586 ARM-format mode 2 load or store instruction. If is_t is true,
7587 reject forms that cannot be used with a T instruction (i.e. not
7590 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7592 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7594 encode_arm_addr_mode_common (i
, is_t
);
7596 if (inst
.operands
[i
].immisreg
)
7598 constraint ((inst
.operands
[i
].imm
== REG_PC
7599 || (is_pc
&& inst
.operands
[i
].writeback
)),
7601 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7602 inst
.instruction
|= inst
.operands
[i
].imm
;
7603 if (!inst
.operands
[i
].negative
)
7604 inst
.instruction
|= INDEX_UP
;
7605 if (inst
.operands
[i
].shifted
)
7607 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7608 inst
.instruction
|= SHIFT_ROR
<< 5;
7611 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7612 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7616 else /* immediate offset in inst.reloc */
7618 if (is_pc
&& !inst
.reloc
.pc_rel
)
7620 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7622 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7623 cannot use PC in addressing.
7624 PC cannot be used in writeback addressing, either. */
7625 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7628 /* Use of PC in str is deprecated for ARMv7. */
7629 if (warn_on_deprecated
7631 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7632 as_tsktsk (_("use of PC in this instruction is deprecated"));
7635 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7637 /* Prefer + for zero encoded value. */
7638 if (!inst
.operands
[i
].negative
)
7639 inst
.instruction
|= INDEX_UP
;
7640 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7645 /* inst.operands[i] was set up by parse_address. Encode it into an
7646 ARM-format mode 3 load or store instruction. Reject forms that
7647 cannot be used with such instructions. If is_t is true, reject
7648 forms that cannot be used with a T instruction (i.e. not
7651 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7653 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7655 inst
.error
= _("instruction does not accept scaled register index");
7659 encode_arm_addr_mode_common (i
, is_t
);
7661 if (inst
.operands
[i
].immisreg
)
7663 constraint ((inst
.operands
[i
].imm
== REG_PC
7664 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7666 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7668 inst
.instruction
|= inst
.operands
[i
].imm
;
7669 if (!inst
.operands
[i
].negative
)
7670 inst
.instruction
|= INDEX_UP
;
7672 else /* immediate offset in inst.reloc */
7674 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7675 && inst
.operands
[i
].writeback
),
7677 inst
.instruction
|= HWOFFSET_IMM
;
7678 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7680 /* Prefer + for zero encoded value. */
7681 if (!inst
.operands
[i
].negative
)
7682 inst
.instruction
|= INDEX_UP
;
7684 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7689 /* Write immediate bits [7:0] to the following locations:
7691 |28/24|23 19|18 16|15 4|3 0|
7692 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7694 This function is used by VMOV/VMVN/VORR/VBIC. */
7697 neon_write_immbits (unsigned immbits
)
7699 inst
.instruction
|= immbits
& 0xf;
7700 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7701 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7704 /* Invert low-order SIZE bits of XHI:XLO. */
7707 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7709 unsigned immlo
= xlo
? *xlo
: 0;
7710 unsigned immhi
= xhi
? *xhi
: 0;
7715 immlo
= (~immlo
) & 0xff;
7719 immlo
= (~immlo
) & 0xffff;
7723 immhi
= (~immhi
) & 0xffffffff;
7727 immlo
= (~immlo
) & 0xffffffff;
7741 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7745 neon_bits_same_in_bytes (unsigned imm
)
7747 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7748 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7749 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7750 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7753 /* For immediate of above form, return 0bABCD. */
7756 neon_squash_bits (unsigned imm
)
7758 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7759 | ((imm
& 0x01000000) >> 21);
7762 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7765 neon_qfloat_bits (unsigned imm
)
7767 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7770 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7771 the instruction. *OP is passed as the initial value of the op field, and
7772 may be set to a different value depending on the constant (i.e.
7773 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7774 MVN). If the immediate looks like a repeated pattern then also
7775 try smaller element sizes. */
7778 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7779 unsigned *immbits
, int *op
, int size
,
7780 enum neon_el_type type
)
7782 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7784 if (type
== NT_float
&& !float_p
)
7787 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7789 if (size
!= 32 || *op
== 1)
7791 *immbits
= neon_qfloat_bits (immlo
);
7797 if (neon_bits_same_in_bytes (immhi
)
7798 && neon_bits_same_in_bytes (immlo
))
7802 *immbits
= (neon_squash_bits (immhi
) << 4)
7803 | neon_squash_bits (immlo
);
7814 if (immlo
== (immlo
& 0x000000ff))
7819 else if (immlo
== (immlo
& 0x0000ff00))
7821 *immbits
= immlo
>> 8;
7824 else if (immlo
== (immlo
& 0x00ff0000))
7826 *immbits
= immlo
>> 16;
7829 else if (immlo
== (immlo
& 0xff000000))
7831 *immbits
= immlo
>> 24;
7834 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7836 *immbits
= (immlo
>> 8) & 0xff;
7839 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7841 *immbits
= (immlo
>> 16) & 0xff;
7845 if ((immlo
& 0xffff) != (immlo
>> 16))
7852 if (immlo
== (immlo
& 0x000000ff))
7857 else if (immlo
== (immlo
& 0x0000ff00))
7859 *immbits
= immlo
>> 8;
7863 if ((immlo
& 0xff) != (immlo
>> 8))
7868 if (immlo
== (immlo
& 0x000000ff))
7870 /* Don't allow MVN with 8-bit immediate. */
7880 #if defined BFD_HOST_64_BIT
7881 /* Returns TRUE if double precision value V may be cast
7882 to single precision without loss of accuracy. */
7885 is_double_a_single (bfd_int64_t v
)
7887 int exp
= (int)((v
>> 52) & 0x7FF);
7888 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7890 return (exp
== 0 || exp
== 0x7FF
7891 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7892 && (mantissa
& 0x1FFFFFFFl
) == 0;
7895 /* Returns a double precision value casted to single precision
7896 (ignoring the least significant bits in exponent and mantissa). */
7899 double_to_single (bfd_int64_t v
)
7901 int sign
= (int) ((v
>> 63) & 1l);
7902 int exp
= (int) ((v
>> 52) & 0x7FF);
7903 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7909 exp
= exp
- 1023 + 127;
7918 /* No denormalized numbers. */
7924 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7926 #endif /* BFD_HOST_64_BIT */
7935 static void do_vfp_nsyn_opcode (const char *);
7937 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7938 Determine whether it can be performed with a move instruction; if
7939 it can, convert inst.instruction to that move instruction and
7940 return TRUE; if it can't, convert inst.instruction to a literal-pool
7941 load and return FALSE. If this is not a valid thing to do in the
7942 current context, set inst.error and return TRUE.
7944 inst.operands[i] describes the destination register. */
7947 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7950 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7951 bfd_boolean arm_p
= (t
== CONST_ARM
);
7954 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7958 if ((inst
.instruction
& tbit
) == 0)
7960 inst
.error
= _("invalid pseudo operation");
7964 if (inst
.reloc
.exp
.X_op
!= O_constant
7965 && inst
.reloc
.exp
.X_op
!= O_symbol
7966 && inst
.reloc
.exp
.X_op
!= O_big
)
7968 inst
.error
= _("constant expression expected");
7972 if (inst
.reloc
.exp
.X_op
== O_constant
7973 || inst
.reloc
.exp
.X_op
== O_big
)
7975 #if defined BFD_HOST_64_BIT
7980 if (inst
.reloc
.exp
.X_op
== O_big
)
7982 LITTLENUM_TYPE w
[X_PRECISION
];
7985 if (inst
.reloc
.exp
.X_add_number
== -1)
7987 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7989 /* FIXME: Should we check words w[2..5] ? */
7994 #if defined BFD_HOST_64_BIT
7996 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7997 << LITTLENUM_NUMBER_OF_BITS
)
7998 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7999 << LITTLENUM_NUMBER_OF_BITS
)
8000 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8001 << LITTLENUM_NUMBER_OF_BITS
)
8002 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8004 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8005 | (l
[0] & LITTLENUM_MASK
);
8009 v
= inst
.reloc
.exp
.X_add_number
;
8011 if (!inst
.operands
[i
].issingle
)
8015 /* LDR should not use lead in a flag-setting instruction being
8016 chosen so we do not check whether movs can be used. */
8018 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8019 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8020 && inst
.operands
[i
].reg
!= 13
8021 && inst
.operands
[i
].reg
!= 15)
8023 /* Check if on thumb2 it can be done with a mov.w, mvn or
8024 movw instruction. */
8025 unsigned int newimm
;
8026 bfd_boolean isNegated
;
8028 newimm
= encode_thumb32_immediate (v
);
8029 if (newimm
!= (unsigned int) FAIL
)
8033 newimm
= encode_thumb32_immediate (~v
);
8034 if (newimm
!= (unsigned int) FAIL
)
8038 /* The number can be loaded with a mov.w or mvn
8040 if (newimm
!= (unsigned int) FAIL
8041 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8043 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8044 | (inst
.operands
[i
].reg
<< 8));
8045 /* Change to MOVN. */
8046 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8047 inst
.instruction
|= (newimm
& 0x800) << 15;
8048 inst
.instruction
|= (newimm
& 0x700) << 4;
8049 inst
.instruction
|= (newimm
& 0x0ff);
8052 /* The number can be loaded with a movw instruction. */
8053 else if ((v
& ~0xFFFF) == 0
8054 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8056 int imm
= v
& 0xFFFF;
8058 inst
.instruction
= 0xf2400000; /* MOVW. */
8059 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8060 inst
.instruction
|= (imm
& 0xf000) << 4;
8061 inst
.instruction
|= (imm
& 0x0800) << 15;
8062 inst
.instruction
|= (imm
& 0x0700) << 4;
8063 inst
.instruction
|= (imm
& 0x00ff);
8070 int value
= encode_arm_immediate (v
);
8074 /* This can be done with a mov instruction. */
8075 inst
.instruction
&= LITERAL_MASK
;
8076 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8077 inst
.instruction
|= value
& 0xfff;
8081 value
= encode_arm_immediate (~ v
);
8084 /* This can be done with a mvn instruction. */
8085 inst
.instruction
&= LITERAL_MASK
;
8086 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8087 inst
.instruction
|= value
& 0xfff;
8091 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8094 unsigned immbits
= 0;
8095 unsigned immlo
= inst
.operands
[1].imm
;
8096 unsigned immhi
= inst
.operands
[1].regisimm
8097 ? inst
.operands
[1].reg
8098 : inst
.reloc
.exp
.X_unsigned
8100 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8101 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8102 &op
, 64, NT_invtype
);
8106 neon_invert_size (&immlo
, &immhi
, 64);
8108 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8109 &op
, 64, NT_invtype
);
8114 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8120 /* Fill other bits in vmov encoding for both thumb and arm. */
8122 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8124 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8125 neon_write_immbits (immbits
);
8133 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8134 if (inst
.operands
[i
].issingle
8135 && is_quarter_float (inst
.operands
[1].imm
)
8136 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8138 inst
.operands
[1].imm
=
8139 neon_qfloat_bits (v
);
8140 do_vfp_nsyn_opcode ("fconsts");
8144 /* If our host does not support a 64-bit type then we cannot perform
8145 the following optimization. This mean that there will be a
8146 discrepancy between the output produced by an assembler built for
8147 a 32-bit-only host and the output produced from a 64-bit host, but
8148 this cannot be helped. */
8149 #if defined BFD_HOST_64_BIT
8150 else if (!inst
.operands
[1].issingle
8151 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8153 if (is_double_a_single (v
)
8154 && is_quarter_float (double_to_single (v
)))
8156 inst
.operands
[1].imm
=
8157 neon_qfloat_bits (double_to_single (v
));
8158 do_vfp_nsyn_opcode ("fconstd");
8166 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8167 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8170 inst
.operands
[1].reg
= REG_PC
;
8171 inst
.operands
[1].isreg
= 1;
8172 inst
.operands
[1].preind
= 1;
8173 inst
.reloc
.pc_rel
= 1;
8174 inst
.reloc
.type
= (thumb_p
8175 ? BFD_RELOC_ARM_THUMB_OFFSET
8177 ? BFD_RELOC_ARM_HWLITERAL
8178 : BFD_RELOC_ARM_LITERAL
));
8182 /* inst.operands[i] was set up by parse_address. Encode it into an
8183 ARM-format instruction. Reject all forms which cannot be encoded
8184 into a coprocessor load/store instruction. If wb_ok is false,
8185 reject use of writeback; if unind_ok is false, reject use of
8186 unindexed addressing. If reloc_override is not 0, use it instead
8187 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8188 (in which case it is preserved). */
8191 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8193 if (!inst
.operands
[i
].isreg
)
8196 if (! inst
.operands
[0].isvec
)
8198 inst
.error
= _("invalid co-processor operand");
8201 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8205 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8207 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8209 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8211 gas_assert (!inst
.operands
[i
].writeback
);
8214 inst
.error
= _("instruction does not support unindexed addressing");
8217 inst
.instruction
|= inst
.operands
[i
].imm
;
8218 inst
.instruction
|= INDEX_UP
;
8222 if (inst
.operands
[i
].preind
)
8223 inst
.instruction
|= PRE_INDEX
;
8225 if (inst
.operands
[i
].writeback
)
8227 if (inst
.operands
[i
].reg
== REG_PC
)
8229 inst
.error
= _("pc may not be used with write-back");
8234 inst
.error
= _("instruction does not support writeback");
8237 inst
.instruction
|= WRITE_BACK
;
8241 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8242 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8243 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8244 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8247 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8249 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8252 /* Prefer + for zero encoded value. */
8253 if (!inst
.operands
[i
].negative
)
8254 inst
.instruction
|= INDEX_UP
;
8259 /* Functions for instruction encoding, sorted by sub-architecture.
8260 First some generics; their names are taken from the conventional
8261 bit positions for register arguments in ARM format instructions. */
8271 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8277 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8283 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8284 inst
.instruction
|= inst
.operands
[1].reg
;
8290 inst
.instruction
|= inst
.operands
[0].reg
;
8291 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8297 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8298 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8304 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8305 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8311 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8312 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8316 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8318 if (ARM_CPU_IS_ANY (cpu_variant
))
8320 as_tsktsk ("%s", msg
);
8323 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8335 unsigned Rn
= inst
.operands
[2].reg
;
8336 /* Enforce restrictions on SWP instruction. */
8337 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8339 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8340 _("Rn must not overlap other operands"));
8342 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8344 if (!check_obsolete (&arm_ext_v8
,
8345 _("swp{b} use is obsoleted for ARMv8 and later"))
8346 && warn_on_deprecated
8347 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8348 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8351 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8352 inst
.instruction
|= inst
.operands
[1].reg
;
8353 inst
.instruction
|= Rn
<< 16;
8359 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8360 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8361 inst
.instruction
|= inst
.operands
[2].reg
;
8367 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8368 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8369 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8370 || inst
.reloc
.exp
.X_add_number
!= 0),
8372 inst
.instruction
|= inst
.operands
[0].reg
;
8373 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8374 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8380 inst
.instruction
|= inst
.operands
[0].imm
;
8386 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8387 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8390 /* ARM instructions, in alphabetical order by function name (except
8391 that wrapper functions appear immediately after the function they
8394 /* This is a pseudo-op of the form "adr rd, label" to be converted
8395 into a relative address of the form "add rd, pc, #label-.-8". */
8400 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8402 /* Frag hacking will turn this into a sub instruction if the offset turns
8403 out to be negative. */
8404 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8405 inst
.reloc
.pc_rel
= 1;
8406 inst
.reloc
.exp
.X_add_number
-= 8;
8408 if (inst
.reloc
.exp
.X_op
== O_symbol
8409 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8410 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8411 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8412 inst
.reloc
.exp
.X_add_number
+= 1;
8415 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8416 into a relative address of the form:
8417 add rd, pc, #low(label-.-8)"
8418 add rd, rd, #high(label-.-8)" */
8423 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8425 /* Frag hacking will turn this into a sub instruction if the offset turns
8426 out to be negative. */
8427 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8428 inst
.reloc
.pc_rel
= 1;
8429 inst
.size
= INSN_SIZE
* 2;
8430 inst
.reloc
.exp
.X_add_number
-= 8;
8432 if (inst
.reloc
.exp
.X_op
== O_symbol
8433 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8434 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8435 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8436 inst
.reloc
.exp
.X_add_number
+= 1;
8442 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8443 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8445 if (!inst
.operands
[1].present
)
8446 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8447 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8448 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8449 encode_arm_shifter_operand (2);
8455 if (inst
.operands
[0].present
)
8456 inst
.instruction
|= inst
.operands
[0].imm
;
8458 inst
.instruction
|= 0xf;
8464 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8465 constraint (msb
> 32, _("bit-field extends past end of register"));
8466 /* The instruction encoding stores the LSB and MSB,
8467 not the LSB and width. */
8468 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8469 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8470 inst
.instruction
|= (msb
- 1) << 16;
8478 /* #0 in second position is alternative syntax for bfc, which is
8479 the same instruction but with REG_PC in the Rm field. */
8480 if (!inst
.operands
[1].isreg
)
8481 inst
.operands
[1].reg
= REG_PC
;
8483 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8484 constraint (msb
> 32, _("bit-field extends past end of register"));
8485 /* The instruction encoding stores the LSB and MSB,
8486 not the LSB and width. */
8487 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8488 inst
.instruction
|= inst
.operands
[1].reg
;
8489 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8490 inst
.instruction
|= (msb
- 1) << 16;
8496 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8497 _("bit-field extends past end of register"));
8498 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8499 inst
.instruction
|= inst
.operands
[1].reg
;
8500 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8501 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8504 /* ARM V5 breakpoint instruction (argument parse)
8505 BKPT <16 bit unsigned immediate>
8506 Instruction is not conditional.
8507 The bit pattern given in insns[] has the COND_ALWAYS condition,
8508 and it is an error if the caller tried to override that. */
8513 /* Top 12 of 16 bits to bits 19:8. */
8514 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8516 /* Bottom 4 of 16 bits to bits 3:0. */
8517 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8521 encode_branch (int default_reloc
)
8523 if (inst
.operands
[0].hasreloc
)
8525 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8526 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8527 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8528 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8529 ? BFD_RELOC_ARM_PLT32
8530 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8533 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8534 inst
.reloc
.pc_rel
= 1;
8541 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8542 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8545 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8552 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8554 if (inst
.cond
== COND_ALWAYS
)
8555 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8557 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8561 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8564 /* ARM V5 branch-link-exchange instruction (argument parse)
8565 BLX <target_addr> ie BLX(1)
8566 BLX{<condition>} <Rm> ie BLX(2)
8567 Unfortunately, there are two different opcodes for this mnemonic.
8568 So, the insns[].value is not used, and the code here zaps values
8569 into inst.instruction.
8570 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8575 if (inst
.operands
[0].isreg
)
8577 /* Arg is a register; the opcode provided by insns[] is correct.
8578 It is not illegal to do "blx pc", just useless. */
8579 if (inst
.operands
[0].reg
== REG_PC
)
8580 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8582 inst
.instruction
|= inst
.operands
[0].reg
;
8586 /* Arg is an address; this instruction cannot be executed
8587 conditionally, and the opcode must be adjusted.
8588 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8589 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8590 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8591 inst
.instruction
= 0xfa000000;
8592 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8599 bfd_boolean want_reloc
;
8601 if (inst
.operands
[0].reg
== REG_PC
)
8602 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8604 inst
.instruction
|= inst
.operands
[0].reg
;
8605 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8606 it is for ARMv4t or earlier. */
8607 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8608 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8612 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8617 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8621 /* ARM v5TEJ. Jump to Jazelle code. */
8626 if (inst
.operands
[0].reg
== REG_PC
)
8627 as_tsktsk (_("use of r15 in bxj is not really useful"));
8629 inst
.instruction
|= inst
.operands
[0].reg
;
8632 /* Co-processor data operation:
8633 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8634 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8638 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8639 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8640 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8641 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8642 inst
.instruction
|= inst
.operands
[4].reg
;
8643 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8649 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8650 encode_arm_shifter_operand (1);
8653 /* Transfer between coprocessor and ARM registers.
8654 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8659 No special properties. */
8661 struct deprecated_coproc_regs_s
8668 arm_feature_set deprecated
;
8669 arm_feature_set obsoleted
;
8670 const char *dep_msg
;
8671 const char *obs_msg
;
8674 #define DEPR_ACCESS_V8 \
8675 N_("This coprocessor register access is deprecated in ARMv8")
8677 /* Table of all deprecated coprocessor registers. */
8678 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8680 {15, 0, 7, 10, 5, /* CP15DMB. */
8681 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8682 DEPR_ACCESS_V8
, NULL
},
8683 {15, 0, 7, 10, 4, /* CP15DSB. */
8684 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8685 DEPR_ACCESS_V8
, NULL
},
8686 {15, 0, 7, 5, 4, /* CP15ISB. */
8687 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8688 DEPR_ACCESS_V8
, NULL
},
8689 {14, 6, 1, 0, 0, /* TEEHBR. */
8690 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8691 DEPR_ACCESS_V8
, NULL
},
8692 {14, 6, 0, 0, 0, /* TEECR. */
8693 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8694 DEPR_ACCESS_V8
, NULL
},
8697 #undef DEPR_ACCESS_V8
8699 static const size_t deprecated_coproc_reg_count
=
8700 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8708 Rd
= inst
.operands
[2].reg
;
8711 if (inst
.instruction
== 0xee000010
8712 || inst
.instruction
== 0xfe000010)
8714 reject_bad_reg (Rd
);
8715 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8717 constraint (Rd
== REG_SP
, BAD_SP
);
8722 if (inst
.instruction
== 0xe000010)
8723 constraint (Rd
== REG_PC
, BAD_PC
);
8726 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8728 const struct deprecated_coproc_regs_s
*r
=
8729 deprecated_coproc_regs
+ i
;
8731 if (inst
.operands
[0].reg
== r
->cp
8732 && inst
.operands
[1].imm
== r
->opc1
8733 && inst
.operands
[3].reg
== r
->crn
8734 && inst
.operands
[4].reg
== r
->crm
8735 && inst
.operands
[5].imm
== r
->opc2
)
8737 if (! ARM_CPU_IS_ANY (cpu_variant
)
8738 && warn_on_deprecated
8739 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8740 as_tsktsk ("%s", r
->dep_msg
);
8744 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8745 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8746 inst
.instruction
|= Rd
<< 12;
8747 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8748 inst
.instruction
|= inst
.operands
[4].reg
;
8749 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8752 /* Transfer between coprocessor register and pair of ARM registers.
8753 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8758 Two XScale instructions are special cases of these:
8760 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8761 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8763 Result unpredictable if Rd or Rn is R15. */
8770 Rd
= inst
.operands
[2].reg
;
8771 Rn
= inst
.operands
[3].reg
;
8775 reject_bad_reg (Rd
);
8776 reject_bad_reg (Rn
);
8780 constraint (Rd
== REG_PC
, BAD_PC
);
8781 constraint (Rn
== REG_PC
, BAD_PC
);
8784 /* Only check the MRRC{2} variants. */
8785 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8787 /* If Rd == Rn, error that the operation is
8788 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8789 constraint (Rd
== Rn
, BAD_OVERLAP
);
8792 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8793 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8794 inst
.instruction
|= Rd
<< 12;
8795 inst
.instruction
|= Rn
<< 16;
8796 inst
.instruction
|= inst
.operands
[4].reg
;
8802 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8803 if (inst
.operands
[1].present
)
8805 inst
.instruction
|= CPSI_MMOD
;
8806 inst
.instruction
|= inst
.operands
[1].imm
;
8813 inst
.instruction
|= inst
.operands
[0].imm
;
8819 unsigned Rd
, Rn
, Rm
;
8821 Rd
= inst
.operands
[0].reg
;
8822 Rn
= (inst
.operands
[1].present
8823 ? inst
.operands
[1].reg
: Rd
);
8824 Rm
= inst
.operands
[2].reg
;
8826 constraint ((Rd
== REG_PC
), BAD_PC
);
8827 constraint ((Rn
== REG_PC
), BAD_PC
);
8828 constraint ((Rm
== REG_PC
), BAD_PC
);
8830 inst
.instruction
|= Rd
<< 16;
8831 inst
.instruction
|= Rn
<< 0;
8832 inst
.instruction
|= Rm
<< 8;
8838 /* There is no IT instruction in ARM mode. We
8839 process it to do the validation as if in
8840 thumb mode, just in case the code gets
8841 assembled for thumb using the unified syntax. */
8846 set_it_insn_type (IT_INSN
);
8847 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8848 now_it
.cc
= inst
.operands
[0].imm
;
8852 /* If there is only one register in the register list,
8853 then return its register number. Otherwise return -1. */
8855 only_one_reg_in_list (int range
)
8857 int i
= ffs (range
) - 1;
8858 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8862 encode_ldmstm(int from_push_pop_mnem
)
8864 int base_reg
= inst
.operands
[0].reg
;
8865 int range
= inst
.operands
[1].imm
;
8868 inst
.instruction
|= base_reg
<< 16;
8869 inst
.instruction
|= range
;
8871 if (inst
.operands
[1].writeback
)
8872 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8874 if (inst
.operands
[0].writeback
)
8876 inst
.instruction
|= WRITE_BACK
;
8877 /* Check for unpredictable uses of writeback. */
8878 if (inst
.instruction
& LOAD_BIT
)
8880 /* Not allowed in LDM type 2. */
8881 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8882 && ((range
& (1 << REG_PC
)) == 0))
8883 as_warn (_("writeback of base register is UNPREDICTABLE"));
8884 /* Only allowed if base reg not in list for other types. */
8885 else if (range
& (1 << base_reg
))
8886 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8890 /* Not allowed for type 2. */
8891 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8892 as_warn (_("writeback of base register is UNPREDICTABLE"));
8893 /* Only allowed if base reg not in list, or first in list. */
8894 else if ((range
& (1 << base_reg
))
8895 && (range
& ((1 << base_reg
) - 1)))
8896 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8900 /* If PUSH/POP has only one register, then use the A2 encoding. */
8901 one_reg
= only_one_reg_in_list (range
);
8902 if (from_push_pop_mnem
&& one_reg
>= 0)
8904 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8906 inst
.instruction
&= A_COND_MASK
;
8907 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8908 inst
.instruction
|= one_reg
<< 12;
8915 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8918 /* ARMv5TE load-consecutive (argument parse)
8927 constraint (inst
.operands
[0].reg
% 2 != 0,
8928 _("first transfer register must be even"));
8929 constraint (inst
.operands
[1].present
8930 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8931 _("can only transfer two consecutive registers"));
8932 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8933 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8935 if (!inst
.operands
[1].present
)
8936 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8938 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8939 register and the first register written; we have to diagnose
8940 overlap between the base and the second register written here. */
8942 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8943 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8944 as_warn (_("base register written back, and overlaps "
8945 "second transfer register"));
8947 if (!(inst
.instruction
& V4_STR_BIT
))
8949 /* For an index-register load, the index register must not overlap the
8950 destination (even if not write-back). */
8951 if (inst
.operands
[2].immisreg
8952 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8953 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8954 as_warn (_("index register overlaps transfer register"));
8956 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8957 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8963 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8964 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8965 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8966 || inst
.operands
[1].negative
8967 /* This can arise if the programmer has written
8969 or if they have mistakenly used a register name as the last
8972 It is very difficult to distinguish between these two cases
8973 because "rX" might actually be a label. ie the register
8974 name has been occluded by a symbol of the same name. So we
8975 just generate a general 'bad addressing mode' type error
8976 message and leave it up to the programmer to discover the
8977 true cause and fix their mistake. */
8978 || (inst
.operands
[1].reg
== REG_PC
),
8981 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8982 || inst
.reloc
.exp
.X_add_number
!= 0,
8983 _("offset must be zero in ARM encoding"));
8985 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8987 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8988 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8989 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8995 constraint (inst
.operands
[0].reg
% 2 != 0,
8996 _("even register required"));
8997 constraint (inst
.operands
[1].present
8998 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8999 _("can only load two consecutive registers"));
9000 /* If op 1 were present and equal to PC, this function wouldn't
9001 have been called in the first place. */
9002 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9004 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9005 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9008 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9009 which is not a multiple of four is UNPREDICTABLE. */
9011 check_ldr_r15_aligned (void)
9013 constraint (!(inst
.operands
[1].immisreg
)
9014 && (inst
.operands
[0].reg
== REG_PC
9015 && inst
.operands
[1].reg
== REG_PC
9016 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
9017 _("ldr to register 15 must be 4-byte aligned"));
9023 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9024 if (!inst
.operands
[1].isreg
)
9025 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9027 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9028 check_ldr_r15_aligned ();
9034 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9036 if (inst
.operands
[1].preind
)
9038 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9039 || inst
.reloc
.exp
.X_add_number
!= 0,
9040 _("this instruction requires a post-indexed address"));
9042 inst
.operands
[1].preind
= 0;
9043 inst
.operands
[1].postind
= 1;
9044 inst
.operands
[1].writeback
= 1;
9046 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9047 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9050 /* Halfword and signed-byte load/store operations. */
9055 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9056 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9057 if (!inst
.operands
[1].isreg
)
9058 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9060 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9066 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9068 if (inst
.operands
[1].preind
)
9070 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9071 || inst
.reloc
.exp
.X_add_number
!= 0,
9072 _("this instruction requires a post-indexed address"));
9074 inst
.operands
[1].preind
= 0;
9075 inst
.operands
[1].postind
= 1;
9076 inst
.operands
[1].writeback
= 1;
9078 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9079 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9082 /* Co-processor register load/store.
9083 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9087 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9088 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9089 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9095 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9096 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9097 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9098 && !(inst
.instruction
& 0x00400000))
9099 as_tsktsk (_("Rd and Rm should be different in mla"));
9101 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9102 inst
.instruction
|= inst
.operands
[1].reg
;
9103 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9104 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9110 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9111 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9113 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9114 encode_arm_shifter_operand (1);
9117 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9124 top
= (inst
.instruction
& 0x00400000) != 0;
9125 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9126 _(":lower16: not allowed in this instruction"));
9127 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9128 _(":upper16: not allowed in this instruction"));
9129 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9130 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9132 imm
= inst
.reloc
.exp
.X_add_number
;
9133 /* The value is in two pieces: 0:11, 16:19. */
9134 inst
.instruction
|= (imm
& 0x00000fff);
9135 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9140 do_vfp_nsyn_mrs (void)
9142 if (inst
.operands
[0].isvec
)
9144 if (inst
.operands
[1].reg
!= 1)
9145 first_error (_("operand 1 must be FPSCR"));
9146 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9147 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9148 do_vfp_nsyn_opcode ("fmstat");
9150 else if (inst
.operands
[1].isvec
)
9151 do_vfp_nsyn_opcode ("fmrx");
9159 do_vfp_nsyn_msr (void)
9161 if (inst
.operands
[0].isvec
)
9162 do_vfp_nsyn_opcode ("fmxr");
9172 unsigned Rt
= inst
.operands
[0].reg
;
9174 if (thumb_mode
&& Rt
== REG_SP
)
9176 inst
.error
= BAD_SP
;
9180 /* MVFR2 is only valid at ARMv8-A. */
9181 if (inst
.operands
[1].reg
== 5)
9182 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9185 /* APSR_ sets isvec. All other refs to PC are illegal. */
9186 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9188 inst
.error
= BAD_PC
;
9192 /* If we get through parsing the register name, we just insert the number
9193 generated into the instruction without further validation. */
9194 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9195 inst
.instruction
|= (Rt
<< 12);
9201 unsigned Rt
= inst
.operands
[1].reg
;
9204 reject_bad_reg (Rt
);
9205 else if (Rt
== REG_PC
)
9207 inst
.error
= BAD_PC
;
9211 /* MVFR2 is only valid for ARMv8-A. */
9212 if (inst
.operands
[0].reg
== 5)
9213 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9216 /* If we get through parsing the register name, we just insert the number
9217 generated into the instruction without further validation. */
9218 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9219 inst
.instruction
|= (Rt
<< 12);
9227 if (do_vfp_nsyn_mrs () == SUCCESS
)
9230 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9231 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9233 if (inst
.operands
[1].isreg
)
9235 br
= inst
.operands
[1].reg
;
9236 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9237 as_bad (_("bad register for mrs"));
9241 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9242 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9244 _("'APSR', 'CPSR' or 'SPSR' expected"));
9245 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9248 inst
.instruction
|= br
;
9251 /* Two possible forms:
9252 "{C|S}PSR_<field>, Rm",
9253 "{C|S}PSR_f, #expression". */
9258 if (do_vfp_nsyn_msr () == SUCCESS
)
9261 inst
.instruction
|= inst
.operands
[0].imm
;
9262 if (inst
.operands
[1].isreg
)
9263 inst
.instruction
|= inst
.operands
[1].reg
;
9266 inst
.instruction
|= INST_IMMEDIATE
;
9267 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9268 inst
.reloc
.pc_rel
= 0;
9275 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9277 if (!inst
.operands
[2].present
)
9278 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9279 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9280 inst
.instruction
|= inst
.operands
[1].reg
;
9281 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9283 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9284 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9285 as_tsktsk (_("Rd and Rm should be different in mul"));
9288 /* Long Multiply Parser
9289 UMULL RdLo, RdHi, Rm, Rs
9290 SMULL RdLo, RdHi, Rm, Rs
9291 UMLAL RdLo, RdHi, Rm, Rs
9292 SMLAL RdLo, RdHi, Rm, Rs. */
9297 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9298 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9299 inst
.instruction
|= inst
.operands
[2].reg
;
9300 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9302 /* rdhi and rdlo must be different. */
9303 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9304 as_tsktsk (_("rdhi and rdlo must be different"));
9306 /* rdhi, rdlo and rm must all be different before armv6. */
9307 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9308 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9309 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9310 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9316 if (inst
.operands
[0].present
9317 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9319 /* Architectural NOP hints are CPSR sets with no bits selected. */
9320 inst
.instruction
&= 0xf0000000;
9321 inst
.instruction
|= 0x0320f000;
9322 if (inst
.operands
[0].present
)
9323 inst
.instruction
|= inst
.operands
[0].imm
;
9327 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9328 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9329 Condition defaults to COND_ALWAYS.
9330 Error if Rd, Rn or Rm are R15. */
9335 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9336 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9337 inst
.instruction
|= inst
.operands
[2].reg
;
9338 if (inst
.operands
[3].present
)
9339 encode_arm_shift (3);
9342 /* ARM V6 PKHTB (Argument Parse). */
9347 if (!inst
.operands
[3].present
)
9349 /* If the shift specifier is omitted, turn the instruction
9350 into pkhbt rd, rm, rn. */
9351 inst
.instruction
&= 0xfff00010;
9352 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9353 inst
.instruction
|= inst
.operands
[1].reg
;
9354 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9358 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9359 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9360 inst
.instruction
|= inst
.operands
[2].reg
;
9361 encode_arm_shift (3);
9365 /* ARMv5TE: Preload-Cache
9366 MP Extensions: Preload for write
9370 Syntactically, like LDR with B=1, W=0, L=1. */
9375 constraint (!inst
.operands
[0].isreg
,
9376 _("'[' expected after PLD mnemonic"));
9377 constraint (inst
.operands
[0].postind
,
9378 _("post-indexed expression used in preload instruction"));
9379 constraint (inst
.operands
[0].writeback
,
9380 _("writeback used in preload instruction"));
9381 constraint (!inst
.operands
[0].preind
,
9382 _("unindexed addressing used in preload instruction"));
9383 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9386 /* ARMv7: PLI <addr_mode> */
9390 constraint (!inst
.operands
[0].isreg
,
9391 _("'[' expected after PLI mnemonic"));
9392 constraint (inst
.operands
[0].postind
,
9393 _("post-indexed expression used in preload instruction"));
9394 constraint (inst
.operands
[0].writeback
,
9395 _("writeback used in preload instruction"));
9396 constraint (!inst
.operands
[0].preind
,
9397 _("unindexed addressing used in preload instruction"));
9398 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9399 inst
.instruction
&= ~PRE_INDEX
;
9405 constraint (inst
.operands
[0].writeback
,
9406 _("push/pop do not support {reglist}^"));
9407 inst
.operands
[1] = inst
.operands
[0];
9408 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9409 inst
.operands
[0].isreg
= 1;
9410 inst
.operands
[0].writeback
= 1;
9411 inst
.operands
[0].reg
= REG_SP
;
9412 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9415 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9416 word at the specified address and the following word
9418 Unconditionally executed.
9419 Error if Rn is R15. */
9424 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9425 if (inst
.operands
[0].writeback
)
9426 inst
.instruction
|= WRITE_BACK
;
9429 /* ARM V6 ssat (argument parse). */
9434 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9435 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9436 inst
.instruction
|= inst
.operands
[2].reg
;
9438 if (inst
.operands
[3].present
)
9439 encode_arm_shift (3);
9442 /* ARM V6 usat (argument parse). */
9447 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9448 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9449 inst
.instruction
|= inst
.operands
[2].reg
;
9451 if (inst
.operands
[3].present
)
9452 encode_arm_shift (3);
9455 /* ARM V6 ssat16 (argument parse). */
9460 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9461 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9462 inst
.instruction
|= inst
.operands
[2].reg
;
9468 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9469 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9470 inst
.instruction
|= inst
.operands
[2].reg
;
9473 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9474 preserving the other bits.
9476 setend <endian_specifier>, where <endian_specifier> is either
9482 if (warn_on_deprecated
9483 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9484 as_tsktsk (_("setend use is deprecated for ARMv8"));
9486 if (inst
.operands
[0].imm
)
9487 inst
.instruction
|= 0x200;
9493 unsigned int Rm
= (inst
.operands
[1].present
9494 ? inst
.operands
[1].reg
9495 : inst
.operands
[0].reg
);
9497 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9498 inst
.instruction
|= Rm
;
9499 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9501 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9502 inst
.instruction
|= SHIFT_BY_REG
;
9503 /* PR 12854: Error on extraneous shifts. */
9504 constraint (inst
.operands
[2].shifted
,
9505 _("extraneous shift as part of operand to shift insn"));
9508 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9514 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9515 inst
.reloc
.pc_rel
= 0;
9521 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9522 inst
.reloc
.pc_rel
= 0;
9528 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9529 inst
.reloc
.pc_rel
= 0;
9535 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9536 _("selected processor does not support SETPAN instruction"));
9538 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9544 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9545 _("selected processor does not support SETPAN instruction"));
9547 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9550 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9551 SMLAxy{cond} Rd,Rm,Rs,Rn
9552 SMLAWy{cond} Rd,Rm,Rs,Rn
9553 Error if any register is R15. */
9558 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9559 inst
.instruction
|= inst
.operands
[1].reg
;
9560 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9561 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9564 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9565 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9566 Error if any register is R15.
9567 Warning if Rdlo == Rdhi. */
9572 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9573 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9574 inst
.instruction
|= inst
.operands
[2].reg
;
9575 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9577 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9578 as_tsktsk (_("rdhi and rdlo must be different"));
9581 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9582 SMULxy{cond} Rd,Rm,Rs
9583 Error if any register is R15. */
9588 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9589 inst
.instruction
|= inst
.operands
[1].reg
;
9590 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9593 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9594 the same for both ARM and Thumb-2. */
9601 if (inst
.operands
[0].present
)
9603 reg
= inst
.operands
[0].reg
;
9604 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9609 inst
.instruction
|= reg
<< 16;
9610 inst
.instruction
|= inst
.operands
[1].imm
;
9611 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9612 inst
.instruction
|= WRITE_BACK
;
9615 /* ARM V6 strex (argument parse). */
9620 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9621 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9622 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9623 || inst
.operands
[2].negative
9624 /* See comment in do_ldrex(). */
9625 || (inst
.operands
[2].reg
== REG_PC
),
9628 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9629 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9631 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9632 || inst
.reloc
.exp
.X_add_number
!= 0,
9633 _("offset must be zero in ARM encoding"));
9635 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9636 inst
.instruction
|= inst
.operands
[1].reg
;
9637 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9638 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9644 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9645 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9646 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9647 || inst
.operands
[2].negative
,
9650 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9651 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9659 constraint (inst
.operands
[1].reg
% 2 != 0,
9660 _("even register required"));
9661 constraint (inst
.operands
[2].present
9662 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9663 _("can only store two consecutive registers"));
9664 /* If op 2 were present and equal to PC, this function wouldn't
9665 have been called in the first place. */
9666 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9668 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9669 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9670 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9673 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9674 inst
.instruction
|= inst
.operands
[1].reg
;
9675 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9682 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9683 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9691 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9692 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9697 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9698 extends it to 32-bits, and adds the result to a value in another
9699 register. You can specify a rotation by 0, 8, 16, or 24 bits
9700 before extracting the 16-bit value.
9701 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9702 Condition defaults to COND_ALWAYS.
9703 Error if any register uses R15. */
9708 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9709 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9710 inst
.instruction
|= inst
.operands
[2].reg
;
9711 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9716 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9717 Condition defaults to COND_ALWAYS.
9718 Error if any register uses R15. */
9723 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9724 inst
.instruction
|= inst
.operands
[1].reg
;
9725 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9728 /* VFP instructions. In a logical order: SP variant first, monad
9729 before dyad, arithmetic then move then load/store. */
9732 do_vfp_sp_monadic (void)
9734 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9735 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9739 do_vfp_sp_dyadic (void)
9741 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9742 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9743 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9747 do_vfp_sp_compare_z (void)
9749 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9753 do_vfp_dp_sp_cvt (void)
9755 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9756 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9760 do_vfp_sp_dp_cvt (void)
9762 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9763 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9767 do_vfp_reg_from_sp (void)
9769 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9770 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9774 do_vfp_reg2_from_sp2 (void)
9776 constraint (inst
.operands
[2].imm
!= 2,
9777 _("only two consecutive VFP SP registers allowed here"));
9778 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9779 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9780 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9784 do_vfp_sp_from_reg (void)
9786 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9787 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9791 do_vfp_sp2_from_reg2 (void)
9793 constraint (inst
.operands
[0].imm
!= 2,
9794 _("only two consecutive VFP SP registers allowed here"));
9795 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9796 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9797 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9801 do_vfp_sp_ldst (void)
9803 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9804 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9808 do_vfp_dp_ldst (void)
9810 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9811 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9816 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9818 if (inst
.operands
[0].writeback
)
9819 inst
.instruction
|= WRITE_BACK
;
9821 constraint (ldstm_type
!= VFP_LDSTMIA
,
9822 _("this addressing mode requires base-register writeback"));
9823 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9824 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9825 inst
.instruction
|= inst
.operands
[1].imm
;
9829 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9833 if (inst
.operands
[0].writeback
)
9834 inst
.instruction
|= WRITE_BACK
;
9836 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9837 _("this addressing mode requires base-register writeback"));
9839 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9840 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9842 count
= inst
.operands
[1].imm
<< 1;
9843 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9846 inst
.instruction
|= count
;
9850 do_vfp_sp_ldstmia (void)
9852 vfp_sp_ldstm (VFP_LDSTMIA
);
9856 do_vfp_sp_ldstmdb (void)
9858 vfp_sp_ldstm (VFP_LDSTMDB
);
9862 do_vfp_dp_ldstmia (void)
9864 vfp_dp_ldstm (VFP_LDSTMIA
);
9868 do_vfp_dp_ldstmdb (void)
9870 vfp_dp_ldstm (VFP_LDSTMDB
);
9874 do_vfp_xp_ldstmia (void)
9876 vfp_dp_ldstm (VFP_LDSTMIAX
);
9880 do_vfp_xp_ldstmdb (void)
9882 vfp_dp_ldstm (VFP_LDSTMDBX
);
9886 do_vfp_dp_rd_rm (void)
9888 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9889 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9893 do_vfp_dp_rn_rd (void)
9895 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9896 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9900 do_vfp_dp_rd_rn (void)
9902 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9903 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9907 do_vfp_dp_rd_rn_rm (void)
9909 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9910 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9911 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9917 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9921 do_vfp_dp_rm_rd_rn (void)
9923 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9924 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9925 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9928 /* VFPv3 instructions. */
9930 do_vfp_sp_const (void)
9932 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9933 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9934 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9938 do_vfp_dp_const (void)
9940 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9941 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9942 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9946 vfp_conv (int srcsize
)
9948 int immbits
= srcsize
- inst
.operands
[1].imm
;
9950 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9952 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9953 i.e. immbits must be in range 0 - 16. */
9954 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9957 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9959 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9960 i.e. immbits must be in range 0 - 31. */
9961 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9965 inst
.instruction
|= (immbits
& 1) << 5;
9966 inst
.instruction
|= (immbits
>> 1);
9970 do_vfp_sp_conv_16 (void)
9972 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9977 do_vfp_dp_conv_16 (void)
9979 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9984 do_vfp_sp_conv_32 (void)
9986 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9991 do_vfp_dp_conv_32 (void)
9993 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9997 /* FPA instructions. Also in a logical order. */
10002 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10003 inst
.instruction
|= inst
.operands
[1].reg
;
10007 do_fpa_ldmstm (void)
10009 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10010 switch (inst
.operands
[1].imm
)
10012 case 1: inst
.instruction
|= CP_T_X
; break;
10013 case 2: inst
.instruction
|= CP_T_Y
; break;
10014 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10019 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10021 /* The instruction specified "ea" or "fd", so we can only accept
10022 [Rn]{!}. The instruction does not really support stacking or
10023 unstacking, so we have to emulate these by setting appropriate
10024 bits and offsets. */
10025 constraint (inst
.reloc
.exp
.X_op
!= O_constant
10026 || inst
.reloc
.exp
.X_add_number
!= 0,
10027 _("this instruction does not support indexing"));
10029 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10030 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10032 if (!(inst
.instruction
& INDEX_UP
))
10033 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
10035 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10037 inst
.operands
[2].preind
= 0;
10038 inst
.operands
[2].postind
= 1;
10042 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10045 /* iWMMXt instructions: strictly in alphabetical order. */
10048 do_iwmmxt_tandorc (void)
10050 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10054 do_iwmmxt_textrc (void)
10056 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10057 inst
.instruction
|= inst
.operands
[1].imm
;
10061 do_iwmmxt_textrm (void)
10063 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10064 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10065 inst
.instruction
|= inst
.operands
[2].imm
;
10069 do_iwmmxt_tinsr (void)
10071 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10072 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10073 inst
.instruction
|= inst
.operands
[2].imm
;
10077 do_iwmmxt_tmia (void)
10079 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10080 inst
.instruction
|= inst
.operands
[1].reg
;
10081 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10085 do_iwmmxt_waligni (void)
10087 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10088 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10089 inst
.instruction
|= inst
.operands
[2].reg
;
10090 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10094 do_iwmmxt_wmerge (void)
10096 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10097 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10098 inst
.instruction
|= inst
.operands
[2].reg
;
10099 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10103 do_iwmmxt_wmov (void)
10105 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10106 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10107 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10108 inst
.instruction
|= inst
.operands
[1].reg
;
10112 do_iwmmxt_wldstbh (void)
10115 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10117 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10119 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10120 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10124 do_iwmmxt_wldstw (void)
10126 /* RIWR_RIWC clears .isreg for a control register. */
10127 if (!inst
.operands
[0].isreg
)
10129 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10130 inst
.instruction
|= 0xf0000000;
10133 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10134 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10138 do_iwmmxt_wldstd (void)
10140 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10141 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10142 && inst
.operands
[1].immisreg
)
10144 inst
.instruction
&= ~0x1a000ff;
10145 inst
.instruction
|= (0xfU
<< 28);
10146 if (inst
.operands
[1].preind
)
10147 inst
.instruction
|= PRE_INDEX
;
10148 if (!inst
.operands
[1].negative
)
10149 inst
.instruction
|= INDEX_UP
;
10150 if (inst
.operands
[1].writeback
)
10151 inst
.instruction
|= WRITE_BACK
;
10152 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10153 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10154 inst
.instruction
|= inst
.operands
[1].imm
;
10157 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10161 do_iwmmxt_wshufh (void)
10163 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10164 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10165 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10166 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10170 do_iwmmxt_wzero (void)
10172 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10173 inst
.instruction
|= inst
.operands
[0].reg
;
10174 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10175 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10179 do_iwmmxt_wrwrwr_or_imm5 (void)
10181 if (inst
.operands
[2].isreg
)
10184 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10185 _("immediate operand requires iWMMXt2"));
10187 if (inst
.operands
[2].imm
== 0)
10189 switch ((inst
.instruction
>> 20) & 0xf)
10195 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10196 inst
.operands
[2].imm
= 16;
10197 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10203 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10204 inst
.operands
[2].imm
= 32;
10205 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10212 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10214 wrn
= (inst
.instruction
>> 16) & 0xf;
10215 inst
.instruction
&= 0xff0fff0f;
10216 inst
.instruction
|= wrn
;
10217 /* Bail out here; the instruction is now assembled. */
10222 /* Map 32 -> 0, etc. */
10223 inst
.operands
[2].imm
&= 0x1f;
10224 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10228 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10229 operations first, then control, shift, and load/store. */
10231 /* Insns like "foo X,Y,Z". */
10234 do_mav_triple (void)
10236 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10237 inst
.instruction
|= inst
.operands
[1].reg
;
10238 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10241 /* Insns like "foo W,X,Y,Z".
10242 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10247 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10248 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10249 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10250 inst
.instruction
|= inst
.operands
[3].reg
;
10253 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10255 do_mav_dspsc (void)
10257 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10260 /* Maverick shift immediate instructions.
10261 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10262 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10265 do_mav_shift (void)
10267 int imm
= inst
.operands
[2].imm
;
10269 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10270 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10272 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10273 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10274 Bit 4 should be 0. */
10275 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10277 inst
.instruction
|= imm
;
10280 /* XScale instructions. Also sorted arithmetic before move. */
10282 /* Xscale multiply-accumulate (argument parse)
10285 MIAxycc acc0,Rm,Rs. */
10290 inst
.instruction
|= inst
.operands
[1].reg
;
10291 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10294 /* Xscale move-accumulator-register (argument parse)
10296 MARcc acc0,RdLo,RdHi. */
10301 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10302 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10305 /* Xscale move-register-accumulator (argument parse)
10307 MRAcc RdLo,RdHi,acc0. */
10312 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10313 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10314 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10317 /* Encoding functions relevant only to Thumb. */
10319 /* inst.operands[i] is a shifted-register operand; encode
10320 it into inst.instruction in the format used by Thumb32. */
10323 encode_thumb32_shifted_operand (int i
)
10325 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10326 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10328 constraint (inst
.operands
[i
].immisreg
,
10329 _("shift by register not allowed in thumb mode"));
10330 inst
.instruction
|= inst
.operands
[i
].reg
;
10331 if (shift
== SHIFT_RRX
)
10332 inst
.instruction
|= SHIFT_ROR
<< 4;
10335 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10336 _("expression too complex"));
10338 constraint (value
> 32
10339 || (value
== 32 && (shift
== SHIFT_LSL
10340 || shift
== SHIFT_ROR
)),
10341 _("shift expression is too large"));
10345 else if (value
== 32)
10348 inst
.instruction
|= shift
<< 4;
10349 inst
.instruction
|= (value
& 0x1c) << 10;
10350 inst
.instruction
|= (value
& 0x03) << 6;
10355 /* inst.operands[i] was set up by parse_address. Encode it into a
10356 Thumb32 format load or store instruction. Reject forms that cannot
10357 be used with such instructions. If is_t is true, reject forms that
10358 cannot be used with a T instruction; if is_d is true, reject forms
10359 that cannot be used with a D instruction. If it is a store insn,
10360 reject PC in Rn. */
10363 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10365 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10367 constraint (!inst
.operands
[i
].isreg
,
10368 _("Instruction does not support =N addresses"));
10370 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10371 if (inst
.operands
[i
].immisreg
)
10373 constraint (is_pc
, BAD_PC_ADDRESSING
);
10374 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10375 constraint (inst
.operands
[i
].negative
,
10376 _("Thumb does not support negative register indexing"));
10377 constraint (inst
.operands
[i
].postind
,
10378 _("Thumb does not support register post-indexing"));
10379 constraint (inst
.operands
[i
].writeback
,
10380 _("Thumb does not support register indexing with writeback"));
10381 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10382 _("Thumb supports only LSL in shifted register indexing"));
10384 inst
.instruction
|= inst
.operands
[i
].imm
;
10385 if (inst
.operands
[i
].shifted
)
10387 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10388 _("expression too complex"));
10389 constraint (inst
.reloc
.exp
.X_add_number
< 0
10390 || inst
.reloc
.exp
.X_add_number
> 3,
10391 _("shift out of range"));
10392 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10394 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10396 else if (inst
.operands
[i
].preind
)
10398 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10399 constraint (is_t
&& inst
.operands
[i
].writeback
,
10400 _("cannot use writeback with this instruction"));
10401 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10402 BAD_PC_ADDRESSING
);
10406 inst
.instruction
|= 0x01000000;
10407 if (inst
.operands
[i
].writeback
)
10408 inst
.instruction
|= 0x00200000;
10412 inst
.instruction
|= 0x00000c00;
10413 if (inst
.operands
[i
].writeback
)
10414 inst
.instruction
|= 0x00000100;
10416 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10418 else if (inst
.operands
[i
].postind
)
10420 gas_assert (inst
.operands
[i
].writeback
);
10421 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10422 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10425 inst
.instruction
|= 0x00200000;
10427 inst
.instruction
|= 0x00000900;
10428 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10430 else /* unindexed - only for coprocessor */
10431 inst
.error
= _("instruction does not accept unindexed addressing");
10434 /* Table of Thumb instructions which exist in both 16- and 32-bit
10435 encodings (the latter only in post-V6T2 cores). The index is the
10436 value used in the insns table below. When there is more than one
10437 possible 16-bit encoding for the instruction, this table always
10439 Also contains several pseudo-instructions used during relaxation. */
10440 #define T16_32_TAB \
10441 X(_adc, 4140, eb400000), \
10442 X(_adcs, 4140, eb500000), \
10443 X(_add, 1c00, eb000000), \
10444 X(_adds, 1c00, eb100000), \
10445 X(_addi, 0000, f1000000), \
10446 X(_addis, 0000, f1100000), \
10447 X(_add_pc,000f, f20f0000), \
10448 X(_add_sp,000d, f10d0000), \
10449 X(_adr, 000f, f20f0000), \
10450 X(_and, 4000, ea000000), \
10451 X(_ands, 4000, ea100000), \
10452 X(_asr, 1000, fa40f000), \
10453 X(_asrs, 1000, fa50f000), \
10454 X(_b, e000, f000b000), \
10455 X(_bcond, d000, f0008000), \
10456 X(_bic, 4380, ea200000), \
10457 X(_bics, 4380, ea300000), \
10458 X(_cmn, 42c0, eb100f00), \
10459 X(_cmp, 2800, ebb00f00), \
10460 X(_cpsie, b660, f3af8400), \
10461 X(_cpsid, b670, f3af8600), \
10462 X(_cpy, 4600, ea4f0000), \
10463 X(_dec_sp,80dd, f1ad0d00), \
10464 X(_eor, 4040, ea800000), \
10465 X(_eors, 4040, ea900000), \
10466 X(_inc_sp,00dd, f10d0d00), \
10467 X(_ldmia, c800, e8900000), \
10468 X(_ldr, 6800, f8500000), \
10469 X(_ldrb, 7800, f8100000), \
10470 X(_ldrh, 8800, f8300000), \
10471 X(_ldrsb, 5600, f9100000), \
10472 X(_ldrsh, 5e00, f9300000), \
10473 X(_ldr_pc,4800, f85f0000), \
10474 X(_ldr_pc2,4800, f85f0000), \
10475 X(_ldr_sp,9800, f85d0000), \
10476 X(_lsl, 0000, fa00f000), \
10477 X(_lsls, 0000, fa10f000), \
10478 X(_lsr, 0800, fa20f000), \
10479 X(_lsrs, 0800, fa30f000), \
10480 X(_mov, 2000, ea4f0000), \
10481 X(_movs, 2000, ea5f0000), \
10482 X(_mul, 4340, fb00f000), \
10483 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10484 X(_mvn, 43c0, ea6f0000), \
10485 X(_mvns, 43c0, ea7f0000), \
10486 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10487 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10488 X(_orr, 4300, ea400000), \
10489 X(_orrs, 4300, ea500000), \
10490 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10491 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10492 X(_rev, ba00, fa90f080), \
10493 X(_rev16, ba40, fa90f090), \
10494 X(_revsh, bac0, fa90f0b0), \
10495 X(_ror, 41c0, fa60f000), \
10496 X(_rors, 41c0, fa70f000), \
10497 X(_sbc, 4180, eb600000), \
10498 X(_sbcs, 4180, eb700000), \
10499 X(_stmia, c000, e8800000), \
10500 X(_str, 6000, f8400000), \
10501 X(_strb, 7000, f8000000), \
10502 X(_strh, 8000, f8200000), \
10503 X(_str_sp,9000, f84d0000), \
10504 X(_sub, 1e00, eba00000), \
10505 X(_subs, 1e00, ebb00000), \
10506 X(_subi, 8000, f1a00000), \
10507 X(_subis, 8000, f1b00000), \
10508 X(_sxtb, b240, fa4ff080), \
10509 X(_sxth, b200, fa0ff080), \
10510 X(_tst, 4200, ea100f00), \
10511 X(_uxtb, b2c0, fa5ff080), \
10512 X(_uxth, b280, fa1ff080), \
10513 X(_nop, bf00, f3af8000), \
10514 X(_yield, bf10, f3af8001), \
10515 X(_wfe, bf20, f3af8002), \
10516 X(_wfi, bf30, f3af8003), \
10517 X(_sev, bf40, f3af8004), \
10518 X(_sevl, bf50, f3af8005), \
10519 X(_udf, de00, f7f0a000)
10521 /* To catch errors in encoding functions, the codes are all offset by
10522 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10523 as 16-bit instructions. */
10524 #define X(a,b,c) T_MNEM##a
10525 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10528 #define X(a,b,c) 0x##b
10529 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10530 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10533 #define X(a,b,c) 0x##c
10534 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10535 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10536 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10540 /* Thumb instruction encoders, in alphabetical order. */
10542 /* ADDW or SUBW. */
10545 do_t_add_sub_w (void)
10549 Rd
= inst
.operands
[0].reg
;
10550 Rn
= inst
.operands
[1].reg
;
10552 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10553 is the SP-{plus,minus}-immediate form of the instruction. */
10555 constraint (Rd
== REG_PC
, BAD_PC
);
10557 reject_bad_reg (Rd
);
10559 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10560 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10563 /* Parse an add or subtract instruction. We get here with inst.instruction
10564 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
10567 do_t_add_sub (void)
10571 Rd
= inst
.operands
[0].reg
;
10572 Rs
= (inst
.operands
[1].present
10573 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10574 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10577 set_it_insn_type_last ();
10579 if (unified_syntax
)
10582 bfd_boolean narrow
;
10585 flags
= (inst
.instruction
== T_MNEM_adds
10586 || inst
.instruction
== T_MNEM_subs
);
10588 narrow
= !in_it_block ();
10590 narrow
= in_it_block ();
10591 if (!inst
.operands
[2].isreg
)
10595 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10596 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10598 add
= (inst
.instruction
== T_MNEM_add
10599 || inst
.instruction
== T_MNEM_adds
);
10601 if (inst
.size_req
!= 4)
10603 /* Attempt to use a narrow opcode, with relaxation if
10605 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10606 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10607 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10608 opcode
= T_MNEM_add_sp
;
10609 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10610 opcode
= T_MNEM_add_pc
;
10611 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10614 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10616 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10620 inst
.instruction
= THUMB_OP16(opcode
);
10621 inst
.instruction
|= (Rd
<< 4) | Rs
;
10622 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10623 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10625 if (inst
.size_req
== 2)
10626 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10628 inst
.relax
= opcode
;
10632 constraint (inst
.size_req
== 2, BAD_HIREG
);
10634 if (inst
.size_req
== 4
10635 || (inst
.size_req
!= 2 && !opcode
))
10637 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10638 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10639 THUMB1_RELOC_ONLY
);
10642 constraint (add
, BAD_PC
);
10643 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10644 _("only SUBS PC, LR, #const allowed"));
10645 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10646 _("expression too complex"));
10647 constraint (inst
.reloc
.exp
.X_add_number
< 0
10648 || inst
.reloc
.exp
.X_add_number
> 0xff,
10649 _("immediate value out of range"));
10650 inst
.instruction
= T2_SUBS_PC_LR
10651 | inst
.reloc
.exp
.X_add_number
;
10652 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10655 else if (Rs
== REG_PC
)
10657 /* Always use addw/subw. */
10658 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10659 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10663 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10664 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10667 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10669 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10671 inst
.instruction
|= Rd
<< 8;
10672 inst
.instruction
|= Rs
<< 16;
10677 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10678 unsigned int shift
= inst
.operands
[2].shift_kind
;
10680 Rn
= inst
.operands
[2].reg
;
10681 /* See if we can do this with a 16-bit instruction. */
10682 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10684 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10689 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10690 || inst
.instruction
== T_MNEM_add
)
10692 : T_OPCODE_SUB_R3
);
10693 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10697 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10699 /* Thumb-1 cores (except v6-M) require at least one high
10700 register in a narrow non flag setting add. */
10701 if (Rd
> 7 || Rn
> 7
10702 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10703 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10710 inst
.instruction
= T_OPCODE_ADD_HI
;
10711 inst
.instruction
|= (Rd
& 8) << 4;
10712 inst
.instruction
|= (Rd
& 7);
10713 inst
.instruction
|= Rn
<< 3;
10719 constraint (Rd
== REG_PC
, BAD_PC
);
10720 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10721 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10722 constraint (Rs
== REG_PC
, BAD_PC
);
10723 reject_bad_reg (Rn
);
10725 /* If we get here, it can't be done in 16 bits. */
10726 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10727 _("shift must be constant"));
10728 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10729 inst
.instruction
|= Rd
<< 8;
10730 inst
.instruction
|= Rs
<< 16;
10731 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10732 _("shift value over 3 not allowed in thumb mode"));
10733 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10734 _("only LSL shift allowed in thumb mode"));
10735 encode_thumb32_shifted_operand (2);
10740 constraint (inst
.instruction
== T_MNEM_adds
10741 || inst
.instruction
== T_MNEM_subs
,
10744 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10746 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10747 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10750 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10751 ? 0x0000 : 0x8000);
10752 inst
.instruction
|= (Rd
<< 4) | Rs
;
10753 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10757 Rn
= inst
.operands
[2].reg
;
10758 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10760 /* We now have Rd, Rs, and Rn set to registers. */
10761 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10763 /* Can't do this for SUB. */
10764 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10765 inst
.instruction
= T_OPCODE_ADD_HI
;
10766 inst
.instruction
|= (Rd
& 8) << 4;
10767 inst
.instruction
|= (Rd
& 7);
10769 inst
.instruction
|= Rn
<< 3;
10771 inst
.instruction
|= Rs
<< 3;
10773 constraint (1, _("dest must overlap one source register"));
10777 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10778 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10779 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10789 Rd
= inst
.operands
[0].reg
;
10790 reject_bad_reg (Rd
);
10792 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10794 /* Defer to section relaxation. */
10795 inst
.relax
= inst
.instruction
;
10796 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10797 inst
.instruction
|= Rd
<< 4;
10799 else if (unified_syntax
&& inst
.size_req
!= 2)
10801 /* Generate a 32-bit opcode. */
10802 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10803 inst
.instruction
|= Rd
<< 8;
10804 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10805 inst
.reloc
.pc_rel
= 1;
10809 /* Generate a 16-bit opcode. */
10810 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10811 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10812 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10813 inst
.reloc
.pc_rel
= 1;
10814 inst
.instruction
|= Rd
<< 4;
10817 if (inst
.reloc
.exp
.X_op
== O_symbol
10818 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10819 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10820 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10821 inst
.reloc
.exp
.X_add_number
+= 1;
10824 /* Arithmetic instructions for which there is just one 16-bit
10825 instruction encoding, and it allows only two low registers.
10826 For maximal compatibility with ARM syntax, we allow three register
10827 operands even when Thumb-32 instructions are not available, as long
10828 as the first two are identical. For instance, both "sbc r0,r1" and
10829 "sbc r0,r0,r1" are allowed. */
10835 Rd
= inst
.operands
[0].reg
;
10836 Rs
= (inst
.operands
[1].present
10837 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10838 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10839 Rn
= inst
.operands
[2].reg
;
10841 reject_bad_reg (Rd
);
10842 reject_bad_reg (Rs
);
10843 if (inst
.operands
[2].isreg
)
10844 reject_bad_reg (Rn
);
10846 if (unified_syntax
)
10848 if (!inst
.operands
[2].isreg
)
10850 /* For an immediate, we always generate a 32-bit opcode;
10851 section relaxation will shrink it later if possible. */
10852 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10853 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10854 inst
.instruction
|= Rd
<< 8;
10855 inst
.instruction
|= Rs
<< 16;
10856 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10860 bfd_boolean narrow
;
10862 /* See if we can do this with a 16-bit instruction. */
10863 if (THUMB_SETS_FLAGS (inst
.instruction
))
10864 narrow
= !in_it_block ();
10866 narrow
= in_it_block ();
10868 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10870 if (inst
.operands
[2].shifted
)
10872 if (inst
.size_req
== 4)
10878 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10879 inst
.instruction
|= Rd
;
10880 inst
.instruction
|= Rn
<< 3;
10884 /* If we get here, it can't be done in 16 bits. */
10885 constraint (inst
.operands
[2].shifted
10886 && inst
.operands
[2].immisreg
,
10887 _("shift must be constant"));
10888 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10889 inst
.instruction
|= Rd
<< 8;
10890 inst
.instruction
|= Rs
<< 16;
10891 encode_thumb32_shifted_operand (2);
10896 /* On its face this is a lie - the instruction does set the
10897 flags. However, the only supported mnemonic in this mode
10898 says it doesn't. */
10899 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10901 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10902 _("unshifted register required"));
10903 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10904 constraint (Rd
!= Rs
,
10905 _("dest and source1 must be the same register"));
10907 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10908 inst
.instruction
|= Rd
;
10909 inst
.instruction
|= Rn
<< 3;
10913 /* Similarly, but for instructions where the arithmetic operation is
10914 commutative, so we can allow either of them to be different from
10915 the destination operand in a 16-bit instruction. For instance, all
10916 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10923 Rd
= inst
.operands
[0].reg
;
10924 Rs
= (inst
.operands
[1].present
10925 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10926 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10927 Rn
= inst
.operands
[2].reg
;
10929 reject_bad_reg (Rd
);
10930 reject_bad_reg (Rs
);
10931 if (inst
.operands
[2].isreg
)
10932 reject_bad_reg (Rn
);
10934 if (unified_syntax
)
10936 if (!inst
.operands
[2].isreg
)
10938 /* For an immediate, we always generate a 32-bit opcode;
10939 section relaxation will shrink it later if possible. */
10940 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10941 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10942 inst
.instruction
|= Rd
<< 8;
10943 inst
.instruction
|= Rs
<< 16;
10944 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10948 bfd_boolean narrow
;
10950 /* See if we can do this with a 16-bit instruction. */
10951 if (THUMB_SETS_FLAGS (inst
.instruction
))
10952 narrow
= !in_it_block ();
10954 narrow
= in_it_block ();
10956 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10958 if (inst
.operands
[2].shifted
)
10960 if (inst
.size_req
== 4)
10967 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10968 inst
.instruction
|= Rd
;
10969 inst
.instruction
|= Rn
<< 3;
10974 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10975 inst
.instruction
|= Rd
;
10976 inst
.instruction
|= Rs
<< 3;
10981 /* If we get here, it can't be done in 16 bits. */
10982 constraint (inst
.operands
[2].shifted
10983 && inst
.operands
[2].immisreg
,
10984 _("shift must be constant"));
10985 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10986 inst
.instruction
|= Rd
<< 8;
10987 inst
.instruction
|= Rs
<< 16;
10988 encode_thumb32_shifted_operand (2);
10993 /* On its face this is a lie - the instruction does set the
10994 flags. However, the only supported mnemonic in this mode
10995 says it doesn't. */
10996 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10998 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10999 _("unshifted register required"));
11000 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11002 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11003 inst
.instruction
|= Rd
;
11006 inst
.instruction
|= Rn
<< 3;
11008 inst
.instruction
|= Rs
<< 3;
11010 constraint (1, _("dest must overlap one source register"));
11018 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11019 constraint (msb
> 32, _("bit-field extends past end of register"));
11020 /* The instruction encoding stores the LSB and MSB,
11021 not the LSB and width. */
11022 Rd
= inst
.operands
[0].reg
;
11023 reject_bad_reg (Rd
);
11024 inst
.instruction
|= Rd
<< 8;
11025 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11026 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11027 inst
.instruction
|= msb
- 1;
11036 Rd
= inst
.operands
[0].reg
;
11037 reject_bad_reg (Rd
);
11039 /* #0 in second position is alternative syntax for bfc, which is
11040 the same instruction but with REG_PC in the Rm field. */
11041 if (!inst
.operands
[1].isreg
)
11045 Rn
= inst
.operands
[1].reg
;
11046 reject_bad_reg (Rn
);
11049 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11050 constraint (msb
> 32, _("bit-field extends past end of register"));
11051 /* The instruction encoding stores the LSB and MSB,
11052 not the LSB and width. */
11053 inst
.instruction
|= Rd
<< 8;
11054 inst
.instruction
|= Rn
<< 16;
11055 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11056 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11057 inst
.instruction
|= msb
- 1;
11065 Rd
= inst
.operands
[0].reg
;
11066 Rn
= inst
.operands
[1].reg
;
11068 reject_bad_reg (Rd
);
11069 reject_bad_reg (Rn
);
11071 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11072 _("bit-field extends past end of register"));
11073 inst
.instruction
|= Rd
<< 8;
11074 inst
.instruction
|= Rn
<< 16;
11075 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11076 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11077 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11080 /* ARM V5 Thumb BLX (argument parse)
11081 BLX <target_addr> which is BLX(1)
11082 BLX <Rm> which is BLX(2)
11083 Unfortunately, there are two different opcodes for this mnemonic.
11084 So, the insns[].value is not used, and the code here zaps values
11085 into inst.instruction.
11087 ??? How to take advantage of the additional two bits of displacement
11088 available in Thumb32 mode? Need new relocation? */
11093 set_it_insn_type_last ();
11095 if (inst
.operands
[0].isreg
)
11097 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11098 /* We have a register, so this is BLX(2). */
11099 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11103 /* No register. This must be BLX(1). */
11104 inst
.instruction
= 0xf000e800;
11105 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11114 bfd_reloc_code_real_type reloc
;
11117 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11119 if (in_it_block ())
11121 /* Conditional branches inside IT blocks are encoded as unconditional
11123 cond
= COND_ALWAYS
;
11128 if (cond
!= COND_ALWAYS
)
11129 opcode
= T_MNEM_bcond
;
11131 opcode
= inst
.instruction
;
11134 && (inst
.size_req
== 4
11135 || (inst
.size_req
!= 2
11136 && (inst
.operands
[0].hasreloc
11137 || inst
.reloc
.exp
.X_op
== O_constant
))))
11139 inst
.instruction
= THUMB_OP32(opcode
);
11140 if (cond
== COND_ALWAYS
)
11141 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11144 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11145 _("selected architecture does not support "
11146 "wide conditional branch instruction"));
11148 gas_assert (cond
!= 0xF);
11149 inst
.instruction
|= cond
<< 22;
11150 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11155 inst
.instruction
= THUMB_OP16(opcode
);
11156 if (cond
== COND_ALWAYS
)
11157 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11160 inst
.instruction
|= cond
<< 8;
11161 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11163 /* Allow section relaxation. */
11164 if (unified_syntax
&& inst
.size_req
!= 2)
11165 inst
.relax
= opcode
;
11167 inst
.reloc
.type
= reloc
;
11168 inst
.reloc
.pc_rel
= 1;
11171 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11172 between the two is the maximum immediate allowed - which is passed in
11175 do_t_bkpt_hlt1 (int range
)
11177 constraint (inst
.cond
!= COND_ALWAYS
,
11178 _("instruction is always unconditional"));
11179 if (inst
.operands
[0].present
)
11181 constraint (inst
.operands
[0].imm
> range
,
11182 _("immediate value out of range"));
11183 inst
.instruction
|= inst
.operands
[0].imm
;
11186 set_it_insn_type (NEUTRAL_IT_INSN
);
11192 do_t_bkpt_hlt1 (63);
11198 do_t_bkpt_hlt1 (255);
11202 do_t_branch23 (void)
11204 set_it_insn_type_last ();
11205 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11207 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11208 this file. We used to simply ignore the PLT reloc type here --
11209 the branch encoding is now needed to deal with TLSCALL relocs.
11210 So if we see a PLT reloc now, put it back to how it used to be to
11211 keep the preexisting behaviour. */
11212 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11213 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11215 #if defined(OBJ_COFF)
11216 /* If the destination of the branch is a defined symbol which does not have
11217 the THUMB_FUNC attribute, then we must be calling a function which has
11218 the (interfacearm) attribute. We look for the Thumb entry point to that
11219 function and change the branch to refer to that function instead. */
11220 if ( inst
.reloc
.exp
.X_op
== O_symbol
11221 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11222 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11223 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11224 inst
.reloc
.exp
.X_add_symbol
=
11225 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11232 set_it_insn_type_last ();
11233 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11234 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11235 should cause the alignment to be checked once it is known. This is
11236 because BX PC only works if the instruction is word aligned. */
11244 set_it_insn_type_last ();
11245 Rm
= inst
.operands
[0].reg
;
11246 reject_bad_reg (Rm
);
11247 inst
.instruction
|= Rm
<< 16;
11256 Rd
= inst
.operands
[0].reg
;
11257 Rm
= inst
.operands
[1].reg
;
11259 reject_bad_reg (Rd
);
11260 reject_bad_reg (Rm
);
11262 inst
.instruction
|= Rd
<< 8;
11263 inst
.instruction
|= Rm
<< 16;
11264 inst
.instruction
|= Rm
;
11270 set_it_insn_type (OUTSIDE_IT_INSN
);
11271 inst
.instruction
|= inst
.operands
[0].imm
;
11277 set_it_insn_type (OUTSIDE_IT_INSN
);
11279 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11280 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11282 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11283 inst
.instruction
= 0xf3af8000;
11284 inst
.instruction
|= imod
<< 9;
11285 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11286 if (inst
.operands
[1].present
)
11287 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11291 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11292 && (inst
.operands
[0].imm
& 4),
11293 _("selected processor does not support 'A' form "
11294 "of this instruction"));
11295 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11296 _("Thumb does not support the 2-argument "
11297 "form of this instruction"));
11298 inst
.instruction
|= inst
.operands
[0].imm
;
11302 /* THUMB CPY instruction (argument parse). */
11307 if (inst
.size_req
== 4)
11309 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11310 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11311 inst
.instruction
|= inst
.operands
[1].reg
;
11315 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11316 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11317 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11324 set_it_insn_type (OUTSIDE_IT_INSN
);
11325 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11326 inst
.instruction
|= inst
.operands
[0].reg
;
11327 inst
.reloc
.pc_rel
= 1;
11328 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11334 inst
.instruction
|= inst
.operands
[0].imm
;
11340 unsigned Rd
, Rn
, Rm
;
11342 Rd
= inst
.operands
[0].reg
;
11343 Rn
= (inst
.operands
[1].present
11344 ? inst
.operands
[1].reg
: Rd
);
11345 Rm
= inst
.operands
[2].reg
;
11347 reject_bad_reg (Rd
);
11348 reject_bad_reg (Rn
);
11349 reject_bad_reg (Rm
);
11351 inst
.instruction
|= Rd
<< 8;
11352 inst
.instruction
|= Rn
<< 16;
11353 inst
.instruction
|= Rm
;
11359 if (unified_syntax
&& inst
.size_req
== 4)
11360 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11362 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11368 unsigned int cond
= inst
.operands
[0].imm
;
11370 set_it_insn_type (IT_INSN
);
11371 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11373 now_it
.warn_deprecated
= FALSE
;
11375 /* If the condition is a negative condition, invert the mask. */
11376 if ((cond
& 0x1) == 0x0)
11378 unsigned int mask
= inst
.instruction
& 0x000f;
11380 if ((mask
& 0x7) == 0)
11382 /* No conversion needed. */
11383 now_it
.block_length
= 1;
11385 else if ((mask
& 0x3) == 0)
11388 now_it
.block_length
= 2;
11390 else if ((mask
& 0x1) == 0)
11393 now_it
.block_length
= 3;
11398 now_it
.block_length
= 4;
11401 inst
.instruction
&= 0xfff0;
11402 inst
.instruction
|= mask
;
11405 inst
.instruction
|= cond
<< 4;
11408 /* Helper function used for both push/pop and ldm/stm. */
11410 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11414 load
= (inst
.instruction
& (1 << 20)) != 0;
11416 if (mask
& (1 << 13))
11417 inst
.error
= _("SP not allowed in register list");
11419 if ((mask
& (1 << base
)) != 0
11421 inst
.error
= _("having the base register in the register list when "
11422 "using write back is UNPREDICTABLE");
11426 if (mask
& (1 << 15))
11428 if (mask
& (1 << 14))
11429 inst
.error
= _("LR and PC should not both be in register list");
11431 set_it_insn_type_last ();
11436 if (mask
& (1 << 15))
11437 inst
.error
= _("PC not allowed in register list");
11440 if ((mask
& (mask
- 1)) == 0)
11442 /* Single register transfers implemented as str/ldr. */
11445 if (inst
.instruction
& (1 << 23))
11446 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11448 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11452 if (inst
.instruction
& (1 << 23))
11453 inst
.instruction
= 0x00800000; /* ia -> [base] */
11455 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11458 inst
.instruction
|= 0xf8400000;
11460 inst
.instruction
|= 0x00100000;
11462 mask
= ffs (mask
) - 1;
11465 else if (writeback
)
11466 inst
.instruction
|= WRITE_BACK
;
11468 inst
.instruction
|= mask
;
11469 inst
.instruction
|= base
<< 16;
11475 /* This really doesn't seem worth it. */
11476 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11477 _("expression too complex"));
11478 constraint (inst
.operands
[1].writeback
,
11479 _("Thumb load/store multiple does not support {reglist}^"));
11481 if (unified_syntax
)
11483 bfd_boolean narrow
;
11487 /* See if we can use a 16-bit instruction. */
11488 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11489 && inst
.size_req
!= 4
11490 && !(inst
.operands
[1].imm
& ~0xff))
11492 mask
= 1 << inst
.operands
[0].reg
;
11494 if (inst
.operands
[0].reg
<= 7)
11496 if (inst
.instruction
== T_MNEM_stmia
11497 ? inst
.operands
[0].writeback
11498 : (inst
.operands
[0].writeback
11499 == !(inst
.operands
[1].imm
& mask
)))
11501 if (inst
.instruction
== T_MNEM_stmia
11502 && (inst
.operands
[1].imm
& mask
)
11503 && (inst
.operands
[1].imm
& (mask
- 1)))
11504 as_warn (_("value stored for r%d is UNKNOWN"),
11505 inst
.operands
[0].reg
);
11507 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11508 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11509 inst
.instruction
|= inst
.operands
[1].imm
;
11512 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11514 /* This means 1 register in reg list one of 3 situations:
11515 1. Instruction is stmia, but without writeback.
11516 2. lmdia without writeback, but with Rn not in
11518 3. ldmia with writeback, but with Rn in reglist.
11519 Case 3 is UNPREDICTABLE behaviour, so we handle
11520 case 1 and 2 which can be converted into a 16-bit
11521 str or ldr. The SP cases are handled below. */
11522 unsigned long opcode
;
11523 /* First, record an error for Case 3. */
11524 if (inst
.operands
[1].imm
& mask
11525 && inst
.operands
[0].writeback
)
11527 _("having the base register in the register list when "
11528 "using write back is UNPREDICTABLE");
11530 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11532 inst
.instruction
= THUMB_OP16 (opcode
);
11533 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11534 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11538 else if (inst
.operands
[0] .reg
== REG_SP
)
11540 if (inst
.operands
[0].writeback
)
11543 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11544 ? T_MNEM_push
: T_MNEM_pop
);
11545 inst
.instruction
|= inst
.operands
[1].imm
;
11548 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11551 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11552 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11553 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11561 if (inst
.instruction
< 0xffff)
11562 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11564 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11565 inst
.operands
[0].writeback
);
11570 constraint (inst
.operands
[0].reg
> 7
11571 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11572 constraint (inst
.instruction
!= T_MNEM_ldmia
11573 && inst
.instruction
!= T_MNEM_stmia
,
11574 _("Thumb-2 instruction only valid in unified syntax"));
11575 if (inst
.instruction
== T_MNEM_stmia
)
11577 if (!inst
.operands
[0].writeback
)
11578 as_warn (_("this instruction will write back the base register"));
11579 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11580 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11581 as_warn (_("value stored for r%d is UNKNOWN"),
11582 inst
.operands
[0].reg
);
11586 if (!inst
.operands
[0].writeback
11587 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11588 as_warn (_("this instruction will write back the base register"));
11589 else if (inst
.operands
[0].writeback
11590 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11591 as_warn (_("this instruction will not write back the base register"));
11594 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11595 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11596 inst
.instruction
|= inst
.operands
[1].imm
;
11603 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11604 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11605 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11606 || inst
.operands
[1].negative
,
11609 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11611 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11612 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11613 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11619 if (!inst
.operands
[1].present
)
11621 constraint (inst
.operands
[0].reg
== REG_LR
,
11622 _("r14 not allowed as first register "
11623 "when second register is omitted"));
11624 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11626 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11629 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11630 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11631 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11637 unsigned long opcode
;
11640 if (inst
.operands
[0].isreg
11641 && !inst
.operands
[0].preind
11642 && inst
.operands
[0].reg
== REG_PC
)
11643 set_it_insn_type_last ();
11645 opcode
= inst
.instruction
;
11646 if (unified_syntax
)
11648 if (!inst
.operands
[1].isreg
)
11650 if (opcode
<= 0xffff)
11651 inst
.instruction
= THUMB_OP32 (opcode
);
11652 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11655 if (inst
.operands
[1].isreg
11656 && !inst
.operands
[1].writeback
11657 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11658 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11659 && opcode
<= 0xffff
11660 && inst
.size_req
!= 4)
11662 /* Insn may have a 16-bit form. */
11663 Rn
= inst
.operands
[1].reg
;
11664 if (inst
.operands
[1].immisreg
)
11666 inst
.instruction
= THUMB_OP16 (opcode
);
11668 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11670 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11671 reject_bad_reg (inst
.operands
[1].imm
);
11673 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11674 && opcode
!= T_MNEM_ldrsb
)
11675 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11676 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11683 if (inst
.reloc
.pc_rel
)
11684 opcode
= T_MNEM_ldr_pc2
;
11686 opcode
= T_MNEM_ldr_pc
;
11690 if (opcode
== T_MNEM_ldr
)
11691 opcode
= T_MNEM_ldr_sp
;
11693 opcode
= T_MNEM_str_sp
;
11695 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11699 inst
.instruction
= inst
.operands
[0].reg
;
11700 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11702 inst
.instruction
|= THUMB_OP16 (opcode
);
11703 if (inst
.size_req
== 2)
11704 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11706 inst
.relax
= opcode
;
11710 /* Definitely a 32-bit variant. */
11712 /* Warning for Erratum 752419. */
11713 if (opcode
== T_MNEM_ldr
11714 && inst
.operands
[0].reg
== REG_SP
11715 && inst
.operands
[1].writeback
== 1
11716 && !inst
.operands
[1].immisreg
)
11718 if (no_cpu_selected ()
11719 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11720 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11721 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11722 as_warn (_("This instruction may be unpredictable "
11723 "if executed on M-profile cores "
11724 "with interrupts enabled."));
11727 /* Do some validations regarding addressing modes. */
11728 if (inst
.operands
[1].immisreg
)
11729 reject_bad_reg (inst
.operands
[1].imm
);
11731 constraint (inst
.operands
[1].writeback
== 1
11732 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11735 inst
.instruction
= THUMB_OP32 (opcode
);
11736 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11737 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11738 check_ldr_r15_aligned ();
11742 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11744 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11746 /* Only [Rn,Rm] is acceptable. */
11747 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11748 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11749 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11750 || inst
.operands
[1].negative
,
11751 _("Thumb does not support this addressing mode"));
11752 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11756 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11757 if (!inst
.operands
[1].isreg
)
11758 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11761 constraint (!inst
.operands
[1].preind
11762 || inst
.operands
[1].shifted
11763 || inst
.operands
[1].writeback
,
11764 _("Thumb does not support this addressing mode"));
11765 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11767 constraint (inst
.instruction
& 0x0600,
11768 _("byte or halfword not valid for base register"));
11769 constraint (inst
.operands
[1].reg
== REG_PC
11770 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11771 _("r15 based store not allowed"));
11772 constraint (inst
.operands
[1].immisreg
,
11773 _("invalid base register for register offset"));
11775 if (inst
.operands
[1].reg
== REG_PC
)
11776 inst
.instruction
= T_OPCODE_LDR_PC
;
11777 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11778 inst
.instruction
= T_OPCODE_LDR_SP
;
11780 inst
.instruction
= T_OPCODE_STR_SP
;
11782 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11783 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11787 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11788 if (!inst
.operands
[1].immisreg
)
11790 /* Immediate offset. */
11791 inst
.instruction
|= inst
.operands
[0].reg
;
11792 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11793 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11797 /* Register offset. */
11798 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11799 constraint (inst
.operands
[1].negative
,
11800 _("Thumb does not support this addressing mode"));
11803 switch (inst
.instruction
)
11805 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11806 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11807 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11808 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11809 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11810 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11811 case 0x5600 /* ldrsb */:
11812 case 0x5e00 /* ldrsh */: break;
11816 inst
.instruction
|= inst
.operands
[0].reg
;
11817 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11818 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11824 if (!inst
.operands
[1].present
)
11826 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11827 constraint (inst
.operands
[0].reg
== REG_LR
,
11828 _("r14 not allowed here"));
11829 constraint (inst
.operands
[0].reg
== REG_R12
,
11830 _("r12 not allowed here"));
11833 if (inst
.operands
[2].writeback
11834 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11835 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11836 as_warn (_("base register written back, and overlaps "
11837 "one of transfer registers"));
11839 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11840 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11841 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11847 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11848 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11854 unsigned Rd
, Rn
, Rm
, Ra
;
11856 Rd
= inst
.operands
[0].reg
;
11857 Rn
= inst
.operands
[1].reg
;
11858 Rm
= inst
.operands
[2].reg
;
11859 Ra
= inst
.operands
[3].reg
;
11861 reject_bad_reg (Rd
);
11862 reject_bad_reg (Rn
);
11863 reject_bad_reg (Rm
);
11864 reject_bad_reg (Ra
);
11866 inst
.instruction
|= Rd
<< 8;
11867 inst
.instruction
|= Rn
<< 16;
11868 inst
.instruction
|= Rm
;
11869 inst
.instruction
|= Ra
<< 12;
11875 unsigned RdLo
, RdHi
, Rn
, Rm
;
11877 RdLo
= inst
.operands
[0].reg
;
11878 RdHi
= inst
.operands
[1].reg
;
11879 Rn
= inst
.operands
[2].reg
;
11880 Rm
= inst
.operands
[3].reg
;
11882 reject_bad_reg (RdLo
);
11883 reject_bad_reg (RdHi
);
11884 reject_bad_reg (Rn
);
11885 reject_bad_reg (Rm
);
11887 inst
.instruction
|= RdLo
<< 12;
11888 inst
.instruction
|= RdHi
<< 8;
11889 inst
.instruction
|= Rn
<< 16;
11890 inst
.instruction
|= Rm
;
11894 do_t_mov_cmp (void)
11898 Rn
= inst
.operands
[0].reg
;
11899 Rm
= inst
.operands
[1].reg
;
11902 set_it_insn_type_last ();
11904 if (unified_syntax
)
11906 int r0off
= (inst
.instruction
== T_MNEM_mov
11907 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11908 unsigned long opcode
;
11909 bfd_boolean narrow
;
11910 bfd_boolean low_regs
;
11912 low_regs
= (Rn
<= 7 && Rm
<= 7);
11913 opcode
= inst
.instruction
;
11914 if (in_it_block ())
11915 narrow
= opcode
!= T_MNEM_movs
;
11917 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11918 if (inst
.size_req
== 4
11919 || inst
.operands
[1].shifted
)
11922 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11923 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11924 && !inst
.operands
[1].shifted
11928 inst
.instruction
= T2_SUBS_PC_LR
;
11932 if (opcode
== T_MNEM_cmp
)
11934 constraint (Rn
== REG_PC
, BAD_PC
);
11937 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11939 warn_deprecated_sp (Rm
);
11940 /* R15 was documented as a valid choice for Rm in ARMv6,
11941 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11942 tools reject R15, so we do too. */
11943 constraint (Rm
== REG_PC
, BAD_PC
);
11946 reject_bad_reg (Rm
);
11948 else if (opcode
== T_MNEM_mov
11949 || opcode
== T_MNEM_movs
)
11951 if (inst
.operands
[1].isreg
)
11953 if (opcode
== T_MNEM_movs
)
11955 reject_bad_reg (Rn
);
11956 reject_bad_reg (Rm
);
11960 /* This is mov.n. */
11961 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11962 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11964 as_tsktsk (_("Use of r%u as a source register is "
11965 "deprecated when r%u is the destination "
11966 "register."), Rm
, Rn
);
11971 /* This is mov.w. */
11972 constraint (Rn
== REG_PC
, BAD_PC
);
11973 constraint (Rm
== REG_PC
, BAD_PC
);
11974 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11975 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11979 reject_bad_reg (Rn
);
11982 if (!inst
.operands
[1].isreg
)
11984 /* Immediate operand. */
11985 if (!in_it_block () && opcode
== T_MNEM_mov
)
11987 if (low_regs
&& narrow
)
11989 inst
.instruction
= THUMB_OP16 (opcode
);
11990 inst
.instruction
|= Rn
<< 8;
11991 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11992 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11994 if (inst
.size_req
== 2)
11995 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11997 inst
.relax
= opcode
;
12002 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12003 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
12004 THUMB1_RELOC_ONLY
);
12006 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12007 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12008 inst
.instruction
|= Rn
<< r0off
;
12009 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12012 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12013 && (inst
.instruction
== T_MNEM_mov
12014 || inst
.instruction
== T_MNEM_movs
))
12016 /* Register shifts are encoded as separate shift instructions. */
12017 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12019 if (in_it_block ())
12024 if (inst
.size_req
== 4)
12027 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12033 switch (inst
.operands
[1].shift_kind
)
12036 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12039 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12042 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12045 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12051 inst
.instruction
= opcode
;
12054 inst
.instruction
|= Rn
;
12055 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12060 inst
.instruction
|= CONDS_BIT
;
12062 inst
.instruction
|= Rn
<< 8;
12063 inst
.instruction
|= Rm
<< 16;
12064 inst
.instruction
|= inst
.operands
[1].imm
;
12069 /* Some mov with immediate shift have narrow variants.
12070 Register shifts are handled above. */
12071 if (low_regs
&& inst
.operands
[1].shifted
12072 && (inst
.instruction
== T_MNEM_mov
12073 || inst
.instruction
== T_MNEM_movs
))
12075 if (in_it_block ())
12076 narrow
= (inst
.instruction
== T_MNEM_mov
);
12078 narrow
= (inst
.instruction
== T_MNEM_movs
);
12083 switch (inst
.operands
[1].shift_kind
)
12085 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12086 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12087 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12088 default: narrow
= FALSE
; break;
12094 inst
.instruction
|= Rn
;
12095 inst
.instruction
|= Rm
<< 3;
12096 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12100 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12101 inst
.instruction
|= Rn
<< r0off
;
12102 encode_thumb32_shifted_operand (1);
12106 switch (inst
.instruction
)
12109 /* In v4t or v5t a move of two lowregs produces unpredictable
12110 results. Don't allow this. */
12113 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12114 "MOV Rd, Rs with two low registers is not "
12115 "permitted on this architecture");
12116 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12120 inst
.instruction
= T_OPCODE_MOV_HR
;
12121 inst
.instruction
|= (Rn
& 0x8) << 4;
12122 inst
.instruction
|= (Rn
& 0x7);
12123 inst
.instruction
|= Rm
<< 3;
12127 /* We know we have low registers at this point.
12128 Generate LSLS Rd, Rs, #0. */
12129 inst
.instruction
= T_OPCODE_LSL_I
;
12130 inst
.instruction
|= Rn
;
12131 inst
.instruction
|= Rm
<< 3;
12137 inst
.instruction
= T_OPCODE_CMP_LR
;
12138 inst
.instruction
|= Rn
;
12139 inst
.instruction
|= Rm
<< 3;
12143 inst
.instruction
= T_OPCODE_CMP_HR
;
12144 inst
.instruction
|= (Rn
& 0x8) << 4;
12145 inst
.instruction
|= (Rn
& 0x7);
12146 inst
.instruction
|= Rm
<< 3;
12153 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12155 /* PR 10443: Do not silently ignore shifted operands. */
12156 constraint (inst
.operands
[1].shifted
,
12157 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12159 if (inst
.operands
[1].isreg
)
12161 if (Rn
< 8 && Rm
< 8)
12163 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12164 since a MOV instruction produces unpredictable results. */
12165 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12166 inst
.instruction
= T_OPCODE_ADD_I3
;
12168 inst
.instruction
= T_OPCODE_CMP_LR
;
12170 inst
.instruction
|= Rn
;
12171 inst
.instruction
|= Rm
<< 3;
12175 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12176 inst
.instruction
= T_OPCODE_MOV_HR
;
12178 inst
.instruction
= T_OPCODE_CMP_HR
;
12184 constraint (Rn
> 7,
12185 _("only lo regs allowed with immediate"));
12186 inst
.instruction
|= Rn
<< 8;
12187 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12198 top
= (inst
.instruction
& 0x00800000) != 0;
12199 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12201 constraint (top
, _(":lower16: not allowed in this instruction"));
12202 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12204 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12206 constraint (!top
, _(":upper16: not allowed in this instruction"));
12207 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12210 Rd
= inst
.operands
[0].reg
;
12211 reject_bad_reg (Rd
);
12213 inst
.instruction
|= Rd
<< 8;
12214 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12216 imm
= inst
.reloc
.exp
.X_add_number
;
12217 inst
.instruction
|= (imm
& 0xf000) << 4;
12218 inst
.instruction
|= (imm
& 0x0800) << 15;
12219 inst
.instruction
|= (imm
& 0x0700) << 4;
12220 inst
.instruction
|= (imm
& 0x00ff);
12225 do_t_mvn_tst (void)
12229 Rn
= inst
.operands
[0].reg
;
12230 Rm
= inst
.operands
[1].reg
;
12232 if (inst
.instruction
== T_MNEM_cmp
12233 || inst
.instruction
== T_MNEM_cmn
)
12234 constraint (Rn
== REG_PC
, BAD_PC
);
12236 reject_bad_reg (Rn
);
12237 reject_bad_reg (Rm
);
12239 if (unified_syntax
)
12241 int r0off
= (inst
.instruction
== T_MNEM_mvn
12242 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12243 bfd_boolean narrow
;
12245 if (inst
.size_req
== 4
12246 || inst
.instruction
> 0xffff
12247 || inst
.operands
[1].shifted
12248 || Rn
> 7 || Rm
> 7)
12250 else if (inst
.instruction
== T_MNEM_cmn
12251 || inst
.instruction
== T_MNEM_tst
)
12253 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12254 narrow
= !in_it_block ();
12256 narrow
= in_it_block ();
12258 if (!inst
.operands
[1].isreg
)
12260 /* For an immediate, we always generate a 32-bit opcode;
12261 section relaxation will shrink it later if possible. */
12262 if (inst
.instruction
< 0xffff)
12263 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12264 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12265 inst
.instruction
|= Rn
<< r0off
;
12266 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12270 /* See if we can do this with a 16-bit instruction. */
12273 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12274 inst
.instruction
|= Rn
;
12275 inst
.instruction
|= Rm
<< 3;
12279 constraint (inst
.operands
[1].shifted
12280 && inst
.operands
[1].immisreg
,
12281 _("shift must be constant"));
12282 if (inst
.instruction
< 0xffff)
12283 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12284 inst
.instruction
|= Rn
<< r0off
;
12285 encode_thumb32_shifted_operand (1);
12291 constraint (inst
.instruction
> 0xffff
12292 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12293 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12294 _("unshifted register required"));
12295 constraint (Rn
> 7 || Rm
> 7,
12298 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12299 inst
.instruction
|= Rn
;
12300 inst
.instruction
|= Rm
<< 3;
12309 if (do_vfp_nsyn_mrs () == SUCCESS
)
12312 Rd
= inst
.operands
[0].reg
;
12313 reject_bad_reg (Rd
);
12314 inst
.instruction
|= Rd
<< 8;
12316 if (inst
.operands
[1].isreg
)
12318 unsigned br
= inst
.operands
[1].reg
;
12319 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12320 as_bad (_("bad register for mrs"));
12322 inst
.instruction
|= br
& (0xf << 16);
12323 inst
.instruction
|= (br
& 0x300) >> 4;
12324 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12328 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12330 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12332 /* PR gas/12698: The constraint is only applied for m_profile.
12333 If the user has specified -march=all, we want to ignore it as
12334 we are building for any CPU type, including non-m variants. */
12335 bfd_boolean m_profile
=
12336 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12337 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12338 "not support requested special purpose register"));
12341 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12343 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12344 _("'APSR', 'CPSR' or 'SPSR' expected"));
12346 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12347 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12348 inst
.instruction
|= 0xf0000;
12358 if (do_vfp_nsyn_msr () == SUCCESS
)
12361 constraint (!inst
.operands
[1].isreg
,
12362 _("Thumb encoding does not support an immediate here"));
12364 if (inst
.operands
[0].isreg
)
12365 flags
= (int)(inst
.operands
[0].reg
);
12367 flags
= inst
.operands
[0].imm
;
12369 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12371 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12373 /* PR gas/12698: The constraint is only applied for m_profile.
12374 If the user has specified -march=all, we want to ignore it as
12375 we are building for any CPU type, including non-m variants. */
12376 bfd_boolean m_profile
=
12377 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12378 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12379 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12380 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12381 && bits
!= PSR_f
)) && m_profile
,
12382 _("selected processor does not support requested special "
12383 "purpose register"));
12386 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12387 "requested special purpose register"));
12389 Rn
= inst
.operands
[1].reg
;
12390 reject_bad_reg (Rn
);
12392 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12393 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12394 inst
.instruction
|= (flags
& 0x300) >> 4;
12395 inst
.instruction
|= (flags
& 0xff);
12396 inst
.instruction
|= Rn
<< 16;
12402 bfd_boolean narrow
;
12403 unsigned Rd
, Rn
, Rm
;
12405 if (!inst
.operands
[2].present
)
12406 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12408 Rd
= inst
.operands
[0].reg
;
12409 Rn
= inst
.operands
[1].reg
;
12410 Rm
= inst
.operands
[2].reg
;
12412 if (unified_syntax
)
12414 if (inst
.size_req
== 4
12420 else if (inst
.instruction
== T_MNEM_muls
)
12421 narrow
= !in_it_block ();
12423 narrow
= in_it_block ();
12427 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12428 constraint (Rn
> 7 || Rm
> 7,
12435 /* 16-bit MULS/Conditional MUL. */
12436 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12437 inst
.instruction
|= Rd
;
12440 inst
.instruction
|= Rm
<< 3;
12442 inst
.instruction
|= Rn
<< 3;
12444 constraint (1, _("dest must overlap one source register"));
12448 constraint (inst
.instruction
!= T_MNEM_mul
,
12449 _("Thumb-2 MUL must not set flags"));
12451 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12452 inst
.instruction
|= Rd
<< 8;
12453 inst
.instruction
|= Rn
<< 16;
12454 inst
.instruction
|= Rm
<< 0;
12456 reject_bad_reg (Rd
);
12457 reject_bad_reg (Rn
);
12458 reject_bad_reg (Rm
);
12465 unsigned RdLo
, RdHi
, Rn
, Rm
;
12467 RdLo
= inst
.operands
[0].reg
;
12468 RdHi
= inst
.operands
[1].reg
;
12469 Rn
= inst
.operands
[2].reg
;
12470 Rm
= inst
.operands
[3].reg
;
12472 reject_bad_reg (RdLo
);
12473 reject_bad_reg (RdHi
);
12474 reject_bad_reg (Rn
);
12475 reject_bad_reg (Rm
);
12477 inst
.instruction
|= RdLo
<< 12;
12478 inst
.instruction
|= RdHi
<< 8;
12479 inst
.instruction
|= Rn
<< 16;
12480 inst
.instruction
|= Rm
;
12483 as_tsktsk (_("rdhi and rdlo must be different"));
12489 set_it_insn_type (NEUTRAL_IT_INSN
);
12491 if (unified_syntax
)
12493 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12495 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12496 inst
.instruction
|= inst
.operands
[0].imm
;
12500 /* PR9722: Check for Thumb2 availability before
12501 generating a thumb2 nop instruction. */
12502 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12504 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12505 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12508 inst
.instruction
= 0x46c0;
12513 constraint (inst
.operands
[0].present
,
12514 _("Thumb does not support NOP with hints"));
12515 inst
.instruction
= 0x46c0;
12522 if (unified_syntax
)
12524 bfd_boolean narrow
;
12526 if (THUMB_SETS_FLAGS (inst
.instruction
))
12527 narrow
= !in_it_block ();
12529 narrow
= in_it_block ();
12530 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12532 if (inst
.size_req
== 4)
12537 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12538 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12539 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12543 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12544 inst
.instruction
|= inst
.operands
[0].reg
;
12545 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12550 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12552 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12554 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12555 inst
.instruction
|= inst
.operands
[0].reg
;
12556 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12565 Rd
= inst
.operands
[0].reg
;
12566 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12568 reject_bad_reg (Rd
);
12569 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12570 reject_bad_reg (Rn
);
12572 inst
.instruction
|= Rd
<< 8;
12573 inst
.instruction
|= Rn
<< 16;
12575 if (!inst
.operands
[2].isreg
)
12577 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12578 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12584 Rm
= inst
.operands
[2].reg
;
12585 reject_bad_reg (Rm
);
12587 constraint (inst
.operands
[2].shifted
12588 && inst
.operands
[2].immisreg
,
12589 _("shift must be constant"));
12590 encode_thumb32_shifted_operand (2);
12597 unsigned Rd
, Rn
, Rm
;
12599 Rd
= inst
.operands
[0].reg
;
12600 Rn
= inst
.operands
[1].reg
;
12601 Rm
= inst
.operands
[2].reg
;
12603 reject_bad_reg (Rd
);
12604 reject_bad_reg (Rn
);
12605 reject_bad_reg (Rm
);
12607 inst
.instruction
|= Rd
<< 8;
12608 inst
.instruction
|= Rn
<< 16;
12609 inst
.instruction
|= Rm
;
12610 if (inst
.operands
[3].present
)
12612 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12613 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12614 _("expression too complex"));
12615 inst
.instruction
|= (val
& 0x1c) << 10;
12616 inst
.instruction
|= (val
& 0x03) << 6;
12623 if (!inst
.operands
[3].present
)
12627 inst
.instruction
&= ~0x00000020;
12629 /* PR 10168. Swap the Rm and Rn registers. */
12630 Rtmp
= inst
.operands
[1].reg
;
12631 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12632 inst
.operands
[2].reg
= Rtmp
;
12640 if (inst
.operands
[0].immisreg
)
12641 reject_bad_reg (inst
.operands
[0].imm
);
12643 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12647 do_t_push_pop (void)
12651 constraint (inst
.operands
[0].writeback
,
12652 _("push/pop do not support {reglist}^"));
12653 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12654 _("expression too complex"));
12656 mask
= inst
.operands
[0].imm
;
12657 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12658 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12659 else if (inst
.size_req
!= 4
12660 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12661 ? REG_LR
: REG_PC
)))
12663 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12664 inst
.instruction
|= THUMB_PP_PC_LR
;
12665 inst
.instruction
|= mask
& 0xff;
12667 else if (unified_syntax
)
12669 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12670 encode_thumb2_ldmstm (13, mask
, TRUE
);
12674 inst
.error
= _("invalid register list to push/pop instruction");
12684 Rd
= inst
.operands
[0].reg
;
12685 Rm
= inst
.operands
[1].reg
;
12687 reject_bad_reg (Rd
);
12688 reject_bad_reg (Rm
);
12690 inst
.instruction
|= Rd
<< 8;
12691 inst
.instruction
|= Rm
<< 16;
12692 inst
.instruction
|= Rm
;
12700 Rd
= inst
.operands
[0].reg
;
12701 Rm
= inst
.operands
[1].reg
;
12703 reject_bad_reg (Rd
);
12704 reject_bad_reg (Rm
);
12706 if (Rd
<= 7 && Rm
<= 7
12707 && inst
.size_req
!= 4)
12709 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12710 inst
.instruction
|= Rd
;
12711 inst
.instruction
|= Rm
<< 3;
12713 else if (unified_syntax
)
12715 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12716 inst
.instruction
|= Rd
<< 8;
12717 inst
.instruction
|= Rm
<< 16;
12718 inst
.instruction
|= Rm
;
12721 inst
.error
= BAD_HIREG
;
12729 Rd
= inst
.operands
[0].reg
;
12730 Rm
= inst
.operands
[1].reg
;
12732 reject_bad_reg (Rd
);
12733 reject_bad_reg (Rm
);
12735 inst
.instruction
|= Rd
<< 8;
12736 inst
.instruction
|= Rm
;
12744 Rd
= inst
.operands
[0].reg
;
12745 Rs
= (inst
.operands
[1].present
12746 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12747 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12749 reject_bad_reg (Rd
);
12750 reject_bad_reg (Rs
);
12751 if (inst
.operands
[2].isreg
)
12752 reject_bad_reg (inst
.operands
[2].reg
);
12754 inst
.instruction
|= Rd
<< 8;
12755 inst
.instruction
|= Rs
<< 16;
12756 if (!inst
.operands
[2].isreg
)
12758 bfd_boolean narrow
;
12760 if ((inst
.instruction
& 0x00100000) != 0)
12761 narrow
= !in_it_block ();
12763 narrow
= in_it_block ();
12765 if (Rd
> 7 || Rs
> 7)
12768 if (inst
.size_req
== 4 || !unified_syntax
)
12771 if (inst
.reloc
.exp
.X_op
!= O_constant
12772 || inst
.reloc
.exp
.X_add_number
!= 0)
12775 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12776 relaxation, but it doesn't seem worth the hassle. */
12779 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12780 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12781 inst
.instruction
|= Rs
<< 3;
12782 inst
.instruction
|= Rd
;
12786 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12787 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12791 encode_thumb32_shifted_operand (2);
12797 if (warn_on_deprecated
12798 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12799 as_tsktsk (_("setend use is deprecated for ARMv8"));
12801 set_it_insn_type (OUTSIDE_IT_INSN
);
12802 if (inst
.operands
[0].imm
)
12803 inst
.instruction
|= 0x8;
12809 if (!inst
.operands
[1].present
)
12810 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12812 if (unified_syntax
)
12814 bfd_boolean narrow
;
12817 switch (inst
.instruction
)
12820 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12822 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12824 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12826 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12830 if (THUMB_SETS_FLAGS (inst
.instruction
))
12831 narrow
= !in_it_block ();
12833 narrow
= in_it_block ();
12834 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12836 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12838 if (inst
.operands
[2].isreg
12839 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12840 || inst
.operands
[2].reg
> 7))
12842 if (inst
.size_req
== 4)
12845 reject_bad_reg (inst
.operands
[0].reg
);
12846 reject_bad_reg (inst
.operands
[1].reg
);
12850 if (inst
.operands
[2].isreg
)
12852 reject_bad_reg (inst
.operands
[2].reg
);
12853 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12854 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12855 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12856 inst
.instruction
|= inst
.operands
[2].reg
;
12858 /* PR 12854: Error on extraneous shifts. */
12859 constraint (inst
.operands
[2].shifted
,
12860 _("extraneous shift as part of operand to shift insn"));
12864 inst
.operands
[1].shifted
= 1;
12865 inst
.operands
[1].shift_kind
= shift_kind
;
12866 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12867 ? T_MNEM_movs
: T_MNEM_mov
);
12868 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12869 encode_thumb32_shifted_operand (1);
12870 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12871 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12876 if (inst
.operands
[2].isreg
)
12878 switch (shift_kind
)
12880 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12881 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12882 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12883 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12887 inst
.instruction
|= inst
.operands
[0].reg
;
12888 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12890 /* PR 12854: Error on extraneous shifts. */
12891 constraint (inst
.operands
[2].shifted
,
12892 _("extraneous shift as part of operand to shift insn"));
12896 switch (shift_kind
)
12898 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12899 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12900 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12903 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12904 inst
.instruction
|= inst
.operands
[0].reg
;
12905 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12911 constraint (inst
.operands
[0].reg
> 7
12912 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12913 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12915 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12917 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12918 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12919 _("source1 and dest must be same register"));
12921 switch (inst
.instruction
)
12923 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12924 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12925 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12926 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12930 inst
.instruction
|= inst
.operands
[0].reg
;
12931 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12933 /* PR 12854: Error on extraneous shifts. */
12934 constraint (inst
.operands
[2].shifted
,
12935 _("extraneous shift as part of operand to shift insn"));
12939 switch (inst
.instruction
)
12941 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12942 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12943 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12944 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12947 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12948 inst
.instruction
|= inst
.operands
[0].reg
;
12949 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12957 unsigned Rd
, Rn
, Rm
;
12959 Rd
= inst
.operands
[0].reg
;
12960 Rn
= inst
.operands
[1].reg
;
12961 Rm
= inst
.operands
[2].reg
;
12963 reject_bad_reg (Rd
);
12964 reject_bad_reg (Rn
);
12965 reject_bad_reg (Rm
);
12967 inst
.instruction
|= Rd
<< 8;
12968 inst
.instruction
|= Rn
<< 16;
12969 inst
.instruction
|= Rm
;
12975 unsigned Rd
, Rn
, Rm
;
12977 Rd
= inst
.operands
[0].reg
;
12978 Rm
= inst
.operands
[1].reg
;
12979 Rn
= inst
.operands
[2].reg
;
12981 reject_bad_reg (Rd
);
12982 reject_bad_reg (Rn
);
12983 reject_bad_reg (Rm
);
12985 inst
.instruction
|= Rd
<< 8;
12986 inst
.instruction
|= Rn
<< 16;
12987 inst
.instruction
|= Rm
;
12993 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12994 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12995 _("SMC is not permitted on this architecture"));
12996 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12997 _("expression too complex"));
12998 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12999 inst
.instruction
|= (value
& 0xf000) >> 12;
13000 inst
.instruction
|= (value
& 0x0ff0);
13001 inst
.instruction
|= (value
& 0x000f) << 16;
13002 /* PR gas/15623: SMC instructions must be last in an IT block. */
13003 set_it_insn_type_last ();
13009 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
13011 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13012 inst
.instruction
|= (value
& 0x0fff);
13013 inst
.instruction
|= (value
& 0xf000) << 4;
13017 do_t_ssat_usat (int bias
)
13021 Rd
= inst
.operands
[0].reg
;
13022 Rn
= inst
.operands
[2].reg
;
13024 reject_bad_reg (Rd
);
13025 reject_bad_reg (Rn
);
13027 inst
.instruction
|= Rd
<< 8;
13028 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13029 inst
.instruction
|= Rn
<< 16;
13031 if (inst
.operands
[3].present
)
13033 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
13035 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13037 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
13038 _("expression too complex"));
13040 if (shift_amount
!= 0)
13042 constraint (shift_amount
> 31,
13043 _("shift expression is too large"));
13045 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13046 inst
.instruction
|= 0x00200000; /* sh bit. */
13048 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13049 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13057 do_t_ssat_usat (1);
13065 Rd
= inst
.operands
[0].reg
;
13066 Rn
= inst
.operands
[2].reg
;
13068 reject_bad_reg (Rd
);
13069 reject_bad_reg (Rn
);
13071 inst
.instruction
|= Rd
<< 8;
13072 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13073 inst
.instruction
|= Rn
<< 16;
13079 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13080 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13081 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13082 || inst
.operands
[2].negative
,
13085 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13087 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13088 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13089 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13090 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13096 if (!inst
.operands
[2].present
)
13097 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13099 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13100 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13101 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13104 inst
.instruction
|= inst
.operands
[0].reg
;
13105 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13106 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13107 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13113 unsigned Rd
, Rn
, Rm
;
13115 Rd
= inst
.operands
[0].reg
;
13116 Rn
= inst
.operands
[1].reg
;
13117 Rm
= inst
.operands
[2].reg
;
13119 reject_bad_reg (Rd
);
13120 reject_bad_reg (Rn
);
13121 reject_bad_reg (Rm
);
13123 inst
.instruction
|= Rd
<< 8;
13124 inst
.instruction
|= Rn
<< 16;
13125 inst
.instruction
|= Rm
;
13126 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13134 Rd
= inst
.operands
[0].reg
;
13135 Rm
= inst
.operands
[1].reg
;
13137 reject_bad_reg (Rd
);
13138 reject_bad_reg (Rm
);
13140 if (inst
.instruction
<= 0xffff
13141 && inst
.size_req
!= 4
13142 && Rd
<= 7 && Rm
<= 7
13143 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13145 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13146 inst
.instruction
|= Rd
;
13147 inst
.instruction
|= Rm
<< 3;
13149 else if (unified_syntax
)
13151 if (inst
.instruction
<= 0xffff)
13152 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13153 inst
.instruction
|= Rd
<< 8;
13154 inst
.instruction
|= Rm
;
13155 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13159 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13160 _("Thumb encoding does not support rotation"));
13161 constraint (1, BAD_HIREG
);
13168 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13177 half
= (inst
.instruction
& 0x10) != 0;
13178 set_it_insn_type_last ();
13179 constraint (inst
.operands
[0].immisreg
,
13180 _("instruction requires register index"));
13182 Rn
= inst
.operands
[0].reg
;
13183 Rm
= inst
.operands
[0].imm
;
13185 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13186 constraint (Rn
== REG_SP
, BAD_SP
);
13187 reject_bad_reg (Rm
);
13189 constraint (!half
&& inst
.operands
[0].shifted
,
13190 _("instruction does not allow shifted index"));
13191 inst
.instruction
|= (Rn
<< 16) | Rm
;
13197 if (!inst
.operands
[0].present
)
13198 inst
.operands
[0].imm
= 0;
13200 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13202 constraint (inst
.size_req
== 2,
13203 _("immediate value out of range"));
13204 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13205 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13206 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13210 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13211 inst
.instruction
|= inst
.operands
[0].imm
;
13214 set_it_insn_type (NEUTRAL_IT_INSN
);
13221 do_t_ssat_usat (0);
13229 Rd
= inst
.operands
[0].reg
;
13230 Rn
= inst
.operands
[2].reg
;
13232 reject_bad_reg (Rd
);
13233 reject_bad_reg (Rn
);
13235 inst
.instruction
|= Rd
<< 8;
13236 inst
.instruction
|= inst
.operands
[1].imm
;
13237 inst
.instruction
|= Rn
<< 16;
13240 /* Neon instruction encoder helpers. */
13242 /* Encodings for the different types for various Neon opcodes. */
13244 /* An "invalid" code for the following tables. */
13247 struct neon_tab_entry
13250 unsigned float_or_poly
;
13251 unsigned scalar_or_imm
;
13254 /* Map overloaded Neon opcodes to their respective encodings. */
13255 #define NEON_ENC_TAB \
13256 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13257 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13258 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13259 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13260 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13261 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13262 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13263 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13264 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13265 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13266 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13267 /* Register variants of the following two instructions are encoded as
13268 vcge / vcgt with the operands reversed. */ \
13269 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13270 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13271 X(vfma, N_INV, 0x0000c10, N_INV), \
13272 X(vfms, N_INV, 0x0200c10, N_INV), \
13273 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13274 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13275 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13276 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13277 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13278 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13279 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13280 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13281 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13282 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13283 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13284 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13285 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13286 X(vshl, 0x0000400, N_INV, 0x0800510), \
13287 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13288 X(vand, 0x0000110, N_INV, 0x0800030), \
13289 X(vbic, 0x0100110, N_INV, 0x0800030), \
13290 X(veor, 0x1000110, N_INV, N_INV), \
13291 X(vorn, 0x0300110, N_INV, 0x0800010), \
13292 X(vorr, 0x0200110, N_INV, 0x0800010), \
13293 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13294 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13295 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13296 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13297 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13298 X(vst1, 0x0000000, 0x0800000, N_INV), \
13299 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13300 X(vst2, 0x0000100, 0x0800100, N_INV), \
13301 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13302 X(vst3, 0x0000200, 0x0800200, N_INV), \
13303 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13304 X(vst4, 0x0000300, 0x0800300, N_INV), \
13305 X(vmovn, 0x1b20200, N_INV, N_INV), \
13306 X(vtrn, 0x1b20080, N_INV, N_INV), \
13307 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13308 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13309 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13310 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13311 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13312 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13313 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13314 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13315 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13316 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13317 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13318 X(vseleq, 0xe000a00, N_INV, N_INV), \
13319 X(vselvs, 0xe100a00, N_INV, N_INV), \
13320 X(vselge, 0xe200a00, N_INV, N_INV), \
13321 X(vselgt, 0xe300a00, N_INV, N_INV), \
13322 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13323 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13324 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13325 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13326 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13327 X(aes, 0x3b00300, N_INV, N_INV), \
13328 X(sha3op, 0x2000c00, N_INV, N_INV), \
13329 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13330 X(sha2op, 0x3ba0380, N_INV, N_INV)
13334 #define X(OPC,I,F,S) N_MNEM_##OPC
13339 static const struct neon_tab_entry neon_enc_tab
[] =
13341 #define X(OPC,I,F,S) { (I), (F), (S) }
13346 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13347 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13348 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13349 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13350 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13351 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13352 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13353 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13354 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13355 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13356 #define NEON_ENC_SINGLE_(X) \
13357 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13358 #define NEON_ENC_DOUBLE_(X) \
13359 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13360 #define NEON_ENC_FPV8_(X) \
13361 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13363 #define NEON_ENCODE(type, inst) \
13366 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13367 inst.is_neon = 1; \
13371 #define check_neon_suffixes \
13374 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13376 as_bad (_("invalid neon suffix for non neon instruction")); \
13382 /* Define shapes for instruction operands. The following mnemonic characters
13383 are used in this table:
13385 F - VFP S<n> register
13386 D - Neon D<n> register
13387 Q - Neon Q<n> register
13391 L - D<n> register list
13393 This table is used to generate various data:
13394 - enumerations of the form NS_DDR to be used as arguments to
13396 - a table classifying shapes into single, double, quad, mixed.
13397 - a table used to drive neon_select_shape. */
13399 #define NEON_SHAPE_DEF \
13400 X(3, (D, D, D), DOUBLE), \
13401 X(3, (Q, Q, Q), QUAD), \
13402 X(3, (D, D, I), DOUBLE), \
13403 X(3, (Q, Q, I), QUAD), \
13404 X(3, (D, D, S), DOUBLE), \
13405 X(3, (Q, Q, S), QUAD), \
13406 X(2, (D, D), DOUBLE), \
13407 X(2, (Q, Q), QUAD), \
13408 X(2, (D, S), DOUBLE), \
13409 X(2, (Q, S), QUAD), \
13410 X(2, (D, R), DOUBLE), \
13411 X(2, (Q, R), QUAD), \
13412 X(2, (D, I), DOUBLE), \
13413 X(2, (Q, I), QUAD), \
13414 X(3, (D, L, D), DOUBLE), \
13415 X(2, (D, Q), MIXED), \
13416 X(2, (Q, D), MIXED), \
13417 X(3, (D, Q, I), MIXED), \
13418 X(3, (Q, D, I), MIXED), \
13419 X(3, (Q, D, D), MIXED), \
13420 X(3, (D, Q, Q), MIXED), \
13421 X(3, (Q, Q, D), MIXED), \
13422 X(3, (Q, D, S), MIXED), \
13423 X(3, (D, Q, S), MIXED), \
13424 X(4, (D, D, D, I), DOUBLE), \
13425 X(4, (Q, Q, Q, I), QUAD), \
13426 X(4, (D, D, S, I), DOUBLE), \
13427 X(4, (Q, Q, S, I), QUAD), \
13428 X(2, (F, F), SINGLE), \
13429 X(3, (F, F, F), SINGLE), \
13430 X(2, (F, I), SINGLE), \
13431 X(2, (F, D), MIXED), \
13432 X(2, (D, F), MIXED), \
13433 X(3, (F, F, I), MIXED), \
13434 X(4, (R, R, F, F), SINGLE), \
13435 X(4, (F, F, R, R), SINGLE), \
13436 X(3, (D, R, R), DOUBLE), \
13437 X(3, (R, R, D), DOUBLE), \
13438 X(2, (S, R), SINGLE), \
13439 X(2, (R, S), SINGLE), \
13440 X(2, (F, R), SINGLE), \
13441 X(2, (R, F), SINGLE), \
13442 /* Half float shape supported so far. */\
13443 X (2, (H, D), MIXED), \
13444 X (2, (D, H), MIXED), \
13445 X (2, (H, F), MIXED), \
13446 X (2, (F, H), MIXED), \
13447 X (2, (H, H), HALF), \
13448 X (2, (H, R), HALF), \
13449 X (2, (R, H), HALF), \
13450 X (2, (H, I), HALF), \
13451 X (3, (H, H, H), HALF), \
13452 X (3, (H, F, I), MIXED), \
13453 X (3, (F, H, I), MIXED), \
13454 X (3, (D, H, H), MIXED), \
13455 X (3, (D, H, S), MIXED)
13457 #define S2(A,B) NS_##A##B
13458 #define S3(A,B,C) NS_##A##B##C
13459 #define S4(A,B,C,D) NS_##A##B##C##D
13461 #define X(N, L, C) S##N L
13474 enum neon_shape_class
13483 #define X(N, L, C) SC_##C
13485 static enum neon_shape_class neon_shape_class
[] =
13504 /* Register widths of above. */
13505 static unsigned neon_shape_el_size
[] =
13517 struct neon_shape_info
13520 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13523 #define S2(A,B) { SE_##A, SE_##B }
13524 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13525 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13527 #define X(N, L, C) { N, S##N L }
13529 static struct neon_shape_info neon_shape_tab
[] =
13539 /* Bit masks used in type checking given instructions.
13540 'N_EQK' means the type must be the same as (or based on in some way) the key
13541 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13542 set, various other bits can be set as well in order to modify the meaning of
13543 the type constraint. */
13545 enum neon_type_mask
13569 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13570 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13571 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13572 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13573 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13574 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13575 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13576 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13577 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13578 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13579 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13581 N_MAX_NONSPECIAL
= N_P64
13584 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13586 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13587 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13588 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13589 #define N_S_32 (N_S8 | N_S16 | N_S32)
13590 #define N_F_16_32 (N_F16 | N_F32)
13591 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13592 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13593 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13594 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13596 /* Pass this as the first type argument to neon_check_type to ignore types
13598 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13600 /* Select a "shape" for the current instruction (describing register types or
13601 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13602 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13603 function of operand parsing, so this function doesn't need to be called.
13604 Shapes should be listed in order of decreasing length. */
13606 static enum neon_shape
13607 neon_select_shape (enum neon_shape shape
, ...)
13610 enum neon_shape first_shape
= shape
;
13612 /* Fix missing optional operands. FIXME: we don't know at this point how
13613 many arguments we should have, so this makes the assumption that we have
13614 > 1. This is true of all current Neon opcodes, I think, but may not be
13615 true in the future. */
13616 if (!inst
.operands
[1].present
)
13617 inst
.operands
[1] = inst
.operands
[0];
13619 va_start (ap
, shape
);
13621 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13626 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13628 if (!inst
.operands
[j
].present
)
13634 switch (neon_shape_tab
[shape
].el
[j
])
13636 /* If a .f16, .16, .u16, .s16 type specifier is given over
13637 a VFP single precision register operand, it's essentially
13638 means only half of the register is used.
13640 If the type specifier is given after the mnemonics, the
13641 information is stored in inst.vectype. If the type specifier
13642 is given after register operand, the information is stored
13643 in inst.operands[].vectype.
13645 When there is only one type specifier, and all the register
13646 operands are the same type of hardware register, the type
13647 specifier applies to all register operands.
13649 If no type specifier is given, the shape is inferred from
13650 operand information.
13653 vadd.f16 s0, s1, s2: NS_HHH
13654 vabs.f16 s0, s1: NS_HH
13655 vmov.f16 s0, r1: NS_HR
13656 vmov.f16 r0, s1: NS_RH
13657 vcvt.f16 r0, s1: NS_RH
13658 vcvt.f16.s32 s2, s2, #29: NS_HFI
13659 vcvt.f16.s32 s2, s2: NS_HF
13662 if (!(inst
.operands
[j
].isreg
13663 && inst
.operands
[j
].isvec
13664 && inst
.operands
[j
].issingle
13665 && !inst
.operands
[j
].isquad
13666 && ((inst
.vectype
.elems
== 1
13667 && inst
.vectype
.el
[0].size
== 16)
13668 || (inst
.vectype
.elems
> 1
13669 && inst
.vectype
.el
[j
].size
== 16)
13670 || (inst
.vectype
.elems
== 0
13671 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13672 && inst
.operands
[j
].vectype
.size
== 16))))
13677 if (!(inst
.operands
[j
].isreg
13678 && inst
.operands
[j
].isvec
13679 && inst
.operands
[j
].issingle
13680 && !inst
.operands
[j
].isquad
13681 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13682 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13683 || (inst
.vectype
.elems
== 0
13684 && (inst
.operands
[j
].vectype
.size
== 32
13685 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13690 if (!(inst
.operands
[j
].isreg
13691 && inst
.operands
[j
].isvec
13692 && !inst
.operands
[j
].isquad
13693 && !inst
.operands
[j
].issingle
))
13698 if (!(inst
.operands
[j
].isreg
13699 && !inst
.operands
[j
].isvec
))
13704 if (!(inst
.operands
[j
].isreg
13705 && inst
.operands
[j
].isvec
13706 && inst
.operands
[j
].isquad
13707 && !inst
.operands
[j
].issingle
))
13712 if (!(!inst
.operands
[j
].isreg
13713 && !inst
.operands
[j
].isscalar
))
13718 if (!(!inst
.operands
[j
].isreg
13719 && inst
.operands
[j
].isscalar
))
13729 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13730 /* We've matched all the entries in the shape table, and we don't
13731 have any left over operands which have not been matched. */
13737 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13738 first_error (_("invalid instruction shape"));
13743 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13744 means the Q bit should be set). */
13747 neon_quad (enum neon_shape shape
)
13749 return neon_shape_class
[shape
] == SC_QUAD
;
13753 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13756 /* Allow modification to be made to types which are constrained to be
13757 based on the key element, based on bits set alongside N_EQK. */
13758 if ((typebits
& N_EQK
) != 0)
13760 if ((typebits
& N_HLF
) != 0)
13762 else if ((typebits
& N_DBL
) != 0)
13764 if ((typebits
& N_SGN
) != 0)
13765 *g_type
= NT_signed
;
13766 else if ((typebits
& N_UNS
) != 0)
13767 *g_type
= NT_unsigned
;
13768 else if ((typebits
& N_INT
) != 0)
13769 *g_type
= NT_integer
;
13770 else if ((typebits
& N_FLT
) != 0)
13771 *g_type
= NT_float
;
13772 else if ((typebits
& N_SIZ
) != 0)
13773 *g_type
= NT_untyped
;
13777 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13778 operand type, i.e. the single type specified in a Neon instruction when it
13779 is the only one given. */
13781 static struct neon_type_el
13782 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13784 struct neon_type_el dest
= *key
;
13786 gas_assert ((thisarg
& N_EQK
) != 0);
13788 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13793 /* Convert Neon type and size into compact bitmask representation. */
13795 static enum neon_type_mask
13796 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13803 case 8: return N_8
;
13804 case 16: return N_16
;
13805 case 32: return N_32
;
13806 case 64: return N_64
;
13814 case 8: return N_I8
;
13815 case 16: return N_I16
;
13816 case 32: return N_I32
;
13817 case 64: return N_I64
;
13825 case 16: return N_F16
;
13826 case 32: return N_F32
;
13827 case 64: return N_F64
;
13835 case 8: return N_P8
;
13836 case 16: return N_P16
;
13837 case 64: return N_P64
;
13845 case 8: return N_S8
;
13846 case 16: return N_S16
;
13847 case 32: return N_S32
;
13848 case 64: return N_S64
;
13856 case 8: return N_U8
;
13857 case 16: return N_U16
;
13858 case 32: return N_U32
;
13859 case 64: return N_U64
;
13870 /* Convert compact Neon bitmask type representation to a type and size. Only
13871 handles the case where a single bit is set in the mask. */
13874 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13875 enum neon_type_mask mask
)
13877 if ((mask
& N_EQK
) != 0)
13880 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13882 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13884 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13886 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13891 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13893 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13894 *type
= NT_unsigned
;
13895 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13896 *type
= NT_integer
;
13897 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13898 *type
= NT_untyped
;
13899 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13901 else if ((mask
& (N_F_ALL
)) != 0)
13909 /* Modify a bitmask of allowed types. This is only needed for type
13913 modify_types_allowed (unsigned allowed
, unsigned mods
)
13916 enum neon_el_type type
;
13922 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13924 if (el_type_of_type_chk (&type
, &size
,
13925 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13927 neon_modify_type_size (mods
, &type
, &size
);
13928 destmask
|= type_chk_of_el_type (type
, size
);
13935 /* Check type and return type classification.
13936 The manual states (paraphrase): If one datatype is given, it indicates the
13938 - the second operand, if there is one
13939 - the operand, if there is no second operand
13940 - the result, if there are no operands.
13941 This isn't quite good enough though, so we use a concept of a "key" datatype
13942 which is set on a per-instruction basis, which is the one which matters when
13943 only one data type is written.
13944 Note: this function has side-effects (e.g. filling in missing operands). All
13945 Neon instructions should call it before performing bit encoding. */
13947 static struct neon_type_el
13948 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13951 unsigned i
, pass
, key_el
= 0;
13952 unsigned types
[NEON_MAX_TYPE_ELS
];
13953 enum neon_el_type k_type
= NT_invtype
;
13954 unsigned k_size
= -1u;
13955 struct neon_type_el badtype
= {NT_invtype
, -1};
13956 unsigned key_allowed
= 0;
13958 /* Optional registers in Neon instructions are always (not) in operand 1.
13959 Fill in the missing operand here, if it was omitted. */
13960 if (els
> 1 && !inst
.operands
[1].present
)
13961 inst
.operands
[1] = inst
.operands
[0];
13963 /* Suck up all the varargs. */
13965 for (i
= 0; i
< els
; i
++)
13967 unsigned thisarg
= va_arg (ap
, unsigned);
13968 if (thisarg
== N_IGNORE_TYPE
)
13973 types
[i
] = thisarg
;
13974 if ((thisarg
& N_KEY
) != 0)
13979 if (inst
.vectype
.elems
> 0)
13980 for (i
= 0; i
< els
; i
++)
13981 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13983 first_error (_("types specified in both the mnemonic and operands"));
13987 /* Duplicate inst.vectype elements here as necessary.
13988 FIXME: No idea if this is exactly the same as the ARM assembler,
13989 particularly when an insn takes one register and one non-register
13991 if (inst
.vectype
.elems
== 1 && els
> 1)
13994 inst
.vectype
.elems
= els
;
13995 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13996 for (j
= 0; j
< els
; j
++)
13998 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14001 else if (inst
.vectype
.elems
== 0 && els
> 0)
14004 /* No types were given after the mnemonic, so look for types specified
14005 after each operand. We allow some flexibility here; as long as the
14006 "key" operand has a type, we can infer the others. */
14007 for (j
= 0; j
< els
; j
++)
14008 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
14009 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
14011 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
14013 for (j
= 0; j
< els
; j
++)
14014 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
14015 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14020 first_error (_("operand types can't be inferred"));
14024 else if (inst
.vectype
.elems
!= els
)
14026 first_error (_("type specifier has the wrong number of parts"));
14030 for (pass
= 0; pass
< 2; pass
++)
14032 for (i
= 0; i
< els
; i
++)
14034 unsigned thisarg
= types
[i
];
14035 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
14036 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
14037 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
14038 unsigned g_size
= inst
.vectype
.el
[i
].size
;
14040 /* Decay more-specific signed & unsigned types to sign-insensitive
14041 integer types if sign-specific variants are unavailable. */
14042 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
14043 && (types_allowed
& N_SU_ALL
) == 0)
14044 g_type
= NT_integer
;
14046 /* If only untyped args are allowed, decay any more specific types to
14047 them. Some instructions only care about signs for some element
14048 sizes, so handle that properly. */
14049 if (((types_allowed
& N_UNT
) == 0)
14050 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14051 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14052 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
14053 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
14054 g_type
= NT_untyped
;
14058 if ((thisarg
& N_KEY
) != 0)
14062 key_allowed
= thisarg
& ~N_KEY
;
14064 /* Check architecture constraint on FP16 extension. */
14066 && k_type
== NT_float
14067 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14069 inst
.error
= _(BAD_FP16
);
14076 if ((thisarg
& N_VFP
) != 0)
14078 enum neon_shape_el regshape
;
14079 unsigned regwidth
, match
;
14081 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14084 first_error (_("invalid instruction shape"));
14087 regshape
= neon_shape_tab
[ns
].el
[i
];
14088 regwidth
= neon_shape_el_size
[regshape
];
14090 /* In VFP mode, operands must match register widths. If we
14091 have a key operand, use its width, else use the width of
14092 the current operand. */
14098 /* FP16 will use a single precision register. */
14099 if (regwidth
== 32 && match
== 16)
14101 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14105 inst
.error
= _(BAD_FP16
);
14110 if (regwidth
!= match
)
14112 first_error (_("operand size must match register width"));
14117 if ((thisarg
& N_EQK
) == 0)
14119 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14121 if ((given_type
& types_allowed
) == 0)
14123 first_error (_("bad type in Neon instruction"));
14129 enum neon_el_type mod_k_type
= k_type
;
14130 unsigned mod_k_size
= k_size
;
14131 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14132 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14134 first_error (_("inconsistent types in Neon instruction"));
14142 return inst
.vectype
.el
[key_el
];
14145 /* Neon-style VFP instruction forwarding. */
14147 /* Thumb VFP instructions have 0xE in the condition field. */
14150 do_vfp_cond_or_thumb (void)
14155 inst
.instruction
|= 0xe0000000;
14157 inst
.instruction
|= inst
.cond
<< 28;
14160 /* Look up and encode a simple mnemonic, for use as a helper function for the
14161 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14162 etc. It is assumed that operand parsing has already been done, and that the
14163 operands are in the form expected by the given opcode (this isn't necessarily
14164 the same as the form in which they were parsed, hence some massaging must
14165 take place before this function is called).
14166 Checks current arch version against that in the looked-up opcode. */
14169 do_vfp_nsyn_opcode (const char *opname
)
14171 const struct asm_opcode
*opcode
;
14173 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14178 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14179 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14186 inst
.instruction
= opcode
->tvalue
;
14187 opcode
->tencode ();
14191 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14192 opcode
->aencode ();
14197 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14199 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14201 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14204 do_vfp_nsyn_opcode ("fadds");
14206 do_vfp_nsyn_opcode ("fsubs");
14208 /* ARMv8.2 fp16 instruction. */
14210 do_scalar_fp16_v82_encode ();
14215 do_vfp_nsyn_opcode ("faddd");
14217 do_vfp_nsyn_opcode ("fsubd");
14221 /* Check operand types to see if this is a VFP instruction, and if so call
14225 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14227 enum neon_shape rs
;
14228 struct neon_type_el et
;
14233 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14234 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14238 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14239 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14240 N_F_ALL
| N_KEY
| N_VFP
);
14247 if (et
.type
!= NT_invtype
)
14258 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14260 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14262 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14265 do_vfp_nsyn_opcode ("fmacs");
14267 do_vfp_nsyn_opcode ("fnmacs");
14269 /* ARMv8.2 fp16 instruction. */
14271 do_scalar_fp16_v82_encode ();
14276 do_vfp_nsyn_opcode ("fmacd");
14278 do_vfp_nsyn_opcode ("fnmacd");
14283 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14285 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14287 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14290 do_vfp_nsyn_opcode ("ffmas");
14292 do_vfp_nsyn_opcode ("ffnmas");
14294 /* ARMv8.2 fp16 instruction. */
14296 do_scalar_fp16_v82_encode ();
14301 do_vfp_nsyn_opcode ("ffmad");
14303 do_vfp_nsyn_opcode ("ffnmad");
14308 do_vfp_nsyn_mul (enum neon_shape rs
)
14310 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14312 do_vfp_nsyn_opcode ("fmuls");
14314 /* ARMv8.2 fp16 instruction. */
14316 do_scalar_fp16_v82_encode ();
14319 do_vfp_nsyn_opcode ("fmuld");
14323 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14325 int is_neg
= (inst
.instruction
& 0x80) != 0;
14326 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14328 if (rs
== NS_FF
|| rs
== NS_HH
)
14331 do_vfp_nsyn_opcode ("fnegs");
14333 do_vfp_nsyn_opcode ("fabss");
14335 /* ARMv8.2 fp16 instruction. */
14337 do_scalar_fp16_v82_encode ();
14342 do_vfp_nsyn_opcode ("fnegd");
14344 do_vfp_nsyn_opcode ("fabsd");
14348 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14349 insns belong to Neon, and are handled elsewhere. */
14352 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14354 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14358 do_vfp_nsyn_opcode ("fldmdbs");
14360 do_vfp_nsyn_opcode ("fldmias");
14365 do_vfp_nsyn_opcode ("fstmdbs");
14367 do_vfp_nsyn_opcode ("fstmias");
14372 do_vfp_nsyn_sqrt (void)
14374 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14375 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14377 if (rs
== NS_FF
|| rs
== NS_HH
)
14379 do_vfp_nsyn_opcode ("fsqrts");
14381 /* ARMv8.2 fp16 instruction. */
14383 do_scalar_fp16_v82_encode ();
14386 do_vfp_nsyn_opcode ("fsqrtd");
14390 do_vfp_nsyn_div (void)
14392 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14393 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14394 N_F_ALL
| N_KEY
| N_VFP
);
14396 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14398 do_vfp_nsyn_opcode ("fdivs");
14400 /* ARMv8.2 fp16 instruction. */
14402 do_scalar_fp16_v82_encode ();
14405 do_vfp_nsyn_opcode ("fdivd");
14409 do_vfp_nsyn_nmul (void)
14411 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14412 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14413 N_F_ALL
| N_KEY
| N_VFP
);
14415 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14417 NEON_ENCODE (SINGLE
, inst
);
14418 do_vfp_sp_dyadic ();
14420 /* ARMv8.2 fp16 instruction. */
14422 do_scalar_fp16_v82_encode ();
14426 NEON_ENCODE (DOUBLE
, inst
);
14427 do_vfp_dp_rd_rn_rm ();
14429 do_vfp_cond_or_thumb ();
14434 do_vfp_nsyn_cmp (void)
14436 enum neon_shape rs
;
14437 if (inst
.operands
[1].isreg
)
14439 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14440 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14442 if (rs
== NS_FF
|| rs
== NS_HH
)
14444 NEON_ENCODE (SINGLE
, inst
);
14445 do_vfp_sp_monadic ();
14449 NEON_ENCODE (DOUBLE
, inst
);
14450 do_vfp_dp_rd_rm ();
14455 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14456 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14458 switch (inst
.instruction
& 0x0fffffff)
14461 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14464 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14470 if (rs
== NS_FI
|| rs
== NS_HI
)
14472 NEON_ENCODE (SINGLE
, inst
);
14473 do_vfp_sp_compare_z ();
14477 NEON_ENCODE (DOUBLE
, inst
);
14481 do_vfp_cond_or_thumb ();
14483 /* ARMv8.2 fp16 instruction. */
14484 if (rs
== NS_HI
|| rs
== NS_HH
)
14485 do_scalar_fp16_v82_encode ();
14489 nsyn_insert_sp (void)
14491 inst
.operands
[1] = inst
.operands
[0];
14492 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14493 inst
.operands
[0].reg
= REG_SP
;
14494 inst
.operands
[0].isreg
= 1;
14495 inst
.operands
[0].writeback
= 1;
14496 inst
.operands
[0].present
= 1;
14500 do_vfp_nsyn_push (void)
14504 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14505 _("register list must contain at least 1 and at most 16 "
14508 if (inst
.operands
[1].issingle
)
14509 do_vfp_nsyn_opcode ("fstmdbs");
14511 do_vfp_nsyn_opcode ("fstmdbd");
14515 do_vfp_nsyn_pop (void)
14519 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14520 _("register list must contain at least 1 and at most 16 "
14523 if (inst
.operands
[1].issingle
)
14524 do_vfp_nsyn_opcode ("fldmias");
14526 do_vfp_nsyn_opcode ("fldmiad");
14529 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14530 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14533 neon_dp_fixup (struct arm_it
* insn
)
14535 unsigned int i
= insn
->instruction
;
14540 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14551 insn
->instruction
= i
;
14554 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14558 neon_logbits (unsigned x
)
14560 return ffs (x
) - 4;
14563 #define LOW4(R) ((R) & 0xf)
14564 #define HI1(R) (((R) >> 4) & 1)
14566 /* Encode insns with bit pattern:
14568 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14569 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14571 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14572 different meaning for some instruction. */
14575 neon_three_same (int isquad
, int ubit
, int size
)
14577 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14578 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14579 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14580 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14581 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14582 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14583 inst
.instruction
|= (isquad
!= 0) << 6;
14584 inst
.instruction
|= (ubit
!= 0) << 24;
14586 inst
.instruction
|= neon_logbits (size
) << 20;
14588 neon_dp_fixup (&inst
);
14591 /* Encode instructions of the form:
14593 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14594 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14596 Don't write size if SIZE == -1. */
14599 neon_two_same (int qbit
, int ubit
, int size
)
14601 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14602 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14603 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14604 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14605 inst
.instruction
|= (qbit
!= 0) << 6;
14606 inst
.instruction
|= (ubit
!= 0) << 24;
14609 inst
.instruction
|= neon_logbits (size
) << 18;
14611 neon_dp_fixup (&inst
);
14614 /* Neon instruction encoders, in approximate order of appearance. */
14617 do_neon_dyadic_i_su (void)
14619 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14620 struct neon_type_el et
= neon_check_type (3, rs
,
14621 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14622 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14626 do_neon_dyadic_i64_su (void)
14628 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14629 struct neon_type_el et
= neon_check_type (3, rs
,
14630 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14631 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14635 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14638 unsigned size
= et
.size
>> 3;
14639 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14640 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14641 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14642 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14643 inst
.instruction
|= (isquad
!= 0) << 6;
14644 inst
.instruction
|= immbits
<< 16;
14645 inst
.instruction
|= (size
>> 3) << 7;
14646 inst
.instruction
|= (size
& 0x7) << 19;
14648 inst
.instruction
|= (uval
!= 0) << 24;
14650 neon_dp_fixup (&inst
);
14654 do_neon_shl_imm (void)
14656 if (!inst
.operands
[2].isreg
)
14658 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14659 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14660 int imm
= inst
.operands
[2].imm
;
14662 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14663 _("immediate out of range for shift"));
14664 NEON_ENCODE (IMMED
, inst
);
14665 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14669 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14670 struct neon_type_el et
= neon_check_type (3, rs
,
14671 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14674 /* VSHL/VQSHL 3-register variants have syntax such as:
14676 whereas other 3-register operations encoded by neon_three_same have
14679 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14681 tmp
= inst
.operands
[2].reg
;
14682 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14683 inst
.operands
[1].reg
= tmp
;
14684 NEON_ENCODE (INTEGER
, inst
);
14685 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14690 do_neon_qshl_imm (void)
14692 if (!inst
.operands
[2].isreg
)
14694 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14695 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14696 int imm
= inst
.operands
[2].imm
;
14698 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14699 _("immediate out of range for shift"));
14700 NEON_ENCODE (IMMED
, inst
);
14701 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14705 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14706 struct neon_type_el et
= neon_check_type (3, rs
,
14707 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14710 /* See note in do_neon_shl_imm. */
14711 tmp
= inst
.operands
[2].reg
;
14712 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14713 inst
.operands
[1].reg
= tmp
;
14714 NEON_ENCODE (INTEGER
, inst
);
14715 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14720 do_neon_rshl (void)
14722 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14723 struct neon_type_el et
= neon_check_type (3, rs
,
14724 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14727 tmp
= inst
.operands
[2].reg
;
14728 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14729 inst
.operands
[1].reg
= tmp
;
14730 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14734 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14736 /* Handle .I8 pseudo-instructions. */
14739 /* Unfortunately, this will make everything apart from zero out-of-range.
14740 FIXME is this the intended semantics? There doesn't seem much point in
14741 accepting .I8 if so. */
14742 immediate
|= immediate
<< 8;
14748 if (immediate
== (immediate
& 0x000000ff))
14750 *immbits
= immediate
;
14753 else if (immediate
== (immediate
& 0x0000ff00))
14755 *immbits
= immediate
>> 8;
14758 else if (immediate
== (immediate
& 0x00ff0000))
14760 *immbits
= immediate
>> 16;
14763 else if (immediate
== (immediate
& 0xff000000))
14765 *immbits
= immediate
>> 24;
14768 if ((immediate
& 0xffff) != (immediate
>> 16))
14769 goto bad_immediate
;
14770 immediate
&= 0xffff;
14773 if (immediate
== (immediate
& 0x000000ff))
14775 *immbits
= immediate
;
14778 else if (immediate
== (immediate
& 0x0000ff00))
14780 *immbits
= immediate
>> 8;
14785 first_error (_("immediate value out of range"));
14790 do_neon_logic (void)
14792 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14794 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14795 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14796 /* U bit and size field were set as part of the bitmask. */
14797 NEON_ENCODE (INTEGER
, inst
);
14798 neon_three_same (neon_quad (rs
), 0, -1);
14802 const int three_ops_form
= (inst
.operands
[2].present
14803 && !inst
.operands
[2].isreg
);
14804 const int immoperand
= (three_ops_form
? 2 : 1);
14805 enum neon_shape rs
= (three_ops_form
14806 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14807 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14808 struct neon_type_el et
= neon_check_type (2, rs
,
14809 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14810 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14814 if (et
.type
== NT_invtype
)
14817 if (three_ops_form
)
14818 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14819 _("first and second operands shall be the same register"));
14821 NEON_ENCODE (IMMED
, inst
);
14823 immbits
= inst
.operands
[immoperand
].imm
;
14826 /* .i64 is a pseudo-op, so the immediate must be a repeating
14828 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14829 inst
.operands
[immoperand
].reg
: 0))
14831 /* Set immbits to an invalid constant. */
14832 immbits
= 0xdeadbeef;
14839 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14843 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14847 /* Pseudo-instruction for VBIC. */
14848 neon_invert_size (&immbits
, 0, et
.size
);
14849 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14853 /* Pseudo-instruction for VORR. */
14854 neon_invert_size (&immbits
, 0, et
.size
);
14855 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14865 inst
.instruction
|= neon_quad (rs
) << 6;
14866 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14867 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14868 inst
.instruction
|= cmode
<< 8;
14869 neon_write_immbits (immbits
);
14871 neon_dp_fixup (&inst
);
14876 do_neon_bitfield (void)
14878 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14879 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14880 neon_three_same (neon_quad (rs
), 0, -1);
14884 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14887 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14888 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14890 if (et
.type
== NT_float
)
14892 NEON_ENCODE (FLOAT
, inst
);
14893 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14897 NEON_ENCODE (INTEGER
, inst
);
14898 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14903 do_neon_dyadic_if_su (void)
14905 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14909 do_neon_dyadic_if_su_d (void)
14911 /* This version only allow D registers, but that constraint is enforced during
14912 operand parsing so we don't need to do anything extra here. */
14913 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14917 do_neon_dyadic_if_i_d (void)
14919 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14920 affected if we specify unsigned args. */
14921 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14924 enum vfp_or_neon_is_neon_bits
14927 NEON_CHECK_ARCH
= 2,
14928 NEON_CHECK_ARCH8
= 4
14931 /* Call this function if an instruction which may have belonged to the VFP or
14932 Neon instruction sets, but turned out to be a Neon instruction (due to the
14933 operand types involved, etc.). We have to check and/or fix-up a couple of
14936 - Make sure the user hasn't attempted to make a Neon instruction
14938 - Alter the value in the condition code field if necessary.
14939 - Make sure that the arch supports Neon instructions.
14941 Which of these operations take place depends on bits from enum
14942 vfp_or_neon_is_neon_bits.
14944 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14945 current instruction's condition is COND_ALWAYS, the condition field is
14946 changed to inst.uncond_value. This is necessary because instructions shared
14947 between VFP and Neon may be conditional for the VFP variants only, and the
14948 unconditional Neon version must have, e.g., 0xF in the condition field. */
14951 vfp_or_neon_is_neon (unsigned check
)
14953 /* Conditions are always legal in Thumb mode (IT blocks). */
14954 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14956 if (inst
.cond
!= COND_ALWAYS
)
14958 first_error (_(BAD_COND
));
14961 if (inst
.uncond_value
!= -1)
14962 inst
.instruction
|= inst
.uncond_value
<< 28;
14965 if ((check
& NEON_CHECK_ARCH
)
14966 && !mark_feature_used (&fpu_neon_ext_v1
))
14968 first_error (_(BAD_FPU
));
14972 if ((check
& NEON_CHECK_ARCH8
)
14973 && !mark_feature_used (&fpu_neon_ext_armv8
))
14975 first_error (_(BAD_FPU
));
14983 do_neon_addsub_if_i (void)
14985 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14988 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14991 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14992 affected if we specify unsigned args. */
14993 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14996 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14998 V<op> A,B (A is operand 0, B is operand 2)
15003 so handle that case specially. */
15006 neon_exchange_operands (void)
15008 if (inst
.operands
[1].present
)
15010 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
15012 /* Swap operands[1] and operands[2]. */
15013 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
15014 inst
.operands
[1] = inst
.operands
[2];
15015 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
15020 inst
.operands
[1] = inst
.operands
[2];
15021 inst
.operands
[2] = inst
.operands
[0];
15026 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
15028 if (inst
.operands
[2].isreg
)
15031 neon_exchange_operands ();
15032 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
15036 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15037 struct neon_type_el et
= neon_check_type (2, rs
,
15038 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
15040 NEON_ENCODE (IMMED
, inst
);
15041 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15042 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15043 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15044 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15045 inst
.instruction
|= neon_quad (rs
) << 6;
15046 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15047 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15049 neon_dp_fixup (&inst
);
15056 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
15060 do_neon_cmp_inv (void)
15062 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
15068 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
15071 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
15072 scalars, which are encoded in 5 bits, M : Rm.
15073 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
15074 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
15077 Dot Product instructions are similar to multiply instructions except elsize
15078 should always be 32.
15080 This function translates SCALAR, which is GAS's internal encoding of indexed
15081 scalar register, to raw encoding. There is also register and index range
15082 check based on ELSIZE. */
15085 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
15087 unsigned regno
= NEON_SCALAR_REG (scalar
);
15088 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15093 if (regno
> 7 || elno
> 3)
15095 return regno
| (elno
<< 3);
15098 if (regno
> 15 || elno
> 1)
15100 return regno
| (elno
<< 4);
15104 first_error (_("scalar out of range for multiply instruction"));
15110 /* Encode multiply / multiply-accumulate scalar instructions. */
15113 neon_mul_mac (struct neon_type_el et
, int ubit
)
15117 /* Give a more helpful error message if we have an invalid type. */
15118 if (et
.type
== NT_invtype
)
15121 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15122 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15123 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15124 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15125 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15126 inst
.instruction
|= LOW4 (scalar
);
15127 inst
.instruction
|= HI1 (scalar
) << 5;
15128 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15129 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15130 inst
.instruction
|= (ubit
!= 0) << 24;
15132 neon_dp_fixup (&inst
);
15136 do_neon_mac_maybe_scalar (void)
15138 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15141 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15144 if (inst
.operands
[2].isscalar
)
15146 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15147 struct neon_type_el et
= neon_check_type (3, rs
,
15148 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15149 NEON_ENCODE (SCALAR
, inst
);
15150 neon_mul_mac (et
, neon_quad (rs
));
15154 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15155 affected if we specify unsigned args. */
15156 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15161 do_neon_fmac (void)
15163 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15166 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15169 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15175 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15176 struct neon_type_el et
= neon_check_type (3, rs
,
15177 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15178 neon_three_same (neon_quad (rs
), 0, et
.size
);
15181 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15182 same types as the MAC equivalents. The polynomial type for this instruction
15183 is encoded the same as the integer type. */
15188 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15191 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15194 if (inst
.operands
[2].isscalar
)
15195 do_neon_mac_maybe_scalar ();
15197 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15201 do_neon_qdmulh (void)
15203 if (inst
.operands
[2].isscalar
)
15205 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15206 struct neon_type_el et
= neon_check_type (3, rs
,
15207 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15208 NEON_ENCODE (SCALAR
, inst
);
15209 neon_mul_mac (et
, neon_quad (rs
));
15213 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15214 struct neon_type_el et
= neon_check_type (3, rs
,
15215 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15216 NEON_ENCODE (INTEGER
, inst
);
15217 /* The U bit (rounding) comes from bit mask. */
15218 neon_three_same (neon_quad (rs
), 0, et
.size
);
15223 do_neon_qrdmlah (void)
15225 /* Check we're on the correct architecture. */
15226 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15228 _("instruction form not available on this architecture.");
15229 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15231 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15232 record_feature_use (&fpu_neon_ext_v8_1
);
15235 if (inst
.operands
[2].isscalar
)
15237 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15238 struct neon_type_el et
= neon_check_type (3, rs
,
15239 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15240 NEON_ENCODE (SCALAR
, inst
);
15241 neon_mul_mac (et
, neon_quad (rs
));
15245 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15246 struct neon_type_el et
= neon_check_type (3, rs
,
15247 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15248 NEON_ENCODE (INTEGER
, inst
);
15249 /* The U bit (rounding) comes from bit mask. */
15250 neon_three_same (neon_quad (rs
), 0, et
.size
);
15255 do_neon_fcmp_absolute (void)
15257 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15258 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15259 N_F_16_32
| N_KEY
);
15260 /* Size field comes from bit mask. */
15261 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15265 do_neon_fcmp_absolute_inv (void)
15267 neon_exchange_operands ();
15268 do_neon_fcmp_absolute ();
15272 do_neon_step (void)
15274 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15275 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15276 N_F_16_32
| N_KEY
);
15277 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15281 do_neon_abs_neg (void)
15283 enum neon_shape rs
;
15284 struct neon_type_el et
;
15286 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15289 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15292 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15293 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15295 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15296 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15297 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15298 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15299 inst
.instruction
|= neon_quad (rs
) << 6;
15300 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15301 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15303 neon_dp_fixup (&inst
);
15309 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15310 struct neon_type_el et
= neon_check_type (2, rs
,
15311 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15312 int imm
= inst
.operands
[2].imm
;
15313 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15314 _("immediate out of range for insert"));
15315 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15321 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15322 struct neon_type_el et
= neon_check_type (2, rs
,
15323 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15324 int imm
= inst
.operands
[2].imm
;
15325 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15326 _("immediate out of range for insert"));
15327 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15331 do_neon_qshlu_imm (void)
15333 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15334 struct neon_type_el et
= neon_check_type (2, rs
,
15335 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15336 int imm
= inst
.operands
[2].imm
;
15337 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15338 _("immediate out of range for shift"));
15339 /* Only encodes the 'U present' variant of the instruction.
15340 In this case, signed types have OP (bit 8) set to 0.
15341 Unsigned types have OP set to 1. */
15342 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15343 /* The rest of the bits are the same as other immediate shifts. */
15344 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15348 do_neon_qmovn (void)
15350 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15351 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15352 /* Saturating move where operands can be signed or unsigned, and the
15353 destination has the same signedness. */
15354 NEON_ENCODE (INTEGER
, inst
);
15355 if (et
.type
== NT_unsigned
)
15356 inst
.instruction
|= 0xc0;
15358 inst
.instruction
|= 0x80;
15359 neon_two_same (0, 1, et
.size
/ 2);
15363 do_neon_qmovun (void)
15365 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15366 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15367 /* Saturating move with unsigned results. Operands must be signed. */
15368 NEON_ENCODE (INTEGER
, inst
);
15369 neon_two_same (0, 1, et
.size
/ 2);
15373 do_neon_rshift_sat_narrow (void)
15375 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15376 or unsigned. If operands are unsigned, results must also be unsigned. */
15377 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15378 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15379 int imm
= inst
.operands
[2].imm
;
15380 /* This gets the bounds check, size encoding and immediate bits calculation
15384 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15385 VQMOVN.I<size> <Dd>, <Qm>. */
15388 inst
.operands
[2].present
= 0;
15389 inst
.instruction
= N_MNEM_vqmovn
;
15394 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15395 _("immediate out of range"));
15396 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15400 do_neon_rshift_sat_narrow_u (void)
15402 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15403 or unsigned. If operands are unsigned, results must also be unsigned. */
15404 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15405 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15406 int imm
= inst
.operands
[2].imm
;
15407 /* This gets the bounds check, size encoding and immediate bits calculation
15411 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15412 VQMOVUN.I<size> <Dd>, <Qm>. */
15415 inst
.operands
[2].present
= 0;
15416 inst
.instruction
= N_MNEM_vqmovun
;
15421 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15422 _("immediate out of range"));
15423 /* FIXME: The manual is kind of unclear about what value U should have in
15424 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15426 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15430 do_neon_movn (void)
15432 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15433 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15434 NEON_ENCODE (INTEGER
, inst
);
15435 neon_two_same (0, 1, et
.size
/ 2);
15439 do_neon_rshift_narrow (void)
15441 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15442 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15443 int imm
= inst
.operands
[2].imm
;
15444 /* This gets the bounds check, size encoding and immediate bits calculation
15448 /* If immediate is zero then we are a pseudo-instruction for
15449 VMOVN.I<size> <Dd>, <Qm> */
15452 inst
.operands
[2].present
= 0;
15453 inst
.instruction
= N_MNEM_vmovn
;
15458 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15459 _("immediate out of range for narrowing operation"));
15460 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15464 do_neon_shll (void)
15466 /* FIXME: Type checking when lengthening. */
15467 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15468 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15469 unsigned imm
= inst
.operands
[2].imm
;
15471 if (imm
== et
.size
)
15473 /* Maximum shift variant. */
15474 NEON_ENCODE (INTEGER
, inst
);
15475 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15476 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15477 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15478 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15479 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15481 neon_dp_fixup (&inst
);
15485 /* A more-specific type check for non-max versions. */
15486 et
= neon_check_type (2, NS_QDI
,
15487 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15488 NEON_ENCODE (IMMED
, inst
);
15489 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15493 /* Check the various types for the VCVT instruction, and return which version
15494 the current instruction is. */
15496 #define CVT_FLAVOUR_VAR \
15497 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15498 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15499 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15500 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15501 /* Half-precision conversions. */ \
15502 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15503 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15504 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15505 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15506 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15507 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15508 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15509 Compared with single/double precision variants, only the co-processor \
15510 field is different, so the encoding flow is reused here. */ \
15511 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15512 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15513 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15514 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15515 /* VFP instructions. */ \
15516 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15517 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15518 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15519 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15520 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15521 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15522 /* VFP instructions with bitshift. */ \
15523 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15524 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15525 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15526 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15527 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15528 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15529 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15530 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15532 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15533 neon_cvt_flavour_##C,
15535 /* The different types of conversions we can do. */
15536 enum neon_cvt_flavour
15539 neon_cvt_flavour_invalid
,
15540 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15545 static enum neon_cvt_flavour
15546 get_neon_cvt_flavour (enum neon_shape rs
)
15548 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15549 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15550 if (et.type != NT_invtype) \
15552 inst.error = NULL; \
15553 return (neon_cvt_flavour_##C); \
15556 struct neon_type_el et
;
15557 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15558 || rs
== NS_FF
) ? N_VFP
: 0;
15559 /* The instruction versions which take an immediate take one register
15560 argument, which is extended to the width of the full register. Thus the
15561 "source" and "destination" registers must have the same width. Hack that
15562 here by making the size equal to the key (wider, in this case) operand. */
15563 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15567 return neon_cvt_flavour_invalid
;
15582 /* Neon-syntax VFP conversions. */
15585 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15587 const char *opname
= 0;
15589 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15590 || rs
== NS_FHI
|| rs
== NS_HFI
)
15592 /* Conversions with immediate bitshift. */
15593 const char *enc
[] =
15595 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15601 if (flavour
< (int) ARRAY_SIZE (enc
))
15603 opname
= enc
[flavour
];
15604 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15605 _("operands 0 and 1 must be the same register"));
15606 inst
.operands
[1] = inst
.operands
[2];
15607 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15612 /* Conversions without bitshift. */
15613 const char *enc
[] =
15615 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15621 if (flavour
< (int) ARRAY_SIZE (enc
))
15622 opname
= enc
[flavour
];
15626 do_vfp_nsyn_opcode (opname
);
15628 /* ARMv8.2 fp16 VCVT instruction. */
15629 if (flavour
== neon_cvt_flavour_s32_f16
15630 || flavour
== neon_cvt_flavour_u32_f16
15631 || flavour
== neon_cvt_flavour_f16_u32
15632 || flavour
== neon_cvt_flavour_f16_s32
)
15633 do_scalar_fp16_v82_encode ();
15637 do_vfp_nsyn_cvtz (void)
15639 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15640 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15641 const char *enc
[] =
15643 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15649 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15650 do_vfp_nsyn_opcode (enc
[flavour
]);
15654 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15655 enum neon_cvt_mode mode
)
15660 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15661 D register operands. */
15662 if (flavour
== neon_cvt_flavour_s32_f64
15663 || flavour
== neon_cvt_flavour_u32_f64
)
15664 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15667 if (flavour
== neon_cvt_flavour_s32_f16
15668 || flavour
== neon_cvt_flavour_u32_f16
)
15669 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15672 set_it_insn_type (OUTSIDE_IT_INSN
);
15676 case neon_cvt_flavour_s32_f64
:
15680 case neon_cvt_flavour_s32_f32
:
15684 case neon_cvt_flavour_s32_f16
:
15688 case neon_cvt_flavour_u32_f64
:
15692 case neon_cvt_flavour_u32_f32
:
15696 case neon_cvt_flavour_u32_f16
:
15701 first_error (_("invalid instruction shape"));
15707 case neon_cvt_mode_a
: rm
= 0; break;
15708 case neon_cvt_mode_n
: rm
= 1; break;
15709 case neon_cvt_mode_p
: rm
= 2; break;
15710 case neon_cvt_mode_m
: rm
= 3; break;
15711 default: first_error (_("invalid rounding mode")); return;
15714 NEON_ENCODE (FPV8
, inst
);
15715 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15716 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15717 inst
.instruction
|= sz
<< 8;
15719 /* ARMv8.2 fp16 VCVT instruction. */
15720 if (flavour
== neon_cvt_flavour_s32_f16
15721 ||flavour
== neon_cvt_flavour_u32_f16
)
15722 do_scalar_fp16_v82_encode ();
15723 inst
.instruction
|= op
<< 7;
15724 inst
.instruction
|= rm
<< 16;
15725 inst
.instruction
|= 0xf0000000;
15726 inst
.is_neon
= TRUE
;
15730 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15732 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15733 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15734 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15736 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15738 if (flavour
== neon_cvt_flavour_invalid
)
15741 /* PR11109: Handle round-to-zero for VCVT conversions. */
15742 if (mode
== neon_cvt_mode_z
15743 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15744 && (flavour
== neon_cvt_flavour_s16_f16
15745 || flavour
== neon_cvt_flavour_u16_f16
15746 || flavour
== neon_cvt_flavour_s32_f32
15747 || flavour
== neon_cvt_flavour_u32_f32
15748 || flavour
== neon_cvt_flavour_s32_f64
15749 || flavour
== neon_cvt_flavour_u32_f64
)
15750 && (rs
== NS_FD
|| rs
== NS_FF
))
15752 do_vfp_nsyn_cvtz ();
15756 /* ARMv8.2 fp16 VCVT conversions. */
15757 if (mode
== neon_cvt_mode_z
15758 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15759 && (flavour
== neon_cvt_flavour_s32_f16
15760 || flavour
== neon_cvt_flavour_u32_f16
)
15763 do_vfp_nsyn_cvtz ();
15764 do_scalar_fp16_v82_encode ();
15768 /* VFP rather than Neon conversions. */
15769 if (flavour
>= neon_cvt_flavour_first_fp
)
15771 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15772 do_vfp_nsyn_cvt (rs
, flavour
);
15774 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15785 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15786 0x0000100, 0x1000100, 0x0, 0x1000000};
15788 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15791 /* Fixed-point conversion with #0 immediate is encoded as an
15792 integer conversion. */
15793 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15795 NEON_ENCODE (IMMED
, inst
);
15796 if (flavour
!= neon_cvt_flavour_invalid
)
15797 inst
.instruction
|= enctab
[flavour
];
15798 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15799 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15800 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15801 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15802 inst
.instruction
|= neon_quad (rs
) << 6;
15803 inst
.instruction
|= 1 << 21;
15804 if (flavour
< neon_cvt_flavour_s16_f16
)
15806 inst
.instruction
|= 1 << 21;
15807 immbits
= 32 - inst
.operands
[2].imm
;
15808 inst
.instruction
|= immbits
<< 16;
15812 inst
.instruction
|= 3 << 20;
15813 immbits
= 16 - inst
.operands
[2].imm
;
15814 inst
.instruction
|= immbits
<< 16;
15815 inst
.instruction
&= ~(1 << 9);
15818 neon_dp_fixup (&inst
);
15824 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15826 NEON_ENCODE (FLOAT
, inst
);
15827 set_it_insn_type (OUTSIDE_IT_INSN
);
15829 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15832 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15833 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15834 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15835 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15836 inst
.instruction
|= neon_quad (rs
) << 6;
15837 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15838 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15839 inst
.instruction
|= mode
<< 8;
15840 if (flavour
== neon_cvt_flavour_u16_f16
15841 || flavour
== neon_cvt_flavour_s16_f16
)
15842 /* Mask off the original size bits and reencode them. */
15843 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15846 inst
.instruction
|= 0xfc000000;
15848 inst
.instruction
|= 0xf0000000;
15854 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15855 0x100, 0x180, 0x0, 0x080};
15857 NEON_ENCODE (INTEGER
, inst
);
15859 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15862 if (flavour
!= neon_cvt_flavour_invalid
)
15863 inst
.instruction
|= enctab
[flavour
];
15865 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15866 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15867 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15868 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15869 inst
.instruction
|= neon_quad (rs
) << 6;
15870 if (flavour
>= neon_cvt_flavour_s16_f16
15871 && flavour
<= neon_cvt_flavour_f16_u16
)
15872 /* Half precision. */
15873 inst
.instruction
|= 1 << 18;
15875 inst
.instruction
|= 2 << 18;
15877 neon_dp_fixup (&inst
);
15882 /* Half-precision conversions for Advanced SIMD -- neon. */
15887 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15889 as_bad (_("operand size must match register width"));
15894 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15896 as_bad (_("operand size must match register width"));
15901 inst
.instruction
= 0x3b60600;
15903 inst
.instruction
= 0x3b60700;
15905 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15906 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15907 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15908 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15909 neon_dp_fixup (&inst
);
15913 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15914 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15915 do_vfp_nsyn_cvt (rs
, flavour
);
15917 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15922 do_neon_cvtr (void)
15924 do_neon_cvt_1 (neon_cvt_mode_x
);
15930 do_neon_cvt_1 (neon_cvt_mode_z
);
15934 do_neon_cvta (void)
15936 do_neon_cvt_1 (neon_cvt_mode_a
);
15940 do_neon_cvtn (void)
15942 do_neon_cvt_1 (neon_cvt_mode_n
);
15946 do_neon_cvtp (void)
15948 do_neon_cvt_1 (neon_cvt_mode_p
);
15952 do_neon_cvtm (void)
15954 do_neon_cvt_1 (neon_cvt_mode_m
);
15958 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15961 mark_feature_used (&fpu_vfp_ext_armv8
);
15963 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15964 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15965 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15966 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15967 inst
.instruction
|= to
? 0x10000 : 0;
15968 inst
.instruction
|= t
? 0x80 : 0;
15969 inst
.instruction
|= is_double
? 0x100 : 0;
15970 do_vfp_cond_or_thumb ();
15974 do_neon_cvttb_1 (bfd_boolean t
)
15976 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
15977 NS_DF
, NS_DH
, NS_NULL
);
15981 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15984 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15986 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15989 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15991 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15993 /* The VCVTB and VCVTT instructions with D-register operands
15994 don't work for SP only targets. */
15995 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15999 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
16001 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
16003 /* The VCVTB and VCVTT instructions with D-register operands
16004 don't work for SP only targets. */
16005 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16009 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
16016 do_neon_cvtb (void)
16018 do_neon_cvttb_1 (FALSE
);
16023 do_neon_cvtt (void)
16025 do_neon_cvttb_1 (TRUE
);
16029 neon_move_immediate (void)
16031 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
16032 struct neon_type_el et
= neon_check_type (2, rs
,
16033 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
16034 unsigned immlo
, immhi
= 0, immbits
;
16035 int op
, cmode
, float_p
;
16037 constraint (et
.type
== NT_invtype
,
16038 _("operand size must be specified for immediate VMOV"));
16040 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
16041 op
= (inst
.instruction
& (1 << 5)) != 0;
16043 immlo
= inst
.operands
[1].imm
;
16044 if (inst
.operands
[1].regisimm
)
16045 immhi
= inst
.operands
[1].reg
;
16047 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
16048 _("immediate has bits set outside the operand size"));
16050 float_p
= inst
.operands
[1].immisfloat
;
16052 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
16053 et
.size
, et
.type
)) == FAIL
)
16055 /* Invert relevant bits only. */
16056 neon_invert_size (&immlo
, &immhi
, et
.size
);
16057 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
16058 with one or the other; those cases are caught by
16059 neon_cmode_for_move_imm. */
16061 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
16062 &op
, et
.size
, et
.type
)) == FAIL
)
16064 first_error (_("immediate out of range"));
16069 inst
.instruction
&= ~(1 << 5);
16070 inst
.instruction
|= op
<< 5;
16072 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16073 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16074 inst
.instruction
|= neon_quad (rs
) << 6;
16075 inst
.instruction
|= cmode
<< 8;
16077 neon_write_immbits (immbits
);
16083 if (inst
.operands
[1].isreg
)
16085 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16087 NEON_ENCODE (INTEGER
, inst
);
16088 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16089 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16090 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16091 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16092 inst
.instruction
|= neon_quad (rs
) << 6;
16096 NEON_ENCODE (IMMED
, inst
);
16097 neon_move_immediate ();
16100 neon_dp_fixup (&inst
);
16103 /* Encode instructions of form:
16105 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16106 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16109 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16111 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16112 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16113 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16114 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16115 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16116 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16117 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16118 inst
.instruction
|= neon_logbits (size
) << 20;
16120 neon_dp_fixup (&inst
);
16124 do_neon_dyadic_long (void)
16126 /* FIXME: Type checking for lengthening op. */
16127 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16128 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16129 neon_mixed_length (et
, et
.size
);
16133 do_neon_abal (void)
16135 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16136 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16137 neon_mixed_length (et
, et
.size
);
16141 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16143 if (inst
.operands
[2].isscalar
)
16145 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16146 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16147 NEON_ENCODE (SCALAR
, inst
);
16148 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16152 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16153 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16154 NEON_ENCODE (INTEGER
, inst
);
16155 neon_mixed_length (et
, et
.size
);
16160 do_neon_mac_maybe_scalar_long (void)
16162 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16165 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
16166 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
16169 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
16171 unsigned regno
= NEON_SCALAR_REG (scalar
);
16172 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
16176 if (regno
> 7 || elno
> 3)
16179 return ((regno
& 0x7)
16180 | ((elno
& 0x1) << 3)
16181 | (((elno
>> 1) & 0x1) << 5));
16185 if (regno
> 15 || elno
> 1)
16188 return (((regno
& 0x1) << 5)
16189 | ((regno
>> 1) & 0x7)
16190 | ((elno
& 0x1) << 3));
16194 first_error (_("scalar out of range for multiply instruction"));
16199 do_neon_fmac_maybe_scalar_long (int subtype
)
16201 enum neon_shape rs
;
16203 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
16204 field (bits[21:20]) has different meaning. For scalar index variant, it's
16205 used to differentiate add and subtract, otherwise it's with fixed value
16209 if (inst
.cond
!= COND_ALWAYS
)
16210 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
16211 "behaviour is UNPREDICTABLE"));
16213 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
16216 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
16219 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
16220 be a scalar index register. */
16221 if (inst
.operands
[2].isscalar
)
16223 high8
= 0xfe000000;
16226 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
16230 high8
= 0xfc000000;
16233 inst
.instruction
|= (0x1 << 23);
16234 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
16237 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
16239 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
16240 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
16241 so we simply pass -1 as size. */
16242 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
16243 neon_three_same (quad_p
, 0, size
);
16245 /* Undo neon_dp_fixup. Redo the high eight bits. */
16246 inst
.instruction
&= 0x00ffffff;
16247 inst
.instruction
|= high8
;
16249 #define LOW1(R) ((R) & 0x1)
16250 #define HI4(R) (((R) >> 1) & 0xf)
16251 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
16252 whether the instruction is in Q form and whether Vm is a scalar indexed
16254 if (inst
.operands
[2].isscalar
)
16257 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
16258 inst
.instruction
&= 0xffffffd0;
16259 inst
.instruction
|= rm
;
16263 /* Redo Rn as well. */
16264 inst
.instruction
&= 0xfff0ff7f;
16265 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16266 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16271 /* Redo Rn and Rm. */
16272 inst
.instruction
&= 0xfff0ff50;
16273 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16274 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16275 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
16276 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
16281 do_neon_vfmal (void)
16283 return do_neon_fmac_maybe_scalar_long (0);
16287 do_neon_vfmsl (void)
16289 return do_neon_fmac_maybe_scalar_long (1);
16293 do_neon_dyadic_wide (void)
16295 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16296 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16297 neon_mixed_length (et
, et
.size
);
16301 do_neon_dyadic_narrow (void)
16303 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16304 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16305 /* Operand sign is unimportant, and the U bit is part of the opcode,
16306 so force the operand type to integer. */
16307 et
.type
= NT_integer
;
16308 neon_mixed_length (et
, et
.size
/ 2);
16312 do_neon_mul_sat_scalar_long (void)
16314 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16318 do_neon_vmull (void)
16320 if (inst
.operands
[2].isscalar
)
16321 do_neon_mac_maybe_scalar_long ();
16324 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16325 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16327 if (et
.type
== NT_poly
)
16328 NEON_ENCODE (POLY
, inst
);
16330 NEON_ENCODE (INTEGER
, inst
);
16332 /* For polynomial encoding the U bit must be zero, and the size must
16333 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16334 obviously, as 0b10). */
16337 /* Check we're on the correct architecture. */
16338 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16340 _("Instruction form not available on this architecture.");
16345 neon_mixed_length (et
, et
.size
);
16352 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16353 struct neon_type_el et
= neon_check_type (3, rs
,
16354 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16355 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16357 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16358 _("shift out of range"));
16359 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16360 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16361 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16362 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16363 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16364 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16365 inst
.instruction
|= neon_quad (rs
) << 6;
16366 inst
.instruction
|= imm
<< 8;
16368 neon_dp_fixup (&inst
);
16374 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16375 struct neon_type_el et
= neon_check_type (2, rs
,
16376 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16377 unsigned op
= (inst
.instruction
>> 7) & 3;
16378 /* N (width of reversed regions) is encoded as part of the bitmask. We
16379 extract it here to check the elements to be reversed are smaller.
16380 Otherwise we'd get a reserved instruction. */
16381 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16382 gas_assert (elsize
!= 0);
16383 constraint (et
.size
>= elsize
,
16384 _("elements must be smaller than reversal region"));
16385 neon_two_same (neon_quad (rs
), 1, et
.size
);
16391 if (inst
.operands
[1].isscalar
)
16393 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16394 struct neon_type_el et
= neon_check_type (2, rs
,
16395 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16396 unsigned sizebits
= et
.size
>> 3;
16397 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16398 int logsize
= neon_logbits (et
.size
);
16399 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16401 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16404 NEON_ENCODE (SCALAR
, inst
);
16405 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16406 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16407 inst
.instruction
|= LOW4 (dm
);
16408 inst
.instruction
|= HI1 (dm
) << 5;
16409 inst
.instruction
|= neon_quad (rs
) << 6;
16410 inst
.instruction
|= x
<< 17;
16411 inst
.instruction
|= sizebits
<< 16;
16413 neon_dp_fixup (&inst
);
16417 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16418 struct neon_type_el et
= neon_check_type (2, rs
,
16419 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16420 /* Duplicate ARM register to lanes of vector. */
16421 NEON_ENCODE (ARMREG
, inst
);
16424 case 8: inst
.instruction
|= 0x400000; break;
16425 case 16: inst
.instruction
|= 0x000020; break;
16426 case 32: inst
.instruction
|= 0x000000; break;
16429 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16430 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16431 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16432 inst
.instruction
|= neon_quad (rs
) << 21;
16433 /* The encoding for this instruction is identical for the ARM and Thumb
16434 variants, except for the condition field. */
16435 do_vfp_cond_or_thumb ();
16439 /* VMOV has particularly many variations. It can be one of:
16440 0. VMOV<c><q> <Qd>, <Qm>
16441 1. VMOV<c><q> <Dd>, <Dm>
16442 (Register operations, which are VORR with Rm = Rn.)
16443 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16444 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16446 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16447 (ARM register to scalar.)
16448 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16449 (Two ARM registers to vector.)
16450 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16451 (Scalar to ARM register.)
16452 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16453 (Vector to two ARM registers.)
16454 8. VMOV.F32 <Sd>, <Sm>
16455 9. VMOV.F64 <Dd>, <Dm>
16456 (VFP register moves.)
16457 10. VMOV.F32 <Sd>, #imm
16458 11. VMOV.F64 <Dd>, #imm
16459 (VFP float immediate load.)
16460 12. VMOV <Rd>, <Sm>
16461 (VFP single to ARM reg.)
16462 13. VMOV <Sd>, <Rm>
16463 (ARM reg to VFP single.)
16464 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16465 (Two ARM regs to two VFP singles.)
16466 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16467 (Two VFP singles to two ARM regs.)
16469 These cases can be disambiguated using neon_select_shape, except cases 1/9
16470 and 3/11 which depend on the operand type too.
16472 All the encoded bits are hardcoded by this function.
16474 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16475 Cases 5, 7 may be used with VFPv2 and above.
16477 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16478 can specify a type where it doesn't make sense to, and is ignored). */
16483 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16484 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16485 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16486 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16487 struct neon_type_el et
;
16488 const char *ldconst
= 0;
16492 case NS_DD
: /* case 1/9. */
16493 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16494 /* It is not an error here if no type is given. */
16496 if (et
.type
== NT_float
&& et
.size
== 64)
16498 do_vfp_nsyn_opcode ("fcpyd");
16501 /* fall through. */
16503 case NS_QQ
: /* case 0/1. */
16505 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16507 /* The architecture manual I have doesn't explicitly state which
16508 value the U bit should have for register->register moves, but
16509 the equivalent VORR instruction has U = 0, so do that. */
16510 inst
.instruction
= 0x0200110;
16511 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16512 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16513 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16514 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16515 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16516 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16517 inst
.instruction
|= neon_quad (rs
) << 6;
16519 neon_dp_fixup (&inst
);
16523 case NS_DI
: /* case 3/11. */
16524 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16526 if (et
.type
== NT_float
&& et
.size
== 64)
16528 /* case 11 (fconstd). */
16529 ldconst
= "fconstd";
16530 goto encode_fconstd
;
16532 /* fall through. */
16534 case NS_QI
: /* case 2/3. */
16535 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16537 inst
.instruction
= 0x0800010;
16538 neon_move_immediate ();
16539 neon_dp_fixup (&inst
);
16542 case NS_SR
: /* case 4. */
16544 unsigned bcdebits
= 0;
16546 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16547 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16549 /* .<size> is optional here, defaulting to .32. */
16550 if (inst
.vectype
.elems
== 0
16551 && inst
.operands
[0].vectype
.type
== NT_invtype
16552 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16554 inst
.vectype
.el
[0].type
= NT_untyped
;
16555 inst
.vectype
.el
[0].size
= 32;
16556 inst
.vectype
.elems
= 1;
16559 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16560 logsize
= neon_logbits (et
.size
);
16562 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16564 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16565 && et
.size
!= 32, _(BAD_FPU
));
16566 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16567 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16571 case 8: bcdebits
= 0x8; break;
16572 case 16: bcdebits
= 0x1; break;
16573 case 32: bcdebits
= 0x0; break;
16577 bcdebits
|= x
<< logsize
;
16579 inst
.instruction
= 0xe000b10;
16580 do_vfp_cond_or_thumb ();
16581 inst
.instruction
|= LOW4 (dn
) << 16;
16582 inst
.instruction
|= HI1 (dn
) << 7;
16583 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16584 inst
.instruction
|= (bcdebits
& 3) << 5;
16585 inst
.instruction
|= (bcdebits
>> 2) << 21;
16589 case NS_DRR
: /* case 5 (fmdrr). */
16590 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16593 inst
.instruction
= 0xc400b10;
16594 do_vfp_cond_or_thumb ();
16595 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16596 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16597 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16598 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16601 case NS_RS
: /* case 6. */
16604 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16605 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16606 unsigned abcdebits
= 0;
16608 /* .<dt> is optional here, defaulting to .32. */
16609 if (inst
.vectype
.elems
== 0
16610 && inst
.operands
[0].vectype
.type
== NT_invtype
16611 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16613 inst
.vectype
.el
[0].type
= NT_untyped
;
16614 inst
.vectype
.el
[0].size
= 32;
16615 inst
.vectype
.elems
= 1;
16618 et
= neon_check_type (2, NS_NULL
,
16619 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16620 logsize
= neon_logbits (et
.size
);
16622 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16624 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16625 && et
.size
!= 32, _(BAD_FPU
));
16626 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16627 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16631 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16632 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16633 case 32: abcdebits
= 0x00; break;
16637 abcdebits
|= x
<< logsize
;
16638 inst
.instruction
= 0xe100b10;
16639 do_vfp_cond_or_thumb ();
16640 inst
.instruction
|= LOW4 (dn
) << 16;
16641 inst
.instruction
|= HI1 (dn
) << 7;
16642 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16643 inst
.instruction
|= (abcdebits
& 3) << 5;
16644 inst
.instruction
|= (abcdebits
>> 2) << 21;
16648 case NS_RRD
: /* case 7 (fmrrd). */
16649 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16652 inst
.instruction
= 0xc500b10;
16653 do_vfp_cond_or_thumb ();
16654 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16655 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16656 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16657 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16660 case NS_FF
: /* case 8 (fcpys). */
16661 do_vfp_nsyn_opcode ("fcpys");
16665 case NS_FI
: /* case 10 (fconsts). */
16666 ldconst
= "fconsts";
16668 if (is_quarter_float (inst
.operands
[1].imm
))
16670 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16671 do_vfp_nsyn_opcode (ldconst
);
16673 /* ARMv8.2 fp16 vmov.f16 instruction. */
16675 do_scalar_fp16_v82_encode ();
16678 first_error (_("immediate out of range"));
16682 case NS_RF
: /* case 12 (fmrs). */
16683 do_vfp_nsyn_opcode ("fmrs");
16684 /* ARMv8.2 fp16 vmov.f16 instruction. */
16686 do_scalar_fp16_v82_encode ();
16690 case NS_FR
: /* case 13 (fmsr). */
16691 do_vfp_nsyn_opcode ("fmsr");
16692 /* ARMv8.2 fp16 vmov.f16 instruction. */
16694 do_scalar_fp16_v82_encode ();
16697 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16698 (one of which is a list), but we have parsed four. Do some fiddling to
16699 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16701 case NS_RRFF
: /* case 14 (fmrrs). */
16702 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16703 _("VFP registers must be adjacent"));
16704 inst
.operands
[2].imm
= 2;
16705 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16706 do_vfp_nsyn_opcode ("fmrrs");
16709 case NS_FFRR
: /* case 15 (fmsrr). */
16710 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16711 _("VFP registers must be adjacent"));
16712 inst
.operands
[1] = inst
.operands
[2];
16713 inst
.operands
[2] = inst
.operands
[3];
16714 inst
.operands
[0].imm
= 2;
16715 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16716 do_vfp_nsyn_opcode ("fmsrr");
16720 /* neon_select_shape has determined that the instruction
16721 shape is wrong and has already set the error message. */
16730 do_neon_rshift_round_imm (void)
16732 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16733 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16734 int imm
= inst
.operands
[2].imm
;
16736 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16739 inst
.operands
[2].present
= 0;
16744 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16745 _("immediate out of range for shift"));
16746 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16751 do_neon_movhf (void)
16753 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16754 constraint (rs
!= NS_HH
, _("invalid suffix"));
16756 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16759 do_vfp_sp_monadic ();
16762 inst
.instruction
|= 0xf0000000;
16766 do_neon_movl (void)
16768 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16769 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16770 unsigned sizebits
= et
.size
>> 3;
16771 inst
.instruction
|= sizebits
<< 19;
16772 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16778 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16779 struct neon_type_el et
= neon_check_type (2, rs
,
16780 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16781 NEON_ENCODE (INTEGER
, inst
);
16782 neon_two_same (neon_quad (rs
), 1, et
.size
);
16786 do_neon_zip_uzp (void)
16788 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16789 struct neon_type_el et
= neon_check_type (2, rs
,
16790 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16791 if (rs
== NS_DD
&& et
.size
== 32)
16793 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16794 inst
.instruction
= N_MNEM_vtrn
;
16798 neon_two_same (neon_quad (rs
), 1, et
.size
);
16802 do_neon_sat_abs_neg (void)
16804 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16805 struct neon_type_el et
= neon_check_type (2, rs
,
16806 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16807 neon_two_same (neon_quad (rs
), 1, et
.size
);
16811 do_neon_pair_long (void)
16813 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16814 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16815 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16816 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16817 neon_two_same (neon_quad (rs
), 1, et
.size
);
16821 do_neon_recip_est (void)
16823 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16824 struct neon_type_el et
= neon_check_type (2, rs
,
16825 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16826 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16827 neon_two_same (neon_quad (rs
), 1, et
.size
);
16833 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16834 struct neon_type_el et
= neon_check_type (2, rs
,
16835 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16836 neon_two_same (neon_quad (rs
), 1, et
.size
);
16842 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16843 struct neon_type_el et
= neon_check_type (2, rs
,
16844 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16845 neon_two_same (neon_quad (rs
), 1, et
.size
);
16851 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16852 struct neon_type_el et
= neon_check_type (2, rs
,
16853 N_EQK
| N_INT
, N_8
| N_KEY
);
16854 neon_two_same (neon_quad (rs
), 1, et
.size
);
16860 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16861 neon_two_same (neon_quad (rs
), 1, -1);
16865 do_neon_tbl_tbx (void)
16867 unsigned listlenbits
;
16868 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16870 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16872 first_error (_("bad list length for table lookup"));
16876 listlenbits
= inst
.operands
[1].imm
- 1;
16877 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16878 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16879 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16880 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16881 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16882 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16883 inst
.instruction
|= listlenbits
<< 8;
16885 neon_dp_fixup (&inst
);
16889 do_neon_ldm_stm (void)
16891 /* P, U and L bits are part of bitmask. */
16892 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16893 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16895 if (inst
.operands
[1].issingle
)
16897 do_vfp_nsyn_ldm_stm (is_dbmode
);
16901 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16902 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16904 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16905 _("register list must contain at least 1 and at most 16 "
16908 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16909 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16910 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16911 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16913 inst
.instruction
|= offsetbits
;
16915 do_vfp_cond_or_thumb ();
16919 do_neon_ldr_str (void)
16921 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16923 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16924 And is UNPREDICTABLE in thumb mode. */
16926 && inst
.operands
[1].reg
== REG_PC
16927 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16930 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16931 else if (warn_on_deprecated
)
16932 as_tsktsk (_("Use of PC here is deprecated"));
16935 if (inst
.operands
[0].issingle
)
16938 do_vfp_nsyn_opcode ("flds");
16940 do_vfp_nsyn_opcode ("fsts");
16942 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16943 if (inst
.vectype
.el
[0].size
== 16)
16944 do_scalar_fp16_v82_encode ();
16949 do_vfp_nsyn_opcode ("fldd");
16951 do_vfp_nsyn_opcode ("fstd");
16955 /* "interleave" version also handles non-interleaving register VLD1/VST1
16959 do_neon_ld_st_interleave (void)
16961 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16962 N_8
| N_16
| N_32
| N_64
);
16963 unsigned alignbits
= 0;
16965 /* The bits in this table go:
16966 0: register stride of one (0) or two (1)
16967 1,2: register list length, minus one (1, 2, 3, 4).
16968 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16969 We use -1 for invalid entries. */
16970 const int typetable
[] =
16972 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16973 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16974 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16975 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16979 if (et
.type
== NT_invtype
)
16982 if (inst
.operands
[1].immisalign
)
16983 switch (inst
.operands
[1].imm
>> 8)
16985 case 64: alignbits
= 1; break;
16987 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16988 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16989 goto bad_alignment
;
16993 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16994 goto bad_alignment
;
16999 first_error (_("bad alignment"));
17003 inst
.instruction
|= alignbits
<< 4;
17004 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17006 /* Bits [4:6] of the immediate in a list specifier encode register stride
17007 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
17008 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
17009 up the right value for "type" in a table based on this value and the given
17010 list style, then stick it back. */
17011 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
17012 | (((inst
.instruction
>> 8) & 3) << 3);
17014 typebits
= typetable
[idx
];
17016 constraint (typebits
== -1, _("bad list type for instruction"));
17017 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
17018 _("bad element type for instruction"));
17020 inst
.instruction
&= ~0xf00;
17021 inst
.instruction
|= typebits
<< 8;
17024 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
17025 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
17026 otherwise. The variable arguments are a list of pairs of legal (size, align)
17027 values, terminated with -1. */
17030 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
17033 int result
= FAIL
, thissize
, thisalign
;
17035 if (!inst
.operands
[1].immisalign
)
17041 va_start (ap
, do_alignment
);
17045 thissize
= va_arg (ap
, int);
17046 if (thissize
== -1)
17048 thisalign
= va_arg (ap
, int);
17050 if (size
== thissize
&& align
== thisalign
)
17053 while (result
!= SUCCESS
);
17057 if (result
== SUCCESS
)
17060 first_error (_("unsupported alignment for instruction"));
17066 do_neon_ld_st_lane (void)
17068 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17069 int align_good
, do_alignment
= 0;
17070 int logsize
= neon_logbits (et
.size
);
17071 int align
= inst
.operands
[1].imm
>> 8;
17072 int n
= (inst
.instruction
>> 8) & 3;
17073 int max_el
= 64 / et
.size
;
17075 if (et
.type
== NT_invtype
)
17078 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
17079 _("bad list length"));
17080 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
17081 _("scalar index out of range"));
17082 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
17084 _("stride of 2 unavailable when element size is 8"));
17088 case 0: /* VLD1 / VST1. */
17089 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
17091 if (align_good
== FAIL
)
17095 unsigned alignbits
= 0;
17098 case 16: alignbits
= 0x1; break;
17099 case 32: alignbits
= 0x3; break;
17102 inst
.instruction
|= alignbits
<< 4;
17106 case 1: /* VLD2 / VST2. */
17107 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
17108 16, 32, 32, 64, -1);
17109 if (align_good
== FAIL
)
17112 inst
.instruction
|= 1 << 4;
17115 case 2: /* VLD3 / VST3. */
17116 constraint (inst
.operands
[1].immisalign
,
17117 _("can't use alignment with this instruction"));
17120 case 3: /* VLD4 / VST4. */
17121 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17122 16, 64, 32, 64, 32, 128, -1);
17123 if (align_good
== FAIL
)
17127 unsigned alignbits
= 0;
17130 case 8: alignbits
= 0x1; break;
17131 case 16: alignbits
= 0x1; break;
17132 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
17135 inst
.instruction
|= alignbits
<< 4;
17142 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
17143 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17144 inst
.instruction
|= 1 << (4 + logsize
);
17146 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
17147 inst
.instruction
|= logsize
<< 10;
17150 /* Encode single n-element structure to all lanes VLD<n> instructions. */
17153 do_neon_ld_dup (void)
17155 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17156 int align_good
, do_alignment
= 0;
17158 if (et
.type
== NT_invtype
)
17161 switch ((inst
.instruction
>> 8) & 3)
17163 case 0: /* VLD1. */
17164 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
17165 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17166 &do_alignment
, 16, 16, 32, 32, -1);
17167 if (align_good
== FAIL
)
17169 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
17172 case 2: inst
.instruction
|= 1 << 5; break;
17173 default: first_error (_("bad list length")); return;
17175 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17178 case 1: /* VLD2. */
17179 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17180 &do_alignment
, 8, 16, 16, 32, 32, 64,
17182 if (align_good
== FAIL
)
17184 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
17185 _("bad list length"));
17186 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17187 inst
.instruction
|= 1 << 5;
17188 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17191 case 2: /* VLD3. */
17192 constraint (inst
.operands
[1].immisalign
,
17193 _("can't use alignment with this instruction"));
17194 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
17195 _("bad list length"));
17196 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17197 inst
.instruction
|= 1 << 5;
17198 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17201 case 3: /* VLD4. */
17203 int align
= inst
.operands
[1].imm
>> 8;
17204 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17205 16, 64, 32, 64, 32, 128, -1);
17206 if (align_good
== FAIL
)
17208 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
17209 _("bad list length"));
17210 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17211 inst
.instruction
|= 1 << 5;
17212 if (et
.size
== 32 && align
== 128)
17213 inst
.instruction
|= 0x3 << 6;
17215 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17222 inst
.instruction
|= do_alignment
<< 4;
17225 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17226 apart from bits [11:4]. */
17229 do_neon_ldx_stx (void)
17231 if (inst
.operands
[1].isreg
)
17232 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17234 switch (NEON_LANE (inst
.operands
[0].imm
))
17236 case NEON_INTERLEAVE_LANES
:
17237 NEON_ENCODE (INTERLV
, inst
);
17238 do_neon_ld_st_interleave ();
17241 case NEON_ALL_LANES
:
17242 NEON_ENCODE (DUP
, inst
);
17243 if (inst
.instruction
== N_INV
)
17245 first_error ("only loads support such operands");
17252 NEON_ENCODE (LANE
, inst
);
17253 do_neon_ld_st_lane ();
17256 /* L bit comes from bit mask. */
17257 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17258 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17259 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17261 if (inst
.operands
[1].postind
)
17263 int postreg
= inst
.operands
[1].imm
& 0xf;
17264 constraint (!inst
.operands
[1].immisreg
,
17265 _("post-index must be a register"));
17266 constraint (postreg
== 0xd || postreg
== 0xf,
17267 _("bad register for post-index"));
17268 inst
.instruction
|= postreg
;
17272 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17273 constraint (inst
.reloc
.exp
.X_op
!= O_constant
17274 || inst
.reloc
.exp
.X_add_number
!= 0,
17277 if (inst
.operands
[1].writeback
)
17279 inst
.instruction
|= 0xd;
17282 inst
.instruction
|= 0xf;
17286 inst
.instruction
|= 0xf9000000;
17288 inst
.instruction
|= 0xf4000000;
17293 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17295 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17296 D register operands. */
17297 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17298 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17301 NEON_ENCODE (FPV8
, inst
);
17303 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17305 do_vfp_sp_dyadic ();
17307 /* ARMv8.2 fp16 instruction. */
17309 do_scalar_fp16_v82_encode ();
17312 do_vfp_dp_rd_rn_rm ();
17315 inst
.instruction
|= 0x100;
17317 inst
.instruction
|= 0xf0000000;
17323 set_it_insn_type (OUTSIDE_IT_INSN
);
17325 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17326 first_error (_("invalid instruction shape"));
17332 set_it_insn_type (OUTSIDE_IT_INSN
);
17334 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17337 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17340 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17344 do_vrint_1 (enum neon_cvt_mode mode
)
17346 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17347 struct neon_type_el et
;
17352 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17353 D register operands. */
17354 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17355 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17358 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17360 if (et
.type
!= NT_invtype
)
17362 /* VFP encodings. */
17363 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17364 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17365 set_it_insn_type (OUTSIDE_IT_INSN
);
17367 NEON_ENCODE (FPV8
, inst
);
17368 if (rs
== NS_FF
|| rs
== NS_HH
)
17369 do_vfp_sp_monadic ();
17371 do_vfp_dp_rd_rm ();
17375 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17376 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17377 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17378 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17379 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17380 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17381 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17385 inst
.instruction
|= (rs
== NS_DD
) << 8;
17386 do_vfp_cond_or_thumb ();
17388 /* ARMv8.2 fp16 vrint instruction. */
17390 do_scalar_fp16_v82_encode ();
17394 /* Neon encodings (or something broken...). */
17396 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17398 if (et
.type
== NT_invtype
)
17401 set_it_insn_type (OUTSIDE_IT_INSN
);
17402 NEON_ENCODE (FLOAT
, inst
);
17404 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17407 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17408 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17409 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17410 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17411 inst
.instruction
|= neon_quad (rs
) << 6;
17412 /* Mask off the original size bits and reencode them. */
17413 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17414 | neon_logbits (et
.size
) << 18);
17418 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17419 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17420 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17421 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17422 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17423 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17424 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17429 inst
.instruction
|= 0xfc000000;
17431 inst
.instruction
|= 0xf0000000;
17438 do_vrint_1 (neon_cvt_mode_x
);
17444 do_vrint_1 (neon_cvt_mode_z
);
17450 do_vrint_1 (neon_cvt_mode_r
);
17456 do_vrint_1 (neon_cvt_mode_a
);
17462 do_vrint_1 (neon_cvt_mode_n
);
17468 do_vrint_1 (neon_cvt_mode_p
);
17474 do_vrint_1 (neon_cvt_mode_m
);
17478 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
17480 unsigned regno
= NEON_SCALAR_REG (opnd
);
17481 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
17483 if (elsize
== 16 && elno
< 2 && regno
< 16)
17484 return regno
| (elno
<< 4);
17485 else if (elsize
== 32 && elno
== 0)
17488 first_error (_("scalar out of range"));
17495 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17497 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17498 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17499 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
17500 _("immediate out of range"));
17502 if (inst
.operands
[2].isscalar
)
17504 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
17505 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17506 N_KEY
| N_F16
| N_F32
).size
;
17507 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
17509 inst
.instruction
= 0xfe000800;
17510 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17511 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17512 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17513 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17514 inst
.instruction
|= LOW4 (m
);
17515 inst
.instruction
|= HI1 (m
) << 5;
17516 inst
.instruction
|= neon_quad (rs
) << 6;
17517 inst
.instruction
|= rot
<< 20;
17518 inst
.instruction
|= (size
== 32) << 23;
17522 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17523 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17524 N_KEY
| N_F16
| N_F32
).size
;
17525 neon_three_same (neon_quad (rs
), 0, -1);
17526 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17527 inst
.instruction
|= 0xfc200800;
17528 inst
.instruction
|= rot
<< 23;
17529 inst
.instruction
|= (size
== 32) << 20;
17536 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17538 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17539 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17540 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17541 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17542 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17543 N_KEY
| N_F16
| N_F32
).size
;
17544 neon_three_same (neon_quad (rs
), 0, -1);
17545 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17546 inst
.instruction
|= 0xfc800800;
17547 inst
.instruction
|= (rot
== 270) << 24;
17548 inst
.instruction
|= (size
== 32) << 20;
17551 /* Dot Product instructions encoding support. */
17554 do_neon_dotproduct (int unsigned_p
)
17556 enum neon_shape rs
;
17557 unsigned scalar_oprd2
= 0;
17560 if (inst
.cond
!= COND_ALWAYS
)
17561 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
17562 "is UNPREDICTABLE"));
17564 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17567 /* Dot Product instructions are in three-same D/Q register format or the third
17568 operand can be a scalar index register. */
17569 if (inst
.operands
[2].isscalar
)
17571 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
17572 high8
= 0xfe000000;
17573 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17577 high8
= 0xfc000000;
17578 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17582 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
17584 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
17586 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
17587 Product instruction, so we pass 0 as the "ubit" parameter. And the
17588 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
17589 neon_three_same (neon_quad (rs
), 0, 32);
17591 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
17592 different NEON three-same encoding. */
17593 inst
.instruction
&= 0x00ffffff;
17594 inst
.instruction
|= high8
;
17595 /* Encode 'U' bit which indicates signedness. */
17596 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
17597 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
17598 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
17599 the instruction encoding. */
17600 if (inst
.operands
[2].isscalar
)
17602 inst
.instruction
&= 0xffffffd0;
17603 inst
.instruction
|= LOW4 (scalar_oprd2
);
17604 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
17608 /* Dot Product instructions for signed integer. */
17611 do_neon_dotproduct_s (void)
17613 return do_neon_dotproduct (0);
17616 /* Dot Product instructions for unsigned integer. */
17619 do_neon_dotproduct_u (void)
17621 return do_neon_dotproduct (1);
17624 /* Crypto v1 instructions. */
17626 do_crypto_2op_1 (unsigned elttype
, int op
)
17628 set_it_insn_type (OUTSIDE_IT_INSN
);
17630 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17636 NEON_ENCODE (INTEGER
, inst
);
17637 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17638 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17639 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17640 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17642 inst
.instruction
|= op
<< 6;
17645 inst
.instruction
|= 0xfc000000;
17647 inst
.instruction
|= 0xf0000000;
17651 do_crypto_3op_1 (int u
, int op
)
17653 set_it_insn_type (OUTSIDE_IT_INSN
);
17655 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17656 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17661 NEON_ENCODE (INTEGER
, inst
);
17662 neon_three_same (1, u
, 8 << op
);
17668 do_crypto_2op_1 (N_8
, 0);
17674 do_crypto_2op_1 (N_8
, 1);
17680 do_crypto_2op_1 (N_8
, 2);
17686 do_crypto_2op_1 (N_8
, 3);
17692 do_crypto_3op_1 (0, 0);
17698 do_crypto_3op_1 (0, 1);
17704 do_crypto_3op_1 (0, 2);
17710 do_crypto_3op_1 (0, 3);
17716 do_crypto_3op_1 (1, 0);
17722 do_crypto_3op_1 (1, 1);
17726 do_sha256su1 (void)
17728 do_crypto_3op_1 (1, 2);
17734 do_crypto_2op_1 (N_32
, -1);
17740 do_crypto_2op_1 (N_32
, 0);
17744 do_sha256su0 (void)
17746 do_crypto_2op_1 (N_32
, 1);
17750 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17752 unsigned int Rd
= inst
.operands
[0].reg
;
17753 unsigned int Rn
= inst
.operands
[1].reg
;
17754 unsigned int Rm
= inst
.operands
[2].reg
;
17756 set_it_insn_type (OUTSIDE_IT_INSN
);
17757 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17758 inst
.instruction
|= LOW4 (Rn
) << 16;
17759 inst
.instruction
|= LOW4 (Rm
);
17760 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17761 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17763 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17764 as_warn (UNPRED_REG ("r15"));
17806 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17808 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
17809 do_vfp_sp_dp_cvt ();
17810 do_vfp_cond_or_thumb ();
17814 /* Overall per-instruction processing. */
17816 /* We need to be able to fix up arbitrary expressions in some statements.
17817 This is so that we can handle symbols that are an arbitrary distance from
17818 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17819 which returns part of an address in a form which will be valid for
17820 a data instruction. We do this by pushing the expression into a symbol
17821 in the expr_section, and creating a fix for that. */
17824 fix_new_arm (fragS
* frag
,
17838 /* Create an absolute valued symbol, so we have something to
17839 refer to in the object file. Unfortunately for us, gas's
17840 generic expression parsing will already have folded out
17841 any use of .set foo/.type foo %function that may have
17842 been used to set type information of the target location,
17843 that's being specified symbolically. We have to presume
17844 the user knows what they are doing. */
17848 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17850 symbol
= symbol_find_or_make (name
);
17851 S_SET_SEGMENT (symbol
, absolute_section
);
17852 symbol_set_frag (symbol
, &zero_address_frag
);
17853 S_SET_VALUE (symbol
, exp
->X_add_number
);
17854 exp
->X_op
= O_symbol
;
17855 exp
->X_add_symbol
= symbol
;
17856 exp
->X_add_number
= 0;
17862 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17863 (enum bfd_reloc_code_real
) reloc
);
17867 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17868 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17872 /* Mark whether the fix is to a THUMB instruction, or an ARM
17874 new_fix
->tc_fix_data
= thumb_mode
;
17877 /* Create a frg for an instruction requiring relaxation. */
17879 output_relax_insn (void)
17885 /* The size of the instruction is unknown, so tie the debug info to the
17886 start of the instruction. */
17887 dwarf2_emit_insn (0);
17889 switch (inst
.reloc
.exp
.X_op
)
17892 sym
= inst
.reloc
.exp
.X_add_symbol
;
17893 offset
= inst
.reloc
.exp
.X_add_number
;
17897 offset
= inst
.reloc
.exp
.X_add_number
;
17900 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17904 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17905 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17906 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17909 /* Write a 32-bit thumb instruction to buf. */
17911 put_thumb32_insn (char * buf
, unsigned long insn
)
17913 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17914 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17918 output_inst (const char * str
)
17924 as_bad ("%s -- `%s'", inst
.error
, str
);
17929 output_relax_insn ();
17932 if (inst
.size
== 0)
17935 to
= frag_more (inst
.size
);
17936 /* PR 9814: Record the thumb mode into the current frag so that we know
17937 what type of NOP padding to use, if necessary. We override any previous
17938 setting so that if the mode has changed then the NOPS that we use will
17939 match the encoding of the last instruction in the frag. */
17940 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17942 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17944 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17945 put_thumb32_insn (to
, inst
.instruction
);
17947 else if (inst
.size
> INSN_SIZE
)
17949 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17950 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17951 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17954 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17956 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17957 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17958 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17961 dwarf2_emit_insn (inst
.size
);
17965 output_it_inst (int cond
, int mask
, char * to
)
17967 unsigned long instruction
= 0xbf00;
17970 instruction
|= mask
;
17971 instruction
|= cond
<< 4;
17975 to
= frag_more (2);
17977 dwarf2_emit_insn (2);
17981 md_number_to_chars (to
, instruction
, 2);
17986 /* Tag values used in struct asm_opcode's tag field. */
17989 OT_unconditional
, /* Instruction cannot be conditionalized.
17990 The ARM condition field is still 0xE. */
17991 OT_unconditionalF
, /* Instruction cannot be conditionalized
17992 and carries 0xF in its ARM condition field. */
17993 OT_csuffix
, /* Instruction takes a conditional suffix. */
17994 OT_csuffixF
, /* Some forms of the instruction take a conditional
17995 suffix, others place 0xF where the condition field
17997 OT_cinfix3
, /* Instruction takes a conditional infix,
17998 beginning at character index 3. (In
17999 unified mode, it becomes a suffix.) */
18000 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
18001 tsts, cmps, cmns, and teqs. */
18002 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
18003 character index 3, even in unified mode. Used for
18004 legacy instructions where suffix and infix forms
18005 may be ambiguous. */
18006 OT_csuf_or_in3
, /* Instruction takes either a conditional
18007 suffix or an infix at character index 3. */
18008 OT_odd_infix_unc
, /* This is the unconditional variant of an
18009 instruction that takes a conditional infix
18010 at an unusual position. In unified mode,
18011 this variant will accept a suffix. */
18012 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
18013 are the conditional variants of instructions that
18014 take conditional infixes in unusual positions.
18015 The infix appears at character index
18016 (tag - OT_odd_infix_0). These are not accepted
18017 in unified mode. */
18020 /* Subroutine of md_assemble, responsible for looking up the primary
18021 opcode from the mnemonic the user wrote. STR points to the
18022 beginning of the mnemonic.
18024 This is not simply a hash table lookup, because of conditional
18025 variants. Most instructions have conditional variants, which are
18026 expressed with a _conditional affix_ to the mnemonic. If we were
18027 to encode each conditional variant as a literal string in the opcode
18028 table, it would have approximately 20,000 entries.
18030 Most mnemonics take this affix as a suffix, and in unified syntax,
18031 'most' is upgraded to 'all'. However, in the divided syntax, some
18032 instructions take the affix as an infix, notably the s-variants of
18033 the arithmetic instructions. Of those instructions, all but six
18034 have the infix appear after the third character of the mnemonic.
18036 Accordingly, the algorithm for looking up primary opcodes given
18039 1. Look up the identifier in the opcode table.
18040 If we find a match, go to step U.
18042 2. Look up the last two characters of the identifier in the
18043 conditions table. If we find a match, look up the first N-2
18044 characters of the identifier in the opcode table. If we
18045 find a match, go to step CE.
18047 3. Look up the fourth and fifth characters of the identifier in
18048 the conditions table. If we find a match, extract those
18049 characters from the identifier, and look up the remaining
18050 characters in the opcode table. If we find a match, go
18055 U. Examine the tag field of the opcode structure, in case this is
18056 one of the six instructions with its conditional infix in an
18057 unusual place. If it is, the tag tells us where to find the
18058 infix; look it up in the conditions table and set inst.cond
18059 accordingly. Otherwise, this is an unconditional instruction.
18060 Again set inst.cond accordingly. Return the opcode structure.
18062 CE. Examine the tag field to make sure this is an instruction that
18063 should receive a conditional suffix. If it is not, fail.
18064 Otherwise, set inst.cond from the suffix we already looked up,
18065 and return the opcode structure.
18067 CM. Examine the tag field to make sure this is an instruction that
18068 should receive a conditional infix after the third character.
18069 If it is not, fail. Otherwise, undo the edits to the current
18070 line of input and proceed as for case CE. */
18072 static const struct asm_opcode
*
18073 opcode_lookup (char **str
)
18077 const struct asm_opcode
*opcode
;
18078 const struct asm_cond
*cond
;
18081 /* Scan up to the end of the mnemonic, which must end in white space,
18082 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
18083 for (base
= end
= *str
; *end
!= '\0'; end
++)
18084 if (*end
== ' ' || *end
== '.')
18090 /* Handle a possible width suffix and/or Neon type suffix. */
18095 /* The .w and .n suffixes are only valid if the unified syntax is in
18097 if (unified_syntax
&& end
[1] == 'w')
18099 else if (unified_syntax
&& end
[1] == 'n')
18104 inst
.vectype
.elems
= 0;
18106 *str
= end
+ offset
;
18108 if (end
[offset
] == '.')
18110 /* See if we have a Neon type suffix (possible in either unified or
18111 non-unified ARM syntax mode). */
18112 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
18115 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
18121 /* Look for unaffixed or special-case affixed mnemonic. */
18122 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18127 if (opcode
->tag
< OT_odd_infix_0
)
18129 inst
.cond
= COND_ALWAYS
;
18133 if (warn_on_deprecated
&& unified_syntax
)
18134 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18135 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
18136 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18139 inst
.cond
= cond
->value
;
18143 /* Cannot have a conditional suffix on a mnemonic of less than two
18145 if (end
- base
< 3)
18148 /* Look for suffixed mnemonic. */
18150 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18151 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18153 if (opcode
&& cond
)
18156 switch (opcode
->tag
)
18158 case OT_cinfix3_legacy
:
18159 /* Ignore conditional suffixes matched on infix only mnemonics. */
18163 case OT_cinfix3_deprecated
:
18164 case OT_odd_infix_unc
:
18165 if (!unified_syntax
)
18167 /* Fall through. */
18171 case OT_csuf_or_in3
:
18172 inst
.cond
= cond
->value
;
18175 case OT_unconditional
:
18176 case OT_unconditionalF
:
18178 inst
.cond
= cond
->value
;
18181 /* Delayed diagnostic. */
18182 inst
.error
= BAD_COND
;
18183 inst
.cond
= COND_ALWAYS
;
18192 /* Cannot have a usual-position infix on a mnemonic of less than
18193 six characters (five would be a suffix). */
18194 if (end
- base
< 6)
18197 /* Look for infixed mnemonic in the usual position. */
18199 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18203 memcpy (save
, affix
, 2);
18204 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
18205 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18207 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
18208 memcpy (affix
, save
, 2);
18211 && (opcode
->tag
== OT_cinfix3
18212 || opcode
->tag
== OT_cinfix3_deprecated
18213 || opcode
->tag
== OT_csuf_or_in3
18214 || opcode
->tag
== OT_cinfix3_legacy
))
18217 if (warn_on_deprecated
&& unified_syntax
18218 && (opcode
->tag
== OT_cinfix3
18219 || opcode
->tag
== OT_cinfix3_deprecated
))
18220 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18222 inst
.cond
= cond
->value
;
18229 /* This function generates an initial IT instruction, leaving its block
18230 virtually open for the new instructions. Eventually,
18231 the mask will be updated by now_it_add_mask () each time
18232 a new instruction needs to be included in the IT block.
18233 Finally, the block is closed with close_automatic_it_block ().
18234 The block closure can be requested either from md_assemble (),
18235 a tencode (), or due to a label hook. */
18238 new_automatic_it_block (int cond
)
18240 now_it
.state
= AUTOMATIC_IT_BLOCK
;
18241 now_it
.mask
= 0x18;
18243 now_it
.block_length
= 1;
18244 mapping_state (MAP_THUMB
);
18245 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
18246 now_it
.warn_deprecated
= FALSE
;
18247 now_it
.insn_cond
= TRUE
;
18250 /* Close an automatic IT block.
18251 See comments in new_automatic_it_block (). */
18254 close_automatic_it_block (void)
18256 now_it
.mask
= 0x10;
18257 now_it
.block_length
= 0;
18260 /* Update the mask of the current automatically-generated IT
18261 instruction. See comments in new_automatic_it_block (). */
18264 now_it_add_mask (int cond
)
18266 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
18267 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
18268 | ((bitvalue) << (nbit)))
18269 const int resulting_bit
= (cond
& 1);
18271 now_it
.mask
&= 0xf;
18272 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18274 (5 - now_it
.block_length
));
18275 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18277 ((5 - now_it
.block_length
) - 1) );
18278 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
18281 #undef SET_BIT_VALUE
18284 /* The IT blocks handling machinery is accessed through the these functions:
18285 it_fsm_pre_encode () from md_assemble ()
18286 set_it_insn_type () optional, from the tencode functions
18287 set_it_insn_type_last () ditto
18288 in_it_block () ditto
18289 it_fsm_post_encode () from md_assemble ()
18290 force_automatic_it_block_close () from label handling functions
18293 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
18294 initializing the IT insn type with a generic initial value depending
18295 on the inst.condition.
18296 2) During the tencode function, two things may happen:
18297 a) The tencode function overrides the IT insn type by
18298 calling either set_it_insn_type (type) or set_it_insn_type_last ().
18299 b) The tencode function queries the IT block state by
18300 calling in_it_block () (i.e. to determine narrow/not narrow mode).
18302 Both set_it_insn_type and in_it_block run the internal FSM state
18303 handling function (handle_it_state), because: a) setting the IT insn
18304 type may incur in an invalid state (exiting the function),
18305 and b) querying the state requires the FSM to be updated.
18306 Specifically we want to avoid creating an IT block for conditional
18307 branches, so it_fsm_pre_encode is actually a guess and we can't
18308 determine whether an IT block is required until the tencode () routine
18309 has decided what type of instruction this actually it.
18310 Because of this, if set_it_insn_type and in_it_block have to be used,
18311 set_it_insn_type has to be called first.
18313 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
18314 determines the insn IT type depending on the inst.cond code.
18315 When a tencode () routine encodes an instruction that can be
18316 either outside an IT block, or, in the case of being inside, has to be
18317 the last one, set_it_insn_type_last () will determine the proper
18318 IT instruction type based on the inst.cond code. Otherwise,
18319 set_it_insn_type can be called for overriding that logic or
18320 for covering other cases.
18322 Calling handle_it_state () may not transition the IT block state to
18323 OUTSIDE_IT_BLOCK immediately, since the (current) state could be
18324 still queried. Instead, if the FSM determines that the state should
18325 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
18326 after the tencode () function: that's what it_fsm_post_encode () does.
18328 Since in_it_block () calls the state handling function to get an
18329 updated state, an error may occur (due to invalid insns combination).
18330 In that case, inst.error is set.
18331 Therefore, inst.error has to be checked after the execution of
18332 the tencode () routine.
18334 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
18335 any pending state change (if any) that didn't take place in
18336 handle_it_state () as explained above. */
18339 it_fsm_pre_encode (void)
18341 if (inst
.cond
!= COND_ALWAYS
)
18342 inst
.it_insn_type
= INSIDE_IT_INSN
;
18344 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
18346 now_it
.state_handled
= 0;
18349 /* IT state FSM handling function. */
18352 handle_it_state (void)
18354 now_it
.state_handled
= 1;
18355 now_it
.insn_cond
= FALSE
;
18357 switch (now_it
.state
)
18359 case OUTSIDE_IT_BLOCK
:
18360 switch (inst
.it_insn_type
)
18362 case OUTSIDE_IT_INSN
:
18365 case INSIDE_IT_INSN
:
18366 case INSIDE_IT_LAST_INSN
:
18367 if (thumb_mode
== 0)
18370 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
18371 as_tsktsk (_("Warning: conditional outside an IT block"\
18376 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
18377 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
18379 /* Automatically generate the IT instruction. */
18380 new_automatic_it_block (inst
.cond
);
18381 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
18382 close_automatic_it_block ();
18386 inst
.error
= BAD_OUT_IT
;
18392 case IF_INSIDE_IT_LAST_INSN
:
18393 case NEUTRAL_IT_INSN
:
18397 now_it
.state
= MANUAL_IT_BLOCK
;
18398 now_it
.block_length
= 0;
18403 case AUTOMATIC_IT_BLOCK
:
18404 /* Three things may happen now:
18405 a) We should increment current it block size;
18406 b) We should close current it block (closing insn or 4 insns);
18407 c) We should close current it block and start a new one (due
18408 to incompatible conditions or
18409 4 insns-length block reached). */
18411 switch (inst
.it_insn_type
)
18413 case OUTSIDE_IT_INSN
:
18414 /* The closure of the block shall happen immediately,
18415 so any in_it_block () call reports the block as closed. */
18416 force_automatic_it_block_close ();
18419 case INSIDE_IT_INSN
:
18420 case INSIDE_IT_LAST_INSN
:
18421 case IF_INSIDE_IT_LAST_INSN
:
18422 now_it
.block_length
++;
18424 if (now_it
.block_length
> 4
18425 || !now_it_compatible (inst
.cond
))
18427 force_automatic_it_block_close ();
18428 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18429 new_automatic_it_block (inst
.cond
);
18433 now_it
.insn_cond
= TRUE
;
18434 now_it_add_mask (inst
.cond
);
18437 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18438 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18439 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18440 close_automatic_it_block ();
18443 case NEUTRAL_IT_INSN
:
18444 now_it
.block_length
++;
18445 now_it
.insn_cond
= TRUE
;
18447 if (now_it
.block_length
> 4)
18448 force_automatic_it_block_close ();
18450 now_it_add_mask (now_it
.cc
& 1);
18454 close_automatic_it_block ();
18455 now_it
.state
= MANUAL_IT_BLOCK
;
18460 case MANUAL_IT_BLOCK
:
18462 /* Check conditional suffixes. */
18463 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18466 now_it
.mask
&= 0x1f;
18467 is_last
= (now_it
.mask
== 0x10);
18468 now_it
.insn_cond
= TRUE
;
18470 switch (inst
.it_insn_type
)
18472 case OUTSIDE_IT_INSN
:
18473 inst
.error
= BAD_NOT_IT
;
18476 case INSIDE_IT_INSN
:
18477 if (cond
!= inst
.cond
)
18479 inst
.error
= BAD_IT_COND
;
18484 case INSIDE_IT_LAST_INSN
:
18485 case IF_INSIDE_IT_LAST_INSN
:
18486 if (cond
!= inst
.cond
)
18488 inst
.error
= BAD_IT_COND
;
18493 inst
.error
= BAD_BRANCH
;
18498 case NEUTRAL_IT_INSN
:
18499 /* The BKPT instruction is unconditional even in an IT block. */
18503 inst
.error
= BAD_IT_IT
;
18513 struct depr_insn_mask
18515 unsigned long pattern
;
18516 unsigned long mask
;
18517 const char* description
;
18520 /* List of 16-bit instruction patterns deprecated in an IT block in
18522 static const struct depr_insn_mask depr_it_insns
[] = {
18523 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18524 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18525 { 0xa000, 0xb800, N_("ADR") },
18526 { 0x4800, 0xf800, N_("Literal loads") },
18527 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18528 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18529 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18530 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18531 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18536 it_fsm_post_encode (void)
18540 if (!now_it
.state_handled
)
18541 handle_it_state ();
18543 if (now_it
.insn_cond
18544 && !now_it
.warn_deprecated
18545 && warn_on_deprecated
18546 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
18548 if (inst
.instruction
>= 0x10000)
18550 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18551 "deprecated in ARMv8"));
18552 now_it
.warn_deprecated
= TRUE
;
18556 const struct depr_insn_mask
*p
= depr_it_insns
;
18558 while (p
->mask
!= 0)
18560 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18562 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18563 "of the following class are deprecated in ARMv8: "
18564 "%s"), p
->description
);
18565 now_it
.warn_deprecated
= TRUE
;
18573 if (now_it
.block_length
> 1)
18575 as_tsktsk (_("IT blocks containing more than one conditional "
18576 "instruction are deprecated in ARMv8"));
18577 now_it
.warn_deprecated
= TRUE
;
18581 is_last
= (now_it
.mask
== 0x10);
18584 now_it
.state
= OUTSIDE_IT_BLOCK
;
18590 force_automatic_it_block_close (void)
18592 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18594 close_automatic_it_block ();
18595 now_it
.state
= OUTSIDE_IT_BLOCK
;
18603 if (!now_it
.state_handled
)
18604 handle_it_state ();
18606 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18609 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18610 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18611 here, hence the "known" in the function name. */
18614 known_t32_only_insn (const struct asm_opcode
*opcode
)
18616 /* Original Thumb-1 wide instruction. */
18617 if (opcode
->tencode
== do_t_blx
18618 || opcode
->tencode
== do_t_branch23
18619 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18620 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18623 /* Wide-only instruction added to ARMv8-M Baseline. */
18624 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18625 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18626 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18627 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18633 /* Whether wide instruction variant can be used if available for a valid OPCODE
18637 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18639 if (known_t32_only_insn (opcode
))
18642 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18643 of variant T3 of B.W is checked in do_t_branch. */
18644 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18645 && opcode
->tencode
== do_t_branch
)
18648 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
18649 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18650 && opcode
->tencode
== do_t_mov_cmp
18651 /* Make sure CMP instruction is not affected. */
18652 && opcode
->aencode
== do_mov
)
18655 /* Wide instruction variants of all instructions with narrow *and* wide
18656 variants become available with ARMv6t2. Other opcodes are either
18657 narrow-only or wide-only and are thus available if OPCODE is valid. */
18658 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18661 /* OPCODE with narrow only instruction variant or wide variant not
18667 md_assemble (char *str
)
18670 const struct asm_opcode
* opcode
;
18672 /* Align the previous label if needed. */
18673 if (last_label_seen
!= NULL
)
18675 symbol_set_frag (last_label_seen
, frag_now
);
18676 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18677 S_SET_SEGMENT (last_label_seen
, now_seg
);
18680 memset (&inst
, '\0', sizeof (inst
));
18681 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18683 opcode
= opcode_lookup (&p
);
18686 /* It wasn't an instruction, but it might be a register alias of
18687 the form alias .req reg, or a Neon .dn/.qn directive. */
18688 if (! create_register_alias (str
, p
)
18689 && ! create_neon_reg_alias (str
, p
))
18690 as_bad (_("bad instruction `%s'"), str
);
18695 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18696 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18698 /* The value which unconditional instructions should have in place of the
18699 condition field. */
18700 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18704 arm_feature_set variant
;
18706 variant
= cpu_variant
;
18707 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18708 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18709 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18710 /* Check that this instruction is supported for this CPU. */
18711 if (!opcode
->tvariant
18712 || (thumb_mode
== 1
18713 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18715 if (opcode
->tencode
== do_t_swi
)
18716 as_bad (_("SVC is not permitted on this architecture"));
18718 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18721 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18722 && opcode
->tencode
!= do_t_branch
)
18724 as_bad (_("Thumb does not support conditional execution"));
18728 /* Two things are addressed here:
18729 1) Implicit require narrow instructions on Thumb-1.
18730 This avoids relaxation accidentally introducing Thumb-2
18732 2) Reject wide instructions in non Thumb-2 cores.
18734 Only instructions with narrow and wide variants need to be handled
18735 but selecting all non wide-only instructions is easier. */
18736 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18737 && !t32_insn_ok (variant
, opcode
))
18739 if (inst
.size_req
== 0)
18741 else if (inst
.size_req
== 4)
18743 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18744 as_bad (_("selected processor does not support 32bit wide "
18745 "variant of instruction `%s'"), str
);
18747 as_bad (_("selected processor does not support `%s' in "
18748 "Thumb-2 mode"), str
);
18753 inst
.instruction
= opcode
->tvalue
;
18755 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18757 /* Prepare the it_insn_type for those encodings that don't set
18759 it_fsm_pre_encode ();
18761 opcode
->tencode ();
18763 it_fsm_post_encode ();
18766 if (!(inst
.error
|| inst
.relax
))
18768 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18769 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18770 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18772 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18777 /* Something has gone badly wrong if we try to relax a fixed size
18779 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18781 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18782 *opcode
->tvariant
);
18783 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18784 set those bits when Thumb-2 32-bit instructions are seen. The impact
18785 of relaxable instructions will be considered later after we finish all
18787 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18788 variant
= arm_arch_none
;
18790 variant
= cpu_variant
;
18791 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18792 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18795 check_neon_suffixes
;
18799 mapping_state (MAP_THUMB
);
18802 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18806 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18807 is_bx
= (opcode
->aencode
== do_bx
);
18809 /* Check that this instruction is supported for this CPU. */
18810 if (!(is_bx
&& fix_v4bx
)
18811 && !(opcode
->avariant
&&
18812 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18814 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18819 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18823 inst
.instruction
= opcode
->avalue
;
18824 if (opcode
->tag
== OT_unconditionalF
)
18825 inst
.instruction
|= 0xFU
<< 28;
18827 inst
.instruction
|= inst
.cond
<< 28;
18828 inst
.size
= INSN_SIZE
;
18829 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18831 it_fsm_pre_encode ();
18832 opcode
->aencode ();
18833 it_fsm_post_encode ();
18835 /* Arm mode bx is marked as both v4T and v5 because it's still required
18836 on a hypothetical non-thumb v5 core. */
18838 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18840 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18841 *opcode
->avariant
);
18843 check_neon_suffixes
;
18847 mapping_state (MAP_ARM
);
18852 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18860 check_it_blocks_finished (void)
18865 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18866 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18867 == MANUAL_IT_BLOCK
)
18869 as_warn (_("section '%s' finished with an open IT block."),
18873 if (now_it
.state
== MANUAL_IT_BLOCK
)
18874 as_warn (_("file finished with an open IT block."));
18878 /* Various frobbings of labels and their addresses. */
18881 arm_start_line_hook (void)
18883 last_label_seen
= NULL
;
18887 arm_frob_label (symbolS
* sym
)
18889 last_label_seen
= sym
;
18891 ARM_SET_THUMB (sym
, thumb_mode
);
18893 #if defined OBJ_COFF || defined OBJ_ELF
18894 ARM_SET_INTERWORK (sym
, support_interwork
);
18897 force_automatic_it_block_close ();
18899 /* Note - do not allow local symbols (.Lxxx) to be labelled
18900 as Thumb functions. This is because these labels, whilst
18901 they exist inside Thumb code, are not the entry points for
18902 possible ARM->Thumb calls. Also, these labels can be used
18903 as part of a computed goto or switch statement. eg gcc
18904 can generate code that looks like this:
18906 ldr r2, [pc, .Laaa]
18916 The first instruction loads the address of the jump table.
18917 The second instruction converts a table index into a byte offset.
18918 The third instruction gets the jump address out of the table.
18919 The fourth instruction performs the jump.
18921 If the address stored at .Laaa is that of a symbol which has the
18922 Thumb_Func bit set, then the linker will arrange for this address
18923 to have the bottom bit set, which in turn would mean that the
18924 address computation performed by the third instruction would end
18925 up with the bottom bit set. Since the ARM is capable of unaligned
18926 word loads, the instruction would then load the incorrect address
18927 out of the jump table, and chaos would ensue. */
18928 if (label_is_thumb_function_name
18929 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18930 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18932 /* When the address of a Thumb function is taken the bottom
18933 bit of that address should be set. This will allow
18934 interworking between Arm and Thumb functions to work
18937 THUMB_SET_FUNC (sym
, 1);
18939 label_is_thumb_function_name
= FALSE
;
18942 dwarf2_emit_label (sym
);
18946 arm_data_in_code (void)
18948 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18950 *input_line_pointer
= '/';
18951 input_line_pointer
+= 5;
18952 *input_line_pointer
= 0;
18960 arm_canonicalize_symbol_name (char * name
)
18964 if (thumb_mode
&& (len
= strlen (name
)) > 5
18965 && streq (name
+ len
- 5, "/data"))
18966 *(name
+ len
- 5) = 0;
18971 /* Table of all register names defined by default. The user can
18972 define additional names with .req. Note that all register names
18973 should appear in both upper and lowercase variants. Some registers
18974 also have mixed-case names. */
18976 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18977 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18978 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18979 #define REGSET(p,t) \
18980 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18981 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18982 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18983 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18984 #define REGSETH(p,t) \
18985 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18986 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18987 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18988 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18989 #define REGSET2(p,t) \
18990 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18991 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18992 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18993 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18994 #define SPLRBANK(base,bank,t) \
18995 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18996 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18997 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18998 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18999 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
19000 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
19002 static const struct reg_entry reg_names
[] =
19004 /* ARM integer registers. */
19005 REGSET(r
, RN
), REGSET(R
, RN
),
19007 /* ATPCS synonyms. */
19008 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
19009 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
19010 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
19012 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
19013 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
19014 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
19016 /* Well-known aliases. */
19017 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
19018 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
19020 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
19021 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
19023 /* Coprocessor numbers. */
19024 REGSET(p
, CP
), REGSET(P
, CP
),
19026 /* Coprocessor register numbers. The "cr" variants are for backward
19028 REGSET(c
, CN
), REGSET(C
, CN
),
19029 REGSET(cr
, CN
), REGSET(CR
, CN
),
19031 /* ARM banked registers. */
19032 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
19033 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
19034 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
19035 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
19036 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
19037 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
19038 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
19040 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
19041 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
19042 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
19043 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
19044 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
19045 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
19046 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
19047 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
19049 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
19050 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
19051 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
19052 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
19053 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
19054 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
19055 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
19056 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19057 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19059 /* FPA registers. */
19060 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
19061 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
19063 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
19064 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
19066 /* VFP SP registers. */
19067 REGSET(s
,VFS
), REGSET(S
,VFS
),
19068 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
19070 /* VFP DP Registers. */
19071 REGSET(d
,VFD
), REGSET(D
,VFD
),
19072 /* Extra Neon DP registers. */
19073 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
19075 /* Neon QP registers. */
19076 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
19078 /* VFP control registers. */
19079 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
19080 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
19081 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
19082 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
19083 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
19084 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
19085 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
19087 /* Maverick DSP coprocessor registers. */
19088 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
19089 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
19091 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
19092 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
19093 REGDEF(dspsc
,0,DSPSC
),
19095 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
19096 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
19097 REGDEF(DSPSC
,0,DSPSC
),
19099 /* iWMMXt data registers - p0, c0-15. */
19100 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
19102 /* iWMMXt control registers - p1, c0-3. */
19103 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
19104 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
19105 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
19106 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
19108 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
19109 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
19110 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
19111 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
19112 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
19114 /* XScale accumulator registers. */
19115 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
19121 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
19122 within psr_required_here. */
19123 static const struct asm_psr psrs
[] =
19125 /* Backward compatibility notation. Note that "all" is no longer
19126 truly all possible PSR bits. */
19127 {"all", PSR_c
| PSR_f
},
19131 /* Individual flags. */
19137 /* Combinations of flags. */
19138 {"fs", PSR_f
| PSR_s
},
19139 {"fx", PSR_f
| PSR_x
},
19140 {"fc", PSR_f
| PSR_c
},
19141 {"sf", PSR_s
| PSR_f
},
19142 {"sx", PSR_s
| PSR_x
},
19143 {"sc", PSR_s
| PSR_c
},
19144 {"xf", PSR_x
| PSR_f
},
19145 {"xs", PSR_x
| PSR_s
},
19146 {"xc", PSR_x
| PSR_c
},
19147 {"cf", PSR_c
| PSR_f
},
19148 {"cs", PSR_c
| PSR_s
},
19149 {"cx", PSR_c
| PSR_x
},
19150 {"fsx", PSR_f
| PSR_s
| PSR_x
},
19151 {"fsc", PSR_f
| PSR_s
| PSR_c
},
19152 {"fxs", PSR_f
| PSR_x
| PSR_s
},
19153 {"fxc", PSR_f
| PSR_x
| PSR_c
},
19154 {"fcs", PSR_f
| PSR_c
| PSR_s
},
19155 {"fcx", PSR_f
| PSR_c
| PSR_x
},
19156 {"sfx", PSR_s
| PSR_f
| PSR_x
},
19157 {"sfc", PSR_s
| PSR_f
| PSR_c
},
19158 {"sxf", PSR_s
| PSR_x
| PSR_f
},
19159 {"sxc", PSR_s
| PSR_x
| PSR_c
},
19160 {"scf", PSR_s
| PSR_c
| PSR_f
},
19161 {"scx", PSR_s
| PSR_c
| PSR_x
},
19162 {"xfs", PSR_x
| PSR_f
| PSR_s
},
19163 {"xfc", PSR_x
| PSR_f
| PSR_c
},
19164 {"xsf", PSR_x
| PSR_s
| PSR_f
},
19165 {"xsc", PSR_x
| PSR_s
| PSR_c
},
19166 {"xcf", PSR_x
| PSR_c
| PSR_f
},
19167 {"xcs", PSR_x
| PSR_c
| PSR_s
},
19168 {"cfs", PSR_c
| PSR_f
| PSR_s
},
19169 {"cfx", PSR_c
| PSR_f
| PSR_x
},
19170 {"csf", PSR_c
| PSR_s
| PSR_f
},
19171 {"csx", PSR_c
| PSR_s
| PSR_x
},
19172 {"cxf", PSR_c
| PSR_x
| PSR_f
},
19173 {"cxs", PSR_c
| PSR_x
| PSR_s
},
19174 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
19175 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
19176 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
19177 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
19178 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
19179 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
19180 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
19181 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
19182 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
19183 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
19184 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
19185 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
19186 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
19187 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
19188 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
19189 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
19190 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
19191 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
19192 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
19193 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
19194 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
19195 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
19196 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
19197 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
19200 /* Table of V7M psr names. */
19201 static const struct asm_psr v7m_psrs
[] =
19203 {"apsr", 0x0 }, {"APSR", 0x0 },
19204 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
19205 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
19206 {"psr", 0x3 }, {"PSR", 0x3 },
19207 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
19208 {"ipsr", 0x5 }, {"IPSR", 0x5 },
19209 {"epsr", 0x6 }, {"EPSR", 0x6 },
19210 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
19211 {"msp", 0x8 }, {"MSP", 0x8 },
19212 {"psp", 0x9 }, {"PSP", 0x9 },
19213 {"msplim", 0xa }, {"MSPLIM", 0xa },
19214 {"psplim", 0xb }, {"PSPLIM", 0xb },
19215 {"primask", 0x10}, {"PRIMASK", 0x10},
19216 {"basepri", 0x11}, {"BASEPRI", 0x11},
19217 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
19218 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
19219 {"control", 0x14}, {"CONTROL", 0x14},
19220 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
19221 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
19222 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
19223 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
19224 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
19225 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
19226 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
19227 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
19228 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
19231 /* Table of all shift-in-operand names. */
19232 static const struct asm_shift_name shift_names
[] =
19234 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
19235 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
19236 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
19237 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
19238 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
19239 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
19242 /* Table of all explicit relocation names. */
19244 static struct reloc_entry reloc_names
[] =
19246 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
19247 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
19248 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
19249 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
19250 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
19251 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
19252 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
19253 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
19254 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
19255 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
19256 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
19257 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
19258 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
19259 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
19260 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
19261 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
19262 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
19263 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
19267 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
19268 static const struct asm_cond conds
[] =
19272 {"cs", 0x2}, {"hs", 0x2},
19273 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
19287 #define UL_BARRIER(L,U,CODE,FEAT) \
19288 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
19289 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
19291 static struct asm_barrier_opt barrier_opt_names
[] =
19293 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
19294 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
19295 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
19296 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
19297 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
19298 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
19299 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
19300 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
19301 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
19302 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
19303 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
19304 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
19305 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
19306 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
19307 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
19308 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
19313 /* Table of ARM-format instructions. */
19315 /* Macros for gluing together operand strings. N.B. In all cases
19316 other than OPS0, the trailing OP_stop comes from default
19317 zero-initialization of the unspecified elements of the array. */
19318 #define OPS0() { OP_stop, }
19319 #define OPS1(a) { OP_##a, }
19320 #define OPS2(a,b) { OP_##a,OP_##b, }
19321 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
19322 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
19323 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
19324 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
19326 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
19327 This is useful when mixing operands for ARM and THUMB, i.e. using the
19328 MIX_ARM_THUMB_OPERANDS macro.
19329 In order to use these macros, prefix the number of operands with _
19331 #define OPS_1(a) { a, }
19332 #define OPS_2(a,b) { a,b, }
19333 #define OPS_3(a,b,c) { a,b,c, }
19334 #define OPS_4(a,b,c,d) { a,b,c,d, }
19335 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
19336 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
19338 /* These macros abstract out the exact format of the mnemonic table and
19339 save some repeated characters. */
19341 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
19342 #define TxCE(mnem, op, top, nops, ops, ae, te) \
19343 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
19344 THUMB_VARIANT, do_##ae, do_##te }
19346 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
19347 a T_MNEM_xyz enumerator. */
19348 #define TCE(mnem, aop, top, nops, ops, ae, te) \
19349 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
19350 #define tCE(mnem, aop, top, nops, ops, ae, te) \
19351 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19353 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
19354 infix after the third character. */
19355 #define TxC3(mnem, op, top, nops, ops, ae, te) \
19356 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
19357 THUMB_VARIANT, do_##ae, do_##te }
19358 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
19359 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
19360 THUMB_VARIANT, do_##ae, do_##te }
19361 #define TC3(mnem, aop, top, nops, ops, ae, te) \
19362 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
19363 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
19364 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
19365 #define tC3(mnem, aop, top, nops, ops, ae, te) \
19366 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19367 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
19368 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19370 /* Mnemonic that cannot be conditionalized. The ARM condition-code
19371 field is still 0xE. Many of the Thumb variants can be executed
19372 conditionally, so this is checked separately. */
19373 #define TUE(mnem, op, top, nops, ops, ae, te) \
19374 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19375 THUMB_VARIANT, do_##ae, do_##te }
19377 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
19378 Used by mnemonics that have very minimal differences in the encoding for
19379 ARM and Thumb variants and can be handled in a common function. */
19380 #define TUEc(mnem, op, top, nops, ops, en) \
19381 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19382 THUMB_VARIANT, do_##en, do_##en }
19384 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
19385 condition code field. */
19386 #define TUF(mnem, op, top, nops, ops, ae, te) \
19387 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19388 THUMB_VARIANT, do_##ae, do_##te }
19390 /* ARM-only variants of all the above. */
19391 #define CE(mnem, op, nops, ops, ae) \
19392 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19394 #define C3(mnem, op, nops, ops, ae) \
19395 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19397 /* Legacy mnemonics that always have conditional infix after the third
19399 #define CL(mnem, op, nops, ops, ae) \
19400 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19401 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19403 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19404 #define cCE(mnem, op, nops, ops, ae) \
19405 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19407 /* Legacy coprocessor instructions where conditional infix and conditional
19408 suffix are ambiguous. For consistency this includes all FPA instructions,
19409 not just the potentially ambiguous ones. */
19410 #define cCL(mnem, op, nops, ops, ae) \
19411 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19412 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19414 /* Coprocessor, takes either a suffix or a position-3 infix
19415 (for an FPA corner case). */
19416 #define C3E(mnem, op, nops, ops, ae) \
19417 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19418 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19420 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19421 { m1 #m2 m3, OPS##nops ops, \
19422 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19423 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19425 #define CM(m1, m2, op, nops, ops, ae) \
19426 xCM_ (m1, , m2, op, nops, ops, ae), \
19427 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19428 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19429 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19430 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19431 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19432 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19433 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19434 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19435 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19436 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19437 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19438 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19439 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19440 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19441 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19442 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19443 xCM_ (m1, le, m2, op, nops, ops, ae), \
19444 xCM_ (m1, al, m2, op, nops, ops, ae)
19446 #define UE(mnem, op, nops, ops, ae) \
19447 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19449 #define UF(mnem, op, nops, ops, ae) \
19450 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19452 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19453 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19454 use the same encoding function for each. */
19455 #define NUF(mnem, op, nops, ops, enc) \
19456 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19457 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19459 /* Neon data processing, version which indirects through neon_enc_tab for
19460 the various overloaded versions of opcodes. */
19461 #define nUF(mnem, op, nops, ops, enc) \
19462 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19463 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19465 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19467 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19468 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19469 THUMB_VARIANT, do_##enc, do_##enc }
19471 #define NCE(mnem, op, nops, ops, enc) \
19472 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19474 #define NCEF(mnem, op, nops, ops, enc) \
19475 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19477 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19478 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19479 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19480 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19482 #define nCE(mnem, op, nops, ops, enc) \
19483 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19485 #define nCEF(mnem, op, nops, ops, enc) \
19486 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19490 static const struct asm_opcode insns
[] =
19492 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19493 #define THUMB_VARIANT & arm_ext_v4t
19494 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19495 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19496 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19497 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19498 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19499 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19500 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19501 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19502 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19503 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19504 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19505 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19506 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19507 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19508 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19509 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19511 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19512 for setting PSR flag bits. They are obsolete in V6 and do not
19513 have Thumb equivalents. */
19514 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19515 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19516 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19517 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19518 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19519 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19520 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19521 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19522 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19524 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19525 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19526 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19527 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19529 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19530 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19531 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19533 OP_ADDRGLDR
),ldst
, t_ldst
),
19534 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19536 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19537 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19538 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19539 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19540 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19541 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19543 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19544 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19547 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19548 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19549 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19550 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19552 /* Thumb-compatibility pseudo ops. */
19553 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19554 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19555 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19556 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19557 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19558 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19559 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19560 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19561 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19562 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19563 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19564 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19566 /* These may simplify to neg. */
19567 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19568 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19570 #undef THUMB_VARIANT
19571 #define THUMB_VARIANT & arm_ext_os
19573 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19574 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19576 #undef THUMB_VARIANT
19577 #define THUMB_VARIANT & arm_ext_v6
19579 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19581 /* V1 instructions with no Thumb analogue prior to V6T2. */
19582 #undef THUMB_VARIANT
19583 #define THUMB_VARIANT & arm_ext_v6t2
19585 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19586 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19587 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19589 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19590 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19591 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19592 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19594 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19595 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19597 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19598 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19600 /* V1 instructions with no Thumb analogue at all. */
19601 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19602 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19604 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19605 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19606 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19607 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19608 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19609 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19610 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19611 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19614 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19615 #undef THUMB_VARIANT
19616 #define THUMB_VARIANT & arm_ext_v4t
19618 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19619 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19621 #undef THUMB_VARIANT
19622 #define THUMB_VARIANT & arm_ext_v6t2
19624 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19625 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19627 /* Generic coprocessor instructions. */
19628 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19629 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19630 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19631 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19632 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19633 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19634 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19637 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19639 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19640 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19643 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19644 #undef THUMB_VARIANT
19645 #define THUMB_VARIANT & arm_ext_msr
19647 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19648 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19651 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19652 #undef THUMB_VARIANT
19653 #define THUMB_VARIANT & arm_ext_v6t2
19655 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19656 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19657 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19658 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19659 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19660 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19661 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19662 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19665 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19666 #undef THUMB_VARIANT
19667 #define THUMB_VARIANT & arm_ext_v4t
19669 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19670 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19671 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19672 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19673 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19674 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19677 #define ARM_VARIANT & arm_ext_v4t_5
19679 /* ARM Architecture 4T. */
19680 /* Note: bx (and blx) are required on V5, even if the processor does
19681 not support Thumb. */
19682 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19685 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19686 #undef THUMB_VARIANT
19687 #define THUMB_VARIANT & arm_ext_v5t
19689 /* Note: blx has 2 variants; the .value coded here is for
19690 BLX(2). Only this variant has conditional execution. */
19691 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19692 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19694 #undef THUMB_VARIANT
19695 #define THUMB_VARIANT & arm_ext_v6t2
19697 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19698 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19699 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19700 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19701 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19702 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19703 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19704 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19707 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19708 #undef THUMB_VARIANT
19709 #define THUMB_VARIANT & arm_ext_v5exp
19711 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19712 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19713 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19714 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19716 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19717 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19719 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19720 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19721 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19722 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19724 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19725 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19726 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19727 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19729 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19730 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19732 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19733 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19734 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19735 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19738 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19739 #undef THUMB_VARIANT
19740 #define THUMB_VARIANT & arm_ext_v6t2
19742 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19743 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19745 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19746 ADDRGLDRS
), ldrd
, t_ldstd
),
19748 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19749 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19752 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19754 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19757 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19758 #undef THUMB_VARIANT
19759 #define THUMB_VARIANT & arm_ext_v6
19761 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19762 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19763 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19764 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19765 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19766 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19767 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19768 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19769 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19770 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19772 #undef THUMB_VARIANT
19773 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19775 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19776 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19778 #undef THUMB_VARIANT
19779 #define THUMB_VARIANT & arm_ext_v6t2
19781 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19782 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19784 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19785 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19787 /* ARM V6 not included in V7M. */
19788 #undef THUMB_VARIANT
19789 #define THUMB_VARIANT & arm_ext_v6_notm
19790 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19791 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19792 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19793 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19794 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19795 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19796 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19797 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19798 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19799 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19800 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19801 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19802 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19803 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19804 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19805 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19806 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19807 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19808 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19810 /* ARM V6 not included in V7M (eg. integer SIMD). */
19811 #undef THUMB_VARIANT
19812 #define THUMB_VARIANT & arm_ext_v6_dsp
19813 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19814 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19815 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19816 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19817 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19818 /* Old name for QASX. */
19819 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19820 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19821 /* Old name for QSAX. */
19822 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19823 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19824 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19825 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19826 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19827 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19828 /* Old name for SASX. */
19829 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19830 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19831 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19832 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19833 /* Old name for SHASX. */
19834 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19835 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19836 /* Old name for SHSAX. */
19837 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19838 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19839 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19840 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19841 /* Old name for SSAX. */
19842 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19843 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19844 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19845 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19846 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19847 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19848 /* Old name for UASX. */
19849 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19850 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19851 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19852 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19853 /* Old name for UHASX. */
19854 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19855 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19856 /* Old name for UHSAX. */
19857 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19858 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19859 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19860 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19861 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19862 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19863 /* Old name for UQASX. */
19864 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19865 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19866 /* Old name for UQSAX. */
19867 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19868 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19869 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19870 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19871 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19872 /* Old name for USAX. */
19873 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19874 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19875 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19876 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19877 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19878 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19879 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19880 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19881 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19882 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19883 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19884 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19885 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19886 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19887 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19888 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19889 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19890 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19891 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19892 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19893 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19894 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19895 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19896 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19897 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19898 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19899 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19900 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19901 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19902 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19903 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19904 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19905 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19906 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19909 #define ARM_VARIANT & arm_ext_v6k
19910 #undef THUMB_VARIANT
19911 #define THUMB_VARIANT & arm_ext_v6k
19913 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19914 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19915 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19916 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19918 #undef THUMB_VARIANT
19919 #define THUMB_VARIANT & arm_ext_v6_notm
19920 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19922 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19923 RRnpcb
), strexd
, t_strexd
),
19925 #undef THUMB_VARIANT
19926 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19927 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19929 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19931 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19933 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19935 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19938 #define ARM_VARIANT & arm_ext_sec
19939 #undef THUMB_VARIANT
19940 #define THUMB_VARIANT & arm_ext_sec
19942 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19945 #define ARM_VARIANT & arm_ext_virt
19946 #undef THUMB_VARIANT
19947 #define THUMB_VARIANT & arm_ext_virt
19949 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19950 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19953 #define ARM_VARIANT & arm_ext_pan
19954 #undef THUMB_VARIANT
19955 #define THUMB_VARIANT & arm_ext_pan
19957 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19960 #define ARM_VARIANT & arm_ext_v6t2
19961 #undef THUMB_VARIANT
19962 #define THUMB_VARIANT & arm_ext_v6t2
19964 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19965 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19966 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19967 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19969 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19970 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19972 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19973 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19974 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19975 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19977 #undef THUMB_VARIANT
19978 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19979 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19980 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19982 /* Thumb-only instructions. */
19984 #define ARM_VARIANT NULL
19985 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19986 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19988 /* ARM does not really have an IT instruction, so always allow it.
19989 The opcode is copied from Thumb in order to allow warnings in
19990 -mimplicit-it=[never | arm] modes. */
19992 #define ARM_VARIANT & arm_ext_v1
19993 #undef THUMB_VARIANT
19994 #define THUMB_VARIANT & arm_ext_v6t2
19996 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19997 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19998 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19999 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
20000 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
20001 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
20002 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
20003 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
20004 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
20005 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
20006 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
20007 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
20008 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
20009 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
20010 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
20011 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
20012 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20013 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20015 /* Thumb2 only instructions. */
20017 #define ARM_VARIANT NULL
20019 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20020 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20021 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20022 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20023 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
20024 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
20026 /* Hardware division instructions. */
20028 #define ARM_VARIANT & arm_ext_adiv
20029 #undef THUMB_VARIANT
20030 #define THUMB_VARIANT & arm_ext_div
20032 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20033 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20035 /* ARM V6M/V7 instructions. */
20037 #define ARM_VARIANT & arm_ext_barrier
20038 #undef THUMB_VARIANT
20039 #define THUMB_VARIANT & arm_ext_barrier
20041 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
20042 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
20043 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
20045 /* ARM V7 instructions. */
20047 #define ARM_VARIANT & arm_ext_v7
20048 #undef THUMB_VARIANT
20049 #define THUMB_VARIANT & arm_ext_v7
20051 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
20052 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
20055 #define ARM_VARIANT & arm_ext_mp
20056 #undef THUMB_VARIANT
20057 #define THUMB_VARIANT & arm_ext_mp
20059 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
20061 /* AArchv8 instructions. */
20063 #define ARM_VARIANT & arm_ext_v8
20065 /* Instructions shared between armv8-a and armv8-m. */
20066 #undef THUMB_VARIANT
20067 #define THUMB_VARIANT & arm_ext_atomics
20069 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20070 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20071 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20072 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20073 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20074 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20075 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20076 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
20077 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20078 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20080 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20082 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20084 #undef THUMB_VARIANT
20085 #define THUMB_VARIANT & arm_ext_v8
20087 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
20088 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
20089 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
20091 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
20093 /* ARMv8 T32 only. */
20095 #define ARM_VARIANT NULL
20096 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
20097 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
20098 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
20100 /* FP for ARMv8. */
20102 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
20103 #undef THUMB_VARIANT
20104 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
20106 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20107 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20108 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20109 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20110 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20111 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20112 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
20113 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
20114 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
20115 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
20116 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
20117 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
20118 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
20119 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
20120 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
20121 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
20122 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
20124 /* Crypto v1 extensions. */
20126 #define ARM_VARIANT & fpu_crypto_ext_armv8
20127 #undef THUMB_VARIANT
20128 #define THUMB_VARIANT & fpu_crypto_ext_armv8
20130 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
20131 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
20132 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
20133 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
20134 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
20135 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
20136 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
20137 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
20138 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
20139 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
20140 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
20141 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
20142 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
20143 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
20146 #define ARM_VARIANT & crc_ext_armv8
20147 #undef THUMB_VARIANT
20148 #define THUMB_VARIANT & crc_ext_armv8
20149 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
20150 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
20151 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
20152 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
20153 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
20154 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
20156 /* ARMv8.2 RAS extension. */
20158 #define ARM_VARIANT & arm_ext_ras
20159 #undef THUMB_VARIANT
20160 #define THUMB_VARIANT & arm_ext_ras
20161 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
20164 #define ARM_VARIANT & arm_ext_v8_3
20165 #undef THUMB_VARIANT
20166 #define THUMB_VARIANT & arm_ext_v8_3
20167 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
20168 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
20169 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
20172 #define ARM_VARIANT & fpu_neon_ext_dotprod
20173 #undef THUMB_VARIANT
20174 #define THUMB_VARIANT & fpu_neon_ext_dotprod
20175 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
20176 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
20179 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
20180 #undef THUMB_VARIANT
20181 #define THUMB_VARIANT NULL
20183 cCE("wfs", e200110
, 1, (RR
), rd
),
20184 cCE("rfs", e300110
, 1, (RR
), rd
),
20185 cCE("wfc", e400110
, 1, (RR
), rd
),
20186 cCE("rfc", e500110
, 1, (RR
), rd
),
20188 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20189 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20190 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20191 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20193 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20194 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20195 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20196 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20198 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
20199 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
20200 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
20201 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
20202 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
20203 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
20204 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
20205 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
20206 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
20207 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
20208 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
20209 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
20211 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
20212 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
20213 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
20214 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
20215 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
20216 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
20217 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
20218 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
20219 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
20220 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
20221 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
20222 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
20224 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
20225 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
20226 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
20227 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
20228 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
20229 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
20230 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
20231 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
20232 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
20233 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
20234 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
20235 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
20237 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
20238 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
20239 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
20240 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
20241 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
20242 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
20243 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
20244 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
20245 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
20246 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
20247 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
20248 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
20250 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
20251 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
20252 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
20253 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
20254 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
20255 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
20256 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
20257 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
20258 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
20259 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
20260 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
20261 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
20263 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
20264 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
20265 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
20266 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
20267 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
20268 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
20269 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
20270 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
20271 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
20272 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
20273 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
20274 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
20276 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
20277 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
20278 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
20279 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
20280 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
20281 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
20282 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
20283 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
20284 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
20285 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
20286 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
20287 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
20289 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
20290 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
20291 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
20292 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
20293 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
20294 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
20295 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
20296 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
20297 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
20298 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
20299 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
20300 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
20302 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
20303 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
20304 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
20305 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
20306 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
20307 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
20308 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
20309 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
20310 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
20311 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
20312 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
20313 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
20315 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
20316 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
20317 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
20318 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
20319 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
20320 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
20321 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
20322 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
20323 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
20324 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
20325 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
20326 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
20328 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
20329 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
20330 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
20331 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
20332 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
20333 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
20334 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
20335 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
20336 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
20337 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
20338 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
20339 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
20341 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
20342 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
20343 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
20344 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
20345 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
20346 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
20347 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
20348 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
20349 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
20350 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
20351 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
20352 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
20354 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
20355 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
20356 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
20357 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
20358 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
20359 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
20360 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
20361 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
20362 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
20363 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
20364 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
20365 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
20367 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
20368 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
20369 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
20370 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
20371 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
20372 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
20373 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
20374 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
20375 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
20376 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
20377 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
20378 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
20380 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
20381 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
20382 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
20383 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
20384 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
20385 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
20386 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
20387 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
20388 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
20389 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
20390 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
20391 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
20393 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
20394 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
20395 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
20396 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
20397 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
20398 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
20399 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
20400 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
20401 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
20402 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
20403 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
20404 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
20406 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20407 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20408 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20409 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20410 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20411 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20412 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20413 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20414 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20415 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20416 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20417 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20419 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20420 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20421 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20422 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20423 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20424 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20425 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20426 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20427 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20428 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20429 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20430 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20432 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20433 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20434 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20435 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20436 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20437 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20438 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20439 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20440 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20441 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20442 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20443 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20445 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20446 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20447 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20448 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20449 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20450 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20451 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20452 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20453 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20454 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20455 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20456 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20458 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20459 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20460 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20461 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20462 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20463 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20464 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20465 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20466 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20467 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20468 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20469 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20471 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20472 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20473 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20474 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20475 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20476 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20477 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20478 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20479 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20480 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20481 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20482 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20484 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20485 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20486 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20487 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20488 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20489 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20490 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20491 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20492 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20493 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20494 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20495 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20497 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20498 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20499 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20500 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20501 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20502 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20503 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20504 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20505 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20506 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20507 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20508 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20510 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20511 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20512 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20513 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20514 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20515 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20516 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20517 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20518 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20519 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20520 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20521 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20523 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20524 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20525 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20526 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20527 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20528 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20529 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20530 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20531 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20532 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20533 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20534 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20536 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20537 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20538 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20539 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20540 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20541 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20542 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20543 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20544 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20545 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20546 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20547 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20549 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20550 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20551 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20552 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20553 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20554 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20555 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20556 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20557 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20558 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20559 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20560 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20562 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20563 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20564 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20565 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20566 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20567 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20568 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20569 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20570 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20571 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20572 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20573 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20575 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20576 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20577 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20578 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20580 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20581 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20582 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20583 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20584 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20585 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20586 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20587 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20588 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20589 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20590 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20591 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20593 /* The implementation of the FIX instruction is broken on some
20594 assemblers, in that it accepts a precision specifier as well as a
20595 rounding specifier, despite the fact that this is meaningless.
20596 To be more compatible, we accept it as well, though of course it
20597 does not set any bits. */
20598 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20599 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20600 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20601 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20602 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20603 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20604 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20605 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20606 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20607 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20608 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20609 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20610 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20612 /* Instructions that were new with the real FPA, call them V2. */
20614 #define ARM_VARIANT & fpu_fpa_ext_v2
20616 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20617 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20618 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20619 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20620 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20621 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20624 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20626 /* Moves and type conversions. */
20627 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20628 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20629 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20630 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20631 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20632 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20633 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20634 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20635 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20636 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20637 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20638 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20639 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20640 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20642 /* Memory operations. */
20643 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20644 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20645 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20646 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20647 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20648 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20649 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20650 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20651 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20652 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20653 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20654 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20655 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20656 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20657 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20658 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20659 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20660 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20662 /* Monadic operations. */
20663 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20664 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20665 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20667 /* Dyadic operations. */
20668 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20669 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20670 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20671 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20672 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20673 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20674 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20675 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20676 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20679 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20680 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20681 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20682 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20684 /* Double precision load/store are still present on single precision
20685 implementations. */
20686 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20687 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20688 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20689 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20690 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20691 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20692 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20693 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20694 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20695 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20698 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20700 /* Moves and type conversions. */
20701 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20702 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20703 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20704 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20705 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20706 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20707 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20708 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20709 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20710 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20711 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20712 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20713 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20715 /* Monadic operations. */
20716 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20717 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20718 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20720 /* Dyadic operations. */
20721 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20722 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20723 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20724 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20725 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20726 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20727 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20728 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20729 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20732 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20733 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20734 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20735 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20738 #define ARM_VARIANT & fpu_vfp_ext_v2
20740 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20741 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20742 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20743 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20745 /* Instructions which may belong to either the Neon or VFP instruction sets.
20746 Individual encoder functions perform additional architecture checks. */
20748 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20749 #undef THUMB_VARIANT
20750 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20752 /* These mnemonics are unique to VFP. */
20753 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20754 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20755 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20756 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20757 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20758 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20759 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20760 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20761 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20762 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20764 /* Mnemonics shared by Neon and VFP. */
20765 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20766 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20767 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20769 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20770 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20772 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20773 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20775 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20776 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20777 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20778 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20779 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20780 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20781 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20782 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20784 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20785 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20786 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20787 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20790 /* NOTE: All VMOV encoding is special-cased! */
20791 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20792 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20795 #define ARM_VARIANT & arm_ext_fp16
20796 #undef THUMB_VARIANT
20797 #define THUMB_VARIANT & arm_ext_fp16
20798 /* New instructions added from v8.2, allowing the extraction and insertion of
20799 the upper 16 bits of a 32-bit vector register. */
20800 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20801 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20803 /* New backported fma/fms instructions optional in v8.2. */
20804 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
20805 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
20807 #undef THUMB_VARIANT
20808 #define THUMB_VARIANT & fpu_neon_ext_v1
20810 #define ARM_VARIANT & fpu_neon_ext_v1
20812 /* Data processing with three registers of the same length. */
20813 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20814 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20815 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20816 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20817 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20818 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20819 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20820 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20821 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20822 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20823 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20824 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20825 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20826 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20827 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20828 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20829 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20830 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20831 /* If not immediate, fall back to neon_dyadic_i64_su.
20832 shl_imm should accept I8 I16 I32 I64,
20833 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20834 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20835 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20836 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20837 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20838 /* Logic ops, types optional & ignored. */
20839 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20840 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20841 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20842 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20843 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20844 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20845 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20846 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20847 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20848 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20849 /* Bitfield ops, untyped. */
20850 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20851 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20852 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20853 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20854 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20855 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20856 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20857 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20858 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20859 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20860 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20861 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20862 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20863 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20864 back to neon_dyadic_if_su. */
20865 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20866 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20867 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20868 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20869 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20870 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20871 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20872 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20873 /* Comparison. Type I8 I16 I32 F32. */
20874 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20875 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20876 /* As above, D registers only. */
20877 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20878 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20879 /* Int and float variants, signedness unimportant. */
20880 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20881 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20882 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20883 /* Add/sub take types I8 I16 I32 I64 F32. */
20884 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20885 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20886 /* vtst takes sizes 8, 16, 32. */
20887 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20888 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20889 /* VMUL takes I8 I16 I32 F32 P8. */
20890 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20891 /* VQD{R}MULH takes S16 S32. */
20892 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20893 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20894 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20895 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20896 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20897 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20898 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20899 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20900 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20901 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20902 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20903 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20904 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20905 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20906 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20907 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20908 /* ARM v8.1 extension. */
20909 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20910 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20911 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20912 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20914 /* Two address, int/float. Types S8 S16 S32 F32. */
20915 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20916 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20918 /* Data processing with two registers and a shift amount. */
20919 /* Right shifts, and variants with rounding.
20920 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20921 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20922 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20923 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20924 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20925 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20926 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20927 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20928 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20929 /* Shift and insert. Sizes accepted 8 16 32 64. */
20930 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20931 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20932 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20933 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20934 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20935 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20936 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20937 /* Right shift immediate, saturating & narrowing, with rounding variants.
20938 Types accepted S16 S32 S64 U16 U32 U64. */
20939 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20940 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20941 /* As above, unsigned. Types accepted S16 S32 S64. */
20942 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20943 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20944 /* Right shift narrowing. Types accepted I16 I32 I64. */
20945 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20946 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20947 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20948 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20949 /* CVT with optional immediate for fixed-point variant. */
20950 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20952 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20953 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20955 /* Data processing, three registers of different lengths. */
20956 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20957 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20958 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20959 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20960 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20961 /* If not scalar, fall back to neon_dyadic_long.
20962 Vector types as above, scalar types S16 S32 U16 U32. */
20963 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20964 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20965 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20966 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20967 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20968 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20969 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20970 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20971 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20972 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20973 /* Saturating doubling multiplies. Types S16 S32. */
20974 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20975 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20976 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20977 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20978 S16 S32 U16 U32. */
20979 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20981 /* Extract. Size 8. */
20982 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20983 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20985 /* Two registers, miscellaneous. */
20986 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20987 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20988 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20989 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20990 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20991 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20992 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20993 /* Vector replicate. Sizes 8 16 32. */
20994 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20995 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20996 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20997 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20998 /* VMOVN. Types I16 I32 I64. */
20999 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
21000 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
21001 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
21002 /* VQMOVUN. Types S16 S32 S64. */
21003 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
21004 /* VZIP / VUZP. Sizes 8 16 32. */
21005 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21006 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21007 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21008 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21009 /* VQABS / VQNEG. Types S8 S16 S32. */
21010 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21011 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21012 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21013 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21014 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
21015 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21016 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
21017 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21018 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
21019 /* Reciprocal estimates. Types U32 F16 F32. */
21020 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21021 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
21022 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21023 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
21024 /* VCLS. Types S8 S16 S32. */
21025 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
21026 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
21027 /* VCLZ. Types I8 I16 I32. */
21028 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
21029 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
21030 /* VCNT. Size 8. */
21031 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
21032 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
21033 /* Two address, untyped. */
21034 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
21035 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
21036 /* VTRN. Sizes 8 16 32. */
21037 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
21038 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
21040 /* Table lookup. Size 8. */
21041 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21042 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21044 #undef THUMB_VARIANT
21045 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
21047 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
21049 /* Neon element/structure load/store. */
21050 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21051 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21052 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21053 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21054 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21055 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21056 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21057 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21059 #undef THUMB_VARIANT
21060 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
21062 #define ARM_VARIANT & fpu_vfp_ext_v3xd
21063 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
21064 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21065 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21066 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21067 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21068 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21069 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21070 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21071 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21073 #undef THUMB_VARIANT
21074 #define THUMB_VARIANT & fpu_vfp_ext_v3
21076 #define ARM_VARIANT & fpu_vfp_ext_v3
21078 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
21079 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21080 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21081 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21082 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21083 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21084 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21085 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21086 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21089 #define ARM_VARIANT & fpu_vfp_ext_fma
21090 #undef THUMB_VARIANT
21091 #define THUMB_VARIANT & fpu_vfp_ext_fma
21092 /* Mnemonics shared by Neon and VFP. These are included in the
21093 VFP FMA variant; NEON and VFP FMA always includes the NEON
21094 FMA instructions. */
21095 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21096 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21097 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
21098 the v form should always be used. */
21099 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21100 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21101 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21102 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21103 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21104 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21106 #undef THUMB_VARIANT
21108 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
21110 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21111 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21112 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21113 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21114 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21115 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21116 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
21117 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
21120 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
21122 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
21123 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
21124 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
21125 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
21126 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
21127 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
21128 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
21129 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
21130 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
21131 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21132 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21133 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21134 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21135 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21136 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21137 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21138 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21139 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21140 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
21141 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
21142 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21143 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21144 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21145 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21146 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21147 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21148 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
21149 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
21150 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
21151 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
21152 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
21153 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
21154 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
21155 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
21156 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21157 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21158 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21159 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21160 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21161 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21162 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21163 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21164 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21165 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21166 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21167 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21168 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
21169 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21170 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21171 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21172 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21173 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21174 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21175 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21176 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21177 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21178 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21179 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21180 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21181 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21182 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21183 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21184 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21185 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21186 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21187 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21188 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21189 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21190 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21191 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21192 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21193 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21194 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21195 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21196 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21197 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21198 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21199 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21200 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21201 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21202 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21203 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21204 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21205 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21206 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21207 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21208 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21209 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21210 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
21211 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21212 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21213 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21214 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21215 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21216 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21217 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21218 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21219 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21220 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21221 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21222 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21223 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21224 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21225 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21226 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21227 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21228 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21229 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21230 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21231 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21232 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
21233 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21234 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21235 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21236 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21237 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21238 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21239 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21240 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21241 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21242 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21243 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21244 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21245 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21246 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21247 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21248 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21249 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21250 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21251 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21252 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21253 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21254 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21255 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21256 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21257 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21258 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21259 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21260 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21261 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21262 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21263 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21264 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21265 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21266 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21267 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21268 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21269 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21270 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21271 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21272 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21273 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21274 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21275 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21276 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21277 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21278 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21279 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21280 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21281 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21282 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21283 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
21286 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
21288 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
21289 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
21290 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
21291 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21292 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21293 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21294 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21295 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21296 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21297 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21298 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21299 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21300 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21301 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21302 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21303 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21304 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21305 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21306 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21307 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21308 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
21309 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21310 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21311 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21312 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21313 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21314 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21315 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21316 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21317 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21318 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21319 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21320 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21321 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21322 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21323 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21324 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21325 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21326 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21327 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21328 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21329 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21330 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21331 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21332 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21333 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21334 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21335 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21336 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21337 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21338 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21339 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21340 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21341 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21342 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21343 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21344 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21347 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
21349 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21350 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21351 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21352 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21353 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21354 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21355 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21356 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21357 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
21358 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
21359 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
21360 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
21361 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
21362 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
21363 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
21364 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
21365 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
21366 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
21367 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
21368 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
21369 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
21370 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
21371 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
21372 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
21373 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
21374 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
21375 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
21376 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
21377 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
21378 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
21379 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
21380 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
21381 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
21382 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
21383 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
21384 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
21385 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
21386 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
21387 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
21388 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
21389 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
21390 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
21391 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
21392 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
21393 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
21394 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
21395 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
21396 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
21397 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
21398 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
21399 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
21400 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
21401 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
21402 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
21403 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21404 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21405 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21406 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21407 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21408 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21409 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
21410 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
21411 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
21412 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
21413 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21414 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21415 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21416 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21417 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21418 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21419 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21420 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21421 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21422 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21423 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21424 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21426 /* ARMv8-M instructions. */
21428 #define ARM_VARIANT NULL
21429 #undef THUMB_VARIANT
21430 #define THUMB_VARIANT & arm_ext_v8m
21431 TUE("sg", 0, e97fe97f
, 0, (), 0, noargs
),
21432 TUE("blxns", 0, 4784, 1, (RRnpc
), 0, t_blx
),
21433 TUE("bxns", 0, 4704, 1, (RRnpc
), 0, t_bx
),
21434 TUE("tt", 0, e840f000
, 2, (RRnpc
, RRnpc
), 0, tt
),
21435 TUE("ttt", 0, e840f040
, 2, (RRnpc
, RRnpc
), 0, tt
),
21436 TUE("tta", 0, e840f080
, 2, (RRnpc
, RRnpc
), 0, tt
),
21437 TUE("ttat", 0, e840f0c0
, 2, (RRnpc
, RRnpc
), 0, tt
),
21439 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21440 instructions behave as nop if no VFP is present. */
21441 #undef THUMB_VARIANT
21442 #define THUMB_VARIANT & arm_ext_v8m_main
21443 TUEc("vlldm", 0, ec300a00
, 1, (RRnpc
), rn
),
21444 TUEc("vlstm", 0, ec200a00
, 1, (RRnpc
), rn
),
21447 #undef THUMB_VARIANT
21473 /* MD interface: bits in the object file. */
21475 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21476 for use in the a.out file, and stores them in the array pointed to by buf.
21477 This knows about the endian-ness of the target machine and does
21478 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21479 2 (short) and 4 (long) Floating numbers are put out as a series of
21480 LITTLENUMS (shorts, here at least). */
21483 md_number_to_chars (char * buf
, valueT val
, int n
)
21485 if (target_big_endian
)
21486 number_to_chars_bigendian (buf
, val
, n
);
21488 number_to_chars_littleendian (buf
, val
, n
);
21492 md_chars_to_number (char * buf
, int n
)
21495 unsigned char * where
= (unsigned char *) buf
;
21497 if (target_big_endian
)
21502 result
|= (*where
++ & 255);
21510 result
|= (where
[n
] & 255);
21517 /* MD interface: Sections. */
21519 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21520 that an rs_machine_dependent frag may reach. */
21523 arm_frag_max_var (fragS
*fragp
)
21525 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21526 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21528 Note that we generate relaxable instructions even for cases that don't
21529 really need it, like an immediate that's a trivial constant. So we're
21530 overestimating the instruction size for some of those cases. Rather
21531 than putting more intelligence here, it would probably be better to
21532 avoid generating a relaxation frag in the first place when it can be
21533 determined up front that a short instruction will suffice. */
21535 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21539 /* Estimate the size of a frag before relaxing. Assume everything fits in
21543 md_estimate_size_before_relax (fragS
* fragp
,
21544 segT segtype ATTRIBUTE_UNUSED
)
21550 /* Convert a machine dependent frag. */
21553 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21555 unsigned long insn
;
21556 unsigned long old_op
;
21564 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21566 old_op
= bfd_get_16(abfd
, buf
);
21567 if (fragp
->fr_symbol
)
21569 exp
.X_op
= O_symbol
;
21570 exp
.X_add_symbol
= fragp
->fr_symbol
;
21574 exp
.X_op
= O_constant
;
21576 exp
.X_add_number
= fragp
->fr_offset
;
21577 opcode
= fragp
->fr_subtype
;
21580 case T_MNEM_ldr_pc
:
21581 case T_MNEM_ldr_pc2
:
21582 case T_MNEM_ldr_sp
:
21583 case T_MNEM_str_sp
:
21590 if (fragp
->fr_var
== 4)
21592 insn
= THUMB_OP32 (opcode
);
21593 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21595 insn
|= (old_op
& 0x700) << 4;
21599 insn
|= (old_op
& 7) << 12;
21600 insn
|= (old_op
& 0x38) << 13;
21602 insn
|= 0x00000c00;
21603 put_thumb32_insn (buf
, insn
);
21604 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21608 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21610 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21613 if (fragp
->fr_var
== 4)
21615 insn
= THUMB_OP32 (opcode
);
21616 insn
|= (old_op
& 0xf0) << 4;
21617 put_thumb32_insn (buf
, insn
);
21618 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21622 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21623 exp
.X_add_number
-= 4;
21631 if (fragp
->fr_var
== 4)
21633 int r0off
= (opcode
== T_MNEM_mov
21634 || opcode
== T_MNEM_movs
) ? 0 : 8;
21635 insn
= THUMB_OP32 (opcode
);
21636 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21637 insn
|= (old_op
& 0x700) << r0off
;
21638 put_thumb32_insn (buf
, insn
);
21639 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21643 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21648 if (fragp
->fr_var
== 4)
21650 insn
= THUMB_OP32(opcode
);
21651 put_thumb32_insn (buf
, insn
);
21652 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21655 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21659 if (fragp
->fr_var
== 4)
21661 insn
= THUMB_OP32(opcode
);
21662 insn
|= (old_op
& 0xf00) << 14;
21663 put_thumb32_insn (buf
, insn
);
21664 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21667 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21670 case T_MNEM_add_sp
:
21671 case T_MNEM_add_pc
:
21672 case T_MNEM_inc_sp
:
21673 case T_MNEM_dec_sp
:
21674 if (fragp
->fr_var
== 4)
21676 /* ??? Choose between add and addw. */
21677 insn
= THUMB_OP32 (opcode
);
21678 insn
|= (old_op
& 0xf0) << 4;
21679 put_thumb32_insn (buf
, insn
);
21680 if (opcode
== T_MNEM_add_pc
)
21681 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21683 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21686 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21694 if (fragp
->fr_var
== 4)
21696 insn
= THUMB_OP32 (opcode
);
21697 insn
|= (old_op
& 0xf0) << 4;
21698 insn
|= (old_op
& 0xf) << 16;
21699 put_thumb32_insn (buf
, insn
);
21700 if (insn
& (1 << 20))
21701 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21703 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21706 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21712 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21713 (enum bfd_reloc_code_real
) reloc_type
);
21714 fixp
->fx_file
= fragp
->fr_file
;
21715 fixp
->fx_line
= fragp
->fr_line
;
21716 fragp
->fr_fix
+= fragp
->fr_var
;
21718 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21719 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21720 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21721 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21724 /* Return the size of a relaxable immediate operand instruction.
21725 SHIFT and SIZE specify the form of the allowable immediate. */
21727 relax_immediate (fragS
*fragp
, int size
, int shift
)
21733 /* ??? Should be able to do better than this. */
21734 if (fragp
->fr_symbol
)
21737 low
= (1 << shift
) - 1;
21738 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21739 offset
= fragp
->fr_offset
;
21740 /* Force misaligned offsets to 32-bit variant. */
21743 if (offset
& ~mask
)
21748 /* Get the address of a symbol during relaxation. */
21750 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21756 sym
= fragp
->fr_symbol
;
21757 sym_frag
= symbol_get_frag (sym
);
21758 know (S_GET_SEGMENT (sym
) != absolute_section
21759 || sym_frag
== &zero_address_frag
);
21760 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21762 /* If frag has yet to be reached on this pass, assume it will
21763 move by STRETCH just as we did. If this is not so, it will
21764 be because some frag between grows, and that will force
21768 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21772 /* Adjust stretch for any alignment frag. Note that if have
21773 been expanding the earlier code, the symbol may be
21774 defined in what appears to be an earlier frag. FIXME:
21775 This doesn't handle the fr_subtype field, which specifies
21776 a maximum number of bytes to skip when doing an
21778 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21780 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21783 stretch
= - ((- stretch
)
21784 & ~ ((1 << (int) f
->fr_offset
) - 1));
21786 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21798 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21801 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21806 /* Assume worst case for symbols not known to be in the same section. */
21807 if (fragp
->fr_symbol
== NULL
21808 || !S_IS_DEFINED (fragp
->fr_symbol
)
21809 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21810 || S_IS_WEAK (fragp
->fr_symbol
))
21813 val
= relaxed_symbol_addr (fragp
, stretch
);
21814 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21815 addr
= (addr
+ 4) & ~3;
21816 /* Force misaligned targets to 32-bit variant. */
21820 if (val
< 0 || val
> 1020)
21825 /* Return the size of a relaxable add/sub immediate instruction. */
21827 relax_addsub (fragS
*fragp
, asection
*sec
)
21832 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21833 op
= bfd_get_16(sec
->owner
, buf
);
21834 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21835 return relax_immediate (fragp
, 8, 0);
21837 return relax_immediate (fragp
, 3, 0);
21840 /* Return TRUE iff the definition of symbol S could be pre-empted
21841 (overridden) at link or load time. */
21843 symbol_preemptible (symbolS
*s
)
21845 /* Weak symbols can always be pre-empted. */
21849 /* Non-global symbols cannot be pre-empted. */
21850 if (! S_IS_EXTERNAL (s
))
21854 /* In ELF, a global symbol can be marked protected, or private. In that
21855 case it can't be pre-empted (other definitions in the same link unit
21856 would violate the ODR). */
21857 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21861 /* Other global symbols might be pre-empted. */
21865 /* Return the size of a relaxable branch instruction. BITS is the
21866 size of the offset field in the narrow instruction. */
21869 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21875 /* Assume worst case for symbols not known to be in the same section. */
21876 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21877 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21878 || S_IS_WEAK (fragp
->fr_symbol
))
21882 /* A branch to a function in ARM state will require interworking. */
21883 if (S_IS_DEFINED (fragp
->fr_symbol
)
21884 && ARM_IS_FUNC (fragp
->fr_symbol
))
21888 if (symbol_preemptible (fragp
->fr_symbol
))
21891 val
= relaxed_symbol_addr (fragp
, stretch
);
21892 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21895 /* Offset is a signed value *2 */
21897 if (val
>= limit
|| val
< -limit
)
21903 /* Relax a machine dependent frag. This returns the amount by which
21904 the current size of the frag should change. */
21907 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21912 oldsize
= fragp
->fr_var
;
21913 switch (fragp
->fr_subtype
)
21915 case T_MNEM_ldr_pc2
:
21916 newsize
= relax_adr (fragp
, sec
, stretch
);
21918 case T_MNEM_ldr_pc
:
21919 case T_MNEM_ldr_sp
:
21920 case T_MNEM_str_sp
:
21921 newsize
= relax_immediate (fragp
, 8, 2);
21925 newsize
= relax_immediate (fragp
, 5, 2);
21929 newsize
= relax_immediate (fragp
, 5, 1);
21933 newsize
= relax_immediate (fragp
, 5, 0);
21936 newsize
= relax_adr (fragp
, sec
, stretch
);
21942 newsize
= relax_immediate (fragp
, 8, 0);
21945 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21948 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21950 case T_MNEM_add_sp
:
21951 case T_MNEM_add_pc
:
21952 newsize
= relax_immediate (fragp
, 8, 2);
21954 case T_MNEM_inc_sp
:
21955 case T_MNEM_dec_sp
:
21956 newsize
= relax_immediate (fragp
, 7, 2);
21962 newsize
= relax_addsub (fragp
, sec
);
21968 fragp
->fr_var
= newsize
;
21969 /* Freeze wide instructions that are at or before the same location as
21970 in the previous pass. This avoids infinite loops.
21971 Don't freeze them unconditionally because targets may be artificially
21972 misaligned by the expansion of preceding frags. */
21973 if (stretch
<= 0 && newsize
> 2)
21975 md_convert_frag (sec
->owner
, sec
, fragp
);
21979 return newsize
- oldsize
;
21982 /* Round up a section size to the appropriate boundary. */
21985 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21988 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21989 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21991 /* For a.out, force the section size to be aligned. If we don't do
21992 this, BFD will align it for us, but it will not write out the
21993 final bytes of the section. This may be a bug in BFD, but it is
21994 easier to fix it here since that is how the other a.out targets
21998 align
= bfd_get_section_alignment (stdoutput
, segment
);
21999 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
22006 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
22007 of an rs_align_code fragment. */
22010 arm_handle_align (fragS
* fragP
)
22012 static unsigned char const arm_noop
[2][2][4] =
22015 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
22016 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
22019 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
22020 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
22023 static unsigned char const thumb_noop
[2][2][2] =
22026 {0xc0, 0x46}, /* LE */
22027 {0x46, 0xc0}, /* BE */
22030 {0x00, 0xbf}, /* LE */
22031 {0xbf, 0x00} /* BE */
22034 static unsigned char const wide_thumb_noop
[2][4] =
22035 { /* Wide Thumb-2 */
22036 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
22037 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
22040 unsigned bytes
, fix
, noop_size
;
22042 const unsigned char * noop
;
22043 const unsigned char *narrow_noop
= NULL
;
22048 if (fragP
->fr_type
!= rs_align_code
)
22051 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
22052 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
22055 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22056 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
22058 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
22060 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
22062 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22063 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
22065 narrow_noop
= thumb_noop
[1][target_big_endian
];
22066 noop
= wide_thumb_noop
[target_big_endian
];
22069 noop
= thumb_noop
[0][target_big_endian
];
22077 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22078 ? selected_cpu
: arm_arch_none
,
22080 [target_big_endian
];
22087 fragP
->fr_var
= noop_size
;
22089 if (bytes
& (noop_size
- 1))
22091 fix
= bytes
& (noop_size
- 1);
22093 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
22095 memset (p
, 0, fix
);
22102 if (bytes
& noop_size
)
22104 /* Insert a narrow noop. */
22105 memcpy (p
, narrow_noop
, noop_size
);
22107 bytes
-= noop_size
;
22111 /* Use wide noops for the remainder */
22115 while (bytes
>= noop_size
)
22117 memcpy (p
, noop
, noop_size
);
22119 bytes
-= noop_size
;
22123 fragP
->fr_fix
+= fix
;
22126 /* Called from md_do_align. Used to create an alignment
22127 frag in a code section. */
22130 arm_frag_align_code (int n
, int max
)
22134 /* We assume that there will never be a requirement
22135 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
22136 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22141 _("alignments greater than %d bytes not supported in .text sections."),
22142 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
22143 as_fatal ("%s", err_msg
);
22146 p
= frag_var (rs_align_code
,
22147 MAX_MEM_FOR_RS_ALIGN_CODE
,
22149 (relax_substateT
) max
,
22156 /* Perform target specific initialisation of a frag.
22157 Note - despite the name this initialisation is not done when the frag
22158 is created, but only when its type is assigned. A frag can be created
22159 and used a long time before its type is set, so beware of assuming that
22160 this initialisation is performed first. */
22164 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
22166 /* Record whether this frag is in an ARM or a THUMB area. */
22167 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22170 #else /* OBJ_ELF is defined. */
22172 arm_init_frag (fragS
* fragP
, int max_chars
)
22174 bfd_boolean frag_thumb_mode
;
22176 /* If the current ARM vs THUMB mode has not already
22177 been recorded into this frag then do so now. */
22178 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
22179 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22181 /* PR 21809: Do not set a mapping state for debug sections
22182 - it just confuses other tools. */
22183 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
22186 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
22188 /* Record a mapping symbol for alignment frags. We will delete this
22189 later if the alignment ends up empty. */
22190 switch (fragP
->fr_type
)
22193 case rs_align_test
:
22195 mapping_state_2 (MAP_DATA
, max_chars
);
22197 case rs_align_code
:
22198 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
22205 /* When we change sections we need to issue a new mapping symbol. */
22208 arm_elf_change_section (void)
22210 /* Link an unlinked unwind index table section to the .text section. */
22211 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
22212 && elf_linked_to_section (now_seg
) == NULL
)
22213 elf_linked_to_section (now_seg
) = text_section
;
22217 arm_elf_section_type (const char * str
, size_t len
)
22219 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
22220 return SHT_ARM_EXIDX
;
22225 /* Code to deal with unwinding tables. */
22227 static void add_unwind_adjustsp (offsetT
);
22229 /* Generate any deferred unwind frame offset. */
22232 flush_pending_unwind (void)
22236 offset
= unwind
.pending_offset
;
22237 unwind
.pending_offset
= 0;
22239 add_unwind_adjustsp (offset
);
22242 /* Add an opcode to this list for this function. Two-byte opcodes should
22243 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
22247 add_unwind_opcode (valueT op
, int length
)
22249 /* Add any deferred stack adjustment. */
22250 if (unwind
.pending_offset
)
22251 flush_pending_unwind ();
22253 unwind
.sp_restored
= 0;
22255 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
22257 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
22258 if (unwind
.opcodes
)
22259 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
22260 unwind
.opcode_alloc
);
22262 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
22267 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
22269 unwind
.opcode_count
++;
22273 /* Add unwind opcodes to adjust the stack pointer. */
22276 add_unwind_adjustsp (offsetT offset
)
22280 if (offset
> 0x200)
22282 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
22287 /* Long form: 0xb2, uleb128. */
22288 /* This might not fit in a word so add the individual bytes,
22289 remembering the list is built in reverse order. */
22290 o
= (valueT
) ((offset
- 0x204) >> 2);
22292 add_unwind_opcode (0, 1);
22294 /* Calculate the uleb128 encoding of the offset. */
22298 bytes
[n
] = o
& 0x7f;
22304 /* Add the insn. */
22306 add_unwind_opcode (bytes
[n
- 1], 1);
22307 add_unwind_opcode (0xb2, 1);
22309 else if (offset
> 0x100)
22311 /* Two short opcodes. */
22312 add_unwind_opcode (0x3f, 1);
22313 op
= (offset
- 0x104) >> 2;
22314 add_unwind_opcode (op
, 1);
22316 else if (offset
> 0)
22318 /* Short opcode. */
22319 op
= (offset
- 4) >> 2;
22320 add_unwind_opcode (op
, 1);
22322 else if (offset
< 0)
22325 while (offset
> 0x100)
22327 add_unwind_opcode (0x7f, 1);
22330 op
= ((offset
- 4) >> 2) | 0x40;
22331 add_unwind_opcode (op
, 1);
22335 /* Finish the list of unwind opcodes for this function. */
22338 finish_unwind_opcodes (void)
22342 if (unwind
.fp_used
)
22344 /* Adjust sp as necessary. */
22345 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
22346 flush_pending_unwind ();
22348 /* After restoring sp from the frame pointer. */
22349 op
= 0x90 | unwind
.fp_reg
;
22350 add_unwind_opcode (op
, 1);
22353 flush_pending_unwind ();
22357 /* Start an exception table entry. If idx is nonzero this is an index table
22361 start_unwind_section (const segT text_seg
, int idx
)
22363 const char * text_name
;
22364 const char * prefix
;
22365 const char * prefix_once
;
22366 const char * group_name
;
22374 prefix
= ELF_STRING_ARM_unwind
;
22375 prefix_once
= ELF_STRING_ARM_unwind_once
;
22376 type
= SHT_ARM_EXIDX
;
22380 prefix
= ELF_STRING_ARM_unwind_info
;
22381 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
22382 type
= SHT_PROGBITS
;
22385 text_name
= segment_name (text_seg
);
22386 if (streq (text_name
, ".text"))
22389 if (strncmp (text_name
, ".gnu.linkonce.t.",
22390 strlen (".gnu.linkonce.t.")) == 0)
22392 prefix
= prefix_once
;
22393 text_name
+= strlen (".gnu.linkonce.t.");
22396 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
22402 /* Handle COMDAT group. */
22403 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
22405 group_name
= elf_group_name (text_seg
);
22406 if (group_name
== NULL
)
22408 as_bad (_("Group section `%s' has no group signature"),
22409 segment_name (text_seg
));
22410 ignore_rest_of_line ();
22413 flags
|= SHF_GROUP
;
22417 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
22420 /* Set the section link for index tables. */
22422 elf_linked_to_section (now_seg
) = text_seg
;
22426 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22427 personality routine data. Returns zero, or the index table value for
22428 an inline entry. */
22431 create_unwind_entry (int have_data
)
22436 /* The current word of data. */
22438 /* The number of bytes left in this word. */
22441 finish_unwind_opcodes ();
22443 /* Remember the current text section. */
22444 unwind
.saved_seg
= now_seg
;
22445 unwind
.saved_subseg
= now_subseg
;
22447 start_unwind_section (now_seg
, 0);
22449 if (unwind
.personality_routine
== NULL
)
22451 if (unwind
.personality_index
== -2)
22454 as_bad (_("handlerdata in cantunwind frame"));
22455 return 1; /* EXIDX_CANTUNWIND. */
22458 /* Use a default personality routine if none is specified. */
22459 if (unwind
.personality_index
== -1)
22461 if (unwind
.opcode_count
> 3)
22462 unwind
.personality_index
= 1;
22464 unwind
.personality_index
= 0;
22467 /* Space for the personality routine entry. */
22468 if (unwind
.personality_index
== 0)
22470 if (unwind
.opcode_count
> 3)
22471 as_bad (_("too many unwind opcodes for personality routine 0"));
22475 /* All the data is inline in the index table. */
22478 while (unwind
.opcode_count
> 0)
22480 unwind
.opcode_count
--;
22481 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22485 /* Pad with "finish" opcodes. */
22487 data
= (data
<< 8) | 0xb0;
22494 /* We get two opcodes "free" in the first word. */
22495 size
= unwind
.opcode_count
- 2;
22499 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22500 if (unwind
.personality_index
!= -1)
22502 as_bad (_("attempt to recreate an unwind entry"));
22506 /* An extra byte is required for the opcode count. */
22507 size
= unwind
.opcode_count
+ 1;
22510 size
= (size
+ 3) >> 2;
22512 as_bad (_("too many unwind opcodes"));
22514 frag_align (2, 0, 0);
22515 record_alignment (now_seg
, 2);
22516 unwind
.table_entry
= expr_build_dot ();
22518 /* Allocate the table entry. */
22519 ptr
= frag_more ((size
<< 2) + 4);
22520 /* PR 13449: Zero the table entries in case some of them are not used. */
22521 memset (ptr
, 0, (size
<< 2) + 4);
22522 where
= frag_now_fix () - ((size
<< 2) + 4);
22524 switch (unwind
.personality_index
)
22527 /* ??? Should this be a PLT generating relocation? */
22528 /* Custom personality routine. */
22529 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22530 BFD_RELOC_ARM_PREL31
);
22535 /* Set the first byte to the number of additional words. */
22536 data
= size
> 0 ? size
- 1 : 0;
22540 /* ABI defined personality routines. */
22542 /* Three opcodes bytes are packed into the first word. */
22549 /* The size and first two opcode bytes go in the first word. */
22550 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22555 /* Should never happen. */
22559 /* Pack the opcodes into words (MSB first), reversing the list at the same
22561 while (unwind
.opcode_count
> 0)
22565 md_number_to_chars (ptr
, data
, 4);
22570 unwind
.opcode_count
--;
22572 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22575 /* Finish off the last word. */
22578 /* Pad with "finish" opcodes. */
22580 data
= (data
<< 8) | 0xb0;
22582 md_number_to_chars (ptr
, data
, 4);
22587 /* Add an empty descriptor if there is no user-specified data. */
22588 ptr
= frag_more (4);
22589 md_number_to_chars (ptr
, 0, 4);
22596 /* Initialize the DWARF-2 unwind information for this procedure. */
22599 tc_arm_frame_initial_instructions (void)
22601 cfi_add_CFA_def_cfa (REG_SP
, 0);
22603 #endif /* OBJ_ELF */
22605 /* Convert REGNAME to a DWARF-2 register number. */
22608 tc_arm_regname_to_dw2regnum (char *regname
)
22610 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22614 /* PR 16694: Allow VFP registers as well. */
22615 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22619 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22628 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22632 exp
.X_op
= O_secrel
;
22633 exp
.X_add_symbol
= symbol
;
22634 exp
.X_add_number
= 0;
22635 emit_expr (&exp
, size
);
22639 /* MD interface: Symbol and relocation handling. */
22641 /* Return the address within the segment that a PC-relative fixup is
22642 relative to. For ARM, PC-relative fixups applied to instructions
22643 are generally relative to the location of the fixup plus 8 bytes.
22644 Thumb branches are offset by 4, and Thumb loads relative to PC
22645 require special handling. */
22648 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22650 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22652 /* If this is pc-relative and we are going to emit a relocation
22653 then we just want to put out any pipeline compensation that the linker
22654 will need. Otherwise we want to use the calculated base.
22655 For WinCE we skip the bias for externals as well, since this
22656 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22658 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22659 || (arm_force_relocation (fixP
)
22661 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22667 switch (fixP
->fx_r_type
)
22669 /* PC relative addressing on the Thumb is slightly odd as the
22670 bottom two bits of the PC are forced to zero for the
22671 calculation. This happens *after* application of the
22672 pipeline offset. However, Thumb adrl already adjusts for
22673 this, so we need not do it again. */
22674 case BFD_RELOC_ARM_THUMB_ADD
:
22677 case BFD_RELOC_ARM_THUMB_OFFSET
:
22678 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22679 case BFD_RELOC_ARM_T32_ADD_PC12
:
22680 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22681 return (base
+ 4) & ~3;
22683 /* Thumb branches are simply offset by +4. */
22684 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22685 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22686 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22687 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22688 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22691 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22693 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22694 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22695 && ARM_IS_FUNC (fixP
->fx_addsy
)
22696 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22697 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22700 /* BLX is like branches above, but forces the low two bits of PC to
22702 case BFD_RELOC_THUMB_PCREL_BLX
:
22704 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22705 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22706 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22707 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22708 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22709 return (base
+ 4) & ~3;
22711 /* ARM mode branches are offset by +8. However, the Windows CE
22712 loader expects the relocation not to take this into account. */
22713 case BFD_RELOC_ARM_PCREL_BLX
:
22715 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22716 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22717 && ARM_IS_FUNC (fixP
->fx_addsy
)
22718 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22719 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22722 case BFD_RELOC_ARM_PCREL_CALL
:
22724 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22725 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22726 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22727 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22728 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22731 case BFD_RELOC_ARM_PCREL_BRANCH
:
22732 case BFD_RELOC_ARM_PCREL_JUMP
:
22733 case BFD_RELOC_ARM_PLT32
:
22735 /* When handling fixups immediately, because we have already
22736 discovered the value of a symbol, or the address of the frag involved
22737 we must account for the offset by +8, as the OS loader will never see the reloc.
22738 see fixup_segment() in write.c
22739 The S_IS_EXTERNAL test handles the case of global symbols.
22740 Those need the calculated base, not just the pipe compensation the linker will need. */
22742 && fixP
->fx_addsy
!= NULL
22743 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22744 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22752 /* ARM mode loads relative to PC are also offset by +8. Unlike
22753 branches, the Windows CE loader *does* expect the relocation
22754 to take this into account. */
22755 case BFD_RELOC_ARM_OFFSET_IMM
:
22756 case BFD_RELOC_ARM_OFFSET_IMM8
:
22757 case BFD_RELOC_ARM_HWLITERAL
:
22758 case BFD_RELOC_ARM_LITERAL
:
22759 case BFD_RELOC_ARM_CP_OFF_IMM
:
22763 /* Other PC-relative relocations are un-offset. */
22769 static bfd_boolean flag_warn_syms
= TRUE
;
22772 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22774 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22775 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22776 does mean that the resulting code might be very confusing to the reader.
22777 Also this warning can be triggered if the user omits an operand before
22778 an immediate address, eg:
22782 GAS treats this as an assignment of the value of the symbol foo to a
22783 symbol LDR, and so (without this code) it will not issue any kind of
22784 warning or error message.
22786 Note - ARM instructions are case-insensitive but the strings in the hash
22787 table are all stored in lower case, so we must first ensure that name is
22789 if (flag_warn_syms
&& arm_ops_hsh
)
22791 char * nbuf
= strdup (name
);
22794 for (p
= nbuf
; *p
; p
++)
22796 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22798 static struct hash_control
* already_warned
= NULL
;
22800 if (already_warned
== NULL
)
22801 already_warned
= hash_new ();
22802 /* Only warn about the symbol once. To keep the code
22803 simple we let hash_insert do the lookup for us. */
22804 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22805 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22814 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22815 Otherwise we have no need to default values of symbols. */
22818 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22821 if (name
[0] == '_' && name
[1] == 'G'
22822 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22826 if (symbol_find (name
))
22827 as_bad (_("GOT already in the symbol table"));
22829 GOT_symbol
= symbol_new (name
, undefined_section
,
22830 (valueT
) 0, & zero_address_frag
);
22840 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22841 computed as two separate immediate values, added together. We
22842 already know that this value cannot be computed by just one ARM
22845 static unsigned int
22846 validate_immediate_twopart (unsigned int val
,
22847 unsigned int * highpart
)
22852 for (i
= 0; i
< 32; i
+= 2)
22853 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22859 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22861 else if (a
& 0xff0000)
22863 if (a
& 0xff000000)
22865 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22869 gas_assert (a
& 0xff000000);
22870 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22873 return (a
& 0xff) | (i
<< 7);
22880 validate_offset_imm (unsigned int val
, int hwse
)
22882 if ((hwse
&& val
> 255) || val
> 4095)
22887 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22888 negative immediate constant by altering the instruction. A bit of
22893 by inverting the second operand, and
22896 by negating the second operand. */
22899 negate_data_op (unsigned long * instruction
,
22900 unsigned long value
)
22903 unsigned long negated
, inverted
;
22905 negated
= encode_arm_immediate (-value
);
22906 inverted
= encode_arm_immediate (~value
);
22908 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22911 /* First negates. */
22912 case OPCODE_SUB
: /* ADD <-> SUB */
22913 new_inst
= OPCODE_ADD
;
22918 new_inst
= OPCODE_SUB
;
22922 case OPCODE_CMP
: /* CMP <-> CMN */
22923 new_inst
= OPCODE_CMN
;
22928 new_inst
= OPCODE_CMP
;
22932 /* Now Inverted ops. */
22933 case OPCODE_MOV
: /* MOV <-> MVN */
22934 new_inst
= OPCODE_MVN
;
22939 new_inst
= OPCODE_MOV
;
22943 case OPCODE_AND
: /* AND <-> BIC */
22944 new_inst
= OPCODE_BIC
;
22949 new_inst
= OPCODE_AND
;
22953 case OPCODE_ADC
: /* ADC <-> SBC */
22954 new_inst
= OPCODE_SBC
;
22959 new_inst
= OPCODE_ADC
;
22963 /* We cannot do anything. */
22968 if (value
== (unsigned) FAIL
)
22971 *instruction
&= OPCODE_MASK
;
22972 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22976 /* Like negate_data_op, but for Thumb-2. */
22978 static unsigned int
22979 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22983 unsigned int negated
, inverted
;
22985 negated
= encode_thumb32_immediate (-value
);
22986 inverted
= encode_thumb32_immediate (~value
);
22988 rd
= (*instruction
>> 8) & 0xf;
22989 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22992 /* ADD <-> SUB. Includes CMP <-> CMN. */
22993 case T2_OPCODE_SUB
:
22994 new_inst
= T2_OPCODE_ADD
;
22998 case T2_OPCODE_ADD
:
22999 new_inst
= T2_OPCODE_SUB
;
23003 /* ORR <-> ORN. Includes MOV <-> MVN. */
23004 case T2_OPCODE_ORR
:
23005 new_inst
= T2_OPCODE_ORN
;
23009 case T2_OPCODE_ORN
:
23010 new_inst
= T2_OPCODE_ORR
;
23014 /* AND <-> BIC. TST has no inverted equivalent. */
23015 case T2_OPCODE_AND
:
23016 new_inst
= T2_OPCODE_BIC
;
23023 case T2_OPCODE_BIC
:
23024 new_inst
= T2_OPCODE_AND
;
23029 case T2_OPCODE_ADC
:
23030 new_inst
= T2_OPCODE_SBC
;
23034 case T2_OPCODE_SBC
:
23035 new_inst
= T2_OPCODE_ADC
;
23039 /* We cannot do anything. */
23044 if (value
== (unsigned int)FAIL
)
23047 *instruction
&= T2_OPCODE_MASK
;
23048 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
23052 /* Read a 32-bit thumb instruction from buf. */
23054 static unsigned long
23055 get_thumb32_insn (char * buf
)
23057 unsigned long insn
;
23058 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
23059 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23064 /* We usually want to set the low bit on the address of thumb function
23065 symbols. In particular .word foo - . should have the low bit set.
23066 Generic code tries to fold the difference of two symbols to
23067 a constant. Prevent this and force a relocation when the first symbols
23068 is a thumb function. */
23071 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
23073 if (op
== O_subtract
23074 && l
->X_op
== O_symbol
23075 && r
->X_op
== O_symbol
23076 && THUMB_IS_FUNC (l
->X_add_symbol
))
23078 l
->X_op
= O_subtract
;
23079 l
->X_op_symbol
= r
->X_add_symbol
;
23080 l
->X_add_number
-= r
->X_add_number
;
23084 /* Process as normal. */
23088 /* Encode Thumb2 unconditional branches and calls. The encoding
23089 for the 2 are identical for the immediate values. */
23092 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
23094 #define T2I1I2MASK ((1 << 13) | (1 << 11))
23097 addressT S
, I1
, I2
, lo
, hi
;
23099 S
= (value
>> 24) & 0x01;
23100 I1
= (value
>> 23) & 0x01;
23101 I2
= (value
>> 22) & 0x01;
23102 hi
= (value
>> 12) & 0x3ff;
23103 lo
= (value
>> 1) & 0x7ff;
23104 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23105 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23106 newval
|= (S
<< 10) | hi
;
23107 newval2
&= ~T2I1I2MASK
;
23108 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
23109 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23110 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23114 md_apply_fix (fixS
* fixP
,
23118 offsetT value
= * valP
;
23120 unsigned int newimm
;
23121 unsigned long temp
;
23123 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
23125 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
23127 /* Note whether this will delete the relocation. */
23129 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
23132 /* On a 64-bit host, silently truncate 'value' to 32 bits for
23133 consistency with the behaviour on 32-bit hosts. Remember value
23135 value
&= 0xffffffff;
23136 value
^= 0x80000000;
23137 value
-= 0x80000000;
23140 fixP
->fx_addnumber
= value
;
23142 /* Same treatment for fixP->fx_offset. */
23143 fixP
->fx_offset
&= 0xffffffff;
23144 fixP
->fx_offset
^= 0x80000000;
23145 fixP
->fx_offset
-= 0x80000000;
23147 switch (fixP
->fx_r_type
)
23149 case BFD_RELOC_NONE
:
23150 /* This will need to go in the object file. */
23154 case BFD_RELOC_ARM_IMMEDIATE
:
23155 /* We claim that this fixup has been processed here,
23156 even if in fact we generate an error because we do
23157 not have a reloc for it, so tc_gen_reloc will reject it. */
23160 if (fixP
->fx_addsy
)
23162 const char *msg
= 0;
23164 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23165 msg
= _("undefined symbol %s used as an immediate value");
23166 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23167 msg
= _("symbol %s is in a different section");
23168 else if (S_IS_WEAK (fixP
->fx_addsy
))
23169 msg
= _("symbol %s is weak and may be overridden later");
23173 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23174 msg
, S_GET_NAME (fixP
->fx_addsy
));
23179 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23181 /* If the offset is negative, we should use encoding A2 for ADR. */
23182 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
23183 newimm
= negate_data_op (&temp
, value
);
23186 newimm
= encode_arm_immediate (value
);
23188 /* If the instruction will fail, see if we can fix things up by
23189 changing the opcode. */
23190 if (newimm
== (unsigned int) FAIL
)
23191 newimm
= negate_data_op (&temp
, value
);
23192 /* MOV accepts both ARM modified immediate (A1 encoding) and
23193 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
23194 When disassembling, MOV is preferred when there is no encoding
23196 if (newimm
== (unsigned int) FAIL
23197 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
23198 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
23199 && !((temp
>> SBIT_SHIFT
) & 0x1)
23200 && value
>= 0 && value
<= 0xffff)
23202 /* Clear bits[23:20] to change encoding from A1 to A2. */
23203 temp
&= 0xff0fffff;
23204 /* Encoding high 4bits imm. Code below will encode the remaining
23206 temp
|= (value
& 0x0000f000) << 4;
23207 newimm
= value
& 0x00000fff;
23211 if (newimm
== (unsigned int) FAIL
)
23213 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23214 _("invalid constant (%lx) after fixup"),
23215 (unsigned long) value
);
23219 newimm
|= (temp
& 0xfffff000);
23220 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23223 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23225 unsigned int highpart
= 0;
23226 unsigned int newinsn
= 0xe1a00000; /* nop. */
23228 if (fixP
->fx_addsy
)
23230 const char *msg
= 0;
23232 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23233 msg
= _("undefined symbol %s used as an immediate value");
23234 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23235 msg
= _("symbol %s is in a different section");
23236 else if (S_IS_WEAK (fixP
->fx_addsy
))
23237 msg
= _("symbol %s is weak and may be overridden later");
23241 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23242 msg
, S_GET_NAME (fixP
->fx_addsy
));
23247 newimm
= encode_arm_immediate (value
);
23248 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23250 /* If the instruction will fail, see if we can fix things up by
23251 changing the opcode. */
23252 if (newimm
== (unsigned int) FAIL
23253 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
23255 /* No ? OK - try using two ADD instructions to generate
23257 newimm
= validate_immediate_twopart (value
, & highpart
);
23259 /* Yes - then make sure that the second instruction is
23261 if (newimm
!= (unsigned int) FAIL
)
23263 /* Still No ? Try using a negated value. */
23264 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
23265 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
23266 /* Otherwise - give up. */
23269 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23270 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
23275 /* Replace the first operand in the 2nd instruction (which
23276 is the PC) with the destination register. We have
23277 already added in the PC in the first instruction and we
23278 do not want to do it again. */
23279 newinsn
&= ~ 0xf0000;
23280 newinsn
|= ((newinsn
& 0x0f000) << 4);
23283 newimm
|= (temp
& 0xfffff000);
23284 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23286 highpart
|= (newinsn
& 0xfffff000);
23287 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
23291 case BFD_RELOC_ARM_OFFSET_IMM
:
23292 if (!fixP
->fx_done
&& seg
->use_rela_p
)
23294 /* Fall through. */
23296 case BFD_RELOC_ARM_LITERAL
:
23302 if (validate_offset_imm (value
, 0) == FAIL
)
23304 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
23305 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23306 _("invalid literal constant: pool needs to be closer"));
23308 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23309 _("bad immediate value for offset (%ld)"),
23314 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23316 newval
&= 0xfffff000;
23319 newval
&= 0xff7ff000;
23320 newval
|= value
| (sign
? INDEX_UP
: 0);
23322 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23325 case BFD_RELOC_ARM_OFFSET_IMM8
:
23326 case BFD_RELOC_ARM_HWLITERAL
:
23332 if (validate_offset_imm (value
, 1) == FAIL
)
23334 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
23335 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23336 _("invalid literal constant: pool needs to be closer"));
23338 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23339 _("bad immediate value for 8-bit offset (%ld)"),
23344 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23346 newval
&= 0xfffff0f0;
23349 newval
&= 0xff7ff0f0;
23350 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
23352 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23355 case BFD_RELOC_ARM_T32_OFFSET_U8
:
23356 if (value
< 0 || value
> 1020 || value
% 4 != 0)
23357 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23358 _("bad immediate value for offset (%ld)"), (long) value
);
23361 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
23363 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
23366 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23367 /* This is a complicated relocation used for all varieties of Thumb32
23368 load/store instruction with immediate offset:
23370 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
23371 *4, optional writeback(W)
23372 (doubleword load/store)
23374 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
23375 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
23376 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
23377 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
23378 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
23380 Uppercase letters indicate bits that are already encoded at
23381 this point. Lowercase letters are our problem. For the
23382 second block of instructions, the secondary opcode nybble
23383 (bits 8..11) is present, and bit 23 is zero, even if this is
23384 a PC-relative operation. */
23385 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23387 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
23389 if ((newval
& 0xf0000000) == 0xe0000000)
23391 /* Doubleword load/store: 8-bit offset, scaled by 4. */
23393 newval
|= (1 << 23);
23396 if (value
% 4 != 0)
23398 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23399 _("offset not a multiple of 4"));
23405 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23406 _("offset out of range"));
23411 else if ((newval
& 0x000f0000) == 0x000f0000)
23413 /* PC-relative, 12-bit offset. */
23415 newval
|= (1 << 23);
23420 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23421 _("offset out of range"));
23426 else if ((newval
& 0x00000100) == 0x00000100)
23428 /* Writeback: 8-bit, +/- offset. */
23430 newval
|= (1 << 9);
23435 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23436 _("offset out of range"));
23441 else if ((newval
& 0x00000f00) == 0x00000e00)
23443 /* T-instruction: positive 8-bit offset. */
23444 if (value
< 0 || value
> 0xff)
23446 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23447 _("offset out of range"));
23455 /* Positive 12-bit or negative 8-bit offset. */
23459 newval
|= (1 << 23);
23469 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23470 _("offset out of range"));
23477 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23478 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23481 case BFD_RELOC_ARM_SHIFT_IMM
:
23482 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23483 if (((unsigned long) value
) > 32
23485 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23487 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23488 _("shift expression is too large"));
23493 /* Shifts of zero must be done as lsl. */
23495 else if (value
== 32)
23497 newval
&= 0xfffff07f;
23498 newval
|= (value
& 0x1f) << 7;
23499 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23502 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23503 case BFD_RELOC_ARM_T32_ADD_IMM
:
23504 case BFD_RELOC_ARM_T32_IMM12
:
23505 case BFD_RELOC_ARM_T32_ADD_PC12
:
23506 /* We claim that this fixup has been processed here,
23507 even if in fact we generate an error because we do
23508 not have a reloc for it, so tc_gen_reloc will reject it. */
23512 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23514 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23515 _("undefined symbol %s used as an immediate value"),
23516 S_GET_NAME (fixP
->fx_addsy
));
23520 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23522 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23525 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23526 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
23527 Thumb2 modified immediate encoding (T2). */
23528 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
23529 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23531 newimm
= encode_thumb32_immediate (value
);
23532 if (newimm
== (unsigned int) FAIL
)
23533 newimm
= thumb32_negate_data_op (&newval
, value
);
23535 if (newimm
== (unsigned int) FAIL
)
23537 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
23539 /* Turn add/sum into addw/subw. */
23540 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23541 newval
= (newval
& 0xfeffffff) | 0x02000000;
23542 /* No flat 12-bit imm encoding for addsw/subsw. */
23543 if ((newval
& 0x00100000) == 0)
23545 /* 12 bit immediate for addw/subw. */
23549 newval
^= 0x00a00000;
23552 newimm
= (unsigned int) FAIL
;
23559 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
23560 UINT16 (T3 encoding), MOVW only accepts UINT16. When
23561 disassembling, MOV is preferred when there is no encoding
23563 NOTE: MOV is using ORR opcode under Thumb 2 mode. */
23564 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
23565 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
23566 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
23567 && value
>= 0 && value
<=0xffff)
23569 /* Toggle bit[25] to change encoding from T2 to T3. */
23571 /* Clear bits[19:16]. */
23572 newval
&= 0xfff0ffff;
23573 /* Encoding high 4bits imm. Code below will encode the
23574 remaining low 12bits. */
23575 newval
|= (value
& 0x0000f000) << 4;
23576 newimm
= value
& 0x00000fff;
23581 if (newimm
== (unsigned int)FAIL
)
23583 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23584 _("invalid constant (%lx) after fixup"),
23585 (unsigned long) value
);
23589 newval
|= (newimm
& 0x800) << 15;
23590 newval
|= (newimm
& 0x700) << 4;
23591 newval
|= (newimm
& 0x0ff);
23593 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23594 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23597 case BFD_RELOC_ARM_SMC
:
23598 if (((unsigned long) value
) > 0xffff)
23599 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23600 _("invalid smc expression"));
23601 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23602 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23603 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23606 case BFD_RELOC_ARM_HVC
:
23607 if (((unsigned long) value
) > 0xffff)
23608 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23609 _("invalid hvc expression"));
23610 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23611 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23612 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23615 case BFD_RELOC_ARM_SWI
:
23616 if (fixP
->tc_fix_data
!= 0)
23618 if (((unsigned long) value
) > 0xff)
23619 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23620 _("invalid swi expression"));
23621 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23623 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23627 if (((unsigned long) value
) > 0x00ffffff)
23628 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23629 _("invalid swi expression"));
23630 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23632 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23636 case BFD_RELOC_ARM_MULTI
:
23637 if (((unsigned long) value
) > 0xffff)
23638 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23639 _("invalid expression in load/store multiple"));
23640 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23641 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23645 case BFD_RELOC_ARM_PCREL_CALL
:
23647 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23649 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23650 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23651 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23652 /* Flip the bl to blx. This is a simple flip
23653 bit here because we generate PCREL_CALL for
23654 unconditional bls. */
23656 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23657 newval
= newval
| 0x10000000;
23658 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23664 goto arm_branch_common
;
23666 case BFD_RELOC_ARM_PCREL_JUMP
:
23667 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23669 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23670 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23671 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23673 /* This would map to a bl<cond>, b<cond>,
23674 b<always> to a Thumb function. We
23675 need to force a relocation for this particular
23677 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23680 /* Fall through. */
23682 case BFD_RELOC_ARM_PLT32
:
23684 case BFD_RELOC_ARM_PCREL_BRANCH
:
23686 goto arm_branch_common
;
23688 case BFD_RELOC_ARM_PCREL_BLX
:
23691 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23693 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23694 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23695 && ARM_IS_FUNC (fixP
->fx_addsy
))
23697 /* Flip the blx to a bl and warn. */
23698 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23699 newval
= 0xeb000000;
23700 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23701 _("blx to '%s' an ARM ISA state function changed to bl"),
23703 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23709 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23710 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23714 /* We are going to store value (shifted right by two) in the
23715 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23716 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23719 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23720 _("misaligned branch destination"));
23721 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23722 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23723 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23725 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23727 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23728 newval
|= (value
>> 2) & 0x00ffffff;
23729 /* Set the H bit on BLX instructions. */
23733 newval
|= 0x01000000;
23735 newval
&= ~0x01000000;
23737 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23741 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23742 /* CBZ can only branch forward. */
23744 /* Attempts to use CBZ to branch to the next instruction
23745 (which, strictly speaking, are prohibited) will be turned into
23748 FIXME: It may be better to remove the instruction completely and
23749 perform relaxation. */
23752 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23753 newval
= 0xbf00; /* NOP encoding T1 */
23754 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23759 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23761 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23763 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23764 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23765 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23770 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23771 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23772 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23774 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23776 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23777 newval
|= (value
& 0x1ff) >> 1;
23778 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23782 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23783 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23784 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23786 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23788 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23789 newval
|= (value
& 0xfff) >> 1;
23790 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23794 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23796 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23797 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23798 && ARM_IS_FUNC (fixP
->fx_addsy
)
23799 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23801 /* Force a relocation for a branch 20 bits wide. */
23804 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23805 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23806 _("conditional branch out of range"));
23808 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23811 addressT S
, J1
, J2
, lo
, hi
;
23813 S
= (value
& 0x00100000) >> 20;
23814 J2
= (value
& 0x00080000) >> 19;
23815 J1
= (value
& 0x00040000) >> 18;
23816 hi
= (value
& 0x0003f000) >> 12;
23817 lo
= (value
& 0x00000ffe) >> 1;
23819 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23820 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23821 newval
|= (S
<< 10) | hi
;
23822 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23823 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23824 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23828 case BFD_RELOC_THUMB_PCREL_BLX
:
23829 /* If there is a blx from a thumb state function to
23830 another thumb function flip this to a bl and warn
23834 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23835 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23836 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23838 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23839 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23840 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23842 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23843 newval
= newval
| 0x1000;
23844 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23845 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23850 goto thumb_bl_common
;
23852 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23853 /* A bl from Thumb state ISA to an internal ARM state function
23854 is converted to a blx. */
23856 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23857 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23858 && ARM_IS_FUNC (fixP
->fx_addsy
)
23859 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23861 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23862 newval
= newval
& ~0x1000;
23863 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23864 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23870 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23871 /* For a BLX instruction, make sure that the relocation is rounded up
23872 to a word boundary. This follows the semantics of the instruction
23873 which specifies that bit 1 of the target address will come from bit
23874 1 of the base address. */
23875 value
= (value
+ 3) & ~ 3;
23878 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23879 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23880 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23883 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23885 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23886 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23887 else if ((value
& ~0x1ffffff)
23888 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23889 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23890 _("Thumb2 branch out of range"));
23893 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23894 encode_thumb2_b_bl_offset (buf
, value
);
23898 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23899 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23900 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23902 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23903 encode_thumb2_b_bl_offset (buf
, value
);
23908 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23913 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23914 md_number_to_chars (buf
, value
, 2);
23918 case BFD_RELOC_ARM_TLS_CALL
:
23919 case BFD_RELOC_ARM_THM_TLS_CALL
:
23920 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23921 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23922 case BFD_RELOC_ARM_TLS_GOTDESC
:
23923 case BFD_RELOC_ARM_TLS_GD32
:
23924 case BFD_RELOC_ARM_TLS_LE32
:
23925 case BFD_RELOC_ARM_TLS_IE32
:
23926 case BFD_RELOC_ARM_TLS_LDM32
:
23927 case BFD_RELOC_ARM_TLS_LDO32
:
23928 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23931 case BFD_RELOC_ARM_GOT32
:
23932 case BFD_RELOC_ARM_GOTOFF
:
23935 case BFD_RELOC_ARM_GOT_PREL
:
23936 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23937 md_number_to_chars (buf
, value
, 4);
23940 case BFD_RELOC_ARM_TARGET2
:
23941 /* TARGET2 is not partial-inplace, so we need to write the
23942 addend here for REL targets, because it won't be written out
23943 during reloc processing later. */
23944 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23945 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
23949 case BFD_RELOC_RVA
:
23951 case BFD_RELOC_ARM_TARGET1
:
23952 case BFD_RELOC_ARM_ROSEGREL32
:
23953 case BFD_RELOC_ARM_SBREL32
:
23954 case BFD_RELOC_32_PCREL
:
23956 case BFD_RELOC_32_SECREL
:
23958 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23960 /* For WinCE we only do this for pcrel fixups. */
23961 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
23963 md_number_to_chars (buf
, value
, 4);
23967 case BFD_RELOC_ARM_PREL31
:
23968 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23970 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
23971 if ((value
^ (value
>> 1)) & 0x40000000)
23973 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23974 _("rel31 relocation overflow"));
23976 newval
|= value
& 0x7fffffff;
23977 md_number_to_chars (buf
, newval
, 4);
23982 case BFD_RELOC_ARM_CP_OFF_IMM
:
23983 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23984 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
23985 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23987 newval
= get_thumb32_insn (buf
);
23988 if ((newval
& 0x0f200f00) == 0x0d000900)
23990 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23991 has permitted values that are multiples of 2, in the range 0
23993 if (value
< -510 || value
> 510 || (value
& 1))
23994 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23995 _("co-processor offset out of range"));
23997 else if (value
< -1023 || value
> 1023 || (value
& 3))
23998 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23999 _("co-processor offset out of range"));
24004 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24005 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24006 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24008 newval
= get_thumb32_insn (buf
);
24010 newval
&= 0xffffff00;
24013 newval
&= 0xff7fff00;
24014 if ((newval
& 0x0f200f00) == 0x0d000900)
24016 /* This is a fp16 vstr/vldr.
24018 It requires the immediate offset in the instruction is shifted
24019 left by 1 to be a half-word offset.
24021 Here, left shift by 1 first, and later right shift by 2
24022 should get the right offset. */
24025 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
24027 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24028 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24029 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24031 put_thumb32_insn (buf
, newval
);
24034 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
24035 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
24036 if (value
< -255 || value
> 255)
24037 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24038 _("co-processor offset out of range"));
24040 goto cp_off_common
;
24042 case BFD_RELOC_ARM_THUMB_OFFSET
:
24043 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24044 /* Exactly what ranges, and where the offset is inserted depends
24045 on the type of instruction, we can establish this from the
24047 switch (newval
>> 12)
24049 case 4: /* PC load. */
24050 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
24051 forced to zero for these loads; md_pcrel_from has already
24052 compensated for this. */
24054 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24055 _("invalid offset, target not word aligned (0x%08lX)"),
24056 (((unsigned long) fixP
->fx_frag
->fr_address
24057 + (unsigned long) fixP
->fx_where
) & ~3)
24058 + (unsigned long) value
);
24060 if (value
& ~0x3fc)
24061 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24062 _("invalid offset, value too big (0x%08lX)"),
24065 newval
|= value
>> 2;
24068 case 9: /* SP load/store. */
24069 if (value
& ~0x3fc)
24070 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24071 _("invalid offset, value too big (0x%08lX)"),
24073 newval
|= value
>> 2;
24076 case 6: /* Word load/store. */
24078 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24079 _("invalid offset, value too big (0x%08lX)"),
24081 newval
|= value
<< 4; /* 6 - 2. */
24084 case 7: /* Byte load/store. */
24086 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24087 _("invalid offset, value too big (0x%08lX)"),
24089 newval
|= value
<< 6;
24092 case 8: /* Halfword load/store. */
24094 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24095 _("invalid offset, value too big (0x%08lX)"),
24097 newval
|= value
<< 5; /* 6 - 1. */
24101 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24102 "Unable to process relocation for thumb opcode: %lx",
24103 (unsigned long) newval
);
24106 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24109 case BFD_RELOC_ARM_THUMB_ADD
:
24110 /* This is a complicated relocation, since we use it for all of
24111 the following immediate relocations:
24115 9bit ADD/SUB SP word-aligned
24116 10bit ADD PC/SP word-aligned
24118 The type of instruction being processed is encoded in the
24125 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24127 int rd
= (newval
>> 4) & 0xf;
24128 int rs
= newval
& 0xf;
24129 int subtract
= !!(newval
& 0x8000);
24131 /* Check for HI regs, only very restricted cases allowed:
24132 Adjusting SP, and using PC or SP to get an address. */
24133 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
24134 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
24135 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24136 _("invalid Hi register with immediate"));
24138 /* If value is negative, choose the opposite instruction. */
24142 subtract
= !subtract
;
24144 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24145 _("immediate value out of range"));
24150 if (value
& ~0x1fc)
24151 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24152 _("invalid immediate for stack address calculation"));
24153 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
24154 newval
|= value
>> 2;
24156 else if (rs
== REG_PC
|| rs
== REG_SP
)
24158 /* PR gas/18541. If the addition is for a defined symbol
24159 within range of an ADR instruction then accept it. */
24162 && fixP
->fx_addsy
!= NULL
)
24166 if (! S_IS_DEFINED (fixP
->fx_addsy
)
24167 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
24168 || S_IS_WEAK (fixP
->fx_addsy
))
24170 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24171 _("address calculation needs a strongly defined nearby symbol"));
24175 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
24177 /* Round up to the next 4-byte boundary. */
24182 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
24186 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24187 _("symbol too far away"));
24197 if (subtract
|| value
& ~0x3fc)
24198 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24199 _("invalid immediate for address calculation (value = 0x%08lX)"),
24200 (unsigned long) (subtract
? - value
: value
));
24201 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
24203 newval
|= value
>> 2;
24208 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24209 _("immediate value out of range"));
24210 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
24211 newval
|= (rd
<< 8) | value
;
24216 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24217 _("immediate value out of range"));
24218 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
24219 newval
|= rd
| (rs
<< 3) | (value
<< 6);
24222 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24225 case BFD_RELOC_ARM_THUMB_IMM
:
24226 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24227 if (value
< 0 || value
> 255)
24228 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24229 _("invalid immediate: %ld is out of range"),
24232 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24235 case BFD_RELOC_ARM_THUMB_SHIFT
:
24236 /* 5bit shift value (0..32). LSL cannot take 32. */
24237 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
24238 temp
= newval
& 0xf800;
24239 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
24240 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24241 _("invalid shift value: %ld"), (long) value
);
24242 /* Shifts of zero must be encoded as LSL. */
24244 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
24245 /* Shifts of 32 are encoded as zero. */
24246 else if (value
== 32)
24248 newval
|= value
<< 6;
24249 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24252 case BFD_RELOC_VTABLE_INHERIT
:
24253 case BFD_RELOC_VTABLE_ENTRY
:
24257 case BFD_RELOC_ARM_MOVW
:
24258 case BFD_RELOC_ARM_MOVT
:
24259 case BFD_RELOC_ARM_THUMB_MOVW
:
24260 case BFD_RELOC_ARM_THUMB_MOVT
:
24261 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24263 /* REL format relocations are limited to a 16-bit addend. */
24264 if (!fixP
->fx_done
)
24266 if (value
< -0x8000 || value
> 0x7fff)
24267 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24268 _("offset out of range"));
24270 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24271 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24276 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24277 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24279 newval
= get_thumb32_insn (buf
);
24280 newval
&= 0xfbf08f00;
24281 newval
|= (value
& 0xf000) << 4;
24282 newval
|= (value
& 0x0800) << 15;
24283 newval
|= (value
& 0x0700) << 4;
24284 newval
|= (value
& 0x00ff);
24285 put_thumb32_insn (buf
, newval
);
24289 newval
= md_chars_to_number (buf
, 4);
24290 newval
&= 0xfff0f000;
24291 newval
|= value
& 0x0fff;
24292 newval
|= (value
& 0xf000) << 4;
24293 md_number_to_chars (buf
, newval
, 4);
24298 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24299 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24300 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24301 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24302 gas_assert (!fixP
->fx_done
);
24305 bfd_boolean is_mov
;
24306 bfd_vma encoded_addend
= value
;
24308 /* Check that addend can be encoded in instruction. */
24309 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
24310 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24311 _("the offset 0x%08lX is not representable"),
24312 (unsigned long) encoded_addend
);
24314 /* Extract the instruction. */
24315 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
24316 is_mov
= (insn
& 0xf800) == 0x2000;
24321 if (!seg
->use_rela_p
)
24322 insn
|= encoded_addend
;
24328 /* Extract the instruction. */
24329 /* Encoding is the following
24334 /* The following conditions must be true :
24339 rd
= (insn
>> 4) & 0xf;
24341 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
24342 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24343 _("Unable to process relocation for thumb opcode: %lx"),
24344 (unsigned long) insn
);
24346 /* Encode as ADD immediate8 thumb 1 code. */
24347 insn
= 0x3000 | (rd
<< 8);
24349 /* Place the encoded addend into the first 8 bits of the
24351 if (!seg
->use_rela_p
)
24352 insn
|= encoded_addend
;
24355 /* Update the instruction. */
24356 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
24360 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24361 case BFD_RELOC_ARM_ALU_PC_G0
:
24362 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24363 case BFD_RELOC_ARM_ALU_PC_G1
:
24364 case BFD_RELOC_ARM_ALU_PC_G2
:
24365 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24366 case BFD_RELOC_ARM_ALU_SB_G0
:
24367 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24368 case BFD_RELOC_ARM_ALU_SB_G1
:
24369 case BFD_RELOC_ARM_ALU_SB_G2
:
24370 gas_assert (!fixP
->fx_done
);
24371 if (!seg
->use_rela_p
)
24374 bfd_vma encoded_addend
;
24375 bfd_vma addend_abs
= abs (value
);
24377 /* Check that the absolute value of the addend can be
24378 expressed as an 8-bit constant plus a rotation. */
24379 encoded_addend
= encode_arm_immediate (addend_abs
);
24380 if (encoded_addend
== (unsigned int) FAIL
)
24381 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24382 _("the offset 0x%08lX is not representable"),
24383 (unsigned long) addend_abs
);
24385 /* Extract the instruction. */
24386 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24388 /* If the addend is positive, use an ADD instruction.
24389 Otherwise use a SUB. Take care not to destroy the S bit. */
24390 insn
&= 0xff1fffff;
24396 /* Place the encoded addend into the first 12 bits of the
24398 insn
&= 0xfffff000;
24399 insn
|= encoded_addend
;
24401 /* Update the instruction. */
24402 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24406 case BFD_RELOC_ARM_LDR_PC_G0
:
24407 case BFD_RELOC_ARM_LDR_PC_G1
:
24408 case BFD_RELOC_ARM_LDR_PC_G2
:
24409 case BFD_RELOC_ARM_LDR_SB_G0
:
24410 case BFD_RELOC_ARM_LDR_SB_G1
:
24411 case BFD_RELOC_ARM_LDR_SB_G2
:
24412 gas_assert (!fixP
->fx_done
);
24413 if (!seg
->use_rela_p
)
24416 bfd_vma addend_abs
= abs (value
);
24418 /* Check that the absolute value of the addend can be
24419 encoded in 12 bits. */
24420 if (addend_abs
>= 0x1000)
24421 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24422 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
24423 (unsigned long) addend_abs
);
24425 /* Extract the instruction. */
24426 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24428 /* If the addend is negative, clear bit 23 of the instruction.
24429 Otherwise set it. */
24431 insn
&= ~(1 << 23);
24435 /* Place the absolute value of the addend into the first 12 bits
24436 of the instruction. */
24437 insn
&= 0xfffff000;
24438 insn
|= addend_abs
;
24440 /* Update the instruction. */
24441 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24445 case BFD_RELOC_ARM_LDRS_PC_G0
:
24446 case BFD_RELOC_ARM_LDRS_PC_G1
:
24447 case BFD_RELOC_ARM_LDRS_PC_G2
:
24448 case BFD_RELOC_ARM_LDRS_SB_G0
:
24449 case BFD_RELOC_ARM_LDRS_SB_G1
:
24450 case BFD_RELOC_ARM_LDRS_SB_G2
:
24451 gas_assert (!fixP
->fx_done
);
24452 if (!seg
->use_rela_p
)
24455 bfd_vma addend_abs
= abs (value
);
24457 /* Check that the absolute value of the addend can be
24458 encoded in 8 bits. */
24459 if (addend_abs
>= 0x100)
24460 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24461 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
24462 (unsigned long) addend_abs
);
24464 /* Extract the instruction. */
24465 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24467 /* If the addend is negative, clear bit 23 of the instruction.
24468 Otherwise set it. */
24470 insn
&= ~(1 << 23);
24474 /* Place the first four bits of the absolute value of the addend
24475 into the first 4 bits of the instruction, and the remaining
24476 four into bits 8 .. 11. */
24477 insn
&= 0xfffff0f0;
24478 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
24480 /* Update the instruction. */
24481 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24485 case BFD_RELOC_ARM_LDC_PC_G0
:
24486 case BFD_RELOC_ARM_LDC_PC_G1
:
24487 case BFD_RELOC_ARM_LDC_PC_G2
:
24488 case BFD_RELOC_ARM_LDC_SB_G0
:
24489 case BFD_RELOC_ARM_LDC_SB_G1
:
24490 case BFD_RELOC_ARM_LDC_SB_G2
:
24491 gas_assert (!fixP
->fx_done
);
24492 if (!seg
->use_rela_p
)
24495 bfd_vma addend_abs
= abs (value
);
24497 /* Check that the absolute value of the addend is a multiple of
24498 four and, when divided by four, fits in 8 bits. */
24499 if (addend_abs
& 0x3)
24500 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24501 _("bad offset 0x%08lX (must be word-aligned)"),
24502 (unsigned long) addend_abs
);
24504 if ((addend_abs
>> 2) > 0xff)
24505 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24506 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24507 (unsigned long) addend_abs
);
24509 /* Extract the instruction. */
24510 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24512 /* If the addend is negative, clear bit 23 of the instruction.
24513 Otherwise set it. */
24515 insn
&= ~(1 << 23);
24519 /* Place the addend (divided by four) into the first eight
24520 bits of the instruction. */
24521 insn
&= 0xfffffff0;
24522 insn
|= addend_abs
>> 2;
24524 /* Update the instruction. */
24525 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24529 case BFD_RELOC_ARM_V4BX
:
24530 /* This will need to go in the object file. */
24534 case BFD_RELOC_UNUSED
:
24536 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24537 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24541 /* Translate internal representation of relocation info to BFD target
24545 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24548 bfd_reloc_code_real_type code
;
24550 reloc
= XNEW (arelent
);
24552 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24553 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24554 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24556 if (fixp
->fx_pcrel
)
24558 if (section
->use_rela_p
)
24559 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24561 fixp
->fx_offset
= reloc
->address
;
24563 reloc
->addend
= fixp
->fx_offset
;
24565 switch (fixp
->fx_r_type
)
24568 if (fixp
->fx_pcrel
)
24570 code
= BFD_RELOC_8_PCREL
;
24573 /* Fall through. */
24576 if (fixp
->fx_pcrel
)
24578 code
= BFD_RELOC_16_PCREL
;
24581 /* Fall through. */
24584 if (fixp
->fx_pcrel
)
24586 code
= BFD_RELOC_32_PCREL
;
24589 /* Fall through. */
24591 case BFD_RELOC_ARM_MOVW
:
24592 if (fixp
->fx_pcrel
)
24594 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24597 /* Fall through. */
24599 case BFD_RELOC_ARM_MOVT
:
24600 if (fixp
->fx_pcrel
)
24602 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24605 /* Fall through. */
24607 case BFD_RELOC_ARM_THUMB_MOVW
:
24608 if (fixp
->fx_pcrel
)
24610 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24613 /* Fall through. */
24615 case BFD_RELOC_ARM_THUMB_MOVT
:
24616 if (fixp
->fx_pcrel
)
24618 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24621 /* Fall through. */
24623 case BFD_RELOC_NONE
:
24624 case BFD_RELOC_ARM_PCREL_BRANCH
:
24625 case BFD_RELOC_ARM_PCREL_BLX
:
24626 case BFD_RELOC_RVA
:
24627 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24628 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24629 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24630 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24631 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24632 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24633 case BFD_RELOC_VTABLE_ENTRY
:
24634 case BFD_RELOC_VTABLE_INHERIT
:
24636 case BFD_RELOC_32_SECREL
:
24638 code
= fixp
->fx_r_type
;
24641 case BFD_RELOC_THUMB_PCREL_BLX
:
24643 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24644 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24647 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24650 case BFD_RELOC_ARM_LITERAL
:
24651 case BFD_RELOC_ARM_HWLITERAL
:
24652 /* If this is called then the a literal has
24653 been referenced across a section boundary. */
24654 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24655 _("literal referenced across section boundary"));
24659 case BFD_RELOC_ARM_TLS_CALL
:
24660 case BFD_RELOC_ARM_THM_TLS_CALL
:
24661 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24662 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24663 case BFD_RELOC_ARM_GOT32
:
24664 case BFD_RELOC_ARM_GOTOFF
:
24665 case BFD_RELOC_ARM_GOT_PREL
:
24666 case BFD_RELOC_ARM_PLT32
:
24667 case BFD_RELOC_ARM_TARGET1
:
24668 case BFD_RELOC_ARM_ROSEGREL32
:
24669 case BFD_RELOC_ARM_SBREL32
:
24670 case BFD_RELOC_ARM_PREL31
:
24671 case BFD_RELOC_ARM_TARGET2
:
24672 case BFD_RELOC_ARM_TLS_LDO32
:
24673 case BFD_RELOC_ARM_PCREL_CALL
:
24674 case BFD_RELOC_ARM_PCREL_JUMP
:
24675 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24676 case BFD_RELOC_ARM_ALU_PC_G0
:
24677 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24678 case BFD_RELOC_ARM_ALU_PC_G1
:
24679 case BFD_RELOC_ARM_ALU_PC_G2
:
24680 case BFD_RELOC_ARM_LDR_PC_G0
:
24681 case BFD_RELOC_ARM_LDR_PC_G1
:
24682 case BFD_RELOC_ARM_LDR_PC_G2
:
24683 case BFD_RELOC_ARM_LDRS_PC_G0
:
24684 case BFD_RELOC_ARM_LDRS_PC_G1
:
24685 case BFD_RELOC_ARM_LDRS_PC_G2
:
24686 case BFD_RELOC_ARM_LDC_PC_G0
:
24687 case BFD_RELOC_ARM_LDC_PC_G1
:
24688 case BFD_RELOC_ARM_LDC_PC_G2
:
24689 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24690 case BFD_RELOC_ARM_ALU_SB_G0
:
24691 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24692 case BFD_RELOC_ARM_ALU_SB_G1
:
24693 case BFD_RELOC_ARM_ALU_SB_G2
:
24694 case BFD_RELOC_ARM_LDR_SB_G0
:
24695 case BFD_RELOC_ARM_LDR_SB_G1
:
24696 case BFD_RELOC_ARM_LDR_SB_G2
:
24697 case BFD_RELOC_ARM_LDRS_SB_G0
:
24698 case BFD_RELOC_ARM_LDRS_SB_G1
:
24699 case BFD_RELOC_ARM_LDRS_SB_G2
:
24700 case BFD_RELOC_ARM_LDC_SB_G0
:
24701 case BFD_RELOC_ARM_LDC_SB_G1
:
24702 case BFD_RELOC_ARM_LDC_SB_G2
:
24703 case BFD_RELOC_ARM_V4BX
:
24704 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24705 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24706 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24707 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24708 code
= fixp
->fx_r_type
;
24711 case BFD_RELOC_ARM_TLS_GOTDESC
:
24712 case BFD_RELOC_ARM_TLS_GD32
:
24713 case BFD_RELOC_ARM_TLS_LE32
:
24714 case BFD_RELOC_ARM_TLS_IE32
:
24715 case BFD_RELOC_ARM_TLS_LDM32
:
24716 /* BFD will include the symbol's address in the addend.
24717 But we don't want that, so subtract it out again here. */
24718 if (!S_IS_COMMON (fixp
->fx_addsy
))
24719 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24720 code
= fixp
->fx_r_type
;
24724 case BFD_RELOC_ARM_IMMEDIATE
:
24725 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24726 _("internal relocation (type: IMMEDIATE) not fixed up"));
24729 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24730 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24731 _("ADRL used for a symbol not defined in the same file"));
24734 case BFD_RELOC_ARM_OFFSET_IMM
:
24735 if (section
->use_rela_p
)
24737 code
= fixp
->fx_r_type
;
24741 if (fixp
->fx_addsy
!= NULL
24742 && !S_IS_DEFINED (fixp
->fx_addsy
)
24743 && S_IS_LOCAL (fixp
->fx_addsy
))
24745 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24746 _("undefined local label `%s'"),
24747 S_GET_NAME (fixp
->fx_addsy
));
24751 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24752 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24759 switch (fixp
->fx_r_type
)
24761 case BFD_RELOC_NONE
: type
= "NONE"; break;
24762 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24763 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24764 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24765 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24766 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24767 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24768 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24769 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24770 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24771 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24772 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24773 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24774 default: type
= _("<unknown>"); break;
24776 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24777 _("cannot represent %s relocation in this object file format"),
24784 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24786 && fixp
->fx_addsy
== GOT_symbol
)
24788 code
= BFD_RELOC_ARM_GOTPC
;
24789 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24793 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24795 if (reloc
->howto
== NULL
)
24797 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24798 _("cannot represent %s relocation in this object file format"),
24799 bfd_get_reloc_code_name (code
));
24803 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24804 vtable entry to be used in the relocation's section offset. */
24805 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24806 reloc
->address
= fixp
->fx_offset
;
24811 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24814 cons_fix_new_arm (fragS
* frag
,
24818 bfd_reloc_code_real_type reloc
)
24823 FIXME: @@ Should look at CPU word size. */
24827 reloc
= BFD_RELOC_8
;
24830 reloc
= BFD_RELOC_16
;
24834 reloc
= BFD_RELOC_32
;
24837 reloc
= BFD_RELOC_64
;
24842 if (exp
->X_op
== O_secrel
)
24844 exp
->X_op
= O_symbol
;
24845 reloc
= BFD_RELOC_32_SECREL
;
24849 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24852 #if defined (OBJ_COFF)
24854 arm_validate_fix (fixS
* fixP
)
24856 /* If the destination of the branch is a defined symbol which does not have
24857 the THUMB_FUNC attribute, then we must be calling a function which has
24858 the (interfacearm) attribute. We look for the Thumb entry point to that
24859 function and change the branch to refer to that function instead. */
24860 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24861 && fixP
->fx_addsy
!= NULL
24862 && S_IS_DEFINED (fixP
->fx_addsy
)
24863 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24865 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24872 arm_force_relocation (struct fix
* fixp
)
24874 #if defined (OBJ_COFF) && defined (TE_PE)
24875 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24879 /* In case we have a call or a branch to a function in ARM ISA mode from
24880 a thumb function or vice-versa force the relocation. These relocations
24881 are cleared off for some cores that might have blx and simple transformations
24885 switch (fixp
->fx_r_type
)
24887 case BFD_RELOC_ARM_PCREL_JUMP
:
24888 case BFD_RELOC_ARM_PCREL_CALL
:
24889 case BFD_RELOC_THUMB_PCREL_BLX
:
24890 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24894 case BFD_RELOC_ARM_PCREL_BLX
:
24895 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24896 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24897 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24898 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24907 /* Resolve these relocations even if the symbol is extern or weak.
24908 Technically this is probably wrong due to symbol preemption.
24909 In practice these relocations do not have enough range to be useful
24910 at dynamic link time, and some code (e.g. in the Linux kernel)
24911 expects these references to be resolved. */
24912 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24913 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24914 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24915 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24916 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24917 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24918 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24919 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24920 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24921 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24922 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
24923 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
24924 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
24925 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
24928 /* Always leave these relocations for the linker. */
24929 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24930 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24931 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24934 /* Always generate relocations against function symbols. */
24935 if (fixp
->fx_r_type
== BFD_RELOC_32
24937 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
24940 return generic_force_reloc (fixp
);
24943 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24944 /* Relocations against function names must be left unadjusted,
24945 so that the linker can use this information to generate interworking
24946 stubs. The MIPS version of this function
24947 also prevents relocations that are mips-16 specific, but I do not
24948 know why it does this.
24951 There is one other problem that ought to be addressed here, but
24952 which currently is not: Taking the address of a label (rather
24953 than a function) and then later jumping to that address. Such
24954 addresses also ought to have their bottom bit set (assuming that
24955 they reside in Thumb code), but at the moment they will not. */
24958 arm_fix_adjustable (fixS
* fixP
)
24960 if (fixP
->fx_addsy
== NULL
)
24963 /* Preserve relocations against symbols with function type. */
24964 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
24967 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
24968 && fixP
->fx_subsy
== NULL
)
24971 /* We need the symbol name for the VTABLE entries. */
24972 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
24973 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24976 /* Don't allow symbols to be discarded on GOT related relocs. */
24977 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
24978 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
24979 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
24980 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
24981 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
24982 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
24983 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
24984 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
24985 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
24986 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
24987 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
24988 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
24989 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
24990 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
24993 /* Similarly for group relocations. */
24994 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24995 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24996 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24999 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
25000 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
25001 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
25002 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
25003 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
25004 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
25005 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
25006 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
25007 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
25010 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
25011 offsets, so keep these symbols. */
25012 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
25013 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
25018 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
25022 elf32_arm_target_format (void)
25025 return (target_big_endian
25026 ? "elf32-bigarm-symbian"
25027 : "elf32-littlearm-symbian");
25028 #elif defined (TE_VXWORKS)
25029 return (target_big_endian
25030 ? "elf32-bigarm-vxworks"
25031 : "elf32-littlearm-vxworks");
25032 #elif defined (TE_NACL)
25033 return (target_big_endian
25034 ? "elf32-bigarm-nacl"
25035 : "elf32-littlearm-nacl");
25037 if (target_big_endian
)
25038 return "elf32-bigarm";
25040 return "elf32-littlearm";
25045 armelf_frob_symbol (symbolS
* symp
,
25048 elf_frob_symbol (symp
, puntp
);
25052 /* MD interface: Finalization. */
25057 literal_pool
* pool
;
25059 /* Ensure that all the IT blocks are properly closed. */
25060 check_it_blocks_finished ();
25062 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
25064 /* Put it at the end of the relevant section. */
25065 subseg_set (pool
->section
, pool
->sub_section
);
25067 arm_elf_change_section ();
25074 /* Remove any excess mapping symbols generated for alignment frags in
25075 SEC. We may have created a mapping symbol before a zero byte
25076 alignment; remove it if there's a mapping symbol after the
25079 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
25080 void *dummy ATTRIBUTE_UNUSED
)
25082 segment_info_type
*seginfo
= seg_info (sec
);
25085 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
25088 for (fragp
= seginfo
->frchainP
->frch_root
;
25090 fragp
= fragp
->fr_next
)
25092 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
25093 fragS
*next
= fragp
->fr_next
;
25095 /* Variable-sized frags have been converted to fixed size by
25096 this point. But if this was variable-sized to start with,
25097 there will be a fixed-size frag after it. So don't handle
25099 if (sym
== NULL
|| next
== NULL
)
25102 if (S_GET_VALUE (sym
) < next
->fr_address
)
25103 /* Not at the end of this frag. */
25105 know (S_GET_VALUE (sym
) == next
->fr_address
);
25109 if (next
->tc_frag_data
.first_map
!= NULL
)
25111 /* Next frag starts with a mapping symbol. Discard this
25113 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25117 if (next
->fr_next
== NULL
)
25119 /* This mapping symbol is at the end of the section. Discard
25121 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
25122 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25126 /* As long as we have empty frags without any mapping symbols,
25128 /* If the next frag is non-empty and does not start with a
25129 mapping symbol, then this mapping symbol is required. */
25130 if (next
->fr_address
!= next
->fr_next
->fr_address
)
25133 next
= next
->fr_next
;
25135 while (next
!= NULL
);
25140 /* Adjust the symbol table. This marks Thumb symbols as distinct from
25144 arm_adjust_symtab (void)
25149 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25151 if (ARM_IS_THUMB (sym
))
25153 if (THUMB_IS_FUNC (sym
))
25155 /* Mark the symbol as a Thumb function. */
25156 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
25157 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
25158 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
25160 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
25161 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
25163 as_bad (_("%s: unexpected function type: %d"),
25164 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
25166 else switch (S_GET_STORAGE_CLASS (sym
))
25169 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
25172 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
25175 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
25183 if (ARM_IS_INTERWORK (sym
))
25184 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
25191 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25193 if (ARM_IS_THUMB (sym
))
25195 elf_symbol_type
* elf_sym
;
25197 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
25198 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
25200 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
25201 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
25203 /* If it's a .thumb_func, declare it as so,
25204 otherwise tag label as .code 16. */
25205 if (THUMB_IS_FUNC (sym
))
25206 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
25207 ST_BRANCH_TO_THUMB
);
25208 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25209 elf_sym
->internal_elf_sym
.st_info
=
25210 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
25215 /* Remove any overlapping mapping symbols generated by alignment frags. */
25216 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
25217 /* Now do generic ELF adjustments. */
25218 elf_adjust_symtab ();
25222 /* MD interface: Initialization. */
25225 set_constant_flonums (void)
25229 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
25230 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
25234 /* Auto-select Thumb mode if it's the only available instruction set for the
25235 given architecture. */
25238 autoselect_thumb_from_cpu_variant (void)
25240 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
25241 opcode_select (16);
25250 if ( (arm_ops_hsh
= hash_new ()) == NULL
25251 || (arm_cond_hsh
= hash_new ()) == NULL
25252 || (arm_shift_hsh
= hash_new ()) == NULL
25253 || (arm_psr_hsh
= hash_new ()) == NULL
25254 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
25255 || (arm_reg_hsh
= hash_new ()) == NULL
25256 || (arm_reloc_hsh
= hash_new ()) == NULL
25257 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
25258 as_fatal (_("virtual memory exhausted"));
25260 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
25261 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
25262 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
25263 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
25264 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
25265 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
25266 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
25267 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
25268 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
25269 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
25270 (void *) (v7m_psrs
+ i
));
25271 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
25272 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
25274 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
25276 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
25277 (void *) (barrier_opt_names
+ i
));
25279 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
25281 struct reloc_entry
* entry
= reloc_names
+ i
;
25283 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
25284 /* This makes encode_branch() use the EABI versions of this relocation. */
25285 entry
->reloc
= BFD_RELOC_UNUSED
;
25287 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
25291 set_constant_flonums ();
25293 /* Set the cpu variant based on the command-line options. We prefer
25294 -mcpu= over -march= if both are set (as for GCC); and we prefer
25295 -mfpu= over any other way of setting the floating point unit.
25296 Use of legacy options with new options are faulted. */
25299 if (mcpu_cpu_opt
|| march_cpu_opt
)
25300 as_bad (_("use of old and new-style options to set CPU type"));
25302 mcpu_cpu_opt
= legacy_cpu
;
25304 else if (!mcpu_cpu_opt
)
25306 mcpu_cpu_opt
= march_cpu_opt
;
25307 dyn_mcpu_ext_opt
= dyn_march_ext_opt
;
25308 /* Avoid double free in arm_md_end. */
25309 dyn_march_ext_opt
= NULL
;
25315 as_bad (_("use of old and new-style options to set FPU type"));
25317 mfpu_opt
= legacy_fpu
;
25319 else if (!mfpu_opt
)
25321 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
25322 || defined (TE_NetBSD) || defined (TE_VXWORKS))
25323 /* Some environments specify a default FPU. If they don't, infer it
25324 from the processor. */
25326 mfpu_opt
= mcpu_fpu_opt
;
25328 mfpu_opt
= march_fpu_opt
;
25330 mfpu_opt
= &fpu_default
;
25336 if (mcpu_cpu_opt
!= NULL
)
25337 mfpu_opt
= &fpu_default
;
25338 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
25339 mfpu_opt
= &fpu_arch_vfp_v2
;
25341 mfpu_opt
= &fpu_arch_fpa
;
25347 mcpu_cpu_opt
= &cpu_default
;
25348 selected_cpu
= cpu_default
;
25350 else if (dyn_mcpu_ext_opt
)
25351 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
25353 selected_cpu
= *mcpu_cpu_opt
;
25355 if (mcpu_cpu_opt
&& dyn_mcpu_ext_opt
)
25356 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
25357 else if (mcpu_cpu_opt
)
25358 selected_cpu
= *mcpu_cpu_opt
;
25360 mcpu_cpu_opt
= &arm_arch_any
;
25363 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25364 if (dyn_mcpu_ext_opt
)
25365 ARM_MERGE_FEATURE_SETS (cpu_variant
, cpu_variant
, *dyn_mcpu_ext_opt
);
25367 autoselect_thumb_from_cpu_variant ();
25369 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
25371 #if defined OBJ_COFF || defined OBJ_ELF
25373 unsigned int flags
= 0;
25375 #if defined OBJ_ELF
25376 flags
= meabi_flags
;
25378 switch (meabi_flags
)
25380 case EF_ARM_EABI_UNKNOWN
:
25382 /* Set the flags in the private structure. */
25383 if (uses_apcs_26
) flags
|= F_APCS26
;
25384 if (support_interwork
) flags
|= F_INTERWORK
;
25385 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
25386 if (pic_code
) flags
|= F_PIC
;
25387 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
25388 flags
|= F_SOFT_FLOAT
;
25390 switch (mfloat_abi_opt
)
25392 case ARM_FLOAT_ABI_SOFT
:
25393 case ARM_FLOAT_ABI_SOFTFP
:
25394 flags
|= F_SOFT_FLOAT
;
25397 case ARM_FLOAT_ABI_HARD
:
25398 if (flags
& F_SOFT_FLOAT
)
25399 as_bad (_("hard-float conflicts with specified fpu"));
25403 /* Using pure-endian doubles (even if soft-float). */
25404 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
25405 flags
|= F_VFP_FLOAT
;
25407 #if defined OBJ_ELF
25408 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
25409 flags
|= EF_ARM_MAVERICK_FLOAT
;
25412 case EF_ARM_EABI_VER4
:
25413 case EF_ARM_EABI_VER5
:
25414 /* No additional flags to set. */
25421 bfd_set_private_flags (stdoutput
, flags
);
25423 /* We have run out flags in the COFF header to encode the
25424 status of ATPCS support, so instead we create a dummy,
25425 empty, debug section called .arm.atpcs. */
25430 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
25434 bfd_set_section_flags
25435 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
25436 bfd_set_section_size (stdoutput
, sec
, 0);
25437 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
25443 /* Record the CPU type as well. */
25444 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
25445 mach
= bfd_mach_arm_iWMMXt2
;
25446 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
25447 mach
= bfd_mach_arm_iWMMXt
;
25448 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
25449 mach
= bfd_mach_arm_XScale
;
25450 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
25451 mach
= bfd_mach_arm_ep9312
;
25452 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
25453 mach
= bfd_mach_arm_5TE
;
25454 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
25456 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25457 mach
= bfd_mach_arm_5T
;
25459 mach
= bfd_mach_arm_5
;
25461 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
25463 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25464 mach
= bfd_mach_arm_4T
;
25466 mach
= bfd_mach_arm_4
;
25468 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
25469 mach
= bfd_mach_arm_3M
;
25470 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
25471 mach
= bfd_mach_arm_3
;
25472 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
25473 mach
= bfd_mach_arm_2a
;
25474 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
25475 mach
= bfd_mach_arm_2
;
25477 mach
= bfd_mach_arm_unknown
;
25479 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
25482 /* Command line processing. */
25485 Invocation line includes a switch not recognized by the base assembler.
25486 See if it's a processor-specific option.
25488 This routine is somewhat complicated by the need for backwards
25489 compatibility (since older releases of gcc can't be changed).
25490 The new options try to make the interface as compatible as
25493 New options (supported) are:
25495 -mcpu=<cpu name> Assemble for selected processor
25496 -march=<architecture name> Assemble for selected architecture
25497 -mfpu=<fpu architecture> Assemble for selected FPU.
25498 -EB/-mbig-endian Big-endian
25499 -EL/-mlittle-endian Little-endian
25500 -k Generate PIC code
25501 -mthumb Start in Thumb mode
25502 -mthumb-interwork Code supports ARM/Thumb interworking
25504 -m[no-]warn-deprecated Warn about deprecated features
25505 -m[no-]warn-syms Warn when symbols match instructions
25507 For now we will also provide support for:
25509 -mapcs-32 32-bit Program counter
25510 -mapcs-26 26-bit Program counter
25511 -macps-float Floats passed in FP registers
25512 -mapcs-reentrant Reentrant code
25514 (sometime these will probably be replaced with -mapcs=<list of options>
25515 and -matpcs=<list of options>)
25517 The remaining options are only supported for back-wards compatibility.
25518 Cpu variants, the arm part is optional:
25519 -m[arm]1 Currently not supported.
25520 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25521 -m[arm]3 Arm 3 processor
25522 -m[arm]6[xx], Arm 6 processors
25523 -m[arm]7[xx][t][[d]m] Arm 7 processors
25524 -m[arm]8[10] Arm 8 processors
25525 -m[arm]9[20][tdmi] Arm 9 processors
25526 -mstrongarm[110[0]] StrongARM processors
25527 -mxscale XScale processors
25528 -m[arm]v[2345[t[e]]] Arm architectures
25529 -mall All (except the ARM1)
25531 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25532 -mfpe-old (No float load/store multiples)
25533 -mvfpxd VFP Single precision
25535 -mno-fpu Disable all floating point instructions
25537 The following CPU names are recognized:
25538 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25539 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25540 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25541 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25542 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25543 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25544 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25548 const char * md_shortopts
= "m:k";
25550 #ifdef ARM_BI_ENDIAN
25551 #define OPTION_EB (OPTION_MD_BASE + 0)
25552 #define OPTION_EL (OPTION_MD_BASE + 1)
25554 #if TARGET_BYTES_BIG_ENDIAN
25555 #define OPTION_EB (OPTION_MD_BASE + 0)
25557 #define OPTION_EL (OPTION_MD_BASE + 1)
25560 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25562 struct option md_longopts
[] =
25565 {"EB", no_argument
, NULL
, OPTION_EB
},
25568 {"EL", no_argument
, NULL
, OPTION_EL
},
25570 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25571 {NULL
, no_argument
, NULL
, 0}
25574 size_t md_longopts_size
= sizeof (md_longopts
);
25576 struct arm_option_table
25578 const char * option
; /* Option name to match. */
25579 const char * help
; /* Help information. */
25580 int * var
; /* Variable to change. */
25581 int value
; /* What to change it to. */
25582 const char * deprecated
; /* If non-null, print this message. */
25585 struct arm_option_table arm_opts
[] =
25587 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25588 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25589 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25590 &support_interwork
, 1, NULL
},
25591 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25592 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25593 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25595 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25596 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25597 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25598 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25601 /* These are recognized by the assembler, but have no affect on code. */
25602 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25603 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25605 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25606 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25607 &warn_on_deprecated
, 0, NULL
},
25608 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25609 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25610 {NULL
, NULL
, NULL
, 0, NULL
}
25613 struct arm_legacy_option_table
25615 const char * option
; /* Option name to match. */
25616 const arm_feature_set
** var
; /* Variable to change. */
25617 const arm_feature_set value
; /* What to change it to. */
25618 const char * deprecated
; /* If non-null, print this message. */
25621 const struct arm_legacy_option_table arm_legacy_opts
[] =
25623 /* DON'T add any new processors to this list -- we want the whole list
25624 to go away... Add them to the processors table instead. */
25625 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25626 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25627 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25628 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25629 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25630 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25631 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25632 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25633 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25634 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25635 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25636 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25637 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25638 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25639 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25640 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25641 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25642 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25643 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25644 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25645 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25646 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25647 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25648 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25649 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25650 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25651 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25652 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25653 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25654 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25655 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25656 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25657 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25658 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25659 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25660 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25661 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25662 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25663 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25664 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25665 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25666 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25667 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25668 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25669 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25670 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25671 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25672 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25673 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25674 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25675 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25676 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25677 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25678 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25679 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25680 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25681 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25682 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25683 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25684 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25685 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25686 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25687 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25688 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25689 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25690 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25691 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25692 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25693 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25694 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25695 N_("use -mcpu=strongarm110")},
25696 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25697 N_("use -mcpu=strongarm1100")},
25698 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25699 N_("use -mcpu=strongarm1110")},
25700 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25701 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25702 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25704 /* Architecture variants -- don't add any more to this list either. */
25705 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25706 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25707 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25708 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25709 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25710 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25711 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25712 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25713 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25714 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25715 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25716 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25717 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25718 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25719 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25720 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25721 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25722 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25724 /* Floating point variants -- don't add any more to this list either. */
25725 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25726 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25727 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25728 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25729 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25731 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25734 struct arm_cpu_option_table
25738 const arm_feature_set value
;
25739 const arm_feature_set ext
;
25740 /* For some CPUs we assume an FPU unless the user explicitly sets
25742 const arm_feature_set default_fpu
;
25743 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25745 const char * canonical_name
;
25748 /* This list should, at a minimum, contain all the cpu names
25749 recognized by GCC. */
25750 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
25752 static const struct arm_cpu_option_table arm_cpus
[] =
25754 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
25757 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
25760 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
25763 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
25766 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
25769 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
25772 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
25775 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
25778 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
25781 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
25784 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
25787 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
25790 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
25793 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
25796 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
25799 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
25802 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
25805 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
25808 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
25811 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
25814 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
25817 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
25820 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
25823 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
25826 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
25829 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
25832 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
25835 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
25838 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
25841 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
25844 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
25847 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
25850 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
25853 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
25856 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
25859 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
25862 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
25865 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
25868 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
25871 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
25874 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
25877 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
25880 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
25883 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
25886 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
25889 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
25893 /* For V5 or later processors we default to using VFP; but the user
25894 should really set the FPU type explicitly. */
25895 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
25898 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
25901 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
25904 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
25907 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
25910 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
25913 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
25916 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
25919 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
25922 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
25925 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
25928 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
25931 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
25934 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
25937 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
25940 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
25943 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
25946 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
25949 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
25952 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
25955 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
25958 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
25961 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
25964 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
25967 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
25970 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
25973 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
25976 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
25979 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
25982 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
25985 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
25988 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
25991 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
25994 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
25997 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
26000 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
26003 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
26004 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26006 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
26008 FPU_ARCH_NEON_VFP_V4
),
26009 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
26010 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26011 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26012 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
26013 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26014 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26015 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
26017 FPU_ARCH_NEON_VFP_V4
),
26018 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
26020 FPU_ARCH_NEON_VFP_V4
),
26021 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
26023 FPU_ARCH_NEON_VFP_V4
),
26024 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
26025 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26026 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26027 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
26028 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26029 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26030 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
26031 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26032 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26033 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
26034 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26035 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26036 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
26037 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26038 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26039 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
26040 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26041 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26042 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
26043 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26044 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26045 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
26046 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26047 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26048 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
26051 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
26053 FPU_ARCH_VFP_V3D16
),
26054 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
26055 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26057 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
26058 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26059 FPU_ARCH_VFP_V3D16
),
26060 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
26061 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26062 FPU_ARCH_VFP_V3D16
),
26063 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
26064 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26065 FPU_ARCH_NEON_VFP_ARMV8
),
26066 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
26067 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26069 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
26072 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
26075 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
26078 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
26081 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
26084 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
26087 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
26090 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
26091 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26092 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26094 /* ??? XSCALE is really an architecture. */
26095 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
26099 /* ??? iwmmxt is not a processor. */
26100 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
26103 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
26106 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
26111 ARM_CPU_OPT ("ep9312", "ARM920T",
26112 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
26113 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
26115 /* Marvell processors. */
26116 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
26117 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26118 FPU_ARCH_VFP_V3D16
),
26119 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
26120 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26121 FPU_ARCH_NEON_VFP_V4
),
26123 /* APM X-Gene family. */
26124 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
26126 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26127 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
26128 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26129 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26131 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
26135 struct arm_arch_option_table
26139 const arm_feature_set value
;
26140 const arm_feature_set default_fpu
;
26143 /* This list should, at a minimum, contain all the architecture names
26144 recognized by GCC. */
26145 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
26147 static const struct arm_arch_option_table arm_archs
[] =
26149 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
26150 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
26151 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
26152 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
26153 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
26154 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
26155 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
26156 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
26157 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
26158 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
26159 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
26160 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
26161 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
26162 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
26163 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
26164 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
26165 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
26166 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
26167 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
26168 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
26169 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
26170 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
26171 kept to preserve existing behaviour. */
26172 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
26173 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
26174 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
26175 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
26176 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
26177 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
26178 kept to preserve existing behaviour. */
26179 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
26180 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
26181 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
26182 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
26183 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
26184 /* The official spelling of the ARMv7 profile variants is the dashed form.
26185 Accept the non-dashed form for compatibility with old toolchains. */
26186 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
26187 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
26188 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
26189 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26190 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
26191 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
26192 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26193 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
26194 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
26195 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
26196 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
26197 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
26198 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
26199 ARM_ARCH_OPT ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
),
26200 ARM_ARCH_OPT ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
),
26201 ARM_ARCH_OPT ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
),
26202 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
26203 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
26204 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
26205 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26207 #undef ARM_ARCH_OPT
26209 /* ISA extensions in the co-processor and main instruction set space. */
26211 struct arm_option_extension_value_table
26215 const arm_feature_set merge_value
;
26216 const arm_feature_set clear_value
;
26217 /* List of architectures for which an extension is available. ARM_ARCH_NONE
26218 indicates that an extension is available for all architectures while
26219 ARM_ANY marks an empty entry. */
26220 const arm_feature_set allowed_archs
[2];
26223 /* The following table must be in alphabetical order with a NULL last entry. */
26225 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
26226 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
26228 static const struct arm_option_extension_value_table arm_extensions
[] =
26230 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26231 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26232 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
26233 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
26234 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26235 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
26236 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
26238 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26239 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26240 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
26241 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
26242 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26243 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26246 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26247 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26248 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
26249 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
26250 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
26251 Thumb divide instruction. Due to this having the same name as the
26252 previous entry, this will be ignored when doing command-line parsing and
26253 only considered by build attribute selection code. */
26254 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
26255 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
26256 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
26257 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
26258 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
26259 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
26260 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
26261 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
26262 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
26263 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
26264 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
26265 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
26266 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
26267 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
26268 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
26269 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
26270 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
26271 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
26272 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26273 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
26274 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
26275 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26276 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
26277 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
26278 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26279 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26280 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26281 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
26282 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26283 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
26284 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
26285 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26286 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
26288 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
26289 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26290 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
26291 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
26292 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
26296 /* ISA floating-point and Advanced SIMD extensions. */
26297 struct arm_option_fpu_value_table
26300 const arm_feature_set value
;
26303 /* This list should, at a minimum, contain all the fpu names
26304 recognized by GCC. */
26305 static const struct arm_option_fpu_value_table arm_fpus
[] =
26307 {"softfpa", FPU_NONE
},
26308 {"fpe", FPU_ARCH_FPE
},
26309 {"fpe2", FPU_ARCH_FPE
},
26310 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
26311 {"fpa", FPU_ARCH_FPA
},
26312 {"fpa10", FPU_ARCH_FPA
},
26313 {"fpa11", FPU_ARCH_FPA
},
26314 {"arm7500fe", FPU_ARCH_FPA
},
26315 {"softvfp", FPU_ARCH_VFP
},
26316 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
26317 {"vfp", FPU_ARCH_VFP_V2
},
26318 {"vfp9", FPU_ARCH_VFP_V2
},
26319 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
26320 {"vfp10", FPU_ARCH_VFP_V2
},
26321 {"vfp10-r0", FPU_ARCH_VFP_V1
},
26322 {"vfpxd", FPU_ARCH_VFP_V1xD
},
26323 {"vfpv2", FPU_ARCH_VFP_V2
},
26324 {"vfpv3", FPU_ARCH_VFP_V3
},
26325 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
26326 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
26327 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
26328 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
26329 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
26330 {"arm1020t", FPU_ARCH_VFP_V1
},
26331 {"arm1020e", FPU_ARCH_VFP_V2
},
26332 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
26333 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
26334 {"maverick", FPU_ARCH_MAVERICK
},
26335 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26336 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26337 {"neon-fp16", FPU_ARCH_NEON_FP16
},
26338 {"vfpv4", FPU_ARCH_VFP_V4
},
26339 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
26340 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
26341 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
26342 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
26343 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
26344 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
26345 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
26346 {"crypto-neon-fp-armv8",
26347 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
26348 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
26349 {"crypto-neon-fp-armv8.1",
26350 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
26351 {NULL
, ARM_ARCH_NONE
}
26354 struct arm_option_value_table
26360 static const struct arm_option_value_table arm_float_abis
[] =
26362 {"hard", ARM_FLOAT_ABI_HARD
},
26363 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
26364 {"soft", ARM_FLOAT_ABI_SOFT
},
26369 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
26370 static const struct arm_option_value_table arm_eabis
[] =
26372 {"gnu", EF_ARM_EABI_UNKNOWN
},
26373 {"4", EF_ARM_EABI_VER4
},
26374 {"5", EF_ARM_EABI_VER5
},
26379 struct arm_long_option_table
26381 const char * option
; /* Substring to match. */
26382 const char * help
; /* Help information. */
26383 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
26384 const char * deprecated
; /* If non-null, print this message. */
26388 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
26389 arm_feature_set
**ext_set_p
)
26391 /* We insist on extensions being specified in alphabetical order, and with
26392 extensions being added before being removed. We achieve this by having
26393 the global ARM_EXTENSIONS table in alphabetical order, and using the
26394 ADDING_VALUE variable to indicate whether we are adding an extension (1)
26395 or removing it (0) and only allowing it to change in the order
26397 const struct arm_option_extension_value_table
* opt
= NULL
;
26398 const arm_feature_set arm_any
= ARM_ANY
;
26399 int adding_value
= -1;
26403 *ext_set_p
= XNEW (arm_feature_set
);
26404 **ext_set_p
= arm_arch_none
;
26407 while (str
!= NULL
&& *str
!= 0)
26414 as_bad (_("invalid architectural extension"));
26419 ext
= strchr (str
, '+');
26424 len
= strlen (str
);
26426 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
26428 if (adding_value
!= 0)
26431 opt
= arm_extensions
;
26439 if (adding_value
== -1)
26442 opt
= arm_extensions
;
26444 else if (adding_value
!= 1)
26446 as_bad (_("must specify extensions to add before specifying "
26447 "those to remove"));
26454 as_bad (_("missing architectural extension"));
26458 gas_assert (adding_value
!= -1);
26459 gas_assert (opt
!= NULL
);
26461 /* Scan over the options table trying to find an exact match. */
26462 for (; opt
->name
!= NULL
; opt
++)
26463 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26465 int i
, nb_allowed_archs
=
26466 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
26467 /* Check we can apply the extension to this architecture. */
26468 for (i
= 0; i
< nb_allowed_archs
; i
++)
26471 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26473 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
26476 if (i
== nb_allowed_archs
)
26478 as_bad (_("extension does not apply to the base architecture"));
26482 /* Add or remove the extension. */
26484 ARM_MERGE_FEATURE_SETS (**ext_set_p
, **ext_set_p
,
26487 ARM_CLEAR_FEATURE (**ext_set_p
, **ext_set_p
, opt
->clear_value
);
26489 /* Allowing Thumb division instructions for ARMv7 in autodetection
26490 rely on this break so that duplicate extensions (extensions
26491 with the same name as a previous extension in the list) are not
26492 considered for command-line parsing. */
26496 if (opt
->name
== NULL
)
26498 /* Did we fail to find an extension because it wasn't specified in
26499 alphabetical order, or because it does not exist? */
26501 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26502 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26505 if (opt
->name
== NULL
)
26506 as_bad (_("unknown architectural extension `%s'"), str
);
26508 as_bad (_("architectural extensions must be specified in "
26509 "alphabetical order"));
26515 /* We should skip the extension we've just matched the next time
26527 arm_parse_cpu (const char *str
)
26529 const struct arm_cpu_option_table
*opt
;
26530 const char *ext
= strchr (str
, '+');
26536 len
= strlen (str
);
26540 as_bad (_("missing cpu name `%s'"), str
);
26544 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
26545 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26547 mcpu_cpu_opt
= &opt
->value
;
26548 if (!dyn_mcpu_ext_opt
)
26549 dyn_mcpu_ext_opt
= XNEW (arm_feature_set
);
26550 *dyn_mcpu_ext_opt
= opt
->ext
;
26551 mcpu_fpu_opt
= &opt
->default_fpu
;
26552 if (opt
->canonical_name
)
26554 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
26555 strcpy (selected_cpu_name
, opt
->canonical_name
);
26561 if (len
>= sizeof selected_cpu_name
)
26562 len
= (sizeof selected_cpu_name
) - 1;
26564 for (i
= 0; i
< len
; i
++)
26565 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26566 selected_cpu_name
[i
] = 0;
26570 return arm_parse_extension (ext
, mcpu_cpu_opt
, &dyn_mcpu_ext_opt
);
26575 as_bad (_("unknown cpu `%s'"), str
);
26580 arm_parse_arch (const char *str
)
26582 const struct arm_arch_option_table
*opt
;
26583 const char *ext
= strchr (str
, '+');
26589 len
= strlen (str
);
26593 as_bad (_("missing architecture name `%s'"), str
);
26597 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
26598 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26600 march_cpu_opt
= &opt
->value
;
26601 march_fpu_opt
= &opt
->default_fpu
;
26602 strcpy (selected_cpu_name
, opt
->name
);
26605 return arm_parse_extension (ext
, march_cpu_opt
, &dyn_march_ext_opt
);
26610 as_bad (_("unknown architecture `%s'\n"), str
);
26615 arm_parse_fpu (const char * str
)
26617 const struct arm_option_fpu_value_table
* opt
;
26619 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26620 if (streq (opt
->name
, str
))
26622 mfpu_opt
= &opt
->value
;
26626 as_bad (_("unknown floating point format `%s'\n"), str
);
26631 arm_parse_float_abi (const char * str
)
26633 const struct arm_option_value_table
* opt
;
26635 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
26636 if (streq (opt
->name
, str
))
26638 mfloat_abi_opt
= opt
->value
;
26642 as_bad (_("unknown floating point abi `%s'\n"), str
);
26648 arm_parse_eabi (const char * str
)
26650 const struct arm_option_value_table
*opt
;
26652 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
26653 if (streq (opt
->name
, str
))
26655 meabi_flags
= opt
->value
;
26658 as_bad (_("unknown EABI `%s'\n"), str
);
26664 arm_parse_it_mode (const char * str
)
26666 bfd_boolean ret
= TRUE
;
26668 if (streq ("arm", str
))
26669 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
26670 else if (streq ("thumb", str
))
26671 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
26672 else if (streq ("always", str
))
26673 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
26674 else if (streq ("never", str
))
26675 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
26678 as_bad (_("unknown implicit IT mode `%s', should be "\
26679 "arm, thumb, always, or never."), str
);
26687 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
26689 codecomposer_syntax
= TRUE
;
26690 arm_comment_chars
[0] = ';';
26691 arm_line_separator_chars
[0] = 0;
26695 struct arm_long_option_table arm_long_opts
[] =
26697 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
26698 arm_parse_cpu
, NULL
},
26699 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
26700 arm_parse_arch
, NULL
},
26701 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
26702 arm_parse_fpu
, NULL
},
26703 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
26704 arm_parse_float_abi
, NULL
},
26706 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
26707 arm_parse_eabi
, NULL
},
26709 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
26710 arm_parse_it_mode
, NULL
},
26711 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
26712 arm_ccs_mode
, NULL
},
26713 {NULL
, NULL
, 0, NULL
}
26717 md_parse_option (int c
, const char * arg
)
26719 struct arm_option_table
*opt
;
26720 const struct arm_legacy_option_table
*fopt
;
26721 struct arm_long_option_table
*lopt
;
26727 target_big_endian
= 1;
26733 target_big_endian
= 0;
26737 case OPTION_FIX_V4BX
:
26742 /* Listing option. Just ignore these, we don't support additional
26747 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26749 if (c
== opt
->option
[0]
26750 && ((arg
== NULL
&& opt
->option
[1] == 0)
26751 || streq (arg
, opt
->option
+ 1)))
26753 /* If the option is deprecated, tell the user. */
26754 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
26755 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26756 arg
? arg
: "", _(opt
->deprecated
));
26758 if (opt
->var
!= NULL
)
26759 *opt
->var
= opt
->value
;
26765 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
26767 if (c
== fopt
->option
[0]
26768 && ((arg
== NULL
&& fopt
->option
[1] == 0)
26769 || streq (arg
, fopt
->option
+ 1)))
26771 /* If the option is deprecated, tell the user. */
26772 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
26773 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26774 arg
? arg
: "", _(fopt
->deprecated
));
26776 if (fopt
->var
!= NULL
)
26777 *fopt
->var
= &fopt
->value
;
26783 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26785 /* These options are expected to have an argument. */
26786 if (c
== lopt
->option
[0]
26788 && strncmp (arg
, lopt
->option
+ 1,
26789 strlen (lopt
->option
+ 1)) == 0)
26791 /* If the option is deprecated, tell the user. */
26792 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
26793 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
26794 _(lopt
->deprecated
));
26796 /* Call the sup-option parser. */
26797 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
26808 md_show_usage (FILE * fp
)
26810 struct arm_option_table
*opt
;
26811 struct arm_long_option_table
*lopt
;
26813 fprintf (fp
, _(" ARM-specific assembler options:\n"));
26815 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26816 if (opt
->help
!= NULL
)
26817 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
26819 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26820 if (lopt
->help
!= NULL
)
26821 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
26825 -EB assemble code for a big-endian cpu\n"));
26830 -EL assemble code for a little-endian cpu\n"));
26834 --fix-v4bx Allow BX in ARMv4 code\n"));
26842 arm_feature_set flags
;
26843 } cpu_arch_ver_table
;
26845 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
26846 chronologically for architectures, with an exception for ARMv6-M and
26847 ARMv6S-M due to legacy reasons. No new architecture should have a
26848 special case. This allows for build attribute selection results to be
26849 stable when new architectures are added. */
26850 static const cpu_arch_ver_table cpu_arch_ver
[] =
26857 {1, ARM_ARCH_V4xM
},
26859 {2, ARM_ARCH_V4TxM
},
26861 {3, ARM_ARCH_V5xM
},
26863 {3, ARM_ARCH_V5TxM
},
26865 {4, ARM_ARCH_V5TExP
},
26866 {4, ARM_ARCH_V5TE
},
26867 {5, ARM_ARCH_V5TEJ
},
26870 {7, ARM_ARCH_V6KZ
},
26872 {8, ARM_ARCH_V6T2
},
26873 {8, ARM_ARCH_V6KT2
},
26874 {8, ARM_ARCH_V6ZT2
},
26875 {8, ARM_ARCH_V6KZT2
},
26877 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
26878 always selected build attributes to match those of ARMv6-M
26879 (resp. ARMv6S-M). However, due to these architectures being a strict
26880 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
26881 would be selected when fully respecting chronology of architectures.
26882 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
26883 move them before ARMv7 architectures. */
26884 {11, ARM_ARCH_V6M
},
26885 {12, ARM_ARCH_V6SM
},
26888 {10, ARM_ARCH_V7A
},
26889 {10, ARM_ARCH_V7R
},
26890 {10, ARM_ARCH_V7M
},
26891 {10, ARM_ARCH_V7VE
},
26892 {13, ARM_ARCH_V7EM
},
26893 {14, ARM_ARCH_V8A
},
26894 {14, ARM_ARCH_V8_1A
},
26895 {14, ARM_ARCH_V8_2A
},
26896 {14, ARM_ARCH_V8_3A
},
26897 {16, ARM_ARCH_V8M_BASE
},
26898 {17, ARM_ARCH_V8M_MAIN
},
26899 {15, ARM_ARCH_V8R
},
26900 {16, ARM_ARCH_V8_4A
},
26901 {-1, ARM_ARCH_NONE
}
26904 /* Set an attribute if it has not already been set by the user. */
26907 aeabi_set_attribute_int (int tag
, int value
)
26910 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26911 || !attributes_set_explicitly
[tag
])
26912 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
26916 aeabi_set_attribute_string (int tag
, const char *value
)
26919 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26920 || !attributes_set_explicitly
[tag
])
26921 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
26924 /* Return whether features in the *NEEDED feature set are available via
26925 extensions for the architecture whose feature set is *ARCH_FSET. */
26928 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
26929 const arm_feature_set
*needed
)
26931 int i
, nb_allowed_archs
;
26932 arm_feature_set ext_fset
;
26933 const struct arm_option_extension_value_table
*opt
;
26935 ext_fset
= arm_arch_none
;
26936 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26938 /* Extension does not provide any feature we need. */
26939 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
26943 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
26944 for (i
= 0; i
< nb_allowed_archs
; i
++)
26947 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
26950 /* Extension is available, add it. */
26951 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
26952 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
26956 /* Can we enable all features in *needed? */
26957 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
26960 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
26961 a given architecture feature set *ARCH_EXT_FSET including extension feature
26962 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
26963 - if true, check for an exact match of the architecture modulo extensions;
26964 - otherwise, select build attribute value of the first superset
26965 architecture released so that results remains stable when new architectures
26967 For -march/-mcpu=all the build attribute value of the most featureful
26968 architecture is returned. Tag_CPU_arch_profile result is returned in
26972 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
26973 const arm_feature_set
*ext_fset
,
26974 char *profile
, int exact_match
)
26976 arm_feature_set arch_fset
;
26977 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
26979 /* Select most featureful architecture with all its extensions if building
26980 for -march=all as the feature sets used to set build attributes. */
26981 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
26983 /* Force revisiting of decision for each new architecture. */
26984 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8M_MAIN
);
26986 return TAG_CPU_ARCH_V8
;
26989 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
26991 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
26993 arm_feature_set known_arch_fset
;
26995 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
26998 /* Base architecture match user-specified architecture and
26999 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
27000 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
27005 /* Base architecture match user-specified architecture only
27006 (eg. ARMv6-M in the same case as above). Record it in case we
27007 find a match with above condition. */
27008 else if (p_ver_ret
== NULL
27009 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
27015 /* Architecture has all features wanted. */
27016 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
27018 arm_feature_set added_fset
;
27020 /* Compute features added by this architecture over the one
27021 recorded in p_ver_ret. */
27022 if (p_ver_ret
!= NULL
)
27023 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
27025 /* First architecture that match incl. with extensions, or the
27026 only difference in features over the recorded match is
27027 features that were optional and are now mandatory. */
27028 if (p_ver_ret
== NULL
27029 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
27035 else if (p_ver_ret
== NULL
)
27037 arm_feature_set needed_ext_fset
;
27039 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
27041 /* Architecture has all features needed when using some
27042 extensions. Record it and continue searching in case there
27043 exist an architecture providing all needed features without
27044 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
27046 if (have_ext_for_needed_feat_p (&known_arch_fset
,
27053 if (p_ver_ret
== NULL
)
27057 /* Tag_CPU_arch_profile. */
27058 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
27059 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
27060 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
27061 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
27063 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
27065 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
27069 return p_ver_ret
->val
;
27072 /* Set the public EABI object attributes. */
27075 aeabi_set_public_attributes (void)
27080 int fp16_optional
= 0;
27081 int skip_exact_match
= 0;
27082 arm_feature_set flags
, flags_arch
, flags_ext
;
27084 /* Autodetection mode, choose the architecture based the instructions
27086 if (no_cpu_selected ())
27088 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
27090 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
27091 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
27093 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
27094 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
27096 /* Code run during relaxation relies on selected_cpu being set. */
27097 selected_cpu
= flags
;
27099 /* Otherwise, choose the architecture based on the capabilities of the
27102 flags
= selected_cpu
;
27103 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
27105 /* Allow the user to override the reported architecture. */
27108 ARM_CLEAR_FEATURE (flags_arch
, *object_arch
, fpu_any
);
27109 flags_ext
= arm_arch_none
;
27113 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
27114 flags_ext
= dyn_mcpu_ext_opt
? *dyn_mcpu_ext_opt
: arm_arch_none
;
27115 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
27118 /* When this function is run again after relaxation has happened there is no
27119 way to determine whether an architecture or CPU was specified by the user:
27120 - selected_cpu is set above for relaxation to work;
27121 - march_cpu_opt is not set if only -mcpu or .cpu is used;
27122 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
27123 Therefore, if not in -march=all case we first try an exact match and fall
27124 back to autodetection. */
27125 if (!skip_exact_match
)
27126 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
27128 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
27130 as_bad (_("no architecture contains all the instructions used\n"));
27132 /* Tag_CPU_name. */
27133 if (selected_cpu_name
[0])
27137 q
= selected_cpu_name
;
27138 if (strncmp (q
, "armv", 4) == 0)
27143 for (i
= 0; q
[i
]; i
++)
27144 q
[i
] = TOUPPER (q
[i
]);
27146 aeabi_set_attribute_string (Tag_CPU_name
, q
);
27149 /* Tag_CPU_arch. */
27150 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
27152 /* Tag_CPU_arch_profile. */
27153 if (profile
!= '\0')
27154 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
27156 /* Tag_DSP_extension. */
27157 if (dyn_mcpu_ext_opt
&& ARM_CPU_HAS_FEATURE (*dyn_mcpu_ext_opt
, arm_ext_dsp
))
27158 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
27160 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
27161 /* Tag_ARM_ISA_use. */
27162 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
27163 || ARM_FEATURE_ZERO (flags_arch
))
27164 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
27166 /* Tag_THUMB_ISA_use. */
27167 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
27168 || ARM_FEATURE_ZERO (flags_arch
))
27172 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
27173 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
27175 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
27179 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
27182 /* Tag_VFP_arch. */
27183 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
27184 aeabi_set_attribute_int (Tag_VFP_arch
,
27185 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
27187 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
27188 aeabi_set_attribute_int (Tag_VFP_arch
,
27189 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
27191 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
27194 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
27196 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
27198 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
27201 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
27202 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
27203 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
27204 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
27205 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
27207 /* Tag_ABI_HardFP_use. */
27208 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
27209 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
27210 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
27212 /* Tag_WMMX_arch. */
27213 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
27214 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
27215 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
27216 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
27218 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
27219 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
27220 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
27221 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
27222 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
27223 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
27225 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
27227 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
27231 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
27236 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
27237 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
27238 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
27242 We set Tag_DIV_use to two when integer divide instructions have been used
27243 in ARM state, or when Thumb integer divide instructions have been used,
27244 but we have no architecture profile set, nor have we any ARM instructions.
27246 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
27247 by the base architecture.
27249 For new architectures we will have to check these tests. */
27250 gas_assert (arch
<= TAG_CPU_ARCH_V8M_MAIN
);
27251 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
27252 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
27253 aeabi_set_attribute_int (Tag_DIV_use
, 0);
27254 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
27255 || (profile
== '\0'
27256 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
27257 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
27258 aeabi_set_attribute_int (Tag_DIV_use
, 2);
27260 /* Tag_MP_extension_use. */
27261 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
27262 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
27264 /* Tag Virtualization_use. */
27265 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
27267 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
27270 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
27273 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
27274 finished and free extension feature bits which will not be used anymore. */
27277 arm_md_post_relax (void)
27279 aeabi_set_public_attributes ();
27280 XDELETE (dyn_mcpu_ext_opt
);
27281 dyn_mcpu_ext_opt
= NULL
;
27282 XDELETE (dyn_march_ext_opt
);
27283 dyn_march_ext_opt
= NULL
;
27286 /* Add the default contents for the .ARM.attributes section. */
27291 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
27294 aeabi_set_public_attributes ();
27296 #endif /* OBJ_ELF */
27298 /* Parse a .cpu directive. */
27301 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
27303 const struct arm_cpu_option_table
*opt
;
27307 name
= input_line_pointer
;
27308 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27309 input_line_pointer
++;
27310 saved_char
= *input_line_pointer
;
27311 *input_line_pointer
= 0;
27313 /* Skip the first "all" entry. */
27314 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
27315 if (streq (opt
->name
, name
))
27317 mcpu_cpu_opt
= &opt
->value
;
27318 if (!dyn_mcpu_ext_opt
)
27319 dyn_mcpu_ext_opt
= XNEW (arm_feature_set
);
27320 *dyn_mcpu_ext_opt
= opt
->ext
;
27321 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
27322 if (opt
->canonical_name
)
27323 strcpy (selected_cpu_name
, opt
->canonical_name
);
27327 for (i
= 0; opt
->name
[i
]; i
++)
27328 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
27330 selected_cpu_name
[i
] = 0;
27332 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
27333 if (dyn_mcpu_ext_opt
)
27334 ARM_MERGE_FEATURE_SETS (cpu_variant
, cpu_variant
, *dyn_mcpu_ext_opt
);
27335 *input_line_pointer
= saved_char
;
27336 demand_empty_rest_of_line ();
27339 as_bad (_("unknown cpu `%s'"), name
);
27340 *input_line_pointer
= saved_char
;
27341 ignore_rest_of_line ();
27344 /* Parse a .arch directive. */
27347 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
27349 const struct arm_arch_option_table
*opt
;
27353 name
= input_line_pointer
;
27354 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27355 input_line_pointer
++;
27356 saved_char
= *input_line_pointer
;
27357 *input_line_pointer
= 0;
27359 /* Skip the first "all" entry. */
27360 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27361 if (streq (opt
->name
, name
))
27363 mcpu_cpu_opt
= &opt
->value
;
27364 XDELETE (dyn_mcpu_ext_opt
);
27365 dyn_mcpu_ext_opt
= NULL
;
27366 selected_cpu
= *mcpu_cpu_opt
;
27367 strcpy (selected_cpu_name
, opt
->name
);
27368 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, *mfpu_opt
);
27369 *input_line_pointer
= saved_char
;
27370 demand_empty_rest_of_line ();
27374 as_bad (_("unknown architecture `%s'\n"), name
);
27375 *input_line_pointer
= saved_char
;
27376 ignore_rest_of_line ();
27379 /* Parse a .object_arch directive. */
27382 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
27384 const struct arm_arch_option_table
*opt
;
27388 name
= input_line_pointer
;
27389 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27390 input_line_pointer
++;
27391 saved_char
= *input_line_pointer
;
27392 *input_line_pointer
= 0;
27394 /* Skip the first "all" entry. */
27395 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27396 if (streq (opt
->name
, name
))
27398 object_arch
= &opt
->value
;
27399 *input_line_pointer
= saved_char
;
27400 demand_empty_rest_of_line ();
27404 as_bad (_("unknown architecture `%s'\n"), name
);
27405 *input_line_pointer
= saved_char
;
27406 ignore_rest_of_line ();
27409 /* Parse a .arch_extension directive. */
27412 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
27414 const struct arm_option_extension_value_table
*opt
;
27415 const arm_feature_set arm_any
= ARM_ANY
;
27418 int adding_value
= 1;
27420 name
= input_line_pointer
;
27421 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27422 input_line_pointer
++;
27423 saved_char
= *input_line_pointer
;
27424 *input_line_pointer
= 0;
27426 if (strlen (name
) >= 2
27427 && strncmp (name
, "no", 2) == 0)
27433 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27434 if (streq (opt
->name
, name
))
27436 int i
, nb_allowed_archs
=
27437 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
27438 for (i
= 0; i
< nb_allowed_archs
; i
++)
27441 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
27443 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *mcpu_cpu_opt
))
27447 if (i
== nb_allowed_archs
)
27449 as_bad (_("architectural extension `%s' is not allowed for the "
27450 "current base architecture"), name
);
27454 if (!dyn_mcpu_ext_opt
)
27456 dyn_mcpu_ext_opt
= XNEW (arm_feature_set
);
27457 *dyn_mcpu_ext_opt
= arm_arch_none
;
27460 ARM_MERGE_FEATURE_SETS (*dyn_mcpu_ext_opt
, *dyn_mcpu_ext_opt
,
27463 ARM_CLEAR_FEATURE (*dyn_mcpu_ext_opt
, *dyn_mcpu_ext_opt
,
27466 ARM_MERGE_FEATURE_SETS (selected_cpu
, *mcpu_cpu_opt
, *dyn_mcpu_ext_opt
);
27467 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, *mfpu_opt
);
27468 *input_line_pointer
= saved_char
;
27469 demand_empty_rest_of_line ();
27470 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
27471 on this return so that duplicate extensions (extensions with the
27472 same name as a previous extension in the list) are not considered
27473 for command-line parsing. */
27477 if (opt
->name
== NULL
)
27478 as_bad (_("unknown architecture extension `%s'\n"), name
);
27480 *input_line_pointer
= saved_char
;
27481 ignore_rest_of_line ();
27484 /* Parse a .fpu directive. */
27487 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
27489 const struct arm_option_fpu_value_table
*opt
;
27493 name
= input_line_pointer
;
27494 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27495 input_line_pointer
++;
27496 saved_char
= *input_line_pointer
;
27497 *input_line_pointer
= 0;
27499 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
27500 if (streq (opt
->name
, name
))
27502 mfpu_opt
= &opt
->value
;
27503 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
27504 if (dyn_mcpu_ext_opt
)
27505 ARM_MERGE_FEATURE_SETS (cpu_variant
, cpu_variant
, *dyn_mcpu_ext_opt
);
27506 *input_line_pointer
= saved_char
;
27507 demand_empty_rest_of_line ();
27511 as_bad (_("unknown floating point format `%s'\n"), name
);
27512 *input_line_pointer
= saved_char
;
27513 ignore_rest_of_line ();
27516 /* Copy symbol information. */
27519 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
27521 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
27525 /* Given a symbolic attribute NAME, return the proper integer value.
27526 Returns -1 if the attribute is not known. */
27529 arm_convert_symbolic_attribute (const char *name
)
27531 static const struct
27536 attribute_table
[] =
27538 /* When you modify this table you should
27539 also modify the list in doc/c-arm.texi. */
27540 #define T(tag) {#tag, tag}
27541 T (Tag_CPU_raw_name
),
27544 T (Tag_CPU_arch_profile
),
27545 T (Tag_ARM_ISA_use
),
27546 T (Tag_THUMB_ISA_use
),
27550 T (Tag_Advanced_SIMD_arch
),
27551 T (Tag_PCS_config
),
27552 T (Tag_ABI_PCS_R9_use
),
27553 T (Tag_ABI_PCS_RW_data
),
27554 T (Tag_ABI_PCS_RO_data
),
27555 T (Tag_ABI_PCS_GOT_use
),
27556 T (Tag_ABI_PCS_wchar_t
),
27557 T (Tag_ABI_FP_rounding
),
27558 T (Tag_ABI_FP_denormal
),
27559 T (Tag_ABI_FP_exceptions
),
27560 T (Tag_ABI_FP_user_exceptions
),
27561 T (Tag_ABI_FP_number_model
),
27562 T (Tag_ABI_align_needed
),
27563 T (Tag_ABI_align8_needed
),
27564 T (Tag_ABI_align_preserved
),
27565 T (Tag_ABI_align8_preserved
),
27566 T (Tag_ABI_enum_size
),
27567 T (Tag_ABI_HardFP_use
),
27568 T (Tag_ABI_VFP_args
),
27569 T (Tag_ABI_WMMX_args
),
27570 T (Tag_ABI_optimization_goals
),
27571 T (Tag_ABI_FP_optimization_goals
),
27572 T (Tag_compatibility
),
27573 T (Tag_CPU_unaligned_access
),
27574 T (Tag_FP_HP_extension
),
27575 T (Tag_VFP_HP_extension
),
27576 T (Tag_ABI_FP_16bit_format
),
27577 T (Tag_MPextension_use
),
27579 T (Tag_nodefaults
),
27580 T (Tag_also_compatible_with
),
27581 T (Tag_conformance
),
27583 T (Tag_Virtualization_use
),
27584 T (Tag_DSP_extension
),
27585 /* We deliberately do not include Tag_MPextension_use_legacy. */
27593 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
27594 if (streq (name
, attribute_table
[i
].name
))
27595 return attribute_table
[i
].tag
;
27600 /* Apply sym value for relocations only in the case that they are for
27601 local symbols in the same segment as the fixup and you have the
27602 respective architectural feature for blx and simple switches. */
27605 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
27608 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27609 /* PR 17444: If the local symbol is in a different section then a reloc
27610 will always be generated for it, so applying the symbol value now
27611 will result in a double offset being stored in the relocation. */
27612 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
27613 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
27615 switch (fixP
->fx_r_type
)
27617 case BFD_RELOC_ARM_PCREL_BLX
:
27618 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27619 if (ARM_IS_FUNC (fixP
->fx_addsy
))
27623 case BFD_RELOC_ARM_PCREL_CALL
:
27624 case BFD_RELOC_THUMB_PCREL_BLX
:
27625 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
27636 #endif /* OBJ_ELF */