1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994, 95, 96, 1997 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
35 /* ??? This is currently unused. */
37 #define internalError() \
38 as_fatal ("ARM Internal Error, line %d, %s", __LINE__, __FILE__)
40 #define internalError() as_fatal ("ARM Internal Error")
43 /* Types of processor to assemble for. */
44 #define ARM_1 0x00000001
45 #define ARM_2 0x00000002
46 #define ARM_3 0x00000004
48 #define ARM_6 0x00000008
49 #define ARM_7 ARM_6 /* same core instruction set */
50 #define ARM_CPU_MASK 0x0000000f
52 /* The following bitmasks control CPU extensions (ARM7 onwards): */
53 #define ARM_LONGMUL 0x00000010 /* allow long multiplies */
54 #define ARM_ARCH4 0x00000020
55 #define ARM_THUMB ARM_ARCH4
57 /* Some useful combinations: */
58 #define ARM_ANY 0x00ffffff
59 #define ARM_2UP 0x00fffffe
60 #define ARM_ALL ARM_2UP /* Not arm1 only */
61 #define ARM_3UP 0x00fffffc
62 #define ARM_6UP 0x00fffff8 /* Includes ARM7 */
64 #define FPU_CORE 0x80000000
65 #define FPU_FPA10 0x40000000
66 #define FPU_FPA11 0x40000000
69 /* Some useful combinations */
70 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY */
71 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core */
76 #define CPU_DEFAULT (ARM_7 | ARM_THUMB)
78 #define CPU_DEFAULT ARM_ALL
83 #define FPU_DEFAULT FPU_ALL
86 static unsigned long cpu_variant
= CPU_DEFAULT
| FPU_DEFAULT
;
89 /* Flags stored in private area of BFD COFF structure */
90 static boolean uses_apcs_26
= false;
93 /* This array holds the chars that always start a comment. If the
94 pre-processor is disabled, these aren't very useful */
95 CONST
char comment_chars
[] = "@";
97 /* This array holds the chars that only start a comment at the beginning of
98 a line. If the line seems to have the form '# 123 filename'
99 .line and .file directives will appear in the pre-processed output */
100 /* Note that input_file.c hand checks for '#' at the beginning of the
101 first line of the input file. This is because the compiler outputs
102 #NO_APP at the beginning of its output. */
103 /* Also note that comments like this one will always work. */
104 CONST
char line_comment_chars
[] = "#";
106 CONST
char line_separator_chars
[] = "";
108 /* Chars that can be used to separate mant from exp in floating point nums */
109 CONST
char EXP_CHARS
[] = "eE";
111 /* Chars that mean this number is a floating point constant */
115 CONST
char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
117 CONST
int md_reloc_size
= 8; /* Size of relocation record */
119 static int thumb_mode
= 0; /* non-zero if assembling thumb instructions */
121 typedef struct arm_fix
129 unsigned long instruction
;
134 bfd_reloc_code_real_type type
;
144 CONST
char *template;
148 static CONST
struct asm_shift shift
[] =
164 #define NO_SHIFT_RESTRICT 1
165 #define SHIFT_RESTRICT 0
167 #define NUM_FLOAT_VALS 8
169 CONST
char *fp_const
[] =
171 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
174 /* Number of littlenums required to hold an extended precision number */
175 #define MAX_LITTLENUMS 6
177 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
187 #define CP_T_X 0x00008000
188 #define CP_T_Y 0x00400000
189 #define CP_T_Pre 0x01000000
190 #define CP_T_UD 0x00800000
191 #define CP_T_WB 0x00200000
193 #define CONDS_BIT (0x00100000)
194 #define LOAD_BIT (0x00100000)
195 #define TRANS_BIT (0x00200000)
199 CONST
char *template;
203 /* This is to save a hash look-up in the common case */
204 #define COND_ALWAYS 0xe0000000
206 static CONST
struct asm_cond conds
[] =
210 {"cs", 0x20000000}, {"hs", 0x20000000},
211 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
226 /* Warning: If the top bit of the set_bits is set, then the standard
227 instruction bitmask is ignored, and the new bitmask is taken from
231 CONST
char *template; /* Basic flag string */
232 unsigned long set_bits
; /* Bits to set */
235 static CONST
struct asm_flg s_flag
[] =
241 static CONST
struct asm_flg ldr_flags
[] =
245 {"bt", 0x00400000 | TRANS_BIT
},
252 static CONST
struct asm_flg str_flags
[] =
256 {"bt", 0x00400000 | TRANS_BIT
},
261 static CONST
struct asm_flg byte_flag
[] =
267 static CONST
struct asm_flg cmp_flags
[] =
274 static CONST
struct asm_flg ldm_flags
[] =
287 static CONST
struct asm_flg stm_flags
[] =
300 static CONST
struct asm_flg lfm_flags
[] =
307 static CONST
struct asm_flg sfm_flags
[] =
314 static CONST
struct asm_flg round_flags
[] =
322 /* The implementation of the FIX instruction is broken on some assemblers,
323 in that it accepts a precision specifier as well as a rounding specifier,
324 despite the fact that this is meaningless. To be more compatible, we
325 accept it as well, though of course it does not set any bits. */
326 static CONST
struct asm_flg fix_flags
[] =
343 static CONST
struct asm_flg except_flag
[] =
349 static CONST
struct asm_flg cplong_flag
[] =
357 CONST
char *template;
358 unsigned long number
;
361 #define PSR_ALL 0x00010000
363 static CONST
struct asm_psr psrs
[] =
376 /* Functions called by parser */
377 /* ARM instructions */
378 static void do_arit
PARAMS ((char *operands
, unsigned long flags
));
379 static void do_cmp
PARAMS ((char *operands
, unsigned long flags
));
380 static void do_mov
PARAMS ((char *operands
, unsigned long flags
));
381 static void do_ldst
PARAMS ((char *operands
, unsigned long flags
));
382 static void do_ldmstm
PARAMS ((char *operands
, unsigned long flags
));
383 static void do_branch
PARAMS ((char *operands
, unsigned long flags
));
384 static void do_swi
PARAMS ((char *operands
, unsigned long flags
));
385 /* Pseudo Op codes */
386 static void do_adr
PARAMS ((char *operands
, unsigned long flags
));
387 static void do_nop
PARAMS ((char *operands
, unsigned long flags
));
389 static void do_mul
PARAMS ((char *operands
, unsigned long flags
));
390 static void do_mla
PARAMS ((char *operands
, unsigned long flags
));
392 static void do_swap
PARAMS ((char *operands
, unsigned long flags
));
394 static void do_msr
PARAMS ((char *operands
, unsigned long flags
));
395 static void do_mrs
PARAMS ((char *operands
, unsigned long flags
));
397 static void do_mull
PARAMS ((char *operands
, unsigned long flags
));
399 static void do_bx
PARAMS ((char *operands
, unsigned long flags
));
401 /* Coprocessor Instructions */
402 static void do_cdp
PARAMS ((char *operands
, unsigned long flags
));
403 static void do_lstc
PARAMS ((char *operands
, unsigned long flags
));
404 static void do_co_reg
PARAMS ((char *operands
, unsigned long flags
));
405 static void do_fp_ctrl
PARAMS ((char *operands
, unsigned long flags
));
406 static void do_fp_ldst
PARAMS ((char *operands
, unsigned long flags
));
407 static void do_fp_ldmstm
PARAMS ((char *operands
, unsigned long flags
));
408 static void do_fp_dyadic
PARAMS ((char *operands
, unsigned long flags
));
409 static void do_fp_monadic
PARAMS ((char *operands
, unsigned long flags
));
410 static void do_fp_cmp
PARAMS ((char *operands
, unsigned long flags
));
411 static void do_fp_from_reg
PARAMS ((char *operands
, unsigned long flags
));
412 static void do_fp_to_reg
PARAMS ((char *operands
, unsigned long flags
));
414 static void fix_new_arm
PARAMS ((fragS
*frag
, int where
,
415 short int size
, expressionS
*exp
,
416 int pc_rel
, int reloc
));
417 static int arm_reg_parse
PARAMS ((char **ccp
));
418 static int arm_psr_parse
PARAMS ((char **ccp
));
419 static void symbol_locate
PARAMS ((symbolS
*, CONST
char *, segT
,
421 static int add_to_lit_pool
PARAMS ((void));
422 static int validate_immediate
PARAMS ((int));
423 static int validate_offset_imm
PARAMS ((int, int));
424 static void opcode_select
PARAMS ((int));
425 static void end_of_line
PARAMS ((char *));
426 static int reg_required_here
PARAMS ((char **, int));
427 static int psr_required_here
PARAMS ((char **, int));
428 static int psrf_required_here
PARAMS ((char **, int));
429 static int co_proc_number
PARAMS ((char **));
430 static int cp_opc_expr
PARAMS ((char **, int, int));
431 static int cp_reg_required_here
PARAMS ((char **, int));
432 static int fp_reg_required_here
PARAMS ((char **, int));
433 static int cp_address_offset
PARAMS ((char **));
434 static int cp_address_required_here
PARAMS ((char **));
435 static int my_get_float_expression
PARAMS ((char **));
436 static int skip_past_comma
PARAMS ((char **));
437 static int walk_no_bignums
PARAMS ((symbolS
*));
438 static int negate_data_op
PARAMS ((unsigned long *,
440 static int data_op2
PARAMS ((char **));
441 static int fp_op2
PARAMS ((char **));
442 static long reg_list
PARAMS ((char **));
443 static void thumb_load_store
PARAMS ((char *, int, int));
444 static int decode_shift
PARAMS ((char **, int));
445 static int ldst_extend
PARAMS ((char **, int));
446 static void thumb_add_sub
PARAMS ((char *, int));
447 static void insert_reg
PARAMS ((int));
448 static void thumb_shift
PARAMS ((char *, int));
449 static void thumb_mov_compare
PARAMS ((char *, int));
450 static void set_constant_flonums
PARAMS ((void));
451 static valueT md_chars_to_number
PARAMS ((char *, int));
452 static void insert_reg_alias
PARAMS ((char *, int));
453 static void output_inst
PARAMS ((char *));
455 /* ARM instructions take 4bytes in the object file, Thumb instructions
459 /* LONGEST_INST is the longest basic instruction name without conditions or
461 * ARM7M has 4 of length 5
464 #define LONGEST_INST 5
468 CONST
char *template; /* Basic string to match */
469 unsigned long value
; /* Basic instruction code */
470 CONST
char *comp_suffix
; /* Compulsory suffix that must follow conds */
471 CONST
struct asm_flg
*flags
; /* Bits to toggle if flag 'n' set */
472 unsigned long variants
; /* Which CPU variants this exists for */
473 /* Function to call to parse args */
474 void (*parms
) PARAMS ((char *, unsigned long));
477 static CONST
struct asm_opcode insns
[] =
479 /* ARM Instructions */
480 {"and", 0x00000000, NULL
, s_flag
, ARM_ANY
, do_arit
},
481 {"eor", 0x00200000, NULL
, s_flag
, ARM_ANY
, do_arit
},
482 {"sub", 0x00400000, NULL
, s_flag
, ARM_ANY
, do_arit
},
483 {"rsb", 0x00600000, NULL
, s_flag
, ARM_ANY
, do_arit
},
484 {"add", 0x00800000, NULL
, s_flag
, ARM_ANY
, do_arit
},
485 {"adc", 0x00a00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
486 {"sbc", 0x00c00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
487 {"rsc", 0x00e00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
488 {"orr", 0x01800000, NULL
, s_flag
, ARM_ANY
, do_arit
},
489 {"bic", 0x01c00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
490 {"tst", 0x01000000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
491 {"teq", 0x01200000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
492 {"cmp", 0x01400000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
493 {"cmn", 0x01600000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
494 {"mov", 0x01a00000, NULL
, s_flag
, ARM_ANY
, do_mov
},
495 {"mvn", 0x01e00000, NULL
, s_flag
, ARM_ANY
, do_mov
},
496 {"str", 0x04000000, NULL
, str_flags
, ARM_ANY
, do_ldst
},
497 {"ldr", 0x04100000, NULL
, ldr_flags
, ARM_ANY
, do_ldst
},
498 {"stm", 0x08000000, NULL
, stm_flags
, ARM_ANY
, do_ldmstm
},
499 {"ldm", 0x08100000, NULL
, ldm_flags
, ARM_ANY
, do_ldmstm
},
500 {"swi", 0x0f000000, NULL
, NULL
, ARM_ANY
, do_swi
},
501 {"bl", 0x0bfffffe, NULL
, NULL
, ARM_ANY
, do_branch
},
502 {"b", 0x0afffffe, NULL
, NULL
, ARM_ANY
, do_branch
},
505 {"adr", 0x028f0000, NULL
, NULL
, ARM_ANY
, do_adr
},
506 {"nop", 0x01a00000, NULL
, NULL
, ARM_ANY
, do_nop
},
508 /* ARM 2 multiplies */
509 {"mul", 0x00000090, NULL
, s_flag
, ARM_2UP
, do_mul
},
510 {"mla", 0x00200090, NULL
, s_flag
, ARM_2UP
, do_mla
},
512 /* ARM 3 - swp instructions */
513 {"swp", 0x01000090, NULL
, byte_flag
, ARM_3UP
, do_swap
},
515 /* ARM 6 Coprocessor instructions */
516 {"mrs", 0x010f0000, NULL
, NULL
, ARM_6UP
, do_mrs
},
517 {"msr", 0x0128f000, NULL
, NULL
, ARM_6UP
, do_msr
},
519 /* ARM 7M long multiplies - need signed/unsigned flags! */
520 {"smull", 0x00c00090, NULL
, s_flag
, ARM_LONGMUL
, do_mull
},
521 {"umull", 0x00800090, NULL
, s_flag
, ARM_LONGMUL
, do_mull
},
522 {"smlal", 0x00e00090, NULL
, s_flag
, ARM_LONGMUL
, do_mull
},
523 {"umlal", 0x00a00090, NULL
, s_flag
, ARM_LONGMUL
, do_mull
},
525 /* ARM THUMB interworking */
526 {"bx", 0x012fff10, NULL
, NULL
, ARM_THUMB
, do_bx
},
528 /* Floating point instructions */
529 {"wfs", 0x0e200110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
530 {"rfs", 0x0e300110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
531 {"wfc", 0x0e400110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
532 {"rfc", 0x0e500110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
533 {"ldf", 0x0c100100, "sdep", NULL
, FPU_ALL
, do_fp_ldst
},
534 {"stf", 0x0c000100, "sdep", NULL
, FPU_ALL
, do_fp_ldst
},
535 {"lfm", 0x0c100200, NULL
, lfm_flags
, FPU_MEMMULTI
, do_fp_ldmstm
},
536 {"sfm", 0x0c000200, NULL
, sfm_flags
, FPU_MEMMULTI
, do_fp_ldmstm
},
537 {"mvf", 0x0e008100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
538 {"mnf", 0x0e108100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
539 {"abs", 0x0e208100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
540 {"rnd", 0x0e308100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
541 {"sqt", 0x0e408100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
542 {"log", 0x0e508100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
543 {"lgn", 0x0e608100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
544 {"exp", 0x0e708100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
545 {"sin", 0x0e808100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
546 {"cos", 0x0e908100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
547 {"tan", 0x0ea08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
548 {"asn", 0x0eb08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
549 {"acs", 0x0ec08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
550 {"atn", 0x0ed08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
551 {"urd", 0x0ee08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
552 {"nrm", 0x0ef08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
553 {"adf", 0x0e000100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
554 {"suf", 0x0e200100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
555 {"rsf", 0x0e300100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
556 {"muf", 0x0e100100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
557 {"dvf", 0x0e400100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
558 {"rdf", 0x0e500100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
559 {"pow", 0x0e600100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
560 {"rpw", 0x0e700100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
561 {"rmf", 0x0e800100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
562 {"fml", 0x0e900100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
563 {"fdv", 0x0ea00100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
564 {"frd", 0x0eb00100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
565 {"pol", 0x0ec00100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
566 {"cmf", 0x0e90f110, NULL
, except_flag
, FPU_ALL
, do_fp_cmp
},
567 {"cnf", 0x0eb0f110, NULL
, except_flag
, FPU_ALL
, do_fp_cmp
},
568 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
569 be an optional suffix, but part of the instruction. To be compatible,
571 {"cmfe", 0x0ed0f110, NULL
, NULL
, FPU_ALL
, do_fp_cmp
},
572 {"cnfe", 0x0ef0f110, NULL
, NULL
, FPU_ALL
, do_fp_cmp
},
573 {"flt", 0x0e000110, "sde", round_flags
, FPU_ALL
, do_fp_from_reg
},
574 {"fix", 0x0e100110, NULL
, fix_flags
, FPU_ALL
, do_fp_to_reg
},
576 /* Generic copressor instructions */
577 {"cdp", 0x0e000000, NULL
, NULL
, ARM_2UP
, do_cdp
},
578 {"ldc", 0x0c100000, NULL
, cplong_flag
, ARM_2UP
, do_lstc
},
579 {"stc", 0x0c000000, NULL
, cplong_flag
, ARM_2UP
, do_lstc
},
580 {"mcr", 0x0e000010, NULL
, NULL
, ARM_2UP
, do_co_reg
},
581 {"mrc", 0x0e100010, NULL
, NULL
, ARM_2UP
, do_co_reg
},
584 /* defines for various bits that we will want to toggle */
586 #define INST_IMMEDIATE 0x02000000
587 #define OFFSET_REG 0x02000000
588 #define HWOFFSET_IMM 0x00400000
589 #define SHIFT_BY_REG 0x00000010
590 #define PRE_INDEX 0x01000000
591 #define INDEX_UP 0x00800000
592 #define WRITE_BACK 0x00200000
593 #define MULTI_SET_PSR 0x00400000
595 #define LITERAL_MASK 0xf000f000
596 #define COND_MASK 0xf0000000
597 #define OPCODE_MASK 0xfe1fffff
598 #define DATA_OP_SHIFT 21
600 /* Codes to distinguish the arithmetic instructions */
612 #define OPCODE_CMP 10
613 #define OPCODE_CMN 11
614 #define OPCODE_ORR 12
615 #define OPCODE_MOV 13
616 #define OPCODE_BIC 14
617 #define OPCODE_MVN 15
619 static void do_t_nop
PARAMS ((char *operands
));
620 static void do_t_arit
PARAMS ((char *operands
));
621 static void do_t_add
PARAMS ((char *operands
));
622 static void do_t_asr
PARAMS ((char *operands
));
623 static void do_t_branch9
PARAMS ((char *operands
));
624 static void do_t_branch12
PARAMS ((char *operands
));
625 static void do_t_branch23
PARAMS ((char *operands
));
626 static void do_t_bx
PARAMS ((char *operands
));
627 static void do_t_compare
PARAMS ((char *operands
));
628 static void do_t_ldmstm
PARAMS ((char *operands
));
629 static void do_t_ldr
PARAMS ((char *operands
));
630 static void do_t_ldrb
PARAMS ((char *operands
));
631 static void do_t_ldrh
PARAMS ((char *operands
));
632 static void do_t_lds
PARAMS ((char *operands
));
633 static void do_t_lsl
PARAMS ((char *operands
));
634 static void do_t_lsr
PARAMS ((char *operands
));
635 static void do_t_mov
PARAMS ((char *operands
));
636 static void do_t_push_pop
PARAMS ((char *operands
));
637 static void do_t_str
PARAMS ((char *operands
));
638 static void do_t_strb
PARAMS ((char *operands
));
639 static void do_t_strh
PARAMS ((char *operands
));
640 static void do_t_sub
PARAMS ((char *operands
));
641 static void do_t_swi
PARAMS ((char *operands
));
642 static void do_t_adr
PARAMS ((char *operands
));
644 #define T_OPCODE_MUL 0x4340
645 #define T_OPCODE_TST 0x4200
646 #define T_OPCODE_CMN 0x42c0
647 #define T_OPCODE_NEG 0x4240
648 #define T_OPCODE_MVN 0x43c0
650 #define T_OPCODE_ADD_R3 0x1800
651 #define T_OPCODE_SUB_R3 0x1a00
652 #define T_OPCODE_ADD_HI 0x4400
653 #define T_OPCODE_ADD_ST 0xb000
654 #define T_OPCODE_SUB_ST 0xb080
655 #define T_OPCODE_ADD_SP 0xa800
656 #define T_OPCODE_ADD_PC 0xa000
657 #define T_OPCODE_ADD_I8 0x3000
658 #define T_OPCODE_SUB_I8 0x3800
659 #define T_OPCODE_ADD_I3 0x1c00
660 #define T_OPCODE_SUB_I3 0x1e00
662 #define T_OPCODE_ASR_R 0x4100
663 #define T_OPCODE_LSL_R 0x4080
664 #define T_OPCODE_LSR_R 0x40c0
665 #define T_OPCODE_ASR_I 0x1000
666 #define T_OPCODE_LSL_I 0x0000
667 #define T_OPCODE_LSR_I 0x0800
669 #define T_OPCODE_MOV_I8 0x2000
670 #define T_OPCODE_CMP_I8 0x2800
671 #define T_OPCODE_CMP_LR 0x4280
672 #define T_OPCODE_MOV_HR 0x4600
673 #define T_OPCODE_CMP_HR 0x4500
675 #define T_OPCODE_LDR_PC 0x4800
676 #define T_OPCODE_LDR_SP 0x9800
677 #define T_OPCODE_STR_SP 0x9000
678 #define T_OPCODE_LDR_IW 0x6800
679 #define T_OPCODE_STR_IW 0x6000
680 #define T_OPCODE_LDR_IH 0x8800
681 #define T_OPCODE_STR_IH 0x8000
682 #define T_OPCODE_LDR_IB 0x7800
683 #define T_OPCODE_STR_IB 0x7000
684 #define T_OPCODE_LDR_RW 0x5800
685 #define T_OPCODE_STR_RW 0x5000
686 #define T_OPCODE_LDR_RH 0x5a00
687 #define T_OPCODE_STR_RH 0x5200
688 #define T_OPCODE_LDR_RB 0x5c00
689 #define T_OPCODE_STR_RB 0x5400
691 #define T_OPCODE_PUSH 0xb400
692 #define T_OPCODE_POP 0xbc00
694 #define T_OPCODE_BRANCH 0xe7fe
696 static int thumb_reg
PARAMS ((char **str
, int hi_lo
));
698 #define THUMB_SIZE 2 /* Size of thumb instruction */
699 #define THUMB_REG_LO 0x1
700 #define THUMB_REG_HI 0x2
701 #define THUMB_REG_ANY 0x3
703 #define THUMB_H1 0x0080
704 #define THUMB_H2 0x0040
711 #define THUMB_COMPARE 1
714 #define THUMB_STORE 1
716 #define THUMB_PP_PC_LR 0x0100
718 /* These three are used for immediate shifts, do not alter */
720 #define THUMB_HALFWORD 1
725 CONST
char *template; /* Basic string to match */
726 unsigned long value
; /* Basic instruction code */
728 /* Function to call to parse args */
729 void (*parms
) PARAMS ((char *));
732 static CONST
struct thumb_opcode tinsns
[] =
734 {"adc", 0x4140, 2, do_t_arit
},
735 {"add", 0x0000, 2, do_t_add
},
736 {"and", 0x4000, 2, do_t_arit
},
737 {"asr", 0x0000, 2, do_t_asr
},
738 {"b", T_OPCODE_BRANCH
, 2, do_t_branch12
},
739 {"beq", 0xd0fe, 2, do_t_branch9
},
740 {"bne", 0xd1fe, 2, do_t_branch9
},
741 {"bcs", 0xd2fe, 2, do_t_branch9
},
742 {"bhs", 0xd2fe, 2, do_t_branch9
},
743 {"bcc", 0xd3fe, 2, do_t_branch9
},
744 {"bul", 0xd3fe, 2, do_t_branch9
},
745 {"blo", 0xd3fe, 2, do_t_branch9
},
746 {"bmi", 0xd4fe, 2, do_t_branch9
},
747 {"bpl", 0xd5fe, 2, do_t_branch9
},
748 {"bvs", 0xd6fe, 2, do_t_branch9
},
749 {"bvc", 0xd7fe, 2, do_t_branch9
},
750 {"bhi", 0xd8fe, 2, do_t_branch9
},
751 {"bls", 0xd9fe, 2, do_t_branch9
},
752 {"bge", 0xdafe, 2, do_t_branch9
},
753 {"blt", 0xdbfe, 2, do_t_branch9
},
754 {"bgt", 0xdcfe, 2, do_t_branch9
},
755 {"ble", 0xddfe, 2, do_t_branch9
},
756 {"bic", 0x4380, 2, do_t_arit
},
757 {"bl", 0xf7fffffe, 4, do_t_branch23
},
758 {"bx", 0x4700, 2, do_t_bx
},
759 {"cmn", T_OPCODE_CMN
, 2, do_t_arit
},
760 {"cmp", 0x0000, 2, do_t_compare
},
761 {"eor", 0x4040, 2, do_t_arit
},
762 {"ldmia", 0xc800, 2, do_t_ldmstm
},
763 {"ldr", 0x0000, 2, do_t_ldr
},
764 {"ldrb", 0x0000, 2, do_t_ldrb
},
765 {"ldrh", 0x0000, 2, do_t_ldrh
},
766 {"ldrsb", 0x5600, 2, do_t_lds
},
767 {"ldrsh", 0x5e00, 2, do_t_lds
},
768 {"ldsb", 0x5600, 2, do_t_lds
},
769 {"ldsh", 0x5e00, 2, do_t_lds
},
770 {"lsl", 0x0000, 2, do_t_lsl
},
771 {"lsr", 0x0000, 2, do_t_lsr
},
772 {"mov", 0x0000, 2, do_t_mov
},
773 {"mul", T_OPCODE_MUL
, 2, do_t_arit
},
774 {"mvn", T_OPCODE_MVN
, 2, do_t_arit
},
775 {"neg", T_OPCODE_NEG
, 2, do_t_arit
},
776 {"orr", 0x4300, 2, do_t_arit
},
777 {"pop", 0xbc00, 2, do_t_push_pop
},
778 {"push", 0xb400, 2, do_t_push_pop
},
779 {"ror", 0x41c0, 2, do_t_arit
},
780 {"sbc", 0x4180, 2, do_t_arit
},
781 {"stmia", 0xc000, 2, do_t_ldmstm
},
782 {"str", 0x0000, 2, do_t_str
},
783 {"strb", 0x0000, 2, do_t_strb
},
784 {"strh", 0x0000, 2, do_t_strh
},
785 {"swi", 0xdf00, 2, do_t_swi
},
786 {"sub", 0x0000, 2, do_t_sub
},
787 {"tst", T_OPCODE_TST
, 2, do_t_arit
},
789 {"adr", 0x0000, 2, do_t_adr
},
790 {"nop", 0x46C0, 2, do_t_nop
}, /* mov r8,r8 */
799 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
800 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
801 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
807 /* These are the standard names; Users can add aliases with .req */
808 static CONST
struct reg_entry reg_table
[] =
810 /* Processor Register Numbers */
811 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
812 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
813 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
814 {"r12", 12}, {"r13", REG_SP
},{"r14", REG_LR
},{"r15", REG_PC
},
815 /* APCS conventions */
816 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
817 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
818 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
819 {"fp", 11}, {"ip", 12}, {"sp", REG_SP
},{"lr", REG_LR
},{"pc", REG_PC
},
821 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
822 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
823 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
824 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
825 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
826 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
827 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
828 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
829 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
830 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
834 static CONST
char *bad_args
= "Bad arguments to instruction";
835 static CONST
char *bad_pc
= "r15 not allowed here";
837 static struct hash_control
*arm_ops_hsh
= NULL
;
838 static struct hash_control
*arm_tops_hsh
= NULL
;
839 static struct hash_control
*arm_cond_hsh
= NULL
;
840 static struct hash_control
*arm_shift_hsh
= NULL
;
841 static struct hash_control
*arm_reg_hsh
= NULL
;
842 static struct hash_control
*arm_psr_hsh
= NULL
;
844 /* This table describes all the machine specific pseudo-ops the assembler
845 has to support. The fields are:
846 pseudo-op name without dot
847 function to call to execute this pseudo-op
848 Integer arg to pass to the function
851 static void s_req
PARAMS ((int));
852 static void s_align
PARAMS ((int));
853 static void s_bss
PARAMS ((int));
854 static void s_even
PARAMS ((int));
855 static void s_ltorg
PARAMS ((int));
856 static void s_arm
PARAMS ((int));
857 static void s_thumb
PARAMS ((int));
858 static void s_code
PARAMS ((int));
860 static int my_get_expression
PARAMS ((expressionS
*, char **));
862 CONST pseudo_typeS md_pseudo_table
[] =
864 {"req", s_req
, 0}, /* Never called becasue '.req' does not start line */
866 {"align", s_align
, 0},
868 {"thumb", s_thumb
, 0},
871 {"ltorg", s_ltorg
, 0},
872 {"pool", s_ltorg
, 0},
874 {"extend", float_cons
, 'x'},
875 {"ldouble", float_cons
, 'x'},
876 {"packed", float_cons
, 'p'},
880 /* Stuff needed to resolve the label ambiguity
890 symbolS
*last_label_seen
;
894 #define MAX_LITERAL_POOL_SIZE 1024
896 typedef struct literalS
898 struct expressionS exp
;
902 literalT literals
[MAX_LITERAL_POOL_SIZE
];
903 int next_literal_pool_place
= 0; /* Next free entry in the pool */
904 int lit_pool_num
= 1; /* Next literal pool number */
905 symbolS
*current_poolP
= NULL
;
906 symbolS
*symbol_make_empty
PARAMS ((void));
913 if (current_poolP
== NULL
)
914 current_poolP
= symbol_make_empty();
916 /* Check if this literal value is already in the pool: */
917 while (lit_count
< next_literal_pool_place
)
919 if (literals
[lit_count
].exp
.X_op
== inst
.reloc
.exp
.X_op
920 && inst
.reloc
.exp
.X_op
== O_constant
921 && literals
[lit_count
].exp
.X_add_number
== inst
.reloc
.exp
.X_add_number
922 && literals
[lit_count
].exp
.X_unsigned
== inst
.reloc
.exp
.X_unsigned
)
927 if (lit_count
== next_literal_pool_place
) /* new entry */
929 if (next_literal_pool_place
> MAX_LITERAL_POOL_SIZE
)
931 inst
.error
= "Literal Pool Overflow\n";
935 literals
[next_literal_pool_place
].exp
= inst
.reloc
.exp
;
936 lit_count
= next_literal_pool_place
++;
939 inst
.reloc
.exp
.X_op
= O_symbol
;
940 inst
.reloc
.exp
.X_add_number
= (lit_count
)*4-8;
941 inst
.reloc
.exp
.X_add_symbol
= current_poolP
;
946 /* Can't use symbol_new here, so have to create a symbol and then at
947 a later date assign it a value. Thats what these functions do */
949 symbol_locate (symbolP
, name
, segment
, valu
, frag
)
951 CONST
char *name
; /* It is copied, the caller can modify */
952 segT segment
; /* Segment identifier (SEG_<something>) */
953 valueT valu
; /* Symbol value */
954 fragS
*frag
; /* Associated fragment */
956 unsigned int name_length
;
957 char *preserved_copy_of_name
;
959 name_length
= strlen (name
) + 1; /* +1 for \0 */
960 obstack_grow (¬es
, name
, name_length
);
961 preserved_copy_of_name
= obstack_finish (¬es
);
962 #ifdef STRIP_UNDERSCORE
963 if (preserved_copy_of_name
[0] == '_')
964 preserved_copy_of_name
++;
967 #ifdef tc_canonicalize_symbol_name
968 preserved_copy_of_name
=
969 tc_canonicalize_symbol_name (preserved_copy_of_name
);
972 S_SET_NAME (symbolP
, preserved_copy_of_name
);
974 S_SET_SEGMENT (symbolP
, segment
);
975 S_SET_VALUE (symbolP
, valu
);
976 symbol_clear_list_pointers(symbolP
);
978 symbolP
->sy_frag
= frag
;
981 * Link to end of symbol chain.
984 extern int symbol_table_frozen
;
985 if (symbol_table_frozen
)
989 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
991 obj_symbol_new_hook (symbolP
);
993 #ifdef tc_symbol_new_hook
994 tc_symbol_new_hook (symbolP
);
998 verify_symbol_chain(symbol_rootP
, symbol_lastP
);
999 #endif /* DEBUG_SYMS */
1003 symbol_make_empty ()
1007 symbolP
= (symbolS
*) obstack_alloc (¬es
, sizeof (symbolS
));
1009 /* symbol must be born in some fixed state. This seems as good as any. */
1010 memset (symbolP
, 0, sizeof (symbolS
));
1012 symbolP
->bsym
= bfd_make_empty_symbol (stdoutput
);
1013 assert (symbolP
->bsym
!= 0);
1014 symbolP
->bsym
->udata
.p
= (PTR
) symbolP
;
1019 /* Check that an immediate is valid, and if so, convert it to the right format
1022 /* OH, for a rotate instruction in C! */
1025 validate_immediate (val
)
1028 unsigned int a
= (unsigned int) val
;
1031 /* Do the easy (and most common ones) quickly */
1032 for (i
= 0; i
<= 24; i
+= 2)
1034 if ((a
& (0xff << i
)) == a
)
1035 return (int) (((32 - i
) & 0x1e) << 7) | ((a
>> i
) & 0xff);
1038 /* Now do the harder ones */
1039 for (; i
< 32; i
+= 2)
1041 if ((a
& ((0xff << i
) | (0xff >> (32 - i
)))) == a
)
1043 a
= ((a
>> i
) & 0xff) | ((a
<< (32 - i
)) & 0xff);
1044 return (int) a
| (((32 - i
) >> 1) << 8);
1051 validate_offset_imm (val
, hwse
)
1055 if ((hwse
&& (val
< -255 || val
> 255))
1056 || (val
< -4095 || val
> 4095))
1066 as_bad ("Invalid syntax for .req directive.");
1073 /* We don't support putting frags in the BSS segment, we fake it by
1074 marking in_bss, then looking at s_skip for clues?.. */
1075 subseg_set (bss_section
, 0);
1076 demand_empty_rest_of_line ();
1083 if (!need_pass_2
) /* Never make frag if expect extra pass. */
1084 frag_align (1, 0, 0);
1085 record_alignment (now_seg
, 1);
1086 demand_empty_rest_of_line ();
1096 if (current_poolP
== NULL
)
1100 as_tsktsk ("Nothing to put in the pool\n");
1104 /* Align pool as you have word accesses */
1105 /* Only make a frag if we have to ... */
1107 frag_align (2, 0, 0);
1109 record_alignment (now_seg
, 2);
1112 as_tsktsk ("Inserting implicit pool at change of section");
1114 sprintf (sym_name
, "$$lit_\002%x", lit_pool_num
++);
1116 symbol_locate (current_poolP
, sym_name
, now_seg
,
1117 (valueT
) frag_now_fix (), frag_now
);
1118 symbol_table_insert (current_poolP
);
1120 while (lit_count
< next_literal_pool_place
)
1121 /* First output the expression in the instruction to the pool */
1122 emit_expr (&(literals
[lit_count
++].exp
), 4); /* .word */
1124 next_literal_pool_place
= 0;
1125 current_poolP
= NULL
;
1128 #if 0 /* not used */
1130 arm_align (power
, fill
)
1134 /* Only make a frag if we HAVE to ... */
1135 if (power
&& !need_pass_2
)
1136 frag_align (power
, fill
, 0);
1138 record_alignment (now_seg
, power
);
1143 s_align (unused
) /* Same as s_align_ptwo but align 0 => align 2 */
1147 register long temp_fill
;
1148 long max_alignment
= 15;
1150 temp
= get_absolute_expression ();
1151 if (temp
> max_alignment
)
1152 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
1155 as_bad ("Alignment negative. 0 assumed.");
1159 if (*input_line_pointer
== ',')
1161 input_line_pointer
++;
1162 temp_fill
= get_absolute_expression ();
1170 /* Only make a frag if we HAVE to. . . */
1171 if (temp
&& !need_pass_2
)
1172 frag_align (temp
, (int) temp_fill
, 0);
1173 demand_empty_rest_of_line ();
1175 record_alignment (now_seg
, temp
);
1179 opcode_select (width
)
1187 if (! (cpu_variant
& ARM_THUMB
))
1188 as_bad ("selected processor does not support THUMB opcodes");
1190 /* No need to force the alignment, since we will have been
1191 coming from ARM mode, which is word-aligned. */
1192 record_alignment (now_seg
, 1);
1199 if ((cpu_variant
& ARM_ANY
) == ARM_THUMB
)
1200 as_bad ("selected processor does not support ARM opcodes");
1203 frag_align (2, 0, 0);
1204 record_alignment (now_seg
, 1);
1209 as_bad ("invalid instruction size selected (%d)", width
);
1218 demand_empty_rest_of_line ();
1226 demand_empty_rest_of_line ();
1235 temp
= get_absolute_expression ();
1240 opcode_select(temp
);
1244 as_bad ("invalid operand to .code directive (%d) (expecting 16 or 32)", temp
);
1256 inst
.error
= "Garbage following instruction";
1260 skip_past_comma (str
)
1266 while ((c
= *p
) == ' ' || c
== ',')
1269 if (c
== ',' && comma
++)
1277 return comma
? SUCCESS
: FAIL
;
1280 /* A standard register must be given at this point. Shift is the place to
1281 put it in the instruction. */
1284 reg_required_here (str
, shift
)
1291 if ((reg
= arm_reg_parse (str
)) != FAIL
&& int_register (reg
))
1293 inst
.instruction
|= reg
<< shift
;
1297 /* In the few cases where we might be able to accept something else
1298 this error can be overridden */
1299 inst
.error
= "Register expected";
1301 /* Restore the start point, we may have got a reg of the wrong class. */
1307 psr_required_here (str
, shift
)
1314 if ((psr
= arm_psr_parse (str
)) != FAIL
&& psr
< 2)
1317 inst
.instruction
|= 1 << shift
; /* Should be bit 22 */
1321 /* In the few cases where we might be able to accept something else
1322 this error can be overridden */
1323 inst
.error
= "<psr> expected";
1325 /* Restore the start point. */
1331 psrf_required_here (str
, shift
)
1338 if ((psrf
= arm_psr_parse (str
)) != FAIL
&& psrf
> 1)
1340 if (psrf
== 1 || psrf
== 3)
1341 inst
.instruction
|= 1 << shift
; /* Should be bit 22 */
1345 /* In the few cases where we might be able to accept something else
1346 this error can be overridden */
1347 inst
.error
= "<psrf> expected";
1349 /* Restore the start point. */
1355 co_proc_number (str
)
1358 int processor
, pchar
;
1360 while (**str
== ' ')
1363 /* The data sheet seems to imply that just a number on its own is valid
1364 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1366 if (**str
== 'p' || **str
== 'P')
1370 if (pchar
>= '0' && pchar
<= '9')
1372 processor
= pchar
- '0';
1373 if (**str
>= '0' && **str
<= '9')
1375 processor
= processor
* 10 + *(*str
)++ - '0';
1378 inst
.error
= "Illegal co-processor number";
1385 inst
.error
= "Bad or missing co-processor number";
1389 inst
.instruction
|= processor
<< 8;
1394 cp_opc_expr (str
, where
, length
)
1401 while (**str
== ' ')
1404 memset (&expr
, '\0', sizeof (expr
));
1406 if (my_get_expression (&expr
, str
))
1408 if (expr
.X_op
!= O_constant
)
1410 inst
.error
= "bad or missing expression";
1414 if ((expr
.X_add_number
& ((1 << length
) - 1)) != expr
.X_add_number
)
1416 inst
.error
= "immediate co-processor expression too large";
1420 inst
.instruction
|= expr
.X_add_number
<< where
;
1425 cp_reg_required_here (str
, where
)
1432 if ((reg
= arm_reg_parse (str
)) != FAIL
&& cp_register (reg
))
1435 inst
.instruction
|= reg
<< where
;
1439 /* In the few cases where we might be able to accept something else
1440 this error can be overridden */
1441 inst
.error
= "Co-processor register expected";
1443 /* Restore the start point */
1449 fp_reg_required_here (str
, where
)
1456 if ((reg
= arm_reg_parse (str
)) != FAIL
&& fp_register (reg
))
1459 inst
.instruction
|= reg
<< where
;
1463 /* In the few cases where we might be able to accept something else
1464 this error can be overridden */
1465 inst
.error
= "Floating point register expected";
1467 /* Restore the start point */
1473 cp_address_offset (str
)
1478 while (**str
== ' ')
1483 inst
.error
= "immediate expression expected";
1488 if (my_get_expression (&inst
.reloc
.exp
, str
))
1490 if (inst
.reloc
.exp
.X_op
== O_constant
)
1492 offset
= inst
.reloc
.exp
.X_add_number
;
1495 inst
.error
= "co-processor address must be word aligned";
1499 if (offset
> 1023 || offset
< -1023)
1501 inst
.error
= "offset too large";
1506 inst
.instruction
|= INDEX_UP
;
1510 inst
.instruction
|= offset
>> 2;
1513 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
1519 cp_address_required_here (str
)
1534 if ((reg
= reg_required_here (&p
, 16)) == FAIL
)
1536 inst
.error
= "Register required";
1546 if (skip_past_comma (&p
) == SUCCESS
)
1549 write_back
= WRITE_BACK
;
1552 inst
.error
= "pc may not be used in post-increment";
1556 if (cp_address_offset (&p
) == FAIL
)
1560 pre_inc
= PRE_INDEX
| INDEX_UP
;
1564 /* '['Rn, #expr']'[!] */
1566 if (skip_past_comma (&p
) == FAIL
)
1568 inst
.error
= "pre-indexed expression expected";
1572 pre_inc
= PRE_INDEX
;
1573 if (cp_address_offset (&p
) == FAIL
)
1581 inst
.error
= "missing ]";
1592 inst
.error
= "pc may not be used with write-back";
1597 write_back
= WRITE_BACK
;
1603 if (my_get_expression (&inst
.reloc
.exp
, &p
))
1606 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
1607 inst
.reloc
.exp
.X_add_number
-= 8; /* PC rel adjust */
1608 inst
.reloc
.pc_rel
= 1;
1609 inst
.instruction
|= (REG_PC
<< 16);
1610 pre_inc
= PRE_INDEX
;
1613 inst
.instruction
|= write_back
| pre_inc
;
1621 unsigned long flags
;
1623 /* Do nothing really */
1624 inst
.instruction
|= flags
; /* This is pointless */
1632 unsigned long flags
;
1634 /* Only one syntax */
1638 if (reg_required_here (&str
, 12) == FAIL
)
1640 inst
.error
= bad_args
;
1644 if (skip_past_comma (&str
) == FAIL
1645 || psr_required_here (&str
, 22) == FAIL
)
1647 inst
.error
= "<psr> expected";
1651 inst
.instruction
|= flags
;
1659 unsigned long flags
;
1662 /* Three possible forms: "<psr>, Rm", "<psrf>, Rm", "<psrf>, #expression" */
1667 if ((psr
= psr_required_here (&str
, 22)) != FAIL
)
1669 inst
.instruction
|= PSR_ALL
;
1670 /* Sytax should be "<psr>, Rm" */
1671 if (skip_past_comma (&str
) == FAIL
1672 || (reg
= reg_required_here (&str
, 0)) == FAIL
)
1674 inst
.error
= bad_args
;
1678 else if ((psrf
= psrf_required_here (&str
, 22)) != FAIL
)
1679 /* Syntax could be "<psrf>, rm", "<psrf>, #expression" */
1681 if (skip_past_comma (&str
) == FAIL
)
1683 inst
.error
= bad_args
;
1686 if ((reg
= reg_required_here (&str
, 0)) != FAIL
)
1688 /* Immediate expression */
1689 else if (*(str
++) == '#')
1692 if (my_get_expression (&inst
.reloc
.exp
, &str
))
1694 inst
.error
= "Register or shift expression expected";
1698 if (inst
.reloc
.exp
.X_add_symbol
)
1700 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
1701 inst
.reloc
.pc_rel
= 0;
1705 int value
= validate_immediate (inst
.reloc
.exp
.X_add_number
);
1708 inst
.error
= "Invalid constant";
1712 inst
.instruction
|= value
;
1715 flags
|= INST_IMMEDIATE
;
1719 inst
.error
= "Error: the other";
1725 inst
.error
= bad_args
;
1730 inst
.instruction
|= flags
;
1735 /* Long Multiply Parser
1736 UMULL RdLo, RdHi, Rm, Rs
1737 SMULL RdLo, RdHi, Rm, Rs
1738 UMLAL RdLo, RdHi, Rm, Rs
1739 SMLAL RdLo, RdHi, Rm, Rs
1742 do_mull (str
, flags
)
1744 unsigned long flags
;
1746 int rdlo
, rdhi
, rm
, rs
;
1748 /* only one format "rdlo, rdhi, rm, rs" */
1752 if ((rdlo
= reg_required_here (&str
, 12)) == FAIL
)
1754 inst
.error
= bad_args
;
1758 if (skip_past_comma (&str
) == FAIL
1759 || (rdhi
= reg_required_here (&str
, 16)) == FAIL
)
1761 inst
.error
= bad_args
;
1765 if (skip_past_comma (&str
) == FAIL
1766 || (rm
= reg_required_here (&str
, 0)) == FAIL
)
1768 inst
.error
= bad_args
;
1772 /* rdhi, rdlo and rm must all be different */
1773 if (rdlo
== rdhi
|| rdlo
== rm
|| rdhi
== rm
)
1774 as_tsktsk ("rdhi, rdlo and rm must all be different");
1776 if (skip_past_comma (&str
) == FAIL
1777 || (rs
= reg_required_here (&str
, 8)) == FAIL
)
1779 inst
.error
= bad_args
;
1783 if (rdhi
== REG_PC
|| rdhi
== REG_PC
|| rdhi
== REG_PC
|| rdhi
== REG_PC
)
1785 inst
.error
= bad_pc
;
1789 inst
.instruction
|= flags
;
1797 unsigned long flags
;
1801 /* only one format "rd, rm, rs" */
1805 if ((rd
= reg_required_here (&str
, 16)) == FAIL
)
1807 inst
.error
= bad_args
;
1813 inst
.error
= bad_pc
;
1817 if (skip_past_comma (&str
) == FAIL
1818 || (rm
= reg_required_here (&str
, 0)) == FAIL
)
1820 inst
.error
= bad_args
;
1826 inst
.error
= bad_pc
;
1831 as_tsktsk ("rd and rm should be different in mul");
1833 if (skip_past_comma (&str
) == FAIL
1834 || (rm
= reg_required_here (&str
, 8)) == FAIL
)
1836 inst
.error
= bad_args
;
1842 inst
.error
= bad_pc
;
1846 inst
.instruction
|= flags
;
1854 unsigned long flags
;
1858 /* only one format "rd, rm, rs, rn" */
1862 if ((rd
= reg_required_here (&str
, 16)) == FAIL
)
1864 inst
.error
= bad_args
;
1870 inst
.error
= bad_pc
;
1874 if (skip_past_comma (&str
) == FAIL
1875 || (rm
= reg_required_here (&str
, 0)) == FAIL
)
1877 inst
.error
= bad_args
;
1883 inst
.error
= bad_pc
;
1888 as_tsktsk ("rd and rm should be different in mla");
1890 if (skip_past_comma (&str
) == FAIL
1891 || (rd
= reg_required_here (&str
, 8)) == FAIL
1892 || skip_past_comma (&str
) == FAIL
1893 || (rm
= reg_required_here (&str
, 12)) == FAIL
)
1895 inst
.error
= bad_args
;
1899 if (rd
== REG_PC
|| rm
== REG_PC
)
1901 inst
.error
= bad_pc
;
1905 inst
.instruction
|= flags
;
1910 /* Returns the index into fp_values of a floating point number, or -1 if
1911 not in the table. */
1913 my_get_float_expression (str
)
1916 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1921 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
1922 /* Look for a raw floating point number */
1923 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
1924 && (is_end_of_line
[(int)(*save_in
)] || *save_in
== '\0'))
1926 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
1928 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
1930 if (words
[j
] != fp_values
[i
][j
])
1934 if (j
== MAX_LITTLENUMS
)
1942 /* Try and parse a more complex expression, this will probably fail
1943 unless the code uses a floating point prefix (eg "0f") */
1944 save_in
= input_line_pointer
;
1945 input_line_pointer
= *str
;
1946 if (expression (&exp
) == absolute_section
1947 && exp
.X_op
== O_big
1948 && exp
.X_add_number
< 0)
1950 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
1952 if (gen_to_words (words
, 5, (long)15) == 0)
1954 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
1956 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
1958 if (words
[j
] != fp_values
[i
][j
])
1962 if (j
== MAX_LITTLENUMS
)
1964 *str
= input_line_pointer
;
1965 input_line_pointer
= save_in
;
1972 *str
= input_line_pointer
;
1973 input_line_pointer
= save_in
;
1977 /* Return true if anything in the expression is a bignum */
1979 walk_no_bignums (sp
)
1982 if (sp
->sy_value
.X_op
== O_big
)
1985 if (sp
->sy_value
.X_add_symbol
)
1987 return (walk_no_bignums (sp
->sy_value
.X_add_symbol
)
1988 || (sp
->sy_value
.X_op_symbol
1989 && walk_no_bignums (sp
->sy_value
.X_op_symbol
)));
1996 my_get_expression (ep
, str
)
2003 save_in
= input_line_pointer
;
2004 input_line_pointer
= *str
;
2005 seg
= expression (ep
);
2008 if (seg
!= absolute_section
2009 && seg
!= text_section
2010 && seg
!= data_section
2011 && seg
!= bss_section
2012 && seg
!= undefined_section
)
2014 inst
.error
= "bad_segment";
2015 *str
= input_line_pointer
;
2016 input_line_pointer
= save_in
;
2021 /* Get rid of any bignums now, so that we don't generate an error for which
2022 we can't establish a line number later on. Big numbers are never valid
2023 in instructions, which is where this routine is always called. */
2024 if (ep
->X_op
== O_big
2025 || (ep
->X_add_symbol
2026 && (walk_no_bignums (ep
->X_add_symbol
)
2028 && walk_no_bignums (ep
->X_op_symbol
)))))
2030 inst
.error
= "Invalid constant";
2031 *str
= input_line_pointer
;
2032 input_line_pointer
= save_in
;
2036 *str
= input_line_pointer
;
2037 input_line_pointer
= save_in
;
2041 /* unrestrict should be one if <shift> <register> is permitted for this
2045 decode_shift (str
, unrestrict
)
2049 struct asm_shift
*shft
;
2053 while (**str
== ' ')
2056 for (p
= *str
; isalpha (*p
); p
++)
2061 inst
.error
= "Shift expression expected";
2067 shft
= (struct asm_shift
*) hash_find (arm_shift_hsh
, *str
);
2071 if (!strcmp (*str
, "rrx")
2072 || !strcmp (*str
, "RRX"))
2075 inst
.instruction
|= shft
->value
;
2082 if (unrestrict
&& reg_required_here (&p
, 8) != FAIL
)
2084 inst
.instruction
|= shft
->value
| SHIFT_BY_REG
;
2092 if (my_get_expression (&inst
.reloc
.exp
, &p
))
2095 /* Validate some simple #expressions */
2096 if (inst
.reloc
.exp
.X_op
== O_constant
)
2098 unsigned num
= inst
.reloc
.exp
.X_add_number
;
2100 /* Reject operations greater than 32, or lsl #32 */
2101 if (num
> 32 || (num
== 32 && shft
->value
== 0))
2103 inst
.error
= "Invalid immediate shift";
2107 /* Shifts of zero should be converted to lsl (which is zero)*/
2114 /* Shifts of 32 are encoded as 0, for those shifts that
2119 inst
.instruction
|= (num
<< 7) | shft
->value
;
2124 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
2125 inst
.reloc
.pc_rel
= 0;
2126 inst
.instruction
|= shft
->value
;
2132 inst
.error
= unrestrict
? "shift requires register or #expression"
2133 : "shift requires #expression";
2139 inst
.error
= "Shift expression expected";
2143 /* Do those data_ops which can take a negative immediate constant */
2144 /* by altering the instuction. A bit of a hack really */
2148 by inverting the second operand, and
2151 by negating the second operand.
2154 negate_data_op (instruction
, value
)
2155 unsigned long *instruction
;
2156 unsigned long value
;
2159 unsigned long negated
, inverted
;
2161 negated
= validate_immediate (-value
);
2162 inverted
= validate_immediate (~value
);
2164 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
2168 case OPCODE_SUB
: /* ADD <-> SUB */
2169 new_inst
= OPCODE_ADD
;
2174 new_inst
= OPCODE_SUB
;
2178 case OPCODE_CMP
: /* CMP <-> CMN */
2179 new_inst
= OPCODE_CMN
;
2184 new_inst
= OPCODE_CMP
;
2188 /* Now Inverted ops */
2189 case OPCODE_MOV
: /* MOV <-> MVN */
2190 new_inst
= OPCODE_MVN
;
2195 new_inst
= OPCODE_MOV
;
2199 case OPCODE_AND
: /* AND <-> BIC */
2200 new_inst
= OPCODE_BIC
;
2205 new_inst
= OPCODE_AND
;
2209 case OPCODE_ADC
: /* ADC <-> SBC */
2210 new_inst
= OPCODE_SBC
;
2215 new_inst
= OPCODE_ADC
;
2219 /* We cannot do anything */
2227 *instruction
&= OPCODE_MASK
;
2228 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
2239 while (**str
== ' ')
2242 if (reg_required_here (str
, 0) != FAIL
)
2244 if (skip_past_comma (str
) == SUCCESS
)
2246 /* Shift operation on register */
2247 return decode_shift (str
, NO_SHIFT_RESTRICT
);
2253 /* Immediate expression */
2254 if (*((*str
)++) == '#')
2257 if (my_get_expression (&inst
.reloc
.exp
, str
))
2260 if (inst
.reloc
.exp
.X_add_symbol
)
2262 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
2263 inst
.reloc
.pc_rel
= 0;
2267 if (skip_past_comma (str
) == SUCCESS
)
2269 /* #x, y -- ie explicit rotation by Y */
2270 if (my_get_expression (&expr
, str
))
2273 if (expr
.X_op
!= O_constant
)
2275 inst
.error
= "Constant expression expected";
2279 /* Rotate must be a multiple of 2 */
2280 if (((unsigned) expr
.X_add_number
) > 30
2281 || (expr
.X_add_number
& 1) != 0
2282 || ((unsigned) inst
.reloc
.exp
.X_add_number
) > 255)
2284 inst
.error
= "Invalid constant";
2287 inst
.instruction
|= INST_IMMEDIATE
;
2288 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
2289 inst
.instruction
|= expr
.X_add_number
<< 7;
2293 /* Implicit rotation, select a suitable one */
2294 value
= validate_immediate (inst
.reloc
.exp
.X_add_number
);
2298 /* Can't be done, perhaps the code reads something like
2299 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be ok */
2300 if ((value
= negate_data_op (&inst
.instruction
,
2301 inst
.reloc
.exp
.X_add_number
))
2304 inst
.error
= "Invalid constant";
2309 inst
.instruction
|= value
;
2312 inst
.instruction
|= INST_IMMEDIATE
;
2316 inst
.error
= "Register or shift expression expected";
2325 while (**str
== ' ')
2328 if (fp_reg_required_here (str
, 0) != FAIL
)
2332 /* Immediate expression */
2333 if (*((*str
)++) == '#')
2338 while (**str
== ' ')
2341 /* First try and match exact strings, this is to guarantee that
2342 some formats will work even for cross assembly */
2344 for (i
= 0; fp_const
[i
]; i
++)
2346 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
2350 *str
+= strlen (fp_const
[i
]);
2351 if (is_end_of_line
[(int)**str
] || **str
== '\0')
2353 inst
.instruction
|= i
+ 8;
2360 /* Just because we didn't get a match doesn't mean that the
2361 constant isn't valid, just that it is in a format that we
2362 don't automatically recognize. Try parsing it with
2363 the standard expression routines. */
2364 if ((i
= my_get_float_expression (str
)) >= 0)
2366 inst
.instruction
|= i
+ 8;
2370 inst
.error
= "Invalid floating point immediate expression";
2373 inst
.error
= "Floating point register or immediate expression expected";
2379 do_arit (str
, flags
)
2381 unsigned long flags
;
2386 if (reg_required_here (&str
, 12) == FAIL
2387 || skip_past_comma (&str
) == FAIL
2388 || reg_required_here (&str
, 16) == FAIL
2389 || skip_past_comma (&str
) == FAIL
2390 || data_op2 (&str
) == FAIL
)
2393 inst
.error
= bad_args
;
2397 inst
.instruction
|= flags
;
2405 unsigned long flags
;
2407 /* This is a pseudo-op of the form "adr rd, label" to be converted
2408 into a relative address of the form "add rd, pc, #label-.-8" */
2413 if (reg_required_here (&str
, 12) == FAIL
2414 || skip_past_comma (&str
) == FAIL
2415 || my_get_expression (&inst
.reloc
.exp
, &str
))
2418 inst
.error
= bad_args
;
2421 /* Frag hacking will turn this into a sub instruction if the offset turns
2422 out to be negative. */
2423 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
2424 inst
.reloc
.exp
.X_add_number
-= 8; /* PC relative adjust */
2425 inst
.reloc
.pc_rel
= 1;
2426 inst
.instruction
|= flags
;
2434 unsigned long flags
;
2439 if (reg_required_here (&str
, 16) == FAIL
)
2442 inst
.error
= bad_args
;
2446 if (skip_past_comma (&str
) == FAIL
2447 || data_op2 (&str
) == FAIL
)
2450 inst
.error
= bad_args
;
2454 inst
.instruction
|= flags
;
2455 if ((flags
& 0x0000f000) == 0)
2456 inst
.instruction
|= CONDS_BIT
;
2465 unsigned long flags
;
2470 if (reg_required_here (&str
, 12) == FAIL
)
2473 inst
.error
= bad_args
;
2477 if (skip_past_comma (&str
) == FAIL
2478 || data_op2 (&str
) == FAIL
)
2481 inst
.error
= bad_args
;
2485 inst
.instruction
|= flags
;
2491 ldst_extend (str
, hwse
)
2501 if (my_get_expression (&inst
.reloc
.exp
, str
))
2504 if (inst
.reloc
.exp
.X_op
== O_constant
)
2506 int value
= inst
.reloc
.exp
.X_add_number
;
2508 if ((hwse
&& (value
< -255 || value
> 255))
2509 || (value
< -4095 || value
> 4095))
2511 inst
.error
= "address offset too large";
2521 /* Halfword and signextension instructions have the
2522 immediate value split across bits 11..8 and bits 3..0 */
2524 inst
.instruction
|= add
| HWOFFSET_IMM
| (value
>> 4) << 8 | value
& 0xF;
2526 inst
.instruction
|= add
| value
;
2532 inst
.instruction
|= HWOFFSET_IMM
;
2533 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
2536 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
2537 inst
.reloc
.pc_rel
= 0;
2542 add
= 0; /* and fall through */
2544 (*str
)++; /* and fall through */
2546 if (reg_required_here (str
, 0) == FAIL
)
2548 inst
.error
= "Register expected";
2553 inst
.instruction
|= add
;
2556 inst
.instruction
|= add
| OFFSET_REG
;
2557 if (skip_past_comma (str
) == SUCCESS
)
2558 return decode_shift (str
, SHIFT_RESTRICT
);
2566 do_ldst (str
, flags
)
2568 unsigned long flags
;
2575 /* This is not ideal, but it is the simplest way of dealing with the
2576 ARM7T halfword instructions (since they use a different
2577 encoding, but the same mnemonic): */
2578 if (halfword
= ((flags
& 0x80000000) != 0))
2580 /* This is actually a load/store of a halfword, or a
2581 signed-extension load */
2582 if ((cpu_variant
& ARM_ARCH4
) == 0)
2585 = "Processor does not support halfwords or signed bytes\n";
2589 inst
.instruction
= (inst
.instruction
& COND_MASK
)
2590 | (flags
& ~COND_MASK
);
2598 if ((conflict_reg
= reg_required_here (&str
, 12)) == FAIL
)
2601 inst
.error
= bad_args
;
2605 if (skip_past_comma (&str
) == FAIL
)
2607 inst
.error
= "Address expected";
2619 if ((reg
= reg_required_here (&str
, 16)) == FAIL
)
2621 inst
.error
= "Register required";
2625 conflict_reg
= (((conflict_reg
== reg
)
2626 && (inst
.instruction
& LOAD_BIT
))
2635 if (skip_past_comma (&str
) == SUCCESS
)
2637 /* [Rn],... (post inc) */
2638 if (ldst_extend (&str
, halfword
) == FAIL
)
2641 as_warn ("destination register same as write-back base\n");
2647 inst
.instruction
|= HWOFFSET_IMM
;
2655 as_warn ("destination register same as write-back base\n");
2657 inst
.instruction
|= WRITE_BACK
;
2661 if (! (flags
& TRANS_BIT
))
2668 if (skip_past_comma (&str
) == FAIL
)
2670 inst
.error
= "pre-indexed expression expected";
2675 if (ldst_extend (&str
, halfword
) == FAIL
)
2683 inst
.error
= "missing ]";
2693 as_tsktsk ("destination register same as write-back base\n");
2695 inst
.instruction
|= WRITE_BACK
;
2699 else if (*str
== '=')
2701 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
2707 if (my_get_expression (&inst
.reloc
.exp
, &str
))
2710 if (inst
.reloc
.exp
.X_op
!= O_constant
2711 && inst
.reloc
.exp
.X_op
!= O_symbol
)
2713 inst
.error
= "Constant expression expected";
2717 if (inst
.reloc
.exp
.X_op
== O_constant
2718 && (value
= validate_immediate(inst
.reloc
.exp
.X_add_number
)) != FAIL
)
2720 /* This can be done with a mov instruction */
2721 inst
.instruction
&= LITERAL_MASK
;
2722 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
2723 inst
.instruction
|= (flags
& COND_MASK
) | (value
& 0xfff);
2729 /* Insert into literal pool */
2730 if (add_to_lit_pool () == FAIL
)
2733 inst
.error
= "literal pool insertion failed\n";
2737 /* Change the instruction exp to point to the pool */
2740 inst
.instruction
|= HWOFFSET_IMM
;
2741 inst
.reloc
.type
= BFD_RELOC_ARM_HWLITERAL
;
2744 inst
.reloc
.type
= BFD_RELOC_ARM_LITERAL
;
2745 inst
.reloc
.pc_rel
= 1;
2746 inst
.instruction
|= (REG_PC
<< 16);
2752 if (my_get_expression (&inst
.reloc
.exp
, &str
))
2757 inst
.instruction
|= HWOFFSET_IMM
;
2758 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
2761 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
2762 inst
.reloc
.exp
.X_add_number
-= 8; /* PC rel adjust */
2763 inst
.reloc
.pc_rel
= 1;
2764 inst
.instruction
|= (REG_PC
<< 16);
2768 if (pre_inc
&& (flags
& TRANS_BIT
))
2769 inst
.error
= "Pre-increment instruction with translate";
2771 inst
.instruction
|= flags
| (pre_inc
? PRE_INDEX
: 0);
2784 /* We come back here if we get ranges concatenated by '+' or '|' */
2802 if ((reg
= arm_reg_parse (&str
)) == FAIL
|| !int_register (reg
))
2804 inst
.error
= "Register expected";
2814 inst
.error
= "Bad range in register list";
2818 for (i
= cur_reg
+ 1; i
< reg
; i
++)
2820 if (range
& (1 << i
))
2822 ("Warning: Duplicated register (r%d) in register list",
2830 if (range
& (1 << reg
))
2831 as_tsktsk ("Warning: Duplicated register (r%d) in register list",
2833 else if (reg
<= cur_reg
)
2834 as_tsktsk ("Warning: Register range not in ascending order");
2838 } while (skip_past_comma (&str
) != FAIL
2839 || (in_range
= 1, *str
++ == '-'));
2846 inst
.error
= "Missing `}'";
2854 if (my_get_expression (&expr
, &str
))
2857 if (expr
.X_op
== O_constant
)
2859 if (expr
.X_add_number
2860 != (expr
.X_add_number
& 0x0000ffff))
2862 inst
.error
= "invalid register mask";
2866 if ((range
& expr
.X_add_number
) != 0)
2868 int regno
= range
& expr
.X_add_number
;
2871 regno
= (1 << regno
) - 1;
2873 ("Warning: Duplicated register (r%d) in register list",
2877 range
|= expr
.X_add_number
;
2881 if (inst
.reloc
.type
!= 0)
2883 inst
.error
= "expression too complex";
2887 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
2888 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
2889 inst
.reloc
.pc_rel
= 0;
2896 if (*str
== '|' || *str
== '+')
2901 } while (another_range
);
2908 do_ldmstm (str
, flags
)
2910 unsigned long flags
;
2918 if ((base_reg
= reg_required_here (&str
, 16)) == FAIL
)
2921 inst
.error
= bad_args
;
2925 if (base_reg
== REG_PC
)
2927 inst
.error
= "r15 not allowed as base register";
2935 flags
|= WRITE_BACK
;
2939 if (skip_past_comma (&str
) == FAIL
2940 || (range
= reg_list (&str
)) == FAIL
)
2943 inst
.error
= bad_args
;
2950 flags
|= MULTI_SET_PSR
;
2953 inst
.instruction
|= flags
| range
;
2961 unsigned long flags
;
2963 /* Allow optional leading '#'. */
2969 if (my_get_expression (&inst
.reloc
.exp
, &str
))
2972 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
2973 inst
.reloc
.pc_rel
= 0;
2974 inst
.instruction
|= flags
;
2980 do_swap (str
, flags
)
2982 unsigned long flags
;
2989 if ((reg
= reg_required_here (&str
, 12)) == FAIL
)
2994 inst
.error
= "r15 not allowed in swap";
2998 if (skip_past_comma (&str
) == FAIL
2999 || (reg
= reg_required_here (&str
, 0)) == FAIL
)
3002 inst
.error
= bad_args
;
3008 inst
.error
= "r15 not allowed in swap";
3012 if (skip_past_comma (&str
) == FAIL
3015 inst
.error
= bad_args
;
3022 if ((reg
= reg_required_here (&str
, 16)) == FAIL
)
3027 inst
.error
= bad_pc
;
3036 inst
.error
= "missing ]";
3040 inst
.instruction
|= flags
;
3046 do_branch (str
, flags
)
3048 unsigned long flags
;
3050 if (my_get_expression (&inst
.reloc
.exp
, &str
))
3052 inst
.reloc
.type
= BFD_RELOC_ARM_PCREL_BRANCH
;
3053 inst
.reloc
.pc_rel
= 1;
3061 unsigned long flags
;
3068 if ((reg
= reg_required_here (&str
, 0)) == FAIL
)
3072 as_tsktsk ("Use of r15 in bx has undefined behaviour");
3081 unsigned long flags
;
3083 /* Co-processor data operation.
3084 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
3088 if (co_proc_number (&str
) == FAIL
)
3091 inst
.error
= bad_args
;
3095 if (skip_past_comma (&str
) == FAIL
3096 || cp_opc_expr (&str
, 20,4) == FAIL
)
3099 inst
.error
= bad_args
;
3103 if (skip_past_comma (&str
) == FAIL
3104 || cp_reg_required_here (&str
, 12) == FAIL
)
3107 inst
.error
= bad_args
;
3111 if (skip_past_comma (&str
) == FAIL
3112 || cp_reg_required_here (&str
, 16) == FAIL
)
3115 inst
.error
= bad_args
;
3119 if (skip_past_comma (&str
) == FAIL
3120 || cp_reg_required_here (&str
, 0) == FAIL
)
3123 inst
.error
= bad_args
;
3127 if (skip_past_comma (&str
) == SUCCESS
)
3129 if (cp_opc_expr (&str
, 5, 3) == FAIL
)
3132 inst
.error
= bad_args
;
3142 do_lstc (str
, flags
)
3144 unsigned long flags
;
3146 /* Co-processor register load/store.
3147 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
3152 if (co_proc_number (&str
) == FAIL
)
3155 inst
.error
= bad_args
;
3159 if (skip_past_comma (&str
) == FAIL
3160 || cp_reg_required_here (&str
, 12) == FAIL
)
3163 inst
.error
= bad_args
;
3167 if (skip_past_comma (&str
) == FAIL
3168 || cp_address_required_here (&str
) == FAIL
)
3171 inst
.error
= bad_args
;
3175 inst
.instruction
|= flags
;
3181 do_co_reg (str
, flags
)
3183 unsigned long flags
;
3185 /* Co-processor register transfer.
3186 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
3191 if (co_proc_number (&str
) == FAIL
)
3194 inst
.error
= bad_args
;
3198 if (skip_past_comma (&str
) == FAIL
3199 || cp_opc_expr (&str
, 21, 3) == FAIL
)
3202 inst
.error
= bad_args
;
3206 if (skip_past_comma (&str
) == FAIL
3207 || reg_required_here (&str
, 12) == FAIL
)
3210 inst
.error
= bad_args
;
3214 if (skip_past_comma (&str
) == FAIL
3215 || cp_reg_required_here (&str
, 16) == FAIL
)
3218 inst
.error
= bad_args
;
3222 if (skip_past_comma (&str
) == FAIL
3223 || cp_reg_required_here (&str
, 0) == FAIL
)
3226 inst
.error
= bad_args
;
3230 if (skip_past_comma (&str
) == SUCCESS
)
3232 if (cp_opc_expr (&str
, 5, 3) == FAIL
)
3235 inst
.error
= bad_args
;
3245 do_fp_ctrl (str
, flags
)
3247 unsigned long flags
;
3249 /* FP control registers.
3250 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
3255 if (reg_required_here (&str
, 12) == FAIL
)
3258 inst
.error
= bad_args
;
3267 do_fp_ldst (str
, flags
)
3269 unsigned long flags
;
3274 switch (inst
.suffix
)
3279 inst
.instruction
|= CP_T_X
;
3282 inst
.instruction
|= CP_T_Y
;
3285 inst
.instruction
|= CP_T_X
| CP_T_Y
;
3291 if (fp_reg_required_here (&str
, 12) == FAIL
)
3294 inst
.error
= bad_args
;
3298 if (skip_past_comma (&str
) == FAIL
3299 || cp_address_required_here (&str
) == FAIL
)
3302 inst
.error
= bad_args
;
3310 do_fp_ldmstm (str
, flags
)
3312 unsigned long flags
;
3319 if (fp_reg_required_here (&str
, 12) == FAIL
)
3322 inst
.error
= bad_args
;
3326 /* Get Number of registers to transfer */
3327 if (skip_past_comma (&str
) == FAIL
3328 || my_get_expression (&inst
.reloc
.exp
, &str
))
3331 inst
.error
= "constant expression expected";
3335 if (inst
.reloc
.exp
.X_op
!= O_constant
)
3337 inst
.error
= "Constant value required for number of registers";
3341 num_regs
= inst
.reloc
.exp
.X_add_number
;
3343 if (num_regs
< 1 || num_regs
> 4)
3345 inst
.error
= "number of registers must be in the range [1:4]";
3352 inst
.instruction
|= CP_T_X
;
3355 inst
.instruction
|= CP_T_Y
;
3358 inst
.instruction
|= CP_T_Y
| CP_T_X
;
3372 /* The instruction specified "ea" or "fd", so we can only accept
3373 [Rn]{!}. The instruction does not really support stacking or
3374 unstacking, so we have to emulate these by setting appropriate
3375 bits and offsets. */
3376 if (skip_past_comma (&str
) == FAIL
3380 inst
.error
= bad_args
;
3388 if ((reg
= reg_required_here (&str
, 16)) == FAIL
)
3390 inst
.error
= "Register required";
3399 inst
.error
= bad_args
;
3410 inst
.error
= "R15 not allowed as base register with write-back";
3417 if (flags
& CP_T_Pre
)
3420 offset
= 3 * num_regs
;
3426 /* Post-increment */
3430 offset
= 3 * num_regs
;
3434 /* No write-back, so convert this into a standard pre-increment
3435 instruction -- aesthetically more pleasing. */
3436 flags
= CP_T_Pre
| CP_T_UD
;
3441 inst
.instruction
|= flags
| offset
;
3443 else if (skip_past_comma (&str
) == FAIL
3444 || cp_address_required_here (&str
) == FAIL
)
3447 inst
.error
= bad_args
;
3455 do_fp_dyadic (str
, flags
)
3457 unsigned long flags
;
3462 switch (inst
.suffix
)
3467 inst
.instruction
|= 0x00000080;
3470 inst
.instruction
|= 0x00080000;
3476 if (fp_reg_required_here (&str
, 12) == FAIL
)
3479 inst
.error
= bad_args
;
3483 if (skip_past_comma (&str
) == FAIL
3484 || fp_reg_required_here (&str
, 16) == FAIL
)
3487 inst
.error
= bad_args
;
3491 if (skip_past_comma (&str
) == FAIL
3492 || fp_op2 (&str
) == FAIL
)
3495 inst
.error
= bad_args
;
3499 inst
.instruction
|= flags
;
3505 do_fp_monadic (str
, flags
)
3507 unsigned long flags
;
3512 switch (inst
.suffix
)
3517 inst
.instruction
|= 0x00000080;
3520 inst
.instruction
|= 0x00080000;
3526 if (fp_reg_required_here (&str
, 12) == FAIL
)
3529 inst
.error
= bad_args
;
3533 if (skip_past_comma (&str
) == FAIL
3534 || fp_op2 (&str
) == FAIL
)
3537 inst
.error
= bad_args
;
3541 inst
.instruction
|= flags
;
3547 do_fp_cmp (str
, flags
)
3549 unsigned long flags
;
3554 if (fp_reg_required_here (&str
, 16) == FAIL
)
3557 inst
.error
= bad_args
;
3561 if (skip_past_comma (&str
) == FAIL
3562 || fp_op2 (&str
) == FAIL
)
3565 inst
.error
= bad_args
;
3569 inst
.instruction
|= flags
;
3575 do_fp_from_reg (str
, flags
)
3577 unsigned long flags
;
3582 switch (inst
.suffix
)
3587 inst
.instruction
|= 0x00000080;
3590 inst
.instruction
|= 0x00080000;
3596 if (fp_reg_required_here (&str
, 16) == FAIL
)
3599 inst
.error
= bad_args
;
3603 if (skip_past_comma (&str
) == FAIL
3604 || reg_required_here (&str
, 12) == FAIL
)
3607 inst
.error
= bad_args
;
3611 inst
.instruction
|= flags
;
3617 do_fp_to_reg (str
, flags
)
3619 unsigned long flags
;
3624 if (reg_required_here (&str
, 12) == FAIL
)
3627 inst
.error
= bad_args
;
3631 if (skip_past_comma (&str
) == FAIL
3632 || fp_reg_required_here (&str
, 0) == FAIL
)
3635 inst
.error
= bad_args
;
3639 inst
.instruction
|= flags
;
3644 /* Thumb specific routines */
3646 /* Parse and validate that a register is of the right form, this saves
3647 repeated checking of this information in many similar cases.
3648 Unlike the 32-bit case we do not insert the register into the opcode
3649 here, since the position is often unknown until the full instruction
3652 thumb_reg (strp
, hi_lo
)
3658 if ((reg
= arm_reg_parse (strp
)) == FAIL
|| ! int_register (reg
))
3660 inst
.error
= "Register expected";
3669 inst
.error
= "lo register required";
3677 inst
.error
= "hi register required";
3689 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
3692 thumb_add_sub (str
, subtract
)
3696 int Rd
, Rs
, Rn
= FAIL
;
3701 if ((Rd
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
3702 || skip_past_comma (&str
) == FAIL
)
3705 inst
.error
= bad_args
;
3713 if (my_get_expression (&inst
.reloc
.exp
, &str
))
3718 if ((Rs
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
3721 if (skip_past_comma (&str
) == FAIL
)
3723 /* Two operand format, shuffle the registers and pretend there
3728 else if (*str
== '#')
3731 if (my_get_expression (&inst
.reloc
.exp
, &str
))
3734 else if ((Rn
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
3738 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
3739 for the latter case, EXPR contains the immediate that was found. */
3742 /* All register format. */
3743 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
3747 inst
.error
= "dest and source1 must be the same register";
3751 /* Can't do this for SUB */
3754 inst
.error
= "subtract valid only on lo regs";
3758 inst
.instruction
= (T_OPCODE_ADD_HI
3759 | (Rd
> 7 ? THUMB_H1
: 0)
3760 | (Rn
> 7 ? THUMB_H2
: 0));
3761 inst
.instruction
|= (Rd
& 7) | ((Rn
& 7) << 3);
3765 inst
.instruction
= subtract
? T_OPCODE_SUB_R3
: T_OPCODE_ADD_R3
;
3766 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
3771 /* Immediate expression, now things start to get nasty. */
3773 /* First deal with HI regs, only very restricted cases allowed:
3774 Adjusting SP, and using PC or SP to get an address. */
3775 if ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
3776 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
))
3778 inst
.error
= "invalid Hi register with immediate";
3782 if (inst
.reloc
.exp
.X_op
!= O_constant
)
3784 /* Value isn't known yet, all we can do is store all the fragments
3785 we know about in the instruction and let the reloc hacking
3787 inst
.instruction
= (subtract
? 0x8000 : 0) | (Rd
<< 4) | Rs
;
3788 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
3792 int offset
= inst
.reloc
.exp
.X_add_number
;
3802 /* Quick check, in case offset is MIN_INT */
3805 inst
.error
= "immediate value out of range";
3814 if (offset
& ~0x1fc)
3816 inst
.error
= "invalid immediate value for stack adjust";
3819 inst
.instruction
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
3820 inst
.instruction
|= offset
>> 2;
3822 else if (Rs
== REG_PC
|| Rs
== REG_SP
)
3825 || (offset
& ~0x3fc))
3827 inst
.error
= "invalid immediate for address calculation";
3830 inst
.instruction
= (Rs
== REG_PC
? T_OPCODE_ADD_PC
3832 inst
.instruction
|= (Rd
<< 8) | (offset
>> 2);
3838 inst
.error
= "immediate value out of range";
3841 inst
.instruction
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
3842 inst
.instruction
|= (Rd
<< 8) | offset
;
3848 inst
.error
= "immediate value out of range";
3851 inst
.instruction
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
3852 inst
.instruction
|= Rd
| (Rs
<< 3) | (offset
<< 6);
3860 thumb_shift (str
, shift
)
3864 int Rd
, Rs
, Rn
= FAIL
;
3869 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
3870 || skip_past_comma (&str
) == FAIL
)
3873 inst
.error
= bad_args
;
3879 /* Two operand immediate format, set Rs to Rd. */
3882 if (my_get_expression (&inst
.reloc
.exp
, &str
))
3887 if ((Rs
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
3890 if (skip_past_comma (&str
) == FAIL
)
3892 /* Two operand format, shuffle the registers and pretend there
3897 else if (*str
== '#')
3900 if (my_get_expression (&inst
.reloc
.exp
, &str
))
3903 else if ((Rn
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
3907 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
3908 for the latter case, EXPR contains the immediate that was found. */
3914 inst
.error
= "source1 and dest must be same register";
3920 case THUMB_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
3921 case THUMB_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
3922 case THUMB_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
3925 inst
.instruction
|= Rd
| (Rn
<< 3);
3931 case THUMB_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
3932 case THUMB_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
3933 case THUMB_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
3936 if (inst
.reloc
.exp
.X_op
!= O_constant
)
3938 /* Value isn't known yet, create a dummy reloc and let reloc
3939 hacking fix it up */
3941 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
3945 unsigned shift_value
= inst
.reloc
.exp
.X_add_number
;
3947 if (shift_value
> 32 || (shift_value
== 32 && shift
== THUMB_LSL
))
3949 inst
.error
= "Invalid immediate for shift";
3953 /* Shifts of zero are handled by converting to LSL */
3954 if (shift_value
== 0)
3955 inst
.instruction
= T_OPCODE_LSL_I
;
3957 /* Shifts of 32 are encoded as a shift of zero */
3958 if (shift_value
== 32)
3961 inst
.instruction
|= shift_value
<< 6;
3964 inst
.instruction
|= Rd
| (Rs
<< 3);
3970 thumb_mov_compare (str
, move
)
3979 if ((Rd
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
3980 || skip_past_comma (&str
) == FAIL
)
3983 inst
.error
= bad_args
;
3990 if (my_get_expression (&inst
.reloc
.exp
, &str
))
3993 else if ((Rs
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
3998 if (Rs
< 8 && Rd
< 8)
4000 if (move
== THUMB_MOVE
)
4001 /* A move of two lowregs is, by convention, encoded as
4003 inst
.instruction
= T_OPCODE_ADD_I3
;
4005 inst
.instruction
= T_OPCODE_CMP_LR
;
4006 inst
.instruction
|= Rd
| (Rs
<< 3);
4010 if (move
== THUMB_MOVE
)
4011 inst
.instruction
= T_OPCODE_MOV_HR
;
4013 inst
.instruction
= T_OPCODE_CMP_HR
;
4016 inst
.instruction
|= THUMB_H1
;
4019 inst
.instruction
|= THUMB_H2
;
4021 inst
.instruction
|= (Rd
& 7) | ((Rs
& 7) << 3);
4028 inst
.error
= "only lo regs allowed with immediate";
4032 if (move
== THUMB_MOVE
)
4033 inst
.instruction
= T_OPCODE_MOV_I8
;
4035 inst
.instruction
= T_OPCODE_CMP_I8
;
4037 inst
.instruction
|= Rd
<< 8;
4039 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4040 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
4043 unsigned value
= inst
.reloc
.exp
.X_add_number
;
4047 inst
.error
= "invalid immediate";
4051 inst
.instruction
|= value
;
4059 thumb_load_store (str
, load_store
, size
)
4064 int Rd
, Rb
, Ro
= FAIL
;
4069 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
4070 || skip_past_comma (&str
) == FAIL
)
4073 inst
.error
= bad_args
;
4080 if ((Rb
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
4083 if (skip_past_comma (&str
) != FAIL
)
4088 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4091 else if ((Ro
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4096 inst
.reloc
.exp
.X_op
= O_constant
;
4097 inst
.reloc
.exp
.X_add_number
= 0;
4102 inst
.error
= "expected ']'";
4107 else if (*str
== '=')
4109 /* TODO: We should allow the "ldr Rd,=expr" pseudo op in thumb mode */
4114 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4117 inst
.instruction
= T_OPCODE_LDR_PC
| (Rd
<< 8);
4118 inst
.reloc
.pc_rel
= 1;
4119 inst
.reloc
.exp
.X_add_number
-= 4; /* Pipeline offset */
4120 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
4125 if (Rb
== REG_PC
|| Rb
== REG_SP
)
4127 if (size
!= THUMB_WORD
)
4129 inst
.error
= "byte or halfword not valid for base register";
4132 else if (Rb
== REG_PC
&& load_store
!= THUMB_LOAD
)
4134 inst
.error
= "R15 based store not allowed";
4137 else if (Ro
!= FAIL
)
4139 inst
.error
= "Invalid base register for register offset";
4144 inst
.instruction
= T_OPCODE_LDR_PC
;
4145 else if (load_store
== THUMB_LOAD
)
4146 inst
.instruction
= T_OPCODE_LDR_SP
;
4148 inst
.instruction
= T_OPCODE_STR_SP
;
4150 inst
.instruction
|= Rd
<< 8;
4151 if (inst
.reloc
.exp
.X_op
== O_constant
)
4153 unsigned offset
= inst
.reloc
.exp
.X_add_number
;
4155 if (offset
& ~0x3fc)
4157 inst
.error
= "invalid offset";
4161 inst
.instruction
|= offset
>> 2;
4164 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
4168 inst
.error
= "invalid base register in load/store";
4171 else if (Ro
== FAIL
)
4173 /* Immediate offset */
4174 if (size
== THUMB_WORD
)
4175 inst
.instruction
= (load_store
== THUMB_LOAD
4176 ? T_OPCODE_LDR_IW
: T_OPCODE_STR_IW
);
4177 else if (size
== THUMB_HALFWORD
)
4178 inst
.instruction
= (load_store
== THUMB_LOAD
4179 ? T_OPCODE_LDR_IH
: T_OPCODE_STR_IH
);
4181 inst
.instruction
= (load_store
== THUMB_LOAD
4182 ? T_OPCODE_LDR_IB
: T_OPCODE_STR_IB
);
4184 inst
.instruction
|= Rd
| (Rb
<< 3);
4186 if (inst
.reloc
.exp
.X_op
== O_constant
)
4188 unsigned offset
= inst
.reloc
.exp
.X_add_number
;
4190 if (offset
& ~(0x1f << size
))
4192 inst
.error
= "Invalid offset";
4195 inst
.instruction
|= (offset
>> size
) << 6;
4198 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
4202 /* Register offset */
4203 if (size
== THUMB_WORD
)
4204 inst
.instruction
= (load_store
== THUMB_LOAD
4205 ? T_OPCODE_LDR_RW
: T_OPCODE_STR_RW
);
4206 else if (size
== THUMB_HALFWORD
)
4207 inst
.instruction
= (load_store
== THUMB_LOAD
4208 ? T_OPCODE_LDR_RH
: T_OPCODE_STR_RH
);
4210 inst
.instruction
= (load_store
== THUMB_LOAD
4211 ? T_OPCODE_LDR_RB
: T_OPCODE_STR_RB
);
4213 inst
.instruction
|= Rd
| (Rb
<< 3) | (Ro
<< 6);
4228 /* Handle the Format 4 instructions that do not have equivalents in other
4229 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
4240 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4243 if (skip_past_comma (&str
) == FAIL
4244 || (Rs
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4247 inst
.error
= bad_args
;
4251 if (skip_past_comma (&str
) != FAIL
)
4253 /* Three operand format not allowed for TST, CMN, NEG and MVN.
4254 (It isn't allowed for CMP either, but that isn't handled by this
4256 if (inst
.instruction
== T_OPCODE_TST
4257 || inst
.instruction
== T_OPCODE_CMN
4258 || inst
.instruction
== T_OPCODE_NEG
4259 || inst
.instruction
== T_OPCODE_MVN
)
4261 inst
.error
= bad_args
;
4265 if ((Rn
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4270 inst
.error
= "dest and source1 one must be the same register";
4276 if (inst
.instruction
== T_OPCODE_MUL
4278 as_tsktsk ("Rs and Rd must be different in MUL");
4280 inst
.instruction
|= Rd
| (Rs
<< 3);
4288 thumb_add_sub (str
, 0);
4295 thumb_shift (str
, THUMB_ASR
);
4302 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4304 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
4305 inst
.reloc
.pc_rel
= 1;
4313 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4315 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
4316 inst
.reloc
.pc_rel
= 1;
4324 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4326 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
4327 inst
.reloc
.pc_rel
= 1;
4340 if ((reg
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
4343 /* This sets THUMB_H2 from the top bit of reg. */
4344 inst
.instruction
|= reg
<< 3;
4346 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
4347 should cause the alignment to be checked once it is known. This is
4348 because BX PC only works if the instruction is word aligned. */
4357 thumb_mov_compare (str
, THUMB_COMPARE
);
4370 if ((Rb
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4374 as_warn ("Inserted missing '!': load/store multiple always writes back base register");
4378 if (skip_past_comma (&str
) == FAIL
4379 || (range
= reg_list (&str
)) == FAIL
)
4382 inst
.error
= bad_args
;
4386 if (inst
.reloc
.type
!= BFD_RELOC_NONE
)
4388 /* This really doesn't seem worth it. */
4389 inst
.reloc
.type
= BFD_RELOC_NONE
;
4390 inst
.error
= "Expression too complex";
4396 inst
.error
= "only lo-regs valid in load/store multiple";
4400 inst
.instruction
|= (Rb
<< 8) | range
;
4408 thumb_load_store (str
, THUMB_LOAD
, THUMB_WORD
);
4415 thumb_load_store (str
, THUMB_LOAD
, THUMB_BYTE
);
4422 thumb_load_store (str
, THUMB_LOAD
, THUMB_HALFWORD
);
4434 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
4435 || skip_past_comma (&str
) == FAIL
4437 || (Rb
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
4438 || skip_past_comma (&str
) == FAIL
4439 || (Ro
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
4443 inst
.error
= "Syntax: ldrs[b] Rd, [Rb, Ro]";
4447 inst
.instruction
|= Rd
| (Rb
<< 3) | (Ro
<< 6);
4455 thumb_shift (str
, THUMB_LSL
);
4462 thumb_shift (str
, THUMB_LSR
);
4469 thumb_mov_compare (str
, THUMB_MOVE
);
4481 if ((range
= reg_list (&str
)) == FAIL
)
4484 inst
.error
= bad_args
;
4488 if (inst
.reloc
.type
!= BFD_RELOC_NONE
)
4490 /* This really doesn't seem worth it. */
4491 inst
.reloc
.type
= BFD_RELOC_NONE
;
4492 inst
.error
= "Expression too complex";
4498 if ((inst
.instruction
== T_OPCODE_PUSH
4499 && (range
& ~0xff) == 1 << REG_LR
)
4500 || (inst
.instruction
== T_OPCODE_POP
4501 && (range
& ~0xff) == 1 << REG_PC
))
4503 inst
.instruction
|= THUMB_PP_PC_LR
;
4508 inst
.error
= "invalid register list to push/pop instruction";
4513 inst
.instruction
|= range
;
4521 thumb_load_store (str
, THUMB_STORE
, THUMB_WORD
);
4528 thumb_load_store (str
, THUMB_STORE
, THUMB_BYTE
);
4535 thumb_load_store (str
, THUMB_STORE
, THUMB_HALFWORD
);
4542 thumb_add_sub (str
, 1);
4552 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4555 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
4564 /* This is a pseudo-op of the form "adr rd, label" to be converted
4565 into a relative address of the form "add rd, pc, #label-.-4" */
4569 if (reg_required_here (&str
, 8) == FAIL
4570 || skip_past_comma (&str
) == FAIL
4571 || my_get_expression (&inst
.reloc
.exp
, &str
))
4574 inst
.error
= bad_args
;
4578 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
4579 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust */
4580 inst
.reloc
.pc_rel
= 1;
4581 inst
.instruction
|= REG_PC
; /* Rd is already placed into the instruction */
4589 int len
= strlen (reg_table
[entry
].name
) + 2;
4590 char *buf
= (char *) xmalloc (len
);
4591 char *buf2
= (char *) xmalloc (len
);
4594 #ifdef REGISTER_PREFIX
4595 buf
[i
++] = REGISTER_PREFIX
;
4598 strcpy (buf
+ i
, reg_table
[entry
].name
);
4600 for (i
= 0; buf
[i
]; i
++)
4601 buf2
[i
] = islower (buf
[i
]) ? toupper (buf
[i
]) : buf
[i
];
4605 hash_insert (arm_reg_hsh
, buf
, (PTR
) ®_table
[entry
]);
4606 hash_insert (arm_reg_hsh
, buf2
, (PTR
) ®_table
[entry
]);
4610 insert_reg_alias (str
, regnum
)
4614 struct reg_entry
*new =
4615 (struct reg_entry
*)xmalloc (sizeof (struct reg_entry
));
4616 char *name
= xmalloc (strlen (str
) + 1);
4620 new->number
= regnum
;
4622 hash_insert (arm_reg_hsh
, name
, (PTR
) new);
4626 set_constant_flonums ()
4630 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4631 if (atof_ieee ((char *)fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
4640 if ((arm_ops_hsh
= hash_new ()) == NULL
4641 || (arm_tops_hsh
= hash_new ()) == NULL
4642 || (arm_cond_hsh
= hash_new ()) == NULL
4643 || (arm_shift_hsh
= hash_new ()) == NULL
4644 || (arm_reg_hsh
= hash_new ()) == NULL
4645 || (arm_psr_hsh
= hash_new ()) == NULL
)
4646 as_fatal ("Virtual memory exhausted");
4648 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
4649 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
4650 for (i
= 0; i
< sizeof (tinsns
) / sizeof (struct thumb_opcode
); i
++)
4651 hash_insert (arm_tops_hsh
, tinsns
[i
].template, (PTR
) (tinsns
+ i
));
4652 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
4653 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
4654 for (i
= 0; i
< sizeof (shift
) / sizeof (struct asm_shift
); i
++)
4655 hash_insert (arm_shift_hsh
, shift
[i
].template, (PTR
) (shift
+ i
));
4656 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
4657 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
4659 for (i
= 0; reg_table
[i
].name
; i
++)
4662 set_constant_flonums ();
4665 /* Set the flags in the private structure */
4666 bfd_set_private_flags (stdoutput
, uses_apcs_26
? F_APCS26
: 0);
4672 /* Record the CPU type as well */
4673 switch (cpu_variant
& ARM_CPU_MASK
)
4676 mach
= bfd_mach_arm_2
;
4679 case ARM_3
: /* also ARM_250 */
4680 mach
= bfd_mach_arm_2a
;
4684 case ARM_6
| ARM_3
| ARM_2
: /* Actually no CPU type defined */
4685 mach
= bfd_mach_arm_4
;
4688 case ARM_7
: /* also ARM_6 */
4689 mach
= bfd_mach_arm_3
;
4693 /* Catch special cases */
4694 if (cpu_variant
!= (FPU_DEFAULT
| CPU_DEFAULT
))
4696 if (cpu_variant
& ARM_THUMB
)
4697 mach
= bfd_mach_arm_4T
;
4698 else if (cpu_variant
& ARM_ARCH4
)
4699 mach
= bfd_mach_arm_4
;
4700 else if (cpu_variant
& ARM_LONGMUL
)
4701 mach
= bfd_mach_arm_3M
;
4704 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
4708 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
4709 for use in the a.out file, and stores them in the array pointed to by buf.
4710 This knows about the endian-ness of the target machine and does
4711 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
4712 2 (short) and 4 (long) Floating numbers are put out as a series of
4713 LITTLENUMS (shorts, here at least)
4716 md_number_to_chars (buf
, val
, n
)
4721 if (target_big_endian
)
4722 number_to_chars_bigendian (buf
, val
, n
);
4724 number_to_chars_littleendian (buf
, val
, n
);
4728 md_chars_to_number (buf
, n
)
4733 unsigned char *where
= (unsigned char *) buf
;
4735 if (target_big_endian
)
4740 result
|= (*where
++ & 255);
4748 result
|= (where
[n
] & 255);
4755 /* Turn a string in input_line_pointer into a floating point constant
4756 of type TYPE, and store the appropriate bytes in *litP. The number
4757 of LITTLENUMS emitted is stored in *sizeP . An error message is
4758 returned, or NULL on OK.
4760 Note that fp constants aren't represent in the normal way on the ARM.
4761 In big endian mode, things are as expected. However, in little endian
4762 mode fp constants are big-endian word-wise, and little-endian byte-wise
4763 within the words. For example, (double) 1.1 in big endian mode is
4764 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
4765 the byte sequence 99 99 f1 3f 9a 99 99 99.
4767 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
4770 md_atof (type
, litP
, sizeP
)
4776 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4808 return "Bad call to MD_ATOF()";
4811 t
= atof_ieee (input_line_pointer
, type
, words
);
4813 input_line_pointer
= t
;
4816 if (target_big_endian
)
4818 for (i
= 0; i
< prec
; i
++)
4820 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4826 /* For a 4 byte float the order of elements in `words' is 1 0. For an
4827 8 byte float the order is 1 0 3 2. */
4828 for (i
= 0; i
< prec
; i
+= 2)
4830 md_number_to_chars (litP
, (valueT
) words
[i
+ 1], 2);
4831 md_number_to_chars (litP
+ 2, (valueT
) words
[i
], 2);
4839 /* We have already put the pipeline compensation in the instruction */
4842 md_pcrel_from (fixP
)
4845 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) == undefined_section
4846 && fixP
->fx_subsy
== NULL
)
4847 return 0; /* HACK */
4849 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4852 /* Round up a section size to the appropriate boundary. */
4854 md_section_align (segment
, size
)
4858 /* Round all sects to multiple of 4 */
4859 return (size
+ 3) & ~3;
4862 /* We have no need to default values of symbols. */
4866 md_undefined_symbol (name
)
4872 /* arm_reg_parse () := if it looks like a register, return its token and
4873 advance the pointer. */
4877 register char **ccp
;
4882 struct reg_entry
*reg
;
4884 #ifdef REGISTER_PREFIX
4885 if (*start
!= REGISTER_PREFIX
)
4890 #ifdef OPTIONAL_REGISTER_PREFIX
4891 if (*p
== OPTIONAL_REGISTER_PREFIX
)
4895 if (!isalpha (*p
) || !is_name_beginner (*p
))
4899 while (isalpha (c
) || isdigit (c
) || c
== '_')
4903 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, start
);
4917 register char **ccp
;
4921 CONST
struct asm_psr
*psr
;
4925 while (isalpha (c
) || c
== '_')
4929 psr
= (CONST
struct asm_psr
*) hash_find (arm_psr_hsh
, start
);
4942 md_apply_fix3 (fixP
, val
, seg
)
4947 offsetT value
= *val
;
4948 offsetT newval
, temp
;
4950 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4951 arm_fix_data
*arm_data
= (arm_fix_data
*) fixP
->tc_fix_data
;
4953 assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
4955 /* Note whether this will delete the relocation. */
4956 #if 0 /* patch from REarnshaw to JDavis (disabled for the moment, since it doesn't work fully) */
4957 if ((fixP
->fx_addsy
== 0 || fixP
->fx_addsy
->sy_value
.X_op
== O_constant
)
4960 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
4964 /* If this symbol is in a different section then we need to leave it for
4965 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
4966 so we have to undo it's effects here. */
4969 if (S_IS_DEFINED (fixP
->fx_addsy
)
4970 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4971 value
+= md_pcrel_from (fixP
);
4974 fixP
->fx_addnumber
= value
; /* Remember value for emit_reloc */
4976 switch (fixP
->fx_r_type
)
4978 case BFD_RELOC_ARM_IMMEDIATE
:
4979 newval
= validate_immediate (value
);
4980 temp
= md_chars_to_number (buf
, INSN_SIZE
);
4982 /* If the instruction will fail, see if we can fix things up by
4983 changing the opcode. */
4985 && (newval
= negate_data_op (&temp
, value
)) == FAIL
)
4987 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4988 "invalid constant after fixup\n");
4992 newval
|= (temp
& 0xfffff000);
4993 md_number_to_chars (buf
, newval
, INSN_SIZE
);
4996 case BFD_RELOC_ARM_OFFSET_IMM
:
4998 if ((value
= validate_offset_imm (value
, 0)) == FAIL
)
5000 as_bad ("bad immediate value for offset (%d)", val
);
5006 newval
= md_chars_to_number (buf
, INSN_SIZE
);
5007 newval
&= 0xff7ff000;
5008 newval
|= value
| (sign
? INDEX_UP
: 0);
5009 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5012 case BFD_RELOC_ARM_OFFSET_IMM8
:
5013 case BFD_RELOC_ARM_HWLITERAL
:
5015 if ((value
= validate_offset_imm (value
, 1)) == FAIL
)
5017 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
5018 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5019 "invalid literal constant: pool needs to be closer\n");
5021 as_bad ("bad immediate value for offset (%d)", value
);
5028 newval
= md_chars_to_number (buf
, INSN_SIZE
);
5029 newval
&= 0xff7ff0f0;
5030 newval
|= ((value
>> 4) << 8) | value
& 0xf | (sign
? INDEX_UP
: 0);
5031 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5034 case BFD_RELOC_ARM_LITERAL
:
5039 if ((value
= validate_offset_imm (value
, 0)) == FAIL
)
5041 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5042 "invalid literal constant: pool needs to be closer\n");
5046 newval
= md_chars_to_number (buf
, INSN_SIZE
);
5047 newval
&= 0xff7ff000;
5048 newval
|= value
| (sign
? INDEX_UP
: 0);
5049 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5052 case BFD_RELOC_ARM_SHIFT_IMM
:
5053 newval
= md_chars_to_number (buf
, INSN_SIZE
);
5054 if (((unsigned long) value
) > 32
5056 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
5058 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5059 "shift expression is too large");
5064 newval
&= ~0x60; /* Shifts of zero must be done as lsl */
5065 else if (value
== 32)
5067 newval
&= 0xfffff07f;
5068 newval
|= (value
& 0x1f) << 7;
5069 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5072 case BFD_RELOC_ARM_SWI
:
5073 if (arm_data
->thumb_mode
)
5075 if (((unsigned long) value
) > 0xff)
5076 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5077 "Invalid swi expression");
5078 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xff00;
5080 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5084 if (((unsigned long) value
) > 0x00ffffff)
5085 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5086 "Invalid swi expression");
5087 newval
= md_chars_to_number (buf
, INSN_SIZE
) & 0xff000000;
5089 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5093 case BFD_RELOC_ARM_MULTI
:
5094 if (((unsigned long) value
) > 0xffff)
5095 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5096 "Invalid expression in load/store multiple");
5097 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
5098 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5101 case BFD_RELOC_ARM_PCREL_BRANCH
:
5102 value
= (value
>> 2) & 0x00ffffff;
5103 newval
= md_chars_to_number (buf
, INSN_SIZE
);
5104 value
= (value
+ (newval
& 0x00ffffff)) & 0x00ffffff;
5105 newval
= value
| (newval
& 0xff000000);
5106 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5109 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* conditional branch */
5110 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
5112 addressT diff
= (newval
& 0xff) << 1;
5117 if ((value
& 0x100) && ((value
& ~0xff) != ~0xff))
5118 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5119 "Branch out of range");
5120 newval
= (newval
& 0xff00) | ((value
& 0x1ff) >> 1);
5122 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5125 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* unconditional branch */
5126 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
5128 addressT diff
= (newval
& 0x7ff) << 1;
5133 if ((value
& 0x800) && ((value
& ~0x7ff) != ~0x7ff))
5134 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5135 "Branch out of range");
5136 newval
= (newval
& 0xf800) | ((value
& 0xfff) >> 1);
5138 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5141 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
5142 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
5147 newval2
= md_chars_to_number (buf
+ 2, THUMB_SIZE
);
5148 diff
= ((newval
& 0x7ff) << 12) | ((newval2
& 0x7ff) << 1);
5149 if (diff
& 0x400000)
5152 if ((value
& 0x400000) && ((value
& ~0x3fffff) != ~0x3fffff))
5153 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5154 "Branch with link out of range");
5156 newval
= (newval
& 0xf800) | ((value
& 0x7fffff) >> 12);
5157 newval2
= (newval2
& 0xf800) | ((value
& 0xfff) >> 1);
5158 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5159 md_number_to_chars (buf
+ 2, newval2
, THUMB_SIZE
);
5164 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
5165 md_number_to_chars (buf
, value
, 1);
5169 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
5170 md_number_to_chars (buf
, value
, 2);
5175 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
5176 md_number_to_chars (buf
, value
, 4);
5179 case BFD_RELOC_ARM_CP_OFF_IMM
:
5181 if (value
< -1023 || value
> 1023 || (value
& 3))
5182 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5183 "Illegal value for co-processor offset");
5186 newval
= md_chars_to_number (buf
, INSN_SIZE
) & 0xff7fff00;
5187 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
5188 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5191 case BFD_RELOC_ARM_THUMB_OFFSET
:
5192 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
5193 /* Exactly what ranges, and where the offset is inserted depends on
5194 the type of instruction, we can establish this from the top 4 bits */
5195 switch (newval
>> 12)
5197 case 4: /* PC load */
5198 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
5199 forced to zero for these loads, so we will need to round
5200 up the offset if the instruction address is not word
5201 aligned (since the final address produced must be, and
5202 we can only describe word-aligned immediate offsets). */
5204 if ((fixP
->fx_frag
->fr_address
+ fixP
->fx_where
+ value
) & 3)
5205 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5206 "Invalid offset, target not word aligned (0x%08X)",
5207 (unsigned int)(fixP
->fx_frag
->fr_address
+ fixP
->fx_where
+ value
));
5209 if ((value
+ 2) & ~0x3fe)
5210 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5213 /* Round up, since pc will be rounded down. */
5214 newval
|= (value
+ 2) >> 2;
5217 case 9: /* SP load/store */
5219 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5221 newval
|= value
>> 2;
5224 case 6: /* Word load/store */
5226 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5228 newval
|= value
<< 4; /* 6 - 2 */
5231 case 7: /* Byte load/store */
5233 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5235 newval
|= value
<< 6;
5238 case 8: /* Halfword load/store */
5240 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5242 newval
|= value
<< 5; /* 6 - 1 */
5248 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5251 case BFD_RELOC_ARM_THUMB_ADD
:
5252 /* This is a complicated relocation, since we use it for all of
5253 the following immediate relocations:
5256 9bit ADD/SUB SP word-aligned
5257 10bit ADD PC/SP word-aligned
5259 The type of instruction being processed is encoded in the
5265 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
5267 int rd
= (newval
>> 4) & 0xf;
5268 int rs
= newval
& 0xf;
5269 int subtract
= newval
& 0x8000;
5274 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5275 "Invalid immediate for stack address calculation");
5276 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
5277 newval
|= value
>> 2;
5279 else if (rs
== REG_PC
|| rs
== REG_SP
)
5283 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5284 "Invalid immediate for address calculation (value = 0x%08X)", value
);
5285 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
5286 newval
|= value
>> 2;
5291 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5292 "Invalid 8bit immediate");
5293 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
5294 newval
|= (rd
<< 8) | value
;
5299 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5300 "Invalid 3bit immediate");
5301 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
5302 newval
|= rd
| (rs
<< 3) | (value
<< 6);
5305 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5308 case BFD_RELOC_ARM_THUMB_IMM
:
5309 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
5310 switch (newval
>> 11)
5312 case 0x04: /* 8bit immediate MOV */
5313 case 0x05: /* 8bit immediate CMP */
5314 if (value
< 0 || value
> 255)
5315 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5316 "Invalid immediate: %d is too large", value
);
5323 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5326 case BFD_RELOC_ARM_THUMB_SHIFT
:
5327 /* 5bit shift value (0..31) */
5328 if (value
< 0 || value
> 31)
5329 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5330 "Illegal Thumb shift value: %d", value
);
5331 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf03f;
5332 newval
|= value
<< 6;
5333 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5336 case BFD_RELOC_NONE
:
5338 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5339 "Bad relocation fixup type (%d)\n", fixP
->fx_r_type
);
5345 /* Translate internal representation of relocation info to BFD target
5348 tc_gen_reloc (section
, fixp
)
5353 bfd_reloc_code_real_type code
;
5355 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5357 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
5358 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5360 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
5361 if (fixp
->fx_pcrel
== 0)
5362 reloc
->addend
= fixp
->fx_offset
;
5364 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
5366 switch (fixp
->fx_r_type
)
5371 code
= BFD_RELOC_8_PCREL
;
5378 code
= BFD_RELOC_16_PCREL
;
5385 code
= BFD_RELOC_32_PCREL
;
5389 case BFD_RELOC_ARM_PCREL_BRANCH
:
5391 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
5392 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
5393 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
5394 code
= fixp
->fx_r_type
;
5397 case BFD_RELOC_ARM_LITERAL
:
5398 case BFD_RELOC_ARM_HWLITERAL
:
5399 /* If this is called then the a literal has been referenced across
5400 a section boundry - possibly due to an implicit dump */
5401 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5402 "Literal referenced across section boundry (Implicit dump?)");
5405 case BFD_RELOC_ARM_IMMEDIATE
:
5406 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5407 "Internal_relocation (type %d) not fixed up (IMMEDIATE)",
5411 case BFD_RELOC_ARM_OFFSET_IMM
:
5412 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5413 "Internal_relocation (type %d) not fixed up (OFFSET_IMM)",
5417 case BFD_RELOC_ARM_OFFSET_IMM8
:
5418 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5419 "Internal_relocation (type %d) not fixed up (OFFSET_IMM8)",
5423 case BFD_RELOC_ARM_SHIFT_IMM
:
5424 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5425 "Internal_relocation (type %d) not fixed up (SHIFT_IMM)",
5429 case BFD_RELOC_ARM_SWI
:
5430 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5431 "Internal_relocation (type %d) not fixed up (SWI)",
5435 case BFD_RELOC_ARM_MULTI
:
5436 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5437 "Internal_relocation (type %d) not fixed up (MULTI)",
5441 case BFD_RELOC_ARM_CP_OFF_IMM
:
5442 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5443 "Internal_relocation (type %d) not fixed up (CP_OFF_IMM)",
5447 case BFD_RELOC_ARM_THUMB_OFFSET
:
5448 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5449 "Internal_relocation (type %d) not fixed up (THUMB_OFFSET)",
5457 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5458 assert (reloc
->howto
!= 0);
5463 CONST
int md_short_jump_size
= 4;
5464 CONST
int md_long_jump_size
= 4;
5466 /* These should never be called on the arm */
5468 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5470 addressT from_addr
, to_addr
;
5474 as_fatal ("md_create_long_jump\n");
5478 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5480 addressT from_addr
, to_addr
;
5484 as_fatal ("md_create_short_jump\n");
5488 md_estimate_size_before_relax (fragP
, segtype
)
5492 as_fatal ("md_estimate_size_before_relax\n");
5504 as_bad ("%s -- statement `%s'\n", inst
.error
, str
);
5508 to
= frag_more (inst
.size
);
5509 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
5511 assert (inst
.size
== (2 * THUMB_SIZE
));
5512 md_number_to_chars (to
, inst
.instruction
>> 16, THUMB_SIZE
);
5513 md_number_to_chars (to
+ 2, inst
.instruction
, THUMB_SIZE
);
5516 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
5518 if (inst
.reloc
.type
!= BFD_RELOC_NONE
)
5519 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
5520 inst
.size
, &inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
5531 char *p
, *q
, *start
;
5533 /* Align the instruction */
5534 /* this may not be the right thing to do but ... */
5535 /* arm_align (2, 0); */
5536 listing_prev_line (); /* Defined in listing.h */
5538 /* Align the previous label if needed */
5539 if (last_label_seen
!= NULL
)
5541 last_label_seen
->sy_frag
= frag_now
;
5542 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
5543 S_SET_SEGMENT (last_label_seen
, now_seg
);
5546 memset (&inst
, '\0', sizeof (inst
));
5547 inst
.reloc
.type
= BFD_RELOC_NONE
;
5550 str
++; /* Skip leading white space */
5552 /* scan up to the end of the op-code, which must end in white space or
5554 for (start
= p
= str
; *p
!= '\0'; p
++)
5560 as_bad ("No operator -- statement `%s'\n", str
);
5566 CONST
struct thumb_opcode
*opcode
;
5570 opcode
= (CONST
struct thumb_opcode
*) hash_find (arm_tops_hsh
, str
);
5574 inst
.instruction
= opcode
->value
;
5575 inst
.size
= opcode
->size
;
5576 (*opcode
->parms
)(p
);
5577 output_inst (start
);
5583 CONST
struct asm_opcode
*opcode
;
5585 inst
.size
= INSN_SIZE
;
5586 /* p now points to the end of the opcode, probably white space, but we
5587 have to break the opcode up in case it contains condionals and flags;
5588 keep trying with progressively smaller basic instructions until one
5589 matches, or we run out of opcode. */
5590 q
= (p
- str
> LONGEST_INST
) ? str
+ LONGEST_INST
: p
;
5591 for (; q
!= str
; q
--)
5595 opcode
= (CONST
struct asm_opcode
*) hash_find (arm_ops_hsh
, str
);
5597 if (opcode
&& opcode
->template)
5599 unsigned long flag_bits
= 0;
5602 /* Check that this instruction is supported for this CPU */
5603 if ((opcode
->variants
& cpu_variant
) == 0)
5606 inst
.instruction
= opcode
->value
;
5607 if (q
== p
) /* Just a simple opcode */
5609 if (opcode
->comp_suffix
!= 0)
5610 as_bad ("Opcode `%s' must have suffix from <%s>\n", str
,
5611 opcode
->comp_suffix
);
5614 inst
.instruction
|= COND_ALWAYS
;
5615 (*opcode
->parms
)(q
, 0);
5617 output_inst (start
);
5621 /* Now check for a conditional */
5625 CONST
struct asm_cond
*cond
;
5629 cond
= (CONST
struct asm_cond
*) hash_find (arm_cond_hsh
, r
);
5633 if (cond
->value
== 0xf0000000)
5635 "Warning: Use of the 'nv' conditional is deprecated\n");
5637 inst
.instruction
|= cond
->value
;
5641 inst
.instruction
|= COND_ALWAYS
;
5644 inst
.instruction
|= COND_ALWAYS
;
5646 /* if there is a compulsory suffix, it should come here, before
5647 any optional flags. */
5648 if (opcode
->comp_suffix
)
5650 CONST
char *s
= opcode
->comp_suffix
;
5662 as_bad ("Opcode `%s' must have suffix from <%s>\n", str
,
5663 opcode
->comp_suffix
);
5670 /* The remainder, if any should now be flags for the instruction;
5671 Scan these checking each one found with the opcode. */
5675 CONST
struct asm_flg
*flag
= opcode
->flags
;
5684 for (flagno
= 0; flag
[flagno
].template; flagno
++)
5686 if (! strcmp (r
, flag
[flagno
].template))
5688 flag_bits
|= flag
[flagno
].set_bits
;
5694 if (! flag
[flagno
].template)
5701 (*opcode
->parms
) (p
, flag_bits
);
5702 output_inst (start
);
5711 /* It wasn't an instruction, but it might be a register alias of the form
5721 if (*q
&& !strncmp (q
, ".req ", 4))
5724 if ((reg
= arm_reg_parse (&str
)) == FAIL
)
5732 for (r
= q
; *r
!= '\0'; r
++)
5742 regnum
= arm_reg_parse (&q
);
5746 insert_reg_alias (str
, regnum
);
5760 as_bad ("bad instruction `%s'", start
);
5765 * Invocation line includes a switch not recognized by the base assembler.
5766 * See if it's a processor-specific option. These are:
5767 * Cpu variants, the arm part is optional:
5768 * -m[arm]1 Currently not supported.
5769 * -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
5770 * -m[arm]3 Arm 3 processor
5771 * -m[arm]6, Arm 6 processors
5772 * -m[arm]7[t][[d]m] Arm 7 processors
5773 * -mall All (except the ARM1)
5775 * -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
5776 * -mfpe-old (No float load/store multiples)
5777 * -mno-fpu Disable all floating point instructions
5778 * Run-time endian selection:
5779 * -EB big endian cpu
5780 * -EL little endian cpu
5781 * ARM Procedure Calling Standard:
5782 * -mapcs-32 32 bit APCS
5783 * -mapcs-26 26 bit APCS
5786 CONST
char *md_shortopts
= "m:";
5787 struct option md_longopts
[] =
5789 #ifdef ARM_BI_ENDIAN
5790 #define OPTION_EB (OPTION_MD_BASE + 0)
5791 {"EB", no_argument
, NULL
, OPTION_EB
},
5792 #define OPTION_EL (OPTION_MD_BASE + 1)
5793 {"EL", no_argument
, NULL
, OPTION_EL
},
5795 {NULL
, no_argument
, NULL
, 0}
5797 size_t md_longopts_size
= sizeof (md_longopts
);
5800 md_parse_option (c
, arg
)
5808 #ifdef ARM_BI_ENDIAN
5810 target_big_endian
= 1;
5813 target_big_endian
= 0;
5821 if (! strcmp (str
, "fpa10"))
5822 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_FPA10
;
5823 else if (! strcmp (str
, "fpa11"))
5824 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_FPA11
;
5825 else if (! strcmp (str
, "fpe-old"))
5826 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_CORE
;
5832 if (! strcmp (str
, "no-fpu"))
5833 cpu_variant
&= ~FPU_ALL
;
5837 /* Limit assembler to generating only Thumb instructions: */
5838 if (! strcmp (str
, "thumb"))
5840 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_THUMB
;
5841 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_NONE
;
5849 if (! strcmp (str
, "all"))
5851 cpu_variant
= ARM_ALL
| FPU_ALL
;
5855 if (! strcmp (str
, "apcs-32"))
5857 uses_apcs_26
= false;
5860 else if (! strcmp (str
, "apcs-26"))
5862 uses_apcs_26
= true;
5866 /* Strip off optional "arm" */
5867 if (! strncmp (str
, "arm", 3))
5873 if (! strcmp (str
, "1"))
5874 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_1
;
5880 if (! strcmp (str
, "2"))
5881 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_2
;
5882 else if (! strcmp (str
, "250"))
5883 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_250
;
5889 if (! strcmp (str
, "3"))
5890 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_3
;
5896 if (! strcmp (str
, "6"))
5897 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_6
;
5903 str
++; /* eat the '7' */
5904 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_7
;
5910 cpu_variant
|= ARM_THUMB
;
5914 cpu_variant
|= ARM_LONGMUL
;
5917 case 'd': /* debug */
5918 case 'i': /* embedded ice */
5919 /* Included for completeness in ARM processor
5930 /* Select variant based on architecture rather than processor */
5936 case 'a': cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_3
; break;
5937 case 0: cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_2
; break;
5938 default: as_bad ("Invalid architecture variant -m%s", arg
); break;
5943 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_7
;
5947 case 'm': cpu_variant
|= ARM_LONGMUL
; break;
5949 default: as_bad ("Invalid architecture variant -m%s", arg
); break;
5954 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_7
;
5958 case 't': cpu_variant
|= ARM_THUMB
; break;
5960 default: as_bad ("Invalid architecture variant -m%s", arg
); break;
5965 as_bad ("Invalid architecture variant -m%s", arg
);
5972 as_bad ("Invalid processor variant -m%s", arg
);
5990 "-m[arm][1|2|250|3|6|7[t][d][m][i]] select processor variant\n\
5991 -m[arm]v[2|2a|3|3m|4|4t] select architecture variant\n\
5992 -mthumb\t\t\tonly allow Thumb instructions\n\
5993 -mall\t\t\tallow any instruction\n\
5994 -mfpa10, -mfpa11\tselect floating point architecture\n\
5995 -mfpe-old\t\tdon't allow floating-point multiple instructions\n\
5996 -mno-fpu\t\tdon't allow any floating-point instructions.\n");
5999 "-mapcs-32, -mapcs-26\tspecify which ARM Procedure Calling Standard is in use\n");
6001 #ifdef ARM_BI_ENDIAN
6003 "-EB\t\t\tassemble code for a big endian cpu\n\
6004 -EL\t\t\tassemble code for a little endian cpu\n");
6008 /* We need to be able to fix up arbitrary expressions in some statements.
6009 This is so that we can handle symbols that are an arbitrary distance from
6010 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
6011 which returns part of an address in a form which will be valid for
6012 a data instruction. We do this by pushing the expression into a symbol
6013 in the expr_section, and creating a fix for that. */
6016 fix_new_arm (frag
, where
, size
, exp
, pc_rel
, reloc
)
6025 arm_fix_data
*arm_data
;
6033 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
6037 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
6042 /* Mark whether the fix is to a THUMB instruction, or an ARM instruction */
6043 arm_data
= (arm_fix_data
*) obstack_alloc (¬es
, sizeof (arm_fix_data
));
6044 new_fix
->tc_fix_data
= (PTR
) arm_data
;
6045 arm_data
->thumb_mode
= thumb_mode
;
6050 /* A good place to do this, although this was probably not intended
6051 * for this kind of use. We need to dump the literal pool before
6052 * references are made to a null symbol pointer. */
6054 arm_after_pass_hook ()
6056 if (current_poolP
!= NULL
)
6058 subseg_set (text_section
, 0); /* Put it at the end of text section */
6060 listing_prev_line ();
6065 arm_start_line_hook ()
6067 last_label_seen
= NULL
;
6071 arm_frob_label (sym
)
6074 last_label_seen
= sym
;
6075 ARM_SET_TYPE(sym
,thumb_mode
);
6078 /* Adjust the symbol table. This marks Thumb symbols as distinct from
6082 arm_adjust_symtab ()
6086 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
6088 if (ARM_GET_TYPE(sym
)) /* Thumb */
6090 switch (S_GET_STORAGE_CLASS (sym
))
6093 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
6096 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
6099 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
6101 default: /* do nothing */
6113 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
6115 *input_line_pointer
= '/';
6116 input_line_pointer
+= 5;
6117 *input_line_pointer
= 0;
6124 arm_canonicalize_symbol_name (name
)
6129 if (thumb_mode
&& (len
= strlen (name
)) > 5
6130 && ! strcmp (name
+ len
- 5, "/data"))
6132 *(name
+ len
- 5) = 0;