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Use MVN to build simple inverted constants.
[deliverable/binutils-gdb.git] / gas / config / tc-arm.c
1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
5 Modified by David Taylor (dtaylor@armltd.co.uk)
6
7 This file is part of GAS, the GNU Assembler.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 02111-1307, USA. */
23
24 #include <ctype.h>
25 #include <string.h>
26 #define NO_RELOC 0
27 #include "as.h"
28
29 /* Need TARGET_CPU. */
30 #include "config.h"
31 #include "subsegs.h"
32 #include "obstack.h"
33 #include "symbols.h"
34 #include "listing.h"
35
36 #ifdef OBJ_ELF
37 #include "elf/arm.h"
38 #include "dwarf2dbg.h"
39 #endif
40
41 /* Types of processor to assemble for. */
42 #define ARM_1 0x00000001
43 #define ARM_2 0x00000002
44 #define ARM_3 0x00000004
45 #define ARM_250 ARM_3
46 #define ARM_6 0x00000008
47 #define ARM_7 ARM_6 /* Same core instruction set. */
48 #define ARM_8 ARM_6 /* Same core instruction set. */
49 #define ARM_9 ARM_6 /* Same core instruction set. */
50 #define ARM_CPU_MASK 0x0000000f
51
52 /* The following bitmasks control CPU extensions (ARM7 onwards): */
53 #define ARM_EXT_LONGMUL 0x00000010 /* Allow long multiplies. */
54 #define ARM_EXT_HALFWORD 0x00000020 /* Allow half word loads. */
55 #define ARM_EXT_THUMB 0x00000040 /* Allow BX instruction. */
56 #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
57 #define ARM_EXT_V5E 0x00000100 /* "El Segundo". */
58 #define ARM_EXT_XSCALE 0x00000200 /* Allow MIA etc. */
59
60 /* Architectures are the sum of the base and extensions. */
61 #define ARM_ARCH_V3M ARM_EXT_LONGMUL
62 #define ARM_ARCH_V4 (ARM_ARCH_V3M | ARM_EXT_HALFWORD)
63 #define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_EXT_THUMB)
64 #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
65 #define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_EXT_THUMB)
66 #define ARM_ARCH_V5TE (ARM_ARCH_V5T | ARM_EXT_V5E)
67 #define ARM_ARCH_XSCALE (ARM_ARCH_V5TE | ARM_EXT_XSCALE)
68
69 /* Some useful combinations: */
70 #define ARM_ANY 0x00ffffff
71 #define ARM_2UP (ARM_ANY - ARM_1)
72 #define ARM_ALL ARM_2UP /* Not arm1 only. */
73 #define ARM_3UP 0x00fffffc
74 #define ARM_6UP 0x00fffff8 /* Includes ARM7. */
75
76 #define FPU_CORE 0x80000000
77 #define FPU_FPA10 0x40000000
78 #define FPU_FPA11 0x40000000
79 #define FPU_NONE 0
80
81 /* Some useful combinations. */
82 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY. */
83 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core. */
84
85 #ifndef CPU_DEFAULT
86 #if defined __XSCALE__
87 #define CPU_DEFAULT (ARM_9 | ARM_ARCH_XSCALE)
88 #else
89 #if defined __thumb__
90 #define CPU_DEFAULT (ARM_7 | ARM_ARCH_V4T)
91 #else
92 #define CPU_DEFAULT ARM_ALL
93 #endif
94 #endif
95 #endif
96
97 #ifndef FPU_DEFAULT
98 #define FPU_DEFAULT FPU_ALL
99 #endif
100
101 #define streq(a, b) (strcmp (a, b) == 0)
102 #define skip_whitespace(str) while (*(str) == ' ') ++(str)
103
104 static unsigned long cpu_variant = CPU_DEFAULT | FPU_DEFAULT;
105 static int target_oabi = 0;
106
107 #if defined OBJ_COFF || defined OBJ_ELF
108 /* Flags stored in private area of BFD structure. */
109 static boolean uses_apcs_26 = false;
110 static boolean atpcs = false;
111 static boolean support_interwork = false;
112 static boolean uses_apcs_float = false;
113 static boolean pic_code = false;
114 #endif
115
116 /* This array holds the chars that always start a comment. If the
117 pre-processor is disabled, these aren't very useful. */
118 CONST char comment_chars[] = "@";
119
120 /* This array holds the chars that only start a comment at the beginning of
121 a line. If the line seems to have the form '# 123 filename'
122 .line and .file directives will appear in the pre-processed output. */
123 /* Note that input_file.c hand checks for '#' at the beginning of the
124 first line of the input file. This is because the compiler outputs
125 #NO_APP at the beginning of its output. */
126 /* Also note that comments like this one will always work. */
127 CONST char line_comment_chars[] = "#";
128
129 CONST char line_separator_chars[] = ";";
130
131 /* Chars that can be used to separate mant
132 from exp in floating point numbers. */
133 CONST char EXP_CHARS[] = "eE";
134
135 /* Chars that mean this number is a floating point constant. */
136 /* As in 0f12.456 */
137 /* or 0d1.2345e12 */
138
139 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
140
141 /* Prefix characters that indicate the start of an immediate
142 value. */
143 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
144
145 #ifdef OBJ_ELF
146 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
147 symbolS * GOT_symbol;
148 #endif
149
150 /* Size of relocation record. */
151 CONST int md_reloc_size = 8;
152
153 /* 0: assemble for ARM,
154 1: assemble for Thumb,
155 2: assemble for Thumb even though target CPU does not support thumb
156 instructions. */
157 static int thumb_mode = 0;
158
159 typedef struct arm_fix
160 {
161 int thumb_mode;
162 } arm_fix_data;
163
164 struct arm_it
165 {
166 CONST char * error;
167 unsigned long instruction;
168 int suffix;
169 int size;
170 struct
171 {
172 bfd_reloc_code_real_type type;
173 expressionS exp;
174 int pc_rel;
175 } reloc;
176 };
177
178 struct arm_it inst;
179
180 enum asm_shift_index
181 {
182 SHIFT_LSL = 0,
183 SHIFT_LSR,
184 SHIFT_ASR,
185 SHIFT_ROR,
186 SHIFT_RRX
187 };
188
189 struct asm_shift_properties
190 {
191 enum asm_shift_index index;
192 unsigned long bit_field;
193 unsigned int allows_0 : 1;
194 unsigned int allows_32 : 1;
195 };
196
197 static const struct asm_shift_properties shift_properties [] =
198 {
199 { SHIFT_LSL, 0, 1, 0},
200 { SHIFT_LSR, 0x20, 0, 1},
201 { SHIFT_ASR, 0x40, 0, 1},
202 { SHIFT_ROR, 0x60, 0, 0},
203 { SHIFT_RRX, 0x60, 0, 0}
204 };
205
206 struct asm_shift_name
207 {
208 const char * name;
209 const struct asm_shift_properties * properties;
210 };
211
212 static const struct asm_shift_name shift_names [] =
213 {
214 { "asl", shift_properties + SHIFT_LSL },
215 { "lsl", shift_properties + SHIFT_LSL },
216 { "lsr", shift_properties + SHIFT_LSR },
217 { "asr", shift_properties + SHIFT_ASR },
218 { "ror", shift_properties + SHIFT_ROR },
219 { "rrx", shift_properties + SHIFT_RRX },
220 { "ASL", shift_properties + SHIFT_LSL },
221 { "LSL", shift_properties + SHIFT_LSL },
222 { "LSR", shift_properties + SHIFT_LSR },
223 { "ASR", shift_properties + SHIFT_ASR },
224 { "ROR", shift_properties + SHIFT_ROR },
225 { "RRX", shift_properties + SHIFT_RRX }
226 };
227
228 #define NO_SHIFT_RESTRICT 1
229 #define SHIFT_RESTRICT 0
230
231 #define NUM_FLOAT_VALS 8
232
233 CONST char * fp_const[] =
234 {
235 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
236 };
237
238 /* Number of littlenums required to hold an extended precision number. */
239 #define MAX_LITTLENUMS 6
240
241 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
242
243 #define FAIL (-1)
244 #define SUCCESS (0)
245
246 #define SUFF_S 1
247 #define SUFF_D 2
248 #define SUFF_E 3
249 #define SUFF_P 4
250
251 #define CP_T_X 0x00008000
252 #define CP_T_Y 0x00400000
253 #define CP_T_Pre 0x01000000
254 #define CP_T_UD 0x00800000
255 #define CP_T_WB 0x00200000
256
257 #define CONDS_BIT 0x00100000
258 #define LOAD_BIT 0x00100000
259 #define TRANS_BIT 0x00200000
260
261 #define DOUBLE_LOAD_FLAG 0x00000001
262
263 struct asm_cond
264 {
265 CONST char * template;
266 unsigned long value;
267 };
268
269 /* This is to save a hash look-up in the common case. */
270 #define COND_ALWAYS 0xe0000000
271
272 static CONST struct asm_cond conds[] =
273 {
274 {"eq", 0x00000000},
275 {"ne", 0x10000000},
276 {"cs", 0x20000000}, {"hs", 0x20000000},
277 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
278 {"mi", 0x40000000},
279 {"pl", 0x50000000},
280 {"vs", 0x60000000},
281 {"vc", 0x70000000},
282 {"hi", 0x80000000},
283 {"ls", 0x90000000},
284 {"ge", 0xa0000000},
285 {"lt", 0xb0000000},
286 {"gt", 0xc0000000},
287 {"le", 0xd0000000},
288 {"al", 0xe0000000},
289 {"nv", 0xf0000000}
290 };
291
292 /* Warning: If the top bit of the set_bits is set, then the standard
293 instruction bitmask is ignored, and the new bitmask is taken from
294 the set_bits: */
295 struct asm_flg
296 {
297 CONST char * template; /* Basic flag string. */
298 unsigned long set_bits; /* Bits to set. */
299 };
300
301 static CONST struct asm_flg s_flag[] =
302 {
303 {"s", CONDS_BIT},
304 {NULL, 0}
305 };
306
307 static CONST struct asm_flg ldr_flags[] =
308 {
309 {"d", DOUBLE_LOAD_FLAG},
310 {"b", 0x00400000},
311 {"t", TRANS_BIT},
312 {"bt", 0x00400000 | TRANS_BIT},
313 {"h", 0x801000b0},
314 {"sh", 0x801000f0},
315 {"sb", 0x801000d0},
316 {NULL, 0}
317 };
318
319 static CONST struct asm_flg str_flags[] =
320 {
321 {"d", DOUBLE_LOAD_FLAG},
322 {"b", 0x00400000},
323 {"t", TRANS_BIT},
324 {"bt", 0x00400000 | TRANS_BIT},
325 {"h", 0x800000b0},
326 {NULL, 0}
327 };
328
329 static CONST struct asm_flg byte_flag[] =
330 {
331 {"b", 0x00400000},
332 {NULL, 0}
333 };
334
335 static CONST struct asm_flg cmp_flags[] =
336 {
337 {"s", CONDS_BIT},
338 {"p", 0x0010f000},
339 {NULL, 0}
340 };
341
342 static CONST struct asm_flg ldm_flags[] =
343 {
344 {"ed", 0x01800000},
345 {"fd", 0x00800000},
346 {"ea", 0x01000000},
347 {"fa", 0x00000000},
348 {"ib", 0x01800000},
349 {"ia", 0x00800000},
350 {"db", 0x01000000},
351 {"da", 0x00000000},
352 {NULL, 0}
353 };
354
355 static CONST struct asm_flg stm_flags[] =
356 {
357 {"ed", 0x00000000},
358 {"fd", 0x01000000},
359 {"ea", 0x00800000},
360 {"fa", 0x01800000},
361 {"ib", 0x01800000},
362 {"ia", 0x00800000},
363 {"db", 0x01000000},
364 {"da", 0x00000000},
365 {NULL, 0}
366 };
367
368 static CONST struct asm_flg lfm_flags[] =
369 {
370 {"fd", 0x00800000},
371 {"ea", 0x01000000},
372 {NULL, 0}
373 };
374
375 static CONST struct asm_flg sfm_flags[] =
376 {
377 {"fd", 0x01000000},
378 {"ea", 0x00800000},
379 {NULL, 0}
380 };
381
382 static CONST struct asm_flg round_flags[] =
383 {
384 {"p", 0x00000020},
385 {"m", 0x00000040},
386 {"z", 0x00000060},
387 {NULL, 0}
388 };
389
390 /* The implementation of the FIX instruction is broken on some assemblers,
391 in that it accepts a precision specifier as well as a rounding specifier,
392 despite the fact that this is meaningless. To be more compatible, we
393 accept it as well, though of course it does not set any bits. */
394 static CONST struct asm_flg fix_flags[] =
395 {
396 {"p", 0x00000020},
397 {"m", 0x00000040},
398 {"z", 0x00000060},
399 {"sp", 0x00000020},
400 {"sm", 0x00000040},
401 {"sz", 0x00000060},
402 {"dp", 0x00000020},
403 {"dm", 0x00000040},
404 {"dz", 0x00000060},
405 {"ep", 0x00000020},
406 {"em", 0x00000040},
407 {"ez", 0x00000060},
408 {NULL, 0}
409 };
410
411 static CONST struct asm_flg except_flag[] =
412 {
413 {"e", 0x00400000},
414 {NULL, 0}
415 };
416
417 static CONST struct asm_flg long_flag[] =
418 {
419 {"l", 0x00400000},
420 {NULL, 0}
421 };
422
423 struct asm_psr
424 {
425 CONST char * template;
426 boolean cpsr;
427 unsigned long field;
428 };
429
430 /* The bit that distnguishes CPSR and SPSR. */
431 #define SPSR_BIT (1 << 22)
432
433 /* How many bits to shift the PSR_xxx bits up by. */
434 #define PSR_SHIFT 16
435
436 #define PSR_c (1 << 0)
437 #define PSR_x (1 << 1)
438 #define PSR_s (1 << 2)
439 #define PSR_f (1 << 3)
440
441 static CONST struct asm_psr psrs[] =
442 {
443 {"CPSR", true, PSR_c | PSR_f},
444 {"CPSR_all", true, PSR_c | PSR_f},
445 {"SPSR", false, PSR_c | PSR_f},
446 {"SPSR_all", false, PSR_c | PSR_f},
447 {"CPSR_flg", true, PSR_f},
448 {"CPSR_f", true, PSR_f},
449 {"SPSR_flg", false, PSR_f},
450 {"SPSR_f", false, PSR_f},
451 {"CPSR_c", true, PSR_c},
452 {"CPSR_ctl", true, PSR_c},
453 {"SPSR_c", false, PSR_c},
454 {"SPSR_ctl", false, PSR_c},
455 {"CPSR_x", true, PSR_x},
456 {"CPSR_s", true, PSR_s},
457 {"SPSR_x", false, PSR_x},
458 {"SPSR_s", false, PSR_s},
459 /* Combinations of flags. */
460 {"CPSR_fs", true, PSR_f | PSR_s},
461 {"CPSR_fx", true, PSR_f | PSR_x},
462 {"CPSR_fc", true, PSR_f | PSR_c},
463 {"CPSR_sf", true, PSR_s | PSR_f},
464 {"CPSR_sx", true, PSR_s | PSR_x},
465 {"CPSR_sc", true, PSR_s | PSR_c},
466 {"CPSR_xf", true, PSR_x | PSR_f},
467 {"CPSR_xs", true, PSR_x | PSR_s},
468 {"CPSR_xc", true, PSR_x | PSR_c},
469 {"CPSR_cf", true, PSR_c | PSR_f},
470 {"CPSR_cs", true, PSR_c | PSR_s},
471 {"CPSR_cx", true, PSR_c | PSR_x},
472 {"CPSR_fsx", true, PSR_f | PSR_s | PSR_x},
473 {"CPSR_fsc", true, PSR_f | PSR_s | PSR_c},
474 {"CPSR_fxs", true, PSR_f | PSR_x | PSR_s},
475 {"CPSR_fxc", true, PSR_f | PSR_x | PSR_c},
476 {"CPSR_fcs", true, PSR_f | PSR_c | PSR_s},
477 {"CPSR_fcx", true, PSR_f | PSR_c | PSR_x},
478 {"CPSR_sfx", true, PSR_s | PSR_f | PSR_x},
479 {"CPSR_sfc", true, PSR_s | PSR_f | PSR_c},
480 {"CPSR_sxf", true, PSR_s | PSR_x | PSR_f},
481 {"CPSR_sxc", true, PSR_s | PSR_x | PSR_c},
482 {"CPSR_scf", true, PSR_s | PSR_c | PSR_f},
483 {"CPSR_scx", true, PSR_s | PSR_c | PSR_x},
484 {"CPSR_xfs", true, PSR_x | PSR_f | PSR_s},
485 {"CPSR_xfc", true, PSR_x | PSR_f | PSR_c},
486 {"CPSR_xsf", true, PSR_x | PSR_s | PSR_f},
487 {"CPSR_xsc", true, PSR_x | PSR_s | PSR_c},
488 {"CPSR_xcf", true, PSR_x | PSR_c | PSR_f},
489 {"CPSR_xcs", true, PSR_x | PSR_c | PSR_s},
490 {"CPSR_cfs", true, PSR_c | PSR_f | PSR_s},
491 {"CPSR_cfx", true, PSR_c | PSR_f | PSR_x},
492 {"CPSR_csf", true, PSR_c | PSR_s | PSR_f},
493 {"CPSR_csx", true, PSR_c | PSR_s | PSR_x},
494 {"CPSR_cxf", true, PSR_c | PSR_x | PSR_f},
495 {"CPSR_cxs", true, PSR_c | PSR_x | PSR_s},
496 {"CPSR_fsxc", true, PSR_f | PSR_s | PSR_x | PSR_c},
497 {"CPSR_fscx", true, PSR_f | PSR_s | PSR_c | PSR_x},
498 {"CPSR_fxsc", true, PSR_f | PSR_x | PSR_s | PSR_c},
499 {"CPSR_fxcs", true, PSR_f | PSR_x | PSR_c | PSR_s},
500 {"CPSR_fcsx", true, PSR_f | PSR_c | PSR_s | PSR_x},
501 {"CPSR_fcxs", true, PSR_f | PSR_c | PSR_x | PSR_s},
502 {"CPSR_sfxc", true, PSR_s | PSR_f | PSR_x | PSR_c},
503 {"CPSR_sfcx", true, PSR_s | PSR_f | PSR_c | PSR_x},
504 {"CPSR_sxfc", true, PSR_s | PSR_x | PSR_f | PSR_c},
505 {"CPSR_sxcf", true, PSR_s | PSR_x | PSR_c | PSR_f},
506 {"CPSR_scfx", true, PSR_s | PSR_c | PSR_f | PSR_x},
507 {"CPSR_scxf", true, PSR_s | PSR_c | PSR_x | PSR_f},
508 {"CPSR_xfsc", true, PSR_x | PSR_f | PSR_s | PSR_c},
509 {"CPSR_xfcs", true, PSR_x | PSR_f | PSR_c | PSR_s},
510 {"CPSR_xsfc", true, PSR_x | PSR_s | PSR_f | PSR_c},
511 {"CPSR_xscf", true, PSR_x | PSR_s | PSR_c | PSR_f},
512 {"CPSR_xcfs", true, PSR_x | PSR_c | PSR_f | PSR_s},
513 {"CPSR_xcsf", true, PSR_x | PSR_c | PSR_s | PSR_f},
514 {"CPSR_cfsx", true, PSR_c | PSR_f | PSR_s | PSR_x},
515 {"CPSR_cfxs", true, PSR_c | PSR_f | PSR_x | PSR_s},
516 {"CPSR_csfx", true, PSR_c | PSR_s | PSR_f | PSR_x},
517 {"CPSR_csxf", true, PSR_c | PSR_s | PSR_x | PSR_f},
518 {"CPSR_cxfs", true, PSR_c | PSR_x | PSR_f | PSR_s},
519 {"CPSR_cxsf", true, PSR_c | PSR_x | PSR_s | PSR_f},
520 {"SPSR_fs", false, PSR_f | PSR_s},
521 {"SPSR_fx", false, PSR_f | PSR_x},
522 {"SPSR_fc", false, PSR_f | PSR_c},
523 {"SPSR_sf", false, PSR_s | PSR_f},
524 {"SPSR_sx", false, PSR_s | PSR_x},
525 {"SPSR_sc", false, PSR_s | PSR_c},
526 {"SPSR_xf", false, PSR_x | PSR_f},
527 {"SPSR_xs", false, PSR_x | PSR_s},
528 {"SPSR_xc", false, PSR_x | PSR_c},
529 {"SPSR_cf", false, PSR_c | PSR_f},
530 {"SPSR_cs", false, PSR_c | PSR_s},
531 {"SPSR_cx", false, PSR_c | PSR_x},
532 {"SPSR_fsx", false, PSR_f | PSR_s | PSR_x},
533 {"SPSR_fsc", false, PSR_f | PSR_s | PSR_c},
534 {"SPSR_fxs", false, PSR_f | PSR_x | PSR_s},
535 {"SPSR_fxc", false, PSR_f | PSR_x | PSR_c},
536 {"SPSR_fcs", false, PSR_f | PSR_c | PSR_s},
537 {"SPSR_fcx", false, PSR_f | PSR_c | PSR_x},
538 {"SPSR_sfx", false, PSR_s | PSR_f | PSR_x},
539 {"SPSR_sfc", false, PSR_s | PSR_f | PSR_c},
540 {"SPSR_sxf", false, PSR_s | PSR_x | PSR_f},
541 {"SPSR_sxc", false, PSR_s | PSR_x | PSR_c},
542 {"SPSR_scf", false, PSR_s | PSR_c | PSR_f},
543 {"SPSR_scx", false, PSR_s | PSR_c | PSR_x},
544 {"SPSR_xfs", false, PSR_x | PSR_f | PSR_s},
545 {"SPSR_xfc", false, PSR_x | PSR_f | PSR_c},
546 {"SPSR_xsf", false, PSR_x | PSR_s | PSR_f},
547 {"SPSR_xsc", false, PSR_x | PSR_s | PSR_c},
548 {"SPSR_xcf", false, PSR_x | PSR_c | PSR_f},
549 {"SPSR_xcs", false, PSR_x | PSR_c | PSR_s},
550 {"SPSR_cfs", false, PSR_c | PSR_f | PSR_s},
551 {"SPSR_cfx", false, PSR_c | PSR_f | PSR_x},
552 {"SPSR_csf", false, PSR_c | PSR_s | PSR_f},
553 {"SPSR_csx", false, PSR_c | PSR_s | PSR_x},
554 {"SPSR_cxf", false, PSR_c | PSR_x | PSR_f},
555 {"SPSR_cxs", false, PSR_c | PSR_x | PSR_s},
556 {"SPSR_fsxc", false, PSR_f | PSR_s | PSR_x | PSR_c},
557 {"SPSR_fscx", false, PSR_f | PSR_s | PSR_c | PSR_x},
558 {"SPSR_fxsc", false, PSR_f | PSR_x | PSR_s | PSR_c},
559 {"SPSR_fxcs", false, PSR_f | PSR_x | PSR_c | PSR_s},
560 {"SPSR_fcsx", false, PSR_f | PSR_c | PSR_s | PSR_x},
561 {"SPSR_fcxs", false, PSR_f | PSR_c | PSR_x | PSR_s},
562 {"SPSR_sfxc", false, PSR_s | PSR_f | PSR_x | PSR_c},
563 {"SPSR_sfcx", false, PSR_s | PSR_f | PSR_c | PSR_x},
564 {"SPSR_sxfc", false, PSR_s | PSR_x | PSR_f | PSR_c},
565 {"SPSR_sxcf", false, PSR_s | PSR_x | PSR_c | PSR_f},
566 {"SPSR_scfx", false, PSR_s | PSR_c | PSR_f | PSR_x},
567 {"SPSR_scxf", false, PSR_s | PSR_c | PSR_x | PSR_f},
568 {"SPSR_xfsc", false, PSR_x | PSR_f | PSR_s | PSR_c},
569 {"SPSR_xfcs", false, PSR_x | PSR_f | PSR_c | PSR_s},
570 {"SPSR_xsfc", false, PSR_x | PSR_s | PSR_f | PSR_c},
571 {"SPSR_xscf", false, PSR_x | PSR_s | PSR_c | PSR_f},
572 {"SPSR_xcfs", false, PSR_x | PSR_c | PSR_f | PSR_s},
573 {"SPSR_xcsf", false, PSR_x | PSR_c | PSR_s | PSR_f},
574 {"SPSR_cfsx", false, PSR_c | PSR_f | PSR_s | PSR_x},
575 {"SPSR_cfxs", false, PSR_c | PSR_f | PSR_x | PSR_s},
576 {"SPSR_csfx", false, PSR_c | PSR_s | PSR_f | PSR_x},
577 {"SPSR_csxf", false, PSR_c | PSR_s | PSR_x | PSR_f},
578 {"SPSR_cxfs", false, PSR_c | PSR_x | PSR_f | PSR_s},
579 {"SPSR_cxsf", false, PSR_c | PSR_x | PSR_s | PSR_f},
580 };
581
582 /* Functions called by parser. */
583 /* ARM instructions. */
584 static void do_arit PARAMS ((char *, unsigned long));
585 static void do_cmp PARAMS ((char *, unsigned long));
586 static void do_mov PARAMS ((char *, unsigned long));
587 static void do_ldst PARAMS ((char *, unsigned long));
588 static void do_ldmstm PARAMS ((char *, unsigned long));
589 static void do_branch PARAMS ((char *, unsigned long));
590 static void do_swi PARAMS ((char *, unsigned long));
591 /* Pseudo Op codes. */
592 static void do_adr PARAMS ((char *, unsigned long));
593 static void do_adrl PARAMS ((char *, unsigned long));
594 static void do_nop PARAMS ((char *, unsigned long));
595 /* ARM 2. */
596 static void do_mul PARAMS ((char *, unsigned long));
597 static void do_mla PARAMS ((char *, unsigned long));
598 /* ARM 3. */
599 static void do_swap PARAMS ((char *, unsigned long));
600 /* ARM 6. */
601 static void do_msr PARAMS ((char *, unsigned long));
602 static void do_mrs PARAMS ((char *, unsigned long));
603 /* ARM 7M. */
604 static void do_mull PARAMS ((char *, unsigned long));
605 /* ARM THUMB. */
606 static void do_bx PARAMS ((char *, unsigned long));
607
608 /* ARM_EXT_XScale. */
609 static void do_mia PARAMS ((char *, unsigned long));
610 static void do_mar PARAMS ((char *, unsigned long));
611 static void do_mra PARAMS ((char *, unsigned long));
612 static void do_pld PARAMS ((char *, unsigned long));
613 static void do_ldrd PARAMS ((char *, unsigned long));
614
615 /* ARM_EXT_V5. */
616 static void do_blx PARAMS ((char *, unsigned long));
617 static void do_bkpt PARAMS ((char *, unsigned long));
618 static void do_clz PARAMS ((char *, unsigned long));
619 static void do_lstc2 PARAMS ((char *, unsigned long));
620 static void do_cdp2 PARAMS ((char *, unsigned long));
621 static void do_co_reg2 PARAMS ((char *, unsigned long));
622
623 static void do_t_blx PARAMS ((char *));
624 static void do_t_bkpt PARAMS ((char *));
625
626 /* ARM_EXT_V5E. */
627 static void do_smla PARAMS ((char *, unsigned long));
628 static void do_smlal PARAMS ((char *, unsigned long));
629 static void do_smul PARAMS ((char *, unsigned long));
630 static void do_qadd PARAMS ((char *, unsigned long));
631 static void do_co_reg2c PARAMS ((char *, unsigned long));
632
633 /* Coprocessor Instructions. */
634 static void do_cdp PARAMS ((char *, unsigned long));
635 static void do_lstc PARAMS ((char *, unsigned long));
636 static void do_co_reg PARAMS ((char *, unsigned long));
637 static void do_fp_ctrl PARAMS ((char *, unsigned long));
638 static void do_fp_ldst PARAMS ((char *, unsigned long));
639 static void do_fp_ldmstm PARAMS ((char *, unsigned long));
640 static void do_fp_dyadic PARAMS ((char *, unsigned long));
641 static void do_fp_monadic PARAMS ((char *, unsigned long));
642 static void do_fp_cmp PARAMS ((char *, unsigned long));
643 static void do_fp_from_reg PARAMS ((char *, unsigned long));
644 static void do_fp_to_reg PARAMS ((char *, unsigned long));
645
646 static void fix_new_arm PARAMS ((fragS *, int, short, expressionS *, int, int));
647 static int arm_reg_parse PARAMS ((char **));
648 static CONST struct asm_psr * arm_psr_parse PARAMS ((char **));
649 static void symbol_locate PARAMS ((symbolS *, CONST char *, segT, valueT, fragS *));
650 static int add_to_lit_pool PARAMS ((void));
651 static unsigned validate_immediate PARAMS ((unsigned));
652 static unsigned validate_immediate_twopart PARAMS ((unsigned int, unsigned int *));
653 static int validate_offset_imm PARAMS ((unsigned int, int));
654 static void opcode_select PARAMS ((int));
655 static void end_of_line PARAMS ((char *));
656 static int reg_required_here PARAMS ((char **, int));
657 static int psr_required_here PARAMS ((char **));
658 static int co_proc_number PARAMS ((char **));
659 static int cp_opc_expr PARAMS ((char **, int, int));
660 static int cp_reg_required_here PARAMS ((char **, int));
661 static int fp_reg_required_here PARAMS ((char **, int));
662 static int cp_address_offset PARAMS ((char **));
663 static int cp_address_required_here PARAMS ((char **));
664 static int my_get_float_expression PARAMS ((char **));
665 static int skip_past_comma PARAMS ((char **));
666 static int walk_no_bignums PARAMS ((symbolS *));
667 static int negate_data_op PARAMS ((unsigned long *, unsigned long));
668 static int data_op2 PARAMS ((char **));
669 static int fp_op2 PARAMS ((char **));
670 static long reg_list PARAMS ((char **));
671 static void thumb_load_store PARAMS ((char *, int, int));
672 static int decode_shift PARAMS ((char **, int));
673 static int ldst_extend PARAMS ((char **, int));
674 static void thumb_add_sub PARAMS ((char *, int));
675 static void insert_reg PARAMS ((int));
676 static void thumb_shift PARAMS ((char *, int));
677 static void thumb_mov_compare PARAMS ((char *, int));
678 static void set_constant_flonums PARAMS ((void));
679 static valueT md_chars_to_number PARAMS ((char *, int));
680 static void insert_reg_alias PARAMS ((char *, int));
681 static void output_inst PARAMS ((void));
682 #ifdef OBJ_ELF
683 static bfd_reloc_code_real_type arm_parse_reloc PARAMS ((void));
684 #endif
685
686 /* ARM instructions take 4bytes in the object file, Thumb instructions
687 take 2: */
688 #define INSN_SIZE 4
689
690 /* LONGEST_INST is the longest basic instruction name without
691 conditions or flags. ARM7M has 4 of length 5. El Segundo
692 has one basic instruction name of length 7 (SMLALxy). */
693 #define LONGEST_INST 7
694
695 struct asm_opcode
696 {
697 /* Basic string to match. */
698 CONST char * template;
699
700 /* Basic instruction code. */
701 unsigned long value;
702
703 /* Compulsory suffix that must follow conds. If "", then the
704 instruction is not conditional and must have no suffix. */
705 CONST char * comp_suffix;
706
707 /* Bits to toggle if flag 'n' set. */
708 CONST struct asm_flg * flags;
709
710 /* Which CPU variants this exists for. */
711 unsigned long variants;
712
713 /* Function to call to parse args. */
714 void (* parms) PARAMS ((char *, unsigned long));
715 };
716
717 static CONST struct asm_opcode insns[] =
718 {
719 /* Intel XScale extensions to ARM V5 ISA. */
720 {"mia", 0x0e200010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
721 {"miaph", 0x0e280010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
722 {"miabb", 0x0e2c0010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
723 {"miabt", 0x0e2d0010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
724 {"miatb", 0x0e2e0010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
725 {"miatt", 0x0e2f0010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
726 {"mar", 0x0c400000, NULL, NULL, ARM_EXT_XSCALE, do_mar},
727 {"mra", 0x0c500000, NULL, NULL, ARM_EXT_XSCALE, do_mra},
728 {"pld", 0xf450f000, "", NULL, ARM_EXT_XSCALE, do_pld},
729 {"ldr", 0x000000d0, NULL, ldr_flags, ARM_ANY, do_ldrd},
730 {"str", 0x000000f0, NULL, str_flags, ARM_ANY, do_ldrd},
731
732 /* ARM Instructions. */
733 {"and", 0x00000000, NULL, s_flag, ARM_ANY, do_arit},
734 {"eor", 0x00200000, NULL, s_flag, ARM_ANY, do_arit},
735 {"sub", 0x00400000, NULL, s_flag, ARM_ANY, do_arit},
736 {"rsb", 0x00600000, NULL, s_flag, ARM_ANY, do_arit},
737 {"add", 0x00800000, NULL, s_flag, ARM_ANY, do_arit},
738 {"adc", 0x00a00000, NULL, s_flag, ARM_ANY, do_arit},
739 {"sbc", 0x00c00000, NULL, s_flag, ARM_ANY, do_arit},
740 {"rsc", 0x00e00000, NULL, s_flag, ARM_ANY, do_arit},
741 {"orr", 0x01800000, NULL, s_flag, ARM_ANY, do_arit},
742 {"bic", 0x01c00000, NULL, s_flag, ARM_ANY, do_arit},
743 {"tst", 0x01000000, NULL, cmp_flags, ARM_ANY, do_cmp},
744 {"teq", 0x01200000, NULL, cmp_flags, ARM_ANY, do_cmp},
745 {"cmp", 0x01400000, NULL, cmp_flags, ARM_ANY, do_cmp},
746 {"cmn", 0x01600000, NULL, cmp_flags, ARM_ANY, do_cmp},
747 {"mov", 0x01a00000, NULL, s_flag, ARM_ANY, do_mov},
748 {"mvn", 0x01e00000, NULL, s_flag, ARM_ANY, do_mov},
749 {"str", 0x04000000, NULL, str_flags, ARM_ANY, do_ldst},
750 {"ldr", 0x04100000, NULL, ldr_flags, ARM_ANY, do_ldst},
751 {"stm", 0x08000000, NULL, stm_flags, ARM_ANY, do_ldmstm},
752 {"ldm", 0x08100000, NULL, ldm_flags, ARM_ANY, do_ldmstm},
753 {"swi", 0x0f000000, NULL, NULL, ARM_ANY, do_swi},
754 #ifdef TE_WINCE
755 {"bl", 0x0b000000, NULL, NULL, ARM_ANY, do_branch},
756 {"b", 0x0a000000, NULL, NULL, ARM_ANY, do_branch},
757 #else
758 {"bl", 0x0bfffffe, NULL, NULL, ARM_ANY, do_branch},
759 {"b", 0x0afffffe, NULL, NULL, ARM_ANY, do_branch},
760 #endif
761
762 /* Pseudo ops. */
763 {"adr", 0x028f0000, NULL, long_flag, ARM_ANY, do_adr},
764 {"nop", 0x01a00000, NULL, NULL, ARM_ANY, do_nop},
765
766 /* ARM 2 multiplies. */
767 {"mul", 0x00000090, NULL, s_flag, ARM_2UP, do_mul},
768 {"mla", 0x00200090, NULL, s_flag, ARM_2UP, do_mla},
769
770 /* ARM 3 - swp instructions. */
771 {"swp", 0x01000090, NULL, byte_flag, ARM_3UP, do_swap},
772
773 /* ARM 6 Coprocessor instructions. */
774 {"mrs", 0x010f0000, NULL, NULL, ARM_6UP, do_mrs},
775 {"msr", 0x0120f000, NULL, NULL, ARM_6UP, do_msr},
776 /* ScottB: our code uses 0x0128f000 for msr.
777 NickC: but this is wrong because the bits 16 through 19 are
778 handled by the PSR_xxx defines above. */
779
780 /* ARM 7M long multiplies - need signed/unsigned flags! */
781 {"smull", 0x00c00090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull},
782 {"umull", 0x00800090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull},
783 {"smlal", 0x00e00090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull},
784 {"umlal", 0x00a00090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull},
785
786 /* ARM THUMB interworking. */
787 {"bx", 0x012fff10, NULL, NULL, ARM_EXT_THUMB, do_bx},
788
789 /* Floating point instructions. */
790 {"wfs", 0x0e200110, NULL, NULL, FPU_ALL, do_fp_ctrl},
791 {"rfs", 0x0e300110, NULL, NULL, FPU_ALL, do_fp_ctrl},
792 {"wfc", 0x0e400110, NULL, NULL, FPU_ALL, do_fp_ctrl},
793 {"rfc", 0x0e500110, NULL, NULL, FPU_ALL, do_fp_ctrl},
794 {"ldf", 0x0c100100, "sdep", NULL, FPU_ALL, do_fp_ldst},
795 {"stf", 0x0c000100, "sdep", NULL, FPU_ALL, do_fp_ldst},
796 {"lfm", 0x0c100200, NULL, lfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
797 {"sfm", 0x0c000200, NULL, sfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
798 {"mvf", 0x0e008100, "sde", round_flags, FPU_ALL, do_fp_monadic},
799 {"mnf", 0x0e108100, "sde", round_flags, FPU_ALL, do_fp_monadic},
800 {"abs", 0x0e208100, "sde", round_flags, FPU_ALL, do_fp_monadic},
801 {"rnd", 0x0e308100, "sde", round_flags, FPU_ALL, do_fp_monadic},
802 {"sqt", 0x0e408100, "sde", round_flags, FPU_ALL, do_fp_monadic},
803 {"log", 0x0e508100, "sde", round_flags, FPU_ALL, do_fp_monadic},
804 {"lgn", 0x0e608100, "sde", round_flags, FPU_ALL, do_fp_monadic},
805 {"exp", 0x0e708100, "sde", round_flags, FPU_ALL, do_fp_monadic},
806 {"sin", 0x0e808100, "sde", round_flags, FPU_ALL, do_fp_monadic},
807 {"cos", 0x0e908100, "sde", round_flags, FPU_ALL, do_fp_monadic},
808 {"tan", 0x0ea08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
809 {"asn", 0x0eb08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
810 {"acs", 0x0ec08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
811 {"atn", 0x0ed08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
812 {"urd", 0x0ee08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
813 {"nrm", 0x0ef08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
814 {"adf", 0x0e000100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
815 {"suf", 0x0e200100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
816 {"rsf", 0x0e300100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
817 {"muf", 0x0e100100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
818 {"dvf", 0x0e400100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
819 {"rdf", 0x0e500100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
820 {"pow", 0x0e600100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
821 {"rpw", 0x0e700100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
822 {"rmf", 0x0e800100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
823 {"fml", 0x0e900100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
824 {"fdv", 0x0ea00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
825 {"frd", 0x0eb00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
826 {"pol", 0x0ec00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
827 {"cmf", 0x0e90f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
828 {"cnf", 0x0eb0f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
829 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
830 be an optional suffix, but part of the instruction. To be compatible,
831 we accept either. */
832 {"cmfe", 0x0ed0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
833 {"cnfe", 0x0ef0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
834 {"flt", 0x0e000110, "sde", round_flags, FPU_ALL, do_fp_from_reg},
835 {"fix", 0x0e100110, NULL, fix_flags, FPU_ALL, do_fp_to_reg},
836
837 /* Generic copressor instructions. */
838 {"cdp", 0x0e000000, NULL, NULL, ARM_2UP, do_cdp},
839 {"ldc", 0x0c100000, NULL, long_flag, ARM_2UP, do_lstc},
840 {"stc", 0x0c000000, NULL, long_flag, ARM_2UP, do_lstc},
841 {"mcr", 0x0e000010, NULL, NULL, ARM_2UP, do_co_reg},
842 {"mrc", 0x0e100010, NULL, NULL, ARM_2UP, do_co_reg},
843
844 /* ARM ISA extension 5. */
845 /* Note: blx is actually 2 opcodes, so the .value is set dynamically.
846 And it's sometimes conditional and sometimes not. */
847 {"blx", 0, NULL, NULL, ARM_EXT_V5, do_blx},
848 {"clz", 0x016f0f10, NULL, NULL, ARM_EXT_V5, do_clz},
849 {"bkpt", 0xe1200070, "", NULL, ARM_EXT_V5, do_bkpt},
850 {"ldc2", 0xfc100000, "", long_flag, ARM_EXT_V5, do_lstc2},
851 {"stc2", 0xfc000000, "", long_flag, ARM_EXT_V5, do_lstc2},
852 {"cdp2", 0xfe000000, "", NULL, ARM_EXT_V5, do_cdp2},
853 {"mcr2", 0xfe000010, "", NULL, ARM_EXT_V5, do_co_reg2},
854 {"mrc2", 0xfe100010, "", NULL, ARM_EXT_V5, do_co_reg2},
855
856 /* ARM ISA extension 5E, El Segundo. */
857 {"smlabb", 0x01000080, NULL, NULL, ARM_EXT_V5E, do_smla},
858 {"smlatb", 0x010000a0, NULL, NULL, ARM_EXT_V5E, do_smla},
859 {"smlabt", 0x010000c0, NULL, NULL, ARM_EXT_V5E, do_smla},
860 {"smlatt", 0x010000e0, NULL, NULL, ARM_EXT_V5E, do_smla},
861
862 {"smlawb", 0x01200080, NULL, NULL, ARM_EXT_V5E, do_smla},
863 {"smlawt", 0x012000c0, NULL, NULL, ARM_EXT_V5E, do_smla},
864
865 {"smlalbb",0x01400080, NULL, NULL, ARM_EXT_V5E, do_smlal},
866 {"smlaltb",0x014000a0, NULL, NULL, ARM_EXT_V5E, do_smlal},
867 {"smlalbt",0x014000c0, NULL, NULL, ARM_EXT_V5E, do_smlal},
868 {"smlaltt",0x014000e0, NULL, NULL, ARM_EXT_V5E, do_smlal},
869
870 {"smulbb", 0x01600080, NULL, NULL, ARM_EXT_V5E, do_smul},
871 {"smultb", 0x016000a0, NULL, NULL, ARM_EXT_V5E, do_smul},
872 {"smulbt", 0x016000c0, NULL, NULL, ARM_EXT_V5E, do_smul},
873 {"smultt", 0x016000e0, NULL, NULL, ARM_EXT_V5E, do_smul},
874
875 {"smulwb", 0x012000a0, NULL, NULL, ARM_EXT_V5E, do_smul},
876 {"smulwt", 0x012000e0, NULL, NULL, ARM_EXT_V5E, do_smul},
877
878 {"qadd", 0x01000050, NULL, NULL, ARM_EXT_V5E, do_qadd},
879 {"qdadd", 0x01400050, NULL, NULL, ARM_EXT_V5E, do_qadd},
880 {"qsub", 0x01200050, NULL, NULL, ARM_EXT_V5E, do_qadd},
881 {"qdsub", 0x01600050, NULL, NULL, ARM_EXT_V5E, do_qadd},
882
883 {"mcrr", 0x0c400000, NULL, NULL, ARM_EXT_V5E, do_co_reg2c},
884 {"mrrc", 0x0c500000, NULL, NULL, ARM_EXT_V5E, do_co_reg2c},
885 };
886
887 /* Defines for various bits that we will want to toggle. */
888 #define INST_IMMEDIATE 0x02000000
889 #define OFFSET_REG 0x02000000
890 #define HWOFFSET_IMM 0x00400000
891 #define SHIFT_BY_REG 0x00000010
892 #define PRE_INDEX 0x01000000
893 #define INDEX_UP 0x00800000
894 #define WRITE_BACK 0x00200000
895 #define LDM_TYPE_2_OR_3 0x00400000
896
897 #define LITERAL_MASK 0xf000f000
898 #define COND_MASK 0xf0000000
899 #define OPCODE_MASK 0xfe1fffff
900 #define DATA_OP_SHIFT 21
901
902 /* Codes to distinguish the arithmetic instructions. */
903 #define OPCODE_AND 0
904 #define OPCODE_EOR 1
905 #define OPCODE_SUB 2
906 #define OPCODE_RSB 3
907 #define OPCODE_ADD 4
908 #define OPCODE_ADC 5
909 #define OPCODE_SBC 6
910 #define OPCODE_RSC 7
911 #define OPCODE_TST 8
912 #define OPCODE_TEQ 9
913 #define OPCODE_CMP 10
914 #define OPCODE_CMN 11
915 #define OPCODE_ORR 12
916 #define OPCODE_MOV 13
917 #define OPCODE_BIC 14
918 #define OPCODE_MVN 15
919
920 static void do_t_nop PARAMS ((char *));
921 static void do_t_arit PARAMS ((char *));
922 static void do_t_add PARAMS ((char *));
923 static void do_t_asr PARAMS ((char *));
924 static void do_t_branch9 PARAMS ((char *));
925 static void do_t_branch12 PARAMS ((char *));
926 static void do_t_branch23 PARAMS ((char *));
927 static void do_t_bx PARAMS ((char *));
928 static void do_t_compare PARAMS ((char *));
929 static void do_t_ldmstm PARAMS ((char *));
930 static void do_t_ldr PARAMS ((char *));
931 static void do_t_ldrb PARAMS ((char *));
932 static void do_t_ldrh PARAMS ((char *));
933 static void do_t_lds PARAMS ((char *));
934 static void do_t_lsl PARAMS ((char *));
935 static void do_t_lsr PARAMS ((char *));
936 static void do_t_mov PARAMS ((char *));
937 static void do_t_push_pop PARAMS ((char *));
938 static void do_t_str PARAMS ((char *));
939 static void do_t_strb PARAMS ((char *));
940 static void do_t_strh PARAMS ((char *));
941 static void do_t_sub PARAMS ((char *));
942 static void do_t_swi PARAMS ((char *));
943 static void do_t_adr PARAMS ((char *));
944
945 #define T_OPCODE_MUL 0x4340
946 #define T_OPCODE_TST 0x4200
947 #define T_OPCODE_CMN 0x42c0
948 #define T_OPCODE_NEG 0x4240
949 #define T_OPCODE_MVN 0x43c0
950
951 #define T_OPCODE_ADD_R3 0x1800
952 #define T_OPCODE_SUB_R3 0x1a00
953 #define T_OPCODE_ADD_HI 0x4400
954 #define T_OPCODE_ADD_ST 0xb000
955 #define T_OPCODE_SUB_ST 0xb080
956 #define T_OPCODE_ADD_SP 0xa800
957 #define T_OPCODE_ADD_PC 0xa000
958 #define T_OPCODE_ADD_I8 0x3000
959 #define T_OPCODE_SUB_I8 0x3800
960 #define T_OPCODE_ADD_I3 0x1c00
961 #define T_OPCODE_SUB_I3 0x1e00
962
963 #define T_OPCODE_ASR_R 0x4100
964 #define T_OPCODE_LSL_R 0x4080
965 #define T_OPCODE_LSR_R 0x40c0
966 #define T_OPCODE_ASR_I 0x1000
967 #define T_OPCODE_LSL_I 0x0000
968 #define T_OPCODE_LSR_I 0x0800
969
970 #define T_OPCODE_MOV_I8 0x2000
971 #define T_OPCODE_CMP_I8 0x2800
972 #define T_OPCODE_CMP_LR 0x4280
973 #define T_OPCODE_MOV_HR 0x4600
974 #define T_OPCODE_CMP_HR 0x4500
975
976 #define T_OPCODE_LDR_PC 0x4800
977 #define T_OPCODE_LDR_SP 0x9800
978 #define T_OPCODE_STR_SP 0x9000
979 #define T_OPCODE_LDR_IW 0x6800
980 #define T_OPCODE_STR_IW 0x6000
981 #define T_OPCODE_LDR_IH 0x8800
982 #define T_OPCODE_STR_IH 0x8000
983 #define T_OPCODE_LDR_IB 0x7800
984 #define T_OPCODE_STR_IB 0x7000
985 #define T_OPCODE_LDR_RW 0x5800
986 #define T_OPCODE_STR_RW 0x5000
987 #define T_OPCODE_LDR_RH 0x5a00
988 #define T_OPCODE_STR_RH 0x5200
989 #define T_OPCODE_LDR_RB 0x5c00
990 #define T_OPCODE_STR_RB 0x5400
991
992 #define T_OPCODE_PUSH 0xb400
993 #define T_OPCODE_POP 0xbc00
994
995 #define T_OPCODE_BRANCH 0xe7fe
996
997 static int thumb_reg PARAMS ((char ** str, int hi_lo));
998
999 #define THUMB_SIZE 2 /* Size of thumb instruction. */
1000 #define THUMB_REG_LO 0x1
1001 #define THUMB_REG_HI 0x2
1002 #define THUMB_REG_ANY 0x3
1003
1004 #define THUMB_H1 0x0080
1005 #define THUMB_H2 0x0040
1006
1007 #define THUMB_ASR 0
1008 #define THUMB_LSL 1
1009 #define THUMB_LSR 2
1010
1011 #define THUMB_MOVE 0
1012 #define THUMB_COMPARE 1
1013
1014 #define THUMB_LOAD 0
1015 #define THUMB_STORE 1
1016
1017 #define THUMB_PP_PC_LR 0x0100
1018
1019 /* These three are used for immediate shifts, do not alter. */
1020 #define THUMB_WORD 2
1021 #define THUMB_HALFWORD 1
1022 #define THUMB_BYTE 0
1023
1024 struct thumb_opcode
1025 {
1026 /* Basic string to match. */
1027 CONST char * template;
1028
1029 /* Basic instruction code. */
1030 unsigned long value;
1031
1032 int size;
1033
1034 /* Which CPU variants this exists for. */
1035 unsigned long variants;
1036
1037 /* Function to call to parse args. */
1038 void (* parms) PARAMS ((char *));
1039 };
1040
1041 static CONST struct thumb_opcode tinsns[] =
1042 {
1043 {"adc", 0x4140, 2, ARM_EXT_THUMB, do_t_arit},
1044 {"add", 0x0000, 2, ARM_EXT_THUMB, do_t_add},
1045 {"and", 0x4000, 2, ARM_EXT_THUMB, do_t_arit},
1046 {"asr", 0x0000, 2, ARM_EXT_THUMB, do_t_asr},
1047 {"b", T_OPCODE_BRANCH, 2, ARM_EXT_THUMB, do_t_branch12},
1048 {"beq", 0xd0fe, 2, ARM_EXT_THUMB, do_t_branch9},
1049 {"bne", 0xd1fe, 2, ARM_EXT_THUMB, do_t_branch9},
1050 {"bcs", 0xd2fe, 2, ARM_EXT_THUMB, do_t_branch9},
1051 {"bhs", 0xd2fe, 2, ARM_EXT_THUMB, do_t_branch9},
1052 {"bcc", 0xd3fe, 2, ARM_EXT_THUMB, do_t_branch9},
1053 {"bul", 0xd3fe, 2, ARM_EXT_THUMB, do_t_branch9},
1054 {"blo", 0xd3fe, 2, ARM_EXT_THUMB, do_t_branch9},
1055 {"bmi", 0xd4fe, 2, ARM_EXT_THUMB, do_t_branch9},
1056 {"bpl", 0xd5fe, 2, ARM_EXT_THUMB, do_t_branch9},
1057 {"bvs", 0xd6fe, 2, ARM_EXT_THUMB, do_t_branch9},
1058 {"bvc", 0xd7fe, 2, ARM_EXT_THUMB, do_t_branch9},
1059 {"bhi", 0xd8fe, 2, ARM_EXT_THUMB, do_t_branch9},
1060 {"bls", 0xd9fe, 2, ARM_EXT_THUMB, do_t_branch9},
1061 {"bge", 0xdafe, 2, ARM_EXT_THUMB, do_t_branch9},
1062 {"blt", 0xdbfe, 2, ARM_EXT_THUMB, do_t_branch9},
1063 {"bgt", 0xdcfe, 2, ARM_EXT_THUMB, do_t_branch9},
1064 {"ble", 0xddfe, 2, ARM_EXT_THUMB, do_t_branch9},
1065 {"bal", 0xdefe, 2, ARM_EXT_THUMB, do_t_branch9},
1066 {"bic", 0x4380, 2, ARM_EXT_THUMB, do_t_arit},
1067 {"bl", 0xf7fffffe, 4, ARM_EXT_THUMB, do_t_branch23},
1068 {"blx", 0, 0, ARM_EXT_V5, do_t_blx},
1069 {"bkpt", 0xbe00, 2, ARM_EXT_V5, do_t_bkpt},
1070 {"bx", 0x4700, 2, ARM_EXT_THUMB, do_t_bx},
1071 {"cmn", T_OPCODE_CMN, 2, ARM_EXT_THUMB, do_t_arit},
1072 {"cmp", 0x0000, 2, ARM_EXT_THUMB, do_t_compare},
1073 {"eor", 0x4040, 2, ARM_EXT_THUMB, do_t_arit},
1074 {"ldmia", 0xc800, 2, ARM_EXT_THUMB, do_t_ldmstm},
1075 {"ldr", 0x0000, 2, ARM_EXT_THUMB, do_t_ldr},
1076 {"ldrb", 0x0000, 2, ARM_EXT_THUMB, do_t_ldrb},
1077 {"ldrh", 0x0000, 2, ARM_EXT_THUMB, do_t_ldrh},
1078 {"ldrsb", 0x5600, 2, ARM_EXT_THUMB, do_t_lds},
1079 {"ldrsh", 0x5e00, 2, ARM_EXT_THUMB, do_t_lds},
1080 {"ldsb", 0x5600, 2, ARM_EXT_THUMB, do_t_lds},
1081 {"ldsh", 0x5e00, 2, ARM_EXT_THUMB, do_t_lds},
1082 {"lsl", 0x0000, 2, ARM_EXT_THUMB, do_t_lsl},
1083 {"lsr", 0x0000, 2, ARM_EXT_THUMB, do_t_lsr},
1084 {"mov", 0x0000, 2, ARM_EXT_THUMB, do_t_mov},
1085 {"mul", T_OPCODE_MUL, 2, ARM_EXT_THUMB, do_t_arit},
1086 {"mvn", T_OPCODE_MVN, 2, ARM_EXT_THUMB, do_t_arit},
1087 {"neg", T_OPCODE_NEG, 2, ARM_EXT_THUMB, do_t_arit},
1088 {"orr", 0x4300, 2, ARM_EXT_THUMB, do_t_arit},
1089 {"pop", 0xbc00, 2, ARM_EXT_THUMB, do_t_push_pop},
1090 {"push", 0xb400, 2, ARM_EXT_THUMB, do_t_push_pop},
1091 {"ror", 0x41c0, 2, ARM_EXT_THUMB, do_t_arit},
1092 {"sbc", 0x4180, 2, ARM_EXT_THUMB, do_t_arit},
1093 {"stmia", 0xc000, 2, ARM_EXT_THUMB, do_t_ldmstm},
1094 {"str", 0x0000, 2, ARM_EXT_THUMB, do_t_str},
1095 {"strb", 0x0000, 2, ARM_EXT_THUMB, do_t_strb},
1096 {"strh", 0x0000, 2, ARM_EXT_THUMB, do_t_strh},
1097 {"swi", 0xdf00, 2, ARM_EXT_THUMB, do_t_swi},
1098 {"sub", 0x0000, 2, ARM_EXT_THUMB, do_t_sub},
1099 {"tst", T_OPCODE_TST, 2, ARM_EXT_THUMB, do_t_arit},
1100 /* Pseudo ops: */
1101 {"adr", 0x0000, 2, ARM_EXT_THUMB, do_t_adr},
1102 {"nop", 0x46C0, 2, ARM_EXT_THUMB, do_t_nop}, /* mov r8,r8 */
1103 };
1104
1105 struct reg_entry
1106 {
1107 CONST char * name;
1108 int number;
1109 };
1110
1111 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
1112 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
1113 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
1114
1115 #define REG_PC 15
1116 #define REG_LR 14
1117 #define REG_SP 13
1118
1119 /* These are the standard names. Users can add aliases with .req. */
1120 static CONST struct reg_entry reg_table[] =
1121 {
1122 /* Processor Register Numbers. */
1123 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
1124 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
1125 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
1126 {"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC},
1127 /* APCS conventions. */
1128 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
1129 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
1130 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
1131 {"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC},
1132 /* ATPCS additions to APCS conventions. */
1133 {"wr", 7}, {"v8", 11},
1134 /* FP Registers. */
1135 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
1136 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
1137 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
1138 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
1139 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
1140 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
1141 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
1142 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
1143 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
1144 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
1145 /* ATPCS additions to float register names. */
1146 {"s0",16}, {"s1",17}, {"s2",18}, {"s3",19},
1147 {"s4",20}, {"s5",21}, {"s6",22}, {"s7",23},
1148 {"d0",16}, {"d1",17}, {"d2",18}, {"d3",19},
1149 {"d4",20}, {"d5",21}, {"d6",22}, {"d7",23},
1150 /* FIXME: At some point we need to add VFP register names. */
1151 /* Array terminator. */
1152 {NULL, 0}
1153 };
1154
1155 #define BAD_ARGS _("Bad arguments to instruction")
1156 #define BAD_PC _("r15 not allowed here")
1157 #define BAD_FLAGS _("Instruction should not have flags")
1158 #define BAD_COND _("Instruction is not conditional")
1159 #define ERR_NO_ACCUM _("acc0 expected")
1160
1161 static struct hash_control * arm_ops_hsh = NULL;
1162 static struct hash_control * arm_tops_hsh = NULL;
1163 static struct hash_control * arm_cond_hsh = NULL;
1164 static struct hash_control * arm_shift_hsh = NULL;
1165 static struct hash_control * arm_reg_hsh = NULL;
1166 static struct hash_control * arm_psr_hsh = NULL;
1167
1168 /* This table describes all the machine specific pseudo-ops the assembler
1169 has to support. The fields are:
1170 pseudo-op name without dot
1171 function to call to execute this pseudo-op
1172 Integer arg to pass to the function. */
1173
1174 static void s_req PARAMS ((int));
1175 static void s_align PARAMS ((int));
1176 static void s_bss PARAMS ((int));
1177 static void s_even PARAMS ((int));
1178 static void s_ltorg PARAMS ((int));
1179 static void s_arm PARAMS ((int));
1180 static void s_thumb PARAMS ((int));
1181 static void s_code PARAMS ((int));
1182 static void s_force_thumb PARAMS ((int));
1183 static void s_thumb_func PARAMS ((int));
1184 static void s_thumb_set PARAMS ((int));
1185 static void arm_s_text PARAMS ((int));
1186 static void arm_s_data PARAMS ((int));
1187 #ifdef OBJ_ELF
1188 static void arm_s_section PARAMS ((int));
1189 static void s_arm_elf_cons PARAMS ((int));
1190 #endif
1191
1192 static int my_get_expression PARAMS ((expressionS *, char **));
1193
1194 CONST pseudo_typeS md_pseudo_table[] =
1195 {
1196 /* Never called becasue '.req' does not start line. */
1197 { "req", s_req, 0 },
1198 { "bss", s_bss, 0 },
1199 { "align", s_align, 0 },
1200 { "arm", s_arm, 0 },
1201 { "thumb", s_thumb, 0 },
1202 { "code", s_code, 0 },
1203 { "force_thumb", s_force_thumb, 0 },
1204 { "thumb_func", s_thumb_func, 0 },
1205 { "thumb_set", s_thumb_set, 0 },
1206 { "even", s_even, 0 },
1207 { "ltorg", s_ltorg, 0 },
1208 { "pool", s_ltorg, 0 },
1209 /* Allow for the effect of section changes. */
1210 { "text", arm_s_text, 0 },
1211 { "data", arm_s_data, 0 },
1212 #ifdef OBJ_ELF
1213 { "section", arm_s_section, 0 },
1214 { "section.s", arm_s_section, 0 },
1215 { "sect", arm_s_section, 0 },
1216 { "sect.s", arm_s_section, 0 },
1217 { "word", s_arm_elf_cons, 4 },
1218 { "long", s_arm_elf_cons, 4 },
1219 { "file", dwarf2_directive_file, 0 },
1220 { "loc", dwarf2_directive_loc, 0 },
1221 #else
1222 { "word", cons, 4},
1223 #endif
1224 { "extend", float_cons, 'x' },
1225 { "ldouble", float_cons, 'x' },
1226 { "packed", float_cons, 'p' },
1227 { 0, 0, 0 }
1228 };
1229
1230 /* Stuff needed to resolve the label ambiguity
1231 As:
1232 ...
1233 label: <insn>
1234 may differ from:
1235 ...
1236 label:
1237 <insn>
1238 */
1239
1240 symbolS * last_label_seen;
1241 static int label_is_thumb_function_name = false;
1242
1243 /* Literal stuff. */
1244
1245 #define MAX_LITERAL_POOL_SIZE 1024
1246
1247 typedef struct literalS
1248 {
1249 struct expressionS exp;
1250 struct arm_it * inst;
1251 } literalT;
1252
1253 literalT literals[MAX_LITERAL_POOL_SIZE];
1254
1255 /* Next free entry in the pool. */
1256 int next_literal_pool_place = 0;
1257
1258 /* Next literal pool number. */
1259 int lit_pool_num = 1;
1260
1261 symbolS * current_poolP = NULL;
1262
1263 static int
1264 add_to_lit_pool ()
1265 {
1266 int lit_count = 0;
1267
1268 if (current_poolP == NULL)
1269 current_poolP = symbol_create (FAKE_LABEL_NAME, undefined_section,
1270 (valueT) 0, &zero_address_frag);
1271
1272 /* Check if this literal value is already in the pool: */
1273 while (lit_count < next_literal_pool_place)
1274 {
1275 if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
1276 && inst.reloc.exp.X_op == O_constant
1277 && (literals[lit_count].exp.X_add_number
1278 == inst.reloc.exp.X_add_number)
1279 && literals[lit_count].exp.X_unsigned == inst.reloc.exp.X_unsigned)
1280 break;
1281
1282 if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
1283 && inst.reloc.exp.X_op == O_symbol
1284 && (literals[lit_count].exp.X_add_number
1285 == inst.reloc.exp.X_add_number)
1286 && (literals[lit_count].exp.X_add_symbol
1287 == inst.reloc.exp.X_add_symbol)
1288 && (literals[lit_count].exp.X_op_symbol
1289 == inst.reloc.exp.X_op_symbol))
1290 break;
1291
1292 lit_count++;
1293 }
1294
1295 if (lit_count == next_literal_pool_place) /* New entry. */
1296 {
1297 if (next_literal_pool_place >= MAX_LITERAL_POOL_SIZE)
1298 {
1299 inst.error = _("Literal Pool Overflow");
1300 return FAIL;
1301 }
1302
1303 literals[next_literal_pool_place].exp = inst.reloc.exp;
1304 lit_count = next_literal_pool_place++;
1305 }
1306
1307 inst.reloc.exp.X_op = O_symbol;
1308 inst.reloc.exp.X_add_number = (lit_count) * 4 - 8;
1309 inst.reloc.exp.X_add_symbol = current_poolP;
1310
1311 return SUCCESS;
1312 }
1313
1314 /* Can't use symbol_new here, so have to create a symbol and then at
1315 a later date assign it a value. Thats what these functions do. */
1316
1317 static void
1318 symbol_locate (symbolP, name, segment, valu, frag)
1319 symbolS * symbolP;
1320 CONST char * name; /* It is copied, the caller can modify. */
1321 segT segment; /* Segment identifier (SEG_<something>). */
1322 valueT valu; /* Symbol value. */
1323 fragS * frag; /* Associated fragment. */
1324 {
1325 unsigned int name_length;
1326 char * preserved_copy_of_name;
1327
1328 name_length = strlen (name) + 1; /* +1 for \0. */
1329 obstack_grow (&notes, name, name_length);
1330 preserved_copy_of_name = obstack_finish (&notes);
1331 #ifdef STRIP_UNDERSCORE
1332 if (preserved_copy_of_name[0] == '_')
1333 preserved_copy_of_name++;
1334 #endif
1335
1336 #ifdef tc_canonicalize_symbol_name
1337 preserved_copy_of_name =
1338 tc_canonicalize_symbol_name (preserved_copy_of_name);
1339 #endif
1340
1341 S_SET_NAME (symbolP, preserved_copy_of_name);
1342
1343 S_SET_SEGMENT (symbolP, segment);
1344 S_SET_VALUE (symbolP, valu);
1345 symbol_clear_list_pointers(symbolP);
1346
1347 symbol_set_frag (symbolP, frag);
1348
1349 /* Link to end of symbol chain. */
1350 {
1351 extern int symbol_table_frozen;
1352 if (symbol_table_frozen)
1353 abort ();
1354 }
1355
1356 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1357
1358 obj_symbol_new_hook (symbolP);
1359
1360 #ifdef tc_symbol_new_hook
1361 tc_symbol_new_hook (symbolP);
1362 #endif
1363
1364 #ifdef DEBUG_SYMS
1365 verify_symbol_chain (symbol_rootP, symbol_lastP);
1366 #endif /* DEBUG_SYMS */
1367 }
1368
1369 /* Check that an immediate is valid.
1370 If so, convert it to the right format. */
1371
1372 static unsigned int
1373 validate_immediate (val)
1374 unsigned int val;
1375 {
1376 unsigned int a;
1377 unsigned int i;
1378
1379 #define rotate_left(v, n) (v << n | v >> (32 - n))
1380
1381 for (i = 0; i < 32; i += 2)
1382 if ((a = rotate_left (val, i)) <= 0xff)
1383 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
1384
1385 return FAIL;
1386 }
1387
1388 /* Check to see if an immediate can be computed as two seperate immediate
1389 values, added together. We already know that this value cannot be
1390 computed by just one ARM instruction. */
1391
1392 static unsigned int
1393 validate_immediate_twopart (val, highpart)
1394 unsigned int val;
1395 unsigned int * highpart;
1396 {
1397 unsigned int a;
1398 unsigned int i;
1399
1400 for (i = 0; i < 32; i += 2)
1401 if (((a = rotate_left (val, i)) & 0xff) != 0)
1402 {
1403 if (a & 0xff00)
1404 {
1405 if (a & ~ 0xffff)
1406 continue;
1407 * highpart = (a >> 8) | ((i + 24) << 7);
1408 }
1409 else if (a & 0xff0000)
1410 {
1411 if (a & 0xff000000)
1412 continue;
1413 * highpart = (a >> 16) | ((i + 16) << 7);
1414 }
1415 else
1416 {
1417 assert (a & 0xff000000);
1418 * highpart = (a >> 24) | ((i + 8) << 7);
1419 }
1420
1421 return (a & 0xff) | (i << 7);
1422 }
1423
1424 return FAIL;
1425 }
1426
1427 static int
1428 validate_offset_imm (val, hwse)
1429 unsigned int val;
1430 int hwse;
1431 {
1432 if ((hwse && val > 255) || val > 4095)
1433 return FAIL;
1434 return val;
1435 }
1436
1437 static void
1438 s_req (a)
1439 int a ATTRIBUTE_UNUSED;
1440 {
1441 as_bad (_("Invalid syntax for .req directive."));
1442 }
1443
1444 static void
1445 s_bss (ignore)
1446 int ignore ATTRIBUTE_UNUSED;
1447 {
1448 /* We don't support putting frags in the BSS segment, we fake it by
1449 marking in_bss, then looking at s_skip for clues. */
1450 subseg_set (bss_section, 0);
1451 demand_empty_rest_of_line ();
1452 }
1453
1454 static void
1455 s_even (ignore)
1456 int ignore ATTRIBUTE_UNUSED;
1457 {
1458 /* Never make frag if expect extra pass. */
1459 if (!need_pass_2)
1460 frag_align (1, 0, 0);
1461
1462 record_alignment (now_seg, 1);
1463
1464 demand_empty_rest_of_line ();
1465 }
1466
1467 static void
1468 s_ltorg (ignored)
1469 int ignored ATTRIBUTE_UNUSED;
1470 {
1471 int lit_count = 0;
1472 char sym_name[20];
1473
1474 if (current_poolP == NULL)
1475 return;
1476
1477 /* Align pool as you have word accesses.
1478 Only make a frag if we have to. */
1479 if (!need_pass_2)
1480 frag_align (2, 0, 0);
1481
1482 record_alignment (now_seg, 2);
1483
1484 sprintf (sym_name, "$$lit_\002%x", lit_pool_num++);
1485
1486 symbol_locate (current_poolP, sym_name, now_seg,
1487 (valueT) frag_now_fix (), frag_now);
1488 symbol_table_insert (current_poolP);
1489
1490 ARM_SET_THUMB (current_poolP, thumb_mode);
1491
1492 #if defined OBJ_COFF || defined OBJ_ELF
1493 ARM_SET_INTERWORK (current_poolP, support_interwork);
1494 #endif
1495
1496 while (lit_count < next_literal_pool_place)
1497 /* First output the expression in the instruction to the pool. */
1498 emit_expr (&(literals[lit_count++].exp), 4); /* .word */
1499
1500 next_literal_pool_place = 0;
1501 current_poolP = NULL;
1502 }
1503
1504 /* Same as s_align_ptwo but align 0 => align 2. */
1505
1506 static void
1507 s_align (unused)
1508 int unused ATTRIBUTE_UNUSED;
1509 {
1510 register int temp;
1511 register long temp_fill;
1512 long max_alignment = 15;
1513
1514 temp = get_absolute_expression ();
1515 if (temp > max_alignment)
1516 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
1517 else if (temp < 0)
1518 {
1519 as_bad (_("Alignment negative. 0 assumed."));
1520 temp = 0;
1521 }
1522
1523 if (*input_line_pointer == ',')
1524 {
1525 input_line_pointer++;
1526 temp_fill = get_absolute_expression ();
1527 }
1528 else
1529 temp_fill = 0;
1530
1531 if (!temp)
1532 temp = 2;
1533
1534 /* Only make a frag if we HAVE to. */
1535 if (temp && !need_pass_2)
1536 frag_align (temp, (int) temp_fill, 0);
1537 demand_empty_rest_of_line ();
1538
1539 record_alignment (now_seg, temp);
1540 }
1541
1542 static void
1543 s_force_thumb (ignore)
1544 int ignore ATTRIBUTE_UNUSED;
1545 {
1546 /* If we are not already in thumb mode go into it, EVEN if
1547 the target processor does not support thumb instructions.
1548 This is used by gcc/config/arm/lib1funcs.asm for example
1549 to compile interworking support functions even if the
1550 target processor should not support interworking. */
1551 if (! thumb_mode)
1552 {
1553 thumb_mode = 2;
1554
1555 record_alignment (now_seg, 1);
1556 }
1557
1558 demand_empty_rest_of_line ();
1559 }
1560
1561 static void
1562 s_thumb_func (ignore)
1563 int ignore ATTRIBUTE_UNUSED;
1564 {
1565 if (! thumb_mode)
1566 opcode_select (16);
1567
1568 /* The following label is the name/address of the start of a Thumb function.
1569 We need to know this for the interworking support. */
1570 label_is_thumb_function_name = true;
1571
1572 demand_empty_rest_of_line ();
1573 }
1574
1575 /* Perform a .set directive, but also mark the alias as
1576 being a thumb function. */
1577
1578 static void
1579 s_thumb_set (equiv)
1580 int equiv;
1581 {
1582 /* XXX the following is a duplicate of the code for s_set() in read.c
1583 We cannot just call that code as we need to get at the symbol that
1584 is created. */
1585 register char * name;
1586 register char delim;
1587 register char * end_name;
1588 register symbolS * symbolP;
1589
1590 /* Especial apologies for the random logic:
1591 This just grew, and could be parsed much more simply!
1592 Dean - in haste. */
1593 name = input_line_pointer;
1594 delim = get_symbol_end ();
1595 end_name = input_line_pointer;
1596 *end_name = delim;
1597
1598 SKIP_WHITESPACE ();
1599
1600 if (*input_line_pointer != ',')
1601 {
1602 *end_name = 0;
1603 as_bad (_("Expected comma after name \"%s\""), name);
1604 *end_name = delim;
1605 ignore_rest_of_line ();
1606 return;
1607 }
1608
1609 input_line_pointer++;
1610 *end_name = 0;
1611
1612 if (name[0] == '.' && name[1] == '\0')
1613 {
1614 /* XXX - this should not happen to .thumb_set. */
1615 abort ();
1616 }
1617
1618 if ((symbolP = symbol_find (name)) == NULL
1619 && (symbolP = md_undefined_symbol (name)) == NULL)
1620 {
1621 #ifndef NO_LISTING
1622 /* When doing symbol listings, play games with dummy fragments living
1623 outside the normal fragment chain to record the file and line info
1624 for this symbol. */
1625 if (listing & LISTING_SYMBOLS)
1626 {
1627 extern struct list_info_struct * listing_tail;
1628 fragS * dummy_frag = (fragS *) xmalloc (sizeof (fragS));
1629
1630 memset (dummy_frag, 0, sizeof (fragS));
1631 dummy_frag->fr_type = rs_fill;
1632 dummy_frag->line = listing_tail;
1633 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1634 dummy_frag->fr_symbol = symbolP;
1635 }
1636 else
1637 #endif
1638 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1639
1640 #ifdef OBJ_COFF
1641 /* "set" symbols are local unless otherwise specified. */
1642 SF_SET_LOCAL (symbolP);
1643 #endif /* OBJ_COFF */
1644 } /* Make a new symbol. */
1645
1646 symbol_table_insert (symbolP);
1647
1648 * end_name = delim;
1649
1650 if (equiv
1651 && S_IS_DEFINED (symbolP)
1652 && S_GET_SEGMENT (symbolP) != reg_section)
1653 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1654
1655 pseudo_set (symbolP);
1656
1657 demand_empty_rest_of_line ();
1658
1659 /* XXX Now we come to the Thumb specific bit of code. */
1660
1661 THUMB_SET_FUNC (symbolP, 1);
1662 ARM_SET_THUMB (symbolP, 1);
1663 #if defined OBJ_ELF || defined OBJ_COFF
1664 ARM_SET_INTERWORK (symbolP, support_interwork);
1665 #endif
1666 }
1667
1668 /* If we change section we must dump the literal pool first. */
1669
1670 static void
1671 arm_s_text (ignore)
1672 int ignore;
1673 {
1674 if (now_seg != text_section)
1675 s_ltorg (0);
1676
1677 #ifdef OBJ_ELF
1678 obj_elf_text (ignore);
1679 #else
1680 s_text (ignore);
1681 #endif
1682 }
1683
1684 static void
1685 arm_s_data (ignore)
1686 int ignore;
1687 {
1688 if (flag_readonly_data_in_text)
1689 {
1690 if (now_seg != text_section)
1691 s_ltorg (0);
1692 }
1693 else if (now_seg != data_section)
1694 s_ltorg (0);
1695
1696 #ifdef OBJ_ELF
1697 obj_elf_data (ignore);
1698 #else
1699 s_data (ignore);
1700 #endif
1701 }
1702
1703 #ifdef OBJ_ELF
1704 static void
1705 arm_s_section (ignore)
1706 int ignore;
1707 {
1708 s_ltorg (0);
1709
1710 obj_elf_section (ignore);
1711 }
1712 #endif
1713
1714 static void
1715 opcode_select (width)
1716 int width;
1717 {
1718 switch (width)
1719 {
1720 case 16:
1721 if (! thumb_mode)
1722 {
1723 if (! (cpu_variant & ARM_EXT_THUMB))
1724 as_bad (_("selected processor does not support THUMB opcodes"));
1725
1726 thumb_mode = 1;
1727 /* No need to force the alignment, since we will have been
1728 coming from ARM mode, which is word-aligned. */
1729 record_alignment (now_seg, 1);
1730 }
1731 break;
1732
1733 case 32:
1734 if (thumb_mode)
1735 {
1736 if ((cpu_variant & ARM_ANY) == ARM_EXT_THUMB)
1737 as_bad (_("selected processor does not support ARM opcodes"));
1738
1739 thumb_mode = 0;
1740
1741 if (!need_pass_2)
1742 frag_align (2, 0, 0);
1743
1744 record_alignment (now_seg, 1);
1745 }
1746 break;
1747
1748 default:
1749 as_bad (_("invalid instruction size selected (%d)"), width);
1750 }
1751 }
1752
1753 static void
1754 s_arm (ignore)
1755 int ignore ATTRIBUTE_UNUSED;
1756 {
1757 opcode_select (32);
1758 demand_empty_rest_of_line ();
1759 }
1760
1761 static void
1762 s_thumb (ignore)
1763 int ignore ATTRIBUTE_UNUSED;
1764 {
1765 opcode_select (16);
1766 demand_empty_rest_of_line ();
1767 }
1768
1769 static void
1770 s_code (unused)
1771 int unused ATTRIBUTE_UNUSED;
1772 {
1773 register int temp;
1774
1775 temp = get_absolute_expression ();
1776 switch (temp)
1777 {
1778 case 16:
1779 case 32:
1780 opcode_select (temp);
1781 break;
1782
1783 default:
1784 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1785 }
1786 }
1787
1788 static void
1789 end_of_line (str)
1790 char * str;
1791 {
1792 skip_whitespace (str);
1793
1794 if (* str != '\0')
1795 inst.error = _("Garbage following instruction");
1796 }
1797
1798 static int
1799 skip_past_comma (str)
1800 char ** str;
1801 {
1802 char * p = * str, c;
1803 int comma = 0;
1804
1805 while ((c = *p) == ' ' || c == ',')
1806 {
1807 p++;
1808 if (c == ',' && comma++)
1809 return FAIL;
1810 }
1811
1812 if (c == '\0')
1813 return FAIL;
1814
1815 *str = p;
1816 return comma ? SUCCESS : FAIL;
1817 }
1818
1819 /* A standard register must be given at this point.
1820 SHIFT is the place to put it in inst.instruction.
1821 Restores input start point on error.
1822 Returns the reg#, or FAIL. */
1823
1824 static int
1825 reg_required_here (str, shift)
1826 char ** str;
1827 int shift;
1828 {
1829 static char buff [128]; /* XXX */
1830 int reg;
1831 char * start = * str;
1832
1833 if ((reg = arm_reg_parse (str)) != FAIL && int_register (reg))
1834 {
1835 if (shift >= 0)
1836 inst.instruction |= reg << shift;
1837 return reg;
1838 }
1839
1840 /* Restore the start point, we may have got a reg of the wrong class. */
1841 *str = start;
1842
1843 /* In the few cases where we might be able to accept something else
1844 this error can be overridden. */
1845 sprintf (buff, _("Register expected, not '%.100s'"), start);
1846 inst.error = buff;
1847
1848 return FAIL;
1849 }
1850
1851 static CONST struct asm_psr *
1852 arm_psr_parse (ccp)
1853 register char ** ccp;
1854 {
1855 char * start = * ccp;
1856 char c;
1857 char * p;
1858 CONST struct asm_psr * psr;
1859
1860 p = start;
1861
1862 /* Skip to the end of the next word in the input stream. */
1863 do
1864 {
1865 c = *p++;
1866 }
1867 while (isalpha (c) || c == '_');
1868
1869 /* Terminate the word. */
1870 *--p = 0;
1871
1872 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
1873 feature for ease of use and backwards compatibility. */
1874 if (!strncmp (start, "cpsr", 4))
1875 strncpy (start, "CPSR", 4);
1876 else if (!strncmp (start, "spsr", 4))
1877 strncpy (start, "SPSR", 4);
1878
1879 /* Now locate the word in the psr hash table. */
1880 psr = (CONST struct asm_psr *) hash_find (arm_psr_hsh, start);
1881
1882 /* Restore the input stream. */
1883 *p = c;
1884
1885 /* If we found a valid match, advance the
1886 stream pointer past the end of the word. */
1887 *ccp = p;
1888
1889 return psr;
1890 }
1891
1892 /* Parse the input looking for a PSR flag. */
1893
1894 static int
1895 psr_required_here (str)
1896 char ** str;
1897 {
1898 char * start = * str;
1899 CONST struct asm_psr * psr;
1900
1901 psr = arm_psr_parse (str);
1902
1903 if (psr)
1904 {
1905 /* If this is the SPSR that is being modified, set the R bit. */
1906 if (! psr->cpsr)
1907 inst.instruction |= SPSR_BIT;
1908
1909 /* Set the psr flags in the MSR instruction. */
1910 inst.instruction |= psr->field << PSR_SHIFT;
1911
1912 return SUCCESS;
1913 }
1914
1915 /* In the few cases where we might be able to accept
1916 something else this error can be overridden. */
1917 inst.error = _("flag for {c}psr instruction expected");
1918
1919 /* Restore the start point. */
1920 *str = start;
1921 return FAIL;
1922 }
1923
1924 static int
1925 co_proc_number (str)
1926 char ** str;
1927 {
1928 int processor, pchar;
1929
1930 skip_whitespace (* str);
1931
1932 /* The data sheet seems to imply that just a number on its own is valid
1933 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1934 accept either. */
1935 if (**str == 'p' || **str == 'P')
1936 (*str)++;
1937
1938 pchar = *(*str)++;
1939 if (pchar >= '0' && pchar <= '9')
1940 {
1941 processor = pchar - '0';
1942 if (**str >= '0' && **str <= '9')
1943 {
1944 processor = processor * 10 + *(*str)++ - '0';
1945 if (processor > 15)
1946 {
1947 inst.error = _("Illegal co-processor number");
1948 return FAIL;
1949 }
1950 }
1951 }
1952 else
1953 {
1954 inst.error = _("Bad or missing co-processor number");
1955 return FAIL;
1956 }
1957
1958 inst.instruction |= processor << 8;
1959 return SUCCESS;
1960 }
1961
1962 static int
1963 cp_opc_expr (str, where, length)
1964 char ** str;
1965 int where;
1966 int length;
1967 {
1968 expressionS expr;
1969
1970 skip_whitespace (* str);
1971
1972 memset (&expr, '\0', sizeof (expr));
1973
1974 if (my_get_expression (&expr, str))
1975 return FAIL;
1976 if (expr.X_op != O_constant)
1977 {
1978 inst.error = _("bad or missing expression");
1979 return FAIL;
1980 }
1981
1982 if ((expr.X_add_number & ((1 << length) - 1)) != expr.X_add_number)
1983 {
1984 inst.error = _("immediate co-processor expression too large");
1985 return FAIL;
1986 }
1987
1988 inst.instruction |= expr.X_add_number << where;
1989 return SUCCESS;
1990 }
1991
1992 static int
1993 cp_reg_required_here (str, where)
1994 char ** str;
1995 int where;
1996 {
1997 int reg;
1998 char * start = *str;
1999
2000 if ((reg = arm_reg_parse (str)) != FAIL && cp_register (reg))
2001 {
2002 reg &= 15;
2003 inst.instruction |= reg << where;
2004 return reg;
2005 }
2006
2007 /* In the few cases where we might be able to accept something else
2008 this error can be overridden. */
2009 inst.error = _("Co-processor register expected");
2010
2011 /* Restore the start point. */
2012 *str = start;
2013 return FAIL;
2014 }
2015
2016 static int
2017 fp_reg_required_here (str, where)
2018 char ** str;
2019 int where;
2020 {
2021 int reg;
2022 char * start = * str;
2023
2024 if ((reg = arm_reg_parse (str)) != FAIL && fp_register (reg))
2025 {
2026 reg &= 7;
2027 inst.instruction |= reg << where;
2028 return reg;
2029 }
2030
2031 /* In the few cases where we might be able to accept something else
2032 this error can be overridden. */
2033 inst.error = _("Floating point register expected");
2034
2035 /* Restore the start point. */
2036 *str = start;
2037 return FAIL;
2038 }
2039
2040 static int
2041 cp_address_offset (str)
2042 char ** str;
2043 {
2044 int offset;
2045
2046 skip_whitespace (* str);
2047
2048 if (! is_immediate_prefix (**str))
2049 {
2050 inst.error = _("immediate expression expected");
2051 return FAIL;
2052 }
2053
2054 (*str)++;
2055
2056 if (my_get_expression (& inst.reloc.exp, str))
2057 return FAIL;
2058
2059 if (inst.reloc.exp.X_op == O_constant)
2060 {
2061 offset = inst.reloc.exp.X_add_number;
2062
2063 if (offset & 3)
2064 {
2065 inst.error = _("co-processor address must be word aligned");
2066 return FAIL;
2067 }
2068
2069 if (offset > 1023 || offset < -1023)
2070 {
2071 inst.error = _("offset too large");
2072 return FAIL;
2073 }
2074
2075 if (offset >= 0)
2076 inst.instruction |= INDEX_UP;
2077 else
2078 offset = -offset;
2079
2080 inst.instruction |= offset >> 2;
2081 }
2082 else
2083 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
2084
2085 return SUCCESS;
2086 }
2087
2088 static int
2089 cp_address_required_here (str)
2090 char ** str;
2091 {
2092 char * p = * str;
2093 int pre_inc = 0;
2094 int write_back = 0;
2095
2096 if (*p == '[')
2097 {
2098 int reg;
2099
2100 p++;
2101 skip_whitespace (p);
2102
2103 if ((reg = reg_required_here (& p, 16)) == FAIL)
2104 return FAIL;
2105
2106 skip_whitespace (p);
2107
2108 if (*p == ']')
2109 {
2110 p++;
2111
2112 if (skip_past_comma (& p) == SUCCESS)
2113 {
2114 /* [Rn], #expr */
2115 write_back = WRITE_BACK;
2116
2117 if (reg == REG_PC)
2118 {
2119 inst.error = _("pc may not be used in post-increment");
2120 return FAIL;
2121 }
2122
2123 if (cp_address_offset (& p) == FAIL)
2124 return FAIL;
2125 }
2126 else
2127 pre_inc = PRE_INDEX | INDEX_UP;
2128 }
2129 else
2130 {
2131 /* '['Rn, #expr']'[!] */
2132
2133 if (skip_past_comma (& p) == FAIL)
2134 {
2135 inst.error = _("pre-indexed expression expected");
2136 return FAIL;
2137 }
2138
2139 pre_inc = PRE_INDEX;
2140
2141 if (cp_address_offset (& p) == FAIL)
2142 return FAIL;
2143
2144 skip_whitespace (p);
2145
2146 if (*p++ != ']')
2147 {
2148 inst.error = _("missing ]");
2149 return FAIL;
2150 }
2151
2152 skip_whitespace (p);
2153
2154 if (*p == '!')
2155 {
2156 if (reg == REG_PC)
2157 {
2158 inst.error = _("pc may not be used with write-back");
2159 return FAIL;
2160 }
2161
2162 p++;
2163 write_back = WRITE_BACK;
2164 }
2165 }
2166 }
2167 else
2168 {
2169 if (my_get_expression (&inst.reloc.exp, &p))
2170 return FAIL;
2171
2172 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
2173 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust. */
2174 inst.reloc.pc_rel = 1;
2175 inst.instruction |= (REG_PC << 16);
2176 pre_inc = PRE_INDEX;
2177 }
2178
2179 inst.instruction |= write_back | pre_inc;
2180 *str = p;
2181 return SUCCESS;
2182 }
2183
2184 static void
2185 do_nop (str, flags)
2186 char * str;
2187 unsigned long flags;
2188 {
2189 /* Do nothing really. */
2190 inst.instruction |= flags; /* This is pointless. */
2191 end_of_line (str);
2192 return;
2193 }
2194
2195 static void
2196 do_mrs (str, flags)
2197 char *str;
2198 unsigned long flags;
2199 {
2200 int skip = 0;
2201
2202 /* Only one syntax. */
2203 skip_whitespace (str);
2204
2205 if (reg_required_here (&str, 12) == FAIL)
2206 {
2207 inst.error = BAD_ARGS;
2208 return;
2209 }
2210
2211 if (skip_past_comma (&str) == FAIL)
2212 {
2213 inst.error = _("comma expected after register name");
2214 return;
2215 }
2216
2217 skip_whitespace (str);
2218
2219 if ( strcmp (str, "CPSR") == 0
2220 || strcmp (str, "SPSR") == 0
2221 /* Lower case versions for backwards compatability. */
2222 || strcmp (str, "cpsr") == 0
2223 || strcmp (str, "spsr") == 0)
2224 skip = 4;
2225
2226 /* This is for backwards compatability with older toolchains. */
2227 else if ( strcmp (str, "cpsr_all") == 0
2228 || strcmp (str, "spsr_all") == 0)
2229 skip = 8;
2230 else
2231 {
2232 inst.error = _("{C|S}PSR expected");
2233 return;
2234 }
2235
2236 if (* str == 's' || * str == 'S')
2237 inst.instruction |= SPSR_BIT;
2238 str += skip;
2239
2240 inst.instruction |= flags;
2241 end_of_line (str);
2242 }
2243
2244 /* Two possible forms:
2245 "{C|S}PSR_<field>, Rm",
2246 "{C|S}PSR_f, #expression". */
2247
2248 static void
2249 do_msr (str, flags)
2250 char * str;
2251 unsigned long flags;
2252 {
2253 skip_whitespace (str);
2254
2255 if (psr_required_here (& str) == FAIL)
2256 return;
2257
2258 if (skip_past_comma (& str) == FAIL)
2259 {
2260 inst.error = _("comma missing after psr flags");
2261 return;
2262 }
2263
2264 skip_whitespace (str);
2265
2266 if (reg_required_here (& str, 0) != FAIL)
2267 {
2268 inst.error = NULL;
2269 inst.instruction |= flags;
2270 end_of_line (str);
2271 return;
2272 }
2273
2274 if (! is_immediate_prefix (* str))
2275 {
2276 inst.error =
2277 _("only a register or immediate value can follow a psr flag");
2278 return;
2279 }
2280
2281 str ++;
2282 inst.error = NULL;
2283
2284 if (my_get_expression (& inst.reloc.exp, & str))
2285 {
2286 inst.error =
2287 _("only a register or immediate value can follow a psr flag");
2288 return;
2289 }
2290
2291 #if 0 /* The first edition of the ARM architecture manual stated that
2292 writing anything other than the flags with an immediate operation
2293 had UNPREDICTABLE effects. This constraint was removed in the
2294 second edition of the specification. */
2295 if ((cpu_variant & ARM_EXT_V5) != ARM_EXT_V5
2296 && inst.instruction & ((PSR_c | PSR_x | PSR_s) << PSR_SHIFT))
2297 {
2298 inst.error = _("immediate value cannot be used to set this field");
2299 return;
2300 }
2301 #endif
2302
2303 flags |= INST_IMMEDIATE;
2304
2305 if (inst.reloc.exp.X_add_symbol)
2306 {
2307 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2308 inst.reloc.pc_rel = 0;
2309 }
2310 else
2311 {
2312 unsigned value = validate_immediate (inst.reloc.exp.X_add_number);
2313
2314 if (value == (unsigned) FAIL)
2315 {
2316 inst.error = _("Invalid constant");
2317 return;
2318 }
2319
2320 inst.instruction |= value;
2321 }
2322
2323 inst.error = NULL;
2324 inst.instruction |= flags;
2325 end_of_line (str);
2326 }
2327
2328 /* Long Multiply Parser
2329 UMULL RdLo, RdHi, Rm, Rs
2330 SMULL RdLo, RdHi, Rm, Rs
2331 UMLAL RdLo, RdHi, Rm, Rs
2332 SMLAL RdLo, RdHi, Rm, Rs. */
2333
2334 static void
2335 do_mull (str, flags)
2336 char * str;
2337 unsigned long flags;
2338 {
2339 int rdlo, rdhi, rm, rs;
2340
2341 /* Only one format "rdlo, rdhi, rm, rs". */
2342 skip_whitespace (str);
2343
2344 if ((rdlo = reg_required_here (&str, 12)) == FAIL)
2345 {
2346 inst.error = BAD_ARGS;
2347 return;
2348 }
2349
2350 if (skip_past_comma (&str) == FAIL
2351 || (rdhi = reg_required_here (&str, 16)) == FAIL)
2352 {
2353 inst.error = BAD_ARGS;
2354 return;
2355 }
2356
2357 if (skip_past_comma (&str) == FAIL
2358 || (rm = reg_required_here (&str, 0)) == FAIL)
2359 {
2360 inst.error = BAD_ARGS;
2361 return;
2362 }
2363
2364 /* rdhi, rdlo and rm must all be different. */
2365 if (rdlo == rdhi || rdlo == rm || rdhi == rm)
2366 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
2367
2368 if (skip_past_comma (&str) == FAIL
2369 || (rs = reg_required_here (&str, 8)) == FAIL)
2370 {
2371 inst.error = BAD_ARGS;
2372 return;
2373 }
2374
2375 if (rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC)
2376 {
2377 inst.error = BAD_PC;
2378 return;
2379 }
2380
2381 inst.instruction |= flags;
2382 end_of_line (str);
2383 return;
2384 }
2385
2386 static void
2387 do_mul (str, flags)
2388 char * str;
2389 unsigned long flags;
2390 {
2391 int rd, rm;
2392
2393 /* Only one format "rd, rm, rs". */
2394 skip_whitespace (str);
2395
2396 if ((rd = reg_required_here (&str, 16)) == FAIL)
2397 {
2398 inst.error = BAD_ARGS;
2399 return;
2400 }
2401
2402 if (rd == REG_PC)
2403 {
2404 inst.error = BAD_PC;
2405 return;
2406 }
2407
2408 if (skip_past_comma (&str) == FAIL
2409 || (rm = reg_required_here (&str, 0)) == FAIL)
2410 {
2411 inst.error = BAD_ARGS;
2412 return;
2413 }
2414
2415 if (rm == REG_PC)
2416 {
2417 inst.error = BAD_PC;
2418 return;
2419 }
2420
2421 if (rm == rd)
2422 as_tsktsk (_("rd and rm should be different in mul"));
2423
2424 if (skip_past_comma (&str) == FAIL
2425 || (rm = reg_required_here (&str, 8)) == FAIL)
2426 {
2427 inst.error = BAD_ARGS;
2428 return;
2429 }
2430
2431 if (rm == REG_PC)
2432 {
2433 inst.error = BAD_PC;
2434 return;
2435 }
2436
2437 inst.instruction |= flags;
2438 end_of_line (str);
2439 return;
2440 }
2441
2442 static void
2443 do_mla (str, flags)
2444 char * str;
2445 unsigned long flags;
2446 {
2447 int rd, rm;
2448
2449 /* Only one format "rd, rm, rs, rn". */
2450 skip_whitespace (str);
2451
2452 if ((rd = reg_required_here (&str, 16)) == FAIL)
2453 {
2454 inst.error = BAD_ARGS;
2455 return;
2456 }
2457
2458 if (rd == REG_PC)
2459 {
2460 inst.error = BAD_PC;
2461 return;
2462 }
2463
2464 if (skip_past_comma (&str) == FAIL
2465 || (rm = reg_required_here (&str, 0)) == FAIL)
2466 {
2467 inst.error = BAD_ARGS;
2468 return;
2469 }
2470
2471 if (rm == REG_PC)
2472 {
2473 inst.error = BAD_PC;
2474 return;
2475 }
2476
2477 if (rm == rd)
2478 as_tsktsk (_("rd and rm should be different in mla"));
2479
2480 if (skip_past_comma (&str) == FAIL
2481 || (rd = reg_required_here (&str, 8)) == FAIL
2482 || skip_past_comma (&str) == FAIL
2483 || (rm = reg_required_here (&str, 12)) == FAIL)
2484 {
2485 inst.error = BAD_ARGS;
2486 return;
2487 }
2488
2489 if (rd == REG_PC || rm == REG_PC)
2490 {
2491 inst.error = BAD_PC;
2492 return;
2493 }
2494
2495 inst.instruction |= flags;
2496 end_of_line (str);
2497 return;
2498 }
2499
2500 /* Expects *str -> the characters "acc0", possibly with leading blanks.
2501 Advances *str to the next non-alphanumeric.
2502 Returns 0, or else FAIL (in which case sets inst.error).
2503
2504 (In a future XScale, there may be accumulators other than zero.
2505 At that time this routine and its callers can be upgraded to suit.) */
2506
2507 static int
2508 accum0_required_here (str)
2509 char ** str;
2510 {
2511 static char buff [128]; /* Note the address is taken. Hence, static. */
2512 char * p = * str;
2513 char c;
2514 int result = 0; /* The accum number. */
2515
2516 skip_whitespace (p);
2517
2518 *str = p; /* Advance caller's string pointer too. */
2519 c = *p++;
2520 while (isalnum (c))
2521 c = *p++;
2522
2523 *--p = 0; /* Aap nul into input buffer at non-alnum. */
2524
2525 if (! ( streq (*str, "acc0") || streq (*str, "ACC0")))
2526 {
2527 sprintf (buff, _("acc0 expected, not '%.100s'"), *str);
2528 inst.error = buff;
2529 result = FAIL;
2530 }
2531
2532 *p = c; /* Unzap. */
2533 *str = p; /* Caller's string pointer to after match. */
2534 return result;
2535 }
2536
2537 /* Expects **str -> after a comma. May be leading blanks.
2538 Advances *str, recognizing a load mode, and setting inst.instruction.
2539 Returns rn, or else FAIL (in which case may set inst.error
2540 and not advance str)
2541
2542 Note: doesn't know Rd, so no err checks that require such knowledge. */
2543
2544 static int
2545 ld_mode_required_here (string)
2546 char ** string;
2547 {
2548 char * str = * string;
2549 int rn;
2550 int pre_inc = 0;
2551
2552 skip_whitespace (str);
2553
2554 if (* str == '[')
2555 {
2556 str++;
2557
2558 skip_whitespace (str);
2559
2560 if ((rn = reg_required_here (& str, 16)) == FAIL)
2561 return FAIL;
2562
2563 skip_whitespace (str);
2564
2565 if (* str == ']')
2566 {
2567 str ++;
2568
2569 if (skip_past_comma (& str) == SUCCESS)
2570 {
2571 /* [Rn],... (post inc) */
2572 if (ldst_extend (& str, 1) == FAIL)
2573 return FAIL;
2574 }
2575 else /* [Rn] */
2576 {
2577 skip_whitespace (str);
2578
2579 if (* str == '!')
2580 {
2581 str ++;
2582 inst.instruction |= WRITE_BACK;
2583 }
2584
2585 inst.instruction |= INDEX_UP | HWOFFSET_IMM;
2586 pre_inc = 1;
2587 }
2588 }
2589 else /* [Rn,...] */
2590 {
2591 if (skip_past_comma (& str) == FAIL)
2592 {
2593 inst.error = _("pre-indexed expression expected");
2594 return FAIL;
2595 }
2596
2597 pre_inc = 1;
2598
2599 if (ldst_extend (& str, 1) == FAIL)
2600 return FAIL;
2601
2602 skip_whitespace (str);
2603
2604 if (* str ++ != ']')
2605 {
2606 inst.error = _("missing ]");
2607 return FAIL;
2608 }
2609
2610 skip_whitespace (str);
2611
2612 if (* str == '!')
2613 {
2614 str ++;
2615 inst.instruction |= WRITE_BACK;
2616 }
2617 }
2618 }
2619 else if (* str == '=') /* ldr's "r,=label" syntax */
2620 /* We should never reach here, because <text> = <expression> is
2621 caught gas/read.c read_a_source_file() as a .set operation. */
2622 return FAIL;
2623 else /* PC +- 8 bit immediate offset. */
2624 {
2625 if (my_get_expression (& inst.reloc.exp, & str))
2626 return FAIL;
2627
2628 inst.instruction |= HWOFFSET_IMM; /* The I bit. */
2629 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
2630 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust. */
2631 inst.reloc.pc_rel = 1;
2632 inst.instruction |= (REG_PC << 16);
2633
2634 rn = REG_PC;
2635 pre_inc = 1;
2636 }
2637
2638 inst.instruction |= (pre_inc ? PRE_INDEX : 0);
2639 * string = str;
2640
2641 return rn;
2642 }
2643
2644 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
2645 SMLAxy{cond} Rd,Rm,Rs,Rn
2646 SMLAWy{cond} Rd,Rm,Rs,Rn
2647 Error if any register is R15. */
2648
2649 static void
2650 do_smla (str, flags)
2651 char * str;
2652 unsigned long flags;
2653 {
2654 int rd, rm, rs, rn;
2655
2656 skip_whitespace (str);
2657
2658 if ((rd = reg_required_here (& str, 16)) == FAIL
2659 || skip_past_comma (& str) == FAIL
2660 || (rm = reg_required_here (& str, 0)) == FAIL
2661 || skip_past_comma (& str) == FAIL
2662 || (rs = reg_required_here (& str, 8)) == FAIL
2663 || skip_past_comma (& str) == FAIL
2664 || (rn = reg_required_here (& str, 12)) == FAIL)
2665 inst.error = BAD_ARGS;
2666
2667 else if (rd == REG_PC || rm == REG_PC || rs == REG_PC || rn == REG_PC)
2668 inst.error = BAD_PC;
2669
2670 else if (flags)
2671 inst.error = BAD_FLAGS;
2672
2673 else
2674 end_of_line (str);
2675 }
2676
2677 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
2678 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
2679 Error if any register is R15.
2680 Warning if Rdlo == Rdhi. */
2681
2682 static void
2683 do_smlal (str, flags)
2684 char * str;
2685 unsigned long flags;
2686 {
2687 int rdlo, rdhi, rm, rs;
2688
2689 skip_whitespace (str);
2690
2691 if ((rdlo = reg_required_here (& str, 12)) == FAIL
2692 || skip_past_comma (& str) == FAIL
2693 || (rdhi = reg_required_here (& str, 16)) == FAIL
2694 || skip_past_comma (& str) == FAIL
2695 || (rm = reg_required_here (& str, 0)) == FAIL
2696 || skip_past_comma (& str) == FAIL
2697 || (rs = reg_required_here (& str, 8)) == FAIL)
2698 {
2699 inst.error = BAD_ARGS;
2700 return;
2701 }
2702
2703 if (rdlo == REG_PC || rdhi == REG_PC || rm == REG_PC || rs == REG_PC)
2704 {
2705 inst.error = BAD_PC;
2706 return;
2707 }
2708
2709 if (rdlo == rdhi)
2710 as_tsktsk (_("rdhi and rdlo must be different"));
2711
2712 if (flags)
2713 inst.error = BAD_FLAGS;
2714 else
2715 end_of_line (str);
2716 }
2717
2718 /* ARM V5E (El Segundo) signed-multiply (argument parse)
2719 SMULxy{cond} Rd,Rm,Rs
2720 Error if any register is R15. */
2721
2722 static void
2723 do_smul (str, flags)
2724 char * str;
2725 unsigned long flags;
2726 {
2727 int rd, rm, rs;
2728
2729 skip_whitespace (str);
2730
2731 if ((rd = reg_required_here (& str, 16)) == FAIL
2732 || skip_past_comma (& str) == FAIL
2733 || (rm = reg_required_here (& str, 0)) == FAIL
2734 || skip_past_comma (& str) == FAIL
2735 || (rs = reg_required_here (& str, 8)) == FAIL)
2736 inst.error = BAD_ARGS;
2737
2738 else if (rd == REG_PC || rm == REG_PC || rs == REG_PC)
2739 inst.error = BAD_PC;
2740
2741 else if (flags)
2742 inst.error = BAD_FLAGS;
2743
2744 else
2745 end_of_line (str);
2746 }
2747
2748 /* ARM V5E (El Segundo) saturating-add/subtract (argument parse)
2749 Q[D]{ADD,SUB}{cond} Rd,Rm,Rn
2750 Error if any register is R15. */
2751
2752 static void
2753 do_qadd (str, flags)
2754 char * str;
2755 unsigned long flags;
2756 {
2757 int rd, rm, rn;
2758
2759 skip_whitespace (str);
2760
2761 if ((rd = reg_required_here (& str, 12)) == FAIL
2762 || skip_past_comma (& str) == FAIL
2763 || (rm = reg_required_here (& str, 0)) == FAIL
2764 || skip_past_comma (& str) == FAIL
2765 || (rn = reg_required_here (& str, 16)) == FAIL)
2766 inst.error = BAD_ARGS;
2767
2768 else if (rd == REG_PC || rm == REG_PC || rn == REG_PC)
2769 inst.error = BAD_PC;
2770
2771 else if (flags)
2772 inst.error = BAD_FLAGS;
2773
2774 else
2775 end_of_line (str);
2776 }
2777
2778 /* ARM V5E (el Segundo)
2779 MCRRcc <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
2780 MRRCcc <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
2781
2782 These are equivalent to the XScale instructions MAR and MRA,
2783 respectively, when coproc == 0, opcode == 0, and CRm == 0.
2784
2785 Result unpredicatable if Rd or Rn is R15. */
2786
2787 static void
2788 do_co_reg2c (str, flags)
2789 char * str;
2790 unsigned long flags;
2791 {
2792 int rd, rn;
2793
2794 skip_whitespace (str);
2795
2796 if (co_proc_number (& str) == FAIL)
2797 {
2798 if (!inst.error)
2799 inst.error = BAD_ARGS;
2800 return;
2801 }
2802
2803 if (skip_past_comma (& str) == FAIL
2804 || cp_opc_expr (& str, 4, 4) == FAIL)
2805 {
2806 if (!inst.error)
2807 inst.error = BAD_ARGS;
2808 return;
2809 }
2810
2811 if (skip_past_comma (& str) == FAIL
2812 || (rd = reg_required_here (& str, 12)) == FAIL)
2813 {
2814 if (!inst.error)
2815 inst.error = BAD_ARGS;
2816 return;
2817 }
2818
2819 if (skip_past_comma (& str) == FAIL
2820 || (rn = reg_required_here (& str, 16)) == FAIL)
2821 {
2822 if (!inst.error)
2823 inst.error = BAD_ARGS;
2824 return;
2825 }
2826
2827 /* Unpredictable result if rd or rn is R15. */
2828 if (rd == REG_PC || rn == REG_PC)
2829 as_tsktsk
2830 (_("Warning: Instruction unpredictable when using r15"));
2831
2832 if (skip_past_comma (& str) == FAIL
2833 || cp_reg_required_here (& str, 0) == FAIL)
2834 {
2835 if (!inst.error)
2836 inst.error = BAD_ARGS;
2837 return;
2838 }
2839
2840 if (flags)
2841 inst.error = BAD_COND;
2842
2843 end_of_line (str);
2844 }
2845
2846 /* ARM V5 count-leading-zeroes instruction (argument parse)
2847 CLZ{<cond>} <Rd>, <Rm>
2848 Condition defaults to COND_ALWAYS.
2849 Error if Rd or Rm are R15. */
2850
2851 static void
2852 do_clz (str, flags)
2853 char * str;
2854 unsigned long flags;
2855 {
2856 int rd, rm;
2857
2858 if (flags)
2859 {
2860 as_bad (BAD_FLAGS);
2861 return;
2862 }
2863
2864 skip_whitespace (str);
2865
2866 if (((rd = reg_required_here (& str, 12)) == FAIL)
2867 || (skip_past_comma (& str) == FAIL)
2868 || ((rm = reg_required_here (& str, 0)) == FAIL))
2869 inst.error = BAD_ARGS;
2870
2871 else if (rd == REG_PC || rm == REG_PC )
2872 inst.error = BAD_PC;
2873
2874 else
2875 end_of_line (str);
2876 }
2877
2878 /* ARM V5 (argument parse)
2879 LDC2{L} <coproc>, <CRd>, <addressing mode>
2880 STC2{L} <coproc>, <CRd>, <addressing mode>
2881 Instruction is not conditional, and has 0xf in the codition field.
2882 Otherwise, it's the same as LDC/STC. */
2883
2884 static void
2885 do_lstc2 (str, flags)
2886 char * str;
2887 unsigned long flags;
2888 {
2889 if (flags)
2890 inst.error = BAD_COND;
2891
2892 skip_whitespace (str);
2893
2894 if (co_proc_number (& str) == FAIL)
2895 {
2896 if (!inst.error)
2897 inst.error = BAD_ARGS;
2898 }
2899 else if (skip_past_comma (& str) == FAIL
2900 || cp_reg_required_here (& str, 12) == FAIL)
2901 {
2902 if (!inst.error)
2903 inst.error = BAD_ARGS;
2904 }
2905 else if (skip_past_comma (& str) == FAIL
2906 || cp_address_required_here (& str) == FAIL)
2907 {
2908 if (! inst.error)
2909 inst.error = BAD_ARGS;
2910 }
2911 else
2912 end_of_line (str);
2913 }
2914
2915 /* ARM V5 (argument parse)
2916 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2>
2917 Instruction is not conditional, and has 0xf in the condition field.
2918 Otherwise, it's the same as CDP. */
2919
2920 static void
2921 do_cdp2 (str, flags)
2922 char * str;
2923 unsigned long flags;
2924 {
2925 skip_whitespace (str);
2926
2927 if (co_proc_number (& str) == FAIL)
2928 {
2929 if (!inst.error)
2930 inst.error = BAD_ARGS;
2931 return;
2932 }
2933
2934 if (skip_past_comma (& str) == FAIL
2935 || cp_opc_expr (& str, 20,4) == FAIL)
2936 {
2937 if (!inst.error)
2938 inst.error = BAD_ARGS;
2939 return;
2940 }
2941
2942 if (skip_past_comma (& str) == FAIL
2943 || cp_reg_required_here (& str, 12) == FAIL)
2944 {
2945 if (!inst.error)
2946 inst.error = BAD_ARGS;
2947 return;
2948 }
2949
2950 if (skip_past_comma (& str) == FAIL
2951 || cp_reg_required_here (& str, 16) == FAIL)
2952 {
2953 if (!inst.error)
2954 inst.error = BAD_ARGS;
2955 return;
2956 }
2957
2958 if (skip_past_comma (& str) == FAIL
2959 || cp_reg_required_here (& str, 0) == FAIL)
2960 {
2961 if (!inst.error)
2962 inst.error = BAD_ARGS;
2963 return;
2964 }
2965
2966 if (skip_past_comma (& str) == SUCCESS)
2967 {
2968 if (cp_opc_expr (& str, 5, 3) == FAIL)
2969 {
2970 if (!inst.error)
2971 inst.error = BAD_ARGS;
2972 return;
2973 }
2974 }
2975
2976 if (flags)
2977 inst.error = BAD_FLAGS;
2978
2979 end_of_line (str);
2980 }
2981
2982 /* ARM V5 (argument parse)
2983 MCR2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>, <opcode_2>
2984 MRC2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>, <opcode_2>
2985 Instruction is not conditional, and has 0xf in the condition field.
2986 Otherwise, it's the same as MCR/MRC. */
2987
2988 static void
2989 do_co_reg2 (str, flags)
2990 char * str;
2991 unsigned long flags;
2992 {
2993 skip_whitespace (str);
2994
2995 if (co_proc_number (& str) == FAIL)
2996 {
2997 if (!inst.error)
2998 inst.error = BAD_ARGS;
2999 return;
3000 }
3001
3002 if (skip_past_comma (& str) == FAIL
3003 || cp_opc_expr (& str, 21, 3) == FAIL)
3004 {
3005 if (!inst.error)
3006 inst.error = BAD_ARGS;
3007 return;
3008 }
3009
3010 if (skip_past_comma (& str) == FAIL
3011 || reg_required_here (& str, 12) == FAIL)
3012 {
3013 if (!inst.error)
3014 inst.error = BAD_ARGS;
3015 return;
3016 }
3017
3018 if (skip_past_comma (& str) == FAIL
3019 || cp_reg_required_here (& str, 16) == FAIL)
3020 {
3021 if (!inst.error)
3022 inst.error = BAD_ARGS;
3023 return;
3024 }
3025
3026 if (skip_past_comma (& str) == FAIL
3027 || cp_reg_required_here (& str, 0) == FAIL)
3028 {
3029 if (!inst.error)
3030 inst.error = BAD_ARGS;
3031 return;
3032 }
3033
3034 if (skip_past_comma (& str) == SUCCESS)
3035 {
3036 if (cp_opc_expr (& str, 5, 3) == FAIL)
3037 {
3038 if (!inst.error)
3039 inst.error = BAD_ARGS;
3040 return;
3041 }
3042 }
3043
3044 if (flags)
3045 inst.error = BAD_COND;
3046
3047 end_of_line (str);
3048 }
3049
3050 /* THUMB V5 breakpoint instruction (argument parse)
3051 BKPT <immed_8>. */
3052
3053 static void
3054 do_t_bkpt (str)
3055 char * str;
3056 {
3057 expressionS expr;
3058 unsigned long number;
3059
3060 skip_whitespace (str);
3061
3062 /* Allow optional leading '#'. */
3063 if (is_immediate_prefix (*str))
3064 str ++;
3065
3066 memset (& expr, '\0', sizeof (expr));
3067 if (my_get_expression (& expr, & str) || (expr.X_op != O_constant))
3068 {
3069 inst.error = _("bad or missing expression");
3070 return;
3071 }
3072
3073 number = expr.X_add_number;
3074
3075 /* Check it fits an 8 bit unsigned. */
3076 if (number != (number & 0xff))
3077 {
3078 inst.error = _("immediate value out of range");
3079 return;
3080 }
3081
3082 inst.instruction |= number;
3083
3084 end_of_line (str);
3085 }
3086
3087 /* ARM V5 branch-link-exchange (argument parse) for BLX(1) only.
3088 Expects inst.instruction is set for BLX(1).
3089 Note: this is cloned from do_branch, and the reloc changed to be a
3090 new one that can cope with setting one extra bit (the H bit). */
3091
3092 static void
3093 do_branch25 (str, flags)
3094 char * str;
3095 unsigned long flags ATTRIBUTE_UNUSED;
3096 {
3097 if (my_get_expression (& inst.reloc.exp, & str))
3098 return;
3099
3100 #ifdef OBJ_ELF
3101 {
3102 char * save_in;
3103
3104 /* ScottB: February 5, 1998 */
3105 /* Check to see of PLT32 reloc required for the instruction. */
3106
3107 /* arm_parse_reloc() works on input_line_pointer.
3108 We actually want to parse the operands to the branch instruction
3109 passed in 'str'. Save the input pointer and restore it later. */
3110 save_in = input_line_pointer;
3111 input_line_pointer = str;
3112
3113 if (inst.reloc.exp.X_op == O_symbol
3114 && *str == '('
3115 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
3116 {
3117 inst.reloc.type = BFD_RELOC_ARM_PLT32;
3118 inst.reloc.pc_rel = 0;
3119 /* Modify str to point to after parsed operands, otherwise
3120 end_of_line() will complain about the (PLT) left in str. */
3121 str = input_line_pointer;
3122 }
3123 else
3124 {
3125 inst.reloc.type = BFD_RELOC_ARM_PCREL_BLX;
3126 inst.reloc.pc_rel = 1;
3127 }
3128
3129 input_line_pointer = save_in;
3130 }
3131 #else
3132 inst.reloc.type = BFD_RELOC_ARM_PCREL_BLX;
3133 inst.reloc.pc_rel = 1;
3134 #endif /* OBJ_ELF */
3135
3136 end_of_line (str);
3137 }
3138
3139 /* ARM V5 branch-link-exchange instruction (argument parse)
3140 BLX <target_addr> ie BLX(1)
3141 BLX{<condition>} <Rm> ie BLX(2)
3142 Unfortunately, there are two different opcodes for this mnemonic.
3143 So, the insns[].value is not used, and the code here zaps values
3144 into inst.instruction.
3145 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
3146
3147 static void
3148 do_blx (str, flags)
3149 char * str;
3150 unsigned long flags;
3151 {
3152 char * mystr = str;
3153 int rm;
3154
3155 if (flags)
3156 {
3157 as_bad (BAD_FLAGS);
3158 return;
3159 }
3160
3161 skip_whitespace (mystr);
3162 rm = reg_required_here (& mystr, 0);
3163
3164 /* The above may set inst.error. Ignore his opinion. */
3165 inst.error = 0;
3166
3167 if (rm != FAIL)
3168 {
3169 /* Arg is a register.
3170 Use the condition code our caller put in inst.instruction.
3171 Pass ourselves off as a BX with a funny opcode. */
3172 inst.instruction |= 0x012fff30;
3173 do_bx (str, flags);
3174 }
3175 else
3176 {
3177 /* This must be is BLX <target address>, no condition allowed. */
3178 if (inst.instruction != COND_ALWAYS)
3179 {
3180 inst.error = BAD_COND;
3181 return;
3182 }
3183
3184 inst.instruction = 0xfafffffe;
3185
3186 /* Process like a B/BL, but with a different reloc.
3187 Note that B/BL expecte fffffe, not 0, offset in the opcode table. */
3188 do_branch25 (str, flags);
3189 }
3190 }
3191
3192 /* ARM V5 Thumb BLX (argument parse)
3193 BLX <target_addr> which is BLX(1)
3194 BLX <Rm> which is BLX(2)
3195 Unfortunately, there are two different opcodes for this mnemonic.
3196 So, the tinsns[].value is not used, and the code here zaps values
3197 into inst.instruction. */
3198
3199 static void
3200 do_t_blx (str)
3201 char * str;
3202 {
3203 char * mystr = str;
3204 int rm;
3205
3206 skip_whitespace (mystr);
3207 inst.instruction = 0x4780;
3208
3209 /* Note that this call is to the ARM register recognizer. BLX(2)
3210 uses the ARM register space, not the Thumb one, so a call to
3211 thumb_reg() would be wrong. */
3212 rm = reg_required_here (& mystr, 3);
3213 inst.error = 0;
3214
3215 if (rm != FAIL)
3216 {
3217 /* It's BLX(2). The .instruction was zapped with rm & is final. */
3218 inst.size = 2;
3219 }
3220 else
3221 {
3222 /* No ARM register. This must be BLX(1). Change the .instruction. */
3223 inst.instruction = 0xf7ffeffe;
3224 inst.size = 4;
3225
3226 if (my_get_expression (& inst.reloc.exp, & mystr))
3227 return;
3228
3229 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
3230 inst.reloc.pc_rel = 1;
3231 }
3232
3233 end_of_line (mystr);
3234 }
3235
3236 /* ARM V5 breakpoint instruction (argument parse)
3237 BKPT <16 bit unsigned immediate>
3238 Instruction is not conditional.
3239 The bit pattern given in insns[] has the COND_ALWAYS condition,
3240 and it is an error if the caller tried to override that.
3241 Note "flags" is nonzero if a flag was supplied (which is an error). */
3242
3243 static void
3244 do_bkpt (str, flags)
3245 char * str;
3246 unsigned long flags;
3247 {
3248 expressionS expr;
3249 unsigned long number;
3250
3251 skip_whitespace (str);
3252
3253 /* Allow optional leading '#'. */
3254 if (is_immediate_prefix (* str))
3255 str++;
3256
3257 memset (& expr, '\0', sizeof (expr));
3258
3259 if (my_get_expression (& expr, & str) || (expr.X_op != O_constant))
3260 {
3261 inst.error = _("bad or missing expression");
3262 return;
3263 }
3264
3265 number = expr.X_add_number;
3266
3267 /* Check it fits a 16 bit unsigned. */
3268 if (number != (number & 0xffff))
3269 {
3270 inst.error = _("immediate value out of range");
3271 return;
3272 }
3273
3274 /* Top 12 of 16 bits to bits 19:8. */
3275 inst.instruction |= (number & 0xfff0) << 4;
3276
3277 /* Bottom 4 of 16 bits to bits 3:0. */
3278 inst.instruction |= number & 0xf;
3279
3280 end_of_line (str);
3281
3282 if (flags)
3283 inst.error = BAD_FLAGS;
3284 }
3285
3286 /* Xscale multiply-accumulate (argument parse)
3287 MIAcc acc0,Rm,Rs
3288 MIAPHcc acc0,Rm,Rs
3289 MIAxycc acc0,Rm,Rs. */
3290
3291 static void
3292 do_mia (str, flags)
3293 char * str;
3294 unsigned long flags;
3295 {
3296 int rs;
3297 int rm;
3298
3299 if (flags)
3300 as_bad (BAD_FLAGS);
3301
3302 else if (accum0_required_here (& str) == FAIL)
3303 inst.error = ERR_NO_ACCUM;
3304
3305 else if (skip_past_comma (& str) == FAIL
3306 || (rm = reg_required_here (& str, 0)) == FAIL)
3307 inst.error = BAD_ARGS;
3308
3309 else if (skip_past_comma (& str) == FAIL
3310 || (rs = reg_required_here (& str, 12)) == FAIL)
3311 inst.error = BAD_ARGS;
3312
3313 /* inst.instruction has now been zapped with both rm and rs. */
3314 else if (rm == REG_PC || rs == REG_PC)
3315 inst.error = BAD_PC; /* Undefined result if rm or rs is R15. */
3316
3317 else
3318 end_of_line (str);
3319 }
3320
3321 /* Xscale move-accumulator-register (argument parse)
3322
3323 MARcc acc0,RdLo,RdHi. */
3324
3325 static void
3326 do_mar (str, flags)
3327 char * str;
3328 unsigned long flags;
3329 {
3330 int rdlo, rdhi;
3331
3332 if (flags)
3333 as_bad (BAD_FLAGS);
3334
3335 else if (accum0_required_here (& str) == FAIL)
3336 inst.error = ERR_NO_ACCUM;
3337
3338 else if (skip_past_comma (& str) == FAIL
3339 || (rdlo = reg_required_here (& str, 12)) == FAIL)
3340 inst.error = BAD_ARGS;
3341
3342 else if (skip_past_comma (& str) == FAIL
3343 || (rdhi = reg_required_here (& str, 16)) == FAIL)
3344 inst.error = BAD_ARGS;
3345
3346 /* inst.instruction has now been zapped with both rdlo and rdhi. */
3347 else if (rdlo == REG_PC || rdhi == REG_PC)
3348 inst.error = BAD_PC; /* Undefined result if rdlo or rdhi is R15. */
3349
3350 else
3351 end_of_line (str);
3352 }
3353
3354 /* Xscale move-register-accumulator (argument parse)
3355
3356 MRAcc RdLo,RdHi,acc0. */
3357
3358 static void
3359 do_mra (str, flags)
3360 char * str;
3361 unsigned long flags;
3362 {
3363 int rdlo;
3364 int rdhi;
3365
3366 if (flags)
3367 {
3368 as_bad (BAD_FLAGS);
3369 return;
3370 }
3371
3372 skip_whitespace (str);
3373
3374 if ((rdlo = reg_required_here (& str, 12)) == FAIL)
3375 inst.error = BAD_ARGS;
3376
3377 else if (skip_past_comma (& str) == FAIL
3378 || (rdhi = reg_required_here (& str, 16)) == FAIL)
3379 inst.error = BAD_ARGS;
3380
3381 else if (skip_past_comma (& str) == FAIL
3382 || accum0_required_here (& str) == FAIL)
3383 inst.error = ERR_NO_ACCUM;
3384
3385 /* inst.instruction has now been zapped with both rdlo and rdhi. */
3386 else if (rdlo == rdhi)
3387 inst.error = BAD_ARGS; /* Undefined result if 2 writes to same reg. */
3388
3389 else if (rdlo == REG_PC || rdhi == REG_PC)
3390 inst.error = BAD_PC; /* Undefined result if rdlo or rdhi is R15. */
3391 else
3392 end_of_line (str);
3393 }
3394
3395 /* Xscale: Preload-Cache
3396
3397 PLD <addr_mode>
3398
3399 Syntactically, like LDR with B=1, W=0, L=1. */
3400
3401 static void
3402 do_pld (str, flags)
3403 char * str;
3404 unsigned long flags;
3405 {
3406 int rd;
3407
3408 if (flags)
3409 {
3410 as_bad (BAD_FLAGS);
3411 return;
3412 }
3413
3414 skip_whitespace (str);
3415
3416 if (* str != '[')
3417 {
3418 inst.error = _("'[' expected after PLD mnemonic");
3419 return;
3420 }
3421
3422 ++ str;
3423 skip_whitespace (str);
3424
3425 if ((rd = reg_required_here (& str, 16)) == FAIL)
3426 return;
3427
3428 skip_whitespace (str);
3429
3430 if (* str == ']')
3431 {
3432 /* [Rn], ... ? */
3433 ++ str;
3434 skip_whitespace (str);
3435
3436 if (skip_past_comma (& str) == SUCCESS)
3437 {
3438 if (ldst_extend (& str, 0) == FAIL)
3439 return;
3440 }
3441 else if (* str == '!') /* [Rn]! */
3442 {
3443 inst.error = _("writeback used in preload instruction");
3444 ++ str;
3445 }
3446 else /* [Rn] */
3447 inst.instruction |= INDEX_UP | PRE_INDEX;
3448 }
3449 else /* [Rn, ...] */
3450 {
3451 if (skip_past_comma (& str) == FAIL)
3452 {
3453 inst.error = _("pre-indexed expression expected");
3454 return;
3455 }
3456
3457 if (ldst_extend (& str, 0) == FAIL)
3458 return;
3459
3460 skip_whitespace (str);
3461
3462 if (* str != ']')
3463 {
3464 inst.error = _("missing ]");
3465 return;
3466 }
3467
3468 ++ str;
3469 skip_whitespace (str);
3470
3471 if (* str == '!') /* [Rn]! */
3472 {
3473 inst.error = _("writeback used in preload instruction");
3474 ++ str;
3475 }
3476
3477 inst.instruction |= PRE_INDEX;
3478 }
3479
3480 end_of_line (str);
3481 }
3482
3483 /* Xscale load-consecutive (argument parse)
3484 Mode is like LDRH.
3485
3486 LDRccD R, mode
3487 STRccD R, mode. */
3488
3489 static void
3490 do_ldrd (str, flags)
3491 char * str;
3492 unsigned long flags;
3493 {
3494 int rd;
3495 int rn;
3496
3497 if (flags != DOUBLE_LOAD_FLAG)
3498 {
3499 /* Change instruction pattern to normal ldr/str. */
3500 if (inst.instruction & 0x20)
3501 inst.instruction = (inst.instruction & COND_MASK) | 0x04000000; /* str */
3502 else
3503 inst.instruction = (inst.instruction & COND_MASK) | 0x04100000; /* ldr */
3504
3505 /* Perform a normal load/store instruction parse. */
3506 do_ldst (str, flags);
3507
3508 return;
3509 }
3510
3511 if ((cpu_variant & ARM_EXT_XSCALE) != ARM_EXT_XSCALE)
3512 {
3513 static char buff[128];
3514
3515 --str;
3516 while (isspace (*str))
3517 --str;
3518 str -= 4;
3519
3520 /* Deny all knowledge. */
3521 sprintf (buff, _("bad instruction '%.100s'"), str);
3522 inst.error = buff;
3523 return;
3524 }
3525
3526 skip_whitespace (str);
3527
3528 if ((rd = reg_required_here (& str, 12)) == FAIL)
3529 {
3530 inst.error = BAD_ARGS;
3531 return;
3532 }
3533
3534 if (skip_past_comma (& str) == FAIL
3535 || (rn = ld_mode_required_here (& str)) == FAIL)
3536 {
3537 if (!inst.error)
3538 inst.error = BAD_ARGS;
3539 return;
3540 }
3541
3542 /* inst.instruction has now been zapped with Rd and the addressing mode. */
3543 if (rd & 1) /* Unpredictable result if Rd is odd. */
3544 {
3545 inst.error = _("Destination register must be even");
3546 return;
3547 }
3548
3549 if (rd == REG_LR || rd == 12)
3550 {
3551 inst.error = _("r12 or r14 not allowed here");
3552 return;
3553 }
3554
3555 if (((rd == rn) || (rd + 1 == rn))
3556 &&
3557 ((inst.instruction & WRITE_BACK)
3558 || (!(inst.instruction & PRE_INDEX))))
3559 as_warn (_("pre/post-indexing used when modified address register is destination"));
3560
3561 end_of_line (str);
3562 }
3563
3564 /* Returns the index into fp_values of a floating point number,
3565 or -1 if not in the table. */
3566
3567 static int
3568 my_get_float_expression (str)
3569 char ** str;
3570 {
3571 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3572 char * save_in;
3573 expressionS exp;
3574 int i;
3575 int j;
3576
3577 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
3578
3579 /* Look for a raw floating point number. */
3580 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
3581 && is_end_of_line[(unsigned char) *save_in])
3582 {
3583 for (i = 0; i < NUM_FLOAT_VALS; i++)
3584 {
3585 for (j = 0; j < MAX_LITTLENUMS; j++)
3586 {
3587 if (words[j] != fp_values[i][j])
3588 break;
3589 }
3590
3591 if (j == MAX_LITTLENUMS)
3592 {
3593 *str = save_in;
3594 return i;
3595 }
3596 }
3597 }
3598
3599 /* Try and parse a more complex expression, this will probably fail
3600 unless the code uses a floating point prefix (eg "0f"). */
3601 save_in = input_line_pointer;
3602 input_line_pointer = *str;
3603 if (expression (&exp) == absolute_section
3604 && exp.X_op == O_big
3605 && exp.X_add_number < 0)
3606 {
3607 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
3608 Ditto for 15. */
3609 if (gen_to_words (words, 5, (long) 15) == 0)
3610 {
3611 for (i = 0; i < NUM_FLOAT_VALS; i++)
3612 {
3613 for (j = 0; j < MAX_LITTLENUMS; j++)
3614 {
3615 if (words[j] != fp_values[i][j])
3616 break;
3617 }
3618
3619 if (j == MAX_LITTLENUMS)
3620 {
3621 *str = input_line_pointer;
3622 input_line_pointer = save_in;
3623 return i;
3624 }
3625 }
3626 }
3627 }
3628
3629 *str = input_line_pointer;
3630 input_line_pointer = save_in;
3631 return -1;
3632 }
3633
3634 /* Return true if anything in the expression is a bignum. */
3635
3636 static int
3637 walk_no_bignums (sp)
3638 symbolS * sp;
3639 {
3640 if (symbol_get_value_expression (sp)->X_op == O_big)
3641 return 1;
3642
3643 if (symbol_get_value_expression (sp)->X_add_symbol)
3644 {
3645 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
3646 || (symbol_get_value_expression (sp)->X_op_symbol
3647 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
3648 }
3649
3650 return 0;
3651 }
3652
3653 static int
3654 my_get_expression (ep, str)
3655 expressionS * ep;
3656 char ** str;
3657 {
3658 char * save_in;
3659 segT seg;
3660
3661 save_in = input_line_pointer;
3662 input_line_pointer = *str;
3663 seg = expression (ep);
3664
3665 #ifdef OBJ_AOUT
3666 if (seg != absolute_section
3667 && seg != text_section
3668 && seg != data_section
3669 && seg != bss_section
3670 && seg != undefined_section)
3671 {
3672 inst.error = _("bad_segment");
3673 *str = input_line_pointer;
3674 input_line_pointer = save_in;
3675 return 1;
3676 }
3677 #endif
3678
3679 /* Get rid of any bignums now, so that we don't generate an error for which
3680 we can't establish a line number later on. Big numbers are never valid
3681 in instructions, which is where this routine is always called. */
3682 if (ep->X_op == O_big
3683 || (ep->X_add_symbol
3684 && (walk_no_bignums (ep->X_add_symbol)
3685 || (ep->X_op_symbol
3686 && walk_no_bignums (ep->X_op_symbol)))))
3687 {
3688 inst.error = _("Invalid constant");
3689 *str = input_line_pointer;
3690 input_line_pointer = save_in;
3691 return 1;
3692 }
3693
3694 *str = input_line_pointer;
3695 input_line_pointer = save_in;
3696 return 0;
3697 }
3698
3699 /* UNRESTRICT should be one if <shift> <register> is permitted for this
3700 instruction. */
3701
3702 static int
3703 decode_shift (str, unrestrict)
3704 char ** str;
3705 int unrestrict;
3706 {
3707 const struct asm_shift_name * shift;
3708 char * p;
3709 char c;
3710
3711 skip_whitespace (* str);
3712
3713 for (p = * str; isalpha (* p); p ++)
3714 ;
3715
3716 if (p == * str)
3717 {
3718 inst.error = _("Shift expression expected");
3719 return FAIL;
3720 }
3721
3722 c = * p;
3723 * p = '\0';
3724 shift = (const struct asm_shift_name *) hash_find (arm_shift_hsh, * str);
3725 * p = c;
3726
3727 if (shift == NULL)
3728 {
3729 inst.error = _("Shift expression expected");
3730 return FAIL;
3731 }
3732
3733 assert (shift->properties->index == shift_properties[shift->properties->index].index);
3734
3735 if (shift->properties->index == SHIFT_RRX)
3736 {
3737 * str = p;
3738 inst.instruction |= shift->properties->bit_field;
3739 return SUCCESS;
3740 }
3741
3742 skip_whitespace (p);
3743
3744 if (unrestrict && reg_required_here (& p, 8) != FAIL)
3745 {
3746 inst.instruction |= shift->properties->bit_field | SHIFT_BY_REG;
3747 * str = p;
3748 return SUCCESS;
3749 }
3750 else if (! is_immediate_prefix (* p))
3751 {
3752 inst.error = (unrestrict
3753 ? _("shift requires register or #expression")
3754 : _("shift requires #expression"));
3755 * str = p;
3756 return FAIL;
3757 }
3758
3759 inst.error = NULL;
3760 p ++;
3761
3762 if (my_get_expression (& inst.reloc.exp, & p))
3763 return FAIL;
3764
3765 /* Validate some simple #expressions. */
3766 if (inst.reloc.exp.X_op == O_constant)
3767 {
3768 unsigned num = inst.reloc.exp.X_add_number;
3769
3770 /* Reject operations greater than 32. */
3771 if (num > 32
3772 /* Reject a shift of 0 unless the mode allows it. */
3773 || (num == 0 && shift->properties->allows_0 == 0)
3774 /* Reject a shift of 32 unless the mode allows it. */
3775 || (num == 32 && shift->properties->allows_32 == 0)
3776 )
3777 {
3778 /* As a special case we allow a shift of zero for
3779 modes that do not support it to be recoded as an
3780 logical shift left of zero (ie nothing). We warn
3781 about this though. */
3782 if (num == 0)
3783 {
3784 as_warn (_("Shift of 0 ignored."));
3785 shift = & shift_names[0];
3786 assert (shift->properties->index == SHIFT_LSL);
3787 }
3788 else
3789 {
3790 inst.error = _("Invalid immediate shift");
3791 return FAIL;
3792 }
3793 }
3794
3795 /* Shifts of 32 are encoded as 0, for those shifts that
3796 support it. */
3797 if (num == 32)
3798 num = 0;
3799
3800 inst.instruction |= (num << 7) | shift->properties->bit_field;
3801 }
3802 else
3803 {
3804 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
3805 inst.reloc.pc_rel = 0;
3806 inst.instruction |= shift->properties->bit_field;
3807 }
3808
3809 * str = p;
3810 return SUCCESS;
3811 }
3812
3813 /* Do those data_ops which can take a negative immediate constant
3814 by altering the instuction. A bit of a hack really.
3815 MOV <-> MVN
3816 AND <-> BIC
3817 ADC <-> SBC
3818 by inverting the second operand, and
3819 ADD <-> SUB
3820 CMP <-> CMN
3821 by negating the second operand. */
3822
3823 static int
3824 negate_data_op (instruction, value)
3825 unsigned long * instruction;
3826 unsigned long value;
3827 {
3828 int op, new_inst;
3829 unsigned long negated, inverted;
3830
3831 negated = validate_immediate (-value);
3832 inverted = validate_immediate (~value);
3833
3834 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
3835 switch (op)
3836 {
3837 /* First negates. */
3838 case OPCODE_SUB: /* ADD <-> SUB */
3839 new_inst = OPCODE_ADD;
3840 value = negated;
3841 break;
3842
3843 case OPCODE_ADD:
3844 new_inst = OPCODE_SUB;
3845 value = negated;
3846 break;
3847
3848 case OPCODE_CMP: /* CMP <-> CMN */
3849 new_inst = OPCODE_CMN;
3850 value = negated;
3851 break;
3852
3853 case OPCODE_CMN:
3854 new_inst = OPCODE_CMP;
3855 value = negated;
3856 break;
3857
3858 /* Now Inverted ops. */
3859 case OPCODE_MOV: /* MOV <-> MVN */
3860 new_inst = OPCODE_MVN;
3861 value = inverted;
3862 break;
3863
3864 case OPCODE_MVN:
3865 new_inst = OPCODE_MOV;
3866 value = inverted;
3867 break;
3868
3869 case OPCODE_AND: /* AND <-> BIC */
3870 new_inst = OPCODE_BIC;
3871 value = inverted;
3872 break;
3873
3874 case OPCODE_BIC:
3875 new_inst = OPCODE_AND;
3876 value = inverted;
3877 break;
3878
3879 case OPCODE_ADC: /* ADC <-> SBC */
3880 new_inst = OPCODE_SBC;
3881 value = inverted;
3882 break;
3883
3884 case OPCODE_SBC:
3885 new_inst = OPCODE_ADC;
3886 value = inverted;
3887 break;
3888
3889 /* We cannot do anything. */
3890 default:
3891 return FAIL;
3892 }
3893
3894 if (value == (unsigned) FAIL)
3895 return FAIL;
3896
3897 *instruction &= OPCODE_MASK;
3898 *instruction |= new_inst << DATA_OP_SHIFT;
3899 return value;
3900 }
3901
3902 static int
3903 data_op2 (str)
3904 char ** str;
3905 {
3906 int value;
3907 expressionS expr;
3908
3909 skip_whitespace (* str);
3910
3911 if (reg_required_here (str, 0) != FAIL)
3912 {
3913 if (skip_past_comma (str) == SUCCESS)
3914 /* Shift operation on register. */
3915 return decode_shift (str, NO_SHIFT_RESTRICT);
3916
3917 return SUCCESS;
3918 }
3919 else
3920 {
3921 /* Immediate expression. */
3922 if (is_immediate_prefix (**str))
3923 {
3924 (*str)++;
3925 inst.error = NULL;
3926
3927 if (my_get_expression (&inst.reloc.exp, str))
3928 return FAIL;
3929
3930 if (inst.reloc.exp.X_add_symbol)
3931 {
3932 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
3933 inst.reloc.pc_rel = 0;
3934 }
3935 else
3936 {
3937 if (skip_past_comma (str) == SUCCESS)
3938 {
3939 /* #x, y -- ie explicit rotation by Y. */
3940 if (my_get_expression (&expr, str))
3941 return FAIL;
3942
3943 if (expr.X_op != O_constant)
3944 {
3945 inst.error = _("Constant expression expected");
3946 return FAIL;
3947 }
3948
3949 /* Rotate must be a multiple of 2. */
3950 if (((unsigned) expr.X_add_number) > 30
3951 || (expr.X_add_number & 1) != 0
3952 || ((unsigned) inst.reloc.exp.X_add_number) > 255)
3953 {
3954 inst.error = _("Invalid constant");
3955 return FAIL;
3956 }
3957 inst.instruction |= INST_IMMEDIATE;
3958 inst.instruction |= inst.reloc.exp.X_add_number;
3959 inst.instruction |= expr.X_add_number << 7;
3960 return SUCCESS;
3961 }
3962
3963 /* Implicit rotation, select a suitable one. */
3964 value = validate_immediate (inst.reloc.exp.X_add_number);
3965
3966 if (value == FAIL)
3967 {
3968 /* Can't be done. Perhaps the code reads something like
3969 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be OK. */
3970 if ((value = negate_data_op (&inst.instruction,
3971 inst.reloc.exp.X_add_number))
3972 == FAIL)
3973 {
3974 inst.error = _("Invalid constant");
3975 return FAIL;
3976 }
3977 }
3978
3979 inst.instruction |= value;
3980 }
3981
3982 inst.instruction |= INST_IMMEDIATE;
3983 return SUCCESS;
3984 }
3985
3986 (*str)++;
3987 inst.error = _("Register or shift expression expected");
3988 return FAIL;
3989 }
3990 }
3991
3992 static int
3993 fp_op2 (str)
3994 char ** str;
3995 {
3996 skip_whitespace (* str);
3997
3998 if (fp_reg_required_here (str, 0) != FAIL)
3999 return SUCCESS;
4000 else
4001 {
4002 /* Immediate expression. */
4003 if (*((*str)++) == '#')
4004 {
4005 int i;
4006
4007 inst.error = NULL;
4008
4009 skip_whitespace (* str);
4010
4011 /* First try and match exact strings, this is to guarantee
4012 that some formats will work even for cross assembly. */
4013
4014 for (i = 0; fp_const[i]; i++)
4015 {
4016 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4017 {
4018 char *start = *str;
4019
4020 *str += strlen (fp_const[i]);
4021 if (is_end_of_line[(unsigned char) **str])
4022 {
4023 inst.instruction |= i + 8;
4024 return SUCCESS;
4025 }
4026 *str = start;
4027 }
4028 }
4029
4030 /* Just because we didn't get a match doesn't mean that the
4031 constant isn't valid, just that it is in a format that we
4032 don't automatically recognize. Try parsing it with
4033 the standard expression routines. */
4034 if ((i = my_get_float_expression (str)) >= 0)
4035 {
4036 inst.instruction |= i + 8;
4037 return SUCCESS;
4038 }
4039
4040 inst.error = _("Invalid floating point immediate expression");
4041 return FAIL;
4042 }
4043 inst.error =
4044 _("Floating point register or immediate expression expected");
4045 return FAIL;
4046 }
4047 }
4048
4049 static void
4050 do_arit (str, flags)
4051 char * str;
4052 unsigned long flags;
4053 {
4054 skip_whitespace (str);
4055
4056 if (reg_required_here (&str, 12) == FAIL
4057 || skip_past_comma (&str) == FAIL
4058 || reg_required_here (&str, 16) == FAIL
4059 || skip_past_comma (&str) == FAIL
4060 || data_op2 (&str) == FAIL)
4061 {
4062 if (!inst.error)
4063 inst.error = BAD_ARGS;
4064 return;
4065 }
4066
4067 inst.instruction |= flags;
4068 end_of_line (str);
4069 return;
4070 }
4071
4072 static void
4073 do_adr (str, flags)
4074 char * str;
4075 unsigned long flags;
4076 {
4077 skip_whitespace (str);
4078
4079 if (reg_required_here (&str, 12) == FAIL
4080 || skip_past_comma (&str) == FAIL
4081 || my_get_expression (&inst.reloc.exp, &str))
4082 {
4083 if (!inst.error)
4084 inst.error = BAD_ARGS;
4085 return;
4086 }
4087
4088 if (flags & 0x00400000)
4089 {
4090 /* This is a pseudo-op of the form "adrl rd, label" to be converted
4091 into a relative address of the form:
4092 add rd, pc, #low(label-.-8)"
4093 add rd, rd, #high(label-.-8)" */
4094 /* Frag hacking will turn this into a sub instruction if the offset turns
4095 out to be negative. */
4096 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
4097 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
4098 inst.reloc.pc_rel = 1;
4099 inst.instruction |= flags & ~0x00400000;
4100 inst.size = INSN_SIZE * 2;
4101 }
4102 else
4103 {
4104 /* This is a pseudo-op of the form "adr rd, label" to be converted
4105 into a relative address of the form "add rd, pc, #label-.-8". */
4106 /* Frag hacking will turn this into a sub instruction if the offset turns
4107 out to be negative. */
4108 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4109 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */
4110 inst.reloc.pc_rel = 1;
4111 inst.instruction |= flags;
4112 }
4113
4114 end_of_line (str);
4115 }
4116
4117 static void
4118 do_cmp (str, flags)
4119 char * str;
4120 unsigned long flags;
4121 {
4122 skip_whitespace (str);
4123
4124 if (reg_required_here (&str, 16) == FAIL)
4125 {
4126 if (!inst.error)
4127 inst.error = BAD_ARGS;
4128 return;
4129 }
4130
4131 if (skip_past_comma (&str) == FAIL
4132 || data_op2 (&str) == FAIL)
4133 {
4134 if (!inst.error)
4135 inst.error = BAD_ARGS;
4136 return;
4137 }
4138
4139 inst.instruction |= flags;
4140 if ((flags & 0x0000f000) == 0)
4141 inst.instruction |= CONDS_BIT;
4142
4143 end_of_line (str);
4144 return;
4145 }
4146
4147 static void
4148 do_mov (str, flags)
4149 char * str;
4150 unsigned long flags;
4151 {
4152 skip_whitespace (str);
4153
4154 if (reg_required_here (&str, 12) == FAIL)
4155 {
4156 if (!inst.error)
4157 inst.error = BAD_ARGS;
4158 return;
4159 }
4160
4161 if (skip_past_comma (&str) == FAIL
4162 || data_op2 (&str) == FAIL)
4163 {
4164 if (!inst.error)
4165 inst.error = BAD_ARGS;
4166 return;
4167 }
4168
4169 inst.instruction |= flags;
4170 end_of_line (str);
4171 return;
4172 }
4173
4174 static int
4175 ldst_extend (str, hwse)
4176 char ** str;
4177 int hwse;
4178 {
4179 int add = INDEX_UP;
4180
4181 switch (**str)
4182 {
4183 case '#':
4184 case '$':
4185 (*str)++;
4186 if (my_get_expression (& inst.reloc.exp, str))
4187 return FAIL;
4188
4189 if (inst.reloc.exp.X_op == O_constant)
4190 {
4191 int value = inst.reloc.exp.X_add_number;
4192
4193 if ((hwse && (value < -255 || value > 255))
4194 || (value < -4095 || value > 4095))
4195 {
4196 inst.error = _("address offset too large");
4197 return FAIL;
4198 }
4199
4200 if (value < 0)
4201 {
4202 value = -value;
4203 add = 0;
4204 }
4205
4206 /* Halfword and signextension instructions have the
4207 immediate value split across bits 11..8 and bits 3..0. */
4208 if (hwse)
4209 inst.instruction |= (add | HWOFFSET_IMM
4210 | ((value >> 4) << 8) | (value & 0xF));
4211 else
4212 inst.instruction |= add | value;
4213 }
4214 else
4215 {
4216 if (hwse)
4217 {
4218 inst.instruction |= HWOFFSET_IMM;
4219 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
4220 }
4221 else
4222 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
4223 inst.reloc.pc_rel = 0;
4224 }
4225 return SUCCESS;
4226
4227 case '-':
4228 add = 0;
4229 /* Fall through. */
4230
4231 case '+':
4232 (*str)++;
4233 /* Fall through. */
4234
4235 default:
4236 if (reg_required_here (str, 0) == FAIL)
4237 return FAIL;
4238
4239 if (hwse)
4240 inst.instruction |= add;
4241 else
4242 {
4243 inst.instruction |= add | OFFSET_REG;
4244 if (skip_past_comma (str) == SUCCESS)
4245 return decode_shift (str, SHIFT_RESTRICT);
4246 }
4247
4248 return SUCCESS;
4249 }
4250 }
4251
4252 static void
4253 do_ldst (str, flags)
4254 char * str;
4255 unsigned long flags;
4256 {
4257 int halfword = 0;
4258 int pre_inc = 0;
4259 int conflict_reg;
4260 int value;
4261
4262 /* This is not ideal, but it is the simplest way of dealing with the
4263 ARM7T halfword instructions (since they use a different
4264 encoding, but the same mnemonic): */
4265 halfword = (flags & 0x80000000) != 0;
4266 if (halfword)
4267 {
4268 /* This is actually a load/store of a halfword, or a
4269 signed-extension load. */
4270 if ((cpu_variant & ARM_EXT_HALFWORD) == 0)
4271 {
4272 inst.error
4273 = _("Processor does not support halfwords or signed bytes");
4274 return;
4275 }
4276
4277 inst.instruction = ((inst.instruction & COND_MASK)
4278 | (flags & ~COND_MASK));
4279
4280 flags = 0;
4281 }
4282
4283 skip_whitespace (str);
4284
4285 if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
4286 {
4287 if (!inst.error)
4288 inst.error = BAD_ARGS;
4289 return;
4290 }
4291
4292 if (skip_past_comma (& str) == FAIL)
4293 {
4294 inst.error = _("Address expected");
4295 return;
4296 }
4297
4298 if (*str == '[')
4299 {
4300 int reg;
4301
4302 str++;
4303
4304 skip_whitespace (str);
4305
4306 if ((reg = reg_required_here (&str, 16)) == FAIL)
4307 return;
4308
4309 /* Conflicts can occur on stores as well as loads. */
4310 conflict_reg = (conflict_reg == reg);
4311
4312 skip_whitespace (str);
4313
4314 if (*str == ']')
4315 {
4316 str ++;
4317
4318 if (skip_past_comma (&str) == SUCCESS)
4319 {
4320 /* [Rn],... (post inc) */
4321 if (ldst_extend (&str, halfword) == FAIL)
4322 return;
4323 if (conflict_reg)
4324 {
4325 if (flags & TRANS_BIT)
4326 as_warn (_("Rn and Rd must be different in %s"),
4327 ((inst.instruction & LOAD_BIT)
4328 ? "LDRT" : "STRT"));
4329 else
4330 as_warn (_("%s register same as write-back base"),
4331 ((inst.instruction & LOAD_BIT)
4332 ? _("destination") : _("source")));
4333 }
4334 }
4335 else
4336 {
4337 /* [Rn] */
4338 if (halfword)
4339 inst.instruction |= HWOFFSET_IMM;
4340
4341 skip_whitespace (str);
4342
4343 if (*str == '!')
4344 {
4345 if (conflict_reg)
4346 as_warn (_("%s register same as write-back base"),
4347 ((inst.instruction & LOAD_BIT)
4348 ? _("destination") : _("source")));
4349 str++;
4350 inst.instruction |= WRITE_BACK;
4351 }
4352
4353 flags |= INDEX_UP;
4354 if (flags & TRANS_BIT)
4355 {
4356 if (conflict_reg)
4357 as_warn (_("Rn and Rd must be different in %s"),
4358 ((inst.instruction & LOAD_BIT)
4359 ? "LDRT" : "STRT"));
4360 }
4361 else
4362 pre_inc = 1;
4363 }
4364 }
4365 else
4366 {
4367 /* [Rn,...] */
4368 if (skip_past_comma (&str) == FAIL)
4369 {
4370 inst.error = _("pre-indexed expression expected");
4371 return;
4372 }
4373
4374 pre_inc = 1;
4375 if (ldst_extend (&str, halfword) == FAIL)
4376 return;
4377
4378 skip_whitespace (str);
4379
4380 if (*str++ != ']')
4381 {
4382 inst.error = _("missing ]");
4383 return;
4384 }
4385
4386 skip_whitespace (str);
4387
4388 if (*str == '!')
4389 {
4390 if (conflict_reg)
4391 as_warn (_("%s register same as write-back base"),
4392 ((inst.instruction & LOAD_BIT)
4393 ? _("destination") : _("source")));
4394 str++;
4395 inst.instruction |= WRITE_BACK;
4396 }
4397 }
4398 }
4399 else if (*str == '=')
4400 {
4401 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
4402 str++;
4403
4404 skip_whitespace (str);
4405
4406 if (my_get_expression (&inst.reloc.exp, &str))
4407 return;
4408
4409 if (inst.reloc.exp.X_op != O_constant
4410 && inst.reloc.exp.X_op != O_symbol)
4411 {
4412 inst.error = _("Constant expression expected");
4413 return;
4414 }
4415
4416 if (inst.reloc.exp.X_op == O_constant)
4417 {
4418 value = validate_immediate (inst.reloc.exp.X_add_number);
4419
4420 if (value != FAIL)
4421 {
4422 /* This can be done with a mov instruction. */
4423 inst.instruction &= LITERAL_MASK;
4424 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
4425 inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
4426 end_of_line (str);
4427 return;
4428 }
4429
4430 value = validate_immediate (~ inst.reloc.exp.X_add_number);
4431
4432 if (value != FAIL)
4433 {
4434 /* This can be done with a mvn instruction. */
4435 inst.instruction &= LITERAL_MASK;
4436 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
4437 inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
4438 end_of_line (str);
4439 return;
4440 }
4441 }
4442
4443 /* Insert into literal pool. */
4444 if (add_to_lit_pool () == FAIL)
4445 {
4446 if (!inst.error)
4447 inst.error = _("literal pool insertion failed");
4448 return;
4449 }
4450
4451 /* Change the instruction exp to point to the pool. */
4452 if (halfword)
4453 {
4454 inst.instruction |= HWOFFSET_IMM;
4455 inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
4456 }
4457 else
4458 inst.reloc.type = BFD_RELOC_ARM_LITERAL;
4459
4460 inst.reloc.pc_rel = 1;
4461 inst.instruction |= (REG_PC << 16);
4462 pre_inc = 1;
4463 }
4464 else
4465 {
4466 if (my_get_expression (&inst.reloc.exp, &str))
4467 return;
4468
4469 if (halfword)
4470 {
4471 inst.instruction |= HWOFFSET_IMM;
4472 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
4473 }
4474 else
4475 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
4476 #ifndef TE_WINCE
4477 /* PC rel adjust. */
4478 inst.reloc.exp.X_add_number -= 8;
4479 #endif
4480 inst.reloc.pc_rel = 1;
4481 inst.instruction |= (REG_PC << 16);
4482 pre_inc = 1;
4483 }
4484
4485 if (pre_inc && (flags & TRANS_BIT))
4486 inst.error = _("Pre-increment instruction with translate");
4487
4488 inst.instruction |= flags | (pre_inc ? PRE_INDEX : 0);
4489 end_of_line (str);
4490 return;
4491 }
4492
4493 static long
4494 reg_list (strp)
4495 char ** strp;
4496 {
4497 char * str = * strp;
4498 long range = 0;
4499 int another_range;
4500
4501 /* We come back here if we get ranges concatenated by '+' or '|'. */
4502 do
4503 {
4504 another_range = 0;
4505
4506 if (*str == '{')
4507 {
4508 int in_range = 0;
4509 int cur_reg = -1;
4510
4511 str++;
4512 do
4513 {
4514 int reg;
4515
4516 skip_whitespace (str);
4517
4518 if ((reg = reg_required_here (& str, -1)) == FAIL)
4519 return FAIL;
4520
4521 if (in_range)
4522 {
4523 int i;
4524
4525 if (reg <= cur_reg)
4526 {
4527 inst.error = _("Bad range in register list");
4528 return FAIL;
4529 }
4530
4531 for (i = cur_reg + 1; i < reg; i++)
4532 {
4533 if (range & (1 << i))
4534 as_tsktsk
4535 (_("Warning: Duplicated register (r%d) in register list"),
4536 i);
4537 else
4538 range |= 1 << i;
4539 }
4540 in_range = 0;
4541 }
4542
4543 if (range & (1 << reg))
4544 as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
4545 reg);
4546 else if (reg <= cur_reg)
4547 as_tsktsk (_("Warning: Register range not in ascending order"));
4548
4549 range |= 1 << reg;
4550 cur_reg = reg;
4551 }
4552 while (skip_past_comma (&str) != FAIL
4553 || (in_range = 1, *str++ == '-'));
4554 str--;
4555 skip_whitespace (str);
4556
4557 if (*str++ != '}')
4558 {
4559 inst.error = _("Missing `}'");
4560 return FAIL;
4561 }
4562 }
4563 else
4564 {
4565 expressionS expr;
4566
4567 if (my_get_expression (&expr, &str))
4568 return FAIL;
4569
4570 if (expr.X_op == O_constant)
4571 {
4572 if (expr.X_add_number
4573 != (expr.X_add_number & 0x0000ffff))
4574 {
4575 inst.error = _("invalid register mask");
4576 return FAIL;
4577 }
4578
4579 if ((range & expr.X_add_number) != 0)
4580 {
4581 int regno = range & expr.X_add_number;
4582
4583 regno &= -regno;
4584 regno = (1 << regno) - 1;
4585 as_tsktsk
4586 (_("Warning: Duplicated register (r%d) in register list"),
4587 regno);
4588 }
4589
4590 range |= expr.X_add_number;
4591 }
4592 else
4593 {
4594 if (inst.reloc.type != 0)
4595 {
4596 inst.error = _("expression too complex");
4597 return FAIL;
4598 }
4599
4600 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
4601 inst.reloc.type = BFD_RELOC_ARM_MULTI;
4602 inst.reloc.pc_rel = 0;
4603 }
4604 }
4605
4606 skip_whitespace (str);
4607
4608 if (*str == '|' || *str == '+')
4609 {
4610 str++;
4611 another_range = 1;
4612 }
4613 }
4614 while (another_range);
4615
4616 *strp = str;
4617 return range;
4618 }
4619
4620 static void
4621 do_ldmstm (str, flags)
4622 char * str;
4623 unsigned long flags;
4624 {
4625 int base_reg;
4626 long range;
4627
4628 skip_whitespace (str);
4629
4630 if ((base_reg = reg_required_here (&str, 16)) == FAIL)
4631 return;
4632
4633 if (base_reg == REG_PC)
4634 {
4635 inst.error = _("r15 not allowed as base register");
4636 return;
4637 }
4638
4639 skip_whitespace (str);
4640
4641 if (*str == '!')
4642 {
4643 flags |= WRITE_BACK;
4644 str++;
4645 }
4646
4647 if (skip_past_comma (&str) == FAIL
4648 || (range = reg_list (&str)) == FAIL)
4649 {
4650 if (! inst.error)
4651 inst.error = BAD_ARGS;
4652 return;
4653 }
4654
4655 if (*str == '^')
4656 {
4657 str++;
4658 flags |= LDM_TYPE_2_OR_3;
4659 }
4660
4661 inst.instruction |= flags | range;
4662 end_of_line (str);
4663 return;
4664 }
4665
4666 static void
4667 do_swi (str, flags)
4668 char * str;
4669 unsigned long flags;
4670 {
4671 skip_whitespace (str);
4672
4673 /* Allow optional leading '#'. */
4674 if (is_immediate_prefix (*str))
4675 str++;
4676
4677 if (my_get_expression (& inst.reloc.exp, & str))
4678 return;
4679
4680 inst.reloc.type = BFD_RELOC_ARM_SWI;
4681 inst.reloc.pc_rel = 0;
4682 inst.instruction |= flags;
4683
4684 end_of_line (str);
4685
4686 return;
4687 }
4688
4689 static void
4690 do_swap (str, flags)
4691 char * str;
4692 unsigned long flags;
4693 {
4694 int reg;
4695
4696 skip_whitespace (str);
4697
4698 if ((reg = reg_required_here (&str, 12)) == FAIL)
4699 return;
4700
4701 if (reg == REG_PC)
4702 {
4703 inst.error = _("r15 not allowed in swap");
4704 return;
4705 }
4706
4707 if (skip_past_comma (&str) == FAIL
4708 || (reg = reg_required_here (&str, 0)) == FAIL)
4709 {
4710 if (!inst.error)
4711 inst.error = BAD_ARGS;
4712 return;
4713 }
4714
4715 if (reg == REG_PC)
4716 {
4717 inst.error = _("r15 not allowed in swap");
4718 return;
4719 }
4720
4721 if (skip_past_comma (&str) == FAIL
4722 || *str++ != '[')
4723 {
4724 inst.error = BAD_ARGS;
4725 return;
4726 }
4727
4728 skip_whitespace (str);
4729
4730 if ((reg = reg_required_here (&str, 16)) == FAIL)
4731 return;
4732
4733 if (reg == REG_PC)
4734 {
4735 inst.error = BAD_PC;
4736 return;
4737 }
4738
4739 skip_whitespace (str);
4740
4741 if (*str++ != ']')
4742 {
4743 inst.error = _("missing ]");
4744 return;
4745 }
4746
4747 inst.instruction |= flags;
4748 end_of_line (str);
4749 return;
4750 }
4751
4752 static void
4753 do_branch (str, flags)
4754 char * str;
4755 unsigned long flags ATTRIBUTE_UNUSED;
4756 {
4757 if (my_get_expression (&inst.reloc.exp, &str))
4758 return;
4759
4760 #ifdef OBJ_ELF
4761 {
4762 char * save_in;
4763
4764 /* ScottB: February 5, 1998 - Check to see of PLT32 reloc
4765 required for the instruction. */
4766
4767 /* arm_parse_reloc () works on input_line_pointer.
4768 We actually want to parse the operands to the branch instruction
4769 passed in 'str'. Save the input pointer and restore it later. */
4770 save_in = input_line_pointer;
4771 input_line_pointer = str;
4772 if (inst.reloc.exp.X_op == O_symbol
4773 && *str == '('
4774 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
4775 {
4776 inst.reloc.type = BFD_RELOC_ARM_PLT32;
4777 inst.reloc.pc_rel = 0;
4778 /* Modify str to point to after parsed operands, otherwise
4779 end_of_line() will complain about the (PLT) left in str. */
4780 str = input_line_pointer;
4781 }
4782 else
4783 {
4784 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
4785 inst.reloc.pc_rel = 1;
4786 }
4787 input_line_pointer = save_in;
4788 }
4789 #else
4790 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
4791 inst.reloc.pc_rel = 1;
4792 #endif /* OBJ_ELF */
4793
4794 end_of_line (str);
4795 return;
4796 }
4797
4798 static void
4799 do_bx (str, flags)
4800 char * str;
4801 unsigned long flags ATTRIBUTE_UNUSED;
4802 {
4803 int reg;
4804
4805 skip_whitespace (str);
4806
4807 if ((reg = reg_required_here (&str, 0)) == FAIL)
4808 {
4809 inst.error = BAD_ARGS;
4810 return;
4811 }
4812
4813 /* Note - it is not illegal to do a "bx pc". Useless, but not illegal. */
4814 if (reg == REG_PC)
4815 as_tsktsk (_("Use of r15 in bx in ARM mode is not really useful"));
4816
4817 end_of_line (str);
4818 }
4819
4820 static void
4821 do_cdp (str, flags)
4822 char * str;
4823 unsigned long flags ATTRIBUTE_UNUSED;
4824 {
4825 /* Co-processor data operation.
4826 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
4827 skip_whitespace (str);
4828
4829 if (co_proc_number (&str) == FAIL)
4830 {
4831 if (!inst.error)
4832 inst.error = BAD_ARGS;
4833 return;
4834 }
4835
4836 if (skip_past_comma (&str) == FAIL
4837 || cp_opc_expr (&str, 20,4) == FAIL)
4838 {
4839 if (!inst.error)
4840 inst.error = BAD_ARGS;
4841 return;
4842 }
4843
4844 if (skip_past_comma (&str) == FAIL
4845 || cp_reg_required_here (&str, 12) == FAIL)
4846 {
4847 if (!inst.error)
4848 inst.error = BAD_ARGS;
4849 return;
4850 }
4851
4852 if (skip_past_comma (&str) == FAIL
4853 || cp_reg_required_here (&str, 16) == FAIL)
4854 {
4855 if (!inst.error)
4856 inst.error = BAD_ARGS;
4857 return;
4858 }
4859
4860 if (skip_past_comma (&str) == FAIL
4861 || cp_reg_required_here (&str, 0) == FAIL)
4862 {
4863 if (!inst.error)
4864 inst.error = BAD_ARGS;
4865 return;
4866 }
4867
4868 if (skip_past_comma (&str) == SUCCESS)
4869 {
4870 if (cp_opc_expr (&str, 5, 3) == FAIL)
4871 {
4872 if (!inst.error)
4873 inst.error = BAD_ARGS;
4874 return;
4875 }
4876 }
4877
4878 end_of_line (str);
4879 return;
4880 }
4881
4882 static void
4883 do_lstc (str, flags)
4884 char * str;
4885 unsigned long flags;
4886 {
4887 /* Co-processor register load/store.
4888 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
4889
4890 skip_whitespace (str);
4891
4892 if (co_proc_number (&str) == FAIL)
4893 {
4894 if (!inst.error)
4895 inst.error = BAD_ARGS;
4896 return;
4897 }
4898
4899 if (skip_past_comma (&str) == FAIL
4900 || cp_reg_required_here (&str, 12) == FAIL)
4901 {
4902 if (!inst.error)
4903 inst.error = BAD_ARGS;
4904 return;
4905 }
4906
4907 if (skip_past_comma (&str) == FAIL
4908 || cp_address_required_here (&str) == FAIL)
4909 {
4910 if (! inst.error)
4911 inst.error = BAD_ARGS;
4912 return;
4913 }
4914
4915 inst.instruction |= flags;
4916 end_of_line (str);
4917 return;
4918 }
4919
4920 static void
4921 do_co_reg (str, flags)
4922 char * str;
4923 unsigned long flags;
4924 {
4925 /* Co-processor register transfer.
4926 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
4927
4928 skip_whitespace (str);
4929
4930 if (co_proc_number (&str) == FAIL)
4931 {
4932 if (!inst.error)
4933 inst.error = BAD_ARGS;
4934 return;
4935 }
4936
4937 if (skip_past_comma (&str) == FAIL
4938 || cp_opc_expr (&str, 21, 3) == FAIL)
4939 {
4940 if (!inst.error)
4941 inst.error = BAD_ARGS;
4942 return;
4943 }
4944
4945 if (skip_past_comma (&str) == FAIL
4946 || reg_required_here (&str, 12) == FAIL)
4947 {
4948 if (!inst.error)
4949 inst.error = BAD_ARGS;
4950 return;
4951 }
4952
4953 if (skip_past_comma (&str) == FAIL
4954 || cp_reg_required_here (&str, 16) == FAIL)
4955 {
4956 if (!inst.error)
4957 inst.error = BAD_ARGS;
4958 return;
4959 }
4960
4961 if (skip_past_comma (&str) == FAIL
4962 || cp_reg_required_here (&str, 0) == FAIL)
4963 {
4964 if (!inst.error)
4965 inst.error = BAD_ARGS;
4966 return;
4967 }
4968
4969 if (skip_past_comma (&str) == SUCCESS)
4970 {
4971 if (cp_opc_expr (&str, 5, 3) == FAIL)
4972 {
4973 if (!inst.error)
4974 inst.error = BAD_ARGS;
4975 return;
4976 }
4977 }
4978 if (flags)
4979 {
4980 inst.error = BAD_COND;
4981 }
4982
4983 end_of_line (str);
4984 return;
4985 }
4986
4987 static void
4988 do_fp_ctrl (str, flags)
4989 char * str;
4990 unsigned long flags ATTRIBUTE_UNUSED;
4991 {
4992 /* FP control registers.
4993 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
4994
4995 skip_whitespace (str);
4996
4997 if (reg_required_here (&str, 12) == FAIL)
4998 {
4999 if (!inst.error)
5000 inst.error = BAD_ARGS;
5001 return;
5002 }
5003
5004 end_of_line (str);
5005 return;
5006 }
5007
5008 static void
5009 do_fp_ldst (str, flags)
5010 char * str;
5011 unsigned long flags ATTRIBUTE_UNUSED;
5012 {
5013 skip_whitespace (str);
5014
5015 switch (inst.suffix)
5016 {
5017 case SUFF_S:
5018 break;
5019 case SUFF_D:
5020 inst.instruction |= CP_T_X;
5021 break;
5022 case SUFF_E:
5023 inst.instruction |= CP_T_Y;
5024 break;
5025 case SUFF_P:
5026 inst.instruction |= CP_T_X | CP_T_Y;
5027 break;
5028 default:
5029 abort ();
5030 }
5031
5032 if (fp_reg_required_here (&str, 12) == FAIL)
5033 {
5034 if (!inst.error)
5035 inst.error = BAD_ARGS;
5036 return;
5037 }
5038
5039 if (skip_past_comma (&str) == FAIL
5040 || cp_address_required_here (&str) == FAIL)
5041 {
5042 if (!inst.error)
5043 inst.error = BAD_ARGS;
5044 return;
5045 }
5046
5047 end_of_line (str);
5048 }
5049
5050 static void
5051 do_fp_ldmstm (str, flags)
5052 char * str;
5053 unsigned long flags;
5054 {
5055 int num_regs;
5056
5057 skip_whitespace (str);
5058
5059 if (fp_reg_required_here (&str, 12) == FAIL)
5060 {
5061 if (! inst.error)
5062 inst.error = BAD_ARGS;
5063 return;
5064 }
5065
5066 /* Get Number of registers to transfer. */
5067 if (skip_past_comma (&str) == FAIL
5068 || my_get_expression (&inst.reloc.exp, &str))
5069 {
5070 if (! inst.error)
5071 inst.error = _("constant expression expected");
5072 return;
5073 }
5074
5075 if (inst.reloc.exp.X_op != O_constant)
5076 {
5077 inst.error = _("Constant value required for number of registers");
5078 return;
5079 }
5080
5081 num_regs = inst.reloc.exp.X_add_number;
5082
5083 if (num_regs < 1 || num_regs > 4)
5084 {
5085 inst.error = _("number of registers must be in the range [1:4]");
5086 return;
5087 }
5088
5089 switch (num_regs)
5090 {
5091 case 1:
5092 inst.instruction |= CP_T_X;
5093 break;
5094 case 2:
5095 inst.instruction |= CP_T_Y;
5096 break;
5097 case 3:
5098 inst.instruction |= CP_T_Y | CP_T_X;
5099 break;
5100 case 4:
5101 break;
5102 default:
5103 abort ();
5104 }
5105
5106 if (flags)
5107 {
5108 int reg;
5109 int write_back;
5110 int offset;
5111
5112 /* The instruction specified "ea" or "fd", so we can only accept
5113 [Rn]{!}. The instruction does not really support stacking or
5114 unstacking, so we have to emulate these by setting appropriate
5115 bits and offsets. */
5116 if (skip_past_comma (&str) == FAIL
5117 || *str != '[')
5118 {
5119 if (! inst.error)
5120 inst.error = BAD_ARGS;
5121 return;
5122 }
5123
5124 str++;
5125 skip_whitespace (str);
5126
5127 if ((reg = reg_required_here (&str, 16)) == FAIL)
5128 return;
5129
5130 skip_whitespace (str);
5131
5132 if (*str != ']')
5133 {
5134 inst.error = BAD_ARGS;
5135 return;
5136 }
5137
5138 str++;
5139 if (*str == '!')
5140 {
5141 write_back = 1;
5142 str++;
5143 if (reg == REG_PC)
5144 {
5145 inst.error =
5146 _("R15 not allowed as base register with write-back");
5147 return;
5148 }
5149 }
5150 else
5151 write_back = 0;
5152
5153 if (flags & CP_T_Pre)
5154 {
5155 /* Pre-decrement. */
5156 offset = 3 * num_regs;
5157 if (write_back)
5158 flags |= CP_T_WB;
5159 }
5160 else
5161 {
5162 /* Post-increment. */
5163 if (write_back)
5164 {
5165 flags |= CP_T_WB;
5166 offset = 3 * num_regs;
5167 }
5168 else
5169 {
5170 /* No write-back, so convert this into a standard pre-increment
5171 instruction -- aesthetically more pleasing. */
5172 flags = CP_T_Pre | CP_T_UD;
5173 offset = 0;
5174 }
5175 }
5176
5177 inst.instruction |= flags | offset;
5178 }
5179 else if (skip_past_comma (&str) == FAIL
5180 || cp_address_required_here (&str) == FAIL)
5181 {
5182 if (! inst.error)
5183 inst.error = BAD_ARGS;
5184 return;
5185 }
5186
5187 end_of_line (str);
5188 }
5189
5190 static void
5191 do_fp_dyadic (str, flags)
5192 char * str;
5193 unsigned long flags;
5194 {
5195 skip_whitespace (str);
5196
5197 switch (inst.suffix)
5198 {
5199 case SUFF_S:
5200 break;
5201 case SUFF_D:
5202 inst.instruction |= 0x00000080;
5203 break;
5204 case SUFF_E:
5205 inst.instruction |= 0x00080000;
5206 break;
5207 default:
5208 abort ();
5209 }
5210
5211 if (fp_reg_required_here (&str, 12) == FAIL)
5212 {
5213 if (! inst.error)
5214 inst.error = BAD_ARGS;
5215 return;
5216 }
5217
5218 if (skip_past_comma (&str) == FAIL
5219 || fp_reg_required_here (&str, 16) == FAIL)
5220 {
5221 if (! inst.error)
5222 inst.error = BAD_ARGS;
5223 return;
5224 }
5225
5226 if (skip_past_comma (&str) == FAIL
5227 || fp_op2 (&str) == FAIL)
5228 {
5229 if (! inst.error)
5230 inst.error = BAD_ARGS;
5231 return;
5232 }
5233
5234 inst.instruction |= flags;
5235 end_of_line (str);
5236 return;
5237 }
5238
5239 static void
5240 do_fp_monadic (str, flags)
5241 char * str;
5242 unsigned long flags;
5243 {
5244 skip_whitespace (str);
5245
5246 switch (inst.suffix)
5247 {
5248 case SUFF_S:
5249 break;
5250 case SUFF_D:
5251 inst.instruction |= 0x00000080;
5252 break;
5253 case SUFF_E:
5254 inst.instruction |= 0x00080000;
5255 break;
5256 default:
5257 abort ();
5258 }
5259
5260 if (fp_reg_required_here (&str, 12) == FAIL)
5261 {
5262 if (! inst.error)
5263 inst.error = BAD_ARGS;
5264 return;
5265 }
5266
5267 if (skip_past_comma (&str) == FAIL
5268 || fp_op2 (&str) == FAIL)
5269 {
5270 if (! inst.error)
5271 inst.error = BAD_ARGS;
5272 return;
5273 }
5274
5275 inst.instruction |= flags;
5276 end_of_line (str);
5277 return;
5278 }
5279
5280 static void
5281 do_fp_cmp (str, flags)
5282 char * str;
5283 unsigned long flags;
5284 {
5285 skip_whitespace (str);
5286
5287 if (fp_reg_required_here (&str, 16) == FAIL)
5288 {
5289 if (! inst.error)
5290 inst.error = BAD_ARGS;
5291 return;
5292 }
5293
5294 if (skip_past_comma (&str) == FAIL
5295 || fp_op2 (&str) == FAIL)
5296 {
5297 if (! inst.error)
5298 inst.error = BAD_ARGS;
5299 return;
5300 }
5301
5302 inst.instruction |= flags;
5303 end_of_line (str);
5304 return;
5305 }
5306
5307 static void
5308 do_fp_from_reg (str, flags)
5309 char * str;
5310 unsigned long flags;
5311 {
5312 skip_whitespace (str);
5313
5314 switch (inst.suffix)
5315 {
5316 case SUFF_S:
5317 break;
5318 case SUFF_D:
5319 inst.instruction |= 0x00000080;
5320 break;
5321 case SUFF_E:
5322 inst.instruction |= 0x00080000;
5323 break;
5324 default:
5325 abort ();
5326 }
5327
5328 if (fp_reg_required_here (&str, 16) == FAIL)
5329 {
5330 if (! inst.error)
5331 inst.error = BAD_ARGS;
5332 return;
5333 }
5334
5335 if (skip_past_comma (&str) == FAIL
5336 || reg_required_here (&str, 12) == FAIL)
5337 {
5338 if (! inst.error)
5339 inst.error = BAD_ARGS;
5340 return;
5341 }
5342
5343 inst.instruction |= flags;
5344 end_of_line (str);
5345 return;
5346 }
5347
5348 static void
5349 do_fp_to_reg (str, flags)
5350 char * str;
5351 unsigned long flags;
5352 {
5353 skip_whitespace (str);
5354
5355 if (reg_required_here (&str, 12) == FAIL)
5356 return;
5357
5358 if (skip_past_comma (&str) == FAIL
5359 || fp_reg_required_here (&str, 0) == FAIL)
5360 {
5361 if (! inst.error)
5362 inst.error = BAD_ARGS;
5363 return;
5364 }
5365
5366 inst.instruction |= flags;
5367 end_of_line (str);
5368 return;
5369 }
5370
5371 /* Thumb specific routines. */
5372
5373 /* Parse and validate that a register is of the right form, this saves
5374 repeated checking of this information in many similar cases.
5375 Unlike the 32-bit case we do not insert the register into the opcode
5376 here, since the position is often unknown until the full instruction
5377 has been parsed. */
5378
5379 static int
5380 thumb_reg (strp, hi_lo)
5381 char ** strp;
5382 int hi_lo;
5383 {
5384 int reg;
5385
5386 if ((reg = reg_required_here (strp, -1)) == FAIL)
5387 return FAIL;
5388
5389 switch (hi_lo)
5390 {
5391 case THUMB_REG_LO:
5392 if (reg > 7)
5393 {
5394 inst.error = _("lo register required");
5395 return FAIL;
5396 }
5397 break;
5398
5399 case THUMB_REG_HI:
5400 if (reg < 8)
5401 {
5402 inst.error = _("hi register required");
5403 return FAIL;
5404 }
5405 break;
5406
5407 default:
5408 break;
5409 }
5410
5411 return reg;
5412 }
5413
5414 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
5415 was SUB. */
5416
5417 static void
5418 thumb_add_sub (str, subtract)
5419 char * str;
5420 int subtract;
5421 {
5422 int Rd, Rs, Rn = FAIL;
5423
5424 skip_whitespace (str);
5425
5426 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
5427 || skip_past_comma (&str) == FAIL)
5428 {
5429 if (! inst.error)
5430 inst.error = BAD_ARGS;
5431 return;
5432 }
5433
5434 if (is_immediate_prefix (*str))
5435 {
5436 Rs = Rd;
5437 str++;
5438 if (my_get_expression (&inst.reloc.exp, &str))
5439 return;
5440 }
5441 else
5442 {
5443 if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
5444 return;
5445
5446 if (skip_past_comma (&str) == FAIL)
5447 {
5448 /* Two operand format, shuffle the registers
5449 and pretend there are 3. */
5450 Rn = Rs;
5451 Rs = Rd;
5452 }
5453 else if (is_immediate_prefix (*str))
5454 {
5455 str++;
5456 if (my_get_expression (&inst.reloc.exp, &str))
5457 return;
5458 }
5459 else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
5460 return;
5461 }
5462
5463 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
5464 for the latter case, EXPR contains the immediate that was found. */
5465 if (Rn != FAIL)
5466 {
5467 /* All register format. */
5468 if (Rd > 7 || Rs > 7 || Rn > 7)
5469 {
5470 if (Rs != Rd)
5471 {
5472 inst.error = _("dest and source1 must be the same register");
5473 return;
5474 }
5475
5476 /* Can't do this for SUB. */
5477 if (subtract)
5478 {
5479 inst.error = _("subtract valid only on lo regs");
5480 return;
5481 }
5482
5483 inst.instruction = (T_OPCODE_ADD_HI
5484 | (Rd > 7 ? THUMB_H1 : 0)
5485 | (Rn > 7 ? THUMB_H2 : 0));
5486 inst.instruction |= (Rd & 7) | ((Rn & 7) << 3);
5487 }
5488 else
5489 {
5490 inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3;
5491 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
5492 }
5493 }
5494 else
5495 {
5496 /* Immediate expression, now things start to get nasty. */
5497
5498 /* First deal with HI regs, only very restricted cases allowed:
5499 Adjusting SP, and using PC or SP to get an address. */
5500 if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
5501 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC))
5502 {
5503 inst.error = _("invalid Hi register with immediate");
5504 return;
5505 }
5506
5507 if (inst.reloc.exp.X_op != O_constant)
5508 {
5509 /* Value isn't known yet, all we can do is store all the fragments
5510 we know about in the instruction and let the reloc hacking
5511 work it all out. */
5512 inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs;
5513 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
5514 }
5515 else
5516 {
5517 int offset = inst.reloc.exp.X_add_number;
5518
5519 if (subtract)
5520 offset = -offset;
5521
5522 if (offset < 0)
5523 {
5524 offset = -offset;
5525 subtract = 1;
5526
5527 /* Quick check, in case offset is MIN_INT. */
5528 if (offset < 0)
5529 {
5530 inst.error = _("immediate value out of range");
5531 return;
5532 }
5533 }
5534 else
5535 subtract = 0;
5536
5537 if (Rd == REG_SP)
5538 {
5539 if (offset & ~0x1fc)
5540 {
5541 inst.error = _("invalid immediate value for stack adjust");
5542 return;
5543 }
5544 inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
5545 inst.instruction |= offset >> 2;
5546 }
5547 else if (Rs == REG_PC || Rs == REG_SP)
5548 {
5549 if (subtract
5550 || (offset & ~0x3fc))
5551 {
5552 inst.error = _("invalid immediate for address calculation");
5553 return;
5554 }
5555 inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC
5556 : T_OPCODE_ADD_SP);
5557 inst.instruction |= (Rd << 8) | (offset >> 2);
5558 }
5559 else if (Rs == Rd)
5560 {
5561 if (offset & ~0xff)
5562 {
5563 inst.error = _("immediate value out of range");
5564 return;
5565 }
5566 inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
5567 inst.instruction |= (Rd << 8) | offset;
5568 }
5569 else
5570 {
5571 if (offset & ~0x7)
5572 {
5573 inst.error = _("immediate value out of range");
5574 return;
5575 }
5576 inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
5577 inst.instruction |= Rd | (Rs << 3) | (offset << 6);
5578 }
5579 }
5580 }
5581
5582 end_of_line (str);
5583 }
5584
5585 static void
5586 thumb_shift (str, shift)
5587 char * str;
5588 int shift;
5589 {
5590 int Rd, Rs, Rn = FAIL;
5591
5592 skip_whitespace (str);
5593
5594 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
5595 || skip_past_comma (&str) == FAIL)
5596 {
5597 if (! inst.error)
5598 inst.error = BAD_ARGS;
5599 return;
5600 }
5601
5602 if (is_immediate_prefix (*str))
5603 {
5604 /* Two operand immediate format, set Rs to Rd. */
5605 Rs = Rd;
5606 str ++;
5607 if (my_get_expression (&inst.reloc.exp, &str))
5608 return;
5609 }
5610 else
5611 {
5612 if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
5613 return;
5614
5615 if (skip_past_comma (&str) == FAIL)
5616 {
5617 /* Two operand format, shuffle the registers
5618 and pretend there are 3. */
5619 Rn = Rs;
5620 Rs = Rd;
5621 }
5622 else if (is_immediate_prefix (*str))
5623 {
5624 str++;
5625 if (my_get_expression (&inst.reloc.exp, &str))
5626 return;
5627 }
5628 else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
5629 return;
5630 }
5631
5632 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
5633 for the latter case, EXPR contains the immediate that was found. */
5634
5635 if (Rn != FAIL)
5636 {
5637 if (Rs != Rd)
5638 {
5639 inst.error = _("source1 and dest must be same register");
5640 return;
5641 }
5642
5643 switch (shift)
5644 {
5645 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break;
5646 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break;
5647 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break;
5648 }
5649
5650 inst.instruction |= Rd | (Rn << 3);
5651 }
5652 else
5653 {
5654 switch (shift)
5655 {
5656 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break;
5657 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break;
5658 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break;
5659 }
5660
5661 if (inst.reloc.exp.X_op != O_constant)
5662 {
5663 /* Value isn't known yet, create a dummy reloc and let reloc
5664 hacking fix it up. */
5665 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
5666 }
5667 else
5668 {
5669 unsigned shift_value = inst.reloc.exp.X_add_number;
5670
5671 if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
5672 {
5673 inst.error = _("Invalid immediate for shift");
5674 return;
5675 }
5676
5677 /* Shifts of zero are handled by converting to LSL. */
5678 if (shift_value == 0)
5679 inst.instruction = T_OPCODE_LSL_I;
5680
5681 /* Shifts of 32 are encoded as a shift of zero. */
5682 if (shift_value == 32)
5683 shift_value = 0;
5684
5685 inst.instruction |= shift_value << 6;
5686 }
5687
5688 inst.instruction |= Rd | (Rs << 3);
5689 }
5690
5691 end_of_line (str);
5692 }
5693
5694 static void
5695 thumb_mov_compare (str, move)
5696 char * str;
5697 int move;
5698 {
5699 int Rd, Rs = FAIL;
5700
5701 skip_whitespace (str);
5702
5703 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
5704 || skip_past_comma (&str) == FAIL)
5705 {
5706 if (! inst.error)
5707 inst.error = BAD_ARGS;
5708 return;
5709 }
5710
5711 if (is_immediate_prefix (*str))
5712 {
5713 str++;
5714 if (my_get_expression (&inst.reloc.exp, &str))
5715 return;
5716 }
5717 else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
5718 return;
5719
5720 if (Rs != FAIL)
5721 {
5722 if (Rs < 8 && Rd < 8)
5723 {
5724 if (move == THUMB_MOVE)
5725 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
5726 since a MOV instruction produces unpredictable results. */
5727 inst.instruction = T_OPCODE_ADD_I3;
5728 else
5729 inst.instruction = T_OPCODE_CMP_LR;
5730 inst.instruction |= Rd | (Rs << 3);
5731 }
5732 else
5733 {
5734 if (move == THUMB_MOVE)
5735 inst.instruction = T_OPCODE_MOV_HR;
5736 else
5737 inst.instruction = T_OPCODE_CMP_HR;
5738
5739 if (Rd > 7)
5740 inst.instruction |= THUMB_H1;
5741
5742 if (Rs > 7)
5743 inst.instruction |= THUMB_H2;
5744
5745 inst.instruction |= (Rd & 7) | ((Rs & 7) << 3);
5746 }
5747 }
5748 else
5749 {
5750 if (Rd > 7)
5751 {
5752 inst.error = _("only lo regs allowed with immediate");
5753 return;
5754 }
5755
5756 if (move == THUMB_MOVE)
5757 inst.instruction = T_OPCODE_MOV_I8;
5758 else
5759 inst.instruction = T_OPCODE_CMP_I8;
5760
5761 inst.instruction |= Rd << 8;
5762
5763 if (inst.reloc.exp.X_op != O_constant)
5764 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
5765 else
5766 {
5767 unsigned value = inst.reloc.exp.X_add_number;
5768
5769 if (value > 255)
5770 {
5771 inst.error = _("invalid immediate");
5772 return;
5773 }
5774
5775 inst.instruction |= value;
5776 }
5777 }
5778
5779 end_of_line (str);
5780 }
5781
5782 static void
5783 thumb_load_store (str, load_store, size)
5784 char * str;
5785 int load_store;
5786 int size;
5787 {
5788 int Rd, Rb, Ro = FAIL;
5789
5790 skip_whitespace (str);
5791
5792 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
5793 || skip_past_comma (&str) == FAIL)
5794 {
5795 if (! inst.error)
5796 inst.error = BAD_ARGS;
5797 return;
5798 }
5799
5800 if (*str == '[')
5801 {
5802 str++;
5803 if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
5804 return;
5805
5806 if (skip_past_comma (&str) != FAIL)
5807 {
5808 if (is_immediate_prefix (*str))
5809 {
5810 str++;
5811 if (my_get_expression (&inst.reloc.exp, &str))
5812 return;
5813 }
5814 else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
5815 return;
5816 }
5817 else
5818 {
5819 inst.reloc.exp.X_op = O_constant;
5820 inst.reloc.exp.X_add_number = 0;
5821 }
5822
5823 if (*str != ']')
5824 {
5825 inst.error = _("expected ']'");
5826 return;
5827 }
5828 str++;
5829 }
5830 else if (*str == '=')
5831 {
5832 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
5833 str++;
5834
5835 skip_whitespace (str);
5836
5837 if (my_get_expression (& inst.reloc.exp, & str))
5838 return;
5839
5840 end_of_line (str);
5841
5842 if ( inst.reloc.exp.X_op != O_constant
5843 && inst.reloc.exp.X_op != O_symbol)
5844 {
5845 inst.error = "Constant expression expected";
5846 return;
5847 }
5848
5849 if (inst.reloc.exp.X_op == O_constant
5850 && ((inst.reloc.exp.X_add_number & ~0xFF) == 0))
5851 {
5852 /* This can be done with a mov instruction. */
5853
5854 inst.instruction = T_OPCODE_MOV_I8 | (Rd << 8);
5855 inst.instruction |= inst.reloc.exp.X_add_number;
5856 return;
5857 }
5858
5859 /* Insert into literal pool. */
5860 if (add_to_lit_pool () == FAIL)
5861 {
5862 if (!inst.error)
5863 inst.error = "literal pool insertion failed";
5864 return;
5865 }
5866
5867 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
5868 inst.reloc.pc_rel = 1;
5869 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
5870 /* Adjust ARM pipeline offset to Thumb. */
5871 inst.reloc.exp.X_add_number += 4;
5872
5873 return;
5874 }
5875 else
5876 {
5877 if (my_get_expression (&inst.reloc.exp, &str))
5878 return;
5879
5880 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
5881 inst.reloc.pc_rel = 1;
5882 inst.reloc.exp.X_add_number -= 4; /* Pipeline offset. */
5883 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
5884 end_of_line (str);
5885 return;
5886 }
5887
5888 if (Rb == REG_PC || Rb == REG_SP)
5889 {
5890 if (size != THUMB_WORD)
5891 {
5892 inst.error = _("byte or halfword not valid for base register");
5893 return;
5894 }
5895 else if (Rb == REG_PC && load_store != THUMB_LOAD)
5896 {
5897 inst.error = _("R15 based store not allowed");
5898 return;
5899 }
5900 else if (Ro != FAIL)
5901 {
5902 inst.error = _("Invalid base register for register offset");
5903 return;
5904 }
5905
5906 if (Rb == REG_PC)
5907 inst.instruction = T_OPCODE_LDR_PC;
5908 else if (load_store == THUMB_LOAD)
5909 inst.instruction = T_OPCODE_LDR_SP;
5910 else
5911 inst.instruction = T_OPCODE_STR_SP;
5912
5913 inst.instruction |= Rd << 8;
5914 if (inst.reloc.exp.X_op == O_constant)
5915 {
5916 unsigned offset = inst.reloc.exp.X_add_number;
5917
5918 if (offset & ~0x3fc)
5919 {
5920 inst.error = _("invalid offset");
5921 return;
5922 }
5923
5924 inst.instruction |= offset >> 2;
5925 }
5926 else
5927 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
5928 }
5929 else if (Rb > 7)
5930 {
5931 inst.error = _("invalid base register in load/store");
5932 return;
5933 }
5934 else if (Ro == FAIL)
5935 {
5936 /* Immediate offset. */
5937 if (size == THUMB_WORD)
5938 inst.instruction = (load_store == THUMB_LOAD
5939 ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW);
5940 else if (size == THUMB_HALFWORD)
5941 inst.instruction = (load_store == THUMB_LOAD
5942 ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH);
5943 else
5944 inst.instruction = (load_store == THUMB_LOAD
5945 ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB);
5946
5947 inst.instruction |= Rd | (Rb << 3);
5948
5949 if (inst.reloc.exp.X_op == O_constant)
5950 {
5951 unsigned offset = inst.reloc.exp.X_add_number;
5952
5953 if (offset & ~(0x1f << size))
5954 {
5955 inst.error = _("Invalid offset");
5956 return;
5957 }
5958 inst.instruction |= (offset >> size) << 6;
5959 }
5960 else
5961 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
5962 }
5963 else
5964 {
5965 /* Register offset. */
5966 if (size == THUMB_WORD)
5967 inst.instruction = (load_store == THUMB_LOAD
5968 ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW);
5969 else if (size == THUMB_HALFWORD)
5970 inst.instruction = (load_store == THUMB_LOAD
5971 ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH);
5972 else
5973 inst.instruction = (load_store == THUMB_LOAD
5974 ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB);
5975
5976 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
5977 }
5978
5979 end_of_line (str);
5980 }
5981
5982 static void
5983 do_t_nop (str)
5984 char * str;
5985 {
5986 /* Do nothing. */
5987 end_of_line (str);
5988 return;
5989 }
5990
5991 /* Handle the Format 4 instructions that do not have equivalents in other
5992 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
5993 BIC and MVN. */
5994
5995 static void
5996 do_t_arit (str)
5997 char * str;
5998 {
5999 int Rd, Rs, Rn;
6000
6001 skip_whitespace (str);
6002
6003 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
6004 || skip_past_comma (&str) == FAIL
6005 || (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
6006 {
6007 inst.error = BAD_ARGS;
6008 return;
6009 }
6010
6011 if (skip_past_comma (&str) != FAIL)
6012 {
6013 /* Three operand format not allowed for TST, CMN, NEG and MVN.
6014 (It isn't allowed for CMP either, but that isn't handled by this
6015 function.) */
6016 if (inst.instruction == T_OPCODE_TST
6017 || inst.instruction == T_OPCODE_CMN
6018 || inst.instruction == T_OPCODE_NEG
6019 || inst.instruction == T_OPCODE_MVN)
6020 {
6021 inst.error = BAD_ARGS;
6022 return;
6023 }
6024
6025 if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
6026 return;
6027
6028 if (Rs != Rd)
6029 {
6030 inst.error = _("dest and source1 must be the same register");
6031 return;
6032 }
6033 Rs = Rn;
6034 }
6035
6036 if (inst.instruction == T_OPCODE_MUL
6037 && Rs == Rd)
6038 as_tsktsk (_("Rs and Rd must be different in MUL"));
6039
6040 inst.instruction |= Rd | (Rs << 3);
6041 end_of_line (str);
6042 }
6043
6044 static void
6045 do_t_add (str)
6046 char * str;
6047 {
6048 thumb_add_sub (str, 0);
6049 }
6050
6051 static void
6052 do_t_asr (str)
6053 char * str;
6054 {
6055 thumb_shift (str, THUMB_ASR);
6056 }
6057
6058 static void
6059 do_t_branch9 (str)
6060 char * str;
6061 {
6062 if (my_get_expression (&inst.reloc.exp, &str))
6063 return;
6064 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
6065 inst.reloc.pc_rel = 1;
6066 end_of_line (str);
6067 }
6068
6069 static void
6070 do_t_branch12 (str)
6071 char * str;
6072 {
6073 if (my_get_expression (&inst.reloc.exp, &str))
6074 return;
6075 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
6076 inst.reloc.pc_rel = 1;
6077 end_of_line (str);
6078 }
6079
6080 /* Find the real, Thumb encoded start of a Thumb function. */
6081
6082 static symbolS *
6083 find_real_start (symbolP)
6084 symbolS * symbolP;
6085 {
6086 char * real_start;
6087 const char * name = S_GET_NAME (symbolP);
6088 symbolS * new_target;
6089
6090 /* This definiton must agree with the one in gcc/config/arm/thumb.c. */
6091 #define STUB_NAME ".real_start_of"
6092
6093 if (name == NULL)
6094 abort ();
6095
6096 /* Names that start with '.' are local labels, not function entry points.
6097 The compiler may generate BL instructions to these labels because it
6098 needs to perform a branch to a far away location. */
6099 if (name[0] == '.')
6100 return symbolP;
6101
6102 real_start = malloc (strlen (name) + strlen (STUB_NAME) + 1);
6103 sprintf (real_start, "%s%s", STUB_NAME, name);
6104
6105 new_target = symbol_find (real_start);
6106
6107 if (new_target == NULL)
6108 {
6109 as_warn ("Failed to find real start of function: %s\n", name);
6110 new_target = symbolP;
6111 }
6112
6113 free (real_start);
6114
6115 return new_target;
6116 }
6117
6118 static void
6119 do_t_branch23 (str)
6120 char * str;
6121 {
6122 if (my_get_expression (& inst.reloc.exp, & str))
6123 return;
6124
6125 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
6126 inst.reloc.pc_rel = 1;
6127 end_of_line (str);
6128
6129 /* If the destination of the branch is a defined symbol which does not have
6130 the THUMB_FUNC attribute, then we must be calling a function which has
6131 the (interfacearm) attribute. We look for the Thumb entry point to that
6132 function and change the branch to refer to that function instead. */
6133 if ( inst.reloc.exp.X_op == O_symbol
6134 && inst.reloc.exp.X_add_symbol != NULL
6135 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
6136 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
6137 inst.reloc.exp.X_add_symbol =
6138 find_real_start (inst.reloc.exp.X_add_symbol);
6139 }
6140
6141 static void
6142 do_t_bx (str)
6143 char * str;
6144 {
6145 int reg;
6146
6147 skip_whitespace (str);
6148
6149 if ((reg = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
6150 return;
6151
6152 /* This sets THUMB_H2 from the top bit of reg. */
6153 inst.instruction |= reg << 3;
6154
6155 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
6156 should cause the alignment to be checked once it is known. This is
6157 because BX PC only works if the instruction is word aligned. */
6158
6159 end_of_line (str);
6160 }
6161
6162 static void
6163 do_t_compare (str)
6164 char * str;
6165 {
6166 thumb_mov_compare (str, THUMB_COMPARE);
6167 }
6168
6169 static void
6170 do_t_ldmstm (str)
6171 char * str;
6172 {
6173 int Rb;
6174 long range;
6175
6176 skip_whitespace (str);
6177
6178 if ((Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
6179 return;
6180
6181 if (*str != '!')
6182 as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
6183 else
6184 str++;
6185
6186 if (skip_past_comma (&str) == FAIL
6187 || (range = reg_list (&str)) == FAIL)
6188 {
6189 if (! inst.error)
6190 inst.error = BAD_ARGS;
6191 return;
6192 }
6193
6194 if (inst.reloc.type != BFD_RELOC_NONE)
6195 {
6196 /* This really doesn't seem worth it. */
6197 inst.reloc.type = BFD_RELOC_NONE;
6198 inst.error = _("Expression too complex");
6199 return;
6200 }
6201
6202 if (range & ~0xff)
6203 {
6204 inst.error = _("only lo-regs valid in load/store multiple");
6205 return;
6206 }
6207
6208 inst.instruction |= (Rb << 8) | range;
6209 end_of_line (str);
6210 }
6211
6212 static void
6213 do_t_ldr (str)
6214 char * str;
6215 {
6216 thumb_load_store (str, THUMB_LOAD, THUMB_WORD);
6217 }
6218
6219 static void
6220 do_t_ldrb (str)
6221 char * str;
6222 {
6223 thumb_load_store (str, THUMB_LOAD, THUMB_BYTE);
6224 }
6225
6226 static void
6227 do_t_ldrh (str)
6228 char * str;
6229 {
6230 thumb_load_store (str, THUMB_LOAD, THUMB_HALFWORD);
6231 }
6232
6233 static void
6234 do_t_lds (str)
6235 char * str;
6236 {
6237 int Rd, Rb, Ro;
6238
6239 skip_whitespace (str);
6240
6241 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
6242 || skip_past_comma (&str) == FAIL
6243 || *str++ != '['
6244 || (Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL
6245 || skip_past_comma (&str) == FAIL
6246 || (Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL
6247 || *str++ != ']')
6248 {
6249 if (! inst.error)
6250 inst.error = _("Syntax: ldrs[b] Rd, [Rb, Ro]");
6251 return;
6252 }
6253
6254 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
6255 end_of_line (str);
6256 }
6257
6258 static void
6259 do_t_lsl (str)
6260 char * str;
6261 {
6262 thumb_shift (str, THUMB_LSL);
6263 }
6264
6265 static void
6266 do_t_lsr (str)
6267 char * str;
6268 {
6269 thumb_shift (str, THUMB_LSR);
6270 }
6271
6272 static void
6273 do_t_mov (str)
6274 char * str;
6275 {
6276 thumb_mov_compare (str, THUMB_MOVE);
6277 }
6278
6279 static void
6280 do_t_push_pop (str)
6281 char * str;
6282 {
6283 long range;
6284
6285 skip_whitespace (str);
6286
6287 if ((range = reg_list (&str)) == FAIL)
6288 {
6289 if (! inst.error)
6290 inst.error = BAD_ARGS;
6291 return;
6292 }
6293
6294 if (inst.reloc.type != BFD_RELOC_NONE)
6295 {
6296 /* This really doesn't seem worth it. */
6297 inst.reloc.type = BFD_RELOC_NONE;
6298 inst.error = _("Expression too complex");
6299 return;
6300 }
6301
6302 if (range & ~0xff)
6303 {
6304 if ((inst.instruction == T_OPCODE_PUSH
6305 && (range & ~0xff) == 1 << REG_LR)
6306 || (inst.instruction == T_OPCODE_POP
6307 && (range & ~0xff) == 1 << REG_PC))
6308 {
6309 inst.instruction |= THUMB_PP_PC_LR;
6310 range &= 0xff;
6311 }
6312 else
6313 {
6314 inst.error = _("invalid register list to push/pop instruction");
6315 return;
6316 }
6317 }
6318
6319 inst.instruction |= range;
6320 end_of_line (str);
6321 }
6322
6323 static void
6324 do_t_str (str)
6325 char * str;
6326 {
6327 thumb_load_store (str, THUMB_STORE, THUMB_WORD);
6328 }
6329
6330 static void
6331 do_t_strb (str)
6332 char * str;
6333 {
6334 thumb_load_store (str, THUMB_STORE, THUMB_BYTE);
6335 }
6336
6337 static void
6338 do_t_strh (str)
6339 char * str;
6340 {
6341 thumb_load_store (str, THUMB_STORE, THUMB_HALFWORD);
6342 }
6343
6344 static void
6345 do_t_sub (str)
6346 char * str;
6347 {
6348 thumb_add_sub (str, 1);
6349 }
6350
6351 static void
6352 do_t_swi (str)
6353 char * str;
6354 {
6355 skip_whitespace (str);
6356
6357 if (my_get_expression (&inst.reloc.exp, &str))
6358 return;
6359
6360 inst.reloc.type = BFD_RELOC_ARM_SWI;
6361 end_of_line (str);
6362 return;
6363 }
6364
6365 static void
6366 do_t_adr (str)
6367 char * str;
6368 {
6369 int reg;
6370
6371 /* This is a pseudo-op of the form "adr rd, label" to be converted
6372 into a relative address of the form "add rd, pc, #label-.-4". */
6373 skip_whitespace (str);
6374
6375 /* Store Rd in temporary location inside instruction. */
6376 if ((reg = reg_required_here (&str, 4)) == FAIL
6377 || (reg > 7) /* For Thumb reg must be r0..r7. */
6378 || skip_past_comma (&str) == FAIL
6379 || my_get_expression (&inst.reloc.exp, &str))
6380 {
6381 if (!inst.error)
6382 inst.error = BAD_ARGS;
6383 return;
6384 }
6385
6386 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
6387 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
6388 inst.reloc.pc_rel = 1;
6389 inst.instruction |= REG_PC; /* Rd is already placed into the instruction. */
6390
6391 end_of_line (str);
6392 }
6393
6394 static void
6395 insert_reg (entry)
6396 int entry;
6397 {
6398 int len = strlen (reg_table[entry].name) + 2;
6399 char * buf = (char *) xmalloc (len);
6400 char * buf2 = (char *) xmalloc (len);
6401 int i = 0;
6402
6403 #ifdef REGISTER_PREFIX
6404 buf[i++] = REGISTER_PREFIX;
6405 #endif
6406
6407 strcpy (buf + i, reg_table[entry].name);
6408
6409 for (i = 0; buf[i]; i++)
6410 buf2[i] = islower (buf[i]) ? toupper (buf[i]) : buf[i];
6411
6412 buf2[i] = '\0';
6413
6414 hash_insert (arm_reg_hsh, buf, (PTR) & reg_table[entry]);
6415 hash_insert (arm_reg_hsh, buf2, (PTR) & reg_table[entry]);
6416 }
6417
6418 static void
6419 insert_reg_alias (str, regnum)
6420 char *str;
6421 int regnum;
6422 {
6423 struct reg_entry *new =
6424 (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
6425 char *name = xmalloc (strlen (str) + 1);
6426 strcpy (name, str);
6427
6428 new->name = name;
6429 new->number = regnum;
6430
6431 hash_insert (arm_reg_hsh, name, (PTR) new);
6432 }
6433
6434 static void
6435 set_constant_flonums ()
6436 {
6437 int i;
6438
6439 for (i = 0; i < NUM_FLOAT_VALS; i++)
6440 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
6441 abort ();
6442 }
6443
6444 void
6445 md_begin ()
6446 {
6447 unsigned mach;
6448 unsigned int i;
6449
6450 if ( (arm_ops_hsh = hash_new ()) == NULL
6451 || (arm_tops_hsh = hash_new ()) == NULL
6452 || (arm_cond_hsh = hash_new ()) == NULL
6453 || (arm_shift_hsh = hash_new ()) == NULL
6454 || (arm_reg_hsh = hash_new ()) == NULL
6455 || (arm_psr_hsh = hash_new ()) == NULL)
6456 as_fatal (_("Virtual memory exhausted"));
6457
6458 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
6459 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
6460 for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++)
6461 hash_insert (arm_tops_hsh, tinsns[i].template, (PTR) (tinsns + i));
6462 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
6463 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
6464 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
6465 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
6466 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
6467 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
6468
6469 for (i = 0; reg_table[i].name; i++)
6470 insert_reg (i);
6471
6472 set_constant_flonums ();
6473
6474 #if defined OBJ_COFF || defined OBJ_ELF
6475 {
6476 unsigned int flags = 0;
6477
6478 /* Set the flags in the private structure. */
6479 if (uses_apcs_26) flags |= F_APCS26;
6480 if (support_interwork) flags |= F_INTERWORK;
6481 if (uses_apcs_float) flags |= F_APCS_FLOAT;
6482 if (pic_code) flags |= F_PIC;
6483 if ((cpu_variant & FPU_ALL) == FPU_NONE) flags |= F_SOFT_FLOAT;
6484
6485 bfd_set_private_flags (stdoutput, flags);
6486
6487 /* We have run out flags in the COFF header to encode the
6488 status of ATPCS support, so instead we create a dummy,
6489 empty, debug section called .arm.atpcs. */
6490 if (atpcs)
6491 {
6492 asection * sec;
6493
6494 sec = bfd_make_section (stdoutput, ".arm.atpcs");
6495
6496 if (sec != NULL)
6497 {
6498 bfd_set_section_flags
6499 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
6500 bfd_set_section_size (stdoutput, sec, 0);
6501 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
6502 }
6503 }
6504 }
6505 #endif
6506
6507 /* Record the CPU type as well. */
6508 switch (cpu_variant & ARM_CPU_MASK)
6509 {
6510 case ARM_2:
6511 mach = bfd_mach_arm_2;
6512 break;
6513
6514 case ARM_3: /* Also ARM_250. */
6515 mach = bfd_mach_arm_2a;
6516 break;
6517
6518 default:
6519 case ARM_6 | ARM_3 | ARM_2: /* Actually no CPU type defined. */
6520 mach = bfd_mach_arm_4;
6521 break;
6522
6523 case ARM_7: /* Also ARM_6. */
6524 mach = bfd_mach_arm_3;
6525 break;
6526 }
6527
6528 /* Catch special cases. */
6529 if (cpu_variant & ARM_EXT_XSCALE)
6530 mach = bfd_mach_arm_XScale;
6531 else if (cpu_variant & ARM_EXT_V5E)
6532 mach = bfd_mach_arm_5TE;
6533 else if (cpu_variant & ARM_EXT_V5)
6534 {
6535 if (cpu_variant & ARM_EXT_THUMB)
6536 mach = bfd_mach_arm_5T;
6537 else
6538 mach = bfd_mach_arm_5;
6539 }
6540 else if (cpu_variant & ARM_EXT_HALFWORD)
6541 {
6542 if (cpu_variant & ARM_EXT_THUMB)
6543 mach = bfd_mach_arm_4T;
6544 else
6545 mach = bfd_mach_arm_4;
6546 }
6547 else if (cpu_variant & ARM_EXT_LONGMUL)
6548 mach = bfd_mach_arm_3M;
6549
6550 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
6551 }
6552
6553 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6554 for use in the a.out file, and stores them in the array pointed to by buf.
6555 This knows about the endian-ness of the target machine and does
6556 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6557 2 (short) and 4 (long) Floating numbers are put out as a series of
6558 LITTLENUMS (shorts, here at least). */
6559
6560 void
6561 md_number_to_chars (buf, val, n)
6562 char * buf;
6563 valueT val;
6564 int n;
6565 {
6566 if (target_big_endian)
6567 number_to_chars_bigendian (buf, val, n);
6568 else
6569 number_to_chars_littleendian (buf, val, n);
6570 }
6571
6572 static valueT
6573 md_chars_to_number (buf, n)
6574 char * buf;
6575 int n;
6576 {
6577 valueT result = 0;
6578 unsigned char * where = (unsigned char *) buf;
6579
6580 if (target_big_endian)
6581 {
6582 while (n--)
6583 {
6584 result <<= 8;
6585 result |= (*where++ & 255);
6586 }
6587 }
6588 else
6589 {
6590 while (n--)
6591 {
6592 result <<= 8;
6593 result |= (where[n] & 255);
6594 }
6595 }
6596
6597 return result;
6598 }
6599
6600 /* Turn a string in input_line_pointer into a floating point constant
6601 of type TYPE, and store the appropriate bytes in *LITP. The number
6602 of LITTLENUMS emitted is stored in *SIZEP. An error message is
6603 returned, or NULL on OK.
6604
6605 Note that fp constants aren't represent in the normal way on the ARM.
6606 In big endian mode, things are as expected. However, in little endian
6607 mode fp constants are big-endian word-wise, and little-endian byte-wise
6608 within the words. For example, (double) 1.1 in big endian mode is
6609 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
6610 the byte sequence 99 99 f1 3f 9a 99 99 99.
6611
6612 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
6613
6614 char *
6615 md_atof (type, litP, sizeP)
6616 char type;
6617 char * litP;
6618 int * sizeP;
6619 {
6620 int prec;
6621 LITTLENUM_TYPE words[MAX_LITTLENUMS];
6622 char *t;
6623 int i;
6624
6625 switch (type)
6626 {
6627 case 'f':
6628 case 'F':
6629 case 's':
6630 case 'S':
6631 prec = 2;
6632 break;
6633
6634 case 'd':
6635 case 'D':
6636 case 'r':
6637 case 'R':
6638 prec = 4;
6639 break;
6640
6641 case 'x':
6642 case 'X':
6643 prec = 6;
6644 break;
6645
6646 case 'p':
6647 case 'P':
6648 prec = 6;
6649 break;
6650
6651 default:
6652 *sizeP = 0;
6653 return _("Bad call to MD_ATOF()");
6654 }
6655
6656 t = atof_ieee (input_line_pointer, type, words);
6657 if (t)
6658 input_line_pointer = t;
6659 *sizeP = prec * 2;
6660
6661 if (target_big_endian)
6662 {
6663 for (i = 0; i < prec; i++)
6664 {
6665 md_number_to_chars (litP, (valueT) words[i], 2);
6666 litP += 2;
6667 }
6668 }
6669 else
6670 {
6671 /* For a 4 byte float the order of elements in `words' is 1 0. For an
6672 8 byte float the order is 1 0 3 2. */
6673 for (i = 0; i < prec; i += 2)
6674 {
6675 md_number_to_chars (litP, (valueT) words[i + 1], 2);
6676 md_number_to_chars (litP + 2, (valueT) words[i], 2);
6677 litP += 4;
6678 }
6679 }
6680
6681 return 0;
6682 }
6683
6684 /* The knowledge of the PC's pipeline offset is built into the insns
6685 themselves. */
6686
6687 long
6688 md_pcrel_from (fixP)
6689 fixS * fixP;
6690 {
6691 if (fixP->fx_addsy
6692 && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section
6693 && fixP->fx_subsy == NULL)
6694 return 0;
6695
6696 if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD))
6697 {
6698 /* PC relative addressing on the Thumb is slightly odd
6699 as the bottom two bits of the PC are forced to zero
6700 for the calculation. */
6701 return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
6702 }
6703
6704 #ifdef TE_WINCE
6705 /* The pattern was adjusted to accomodate CE's off-by-one fixups,
6706 so we un-adjust here to compensate for the accomodation. */
6707 return fixP->fx_where + fixP->fx_frag->fr_address + 8;
6708 #else
6709 return fixP->fx_where + fixP->fx_frag->fr_address;
6710 #endif
6711 }
6712
6713 /* Round up a section size to the appropriate boundary. */
6714
6715 valueT
6716 md_section_align (segment, size)
6717 segT segment ATTRIBUTE_UNUSED;
6718 valueT size;
6719 {
6720 #ifdef OBJ_ELF
6721 return size;
6722 #else
6723 /* Round all sects to multiple of 4. */
6724 return (size + 3) & ~3;
6725 #endif
6726 }
6727
6728 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6729 Otherwise we have no need to default values of symbols. */
6730
6731 symbolS *
6732 md_undefined_symbol (name)
6733 char * name ATTRIBUTE_UNUSED;
6734 {
6735 #ifdef OBJ_ELF
6736 if (name[0] == '_' && name[1] == 'G'
6737 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
6738 {
6739 if (!GOT_symbol)
6740 {
6741 if (symbol_find (name))
6742 as_bad ("GOT already in the symbol table");
6743
6744 GOT_symbol = symbol_new (name, undefined_section,
6745 (valueT) 0, & zero_address_frag);
6746 }
6747
6748 return GOT_symbol;
6749 }
6750 #endif
6751
6752 return 0;
6753 }
6754
6755 /* arm_reg_parse () := if it looks like a register, return its token and
6756 advance the pointer. */
6757
6758 static int
6759 arm_reg_parse (ccp)
6760 register char ** ccp;
6761 {
6762 char * start = * ccp;
6763 char c;
6764 char * p;
6765 struct reg_entry * reg;
6766
6767 #ifdef REGISTER_PREFIX
6768 if (*start != REGISTER_PREFIX)
6769 return FAIL;
6770 p = start + 1;
6771 #else
6772 p = start;
6773 #ifdef OPTIONAL_REGISTER_PREFIX
6774 if (*p == OPTIONAL_REGISTER_PREFIX)
6775 p++, start++;
6776 #endif
6777 #endif
6778 if (!isalpha (*p) || !is_name_beginner (*p))
6779 return FAIL;
6780
6781 c = *p++;
6782 while (isalpha (c) || isdigit (c) || c == '_')
6783 c = *p++;
6784
6785 *--p = 0;
6786 reg = (struct reg_entry *) hash_find (arm_reg_hsh, start);
6787 *p = c;
6788
6789 if (reg)
6790 {
6791 *ccp = p;
6792 return reg->number;
6793 }
6794
6795 return FAIL;
6796 }
6797
6798 int
6799 md_apply_fix3 (fixP, val, seg)
6800 fixS * fixP;
6801 valueT * val;
6802 segT seg;
6803 {
6804 offsetT value = * val;
6805 offsetT newval;
6806 unsigned int newimm;
6807 unsigned long temp;
6808 int sign;
6809 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
6810 arm_fix_data * arm_data = (arm_fix_data *) fixP->tc_fix_data;
6811
6812 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
6813
6814 /* Note whether this will delete the relocation. */
6815 #if 0
6816 /* Patch from REarnshaw to JDavis (disabled for the moment, since it
6817 doesn't work fully.) */
6818 if ((fixP->fx_addsy == 0 || symbol_constant_p (fixP->fx_addsy))
6819 && !fixP->fx_pcrel)
6820 #else
6821 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
6822 #endif
6823 fixP->fx_done = 1;
6824
6825 /* If this symbol is in a different section then we need to leave it for
6826 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
6827 so we have to undo it's effects here. */
6828 if (fixP->fx_pcrel)
6829 {
6830 if (fixP->fx_addsy != NULL
6831 && S_IS_DEFINED (fixP->fx_addsy)
6832 && S_GET_SEGMENT (fixP->fx_addsy) != seg)
6833 {
6834 if (target_oabi
6835 && (fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
6836 || fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
6837 ))
6838 value = 0;
6839 else
6840 value += md_pcrel_from (fixP);
6841 }
6842 }
6843
6844 /* Remember value for emit_reloc. */
6845 fixP->fx_addnumber = value;
6846
6847 switch (fixP->fx_r_type)
6848 {
6849 case BFD_RELOC_ARM_IMMEDIATE:
6850 newimm = validate_immediate (value);
6851 temp = md_chars_to_number (buf, INSN_SIZE);
6852
6853 /* If the instruction will fail, see if we can fix things up by
6854 changing the opcode. */
6855 if (newimm == (unsigned int) FAIL
6856 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
6857 {
6858 as_bad_where (fixP->fx_file, fixP->fx_line,
6859 _("invalid constant (%lx) after fixup"),
6860 (unsigned long) value);
6861 break;
6862 }
6863
6864 newimm |= (temp & 0xfffff000);
6865 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
6866 break;
6867
6868 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
6869 {
6870 unsigned int highpart = 0;
6871 unsigned int newinsn = 0xe1a00000; /* nop. */
6872 newimm = validate_immediate (value);
6873 temp = md_chars_to_number (buf, INSN_SIZE);
6874
6875 /* If the instruction will fail, see if we can fix things up by
6876 changing the opcode. */
6877 if (newimm == (unsigned int) FAIL
6878 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
6879 {
6880 /* No ? OK - try using two ADD instructions to generate
6881 the value. */
6882 newimm = validate_immediate_twopart (value, & highpart);
6883
6884 /* Yes - then make sure that the second instruction is
6885 also an add. */
6886 if (newimm != (unsigned int) FAIL)
6887 newinsn = temp;
6888 /* Still No ? Try using a negated value. */
6889 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
6890 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
6891 /* Otherwise - give up. */
6892 else
6893 {
6894 as_bad_where (fixP->fx_file, fixP->fx_line,
6895 _("Unable to compute ADRL instructions for PC offset of 0x%lx"),
6896 value);
6897 break;
6898 }
6899
6900 /* Replace the first operand in the 2nd instruction (which
6901 is the PC) with the destination register. We have
6902 already added in the PC in the first instruction and we
6903 do not want to do it again. */
6904 newinsn &= ~ 0xf0000;
6905 newinsn |= ((newinsn & 0x0f000) << 4);
6906 }
6907
6908 newimm |= (temp & 0xfffff000);
6909 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
6910
6911 highpart |= (newinsn & 0xfffff000);
6912 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
6913 }
6914 break;
6915
6916 case BFD_RELOC_ARM_OFFSET_IMM:
6917 sign = value >= 0;
6918
6919 if (value < 0)
6920 value = - value;
6921
6922 if (validate_offset_imm (value, 0) == FAIL)
6923 {
6924 as_bad_where (fixP->fx_file, fixP->fx_line,
6925 _("bad immediate value for offset (%ld)"),
6926 (long) value);
6927 break;
6928 }
6929
6930 newval = md_chars_to_number (buf, INSN_SIZE);
6931 newval &= 0xff7ff000;
6932 newval |= value | (sign ? INDEX_UP : 0);
6933 md_number_to_chars (buf, newval, INSN_SIZE);
6934 break;
6935
6936 case BFD_RELOC_ARM_OFFSET_IMM8:
6937 case BFD_RELOC_ARM_HWLITERAL:
6938 sign = value >= 0;
6939
6940 if (value < 0)
6941 value = - value;
6942
6943 if (validate_offset_imm (value, 1) == FAIL)
6944 {
6945 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
6946 as_bad_where (fixP->fx_file, fixP->fx_line,
6947 _("invalid literal constant: pool needs to be closer"));
6948 else
6949 as_bad (_("bad immediate value for half-word offset (%ld)"),
6950 (long) value);
6951 break;
6952 }
6953
6954 newval = md_chars_to_number (buf, INSN_SIZE);
6955 newval &= 0xff7ff0f0;
6956 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
6957 md_number_to_chars (buf, newval, INSN_SIZE);
6958 break;
6959
6960 case BFD_RELOC_ARM_LITERAL:
6961 sign = value >= 0;
6962
6963 if (value < 0)
6964 value = - value;
6965
6966 if (validate_offset_imm (value, 0) == FAIL)
6967 {
6968 as_bad_where (fixP->fx_file, fixP->fx_line,
6969 _("invalid literal constant: pool needs to be closer"));
6970 break;
6971 }
6972
6973 newval = md_chars_to_number (buf, INSN_SIZE);
6974 newval &= 0xff7ff000;
6975 newval |= value | (sign ? INDEX_UP : 0);
6976 md_number_to_chars (buf, newval, INSN_SIZE);
6977 break;
6978
6979 case BFD_RELOC_ARM_SHIFT_IMM:
6980 newval = md_chars_to_number (buf, INSN_SIZE);
6981 if (((unsigned long) value) > 32
6982 || (value == 32
6983 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
6984 {
6985 as_bad_where (fixP->fx_file, fixP->fx_line,
6986 _("shift expression is too large"));
6987 break;
6988 }
6989
6990 if (value == 0)
6991 /* Shifts of zero must be done as lsl. */
6992 newval &= ~0x60;
6993 else if (value == 32)
6994 value = 0;
6995 newval &= 0xfffff07f;
6996 newval |= (value & 0x1f) << 7;
6997 md_number_to_chars (buf, newval, INSN_SIZE);
6998 break;
6999
7000 case BFD_RELOC_ARM_SWI:
7001 if (arm_data->thumb_mode)
7002 {
7003 if (((unsigned long) value) > 0xff)
7004 as_bad_where (fixP->fx_file, fixP->fx_line,
7005 _("Invalid swi expression"));
7006 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
7007 newval |= value;
7008 md_number_to_chars (buf, newval, THUMB_SIZE);
7009 }
7010 else
7011 {
7012 if (((unsigned long) value) > 0x00ffffff)
7013 as_bad_where (fixP->fx_file, fixP->fx_line,
7014 _("Invalid swi expression"));
7015 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
7016 newval |= value;
7017 md_number_to_chars (buf, newval, INSN_SIZE);
7018 }
7019 break;
7020
7021 case BFD_RELOC_ARM_MULTI:
7022 if (((unsigned long) value) > 0xffff)
7023 as_bad_where (fixP->fx_file, fixP->fx_line,
7024 _("Invalid expression in load/store multiple"));
7025 newval = value | md_chars_to_number (buf, INSN_SIZE);
7026 md_number_to_chars (buf, newval, INSN_SIZE);
7027 break;
7028
7029 case BFD_RELOC_ARM_PCREL_BRANCH:
7030 newval = md_chars_to_number (buf, INSN_SIZE);
7031
7032 /* Sign-extend a 24-bit number. */
7033 #define SEXT24(x) ((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000)
7034
7035 #ifdef OBJ_ELF
7036 if (! target_oabi)
7037 value = fixP->fx_offset;
7038 #endif
7039
7040 /* We are going to store value (shifted right by two) in the
7041 instruction, in a 24 bit, signed field. Thus we need to check
7042 that none of the top 8 bits of the shifted value (top 7 bits of
7043 the unshifted, unsigned value) are set, or that they are all set. */
7044 if ((value & ~ ((offsetT) 0x1ffffff)) != 0
7045 && ((value & ~ ((offsetT) 0x1ffffff)) != ~ ((offsetT) 0x1ffffff)))
7046 {
7047 #ifdef OBJ_ELF
7048 /* Normally we would be stuck at this point, since we cannot store
7049 the absolute address that is the destination of the branch in the
7050 24 bits of the branch instruction. If however, we happen to know
7051 that the destination of the branch is in the same section as the
7052 branch instruciton itself, then we can compute the relocation for
7053 ourselves and not have to bother the linker with it.
7054
7055 FIXME: The tests for OBJ_ELF and ! target_oabi are only here
7056 because I have not worked out how to do this for OBJ_COFF or
7057 target_oabi. */
7058 if (! target_oabi
7059 && fixP->fx_addsy != NULL
7060 && S_IS_DEFINED (fixP->fx_addsy)
7061 && S_GET_SEGMENT (fixP->fx_addsy) == seg)
7062 {
7063 /* Get pc relative value to go into the branch. */
7064 value = * val;
7065
7066 /* Permit a backward branch provided that enough bits
7067 are set. Allow a forwards branch, provided that
7068 enough bits are clear. */
7069 if ( (value & ~ ((offsetT) 0x1ffffff)) == ~ ((offsetT) 0x1ffffff)
7070 || (value & ~ ((offsetT) 0x1ffffff)) == 0)
7071 fixP->fx_done = 1;
7072 }
7073
7074 if (! fixP->fx_done)
7075 #endif
7076 as_bad_where (fixP->fx_file, fixP->fx_line,
7077 _("gas can't handle same-section branch dest >= 0x04000000"));
7078 }
7079
7080 value >>= 2;
7081 value += SEXT24 (newval);
7082
7083 if ( (value & ~ ((offsetT) 0xffffff)) != 0
7084 && ((value & ~ ((offsetT) 0xffffff)) != ~ ((offsetT) 0xffffff)))
7085 as_bad_where (fixP->fx_file, fixP->fx_line,
7086 _("out of range branch"));
7087
7088 newval = (value & 0x00ffffff) | (newval & 0xff000000);
7089 md_number_to_chars (buf, newval, INSN_SIZE);
7090 break;
7091
7092 case BFD_RELOC_ARM_PCREL_BLX:
7093 {
7094 offsetT hbit;
7095 newval = md_chars_to_number (buf, INSN_SIZE);
7096
7097 #ifdef OBJ_ELF
7098 if (! target_oabi)
7099 value = fixP->fx_offset;
7100 #endif
7101 hbit = (value >> 1) & 1;
7102 value = (value >> 2) & 0x00ffffff;
7103 value = (value + (newval & 0x00ffffff)) & 0x00ffffff;
7104 newval = value | (newval & 0xfe000000) | (hbit << 24);
7105 md_number_to_chars (buf, newval, INSN_SIZE);
7106 }
7107 break;
7108
7109 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
7110 newval = md_chars_to_number (buf, THUMB_SIZE);
7111 {
7112 addressT diff = (newval & 0xff) << 1;
7113 if (diff & 0x100)
7114 diff |= ~0xff;
7115
7116 value += diff;
7117 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
7118 as_bad_where (fixP->fx_file, fixP->fx_line,
7119 _("Branch out of range"));
7120 newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
7121 }
7122 md_number_to_chars (buf, newval, THUMB_SIZE);
7123 break;
7124
7125 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
7126 newval = md_chars_to_number (buf, THUMB_SIZE);
7127 {
7128 addressT diff = (newval & 0x7ff) << 1;
7129 if (diff & 0x800)
7130 diff |= ~0x7ff;
7131
7132 value += diff;
7133 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
7134 as_bad_where (fixP->fx_file, fixP->fx_line,
7135 _("Branch out of range"));
7136 newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
7137 }
7138 md_number_to_chars (buf, newval, THUMB_SIZE);
7139 break;
7140
7141 case BFD_RELOC_THUMB_PCREL_BLX:
7142 case BFD_RELOC_THUMB_PCREL_BRANCH23:
7143 {
7144 offsetT newval2;
7145 addressT diff;
7146
7147 newval = md_chars_to_number (buf, THUMB_SIZE);
7148 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
7149 diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
7150 if (diff & 0x400000)
7151 diff |= ~0x3fffff;
7152 #ifdef OBJ_ELF
7153 value = fixP->fx_offset;
7154 #endif
7155 value += diff;
7156 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
7157 as_bad_where (fixP->fx_file, fixP->fx_line,
7158 _("Branch with link out of range"));
7159
7160 newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
7161 newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
7162 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
7163 /* Remove bit zero of the adjusted offset. Bit zero can only be
7164 set if the upper insn is at a half-word boundary, since the
7165 destination address, an ARM instruction, must always be on a
7166 word boundary. The semantics of the BLX (1) instruction, however,
7167 are that bit zero in the offset must always be zero, and the
7168 corresponding bit one in the target address will be set from bit
7169 one of the source address. */
7170 newval2 &= ~1;
7171 md_number_to_chars (buf, newval, THUMB_SIZE);
7172 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
7173 }
7174 break;
7175
7176 case BFD_RELOC_8:
7177 if (fixP->fx_done || fixP->fx_pcrel)
7178 md_number_to_chars (buf, value, 1);
7179 #ifdef OBJ_ELF
7180 else if (!target_oabi)
7181 {
7182 value = fixP->fx_offset;
7183 md_number_to_chars (buf, value, 1);
7184 }
7185 #endif
7186 break;
7187
7188 case BFD_RELOC_16:
7189 if (fixP->fx_done || fixP->fx_pcrel)
7190 md_number_to_chars (buf, value, 2);
7191 #ifdef OBJ_ELF
7192 else if (!target_oabi)
7193 {
7194 value = fixP->fx_offset;
7195 md_number_to_chars (buf, value, 2);
7196 }
7197 #endif
7198 break;
7199
7200 #ifdef OBJ_ELF
7201 case BFD_RELOC_ARM_GOT32:
7202 case BFD_RELOC_ARM_GOTOFF:
7203 md_number_to_chars (buf, 0, 4);
7204 break;
7205 #endif
7206
7207 case BFD_RELOC_RVA:
7208 case BFD_RELOC_32:
7209 if (fixP->fx_done || fixP->fx_pcrel)
7210 md_number_to_chars (buf, value, 4);
7211 #ifdef OBJ_ELF
7212 else if (!target_oabi)
7213 {
7214 value = fixP->fx_offset;
7215 md_number_to_chars (buf, value, 4);
7216 }
7217 #endif
7218 break;
7219
7220 #ifdef OBJ_ELF
7221 case BFD_RELOC_ARM_PLT32:
7222 /* It appears the instruction is fully prepared at this point. */
7223 break;
7224 #endif
7225
7226 case BFD_RELOC_ARM_GOTPC:
7227 md_number_to_chars (buf, value, 4);
7228 break;
7229
7230 case BFD_RELOC_ARM_CP_OFF_IMM:
7231 sign = value >= 0;
7232 if (value < -1023 || value > 1023 || (value & 3))
7233 as_bad_where (fixP->fx_file, fixP->fx_line,
7234 _("Illegal value for co-processor offset"));
7235 if (value < 0)
7236 value = -value;
7237 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
7238 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
7239 md_number_to_chars (buf, newval, INSN_SIZE);
7240 break;
7241
7242 case BFD_RELOC_ARM_THUMB_OFFSET:
7243 newval = md_chars_to_number (buf, THUMB_SIZE);
7244 /* Exactly what ranges, and where the offset is inserted depends
7245 on the type of instruction, we can establish this from the
7246 top 4 bits. */
7247 switch (newval >> 12)
7248 {
7249 case 4: /* PC load. */
7250 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
7251 forced to zero for these loads, so we will need to round
7252 up the offset if the instruction address is not word
7253 aligned (since the final address produced must be, and
7254 we can only describe word-aligned immediate offsets). */
7255
7256 if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3)
7257 as_bad_where (fixP->fx_file, fixP->fx_line,
7258 _("Invalid offset, target not word aligned (0x%08X)"),
7259 (unsigned int) (fixP->fx_frag->fr_address
7260 + fixP->fx_where + value));
7261
7262 if ((value + 2) & ~0x3fe)
7263 as_bad_where (fixP->fx_file, fixP->fx_line,
7264 _("Invalid offset, value too big (0x%08lX)"), value);
7265
7266 /* Round up, since pc will be rounded down. */
7267 newval |= (value + 2) >> 2;
7268 break;
7269
7270 case 9: /* SP load/store. */
7271 if (value & ~0x3fc)
7272 as_bad_where (fixP->fx_file, fixP->fx_line,
7273 _("Invalid offset, value too big (0x%08lX)"), value);
7274 newval |= value >> 2;
7275 break;
7276
7277 case 6: /* Word load/store. */
7278 if (value & ~0x7c)
7279 as_bad_where (fixP->fx_file, fixP->fx_line,
7280 _("Invalid offset, value too big (0x%08lX)"), value);
7281 newval |= value << 4; /* 6 - 2. */
7282 break;
7283
7284 case 7: /* Byte load/store. */
7285 if (value & ~0x1f)
7286 as_bad_where (fixP->fx_file, fixP->fx_line,
7287 _("Invalid offset, value too big (0x%08lX)"), value);
7288 newval |= value << 6;
7289 break;
7290
7291 case 8: /* Halfword load/store. */
7292 if (value & ~0x3e)
7293 as_bad_where (fixP->fx_file, fixP->fx_line,
7294 _("Invalid offset, value too big (0x%08lX)"), value);
7295 newval |= value << 5; /* 6 - 1. */
7296 break;
7297
7298 default:
7299 as_bad_where (fixP->fx_file, fixP->fx_line,
7300 "Unable to process relocation for thumb opcode: %lx",
7301 (unsigned long) newval);
7302 break;
7303 }
7304 md_number_to_chars (buf, newval, THUMB_SIZE);
7305 break;
7306
7307 case BFD_RELOC_ARM_THUMB_ADD:
7308 /* This is a complicated relocation, since we use it for all of
7309 the following immediate relocations:
7310
7311 3bit ADD/SUB
7312 8bit ADD/SUB
7313 9bit ADD/SUB SP word-aligned
7314 10bit ADD PC/SP word-aligned
7315
7316 The type of instruction being processed is encoded in the
7317 instruction field:
7318
7319 0x8000 SUB
7320 0x00F0 Rd
7321 0x000F Rs
7322 */
7323 newval = md_chars_to_number (buf, THUMB_SIZE);
7324 {
7325 int rd = (newval >> 4) & 0xf;
7326 int rs = newval & 0xf;
7327 int subtract = newval & 0x8000;
7328
7329 if (rd == REG_SP)
7330 {
7331 if (value & ~0x1fc)
7332 as_bad_where (fixP->fx_file, fixP->fx_line,
7333 _("Invalid immediate for stack address calculation"));
7334 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
7335 newval |= value >> 2;
7336 }
7337 else if (rs == REG_PC || rs == REG_SP)
7338 {
7339 if (subtract ||
7340 value & ~0x3fc)
7341 as_bad_where (fixP->fx_file, fixP->fx_line,
7342 _("Invalid immediate for address calculation (value = 0x%08lX)"),
7343 (unsigned long) value);
7344 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
7345 newval |= rd << 8;
7346 newval |= value >> 2;
7347 }
7348 else if (rs == rd)
7349 {
7350 if (value & ~0xff)
7351 as_bad_where (fixP->fx_file, fixP->fx_line,
7352 _("Invalid 8bit immediate"));
7353 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
7354 newval |= (rd << 8) | value;
7355 }
7356 else
7357 {
7358 if (value & ~0x7)
7359 as_bad_where (fixP->fx_file, fixP->fx_line,
7360 _("Invalid 3bit immediate"));
7361 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
7362 newval |= rd | (rs << 3) | (value << 6);
7363 }
7364 }
7365 md_number_to_chars (buf, newval, THUMB_SIZE);
7366 break;
7367
7368 case BFD_RELOC_ARM_THUMB_IMM:
7369 newval = md_chars_to_number (buf, THUMB_SIZE);
7370 switch (newval >> 11)
7371 {
7372 case 0x04: /* 8bit immediate MOV. */
7373 case 0x05: /* 8bit immediate CMP. */
7374 if (value < 0 || value > 255)
7375 as_bad_where (fixP->fx_file, fixP->fx_line,
7376 _("Invalid immediate: %ld is too large"),
7377 (long) value);
7378 newval |= value;
7379 break;
7380
7381 default:
7382 abort ();
7383 }
7384 md_number_to_chars (buf, newval, THUMB_SIZE);
7385 break;
7386
7387 case BFD_RELOC_ARM_THUMB_SHIFT:
7388 /* 5bit shift value (0..31). */
7389 if (value < 0 || value > 31)
7390 as_bad_where (fixP->fx_file, fixP->fx_line,
7391 _("Illegal Thumb shift value: %ld"), (long) value);
7392 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f;
7393 newval |= value << 6;
7394 md_number_to_chars (buf, newval, THUMB_SIZE);
7395 break;
7396
7397 case BFD_RELOC_VTABLE_INHERIT:
7398 case BFD_RELOC_VTABLE_ENTRY:
7399 fixP->fx_done = 0;
7400 return 1;
7401
7402 case BFD_RELOC_NONE:
7403 default:
7404 as_bad_where (fixP->fx_file, fixP->fx_line,
7405 _("Bad relocation fixup type (%d)"), fixP->fx_r_type);
7406 }
7407
7408 return 1;
7409 }
7410
7411 /* Translate internal representation of relocation info to BFD target
7412 format. */
7413
7414 arelent *
7415 tc_gen_reloc (section, fixp)
7416 asection * section ATTRIBUTE_UNUSED;
7417 fixS * fixp;
7418 {
7419 arelent * reloc;
7420 bfd_reloc_code_real_type code;
7421
7422 reloc = (arelent *) xmalloc (sizeof (arelent));
7423
7424 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7425 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
7426 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
7427
7428 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
7429 #ifndef OBJ_ELF
7430 if (fixp->fx_pcrel == 0)
7431 reloc->addend = fixp->fx_offset;
7432 else
7433 reloc->addend = fixp->fx_offset = reloc->address;
7434 #else /* OBJ_ELF */
7435 reloc->addend = fixp->fx_offset;
7436 #endif
7437
7438 switch (fixp->fx_r_type)
7439 {
7440 case BFD_RELOC_8:
7441 if (fixp->fx_pcrel)
7442 {
7443 code = BFD_RELOC_8_PCREL;
7444 break;
7445 }
7446
7447 case BFD_RELOC_16:
7448 if (fixp->fx_pcrel)
7449 {
7450 code = BFD_RELOC_16_PCREL;
7451 break;
7452 }
7453
7454 case BFD_RELOC_32:
7455 if (fixp->fx_pcrel)
7456 {
7457 code = BFD_RELOC_32_PCREL;
7458 break;
7459 }
7460
7461 case BFD_RELOC_ARM_PCREL_BRANCH:
7462 case BFD_RELOC_ARM_PCREL_BLX:
7463 case BFD_RELOC_RVA:
7464 case BFD_RELOC_THUMB_PCREL_BRANCH9:
7465 case BFD_RELOC_THUMB_PCREL_BRANCH12:
7466 case BFD_RELOC_THUMB_PCREL_BRANCH23:
7467 case BFD_RELOC_THUMB_PCREL_BLX:
7468 case BFD_RELOC_VTABLE_ENTRY:
7469 case BFD_RELOC_VTABLE_INHERIT:
7470 code = fixp->fx_r_type;
7471 break;
7472
7473 case BFD_RELOC_ARM_LITERAL:
7474 case BFD_RELOC_ARM_HWLITERAL:
7475 /* If this is called then the a literal has been referenced across
7476 a section boundary - possibly due to an implicit dump. */
7477 as_bad_where (fixp->fx_file, fixp->fx_line,
7478 _("Literal referenced across section boundary (Implicit dump?)"));
7479 return NULL;
7480
7481 #ifdef OBJ_ELF
7482 case BFD_RELOC_ARM_GOT32:
7483 case BFD_RELOC_ARM_GOTOFF:
7484 case BFD_RELOC_ARM_PLT32:
7485 code = fixp->fx_r_type;
7486 break;
7487 #endif
7488
7489 case BFD_RELOC_ARM_IMMEDIATE:
7490 as_bad_where (fixp->fx_file, fixp->fx_line,
7491 _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
7492 fixp->fx_r_type);
7493 return NULL;
7494
7495 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
7496 as_bad_where (fixp->fx_file, fixp->fx_line,
7497 _("ADRL used for a symbol not defined in the same file"));
7498 return NULL;
7499
7500 case BFD_RELOC_ARM_OFFSET_IMM:
7501 as_bad_where (fixp->fx_file, fixp->fx_line,
7502 _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
7503 fixp->fx_r_type);
7504 return NULL;
7505
7506 default:
7507 {
7508 char * type;
7509
7510 switch (fixp->fx_r_type)
7511 {
7512 case BFD_RELOC_ARM_IMMEDIATE: type = "IMMEDIATE"; break;
7513 case BFD_RELOC_ARM_OFFSET_IMM: type = "OFFSET_IMM"; break;
7514 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
7515 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
7516 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
7517 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
7518 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
7519 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
7520 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
7521 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
7522 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
7523 default: type = _("<unknown>"); break;
7524 }
7525 as_bad_where (fixp->fx_file, fixp->fx_line,
7526 _("Cannot represent %s relocation in this object file format"),
7527 type);
7528 return NULL;
7529 }
7530 }
7531
7532 #ifdef OBJ_ELF
7533 if (code == BFD_RELOC_32_PCREL
7534 && GOT_symbol
7535 && fixp->fx_addsy == GOT_symbol)
7536 {
7537 code = BFD_RELOC_ARM_GOTPC;
7538 reloc->addend = fixp->fx_offset = reloc->address;
7539 }
7540 #endif
7541
7542 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
7543
7544 if (reloc->howto == NULL)
7545 {
7546 as_bad_where (fixp->fx_file, fixp->fx_line,
7547 _("Can not represent %s relocation in this object file format"),
7548 bfd_get_reloc_code_name (code));
7549 return NULL;
7550 }
7551
7552 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
7553 vtable entry to be used in the relocation's section offset. */
7554 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7555 reloc->address = fixp->fx_offset;
7556
7557 return reloc;
7558 }
7559
7560 int
7561 md_estimate_size_before_relax (fragP, segtype)
7562 fragS * fragP ATTRIBUTE_UNUSED;
7563 segT segtype ATTRIBUTE_UNUSED;
7564 {
7565 as_fatal (_("md_estimate_size_before_relax\n"));
7566 return 1;
7567 }
7568
7569 static void
7570 output_inst PARAMS ((void))
7571 {
7572 char * to = NULL;
7573
7574 if (inst.error)
7575 {
7576 as_bad (inst.error);
7577 return;
7578 }
7579
7580 to = frag_more (inst.size);
7581
7582 if (thumb_mode && (inst.size > THUMB_SIZE))
7583 {
7584 assert (inst.size == (2 * THUMB_SIZE));
7585 md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
7586 md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE);
7587 }
7588 else if (inst.size > INSN_SIZE)
7589 {
7590 assert (inst.size == (2 * INSN_SIZE));
7591 md_number_to_chars (to, inst.instruction, INSN_SIZE);
7592 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
7593 }
7594 else
7595 md_number_to_chars (to, inst.instruction, inst.size);
7596
7597 if (inst.reloc.type != BFD_RELOC_NONE)
7598 fix_new_arm (frag_now, to - frag_now->fr_literal,
7599 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
7600 inst.reloc.type);
7601
7602 #ifdef OBJ_ELF
7603 dwarf2_emit_insn (inst.size);
7604 #endif
7605 }
7606
7607 void
7608 md_assemble (str)
7609 char * str;
7610 {
7611 char c;
7612 char * p;
7613 char * q;
7614 char * start;
7615
7616 /* Align the instruction.
7617 This may not be the right thing to do but ... */
7618 #if 0
7619 arm_align (2, 0);
7620 #endif
7621 listing_prev_line (); /* Defined in listing.h. */
7622
7623 /* Align the previous label if needed. */
7624 if (last_label_seen != NULL)
7625 {
7626 symbol_set_frag (last_label_seen, frag_now);
7627 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
7628 S_SET_SEGMENT (last_label_seen, now_seg);
7629 }
7630
7631 memset (&inst, '\0', sizeof (inst));
7632 inst.reloc.type = BFD_RELOC_NONE;
7633
7634 skip_whitespace (str);
7635
7636 /* Scan up to the end of the op-code, which must end in white space or
7637 end of string. */
7638 for (start = p = str; *p != '\0'; p++)
7639 if (*p == ' ')
7640 break;
7641
7642 if (p == str)
7643 {
7644 as_bad (_("No operator -- statement `%s'\n"), str);
7645 return;
7646 }
7647
7648 if (thumb_mode)
7649 {
7650 CONST struct thumb_opcode * opcode;
7651
7652 c = *p;
7653 *p = '\0';
7654 opcode = (CONST struct thumb_opcode *) hash_find (arm_tops_hsh, str);
7655 *p = c;
7656
7657 if (opcode)
7658 {
7659 /* Check that this instruction is supported for this CPU. */
7660 if (thumb_mode == 1 && (opcode->variants & cpu_variant) == 0)
7661 {
7662 as_bad (_("selected processor does not support this opcode"));
7663 return;
7664 }
7665
7666 inst.instruction = opcode->value;
7667 inst.size = opcode->size;
7668 (*opcode->parms) (p);
7669 output_inst ();
7670 return;
7671 }
7672 }
7673 else
7674 {
7675 CONST struct asm_opcode * opcode;
7676 unsigned long cond_code;
7677
7678 inst.size = INSN_SIZE;
7679 /* P now points to the end of the opcode, probably white space, but we
7680 have to break the opcode up in case it contains condionals and flags;
7681 keep trying with progressively smaller basic instructions until one
7682 matches, or we run out of opcode. */
7683 q = (p - str > LONGEST_INST) ? str + LONGEST_INST : p;
7684
7685 for (; q != str; q--)
7686 {
7687 c = *q;
7688 *q = '\0';
7689
7690 opcode = (CONST struct asm_opcode *) hash_find (arm_ops_hsh, str);
7691 *q = c;
7692
7693 if (opcode && opcode->template)
7694 {
7695 unsigned long flag_bits = 0;
7696 char * r;
7697
7698 /* Check that this instruction is supported for this CPU. */
7699 if ((opcode->variants & cpu_variant) == 0)
7700 goto try_shorter;
7701
7702 inst.instruction = opcode->value;
7703 if (q == p) /* Just a simple opcode. */
7704 {
7705 if (opcode->comp_suffix)
7706 {
7707 if (*opcode->comp_suffix != '\0')
7708 as_bad (_("Opcode `%s' must have suffix from list: <%s>"),
7709 str, opcode->comp_suffix);
7710 else
7711 /* Not a conditional instruction. */
7712 (*opcode->parms) (q, 0);
7713 }
7714 else
7715 {
7716 /* A conditional instruction with default condition. */
7717 inst.instruction |= COND_ALWAYS;
7718 (*opcode->parms) (q, 0);
7719 }
7720 output_inst ();
7721 return;
7722 }
7723
7724 /* Not just a simple opcode. Check if extra is a
7725 conditional. */
7726 r = q;
7727 if (p - r >= 2)
7728 {
7729 CONST struct asm_cond *cond;
7730 char d = *(r + 2);
7731
7732 *(r + 2) = '\0';
7733 cond = (CONST struct asm_cond *) hash_find (arm_cond_hsh, r);
7734 *(r + 2) = d;
7735 if (cond)
7736 {
7737 if (cond->value == 0xf0000000)
7738 as_tsktsk (
7739 _("Warning: Use of the 'nv' conditional is deprecated\n"));
7740
7741 cond_code = cond->value;
7742 r += 2;
7743 }
7744 else
7745 cond_code = COND_ALWAYS;
7746 }
7747 else
7748 cond_code = COND_ALWAYS;
7749
7750 /* Apply the conditional, or complain it's not allowed. */
7751 if (opcode->comp_suffix && *opcode->comp_suffix == '\0')
7752 {
7753 /* Instruction isn't conditional. */
7754 if (cond_code != COND_ALWAYS)
7755 {
7756 as_bad (_("Opcode `%s' is unconditional\n"), str);
7757 return;
7758 }
7759 }
7760 else
7761 /* Instruction is conditional: set the condition into it. */
7762 inst.instruction |= cond_code;
7763
7764 /* If there is a compulsory suffix, it should come here
7765 before any optional flags. */
7766 if (opcode->comp_suffix && *opcode->comp_suffix != '\0')
7767 {
7768 CONST char *s = opcode->comp_suffix;
7769
7770 while (*s)
7771 {
7772 inst.suffix++;
7773 if (*r == *s)
7774 break;
7775 s++;
7776 }
7777
7778 if (*s == '\0')
7779 {
7780 as_bad (_("Opcode `%s' must have suffix from <%s>\n"),
7781 str, opcode->comp_suffix);
7782 return;
7783 }
7784
7785 r++;
7786 }
7787
7788 /* The remainder, if any should now be flags for the instruction;
7789 Scan these checking each one found with the opcode. */
7790 if (r != p)
7791 {
7792 char d;
7793 CONST struct asm_flg *flag = opcode->flags;
7794
7795 if (flag)
7796 {
7797 int flagno;
7798
7799 d = *p;
7800 *p = '\0';
7801
7802 for (flagno = 0; flag[flagno].template; flagno++)
7803 {
7804 if (streq (r, flag[flagno].template))
7805 {
7806 flag_bits |= flag[flagno].set_bits;
7807 break;
7808 }
7809 }
7810
7811 *p = d;
7812 if (! flag[flagno].template)
7813 goto try_shorter;
7814 }
7815 else
7816 goto try_shorter;
7817 }
7818
7819 (*opcode->parms) (p, flag_bits);
7820 output_inst ();
7821 return;
7822 }
7823
7824 try_shorter:
7825 ;
7826 }
7827 }
7828
7829 /* It wasn't an instruction, but it might be a register alias of the form
7830 alias .req reg. */
7831 q = p;
7832 skip_whitespace (q);
7833
7834 c = *p;
7835 *p = '\0';
7836
7837 if (*q && !strncmp (q, ".req ", 4))
7838 {
7839 int reg;
7840 char * copy_of_str;
7841 char * r;
7842
7843 #ifdef IGNORE_OPCODE_CASE
7844 str = original_case_string;
7845 #endif
7846 copy_of_str = str;
7847
7848 q += 4;
7849 skip_whitespace (q);
7850
7851 for (r = q; *r != '\0'; r++)
7852 if (*r == ' ')
7853 break;
7854
7855 if (r != q)
7856 {
7857 int regnum;
7858 char d = *r;
7859
7860 *r = '\0';
7861 regnum = arm_reg_parse (& q);
7862 *r = d;
7863
7864 reg = arm_reg_parse (& str);
7865
7866 if (reg == FAIL)
7867 {
7868 if (regnum != FAIL)
7869 insert_reg_alias (str, regnum);
7870 else
7871 as_warn (_("register '%s' does not exist\n"), q);
7872 }
7873 else if (regnum != FAIL)
7874 {
7875 if (reg != regnum)
7876 as_warn (_("ignoring redefinition of register alias '%s'"),
7877 copy_of_str);
7878
7879 /* Do not warn about redefinitions to the same alias. */
7880 }
7881 else
7882 as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
7883 copy_of_str, q);
7884 }
7885 else
7886 as_warn (_("ignoring incomplete .req pseuso op"));
7887
7888 *p = c;
7889 return;
7890 }
7891
7892 *p = c;
7893 as_bad (_("bad instruction `%s'"), start);
7894 }
7895
7896 /* md_parse_option
7897 Invocation line includes a switch not recognized by the base assembler.
7898 See if it's a processor-specific option. These are:
7899 Cpu variants, the arm part is optional:
7900 -m[arm]1 Currently not supported.
7901 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
7902 -m[arm]3 Arm 3 processor
7903 -m[arm]6[xx], Arm 6 processors
7904 -m[arm]7[xx][t][[d]m] Arm 7 processors
7905 -m[arm]8[10] Arm 8 processors
7906 -m[arm]9[20][tdmi] Arm 9 processors
7907 -mstrongarm[110[0]] StrongARM processors
7908 -mxscale XScale processors
7909 -m[arm]v[2345[t[e]]] Arm architectures
7910 -mall All (except the ARM1)
7911 FP variants:
7912 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
7913 -mfpe-old (No float load/store multiples)
7914 -mno-fpu Disable all floating point instructions
7915 Run-time endian selection:
7916 -EB big endian cpu
7917 -EL little endian cpu
7918 ARM Procedure Calling Standard:
7919 -mapcs-32 32 bit APCS
7920 -mapcs-26 26 bit APCS
7921 -mapcs-float Pass floats in float regs
7922 -mapcs-reentrant Position independent code
7923 -mthumb-interwork Code supports Arm/Thumb interworking
7924 -matpcs ARM/Thumb Procedure Call Standard
7925 -moabi Old ELF ABI */
7926
7927 CONST char * md_shortopts = "m:k";
7928
7929 struct option md_longopts[] =
7930 {
7931 #ifdef ARM_BI_ENDIAN
7932 #define OPTION_EB (OPTION_MD_BASE + 0)
7933 {"EB", no_argument, NULL, OPTION_EB},
7934 #define OPTION_EL (OPTION_MD_BASE + 1)
7935 {"EL", no_argument, NULL, OPTION_EL},
7936 #ifdef OBJ_ELF
7937 #define OPTION_OABI (OPTION_MD_BASE +2)
7938 {"oabi", no_argument, NULL, OPTION_OABI},
7939 #endif
7940 #endif
7941 {NULL, no_argument, NULL, 0}
7942 };
7943
7944 size_t md_longopts_size = sizeof (md_longopts);
7945
7946 int
7947 md_parse_option (c, arg)
7948 int c;
7949 char * arg;
7950 {
7951 char * str = arg;
7952
7953 switch (c)
7954 {
7955 #ifdef ARM_BI_ENDIAN
7956 case OPTION_EB:
7957 target_big_endian = 1;
7958 break;
7959 case OPTION_EL:
7960 target_big_endian = 0;
7961 break;
7962 #endif
7963
7964 case 'm':
7965 switch (*str)
7966 {
7967 case 'f':
7968 if (streq (str, "fpa10"))
7969 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA10;
7970 else if (streq (str, "fpa11"))
7971 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA11;
7972 else if (streq (str, "fpe-old"))
7973 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_CORE;
7974 else
7975 goto bad;
7976 break;
7977
7978 case 'n':
7979 if (streq (str, "no-fpu"))
7980 cpu_variant &= ~FPU_ALL;
7981 break;
7982
7983 #ifdef OBJ_ELF
7984 case 'o':
7985 if (streq (str, "oabi"))
7986 target_oabi = true;
7987 break;
7988 #endif
7989
7990 case 't':
7991 /* Limit assembler to generating only Thumb instructions: */
7992 if (streq (str, "thumb"))
7993 {
7994 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_EXT_THUMB;
7995 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_NONE;
7996 thumb_mode = 1;
7997 }
7998 else if (streq (str, "thumb-interwork"))
7999 {
8000 if ((cpu_variant & ARM_EXT_THUMB) == 0)
8001 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4T;
8002 #if defined OBJ_COFF || defined OBJ_ELF
8003 support_interwork = true;
8004 #endif
8005 }
8006 else
8007 goto bad;
8008 break;
8009
8010 default:
8011 if (streq (str, "all"))
8012 {
8013 cpu_variant = ARM_ALL | FPU_ALL;
8014 return 1;
8015 }
8016 #if defined OBJ_COFF || defined OBJ_ELF
8017 if (! strncmp (str, "apcs-", 5))
8018 {
8019 /* GCC passes on all command line options starting "-mapcs-..."
8020 to us, so we must parse them here. */
8021
8022 str += 5;
8023
8024 if (streq (str, "32"))
8025 {
8026 uses_apcs_26 = false;
8027 return 1;
8028 }
8029 else if (streq (str, "26"))
8030 {
8031 uses_apcs_26 = true;
8032 return 1;
8033 }
8034 else if (streq (str, "frame"))
8035 {
8036 /* Stack frames are being generated - does not affect
8037 linkage of code. */
8038 return 1;
8039 }
8040 else if (streq (str, "stack-check"))
8041 {
8042 /* Stack checking is being performed - does not affect
8043 linkage, but does require that the functions
8044 __rt_stkovf_split_small and __rt_stkovf_split_big be
8045 present in the final link. */
8046
8047 return 1;
8048 }
8049 else if (streq (str, "float"))
8050 {
8051 /* Floating point arguments are being passed in the floating
8052 point registers. This does affect linking, since this
8053 version of the APCS is incompatible with the version that
8054 passes floating points in the integer registers. */
8055
8056 uses_apcs_float = true;
8057 return 1;
8058 }
8059 else if (streq (str, "reentrant"))
8060 {
8061 /* Reentrant code has been generated. This does affect
8062 linking, since there is no point in linking reentrant/
8063 position independent code with absolute position code. */
8064 pic_code = true;
8065 return 1;
8066 }
8067
8068 as_bad (_("Unrecognised APCS switch -m%s"), arg);
8069 return 0;
8070 }
8071
8072 if (! strcmp (str, "atpcs"))
8073 {
8074 atpcs = true;
8075 return 1;
8076 }
8077 #endif
8078 /* Strip off optional "arm". */
8079 if (! strncmp (str, "arm", 3))
8080 str += 3;
8081
8082 switch (*str)
8083 {
8084 case '1':
8085 if (streq (str, "1"))
8086 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_1;
8087 else
8088 goto bad;
8089 break;
8090
8091 case '2':
8092 if (streq (str, "2"))
8093 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
8094 else if (streq (str, "250"))
8095 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_250;
8096 else
8097 goto bad;
8098 break;
8099
8100 case '3':
8101 if (streq (str, "3"))
8102 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
8103 else
8104 goto bad;
8105 break;
8106
8107 case '6':
8108 switch (strtol (str, NULL, 10))
8109 {
8110 case 6:
8111 case 60:
8112 case 600:
8113 case 610:
8114 case 620:
8115 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_6;
8116 break;
8117 default:
8118 goto bad;
8119 }
8120 break;
8121
8122 case '7':
8123 /* Eat the processor name. */
8124 switch (strtol (str, & str, 10))
8125 {
8126 case 7:
8127 case 70:
8128 case 700:
8129 case 710:
8130 case 720:
8131 case 7100:
8132 case 7500:
8133 break;
8134 default:
8135 goto bad;
8136 }
8137 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
8138 for (; *str; str++)
8139 {
8140 switch (*str)
8141 {
8142 case 't':
8143 cpu_variant |= ARM_ARCH_V4T;
8144 break;
8145
8146 case 'm':
8147 cpu_variant |= ARM_EXT_LONGMUL;
8148 break;
8149
8150 case 'f': /* fe => fp enabled cpu. */
8151 if (str[1] == 'e')
8152 ++ str;
8153 else
8154 goto bad;
8155
8156 case 'c': /* Left over from 710c processor name. */
8157 case 'd': /* Debug. */
8158 case 'i': /* Embedded ICE. */
8159 /* Included for completeness in ARM processor naming. */
8160 break;
8161
8162 default:
8163 goto bad;
8164 }
8165 }
8166 break;
8167
8168 case '8':
8169 if (streq (str, "8") || streq (str, "810"))
8170 cpu_variant = (cpu_variant & ~ARM_ANY)
8171 | ARM_8 | ARM_ARCH_V4;
8172 else
8173 goto bad;
8174 break;
8175
8176 case '9':
8177 if (streq (str, "9"))
8178 cpu_variant = (cpu_variant & ~ARM_ANY)
8179 | ARM_9 | ARM_ARCH_V4T;
8180 else if (streq (str, "920"))
8181 cpu_variant = (cpu_variant & ~ARM_ANY)
8182 | ARM_9 | ARM_ARCH_V4;
8183 else if (streq (str, "920t"))
8184 cpu_variant = (cpu_variant & ~ARM_ANY)
8185 | ARM_9 | ARM_ARCH_V4T;
8186 else if (streq (str, "9tdmi"))
8187 cpu_variant = (cpu_variant & ~ARM_ANY)
8188 | ARM_9 | ARM_ARCH_V4T;
8189 else
8190 goto bad;
8191 break;
8192
8193 case 's':
8194 if (streq (str, "strongarm")
8195 || streq (str, "strongarm110")
8196 || streq (str, "strongarm1100"))
8197 cpu_variant = (cpu_variant & ~ARM_ANY)
8198 | ARM_8 | ARM_ARCH_V4;
8199 else
8200 goto bad;
8201 break;
8202
8203 case 'x':
8204 if (streq (str, "xscale"))
8205 cpu_variant = ARM_9 | ARM_ARCH_XSCALE;
8206 else
8207 goto bad;
8208 break;
8209
8210 case 'v':
8211 /* Select variant based on architecture rather than
8212 processor. */
8213 switch (*++str)
8214 {
8215 case '2':
8216 switch (*++str)
8217 {
8218 case 'a':
8219 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
8220 break;
8221 case 0:
8222 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
8223 break;
8224 default:
8225 as_bad (_("Invalid architecture variant -m%s"), arg);
8226 break;
8227 }
8228 break;
8229
8230 case '3':
8231 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
8232
8233 switch (*++str)
8234 {
8235 case 'm': cpu_variant |= ARM_EXT_LONGMUL; break;
8236 case 0: break;
8237 default:
8238 as_bad (_("Invalid architecture variant -m%s"), arg);
8239 break;
8240 }
8241 break;
8242
8243 case '4':
8244 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7 | ARM_ARCH_V4;
8245
8246 switch (*++str)
8247 {
8248 case 't': cpu_variant |= ARM_EXT_THUMB; break;
8249 case 0: break;
8250 default:
8251 as_bad (_("Invalid architecture variant -m%s"), arg);
8252 break;
8253 }
8254 break;
8255
8256 case '5':
8257 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_9 | ARM_ARCH_V5;
8258 switch (*++str)
8259 {
8260 case 't': cpu_variant |= ARM_EXT_THUMB; break;
8261 case 'e': cpu_variant |= ARM_EXT_V5E; break;
8262 case 0: break;
8263 default:
8264 as_bad (_("Invalid architecture variant -m%s"), arg);
8265 break;
8266 }
8267 break;
8268
8269 default:
8270 as_bad (_("Invalid architecture variant -m%s"), arg);
8271 break;
8272 }
8273 break;
8274
8275 default:
8276 bad:
8277 as_bad (_("Invalid processor variant -m%s"), arg);
8278 return 0;
8279 }
8280 }
8281 break;
8282
8283 #if defined OBJ_ELF || defined OBJ_COFF
8284 case 'k':
8285 pic_code = 1;
8286 break;
8287 #endif
8288
8289 default:
8290 return 0;
8291 }
8292
8293 return 1;
8294 }
8295
8296 void
8297 md_show_usage (fp)
8298 FILE * fp;
8299 {
8300 fprintf (fp, _("\
8301 ARM Specific Assembler Options:\n\
8302 -m[arm][<processor name>] select processor variant\n\
8303 -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
8304 -mthumb only allow Thumb instructions\n\
8305 -mthumb-interwork mark the assembled code as supporting interworking\n\
8306 -mall allow any instruction\n\
8307 -mfpa10, -mfpa11 select floating point architecture\n\
8308 -mfpe-old don't allow floating-point multiple instructions\n\
8309 -mno-fpu don't allow any floating-point instructions.\n\
8310 -k generate PIC code.\n"));
8311 #if defined OBJ_COFF || defined OBJ_ELF
8312 fprintf (fp, _("\
8313 -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n\
8314 -matpcs use ARM/Thumb Procedure Calling Standard\n\
8315 -mapcs-float floating point args are passed in FP regs\n\
8316 -mapcs-reentrant the code is position independent/reentrant\n"));
8317 #endif
8318 #ifdef OBJ_ELF
8319 fprintf (fp, _("\
8320 -moabi support the old ELF ABI\n"));
8321 #endif
8322 #ifdef ARM_BI_ENDIAN
8323 fprintf (fp, _("\
8324 -EB assemble code for a big endian cpu\n\
8325 -EL assemble code for a little endian cpu\n"));
8326 #endif
8327 }
8328
8329 /* We need to be able to fix up arbitrary expressions in some statements.
8330 This is so that we can handle symbols that are an arbitrary distance from
8331 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
8332 which returns part of an address in a form which will be valid for
8333 a data instruction. We do this by pushing the expression into a symbol
8334 in the expr_section, and creating a fix for that. */
8335
8336 static void
8337 fix_new_arm (frag, where, size, exp, pc_rel, reloc)
8338 fragS * frag;
8339 int where;
8340 short int size;
8341 expressionS * exp;
8342 int pc_rel;
8343 int reloc;
8344 {
8345 fixS * new_fix;
8346 arm_fix_data * arm_data;
8347
8348 switch (exp->X_op)
8349 {
8350 case O_constant:
8351 case O_symbol:
8352 case O_add:
8353 case O_subtract:
8354 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
8355 break;
8356
8357 default:
8358 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
8359 pc_rel, reloc);
8360 break;
8361 }
8362
8363 /* Mark whether the fix is to a THUMB instruction, or an ARM
8364 instruction. */
8365 arm_data = (arm_fix_data *) obstack_alloc (& notes, sizeof (arm_fix_data));
8366 new_fix->tc_fix_data = (PTR) arm_data;
8367 arm_data->thumb_mode = thumb_mode;
8368
8369 return;
8370 }
8371
8372 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
8373
8374 void
8375 cons_fix_new_arm (frag, where, size, exp)
8376 fragS * frag;
8377 int where;
8378 int size;
8379 expressionS * exp;
8380 {
8381 bfd_reloc_code_real_type type;
8382 int pcrel = 0;
8383
8384 /* Pick a reloc.
8385 FIXME: @@ Should look at CPU word size. */
8386 switch (size)
8387 {
8388 case 1:
8389 type = BFD_RELOC_8;
8390 break;
8391 case 2:
8392 type = BFD_RELOC_16;
8393 break;
8394 case 4:
8395 default:
8396 type = BFD_RELOC_32;
8397 break;
8398 case 8:
8399 type = BFD_RELOC_64;
8400 break;
8401 }
8402
8403 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
8404 }
8405
8406 /* A good place to do this, although this was probably not intended
8407 for this kind of use. We need to dump the literal pool before
8408 references are made to a null symbol pointer. */
8409
8410 void
8411 arm_cleanup ()
8412 {
8413 if (current_poolP == NULL)
8414 return;
8415
8416 /* Put it at the end of text section. */
8417 subseg_set (text_section, 0);
8418 s_ltorg (0);
8419 listing_prev_line ();
8420 }
8421
8422 void
8423 arm_start_line_hook ()
8424 {
8425 last_label_seen = NULL;
8426 }
8427
8428 void
8429 arm_frob_label (sym)
8430 symbolS * sym;
8431 {
8432 last_label_seen = sym;
8433
8434 ARM_SET_THUMB (sym, thumb_mode);
8435
8436 #if defined OBJ_COFF || defined OBJ_ELF
8437 ARM_SET_INTERWORK (sym, support_interwork);
8438 #endif
8439
8440 /* Note - do not allow local symbols (.Lxxx) to be labeled
8441 as Thumb functions. This is because these labels, whilst
8442 they exist inside Thumb code, are not the entry points for
8443 possible ARM->Thumb calls. Also, these labels can be used
8444 as part of a computed goto or switch statement. eg gcc
8445 can generate code that looks like this:
8446
8447 ldr r2, [pc, .Laaa]
8448 lsl r3, r3, #2
8449 ldr r2, [r3, r2]
8450 mov pc, r2
8451
8452 .Lbbb: .word .Lxxx
8453 .Lccc: .word .Lyyy
8454 ..etc...
8455 .Laaa: .word Lbbb
8456
8457 The first instruction loads the address of the jump table.
8458 The second instruction converts a table index into a byte offset.
8459 The third instruction gets the jump address out of the table.
8460 The fourth instruction performs the jump.
8461
8462 If the address stored at .Laaa is that of a symbol which has the
8463 Thumb_Func bit set, then the linker will arrange for this address
8464 to have the bottom bit set, which in turn would mean that the
8465 address computation performed by the third instruction would end
8466 up with the bottom bit set. Since the ARM is capable of unaligned
8467 word loads, the instruction would then load the incorrect address
8468 out of the jump table, and chaos would ensue. */
8469 if (label_is_thumb_function_name
8470 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
8471 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
8472 {
8473 /* When the address of a Thumb function is taken the bottom
8474 bit of that address should be set. This will allow
8475 interworking between Arm and Thumb functions to work
8476 correctly. */
8477
8478 THUMB_SET_FUNC (sym, 1);
8479
8480 label_is_thumb_function_name = false;
8481 }
8482 }
8483
8484 /* Adjust the symbol table. This marks Thumb symbols as distinct from
8485 ARM ones. */
8486
8487 void
8488 arm_adjust_symtab ()
8489 {
8490 #ifdef OBJ_COFF
8491 symbolS * sym;
8492
8493 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
8494 {
8495 if (ARM_IS_THUMB (sym))
8496 {
8497 if (THUMB_IS_FUNC (sym))
8498 {
8499 /* Mark the symbol as a Thumb function. */
8500 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
8501 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
8502 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
8503
8504 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
8505 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
8506 else
8507 as_bad (_("%s: unexpected function type: %d"),
8508 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
8509 }
8510 else switch (S_GET_STORAGE_CLASS (sym))
8511 {
8512 case C_EXT:
8513 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
8514 break;
8515 case C_STAT:
8516 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
8517 break;
8518 case C_LABEL:
8519 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
8520 break;
8521 default:
8522 /* Do nothing. */
8523 break;
8524 }
8525 }
8526
8527 if (ARM_IS_INTERWORK (sym))
8528 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
8529 }
8530 #endif
8531 #ifdef OBJ_ELF
8532 symbolS * sym;
8533 char bind;
8534
8535 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
8536 {
8537 if (ARM_IS_THUMB (sym))
8538 {
8539 elf_symbol_type * elf_sym;
8540
8541 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
8542 bind = ELF_ST_BIND (elf_sym);
8543
8544 /* If it's a .thumb_func, declare it as so,
8545 otherwise tag label as .code 16. */
8546 if (THUMB_IS_FUNC (sym))
8547 elf_sym->internal_elf_sym.st_info =
8548 ELF_ST_INFO (bind, STT_ARM_TFUNC);
8549 else
8550 elf_sym->internal_elf_sym.st_info =
8551 ELF_ST_INFO (bind, STT_ARM_16BIT);
8552 }
8553 }
8554 #endif
8555 }
8556
8557 int
8558 arm_data_in_code ()
8559 {
8560 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
8561 {
8562 *input_line_pointer = '/';
8563 input_line_pointer += 5;
8564 *input_line_pointer = 0;
8565 return 1;
8566 }
8567
8568 return 0;
8569 }
8570
8571 char *
8572 arm_canonicalize_symbol_name (name)
8573 char * name;
8574 {
8575 int len;
8576
8577 if (thumb_mode && (len = strlen (name)) > 5
8578 && streq (name + len - 5, "/data"))
8579 *(name + len - 5) = 0;
8580
8581 return name;
8582 }
8583
8584 boolean
8585 arm_validate_fix (fixP)
8586 fixS * fixP;
8587 {
8588 /* If the destination of the branch is a defined symbol which does not have
8589 the THUMB_FUNC attribute, then we must be calling a function which has
8590 the (interfacearm) attribute. We look for the Thumb entry point to that
8591 function and change the branch to refer to that function instead. */
8592 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
8593 && fixP->fx_addsy != NULL
8594 && S_IS_DEFINED (fixP->fx_addsy)
8595 && ! THUMB_IS_FUNC (fixP->fx_addsy))
8596 {
8597 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
8598 return true;
8599 }
8600
8601 return false;
8602 }
8603
8604 #ifdef OBJ_COFF
8605 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
8606 local labels from being added to the output symbol table when they
8607 are used with the ADRL pseudo op. The ADRL relocation should always
8608 be resolved before the binbary is emitted, so it is safe to say that
8609 it is adjustable. */
8610
8611 boolean
8612 arm_fix_adjustable (fixP)
8613 fixS * fixP;
8614 {
8615 if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
8616 return 1;
8617 return 0;
8618 }
8619 #endif
8620 #ifdef OBJ_ELF
8621 /* Relocations against Thumb function names must be left unadjusted,
8622 so that the linker can use this information to correctly set the
8623 bottom bit of their addresses. The MIPS version of this function
8624 also prevents relocations that are mips-16 specific, but I do not
8625 know why it does this.
8626
8627 FIXME:
8628 There is one other problem that ought to be addressed here, but
8629 which currently is not: Taking the address of a label (rather
8630 than a function) and then later jumping to that address. Such
8631 addresses also ought to have their bottom bit set (assuming that
8632 they reside in Thumb code), but at the moment they will not. */
8633
8634 boolean
8635 arm_fix_adjustable (fixP)
8636 fixS * fixP;
8637 {
8638 if (fixP->fx_addsy == NULL)
8639 return 1;
8640
8641 /* Prevent all adjustments to global symbols. */
8642 if (S_IS_EXTERN (fixP->fx_addsy))
8643 return 0;
8644
8645 if (S_IS_WEAK (fixP->fx_addsy))
8646 return 0;
8647
8648 if (THUMB_IS_FUNC (fixP->fx_addsy)
8649 && fixP->fx_subsy == NULL)
8650 return 0;
8651
8652 /* We need the symbol name for the VTABLE entries. */
8653 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
8654 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8655 return 0;
8656
8657 return 1;
8658 }
8659
8660 const char *
8661 elf32_arm_target_format ()
8662 {
8663 if (target_big_endian)
8664 {
8665 if (target_oabi)
8666 return "elf32-bigarm-oabi";
8667 else
8668 return "elf32-bigarm";
8669 }
8670 else
8671 {
8672 if (target_oabi)
8673 return "elf32-littlearm-oabi";
8674 else
8675 return "elf32-littlearm";
8676 }
8677 }
8678
8679 void
8680 armelf_frob_symbol (symp, puntp)
8681 symbolS * symp;
8682 int * puntp;
8683 {
8684 elf_frob_symbol (symp, puntp);
8685 }
8686
8687 int
8688 arm_force_relocation (fixp)
8689 struct fix * fixp;
8690 {
8691 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
8692 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
8693 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
8694 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
8695 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX
8696 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23)
8697 return 1;
8698
8699 return 0;
8700 }
8701
8702 static bfd_reloc_code_real_type
8703 arm_parse_reloc ()
8704 {
8705 char id [16];
8706 char * ip;
8707 unsigned int i;
8708 static struct
8709 {
8710 char * str;
8711 int len;
8712 bfd_reloc_code_real_type reloc;
8713 }
8714 reloc_map[] =
8715 {
8716 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
8717 MAP ("(got)", BFD_RELOC_ARM_GOT32),
8718 MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF),
8719 /* ScottB: Jan 30, 1998 - Added support for parsing "var(PLT)"
8720 branch instructions generated by GCC for PLT relocs. */
8721 MAP ("(plt)", BFD_RELOC_ARM_PLT32),
8722 { NULL, 0, BFD_RELOC_UNUSED }
8723 #undef MAP
8724 };
8725
8726 for (i = 0, ip = input_line_pointer;
8727 i < sizeof (id) && (isalnum (*ip) || ispunct (*ip));
8728 i++, ip++)
8729 id[i] = tolower (*ip);
8730
8731 for (i = 0; reloc_map[i].str; i++)
8732 if (strncmp (id, reloc_map[i].str, reloc_map[i].len) == 0)
8733 break;
8734
8735 input_line_pointer += reloc_map[i].len;
8736
8737 return reloc_map[i].reloc;
8738 }
8739
8740 static void
8741 s_arm_elf_cons (nbytes)
8742 int nbytes;
8743 {
8744 expressionS exp;
8745
8746 #ifdef md_flush_pending_output
8747 md_flush_pending_output ();
8748 #endif
8749
8750 if (is_it_end_of_statement ())
8751 {
8752 demand_empty_rest_of_line ();
8753 return;
8754 }
8755
8756 #ifdef md_cons_align
8757 md_cons_align (nbytes);
8758 #endif
8759
8760 do
8761 {
8762 bfd_reloc_code_real_type reloc;
8763
8764 expression (& exp);
8765
8766 if (exp.X_op == O_symbol
8767 && * input_line_pointer == '('
8768 && (reloc = arm_parse_reloc ()) != BFD_RELOC_UNUSED)
8769 {
8770 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
8771 int size = bfd_get_reloc_size (howto);
8772
8773 if (size > nbytes)
8774 as_bad ("%s relocations do not fit in %d bytes",
8775 howto->name, nbytes);
8776 else
8777 {
8778 register char *p = frag_more ((int) nbytes);
8779 int offset = nbytes - size;
8780
8781 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
8782 &exp, 0, reloc);
8783 }
8784 }
8785 else
8786 emit_expr (&exp, (unsigned int) nbytes);
8787 }
8788 while (*input_line_pointer++ == ',');
8789
8790 /* Put terminator back into stream. */
8791 input_line_pointer --;
8792 demand_empty_rest_of_line ();
8793 }
8794
8795 #endif /* OBJ_ELF */
8796
8797 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
8798 of an rs_align_code fragment. */
8799
8800 void
8801 arm_handle_align (fragP)
8802 fragS *fragP;
8803 {
8804 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
8805 static char const thumb_noop[2] = { 0xc0, 0x46 };
8806 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
8807 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
8808
8809 int bytes, fix, noop_size;
8810 char * p;
8811 const char * noop;
8812
8813 if (fragP->fr_type != rs_align_code)
8814 return;
8815
8816 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
8817 p = fragP->fr_literal + fragP->fr_fix;
8818 fix = 0;
8819
8820 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
8821 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
8822
8823 if (fragP->tc_frag_data)
8824 {
8825 if (target_big_endian)
8826 noop = thumb_bigend_noop;
8827 else
8828 noop = thumb_noop;
8829 noop_size = sizeof (thumb_noop);
8830 }
8831 else
8832 {
8833 if (target_big_endian)
8834 noop = arm_bigend_noop;
8835 else
8836 noop = arm_noop;
8837 noop_size = sizeof (arm_noop);
8838 }
8839
8840 if (bytes & (noop_size - 1))
8841 {
8842 fix = bytes & (noop_size - 1);
8843 memset (p, 0, fix);
8844 p += fix;
8845 bytes -= fix;
8846 }
8847
8848 while (bytes >= noop_size)
8849 {
8850 memcpy (p, noop, noop_size);
8851 p += noop_size;
8852 bytes -= noop_size;
8853 fix += noop_size;
8854 }
8855
8856 fragP->fr_fix += fix;
8857 fragP->fr_var = noop_size;
8858 }
8859
8860 /* Called from md_do_align. Used to create an alignment
8861 frag in a code section. */
8862
8863 void
8864 arm_frag_align_code (n, max)
8865 int n;
8866 int max;
8867 {
8868 char * p;
8869
8870 /* We assume that there will never be a requirment
8871 to support alignments greater than 32 bytes. */
8872 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
8873 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
8874
8875 p = frag_var (rs_align_code,
8876 MAX_MEM_FOR_RS_ALIGN_CODE,
8877 1,
8878 (relax_substateT) max,
8879 (symbolS *) NULL,
8880 (offsetT) n,
8881 (char *) NULL);
8882 *p = 0;
8883
8884 }
8885
8886 /* Perform target specific initialisation of a frag. */
8887
8888 void
8889 arm_init_frag (fragP)
8890 fragS *fragP;
8891 {
8892 /* Record whether this frag is in an ARM or a THUMB area. */
8893 fragP->tc_frag_data = thumb_mode;
8894 }
GDB Binutils - Deliverables
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