1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
189 static const arm_feature_set arm_ext_v6_notm
=
190 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
191 static const arm_feature_set arm_ext_v6_dsp
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
193 static const arm_feature_set arm_ext_barrier
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
195 static const arm_feature_set arm_ext_msr
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
197 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
198 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
199 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
200 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
201 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
202 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
203 static const arm_feature_set arm_ext_m
=
204 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
);
205 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
206 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
207 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
208 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
209 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
210 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
212 static const arm_feature_set arm_arch_any
= ARM_ANY
;
213 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1, -1);
214 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
215 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
216 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
218 static const arm_feature_set arm_cext_iwmmxt2
=
219 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
220 static const arm_feature_set arm_cext_iwmmxt
=
221 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
222 static const arm_feature_set arm_cext_xscale
=
223 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
224 static const arm_feature_set arm_cext_maverick
=
225 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
226 static const arm_feature_set fpu_fpa_ext_v1
=
227 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
228 static const arm_feature_set fpu_fpa_ext_v2
=
229 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
230 static const arm_feature_set fpu_vfp_ext_v1xd
=
231 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
232 static const arm_feature_set fpu_vfp_ext_v1
=
233 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
234 static const arm_feature_set fpu_vfp_ext_v2
=
235 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
236 static const arm_feature_set fpu_vfp_ext_v3xd
=
237 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
238 static const arm_feature_set fpu_vfp_ext_v3
=
239 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
240 static const arm_feature_set fpu_vfp_ext_d32
=
241 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
242 static const arm_feature_set fpu_neon_ext_v1
=
243 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
244 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
245 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
246 static const arm_feature_set fpu_vfp_fp16
=
247 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
248 static const arm_feature_set fpu_neon_ext_fma
=
249 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
250 static const arm_feature_set fpu_vfp_ext_fma
=
251 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
252 static const arm_feature_set fpu_vfp_ext_armv8
=
253 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
254 static const arm_feature_set fpu_vfp_ext_armv8xd
=
255 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
256 static const arm_feature_set fpu_neon_ext_armv8
=
257 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
258 static const arm_feature_set fpu_crypto_ext_armv8
=
259 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
260 static const arm_feature_set crc_ext_armv8
=
261 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
263 static int mfloat_abi_opt
= -1;
264 /* Record user cpu selection for object attributes. */
265 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
266 /* Must be long enough to hold any of the names in arm_cpus. */
267 static char selected_cpu_name
[16];
269 extern FLONUM_TYPE generic_floating_point_number
;
271 /* Return if no cpu was selected on command-line. */
273 no_cpu_selected (void)
275 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
280 static int meabi_flags
= EABI_DEFAULT
;
282 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
285 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
290 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
295 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
296 symbolS
* GOT_symbol
;
299 /* 0: assemble for ARM,
300 1: assemble for Thumb,
301 2: assemble for Thumb even though target CPU does not support thumb
303 static int thumb_mode
= 0;
304 /* A value distinct from the possible values for thumb_mode that we
305 can use to record whether thumb_mode has been copied into the
306 tc_frag_data field of a frag. */
307 #define MODE_RECORDED (1 << 4)
309 /* Specifies the intrinsic IT insn behavior mode. */
310 enum implicit_it_mode
312 IMPLICIT_IT_MODE_NEVER
= 0x00,
313 IMPLICIT_IT_MODE_ARM
= 0x01,
314 IMPLICIT_IT_MODE_THUMB
= 0x02,
315 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
317 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
319 /* If unified_syntax is true, we are processing the new unified
320 ARM/Thumb syntax. Important differences from the old ARM mode:
322 - Immediate operands do not require a # prefix.
323 - Conditional affixes always appear at the end of the
324 instruction. (For backward compatibility, those instructions
325 that formerly had them in the middle, continue to accept them
327 - The IT instruction may appear, and if it does is validated
328 against subsequent conditional affixes. It does not generate
331 Important differences from the old Thumb mode:
333 - Immediate operands do not require a # prefix.
334 - Most of the V6T2 instructions are only available in unified mode.
335 - The .N and .W suffixes are recognized and honored (it is an error
336 if they cannot be honored).
337 - All instructions set the flags if and only if they have an 's' affix.
338 - Conditional affixes may be used. They are validated against
339 preceding IT instructions. Unlike ARM mode, you cannot use a
340 conditional affix except in the scope of an IT instruction. */
342 static bfd_boolean unified_syntax
= FALSE
;
344 /* An immediate operand can start with #, and ld*, st*, pld operands
345 can contain [ and ]. We need to tell APP not to elide whitespace
346 before a [, which can appear as the first operand for pld.
347 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
348 const char arm_symbol_chars
[] = "#[]{}";
363 enum neon_el_type type
;
367 #define NEON_MAX_TYPE_ELS 4
371 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
375 enum it_instruction_type
380 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
381 if inside, should be the last one. */
382 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
383 i.e. BKPT and NOP. */
384 IT_INSN
/* The IT insn has been parsed. */
387 /* The maximum number of operands we need. */
388 #define ARM_IT_MAX_OPERANDS 6
393 unsigned long instruction
;
397 /* "uncond_value" is set to the value in place of the conditional field in
398 unconditional versions of the instruction, or -1 if nothing is
401 struct neon_type vectype
;
402 /* This does not indicate an actual NEON instruction, only that
403 the mnemonic accepts neon-style type suffixes. */
405 /* Set to the opcode if the instruction needs relaxation.
406 Zero if the instruction is not relaxed. */
410 bfd_reloc_code_real_type type
;
415 enum it_instruction_type it_insn_type
;
421 struct neon_type_el vectype
;
422 unsigned present
: 1; /* Operand present. */
423 unsigned isreg
: 1; /* Operand was a register. */
424 unsigned immisreg
: 1; /* .imm field is a second register. */
425 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
426 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
427 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
428 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
429 instructions. This allows us to disambiguate ARM <-> vector insns. */
430 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
431 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
432 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
433 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
434 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
435 unsigned writeback
: 1; /* Operand has trailing ! */
436 unsigned preind
: 1; /* Preindexed address. */
437 unsigned postind
: 1; /* Postindexed address. */
438 unsigned negative
: 1; /* Index register was negated. */
439 unsigned shifted
: 1; /* Shift applied to operation. */
440 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
441 } operands
[ARM_IT_MAX_OPERANDS
];
444 static struct arm_it inst
;
446 #define NUM_FLOAT_VALS 8
448 const char * fp_const
[] =
450 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
453 /* Number of littlenums required to hold an extended precision number. */
454 #define MAX_LITTLENUMS 6
456 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
466 #define CP_T_X 0x00008000
467 #define CP_T_Y 0x00400000
469 #define CONDS_BIT 0x00100000
470 #define LOAD_BIT 0x00100000
472 #define DOUBLE_LOAD_FLAG 0x00000001
476 const char * template_name
;
480 #define COND_ALWAYS 0xE
484 const char * template_name
;
488 struct asm_barrier_opt
490 const char * template_name
;
492 const arm_feature_set arch
;
495 /* The bit that distinguishes CPSR and SPSR. */
496 #define SPSR_BIT (1 << 22)
498 /* The individual PSR flag bits. */
499 #define PSR_c (1 << 16)
500 #define PSR_x (1 << 17)
501 #define PSR_s (1 << 18)
502 #define PSR_f (1 << 19)
507 bfd_reloc_code_real_type reloc
;
512 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
513 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
518 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
521 /* Bits for DEFINED field in neon_typed_alias. */
522 #define NTA_HASTYPE 1
523 #define NTA_HASINDEX 2
525 struct neon_typed_alias
527 unsigned char defined
;
529 struct neon_type_el eltype
;
532 /* ARM register categories. This includes coprocessor numbers and various
533 architecture extensions' registers. */
560 /* Structure for a hash table entry for a register.
561 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
562 information which states whether a vector type or index is specified (for a
563 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
569 unsigned char builtin
;
570 struct neon_typed_alias
* neon
;
573 /* Diagnostics used when we don't get a register of the expected type. */
574 const char * const reg_expected_msgs
[] =
576 N_("ARM register expected"),
577 N_("bad or missing co-processor number"),
578 N_("co-processor register expected"),
579 N_("FPA register expected"),
580 N_("VFP single precision register expected"),
581 N_("VFP/Neon double precision register expected"),
582 N_("Neon quad precision register expected"),
583 N_("VFP single or double precision register expected"),
584 N_("Neon double or quad precision register expected"),
585 N_("VFP single, double or Neon quad precision register expected"),
586 N_("VFP system register expected"),
587 N_("Maverick MVF register expected"),
588 N_("Maverick MVD register expected"),
589 N_("Maverick MVFX register expected"),
590 N_("Maverick MVDX register expected"),
591 N_("Maverick MVAX register expected"),
592 N_("Maverick DSPSC register expected"),
593 N_("iWMMXt data register expected"),
594 N_("iWMMXt control register expected"),
595 N_("iWMMXt scalar register expected"),
596 N_("XScale accumulator register expected"),
599 /* Some well known registers that we refer to directly elsewhere. */
605 /* ARM instructions take 4bytes in the object file, Thumb instructions
611 /* Basic string to match. */
612 const char * template_name
;
614 /* Parameters to instruction. */
615 unsigned int operands
[8];
617 /* Conditional tag - see opcode_lookup. */
618 unsigned int tag
: 4;
620 /* Basic instruction code. */
621 unsigned int avalue
: 28;
623 /* Thumb-format instruction code. */
626 /* Which architecture variant provides this instruction. */
627 const arm_feature_set
* avariant
;
628 const arm_feature_set
* tvariant
;
630 /* Function to call to encode instruction in ARM format. */
631 void (* aencode
) (void);
633 /* Function to call to encode instruction in Thumb format. */
634 void (* tencode
) (void);
637 /* Defines for various bits that we will want to toggle. */
638 #define INST_IMMEDIATE 0x02000000
639 #define OFFSET_REG 0x02000000
640 #define HWOFFSET_IMM 0x00400000
641 #define SHIFT_BY_REG 0x00000010
642 #define PRE_INDEX 0x01000000
643 #define INDEX_UP 0x00800000
644 #define WRITE_BACK 0x00200000
645 #define LDM_TYPE_2_OR_3 0x00400000
646 #define CPSI_MMOD 0x00020000
648 #define LITERAL_MASK 0xf000f000
649 #define OPCODE_MASK 0xfe1fffff
650 #define V4_STR_BIT 0x00000020
651 #define VLDR_VMOV_SAME 0x0040f000
653 #define T2_SUBS_PC_LR 0xf3de8f00
655 #define DATA_OP_SHIFT 21
657 #define T2_OPCODE_MASK 0xfe1fffff
658 #define T2_DATA_OP_SHIFT 21
660 #define A_COND_MASK 0xf0000000
661 #define A_PUSH_POP_OP_MASK 0x0fff0000
663 /* Opcodes for pushing/poping registers to/from the stack. */
664 #define A1_OPCODE_PUSH 0x092d0000
665 #define A2_OPCODE_PUSH 0x052d0004
666 #define A2_OPCODE_POP 0x049d0004
668 /* Codes to distinguish the arithmetic instructions. */
679 #define OPCODE_CMP 10
680 #define OPCODE_CMN 11
681 #define OPCODE_ORR 12
682 #define OPCODE_MOV 13
683 #define OPCODE_BIC 14
684 #define OPCODE_MVN 15
686 #define T2_OPCODE_AND 0
687 #define T2_OPCODE_BIC 1
688 #define T2_OPCODE_ORR 2
689 #define T2_OPCODE_ORN 3
690 #define T2_OPCODE_EOR 4
691 #define T2_OPCODE_ADD 8
692 #define T2_OPCODE_ADC 10
693 #define T2_OPCODE_SBC 11
694 #define T2_OPCODE_SUB 13
695 #define T2_OPCODE_RSB 14
697 #define T_OPCODE_MUL 0x4340
698 #define T_OPCODE_TST 0x4200
699 #define T_OPCODE_CMN 0x42c0
700 #define T_OPCODE_NEG 0x4240
701 #define T_OPCODE_MVN 0x43c0
703 #define T_OPCODE_ADD_R3 0x1800
704 #define T_OPCODE_SUB_R3 0x1a00
705 #define T_OPCODE_ADD_HI 0x4400
706 #define T_OPCODE_ADD_ST 0xb000
707 #define T_OPCODE_SUB_ST 0xb080
708 #define T_OPCODE_ADD_SP 0xa800
709 #define T_OPCODE_ADD_PC 0xa000
710 #define T_OPCODE_ADD_I8 0x3000
711 #define T_OPCODE_SUB_I8 0x3800
712 #define T_OPCODE_ADD_I3 0x1c00
713 #define T_OPCODE_SUB_I3 0x1e00
715 #define T_OPCODE_ASR_R 0x4100
716 #define T_OPCODE_LSL_R 0x4080
717 #define T_OPCODE_LSR_R 0x40c0
718 #define T_OPCODE_ROR_R 0x41c0
719 #define T_OPCODE_ASR_I 0x1000
720 #define T_OPCODE_LSL_I 0x0000
721 #define T_OPCODE_LSR_I 0x0800
723 #define T_OPCODE_MOV_I8 0x2000
724 #define T_OPCODE_CMP_I8 0x2800
725 #define T_OPCODE_CMP_LR 0x4280
726 #define T_OPCODE_MOV_HR 0x4600
727 #define T_OPCODE_CMP_HR 0x4500
729 #define T_OPCODE_LDR_PC 0x4800
730 #define T_OPCODE_LDR_SP 0x9800
731 #define T_OPCODE_STR_SP 0x9000
732 #define T_OPCODE_LDR_IW 0x6800
733 #define T_OPCODE_STR_IW 0x6000
734 #define T_OPCODE_LDR_IH 0x8800
735 #define T_OPCODE_STR_IH 0x8000
736 #define T_OPCODE_LDR_IB 0x7800
737 #define T_OPCODE_STR_IB 0x7000
738 #define T_OPCODE_LDR_RW 0x5800
739 #define T_OPCODE_STR_RW 0x5000
740 #define T_OPCODE_LDR_RH 0x5a00
741 #define T_OPCODE_STR_RH 0x5200
742 #define T_OPCODE_LDR_RB 0x5c00
743 #define T_OPCODE_STR_RB 0x5400
745 #define T_OPCODE_PUSH 0xb400
746 #define T_OPCODE_POP 0xbc00
748 #define T_OPCODE_BRANCH 0xe000
750 #define THUMB_SIZE 2 /* Size of thumb instruction. */
751 #define THUMB_PP_PC_LR 0x0100
752 #define THUMB_LOAD_BIT 0x0800
753 #define THUMB2_LOAD_BIT 0x00100000
755 #define BAD_ARGS _("bad arguments to instruction")
756 #define BAD_SP _("r13 not allowed here")
757 #define BAD_PC _("r15 not allowed here")
758 #define BAD_COND _("instruction cannot be conditional")
759 #define BAD_OVERLAP _("registers may not be the same")
760 #define BAD_HIREG _("lo register required")
761 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
762 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
763 #define BAD_BRANCH _("branch must be last instruction in IT block")
764 #define BAD_NOT_IT _("instruction not allowed in IT block")
765 #define BAD_FPU _("selected FPU does not support instruction")
766 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
767 #define BAD_IT_COND _("incorrect condition in IT block")
768 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
769 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
770 #define BAD_PC_ADDRESSING \
771 _("cannot use register index with PC-relative addressing")
772 #define BAD_PC_WRITEBACK \
773 _("cannot use writeback with PC-relative addressing")
774 #define BAD_RANGE _("branch out of range")
775 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
777 static struct hash_control
* arm_ops_hsh
;
778 static struct hash_control
* arm_cond_hsh
;
779 static struct hash_control
* arm_shift_hsh
;
780 static struct hash_control
* arm_psr_hsh
;
781 static struct hash_control
* arm_v7m_psr_hsh
;
782 static struct hash_control
* arm_reg_hsh
;
783 static struct hash_control
* arm_reloc_hsh
;
784 static struct hash_control
* arm_barrier_opt_hsh
;
786 /* Stuff needed to resolve the label ambiguity
795 symbolS
* last_label_seen
;
796 static int label_is_thumb_function_name
= FALSE
;
798 /* Literal pool structure. Held on a per-section
799 and per-sub-section basis. */
801 #define MAX_LITERAL_POOL_SIZE 1024
802 typedef struct literal_pool
804 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
805 unsigned int next_free_entry
;
811 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
813 struct literal_pool
* next
;
814 unsigned int alignment
;
817 /* Pointer to a linked list of literal pools. */
818 literal_pool
* list_of_pools
= NULL
;
820 typedef enum asmfunc_states
823 WAITING_ASMFUNC_NAME
,
827 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
830 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
832 static struct current_it now_it
;
836 now_it_compatible (int cond
)
838 return (cond
& ~1) == (now_it
.cc
& ~1);
842 conditional_insn (void)
844 return inst
.cond
!= COND_ALWAYS
;
847 static int in_it_block (void);
849 static int handle_it_state (void);
851 static void force_automatic_it_block_close (void);
853 static void it_fsm_post_encode (void);
855 #define set_it_insn_type(type) \
858 inst.it_insn_type = type; \
859 if (handle_it_state () == FAIL) \
864 #define set_it_insn_type_nonvoid(type, failret) \
867 inst.it_insn_type = type; \
868 if (handle_it_state () == FAIL) \
873 #define set_it_insn_type_last() \
876 if (inst.cond == COND_ALWAYS) \
877 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
879 set_it_insn_type (INSIDE_IT_LAST_INSN); \
885 /* This array holds the chars that always start a comment. If the
886 pre-processor is disabled, these aren't very useful. */
887 char arm_comment_chars
[] = "@";
889 /* This array holds the chars that only start a comment at the beginning of
890 a line. If the line seems to have the form '# 123 filename'
891 .line and .file directives will appear in the pre-processed output. */
892 /* Note that input_file.c hand checks for '#' at the beginning of the
893 first line of the input file. This is because the compiler outputs
894 #NO_APP at the beginning of its output. */
895 /* Also note that comments like this one will always work. */
896 const char line_comment_chars
[] = "#";
898 char arm_line_separator_chars
[] = ";";
900 /* Chars that can be used to separate mant
901 from exp in floating point numbers. */
902 const char EXP_CHARS
[] = "eE";
904 /* Chars that mean this number is a floating point constant. */
908 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
910 /* Prefix characters that indicate the start of an immediate
912 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
914 /* Separator character handling. */
916 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
919 skip_past_char (char ** str
, char c
)
921 /* PR gas/14987: Allow for whitespace before the expected character. */
922 skip_whitespace (*str
);
933 #define skip_past_comma(str) skip_past_char (str, ',')
935 /* Arithmetic expressions (possibly involving symbols). */
937 /* Return TRUE if anything in the expression is a bignum. */
940 walk_no_bignums (symbolS
* sp
)
942 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
945 if (symbol_get_value_expression (sp
)->X_add_symbol
)
947 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
948 || (symbol_get_value_expression (sp
)->X_op_symbol
949 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
955 static int in_my_get_expression
= 0;
957 /* Third argument to my_get_expression. */
958 #define GE_NO_PREFIX 0
959 #define GE_IMM_PREFIX 1
960 #define GE_OPT_PREFIX 2
961 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
962 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
963 #define GE_OPT_PREFIX_BIG 3
966 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
971 /* In unified syntax, all prefixes are optional. */
973 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
978 case GE_NO_PREFIX
: break;
980 if (!is_immediate_prefix (**str
))
982 inst
.error
= _("immediate expression requires a # prefix");
988 case GE_OPT_PREFIX_BIG
:
989 if (is_immediate_prefix (**str
))
995 memset (ep
, 0, sizeof (expressionS
));
997 save_in
= input_line_pointer
;
998 input_line_pointer
= *str
;
999 in_my_get_expression
= 1;
1000 seg
= expression (ep
);
1001 in_my_get_expression
= 0;
1003 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1005 /* We found a bad or missing expression in md_operand(). */
1006 *str
= input_line_pointer
;
1007 input_line_pointer
= save_in
;
1008 if (inst
.error
== NULL
)
1009 inst
.error
= (ep
->X_op
== O_absent
1010 ? _("missing expression") :_("bad expression"));
1015 if (seg
!= absolute_section
1016 && seg
!= text_section
1017 && seg
!= data_section
1018 && seg
!= bss_section
1019 && seg
!= undefined_section
)
1021 inst
.error
= _("bad segment");
1022 *str
= input_line_pointer
;
1023 input_line_pointer
= save_in
;
1030 /* Get rid of any bignums now, so that we don't generate an error for which
1031 we can't establish a line number later on. Big numbers are never valid
1032 in instructions, which is where this routine is always called. */
1033 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1034 && (ep
->X_op
== O_big
1035 || (ep
->X_add_symbol
1036 && (walk_no_bignums (ep
->X_add_symbol
)
1038 && walk_no_bignums (ep
->X_op_symbol
))))))
1040 inst
.error
= _("invalid constant");
1041 *str
= input_line_pointer
;
1042 input_line_pointer
= save_in
;
1046 *str
= input_line_pointer
;
1047 input_line_pointer
= save_in
;
1051 /* Turn a string in input_line_pointer into a floating point constant
1052 of type TYPE, and store the appropriate bytes in *LITP. The number
1053 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1054 returned, or NULL on OK.
1056 Note that fp constants aren't represent in the normal way on the ARM.
1057 In big endian mode, things are as expected. However, in little endian
1058 mode fp constants are big-endian word-wise, and little-endian byte-wise
1059 within the words. For example, (double) 1.1 in big endian mode is
1060 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1061 the byte sequence 99 99 f1 3f 9a 99 99 99.
1063 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1066 md_atof (int type
, char * litP
, int * sizeP
)
1069 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1101 return _("Unrecognized or unsupported floating point constant");
1104 t
= atof_ieee (input_line_pointer
, type
, words
);
1106 input_line_pointer
= t
;
1107 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1109 if (target_big_endian
)
1111 for (i
= 0; i
< prec
; i
++)
1113 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1114 litP
+= sizeof (LITTLENUM_TYPE
);
1119 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1120 for (i
= prec
- 1; i
>= 0; i
--)
1122 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1123 litP
+= sizeof (LITTLENUM_TYPE
);
1126 /* For a 4 byte float the order of elements in `words' is 1 0.
1127 For an 8 byte float the order is 1 0 3 2. */
1128 for (i
= 0; i
< prec
; i
+= 2)
1130 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1131 sizeof (LITTLENUM_TYPE
));
1132 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1133 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1134 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1141 /* We handle all bad expressions here, so that we can report the faulty
1142 instruction in the error message. */
1144 md_operand (expressionS
* exp
)
1146 if (in_my_get_expression
)
1147 exp
->X_op
= O_illegal
;
1150 /* Immediate values. */
1152 /* Generic immediate-value read function for use in directives.
1153 Accepts anything that 'expression' can fold to a constant.
1154 *val receives the number. */
1157 immediate_for_directive (int *val
)
1160 exp
.X_op
= O_illegal
;
1162 if (is_immediate_prefix (*input_line_pointer
))
1164 input_line_pointer
++;
1168 if (exp
.X_op
!= O_constant
)
1170 as_bad (_("expected #constant"));
1171 ignore_rest_of_line ();
1174 *val
= exp
.X_add_number
;
1179 /* Register parsing. */
1181 /* Generic register parser. CCP points to what should be the
1182 beginning of a register name. If it is indeed a valid register
1183 name, advance CCP over it and return the reg_entry structure;
1184 otherwise return NULL. Does not issue diagnostics. */
1186 static struct reg_entry
*
1187 arm_reg_parse_multi (char **ccp
)
1191 struct reg_entry
*reg
;
1193 skip_whitespace (start
);
1195 #ifdef REGISTER_PREFIX
1196 if (*start
!= REGISTER_PREFIX
)
1200 #ifdef OPTIONAL_REGISTER_PREFIX
1201 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1206 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1211 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1213 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1223 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1224 enum arm_reg_type type
)
1226 /* Alternative syntaxes are accepted for a few register classes. */
1233 /* Generic coprocessor register names are allowed for these. */
1234 if (reg
&& reg
->type
== REG_TYPE_CN
)
1239 /* For backward compatibility, a bare number is valid here. */
1241 unsigned long processor
= strtoul (start
, ccp
, 10);
1242 if (*ccp
!= start
&& processor
<= 15)
1246 case REG_TYPE_MMXWC
:
1247 /* WC includes WCG. ??? I'm not sure this is true for all
1248 instructions that take WC registers. */
1249 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1260 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1261 return value is the register number or FAIL. */
1264 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1267 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1270 /* Do not allow a scalar (reg+index) to parse as a register. */
1271 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1274 if (reg
&& reg
->type
== type
)
1277 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1284 /* Parse a Neon type specifier. *STR should point at the leading '.'
1285 character. Does no verification at this stage that the type fits the opcode
1292 Can all be legally parsed by this function.
1294 Fills in neon_type struct pointer with parsed information, and updates STR
1295 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1296 type, FAIL if not. */
1299 parse_neon_type (struct neon_type
*type
, char **str
)
1306 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1308 enum neon_el_type thistype
= NT_untyped
;
1309 unsigned thissize
= -1u;
1316 /* Just a size without an explicit type. */
1320 switch (TOLOWER (*ptr
))
1322 case 'i': thistype
= NT_integer
; break;
1323 case 'f': thistype
= NT_float
; break;
1324 case 'p': thistype
= NT_poly
; break;
1325 case 's': thistype
= NT_signed
; break;
1326 case 'u': thistype
= NT_unsigned
; break;
1328 thistype
= NT_float
;
1333 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1339 /* .f is an abbreviation for .f32. */
1340 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1345 thissize
= strtoul (ptr
, &ptr
, 10);
1347 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1350 as_bad (_("bad size %d in type specifier"), thissize
);
1358 type
->el
[type
->elems
].type
= thistype
;
1359 type
->el
[type
->elems
].size
= thissize
;
1364 /* Empty/missing type is not a successful parse. */
1365 if (type
->elems
== 0)
1373 /* Errors may be set multiple times during parsing or bit encoding
1374 (particularly in the Neon bits), but usually the earliest error which is set
1375 will be the most meaningful. Avoid overwriting it with later (cascading)
1376 errors by calling this function. */
1379 first_error (const char *err
)
1385 /* Parse a single type, e.g. ".s32", leading period included. */
1387 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1390 struct neon_type optype
;
1394 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1396 if (optype
.elems
== 1)
1397 *vectype
= optype
.el
[0];
1400 first_error (_("only one type should be specified for operand"));
1406 first_error (_("vector type expected"));
1418 /* Special meanings for indices (which have a range of 0-7), which will fit into
1421 #define NEON_ALL_LANES 15
1422 #define NEON_INTERLEAVE_LANES 14
1424 /* Parse either a register or a scalar, with an optional type. Return the
1425 register number, and optionally fill in the actual type of the register
1426 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1427 type/index information in *TYPEINFO. */
1430 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1431 enum arm_reg_type
*rtype
,
1432 struct neon_typed_alias
*typeinfo
)
1435 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1436 struct neon_typed_alias atype
;
1437 struct neon_type_el parsetype
;
1441 atype
.eltype
.type
= NT_invtype
;
1442 atype
.eltype
.size
= -1;
1444 /* Try alternate syntax for some types of register. Note these are mutually
1445 exclusive with the Neon syntax extensions. */
1448 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1456 /* Undo polymorphism when a set of register types may be accepted. */
1457 if ((type
== REG_TYPE_NDQ
1458 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1459 || (type
== REG_TYPE_VFSD
1460 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1461 || (type
== REG_TYPE_NSDQ
1462 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1463 || reg
->type
== REG_TYPE_NQ
))
1464 || (type
== REG_TYPE_MMXWC
1465 && (reg
->type
== REG_TYPE_MMXWCG
)))
1466 type
= (enum arm_reg_type
) reg
->type
;
1468 if (type
!= reg
->type
)
1474 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1476 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1478 first_error (_("can't redefine type for operand"));
1481 atype
.defined
|= NTA_HASTYPE
;
1482 atype
.eltype
= parsetype
;
1485 if (skip_past_char (&str
, '[') == SUCCESS
)
1487 if (type
!= REG_TYPE_VFD
)
1489 first_error (_("only D registers may be indexed"));
1493 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1495 first_error (_("can't change index for operand"));
1499 atype
.defined
|= NTA_HASINDEX
;
1501 if (skip_past_char (&str
, ']') == SUCCESS
)
1502 atype
.index
= NEON_ALL_LANES
;
1507 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1509 if (exp
.X_op
!= O_constant
)
1511 first_error (_("constant expression required"));
1515 if (skip_past_char (&str
, ']') == FAIL
)
1518 atype
.index
= exp
.X_add_number
;
1533 /* Like arm_reg_parse, but allow allow the following extra features:
1534 - If RTYPE is non-zero, return the (possibly restricted) type of the
1535 register (e.g. Neon double or quad reg when either has been requested).
1536 - If this is a Neon vector type with additional type information, fill
1537 in the struct pointed to by VECTYPE (if non-NULL).
1538 This function will fault on encountering a scalar. */
1541 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1542 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1544 struct neon_typed_alias atype
;
1546 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1551 /* Do not allow regname(... to parse as a register. */
1555 /* Do not allow a scalar (reg+index) to parse as a register. */
1556 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1558 first_error (_("register operand expected, but got scalar"));
1563 *vectype
= atype
.eltype
;
1570 #define NEON_SCALAR_REG(X) ((X) >> 4)
1571 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1573 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1574 have enough information to be able to do a good job bounds-checking. So, we
1575 just do easy checks here, and do further checks later. */
1578 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1582 struct neon_typed_alias atype
;
1584 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1586 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1589 if (atype
.index
== NEON_ALL_LANES
)
1591 first_error (_("scalar must have an index"));
1594 else if (atype
.index
>= 64 / elsize
)
1596 first_error (_("scalar index out of range"));
1601 *type
= atype
.eltype
;
1605 return reg
* 16 + atype
.index
;
1608 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1611 parse_reg_list (char ** strp
)
1613 char * str
= * strp
;
1617 /* We come back here if we get ranges concatenated by '+' or '|'. */
1620 skip_whitespace (str
);
1634 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1636 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1646 first_error (_("bad range in register list"));
1650 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1652 if (range
& (1 << i
))
1654 (_("Warning: duplicated register (r%d) in register list"),
1662 if (range
& (1 << reg
))
1663 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1665 else if (reg
<= cur_reg
)
1666 as_tsktsk (_("Warning: register range not in ascending order"));
1671 while (skip_past_comma (&str
) != FAIL
1672 || (in_range
= 1, *str
++ == '-'));
1675 if (skip_past_char (&str
, '}') == FAIL
)
1677 first_error (_("missing `}'"));
1685 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1688 if (exp
.X_op
== O_constant
)
1690 if (exp
.X_add_number
1691 != (exp
.X_add_number
& 0x0000ffff))
1693 inst
.error
= _("invalid register mask");
1697 if ((range
& exp
.X_add_number
) != 0)
1699 int regno
= range
& exp
.X_add_number
;
1702 regno
= (1 << regno
) - 1;
1704 (_("Warning: duplicated register (r%d) in register list"),
1708 range
|= exp
.X_add_number
;
1712 if (inst
.reloc
.type
!= 0)
1714 inst
.error
= _("expression too complex");
1718 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1719 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1720 inst
.reloc
.pc_rel
= 0;
1724 if (*str
== '|' || *str
== '+')
1730 while (another_range
);
1736 /* Types of registers in a list. */
1745 /* Parse a VFP register list. If the string is invalid return FAIL.
1746 Otherwise return the number of registers, and set PBASE to the first
1747 register. Parses registers of type ETYPE.
1748 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1749 - Q registers can be used to specify pairs of D registers
1750 - { } can be omitted from around a singleton register list
1751 FIXME: This is not implemented, as it would require backtracking in
1754 This could be done (the meaning isn't really ambiguous), but doesn't
1755 fit in well with the current parsing framework.
1756 - 32 D registers may be used (also true for VFPv3).
1757 FIXME: Types are ignored in these register lists, which is probably a
1761 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1766 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1770 unsigned long mask
= 0;
1773 if (skip_past_char (&str
, '{') == FAIL
)
1775 inst
.error
= _("expecting {");
1782 regtype
= REG_TYPE_VFS
;
1787 regtype
= REG_TYPE_VFD
;
1790 case REGLIST_NEON_D
:
1791 regtype
= REG_TYPE_NDQ
;
1795 if (etype
!= REGLIST_VFP_S
)
1797 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1798 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1802 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1805 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1812 base_reg
= max_regs
;
1816 int setmask
= 1, addregs
= 1;
1818 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1820 if (new_base
== FAIL
)
1822 first_error (_(reg_expected_msgs
[regtype
]));
1826 if (new_base
>= max_regs
)
1828 first_error (_("register out of range in list"));
1832 /* Note: a value of 2 * n is returned for the register Q<n>. */
1833 if (regtype
== REG_TYPE_NQ
)
1839 if (new_base
< base_reg
)
1840 base_reg
= new_base
;
1842 if (mask
& (setmask
<< new_base
))
1844 first_error (_("invalid register list"));
1848 if ((mask
>> new_base
) != 0 && ! warned
)
1850 as_tsktsk (_("register list not in ascending order"));
1854 mask
|= setmask
<< new_base
;
1857 if (*str
== '-') /* We have the start of a range expression */
1863 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1866 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1870 if (high_range
>= max_regs
)
1872 first_error (_("register out of range in list"));
1876 if (regtype
== REG_TYPE_NQ
)
1877 high_range
= high_range
+ 1;
1879 if (high_range
<= new_base
)
1881 inst
.error
= _("register range not in ascending order");
1885 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1887 if (mask
& (setmask
<< new_base
))
1889 inst
.error
= _("invalid register list");
1893 mask
|= setmask
<< new_base
;
1898 while (skip_past_comma (&str
) != FAIL
);
1902 /* Sanity check -- should have raised a parse error above. */
1903 if (count
== 0 || count
> max_regs
)
1908 /* Final test -- the registers must be consecutive. */
1910 for (i
= 0; i
< count
; i
++)
1912 if ((mask
& (1u << i
)) == 0)
1914 inst
.error
= _("non-contiguous register range");
1924 /* True if two alias types are the same. */
1927 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1935 if (a
->defined
!= b
->defined
)
1938 if ((a
->defined
& NTA_HASTYPE
) != 0
1939 && (a
->eltype
.type
!= b
->eltype
.type
1940 || a
->eltype
.size
!= b
->eltype
.size
))
1943 if ((a
->defined
& NTA_HASINDEX
) != 0
1944 && (a
->index
!= b
->index
))
1950 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1951 The base register is put in *PBASE.
1952 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1954 The register stride (minus one) is put in bit 4 of the return value.
1955 Bits [6:5] encode the list length (minus one).
1956 The type of the list elements is put in *ELTYPE, if non-NULL. */
1958 #define NEON_LANE(X) ((X) & 0xf)
1959 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1960 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1963 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1964 struct neon_type_el
*eltype
)
1971 int leading_brace
= 0;
1972 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1973 const char *const incr_error
= _("register stride must be 1 or 2");
1974 const char *const type_error
= _("mismatched element/structure types in list");
1975 struct neon_typed_alias firsttype
;
1977 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1982 struct neon_typed_alias atype
;
1983 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1987 first_error (_(reg_expected_msgs
[rtype
]));
1994 if (rtype
== REG_TYPE_NQ
)
2000 else if (reg_incr
== -1)
2002 reg_incr
= getreg
- base_reg
;
2003 if (reg_incr
< 1 || reg_incr
> 2)
2005 first_error (_(incr_error
));
2009 else if (getreg
!= base_reg
+ reg_incr
* count
)
2011 first_error (_(incr_error
));
2015 if (! neon_alias_types_same (&atype
, &firsttype
))
2017 first_error (_(type_error
));
2021 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2025 struct neon_typed_alias htype
;
2026 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2028 lane
= NEON_INTERLEAVE_LANES
;
2029 else if (lane
!= NEON_INTERLEAVE_LANES
)
2031 first_error (_(type_error
));
2036 else if (reg_incr
!= 1)
2038 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2042 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2045 first_error (_(reg_expected_msgs
[rtype
]));
2048 if (! neon_alias_types_same (&htype
, &firsttype
))
2050 first_error (_(type_error
));
2053 count
+= hireg
+ dregs
- getreg
;
2057 /* If we're using Q registers, we can't use [] or [n] syntax. */
2058 if (rtype
== REG_TYPE_NQ
)
2064 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2068 else if (lane
!= atype
.index
)
2070 first_error (_(type_error
));
2074 else if (lane
== -1)
2075 lane
= NEON_INTERLEAVE_LANES
;
2076 else if (lane
!= NEON_INTERLEAVE_LANES
)
2078 first_error (_(type_error
));
2083 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2085 /* No lane set by [x]. We must be interleaving structures. */
2087 lane
= NEON_INTERLEAVE_LANES
;
2090 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2091 || (count
> 1 && reg_incr
== -1))
2093 first_error (_("error parsing element/structure list"));
2097 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2099 first_error (_("expected }"));
2107 *eltype
= firsttype
.eltype
;
2112 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2115 /* Parse an explicit relocation suffix on an expression. This is
2116 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2117 arm_reloc_hsh contains no entries, so this function can only
2118 succeed if there is no () after the word. Returns -1 on error,
2119 BFD_RELOC_UNUSED if there wasn't any suffix. */
2122 parse_reloc (char **str
)
2124 struct reloc_entry
*r
;
2128 return BFD_RELOC_UNUSED
;
2133 while (*q
&& *q
!= ')' && *q
!= ',')
2138 if ((r
= (struct reloc_entry
*)
2139 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2146 /* Directives: register aliases. */
2148 static struct reg_entry
*
2149 insert_reg_alias (char *str
, unsigned number
, int type
)
2151 struct reg_entry
*new_reg
;
2154 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2156 if (new_reg
->builtin
)
2157 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2159 /* Only warn about a redefinition if it's not defined as the
2161 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2162 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2167 name
= xstrdup (str
);
2168 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2170 new_reg
->name
= name
;
2171 new_reg
->number
= number
;
2172 new_reg
->type
= type
;
2173 new_reg
->builtin
= FALSE
;
2174 new_reg
->neon
= NULL
;
2176 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2183 insert_neon_reg_alias (char *str
, int number
, int type
,
2184 struct neon_typed_alias
*atype
)
2186 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2190 first_error (_("attempt to redefine typed alias"));
2196 reg
->neon
= (struct neon_typed_alias
*)
2197 xmalloc (sizeof (struct neon_typed_alias
));
2198 *reg
->neon
= *atype
;
2202 /* Look for the .req directive. This is of the form:
2204 new_register_name .req existing_register_name
2206 If we find one, or if it looks sufficiently like one that we want to
2207 handle any error here, return TRUE. Otherwise return FALSE. */
2210 create_register_alias (char * newname
, char *p
)
2212 struct reg_entry
*old
;
2213 char *oldname
, *nbuf
;
2216 /* The input scrubber ensures that whitespace after the mnemonic is
2217 collapsed to single spaces. */
2219 if (strncmp (oldname
, " .req ", 6) != 0)
2223 if (*oldname
== '\0')
2226 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2229 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2233 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2234 the desired alias name, and p points to its end. If not, then
2235 the desired alias name is in the global original_case_string. */
2236 #ifdef TC_CASE_SENSITIVE
2239 newname
= original_case_string
;
2240 nlen
= strlen (newname
);
2243 nbuf
= (char *) alloca (nlen
+ 1);
2244 memcpy (nbuf
, newname
, nlen
);
2247 /* Create aliases under the new name as stated; an all-lowercase
2248 version of the new name; and an all-uppercase version of the new
2250 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2252 for (p
= nbuf
; *p
; p
++)
2255 if (strncmp (nbuf
, newname
, nlen
))
2257 /* If this attempt to create an additional alias fails, do not bother
2258 trying to create the all-lower case alias. We will fail and issue
2259 a second, duplicate error message. This situation arises when the
2260 programmer does something like:
2263 The second .req creates the "Foo" alias but then fails to create
2264 the artificial FOO alias because it has already been created by the
2266 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2270 for (p
= nbuf
; *p
; p
++)
2273 if (strncmp (nbuf
, newname
, nlen
))
2274 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2280 /* Create a Neon typed/indexed register alias using directives, e.g.:
2285 These typed registers can be used instead of the types specified after the
2286 Neon mnemonic, so long as all operands given have types. Types can also be
2287 specified directly, e.g.:
2288 vadd d0.s32, d1.s32, d2.s32 */
2291 create_neon_reg_alias (char *newname
, char *p
)
2293 enum arm_reg_type basetype
;
2294 struct reg_entry
*basereg
;
2295 struct reg_entry mybasereg
;
2296 struct neon_type ntype
;
2297 struct neon_typed_alias typeinfo
;
2298 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2301 typeinfo
.defined
= 0;
2302 typeinfo
.eltype
.type
= NT_invtype
;
2303 typeinfo
.eltype
.size
= -1;
2304 typeinfo
.index
= -1;
2308 if (strncmp (p
, " .dn ", 5) == 0)
2309 basetype
= REG_TYPE_VFD
;
2310 else if (strncmp (p
, " .qn ", 5) == 0)
2311 basetype
= REG_TYPE_NQ
;
2320 basereg
= arm_reg_parse_multi (&p
);
2322 if (basereg
&& basereg
->type
!= basetype
)
2324 as_bad (_("bad type for register"));
2328 if (basereg
== NULL
)
2331 /* Try parsing as an integer. */
2332 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2333 if (exp
.X_op
!= O_constant
)
2335 as_bad (_("expression must be constant"));
2338 basereg
= &mybasereg
;
2339 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2345 typeinfo
= *basereg
->neon
;
2347 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2349 /* We got a type. */
2350 if (typeinfo
.defined
& NTA_HASTYPE
)
2352 as_bad (_("can't redefine the type of a register alias"));
2356 typeinfo
.defined
|= NTA_HASTYPE
;
2357 if (ntype
.elems
!= 1)
2359 as_bad (_("you must specify a single type only"));
2362 typeinfo
.eltype
= ntype
.el
[0];
2365 if (skip_past_char (&p
, '[') == SUCCESS
)
2368 /* We got a scalar index. */
2370 if (typeinfo
.defined
& NTA_HASINDEX
)
2372 as_bad (_("can't redefine the index of a scalar alias"));
2376 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2378 if (exp
.X_op
!= O_constant
)
2380 as_bad (_("scalar index must be constant"));
2384 typeinfo
.defined
|= NTA_HASINDEX
;
2385 typeinfo
.index
= exp
.X_add_number
;
2387 if (skip_past_char (&p
, ']') == FAIL
)
2389 as_bad (_("expecting ]"));
2394 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2395 the desired alias name, and p points to its end. If not, then
2396 the desired alias name is in the global original_case_string. */
2397 #ifdef TC_CASE_SENSITIVE
2398 namelen
= nameend
- newname
;
2400 newname
= original_case_string
;
2401 namelen
= strlen (newname
);
2404 namebuf
= (char *) alloca (namelen
+ 1);
2405 strncpy (namebuf
, newname
, namelen
);
2406 namebuf
[namelen
] = '\0';
2408 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2409 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2411 /* Insert name in all uppercase. */
2412 for (p
= namebuf
; *p
; p
++)
2415 if (strncmp (namebuf
, newname
, namelen
))
2416 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2417 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2419 /* Insert name in all lowercase. */
2420 for (p
= namebuf
; *p
; p
++)
2423 if (strncmp (namebuf
, newname
, namelen
))
2424 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2425 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2430 /* Should never be called, as .req goes between the alias and the
2431 register name, not at the beginning of the line. */
2434 s_req (int a ATTRIBUTE_UNUSED
)
2436 as_bad (_("invalid syntax for .req directive"));
2440 s_dn (int a ATTRIBUTE_UNUSED
)
2442 as_bad (_("invalid syntax for .dn directive"));
2446 s_qn (int a ATTRIBUTE_UNUSED
)
2448 as_bad (_("invalid syntax for .qn directive"));
2451 /* The .unreq directive deletes an alias which was previously defined
2452 by .req. For example:
2458 s_unreq (int a ATTRIBUTE_UNUSED
)
2463 name
= input_line_pointer
;
2465 while (*input_line_pointer
!= 0
2466 && *input_line_pointer
!= ' '
2467 && *input_line_pointer
!= '\n')
2468 ++input_line_pointer
;
2470 saved_char
= *input_line_pointer
;
2471 *input_line_pointer
= 0;
2474 as_bad (_("invalid syntax for .unreq directive"));
2477 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2481 as_bad (_("unknown register alias '%s'"), name
);
2482 else if (reg
->builtin
)
2483 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2490 hash_delete (arm_reg_hsh
, name
, FALSE
);
2491 free ((char *) reg
->name
);
2496 /* Also locate the all upper case and all lower case versions.
2497 Do not complain if we cannot find one or the other as it
2498 was probably deleted above. */
2500 nbuf
= strdup (name
);
2501 for (p
= nbuf
; *p
; p
++)
2503 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2506 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2507 free ((char *) reg
->name
);
2513 for (p
= nbuf
; *p
; p
++)
2515 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2518 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2519 free ((char *) reg
->name
);
2529 *input_line_pointer
= saved_char
;
2530 demand_empty_rest_of_line ();
2533 /* Directives: Instruction set selection. */
2536 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2537 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2538 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2539 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2541 /* Create a new mapping symbol for the transition to STATE. */
2544 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2547 const char * symname
;
2554 type
= BSF_NO_FLAGS
;
2558 type
= BSF_NO_FLAGS
;
2562 type
= BSF_NO_FLAGS
;
2568 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2569 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2574 THUMB_SET_FUNC (symbolP
, 0);
2575 ARM_SET_THUMB (symbolP
, 0);
2576 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2580 THUMB_SET_FUNC (symbolP
, 1);
2581 ARM_SET_THUMB (symbolP
, 1);
2582 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2590 /* Save the mapping symbols for future reference. Also check that
2591 we do not place two mapping symbols at the same offset within a
2592 frag. We'll handle overlap between frags in
2593 check_mapping_symbols.
2595 If .fill or other data filling directive generates zero sized data,
2596 the mapping symbol for the following code will have the same value
2597 as the one generated for the data filling directive. In this case,
2598 we replace the old symbol with the new one at the same address. */
2601 if (frag
->tc_frag_data
.first_map
!= NULL
)
2603 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2604 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2606 frag
->tc_frag_data
.first_map
= symbolP
;
2608 if (frag
->tc_frag_data
.last_map
!= NULL
)
2610 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2611 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2612 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2614 frag
->tc_frag_data
.last_map
= symbolP
;
2617 /* We must sometimes convert a region marked as code to data during
2618 code alignment, if an odd number of bytes have to be padded. The
2619 code mapping symbol is pushed to an aligned address. */
2622 insert_data_mapping_symbol (enum mstate state
,
2623 valueT value
, fragS
*frag
, offsetT bytes
)
2625 /* If there was already a mapping symbol, remove it. */
2626 if (frag
->tc_frag_data
.last_map
!= NULL
2627 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2629 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2633 know (frag
->tc_frag_data
.first_map
== symp
);
2634 frag
->tc_frag_data
.first_map
= NULL
;
2636 frag
->tc_frag_data
.last_map
= NULL
;
2637 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2640 make_mapping_symbol (MAP_DATA
, value
, frag
);
2641 make_mapping_symbol (state
, value
+ bytes
, frag
);
2644 static void mapping_state_2 (enum mstate state
, int max_chars
);
2646 /* Set the mapping state to STATE. Only call this when about to
2647 emit some STATE bytes to the file. */
2649 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2651 mapping_state (enum mstate state
)
2653 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2655 if (mapstate
== state
)
2656 /* The mapping symbol has already been emitted.
2657 There is nothing else to do. */
2660 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2662 All ARM instructions require 4-byte alignment.
2663 (Almost) all Thumb instructions require 2-byte alignment.
2665 When emitting instructions into any section, mark the section
2668 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2669 but themselves require 2-byte alignment; this applies to some
2670 PC- relative forms. However, these cases will invovle implicit
2671 literal pool generation or an explicit .align >=2, both of
2672 which will cause the section to me marked with sufficient
2673 alignment. Thus, we don't handle those cases here. */
2674 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2676 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2677 /* This case will be evaluated later. */
2680 mapping_state_2 (state
, 0);
2683 /* Same as mapping_state, but MAX_CHARS bytes have already been
2684 allocated. Put the mapping symbol that far back. */
2687 mapping_state_2 (enum mstate state
, int max_chars
)
2689 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2691 if (!SEG_NORMAL (now_seg
))
2694 if (mapstate
== state
)
2695 /* The mapping symbol has already been emitted.
2696 There is nothing else to do. */
2699 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2700 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2702 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2703 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2706 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2709 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2710 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2714 #define mapping_state(x) ((void)0)
2715 #define mapping_state_2(x, y) ((void)0)
2718 /* Find the real, Thumb encoded start of a Thumb function. */
2722 find_real_start (symbolS
* symbolP
)
2725 const char * name
= S_GET_NAME (symbolP
);
2726 symbolS
* new_target
;
2728 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2729 #define STUB_NAME ".real_start_of"
2734 /* The compiler may generate BL instructions to local labels because
2735 it needs to perform a branch to a far away location. These labels
2736 do not have a corresponding ".real_start_of" label. We check
2737 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2738 the ".real_start_of" convention for nonlocal branches. */
2739 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2742 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2743 new_target
= symbol_find (real_start
);
2745 if (new_target
== NULL
)
2747 as_warn (_("Failed to find real start of function: %s\n"), name
);
2748 new_target
= symbolP
;
2756 opcode_select (int width
)
2763 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2764 as_bad (_("selected processor does not support THUMB opcodes"));
2767 /* No need to force the alignment, since we will have been
2768 coming from ARM mode, which is word-aligned. */
2769 record_alignment (now_seg
, 1);
2776 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2777 as_bad (_("selected processor does not support ARM opcodes"));
2782 frag_align (2, 0, 0);
2784 record_alignment (now_seg
, 1);
2789 as_bad (_("invalid instruction size selected (%d)"), width
);
2794 s_arm (int ignore ATTRIBUTE_UNUSED
)
2797 demand_empty_rest_of_line ();
2801 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2804 demand_empty_rest_of_line ();
2808 s_code (int unused ATTRIBUTE_UNUSED
)
2812 temp
= get_absolute_expression ();
2817 opcode_select (temp
);
2821 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2826 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2828 /* If we are not already in thumb mode go into it, EVEN if
2829 the target processor does not support thumb instructions.
2830 This is used by gcc/config/arm/lib1funcs.asm for example
2831 to compile interworking support functions even if the
2832 target processor should not support interworking. */
2836 record_alignment (now_seg
, 1);
2839 demand_empty_rest_of_line ();
2843 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2847 /* The following label is the name/address of the start of a Thumb function.
2848 We need to know this for the interworking support. */
2849 label_is_thumb_function_name
= TRUE
;
2852 /* Perform a .set directive, but also mark the alias as
2853 being a thumb function. */
2856 s_thumb_set (int equiv
)
2858 /* XXX the following is a duplicate of the code for s_set() in read.c
2859 We cannot just call that code as we need to get at the symbol that
2866 /* Especial apologies for the random logic:
2867 This just grew, and could be parsed much more simply!
2869 name
= input_line_pointer
;
2870 delim
= get_symbol_end ();
2871 end_name
= input_line_pointer
;
2874 if (*input_line_pointer
!= ',')
2877 as_bad (_("expected comma after name \"%s\""), name
);
2879 ignore_rest_of_line ();
2883 input_line_pointer
++;
2886 if (name
[0] == '.' && name
[1] == '\0')
2888 /* XXX - this should not happen to .thumb_set. */
2892 if ((symbolP
= symbol_find (name
)) == NULL
2893 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2896 /* When doing symbol listings, play games with dummy fragments living
2897 outside the normal fragment chain to record the file and line info
2899 if (listing
& LISTING_SYMBOLS
)
2901 extern struct list_info_struct
* listing_tail
;
2902 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2904 memset (dummy_frag
, 0, sizeof (fragS
));
2905 dummy_frag
->fr_type
= rs_fill
;
2906 dummy_frag
->line
= listing_tail
;
2907 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2908 dummy_frag
->fr_symbol
= symbolP
;
2912 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2915 /* "set" symbols are local unless otherwise specified. */
2916 SF_SET_LOCAL (symbolP
);
2917 #endif /* OBJ_COFF */
2918 } /* Make a new symbol. */
2920 symbol_table_insert (symbolP
);
2925 && S_IS_DEFINED (symbolP
)
2926 && S_GET_SEGMENT (symbolP
) != reg_section
)
2927 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2929 pseudo_set (symbolP
);
2931 demand_empty_rest_of_line ();
2933 /* XXX Now we come to the Thumb specific bit of code. */
2935 THUMB_SET_FUNC (symbolP
, 1);
2936 ARM_SET_THUMB (symbolP
, 1);
2937 #if defined OBJ_ELF || defined OBJ_COFF
2938 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2942 /* Directives: Mode selection. */
2944 /* .syntax [unified|divided] - choose the new unified syntax
2945 (same for Arm and Thumb encoding, modulo slight differences in what
2946 can be represented) or the old divergent syntax for each mode. */
2948 s_syntax (int unused ATTRIBUTE_UNUSED
)
2952 name
= input_line_pointer
;
2953 delim
= get_symbol_end ();
2955 if (!strcasecmp (name
, "unified"))
2956 unified_syntax
= TRUE
;
2957 else if (!strcasecmp (name
, "divided"))
2958 unified_syntax
= FALSE
;
2961 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2964 *input_line_pointer
= delim
;
2965 demand_empty_rest_of_line ();
2968 /* Directives: sectioning and alignment. */
2970 /* Same as s_align_ptwo but align 0 => align 2. */
2973 s_align (int unused ATTRIBUTE_UNUSED
)
2978 long max_alignment
= 15;
2980 temp
= get_absolute_expression ();
2981 if (temp
> max_alignment
)
2982 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2985 as_bad (_("alignment negative. 0 assumed."));
2989 if (*input_line_pointer
== ',')
2991 input_line_pointer
++;
2992 temp_fill
= get_absolute_expression ();
3004 /* Only make a frag if we HAVE to. */
3005 if (temp
&& !need_pass_2
)
3007 if (!fill_p
&& subseg_text_p (now_seg
))
3008 frag_align_code (temp
, 0);
3010 frag_align (temp
, (int) temp_fill
, 0);
3012 demand_empty_rest_of_line ();
3014 record_alignment (now_seg
, temp
);
3018 s_bss (int ignore ATTRIBUTE_UNUSED
)
3020 /* We don't support putting frags in the BSS segment, we fake it by
3021 marking in_bss, then looking at s_skip for clues. */
3022 subseg_set (bss_section
, 0);
3023 demand_empty_rest_of_line ();
3025 #ifdef md_elf_section_change_hook
3026 md_elf_section_change_hook ();
3031 s_even (int ignore ATTRIBUTE_UNUSED
)
3033 /* Never make frag if expect extra pass. */
3035 frag_align (1, 0, 0);
3037 record_alignment (now_seg
, 1);
3039 demand_empty_rest_of_line ();
3042 /* Directives: CodeComposer Studio. */
3044 /* .ref (for CodeComposer Studio syntax only). */
3046 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3048 if (codecomposer_syntax
)
3049 ignore_rest_of_line ();
3051 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3054 /* If name is not NULL, then it is used for marking the beginning of a
3055 function, wherease if it is NULL then it means the function end. */
3057 asmfunc_debug (const char * name
)
3059 static const char * last_name
= NULL
;
3063 gas_assert (last_name
== NULL
);
3066 if (debug_type
== DEBUG_STABS
)
3067 stabs_generate_asm_func (name
, name
);
3071 gas_assert (last_name
!= NULL
);
3073 if (debug_type
== DEBUG_STABS
)
3074 stabs_generate_asm_endfunc (last_name
, last_name
);
3081 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3083 if (codecomposer_syntax
)
3085 switch (asmfunc_state
)
3087 case OUTSIDE_ASMFUNC
:
3088 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3091 case WAITING_ASMFUNC_NAME
:
3092 as_bad (_(".asmfunc repeated."));
3095 case WAITING_ENDASMFUNC
:
3096 as_bad (_(".asmfunc without function."));
3099 demand_empty_rest_of_line ();
3102 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3106 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3108 if (codecomposer_syntax
)
3110 switch (asmfunc_state
)
3112 case OUTSIDE_ASMFUNC
:
3113 as_bad (_(".endasmfunc without a .asmfunc."));
3116 case WAITING_ASMFUNC_NAME
:
3117 as_bad (_(".endasmfunc without function."));
3120 case WAITING_ENDASMFUNC
:
3121 asmfunc_state
= OUTSIDE_ASMFUNC
;
3122 asmfunc_debug (NULL
);
3125 demand_empty_rest_of_line ();
3128 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3132 s_ccs_def (int name
)
3134 if (codecomposer_syntax
)
3137 as_bad (_(".def pseudo-op only available with -mccs flag."));
3140 /* Directives: Literal pools. */
3142 static literal_pool
*
3143 find_literal_pool (void)
3145 literal_pool
* pool
;
3147 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3149 if (pool
->section
== now_seg
3150 && pool
->sub_section
== now_subseg
)
3157 static literal_pool
*
3158 find_or_make_literal_pool (void)
3160 /* Next literal pool ID number. */
3161 static unsigned int latest_pool_num
= 1;
3162 literal_pool
* pool
;
3164 pool
= find_literal_pool ();
3168 /* Create a new pool. */
3169 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
3173 pool
->next_free_entry
= 0;
3174 pool
->section
= now_seg
;
3175 pool
->sub_section
= now_subseg
;
3176 pool
->next
= list_of_pools
;
3177 pool
->symbol
= NULL
;
3178 pool
->alignment
= 2;
3180 /* Add it to the list. */
3181 list_of_pools
= pool
;
3184 /* New pools, and emptied pools, will have a NULL symbol. */
3185 if (pool
->symbol
== NULL
)
3187 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3188 (valueT
) 0, &zero_address_frag
);
3189 pool
->id
= latest_pool_num
++;
3196 /* Add the literal in the global 'inst'
3197 structure to the relevant literal pool. */
3200 add_to_lit_pool (unsigned int nbytes
)
3202 #define PADDING_SLOT 0x1
3203 #define LIT_ENTRY_SIZE_MASK 0xFF
3204 literal_pool
* pool
;
3205 unsigned int entry
, pool_size
= 0;
3206 bfd_boolean padding_slot_p
= FALSE
;
3212 imm1
= inst
.operands
[1].imm
;
3213 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3214 : inst
.reloc
.exp
.X_unsigned
? 0
3215 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3216 if (target_big_endian
)
3219 imm2
= inst
.operands
[1].imm
;
3223 pool
= find_or_make_literal_pool ();
3225 /* Check if this literal value is already in the pool. */
3226 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3230 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3231 && (inst
.reloc
.exp
.X_op
== O_constant
)
3232 && (pool
->literals
[entry
].X_add_number
3233 == inst
.reloc
.exp
.X_add_number
)
3234 && (pool
->literals
[entry
].X_md
== nbytes
)
3235 && (pool
->literals
[entry
].X_unsigned
3236 == inst
.reloc
.exp
.X_unsigned
))
3239 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3240 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3241 && (pool
->literals
[entry
].X_add_number
3242 == inst
.reloc
.exp
.X_add_number
)
3243 && (pool
->literals
[entry
].X_add_symbol
3244 == inst
.reloc
.exp
.X_add_symbol
)
3245 && (pool
->literals
[entry
].X_op_symbol
3246 == inst
.reloc
.exp
.X_op_symbol
)
3247 && (pool
->literals
[entry
].X_md
== nbytes
))
3250 else if ((nbytes
== 8)
3251 && !(pool_size
& 0x7)
3252 && ((entry
+ 1) != pool
->next_free_entry
)
3253 && (pool
->literals
[entry
].X_op
== O_constant
)
3254 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3255 && (pool
->literals
[entry
].X_unsigned
3256 == inst
.reloc
.exp
.X_unsigned
)
3257 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3258 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3259 && (pool
->literals
[entry
+ 1].X_unsigned
3260 == inst
.reloc
.exp
.X_unsigned
))
3263 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3264 if (padding_slot_p
&& (nbytes
== 4))
3270 /* Do we need to create a new entry? */
3271 if (entry
== pool
->next_free_entry
)
3273 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3275 inst
.error
= _("literal pool overflow");
3281 /* For 8-byte entries, we align to an 8-byte boundary,
3282 and split it into two 4-byte entries, because on 32-bit
3283 host, 8-byte constants are treated as big num, thus
3284 saved in "generic_bignum" which will be overwritten
3285 by later assignments.
3287 We also need to make sure there is enough space for
3290 We also check to make sure the literal operand is a
3292 if (!(inst
.reloc
.exp
.X_op
== O_constant
3293 || inst
.reloc
.exp
.X_op
== O_big
))
3295 inst
.error
= _("invalid type for literal pool");
3298 else if (pool_size
& 0x7)
3300 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3302 inst
.error
= _("literal pool overflow");
3306 pool
->literals
[entry
] = inst
.reloc
.exp
;
3307 pool
->literals
[entry
].X_add_number
= 0;
3308 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3309 pool
->next_free_entry
+= 1;
3312 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3314 inst
.error
= _("literal pool overflow");
3318 pool
->literals
[entry
] = inst
.reloc
.exp
;
3319 pool
->literals
[entry
].X_op
= O_constant
;
3320 pool
->literals
[entry
].X_add_number
= imm1
;
3321 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3322 pool
->literals
[entry
++].X_md
= 4;
3323 pool
->literals
[entry
] = inst
.reloc
.exp
;
3324 pool
->literals
[entry
].X_op
= O_constant
;
3325 pool
->literals
[entry
].X_add_number
= imm2
;
3326 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3327 pool
->literals
[entry
].X_md
= 4;
3328 pool
->alignment
= 3;
3329 pool
->next_free_entry
+= 1;
3333 pool
->literals
[entry
] = inst
.reloc
.exp
;
3334 pool
->literals
[entry
].X_md
= 4;
3338 /* PR ld/12974: Record the location of the first source line to reference
3339 this entry in the literal pool. If it turns out during linking that the
3340 symbol does not exist we will be able to give an accurate line number for
3341 the (first use of the) missing reference. */
3342 if (debug_type
== DEBUG_DWARF2
)
3343 dwarf2_where (pool
->locs
+ entry
);
3345 pool
->next_free_entry
+= 1;
3347 else if (padding_slot_p
)
3349 pool
->literals
[entry
] = inst
.reloc
.exp
;
3350 pool
->literals
[entry
].X_md
= nbytes
;
3353 inst
.reloc
.exp
.X_op
= O_symbol
;
3354 inst
.reloc
.exp
.X_add_number
= pool_size
;
3355 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3361 tc_start_label_without_colon (char unused1 ATTRIBUTE_UNUSED
, const char * rest
)
3363 bfd_boolean ret
= TRUE
;
3365 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3367 const char *label
= rest
;
3369 while (!is_end_of_line
[(int) label
[-1]])
3374 as_bad (_("Invalid label '%s'"), label
);
3378 asmfunc_debug (label
);
3380 asmfunc_state
= WAITING_ENDASMFUNC
;
3386 /* Can't use symbol_new here, so have to create a symbol and then at
3387 a later date assign it a value. Thats what these functions do. */
3390 symbol_locate (symbolS
* symbolP
,
3391 const char * name
, /* It is copied, the caller can modify. */
3392 segT segment
, /* Segment identifier (SEG_<something>). */
3393 valueT valu
, /* Symbol value. */
3394 fragS
* frag
) /* Associated fragment. */
3397 char * preserved_copy_of_name
;
3399 name_length
= strlen (name
) + 1; /* +1 for \0. */
3400 obstack_grow (¬es
, name
, name_length
);
3401 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3403 #ifdef tc_canonicalize_symbol_name
3404 preserved_copy_of_name
=
3405 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3408 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3410 S_SET_SEGMENT (symbolP
, segment
);
3411 S_SET_VALUE (symbolP
, valu
);
3412 symbol_clear_list_pointers (symbolP
);
3414 symbol_set_frag (symbolP
, frag
);
3416 /* Link to end of symbol chain. */
3418 extern int symbol_table_frozen
;
3420 if (symbol_table_frozen
)
3424 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3426 obj_symbol_new_hook (symbolP
);
3428 #ifdef tc_symbol_new_hook
3429 tc_symbol_new_hook (symbolP
);
3433 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3434 #endif /* DEBUG_SYMS */
3438 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3441 literal_pool
* pool
;
3444 pool
= find_literal_pool ();
3446 || pool
->symbol
== NULL
3447 || pool
->next_free_entry
== 0)
3450 /* Align pool as you have word accesses.
3451 Only make a frag if we have to. */
3453 frag_align (pool
->alignment
, 0, 0);
3455 record_alignment (now_seg
, 2);
3458 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3459 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3461 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3463 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3464 (valueT
) frag_now_fix (), frag_now
);
3465 symbol_table_insert (pool
->symbol
);
3467 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3469 #if defined OBJ_COFF || defined OBJ_ELF
3470 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3473 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3476 if (debug_type
== DEBUG_DWARF2
)
3477 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3479 /* First output the expression in the instruction to the pool. */
3480 emit_expr (&(pool
->literals
[entry
]),
3481 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3484 /* Mark the pool as empty. */
3485 pool
->next_free_entry
= 0;
3486 pool
->symbol
= NULL
;
3490 /* Forward declarations for functions below, in the MD interface
3492 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3493 static valueT
create_unwind_entry (int);
3494 static void start_unwind_section (const segT
, int);
3495 static void add_unwind_opcode (valueT
, int);
3496 static void flush_pending_unwind (void);
3498 /* Directives: Data. */
3501 s_arm_elf_cons (int nbytes
)
3505 #ifdef md_flush_pending_output
3506 md_flush_pending_output ();
3509 if (is_it_end_of_statement ())
3511 demand_empty_rest_of_line ();
3515 #ifdef md_cons_align
3516 md_cons_align (nbytes
);
3519 mapping_state (MAP_DATA
);
3523 char *base
= input_line_pointer
;
3527 if (exp
.X_op
!= O_symbol
)
3528 emit_expr (&exp
, (unsigned int) nbytes
);
3531 char *before_reloc
= input_line_pointer
;
3532 reloc
= parse_reloc (&input_line_pointer
);
3535 as_bad (_("unrecognized relocation suffix"));
3536 ignore_rest_of_line ();
3539 else if (reloc
== BFD_RELOC_UNUSED
)
3540 emit_expr (&exp
, (unsigned int) nbytes
);
3543 reloc_howto_type
*howto
= (reloc_howto_type
*)
3544 bfd_reloc_type_lookup (stdoutput
,
3545 (bfd_reloc_code_real_type
) reloc
);
3546 int size
= bfd_get_reloc_size (howto
);
3548 if (reloc
== BFD_RELOC_ARM_PLT32
)
3550 as_bad (_("(plt) is only valid on branch targets"));
3551 reloc
= BFD_RELOC_UNUSED
;
3556 as_bad (_("%s relocations do not fit in %d bytes"),
3557 howto
->name
, nbytes
);
3560 /* We've parsed an expression stopping at O_symbol.
3561 But there may be more expression left now that we
3562 have parsed the relocation marker. Parse it again.
3563 XXX Surely there is a cleaner way to do this. */
3564 char *p
= input_line_pointer
;
3566 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3567 memcpy (save_buf
, base
, input_line_pointer
- base
);
3568 memmove (base
+ (input_line_pointer
- before_reloc
),
3569 base
, before_reloc
- base
);
3571 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3573 memcpy (base
, save_buf
, p
- base
);
3575 offset
= nbytes
- size
;
3576 p
= frag_more (nbytes
);
3577 memset (p
, 0, nbytes
);
3578 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3579 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3584 while (*input_line_pointer
++ == ',');
3586 /* Put terminator back into stream. */
3587 input_line_pointer
--;
3588 demand_empty_rest_of_line ();
3591 /* Emit an expression containing a 32-bit thumb instruction.
3592 Implementation based on put_thumb32_insn. */
3595 emit_thumb32_expr (expressionS
* exp
)
3597 expressionS exp_high
= *exp
;
3599 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3600 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3601 exp
->X_add_number
&= 0xffff;
3602 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3605 /* Guess the instruction size based on the opcode. */
3608 thumb_insn_size (int opcode
)
3610 if ((unsigned int) opcode
< 0xe800u
)
3612 else if ((unsigned int) opcode
>= 0xe8000000u
)
3619 emit_insn (expressionS
*exp
, int nbytes
)
3623 if (exp
->X_op
== O_constant
)
3628 size
= thumb_insn_size (exp
->X_add_number
);
3632 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3634 as_bad (_(".inst.n operand too big. "\
3635 "Use .inst.w instead"));
3640 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3641 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3643 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3645 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3646 emit_thumb32_expr (exp
);
3648 emit_expr (exp
, (unsigned int) size
);
3650 it_fsm_post_encode ();
3654 as_bad (_("cannot determine Thumb instruction size. " \
3655 "Use .inst.n/.inst.w instead"));
3658 as_bad (_("constant expression required"));
3663 /* Like s_arm_elf_cons but do not use md_cons_align and
3664 set the mapping state to MAP_ARM/MAP_THUMB. */
3667 s_arm_elf_inst (int nbytes
)
3669 if (is_it_end_of_statement ())
3671 demand_empty_rest_of_line ();
3675 /* Calling mapping_state () here will not change ARM/THUMB,
3676 but will ensure not to be in DATA state. */
3679 mapping_state (MAP_THUMB
);
3684 as_bad (_("width suffixes are invalid in ARM mode"));
3685 ignore_rest_of_line ();
3691 mapping_state (MAP_ARM
);
3700 if (! emit_insn (& exp
, nbytes
))
3702 ignore_rest_of_line ();
3706 while (*input_line_pointer
++ == ',');
3708 /* Put terminator back into stream. */
3709 input_line_pointer
--;
3710 demand_empty_rest_of_line ();
3713 /* Parse a .rel31 directive. */
3716 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3723 if (*input_line_pointer
== '1')
3724 highbit
= 0x80000000;
3725 else if (*input_line_pointer
!= '0')
3726 as_bad (_("expected 0 or 1"));
3728 input_line_pointer
++;
3729 if (*input_line_pointer
!= ',')
3730 as_bad (_("missing comma"));
3731 input_line_pointer
++;
3733 #ifdef md_flush_pending_output
3734 md_flush_pending_output ();
3737 #ifdef md_cons_align
3741 mapping_state (MAP_DATA
);
3746 md_number_to_chars (p
, highbit
, 4);
3747 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3748 BFD_RELOC_ARM_PREL31
);
3750 demand_empty_rest_of_line ();
3753 /* Directives: AEABI stack-unwind tables. */
3755 /* Parse an unwind_fnstart directive. Simply records the current location. */
3758 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3760 demand_empty_rest_of_line ();
3761 if (unwind
.proc_start
)
3763 as_bad (_("duplicate .fnstart directive"));
3767 /* Mark the start of the function. */
3768 unwind
.proc_start
= expr_build_dot ();
3770 /* Reset the rest of the unwind info. */
3771 unwind
.opcode_count
= 0;
3772 unwind
.table_entry
= NULL
;
3773 unwind
.personality_routine
= NULL
;
3774 unwind
.personality_index
= -1;
3775 unwind
.frame_size
= 0;
3776 unwind
.fp_offset
= 0;
3777 unwind
.fp_reg
= REG_SP
;
3779 unwind
.sp_restored
= 0;
3783 /* Parse a handlerdata directive. Creates the exception handling table entry
3784 for the function. */
3787 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3789 demand_empty_rest_of_line ();
3790 if (!unwind
.proc_start
)
3791 as_bad (MISSING_FNSTART
);
3793 if (unwind
.table_entry
)
3794 as_bad (_("duplicate .handlerdata directive"));
3796 create_unwind_entry (1);
3799 /* Parse an unwind_fnend directive. Generates the index table entry. */
3802 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3807 unsigned int marked_pr_dependency
;
3809 demand_empty_rest_of_line ();
3811 if (!unwind
.proc_start
)
3813 as_bad (_(".fnend directive without .fnstart"));
3817 /* Add eh table entry. */
3818 if (unwind
.table_entry
== NULL
)
3819 val
= create_unwind_entry (0);
3823 /* Add index table entry. This is two words. */
3824 start_unwind_section (unwind
.saved_seg
, 1);
3825 frag_align (2, 0, 0);
3826 record_alignment (now_seg
, 2);
3828 ptr
= frag_more (8);
3830 where
= frag_now_fix () - 8;
3832 /* Self relative offset of the function start. */
3833 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3834 BFD_RELOC_ARM_PREL31
);
3836 /* Indicate dependency on EHABI-defined personality routines to the
3837 linker, if it hasn't been done already. */
3838 marked_pr_dependency
3839 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3840 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3841 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3843 static const char *const name
[] =
3845 "__aeabi_unwind_cpp_pr0",
3846 "__aeabi_unwind_cpp_pr1",
3847 "__aeabi_unwind_cpp_pr2"
3849 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3850 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3851 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3852 |= 1 << unwind
.personality_index
;
3856 /* Inline exception table entry. */
3857 md_number_to_chars (ptr
+ 4, val
, 4);
3859 /* Self relative offset of the table entry. */
3860 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3861 BFD_RELOC_ARM_PREL31
);
3863 /* Restore the original section. */
3864 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3866 unwind
.proc_start
= NULL
;
3870 /* Parse an unwind_cantunwind directive. */
3873 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3875 demand_empty_rest_of_line ();
3876 if (!unwind
.proc_start
)
3877 as_bad (MISSING_FNSTART
);
3879 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3880 as_bad (_("personality routine specified for cantunwind frame"));
3882 unwind
.personality_index
= -2;
3886 /* Parse a personalityindex directive. */
3889 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3893 if (!unwind
.proc_start
)
3894 as_bad (MISSING_FNSTART
);
3896 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3897 as_bad (_("duplicate .personalityindex directive"));
3901 if (exp
.X_op
!= O_constant
3902 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3904 as_bad (_("bad personality routine number"));
3905 ignore_rest_of_line ();
3909 unwind
.personality_index
= exp
.X_add_number
;
3911 demand_empty_rest_of_line ();
3915 /* Parse a personality directive. */
3918 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3922 if (!unwind
.proc_start
)
3923 as_bad (MISSING_FNSTART
);
3925 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3926 as_bad (_("duplicate .personality directive"));
3928 name
= input_line_pointer
;
3929 c
= get_symbol_end ();
3930 p
= input_line_pointer
;
3931 unwind
.personality_routine
= symbol_find_or_make (name
);
3933 demand_empty_rest_of_line ();
3937 /* Parse a directive saving core registers. */
3940 s_arm_unwind_save_core (void)
3946 range
= parse_reg_list (&input_line_pointer
);
3949 as_bad (_("expected register list"));
3950 ignore_rest_of_line ();
3954 demand_empty_rest_of_line ();
3956 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3957 into .unwind_save {..., sp...}. We aren't bothered about the value of
3958 ip because it is clobbered by calls. */
3959 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3960 && (range
& 0x3000) == 0x1000)
3962 unwind
.opcode_count
--;
3963 unwind
.sp_restored
= 0;
3964 range
= (range
| 0x2000) & ~0x1000;
3965 unwind
.pending_offset
= 0;
3971 /* See if we can use the short opcodes. These pop a block of up to 8
3972 registers starting with r4, plus maybe r14. */
3973 for (n
= 0; n
< 8; n
++)
3975 /* Break at the first non-saved register. */
3976 if ((range
& (1 << (n
+ 4))) == 0)
3979 /* See if there are any other bits set. */
3980 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3982 /* Use the long form. */
3983 op
= 0x8000 | ((range
>> 4) & 0xfff);
3984 add_unwind_opcode (op
, 2);
3988 /* Use the short form. */
3990 op
= 0xa8; /* Pop r14. */
3992 op
= 0xa0; /* Do not pop r14. */
3994 add_unwind_opcode (op
, 1);
4001 op
= 0xb100 | (range
& 0xf);
4002 add_unwind_opcode (op
, 2);
4005 /* Record the number of bytes pushed. */
4006 for (n
= 0; n
< 16; n
++)
4008 if (range
& (1 << n
))
4009 unwind
.frame_size
+= 4;
4014 /* Parse a directive saving FPA registers. */
4017 s_arm_unwind_save_fpa (int reg
)
4023 /* Get Number of registers to transfer. */
4024 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4027 exp
.X_op
= O_illegal
;
4029 if (exp
.X_op
!= O_constant
)
4031 as_bad (_("expected , <constant>"));
4032 ignore_rest_of_line ();
4036 num_regs
= exp
.X_add_number
;
4038 if (num_regs
< 1 || num_regs
> 4)
4040 as_bad (_("number of registers must be in the range [1:4]"));
4041 ignore_rest_of_line ();
4045 demand_empty_rest_of_line ();
4050 op
= 0xb4 | (num_regs
- 1);
4051 add_unwind_opcode (op
, 1);
4056 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4057 add_unwind_opcode (op
, 2);
4059 unwind
.frame_size
+= num_regs
* 12;
4063 /* Parse a directive saving VFP registers for ARMv6 and above. */
4066 s_arm_unwind_save_vfp_armv6 (void)
4071 int num_vfpv3_regs
= 0;
4072 int num_regs_below_16
;
4074 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4077 as_bad (_("expected register list"));
4078 ignore_rest_of_line ();
4082 demand_empty_rest_of_line ();
4084 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4085 than FSTMX/FLDMX-style ones). */
4087 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4089 num_vfpv3_regs
= count
;
4090 else if (start
+ count
> 16)
4091 num_vfpv3_regs
= start
+ count
- 16;
4093 if (num_vfpv3_regs
> 0)
4095 int start_offset
= start
> 16 ? start
- 16 : 0;
4096 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4097 add_unwind_opcode (op
, 2);
4100 /* Generate opcode for registers numbered in the range 0 .. 15. */
4101 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4102 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4103 if (num_regs_below_16
> 0)
4105 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4106 add_unwind_opcode (op
, 2);
4109 unwind
.frame_size
+= count
* 8;
4113 /* Parse a directive saving VFP registers for pre-ARMv6. */
4116 s_arm_unwind_save_vfp (void)
4122 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4125 as_bad (_("expected register list"));
4126 ignore_rest_of_line ();
4130 demand_empty_rest_of_line ();
4135 op
= 0xb8 | (count
- 1);
4136 add_unwind_opcode (op
, 1);
4141 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4142 add_unwind_opcode (op
, 2);
4144 unwind
.frame_size
+= count
* 8 + 4;
4148 /* Parse a directive saving iWMMXt data registers. */
4151 s_arm_unwind_save_mmxwr (void)
4159 if (*input_line_pointer
== '{')
4160 input_line_pointer
++;
4164 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4168 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4173 as_tsktsk (_("register list not in ascending order"));
4176 if (*input_line_pointer
== '-')
4178 input_line_pointer
++;
4179 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4182 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4185 else if (reg
>= hi_reg
)
4187 as_bad (_("bad register range"));
4190 for (; reg
< hi_reg
; reg
++)
4194 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4196 skip_past_char (&input_line_pointer
, '}');
4198 demand_empty_rest_of_line ();
4200 /* Generate any deferred opcodes because we're going to be looking at
4202 flush_pending_unwind ();
4204 for (i
= 0; i
< 16; i
++)
4206 if (mask
& (1 << i
))
4207 unwind
.frame_size
+= 8;
4210 /* Attempt to combine with a previous opcode. We do this because gcc
4211 likes to output separate unwind directives for a single block of
4213 if (unwind
.opcode_count
> 0)
4215 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4216 if ((i
& 0xf8) == 0xc0)
4219 /* Only merge if the blocks are contiguous. */
4222 if ((mask
& 0xfe00) == (1 << 9))
4224 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4225 unwind
.opcode_count
--;
4228 else if (i
== 6 && unwind
.opcode_count
>= 2)
4230 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4234 op
= 0xffff << (reg
- 1);
4236 && ((mask
& op
) == (1u << (reg
- 1))))
4238 op
= (1 << (reg
+ i
+ 1)) - 1;
4239 op
&= ~((1 << reg
) - 1);
4241 unwind
.opcode_count
-= 2;
4248 /* We want to generate opcodes in the order the registers have been
4249 saved, ie. descending order. */
4250 for (reg
= 15; reg
>= -1; reg
--)
4252 /* Save registers in blocks. */
4254 || !(mask
& (1 << reg
)))
4256 /* We found an unsaved reg. Generate opcodes to save the
4263 op
= 0xc0 | (hi_reg
- 10);
4264 add_unwind_opcode (op
, 1);
4269 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4270 add_unwind_opcode (op
, 2);
4279 ignore_rest_of_line ();
4283 s_arm_unwind_save_mmxwcg (void)
4290 if (*input_line_pointer
== '{')
4291 input_line_pointer
++;
4293 skip_whitespace (input_line_pointer
);
4297 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4301 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4307 as_tsktsk (_("register list not in ascending order"));
4310 if (*input_line_pointer
== '-')
4312 input_line_pointer
++;
4313 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4316 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4319 else if (reg
>= hi_reg
)
4321 as_bad (_("bad register range"));
4324 for (; reg
< hi_reg
; reg
++)
4328 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4330 skip_past_char (&input_line_pointer
, '}');
4332 demand_empty_rest_of_line ();
4334 /* Generate any deferred opcodes because we're going to be looking at
4336 flush_pending_unwind ();
4338 for (reg
= 0; reg
< 16; reg
++)
4340 if (mask
& (1 << reg
))
4341 unwind
.frame_size
+= 4;
4344 add_unwind_opcode (op
, 2);
4347 ignore_rest_of_line ();
4351 /* Parse an unwind_save directive.
4352 If the argument is non-zero, this is a .vsave directive. */
4355 s_arm_unwind_save (int arch_v6
)
4358 struct reg_entry
*reg
;
4359 bfd_boolean had_brace
= FALSE
;
4361 if (!unwind
.proc_start
)
4362 as_bad (MISSING_FNSTART
);
4364 /* Figure out what sort of save we have. */
4365 peek
= input_line_pointer
;
4373 reg
= arm_reg_parse_multi (&peek
);
4377 as_bad (_("register expected"));
4378 ignore_rest_of_line ();
4387 as_bad (_("FPA .unwind_save does not take a register list"));
4388 ignore_rest_of_line ();
4391 input_line_pointer
= peek
;
4392 s_arm_unwind_save_fpa (reg
->number
);
4396 s_arm_unwind_save_core ();
4401 s_arm_unwind_save_vfp_armv6 ();
4403 s_arm_unwind_save_vfp ();
4406 case REG_TYPE_MMXWR
:
4407 s_arm_unwind_save_mmxwr ();
4410 case REG_TYPE_MMXWCG
:
4411 s_arm_unwind_save_mmxwcg ();
4415 as_bad (_(".unwind_save does not support this kind of register"));
4416 ignore_rest_of_line ();
4421 /* Parse an unwind_movsp directive. */
4424 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4430 if (!unwind
.proc_start
)
4431 as_bad (MISSING_FNSTART
);
4433 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4436 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4437 ignore_rest_of_line ();
4441 /* Optional constant. */
4442 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4444 if (immediate_for_directive (&offset
) == FAIL
)
4450 demand_empty_rest_of_line ();
4452 if (reg
== REG_SP
|| reg
== REG_PC
)
4454 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4458 if (unwind
.fp_reg
!= REG_SP
)
4459 as_bad (_("unexpected .unwind_movsp directive"));
4461 /* Generate opcode to restore the value. */
4463 add_unwind_opcode (op
, 1);
4465 /* Record the information for later. */
4466 unwind
.fp_reg
= reg
;
4467 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4468 unwind
.sp_restored
= 1;
4471 /* Parse an unwind_pad directive. */
4474 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4478 if (!unwind
.proc_start
)
4479 as_bad (MISSING_FNSTART
);
4481 if (immediate_for_directive (&offset
) == FAIL
)
4486 as_bad (_("stack increment must be multiple of 4"));
4487 ignore_rest_of_line ();
4491 /* Don't generate any opcodes, just record the details for later. */
4492 unwind
.frame_size
+= offset
;
4493 unwind
.pending_offset
+= offset
;
4495 demand_empty_rest_of_line ();
4498 /* Parse an unwind_setfp directive. */
4501 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4507 if (!unwind
.proc_start
)
4508 as_bad (MISSING_FNSTART
);
4510 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4511 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4514 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4516 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4518 as_bad (_("expected <reg>, <reg>"));
4519 ignore_rest_of_line ();
4523 /* Optional constant. */
4524 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4526 if (immediate_for_directive (&offset
) == FAIL
)
4532 demand_empty_rest_of_line ();
4534 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4536 as_bad (_("register must be either sp or set by a previous"
4537 "unwind_movsp directive"));
4541 /* Don't generate any opcodes, just record the information for later. */
4542 unwind
.fp_reg
= fp_reg
;
4544 if (sp_reg
== REG_SP
)
4545 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4547 unwind
.fp_offset
-= offset
;
4550 /* Parse an unwind_raw directive. */
4553 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4556 /* This is an arbitrary limit. */
4557 unsigned char op
[16];
4560 if (!unwind
.proc_start
)
4561 as_bad (MISSING_FNSTART
);
4564 if (exp
.X_op
== O_constant
4565 && skip_past_comma (&input_line_pointer
) != FAIL
)
4567 unwind
.frame_size
+= exp
.X_add_number
;
4571 exp
.X_op
= O_illegal
;
4573 if (exp
.X_op
!= O_constant
)
4575 as_bad (_("expected <offset>, <opcode>"));
4576 ignore_rest_of_line ();
4582 /* Parse the opcode. */
4587 as_bad (_("unwind opcode too long"));
4588 ignore_rest_of_line ();
4590 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4592 as_bad (_("invalid unwind opcode"));
4593 ignore_rest_of_line ();
4596 op
[count
++] = exp
.X_add_number
;
4598 /* Parse the next byte. */
4599 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4605 /* Add the opcode bytes in reverse order. */
4607 add_unwind_opcode (op
[count
], 1);
4609 demand_empty_rest_of_line ();
4613 /* Parse a .eabi_attribute directive. */
4616 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4618 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4620 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4621 attributes_set_explicitly
[tag
] = 1;
4624 /* Emit a tls fix for the symbol. */
4627 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4631 #ifdef md_flush_pending_output
4632 md_flush_pending_output ();
4635 #ifdef md_cons_align
4639 /* Since we're just labelling the code, there's no need to define a
4642 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4643 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4644 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4645 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4647 #endif /* OBJ_ELF */
4649 static void s_arm_arch (int);
4650 static void s_arm_object_arch (int);
4651 static void s_arm_cpu (int);
4652 static void s_arm_fpu (int);
4653 static void s_arm_arch_extension (int);
4658 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4665 if (exp
.X_op
== O_symbol
)
4666 exp
.X_op
= O_secrel
;
4668 emit_expr (&exp
, 4);
4670 while (*input_line_pointer
++ == ',');
4672 input_line_pointer
--;
4673 demand_empty_rest_of_line ();
4677 /* This table describes all the machine specific pseudo-ops the assembler
4678 has to support. The fields are:
4679 pseudo-op name without dot
4680 function to call to execute this pseudo-op
4681 Integer arg to pass to the function. */
4683 const pseudo_typeS md_pseudo_table
[] =
4685 /* Never called because '.req' does not start a line. */
4686 { "req", s_req
, 0 },
4687 /* Following two are likewise never called. */
4690 { "unreq", s_unreq
, 0 },
4691 { "bss", s_bss
, 0 },
4692 { "align", s_align
, 0 },
4693 { "arm", s_arm
, 0 },
4694 { "thumb", s_thumb
, 0 },
4695 { "code", s_code
, 0 },
4696 { "force_thumb", s_force_thumb
, 0 },
4697 { "thumb_func", s_thumb_func
, 0 },
4698 { "thumb_set", s_thumb_set
, 0 },
4699 { "even", s_even
, 0 },
4700 { "ltorg", s_ltorg
, 0 },
4701 { "pool", s_ltorg
, 0 },
4702 { "syntax", s_syntax
, 0 },
4703 { "cpu", s_arm_cpu
, 0 },
4704 { "arch", s_arm_arch
, 0 },
4705 { "object_arch", s_arm_object_arch
, 0 },
4706 { "fpu", s_arm_fpu
, 0 },
4707 { "arch_extension", s_arm_arch_extension
, 0 },
4709 { "word", s_arm_elf_cons
, 4 },
4710 { "long", s_arm_elf_cons
, 4 },
4711 { "inst.n", s_arm_elf_inst
, 2 },
4712 { "inst.w", s_arm_elf_inst
, 4 },
4713 { "inst", s_arm_elf_inst
, 0 },
4714 { "rel31", s_arm_rel31
, 0 },
4715 { "fnstart", s_arm_unwind_fnstart
, 0 },
4716 { "fnend", s_arm_unwind_fnend
, 0 },
4717 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4718 { "personality", s_arm_unwind_personality
, 0 },
4719 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4720 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4721 { "save", s_arm_unwind_save
, 0 },
4722 { "vsave", s_arm_unwind_save
, 1 },
4723 { "movsp", s_arm_unwind_movsp
, 0 },
4724 { "pad", s_arm_unwind_pad
, 0 },
4725 { "setfp", s_arm_unwind_setfp
, 0 },
4726 { "unwind_raw", s_arm_unwind_raw
, 0 },
4727 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4728 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4732 /* These are used for dwarf. */
4736 /* These are used for dwarf2. */
4737 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4738 { "loc", dwarf2_directive_loc
, 0 },
4739 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4741 { "extend", float_cons
, 'x' },
4742 { "ldouble", float_cons
, 'x' },
4743 { "packed", float_cons
, 'p' },
4745 {"secrel32", pe_directive_secrel
, 0},
4748 /* These are for compatibility with CodeComposer Studio. */
4749 {"ref", s_ccs_ref
, 0},
4750 {"def", s_ccs_def
, 0},
4751 {"asmfunc", s_ccs_asmfunc
, 0},
4752 {"endasmfunc", s_ccs_endasmfunc
, 0},
4757 /* Parser functions used exclusively in instruction operands. */
4759 /* Generic immediate-value read function for use in insn parsing.
4760 STR points to the beginning of the immediate (the leading #);
4761 VAL receives the value; if the value is outside [MIN, MAX]
4762 issue an error. PREFIX_OPT is true if the immediate prefix is
4766 parse_immediate (char **str
, int *val
, int min
, int max
,
4767 bfd_boolean prefix_opt
)
4770 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4771 if (exp
.X_op
!= O_constant
)
4773 inst
.error
= _("constant expression required");
4777 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4779 inst
.error
= _("immediate value out of range");
4783 *val
= exp
.X_add_number
;
4787 /* Less-generic immediate-value read function with the possibility of loading a
4788 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4789 instructions. Puts the result directly in inst.operands[i]. */
4792 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4793 bfd_boolean allow_symbol_p
)
4796 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4799 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4801 if (exp_p
->X_op
== O_constant
)
4803 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4804 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4805 O_constant. We have to be careful not to break compilation for
4806 32-bit X_add_number, though. */
4807 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4809 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4810 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4812 inst
.operands
[i
].regisimm
= 1;
4815 else if (exp_p
->X_op
== O_big
4816 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4818 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4820 /* Bignums have their least significant bits in
4821 generic_bignum[0]. Make sure we put 32 bits in imm and
4822 32 bits in reg, in a (hopefully) portable way. */
4823 gas_assert (parts
!= 0);
4825 /* Make sure that the number is not too big.
4826 PR 11972: Bignums can now be sign-extended to the
4827 size of a .octa so check that the out of range bits
4828 are all zero or all one. */
4829 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4831 LITTLENUM_TYPE m
= -1;
4833 if (generic_bignum
[parts
* 2] != 0
4834 && generic_bignum
[parts
* 2] != m
)
4837 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4838 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4842 inst
.operands
[i
].imm
= 0;
4843 for (j
= 0; j
< parts
; j
++, idx
++)
4844 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4845 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4846 inst
.operands
[i
].reg
= 0;
4847 for (j
= 0; j
< parts
; j
++, idx
++)
4848 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4849 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4850 inst
.operands
[i
].regisimm
= 1;
4852 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4860 /* Returns the pseudo-register number of an FPA immediate constant,
4861 or FAIL if there isn't a valid constant here. */
4864 parse_fpa_immediate (char ** str
)
4866 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4872 /* First try and match exact strings, this is to guarantee
4873 that some formats will work even for cross assembly. */
4875 for (i
= 0; fp_const
[i
]; i
++)
4877 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4881 *str
+= strlen (fp_const
[i
]);
4882 if (is_end_of_line
[(unsigned char) **str
])
4888 /* Just because we didn't get a match doesn't mean that the constant
4889 isn't valid, just that it is in a format that we don't
4890 automatically recognize. Try parsing it with the standard
4891 expression routines. */
4893 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4895 /* Look for a raw floating point number. */
4896 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4897 && is_end_of_line
[(unsigned char) *save_in
])
4899 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4901 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4903 if (words
[j
] != fp_values
[i
][j
])
4907 if (j
== MAX_LITTLENUMS
)
4915 /* Try and parse a more complex expression, this will probably fail
4916 unless the code uses a floating point prefix (eg "0f"). */
4917 save_in
= input_line_pointer
;
4918 input_line_pointer
= *str
;
4919 if (expression (&exp
) == absolute_section
4920 && exp
.X_op
== O_big
4921 && exp
.X_add_number
< 0)
4923 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4925 if (gen_to_words (words
, 5, (long) 15) == 0)
4927 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4929 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4931 if (words
[j
] != fp_values
[i
][j
])
4935 if (j
== MAX_LITTLENUMS
)
4937 *str
= input_line_pointer
;
4938 input_line_pointer
= save_in
;
4945 *str
= input_line_pointer
;
4946 input_line_pointer
= save_in
;
4947 inst
.error
= _("invalid FPA immediate expression");
4951 /* Returns 1 if a number has "quarter-precision" float format
4952 0baBbbbbbc defgh000 00000000 00000000. */
4955 is_quarter_float (unsigned imm
)
4957 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4958 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4962 /* Detect the presence of a floating point or integer zero constant,
4966 parse_ifimm_zero (char **in
)
4970 if (!is_immediate_prefix (**in
))
4975 /* Accept #0x0 as a synonym for #0. */
4976 if (strncmp (*in
, "0x", 2) == 0)
4979 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4984 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4985 &generic_floating_point_number
);
4988 && generic_floating_point_number
.sign
== '+'
4989 && (generic_floating_point_number
.low
4990 > generic_floating_point_number
.leader
))
4996 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4997 0baBbbbbbc defgh000 00000000 00000000.
4998 The zero and minus-zero cases need special handling, since they can't be
4999 encoded in the "quarter-precision" float format, but can nonetheless be
5000 loaded as integer constants. */
5003 parse_qfloat_immediate (char **ccp
, int *immed
)
5007 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5008 int found_fpchar
= 0;
5010 skip_past_char (&str
, '#');
5012 /* We must not accidentally parse an integer as a floating-point number. Make
5013 sure that the value we parse is not an integer by checking for special
5014 characters '.' or 'e'.
5015 FIXME: This is a horrible hack, but doing better is tricky because type
5016 information isn't in a very usable state at parse time. */
5018 skip_whitespace (fpnum
);
5020 if (strncmp (fpnum
, "0x", 2) == 0)
5024 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5025 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5035 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5037 unsigned fpword
= 0;
5040 /* Our FP word must be 32 bits (single-precision FP). */
5041 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5043 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5047 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5060 /* Shift operands. */
5063 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5066 struct asm_shift_name
5069 enum shift_kind kind
;
5072 /* Third argument to parse_shift. */
5073 enum parse_shift_mode
5075 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5076 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5077 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5078 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5079 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5082 /* Parse a <shift> specifier on an ARM data processing instruction.
5083 This has three forms:
5085 (LSL|LSR|ASL|ASR|ROR) Rs
5086 (LSL|LSR|ASL|ASR|ROR) #imm
5089 Note that ASL is assimilated to LSL in the instruction encoding, and
5090 RRX to ROR #0 (which cannot be written as such). */
5093 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5095 const struct asm_shift_name
*shift_name
;
5096 enum shift_kind shift
;
5101 for (p
= *str
; ISALPHA (*p
); p
++)
5106 inst
.error
= _("shift expression expected");
5110 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5113 if (shift_name
== NULL
)
5115 inst
.error
= _("shift expression expected");
5119 shift
= shift_name
->kind
;
5123 case NO_SHIFT_RESTRICT
:
5124 case SHIFT_IMMEDIATE
: break;
5126 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5127 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5129 inst
.error
= _("'LSL' or 'ASR' required");
5134 case SHIFT_LSL_IMMEDIATE
:
5135 if (shift
!= SHIFT_LSL
)
5137 inst
.error
= _("'LSL' required");
5142 case SHIFT_ASR_IMMEDIATE
:
5143 if (shift
!= SHIFT_ASR
)
5145 inst
.error
= _("'ASR' required");
5153 if (shift
!= SHIFT_RRX
)
5155 /* Whitespace can appear here if the next thing is a bare digit. */
5156 skip_whitespace (p
);
5158 if (mode
== NO_SHIFT_RESTRICT
5159 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5161 inst
.operands
[i
].imm
= reg
;
5162 inst
.operands
[i
].immisreg
= 1;
5164 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5167 inst
.operands
[i
].shift_kind
= shift
;
5168 inst
.operands
[i
].shifted
= 1;
5173 /* Parse a <shifter_operand> for an ARM data processing instruction:
5176 #<immediate>, <rotate>
5180 where <shift> is defined by parse_shift above, and <rotate> is a
5181 multiple of 2 between 0 and 30. Validation of immediate operands
5182 is deferred to md_apply_fix. */
5185 parse_shifter_operand (char **str
, int i
)
5190 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5192 inst
.operands
[i
].reg
= value
;
5193 inst
.operands
[i
].isreg
= 1;
5195 /* parse_shift will override this if appropriate */
5196 inst
.reloc
.exp
.X_op
= O_constant
;
5197 inst
.reloc
.exp
.X_add_number
= 0;
5199 if (skip_past_comma (str
) == FAIL
)
5202 /* Shift operation on register. */
5203 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5206 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5209 if (skip_past_comma (str
) == SUCCESS
)
5211 /* #x, y -- ie explicit rotation by Y. */
5212 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5215 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5217 inst
.error
= _("constant expression expected");
5221 value
= exp
.X_add_number
;
5222 if (value
< 0 || value
> 30 || value
% 2 != 0)
5224 inst
.error
= _("invalid rotation");
5227 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5229 inst
.error
= _("invalid constant");
5233 /* Encode as specified. */
5234 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5238 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5239 inst
.reloc
.pc_rel
= 0;
5243 /* Group relocation information. Each entry in the table contains the
5244 textual name of the relocation as may appear in assembler source
5245 and must end with a colon.
5246 Along with this textual name are the relocation codes to be used if
5247 the corresponding instruction is an ALU instruction (ADD or SUB only),
5248 an LDR, an LDRS, or an LDC. */
5250 struct group_reloc_table_entry
5261 /* Varieties of non-ALU group relocation. */
5268 static struct group_reloc_table_entry group_reloc_table
[] =
5269 { /* Program counter relative: */
5271 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5276 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5277 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5278 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5279 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5281 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5286 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5287 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5288 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5289 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5291 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5292 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5293 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5294 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5295 /* Section base relative */
5297 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5302 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5303 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5304 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5305 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5307 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5312 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5313 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5314 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5315 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5317 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5318 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5319 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5320 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
5322 /* Given the address of a pointer pointing to the textual name of a group
5323 relocation as may appear in assembler source, attempt to find its details
5324 in group_reloc_table. The pointer will be updated to the character after
5325 the trailing colon. On failure, FAIL will be returned; SUCCESS
5326 otherwise. On success, *entry will be updated to point at the relevant
5327 group_reloc_table entry. */
5330 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5333 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5335 int length
= strlen (group_reloc_table
[i
].name
);
5337 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5338 && (*str
)[length
] == ':')
5340 *out
= &group_reloc_table
[i
];
5341 *str
+= (length
+ 1);
5349 /* Parse a <shifter_operand> for an ARM data processing instruction
5350 (as for parse_shifter_operand) where group relocations are allowed:
5353 #<immediate>, <rotate>
5354 #:<group_reloc>:<expression>
5358 where <group_reloc> is one of the strings defined in group_reloc_table.
5359 The hashes are optional.
5361 Everything else is as for parse_shifter_operand. */
5363 static parse_operand_result
5364 parse_shifter_operand_group_reloc (char **str
, int i
)
5366 /* Determine if we have the sequence of characters #: or just :
5367 coming next. If we do, then we check for a group relocation.
5368 If we don't, punt the whole lot to parse_shifter_operand. */
5370 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5371 || (*str
)[0] == ':')
5373 struct group_reloc_table_entry
*entry
;
5375 if ((*str
)[0] == '#')
5380 /* Try to parse a group relocation. Anything else is an error. */
5381 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5383 inst
.error
= _("unknown group relocation");
5384 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5387 /* We now have the group relocation table entry corresponding to
5388 the name in the assembler source. Next, we parse the expression. */
5389 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5390 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5392 /* Record the relocation type (always the ALU variant here). */
5393 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5394 gas_assert (inst
.reloc
.type
!= 0);
5396 return PARSE_OPERAND_SUCCESS
;
5399 return parse_shifter_operand (str
, i
) == SUCCESS
5400 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5402 /* Never reached. */
5405 /* Parse a Neon alignment expression. Information is written to
5406 inst.operands[i]. We assume the initial ':' has been skipped.
5408 align .imm = align << 8, .immisalign=1, .preind=0 */
5409 static parse_operand_result
5410 parse_neon_alignment (char **str
, int i
)
5415 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5417 if (exp
.X_op
!= O_constant
)
5419 inst
.error
= _("alignment must be constant");
5420 return PARSE_OPERAND_FAIL
;
5423 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5424 inst
.operands
[i
].immisalign
= 1;
5425 /* Alignments are not pre-indexes. */
5426 inst
.operands
[i
].preind
= 0;
5429 return PARSE_OPERAND_SUCCESS
;
5432 /* Parse all forms of an ARM address expression. Information is written
5433 to inst.operands[i] and/or inst.reloc.
5435 Preindexed addressing (.preind=1):
5437 [Rn, #offset] .reg=Rn .reloc.exp=offset
5438 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5439 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5440 .shift_kind=shift .reloc.exp=shift_imm
5442 These three may have a trailing ! which causes .writeback to be set also.
5444 Postindexed addressing (.postind=1, .writeback=1):
5446 [Rn], #offset .reg=Rn .reloc.exp=offset
5447 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5448 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5449 .shift_kind=shift .reloc.exp=shift_imm
5451 Unindexed addressing (.preind=0, .postind=0):
5453 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5457 [Rn]{!} shorthand for [Rn,#0]{!}
5458 =immediate .isreg=0 .reloc.exp=immediate
5459 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5461 It is the caller's responsibility to check for addressing modes not
5462 supported by the instruction, and to set inst.reloc.type. */
5464 static parse_operand_result
5465 parse_address_main (char **str
, int i
, int group_relocations
,
5466 group_reloc_type group_type
)
5471 if (skip_past_char (&p
, '[') == FAIL
)
5473 if (skip_past_char (&p
, '=') == FAIL
)
5475 /* Bare address - translate to PC-relative offset. */
5476 inst
.reloc
.pc_rel
= 1;
5477 inst
.operands
[i
].reg
= REG_PC
;
5478 inst
.operands
[i
].isreg
= 1;
5479 inst
.operands
[i
].preind
= 1;
5481 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5482 return PARSE_OPERAND_FAIL
;
5484 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5485 /*allow_symbol_p=*/TRUE
))
5486 return PARSE_OPERAND_FAIL
;
5489 return PARSE_OPERAND_SUCCESS
;
5492 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5493 skip_whitespace (p
);
5495 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5497 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5498 return PARSE_OPERAND_FAIL
;
5500 inst
.operands
[i
].reg
= reg
;
5501 inst
.operands
[i
].isreg
= 1;
5503 if (skip_past_comma (&p
) == SUCCESS
)
5505 inst
.operands
[i
].preind
= 1;
5508 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5510 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5512 inst
.operands
[i
].imm
= reg
;
5513 inst
.operands
[i
].immisreg
= 1;
5515 if (skip_past_comma (&p
) == SUCCESS
)
5516 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5517 return PARSE_OPERAND_FAIL
;
5519 else if (skip_past_char (&p
, ':') == SUCCESS
)
5521 /* FIXME: '@' should be used here, but it's filtered out by generic
5522 code before we get to see it here. This may be subject to
5524 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5526 if (result
!= PARSE_OPERAND_SUCCESS
)
5531 if (inst
.operands
[i
].negative
)
5533 inst
.operands
[i
].negative
= 0;
5537 if (group_relocations
5538 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5540 struct group_reloc_table_entry
*entry
;
5542 /* Skip over the #: or : sequence. */
5548 /* Try to parse a group relocation. Anything else is an
5550 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5552 inst
.error
= _("unknown group relocation");
5553 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5556 /* We now have the group relocation table entry corresponding to
5557 the name in the assembler source. Next, we parse the
5559 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5560 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5562 /* Record the relocation type. */
5566 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5570 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5574 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5581 if (inst
.reloc
.type
== 0)
5583 inst
.error
= _("this group relocation is not allowed on this instruction");
5584 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5590 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5591 return PARSE_OPERAND_FAIL
;
5592 /* If the offset is 0, find out if it's a +0 or -0. */
5593 if (inst
.reloc
.exp
.X_op
== O_constant
5594 && inst
.reloc
.exp
.X_add_number
== 0)
5596 skip_whitespace (q
);
5600 skip_whitespace (q
);
5603 inst
.operands
[i
].negative
= 1;
5608 else if (skip_past_char (&p
, ':') == SUCCESS
)
5610 /* FIXME: '@' should be used here, but it's filtered out by generic code
5611 before we get to see it here. This may be subject to change. */
5612 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5614 if (result
!= PARSE_OPERAND_SUCCESS
)
5618 if (skip_past_char (&p
, ']') == FAIL
)
5620 inst
.error
= _("']' expected");
5621 return PARSE_OPERAND_FAIL
;
5624 if (skip_past_char (&p
, '!') == SUCCESS
)
5625 inst
.operands
[i
].writeback
= 1;
5627 else if (skip_past_comma (&p
) == SUCCESS
)
5629 if (skip_past_char (&p
, '{') == SUCCESS
)
5631 /* [Rn], {expr} - unindexed, with option */
5632 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5633 0, 255, TRUE
) == FAIL
)
5634 return PARSE_OPERAND_FAIL
;
5636 if (skip_past_char (&p
, '}') == FAIL
)
5638 inst
.error
= _("'}' expected at end of 'option' field");
5639 return PARSE_OPERAND_FAIL
;
5641 if (inst
.operands
[i
].preind
)
5643 inst
.error
= _("cannot combine index with option");
5644 return PARSE_OPERAND_FAIL
;
5647 return PARSE_OPERAND_SUCCESS
;
5651 inst
.operands
[i
].postind
= 1;
5652 inst
.operands
[i
].writeback
= 1;
5654 if (inst
.operands
[i
].preind
)
5656 inst
.error
= _("cannot combine pre- and post-indexing");
5657 return PARSE_OPERAND_FAIL
;
5661 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5663 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5665 /* We might be using the immediate for alignment already. If we
5666 are, OR the register number into the low-order bits. */
5667 if (inst
.operands
[i
].immisalign
)
5668 inst
.operands
[i
].imm
|= reg
;
5670 inst
.operands
[i
].imm
= reg
;
5671 inst
.operands
[i
].immisreg
= 1;
5673 if (skip_past_comma (&p
) == SUCCESS
)
5674 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5675 return PARSE_OPERAND_FAIL
;
5680 if (inst
.operands
[i
].negative
)
5682 inst
.operands
[i
].negative
= 0;
5685 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5686 return PARSE_OPERAND_FAIL
;
5687 /* If the offset is 0, find out if it's a +0 or -0. */
5688 if (inst
.reloc
.exp
.X_op
== O_constant
5689 && inst
.reloc
.exp
.X_add_number
== 0)
5691 skip_whitespace (q
);
5695 skip_whitespace (q
);
5698 inst
.operands
[i
].negative
= 1;
5704 /* If at this point neither .preind nor .postind is set, we have a
5705 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5706 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5708 inst
.operands
[i
].preind
= 1;
5709 inst
.reloc
.exp
.X_op
= O_constant
;
5710 inst
.reloc
.exp
.X_add_number
= 0;
5713 return PARSE_OPERAND_SUCCESS
;
5717 parse_address (char **str
, int i
)
5719 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5723 static parse_operand_result
5724 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5726 return parse_address_main (str
, i
, 1, type
);
5729 /* Parse an operand for a MOVW or MOVT instruction. */
5731 parse_half (char **str
)
5736 skip_past_char (&p
, '#');
5737 if (strncasecmp (p
, ":lower16:", 9) == 0)
5738 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5739 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5740 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5742 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5745 skip_whitespace (p
);
5748 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5751 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5753 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5755 inst
.error
= _("constant expression expected");
5758 if (inst
.reloc
.exp
.X_add_number
< 0
5759 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5761 inst
.error
= _("immediate value out of range");
5769 /* Miscellaneous. */
5771 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5772 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5774 parse_psr (char **str
, bfd_boolean lhs
)
5777 unsigned long psr_field
;
5778 const struct asm_psr
*psr
;
5780 bfd_boolean is_apsr
= FALSE
;
5781 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5783 /* PR gas/12698: If the user has specified -march=all then m_profile will
5784 be TRUE, but we want to ignore it in this case as we are building for any
5785 CPU type, including non-m variants. */
5786 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5789 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5790 feature for ease of use and backwards compatibility. */
5792 if (strncasecmp (p
, "SPSR", 4) == 0)
5795 goto unsupported_psr
;
5797 psr_field
= SPSR_BIT
;
5799 else if (strncasecmp (p
, "CPSR", 4) == 0)
5802 goto unsupported_psr
;
5806 else if (strncasecmp (p
, "APSR", 4) == 0)
5808 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5809 and ARMv7-R architecture CPUs. */
5818 while (ISALNUM (*p
) || *p
== '_');
5820 if (strncasecmp (start
, "iapsr", 5) == 0
5821 || strncasecmp (start
, "eapsr", 5) == 0
5822 || strncasecmp (start
, "xpsr", 4) == 0
5823 || strncasecmp (start
, "psr", 3) == 0)
5824 p
= start
+ strcspn (start
, "rR") + 1;
5826 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5832 /* If APSR is being written, a bitfield may be specified. Note that
5833 APSR itself is handled above. */
5834 if (psr
->field
<= 3)
5836 psr_field
= psr
->field
;
5842 /* M-profile MSR instructions have the mask field set to "10", except
5843 *PSR variants which modify APSR, which may use a different mask (and
5844 have been handled already). Do that by setting the PSR_f field
5846 return psr
->field
| (lhs
? PSR_f
: 0);
5849 goto unsupported_psr
;
5855 /* A suffix follows. */
5861 while (ISALNUM (*p
) || *p
== '_');
5865 /* APSR uses a notation for bits, rather than fields. */
5866 unsigned int nzcvq_bits
= 0;
5867 unsigned int g_bit
= 0;
5870 for (bit
= start
; bit
!= p
; bit
++)
5872 switch (TOLOWER (*bit
))
5875 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5879 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5883 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5887 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5891 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5895 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5899 inst
.error
= _("unexpected bit specified after APSR");
5904 if (nzcvq_bits
== 0x1f)
5909 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5911 inst
.error
= _("selected processor does not "
5912 "support DSP extension");
5919 if ((nzcvq_bits
& 0x20) != 0
5920 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5921 || (g_bit
& 0x2) != 0)
5923 inst
.error
= _("bad bitmask specified after APSR");
5929 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5934 psr_field
|= psr
->field
;
5940 goto error
; /* Garbage after "[CS]PSR". */
5942 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5943 is deprecated, but allow it anyway. */
5947 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5950 else if (!m_profile
)
5951 /* These bits are never right for M-profile devices: don't set them
5952 (only code paths which read/write APSR reach here). */
5953 psr_field
|= (PSR_c
| PSR_f
);
5959 inst
.error
= _("selected processor does not support requested special "
5960 "purpose register");
5964 inst
.error
= _("flag for {c}psr instruction expected");
5968 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5969 value suitable for splatting into the AIF field of the instruction. */
5972 parse_cps_flags (char **str
)
5981 case '\0': case ',':
5984 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5985 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5986 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5989 inst
.error
= _("unrecognized CPS flag");
5994 if (saw_a_flag
== 0)
5996 inst
.error
= _("missing CPS flags");
6004 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6005 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6008 parse_endian_specifier (char **str
)
6013 if (strncasecmp (s
, "BE", 2))
6015 else if (strncasecmp (s
, "LE", 2))
6019 inst
.error
= _("valid endian specifiers are be or le");
6023 if (ISALNUM (s
[2]) || s
[2] == '_')
6025 inst
.error
= _("valid endian specifiers are be or le");
6030 return little_endian
;
6033 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6034 value suitable for poking into the rotate field of an sxt or sxta
6035 instruction, or FAIL on error. */
6038 parse_ror (char **str
)
6043 if (strncasecmp (s
, "ROR", 3) == 0)
6047 inst
.error
= _("missing rotation field after comma");
6051 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6056 case 0: *str
= s
; return 0x0;
6057 case 8: *str
= s
; return 0x1;
6058 case 16: *str
= s
; return 0x2;
6059 case 24: *str
= s
; return 0x3;
6062 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6067 /* Parse a conditional code (from conds[] below). The value returned is in the
6068 range 0 .. 14, or FAIL. */
6070 parse_cond (char **str
)
6073 const struct asm_cond
*c
;
6075 /* Condition codes are always 2 characters, so matching up to
6076 3 characters is sufficient. */
6081 while (ISALPHA (*q
) && n
< 3)
6083 cond
[n
] = TOLOWER (*q
);
6088 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6091 inst
.error
= _("condition required");
6099 /* If the given feature available in the selected CPU, mark it as used.
6100 Returns TRUE iff feature is available. */
6102 mark_feature_used (const arm_feature_set
*feature
)
6104 /* Ensure the option is valid on the current architecture. */
6105 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6108 /* Add the appropriate architecture feature for the barrier option used.
6111 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6113 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6118 /* Parse an option for a barrier instruction. Returns the encoding for the
6121 parse_barrier (char **str
)
6124 const struct asm_barrier_opt
*o
;
6127 while (ISALPHA (*q
))
6130 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6135 if (!mark_feature_used (&o
->arch
))
6142 /* Parse the operands of a table branch instruction. Similar to a memory
6145 parse_tb (char **str
)
6150 if (skip_past_char (&p
, '[') == FAIL
)
6152 inst
.error
= _("'[' expected");
6156 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6158 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6161 inst
.operands
[0].reg
= reg
;
6163 if (skip_past_comma (&p
) == FAIL
)
6165 inst
.error
= _("',' expected");
6169 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6171 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6174 inst
.operands
[0].imm
= reg
;
6176 if (skip_past_comma (&p
) == SUCCESS
)
6178 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6180 if (inst
.reloc
.exp
.X_add_number
!= 1)
6182 inst
.error
= _("invalid shift");
6185 inst
.operands
[0].shifted
= 1;
6188 if (skip_past_char (&p
, ']') == FAIL
)
6190 inst
.error
= _("']' expected");
6197 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6198 information on the types the operands can take and how they are encoded.
6199 Up to four operands may be read; this function handles setting the
6200 ".present" field for each read operand itself.
6201 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6202 else returns FAIL. */
6205 parse_neon_mov (char **str
, int *which_operand
)
6207 int i
= *which_operand
, val
;
6208 enum arm_reg_type rtype
;
6210 struct neon_type_el optype
;
6212 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6214 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6215 inst
.operands
[i
].reg
= val
;
6216 inst
.operands
[i
].isscalar
= 1;
6217 inst
.operands
[i
].vectype
= optype
;
6218 inst
.operands
[i
++].present
= 1;
6220 if (skip_past_comma (&ptr
) == FAIL
)
6223 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6226 inst
.operands
[i
].reg
= val
;
6227 inst
.operands
[i
].isreg
= 1;
6228 inst
.operands
[i
].present
= 1;
6230 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6233 /* Cases 0, 1, 2, 3, 5 (D only). */
6234 if (skip_past_comma (&ptr
) == FAIL
)
6237 inst
.operands
[i
].reg
= val
;
6238 inst
.operands
[i
].isreg
= 1;
6239 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6240 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6241 inst
.operands
[i
].isvec
= 1;
6242 inst
.operands
[i
].vectype
= optype
;
6243 inst
.operands
[i
++].present
= 1;
6245 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6247 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6248 Case 13: VMOV <Sd>, <Rm> */
6249 inst
.operands
[i
].reg
= val
;
6250 inst
.operands
[i
].isreg
= 1;
6251 inst
.operands
[i
].present
= 1;
6253 if (rtype
== REG_TYPE_NQ
)
6255 first_error (_("can't use Neon quad register here"));
6258 else if (rtype
!= REG_TYPE_VFS
)
6261 if (skip_past_comma (&ptr
) == FAIL
)
6263 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6265 inst
.operands
[i
].reg
= val
;
6266 inst
.operands
[i
].isreg
= 1;
6267 inst
.operands
[i
].present
= 1;
6270 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6273 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6274 Case 1: VMOV<c><q> <Dd>, <Dm>
6275 Case 8: VMOV.F32 <Sd>, <Sm>
6276 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6278 inst
.operands
[i
].reg
= val
;
6279 inst
.operands
[i
].isreg
= 1;
6280 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6281 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6282 inst
.operands
[i
].isvec
= 1;
6283 inst
.operands
[i
].vectype
= optype
;
6284 inst
.operands
[i
].present
= 1;
6286 if (skip_past_comma (&ptr
) == SUCCESS
)
6291 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6294 inst
.operands
[i
].reg
= val
;
6295 inst
.operands
[i
].isreg
= 1;
6296 inst
.operands
[i
++].present
= 1;
6298 if (skip_past_comma (&ptr
) == FAIL
)
6301 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6304 inst
.operands
[i
].reg
= val
;
6305 inst
.operands
[i
].isreg
= 1;
6306 inst
.operands
[i
].present
= 1;
6309 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6310 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6311 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6312 Case 10: VMOV.F32 <Sd>, #<imm>
6313 Case 11: VMOV.F64 <Dd>, #<imm> */
6314 inst
.operands
[i
].immisfloat
= 1;
6315 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6317 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6318 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6322 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6326 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6329 inst
.operands
[i
].reg
= val
;
6330 inst
.operands
[i
].isreg
= 1;
6331 inst
.operands
[i
++].present
= 1;
6333 if (skip_past_comma (&ptr
) == FAIL
)
6336 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6338 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6339 inst
.operands
[i
].reg
= val
;
6340 inst
.operands
[i
].isscalar
= 1;
6341 inst
.operands
[i
].present
= 1;
6342 inst
.operands
[i
].vectype
= optype
;
6344 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6346 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6347 inst
.operands
[i
].reg
= val
;
6348 inst
.operands
[i
].isreg
= 1;
6349 inst
.operands
[i
++].present
= 1;
6351 if (skip_past_comma (&ptr
) == FAIL
)
6354 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6357 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6361 inst
.operands
[i
].reg
= val
;
6362 inst
.operands
[i
].isreg
= 1;
6363 inst
.operands
[i
].isvec
= 1;
6364 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6365 inst
.operands
[i
].vectype
= optype
;
6366 inst
.operands
[i
].present
= 1;
6368 if (rtype
== REG_TYPE_VFS
)
6372 if (skip_past_comma (&ptr
) == FAIL
)
6374 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6377 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6380 inst
.operands
[i
].reg
= val
;
6381 inst
.operands
[i
].isreg
= 1;
6382 inst
.operands
[i
].isvec
= 1;
6383 inst
.operands
[i
].issingle
= 1;
6384 inst
.operands
[i
].vectype
= optype
;
6385 inst
.operands
[i
].present
= 1;
6388 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6392 inst
.operands
[i
].reg
= val
;
6393 inst
.operands
[i
].isreg
= 1;
6394 inst
.operands
[i
].isvec
= 1;
6395 inst
.operands
[i
].issingle
= 1;
6396 inst
.operands
[i
].vectype
= optype
;
6397 inst
.operands
[i
].present
= 1;
6402 first_error (_("parse error"));
6406 /* Successfully parsed the operands. Update args. */
6412 first_error (_("expected comma"));
6416 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6420 /* Use this macro when the operand constraints are different
6421 for ARM and THUMB (e.g. ldrd). */
6422 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6423 ((arm_operand) | ((thumb_operand) << 16))
6425 /* Matcher codes for parse_operands. */
6426 enum operand_parse_code
6428 OP_stop
, /* end of line */
6430 OP_RR
, /* ARM register */
6431 OP_RRnpc
, /* ARM register, not r15 */
6432 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6433 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6434 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6435 optional trailing ! */
6436 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6437 OP_RCP
, /* Coprocessor number */
6438 OP_RCN
, /* Coprocessor register */
6439 OP_RF
, /* FPA register */
6440 OP_RVS
, /* VFP single precision register */
6441 OP_RVD
, /* VFP double precision register (0..15) */
6442 OP_RND
, /* Neon double precision register (0..31) */
6443 OP_RNQ
, /* Neon quad precision register */
6444 OP_RVSD
, /* VFP single or double precision register */
6445 OP_RNDQ
, /* Neon double or quad precision register */
6446 OP_RNSDQ
, /* Neon single, double or quad precision register */
6447 OP_RNSC
, /* Neon scalar D[X] */
6448 OP_RVC
, /* VFP control register */
6449 OP_RMF
, /* Maverick F register */
6450 OP_RMD
, /* Maverick D register */
6451 OP_RMFX
, /* Maverick FX register */
6452 OP_RMDX
, /* Maverick DX register */
6453 OP_RMAX
, /* Maverick AX register */
6454 OP_RMDS
, /* Maverick DSPSC register */
6455 OP_RIWR
, /* iWMMXt wR register */
6456 OP_RIWC
, /* iWMMXt wC register */
6457 OP_RIWG
, /* iWMMXt wCG register */
6458 OP_RXA
, /* XScale accumulator register */
6460 OP_REGLST
, /* ARM register list */
6461 OP_VRSLST
, /* VFP single-precision register list */
6462 OP_VRDLST
, /* VFP double-precision register list */
6463 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6464 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6465 OP_NSTRLST
, /* Neon element/structure list */
6467 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6468 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6469 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6470 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6471 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6472 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6473 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6474 OP_VMOV
, /* Neon VMOV operands. */
6475 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6476 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6477 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6479 OP_I0
, /* immediate zero */
6480 OP_I7
, /* immediate value 0 .. 7 */
6481 OP_I15
, /* 0 .. 15 */
6482 OP_I16
, /* 1 .. 16 */
6483 OP_I16z
, /* 0 .. 16 */
6484 OP_I31
, /* 0 .. 31 */
6485 OP_I31w
, /* 0 .. 31, optional trailing ! */
6486 OP_I32
, /* 1 .. 32 */
6487 OP_I32z
, /* 0 .. 32 */
6488 OP_I63
, /* 0 .. 63 */
6489 OP_I63s
, /* -64 .. 63 */
6490 OP_I64
, /* 1 .. 64 */
6491 OP_I64z
, /* 0 .. 64 */
6492 OP_I255
, /* 0 .. 255 */
6494 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6495 OP_I7b
, /* 0 .. 7 */
6496 OP_I15b
, /* 0 .. 15 */
6497 OP_I31b
, /* 0 .. 31 */
6499 OP_SH
, /* shifter operand */
6500 OP_SHG
, /* shifter operand with possible group relocation */
6501 OP_ADDR
, /* Memory address expression (any mode) */
6502 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6503 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6504 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6505 OP_EXP
, /* arbitrary expression */
6506 OP_EXPi
, /* same, with optional immediate prefix */
6507 OP_EXPr
, /* same, with optional relocation suffix */
6508 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6510 OP_CPSF
, /* CPS flags */
6511 OP_ENDI
, /* Endianness specifier */
6512 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6513 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6514 OP_COND
, /* conditional code */
6515 OP_TB
, /* Table branch. */
6517 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6519 OP_RRnpc_I0
, /* ARM register or literal 0 */
6520 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6521 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6522 OP_RF_IF
, /* FPA register or immediate */
6523 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6524 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6526 /* Optional operands. */
6527 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6528 OP_oI31b
, /* 0 .. 31 */
6529 OP_oI32b
, /* 1 .. 32 */
6530 OP_oI32z
, /* 0 .. 32 */
6531 OP_oIffffb
, /* 0 .. 65535 */
6532 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6534 OP_oRR
, /* ARM register */
6535 OP_oRRnpc
, /* ARM register, not the PC */
6536 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6537 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6538 OP_oRND
, /* Optional Neon double precision register */
6539 OP_oRNQ
, /* Optional Neon quad precision register */
6540 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6541 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6542 OP_oSHll
, /* LSL immediate */
6543 OP_oSHar
, /* ASR immediate */
6544 OP_oSHllar
, /* LSL or ASR immediate */
6545 OP_oROR
, /* ROR 0/8/16/24 */
6546 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6548 /* Some pre-defined mixed (ARM/THUMB) operands. */
6549 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6550 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6551 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6553 OP_FIRST_OPTIONAL
= OP_oI7b
6556 /* Generic instruction operand parser. This does no encoding and no
6557 semantic validation; it merely squirrels values away in the inst
6558 structure. Returns SUCCESS or FAIL depending on whether the
6559 specified grammar matched. */
6561 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6563 unsigned const int *upat
= pattern
;
6564 char *backtrack_pos
= 0;
6565 const char *backtrack_error
= 0;
6566 int i
, val
= 0, backtrack_index
= 0;
6567 enum arm_reg_type rtype
;
6568 parse_operand_result result
;
6569 unsigned int op_parse_code
;
6571 #define po_char_or_fail(chr) \
6574 if (skip_past_char (&str, chr) == FAIL) \
6579 #define po_reg_or_fail(regtype) \
6582 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6583 & inst.operands[i].vectype); \
6586 first_error (_(reg_expected_msgs[regtype])); \
6589 inst.operands[i].reg = val; \
6590 inst.operands[i].isreg = 1; \
6591 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6592 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6593 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6594 || rtype == REG_TYPE_VFD \
6595 || rtype == REG_TYPE_NQ); \
6599 #define po_reg_or_goto(regtype, label) \
6602 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6603 & inst.operands[i].vectype); \
6607 inst.operands[i].reg = val; \
6608 inst.operands[i].isreg = 1; \
6609 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6610 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6611 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6612 || rtype == REG_TYPE_VFD \
6613 || rtype == REG_TYPE_NQ); \
6617 #define po_imm_or_fail(min, max, popt) \
6620 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6622 inst.operands[i].imm = val; \
6626 #define po_scalar_or_goto(elsz, label) \
6629 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6632 inst.operands[i].reg = val; \
6633 inst.operands[i].isscalar = 1; \
6637 #define po_misc_or_fail(expr) \
6645 #define po_misc_or_fail_no_backtrack(expr) \
6649 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6650 backtrack_pos = 0; \
6651 if (result != PARSE_OPERAND_SUCCESS) \
6656 #define po_barrier_or_imm(str) \
6659 val = parse_barrier (&str); \
6660 if (val == FAIL && ! ISALPHA (*str)) \
6663 /* ISB can only take SY as an option. */ \
6664 || ((inst.instruction & 0xf0) == 0x60 \
6667 inst.error = _("invalid barrier type"); \
6668 backtrack_pos = 0; \
6674 skip_whitespace (str
);
6676 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6678 op_parse_code
= upat
[i
];
6679 if (op_parse_code
>= 1<<16)
6680 op_parse_code
= thumb
? (op_parse_code
>> 16)
6681 : (op_parse_code
& ((1<<16)-1));
6683 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6685 /* Remember where we are in case we need to backtrack. */
6686 gas_assert (!backtrack_pos
);
6687 backtrack_pos
= str
;
6688 backtrack_error
= inst
.error
;
6689 backtrack_index
= i
;
6692 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6693 po_char_or_fail (',');
6695 switch (op_parse_code
)
6703 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6704 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6705 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6706 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6707 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6708 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6710 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6712 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6714 /* Also accept generic coprocessor regs for unknown registers. */
6716 po_reg_or_fail (REG_TYPE_CN
);
6718 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6719 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6720 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6721 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6722 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6723 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6724 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6725 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6726 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6727 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6729 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6731 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6732 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6734 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6736 /* Neon scalar. Using an element size of 8 means that some invalid
6737 scalars are accepted here, so deal with those in later code. */
6738 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6742 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6745 po_imm_or_fail (0, 0, TRUE
);
6750 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6755 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6758 if (parse_ifimm_zero (&str
))
6759 inst
.operands
[i
].imm
= 0;
6763 = _("only floating point zero is allowed as immediate value");
6771 po_scalar_or_goto (8, try_rr
);
6774 po_reg_or_fail (REG_TYPE_RN
);
6780 po_scalar_or_goto (8, try_nsdq
);
6783 po_reg_or_fail (REG_TYPE_NSDQ
);
6789 po_scalar_or_goto (8, try_ndq
);
6792 po_reg_or_fail (REG_TYPE_NDQ
);
6798 po_scalar_or_goto (8, try_vfd
);
6801 po_reg_or_fail (REG_TYPE_VFD
);
6806 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6807 not careful then bad things might happen. */
6808 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6813 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6816 /* There's a possibility of getting a 64-bit immediate here, so
6817 we need special handling. */
6818 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6821 inst
.error
= _("immediate value is out of range");
6829 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6832 po_imm_or_fail (0, 63, TRUE
);
6837 po_char_or_fail ('[');
6838 po_reg_or_fail (REG_TYPE_RN
);
6839 po_char_or_fail (']');
6845 po_reg_or_fail (REG_TYPE_RN
);
6846 if (skip_past_char (&str
, '!') == SUCCESS
)
6847 inst
.operands
[i
].writeback
= 1;
6851 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6852 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6853 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6854 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6855 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6856 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6857 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6858 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6859 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6860 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6861 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6862 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6864 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6866 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6867 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6869 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6870 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6871 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6872 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6874 /* Immediate variants */
6876 po_char_or_fail ('{');
6877 po_imm_or_fail (0, 255, TRUE
);
6878 po_char_or_fail ('}');
6882 /* The expression parser chokes on a trailing !, so we have
6883 to find it first and zap it. */
6886 while (*s
&& *s
!= ',')
6891 inst
.operands
[i
].writeback
= 1;
6893 po_imm_or_fail (0, 31, TRUE
);
6901 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6906 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6911 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6913 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6915 val
= parse_reloc (&str
);
6918 inst
.error
= _("unrecognized relocation suffix");
6921 else if (val
!= BFD_RELOC_UNUSED
)
6923 inst
.operands
[i
].imm
= val
;
6924 inst
.operands
[i
].hasreloc
= 1;
6929 /* Operand for MOVW or MOVT. */
6931 po_misc_or_fail (parse_half (&str
));
6934 /* Register or expression. */
6935 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6936 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6938 /* Register or immediate. */
6939 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6940 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6942 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6944 if (!is_immediate_prefix (*str
))
6947 val
= parse_fpa_immediate (&str
);
6950 /* FPA immediates are encoded as registers 8-15.
6951 parse_fpa_immediate has already applied the offset. */
6952 inst
.operands
[i
].reg
= val
;
6953 inst
.operands
[i
].isreg
= 1;
6956 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6957 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6959 /* Two kinds of register. */
6962 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6964 || (rege
->type
!= REG_TYPE_MMXWR
6965 && rege
->type
!= REG_TYPE_MMXWC
6966 && rege
->type
!= REG_TYPE_MMXWCG
))
6968 inst
.error
= _("iWMMXt data or control register expected");
6971 inst
.operands
[i
].reg
= rege
->number
;
6972 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6978 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6980 || (rege
->type
!= REG_TYPE_MMXWC
6981 && rege
->type
!= REG_TYPE_MMXWCG
))
6983 inst
.error
= _("iWMMXt control register expected");
6986 inst
.operands
[i
].reg
= rege
->number
;
6987 inst
.operands
[i
].isreg
= 1;
6992 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6993 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6994 case OP_oROR
: val
= parse_ror (&str
); break;
6995 case OP_COND
: val
= parse_cond (&str
); break;
6996 case OP_oBARRIER_I15
:
6997 po_barrier_or_imm (str
); break;
6999 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7005 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7006 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7008 inst
.error
= _("Banked registers are not available with this "
7014 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7018 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7021 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7023 if (strncasecmp (str
, "APSR_", 5) == 0)
7030 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7031 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7032 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7033 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7034 default: found
= 16;
7038 inst
.operands
[i
].isvec
= 1;
7039 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7040 inst
.operands
[i
].reg
= REG_PC
;
7047 po_misc_or_fail (parse_tb (&str
));
7050 /* Register lists. */
7052 val
= parse_reg_list (&str
);
7055 inst
.operands
[i
].writeback
= 1;
7061 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7065 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7069 /* Allow Q registers too. */
7070 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7075 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7077 inst
.operands
[i
].issingle
= 1;
7082 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7087 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7088 &inst
.operands
[i
].vectype
);
7091 /* Addressing modes */
7093 po_misc_or_fail (parse_address (&str
, i
));
7097 po_misc_or_fail_no_backtrack (
7098 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7102 po_misc_or_fail_no_backtrack (
7103 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7107 po_misc_or_fail_no_backtrack (
7108 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7112 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7116 po_misc_or_fail_no_backtrack (
7117 parse_shifter_operand_group_reloc (&str
, i
));
7121 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7125 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7129 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7133 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7136 /* Various value-based sanity checks and shared operations. We
7137 do not signal immediate failures for the register constraints;
7138 this allows a syntax error to take precedence. */
7139 switch (op_parse_code
)
7147 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7148 inst
.error
= BAD_PC
;
7153 if (inst
.operands
[i
].isreg
)
7155 if (inst
.operands
[i
].reg
== REG_PC
)
7156 inst
.error
= BAD_PC
;
7157 else if (inst
.operands
[i
].reg
== REG_SP
)
7158 inst
.error
= BAD_SP
;
7163 if (inst
.operands
[i
].isreg
7164 && inst
.operands
[i
].reg
== REG_PC
7165 && (inst
.operands
[i
].writeback
|| thumb
))
7166 inst
.error
= BAD_PC
;
7175 case OP_oBARRIER_I15
:
7184 inst
.operands
[i
].imm
= val
;
7191 /* If we get here, this operand was successfully parsed. */
7192 inst
.operands
[i
].present
= 1;
7196 inst
.error
= BAD_ARGS
;
7201 /* The parse routine should already have set inst.error, but set a
7202 default here just in case. */
7204 inst
.error
= _("syntax error");
7208 /* Do not backtrack over a trailing optional argument that
7209 absorbed some text. We will only fail again, with the
7210 'garbage following instruction' error message, which is
7211 probably less helpful than the current one. */
7212 if (backtrack_index
== i
&& backtrack_pos
!= str
7213 && upat
[i
+1] == OP_stop
)
7216 inst
.error
= _("syntax error");
7220 /* Try again, skipping the optional argument at backtrack_pos. */
7221 str
= backtrack_pos
;
7222 inst
.error
= backtrack_error
;
7223 inst
.operands
[backtrack_index
].present
= 0;
7224 i
= backtrack_index
;
7228 /* Check that we have parsed all the arguments. */
7229 if (*str
!= '\0' && !inst
.error
)
7230 inst
.error
= _("garbage following instruction");
7232 return inst
.error
? FAIL
: SUCCESS
;
7235 #undef po_char_or_fail
7236 #undef po_reg_or_fail
7237 #undef po_reg_or_goto
7238 #undef po_imm_or_fail
7239 #undef po_scalar_or_fail
7240 #undef po_barrier_or_imm
7242 /* Shorthand macro for instruction encoding functions issuing errors. */
7243 #define constraint(expr, err) \
7254 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7255 instructions are unpredictable if these registers are used. This
7256 is the BadReg predicate in ARM's Thumb-2 documentation. */
7257 #define reject_bad_reg(reg) \
7259 if (reg == REG_SP || reg == REG_PC) \
7261 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7266 /* If REG is R13 (the stack pointer), warn that its use is
7268 #define warn_deprecated_sp(reg) \
7270 if (warn_on_deprecated && reg == REG_SP) \
7271 as_tsktsk (_("use of r13 is deprecated")); \
7274 /* Functions for operand encoding. ARM, then Thumb. */
7276 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7278 /* If VAL can be encoded in the immediate field of an ARM instruction,
7279 return the encoded form. Otherwise, return FAIL. */
7282 encode_arm_immediate (unsigned int val
)
7286 for (i
= 0; i
< 32; i
+= 2)
7287 if ((a
= rotate_left (val
, i
)) <= 0xff)
7288 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7293 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7294 return the encoded form. Otherwise, return FAIL. */
7296 encode_thumb32_immediate (unsigned int val
)
7303 for (i
= 1; i
<= 24; i
++)
7306 if ((val
& ~(0xff << i
)) == 0)
7307 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7311 if (val
== ((a
<< 16) | a
))
7313 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7317 if (val
== ((a
<< 16) | a
))
7318 return 0x200 | (a
>> 8);
7322 /* Encode a VFP SP or DP register number into inst.instruction. */
7325 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7327 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7330 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7333 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7336 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7341 first_error (_("D register out of range for selected VFP version"));
7349 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7353 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7357 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7361 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7365 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7369 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7377 /* Encode a <shift> in an ARM-format instruction. The immediate,
7378 if any, is handled by md_apply_fix. */
7380 encode_arm_shift (int i
)
7382 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7383 inst
.instruction
|= SHIFT_ROR
<< 5;
7386 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7387 if (inst
.operands
[i
].immisreg
)
7389 inst
.instruction
|= SHIFT_BY_REG
;
7390 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7393 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7398 encode_arm_shifter_operand (int i
)
7400 if (inst
.operands
[i
].isreg
)
7402 inst
.instruction
|= inst
.operands
[i
].reg
;
7403 encode_arm_shift (i
);
7407 inst
.instruction
|= INST_IMMEDIATE
;
7408 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7409 inst
.instruction
|= inst
.operands
[i
].imm
;
7413 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7415 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7418 Generate an error if the operand is not a register. */
7419 constraint (!inst
.operands
[i
].isreg
,
7420 _("Instruction does not support =N addresses"));
7422 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7424 if (inst
.operands
[i
].preind
)
7428 inst
.error
= _("instruction does not accept preindexed addressing");
7431 inst
.instruction
|= PRE_INDEX
;
7432 if (inst
.operands
[i
].writeback
)
7433 inst
.instruction
|= WRITE_BACK
;
7436 else if (inst
.operands
[i
].postind
)
7438 gas_assert (inst
.operands
[i
].writeback
);
7440 inst
.instruction
|= WRITE_BACK
;
7442 else /* unindexed - only for coprocessor */
7444 inst
.error
= _("instruction does not accept unindexed addressing");
7448 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7449 && (((inst
.instruction
& 0x000f0000) >> 16)
7450 == ((inst
.instruction
& 0x0000f000) >> 12)))
7451 as_warn ((inst
.instruction
& LOAD_BIT
)
7452 ? _("destination register same as write-back base")
7453 : _("source register same as write-back base"));
7456 /* inst.operands[i] was set up by parse_address. Encode it into an
7457 ARM-format mode 2 load or store instruction. If is_t is true,
7458 reject forms that cannot be used with a T instruction (i.e. not
7461 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7463 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7465 encode_arm_addr_mode_common (i
, is_t
);
7467 if (inst
.operands
[i
].immisreg
)
7469 constraint ((inst
.operands
[i
].imm
== REG_PC
7470 || (is_pc
&& inst
.operands
[i
].writeback
)),
7472 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7473 inst
.instruction
|= inst
.operands
[i
].imm
;
7474 if (!inst
.operands
[i
].negative
)
7475 inst
.instruction
|= INDEX_UP
;
7476 if (inst
.operands
[i
].shifted
)
7478 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7479 inst
.instruction
|= SHIFT_ROR
<< 5;
7482 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7483 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7487 else /* immediate offset in inst.reloc */
7489 if (is_pc
&& !inst
.reloc
.pc_rel
)
7491 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7493 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7494 cannot use PC in addressing.
7495 PC cannot be used in writeback addressing, either. */
7496 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7499 /* Use of PC in str is deprecated for ARMv7. */
7500 if (warn_on_deprecated
7502 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7503 as_tsktsk (_("use of PC in this instruction is deprecated"));
7506 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7508 /* Prefer + for zero encoded value. */
7509 if (!inst
.operands
[i
].negative
)
7510 inst
.instruction
|= INDEX_UP
;
7511 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7516 /* inst.operands[i] was set up by parse_address. Encode it into an
7517 ARM-format mode 3 load or store instruction. Reject forms that
7518 cannot be used with such instructions. If is_t is true, reject
7519 forms that cannot be used with a T instruction (i.e. not
7522 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7524 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7526 inst
.error
= _("instruction does not accept scaled register index");
7530 encode_arm_addr_mode_common (i
, is_t
);
7532 if (inst
.operands
[i
].immisreg
)
7534 constraint ((inst
.operands
[i
].imm
== REG_PC
7535 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7537 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7539 inst
.instruction
|= inst
.operands
[i
].imm
;
7540 if (!inst
.operands
[i
].negative
)
7541 inst
.instruction
|= INDEX_UP
;
7543 else /* immediate offset in inst.reloc */
7545 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7546 && inst
.operands
[i
].writeback
),
7548 inst
.instruction
|= HWOFFSET_IMM
;
7549 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7551 /* Prefer + for zero encoded value. */
7552 if (!inst
.operands
[i
].negative
)
7553 inst
.instruction
|= INDEX_UP
;
7555 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7560 /* Write immediate bits [7:0] to the following locations:
7562 |28/24|23 19|18 16|15 4|3 0|
7563 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7565 This function is used by VMOV/VMVN/VORR/VBIC. */
7568 neon_write_immbits (unsigned immbits
)
7570 inst
.instruction
|= immbits
& 0xf;
7571 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7572 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7575 /* Invert low-order SIZE bits of XHI:XLO. */
7578 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7580 unsigned immlo
= xlo
? *xlo
: 0;
7581 unsigned immhi
= xhi
? *xhi
: 0;
7586 immlo
= (~immlo
) & 0xff;
7590 immlo
= (~immlo
) & 0xffff;
7594 immhi
= (~immhi
) & 0xffffffff;
7598 immlo
= (~immlo
) & 0xffffffff;
7612 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7616 neon_bits_same_in_bytes (unsigned imm
)
7618 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7619 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7620 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7621 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7624 /* For immediate of above form, return 0bABCD. */
7627 neon_squash_bits (unsigned imm
)
7629 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7630 | ((imm
& 0x01000000) >> 21);
7633 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7636 neon_qfloat_bits (unsigned imm
)
7638 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7641 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7642 the instruction. *OP is passed as the initial value of the op field, and
7643 may be set to a different value depending on the constant (i.e.
7644 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7645 MVN). If the immediate looks like a repeated pattern then also
7646 try smaller element sizes. */
7649 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7650 unsigned *immbits
, int *op
, int size
,
7651 enum neon_el_type type
)
7653 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7655 if (type
== NT_float
&& !float_p
)
7658 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7660 if (size
!= 32 || *op
== 1)
7662 *immbits
= neon_qfloat_bits (immlo
);
7668 if (neon_bits_same_in_bytes (immhi
)
7669 && neon_bits_same_in_bytes (immlo
))
7673 *immbits
= (neon_squash_bits (immhi
) << 4)
7674 | neon_squash_bits (immlo
);
7685 if (immlo
== (immlo
& 0x000000ff))
7690 else if (immlo
== (immlo
& 0x0000ff00))
7692 *immbits
= immlo
>> 8;
7695 else if (immlo
== (immlo
& 0x00ff0000))
7697 *immbits
= immlo
>> 16;
7700 else if (immlo
== (immlo
& 0xff000000))
7702 *immbits
= immlo
>> 24;
7705 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7707 *immbits
= (immlo
>> 8) & 0xff;
7710 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7712 *immbits
= (immlo
>> 16) & 0xff;
7716 if ((immlo
& 0xffff) != (immlo
>> 16))
7723 if (immlo
== (immlo
& 0x000000ff))
7728 else if (immlo
== (immlo
& 0x0000ff00))
7730 *immbits
= immlo
>> 8;
7734 if ((immlo
& 0xff) != (immlo
>> 8))
7739 if (immlo
== (immlo
& 0x000000ff))
7741 /* Don't allow MVN with 8-bit immediate. */
7758 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7759 Determine whether it can be performed with a move instruction; if
7760 it can, convert inst.instruction to that move instruction and
7761 return TRUE; if it can't, convert inst.instruction to a literal-pool
7762 load and return FALSE. If this is not a valid thing to do in the
7763 current context, set inst.error and return TRUE.
7765 inst.operands[i] describes the destination register. */
7768 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7771 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7772 bfd_boolean arm_p
= (t
== CONST_ARM
);
7773 bfd_boolean vec64_p
= (t
== CONST_VEC
) && !inst
.operands
[i
].issingle
;
7776 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7780 if ((inst
.instruction
& tbit
) == 0)
7782 inst
.error
= _("invalid pseudo operation");
7785 if (inst
.reloc
.exp
.X_op
!= O_constant
7786 && inst
.reloc
.exp
.X_op
!= O_symbol
7787 && inst
.reloc
.exp
.X_op
!= O_big
)
7789 inst
.error
= _("constant expression expected");
7792 if ((inst
.reloc
.exp
.X_op
== O_constant
7793 || inst
.reloc
.exp
.X_op
== O_big
)
7794 && !inst
.operands
[i
].issingle
)
7796 if (thumb_p
&& inst
.reloc
.exp
.X_op
== O_constant
)
7798 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7800 /* This can be done with a mov(1) instruction. */
7801 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7802 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7806 else if (arm_p
&& inst
.reloc
.exp
.X_op
== O_constant
)
7808 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7811 /* This can be done with a mov instruction. */
7812 inst
.instruction
&= LITERAL_MASK
;
7813 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7814 inst
.instruction
|= value
& 0xfff;
7818 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7821 /* This can be done with a mvn instruction. */
7822 inst
.instruction
&= LITERAL_MASK
;
7823 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7824 inst
.instruction
|= value
& 0xfff;
7831 unsigned immbits
= 0;
7832 unsigned immlo
= inst
.operands
[1].imm
;
7833 unsigned immhi
= inst
.operands
[1].regisimm
7834 ? inst
.operands
[1].reg
7835 : inst
.reloc
.exp
.X_unsigned
7837 : ((bfd_int64_t
)((int) immlo
)) >> 32;
7838 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7839 &op
, 64, NT_invtype
);
7843 neon_invert_size (&immlo
, &immhi
, 64);
7845 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7846 &op
, 64, NT_invtype
);
7850 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
7855 /* Fill other bits in vmov encoding for both thumb and arm. */
7857 inst
.instruction
|= (0x7 << 29) | (0xF << 24);
7859 inst
.instruction
|= (0xF << 28) | (0x1 << 25);
7860 neon_write_immbits (immbits
);
7866 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
7867 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
7870 inst
.operands
[1].reg
= REG_PC
;
7871 inst
.operands
[1].isreg
= 1;
7872 inst
.operands
[1].preind
= 1;
7873 inst
.reloc
.pc_rel
= 1;
7874 inst
.reloc
.type
= (thumb_p
7875 ? BFD_RELOC_ARM_THUMB_OFFSET
7877 ? BFD_RELOC_ARM_HWLITERAL
7878 : BFD_RELOC_ARM_LITERAL
));
7882 /* inst.operands[i] was set up by parse_address. Encode it into an
7883 ARM-format instruction. Reject all forms which cannot be encoded
7884 into a coprocessor load/store instruction. If wb_ok is false,
7885 reject use of writeback; if unind_ok is false, reject use of
7886 unindexed addressing. If reloc_override is not 0, use it instead
7887 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7888 (in which case it is preserved). */
7891 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
7893 if (!inst
.operands
[i
].isreg
)
7896 if (! inst
.operands
[0].isvec
)
7898 inst
.error
= _("invalid co-processor operand");
7901 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
7905 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7907 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
7909 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
7911 gas_assert (!inst
.operands
[i
].writeback
);
7914 inst
.error
= _("instruction does not support unindexed addressing");
7917 inst
.instruction
|= inst
.operands
[i
].imm
;
7918 inst
.instruction
|= INDEX_UP
;
7922 if (inst
.operands
[i
].preind
)
7923 inst
.instruction
|= PRE_INDEX
;
7925 if (inst
.operands
[i
].writeback
)
7927 if (inst
.operands
[i
].reg
== REG_PC
)
7929 inst
.error
= _("pc may not be used with write-back");
7934 inst
.error
= _("instruction does not support writeback");
7937 inst
.instruction
|= WRITE_BACK
;
7941 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
7942 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
7943 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
7944 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
7947 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
7949 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
7952 /* Prefer + for zero encoded value. */
7953 if (!inst
.operands
[i
].negative
)
7954 inst
.instruction
|= INDEX_UP
;
7959 /* Functions for instruction encoding, sorted by sub-architecture.
7960 First some generics; their names are taken from the conventional
7961 bit positions for register arguments in ARM format instructions. */
7971 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7977 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7978 inst
.instruction
|= inst
.operands
[1].reg
;
7984 inst
.instruction
|= inst
.operands
[0].reg
;
7985 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7991 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7992 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7998 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7999 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8003 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8005 if (ARM_CPU_IS_ANY (cpu_variant
))
8007 as_tsktsk ("%s", msg
);
8010 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8022 unsigned Rn
= inst
.operands
[2].reg
;
8023 /* Enforce restrictions on SWP instruction. */
8024 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8026 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8027 _("Rn must not overlap other operands"));
8029 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8031 if (!check_obsolete (&arm_ext_v8
,
8032 _("swp{b} use is obsoleted for ARMv8 and later"))
8033 && warn_on_deprecated
8034 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8035 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8038 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8039 inst
.instruction
|= inst
.operands
[1].reg
;
8040 inst
.instruction
|= Rn
<< 16;
8046 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8047 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8048 inst
.instruction
|= inst
.operands
[2].reg
;
8054 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8055 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8056 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8057 || inst
.reloc
.exp
.X_add_number
!= 0),
8059 inst
.instruction
|= inst
.operands
[0].reg
;
8060 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8061 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8067 inst
.instruction
|= inst
.operands
[0].imm
;
8073 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8074 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8077 /* ARM instructions, in alphabetical order by function name (except
8078 that wrapper functions appear immediately after the function they
8081 /* This is a pseudo-op of the form "adr rd, label" to be converted
8082 into a relative address of the form "add rd, pc, #label-.-8". */
8087 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8089 /* Frag hacking will turn this into a sub instruction if the offset turns
8090 out to be negative. */
8091 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8092 inst
.reloc
.pc_rel
= 1;
8093 inst
.reloc
.exp
.X_add_number
-= 8;
8096 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8097 into a relative address of the form:
8098 add rd, pc, #low(label-.-8)"
8099 add rd, rd, #high(label-.-8)" */
8104 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8106 /* Frag hacking will turn this into a sub instruction if the offset turns
8107 out to be negative. */
8108 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8109 inst
.reloc
.pc_rel
= 1;
8110 inst
.size
= INSN_SIZE
* 2;
8111 inst
.reloc
.exp
.X_add_number
-= 8;
8117 if (!inst
.operands
[1].present
)
8118 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8119 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8120 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8121 encode_arm_shifter_operand (2);
8127 if (inst
.operands
[0].present
)
8128 inst
.instruction
|= inst
.operands
[0].imm
;
8130 inst
.instruction
|= 0xf;
8136 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8137 constraint (msb
> 32, _("bit-field extends past end of register"));
8138 /* The instruction encoding stores the LSB and MSB,
8139 not the LSB and width. */
8140 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8141 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8142 inst
.instruction
|= (msb
- 1) << 16;
8150 /* #0 in second position is alternative syntax for bfc, which is
8151 the same instruction but with REG_PC in the Rm field. */
8152 if (!inst
.operands
[1].isreg
)
8153 inst
.operands
[1].reg
= REG_PC
;
8155 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8156 constraint (msb
> 32, _("bit-field extends past end of register"));
8157 /* The instruction encoding stores the LSB and MSB,
8158 not the LSB and width. */
8159 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8160 inst
.instruction
|= inst
.operands
[1].reg
;
8161 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8162 inst
.instruction
|= (msb
- 1) << 16;
8168 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8169 _("bit-field extends past end of register"));
8170 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8171 inst
.instruction
|= inst
.operands
[1].reg
;
8172 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8173 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8176 /* ARM V5 breakpoint instruction (argument parse)
8177 BKPT <16 bit unsigned immediate>
8178 Instruction is not conditional.
8179 The bit pattern given in insns[] has the COND_ALWAYS condition,
8180 and it is an error if the caller tried to override that. */
8185 /* Top 12 of 16 bits to bits 19:8. */
8186 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8188 /* Bottom 4 of 16 bits to bits 3:0. */
8189 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8193 encode_branch (int default_reloc
)
8195 if (inst
.operands
[0].hasreloc
)
8197 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8198 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8199 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8200 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8201 ? BFD_RELOC_ARM_PLT32
8202 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8205 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8206 inst
.reloc
.pc_rel
= 1;
8213 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8214 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8217 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8224 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8226 if (inst
.cond
== COND_ALWAYS
)
8227 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8229 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8233 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8236 /* ARM V5 branch-link-exchange instruction (argument parse)
8237 BLX <target_addr> ie BLX(1)
8238 BLX{<condition>} <Rm> ie BLX(2)
8239 Unfortunately, there are two different opcodes for this mnemonic.
8240 So, the insns[].value is not used, and the code here zaps values
8241 into inst.instruction.
8242 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8247 if (inst
.operands
[0].isreg
)
8249 /* Arg is a register; the opcode provided by insns[] is correct.
8250 It is not illegal to do "blx pc", just useless. */
8251 if (inst
.operands
[0].reg
== REG_PC
)
8252 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8254 inst
.instruction
|= inst
.operands
[0].reg
;
8258 /* Arg is an address; this instruction cannot be executed
8259 conditionally, and the opcode must be adjusted.
8260 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8261 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8262 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8263 inst
.instruction
= 0xfa000000;
8264 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8271 bfd_boolean want_reloc
;
8273 if (inst
.operands
[0].reg
== REG_PC
)
8274 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8276 inst
.instruction
|= inst
.operands
[0].reg
;
8277 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8278 it is for ARMv4t or earlier. */
8279 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8280 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8284 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8289 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8293 /* ARM v5TEJ. Jump to Jazelle code. */
8298 if (inst
.operands
[0].reg
== REG_PC
)
8299 as_tsktsk (_("use of r15 in bxj is not really useful"));
8301 inst
.instruction
|= inst
.operands
[0].reg
;
8304 /* Co-processor data operation:
8305 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8306 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8310 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8311 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8312 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8313 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8314 inst
.instruction
|= inst
.operands
[4].reg
;
8315 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8321 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8322 encode_arm_shifter_operand (1);
8325 /* Transfer between coprocessor and ARM registers.
8326 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8331 No special properties. */
8333 struct deprecated_coproc_regs_s
8340 arm_feature_set deprecated
;
8341 arm_feature_set obsoleted
;
8342 const char *dep_msg
;
8343 const char *obs_msg
;
8346 #define DEPR_ACCESS_V8 \
8347 N_("This coprocessor register access is deprecated in ARMv8")
8349 /* Table of all deprecated coprocessor registers. */
8350 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8352 {15, 0, 7, 10, 5, /* CP15DMB. */
8353 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8354 DEPR_ACCESS_V8
, NULL
},
8355 {15, 0, 7, 10, 4, /* CP15DSB. */
8356 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8357 DEPR_ACCESS_V8
, NULL
},
8358 {15, 0, 7, 5, 4, /* CP15ISB. */
8359 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8360 DEPR_ACCESS_V8
, NULL
},
8361 {14, 6, 1, 0, 0, /* TEEHBR. */
8362 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8363 DEPR_ACCESS_V8
, NULL
},
8364 {14, 6, 0, 0, 0, /* TEECR. */
8365 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8366 DEPR_ACCESS_V8
, NULL
},
8369 #undef DEPR_ACCESS_V8
8371 static const size_t deprecated_coproc_reg_count
=
8372 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8380 Rd
= inst
.operands
[2].reg
;
8383 if (inst
.instruction
== 0xee000010
8384 || inst
.instruction
== 0xfe000010)
8386 reject_bad_reg (Rd
);
8389 constraint (Rd
== REG_SP
, BAD_SP
);
8394 if (inst
.instruction
== 0xe000010)
8395 constraint (Rd
== REG_PC
, BAD_PC
);
8398 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8400 const struct deprecated_coproc_regs_s
*r
=
8401 deprecated_coproc_regs
+ i
;
8403 if (inst
.operands
[0].reg
== r
->cp
8404 && inst
.operands
[1].imm
== r
->opc1
8405 && inst
.operands
[3].reg
== r
->crn
8406 && inst
.operands
[4].reg
== r
->crm
8407 && inst
.operands
[5].imm
== r
->opc2
)
8409 if (! ARM_CPU_IS_ANY (cpu_variant
)
8410 && warn_on_deprecated
8411 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8412 as_tsktsk ("%s", r
->dep_msg
);
8416 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8417 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8418 inst
.instruction
|= Rd
<< 12;
8419 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8420 inst
.instruction
|= inst
.operands
[4].reg
;
8421 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8424 /* Transfer between coprocessor register and pair of ARM registers.
8425 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8430 Two XScale instructions are special cases of these:
8432 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8433 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8435 Result unpredictable if Rd or Rn is R15. */
8442 Rd
= inst
.operands
[2].reg
;
8443 Rn
= inst
.operands
[3].reg
;
8447 reject_bad_reg (Rd
);
8448 reject_bad_reg (Rn
);
8452 constraint (Rd
== REG_PC
, BAD_PC
);
8453 constraint (Rn
== REG_PC
, BAD_PC
);
8456 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8457 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8458 inst
.instruction
|= Rd
<< 12;
8459 inst
.instruction
|= Rn
<< 16;
8460 inst
.instruction
|= inst
.operands
[4].reg
;
8466 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8467 if (inst
.operands
[1].present
)
8469 inst
.instruction
|= CPSI_MMOD
;
8470 inst
.instruction
|= inst
.operands
[1].imm
;
8477 inst
.instruction
|= inst
.operands
[0].imm
;
8483 unsigned Rd
, Rn
, Rm
;
8485 Rd
= inst
.operands
[0].reg
;
8486 Rn
= (inst
.operands
[1].present
8487 ? inst
.operands
[1].reg
: Rd
);
8488 Rm
= inst
.operands
[2].reg
;
8490 constraint ((Rd
== REG_PC
), BAD_PC
);
8491 constraint ((Rn
== REG_PC
), BAD_PC
);
8492 constraint ((Rm
== REG_PC
), BAD_PC
);
8494 inst
.instruction
|= Rd
<< 16;
8495 inst
.instruction
|= Rn
<< 0;
8496 inst
.instruction
|= Rm
<< 8;
8502 /* There is no IT instruction in ARM mode. We
8503 process it to do the validation as if in
8504 thumb mode, just in case the code gets
8505 assembled for thumb using the unified syntax. */
8510 set_it_insn_type (IT_INSN
);
8511 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8512 now_it
.cc
= inst
.operands
[0].imm
;
8516 /* If there is only one register in the register list,
8517 then return its register number. Otherwise return -1. */
8519 only_one_reg_in_list (int range
)
8521 int i
= ffs (range
) - 1;
8522 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8526 encode_ldmstm(int from_push_pop_mnem
)
8528 int base_reg
= inst
.operands
[0].reg
;
8529 int range
= inst
.operands
[1].imm
;
8532 inst
.instruction
|= base_reg
<< 16;
8533 inst
.instruction
|= range
;
8535 if (inst
.operands
[1].writeback
)
8536 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8538 if (inst
.operands
[0].writeback
)
8540 inst
.instruction
|= WRITE_BACK
;
8541 /* Check for unpredictable uses of writeback. */
8542 if (inst
.instruction
& LOAD_BIT
)
8544 /* Not allowed in LDM type 2. */
8545 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8546 && ((range
& (1 << REG_PC
)) == 0))
8547 as_warn (_("writeback of base register is UNPREDICTABLE"));
8548 /* Only allowed if base reg not in list for other types. */
8549 else if (range
& (1 << base_reg
))
8550 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8554 /* Not allowed for type 2. */
8555 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8556 as_warn (_("writeback of base register is UNPREDICTABLE"));
8557 /* Only allowed if base reg not in list, or first in list. */
8558 else if ((range
& (1 << base_reg
))
8559 && (range
& ((1 << base_reg
) - 1)))
8560 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8564 /* If PUSH/POP has only one register, then use the A2 encoding. */
8565 one_reg
= only_one_reg_in_list (range
);
8566 if (from_push_pop_mnem
&& one_reg
>= 0)
8568 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8570 inst
.instruction
&= A_COND_MASK
;
8571 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8572 inst
.instruction
|= one_reg
<< 12;
8579 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8582 /* ARMv5TE load-consecutive (argument parse)
8591 constraint (inst
.operands
[0].reg
% 2 != 0,
8592 _("first transfer register must be even"));
8593 constraint (inst
.operands
[1].present
8594 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8595 _("can only transfer two consecutive registers"));
8596 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8597 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8599 if (!inst
.operands
[1].present
)
8600 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8602 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8603 register and the first register written; we have to diagnose
8604 overlap between the base and the second register written here. */
8606 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8607 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8608 as_warn (_("base register written back, and overlaps "
8609 "second transfer register"));
8611 if (!(inst
.instruction
& V4_STR_BIT
))
8613 /* For an index-register load, the index register must not overlap the
8614 destination (even if not write-back). */
8615 if (inst
.operands
[2].immisreg
8616 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8617 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8618 as_warn (_("index register overlaps transfer register"));
8620 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8621 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8627 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8628 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8629 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8630 || inst
.operands
[1].negative
8631 /* This can arise if the programmer has written
8633 or if they have mistakenly used a register name as the last
8636 It is very difficult to distinguish between these two cases
8637 because "rX" might actually be a label. ie the register
8638 name has been occluded by a symbol of the same name. So we
8639 just generate a general 'bad addressing mode' type error
8640 message and leave it up to the programmer to discover the
8641 true cause and fix their mistake. */
8642 || (inst
.operands
[1].reg
== REG_PC
),
8645 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8646 || inst
.reloc
.exp
.X_add_number
!= 0,
8647 _("offset must be zero in ARM encoding"));
8649 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8651 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8652 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8653 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8659 constraint (inst
.operands
[0].reg
% 2 != 0,
8660 _("even register required"));
8661 constraint (inst
.operands
[1].present
8662 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8663 _("can only load two consecutive registers"));
8664 /* If op 1 were present and equal to PC, this function wouldn't
8665 have been called in the first place. */
8666 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8668 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8669 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8672 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8673 which is not a multiple of four is UNPREDICTABLE. */
8675 check_ldr_r15_aligned (void)
8677 constraint (!(inst
.operands
[1].immisreg
)
8678 && (inst
.operands
[0].reg
== REG_PC
8679 && inst
.operands
[1].reg
== REG_PC
8680 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8681 _("ldr to register 15 must be 4-byte alligned"));
8687 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8688 if (!inst
.operands
[1].isreg
)
8689 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8691 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8692 check_ldr_r15_aligned ();
8698 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8700 if (inst
.operands
[1].preind
)
8702 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8703 || inst
.reloc
.exp
.X_add_number
!= 0,
8704 _("this instruction requires a post-indexed address"));
8706 inst
.operands
[1].preind
= 0;
8707 inst
.operands
[1].postind
= 1;
8708 inst
.operands
[1].writeback
= 1;
8710 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8711 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8714 /* Halfword and signed-byte load/store operations. */
8719 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8720 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8721 if (!inst
.operands
[1].isreg
)
8722 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8724 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8730 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8732 if (inst
.operands
[1].preind
)
8734 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8735 || inst
.reloc
.exp
.X_add_number
!= 0,
8736 _("this instruction requires a post-indexed address"));
8738 inst
.operands
[1].preind
= 0;
8739 inst
.operands
[1].postind
= 1;
8740 inst
.operands
[1].writeback
= 1;
8742 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8743 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8746 /* Co-processor register load/store.
8747 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8751 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8752 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8753 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8759 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8760 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8761 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8762 && !(inst
.instruction
& 0x00400000))
8763 as_tsktsk (_("Rd and Rm should be different in mla"));
8765 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8766 inst
.instruction
|= inst
.operands
[1].reg
;
8767 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8768 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8774 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8775 encode_arm_shifter_operand (1);
8778 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8785 top
= (inst
.instruction
& 0x00400000) != 0;
8786 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
8787 _(":lower16: not allowed this instruction"));
8788 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
8789 _(":upper16: not allowed instruction"));
8790 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8791 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
8793 imm
= inst
.reloc
.exp
.X_add_number
;
8794 /* The value is in two pieces: 0:11, 16:19. */
8795 inst
.instruction
|= (imm
& 0x00000fff);
8796 inst
.instruction
|= (imm
& 0x0000f000) << 4;
8800 static void do_vfp_nsyn_opcode (const char *);
8803 do_vfp_nsyn_mrs (void)
8805 if (inst
.operands
[0].isvec
)
8807 if (inst
.operands
[1].reg
!= 1)
8808 first_error (_("operand 1 must be FPSCR"));
8809 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
8810 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
8811 do_vfp_nsyn_opcode ("fmstat");
8813 else if (inst
.operands
[1].isvec
)
8814 do_vfp_nsyn_opcode ("fmrx");
8822 do_vfp_nsyn_msr (void)
8824 if (inst
.operands
[0].isvec
)
8825 do_vfp_nsyn_opcode ("fmxr");
8835 unsigned Rt
= inst
.operands
[0].reg
;
8837 if (thumb_mode
&& Rt
== REG_SP
)
8839 inst
.error
= BAD_SP
;
8843 /* APSR_ sets isvec. All other refs to PC are illegal. */
8844 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
8846 inst
.error
= BAD_PC
;
8850 /* If we get through parsing the register name, we just insert the number
8851 generated into the instruction without further validation. */
8852 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
8853 inst
.instruction
|= (Rt
<< 12);
8859 unsigned Rt
= inst
.operands
[1].reg
;
8862 reject_bad_reg (Rt
);
8863 else if (Rt
== REG_PC
)
8865 inst
.error
= BAD_PC
;
8869 /* If we get through parsing the register name, we just insert the number
8870 generated into the instruction without further validation. */
8871 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
8872 inst
.instruction
|= (Rt
<< 12);
8880 if (do_vfp_nsyn_mrs () == SUCCESS
)
8883 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8884 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8886 if (inst
.operands
[1].isreg
)
8888 br
= inst
.operands
[1].reg
;
8889 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
8890 as_bad (_("bad register for mrs"));
8894 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8895 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
8897 _("'APSR', 'CPSR' or 'SPSR' expected"));
8898 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
8901 inst
.instruction
|= br
;
8904 /* Two possible forms:
8905 "{C|S}PSR_<field>, Rm",
8906 "{C|S}PSR_f, #expression". */
8911 if (do_vfp_nsyn_msr () == SUCCESS
)
8914 inst
.instruction
|= inst
.operands
[0].imm
;
8915 if (inst
.operands
[1].isreg
)
8916 inst
.instruction
|= inst
.operands
[1].reg
;
8919 inst
.instruction
|= INST_IMMEDIATE
;
8920 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8921 inst
.reloc
.pc_rel
= 0;
8928 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
8930 if (!inst
.operands
[2].present
)
8931 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
8932 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8933 inst
.instruction
|= inst
.operands
[1].reg
;
8934 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8936 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8937 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8938 as_tsktsk (_("Rd and Rm should be different in mul"));
8941 /* Long Multiply Parser
8942 UMULL RdLo, RdHi, Rm, Rs
8943 SMULL RdLo, RdHi, Rm, Rs
8944 UMLAL RdLo, RdHi, Rm, Rs
8945 SMLAL RdLo, RdHi, Rm, Rs. */
8950 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8951 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8952 inst
.instruction
|= inst
.operands
[2].reg
;
8953 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8955 /* rdhi and rdlo must be different. */
8956 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8957 as_tsktsk (_("rdhi and rdlo must be different"));
8959 /* rdhi, rdlo and rm must all be different before armv6. */
8960 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
8961 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
8962 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8963 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8969 if (inst
.operands
[0].present
8970 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
8972 /* Architectural NOP hints are CPSR sets with no bits selected. */
8973 inst
.instruction
&= 0xf0000000;
8974 inst
.instruction
|= 0x0320f000;
8975 if (inst
.operands
[0].present
)
8976 inst
.instruction
|= inst
.operands
[0].imm
;
8980 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8981 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8982 Condition defaults to COND_ALWAYS.
8983 Error if Rd, Rn or Rm are R15. */
8988 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8989 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8990 inst
.instruction
|= inst
.operands
[2].reg
;
8991 if (inst
.operands
[3].present
)
8992 encode_arm_shift (3);
8995 /* ARM V6 PKHTB (Argument Parse). */
9000 if (!inst
.operands
[3].present
)
9002 /* If the shift specifier is omitted, turn the instruction
9003 into pkhbt rd, rm, rn. */
9004 inst
.instruction
&= 0xfff00010;
9005 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9006 inst
.instruction
|= inst
.operands
[1].reg
;
9007 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9011 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9012 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9013 inst
.instruction
|= inst
.operands
[2].reg
;
9014 encode_arm_shift (3);
9018 /* ARMv5TE: Preload-Cache
9019 MP Extensions: Preload for write
9023 Syntactically, like LDR with B=1, W=0, L=1. */
9028 constraint (!inst
.operands
[0].isreg
,
9029 _("'[' expected after PLD mnemonic"));
9030 constraint (inst
.operands
[0].postind
,
9031 _("post-indexed expression used in preload instruction"));
9032 constraint (inst
.operands
[0].writeback
,
9033 _("writeback used in preload instruction"));
9034 constraint (!inst
.operands
[0].preind
,
9035 _("unindexed addressing used in preload instruction"));
9036 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9039 /* ARMv7: PLI <addr_mode> */
9043 constraint (!inst
.operands
[0].isreg
,
9044 _("'[' expected after PLI mnemonic"));
9045 constraint (inst
.operands
[0].postind
,
9046 _("post-indexed expression used in preload instruction"));
9047 constraint (inst
.operands
[0].writeback
,
9048 _("writeback used in preload instruction"));
9049 constraint (!inst
.operands
[0].preind
,
9050 _("unindexed addressing used in preload instruction"));
9051 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9052 inst
.instruction
&= ~PRE_INDEX
;
9058 constraint (inst
.operands
[0].writeback
,
9059 _("push/pop do not support {reglist}^"));
9060 inst
.operands
[1] = inst
.operands
[0];
9061 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9062 inst
.operands
[0].isreg
= 1;
9063 inst
.operands
[0].writeback
= 1;
9064 inst
.operands
[0].reg
= REG_SP
;
9065 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9068 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9069 word at the specified address and the following word
9071 Unconditionally executed.
9072 Error if Rn is R15. */
9077 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9078 if (inst
.operands
[0].writeback
)
9079 inst
.instruction
|= WRITE_BACK
;
9082 /* ARM V6 ssat (argument parse). */
9087 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9088 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9089 inst
.instruction
|= inst
.operands
[2].reg
;
9091 if (inst
.operands
[3].present
)
9092 encode_arm_shift (3);
9095 /* ARM V6 usat (argument parse). */
9100 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9101 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9102 inst
.instruction
|= inst
.operands
[2].reg
;
9104 if (inst
.operands
[3].present
)
9105 encode_arm_shift (3);
9108 /* ARM V6 ssat16 (argument parse). */
9113 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9114 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9115 inst
.instruction
|= inst
.operands
[2].reg
;
9121 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9122 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9123 inst
.instruction
|= inst
.operands
[2].reg
;
9126 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9127 preserving the other bits.
9129 setend <endian_specifier>, where <endian_specifier> is either
9135 if (warn_on_deprecated
9136 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9137 as_tsktsk (_("setend use is deprecated for ARMv8"));
9139 if (inst
.operands
[0].imm
)
9140 inst
.instruction
|= 0x200;
9146 unsigned int Rm
= (inst
.operands
[1].present
9147 ? inst
.operands
[1].reg
9148 : inst
.operands
[0].reg
);
9150 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9151 inst
.instruction
|= Rm
;
9152 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9154 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9155 inst
.instruction
|= SHIFT_BY_REG
;
9156 /* PR 12854: Error on extraneous shifts. */
9157 constraint (inst
.operands
[2].shifted
,
9158 _("extraneous shift as part of operand to shift insn"));
9161 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9167 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9168 inst
.reloc
.pc_rel
= 0;
9174 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9175 inst
.reloc
.pc_rel
= 0;
9181 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9182 inst
.reloc
.pc_rel
= 0;
9188 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9189 _("selected processor does not support SETPAN instruction"));
9191 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9197 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9198 _("selected processor does not support SETPAN instruction"));
9200 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9203 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9204 SMLAxy{cond} Rd,Rm,Rs,Rn
9205 SMLAWy{cond} Rd,Rm,Rs,Rn
9206 Error if any register is R15. */
9211 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9212 inst
.instruction
|= inst
.operands
[1].reg
;
9213 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9214 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9217 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9218 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9219 Error if any register is R15.
9220 Warning if Rdlo == Rdhi. */
9225 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9226 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9227 inst
.instruction
|= inst
.operands
[2].reg
;
9228 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9230 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9231 as_tsktsk (_("rdhi and rdlo must be different"));
9234 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9235 SMULxy{cond} Rd,Rm,Rs
9236 Error if any register is R15. */
9241 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9242 inst
.instruction
|= inst
.operands
[1].reg
;
9243 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9246 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9247 the same for both ARM and Thumb-2. */
9254 if (inst
.operands
[0].present
)
9256 reg
= inst
.operands
[0].reg
;
9257 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9262 inst
.instruction
|= reg
<< 16;
9263 inst
.instruction
|= inst
.operands
[1].imm
;
9264 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9265 inst
.instruction
|= WRITE_BACK
;
9268 /* ARM V6 strex (argument parse). */
9273 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9274 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9275 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9276 || inst
.operands
[2].negative
9277 /* See comment in do_ldrex(). */
9278 || (inst
.operands
[2].reg
== REG_PC
),
9281 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9282 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9284 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9285 || inst
.reloc
.exp
.X_add_number
!= 0,
9286 _("offset must be zero in ARM encoding"));
9288 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9289 inst
.instruction
|= inst
.operands
[1].reg
;
9290 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9291 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9297 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9298 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9299 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9300 || inst
.operands
[2].negative
,
9303 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9304 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9312 constraint (inst
.operands
[1].reg
% 2 != 0,
9313 _("even register required"));
9314 constraint (inst
.operands
[2].present
9315 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9316 _("can only store two consecutive registers"));
9317 /* If op 2 were present and equal to PC, this function wouldn't
9318 have been called in the first place. */
9319 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9321 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9322 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9323 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9326 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9327 inst
.instruction
|= inst
.operands
[1].reg
;
9328 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9335 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9336 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9344 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9345 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9350 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9351 extends it to 32-bits, and adds the result to a value in another
9352 register. You can specify a rotation by 0, 8, 16, or 24 bits
9353 before extracting the 16-bit value.
9354 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9355 Condition defaults to COND_ALWAYS.
9356 Error if any register uses R15. */
9361 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9362 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9363 inst
.instruction
|= inst
.operands
[2].reg
;
9364 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9369 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9370 Condition defaults to COND_ALWAYS.
9371 Error if any register uses R15. */
9376 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9377 inst
.instruction
|= inst
.operands
[1].reg
;
9378 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9381 /* VFP instructions. In a logical order: SP variant first, monad
9382 before dyad, arithmetic then move then load/store. */
9385 do_vfp_sp_monadic (void)
9387 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9388 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9392 do_vfp_sp_dyadic (void)
9394 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9395 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9396 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9400 do_vfp_sp_compare_z (void)
9402 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9406 do_vfp_dp_sp_cvt (void)
9408 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9409 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9413 do_vfp_sp_dp_cvt (void)
9415 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9416 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9420 do_vfp_reg_from_sp (void)
9422 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9423 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9427 do_vfp_reg2_from_sp2 (void)
9429 constraint (inst
.operands
[2].imm
!= 2,
9430 _("only two consecutive VFP SP registers allowed here"));
9431 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9432 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9433 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9437 do_vfp_sp_from_reg (void)
9439 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9440 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9444 do_vfp_sp2_from_reg2 (void)
9446 constraint (inst
.operands
[0].imm
!= 2,
9447 _("only two consecutive VFP SP registers allowed here"));
9448 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9449 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9450 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9454 do_vfp_sp_ldst (void)
9456 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9457 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9461 do_vfp_dp_ldst (void)
9463 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9464 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9469 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9471 if (inst
.operands
[0].writeback
)
9472 inst
.instruction
|= WRITE_BACK
;
9474 constraint (ldstm_type
!= VFP_LDSTMIA
,
9475 _("this addressing mode requires base-register writeback"));
9476 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9477 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9478 inst
.instruction
|= inst
.operands
[1].imm
;
9482 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9486 if (inst
.operands
[0].writeback
)
9487 inst
.instruction
|= WRITE_BACK
;
9489 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9490 _("this addressing mode requires base-register writeback"));
9492 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9493 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9495 count
= inst
.operands
[1].imm
<< 1;
9496 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9499 inst
.instruction
|= count
;
9503 do_vfp_sp_ldstmia (void)
9505 vfp_sp_ldstm (VFP_LDSTMIA
);
9509 do_vfp_sp_ldstmdb (void)
9511 vfp_sp_ldstm (VFP_LDSTMDB
);
9515 do_vfp_dp_ldstmia (void)
9517 vfp_dp_ldstm (VFP_LDSTMIA
);
9521 do_vfp_dp_ldstmdb (void)
9523 vfp_dp_ldstm (VFP_LDSTMDB
);
9527 do_vfp_xp_ldstmia (void)
9529 vfp_dp_ldstm (VFP_LDSTMIAX
);
9533 do_vfp_xp_ldstmdb (void)
9535 vfp_dp_ldstm (VFP_LDSTMDBX
);
9539 do_vfp_dp_rd_rm (void)
9541 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9542 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9546 do_vfp_dp_rn_rd (void)
9548 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9549 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9553 do_vfp_dp_rd_rn (void)
9555 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9556 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9560 do_vfp_dp_rd_rn_rm (void)
9562 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9563 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9564 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9570 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9574 do_vfp_dp_rm_rd_rn (void)
9576 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9577 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9578 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9581 /* VFPv3 instructions. */
9583 do_vfp_sp_const (void)
9585 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9586 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9587 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9591 do_vfp_dp_const (void)
9593 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9594 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9595 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9599 vfp_conv (int srcsize
)
9601 int immbits
= srcsize
- inst
.operands
[1].imm
;
9603 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9605 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9606 i.e. immbits must be in range 0 - 16. */
9607 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9610 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9612 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9613 i.e. immbits must be in range 0 - 31. */
9614 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9618 inst
.instruction
|= (immbits
& 1) << 5;
9619 inst
.instruction
|= (immbits
>> 1);
9623 do_vfp_sp_conv_16 (void)
9625 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9630 do_vfp_dp_conv_16 (void)
9632 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9637 do_vfp_sp_conv_32 (void)
9639 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9644 do_vfp_dp_conv_32 (void)
9646 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9650 /* FPA instructions. Also in a logical order. */
9655 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9656 inst
.instruction
|= inst
.operands
[1].reg
;
9660 do_fpa_ldmstm (void)
9662 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9663 switch (inst
.operands
[1].imm
)
9665 case 1: inst
.instruction
|= CP_T_X
; break;
9666 case 2: inst
.instruction
|= CP_T_Y
; break;
9667 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9672 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9674 /* The instruction specified "ea" or "fd", so we can only accept
9675 [Rn]{!}. The instruction does not really support stacking or
9676 unstacking, so we have to emulate these by setting appropriate
9677 bits and offsets. */
9678 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9679 || inst
.reloc
.exp
.X_add_number
!= 0,
9680 _("this instruction does not support indexing"));
9682 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9683 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9685 if (!(inst
.instruction
& INDEX_UP
))
9686 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9688 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9690 inst
.operands
[2].preind
= 0;
9691 inst
.operands
[2].postind
= 1;
9695 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9698 /* iWMMXt instructions: strictly in alphabetical order. */
9701 do_iwmmxt_tandorc (void)
9703 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9707 do_iwmmxt_textrc (void)
9709 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9710 inst
.instruction
|= inst
.operands
[1].imm
;
9714 do_iwmmxt_textrm (void)
9716 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9717 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9718 inst
.instruction
|= inst
.operands
[2].imm
;
9722 do_iwmmxt_tinsr (void)
9724 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9725 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9726 inst
.instruction
|= inst
.operands
[2].imm
;
9730 do_iwmmxt_tmia (void)
9732 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9733 inst
.instruction
|= inst
.operands
[1].reg
;
9734 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9738 do_iwmmxt_waligni (void)
9740 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9741 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9742 inst
.instruction
|= inst
.operands
[2].reg
;
9743 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9747 do_iwmmxt_wmerge (void)
9749 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9750 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9751 inst
.instruction
|= inst
.operands
[2].reg
;
9752 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9756 do_iwmmxt_wmov (void)
9758 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9759 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9760 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9761 inst
.instruction
|= inst
.operands
[1].reg
;
9765 do_iwmmxt_wldstbh (void)
9768 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9770 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
9772 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
9773 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
9777 do_iwmmxt_wldstw (void)
9779 /* RIWR_RIWC clears .isreg for a control register. */
9780 if (!inst
.operands
[0].isreg
)
9782 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9783 inst
.instruction
|= 0xf0000000;
9786 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9787 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9791 do_iwmmxt_wldstd (void)
9793 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9794 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
9795 && inst
.operands
[1].immisreg
)
9797 inst
.instruction
&= ~0x1a000ff;
9798 inst
.instruction
|= (0xf << 28);
9799 if (inst
.operands
[1].preind
)
9800 inst
.instruction
|= PRE_INDEX
;
9801 if (!inst
.operands
[1].negative
)
9802 inst
.instruction
|= INDEX_UP
;
9803 if (inst
.operands
[1].writeback
)
9804 inst
.instruction
|= WRITE_BACK
;
9805 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9806 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9807 inst
.instruction
|= inst
.operands
[1].imm
;
9810 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
9814 do_iwmmxt_wshufh (void)
9816 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9817 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9818 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
9819 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
9823 do_iwmmxt_wzero (void)
9825 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9826 inst
.instruction
|= inst
.operands
[0].reg
;
9827 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9828 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9832 do_iwmmxt_wrwrwr_or_imm5 (void)
9834 if (inst
.operands
[2].isreg
)
9837 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
9838 _("immediate operand requires iWMMXt2"));
9840 if (inst
.operands
[2].imm
== 0)
9842 switch ((inst
.instruction
>> 20) & 0xf)
9848 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9849 inst
.operands
[2].imm
= 16;
9850 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
9856 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9857 inst
.operands
[2].imm
= 32;
9858 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
9865 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9867 wrn
= (inst
.instruction
>> 16) & 0xf;
9868 inst
.instruction
&= 0xff0fff0f;
9869 inst
.instruction
|= wrn
;
9870 /* Bail out here; the instruction is now assembled. */
9875 /* Map 32 -> 0, etc. */
9876 inst
.operands
[2].imm
&= 0x1f;
9877 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
9881 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9882 operations first, then control, shift, and load/store. */
9884 /* Insns like "foo X,Y,Z". */
9887 do_mav_triple (void)
9889 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9890 inst
.instruction
|= inst
.operands
[1].reg
;
9891 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9894 /* Insns like "foo W,X,Y,Z".
9895 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9900 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9901 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9902 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9903 inst
.instruction
|= inst
.operands
[3].reg
;
9906 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9910 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9913 /* Maverick shift immediate instructions.
9914 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9915 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9920 int imm
= inst
.operands
[2].imm
;
9922 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9923 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9925 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9926 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9927 Bit 4 should be 0. */
9928 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
9930 inst
.instruction
|= imm
;
9933 /* XScale instructions. Also sorted arithmetic before move. */
9935 /* Xscale multiply-accumulate (argument parse)
9938 MIAxycc acc0,Rm,Rs. */
9943 inst
.instruction
|= inst
.operands
[1].reg
;
9944 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9947 /* Xscale move-accumulator-register (argument parse)
9949 MARcc acc0,RdLo,RdHi. */
9954 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9955 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9958 /* Xscale move-register-accumulator (argument parse)
9960 MRAcc RdLo,RdHi,acc0. */
9965 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
9966 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9967 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9970 /* Encoding functions relevant only to Thumb. */
9972 /* inst.operands[i] is a shifted-register operand; encode
9973 it into inst.instruction in the format used by Thumb32. */
9976 encode_thumb32_shifted_operand (int i
)
9978 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9979 unsigned int shift
= inst
.operands
[i
].shift_kind
;
9981 constraint (inst
.operands
[i
].immisreg
,
9982 _("shift by register not allowed in thumb mode"));
9983 inst
.instruction
|= inst
.operands
[i
].reg
;
9984 if (shift
== SHIFT_RRX
)
9985 inst
.instruction
|= SHIFT_ROR
<< 4;
9988 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9989 _("expression too complex"));
9991 constraint (value
> 32
9992 || (value
== 32 && (shift
== SHIFT_LSL
9993 || shift
== SHIFT_ROR
)),
9994 _("shift expression is too large"));
9998 else if (value
== 32)
10001 inst
.instruction
|= shift
<< 4;
10002 inst
.instruction
|= (value
& 0x1c) << 10;
10003 inst
.instruction
|= (value
& 0x03) << 6;
10008 /* inst.operands[i] was set up by parse_address. Encode it into a
10009 Thumb32 format load or store instruction. Reject forms that cannot
10010 be used with such instructions. If is_t is true, reject forms that
10011 cannot be used with a T instruction; if is_d is true, reject forms
10012 that cannot be used with a D instruction. If it is a store insn,
10013 reject PC in Rn. */
10016 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10018 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10020 constraint (!inst
.operands
[i
].isreg
,
10021 _("Instruction does not support =N addresses"));
10023 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10024 if (inst
.operands
[i
].immisreg
)
10026 constraint (is_pc
, BAD_PC_ADDRESSING
);
10027 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10028 constraint (inst
.operands
[i
].negative
,
10029 _("Thumb does not support negative register indexing"));
10030 constraint (inst
.operands
[i
].postind
,
10031 _("Thumb does not support register post-indexing"));
10032 constraint (inst
.operands
[i
].writeback
,
10033 _("Thumb does not support register indexing with writeback"));
10034 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10035 _("Thumb supports only LSL in shifted register indexing"));
10037 inst
.instruction
|= inst
.operands
[i
].imm
;
10038 if (inst
.operands
[i
].shifted
)
10040 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10041 _("expression too complex"));
10042 constraint (inst
.reloc
.exp
.X_add_number
< 0
10043 || inst
.reloc
.exp
.X_add_number
> 3,
10044 _("shift out of range"));
10045 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10047 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10049 else if (inst
.operands
[i
].preind
)
10051 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10052 constraint (is_t
&& inst
.operands
[i
].writeback
,
10053 _("cannot use writeback with this instruction"));
10054 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10055 BAD_PC_ADDRESSING
);
10059 inst
.instruction
|= 0x01000000;
10060 if (inst
.operands
[i
].writeback
)
10061 inst
.instruction
|= 0x00200000;
10065 inst
.instruction
|= 0x00000c00;
10066 if (inst
.operands
[i
].writeback
)
10067 inst
.instruction
|= 0x00000100;
10069 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10071 else if (inst
.operands
[i
].postind
)
10073 gas_assert (inst
.operands
[i
].writeback
);
10074 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10075 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10078 inst
.instruction
|= 0x00200000;
10080 inst
.instruction
|= 0x00000900;
10081 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10083 else /* unindexed - only for coprocessor */
10084 inst
.error
= _("instruction does not accept unindexed addressing");
10087 /* Table of Thumb instructions which exist in both 16- and 32-bit
10088 encodings (the latter only in post-V6T2 cores). The index is the
10089 value used in the insns table below. When there is more than one
10090 possible 16-bit encoding for the instruction, this table always
10092 Also contains several pseudo-instructions used during relaxation. */
10093 #define T16_32_TAB \
10094 X(_adc, 4140, eb400000), \
10095 X(_adcs, 4140, eb500000), \
10096 X(_add, 1c00, eb000000), \
10097 X(_adds, 1c00, eb100000), \
10098 X(_addi, 0000, f1000000), \
10099 X(_addis, 0000, f1100000), \
10100 X(_add_pc,000f, f20f0000), \
10101 X(_add_sp,000d, f10d0000), \
10102 X(_adr, 000f, f20f0000), \
10103 X(_and, 4000, ea000000), \
10104 X(_ands, 4000, ea100000), \
10105 X(_asr, 1000, fa40f000), \
10106 X(_asrs, 1000, fa50f000), \
10107 X(_b, e000, f000b000), \
10108 X(_bcond, d000, f0008000), \
10109 X(_bic, 4380, ea200000), \
10110 X(_bics, 4380, ea300000), \
10111 X(_cmn, 42c0, eb100f00), \
10112 X(_cmp, 2800, ebb00f00), \
10113 X(_cpsie, b660, f3af8400), \
10114 X(_cpsid, b670, f3af8600), \
10115 X(_cpy, 4600, ea4f0000), \
10116 X(_dec_sp,80dd, f1ad0d00), \
10117 X(_eor, 4040, ea800000), \
10118 X(_eors, 4040, ea900000), \
10119 X(_inc_sp,00dd, f10d0d00), \
10120 X(_ldmia, c800, e8900000), \
10121 X(_ldr, 6800, f8500000), \
10122 X(_ldrb, 7800, f8100000), \
10123 X(_ldrh, 8800, f8300000), \
10124 X(_ldrsb, 5600, f9100000), \
10125 X(_ldrsh, 5e00, f9300000), \
10126 X(_ldr_pc,4800, f85f0000), \
10127 X(_ldr_pc2,4800, f85f0000), \
10128 X(_ldr_sp,9800, f85d0000), \
10129 X(_lsl, 0000, fa00f000), \
10130 X(_lsls, 0000, fa10f000), \
10131 X(_lsr, 0800, fa20f000), \
10132 X(_lsrs, 0800, fa30f000), \
10133 X(_mov, 2000, ea4f0000), \
10134 X(_movs, 2000, ea5f0000), \
10135 X(_mul, 4340, fb00f000), \
10136 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10137 X(_mvn, 43c0, ea6f0000), \
10138 X(_mvns, 43c0, ea7f0000), \
10139 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10140 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10141 X(_orr, 4300, ea400000), \
10142 X(_orrs, 4300, ea500000), \
10143 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10144 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10145 X(_rev, ba00, fa90f080), \
10146 X(_rev16, ba40, fa90f090), \
10147 X(_revsh, bac0, fa90f0b0), \
10148 X(_ror, 41c0, fa60f000), \
10149 X(_rors, 41c0, fa70f000), \
10150 X(_sbc, 4180, eb600000), \
10151 X(_sbcs, 4180, eb700000), \
10152 X(_stmia, c000, e8800000), \
10153 X(_str, 6000, f8400000), \
10154 X(_strb, 7000, f8000000), \
10155 X(_strh, 8000, f8200000), \
10156 X(_str_sp,9000, f84d0000), \
10157 X(_sub, 1e00, eba00000), \
10158 X(_subs, 1e00, ebb00000), \
10159 X(_subi, 8000, f1a00000), \
10160 X(_subis, 8000, f1b00000), \
10161 X(_sxtb, b240, fa4ff080), \
10162 X(_sxth, b200, fa0ff080), \
10163 X(_tst, 4200, ea100f00), \
10164 X(_uxtb, b2c0, fa5ff080), \
10165 X(_uxth, b280, fa1ff080), \
10166 X(_nop, bf00, f3af8000), \
10167 X(_yield, bf10, f3af8001), \
10168 X(_wfe, bf20, f3af8002), \
10169 X(_wfi, bf30, f3af8003), \
10170 X(_sev, bf40, f3af8004), \
10171 X(_sevl, bf50, f3af8005), \
10172 X(_udf, de00, f7f0a000)
10174 /* To catch errors in encoding functions, the codes are all offset by
10175 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10176 as 16-bit instructions. */
10177 #define X(a,b,c) T_MNEM##a
10178 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10181 #define X(a,b,c) 0x##b
10182 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10183 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10186 #define X(a,b,c) 0x##c
10187 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10188 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10189 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10193 /* Thumb instruction encoders, in alphabetical order. */
10195 /* ADDW or SUBW. */
10198 do_t_add_sub_w (void)
10202 Rd
= inst
.operands
[0].reg
;
10203 Rn
= inst
.operands
[1].reg
;
10205 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10206 is the SP-{plus,minus}-immediate form of the instruction. */
10208 constraint (Rd
== REG_PC
, BAD_PC
);
10210 reject_bad_reg (Rd
);
10212 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10213 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10216 /* Parse an add or subtract instruction. We get here with inst.instruction
10217 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10220 do_t_add_sub (void)
10224 Rd
= inst
.operands
[0].reg
;
10225 Rs
= (inst
.operands
[1].present
10226 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10227 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10230 set_it_insn_type_last ();
10232 if (unified_syntax
)
10235 bfd_boolean narrow
;
10238 flags
= (inst
.instruction
== T_MNEM_adds
10239 || inst
.instruction
== T_MNEM_subs
);
10241 narrow
= !in_it_block ();
10243 narrow
= in_it_block ();
10244 if (!inst
.operands
[2].isreg
)
10248 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10250 add
= (inst
.instruction
== T_MNEM_add
10251 || inst
.instruction
== T_MNEM_adds
);
10253 if (inst
.size_req
!= 4)
10255 /* Attempt to use a narrow opcode, with relaxation if
10257 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10258 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10259 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10260 opcode
= T_MNEM_add_sp
;
10261 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10262 opcode
= T_MNEM_add_pc
;
10263 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10266 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10268 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10272 inst
.instruction
= THUMB_OP16(opcode
);
10273 inst
.instruction
|= (Rd
<< 4) | Rs
;
10274 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10275 if (inst
.size_req
!= 2)
10276 inst
.relax
= opcode
;
10279 constraint (inst
.size_req
== 2, BAD_HIREG
);
10281 if (inst
.size_req
== 4
10282 || (inst
.size_req
!= 2 && !opcode
))
10286 constraint (add
, BAD_PC
);
10287 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10288 _("only SUBS PC, LR, #const allowed"));
10289 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10290 _("expression too complex"));
10291 constraint (inst
.reloc
.exp
.X_add_number
< 0
10292 || inst
.reloc
.exp
.X_add_number
> 0xff,
10293 _("immediate value out of range"));
10294 inst
.instruction
= T2_SUBS_PC_LR
10295 | inst
.reloc
.exp
.X_add_number
;
10296 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10299 else if (Rs
== REG_PC
)
10301 /* Always use addw/subw. */
10302 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10303 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10307 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10308 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10311 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10313 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10315 inst
.instruction
|= Rd
<< 8;
10316 inst
.instruction
|= Rs
<< 16;
10321 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10322 unsigned int shift
= inst
.operands
[2].shift_kind
;
10324 Rn
= inst
.operands
[2].reg
;
10325 /* See if we can do this with a 16-bit instruction. */
10326 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10328 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10333 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10334 || inst
.instruction
== T_MNEM_add
)
10336 : T_OPCODE_SUB_R3
);
10337 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10341 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10343 /* Thumb-1 cores (except v6-M) require at least one high
10344 register in a narrow non flag setting add. */
10345 if (Rd
> 7 || Rn
> 7
10346 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10347 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10354 inst
.instruction
= T_OPCODE_ADD_HI
;
10355 inst
.instruction
|= (Rd
& 8) << 4;
10356 inst
.instruction
|= (Rd
& 7);
10357 inst
.instruction
|= Rn
<< 3;
10363 constraint (Rd
== REG_PC
, BAD_PC
);
10364 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10365 constraint (Rs
== REG_PC
, BAD_PC
);
10366 reject_bad_reg (Rn
);
10368 /* If we get here, it can't be done in 16 bits. */
10369 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10370 _("shift must be constant"));
10371 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10372 inst
.instruction
|= Rd
<< 8;
10373 inst
.instruction
|= Rs
<< 16;
10374 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10375 _("shift value over 3 not allowed in thumb mode"));
10376 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10377 _("only LSL shift allowed in thumb mode"));
10378 encode_thumb32_shifted_operand (2);
10383 constraint (inst
.instruction
== T_MNEM_adds
10384 || inst
.instruction
== T_MNEM_subs
,
10387 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10389 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10390 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10393 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10394 ? 0x0000 : 0x8000);
10395 inst
.instruction
|= (Rd
<< 4) | Rs
;
10396 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10400 Rn
= inst
.operands
[2].reg
;
10401 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10403 /* We now have Rd, Rs, and Rn set to registers. */
10404 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10406 /* Can't do this for SUB. */
10407 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10408 inst
.instruction
= T_OPCODE_ADD_HI
;
10409 inst
.instruction
|= (Rd
& 8) << 4;
10410 inst
.instruction
|= (Rd
& 7);
10412 inst
.instruction
|= Rn
<< 3;
10414 inst
.instruction
|= Rs
<< 3;
10416 constraint (1, _("dest must overlap one source register"));
10420 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10421 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10422 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10432 Rd
= inst
.operands
[0].reg
;
10433 reject_bad_reg (Rd
);
10435 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10437 /* Defer to section relaxation. */
10438 inst
.relax
= inst
.instruction
;
10439 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10440 inst
.instruction
|= Rd
<< 4;
10442 else if (unified_syntax
&& inst
.size_req
!= 2)
10444 /* Generate a 32-bit opcode. */
10445 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10446 inst
.instruction
|= Rd
<< 8;
10447 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10448 inst
.reloc
.pc_rel
= 1;
10452 /* Generate a 16-bit opcode. */
10453 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10454 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10455 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10456 inst
.reloc
.pc_rel
= 1;
10458 inst
.instruction
|= Rd
<< 4;
10462 /* Arithmetic instructions for which there is just one 16-bit
10463 instruction encoding, and it allows only two low registers.
10464 For maximal compatibility with ARM syntax, we allow three register
10465 operands even when Thumb-32 instructions are not available, as long
10466 as the first two are identical. For instance, both "sbc r0,r1" and
10467 "sbc r0,r0,r1" are allowed. */
10473 Rd
= inst
.operands
[0].reg
;
10474 Rs
= (inst
.operands
[1].present
10475 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10476 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10477 Rn
= inst
.operands
[2].reg
;
10479 reject_bad_reg (Rd
);
10480 reject_bad_reg (Rs
);
10481 if (inst
.operands
[2].isreg
)
10482 reject_bad_reg (Rn
);
10484 if (unified_syntax
)
10486 if (!inst
.operands
[2].isreg
)
10488 /* For an immediate, we always generate a 32-bit opcode;
10489 section relaxation will shrink it later if possible. */
10490 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10491 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10492 inst
.instruction
|= Rd
<< 8;
10493 inst
.instruction
|= Rs
<< 16;
10494 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10498 bfd_boolean narrow
;
10500 /* See if we can do this with a 16-bit instruction. */
10501 if (THUMB_SETS_FLAGS (inst
.instruction
))
10502 narrow
= !in_it_block ();
10504 narrow
= in_it_block ();
10506 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10508 if (inst
.operands
[2].shifted
)
10510 if (inst
.size_req
== 4)
10516 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10517 inst
.instruction
|= Rd
;
10518 inst
.instruction
|= Rn
<< 3;
10522 /* If we get here, it can't be done in 16 bits. */
10523 constraint (inst
.operands
[2].shifted
10524 && inst
.operands
[2].immisreg
,
10525 _("shift must be constant"));
10526 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10527 inst
.instruction
|= Rd
<< 8;
10528 inst
.instruction
|= Rs
<< 16;
10529 encode_thumb32_shifted_operand (2);
10534 /* On its face this is a lie - the instruction does set the
10535 flags. However, the only supported mnemonic in this mode
10536 says it doesn't. */
10537 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10539 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10540 _("unshifted register required"));
10541 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10542 constraint (Rd
!= Rs
,
10543 _("dest and source1 must be the same register"));
10545 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10546 inst
.instruction
|= Rd
;
10547 inst
.instruction
|= Rn
<< 3;
10551 /* Similarly, but for instructions where the arithmetic operation is
10552 commutative, so we can allow either of them to be different from
10553 the destination operand in a 16-bit instruction. For instance, all
10554 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10561 Rd
= inst
.operands
[0].reg
;
10562 Rs
= (inst
.operands
[1].present
10563 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10564 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10565 Rn
= inst
.operands
[2].reg
;
10567 reject_bad_reg (Rd
);
10568 reject_bad_reg (Rs
);
10569 if (inst
.operands
[2].isreg
)
10570 reject_bad_reg (Rn
);
10572 if (unified_syntax
)
10574 if (!inst
.operands
[2].isreg
)
10576 /* For an immediate, we always generate a 32-bit opcode;
10577 section relaxation will shrink it later if possible. */
10578 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10579 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10580 inst
.instruction
|= Rd
<< 8;
10581 inst
.instruction
|= Rs
<< 16;
10582 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10586 bfd_boolean narrow
;
10588 /* See if we can do this with a 16-bit instruction. */
10589 if (THUMB_SETS_FLAGS (inst
.instruction
))
10590 narrow
= !in_it_block ();
10592 narrow
= in_it_block ();
10594 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10596 if (inst
.operands
[2].shifted
)
10598 if (inst
.size_req
== 4)
10605 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10606 inst
.instruction
|= Rd
;
10607 inst
.instruction
|= Rn
<< 3;
10612 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10613 inst
.instruction
|= Rd
;
10614 inst
.instruction
|= Rs
<< 3;
10619 /* If we get here, it can't be done in 16 bits. */
10620 constraint (inst
.operands
[2].shifted
10621 && inst
.operands
[2].immisreg
,
10622 _("shift must be constant"));
10623 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10624 inst
.instruction
|= Rd
<< 8;
10625 inst
.instruction
|= Rs
<< 16;
10626 encode_thumb32_shifted_operand (2);
10631 /* On its face this is a lie - the instruction does set the
10632 flags. However, the only supported mnemonic in this mode
10633 says it doesn't. */
10634 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10636 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10637 _("unshifted register required"));
10638 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10640 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10641 inst
.instruction
|= Rd
;
10644 inst
.instruction
|= Rn
<< 3;
10646 inst
.instruction
|= Rs
<< 3;
10648 constraint (1, _("dest must overlap one source register"));
10656 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10657 constraint (msb
> 32, _("bit-field extends past end of register"));
10658 /* The instruction encoding stores the LSB and MSB,
10659 not the LSB and width. */
10660 Rd
= inst
.operands
[0].reg
;
10661 reject_bad_reg (Rd
);
10662 inst
.instruction
|= Rd
<< 8;
10663 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10664 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10665 inst
.instruction
|= msb
- 1;
10674 Rd
= inst
.operands
[0].reg
;
10675 reject_bad_reg (Rd
);
10677 /* #0 in second position is alternative syntax for bfc, which is
10678 the same instruction but with REG_PC in the Rm field. */
10679 if (!inst
.operands
[1].isreg
)
10683 Rn
= inst
.operands
[1].reg
;
10684 reject_bad_reg (Rn
);
10687 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10688 constraint (msb
> 32, _("bit-field extends past end of register"));
10689 /* The instruction encoding stores the LSB and MSB,
10690 not the LSB and width. */
10691 inst
.instruction
|= Rd
<< 8;
10692 inst
.instruction
|= Rn
<< 16;
10693 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10694 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10695 inst
.instruction
|= msb
- 1;
10703 Rd
= inst
.operands
[0].reg
;
10704 Rn
= inst
.operands
[1].reg
;
10706 reject_bad_reg (Rd
);
10707 reject_bad_reg (Rn
);
10709 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10710 _("bit-field extends past end of register"));
10711 inst
.instruction
|= Rd
<< 8;
10712 inst
.instruction
|= Rn
<< 16;
10713 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10714 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10715 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10718 /* ARM V5 Thumb BLX (argument parse)
10719 BLX <target_addr> which is BLX(1)
10720 BLX <Rm> which is BLX(2)
10721 Unfortunately, there are two different opcodes for this mnemonic.
10722 So, the insns[].value is not used, and the code here zaps values
10723 into inst.instruction.
10725 ??? How to take advantage of the additional two bits of displacement
10726 available in Thumb32 mode? Need new relocation? */
10731 set_it_insn_type_last ();
10733 if (inst
.operands
[0].isreg
)
10735 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10736 /* We have a register, so this is BLX(2). */
10737 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10741 /* No register. This must be BLX(1). */
10742 inst
.instruction
= 0xf000e800;
10743 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10755 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10757 if (in_it_block ())
10759 /* Conditional branches inside IT blocks are encoded as unconditional
10761 cond
= COND_ALWAYS
;
10766 if (cond
!= COND_ALWAYS
)
10767 opcode
= T_MNEM_bcond
;
10769 opcode
= inst
.instruction
;
10772 && (inst
.size_req
== 4
10773 || (inst
.size_req
!= 2
10774 && (inst
.operands
[0].hasreloc
10775 || inst
.reloc
.exp
.X_op
== O_constant
))))
10777 inst
.instruction
= THUMB_OP32(opcode
);
10778 if (cond
== COND_ALWAYS
)
10779 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
10782 gas_assert (cond
!= 0xF);
10783 inst
.instruction
|= cond
<< 22;
10784 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
10789 inst
.instruction
= THUMB_OP16(opcode
);
10790 if (cond
== COND_ALWAYS
)
10791 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
10794 inst
.instruction
|= cond
<< 8;
10795 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
10797 /* Allow section relaxation. */
10798 if (unified_syntax
&& inst
.size_req
!= 2)
10799 inst
.relax
= opcode
;
10801 inst
.reloc
.type
= reloc
;
10802 inst
.reloc
.pc_rel
= 1;
10805 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10806 between the two is the maximum immediate allowed - which is passed in
10809 do_t_bkpt_hlt1 (int range
)
10811 constraint (inst
.cond
!= COND_ALWAYS
,
10812 _("instruction is always unconditional"));
10813 if (inst
.operands
[0].present
)
10815 constraint (inst
.operands
[0].imm
> range
,
10816 _("immediate value out of range"));
10817 inst
.instruction
|= inst
.operands
[0].imm
;
10820 set_it_insn_type (NEUTRAL_IT_INSN
);
10826 do_t_bkpt_hlt1 (63);
10832 do_t_bkpt_hlt1 (255);
10836 do_t_branch23 (void)
10838 set_it_insn_type_last ();
10839 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
10841 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10842 this file. We used to simply ignore the PLT reloc type here --
10843 the branch encoding is now needed to deal with TLSCALL relocs.
10844 So if we see a PLT reloc now, put it back to how it used to be to
10845 keep the preexisting behaviour. */
10846 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
10847 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
10849 #if defined(OBJ_COFF)
10850 /* If the destination of the branch is a defined symbol which does not have
10851 the THUMB_FUNC attribute, then we must be calling a function which has
10852 the (interfacearm) attribute. We look for the Thumb entry point to that
10853 function and change the branch to refer to that function instead. */
10854 if ( inst
.reloc
.exp
.X_op
== O_symbol
10855 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10856 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10857 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10858 inst
.reloc
.exp
.X_add_symbol
=
10859 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
10866 set_it_insn_type_last ();
10867 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10868 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10869 should cause the alignment to be checked once it is known. This is
10870 because BX PC only works if the instruction is word aligned. */
10878 set_it_insn_type_last ();
10879 Rm
= inst
.operands
[0].reg
;
10880 reject_bad_reg (Rm
);
10881 inst
.instruction
|= Rm
<< 16;
10890 Rd
= inst
.operands
[0].reg
;
10891 Rm
= inst
.operands
[1].reg
;
10893 reject_bad_reg (Rd
);
10894 reject_bad_reg (Rm
);
10896 inst
.instruction
|= Rd
<< 8;
10897 inst
.instruction
|= Rm
<< 16;
10898 inst
.instruction
|= Rm
;
10904 set_it_insn_type (OUTSIDE_IT_INSN
);
10905 inst
.instruction
|= inst
.operands
[0].imm
;
10911 set_it_insn_type (OUTSIDE_IT_INSN
);
10913 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
10914 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
10916 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
10917 inst
.instruction
= 0xf3af8000;
10918 inst
.instruction
|= imod
<< 9;
10919 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
10920 if (inst
.operands
[1].present
)
10921 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
10925 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
10926 && (inst
.operands
[0].imm
& 4),
10927 _("selected processor does not support 'A' form "
10928 "of this instruction"));
10929 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
10930 _("Thumb does not support the 2-argument "
10931 "form of this instruction"));
10932 inst
.instruction
|= inst
.operands
[0].imm
;
10936 /* THUMB CPY instruction (argument parse). */
10941 if (inst
.size_req
== 4)
10943 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
10944 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10945 inst
.instruction
|= inst
.operands
[1].reg
;
10949 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
10950 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
10951 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10958 set_it_insn_type (OUTSIDE_IT_INSN
);
10959 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10960 inst
.instruction
|= inst
.operands
[0].reg
;
10961 inst
.reloc
.pc_rel
= 1;
10962 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
10968 inst
.instruction
|= inst
.operands
[0].imm
;
10974 unsigned Rd
, Rn
, Rm
;
10976 Rd
= inst
.operands
[0].reg
;
10977 Rn
= (inst
.operands
[1].present
10978 ? inst
.operands
[1].reg
: Rd
);
10979 Rm
= inst
.operands
[2].reg
;
10981 reject_bad_reg (Rd
);
10982 reject_bad_reg (Rn
);
10983 reject_bad_reg (Rm
);
10985 inst
.instruction
|= Rd
<< 8;
10986 inst
.instruction
|= Rn
<< 16;
10987 inst
.instruction
|= Rm
;
10993 if (unified_syntax
&& inst
.size_req
== 4)
10994 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10996 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11002 unsigned int cond
= inst
.operands
[0].imm
;
11004 set_it_insn_type (IT_INSN
);
11005 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11007 now_it
.warn_deprecated
= FALSE
;
11009 /* If the condition is a negative condition, invert the mask. */
11010 if ((cond
& 0x1) == 0x0)
11012 unsigned int mask
= inst
.instruction
& 0x000f;
11014 if ((mask
& 0x7) == 0)
11016 /* No conversion needed. */
11017 now_it
.block_length
= 1;
11019 else if ((mask
& 0x3) == 0)
11022 now_it
.block_length
= 2;
11024 else if ((mask
& 0x1) == 0)
11027 now_it
.block_length
= 3;
11032 now_it
.block_length
= 4;
11035 inst
.instruction
&= 0xfff0;
11036 inst
.instruction
|= mask
;
11039 inst
.instruction
|= cond
<< 4;
11042 /* Helper function used for both push/pop and ldm/stm. */
11044 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11048 load
= (inst
.instruction
& (1 << 20)) != 0;
11050 if (mask
& (1 << 13))
11051 inst
.error
= _("SP not allowed in register list");
11053 if ((mask
& (1 << base
)) != 0
11055 inst
.error
= _("having the base register in the register list when "
11056 "using write back is UNPREDICTABLE");
11060 if (mask
& (1 << 15))
11062 if (mask
& (1 << 14))
11063 inst
.error
= _("LR and PC should not both be in register list");
11065 set_it_insn_type_last ();
11070 if (mask
& (1 << 15))
11071 inst
.error
= _("PC not allowed in register list");
11074 if ((mask
& (mask
- 1)) == 0)
11076 /* Single register transfers implemented as str/ldr. */
11079 if (inst
.instruction
& (1 << 23))
11080 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11082 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11086 if (inst
.instruction
& (1 << 23))
11087 inst
.instruction
= 0x00800000; /* ia -> [base] */
11089 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11092 inst
.instruction
|= 0xf8400000;
11094 inst
.instruction
|= 0x00100000;
11096 mask
= ffs (mask
) - 1;
11099 else if (writeback
)
11100 inst
.instruction
|= WRITE_BACK
;
11102 inst
.instruction
|= mask
;
11103 inst
.instruction
|= base
<< 16;
11109 /* This really doesn't seem worth it. */
11110 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11111 _("expression too complex"));
11112 constraint (inst
.operands
[1].writeback
,
11113 _("Thumb load/store multiple does not support {reglist}^"));
11115 if (unified_syntax
)
11117 bfd_boolean narrow
;
11121 /* See if we can use a 16-bit instruction. */
11122 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11123 && inst
.size_req
!= 4
11124 && !(inst
.operands
[1].imm
& ~0xff))
11126 mask
= 1 << inst
.operands
[0].reg
;
11128 if (inst
.operands
[0].reg
<= 7)
11130 if (inst
.instruction
== T_MNEM_stmia
11131 ? inst
.operands
[0].writeback
11132 : (inst
.operands
[0].writeback
11133 == !(inst
.operands
[1].imm
& mask
)))
11135 if (inst
.instruction
== T_MNEM_stmia
11136 && (inst
.operands
[1].imm
& mask
)
11137 && (inst
.operands
[1].imm
& (mask
- 1)))
11138 as_warn (_("value stored for r%d is UNKNOWN"),
11139 inst
.operands
[0].reg
);
11141 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11142 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11143 inst
.instruction
|= inst
.operands
[1].imm
;
11146 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11148 /* This means 1 register in reg list one of 3 situations:
11149 1. Instruction is stmia, but without writeback.
11150 2. lmdia without writeback, but with Rn not in
11152 3. ldmia with writeback, but with Rn in reglist.
11153 Case 3 is UNPREDICTABLE behaviour, so we handle
11154 case 1 and 2 which can be converted into a 16-bit
11155 str or ldr. The SP cases are handled below. */
11156 unsigned long opcode
;
11157 /* First, record an error for Case 3. */
11158 if (inst
.operands
[1].imm
& mask
11159 && inst
.operands
[0].writeback
)
11161 _("having the base register in the register list when "
11162 "using write back is UNPREDICTABLE");
11164 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11166 inst
.instruction
= THUMB_OP16 (opcode
);
11167 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11168 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11172 else if (inst
.operands
[0] .reg
== REG_SP
)
11174 if (inst
.operands
[0].writeback
)
11177 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11178 ? T_MNEM_push
: T_MNEM_pop
);
11179 inst
.instruction
|= inst
.operands
[1].imm
;
11182 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11185 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11186 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11187 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11195 if (inst
.instruction
< 0xffff)
11196 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11198 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11199 inst
.operands
[0].writeback
);
11204 constraint (inst
.operands
[0].reg
> 7
11205 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11206 constraint (inst
.instruction
!= T_MNEM_ldmia
11207 && inst
.instruction
!= T_MNEM_stmia
,
11208 _("Thumb-2 instruction only valid in unified syntax"));
11209 if (inst
.instruction
== T_MNEM_stmia
)
11211 if (!inst
.operands
[0].writeback
)
11212 as_warn (_("this instruction will write back the base register"));
11213 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11214 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11215 as_warn (_("value stored for r%d is UNKNOWN"),
11216 inst
.operands
[0].reg
);
11220 if (!inst
.operands
[0].writeback
11221 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11222 as_warn (_("this instruction will write back the base register"));
11223 else if (inst
.operands
[0].writeback
11224 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11225 as_warn (_("this instruction will not write back the base register"));
11228 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11229 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11230 inst
.instruction
|= inst
.operands
[1].imm
;
11237 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11238 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11239 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11240 || inst
.operands
[1].negative
,
11243 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11245 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11246 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11247 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11253 if (!inst
.operands
[1].present
)
11255 constraint (inst
.operands
[0].reg
== REG_LR
,
11256 _("r14 not allowed as first register "
11257 "when second register is omitted"));
11258 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11260 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11263 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11264 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11265 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11271 unsigned long opcode
;
11274 if (inst
.operands
[0].isreg
11275 && !inst
.operands
[0].preind
11276 && inst
.operands
[0].reg
== REG_PC
)
11277 set_it_insn_type_last ();
11279 opcode
= inst
.instruction
;
11280 if (unified_syntax
)
11282 if (!inst
.operands
[1].isreg
)
11284 if (opcode
<= 0xffff)
11285 inst
.instruction
= THUMB_OP32 (opcode
);
11286 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11289 if (inst
.operands
[1].isreg
11290 && !inst
.operands
[1].writeback
11291 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11292 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11293 && opcode
<= 0xffff
11294 && inst
.size_req
!= 4)
11296 /* Insn may have a 16-bit form. */
11297 Rn
= inst
.operands
[1].reg
;
11298 if (inst
.operands
[1].immisreg
)
11300 inst
.instruction
= THUMB_OP16 (opcode
);
11302 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11304 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11305 reject_bad_reg (inst
.operands
[1].imm
);
11307 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11308 && opcode
!= T_MNEM_ldrsb
)
11309 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11310 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11317 if (inst
.reloc
.pc_rel
)
11318 opcode
= T_MNEM_ldr_pc2
;
11320 opcode
= T_MNEM_ldr_pc
;
11324 if (opcode
== T_MNEM_ldr
)
11325 opcode
= T_MNEM_ldr_sp
;
11327 opcode
= T_MNEM_str_sp
;
11329 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11333 inst
.instruction
= inst
.operands
[0].reg
;
11334 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11336 inst
.instruction
|= THUMB_OP16 (opcode
);
11337 if (inst
.size_req
== 2)
11338 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11340 inst
.relax
= opcode
;
11344 /* Definitely a 32-bit variant. */
11346 /* Warning for Erratum 752419. */
11347 if (opcode
== T_MNEM_ldr
11348 && inst
.operands
[0].reg
== REG_SP
11349 && inst
.operands
[1].writeback
== 1
11350 && !inst
.operands
[1].immisreg
)
11352 if (no_cpu_selected ()
11353 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11354 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11355 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11356 as_warn (_("This instruction may be unpredictable "
11357 "if executed on M-profile cores "
11358 "with interrupts enabled."));
11361 /* Do some validations regarding addressing modes. */
11362 if (inst
.operands
[1].immisreg
)
11363 reject_bad_reg (inst
.operands
[1].imm
);
11365 constraint (inst
.operands
[1].writeback
== 1
11366 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11369 inst
.instruction
= THUMB_OP32 (opcode
);
11370 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11371 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11372 check_ldr_r15_aligned ();
11376 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11378 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11380 /* Only [Rn,Rm] is acceptable. */
11381 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11382 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11383 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11384 || inst
.operands
[1].negative
,
11385 _("Thumb does not support this addressing mode"));
11386 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11390 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11391 if (!inst
.operands
[1].isreg
)
11392 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11395 constraint (!inst
.operands
[1].preind
11396 || inst
.operands
[1].shifted
11397 || inst
.operands
[1].writeback
,
11398 _("Thumb does not support this addressing mode"));
11399 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11401 constraint (inst
.instruction
& 0x0600,
11402 _("byte or halfword not valid for base register"));
11403 constraint (inst
.operands
[1].reg
== REG_PC
11404 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11405 _("r15 based store not allowed"));
11406 constraint (inst
.operands
[1].immisreg
,
11407 _("invalid base register for register offset"));
11409 if (inst
.operands
[1].reg
== REG_PC
)
11410 inst
.instruction
= T_OPCODE_LDR_PC
;
11411 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11412 inst
.instruction
= T_OPCODE_LDR_SP
;
11414 inst
.instruction
= T_OPCODE_STR_SP
;
11416 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11417 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11421 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11422 if (!inst
.operands
[1].immisreg
)
11424 /* Immediate offset. */
11425 inst
.instruction
|= inst
.operands
[0].reg
;
11426 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11427 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11431 /* Register offset. */
11432 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11433 constraint (inst
.operands
[1].negative
,
11434 _("Thumb does not support this addressing mode"));
11437 switch (inst
.instruction
)
11439 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11440 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11441 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11442 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11443 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11444 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11445 case 0x5600 /* ldrsb */:
11446 case 0x5e00 /* ldrsh */: break;
11450 inst
.instruction
|= inst
.operands
[0].reg
;
11451 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11452 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11458 if (!inst
.operands
[1].present
)
11460 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11461 constraint (inst
.operands
[0].reg
== REG_LR
,
11462 _("r14 not allowed here"));
11463 constraint (inst
.operands
[0].reg
== REG_R12
,
11464 _("r12 not allowed here"));
11467 if (inst
.operands
[2].writeback
11468 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11469 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11470 as_warn (_("base register written back, and overlaps "
11471 "one of transfer registers"));
11473 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11474 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11475 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11481 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11482 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11488 unsigned Rd
, Rn
, Rm
, Ra
;
11490 Rd
= inst
.operands
[0].reg
;
11491 Rn
= inst
.operands
[1].reg
;
11492 Rm
= inst
.operands
[2].reg
;
11493 Ra
= inst
.operands
[3].reg
;
11495 reject_bad_reg (Rd
);
11496 reject_bad_reg (Rn
);
11497 reject_bad_reg (Rm
);
11498 reject_bad_reg (Ra
);
11500 inst
.instruction
|= Rd
<< 8;
11501 inst
.instruction
|= Rn
<< 16;
11502 inst
.instruction
|= Rm
;
11503 inst
.instruction
|= Ra
<< 12;
11509 unsigned RdLo
, RdHi
, Rn
, Rm
;
11511 RdLo
= inst
.operands
[0].reg
;
11512 RdHi
= inst
.operands
[1].reg
;
11513 Rn
= inst
.operands
[2].reg
;
11514 Rm
= inst
.operands
[3].reg
;
11516 reject_bad_reg (RdLo
);
11517 reject_bad_reg (RdHi
);
11518 reject_bad_reg (Rn
);
11519 reject_bad_reg (Rm
);
11521 inst
.instruction
|= RdLo
<< 12;
11522 inst
.instruction
|= RdHi
<< 8;
11523 inst
.instruction
|= Rn
<< 16;
11524 inst
.instruction
|= Rm
;
11528 do_t_mov_cmp (void)
11532 Rn
= inst
.operands
[0].reg
;
11533 Rm
= inst
.operands
[1].reg
;
11536 set_it_insn_type_last ();
11538 if (unified_syntax
)
11540 int r0off
= (inst
.instruction
== T_MNEM_mov
11541 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11542 unsigned long opcode
;
11543 bfd_boolean narrow
;
11544 bfd_boolean low_regs
;
11546 low_regs
= (Rn
<= 7 && Rm
<= 7);
11547 opcode
= inst
.instruction
;
11548 if (in_it_block ())
11549 narrow
= opcode
!= T_MNEM_movs
;
11551 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11552 if (inst
.size_req
== 4
11553 || inst
.operands
[1].shifted
)
11556 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11557 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11558 && !inst
.operands
[1].shifted
11562 inst
.instruction
= T2_SUBS_PC_LR
;
11566 if (opcode
== T_MNEM_cmp
)
11568 constraint (Rn
== REG_PC
, BAD_PC
);
11571 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11573 warn_deprecated_sp (Rm
);
11574 /* R15 was documented as a valid choice for Rm in ARMv6,
11575 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11576 tools reject R15, so we do too. */
11577 constraint (Rm
== REG_PC
, BAD_PC
);
11580 reject_bad_reg (Rm
);
11582 else if (opcode
== T_MNEM_mov
11583 || opcode
== T_MNEM_movs
)
11585 if (inst
.operands
[1].isreg
)
11587 if (opcode
== T_MNEM_movs
)
11589 reject_bad_reg (Rn
);
11590 reject_bad_reg (Rm
);
11594 /* This is mov.n. */
11595 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11596 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11598 as_tsktsk (_("Use of r%u as a source register is "
11599 "deprecated when r%u is the destination "
11600 "register."), Rm
, Rn
);
11605 /* This is mov.w. */
11606 constraint (Rn
== REG_PC
, BAD_PC
);
11607 constraint (Rm
== REG_PC
, BAD_PC
);
11608 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11612 reject_bad_reg (Rn
);
11615 if (!inst
.operands
[1].isreg
)
11617 /* Immediate operand. */
11618 if (!in_it_block () && opcode
== T_MNEM_mov
)
11620 if (low_regs
&& narrow
)
11622 inst
.instruction
= THUMB_OP16 (opcode
);
11623 inst
.instruction
|= Rn
<< 8;
11624 if (inst
.size_req
== 2)
11625 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11627 inst
.relax
= opcode
;
11631 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11632 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11633 inst
.instruction
|= Rn
<< r0off
;
11634 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11637 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11638 && (inst
.instruction
== T_MNEM_mov
11639 || inst
.instruction
== T_MNEM_movs
))
11641 /* Register shifts are encoded as separate shift instructions. */
11642 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11644 if (in_it_block ())
11649 if (inst
.size_req
== 4)
11652 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11658 switch (inst
.operands
[1].shift_kind
)
11661 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11664 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11667 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11670 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11676 inst
.instruction
= opcode
;
11679 inst
.instruction
|= Rn
;
11680 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11685 inst
.instruction
|= CONDS_BIT
;
11687 inst
.instruction
|= Rn
<< 8;
11688 inst
.instruction
|= Rm
<< 16;
11689 inst
.instruction
|= inst
.operands
[1].imm
;
11694 /* Some mov with immediate shift have narrow variants.
11695 Register shifts are handled above. */
11696 if (low_regs
&& inst
.operands
[1].shifted
11697 && (inst
.instruction
== T_MNEM_mov
11698 || inst
.instruction
== T_MNEM_movs
))
11700 if (in_it_block ())
11701 narrow
= (inst
.instruction
== T_MNEM_mov
);
11703 narrow
= (inst
.instruction
== T_MNEM_movs
);
11708 switch (inst
.operands
[1].shift_kind
)
11710 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11711 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11712 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11713 default: narrow
= FALSE
; break;
11719 inst
.instruction
|= Rn
;
11720 inst
.instruction
|= Rm
<< 3;
11721 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11725 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11726 inst
.instruction
|= Rn
<< r0off
;
11727 encode_thumb32_shifted_operand (1);
11731 switch (inst
.instruction
)
11734 /* In v4t or v5t a move of two lowregs produces unpredictable
11735 results. Don't allow this. */
11738 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11739 "MOV Rd, Rs with two low registers is not "
11740 "permitted on this architecture");
11741 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11745 inst
.instruction
= T_OPCODE_MOV_HR
;
11746 inst
.instruction
|= (Rn
& 0x8) << 4;
11747 inst
.instruction
|= (Rn
& 0x7);
11748 inst
.instruction
|= Rm
<< 3;
11752 /* We know we have low registers at this point.
11753 Generate LSLS Rd, Rs, #0. */
11754 inst
.instruction
= T_OPCODE_LSL_I
;
11755 inst
.instruction
|= Rn
;
11756 inst
.instruction
|= Rm
<< 3;
11762 inst
.instruction
= T_OPCODE_CMP_LR
;
11763 inst
.instruction
|= Rn
;
11764 inst
.instruction
|= Rm
<< 3;
11768 inst
.instruction
= T_OPCODE_CMP_HR
;
11769 inst
.instruction
|= (Rn
& 0x8) << 4;
11770 inst
.instruction
|= (Rn
& 0x7);
11771 inst
.instruction
|= Rm
<< 3;
11778 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11780 /* PR 10443: Do not silently ignore shifted operands. */
11781 constraint (inst
.operands
[1].shifted
,
11782 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11784 if (inst
.operands
[1].isreg
)
11786 if (Rn
< 8 && Rm
< 8)
11788 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11789 since a MOV instruction produces unpredictable results. */
11790 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11791 inst
.instruction
= T_OPCODE_ADD_I3
;
11793 inst
.instruction
= T_OPCODE_CMP_LR
;
11795 inst
.instruction
|= Rn
;
11796 inst
.instruction
|= Rm
<< 3;
11800 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11801 inst
.instruction
= T_OPCODE_MOV_HR
;
11803 inst
.instruction
= T_OPCODE_CMP_HR
;
11809 constraint (Rn
> 7,
11810 _("only lo regs allowed with immediate"));
11811 inst
.instruction
|= Rn
<< 8;
11812 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11823 top
= (inst
.instruction
& 0x00800000) != 0;
11824 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
11826 constraint (top
, _(":lower16: not allowed this instruction"));
11827 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
11829 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
11831 constraint (!top
, _(":upper16: not allowed this instruction"));
11832 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
11835 Rd
= inst
.operands
[0].reg
;
11836 reject_bad_reg (Rd
);
11838 inst
.instruction
|= Rd
<< 8;
11839 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
11841 imm
= inst
.reloc
.exp
.X_add_number
;
11842 inst
.instruction
|= (imm
& 0xf000) << 4;
11843 inst
.instruction
|= (imm
& 0x0800) << 15;
11844 inst
.instruction
|= (imm
& 0x0700) << 4;
11845 inst
.instruction
|= (imm
& 0x00ff);
11850 do_t_mvn_tst (void)
11854 Rn
= inst
.operands
[0].reg
;
11855 Rm
= inst
.operands
[1].reg
;
11857 if (inst
.instruction
== T_MNEM_cmp
11858 || inst
.instruction
== T_MNEM_cmn
)
11859 constraint (Rn
== REG_PC
, BAD_PC
);
11861 reject_bad_reg (Rn
);
11862 reject_bad_reg (Rm
);
11864 if (unified_syntax
)
11866 int r0off
= (inst
.instruction
== T_MNEM_mvn
11867 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
11868 bfd_boolean narrow
;
11870 if (inst
.size_req
== 4
11871 || inst
.instruction
> 0xffff
11872 || inst
.operands
[1].shifted
11873 || Rn
> 7 || Rm
> 7)
11875 else if (inst
.instruction
== T_MNEM_cmn
11876 || inst
.instruction
== T_MNEM_tst
)
11878 else if (THUMB_SETS_FLAGS (inst
.instruction
))
11879 narrow
= !in_it_block ();
11881 narrow
= in_it_block ();
11883 if (!inst
.operands
[1].isreg
)
11885 /* For an immediate, we always generate a 32-bit opcode;
11886 section relaxation will shrink it later if possible. */
11887 if (inst
.instruction
< 0xffff)
11888 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11889 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11890 inst
.instruction
|= Rn
<< r0off
;
11891 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11895 /* See if we can do this with a 16-bit instruction. */
11898 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11899 inst
.instruction
|= Rn
;
11900 inst
.instruction
|= Rm
<< 3;
11904 constraint (inst
.operands
[1].shifted
11905 && inst
.operands
[1].immisreg
,
11906 _("shift must be constant"));
11907 if (inst
.instruction
< 0xffff)
11908 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11909 inst
.instruction
|= Rn
<< r0off
;
11910 encode_thumb32_shifted_operand (1);
11916 constraint (inst
.instruction
> 0xffff
11917 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
11918 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
11919 _("unshifted register required"));
11920 constraint (Rn
> 7 || Rm
> 7,
11923 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11924 inst
.instruction
|= Rn
;
11925 inst
.instruction
|= Rm
<< 3;
11934 if (do_vfp_nsyn_mrs () == SUCCESS
)
11937 Rd
= inst
.operands
[0].reg
;
11938 reject_bad_reg (Rd
);
11939 inst
.instruction
|= Rd
<< 8;
11941 if (inst
.operands
[1].isreg
)
11943 unsigned br
= inst
.operands
[1].reg
;
11944 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
11945 as_bad (_("bad register for mrs"));
11947 inst
.instruction
|= br
& (0xf << 16);
11948 inst
.instruction
|= (br
& 0x300) >> 4;
11949 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
11953 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11955 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11957 /* PR gas/12698: The constraint is only applied for m_profile.
11958 If the user has specified -march=all, we want to ignore it as
11959 we are building for any CPU type, including non-m variants. */
11960 bfd_boolean m_profile
=
11961 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
11962 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
11963 "not support requested special purpose register"));
11966 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11968 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
11969 _("'APSR', 'CPSR' or 'SPSR' expected"));
11971 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11972 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
11973 inst
.instruction
|= 0xf0000;
11983 if (do_vfp_nsyn_msr () == SUCCESS
)
11986 constraint (!inst
.operands
[1].isreg
,
11987 _("Thumb encoding does not support an immediate here"));
11989 if (inst
.operands
[0].isreg
)
11990 flags
= (int)(inst
.operands
[0].reg
);
11992 flags
= inst
.operands
[0].imm
;
11994 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11996 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11998 /* PR gas/12698: The constraint is only applied for m_profile.
11999 If the user has specified -march=all, we want to ignore it as
12000 we are building for any CPU type, including non-m variants. */
12001 bfd_boolean m_profile
=
12002 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12003 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12004 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12005 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12006 && bits
!= PSR_f
)) && m_profile
,
12007 _("selected processor does not support requested special "
12008 "purpose register"));
12011 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12012 "requested special purpose register"));
12014 Rn
= inst
.operands
[1].reg
;
12015 reject_bad_reg (Rn
);
12017 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12018 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12019 inst
.instruction
|= (flags
& 0x300) >> 4;
12020 inst
.instruction
|= (flags
& 0xff);
12021 inst
.instruction
|= Rn
<< 16;
12027 bfd_boolean narrow
;
12028 unsigned Rd
, Rn
, Rm
;
12030 if (!inst
.operands
[2].present
)
12031 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12033 Rd
= inst
.operands
[0].reg
;
12034 Rn
= inst
.operands
[1].reg
;
12035 Rm
= inst
.operands
[2].reg
;
12037 if (unified_syntax
)
12039 if (inst
.size_req
== 4
12045 else if (inst
.instruction
== T_MNEM_muls
)
12046 narrow
= !in_it_block ();
12048 narrow
= in_it_block ();
12052 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12053 constraint (Rn
> 7 || Rm
> 7,
12060 /* 16-bit MULS/Conditional MUL. */
12061 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12062 inst
.instruction
|= Rd
;
12065 inst
.instruction
|= Rm
<< 3;
12067 inst
.instruction
|= Rn
<< 3;
12069 constraint (1, _("dest must overlap one source register"));
12073 constraint (inst
.instruction
!= T_MNEM_mul
,
12074 _("Thumb-2 MUL must not set flags"));
12076 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12077 inst
.instruction
|= Rd
<< 8;
12078 inst
.instruction
|= Rn
<< 16;
12079 inst
.instruction
|= Rm
<< 0;
12081 reject_bad_reg (Rd
);
12082 reject_bad_reg (Rn
);
12083 reject_bad_reg (Rm
);
12090 unsigned RdLo
, RdHi
, Rn
, Rm
;
12092 RdLo
= inst
.operands
[0].reg
;
12093 RdHi
= inst
.operands
[1].reg
;
12094 Rn
= inst
.operands
[2].reg
;
12095 Rm
= inst
.operands
[3].reg
;
12097 reject_bad_reg (RdLo
);
12098 reject_bad_reg (RdHi
);
12099 reject_bad_reg (Rn
);
12100 reject_bad_reg (Rm
);
12102 inst
.instruction
|= RdLo
<< 12;
12103 inst
.instruction
|= RdHi
<< 8;
12104 inst
.instruction
|= Rn
<< 16;
12105 inst
.instruction
|= Rm
;
12108 as_tsktsk (_("rdhi and rdlo must be different"));
12114 set_it_insn_type (NEUTRAL_IT_INSN
);
12116 if (unified_syntax
)
12118 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12120 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12121 inst
.instruction
|= inst
.operands
[0].imm
;
12125 /* PR9722: Check for Thumb2 availability before
12126 generating a thumb2 nop instruction. */
12127 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12129 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12130 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12133 inst
.instruction
= 0x46c0;
12138 constraint (inst
.operands
[0].present
,
12139 _("Thumb does not support NOP with hints"));
12140 inst
.instruction
= 0x46c0;
12147 if (unified_syntax
)
12149 bfd_boolean narrow
;
12151 if (THUMB_SETS_FLAGS (inst
.instruction
))
12152 narrow
= !in_it_block ();
12154 narrow
= in_it_block ();
12155 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12157 if (inst
.size_req
== 4)
12162 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12163 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12164 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12168 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12169 inst
.instruction
|= inst
.operands
[0].reg
;
12170 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12175 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12177 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12179 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12180 inst
.instruction
|= inst
.operands
[0].reg
;
12181 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12190 Rd
= inst
.operands
[0].reg
;
12191 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12193 reject_bad_reg (Rd
);
12194 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12195 reject_bad_reg (Rn
);
12197 inst
.instruction
|= Rd
<< 8;
12198 inst
.instruction
|= Rn
<< 16;
12200 if (!inst
.operands
[2].isreg
)
12202 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12203 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12209 Rm
= inst
.operands
[2].reg
;
12210 reject_bad_reg (Rm
);
12212 constraint (inst
.operands
[2].shifted
12213 && inst
.operands
[2].immisreg
,
12214 _("shift must be constant"));
12215 encode_thumb32_shifted_operand (2);
12222 unsigned Rd
, Rn
, Rm
;
12224 Rd
= inst
.operands
[0].reg
;
12225 Rn
= inst
.operands
[1].reg
;
12226 Rm
= inst
.operands
[2].reg
;
12228 reject_bad_reg (Rd
);
12229 reject_bad_reg (Rn
);
12230 reject_bad_reg (Rm
);
12232 inst
.instruction
|= Rd
<< 8;
12233 inst
.instruction
|= Rn
<< 16;
12234 inst
.instruction
|= Rm
;
12235 if (inst
.operands
[3].present
)
12237 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12238 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12239 _("expression too complex"));
12240 inst
.instruction
|= (val
& 0x1c) << 10;
12241 inst
.instruction
|= (val
& 0x03) << 6;
12248 if (!inst
.operands
[3].present
)
12252 inst
.instruction
&= ~0x00000020;
12254 /* PR 10168. Swap the Rm and Rn registers. */
12255 Rtmp
= inst
.operands
[1].reg
;
12256 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12257 inst
.operands
[2].reg
= Rtmp
;
12265 if (inst
.operands
[0].immisreg
)
12266 reject_bad_reg (inst
.operands
[0].imm
);
12268 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12272 do_t_push_pop (void)
12276 constraint (inst
.operands
[0].writeback
,
12277 _("push/pop do not support {reglist}^"));
12278 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12279 _("expression too complex"));
12281 mask
= inst
.operands
[0].imm
;
12282 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12283 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12284 else if (inst
.size_req
!= 4
12285 && (mask
& ~0xff) == (1 << (inst
.instruction
== T_MNEM_push
12286 ? REG_LR
: REG_PC
)))
12288 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12289 inst
.instruction
|= THUMB_PP_PC_LR
;
12290 inst
.instruction
|= mask
& 0xff;
12292 else if (unified_syntax
)
12294 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12295 encode_thumb2_ldmstm (13, mask
, TRUE
);
12299 inst
.error
= _("invalid register list to push/pop instruction");
12309 Rd
= inst
.operands
[0].reg
;
12310 Rm
= inst
.operands
[1].reg
;
12312 reject_bad_reg (Rd
);
12313 reject_bad_reg (Rm
);
12315 inst
.instruction
|= Rd
<< 8;
12316 inst
.instruction
|= Rm
<< 16;
12317 inst
.instruction
|= Rm
;
12325 Rd
= inst
.operands
[0].reg
;
12326 Rm
= inst
.operands
[1].reg
;
12328 reject_bad_reg (Rd
);
12329 reject_bad_reg (Rm
);
12331 if (Rd
<= 7 && Rm
<= 7
12332 && inst
.size_req
!= 4)
12334 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12335 inst
.instruction
|= Rd
;
12336 inst
.instruction
|= Rm
<< 3;
12338 else if (unified_syntax
)
12340 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12341 inst
.instruction
|= Rd
<< 8;
12342 inst
.instruction
|= Rm
<< 16;
12343 inst
.instruction
|= Rm
;
12346 inst
.error
= BAD_HIREG
;
12354 Rd
= inst
.operands
[0].reg
;
12355 Rm
= inst
.operands
[1].reg
;
12357 reject_bad_reg (Rd
);
12358 reject_bad_reg (Rm
);
12360 inst
.instruction
|= Rd
<< 8;
12361 inst
.instruction
|= Rm
;
12369 Rd
= inst
.operands
[0].reg
;
12370 Rs
= (inst
.operands
[1].present
12371 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12372 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12374 reject_bad_reg (Rd
);
12375 reject_bad_reg (Rs
);
12376 if (inst
.operands
[2].isreg
)
12377 reject_bad_reg (inst
.operands
[2].reg
);
12379 inst
.instruction
|= Rd
<< 8;
12380 inst
.instruction
|= Rs
<< 16;
12381 if (!inst
.operands
[2].isreg
)
12383 bfd_boolean narrow
;
12385 if ((inst
.instruction
& 0x00100000) != 0)
12386 narrow
= !in_it_block ();
12388 narrow
= in_it_block ();
12390 if (Rd
> 7 || Rs
> 7)
12393 if (inst
.size_req
== 4 || !unified_syntax
)
12396 if (inst
.reloc
.exp
.X_op
!= O_constant
12397 || inst
.reloc
.exp
.X_add_number
!= 0)
12400 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12401 relaxation, but it doesn't seem worth the hassle. */
12404 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12405 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12406 inst
.instruction
|= Rs
<< 3;
12407 inst
.instruction
|= Rd
;
12411 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12412 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12416 encode_thumb32_shifted_operand (2);
12422 if (warn_on_deprecated
12423 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12424 as_tsktsk (_("setend use is deprecated for ARMv8"));
12426 set_it_insn_type (OUTSIDE_IT_INSN
);
12427 if (inst
.operands
[0].imm
)
12428 inst
.instruction
|= 0x8;
12434 if (!inst
.operands
[1].present
)
12435 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12437 if (unified_syntax
)
12439 bfd_boolean narrow
;
12442 switch (inst
.instruction
)
12445 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12447 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12449 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12451 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12455 if (THUMB_SETS_FLAGS (inst
.instruction
))
12456 narrow
= !in_it_block ();
12458 narrow
= in_it_block ();
12459 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12461 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12463 if (inst
.operands
[2].isreg
12464 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12465 || inst
.operands
[2].reg
> 7))
12467 if (inst
.size_req
== 4)
12470 reject_bad_reg (inst
.operands
[0].reg
);
12471 reject_bad_reg (inst
.operands
[1].reg
);
12475 if (inst
.operands
[2].isreg
)
12477 reject_bad_reg (inst
.operands
[2].reg
);
12478 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12479 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12480 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12481 inst
.instruction
|= inst
.operands
[2].reg
;
12483 /* PR 12854: Error on extraneous shifts. */
12484 constraint (inst
.operands
[2].shifted
,
12485 _("extraneous shift as part of operand to shift insn"));
12489 inst
.operands
[1].shifted
= 1;
12490 inst
.operands
[1].shift_kind
= shift_kind
;
12491 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12492 ? T_MNEM_movs
: T_MNEM_mov
);
12493 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12494 encode_thumb32_shifted_operand (1);
12495 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12496 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12501 if (inst
.operands
[2].isreg
)
12503 switch (shift_kind
)
12505 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12506 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12507 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12508 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12512 inst
.instruction
|= inst
.operands
[0].reg
;
12513 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12515 /* PR 12854: Error on extraneous shifts. */
12516 constraint (inst
.operands
[2].shifted
,
12517 _("extraneous shift as part of operand to shift insn"));
12521 switch (shift_kind
)
12523 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12524 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12525 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12528 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12529 inst
.instruction
|= inst
.operands
[0].reg
;
12530 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12536 constraint (inst
.operands
[0].reg
> 7
12537 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12538 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12540 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12542 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12543 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12544 _("source1 and dest must be same register"));
12546 switch (inst
.instruction
)
12548 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12549 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12550 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12551 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12555 inst
.instruction
|= inst
.operands
[0].reg
;
12556 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12558 /* PR 12854: Error on extraneous shifts. */
12559 constraint (inst
.operands
[2].shifted
,
12560 _("extraneous shift as part of operand to shift insn"));
12564 switch (inst
.instruction
)
12566 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12567 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12568 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12569 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12572 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12573 inst
.instruction
|= inst
.operands
[0].reg
;
12574 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12582 unsigned Rd
, Rn
, Rm
;
12584 Rd
= inst
.operands
[0].reg
;
12585 Rn
= inst
.operands
[1].reg
;
12586 Rm
= inst
.operands
[2].reg
;
12588 reject_bad_reg (Rd
);
12589 reject_bad_reg (Rn
);
12590 reject_bad_reg (Rm
);
12592 inst
.instruction
|= Rd
<< 8;
12593 inst
.instruction
|= Rn
<< 16;
12594 inst
.instruction
|= Rm
;
12600 unsigned Rd
, Rn
, Rm
;
12602 Rd
= inst
.operands
[0].reg
;
12603 Rm
= inst
.operands
[1].reg
;
12604 Rn
= inst
.operands
[2].reg
;
12606 reject_bad_reg (Rd
);
12607 reject_bad_reg (Rn
);
12608 reject_bad_reg (Rm
);
12610 inst
.instruction
|= Rd
<< 8;
12611 inst
.instruction
|= Rn
<< 16;
12612 inst
.instruction
|= Rm
;
12618 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12619 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12620 _("SMC is not permitted on this architecture"));
12621 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12622 _("expression too complex"));
12623 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12624 inst
.instruction
|= (value
& 0xf000) >> 12;
12625 inst
.instruction
|= (value
& 0x0ff0);
12626 inst
.instruction
|= (value
& 0x000f) << 16;
12627 /* PR gas/15623: SMC instructions must be last in an IT block. */
12628 set_it_insn_type_last ();
12634 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12636 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12637 inst
.instruction
|= (value
& 0x0fff);
12638 inst
.instruction
|= (value
& 0xf000) << 4;
12642 do_t_ssat_usat (int bias
)
12646 Rd
= inst
.operands
[0].reg
;
12647 Rn
= inst
.operands
[2].reg
;
12649 reject_bad_reg (Rd
);
12650 reject_bad_reg (Rn
);
12652 inst
.instruction
|= Rd
<< 8;
12653 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12654 inst
.instruction
|= Rn
<< 16;
12656 if (inst
.operands
[3].present
)
12658 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12660 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12662 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12663 _("expression too complex"));
12665 if (shift_amount
!= 0)
12667 constraint (shift_amount
> 31,
12668 _("shift expression is too large"));
12670 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12671 inst
.instruction
|= 0x00200000; /* sh bit. */
12673 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12674 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12682 do_t_ssat_usat (1);
12690 Rd
= inst
.operands
[0].reg
;
12691 Rn
= inst
.operands
[2].reg
;
12693 reject_bad_reg (Rd
);
12694 reject_bad_reg (Rn
);
12696 inst
.instruction
|= Rd
<< 8;
12697 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12698 inst
.instruction
|= Rn
<< 16;
12704 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12705 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12706 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12707 || inst
.operands
[2].negative
,
12710 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12712 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12713 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12714 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12715 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12721 if (!inst
.operands
[2].present
)
12722 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12724 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12725 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12726 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12729 inst
.instruction
|= inst
.operands
[0].reg
;
12730 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12731 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12732 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12738 unsigned Rd
, Rn
, Rm
;
12740 Rd
= inst
.operands
[0].reg
;
12741 Rn
= inst
.operands
[1].reg
;
12742 Rm
= inst
.operands
[2].reg
;
12744 reject_bad_reg (Rd
);
12745 reject_bad_reg (Rn
);
12746 reject_bad_reg (Rm
);
12748 inst
.instruction
|= Rd
<< 8;
12749 inst
.instruction
|= Rn
<< 16;
12750 inst
.instruction
|= Rm
;
12751 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
12759 Rd
= inst
.operands
[0].reg
;
12760 Rm
= inst
.operands
[1].reg
;
12762 reject_bad_reg (Rd
);
12763 reject_bad_reg (Rm
);
12765 if (inst
.instruction
<= 0xffff
12766 && inst
.size_req
!= 4
12767 && Rd
<= 7 && Rm
<= 7
12768 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
12770 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12771 inst
.instruction
|= Rd
;
12772 inst
.instruction
|= Rm
<< 3;
12774 else if (unified_syntax
)
12776 if (inst
.instruction
<= 0xffff)
12777 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12778 inst
.instruction
|= Rd
<< 8;
12779 inst
.instruction
|= Rm
;
12780 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
12784 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
12785 _("Thumb encoding does not support rotation"));
12786 constraint (1, BAD_HIREG
);
12793 /* We have to do the following check manually as ARM_EXT_OS only applies
12795 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
12797 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
12798 /* This only applies to the v6m howver, not later architectures. */
12799 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
12800 as_bad (_("SVC is not permitted on this architecture"));
12801 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
12804 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
12813 half
= (inst
.instruction
& 0x10) != 0;
12814 set_it_insn_type_last ();
12815 constraint (inst
.operands
[0].immisreg
,
12816 _("instruction requires register index"));
12818 Rn
= inst
.operands
[0].reg
;
12819 Rm
= inst
.operands
[0].imm
;
12821 constraint (Rn
== REG_SP
, BAD_SP
);
12822 reject_bad_reg (Rm
);
12824 constraint (!half
&& inst
.operands
[0].shifted
,
12825 _("instruction does not allow shifted index"));
12826 inst
.instruction
|= (Rn
<< 16) | Rm
;
12832 if (!inst
.operands
[0].present
)
12833 inst
.operands
[0].imm
= 0;
12835 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
12837 constraint (inst
.size_req
== 2,
12838 _("immediate value out of range"));
12839 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12840 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
12841 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
12845 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12846 inst
.instruction
|= inst
.operands
[0].imm
;
12849 set_it_insn_type (NEUTRAL_IT_INSN
);
12856 do_t_ssat_usat (0);
12864 Rd
= inst
.operands
[0].reg
;
12865 Rn
= inst
.operands
[2].reg
;
12867 reject_bad_reg (Rd
);
12868 reject_bad_reg (Rn
);
12870 inst
.instruction
|= Rd
<< 8;
12871 inst
.instruction
|= inst
.operands
[1].imm
;
12872 inst
.instruction
|= Rn
<< 16;
12875 /* Neon instruction encoder helpers. */
12877 /* Encodings for the different types for various Neon opcodes. */
12879 /* An "invalid" code for the following tables. */
12882 struct neon_tab_entry
12885 unsigned float_or_poly
;
12886 unsigned scalar_or_imm
;
12889 /* Map overloaded Neon opcodes to their respective encodings. */
12890 #define NEON_ENC_TAB \
12891 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12892 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12893 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12894 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12895 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12896 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12897 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12898 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12899 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12900 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12901 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12902 /* Register variants of the following two instructions are encoded as
12903 vcge / vcgt with the operands reversed. */ \
12904 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12905 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12906 X(vfma, N_INV, 0x0000c10, N_INV), \
12907 X(vfms, N_INV, 0x0200c10, N_INV), \
12908 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12909 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12910 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12911 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12912 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12913 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12914 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12915 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12916 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12917 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12918 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12919 X(vshl, 0x0000400, N_INV, 0x0800510), \
12920 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12921 X(vand, 0x0000110, N_INV, 0x0800030), \
12922 X(vbic, 0x0100110, N_INV, 0x0800030), \
12923 X(veor, 0x1000110, N_INV, N_INV), \
12924 X(vorn, 0x0300110, N_INV, 0x0800010), \
12925 X(vorr, 0x0200110, N_INV, 0x0800010), \
12926 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12927 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12928 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12929 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12930 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12931 X(vst1, 0x0000000, 0x0800000, N_INV), \
12932 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12933 X(vst2, 0x0000100, 0x0800100, N_INV), \
12934 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12935 X(vst3, 0x0000200, 0x0800200, N_INV), \
12936 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12937 X(vst4, 0x0000300, 0x0800300, N_INV), \
12938 X(vmovn, 0x1b20200, N_INV, N_INV), \
12939 X(vtrn, 0x1b20080, N_INV, N_INV), \
12940 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12941 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12942 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12943 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12944 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12945 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12946 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12947 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12948 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12949 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12950 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
12951 X(vseleq, 0xe000a00, N_INV, N_INV), \
12952 X(vselvs, 0xe100a00, N_INV, N_INV), \
12953 X(vselge, 0xe200a00, N_INV, N_INV), \
12954 X(vselgt, 0xe300a00, N_INV, N_INV), \
12955 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
12956 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
12957 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
12958 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
12959 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
12960 X(aes, 0x3b00300, N_INV, N_INV), \
12961 X(sha3op, 0x2000c00, N_INV, N_INV), \
12962 X(sha1h, 0x3b902c0, N_INV, N_INV), \
12963 X(sha2op, 0x3ba0380, N_INV, N_INV)
12967 #define X(OPC,I,F,S) N_MNEM_##OPC
12972 static const struct neon_tab_entry neon_enc_tab
[] =
12974 #define X(OPC,I,F,S) { (I), (F), (S) }
12979 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12980 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12981 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12982 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12983 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12984 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12985 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12986 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12987 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12988 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12989 #define NEON_ENC_SINGLE_(X) \
12990 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12991 #define NEON_ENC_DOUBLE_(X) \
12992 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12993 #define NEON_ENC_FPV8_(X) \
12994 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
12996 #define NEON_ENCODE(type, inst) \
12999 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13000 inst.is_neon = 1; \
13004 #define check_neon_suffixes \
13007 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13009 as_bad (_("invalid neon suffix for non neon instruction")); \
13015 /* Define shapes for instruction operands. The following mnemonic characters
13016 are used in this table:
13018 F - VFP S<n> register
13019 D - Neon D<n> register
13020 Q - Neon Q<n> register
13024 L - D<n> register list
13026 This table is used to generate various data:
13027 - enumerations of the form NS_DDR to be used as arguments to
13029 - a table classifying shapes into single, double, quad, mixed.
13030 - a table used to drive neon_select_shape. */
13032 #define NEON_SHAPE_DEF \
13033 X(3, (D, D, D), DOUBLE), \
13034 X(3, (Q, Q, Q), QUAD), \
13035 X(3, (D, D, I), DOUBLE), \
13036 X(3, (Q, Q, I), QUAD), \
13037 X(3, (D, D, S), DOUBLE), \
13038 X(3, (Q, Q, S), QUAD), \
13039 X(2, (D, D), DOUBLE), \
13040 X(2, (Q, Q), QUAD), \
13041 X(2, (D, S), DOUBLE), \
13042 X(2, (Q, S), QUAD), \
13043 X(2, (D, R), DOUBLE), \
13044 X(2, (Q, R), QUAD), \
13045 X(2, (D, I), DOUBLE), \
13046 X(2, (Q, I), QUAD), \
13047 X(3, (D, L, D), DOUBLE), \
13048 X(2, (D, Q), MIXED), \
13049 X(2, (Q, D), MIXED), \
13050 X(3, (D, Q, I), MIXED), \
13051 X(3, (Q, D, I), MIXED), \
13052 X(3, (Q, D, D), MIXED), \
13053 X(3, (D, Q, Q), MIXED), \
13054 X(3, (Q, Q, D), MIXED), \
13055 X(3, (Q, D, S), MIXED), \
13056 X(3, (D, Q, S), MIXED), \
13057 X(4, (D, D, D, I), DOUBLE), \
13058 X(4, (Q, Q, Q, I), QUAD), \
13059 X(2, (F, F), SINGLE), \
13060 X(3, (F, F, F), SINGLE), \
13061 X(2, (F, I), SINGLE), \
13062 X(2, (F, D), MIXED), \
13063 X(2, (D, F), MIXED), \
13064 X(3, (F, F, I), MIXED), \
13065 X(4, (R, R, F, F), SINGLE), \
13066 X(4, (F, F, R, R), SINGLE), \
13067 X(3, (D, R, R), DOUBLE), \
13068 X(3, (R, R, D), DOUBLE), \
13069 X(2, (S, R), SINGLE), \
13070 X(2, (R, S), SINGLE), \
13071 X(2, (F, R), SINGLE), \
13072 X(2, (R, F), SINGLE)
13074 #define S2(A,B) NS_##A##B
13075 #define S3(A,B,C) NS_##A##B##C
13076 #define S4(A,B,C,D) NS_##A##B##C##D
13078 #define X(N, L, C) S##N L
13091 enum neon_shape_class
13099 #define X(N, L, C) SC_##C
13101 static enum neon_shape_class neon_shape_class
[] =
13119 /* Register widths of above. */
13120 static unsigned neon_shape_el_size
[] =
13131 struct neon_shape_info
13134 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13137 #define S2(A,B) { SE_##A, SE_##B }
13138 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13139 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13141 #define X(N, L, C) { N, S##N L }
13143 static struct neon_shape_info neon_shape_tab
[] =
13153 /* Bit masks used in type checking given instructions.
13154 'N_EQK' means the type must be the same as (or based on in some way) the key
13155 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13156 set, various other bits can be set as well in order to modify the meaning of
13157 the type constraint. */
13159 enum neon_type_mask
13183 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13184 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13185 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13186 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13187 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13188 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13189 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13190 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13191 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13192 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13193 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13195 N_MAX_NONSPECIAL
= N_P64
13198 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13200 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13201 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13202 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13203 #define N_SUF_32 (N_SU_32 | N_F32)
13204 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13205 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
13207 /* Pass this as the first type argument to neon_check_type to ignore types
13209 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13211 /* Select a "shape" for the current instruction (describing register types or
13212 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13213 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13214 function of operand parsing, so this function doesn't need to be called.
13215 Shapes should be listed in order of decreasing length. */
13217 static enum neon_shape
13218 neon_select_shape (enum neon_shape shape
, ...)
13221 enum neon_shape first_shape
= shape
;
13223 /* Fix missing optional operands. FIXME: we don't know at this point how
13224 many arguments we should have, so this makes the assumption that we have
13225 > 1. This is true of all current Neon opcodes, I think, but may not be
13226 true in the future. */
13227 if (!inst
.operands
[1].present
)
13228 inst
.operands
[1] = inst
.operands
[0];
13230 va_start (ap
, shape
);
13232 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13237 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13239 if (!inst
.operands
[j
].present
)
13245 switch (neon_shape_tab
[shape
].el
[j
])
13248 if (!(inst
.operands
[j
].isreg
13249 && inst
.operands
[j
].isvec
13250 && inst
.operands
[j
].issingle
13251 && !inst
.operands
[j
].isquad
))
13256 if (!(inst
.operands
[j
].isreg
13257 && inst
.operands
[j
].isvec
13258 && !inst
.operands
[j
].isquad
13259 && !inst
.operands
[j
].issingle
))
13264 if (!(inst
.operands
[j
].isreg
13265 && !inst
.operands
[j
].isvec
))
13270 if (!(inst
.operands
[j
].isreg
13271 && inst
.operands
[j
].isvec
13272 && inst
.operands
[j
].isquad
13273 && !inst
.operands
[j
].issingle
))
13278 if (!(!inst
.operands
[j
].isreg
13279 && !inst
.operands
[j
].isscalar
))
13284 if (!(!inst
.operands
[j
].isreg
13285 && inst
.operands
[j
].isscalar
))
13295 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13296 /* We've matched all the entries in the shape table, and we don't
13297 have any left over operands which have not been matched. */
13303 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13304 first_error (_("invalid instruction shape"));
13309 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13310 means the Q bit should be set). */
13313 neon_quad (enum neon_shape shape
)
13315 return neon_shape_class
[shape
] == SC_QUAD
;
13319 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13322 /* Allow modification to be made to types which are constrained to be
13323 based on the key element, based on bits set alongside N_EQK. */
13324 if ((typebits
& N_EQK
) != 0)
13326 if ((typebits
& N_HLF
) != 0)
13328 else if ((typebits
& N_DBL
) != 0)
13330 if ((typebits
& N_SGN
) != 0)
13331 *g_type
= NT_signed
;
13332 else if ((typebits
& N_UNS
) != 0)
13333 *g_type
= NT_unsigned
;
13334 else if ((typebits
& N_INT
) != 0)
13335 *g_type
= NT_integer
;
13336 else if ((typebits
& N_FLT
) != 0)
13337 *g_type
= NT_float
;
13338 else if ((typebits
& N_SIZ
) != 0)
13339 *g_type
= NT_untyped
;
13343 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13344 operand type, i.e. the single type specified in a Neon instruction when it
13345 is the only one given. */
13347 static struct neon_type_el
13348 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13350 struct neon_type_el dest
= *key
;
13352 gas_assert ((thisarg
& N_EQK
) != 0);
13354 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13359 /* Convert Neon type and size into compact bitmask representation. */
13361 static enum neon_type_mask
13362 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13369 case 8: return N_8
;
13370 case 16: return N_16
;
13371 case 32: return N_32
;
13372 case 64: return N_64
;
13380 case 8: return N_I8
;
13381 case 16: return N_I16
;
13382 case 32: return N_I32
;
13383 case 64: return N_I64
;
13391 case 16: return N_F16
;
13392 case 32: return N_F32
;
13393 case 64: return N_F64
;
13401 case 8: return N_P8
;
13402 case 16: return N_P16
;
13403 case 64: return N_P64
;
13411 case 8: return N_S8
;
13412 case 16: return N_S16
;
13413 case 32: return N_S32
;
13414 case 64: return N_S64
;
13422 case 8: return N_U8
;
13423 case 16: return N_U16
;
13424 case 32: return N_U32
;
13425 case 64: return N_U64
;
13436 /* Convert compact Neon bitmask type representation to a type and size. Only
13437 handles the case where a single bit is set in the mask. */
13440 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13441 enum neon_type_mask mask
)
13443 if ((mask
& N_EQK
) != 0)
13446 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13448 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13450 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13452 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13457 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13459 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13460 *type
= NT_unsigned
;
13461 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13462 *type
= NT_integer
;
13463 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13464 *type
= NT_untyped
;
13465 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13467 else if ((mask
& (N_F16
| N_F32
| N_F64
)) != 0)
13475 /* Modify a bitmask of allowed types. This is only needed for type
13479 modify_types_allowed (unsigned allowed
, unsigned mods
)
13482 enum neon_el_type type
;
13488 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13490 if (el_type_of_type_chk (&type
, &size
,
13491 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13493 neon_modify_type_size (mods
, &type
, &size
);
13494 destmask
|= type_chk_of_el_type (type
, size
);
13501 /* Check type and return type classification.
13502 The manual states (paraphrase): If one datatype is given, it indicates the
13504 - the second operand, if there is one
13505 - the operand, if there is no second operand
13506 - the result, if there are no operands.
13507 This isn't quite good enough though, so we use a concept of a "key" datatype
13508 which is set on a per-instruction basis, which is the one which matters when
13509 only one data type is written.
13510 Note: this function has side-effects (e.g. filling in missing operands). All
13511 Neon instructions should call it before performing bit encoding. */
13513 static struct neon_type_el
13514 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13517 unsigned i
, pass
, key_el
= 0;
13518 unsigned types
[NEON_MAX_TYPE_ELS
];
13519 enum neon_el_type k_type
= NT_invtype
;
13520 unsigned k_size
= -1u;
13521 struct neon_type_el badtype
= {NT_invtype
, -1};
13522 unsigned key_allowed
= 0;
13524 /* Optional registers in Neon instructions are always (not) in operand 1.
13525 Fill in the missing operand here, if it was omitted. */
13526 if (els
> 1 && !inst
.operands
[1].present
)
13527 inst
.operands
[1] = inst
.operands
[0];
13529 /* Suck up all the varargs. */
13531 for (i
= 0; i
< els
; i
++)
13533 unsigned thisarg
= va_arg (ap
, unsigned);
13534 if (thisarg
== N_IGNORE_TYPE
)
13539 types
[i
] = thisarg
;
13540 if ((thisarg
& N_KEY
) != 0)
13545 if (inst
.vectype
.elems
> 0)
13546 for (i
= 0; i
< els
; i
++)
13547 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13549 first_error (_("types specified in both the mnemonic and operands"));
13553 /* Duplicate inst.vectype elements here as necessary.
13554 FIXME: No idea if this is exactly the same as the ARM assembler,
13555 particularly when an insn takes one register and one non-register
13557 if (inst
.vectype
.elems
== 1 && els
> 1)
13560 inst
.vectype
.elems
= els
;
13561 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13562 for (j
= 0; j
< els
; j
++)
13564 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13567 else if (inst
.vectype
.elems
== 0 && els
> 0)
13570 /* No types were given after the mnemonic, so look for types specified
13571 after each operand. We allow some flexibility here; as long as the
13572 "key" operand has a type, we can infer the others. */
13573 for (j
= 0; j
< els
; j
++)
13574 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13575 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13577 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13579 for (j
= 0; j
< els
; j
++)
13580 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13581 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13586 first_error (_("operand types can't be inferred"));
13590 else if (inst
.vectype
.elems
!= els
)
13592 first_error (_("type specifier has the wrong number of parts"));
13596 for (pass
= 0; pass
< 2; pass
++)
13598 for (i
= 0; i
< els
; i
++)
13600 unsigned thisarg
= types
[i
];
13601 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13602 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13603 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13604 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13606 /* Decay more-specific signed & unsigned types to sign-insensitive
13607 integer types if sign-specific variants are unavailable. */
13608 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13609 && (types_allowed
& N_SU_ALL
) == 0)
13610 g_type
= NT_integer
;
13612 /* If only untyped args are allowed, decay any more specific types to
13613 them. Some instructions only care about signs for some element
13614 sizes, so handle that properly. */
13615 if (((types_allowed
& N_UNT
) == 0)
13616 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13617 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13618 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13619 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13620 g_type
= NT_untyped
;
13624 if ((thisarg
& N_KEY
) != 0)
13628 key_allowed
= thisarg
& ~N_KEY
;
13633 if ((thisarg
& N_VFP
) != 0)
13635 enum neon_shape_el regshape
;
13636 unsigned regwidth
, match
;
13638 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13641 first_error (_("invalid instruction shape"));
13644 regshape
= neon_shape_tab
[ns
].el
[i
];
13645 regwidth
= neon_shape_el_size
[regshape
];
13647 /* In VFP mode, operands must match register widths. If we
13648 have a key operand, use its width, else use the width of
13649 the current operand. */
13655 if (regwidth
!= match
)
13657 first_error (_("operand size must match register width"));
13662 if ((thisarg
& N_EQK
) == 0)
13664 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
13666 if ((given_type
& types_allowed
) == 0)
13668 first_error (_("bad type in Neon instruction"));
13674 enum neon_el_type mod_k_type
= k_type
;
13675 unsigned mod_k_size
= k_size
;
13676 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
13677 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
13679 first_error (_("inconsistent types in Neon instruction"));
13687 return inst
.vectype
.el
[key_el
];
13690 /* Neon-style VFP instruction forwarding. */
13692 /* Thumb VFP instructions have 0xE in the condition field. */
13695 do_vfp_cond_or_thumb (void)
13700 inst
.instruction
|= 0xe0000000;
13702 inst
.instruction
|= inst
.cond
<< 28;
13705 /* Look up and encode a simple mnemonic, for use as a helper function for the
13706 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13707 etc. It is assumed that operand parsing has already been done, and that the
13708 operands are in the form expected by the given opcode (this isn't necessarily
13709 the same as the form in which they were parsed, hence some massaging must
13710 take place before this function is called).
13711 Checks current arch version against that in the looked-up opcode. */
13714 do_vfp_nsyn_opcode (const char *opname
)
13716 const struct asm_opcode
*opcode
;
13718 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
13723 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
13724 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
13731 inst
.instruction
= opcode
->tvalue
;
13732 opcode
->tencode ();
13736 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
13737 opcode
->aencode ();
13742 do_vfp_nsyn_add_sub (enum neon_shape rs
)
13744 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
13749 do_vfp_nsyn_opcode ("fadds");
13751 do_vfp_nsyn_opcode ("fsubs");
13756 do_vfp_nsyn_opcode ("faddd");
13758 do_vfp_nsyn_opcode ("fsubd");
13762 /* Check operand types to see if this is a VFP instruction, and if so call
13766 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
13768 enum neon_shape rs
;
13769 struct neon_type_el et
;
13774 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13775 et
= neon_check_type (2, rs
,
13776 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13780 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13781 et
= neon_check_type (3, rs
,
13782 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13789 if (et
.type
!= NT_invtype
)
13800 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
13802 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
13807 do_vfp_nsyn_opcode ("fmacs");
13809 do_vfp_nsyn_opcode ("fnmacs");
13814 do_vfp_nsyn_opcode ("fmacd");
13816 do_vfp_nsyn_opcode ("fnmacd");
13821 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
13823 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
13828 do_vfp_nsyn_opcode ("ffmas");
13830 do_vfp_nsyn_opcode ("ffnmas");
13835 do_vfp_nsyn_opcode ("ffmad");
13837 do_vfp_nsyn_opcode ("ffnmad");
13842 do_vfp_nsyn_mul (enum neon_shape rs
)
13845 do_vfp_nsyn_opcode ("fmuls");
13847 do_vfp_nsyn_opcode ("fmuld");
13851 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
13853 int is_neg
= (inst
.instruction
& 0x80) != 0;
13854 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
13859 do_vfp_nsyn_opcode ("fnegs");
13861 do_vfp_nsyn_opcode ("fabss");
13866 do_vfp_nsyn_opcode ("fnegd");
13868 do_vfp_nsyn_opcode ("fabsd");
13872 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13873 insns belong to Neon, and are handled elsewhere. */
13876 do_vfp_nsyn_ldm_stm (int is_dbmode
)
13878 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
13882 do_vfp_nsyn_opcode ("fldmdbs");
13884 do_vfp_nsyn_opcode ("fldmias");
13889 do_vfp_nsyn_opcode ("fstmdbs");
13891 do_vfp_nsyn_opcode ("fstmias");
13896 do_vfp_nsyn_sqrt (void)
13898 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13899 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13902 do_vfp_nsyn_opcode ("fsqrts");
13904 do_vfp_nsyn_opcode ("fsqrtd");
13908 do_vfp_nsyn_div (void)
13910 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13911 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
13912 N_F32
| N_F64
| N_KEY
| N_VFP
);
13915 do_vfp_nsyn_opcode ("fdivs");
13917 do_vfp_nsyn_opcode ("fdivd");
13921 do_vfp_nsyn_nmul (void)
13923 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13924 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
13925 N_F32
| N_F64
| N_KEY
| N_VFP
);
13929 NEON_ENCODE (SINGLE
, inst
);
13930 do_vfp_sp_dyadic ();
13934 NEON_ENCODE (DOUBLE
, inst
);
13935 do_vfp_dp_rd_rn_rm ();
13937 do_vfp_cond_or_thumb ();
13941 do_vfp_nsyn_cmp (void)
13943 if (inst
.operands
[1].isreg
)
13945 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13946 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13950 NEON_ENCODE (SINGLE
, inst
);
13951 do_vfp_sp_monadic ();
13955 NEON_ENCODE (DOUBLE
, inst
);
13956 do_vfp_dp_rd_rm ();
13961 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
13962 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
13964 switch (inst
.instruction
& 0x0fffffff)
13967 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
13970 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
13978 NEON_ENCODE (SINGLE
, inst
);
13979 do_vfp_sp_compare_z ();
13983 NEON_ENCODE (DOUBLE
, inst
);
13987 do_vfp_cond_or_thumb ();
13991 nsyn_insert_sp (void)
13993 inst
.operands
[1] = inst
.operands
[0];
13994 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
13995 inst
.operands
[0].reg
= REG_SP
;
13996 inst
.operands
[0].isreg
= 1;
13997 inst
.operands
[0].writeback
= 1;
13998 inst
.operands
[0].present
= 1;
14002 do_vfp_nsyn_push (void)
14005 if (inst
.operands
[1].issingle
)
14006 do_vfp_nsyn_opcode ("fstmdbs");
14008 do_vfp_nsyn_opcode ("fstmdbd");
14012 do_vfp_nsyn_pop (void)
14015 if (inst
.operands
[1].issingle
)
14016 do_vfp_nsyn_opcode ("fldmias");
14018 do_vfp_nsyn_opcode ("fldmiad");
14021 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14022 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14025 neon_dp_fixup (struct arm_it
* insn
)
14027 unsigned int i
= insn
->instruction
;
14032 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14043 insn
->instruction
= i
;
14046 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14050 neon_logbits (unsigned x
)
14052 return ffs (x
) - 4;
14055 #define LOW4(R) ((R) & 0xf)
14056 #define HI1(R) (((R) >> 4) & 1)
14058 /* Encode insns with bit pattern:
14060 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14061 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14063 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14064 different meaning for some instruction. */
14067 neon_three_same (int isquad
, int ubit
, int size
)
14069 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14070 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14071 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14072 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14073 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14074 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14075 inst
.instruction
|= (isquad
!= 0) << 6;
14076 inst
.instruction
|= (ubit
!= 0) << 24;
14078 inst
.instruction
|= neon_logbits (size
) << 20;
14080 neon_dp_fixup (&inst
);
14083 /* Encode instructions of the form:
14085 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14086 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14088 Don't write size if SIZE == -1. */
14091 neon_two_same (int qbit
, int ubit
, int size
)
14093 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14094 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14095 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14096 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14097 inst
.instruction
|= (qbit
!= 0) << 6;
14098 inst
.instruction
|= (ubit
!= 0) << 24;
14101 inst
.instruction
|= neon_logbits (size
) << 18;
14103 neon_dp_fixup (&inst
);
14106 /* Neon instruction encoders, in approximate order of appearance. */
14109 do_neon_dyadic_i_su (void)
14111 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14112 struct neon_type_el et
= neon_check_type (3, rs
,
14113 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14114 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14118 do_neon_dyadic_i64_su (void)
14120 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14121 struct neon_type_el et
= neon_check_type (3, rs
,
14122 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14123 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14127 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14130 unsigned size
= et
.size
>> 3;
14131 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14132 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14133 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14134 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14135 inst
.instruction
|= (isquad
!= 0) << 6;
14136 inst
.instruction
|= immbits
<< 16;
14137 inst
.instruction
|= (size
>> 3) << 7;
14138 inst
.instruction
|= (size
& 0x7) << 19;
14140 inst
.instruction
|= (uval
!= 0) << 24;
14142 neon_dp_fixup (&inst
);
14146 do_neon_shl_imm (void)
14148 if (!inst
.operands
[2].isreg
)
14150 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14151 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14152 int imm
= inst
.operands
[2].imm
;
14154 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14155 _("immediate out of range for shift"));
14156 NEON_ENCODE (IMMED
, inst
);
14157 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14161 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14162 struct neon_type_el et
= neon_check_type (3, rs
,
14163 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14166 /* VSHL/VQSHL 3-register variants have syntax such as:
14168 whereas other 3-register operations encoded by neon_three_same have
14171 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14173 tmp
= inst
.operands
[2].reg
;
14174 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14175 inst
.operands
[1].reg
= tmp
;
14176 NEON_ENCODE (INTEGER
, inst
);
14177 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14182 do_neon_qshl_imm (void)
14184 if (!inst
.operands
[2].isreg
)
14186 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14187 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14188 int imm
= inst
.operands
[2].imm
;
14190 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14191 _("immediate out of range for shift"));
14192 NEON_ENCODE (IMMED
, inst
);
14193 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14197 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14198 struct neon_type_el et
= neon_check_type (3, rs
,
14199 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14202 /* See note in do_neon_shl_imm. */
14203 tmp
= inst
.operands
[2].reg
;
14204 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14205 inst
.operands
[1].reg
= tmp
;
14206 NEON_ENCODE (INTEGER
, inst
);
14207 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14212 do_neon_rshl (void)
14214 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14215 struct neon_type_el et
= neon_check_type (3, rs
,
14216 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14219 tmp
= inst
.operands
[2].reg
;
14220 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14221 inst
.operands
[1].reg
= tmp
;
14222 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14226 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14228 /* Handle .I8 pseudo-instructions. */
14231 /* Unfortunately, this will make everything apart from zero out-of-range.
14232 FIXME is this the intended semantics? There doesn't seem much point in
14233 accepting .I8 if so. */
14234 immediate
|= immediate
<< 8;
14240 if (immediate
== (immediate
& 0x000000ff))
14242 *immbits
= immediate
;
14245 else if (immediate
== (immediate
& 0x0000ff00))
14247 *immbits
= immediate
>> 8;
14250 else if (immediate
== (immediate
& 0x00ff0000))
14252 *immbits
= immediate
>> 16;
14255 else if (immediate
== (immediate
& 0xff000000))
14257 *immbits
= immediate
>> 24;
14260 if ((immediate
& 0xffff) != (immediate
>> 16))
14261 goto bad_immediate
;
14262 immediate
&= 0xffff;
14265 if (immediate
== (immediate
& 0x000000ff))
14267 *immbits
= immediate
;
14270 else if (immediate
== (immediate
& 0x0000ff00))
14272 *immbits
= immediate
>> 8;
14277 first_error (_("immediate value out of range"));
14282 do_neon_logic (void)
14284 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14286 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14287 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14288 /* U bit and size field were set as part of the bitmask. */
14289 NEON_ENCODE (INTEGER
, inst
);
14290 neon_three_same (neon_quad (rs
), 0, -1);
14294 const int three_ops_form
= (inst
.operands
[2].present
14295 && !inst
.operands
[2].isreg
);
14296 const int immoperand
= (three_ops_form
? 2 : 1);
14297 enum neon_shape rs
= (three_ops_form
14298 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14299 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14300 struct neon_type_el et
= neon_check_type (2, rs
,
14301 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14302 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14306 if (et
.type
== NT_invtype
)
14309 if (three_ops_form
)
14310 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14311 _("first and second operands shall be the same register"));
14313 NEON_ENCODE (IMMED
, inst
);
14315 immbits
= inst
.operands
[immoperand
].imm
;
14318 /* .i64 is a pseudo-op, so the immediate must be a repeating
14320 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14321 inst
.operands
[immoperand
].reg
: 0))
14323 /* Set immbits to an invalid constant. */
14324 immbits
= 0xdeadbeef;
14331 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14335 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14339 /* Pseudo-instruction for VBIC. */
14340 neon_invert_size (&immbits
, 0, et
.size
);
14341 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14345 /* Pseudo-instruction for VORR. */
14346 neon_invert_size (&immbits
, 0, et
.size
);
14347 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14357 inst
.instruction
|= neon_quad (rs
) << 6;
14358 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14359 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14360 inst
.instruction
|= cmode
<< 8;
14361 neon_write_immbits (immbits
);
14363 neon_dp_fixup (&inst
);
14368 do_neon_bitfield (void)
14370 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14371 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14372 neon_three_same (neon_quad (rs
), 0, -1);
14376 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14379 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14380 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14382 if (et
.type
== NT_float
)
14384 NEON_ENCODE (FLOAT
, inst
);
14385 neon_three_same (neon_quad (rs
), 0, -1);
14389 NEON_ENCODE (INTEGER
, inst
);
14390 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14395 do_neon_dyadic_if_su (void)
14397 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14401 do_neon_dyadic_if_su_d (void)
14403 /* This version only allow D registers, but that constraint is enforced during
14404 operand parsing so we don't need to do anything extra here. */
14405 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14409 do_neon_dyadic_if_i_d (void)
14411 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14412 affected if we specify unsigned args. */
14413 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14416 enum vfp_or_neon_is_neon_bits
14419 NEON_CHECK_ARCH
= 2,
14420 NEON_CHECK_ARCH8
= 4
14423 /* Call this function if an instruction which may have belonged to the VFP or
14424 Neon instruction sets, but turned out to be a Neon instruction (due to the
14425 operand types involved, etc.). We have to check and/or fix-up a couple of
14428 - Make sure the user hasn't attempted to make a Neon instruction
14430 - Alter the value in the condition code field if necessary.
14431 - Make sure that the arch supports Neon instructions.
14433 Which of these operations take place depends on bits from enum
14434 vfp_or_neon_is_neon_bits.
14436 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14437 current instruction's condition is COND_ALWAYS, the condition field is
14438 changed to inst.uncond_value. This is necessary because instructions shared
14439 between VFP and Neon may be conditional for the VFP variants only, and the
14440 unconditional Neon version must have, e.g., 0xF in the condition field. */
14443 vfp_or_neon_is_neon (unsigned check
)
14445 /* Conditions are always legal in Thumb mode (IT blocks). */
14446 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14448 if (inst
.cond
!= COND_ALWAYS
)
14450 first_error (_(BAD_COND
));
14453 if (inst
.uncond_value
!= -1)
14454 inst
.instruction
|= inst
.uncond_value
<< 28;
14457 if ((check
& NEON_CHECK_ARCH
)
14458 && !mark_feature_used (&fpu_neon_ext_v1
))
14460 first_error (_(BAD_FPU
));
14464 if ((check
& NEON_CHECK_ARCH8
)
14465 && !mark_feature_used (&fpu_neon_ext_armv8
))
14467 first_error (_(BAD_FPU
));
14475 do_neon_addsub_if_i (void)
14477 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14480 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14483 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14484 affected if we specify unsigned args. */
14485 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14488 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14490 V<op> A,B (A is operand 0, B is operand 2)
14495 so handle that case specially. */
14498 neon_exchange_operands (void)
14500 void *scratch
= alloca (sizeof (inst
.operands
[0]));
14501 if (inst
.operands
[1].present
)
14503 /* Swap operands[1] and operands[2]. */
14504 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14505 inst
.operands
[1] = inst
.operands
[2];
14506 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14510 inst
.operands
[1] = inst
.operands
[2];
14511 inst
.operands
[2] = inst
.operands
[0];
14516 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14518 if (inst
.operands
[2].isreg
)
14521 neon_exchange_operands ();
14522 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14526 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14527 struct neon_type_el et
= neon_check_type (2, rs
,
14528 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14530 NEON_ENCODE (IMMED
, inst
);
14531 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14532 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14533 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14534 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14535 inst
.instruction
|= neon_quad (rs
) << 6;
14536 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14537 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14539 neon_dp_fixup (&inst
);
14546 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
14550 do_neon_cmp_inv (void)
14552 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
14558 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14561 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14562 scalars, which are encoded in 5 bits, M : Rm.
14563 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14564 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14568 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14570 unsigned regno
= NEON_SCALAR_REG (scalar
);
14571 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14576 if (regno
> 7 || elno
> 3)
14578 return regno
| (elno
<< 3);
14581 if (regno
> 15 || elno
> 1)
14583 return regno
| (elno
<< 4);
14587 first_error (_("scalar out of range for multiply instruction"));
14593 /* Encode multiply / multiply-accumulate scalar instructions. */
14596 neon_mul_mac (struct neon_type_el et
, int ubit
)
14600 /* Give a more helpful error message if we have an invalid type. */
14601 if (et
.type
== NT_invtype
)
14604 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14605 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14606 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14607 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14608 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14609 inst
.instruction
|= LOW4 (scalar
);
14610 inst
.instruction
|= HI1 (scalar
) << 5;
14611 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14612 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14613 inst
.instruction
|= (ubit
!= 0) << 24;
14615 neon_dp_fixup (&inst
);
14619 do_neon_mac_maybe_scalar (void)
14621 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
14624 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14627 if (inst
.operands
[2].isscalar
)
14629 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14630 struct neon_type_el et
= neon_check_type (3, rs
,
14631 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
14632 NEON_ENCODE (SCALAR
, inst
);
14633 neon_mul_mac (et
, neon_quad (rs
));
14637 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14638 affected if we specify unsigned args. */
14639 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14644 do_neon_fmac (void)
14646 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
14649 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14652 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14658 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14659 struct neon_type_el et
= neon_check_type (3, rs
,
14660 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14661 neon_three_same (neon_quad (rs
), 0, et
.size
);
14664 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14665 same types as the MAC equivalents. The polynomial type for this instruction
14666 is encoded the same as the integer type. */
14671 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
14674 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14677 if (inst
.operands
[2].isscalar
)
14678 do_neon_mac_maybe_scalar ();
14680 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
14684 do_neon_qdmulh (void)
14686 if (inst
.operands
[2].isscalar
)
14688 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14689 struct neon_type_el et
= neon_check_type (3, rs
,
14690 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14691 NEON_ENCODE (SCALAR
, inst
);
14692 neon_mul_mac (et
, neon_quad (rs
));
14696 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14697 struct neon_type_el et
= neon_check_type (3, rs
,
14698 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14699 NEON_ENCODE (INTEGER
, inst
);
14700 /* The U bit (rounding) comes from bit mask. */
14701 neon_three_same (neon_quad (rs
), 0, et
.size
);
14706 do_neon_fcmp_absolute (void)
14708 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14709 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14710 /* Size field comes from bit mask. */
14711 neon_three_same (neon_quad (rs
), 1, -1);
14715 do_neon_fcmp_absolute_inv (void)
14717 neon_exchange_operands ();
14718 do_neon_fcmp_absolute ();
14722 do_neon_step (void)
14724 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14725 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14726 neon_three_same (neon_quad (rs
), 0, -1);
14730 do_neon_abs_neg (void)
14732 enum neon_shape rs
;
14733 struct neon_type_el et
;
14735 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
14738 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14741 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14742 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
14744 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14745 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14746 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14747 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14748 inst
.instruction
|= neon_quad (rs
) << 6;
14749 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14750 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14752 neon_dp_fixup (&inst
);
14758 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14759 struct neon_type_el et
= neon_check_type (2, rs
,
14760 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14761 int imm
= inst
.operands
[2].imm
;
14762 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14763 _("immediate out of range for insert"));
14764 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14770 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14771 struct neon_type_el et
= neon_check_type (2, rs
,
14772 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14773 int imm
= inst
.operands
[2].imm
;
14774 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14775 _("immediate out of range for insert"));
14776 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
14780 do_neon_qshlu_imm (void)
14782 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14783 struct neon_type_el et
= neon_check_type (2, rs
,
14784 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
14785 int imm
= inst
.operands
[2].imm
;
14786 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14787 _("immediate out of range for shift"));
14788 /* Only encodes the 'U present' variant of the instruction.
14789 In this case, signed types have OP (bit 8) set to 0.
14790 Unsigned types have OP set to 1. */
14791 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
14792 /* The rest of the bits are the same as other immediate shifts. */
14793 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14797 do_neon_qmovn (void)
14799 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14800 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14801 /* Saturating move where operands can be signed or unsigned, and the
14802 destination has the same signedness. */
14803 NEON_ENCODE (INTEGER
, inst
);
14804 if (et
.type
== NT_unsigned
)
14805 inst
.instruction
|= 0xc0;
14807 inst
.instruction
|= 0x80;
14808 neon_two_same (0, 1, et
.size
/ 2);
14812 do_neon_qmovun (void)
14814 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14815 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14816 /* Saturating move with unsigned results. Operands must be signed. */
14817 NEON_ENCODE (INTEGER
, inst
);
14818 neon_two_same (0, 1, et
.size
/ 2);
14822 do_neon_rshift_sat_narrow (void)
14824 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14825 or unsigned. If operands are unsigned, results must also be unsigned. */
14826 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14827 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14828 int imm
= inst
.operands
[2].imm
;
14829 /* This gets the bounds check, size encoding and immediate bits calculation
14833 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14834 VQMOVN.I<size> <Dd>, <Qm>. */
14837 inst
.operands
[2].present
= 0;
14838 inst
.instruction
= N_MNEM_vqmovn
;
14843 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14844 _("immediate out of range"));
14845 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
14849 do_neon_rshift_sat_narrow_u (void)
14851 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14852 or unsigned. If operands are unsigned, results must also be unsigned. */
14853 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14854 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14855 int imm
= inst
.operands
[2].imm
;
14856 /* This gets the bounds check, size encoding and immediate bits calculation
14860 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14861 VQMOVUN.I<size> <Dd>, <Qm>. */
14864 inst
.operands
[2].present
= 0;
14865 inst
.instruction
= N_MNEM_vqmovun
;
14870 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14871 _("immediate out of range"));
14872 /* FIXME: The manual is kind of unclear about what value U should have in
14873 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14875 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
14879 do_neon_movn (void)
14881 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14882 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14883 NEON_ENCODE (INTEGER
, inst
);
14884 neon_two_same (0, 1, et
.size
/ 2);
14888 do_neon_rshift_narrow (void)
14890 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14891 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14892 int imm
= inst
.operands
[2].imm
;
14893 /* This gets the bounds check, size encoding and immediate bits calculation
14897 /* If immediate is zero then we are a pseudo-instruction for
14898 VMOVN.I<size> <Dd>, <Qm> */
14901 inst
.operands
[2].present
= 0;
14902 inst
.instruction
= N_MNEM_vmovn
;
14907 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14908 _("immediate out of range for narrowing operation"));
14909 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
14913 do_neon_shll (void)
14915 /* FIXME: Type checking when lengthening. */
14916 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
14917 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
14918 unsigned imm
= inst
.operands
[2].imm
;
14920 if (imm
== et
.size
)
14922 /* Maximum shift variant. */
14923 NEON_ENCODE (INTEGER
, inst
);
14924 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14925 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14926 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14927 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14928 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14930 neon_dp_fixup (&inst
);
14934 /* A more-specific type check for non-max versions. */
14935 et
= neon_check_type (2, NS_QDI
,
14936 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14937 NEON_ENCODE (IMMED
, inst
);
14938 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
14942 /* Check the various types for the VCVT instruction, and return which version
14943 the current instruction is. */
14945 #define CVT_FLAVOUR_VAR \
14946 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
14947 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
14948 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
14949 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
14950 /* Half-precision conversions. */ \
14951 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
14952 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
14953 /* VFP instructions. */ \
14954 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
14955 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
14956 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
14957 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
14958 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
14959 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
14960 /* VFP instructions with bitshift. */ \
14961 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
14962 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
14963 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
14964 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
14965 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
14966 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
14967 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
14968 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
14970 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
14971 neon_cvt_flavour_##C,
14973 /* The different types of conversions we can do. */
14974 enum neon_cvt_flavour
14977 neon_cvt_flavour_invalid
,
14978 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
14983 static enum neon_cvt_flavour
14984 get_neon_cvt_flavour (enum neon_shape rs
)
14986 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
14987 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
14988 if (et.type != NT_invtype) \
14990 inst.error = NULL; \
14991 return (neon_cvt_flavour_##C); \
14994 struct neon_type_el et
;
14995 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
14996 || rs
== NS_FF
) ? N_VFP
: 0;
14997 /* The instruction versions which take an immediate take one register
14998 argument, which is extended to the width of the full register. Thus the
14999 "source" and "destination" registers must have the same width. Hack that
15000 here by making the size equal to the key (wider, in this case) operand. */
15001 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15005 return neon_cvt_flavour_invalid
;
15020 /* Neon-syntax VFP conversions. */
15023 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15025 const char *opname
= 0;
15027 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
15029 /* Conversions with immediate bitshift. */
15030 const char *enc
[] =
15032 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15038 if (flavour
< (int) ARRAY_SIZE (enc
))
15040 opname
= enc
[flavour
];
15041 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15042 _("operands 0 and 1 must be the same register"));
15043 inst
.operands
[1] = inst
.operands
[2];
15044 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15049 /* Conversions without bitshift. */
15050 const char *enc
[] =
15052 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15058 if (flavour
< (int) ARRAY_SIZE (enc
))
15059 opname
= enc
[flavour
];
15063 do_vfp_nsyn_opcode (opname
);
15067 do_vfp_nsyn_cvtz (void)
15069 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
15070 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15071 const char *enc
[] =
15073 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15079 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15080 do_vfp_nsyn_opcode (enc
[flavour
]);
15084 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15085 enum neon_cvt_mode mode
)
15090 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15091 D register operands. */
15092 if (flavour
== neon_cvt_flavour_s32_f64
15093 || flavour
== neon_cvt_flavour_u32_f64
)
15094 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15097 set_it_insn_type (OUTSIDE_IT_INSN
);
15101 case neon_cvt_flavour_s32_f64
:
15105 case neon_cvt_flavour_s32_f32
:
15109 case neon_cvt_flavour_u32_f64
:
15113 case neon_cvt_flavour_u32_f32
:
15118 first_error (_("invalid instruction shape"));
15124 case neon_cvt_mode_a
: rm
= 0; break;
15125 case neon_cvt_mode_n
: rm
= 1; break;
15126 case neon_cvt_mode_p
: rm
= 2; break;
15127 case neon_cvt_mode_m
: rm
= 3; break;
15128 default: first_error (_("invalid rounding mode")); return;
15131 NEON_ENCODE (FPV8
, inst
);
15132 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15133 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15134 inst
.instruction
|= sz
<< 8;
15135 inst
.instruction
|= op
<< 7;
15136 inst
.instruction
|= rm
<< 16;
15137 inst
.instruction
|= 0xf0000000;
15138 inst
.is_neon
= TRUE
;
15142 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15144 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15145 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
15146 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15148 /* PR11109: Handle round-to-zero for VCVT conversions. */
15149 if (mode
== neon_cvt_mode_z
15150 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15151 && (flavour
== neon_cvt_flavour_s32_f32
15152 || flavour
== neon_cvt_flavour_u32_f32
15153 || flavour
== neon_cvt_flavour_s32_f64
15154 || flavour
== neon_cvt_flavour_u32_f64
)
15155 && (rs
== NS_FD
|| rs
== NS_FF
))
15157 do_vfp_nsyn_cvtz ();
15161 /* VFP rather than Neon conversions. */
15162 if (flavour
>= neon_cvt_flavour_first_fp
)
15164 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15165 do_vfp_nsyn_cvt (rs
, flavour
);
15167 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15178 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
15180 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15183 /* Fixed-point conversion with #0 immediate is encoded as an
15184 integer conversion. */
15185 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15187 immbits
= 32 - inst
.operands
[2].imm
;
15188 NEON_ENCODE (IMMED
, inst
);
15189 if (flavour
!= neon_cvt_flavour_invalid
)
15190 inst
.instruction
|= enctab
[flavour
];
15191 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15192 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15193 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15194 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15195 inst
.instruction
|= neon_quad (rs
) << 6;
15196 inst
.instruction
|= 1 << 21;
15197 inst
.instruction
|= immbits
<< 16;
15199 neon_dp_fixup (&inst
);
15205 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15207 NEON_ENCODE (FLOAT
, inst
);
15208 set_it_insn_type (OUTSIDE_IT_INSN
);
15210 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15213 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15214 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15215 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15216 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15217 inst
.instruction
|= neon_quad (rs
) << 6;
15218 inst
.instruction
|= (flavour
== neon_cvt_flavour_u32_f32
) << 7;
15219 inst
.instruction
|= mode
<< 8;
15221 inst
.instruction
|= 0xfc000000;
15223 inst
.instruction
|= 0xf0000000;
15229 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
15231 NEON_ENCODE (INTEGER
, inst
);
15233 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15236 if (flavour
!= neon_cvt_flavour_invalid
)
15237 inst
.instruction
|= enctab
[flavour
];
15239 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15240 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15241 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15242 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15243 inst
.instruction
|= neon_quad (rs
) << 6;
15244 inst
.instruction
|= 2 << 18;
15246 neon_dp_fixup (&inst
);
15251 /* Half-precision conversions for Advanced SIMD -- neon. */
15256 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15258 as_bad (_("operand size must match register width"));
15263 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15265 as_bad (_("operand size must match register width"));
15270 inst
.instruction
= 0x3b60600;
15272 inst
.instruction
= 0x3b60700;
15274 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15275 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15276 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15277 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15278 neon_dp_fixup (&inst
);
15282 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15283 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15284 do_vfp_nsyn_cvt (rs
, flavour
);
15286 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15291 do_neon_cvtr (void)
15293 do_neon_cvt_1 (neon_cvt_mode_x
);
15299 do_neon_cvt_1 (neon_cvt_mode_z
);
15303 do_neon_cvta (void)
15305 do_neon_cvt_1 (neon_cvt_mode_a
);
15309 do_neon_cvtn (void)
15311 do_neon_cvt_1 (neon_cvt_mode_n
);
15315 do_neon_cvtp (void)
15317 do_neon_cvt_1 (neon_cvt_mode_p
);
15321 do_neon_cvtm (void)
15323 do_neon_cvt_1 (neon_cvt_mode_m
);
15327 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15330 mark_feature_used (&fpu_vfp_ext_armv8
);
15332 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15333 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15334 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15335 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15336 inst
.instruction
|= to
? 0x10000 : 0;
15337 inst
.instruction
|= t
? 0x80 : 0;
15338 inst
.instruction
|= is_double
? 0x100 : 0;
15339 do_vfp_cond_or_thumb ();
15343 do_neon_cvttb_1 (bfd_boolean t
)
15345 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_DF
, NS_NULL
);
15349 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15352 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15354 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15357 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15359 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15361 /* The VCVTB and VCVTT instructions with D-register operands
15362 don't work for SP only targets. */
15363 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15367 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15369 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15371 /* The VCVTB and VCVTT instructions with D-register operands
15372 don't work for SP only targets. */
15373 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15377 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15384 do_neon_cvtb (void)
15386 do_neon_cvttb_1 (FALSE
);
15391 do_neon_cvtt (void)
15393 do_neon_cvttb_1 (TRUE
);
15397 neon_move_immediate (void)
15399 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15400 struct neon_type_el et
= neon_check_type (2, rs
,
15401 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15402 unsigned immlo
, immhi
= 0, immbits
;
15403 int op
, cmode
, float_p
;
15405 constraint (et
.type
== NT_invtype
,
15406 _("operand size must be specified for immediate VMOV"));
15408 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15409 op
= (inst
.instruction
& (1 << 5)) != 0;
15411 immlo
= inst
.operands
[1].imm
;
15412 if (inst
.operands
[1].regisimm
)
15413 immhi
= inst
.operands
[1].reg
;
15415 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15416 _("immediate has bits set outside the operand size"));
15418 float_p
= inst
.operands
[1].immisfloat
;
15420 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15421 et
.size
, et
.type
)) == FAIL
)
15423 /* Invert relevant bits only. */
15424 neon_invert_size (&immlo
, &immhi
, et
.size
);
15425 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15426 with one or the other; those cases are caught by
15427 neon_cmode_for_move_imm. */
15429 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15430 &op
, et
.size
, et
.type
)) == FAIL
)
15432 first_error (_("immediate out of range"));
15437 inst
.instruction
&= ~(1 << 5);
15438 inst
.instruction
|= op
<< 5;
15440 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15441 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15442 inst
.instruction
|= neon_quad (rs
) << 6;
15443 inst
.instruction
|= cmode
<< 8;
15445 neon_write_immbits (immbits
);
15451 if (inst
.operands
[1].isreg
)
15453 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15455 NEON_ENCODE (INTEGER
, inst
);
15456 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15457 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15458 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15459 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15460 inst
.instruction
|= neon_quad (rs
) << 6;
15464 NEON_ENCODE (IMMED
, inst
);
15465 neon_move_immediate ();
15468 neon_dp_fixup (&inst
);
15471 /* Encode instructions of form:
15473 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15474 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15477 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15479 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15480 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15481 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15482 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15483 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15484 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15485 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15486 inst
.instruction
|= neon_logbits (size
) << 20;
15488 neon_dp_fixup (&inst
);
15492 do_neon_dyadic_long (void)
15494 /* FIXME: Type checking for lengthening op. */
15495 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15496 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15497 neon_mixed_length (et
, et
.size
);
15501 do_neon_abal (void)
15503 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15504 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15505 neon_mixed_length (et
, et
.size
);
15509 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
15511 if (inst
.operands
[2].isscalar
)
15513 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
15514 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
15515 NEON_ENCODE (SCALAR
, inst
);
15516 neon_mul_mac (et
, et
.type
== NT_unsigned
);
15520 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15521 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
15522 NEON_ENCODE (INTEGER
, inst
);
15523 neon_mixed_length (et
, et
.size
);
15528 do_neon_mac_maybe_scalar_long (void)
15530 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
15534 do_neon_dyadic_wide (void)
15536 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
15537 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15538 neon_mixed_length (et
, et
.size
);
15542 do_neon_dyadic_narrow (void)
15544 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15545 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
15546 /* Operand sign is unimportant, and the U bit is part of the opcode,
15547 so force the operand type to integer. */
15548 et
.type
= NT_integer
;
15549 neon_mixed_length (et
, et
.size
/ 2);
15553 do_neon_mul_sat_scalar_long (void)
15555 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
15559 do_neon_vmull (void)
15561 if (inst
.operands
[2].isscalar
)
15562 do_neon_mac_maybe_scalar_long ();
15565 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15566 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
15568 if (et
.type
== NT_poly
)
15569 NEON_ENCODE (POLY
, inst
);
15571 NEON_ENCODE (INTEGER
, inst
);
15573 /* For polynomial encoding the U bit must be zero, and the size must
15574 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15575 obviously, as 0b10). */
15578 /* Check we're on the correct architecture. */
15579 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
15581 _("Instruction form not available on this architecture.");
15586 neon_mixed_length (et
, et
.size
);
15593 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
15594 struct neon_type_el et
= neon_check_type (3, rs
,
15595 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15596 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
15598 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
15599 _("shift out of range"));
15600 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15601 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15602 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15603 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15604 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15605 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15606 inst
.instruction
|= neon_quad (rs
) << 6;
15607 inst
.instruction
|= imm
<< 8;
15609 neon_dp_fixup (&inst
);
15615 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15616 struct neon_type_el et
= neon_check_type (2, rs
,
15617 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15618 unsigned op
= (inst
.instruction
>> 7) & 3;
15619 /* N (width of reversed regions) is encoded as part of the bitmask. We
15620 extract it here to check the elements to be reversed are smaller.
15621 Otherwise we'd get a reserved instruction. */
15622 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
15623 gas_assert (elsize
!= 0);
15624 constraint (et
.size
>= elsize
,
15625 _("elements must be smaller than reversal region"));
15626 neon_two_same (neon_quad (rs
), 1, et
.size
);
15632 if (inst
.operands
[1].isscalar
)
15634 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
15635 struct neon_type_el et
= neon_check_type (2, rs
,
15636 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15637 unsigned sizebits
= et
.size
>> 3;
15638 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15639 int logsize
= neon_logbits (et
.size
);
15640 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
15642 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
15645 NEON_ENCODE (SCALAR
, inst
);
15646 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15647 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15648 inst
.instruction
|= LOW4 (dm
);
15649 inst
.instruction
|= HI1 (dm
) << 5;
15650 inst
.instruction
|= neon_quad (rs
) << 6;
15651 inst
.instruction
|= x
<< 17;
15652 inst
.instruction
|= sizebits
<< 16;
15654 neon_dp_fixup (&inst
);
15658 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
15659 struct neon_type_el et
= neon_check_type (2, rs
,
15660 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15661 /* Duplicate ARM register to lanes of vector. */
15662 NEON_ENCODE (ARMREG
, inst
);
15665 case 8: inst
.instruction
|= 0x400000; break;
15666 case 16: inst
.instruction
|= 0x000020; break;
15667 case 32: inst
.instruction
|= 0x000000; break;
15670 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15671 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
15672 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
15673 inst
.instruction
|= neon_quad (rs
) << 21;
15674 /* The encoding for this instruction is identical for the ARM and Thumb
15675 variants, except for the condition field. */
15676 do_vfp_cond_or_thumb ();
15680 /* VMOV has particularly many variations. It can be one of:
15681 0. VMOV<c><q> <Qd>, <Qm>
15682 1. VMOV<c><q> <Dd>, <Dm>
15683 (Register operations, which are VORR with Rm = Rn.)
15684 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15685 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15687 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15688 (ARM register to scalar.)
15689 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15690 (Two ARM registers to vector.)
15691 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15692 (Scalar to ARM register.)
15693 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15694 (Vector to two ARM registers.)
15695 8. VMOV.F32 <Sd>, <Sm>
15696 9. VMOV.F64 <Dd>, <Dm>
15697 (VFP register moves.)
15698 10. VMOV.F32 <Sd>, #imm
15699 11. VMOV.F64 <Dd>, #imm
15700 (VFP float immediate load.)
15701 12. VMOV <Rd>, <Sm>
15702 (VFP single to ARM reg.)
15703 13. VMOV <Sd>, <Rm>
15704 (ARM reg to VFP single.)
15705 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15706 (Two ARM regs to two VFP singles.)
15707 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15708 (Two VFP singles to two ARM regs.)
15710 These cases can be disambiguated using neon_select_shape, except cases 1/9
15711 and 3/11 which depend on the operand type too.
15713 All the encoded bits are hardcoded by this function.
15715 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15716 Cases 5, 7 may be used with VFPv2 and above.
15718 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15719 can specify a type where it doesn't make sense to, and is ignored). */
15724 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
15725 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
15727 struct neon_type_el et
;
15728 const char *ldconst
= 0;
15732 case NS_DD
: /* case 1/9. */
15733 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15734 /* It is not an error here if no type is given. */
15736 if (et
.type
== NT_float
&& et
.size
== 64)
15738 do_vfp_nsyn_opcode ("fcpyd");
15741 /* fall through. */
15743 case NS_QQ
: /* case 0/1. */
15745 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15747 /* The architecture manual I have doesn't explicitly state which
15748 value the U bit should have for register->register moves, but
15749 the equivalent VORR instruction has U = 0, so do that. */
15750 inst
.instruction
= 0x0200110;
15751 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15752 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15753 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15754 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15755 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15756 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15757 inst
.instruction
|= neon_quad (rs
) << 6;
15759 neon_dp_fixup (&inst
);
15763 case NS_DI
: /* case 3/11. */
15764 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15766 if (et
.type
== NT_float
&& et
.size
== 64)
15768 /* case 11 (fconstd). */
15769 ldconst
= "fconstd";
15770 goto encode_fconstd
;
15772 /* fall through. */
15774 case NS_QI
: /* case 2/3. */
15775 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15777 inst
.instruction
= 0x0800010;
15778 neon_move_immediate ();
15779 neon_dp_fixup (&inst
);
15782 case NS_SR
: /* case 4. */
15784 unsigned bcdebits
= 0;
15786 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
15787 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
15789 /* .<size> is optional here, defaulting to .32. */
15790 if (inst
.vectype
.elems
== 0
15791 && inst
.operands
[0].vectype
.type
== NT_invtype
15792 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15794 inst
.vectype
.el
[0].type
= NT_untyped
;
15795 inst
.vectype
.el
[0].size
= 32;
15796 inst
.vectype
.elems
= 1;
15799 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15800 logsize
= neon_logbits (et
.size
);
15802 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15804 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15805 && et
.size
!= 32, _(BAD_FPU
));
15806 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15807 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15811 case 8: bcdebits
= 0x8; break;
15812 case 16: bcdebits
= 0x1; break;
15813 case 32: bcdebits
= 0x0; break;
15817 bcdebits
|= x
<< logsize
;
15819 inst
.instruction
= 0xe000b10;
15820 do_vfp_cond_or_thumb ();
15821 inst
.instruction
|= LOW4 (dn
) << 16;
15822 inst
.instruction
|= HI1 (dn
) << 7;
15823 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15824 inst
.instruction
|= (bcdebits
& 3) << 5;
15825 inst
.instruction
|= (bcdebits
>> 2) << 21;
15829 case NS_DRR
: /* case 5 (fmdrr). */
15830 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15833 inst
.instruction
= 0xc400b10;
15834 do_vfp_cond_or_thumb ();
15835 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
15836 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
15837 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15838 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
15841 case NS_RS
: /* case 6. */
15844 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15845 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
15846 unsigned abcdebits
= 0;
15848 /* .<dt> is optional here, defaulting to .32. */
15849 if (inst
.vectype
.elems
== 0
15850 && inst
.operands
[0].vectype
.type
== NT_invtype
15851 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15853 inst
.vectype
.el
[0].type
= NT_untyped
;
15854 inst
.vectype
.el
[0].size
= 32;
15855 inst
.vectype
.elems
= 1;
15858 et
= neon_check_type (2, NS_NULL
,
15859 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
15860 logsize
= neon_logbits (et
.size
);
15862 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15864 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15865 && et
.size
!= 32, _(BAD_FPU
));
15866 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15867 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15871 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
15872 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
15873 case 32: abcdebits
= 0x00; break;
15877 abcdebits
|= x
<< logsize
;
15878 inst
.instruction
= 0xe100b10;
15879 do_vfp_cond_or_thumb ();
15880 inst
.instruction
|= LOW4 (dn
) << 16;
15881 inst
.instruction
|= HI1 (dn
) << 7;
15882 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15883 inst
.instruction
|= (abcdebits
& 3) << 5;
15884 inst
.instruction
|= (abcdebits
>> 2) << 21;
15888 case NS_RRD
: /* case 7 (fmrrd). */
15889 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15892 inst
.instruction
= 0xc500b10;
15893 do_vfp_cond_or_thumb ();
15894 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15895 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15896 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15897 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15900 case NS_FF
: /* case 8 (fcpys). */
15901 do_vfp_nsyn_opcode ("fcpys");
15904 case NS_FI
: /* case 10 (fconsts). */
15905 ldconst
= "fconsts";
15907 if (is_quarter_float (inst
.operands
[1].imm
))
15909 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
15910 do_vfp_nsyn_opcode (ldconst
);
15913 first_error (_("immediate out of range"));
15916 case NS_RF
: /* case 12 (fmrs). */
15917 do_vfp_nsyn_opcode ("fmrs");
15920 case NS_FR
: /* case 13 (fmsr). */
15921 do_vfp_nsyn_opcode ("fmsr");
15924 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15925 (one of which is a list), but we have parsed four. Do some fiddling to
15926 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15928 case NS_RRFF
: /* case 14 (fmrrs). */
15929 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
15930 _("VFP registers must be adjacent"));
15931 inst
.operands
[2].imm
= 2;
15932 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
15933 do_vfp_nsyn_opcode ("fmrrs");
15936 case NS_FFRR
: /* case 15 (fmsrr). */
15937 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
15938 _("VFP registers must be adjacent"));
15939 inst
.operands
[1] = inst
.operands
[2];
15940 inst
.operands
[2] = inst
.operands
[3];
15941 inst
.operands
[0].imm
= 2;
15942 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
15943 do_vfp_nsyn_opcode ("fmsrr");
15947 /* neon_select_shape has determined that the instruction
15948 shape is wrong and has already set the error message. */
15957 do_neon_rshift_round_imm (void)
15959 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15960 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
15961 int imm
= inst
.operands
[2].imm
;
15963 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15966 inst
.operands
[2].present
= 0;
15971 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15972 _("immediate out of range for shift"));
15973 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
15978 do_neon_movl (void)
15980 struct neon_type_el et
= neon_check_type (2, NS_QD
,
15981 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15982 unsigned sizebits
= et
.size
>> 3;
15983 inst
.instruction
|= sizebits
<< 19;
15984 neon_two_same (0, et
.type
== NT_unsigned
, -1);
15990 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15991 struct neon_type_el et
= neon_check_type (2, rs
,
15992 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15993 NEON_ENCODE (INTEGER
, inst
);
15994 neon_two_same (neon_quad (rs
), 1, et
.size
);
15998 do_neon_zip_uzp (void)
16000 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16001 struct neon_type_el et
= neon_check_type (2, rs
,
16002 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16003 if (rs
== NS_DD
&& et
.size
== 32)
16005 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16006 inst
.instruction
= N_MNEM_vtrn
;
16010 neon_two_same (neon_quad (rs
), 1, et
.size
);
16014 do_neon_sat_abs_neg (void)
16016 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16017 struct neon_type_el et
= neon_check_type (2, rs
,
16018 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16019 neon_two_same (neon_quad (rs
), 1, et
.size
);
16023 do_neon_pair_long (void)
16025 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16026 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16027 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16028 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16029 neon_two_same (neon_quad (rs
), 1, et
.size
);
16033 do_neon_recip_est (void)
16035 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16036 struct neon_type_el et
= neon_check_type (2, rs
,
16037 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
16038 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16039 neon_two_same (neon_quad (rs
), 1, et
.size
);
16045 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16046 struct neon_type_el et
= neon_check_type (2, rs
,
16047 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16048 neon_two_same (neon_quad (rs
), 1, et
.size
);
16054 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16055 struct neon_type_el et
= neon_check_type (2, rs
,
16056 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16057 neon_two_same (neon_quad (rs
), 1, et
.size
);
16063 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16064 struct neon_type_el et
= neon_check_type (2, rs
,
16065 N_EQK
| N_INT
, N_8
| N_KEY
);
16066 neon_two_same (neon_quad (rs
), 1, et
.size
);
16072 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16073 neon_two_same (neon_quad (rs
), 1, -1);
16077 do_neon_tbl_tbx (void)
16079 unsigned listlenbits
;
16080 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16082 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16084 first_error (_("bad list length for table lookup"));
16088 listlenbits
= inst
.operands
[1].imm
- 1;
16089 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16090 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16091 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16092 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16093 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16094 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16095 inst
.instruction
|= listlenbits
<< 8;
16097 neon_dp_fixup (&inst
);
16101 do_neon_ldm_stm (void)
16103 /* P, U and L bits are part of bitmask. */
16104 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16105 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16107 if (inst
.operands
[1].issingle
)
16109 do_vfp_nsyn_ldm_stm (is_dbmode
);
16113 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16114 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16116 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16117 _("register list must contain at least 1 and at most 16 "
16120 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16121 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16122 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16123 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16125 inst
.instruction
|= offsetbits
;
16127 do_vfp_cond_or_thumb ();
16131 do_neon_ldr_str (void)
16133 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16135 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16136 And is UNPREDICTABLE in thumb mode. */
16138 && inst
.operands
[1].reg
== REG_PC
16139 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16142 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16143 else if (warn_on_deprecated
)
16144 as_tsktsk (_("Use of PC here is deprecated"));
16147 if (inst
.operands
[0].issingle
)
16150 do_vfp_nsyn_opcode ("flds");
16152 do_vfp_nsyn_opcode ("fsts");
16157 do_vfp_nsyn_opcode ("fldd");
16159 do_vfp_nsyn_opcode ("fstd");
16163 /* "interleave" version also handles non-interleaving register VLD1/VST1
16167 do_neon_ld_st_interleave (void)
16169 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16170 N_8
| N_16
| N_32
| N_64
);
16171 unsigned alignbits
= 0;
16173 /* The bits in this table go:
16174 0: register stride of one (0) or two (1)
16175 1,2: register list length, minus one (1, 2, 3, 4).
16176 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16177 We use -1 for invalid entries. */
16178 const int typetable
[] =
16180 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16181 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16182 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16183 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16187 if (et
.type
== NT_invtype
)
16190 if (inst
.operands
[1].immisalign
)
16191 switch (inst
.operands
[1].imm
>> 8)
16193 case 64: alignbits
= 1; break;
16195 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16196 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16197 goto bad_alignment
;
16201 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16202 goto bad_alignment
;
16207 first_error (_("bad alignment"));
16211 inst
.instruction
|= alignbits
<< 4;
16212 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16214 /* Bits [4:6] of the immediate in a list specifier encode register stride
16215 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16216 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16217 up the right value for "type" in a table based on this value and the given
16218 list style, then stick it back. */
16219 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16220 | (((inst
.instruction
>> 8) & 3) << 3);
16222 typebits
= typetable
[idx
];
16224 constraint (typebits
== -1, _("bad list type for instruction"));
16225 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16226 _("bad element type for instruction"));
16228 inst
.instruction
&= ~0xf00;
16229 inst
.instruction
|= typebits
<< 8;
16232 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16233 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16234 otherwise. The variable arguments are a list of pairs of legal (size, align)
16235 values, terminated with -1. */
16238 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
16241 int result
= FAIL
, thissize
, thisalign
;
16243 if (!inst
.operands
[1].immisalign
)
16249 va_start (ap
, do_align
);
16253 thissize
= va_arg (ap
, int);
16254 if (thissize
== -1)
16256 thisalign
= va_arg (ap
, int);
16258 if (size
== thissize
&& align
== thisalign
)
16261 while (result
!= SUCCESS
);
16265 if (result
== SUCCESS
)
16268 first_error (_("unsupported alignment for instruction"));
16274 do_neon_ld_st_lane (void)
16276 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16277 int align_good
, do_align
= 0;
16278 int logsize
= neon_logbits (et
.size
);
16279 int align
= inst
.operands
[1].imm
>> 8;
16280 int n
= (inst
.instruction
>> 8) & 3;
16281 int max_el
= 64 / et
.size
;
16283 if (et
.type
== NT_invtype
)
16286 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16287 _("bad list length"));
16288 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16289 _("scalar index out of range"));
16290 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16292 _("stride of 2 unavailable when element size is 8"));
16296 case 0: /* VLD1 / VST1. */
16297 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
16299 if (align_good
== FAIL
)
16303 unsigned alignbits
= 0;
16306 case 16: alignbits
= 0x1; break;
16307 case 32: alignbits
= 0x3; break;
16310 inst
.instruction
|= alignbits
<< 4;
16314 case 1: /* VLD2 / VST2. */
16315 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
16317 if (align_good
== FAIL
)
16320 inst
.instruction
|= 1 << 4;
16323 case 2: /* VLD3 / VST3. */
16324 constraint (inst
.operands
[1].immisalign
,
16325 _("can't use alignment with this instruction"));
16328 case 3: /* VLD4 / VST4. */
16329 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16330 16, 64, 32, 64, 32, 128, -1);
16331 if (align_good
== FAIL
)
16335 unsigned alignbits
= 0;
16338 case 8: alignbits
= 0x1; break;
16339 case 16: alignbits
= 0x1; break;
16340 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16343 inst
.instruction
|= alignbits
<< 4;
16350 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16351 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16352 inst
.instruction
|= 1 << (4 + logsize
);
16354 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16355 inst
.instruction
|= logsize
<< 10;
16358 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16361 do_neon_ld_dup (void)
16363 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16364 int align_good
, do_align
= 0;
16366 if (et
.type
== NT_invtype
)
16369 switch ((inst
.instruction
>> 8) & 3)
16371 case 0: /* VLD1. */
16372 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16373 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16374 &do_align
, 16, 16, 32, 32, -1);
16375 if (align_good
== FAIL
)
16377 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16380 case 2: inst
.instruction
|= 1 << 5; break;
16381 default: first_error (_("bad list length")); return;
16383 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16386 case 1: /* VLD2. */
16387 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16388 &do_align
, 8, 16, 16, 32, 32, 64, -1);
16389 if (align_good
== FAIL
)
16391 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16392 _("bad list length"));
16393 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16394 inst
.instruction
|= 1 << 5;
16395 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16398 case 2: /* VLD3. */
16399 constraint (inst
.operands
[1].immisalign
,
16400 _("can't use alignment with this instruction"));
16401 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16402 _("bad list length"));
16403 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16404 inst
.instruction
|= 1 << 5;
16405 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16408 case 3: /* VLD4. */
16410 int align
= inst
.operands
[1].imm
>> 8;
16411 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16412 16, 64, 32, 64, 32, 128, -1);
16413 if (align_good
== FAIL
)
16415 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16416 _("bad list length"));
16417 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16418 inst
.instruction
|= 1 << 5;
16419 if (et
.size
== 32 && align
== 128)
16420 inst
.instruction
|= 0x3 << 6;
16422 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16429 inst
.instruction
|= do_align
<< 4;
16432 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16433 apart from bits [11:4]. */
16436 do_neon_ldx_stx (void)
16438 if (inst
.operands
[1].isreg
)
16439 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16441 switch (NEON_LANE (inst
.operands
[0].imm
))
16443 case NEON_INTERLEAVE_LANES
:
16444 NEON_ENCODE (INTERLV
, inst
);
16445 do_neon_ld_st_interleave ();
16448 case NEON_ALL_LANES
:
16449 NEON_ENCODE (DUP
, inst
);
16450 if (inst
.instruction
== N_INV
)
16452 first_error ("only loads support such operands");
16459 NEON_ENCODE (LANE
, inst
);
16460 do_neon_ld_st_lane ();
16463 /* L bit comes from bit mask. */
16464 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16465 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16466 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16468 if (inst
.operands
[1].postind
)
16470 int postreg
= inst
.operands
[1].imm
& 0xf;
16471 constraint (!inst
.operands
[1].immisreg
,
16472 _("post-index must be a register"));
16473 constraint (postreg
== 0xd || postreg
== 0xf,
16474 _("bad register for post-index"));
16475 inst
.instruction
|= postreg
;
16479 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16480 constraint (inst
.reloc
.exp
.X_op
!= O_constant
16481 || inst
.reloc
.exp
.X_add_number
!= 0,
16484 if (inst
.operands
[1].writeback
)
16486 inst
.instruction
|= 0xd;
16489 inst
.instruction
|= 0xf;
16493 inst
.instruction
|= 0xf9000000;
16495 inst
.instruction
|= 0xf4000000;
16500 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
16502 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16503 D register operands. */
16504 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16505 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16508 NEON_ENCODE (FPV8
, inst
);
16511 do_vfp_sp_dyadic ();
16513 do_vfp_dp_rd_rn_rm ();
16516 inst
.instruction
|= 0x100;
16518 inst
.instruction
|= 0xf0000000;
16524 set_it_insn_type (OUTSIDE_IT_INSN
);
16526 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
16527 first_error (_("invalid instruction shape"));
16533 set_it_insn_type (OUTSIDE_IT_INSN
);
16535 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
16538 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16541 neon_dyadic_misc (NT_untyped
, N_F32
, 0);
16545 do_vrint_1 (enum neon_cvt_mode mode
)
16547 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
16548 struct neon_type_el et
;
16553 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16554 D register operands. */
16555 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16556 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16559 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
16560 if (et
.type
!= NT_invtype
)
16562 /* VFP encodings. */
16563 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
16564 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
16565 set_it_insn_type (OUTSIDE_IT_INSN
);
16567 NEON_ENCODE (FPV8
, inst
);
16569 do_vfp_sp_monadic ();
16571 do_vfp_dp_rd_rm ();
16575 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
16576 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
16577 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
16578 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
16579 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
16580 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
16581 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
16585 inst
.instruction
|= (rs
== NS_DD
) << 8;
16586 do_vfp_cond_or_thumb ();
16590 /* Neon encodings (or something broken...). */
16592 et
= neon_check_type (2, rs
, N_EQK
, N_F32
| N_KEY
);
16594 if (et
.type
== NT_invtype
)
16597 set_it_insn_type (OUTSIDE_IT_INSN
);
16598 NEON_ENCODE (FLOAT
, inst
);
16600 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16603 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16604 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16605 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16606 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16607 inst
.instruction
|= neon_quad (rs
) << 6;
16610 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
16611 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
16612 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
16613 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
16614 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
16615 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
16616 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
16621 inst
.instruction
|= 0xfc000000;
16623 inst
.instruction
|= 0xf0000000;
16630 do_vrint_1 (neon_cvt_mode_x
);
16636 do_vrint_1 (neon_cvt_mode_z
);
16642 do_vrint_1 (neon_cvt_mode_r
);
16648 do_vrint_1 (neon_cvt_mode_a
);
16654 do_vrint_1 (neon_cvt_mode_n
);
16660 do_vrint_1 (neon_cvt_mode_p
);
16666 do_vrint_1 (neon_cvt_mode_m
);
16669 /* Crypto v1 instructions. */
16671 do_crypto_2op_1 (unsigned elttype
, int op
)
16673 set_it_insn_type (OUTSIDE_IT_INSN
);
16675 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
16681 NEON_ENCODE (INTEGER
, inst
);
16682 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16683 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16684 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16685 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16687 inst
.instruction
|= op
<< 6;
16690 inst
.instruction
|= 0xfc000000;
16692 inst
.instruction
|= 0xf0000000;
16696 do_crypto_3op_1 (int u
, int op
)
16698 set_it_insn_type (OUTSIDE_IT_INSN
);
16700 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
16701 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
16706 NEON_ENCODE (INTEGER
, inst
);
16707 neon_three_same (1, u
, 8 << op
);
16713 do_crypto_2op_1 (N_8
, 0);
16719 do_crypto_2op_1 (N_8
, 1);
16725 do_crypto_2op_1 (N_8
, 2);
16731 do_crypto_2op_1 (N_8
, 3);
16737 do_crypto_3op_1 (0, 0);
16743 do_crypto_3op_1 (0, 1);
16749 do_crypto_3op_1 (0, 2);
16755 do_crypto_3op_1 (0, 3);
16761 do_crypto_3op_1 (1, 0);
16767 do_crypto_3op_1 (1, 1);
16771 do_sha256su1 (void)
16773 do_crypto_3op_1 (1, 2);
16779 do_crypto_2op_1 (N_32
, -1);
16785 do_crypto_2op_1 (N_32
, 0);
16789 do_sha256su0 (void)
16791 do_crypto_2op_1 (N_32
, 1);
16795 do_crc32_1 (unsigned int poly
, unsigned int sz
)
16797 unsigned int Rd
= inst
.operands
[0].reg
;
16798 unsigned int Rn
= inst
.operands
[1].reg
;
16799 unsigned int Rm
= inst
.operands
[2].reg
;
16801 set_it_insn_type (OUTSIDE_IT_INSN
);
16802 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
16803 inst
.instruction
|= LOW4 (Rn
) << 16;
16804 inst
.instruction
|= LOW4 (Rm
);
16805 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
16806 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
16808 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
16809 as_warn (UNPRED_REG ("r15"));
16810 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
16811 as_warn (UNPRED_REG ("r13"));
16851 /* Overall per-instruction processing. */
16853 /* We need to be able to fix up arbitrary expressions in some statements.
16854 This is so that we can handle symbols that are an arbitrary distance from
16855 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16856 which returns part of an address in a form which will be valid for
16857 a data instruction. We do this by pushing the expression into a symbol
16858 in the expr_section, and creating a fix for that. */
16861 fix_new_arm (fragS
* frag
,
16875 /* Create an absolute valued symbol, so we have something to
16876 refer to in the object file. Unfortunately for us, gas's
16877 generic expression parsing will already have folded out
16878 any use of .set foo/.type foo %function that may have
16879 been used to set type information of the target location,
16880 that's being specified symbolically. We have to presume
16881 the user knows what they are doing. */
16885 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
16887 symbol
= symbol_find_or_make (name
);
16888 S_SET_SEGMENT (symbol
, absolute_section
);
16889 symbol_set_frag (symbol
, &zero_address_frag
);
16890 S_SET_VALUE (symbol
, exp
->X_add_number
);
16891 exp
->X_op
= O_symbol
;
16892 exp
->X_add_symbol
= symbol
;
16893 exp
->X_add_number
= 0;
16899 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
16900 (enum bfd_reloc_code_real
) reloc
);
16904 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
16905 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
16909 /* Mark whether the fix is to a THUMB instruction, or an ARM
16911 new_fix
->tc_fix_data
= thumb_mode
;
16914 /* Create a frg for an instruction requiring relaxation. */
16916 output_relax_insn (void)
16922 /* The size of the instruction is unknown, so tie the debug info to the
16923 start of the instruction. */
16924 dwarf2_emit_insn (0);
16926 switch (inst
.reloc
.exp
.X_op
)
16929 sym
= inst
.reloc
.exp
.X_add_symbol
;
16930 offset
= inst
.reloc
.exp
.X_add_number
;
16934 offset
= inst
.reloc
.exp
.X_add_number
;
16937 sym
= make_expr_symbol (&inst
.reloc
.exp
);
16941 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
16942 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
16943 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
16946 /* Write a 32-bit thumb instruction to buf. */
16948 put_thumb32_insn (char * buf
, unsigned long insn
)
16950 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
16951 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
16955 output_inst (const char * str
)
16961 as_bad ("%s -- `%s'", inst
.error
, str
);
16966 output_relax_insn ();
16969 if (inst
.size
== 0)
16972 to
= frag_more (inst
.size
);
16973 /* PR 9814: Record the thumb mode into the current frag so that we know
16974 what type of NOP padding to use, if necessary. We override any previous
16975 setting so that if the mode has changed then the NOPS that we use will
16976 match the encoding of the last instruction in the frag. */
16977 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
16979 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
16981 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
16982 put_thumb32_insn (to
, inst
.instruction
);
16984 else if (inst
.size
> INSN_SIZE
)
16986 gas_assert (inst
.size
== (2 * INSN_SIZE
));
16987 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
16988 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
16991 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
16993 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
16994 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
16995 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
16998 dwarf2_emit_insn (inst
.size
);
17002 output_it_inst (int cond
, int mask
, char * to
)
17004 unsigned long instruction
= 0xbf00;
17007 instruction
|= mask
;
17008 instruction
|= cond
<< 4;
17012 to
= frag_more (2);
17014 dwarf2_emit_insn (2);
17018 md_number_to_chars (to
, instruction
, 2);
17023 /* Tag values used in struct asm_opcode's tag field. */
17026 OT_unconditional
, /* Instruction cannot be conditionalized.
17027 The ARM condition field is still 0xE. */
17028 OT_unconditionalF
, /* Instruction cannot be conditionalized
17029 and carries 0xF in its ARM condition field. */
17030 OT_csuffix
, /* Instruction takes a conditional suffix. */
17031 OT_csuffixF
, /* Some forms of the instruction take a conditional
17032 suffix, others place 0xF where the condition field
17034 OT_cinfix3
, /* Instruction takes a conditional infix,
17035 beginning at character index 3. (In
17036 unified mode, it becomes a suffix.) */
17037 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17038 tsts, cmps, cmns, and teqs. */
17039 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17040 character index 3, even in unified mode. Used for
17041 legacy instructions where suffix and infix forms
17042 may be ambiguous. */
17043 OT_csuf_or_in3
, /* Instruction takes either a conditional
17044 suffix or an infix at character index 3. */
17045 OT_odd_infix_unc
, /* This is the unconditional variant of an
17046 instruction that takes a conditional infix
17047 at an unusual position. In unified mode,
17048 this variant will accept a suffix. */
17049 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17050 are the conditional variants of instructions that
17051 take conditional infixes in unusual positions.
17052 The infix appears at character index
17053 (tag - OT_odd_infix_0). These are not accepted
17054 in unified mode. */
17057 /* Subroutine of md_assemble, responsible for looking up the primary
17058 opcode from the mnemonic the user wrote. STR points to the
17059 beginning of the mnemonic.
17061 This is not simply a hash table lookup, because of conditional
17062 variants. Most instructions have conditional variants, which are
17063 expressed with a _conditional affix_ to the mnemonic. If we were
17064 to encode each conditional variant as a literal string in the opcode
17065 table, it would have approximately 20,000 entries.
17067 Most mnemonics take this affix as a suffix, and in unified syntax,
17068 'most' is upgraded to 'all'. However, in the divided syntax, some
17069 instructions take the affix as an infix, notably the s-variants of
17070 the arithmetic instructions. Of those instructions, all but six
17071 have the infix appear after the third character of the mnemonic.
17073 Accordingly, the algorithm for looking up primary opcodes given
17076 1. Look up the identifier in the opcode table.
17077 If we find a match, go to step U.
17079 2. Look up the last two characters of the identifier in the
17080 conditions table. If we find a match, look up the first N-2
17081 characters of the identifier in the opcode table. If we
17082 find a match, go to step CE.
17084 3. Look up the fourth and fifth characters of the identifier in
17085 the conditions table. If we find a match, extract those
17086 characters from the identifier, and look up the remaining
17087 characters in the opcode table. If we find a match, go
17092 U. Examine the tag field of the opcode structure, in case this is
17093 one of the six instructions with its conditional infix in an
17094 unusual place. If it is, the tag tells us where to find the
17095 infix; look it up in the conditions table and set inst.cond
17096 accordingly. Otherwise, this is an unconditional instruction.
17097 Again set inst.cond accordingly. Return the opcode structure.
17099 CE. Examine the tag field to make sure this is an instruction that
17100 should receive a conditional suffix. If it is not, fail.
17101 Otherwise, set inst.cond from the suffix we already looked up,
17102 and return the opcode structure.
17104 CM. Examine the tag field to make sure this is an instruction that
17105 should receive a conditional infix after the third character.
17106 If it is not, fail. Otherwise, undo the edits to the current
17107 line of input and proceed as for case CE. */
17109 static const struct asm_opcode
*
17110 opcode_lookup (char **str
)
17114 const struct asm_opcode
*opcode
;
17115 const struct asm_cond
*cond
;
17118 /* Scan up to the end of the mnemonic, which must end in white space,
17119 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17120 for (base
= end
= *str
; *end
!= '\0'; end
++)
17121 if (*end
== ' ' || *end
== '.')
17127 /* Handle a possible width suffix and/or Neon type suffix. */
17132 /* The .w and .n suffixes are only valid if the unified syntax is in
17134 if (unified_syntax
&& end
[1] == 'w')
17136 else if (unified_syntax
&& end
[1] == 'n')
17141 inst
.vectype
.elems
= 0;
17143 *str
= end
+ offset
;
17145 if (end
[offset
] == '.')
17147 /* See if we have a Neon type suffix (possible in either unified or
17148 non-unified ARM syntax mode). */
17149 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17152 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17158 /* Look for unaffixed or special-case affixed mnemonic. */
17159 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17164 if (opcode
->tag
< OT_odd_infix_0
)
17166 inst
.cond
= COND_ALWAYS
;
17170 if (warn_on_deprecated
&& unified_syntax
)
17171 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17172 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17173 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17176 inst
.cond
= cond
->value
;
17180 /* Cannot have a conditional suffix on a mnemonic of less than two
17182 if (end
- base
< 3)
17185 /* Look for suffixed mnemonic. */
17187 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17188 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17190 if (opcode
&& cond
)
17193 switch (opcode
->tag
)
17195 case OT_cinfix3_legacy
:
17196 /* Ignore conditional suffixes matched on infix only mnemonics. */
17200 case OT_cinfix3_deprecated
:
17201 case OT_odd_infix_unc
:
17202 if (!unified_syntax
)
17204 /* else fall through */
17208 case OT_csuf_or_in3
:
17209 inst
.cond
= cond
->value
;
17212 case OT_unconditional
:
17213 case OT_unconditionalF
:
17215 inst
.cond
= cond
->value
;
17218 /* Delayed diagnostic. */
17219 inst
.error
= BAD_COND
;
17220 inst
.cond
= COND_ALWAYS
;
17229 /* Cannot have a usual-position infix on a mnemonic of less than
17230 six characters (five would be a suffix). */
17231 if (end
- base
< 6)
17234 /* Look for infixed mnemonic in the usual position. */
17236 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17240 memcpy (save
, affix
, 2);
17241 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17242 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17244 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17245 memcpy (affix
, save
, 2);
17248 && (opcode
->tag
== OT_cinfix3
17249 || opcode
->tag
== OT_cinfix3_deprecated
17250 || opcode
->tag
== OT_csuf_or_in3
17251 || opcode
->tag
== OT_cinfix3_legacy
))
17254 if (warn_on_deprecated
&& unified_syntax
17255 && (opcode
->tag
== OT_cinfix3
17256 || opcode
->tag
== OT_cinfix3_deprecated
))
17257 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17259 inst
.cond
= cond
->value
;
17266 /* This function generates an initial IT instruction, leaving its block
17267 virtually open for the new instructions. Eventually,
17268 the mask will be updated by now_it_add_mask () each time
17269 a new instruction needs to be included in the IT block.
17270 Finally, the block is closed with close_automatic_it_block ().
17271 The block closure can be requested either from md_assemble (),
17272 a tencode (), or due to a label hook. */
17275 new_automatic_it_block (int cond
)
17277 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17278 now_it
.mask
= 0x18;
17280 now_it
.block_length
= 1;
17281 mapping_state (MAP_THUMB
);
17282 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17283 now_it
.warn_deprecated
= FALSE
;
17284 now_it
.insn_cond
= TRUE
;
17287 /* Close an automatic IT block.
17288 See comments in new_automatic_it_block (). */
17291 close_automatic_it_block (void)
17293 now_it
.mask
= 0x10;
17294 now_it
.block_length
= 0;
17297 /* Update the mask of the current automatically-generated IT
17298 instruction. See comments in new_automatic_it_block (). */
17301 now_it_add_mask (int cond
)
17303 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17304 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17305 | ((bitvalue) << (nbit)))
17306 const int resulting_bit
= (cond
& 1);
17308 now_it
.mask
&= 0xf;
17309 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17311 (5 - now_it
.block_length
));
17312 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17314 ((5 - now_it
.block_length
) - 1) );
17315 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17318 #undef SET_BIT_VALUE
17321 /* The IT blocks handling machinery is accessed through the these functions:
17322 it_fsm_pre_encode () from md_assemble ()
17323 set_it_insn_type () optional, from the tencode functions
17324 set_it_insn_type_last () ditto
17325 in_it_block () ditto
17326 it_fsm_post_encode () from md_assemble ()
17327 force_automatic_it_block_close () from label habdling functions
17330 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17331 initializing the IT insn type with a generic initial value depending
17332 on the inst.condition.
17333 2) During the tencode function, two things may happen:
17334 a) The tencode function overrides the IT insn type by
17335 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17336 b) The tencode function queries the IT block state by
17337 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17339 Both set_it_insn_type and in_it_block run the internal FSM state
17340 handling function (handle_it_state), because: a) setting the IT insn
17341 type may incur in an invalid state (exiting the function),
17342 and b) querying the state requires the FSM to be updated.
17343 Specifically we want to avoid creating an IT block for conditional
17344 branches, so it_fsm_pre_encode is actually a guess and we can't
17345 determine whether an IT block is required until the tencode () routine
17346 has decided what type of instruction this actually it.
17347 Because of this, if set_it_insn_type and in_it_block have to be used,
17348 set_it_insn_type has to be called first.
17350 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17351 determines the insn IT type depending on the inst.cond code.
17352 When a tencode () routine encodes an instruction that can be
17353 either outside an IT block, or, in the case of being inside, has to be
17354 the last one, set_it_insn_type_last () will determine the proper
17355 IT instruction type based on the inst.cond code. Otherwise,
17356 set_it_insn_type can be called for overriding that logic or
17357 for covering other cases.
17359 Calling handle_it_state () may not transition the IT block state to
17360 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17361 still queried. Instead, if the FSM determines that the state should
17362 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17363 after the tencode () function: that's what it_fsm_post_encode () does.
17365 Since in_it_block () calls the state handling function to get an
17366 updated state, an error may occur (due to invalid insns combination).
17367 In that case, inst.error is set.
17368 Therefore, inst.error has to be checked after the execution of
17369 the tencode () routine.
17371 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17372 any pending state change (if any) that didn't take place in
17373 handle_it_state () as explained above. */
17376 it_fsm_pre_encode (void)
17378 if (inst
.cond
!= COND_ALWAYS
)
17379 inst
.it_insn_type
= INSIDE_IT_INSN
;
17381 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17383 now_it
.state_handled
= 0;
17386 /* IT state FSM handling function. */
17389 handle_it_state (void)
17391 now_it
.state_handled
= 1;
17392 now_it
.insn_cond
= FALSE
;
17394 switch (now_it
.state
)
17396 case OUTSIDE_IT_BLOCK
:
17397 switch (inst
.it_insn_type
)
17399 case OUTSIDE_IT_INSN
:
17402 case INSIDE_IT_INSN
:
17403 case INSIDE_IT_LAST_INSN
:
17404 if (thumb_mode
== 0)
17407 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17408 as_tsktsk (_("Warning: conditional outside an IT block"\
17413 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17414 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
17416 /* Automatically generate the IT instruction. */
17417 new_automatic_it_block (inst
.cond
);
17418 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17419 close_automatic_it_block ();
17423 inst
.error
= BAD_OUT_IT
;
17429 case IF_INSIDE_IT_LAST_INSN
:
17430 case NEUTRAL_IT_INSN
:
17434 now_it
.state
= MANUAL_IT_BLOCK
;
17435 now_it
.block_length
= 0;
17440 case AUTOMATIC_IT_BLOCK
:
17441 /* Three things may happen now:
17442 a) We should increment current it block size;
17443 b) We should close current it block (closing insn or 4 insns);
17444 c) We should close current it block and start a new one (due
17445 to incompatible conditions or
17446 4 insns-length block reached). */
17448 switch (inst
.it_insn_type
)
17450 case OUTSIDE_IT_INSN
:
17451 /* The closure of the block shall happen immediatelly,
17452 so any in_it_block () call reports the block as closed. */
17453 force_automatic_it_block_close ();
17456 case INSIDE_IT_INSN
:
17457 case INSIDE_IT_LAST_INSN
:
17458 case IF_INSIDE_IT_LAST_INSN
:
17459 now_it
.block_length
++;
17461 if (now_it
.block_length
> 4
17462 || !now_it_compatible (inst
.cond
))
17464 force_automatic_it_block_close ();
17465 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
17466 new_automatic_it_block (inst
.cond
);
17470 now_it
.insn_cond
= TRUE
;
17471 now_it_add_mask (inst
.cond
);
17474 if (now_it
.state
== AUTOMATIC_IT_BLOCK
17475 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
17476 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
17477 close_automatic_it_block ();
17480 case NEUTRAL_IT_INSN
:
17481 now_it
.block_length
++;
17482 now_it
.insn_cond
= TRUE
;
17484 if (now_it
.block_length
> 4)
17485 force_automatic_it_block_close ();
17487 now_it_add_mask (now_it
.cc
& 1);
17491 close_automatic_it_block ();
17492 now_it
.state
= MANUAL_IT_BLOCK
;
17497 case MANUAL_IT_BLOCK
:
17499 /* Check conditional suffixes. */
17500 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
17503 now_it
.mask
&= 0x1f;
17504 is_last
= (now_it
.mask
== 0x10);
17505 now_it
.insn_cond
= TRUE
;
17507 switch (inst
.it_insn_type
)
17509 case OUTSIDE_IT_INSN
:
17510 inst
.error
= BAD_NOT_IT
;
17513 case INSIDE_IT_INSN
:
17514 if (cond
!= inst
.cond
)
17516 inst
.error
= BAD_IT_COND
;
17521 case INSIDE_IT_LAST_INSN
:
17522 case IF_INSIDE_IT_LAST_INSN
:
17523 if (cond
!= inst
.cond
)
17525 inst
.error
= BAD_IT_COND
;
17530 inst
.error
= BAD_BRANCH
;
17535 case NEUTRAL_IT_INSN
:
17536 /* The BKPT instruction is unconditional even in an IT block. */
17540 inst
.error
= BAD_IT_IT
;
17550 struct depr_insn_mask
17552 unsigned long pattern
;
17553 unsigned long mask
;
17554 const char* description
;
17557 /* List of 16-bit instruction patterns deprecated in an IT block in
17559 static const struct depr_insn_mask depr_it_insns
[] = {
17560 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17561 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17562 { 0xa000, 0xb800, N_("ADR") },
17563 { 0x4800, 0xf800, N_("Literal loads") },
17564 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17565 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17566 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
17567 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
17568 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
17573 it_fsm_post_encode (void)
17577 if (!now_it
.state_handled
)
17578 handle_it_state ();
17580 if (now_it
.insn_cond
17581 && !now_it
.warn_deprecated
17582 && warn_on_deprecated
17583 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
17585 if (inst
.instruction
>= 0x10000)
17587 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
17588 "deprecated in ARMv8"));
17589 now_it
.warn_deprecated
= TRUE
;
17593 const struct depr_insn_mask
*p
= depr_it_insns
;
17595 while (p
->mask
!= 0)
17597 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
17599 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
17600 "of the following class are deprecated in ARMv8: "
17601 "%s"), p
->description
);
17602 now_it
.warn_deprecated
= TRUE
;
17610 if (now_it
.block_length
> 1)
17612 as_tsktsk (_("IT blocks containing more than one conditional "
17613 "instruction are deprecated in ARMv8"));
17614 now_it
.warn_deprecated
= TRUE
;
17618 is_last
= (now_it
.mask
== 0x10);
17621 now_it
.state
= OUTSIDE_IT_BLOCK
;
17627 force_automatic_it_block_close (void)
17629 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
17631 close_automatic_it_block ();
17632 now_it
.state
= OUTSIDE_IT_BLOCK
;
17640 if (!now_it
.state_handled
)
17641 handle_it_state ();
17643 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
17647 md_assemble (char *str
)
17650 const struct asm_opcode
* opcode
;
17652 /* Align the previous label if needed. */
17653 if (last_label_seen
!= NULL
)
17655 symbol_set_frag (last_label_seen
, frag_now
);
17656 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
17657 S_SET_SEGMENT (last_label_seen
, now_seg
);
17660 memset (&inst
, '\0', sizeof (inst
));
17661 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
17663 opcode
= opcode_lookup (&p
);
17666 /* It wasn't an instruction, but it might be a register alias of
17667 the form alias .req reg, or a Neon .dn/.qn directive. */
17668 if (! create_register_alias (str
, p
)
17669 && ! create_neon_reg_alias (str
, p
))
17670 as_bad (_("bad instruction `%s'"), str
);
17675 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
17676 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
17678 /* The value which unconditional instructions should have in place of the
17679 condition field. */
17680 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
17684 arm_feature_set variant
;
17686 variant
= cpu_variant
;
17687 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17688 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
17689 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
17690 /* Check that this instruction is supported for this CPU. */
17691 if (!opcode
->tvariant
17692 || (thumb_mode
== 1
17693 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
17695 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
17698 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
17699 && opcode
->tencode
!= do_t_branch
)
17701 as_bad (_("Thumb does not support conditional execution"));
17705 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
17707 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
17708 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
17709 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
17711 /* Two things are addressed here.
17712 1) Implicit require narrow instructions on Thumb-1.
17713 This avoids relaxation accidentally introducing Thumb-2
17715 2) Reject wide instructions in non Thumb-2 cores. */
17716 if (inst
.size_req
== 0)
17718 else if (inst
.size_req
== 4)
17720 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
17726 inst
.instruction
= opcode
->tvalue
;
17728 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
17730 /* Prepare the it_insn_type for those encodings that don't set
17732 it_fsm_pre_encode ();
17734 opcode
->tencode ();
17736 it_fsm_post_encode ();
17739 if (!(inst
.error
|| inst
.relax
))
17741 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
17742 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
17743 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
17745 as_bad (_("cannot honor width suffix -- `%s'"), str
);
17750 /* Something has gone badly wrong if we try to relax a fixed size
17752 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
17754 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17755 *opcode
->tvariant
);
17756 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17757 set those bits when Thumb-2 32-bit instructions are seen. ie.
17758 anything other than bl/blx and v6-M instructions.
17759 The impact of relaxable instructions will be considered later after we
17760 finish all relaxation. */
17761 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
17762 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
17763 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
17764 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17767 check_neon_suffixes
;
17771 mapping_state (MAP_THUMB
);
17774 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
17778 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17779 is_bx
= (opcode
->aencode
== do_bx
);
17781 /* Check that this instruction is supported for this CPU. */
17782 if (!(is_bx
&& fix_v4bx
)
17783 && !(opcode
->avariant
&&
17784 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
17786 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
17791 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
17795 inst
.instruction
= opcode
->avalue
;
17796 if (opcode
->tag
== OT_unconditionalF
)
17797 inst
.instruction
|= 0xF << 28;
17799 inst
.instruction
|= inst
.cond
<< 28;
17800 inst
.size
= INSN_SIZE
;
17801 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
17803 it_fsm_pre_encode ();
17804 opcode
->aencode ();
17805 it_fsm_post_encode ();
17807 /* Arm mode bx is marked as both v4T and v5 because it's still required
17808 on a hypothetical non-thumb v5 core. */
17810 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
17812 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
17813 *opcode
->avariant
);
17815 check_neon_suffixes
;
17819 mapping_state (MAP_ARM
);
17824 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17832 check_it_blocks_finished (void)
17837 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
17838 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
17839 == MANUAL_IT_BLOCK
)
17841 as_warn (_("section '%s' finished with an open IT block."),
17845 if (now_it
.state
== MANUAL_IT_BLOCK
)
17846 as_warn (_("file finished with an open IT block."));
17850 /* Various frobbings of labels and their addresses. */
17853 arm_start_line_hook (void)
17855 last_label_seen
= NULL
;
17859 arm_frob_label (symbolS
* sym
)
17861 last_label_seen
= sym
;
17863 ARM_SET_THUMB (sym
, thumb_mode
);
17865 #if defined OBJ_COFF || defined OBJ_ELF
17866 ARM_SET_INTERWORK (sym
, support_interwork
);
17869 force_automatic_it_block_close ();
17871 /* Note - do not allow local symbols (.Lxxx) to be labelled
17872 as Thumb functions. This is because these labels, whilst
17873 they exist inside Thumb code, are not the entry points for
17874 possible ARM->Thumb calls. Also, these labels can be used
17875 as part of a computed goto or switch statement. eg gcc
17876 can generate code that looks like this:
17878 ldr r2, [pc, .Laaa]
17888 The first instruction loads the address of the jump table.
17889 The second instruction converts a table index into a byte offset.
17890 The third instruction gets the jump address out of the table.
17891 The fourth instruction performs the jump.
17893 If the address stored at .Laaa is that of a symbol which has the
17894 Thumb_Func bit set, then the linker will arrange for this address
17895 to have the bottom bit set, which in turn would mean that the
17896 address computation performed by the third instruction would end
17897 up with the bottom bit set. Since the ARM is capable of unaligned
17898 word loads, the instruction would then load the incorrect address
17899 out of the jump table, and chaos would ensue. */
17900 if (label_is_thumb_function_name
17901 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
17902 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
17904 /* When the address of a Thumb function is taken the bottom
17905 bit of that address should be set. This will allow
17906 interworking between Arm and Thumb functions to work
17909 THUMB_SET_FUNC (sym
, 1);
17911 label_is_thumb_function_name
= FALSE
;
17914 dwarf2_emit_label (sym
);
17918 arm_data_in_code (void)
17920 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
17922 *input_line_pointer
= '/';
17923 input_line_pointer
+= 5;
17924 *input_line_pointer
= 0;
17932 arm_canonicalize_symbol_name (char * name
)
17936 if (thumb_mode
&& (len
= strlen (name
)) > 5
17937 && streq (name
+ len
- 5, "/data"))
17938 *(name
+ len
- 5) = 0;
17943 /* Table of all register names defined by default. The user can
17944 define additional names with .req. Note that all register names
17945 should appear in both upper and lowercase variants. Some registers
17946 also have mixed-case names. */
17948 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
17949 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
17950 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
17951 #define REGSET(p,t) \
17952 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
17953 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
17954 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
17955 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
17956 #define REGSETH(p,t) \
17957 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
17958 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
17959 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
17960 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
17961 #define REGSET2(p,t) \
17962 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
17963 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
17964 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
17965 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
17966 #define SPLRBANK(base,bank,t) \
17967 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
17968 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
17969 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
17970 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
17971 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
17972 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
17974 static const struct reg_entry reg_names
[] =
17976 /* ARM integer registers. */
17977 REGSET(r
, RN
), REGSET(R
, RN
),
17979 /* ATPCS synonyms. */
17980 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
17981 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
17982 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
17984 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
17985 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
17986 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
17988 /* Well-known aliases. */
17989 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
17990 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
17992 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
17993 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
17995 /* Coprocessor numbers. */
17996 REGSET(p
, CP
), REGSET(P
, CP
),
17998 /* Coprocessor register numbers. The "cr" variants are for backward
18000 REGSET(c
, CN
), REGSET(C
, CN
),
18001 REGSET(cr
, CN
), REGSET(CR
, CN
),
18003 /* ARM banked registers. */
18004 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18005 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18006 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18007 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18008 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18009 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18010 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18012 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18013 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18014 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18015 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18016 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18017 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18018 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18019 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18021 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18022 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18023 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18024 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18025 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18026 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18027 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18028 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18029 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18031 /* FPA registers. */
18032 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18033 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18035 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18036 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18038 /* VFP SP registers. */
18039 REGSET(s
,VFS
), REGSET(S
,VFS
),
18040 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18042 /* VFP DP Registers. */
18043 REGSET(d
,VFD
), REGSET(D
,VFD
),
18044 /* Extra Neon DP registers. */
18045 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18047 /* Neon QP registers. */
18048 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18050 /* VFP control registers. */
18051 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18052 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18053 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18054 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18055 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18056 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18058 /* Maverick DSP coprocessor registers. */
18059 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18060 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18062 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18063 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18064 REGDEF(dspsc
,0,DSPSC
),
18066 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18067 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18068 REGDEF(DSPSC
,0,DSPSC
),
18070 /* iWMMXt data registers - p0, c0-15. */
18071 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18073 /* iWMMXt control registers - p1, c0-3. */
18074 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18075 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18076 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18077 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18079 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18080 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18081 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18082 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18083 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18085 /* XScale accumulator registers. */
18086 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18092 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18093 within psr_required_here. */
18094 static const struct asm_psr psrs
[] =
18096 /* Backward compatibility notation. Note that "all" is no longer
18097 truly all possible PSR bits. */
18098 {"all", PSR_c
| PSR_f
},
18102 /* Individual flags. */
18108 /* Combinations of flags. */
18109 {"fs", PSR_f
| PSR_s
},
18110 {"fx", PSR_f
| PSR_x
},
18111 {"fc", PSR_f
| PSR_c
},
18112 {"sf", PSR_s
| PSR_f
},
18113 {"sx", PSR_s
| PSR_x
},
18114 {"sc", PSR_s
| PSR_c
},
18115 {"xf", PSR_x
| PSR_f
},
18116 {"xs", PSR_x
| PSR_s
},
18117 {"xc", PSR_x
| PSR_c
},
18118 {"cf", PSR_c
| PSR_f
},
18119 {"cs", PSR_c
| PSR_s
},
18120 {"cx", PSR_c
| PSR_x
},
18121 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18122 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18123 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18124 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18125 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18126 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18127 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18128 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18129 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18130 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18131 {"scf", PSR_s
| PSR_c
| PSR_f
},
18132 {"scx", PSR_s
| PSR_c
| PSR_x
},
18133 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18134 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18135 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18136 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18137 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18138 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18139 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18140 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18141 {"csf", PSR_c
| PSR_s
| PSR_f
},
18142 {"csx", PSR_c
| PSR_s
| PSR_x
},
18143 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18144 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18145 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18146 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18147 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18148 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18149 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18150 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18151 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18152 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18153 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18154 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18155 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18156 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18157 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18158 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18159 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18160 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18161 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18162 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18163 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18164 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18165 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18166 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18167 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18168 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18171 /* Table of V7M psr names. */
18172 static const struct asm_psr v7m_psrs
[] =
18174 {"apsr", 0 }, {"APSR", 0 },
18175 {"iapsr", 1 }, {"IAPSR", 1 },
18176 {"eapsr", 2 }, {"EAPSR", 2 },
18177 {"psr", 3 }, {"PSR", 3 },
18178 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18179 {"ipsr", 5 }, {"IPSR", 5 },
18180 {"epsr", 6 }, {"EPSR", 6 },
18181 {"iepsr", 7 }, {"IEPSR", 7 },
18182 {"msp", 8 }, {"MSP", 8 },
18183 {"psp", 9 }, {"PSP", 9 },
18184 {"primask", 16}, {"PRIMASK", 16},
18185 {"basepri", 17}, {"BASEPRI", 17},
18186 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18187 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
18188 {"faultmask", 19}, {"FAULTMASK", 19},
18189 {"control", 20}, {"CONTROL", 20}
18192 /* Table of all shift-in-operand names. */
18193 static const struct asm_shift_name shift_names
[] =
18195 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18196 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18197 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18198 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18199 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18200 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18203 /* Table of all explicit relocation names. */
18205 static struct reloc_entry reloc_names
[] =
18207 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18208 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18209 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18210 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18211 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18212 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18213 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18214 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18215 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18216 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18217 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18218 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18219 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18220 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18221 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18222 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18223 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18224 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18228 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18229 static const struct asm_cond conds
[] =
18233 {"cs", 0x2}, {"hs", 0x2},
18234 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18248 #define UL_BARRIER(L,U,CODE,FEAT) \
18249 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18250 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18252 static struct asm_barrier_opt barrier_opt_names
[] =
18254 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
18255 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
18256 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
18257 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
18258 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
18259 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
18260 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
18261 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
18262 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
18263 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
18264 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
18265 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
18266 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
18267 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
18268 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
18269 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
18274 /* Table of ARM-format instructions. */
18276 /* Macros for gluing together operand strings. N.B. In all cases
18277 other than OPS0, the trailing OP_stop comes from default
18278 zero-initialization of the unspecified elements of the array. */
18279 #define OPS0() { OP_stop, }
18280 #define OPS1(a) { OP_##a, }
18281 #define OPS2(a,b) { OP_##a,OP_##b, }
18282 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18283 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18284 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18285 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18287 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18288 This is useful when mixing operands for ARM and THUMB, i.e. using the
18289 MIX_ARM_THUMB_OPERANDS macro.
18290 In order to use these macros, prefix the number of operands with _
18292 #define OPS_1(a) { a, }
18293 #define OPS_2(a,b) { a,b, }
18294 #define OPS_3(a,b,c) { a,b,c, }
18295 #define OPS_4(a,b,c,d) { a,b,c,d, }
18296 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18297 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18299 /* These macros abstract out the exact format of the mnemonic table and
18300 save some repeated characters. */
18302 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18303 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18304 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18305 THUMB_VARIANT, do_##ae, do_##te }
18307 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18308 a T_MNEM_xyz enumerator. */
18309 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18310 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18311 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18312 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18314 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18315 infix after the third character. */
18316 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18317 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18318 THUMB_VARIANT, do_##ae, do_##te }
18319 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18320 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18321 THUMB_VARIANT, do_##ae, do_##te }
18322 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18323 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18324 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18325 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18326 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18327 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18328 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18329 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18331 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18332 field is still 0xE. Many of the Thumb variants can be executed
18333 conditionally, so this is checked separately. */
18334 #define TUE(mnem, op, top, nops, ops, ae, te) \
18335 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18336 THUMB_VARIANT, do_##ae, do_##te }
18338 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18339 Used by mnemonics that have very minimal differences in the encoding for
18340 ARM and Thumb variants and can be handled in a common function. */
18341 #define TUEc(mnem, op, top, nops, ops, en) \
18342 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18343 THUMB_VARIANT, do_##en, do_##en }
18345 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18346 condition code field. */
18347 #define TUF(mnem, op, top, nops, ops, ae, te) \
18348 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18349 THUMB_VARIANT, do_##ae, do_##te }
18351 /* ARM-only variants of all the above. */
18352 #define CE(mnem, op, nops, ops, ae) \
18353 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18355 #define C3(mnem, op, nops, ops, ae) \
18356 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18358 /* Legacy mnemonics that always have conditional infix after the third
18360 #define CL(mnem, op, nops, ops, ae) \
18361 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18362 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18364 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18365 #define cCE(mnem, op, nops, ops, ae) \
18366 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18368 /* Legacy coprocessor instructions where conditional infix and conditional
18369 suffix are ambiguous. For consistency this includes all FPA instructions,
18370 not just the potentially ambiguous ones. */
18371 #define cCL(mnem, op, nops, ops, ae) \
18372 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18373 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18375 /* Coprocessor, takes either a suffix or a position-3 infix
18376 (for an FPA corner case). */
18377 #define C3E(mnem, op, nops, ops, ae) \
18378 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18379 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18381 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18382 { m1 #m2 m3, OPS##nops ops, \
18383 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18384 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18386 #define CM(m1, m2, op, nops, ops, ae) \
18387 xCM_ (m1, , m2, op, nops, ops, ae), \
18388 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18389 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18390 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18391 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18392 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18393 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18394 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18395 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18396 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18397 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18398 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18399 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18400 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18401 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18402 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18403 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18404 xCM_ (m1, le, m2, op, nops, ops, ae), \
18405 xCM_ (m1, al, m2, op, nops, ops, ae)
18407 #define UE(mnem, op, nops, ops, ae) \
18408 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18410 #define UF(mnem, op, nops, ops, ae) \
18411 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18413 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
18414 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
18415 use the same encoding function for each. */
18416 #define NUF(mnem, op, nops, ops, enc) \
18417 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
18418 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18420 /* Neon data processing, version which indirects through neon_enc_tab for
18421 the various overloaded versions of opcodes. */
18422 #define nUF(mnem, op, nops, ops, enc) \
18423 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
18424 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18426 /* Neon insn with conditional suffix for the ARM version, non-overloaded
18428 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
18429 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
18430 THUMB_VARIANT, do_##enc, do_##enc }
18432 #define NCE(mnem, op, nops, ops, enc) \
18433 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18435 #define NCEF(mnem, op, nops, ops, enc) \
18436 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18438 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
18439 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
18440 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
18441 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18443 #define nCE(mnem, op, nops, ops, enc) \
18444 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18446 #define nCEF(mnem, op, nops, ops, enc) \
18447 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18451 static const struct asm_opcode insns
[] =
18453 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
18454 #define THUMB_VARIANT & arm_ext_v4t
18455 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18456 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18457 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18458 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18459 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18460 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18461 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18462 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18463 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18464 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18465 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18466 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18467 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18468 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18469 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18470 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18472 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18473 for setting PSR flag bits. They are obsolete in V6 and do not
18474 have Thumb equivalents. */
18475 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18476 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18477 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
18478 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18479 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18480 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
18481 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18482 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18483 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
18485 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18486 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18487 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18488 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18490 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
18491 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18492 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
18494 OP_ADDRGLDR
),ldst
, t_ldst
),
18495 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18497 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18498 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18499 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18500 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18501 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18502 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18504 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18505 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18506 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
18507 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
18510 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
18511 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
18512 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
18513 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
18515 /* Thumb-compatibility pseudo ops. */
18516 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18517 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18518 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18519 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18520 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18521 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18522 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18523 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18524 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
18525 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
18526 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
18527 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
18529 /* These may simplify to neg. */
18530 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18531 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18533 #undef THUMB_VARIANT
18534 #define THUMB_VARIANT & arm_ext_v6
18536 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
18538 /* V1 instructions with no Thumb analogue prior to V6T2. */
18539 #undef THUMB_VARIANT
18540 #define THUMB_VARIANT & arm_ext_v6t2
18542 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18543 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18544 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
18546 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18547 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18548 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
18549 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18551 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18552 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18554 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18555 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18557 /* V1 instructions with no Thumb analogue at all. */
18558 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
18559 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
18561 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18562 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18563 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18564 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18565 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18566 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18567 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18568 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18571 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18572 #undef THUMB_VARIANT
18573 #define THUMB_VARIANT & arm_ext_v4t
18575 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18576 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18578 #undef THUMB_VARIANT
18579 #define THUMB_VARIANT & arm_ext_v6t2
18581 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
18582 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
18584 /* Generic coprocessor instructions. */
18585 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18586 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18587 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18588 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18589 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18590 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18591 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18594 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18596 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18597 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18600 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18601 #undef THUMB_VARIANT
18602 #define THUMB_VARIANT & arm_ext_msr
18604 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
18605 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
18608 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18609 #undef THUMB_VARIANT
18610 #define THUMB_VARIANT & arm_ext_v6t2
18612 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18613 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18614 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18615 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18616 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18617 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18618 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18619 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18622 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18623 #undef THUMB_VARIANT
18624 #define THUMB_VARIANT & arm_ext_v4t
18626 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18627 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18628 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18629 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18630 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18631 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18634 #define ARM_VARIANT & arm_ext_v4t_5
18636 /* ARM Architecture 4T. */
18637 /* Note: bx (and blx) are required on V5, even if the processor does
18638 not support Thumb. */
18639 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
18642 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18643 #undef THUMB_VARIANT
18644 #define THUMB_VARIANT & arm_ext_v5t
18646 /* Note: blx has 2 variants; the .value coded here is for
18647 BLX(2). Only this variant has conditional execution. */
18648 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
18649 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
18651 #undef THUMB_VARIANT
18652 #define THUMB_VARIANT & arm_ext_v6t2
18654 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
18655 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18656 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18657 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18658 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18659 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18660 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18661 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18664 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18665 #undef THUMB_VARIANT
18666 #define THUMB_VARIANT & arm_ext_v5exp
18668 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18669 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18670 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18671 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18673 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18674 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18676 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18677 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18678 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18679 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18681 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18682 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18683 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18684 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18686 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18687 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18689 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18690 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18691 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18692 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18695 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18696 #undef THUMB_VARIANT
18697 #define THUMB_VARIANT & arm_ext_v6t2
18699 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
18700 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
18702 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
18703 ADDRGLDRS
), ldrd
, t_ldstd
),
18705 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18706 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18709 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18711 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
18714 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18715 #undef THUMB_VARIANT
18716 #define THUMB_VARIANT & arm_ext_v6
18718 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18719 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18720 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18721 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18722 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18723 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18724 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18725 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18726 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18727 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
18729 #undef THUMB_VARIANT
18730 #define THUMB_VARIANT & arm_ext_v6t2
18732 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
18733 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18735 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18736 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18738 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
18739 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
18741 /* ARM V6 not included in V7M. */
18742 #undef THUMB_VARIANT
18743 #define THUMB_VARIANT & arm_ext_v6_notm
18744 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18745 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18746 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
18747 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
18748 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18749 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18750 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
18751 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18752 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
18753 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18754 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18755 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18756 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18757 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18758 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
18759 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
18760 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18761 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18763 /* ARM V6 not included in V7M (eg. integer SIMD). */
18764 #undef THUMB_VARIANT
18765 #define THUMB_VARIANT & arm_ext_v6_dsp
18766 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
18767 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
18768 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
18769 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18770 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18771 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18772 /* Old name for QASX. */
18773 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18774 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18775 /* Old name for QSAX. */
18776 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18777 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18778 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18779 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18780 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18781 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18782 /* Old name for SASX. */
18783 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18784 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18785 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18786 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18787 /* Old name for SHASX. */
18788 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18789 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18790 /* Old name for SHSAX. */
18791 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18792 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18793 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18794 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18795 /* Old name for SSAX. */
18796 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18797 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18798 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18799 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18800 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18801 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18802 /* Old name for UASX. */
18803 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18804 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18805 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18806 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18807 /* Old name for UHASX. */
18808 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18809 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18810 /* Old name for UHSAX. */
18811 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18812 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18813 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18814 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18815 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18816 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18817 /* Old name for UQASX. */
18818 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18819 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18820 /* Old name for UQSAX. */
18821 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18822 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18823 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18824 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18825 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18826 /* Old name for USAX. */
18827 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18828 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18829 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18830 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18831 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18832 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18833 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18834 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18835 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18836 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18837 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18838 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18839 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18840 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18841 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18842 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18843 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18844 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18845 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18846 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18847 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18848 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18849 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18850 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18851 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18852 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18853 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18854 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18855 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18856 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
18857 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
18858 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18859 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18860 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
18863 #define ARM_VARIANT & arm_ext_v6k
18864 #undef THUMB_VARIANT
18865 #define THUMB_VARIANT & arm_ext_v6k
18867 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
18868 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
18869 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
18870 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
18872 #undef THUMB_VARIANT
18873 #define THUMB_VARIANT & arm_ext_v6_notm
18874 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
18876 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
18877 RRnpcb
), strexd
, t_strexd
),
18879 #undef THUMB_VARIANT
18880 #define THUMB_VARIANT & arm_ext_v6t2
18881 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
18883 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
18885 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18887 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18889 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
18892 #define ARM_VARIANT & arm_ext_sec
18893 #undef THUMB_VARIANT
18894 #define THUMB_VARIANT & arm_ext_sec
18896 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
18899 #define ARM_VARIANT & arm_ext_virt
18900 #undef THUMB_VARIANT
18901 #define THUMB_VARIANT & arm_ext_virt
18903 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
18904 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
18907 #define ARM_VARIANT & arm_ext_pan
18908 #undef THUMB_VARIANT
18909 #define THUMB_VARIANT & arm_ext_pan
18911 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
18914 #define ARM_VARIANT & arm_ext_v6t2
18915 #undef THUMB_VARIANT
18916 #define THUMB_VARIANT & arm_ext_v6t2
18918 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
18919 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
18920 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
18921 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
18923 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
18924 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
18925 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
18926 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
18928 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18929 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18930 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18931 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18933 /* Thumb-only instructions. */
18935 #define ARM_VARIANT NULL
18936 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
18937 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
18939 /* ARM does not really have an IT instruction, so always allow it.
18940 The opcode is copied from Thumb in order to allow warnings in
18941 -mimplicit-it=[never | arm] modes. */
18943 #define ARM_VARIANT & arm_ext_v1
18945 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
18946 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
18947 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
18948 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
18949 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
18950 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
18951 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
18952 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
18953 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
18954 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
18955 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
18956 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
18957 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
18958 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
18959 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
18960 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
18961 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
18962 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
18964 /* Thumb2 only instructions. */
18966 #define ARM_VARIANT NULL
18968 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
18969 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
18970 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
18971 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
18972 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
18973 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
18975 /* Hardware division instructions. */
18977 #define ARM_VARIANT & arm_ext_adiv
18978 #undef THUMB_VARIANT
18979 #define THUMB_VARIANT & arm_ext_div
18981 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
18982 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
18984 /* ARM V6M/V7 instructions. */
18986 #define ARM_VARIANT & arm_ext_barrier
18987 #undef THUMB_VARIANT
18988 #define THUMB_VARIANT & arm_ext_barrier
18990 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
18991 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
18992 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
18994 /* ARM V7 instructions. */
18996 #define ARM_VARIANT & arm_ext_v7
18997 #undef THUMB_VARIANT
18998 #define THUMB_VARIANT & arm_ext_v7
19000 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19001 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19004 #define ARM_VARIANT & arm_ext_mp
19005 #undef THUMB_VARIANT
19006 #define THUMB_VARIANT & arm_ext_mp
19008 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19010 /* AArchv8 instructions. */
19012 #define ARM_VARIANT & arm_ext_v8
19013 #undef THUMB_VARIANT
19014 #define THUMB_VARIANT & arm_ext_v8
19016 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19017 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19018 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19019 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19021 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19022 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19023 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19025 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19027 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19029 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19031 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19032 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19033 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19034 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19035 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19036 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19038 /* ARMv8 T32 only. */
19040 #define ARM_VARIANT NULL
19041 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19042 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19043 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19045 /* FP for ARMv8. */
19047 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19048 #undef THUMB_VARIANT
19049 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19051 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19052 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19053 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19054 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19055 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19056 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19057 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19058 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19059 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19060 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19061 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19062 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19063 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19064 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19065 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19066 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19067 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19069 /* Crypto v1 extensions. */
19071 #define ARM_VARIANT & fpu_crypto_ext_armv8
19072 #undef THUMB_VARIANT
19073 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19075 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19076 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19077 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19078 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19079 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19080 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19081 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19082 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19083 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19084 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19085 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19086 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19087 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19088 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19091 #define ARM_VARIANT & crc_ext_armv8
19092 #undef THUMB_VARIANT
19093 #define THUMB_VARIANT & crc_ext_armv8
19094 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19095 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19096 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19097 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19098 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19099 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19102 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19103 #undef THUMB_VARIANT
19104 #define THUMB_VARIANT NULL
19106 cCE("wfs", e200110
, 1, (RR
), rd
),
19107 cCE("rfs", e300110
, 1, (RR
), rd
),
19108 cCE("wfc", e400110
, 1, (RR
), rd
),
19109 cCE("rfc", e500110
, 1, (RR
), rd
),
19111 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19112 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19113 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19114 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19116 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19117 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19118 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19119 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19121 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19122 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19123 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19124 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19125 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19126 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19127 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19128 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19129 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19130 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19131 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19132 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19134 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19135 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19136 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19137 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19138 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19139 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19140 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19141 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19142 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19143 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19144 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19145 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19147 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19148 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19149 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19150 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19151 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19152 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19153 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19154 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19155 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19156 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19157 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19158 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19160 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19161 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19162 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19163 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19164 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19165 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19166 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19167 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19168 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19169 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19170 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19171 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19173 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19174 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19175 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19176 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19177 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19178 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19179 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19180 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19181 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19182 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19183 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19184 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19186 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19187 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19188 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19189 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19190 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19191 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19192 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19193 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19194 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19195 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19196 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19197 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19199 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19200 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19201 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19202 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19203 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19204 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19205 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19206 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19207 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19208 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19209 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19210 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19212 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19213 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19214 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19215 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19216 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19217 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
19218 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
19219 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
19220 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
19221 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
19222 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
19223 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
19225 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
19226 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
19227 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
19228 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
19229 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
19230 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
19231 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
19232 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
19233 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
19234 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
19235 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
19236 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
19238 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
19239 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
19240 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
19241 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
19242 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
19243 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
19244 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
19245 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
19246 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
19247 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
19248 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
19249 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
19251 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
19252 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
19253 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
19254 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
19255 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
19256 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
19257 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
19258 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
19259 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
19260 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
19261 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
19262 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
19264 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
19265 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
19266 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
19267 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
19268 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
19269 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
19270 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
19271 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
19272 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
19273 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
19274 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
19275 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
19277 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
19278 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
19279 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
19280 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
19281 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
19282 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
19283 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
19284 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
19285 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
19286 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
19287 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
19288 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
19290 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
19291 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
19292 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
19293 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
19294 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
19295 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
19296 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
19297 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
19298 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
19299 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
19300 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
19301 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
19303 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
19304 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
19305 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
19306 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
19307 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
19308 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19309 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19310 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19311 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19312 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19313 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19314 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19316 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19317 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19318 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19319 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19320 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19321 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19322 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19323 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19324 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19325 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19326 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19327 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19329 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19330 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19331 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19332 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19333 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19334 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19335 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19336 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19337 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19338 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19339 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19340 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19342 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19343 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19344 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19345 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19346 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19347 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19348 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19349 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19350 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19351 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19352 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19353 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19355 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19356 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19357 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19358 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19359 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19360 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19361 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19362 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19363 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19364 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19365 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19366 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19368 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19369 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19370 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19371 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19372 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19373 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19374 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19375 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19376 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19377 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19378 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19379 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19381 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19382 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19383 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19384 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19385 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19386 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19387 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19388 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19389 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19390 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19391 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19392 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19394 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19395 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19396 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19397 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19398 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19399 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19400 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19401 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19402 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19403 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19404 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19405 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19407 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19408 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19409 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19410 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19411 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19412 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19413 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19414 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19415 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19416 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19417 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19418 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19420 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19421 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19422 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19423 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19424 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19425 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19426 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19427 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19428 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19429 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19430 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19431 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19433 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19434 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19435 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19436 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19437 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19438 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19439 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19440 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19441 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19442 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19443 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19444 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19446 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19447 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19448 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19449 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19450 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19451 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19452 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19453 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19454 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19455 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19456 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19457 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19459 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19460 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19461 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19462 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19463 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19464 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19465 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19466 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19467 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19468 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19469 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19470 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19472 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19473 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19474 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19475 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19476 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19477 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19478 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19479 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19480 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19481 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19482 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19483 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19485 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19486 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19487 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19488 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19489 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19490 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19491 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19492 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19493 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19494 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19495 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19496 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19498 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19499 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19500 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19501 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19503 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
19504 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
19505 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
19506 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
19507 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
19508 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
19509 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
19510 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
19511 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
19512 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
19513 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
19514 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
19516 /* The implementation of the FIX instruction is broken on some
19517 assemblers, in that it accepts a precision specifier as well as a
19518 rounding specifier, despite the fact that this is meaningless.
19519 To be more compatible, we accept it as well, though of course it
19520 does not set any bits. */
19521 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
19522 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
19523 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
19524 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
19525 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
19526 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
19527 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
19528 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
19529 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
19530 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
19531 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
19532 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
19533 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
19535 /* Instructions that were new with the real FPA, call them V2. */
19537 #define ARM_VARIANT & fpu_fpa_ext_v2
19539 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19540 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19541 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19542 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19543 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19544 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19547 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19549 /* Moves and type conversions. */
19550 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19551 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
19552 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
19553 cCE("fmstat", ef1fa10
, 0, (), noargs
),
19554 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
19555 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
19556 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19557 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19558 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19559 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19560 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19561 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19562 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
19563 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
19565 /* Memory operations. */
19566 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19567 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19568 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19569 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19570 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19571 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19572 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19573 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19574 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19575 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19576 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19577 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19578 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19579 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19580 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19581 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19582 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19583 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19585 /* Monadic operations. */
19586 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19587 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19588 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19590 /* Dyadic operations. */
19591 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19592 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19593 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19594 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19595 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19596 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19597 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19598 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19599 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19602 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19603 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
19604 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19605 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
19607 /* Double precision load/store are still present on single precision
19608 implementations. */
19609 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19610 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19611 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19612 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19613 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19614 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19615 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19616 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19617 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19618 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19621 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19623 /* Moves and type conversions. */
19624 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19625 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19626 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19627 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19628 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19629 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19630 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19631 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19632 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19633 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19634 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19635 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19636 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19638 /* Monadic operations. */
19639 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19640 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19641 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19643 /* Dyadic operations. */
19644 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19645 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19646 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19647 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19648 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19649 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19650 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19651 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19652 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19655 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19656 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
19657 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19658 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
19661 #define ARM_VARIANT & fpu_vfp_ext_v2
19663 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
19664 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
19665 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
19666 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
19668 /* Instructions which may belong to either the Neon or VFP instruction sets.
19669 Individual encoder functions perform additional architecture checks. */
19671 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19672 #undef THUMB_VARIANT
19673 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19675 /* These mnemonics are unique to VFP. */
19676 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
19677 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
19678 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19679 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19680 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19681 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
19682 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
19683 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
19684 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
19685 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
19687 /* Mnemonics shared by Neon and VFP. */
19688 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
19689 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19690 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19692 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19693 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19695 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19696 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19698 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19699 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19700 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19701 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19702 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19703 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19704 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19705 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19707 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
19708 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
19709 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
19710 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
19713 /* NOTE: All VMOV encoding is special-cased! */
19714 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
19715 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
19717 #undef THUMB_VARIANT
19718 #define THUMB_VARIANT & fpu_neon_ext_v1
19720 #define ARM_VARIANT & fpu_neon_ext_v1
19722 /* Data processing with three registers of the same length. */
19723 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19724 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
19725 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
19726 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19727 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19728 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19729 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19730 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19731 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19732 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19733 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19734 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19735 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19736 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19737 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19738 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19739 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19740 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19741 /* If not immediate, fall back to neon_dyadic_i64_su.
19742 shl_imm should accept I8 I16 I32 I64,
19743 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19744 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
19745 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
19746 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
19747 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
19748 /* Logic ops, types optional & ignored. */
19749 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19750 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19751 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19752 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19753 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19754 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19755 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19756 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19757 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
19758 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
19759 /* Bitfield ops, untyped. */
19760 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19761 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19762 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19763 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19764 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19765 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19766 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19767 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19768 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19769 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19770 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19771 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19772 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19773 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19774 back to neon_dyadic_if_su. */
19775 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19776 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19777 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19778 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19779 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19780 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19781 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19782 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19783 /* Comparison. Type I8 I16 I32 F32. */
19784 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
19785 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
19786 /* As above, D registers only. */
19787 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19788 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19789 /* Int and float variants, signedness unimportant. */
19790 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19791 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19792 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
19793 /* Add/sub take types I8 I16 I32 I64 F32. */
19794 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19795 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19796 /* vtst takes sizes 8, 16, 32. */
19797 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
19798 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
19799 /* VMUL takes I8 I16 I32 F32 P8. */
19800 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
19801 /* VQD{R}MULH takes S16 S32. */
19802 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19803 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19804 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19805 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19806 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19807 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19808 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19809 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19810 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19811 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19812 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19813 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19814 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19815 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19816 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19817 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19819 /* Two address, int/float. Types S8 S16 S32 F32. */
19820 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19821 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19823 /* Data processing with two registers and a shift amount. */
19824 /* Right shifts, and variants with rounding.
19825 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19826 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19827 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19828 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19829 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19830 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19831 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19832 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19833 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19834 /* Shift and insert. Sizes accepted 8 16 32 64. */
19835 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
19836 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
19837 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
19838 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
19839 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19840 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
19841 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
19842 /* Right shift immediate, saturating & narrowing, with rounding variants.
19843 Types accepted S16 S32 S64 U16 U32 U64. */
19844 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
19845 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
19846 /* As above, unsigned. Types accepted S16 S32 S64. */
19847 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
19848 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
19849 /* Right shift narrowing. Types accepted I16 I32 I64. */
19850 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
19851 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
19852 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
19853 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
19854 /* CVT with optional immediate for fixed-point variant. */
19855 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
19857 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
19858 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
19860 /* Data processing, three registers of different lengths. */
19861 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
19862 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
19863 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19864 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19865 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19866 /* If not scalar, fall back to neon_dyadic_long.
19867 Vector types as above, scalar types S16 S32 U16 U32. */
19868 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
19869 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
19870 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
19871 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
19872 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
19873 /* Dyadic, narrowing insns. Types I16 I32 I64. */
19874 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19875 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19876 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19877 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19878 /* Saturating doubling multiplies. Types S16 S32. */
19879 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
19880 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
19881 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
19882 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
19883 S16 S32 U16 U32. */
19884 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
19886 /* Extract. Size 8. */
19887 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
19888 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
19890 /* Two registers, miscellaneous. */
19891 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
19892 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
19893 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
19894 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
19895 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
19896 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
19897 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
19898 /* Vector replicate. Sizes 8 16 32. */
19899 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
19900 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
19901 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
19902 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
19903 /* VMOVN. Types I16 I32 I64. */
19904 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
19905 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
19906 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
19907 /* VQMOVUN. Types S16 S32 S64. */
19908 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
19909 /* VZIP / VUZP. Sizes 8 16 32. */
19910 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
19911 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
19912 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
19913 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
19914 /* VQABS / VQNEG. Types S8 S16 S32. */
19915 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
19916 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
19917 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
19918 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
19919 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
19920 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
19921 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
19922 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
19923 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
19924 /* Reciprocal estimates. Types U32 F32. */
19925 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
19926 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
19927 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
19928 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
19929 /* VCLS. Types S8 S16 S32. */
19930 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
19931 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
19932 /* VCLZ. Types I8 I16 I32. */
19933 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
19934 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
19935 /* VCNT. Size 8. */
19936 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
19937 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
19938 /* Two address, untyped. */
19939 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
19940 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
19941 /* VTRN. Sizes 8 16 32. */
19942 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
19943 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
19945 /* Table lookup. Size 8. */
19946 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
19947 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
19949 #undef THUMB_VARIANT
19950 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
19952 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
19954 /* Neon element/structure load/store. */
19955 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19956 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19957 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19958 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19959 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19960 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19961 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19962 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19964 #undef THUMB_VARIANT
19965 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
19967 #define ARM_VARIANT & fpu_vfp_ext_v3xd
19968 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
19969 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19970 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19971 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19972 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19973 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19974 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19975 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19976 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19978 #undef THUMB_VARIANT
19979 #define THUMB_VARIANT & fpu_vfp_ext_v3
19981 #define ARM_VARIANT & fpu_vfp_ext_v3
19983 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
19984 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19985 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19986 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19987 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19988 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19989 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19990 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19991 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19994 #define ARM_VARIANT & fpu_vfp_ext_fma
19995 #undef THUMB_VARIANT
19996 #define THUMB_VARIANT & fpu_vfp_ext_fma
19997 /* Mnemonics shared by Neon and VFP. These are included in the
19998 VFP FMA variant; NEON and VFP FMA always includes the NEON
19999 FMA instructions. */
20000 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20001 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20002 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20003 the v form should always be used. */
20004 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20005 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20006 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20007 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20008 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20009 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20011 #undef THUMB_VARIANT
20013 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20015 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20016 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20017 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20018 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20019 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20020 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20021 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20022 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20025 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20027 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20028 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20029 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20030 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20031 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20032 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20033 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20034 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20035 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20036 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20037 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20038 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20039 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20040 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20041 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20042 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20043 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20044 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20045 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20046 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20047 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20048 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20049 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20050 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20051 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20052 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20053 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20054 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20055 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20056 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20057 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20058 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20059 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20060 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20061 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20062 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20063 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20064 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20065 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20066 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20067 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20068 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20069 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20070 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20071 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20072 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20073 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20074 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20075 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20076 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20077 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20078 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20079 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20080 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20081 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20082 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20083 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20084 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20085 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20086 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20087 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20088 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20089 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20090 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20091 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20092 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20093 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20094 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20095 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20096 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20097 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20098 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20099 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20100 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20101 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20102 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20103 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20104 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20105 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20106 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20107 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20108 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20109 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20110 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20111 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20112 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20113 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20114 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20115 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20116 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20117 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20118 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20119 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20120 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20121 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20122 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20123 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20124 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20125 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20126 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20127 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20128 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20129 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20130 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20131 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20132 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20133 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20134 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20135 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20136 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20137 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20138 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20139 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20140 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20141 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20142 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20143 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20144 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20145 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20146 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20147 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20148 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20149 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20150 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20151 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20152 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20153 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20154 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20155 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20156 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20157 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20158 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20159 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20160 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20161 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20162 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20163 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20164 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20165 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20166 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20167 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20168 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20169 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20170 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20171 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20172 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20173 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20174 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20175 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20176 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20177 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20178 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20179 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20180 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20181 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20182 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20183 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20184 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20185 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20186 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20187 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20188 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20191 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20193 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20194 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20195 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20196 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20197 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20198 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20199 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20200 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20201 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20202 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20203 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20204 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20205 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20206 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20207 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20208 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20209 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20210 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20211 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20212 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20213 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
20214 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20215 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20216 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20217 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20218 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20219 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20220 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20221 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20222 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20223 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20224 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20225 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20226 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20227 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20228 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20229 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20230 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20231 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20232 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20233 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20234 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20235 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20236 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20237 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20238 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20239 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20240 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20241 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20242 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20243 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20244 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20245 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20246 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20247 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20248 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20249 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20252 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20254 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20255 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20256 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20257 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20258 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20259 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20260 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20261 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20262 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
20263 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
20264 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
20265 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
20266 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
20267 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
20268 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
20269 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
20270 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
20271 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
20272 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
20273 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
20274 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
20275 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
20276 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
20277 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
20278 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
20279 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
20280 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
20281 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
20282 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
20283 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
20284 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
20285 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
20286 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
20287 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
20288 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
20289 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
20290 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
20291 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
20292 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
20293 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
20294 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
20295 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
20296 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
20297 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
20298 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
20299 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
20300 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
20301 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
20302 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
20303 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
20304 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
20305 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
20306 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
20307 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
20308 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20309 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20310 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20311 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20312 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20313 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20314 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20315 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20316 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20317 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20318 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20319 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20320 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20321 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20322 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20323 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20324 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20325 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20326 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20327 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20328 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20329 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20332 #undef THUMB_VARIANT
20358 /* MD interface: bits in the object file. */
20360 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20361 for use in the a.out file, and stores them in the array pointed to by buf.
20362 This knows about the endian-ness of the target machine and does
20363 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20364 2 (short) and 4 (long) Floating numbers are put out as a series of
20365 LITTLENUMS (shorts, here at least). */
20368 md_number_to_chars (char * buf
, valueT val
, int n
)
20370 if (target_big_endian
)
20371 number_to_chars_bigendian (buf
, val
, n
);
20373 number_to_chars_littleendian (buf
, val
, n
);
20377 md_chars_to_number (char * buf
, int n
)
20380 unsigned char * where
= (unsigned char *) buf
;
20382 if (target_big_endian
)
20387 result
|= (*where
++ & 255);
20395 result
|= (where
[n
] & 255);
20402 /* MD interface: Sections. */
20404 /* Calculate the maximum variable size (i.e., excluding fr_fix)
20405 that an rs_machine_dependent frag may reach. */
20408 arm_frag_max_var (fragS
*fragp
)
20410 /* We only use rs_machine_dependent for variable-size Thumb instructions,
20411 which are either THUMB_SIZE (2) or INSN_SIZE (4).
20413 Note that we generate relaxable instructions even for cases that don't
20414 really need it, like an immediate that's a trivial constant. So we're
20415 overestimating the instruction size for some of those cases. Rather
20416 than putting more intelligence here, it would probably be better to
20417 avoid generating a relaxation frag in the first place when it can be
20418 determined up front that a short instruction will suffice. */
20420 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
20424 /* Estimate the size of a frag before relaxing. Assume everything fits in
20428 md_estimate_size_before_relax (fragS
* fragp
,
20429 segT segtype ATTRIBUTE_UNUSED
)
20435 /* Convert a machine dependent frag. */
20438 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
20440 unsigned long insn
;
20441 unsigned long old_op
;
20449 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20451 old_op
= bfd_get_16(abfd
, buf
);
20452 if (fragp
->fr_symbol
)
20454 exp
.X_op
= O_symbol
;
20455 exp
.X_add_symbol
= fragp
->fr_symbol
;
20459 exp
.X_op
= O_constant
;
20461 exp
.X_add_number
= fragp
->fr_offset
;
20462 opcode
= fragp
->fr_subtype
;
20465 case T_MNEM_ldr_pc
:
20466 case T_MNEM_ldr_pc2
:
20467 case T_MNEM_ldr_sp
:
20468 case T_MNEM_str_sp
:
20475 if (fragp
->fr_var
== 4)
20477 insn
= THUMB_OP32 (opcode
);
20478 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
20480 insn
|= (old_op
& 0x700) << 4;
20484 insn
|= (old_op
& 7) << 12;
20485 insn
|= (old_op
& 0x38) << 13;
20487 insn
|= 0x00000c00;
20488 put_thumb32_insn (buf
, insn
);
20489 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
20493 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
20495 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
20498 if (fragp
->fr_var
== 4)
20500 insn
= THUMB_OP32 (opcode
);
20501 insn
|= (old_op
& 0xf0) << 4;
20502 put_thumb32_insn (buf
, insn
);
20503 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
20507 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20508 exp
.X_add_number
-= 4;
20516 if (fragp
->fr_var
== 4)
20518 int r0off
= (opcode
== T_MNEM_mov
20519 || opcode
== T_MNEM_movs
) ? 0 : 8;
20520 insn
= THUMB_OP32 (opcode
);
20521 insn
= (insn
& 0xe1ffffff) | 0x10000000;
20522 insn
|= (old_op
& 0x700) << r0off
;
20523 put_thumb32_insn (buf
, insn
);
20524 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20528 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
20533 if (fragp
->fr_var
== 4)
20535 insn
= THUMB_OP32(opcode
);
20536 put_thumb32_insn (buf
, insn
);
20537 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
20540 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
20544 if (fragp
->fr_var
== 4)
20546 insn
= THUMB_OP32(opcode
);
20547 insn
|= (old_op
& 0xf00) << 14;
20548 put_thumb32_insn (buf
, insn
);
20549 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
20552 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
20555 case T_MNEM_add_sp
:
20556 case T_MNEM_add_pc
:
20557 case T_MNEM_inc_sp
:
20558 case T_MNEM_dec_sp
:
20559 if (fragp
->fr_var
== 4)
20561 /* ??? Choose between add and addw. */
20562 insn
= THUMB_OP32 (opcode
);
20563 insn
|= (old_op
& 0xf0) << 4;
20564 put_thumb32_insn (buf
, insn
);
20565 if (opcode
== T_MNEM_add_pc
)
20566 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
20568 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20571 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20579 if (fragp
->fr_var
== 4)
20581 insn
= THUMB_OP32 (opcode
);
20582 insn
|= (old_op
& 0xf0) << 4;
20583 insn
|= (old_op
& 0xf) << 16;
20584 put_thumb32_insn (buf
, insn
);
20585 if (insn
& (1 << 20))
20586 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20588 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20591 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20597 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
20598 (enum bfd_reloc_code_real
) reloc_type
);
20599 fixp
->fx_file
= fragp
->fr_file
;
20600 fixp
->fx_line
= fragp
->fr_line
;
20601 fragp
->fr_fix
+= fragp
->fr_var
;
20603 /* Set whether we use thumb-2 ISA based on final relaxation results. */
20604 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
20605 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
20606 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
20609 /* Return the size of a relaxable immediate operand instruction.
20610 SHIFT and SIZE specify the form of the allowable immediate. */
20612 relax_immediate (fragS
*fragp
, int size
, int shift
)
20618 /* ??? Should be able to do better than this. */
20619 if (fragp
->fr_symbol
)
20622 low
= (1 << shift
) - 1;
20623 mask
= (1 << (shift
+ size
)) - (1 << shift
);
20624 offset
= fragp
->fr_offset
;
20625 /* Force misaligned offsets to 32-bit variant. */
20628 if (offset
& ~mask
)
20633 /* Get the address of a symbol during relaxation. */
20635 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
20641 sym
= fragp
->fr_symbol
;
20642 sym_frag
= symbol_get_frag (sym
);
20643 know (S_GET_SEGMENT (sym
) != absolute_section
20644 || sym_frag
== &zero_address_frag
);
20645 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
20647 /* If frag has yet to be reached on this pass, assume it will
20648 move by STRETCH just as we did. If this is not so, it will
20649 be because some frag between grows, and that will force
20653 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
20657 /* Adjust stretch for any alignment frag. Note that if have
20658 been expanding the earlier code, the symbol may be
20659 defined in what appears to be an earlier frag. FIXME:
20660 This doesn't handle the fr_subtype field, which specifies
20661 a maximum number of bytes to skip when doing an
20663 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
20665 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
20668 stretch
= - ((- stretch
)
20669 & ~ ((1 << (int) f
->fr_offset
) - 1));
20671 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
20683 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20686 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
20691 /* Assume worst case for symbols not known to be in the same section. */
20692 if (fragp
->fr_symbol
== NULL
20693 || !S_IS_DEFINED (fragp
->fr_symbol
)
20694 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20695 || S_IS_WEAK (fragp
->fr_symbol
))
20698 val
= relaxed_symbol_addr (fragp
, stretch
);
20699 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
20700 addr
= (addr
+ 4) & ~3;
20701 /* Force misaligned targets to 32-bit variant. */
20705 if (val
< 0 || val
> 1020)
20710 /* Return the size of a relaxable add/sub immediate instruction. */
20712 relax_addsub (fragS
*fragp
, asection
*sec
)
20717 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20718 op
= bfd_get_16(sec
->owner
, buf
);
20719 if ((op
& 0xf) == ((op
>> 4) & 0xf))
20720 return relax_immediate (fragp
, 8, 0);
20722 return relax_immediate (fragp
, 3, 0);
20725 /* Return TRUE iff the definition of symbol S could be pre-empted
20726 (overridden) at link or load time. */
20728 symbol_preemptible (symbolS
*s
)
20730 /* Weak symbols can always be pre-empted. */
20734 /* Non-global symbols cannot be pre-empted. */
20735 if (! S_IS_EXTERNAL (s
))
20739 /* In ELF, a global symbol can be marked protected, or private. In that
20740 case it can't be pre-empted (other definitions in the same link unit
20741 would violate the ODR). */
20742 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
20746 /* Other global symbols might be pre-empted. */
20750 /* Return the size of a relaxable branch instruction. BITS is the
20751 size of the offset field in the narrow instruction. */
20754 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
20760 /* Assume worst case for symbols not known to be in the same section. */
20761 if (!S_IS_DEFINED (fragp
->fr_symbol
)
20762 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20763 || S_IS_WEAK (fragp
->fr_symbol
))
20767 /* A branch to a function in ARM state will require interworking. */
20768 if (S_IS_DEFINED (fragp
->fr_symbol
)
20769 && ARM_IS_FUNC (fragp
->fr_symbol
))
20773 if (symbol_preemptible (fragp
->fr_symbol
))
20776 val
= relaxed_symbol_addr (fragp
, stretch
);
20777 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
20780 /* Offset is a signed value *2 */
20782 if (val
>= limit
|| val
< -limit
)
20788 /* Relax a machine dependent frag. This returns the amount by which
20789 the current size of the frag should change. */
20792 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
20797 oldsize
= fragp
->fr_var
;
20798 switch (fragp
->fr_subtype
)
20800 case T_MNEM_ldr_pc2
:
20801 newsize
= relax_adr (fragp
, sec
, stretch
);
20803 case T_MNEM_ldr_pc
:
20804 case T_MNEM_ldr_sp
:
20805 case T_MNEM_str_sp
:
20806 newsize
= relax_immediate (fragp
, 8, 2);
20810 newsize
= relax_immediate (fragp
, 5, 2);
20814 newsize
= relax_immediate (fragp
, 5, 1);
20818 newsize
= relax_immediate (fragp
, 5, 0);
20821 newsize
= relax_adr (fragp
, sec
, stretch
);
20827 newsize
= relax_immediate (fragp
, 8, 0);
20830 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
20833 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
20835 case T_MNEM_add_sp
:
20836 case T_MNEM_add_pc
:
20837 newsize
= relax_immediate (fragp
, 8, 2);
20839 case T_MNEM_inc_sp
:
20840 case T_MNEM_dec_sp
:
20841 newsize
= relax_immediate (fragp
, 7, 2);
20847 newsize
= relax_addsub (fragp
, sec
);
20853 fragp
->fr_var
= newsize
;
20854 /* Freeze wide instructions that are at or before the same location as
20855 in the previous pass. This avoids infinite loops.
20856 Don't freeze them unconditionally because targets may be artificially
20857 misaligned by the expansion of preceding frags. */
20858 if (stretch
<= 0 && newsize
> 2)
20860 md_convert_frag (sec
->owner
, sec
, fragp
);
20864 return newsize
- oldsize
;
20867 /* Round up a section size to the appropriate boundary. */
20870 md_section_align (segT segment ATTRIBUTE_UNUSED
,
20873 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
20874 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
20876 /* For a.out, force the section size to be aligned. If we don't do
20877 this, BFD will align it for us, but it will not write out the
20878 final bytes of the section. This may be a bug in BFD, but it is
20879 easier to fix it here since that is how the other a.out targets
20883 align
= bfd_get_section_alignment (stdoutput
, segment
);
20884 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
20891 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
20892 of an rs_align_code fragment. */
20895 arm_handle_align (fragS
* fragP
)
20897 static char const arm_noop
[2][2][4] =
20900 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
20901 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
20904 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
20905 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
20908 static char const thumb_noop
[2][2][2] =
20911 {0xc0, 0x46}, /* LE */
20912 {0x46, 0xc0}, /* BE */
20915 {0x00, 0xbf}, /* LE */
20916 {0xbf, 0x00} /* BE */
20919 static char const wide_thumb_noop
[2][4] =
20920 { /* Wide Thumb-2 */
20921 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
20922 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
20925 unsigned bytes
, fix
, noop_size
;
20928 const char *narrow_noop
= NULL
;
20933 if (fragP
->fr_type
!= rs_align_code
)
20936 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
20937 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
20940 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
20941 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
20943 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
20945 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
20947 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
20948 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
20950 narrow_noop
= thumb_noop
[1][target_big_endian
];
20951 noop
= wide_thumb_noop
[target_big_endian
];
20954 noop
= thumb_noop
[0][target_big_endian
];
20962 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
20963 ? selected_cpu
: arm_arch_none
,
20965 [target_big_endian
];
20972 fragP
->fr_var
= noop_size
;
20974 if (bytes
& (noop_size
- 1))
20976 fix
= bytes
& (noop_size
- 1);
20978 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
20980 memset (p
, 0, fix
);
20987 if (bytes
& noop_size
)
20989 /* Insert a narrow noop. */
20990 memcpy (p
, narrow_noop
, noop_size
);
20992 bytes
-= noop_size
;
20996 /* Use wide noops for the remainder */
21000 while (bytes
>= noop_size
)
21002 memcpy (p
, noop
, noop_size
);
21004 bytes
-= noop_size
;
21008 fragP
->fr_fix
+= fix
;
21011 /* Called from md_do_align. Used to create an alignment
21012 frag in a code section. */
21015 arm_frag_align_code (int n
, int max
)
21019 /* We assume that there will never be a requirement
21020 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21021 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21026 _("alignments greater than %d bytes not supported in .text sections."),
21027 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21028 as_fatal ("%s", err_msg
);
21031 p
= frag_var (rs_align_code
,
21032 MAX_MEM_FOR_RS_ALIGN_CODE
,
21034 (relax_substateT
) max
,
21041 /* Perform target specific initialisation of a frag.
21042 Note - despite the name this initialisation is not done when the frag
21043 is created, but only when its type is assigned. A frag can be created
21044 and used a long time before its type is set, so beware of assuming that
21045 this initialisationis performed first. */
21049 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21051 /* Record whether this frag is in an ARM or a THUMB area. */
21052 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21055 #else /* OBJ_ELF is defined. */
21057 arm_init_frag (fragS
* fragP
, int max_chars
)
21059 /* If the current ARM vs THUMB mode has not already
21060 been recorded into this frag then do so now. */
21061 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21062 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21064 /* Record a mapping symbol for alignment frags. We will delete this
21065 later if the alignment ends up empty. */
21066 switch (fragP
->fr_type
)
21069 case rs_align_test
:
21071 mapping_state_2 (MAP_DATA
, max_chars
);
21073 case rs_align_code
:
21074 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21081 /* When we change sections we need to issue a new mapping symbol. */
21084 arm_elf_change_section (void)
21086 /* Link an unlinked unwind index table section to the .text section. */
21087 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21088 && elf_linked_to_section (now_seg
) == NULL
)
21089 elf_linked_to_section (now_seg
) = text_section
;
21093 arm_elf_section_type (const char * str
, size_t len
)
21095 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21096 return SHT_ARM_EXIDX
;
21101 /* Code to deal with unwinding tables. */
21103 static void add_unwind_adjustsp (offsetT
);
21105 /* Generate any deferred unwind frame offset. */
21108 flush_pending_unwind (void)
21112 offset
= unwind
.pending_offset
;
21113 unwind
.pending_offset
= 0;
21115 add_unwind_adjustsp (offset
);
21118 /* Add an opcode to this list for this function. Two-byte opcodes should
21119 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21123 add_unwind_opcode (valueT op
, int length
)
21125 /* Add any deferred stack adjustment. */
21126 if (unwind
.pending_offset
)
21127 flush_pending_unwind ();
21129 unwind
.sp_restored
= 0;
21131 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21133 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21134 if (unwind
.opcodes
)
21135 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
21136 unwind
.opcode_alloc
);
21138 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
21143 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21145 unwind
.opcode_count
++;
21149 /* Add unwind opcodes to adjust the stack pointer. */
21152 add_unwind_adjustsp (offsetT offset
)
21156 if (offset
> 0x200)
21158 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21163 /* Long form: 0xb2, uleb128. */
21164 /* This might not fit in a word so add the individual bytes,
21165 remembering the list is built in reverse order. */
21166 o
= (valueT
) ((offset
- 0x204) >> 2);
21168 add_unwind_opcode (0, 1);
21170 /* Calculate the uleb128 encoding of the offset. */
21174 bytes
[n
] = o
& 0x7f;
21180 /* Add the insn. */
21182 add_unwind_opcode (bytes
[n
- 1], 1);
21183 add_unwind_opcode (0xb2, 1);
21185 else if (offset
> 0x100)
21187 /* Two short opcodes. */
21188 add_unwind_opcode (0x3f, 1);
21189 op
= (offset
- 0x104) >> 2;
21190 add_unwind_opcode (op
, 1);
21192 else if (offset
> 0)
21194 /* Short opcode. */
21195 op
= (offset
- 4) >> 2;
21196 add_unwind_opcode (op
, 1);
21198 else if (offset
< 0)
21201 while (offset
> 0x100)
21203 add_unwind_opcode (0x7f, 1);
21206 op
= ((offset
- 4) >> 2) | 0x40;
21207 add_unwind_opcode (op
, 1);
21211 /* Finish the list of unwind opcodes for this function. */
21213 finish_unwind_opcodes (void)
21217 if (unwind
.fp_used
)
21219 /* Adjust sp as necessary. */
21220 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
21221 flush_pending_unwind ();
21223 /* After restoring sp from the frame pointer. */
21224 op
= 0x90 | unwind
.fp_reg
;
21225 add_unwind_opcode (op
, 1);
21228 flush_pending_unwind ();
21232 /* Start an exception table entry. If idx is nonzero this is an index table
21236 start_unwind_section (const segT text_seg
, int idx
)
21238 const char * text_name
;
21239 const char * prefix
;
21240 const char * prefix_once
;
21241 const char * group_name
;
21245 size_t sec_name_len
;
21252 prefix
= ELF_STRING_ARM_unwind
;
21253 prefix_once
= ELF_STRING_ARM_unwind_once
;
21254 type
= SHT_ARM_EXIDX
;
21258 prefix
= ELF_STRING_ARM_unwind_info
;
21259 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
21260 type
= SHT_PROGBITS
;
21263 text_name
= segment_name (text_seg
);
21264 if (streq (text_name
, ".text"))
21267 if (strncmp (text_name
, ".gnu.linkonce.t.",
21268 strlen (".gnu.linkonce.t.")) == 0)
21270 prefix
= prefix_once
;
21271 text_name
+= strlen (".gnu.linkonce.t.");
21274 prefix_len
= strlen (prefix
);
21275 text_len
= strlen (text_name
);
21276 sec_name_len
= prefix_len
+ text_len
;
21277 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
21278 memcpy (sec_name
, prefix
, prefix_len
);
21279 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
21280 sec_name
[prefix_len
+ text_len
] = '\0';
21286 /* Handle COMDAT group. */
21287 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
21289 group_name
= elf_group_name (text_seg
);
21290 if (group_name
== NULL
)
21292 as_bad (_("Group section `%s' has no group signature"),
21293 segment_name (text_seg
));
21294 ignore_rest_of_line ();
21297 flags
|= SHF_GROUP
;
21301 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
21303 /* Set the section link for index tables. */
21305 elf_linked_to_section (now_seg
) = text_seg
;
21309 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21310 personality routine data. Returns zero, or the index table value for
21311 an inline entry. */
21314 create_unwind_entry (int have_data
)
21319 /* The current word of data. */
21321 /* The number of bytes left in this word. */
21324 finish_unwind_opcodes ();
21326 /* Remember the current text section. */
21327 unwind
.saved_seg
= now_seg
;
21328 unwind
.saved_subseg
= now_subseg
;
21330 start_unwind_section (now_seg
, 0);
21332 if (unwind
.personality_routine
== NULL
)
21334 if (unwind
.personality_index
== -2)
21337 as_bad (_("handlerdata in cantunwind frame"));
21338 return 1; /* EXIDX_CANTUNWIND. */
21341 /* Use a default personality routine if none is specified. */
21342 if (unwind
.personality_index
== -1)
21344 if (unwind
.opcode_count
> 3)
21345 unwind
.personality_index
= 1;
21347 unwind
.personality_index
= 0;
21350 /* Space for the personality routine entry. */
21351 if (unwind
.personality_index
== 0)
21353 if (unwind
.opcode_count
> 3)
21354 as_bad (_("too many unwind opcodes for personality routine 0"));
21358 /* All the data is inline in the index table. */
21361 while (unwind
.opcode_count
> 0)
21363 unwind
.opcode_count
--;
21364 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21368 /* Pad with "finish" opcodes. */
21370 data
= (data
<< 8) | 0xb0;
21377 /* We get two opcodes "free" in the first word. */
21378 size
= unwind
.opcode_count
- 2;
21382 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
21383 if (unwind
.personality_index
!= -1)
21385 as_bad (_("attempt to recreate an unwind entry"));
21389 /* An extra byte is required for the opcode count. */
21390 size
= unwind
.opcode_count
+ 1;
21393 size
= (size
+ 3) >> 2;
21395 as_bad (_("too many unwind opcodes"));
21397 frag_align (2, 0, 0);
21398 record_alignment (now_seg
, 2);
21399 unwind
.table_entry
= expr_build_dot ();
21401 /* Allocate the table entry. */
21402 ptr
= frag_more ((size
<< 2) + 4);
21403 /* PR 13449: Zero the table entries in case some of them are not used. */
21404 memset (ptr
, 0, (size
<< 2) + 4);
21405 where
= frag_now_fix () - ((size
<< 2) + 4);
21407 switch (unwind
.personality_index
)
21410 /* ??? Should this be a PLT generating relocation? */
21411 /* Custom personality routine. */
21412 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
21413 BFD_RELOC_ARM_PREL31
);
21418 /* Set the first byte to the number of additional words. */
21419 data
= size
> 0 ? size
- 1 : 0;
21423 /* ABI defined personality routines. */
21425 /* Three opcodes bytes are packed into the first word. */
21432 /* The size and first two opcode bytes go in the first word. */
21433 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
21438 /* Should never happen. */
21442 /* Pack the opcodes into words (MSB first), reversing the list at the same
21444 while (unwind
.opcode_count
> 0)
21448 md_number_to_chars (ptr
, data
, 4);
21453 unwind
.opcode_count
--;
21455 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21458 /* Finish off the last word. */
21461 /* Pad with "finish" opcodes. */
21463 data
= (data
<< 8) | 0xb0;
21465 md_number_to_chars (ptr
, data
, 4);
21470 /* Add an empty descriptor if there is no user-specified data. */
21471 ptr
= frag_more (4);
21472 md_number_to_chars (ptr
, 0, 4);
21479 /* Initialize the DWARF-2 unwind information for this procedure. */
21482 tc_arm_frame_initial_instructions (void)
21484 cfi_add_CFA_def_cfa (REG_SP
, 0);
21486 #endif /* OBJ_ELF */
21488 /* Convert REGNAME to a DWARF-2 register number. */
21491 tc_arm_regname_to_dw2regnum (char *regname
)
21493 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
21497 /* PR 16694: Allow VFP registers as well. */
21498 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
21502 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
21511 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
21515 exp
.X_op
= O_secrel
;
21516 exp
.X_add_symbol
= symbol
;
21517 exp
.X_add_number
= 0;
21518 emit_expr (&exp
, size
);
21522 /* MD interface: Symbol and relocation handling. */
21524 /* Return the address within the segment that a PC-relative fixup is
21525 relative to. For ARM, PC-relative fixups applied to instructions
21526 are generally relative to the location of the fixup plus 8 bytes.
21527 Thumb branches are offset by 4, and Thumb loads relative to PC
21528 require special handling. */
21531 md_pcrel_from_section (fixS
* fixP
, segT seg
)
21533 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21535 /* If this is pc-relative and we are going to emit a relocation
21536 then we just want to put out any pipeline compensation that the linker
21537 will need. Otherwise we want to use the calculated base.
21538 For WinCE we skip the bias for externals as well, since this
21539 is how the MS ARM-CE assembler behaves and we want to be compatible. */
21541 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21542 || (arm_force_relocation (fixP
)
21544 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
21550 switch (fixP
->fx_r_type
)
21552 /* PC relative addressing on the Thumb is slightly odd as the
21553 bottom two bits of the PC are forced to zero for the
21554 calculation. This happens *after* application of the
21555 pipeline offset. However, Thumb adrl already adjusts for
21556 this, so we need not do it again. */
21557 case BFD_RELOC_ARM_THUMB_ADD
:
21560 case BFD_RELOC_ARM_THUMB_OFFSET
:
21561 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
21562 case BFD_RELOC_ARM_T32_ADD_PC12
:
21563 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21564 return (base
+ 4) & ~3;
21566 /* Thumb branches are simply offset by +4. */
21567 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21568 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21569 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21570 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21571 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21574 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21576 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21577 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21578 && ARM_IS_FUNC (fixP
->fx_addsy
)
21579 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21580 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21583 /* BLX is like branches above, but forces the low two bits of PC to
21585 case BFD_RELOC_THUMB_PCREL_BLX
:
21587 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21588 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21589 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21590 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21591 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21592 return (base
+ 4) & ~3;
21594 /* ARM mode branches are offset by +8. However, the Windows CE
21595 loader expects the relocation not to take this into account. */
21596 case BFD_RELOC_ARM_PCREL_BLX
:
21598 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21599 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21600 && ARM_IS_FUNC (fixP
->fx_addsy
)
21601 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21602 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21605 case BFD_RELOC_ARM_PCREL_CALL
:
21607 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21608 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21609 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21610 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21611 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21614 case BFD_RELOC_ARM_PCREL_BRANCH
:
21615 case BFD_RELOC_ARM_PCREL_JUMP
:
21616 case BFD_RELOC_ARM_PLT32
:
21618 /* When handling fixups immediately, because we have already
21619 discovered the value of a symbol, or the address of the frag involved
21620 we must account for the offset by +8, as the OS loader will never see the reloc.
21621 see fixup_segment() in write.c
21622 The S_IS_EXTERNAL test handles the case of global symbols.
21623 Those need the calculated base, not just the pipe compensation the linker will need. */
21625 && fixP
->fx_addsy
!= NULL
21626 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21627 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
21635 /* ARM mode loads relative to PC are also offset by +8. Unlike
21636 branches, the Windows CE loader *does* expect the relocation
21637 to take this into account. */
21638 case BFD_RELOC_ARM_OFFSET_IMM
:
21639 case BFD_RELOC_ARM_OFFSET_IMM8
:
21640 case BFD_RELOC_ARM_HWLITERAL
:
21641 case BFD_RELOC_ARM_LITERAL
:
21642 case BFD_RELOC_ARM_CP_OFF_IMM
:
21646 /* Other PC-relative relocations are un-offset. */
21652 static bfd_boolean flag_warn_syms
= TRUE
;
21655 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
21657 /* PR 18347 - Warn if the user attempts to create a symbol with the same
21658 name as an ARM instruction. Whilst strictly speaking it is allowed, it
21659 does mean that the resulting code might be very confusing to the reader.
21660 Also this warning can be triggered if the user omits an operand before
21661 an immediate address, eg:
21665 GAS treats this as an assignment of the value of the symbol foo to a
21666 symbol LDR, and so (without this code) it will not issue any kind of
21667 warning or error message.
21669 Note - ARM instructions are case-insensitive but the strings in the hash
21670 table are all stored in lower case, so we must first ensure that name is
21672 if (flag_warn_syms
&& arm_ops_hsh
)
21674 char * nbuf
= strdup (name
);
21677 for (p
= nbuf
; *p
; p
++)
21679 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
21681 static struct hash_control
* already_warned
= NULL
;
21683 if (already_warned
== NULL
)
21684 already_warned
= hash_new ();
21685 /* Only warn about the symbol once. To keep the code
21686 simple we let hash_insert do the lookup for us. */
21687 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
21688 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
21697 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21698 Otherwise we have no need to default values of symbols. */
21701 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
21704 if (name
[0] == '_' && name
[1] == 'G'
21705 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
21709 if (symbol_find (name
))
21710 as_bad (_("GOT already in the symbol table"));
21712 GOT_symbol
= symbol_new (name
, undefined_section
,
21713 (valueT
) 0, & zero_address_frag
);
21723 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21724 computed as two separate immediate values, added together. We
21725 already know that this value cannot be computed by just one ARM
21728 static unsigned int
21729 validate_immediate_twopart (unsigned int val
,
21730 unsigned int * highpart
)
21735 for (i
= 0; i
< 32; i
+= 2)
21736 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
21742 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
21744 else if (a
& 0xff0000)
21746 if (a
& 0xff000000)
21748 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
21752 gas_assert (a
& 0xff000000);
21753 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
21756 return (a
& 0xff) | (i
<< 7);
21763 validate_offset_imm (unsigned int val
, int hwse
)
21765 if ((hwse
&& val
> 255) || val
> 4095)
21770 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21771 negative immediate constant by altering the instruction. A bit of
21776 by inverting the second operand, and
21779 by negating the second operand. */
21782 negate_data_op (unsigned long * instruction
,
21783 unsigned long value
)
21786 unsigned long negated
, inverted
;
21788 negated
= encode_arm_immediate (-value
);
21789 inverted
= encode_arm_immediate (~value
);
21791 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
21794 /* First negates. */
21795 case OPCODE_SUB
: /* ADD <-> SUB */
21796 new_inst
= OPCODE_ADD
;
21801 new_inst
= OPCODE_SUB
;
21805 case OPCODE_CMP
: /* CMP <-> CMN */
21806 new_inst
= OPCODE_CMN
;
21811 new_inst
= OPCODE_CMP
;
21815 /* Now Inverted ops. */
21816 case OPCODE_MOV
: /* MOV <-> MVN */
21817 new_inst
= OPCODE_MVN
;
21822 new_inst
= OPCODE_MOV
;
21826 case OPCODE_AND
: /* AND <-> BIC */
21827 new_inst
= OPCODE_BIC
;
21832 new_inst
= OPCODE_AND
;
21836 case OPCODE_ADC
: /* ADC <-> SBC */
21837 new_inst
= OPCODE_SBC
;
21842 new_inst
= OPCODE_ADC
;
21846 /* We cannot do anything. */
21851 if (value
== (unsigned) FAIL
)
21854 *instruction
&= OPCODE_MASK
;
21855 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
21859 /* Like negate_data_op, but for Thumb-2. */
21861 static unsigned int
21862 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
21866 unsigned int negated
, inverted
;
21868 negated
= encode_thumb32_immediate (-value
);
21869 inverted
= encode_thumb32_immediate (~value
);
21871 rd
= (*instruction
>> 8) & 0xf;
21872 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
21875 /* ADD <-> SUB. Includes CMP <-> CMN. */
21876 case T2_OPCODE_SUB
:
21877 new_inst
= T2_OPCODE_ADD
;
21881 case T2_OPCODE_ADD
:
21882 new_inst
= T2_OPCODE_SUB
;
21886 /* ORR <-> ORN. Includes MOV <-> MVN. */
21887 case T2_OPCODE_ORR
:
21888 new_inst
= T2_OPCODE_ORN
;
21892 case T2_OPCODE_ORN
:
21893 new_inst
= T2_OPCODE_ORR
;
21897 /* AND <-> BIC. TST has no inverted equivalent. */
21898 case T2_OPCODE_AND
:
21899 new_inst
= T2_OPCODE_BIC
;
21906 case T2_OPCODE_BIC
:
21907 new_inst
= T2_OPCODE_AND
;
21912 case T2_OPCODE_ADC
:
21913 new_inst
= T2_OPCODE_SBC
;
21917 case T2_OPCODE_SBC
:
21918 new_inst
= T2_OPCODE_ADC
;
21922 /* We cannot do anything. */
21927 if (value
== (unsigned int)FAIL
)
21930 *instruction
&= T2_OPCODE_MASK
;
21931 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
21935 /* Read a 32-bit thumb instruction from buf. */
21936 static unsigned long
21937 get_thumb32_insn (char * buf
)
21939 unsigned long insn
;
21940 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
21941 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21947 /* We usually want to set the low bit on the address of thumb function
21948 symbols. In particular .word foo - . should have the low bit set.
21949 Generic code tries to fold the difference of two symbols to
21950 a constant. Prevent this and force a relocation when the first symbols
21951 is a thumb function. */
21954 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
21956 if (op
== O_subtract
21957 && l
->X_op
== O_symbol
21958 && r
->X_op
== O_symbol
21959 && THUMB_IS_FUNC (l
->X_add_symbol
))
21961 l
->X_op
= O_subtract
;
21962 l
->X_op_symbol
= r
->X_add_symbol
;
21963 l
->X_add_number
-= r
->X_add_number
;
21967 /* Process as normal. */
21971 /* Encode Thumb2 unconditional branches and calls. The encoding
21972 for the 2 are identical for the immediate values. */
21975 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
21977 #define T2I1I2MASK ((1 << 13) | (1 << 11))
21980 addressT S
, I1
, I2
, lo
, hi
;
21982 S
= (value
>> 24) & 0x01;
21983 I1
= (value
>> 23) & 0x01;
21984 I2
= (value
>> 22) & 0x01;
21985 hi
= (value
>> 12) & 0x3ff;
21986 lo
= (value
>> 1) & 0x7ff;
21987 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21988 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21989 newval
|= (S
<< 10) | hi
;
21990 newval2
&= ~T2I1I2MASK
;
21991 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
21992 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21993 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
21997 md_apply_fix (fixS
* fixP
,
22001 offsetT value
= * valP
;
22003 unsigned int newimm
;
22004 unsigned long temp
;
22006 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22008 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22010 /* Note whether this will delete the relocation. */
22012 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22015 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22016 consistency with the behaviour on 32-bit hosts. Remember value
22018 value
&= 0xffffffff;
22019 value
^= 0x80000000;
22020 value
-= 0x80000000;
22023 fixP
->fx_addnumber
= value
;
22025 /* Same treatment for fixP->fx_offset. */
22026 fixP
->fx_offset
&= 0xffffffff;
22027 fixP
->fx_offset
^= 0x80000000;
22028 fixP
->fx_offset
-= 0x80000000;
22030 switch (fixP
->fx_r_type
)
22032 case BFD_RELOC_NONE
:
22033 /* This will need to go in the object file. */
22037 case BFD_RELOC_ARM_IMMEDIATE
:
22038 /* We claim that this fixup has been processed here,
22039 even if in fact we generate an error because we do
22040 not have a reloc for it, so tc_gen_reloc will reject it. */
22043 if (fixP
->fx_addsy
)
22045 const char *msg
= 0;
22047 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22048 msg
= _("undefined symbol %s used as an immediate value");
22049 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22050 msg
= _("symbol %s is in a different section");
22051 else if (S_IS_WEAK (fixP
->fx_addsy
))
22052 msg
= _("symbol %s is weak and may be overridden later");
22056 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22057 msg
, S_GET_NAME (fixP
->fx_addsy
));
22062 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22064 /* If the offset is negative, we should use encoding A2 for ADR. */
22065 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22066 newimm
= negate_data_op (&temp
, value
);
22069 newimm
= encode_arm_immediate (value
);
22071 /* If the instruction will fail, see if we can fix things up by
22072 changing the opcode. */
22073 if (newimm
== (unsigned int) FAIL
)
22074 newimm
= negate_data_op (&temp
, value
);
22077 if (newimm
== (unsigned int) FAIL
)
22079 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22080 _("invalid constant (%lx) after fixup"),
22081 (unsigned long) value
);
22085 newimm
|= (temp
& 0xfffff000);
22086 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22089 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22091 unsigned int highpart
= 0;
22092 unsigned int newinsn
= 0xe1a00000; /* nop. */
22094 if (fixP
->fx_addsy
)
22096 const char *msg
= 0;
22098 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22099 msg
= _("undefined symbol %s used as an immediate value");
22100 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22101 msg
= _("symbol %s is in a different section");
22102 else if (S_IS_WEAK (fixP
->fx_addsy
))
22103 msg
= _("symbol %s is weak and may be overridden later");
22107 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22108 msg
, S_GET_NAME (fixP
->fx_addsy
));
22113 newimm
= encode_arm_immediate (value
);
22114 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22116 /* If the instruction will fail, see if we can fix things up by
22117 changing the opcode. */
22118 if (newimm
== (unsigned int) FAIL
22119 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22121 /* No ? OK - try using two ADD instructions to generate
22123 newimm
= validate_immediate_twopart (value
, & highpart
);
22125 /* Yes - then make sure that the second instruction is
22127 if (newimm
!= (unsigned int) FAIL
)
22129 /* Still No ? Try using a negated value. */
22130 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22131 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22132 /* Otherwise - give up. */
22135 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22136 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22141 /* Replace the first operand in the 2nd instruction (which
22142 is the PC) with the destination register. We have
22143 already added in the PC in the first instruction and we
22144 do not want to do it again. */
22145 newinsn
&= ~ 0xf0000;
22146 newinsn
|= ((newinsn
& 0x0f000) << 4);
22149 newimm
|= (temp
& 0xfffff000);
22150 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22152 highpart
|= (newinsn
& 0xfffff000);
22153 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22157 case BFD_RELOC_ARM_OFFSET_IMM
:
22158 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22161 case BFD_RELOC_ARM_LITERAL
:
22167 if (validate_offset_imm (value
, 0) == FAIL
)
22169 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22170 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22171 _("invalid literal constant: pool needs to be closer"));
22173 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22174 _("bad immediate value for offset (%ld)"),
22179 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22181 newval
&= 0xfffff000;
22184 newval
&= 0xff7ff000;
22185 newval
|= value
| (sign
? INDEX_UP
: 0);
22187 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22190 case BFD_RELOC_ARM_OFFSET_IMM8
:
22191 case BFD_RELOC_ARM_HWLITERAL
:
22197 if (validate_offset_imm (value
, 1) == FAIL
)
22199 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
22200 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22201 _("invalid literal constant: pool needs to be closer"));
22203 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22204 _("bad immediate value for 8-bit offset (%ld)"),
22209 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22211 newval
&= 0xfffff0f0;
22214 newval
&= 0xff7ff0f0;
22215 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
22217 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22220 case BFD_RELOC_ARM_T32_OFFSET_U8
:
22221 if (value
< 0 || value
> 1020 || value
% 4 != 0)
22222 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22223 _("bad immediate value for offset (%ld)"), (long) value
);
22226 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
22228 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
22231 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22232 /* This is a complicated relocation used for all varieties of Thumb32
22233 load/store instruction with immediate offset:
22235 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22236 *4, optional writeback(W)
22237 (doubleword load/store)
22239 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22240 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22241 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22242 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22243 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22245 Uppercase letters indicate bits that are already encoded at
22246 this point. Lowercase letters are our problem. For the
22247 second block of instructions, the secondary opcode nybble
22248 (bits 8..11) is present, and bit 23 is zero, even if this is
22249 a PC-relative operation. */
22250 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22252 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
22254 if ((newval
& 0xf0000000) == 0xe0000000)
22256 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22258 newval
|= (1 << 23);
22261 if (value
% 4 != 0)
22263 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22264 _("offset not a multiple of 4"));
22270 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22271 _("offset out of range"));
22276 else if ((newval
& 0x000f0000) == 0x000f0000)
22278 /* PC-relative, 12-bit offset. */
22280 newval
|= (1 << 23);
22285 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22286 _("offset out of range"));
22291 else if ((newval
& 0x00000100) == 0x00000100)
22293 /* Writeback: 8-bit, +/- offset. */
22295 newval
|= (1 << 9);
22300 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22301 _("offset out of range"));
22306 else if ((newval
& 0x00000f00) == 0x00000e00)
22308 /* T-instruction: positive 8-bit offset. */
22309 if (value
< 0 || value
> 0xff)
22311 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22312 _("offset out of range"));
22320 /* Positive 12-bit or negative 8-bit offset. */
22324 newval
|= (1 << 23);
22334 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22335 _("offset out of range"));
22342 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
22343 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
22346 case BFD_RELOC_ARM_SHIFT_IMM
:
22347 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22348 if (((unsigned long) value
) > 32
22350 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
22352 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22353 _("shift expression is too large"));
22358 /* Shifts of zero must be done as lsl. */
22360 else if (value
== 32)
22362 newval
&= 0xfffff07f;
22363 newval
|= (value
& 0x1f) << 7;
22364 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22367 case BFD_RELOC_ARM_T32_IMMEDIATE
:
22368 case BFD_RELOC_ARM_T32_ADD_IMM
:
22369 case BFD_RELOC_ARM_T32_IMM12
:
22370 case BFD_RELOC_ARM_T32_ADD_PC12
:
22371 /* We claim that this fixup has been processed here,
22372 even if in fact we generate an error because we do
22373 not have a reloc for it, so tc_gen_reloc will reject it. */
22377 && ! S_IS_DEFINED (fixP
->fx_addsy
))
22379 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22380 _("undefined symbol %s used as an immediate value"),
22381 S_GET_NAME (fixP
->fx_addsy
));
22385 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22387 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
22390 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
22391 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22393 newimm
= encode_thumb32_immediate (value
);
22394 if (newimm
== (unsigned int) FAIL
)
22395 newimm
= thumb32_negate_data_op (&newval
, value
);
22397 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
22398 && newimm
== (unsigned int) FAIL
)
22400 /* Turn add/sum into addw/subw. */
22401 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22402 newval
= (newval
& 0xfeffffff) | 0x02000000;
22403 /* No flat 12-bit imm encoding for addsw/subsw. */
22404 if ((newval
& 0x00100000) == 0)
22406 /* 12 bit immediate for addw/subw. */
22410 newval
^= 0x00a00000;
22413 newimm
= (unsigned int) FAIL
;
22419 if (newimm
== (unsigned int)FAIL
)
22421 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22422 _("invalid constant (%lx) after fixup"),
22423 (unsigned long) value
);
22427 newval
|= (newimm
& 0x800) << 15;
22428 newval
|= (newimm
& 0x700) << 4;
22429 newval
|= (newimm
& 0x0ff);
22431 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
22432 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
22435 case BFD_RELOC_ARM_SMC
:
22436 if (((unsigned long) value
) > 0xffff)
22437 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22438 _("invalid smc expression"));
22439 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22440 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22441 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22444 case BFD_RELOC_ARM_HVC
:
22445 if (((unsigned long) value
) > 0xffff)
22446 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22447 _("invalid hvc expression"));
22448 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22449 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22450 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22453 case BFD_RELOC_ARM_SWI
:
22454 if (fixP
->tc_fix_data
!= 0)
22456 if (((unsigned long) value
) > 0xff)
22457 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22458 _("invalid swi expression"));
22459 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22461 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22465 if (((unsigned long) value
) > 0x00ffffff)
22466 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22467 _("invalid swi expression"));
22468 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22470 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22474 case BFD_RELOC_ARM_MULTI
:
22475 if (((unsigned long) value
) > 0xffff)
22476 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22477 _("invalid expression in load/store multiple"));
22478 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
22479 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22483 case BFD_RELOC_ARM_PCREL_CALL
:
22485 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22487 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22488 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22489 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22490 /* Flip the bl to blx. This is a simple flip
22491 bit here because we generate PCREL_CALL for
22492 unconditional bls. */
22494 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22495 newval
= newval
| 0x10000000;
22496 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22502 goto arm_branch_common
;
22504 case BFD_RELOC_ARM_PCREL_JUMP
:
22505 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22507 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22508 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22509 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22511 /* This would map to a bl<cond>, b<cond>,
22512 b<always> to a Thumb function. We
22513 need to force a relocation for this particular
22515 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22519 case BFD_RELOC_ARM_PLT32
:
22521 case BFD_RELOC_ARM_PCREL_BRANCH
:
22523 goto arm_branch_common
;
22525 case BFD_RELOC_ARM_PCREL_BLX
:
22528 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22530 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22531 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22532 && ARM_IS_FUNC (fixP
->fx_addsy
))
22534 /* Flip the blx to a bl and warn. */
22535 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22536 newval
= 0xeb000000;
22537 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22538 _("blx to '%s' an ARM ISA state function changed to bl"),
22540 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22546 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
22547 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
22551 /* We are going to store value (shifted right by two) in the
22552 instruction, in a 24 bit, signed field. Bits 26 through 32 either
22553 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
22554 also be be clear. */
22556 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22557 _("misaligned branch destination"));
22558 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
22559 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
22560 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22562 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22564 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22565 newval
|= (value
>> 2) & 0x00ffffff;
22566 /* Set the H bit on BLX instructions. */
22570 newval
|= 0x01000000;
22572 newval
&= ~0x01000000;
22574 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22578 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
22579 /* CBZ can only branch forward. */
22581 /* Attempts to use CBZ to branch to the next instruction
22582 (which, strictly speaking, are prohibited) will be turned into
22585 FIXME: It may be better to remove the instruction completely and
22586 perform relaxation. */
22589 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22590 newval
= 0xbf00; /* NOP encoding T1 */
22591 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22596 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22598 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22600 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22601 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
22602 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22607 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
22608 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
22609 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22611 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22613 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22614 newval
|= (value
& 0x1ff) >> 1;
22615 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22619 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
22620 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
22621 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22623 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22625 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22626 newval
|= (value
& 0xfff) >> 1;
22627 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22631 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22633 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22634 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22635 && ARM_IS_FUNC (fixP
->fx_addsy
)
22636 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22638 /* Force a relocation for a branch 20 bits wide. */
22641 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
22642 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22643 _("conditional branch out of range"));
22645 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22648 addressT S
, J1
, J2
, lo
, hi
;
22650 S
= (value
& 0x00100000) >> 20;
22651 J2
= (value
& 0x00080000) >> 19;
22652 J1
= (value
& 0x00040000) >> 18;
22653 hi
= (value
& 0x0003f000) >> 12;
22654 lo
= (value
& 0x00000ffe) >> 1;
22656 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22657 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22658 newval
|= (S
<< 10) | hi
;
22659 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
22660 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22661 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22665 case BFD_RELOC_THUMB_PCREL_BLX
:
22666 /* If there is a blx from a thumb state function to
22667 another thumb function flip this to a bl and warn
22671 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22672 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22673 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22675 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22676 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22677 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22679 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22680 newval
= newval
| 0x1000;
22681 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22682 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22687 goto thumb_bl_common
;
22689 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22690 /* A bl from Thumb state ISA to an internal ARM state function
22691 is converted to a blx. */
22693 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22694 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22695 && ARM_IS_FUNC (fixP
->fx_addsy
)
22696 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22698 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22699 newval
= newval
& ~0x1000;
22700 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22701 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
22707 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22708 /* For a BLX instruction, make sure that the relocation is rounded up
22709 to a word boundary. This follows the semantics of the instruction
22710 which specifies that bit 1 of the target address will come from bit
22711 1 of the base address. */
22712 value
= (value
+ 3) & ~ 3;
22715 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
22716 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22717 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22720 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
22722 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
22723 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22724 else if ((value
& ~0x1ffffff)
22725 && ((value
& ~0x1ffffff) != ~0x1ffffff))
22726 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22727 _("Thumb2 branch out of range"));
22730 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22731 encode_thumb2_b_bl_offset (buf
, value
);
22735 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22736 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
22737 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22739 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22740 encode_thumb2_b_bl_offset (buf
, value
);
22745 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22750 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22751 md_number_to_chars (buf
, value
, 2);
22755 case BFD_RELOC_ARM_TLS_CALL
:
22756 case BFD_RELOC_ARM_THM_TLS_CALL
:
22757 case BFD_RELOC_ARM_TLS_DESCSEQ
:
22758 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
22759 case BFD_RELOC_ARM_TLS_GOTDESC
:
22760 case BFD_RELOC_ARM_TLS_GD32
:
22761 case BFD_RELOC_ARM_TLS_LE32
:
22762 case BFD_RELOC_ARM_TLS_IE32
:
22763 case BFD_RELOC_ARM_TLS_LDM32
:
22764 case BFD_RELOC_ARM_TLS_LDO32
:
22765 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
22768 case BFD_RELOC_ARM_GOT32
:
22769 case BFD_RELOC_ARM_GOTOFF
:
22772 case BFD_RELOC_ARM_GOT_PREL
:
22773 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22774 md_number_to_chars (buf
, value
, 4);
22777 case BFD_RELOC_ARM_TARGET2
:
22778 /* TARGET2 is not partial-inplace, so we need to write the
22779 addend here for REL targets, because it won't be written out
22780 during reloc processing later. */
22781 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22782 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
22786 case BFD_RELOC_RVA
:
22788 case BFD_RELOC_ARM_TARGET1
:
22789 case BFD_RELOC_ARM_ROSEGREL32
:
22790 case BFD_RELOC_ARM_SBREL32
:
22791 case BFD_RELOC_32_PCREL
:
22793 case BFD_RELOC_32_SECREL
:
22795 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22797 /* For WinCE we only do this for pcrel fixups. */
22798 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
22800 md_number_to_chars (buf
, value
, 4);
22804 case BFD_RELOC_ARM_PREL31
:
22805 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22807 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
22808 if ((value
^ (value
>> 1)) & 0x40000000)
22810 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22811 _("rel31 relocation overflow"));
22813 newval
|= value
& 0x7fffffff;
22814 md_number_to_chars (buf
, newval
, 4);
22819 case BFD_RELOC_ARM_CP_OFF_IMM
:
22820 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22821 if (value
< -1023 || value
> 1023 || (value
& 3))
22822 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22823 _("co-processor offset out of range"));
22828 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22829 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22830 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22832 newval
= get_thumb32_insn (buf
);
22834 newval
&= 0xffffff00;
22837 newval
&= 0xff7fff00;
22838 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
22840 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22841 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22842 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22844 put_thumb32_insn (buf
, newval
);
22847 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
22848 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
22849 if (value
< -255 || value
> 255)
22850 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22851 _("co-processor offset out of range"));
22853 goto cp_off_common
;
22855 case BFD_RELOC_ARM_THUMB_OFFSET
:
22856 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22857 /* Exactly what ranges, and where the offset is inserted depends
22858 on the type of instruction, we can establish this from the
22860 switch (newval
>> 12)
22862 case 4: /* PC load. */
22863 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
22864 forced to zero for these loads; md_pcrel_from has already
22865 compensated for this. */
22867 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22868 _("invalid offset, target not word aligned (0x%08lX)"),
22869 (((unsigned long) fixP
->fx_frag
->fr_address
22870 + (unsigned long) fixP
->fx_where
) & ~3)
22871 + (unsigned long) value
);
22873 if (value
& ~0x3fc)
22874 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22875 _("invalid offset, value too big (0x%08lX)"),
22878 newval
|= value
>> 2;
22881 case 9: /* SP load/store. */
22882 if (value
& ~0x3fc)
22883 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22884 _("invalid offset, value too big (0x%08lX)"),
22886 newval
|= value
>> 2;
22889 case 6: /* Word load/store. */
22891 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22892 _("invalid offset, value too big (0x%08lX)"),
22894 newval
|= value
<< 4; /* 6 - 2. */
22897 case 7: /* Byte load/store. */
22899 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22900 _("invalid offset, value too big (0x%08lX)"),
22902 newval
|= value
<< 6;
22905 case 8: /* Halfword load/store. */
22907 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22908 _("invalid offset, value too big (0x%08lX)"),
22910 newval
|= value
<< 5; /* 6 - 1. */
22914 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22915 "Unable to process relocation for thumb opcode: %lx",
22916 (unsigned long) newval
);
22919 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22922 case BFD_RELOC_ARM_THUMB_ADD
:
22923 /* This is a complicated relocation, since we use it for all of
22924 the following immediate relocations:
22928 9bit ADD/SUB SP word-aligned
22929 10bit ADD PC/SP word-aligned
22931 The type of instruction being processed is encoded in the
22938 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22940 int rd
= (newval
>> 4) & 0xf;
22941 int rs
= newval
& 0xf;
22942 int subtract
= !!(newval
& 0x8000);
22944 /* Check for HI regs, only very restricted cases allowed:
22945 Adjusting SP, and using PC or SP to get an address. */
22946 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
22947 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
22948 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22949 _("invalid Hi register with immediate"));
22951 /* If value is negative, choose the opposite instruction. */
22955 subtract
= !subtract
;
22957 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22958 _("immediate value out of range"));
22963 if (value
& ~0x1fc)
22964 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22965 _("invalid immediate for stack address calculation"));
22966 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
22967 newval
|= value
>> 2;
22969 else if (rs
== REG_PC
|| rs
== REG_SP
)
22971 if (subtract
|| value
& ~0x3fc)
22972 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22973 _("invalid immediate for address calculation (value = 0x%08lX)"),
22974 (unsigned long) value
);
22975 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
22977 newval
|= value
>> 2;
22982 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22983 _("immediate value out of range"));
22984 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
22985 newval
|= (rd
<< 8) | value
;
22990 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22991 _("immediate value out of range"));
22992 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
22993 newval
|= rd
| (rs
<< 3) | (value
<< 6);
22996 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22999 case BFD_RELOC_ARM_THUMB_IMM
:
23000 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23001 if (value
< 0 || value
> 255)
23002 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23003 _("invalid immediate: %ld is out of range"),
23006 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23009 case BFD_RELOC_ARM_THUMB_SHIFT
:
23010 /* 5bit shift value (0..32). LSL cannot take 32. */
23011 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23012 temp
= newval
& 0xf800;
23013 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23014 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23015 _("invalid shift value: %ld"), (long) value
);
23016 /* Shifts of zero must be encoded as LSL. */
23018 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23019 /* Shifts of 32 are encoded as zero. */
23020 else if (value
== 32)
23022 newval
|= value
<< 6;
23023 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23026 case BFD_RELOC_VTABLE_INHERIT
:
23027 case BFD_RELOC_VTABLE_ENTRY
:
23031 case BFD_RELOC_ARM_MOVW
:
23032 case BFD_RELOC_ARM_MOVT
:
23033 case BFD_RELOC_ARM_THUMB_MOVW
:
23034 case BFD_RELOC_ARM_THUMB_MOVT
:
23035 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23037 /* REL format relocations are limited to a 16-bit addend. */
23038 if (!fixP
->fx_done
)
23040 if (value
< -0x8000 || value
> 0x7fff)
23041 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23042 _("offset out of range"));
23044 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23045 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23050 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23051 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23053 newval
= get_thumb32_insn (buf
);
23054 newval
&= 0xfbf08f00;
23055 newval
|= (value
& 0xf000) << 4;
23056 newval
|= (value
& 0x0800) << 15;
23057 newval
|= (value
& 0x0700) << 4;
23058 newval
|= (value
& 0x00ff);
23059 put_thumb32_insn (buf
, newval
);
23063 newval
= md_chars_to_number (buf
, 4);
23064 newval
&= 0xfff0f000;
23065 newval
|= value
& 0x0fff;
23066 newval
|= (value
& 0xf000) << 4;
23067 md_number_to_chars (buf
, newval
, 4);
23072 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23073 case BFD_RELOC_ARM_ALU_PC_G0
:
23074 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23075 case BFD_RELOC_ARM_ALU_PC_G1
:
23076 case BFD_RELOC_ARM_ALU_PC_G2
:
23077 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23078 case BFD_RELOC_ARM_ALU_SB_G0
:
23079 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23080 case BFD_RELOC_ARM_ALU_SB_G1
:
23081 case BFD_RELOC_ARM_ALU_SB_G2
:
23082 gas_assert (!fixP
->fx_done
);
23083 if (!seg
->use_rela_p
)
23086 bfd_vma encoded_addend
;
23087 bfd_vma addend_abs
= abs (value
);
23089 /* Check that the absolute value of the addend can be
23090 expressed as an 8-bit constant plus a rotation. */
23091 encoded_addend
= encode_arm_immediate (addend_abs
);
23092 if (encoded_addend
== (unsigned int) FAIL
)
23093 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23094 _("the offset 0x%08lX is not representable"),
23095 (unsigned long) addend_abs
);
23097 /* Extract the instruction. */
23098 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23100 /* If the addend is positive, use an ADD instruction.
23101 Otherwise use a SUB. Take care not to destroy the S bit. */
23102 insn
&= 0xff1fffff;
23108 /* Place the encoded addend into the first 12 bits of the
23110 insn
&= 0xfffff000;
23111 insn
|= encoded_addend
;
23113 /* Update the instruction. */
23114 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23118 case BFD_RELOC_ARM_LDR_PC_G0
:
23119 case BFD_RELOC_ARM_LDR_PC_G1
:
23120 case BFD_RELOC_ARM_LDR_PC_G2
:
23121 case BFD_RELOC_ARM_LDR_SB_G0
:
23122 case BFD_RELOC_ARM_LDR_SB_G1
:
23123 case BFD_RELOC_ARM_LDR_SB_G2
:
23124 gas_assert (!fixP
->fx_done
);
23125 if (!seg
->use_rela_p
)
23128 bfd_vma addend_abs
= abs (value
);
23130 /* Check that the absolute value of the addend can be
23131 encoded in 12 bits. */
23132 if (addend_abs
>= 0x1000)
23133 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23134 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23135 (unsigned long) addend_abs
);
23137 /* Extract the instruction. */
23138 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23140 /* If the addend is negative, clear bit 23 of the instruction.
23141 Otherwise set it. */
23143 insn
&= ~(1 << 23);
23147 /* Place the absolute value of the addend into the first 12 bits
23148 of the instruction. */
23149 insn
&= 0xfffff000;
23150 insn
|= addend_abs
;
23152 /* Update the instruction. */
23153 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23157 case BFD_RELOC_ARM_LDRS_PC_G0
:
23158 case BFD_RELOC_ARM_LDRS_PC_G1
:
23159 case BFD_RELOC_ARM_LDRS_PC_G2
:
23160 case BFD_RELOC_ARM_LDRS_SB_G0
:
23161 case BFD_RELOC_ARM_LDRS_SB_G1
:
23162 case BFD_RELOC_ARM_LDRS_SB_G2
:
23163 gas_assert (!fixP
->fx_done
);
23164 if (!seg
->use_rela_p
)
23167 bfd_vma addend_abs
= abs (value
);
23169 /* Check that the absolute value of the addend can be
23170 encoded in 8 bits. */
23171 if (addend_abs
>= 0x100)
23172 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23173 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23174 (unsigned long) addend_abs
);
23176 /* Extract the instruction. */
23177 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23179 /* If the addend is negative, clear bit 23 of the instruction.
23180 Otherwise set it. */
23182 insn
&= ~(1 << 23);
23186 /* Place the first four bits of the absolute value of the addend
23187 into the first 4 bits of the instruction, and the remaining
23188 four into bits 8 .. 11. */
23189 insn
&= 0xfffff0f0;
23190 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
23192 /* Update the instruction. */
23193 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23197 case BFD_RELOC_ARM_LDC_PC_G0
:
23198 case BFD_RELOC_ARM_LDC_PC_G1
:
23199 case BFD_RELOC_ARM_LDC_PC_G2
:
23200 case BFD_RELOC_ARM_LDC_SB_G0
:
23201 case BFD_RELOC_ARM_LDC_SB_G1
:
23202 case BFD_RELOC_ARM_LDC_SB_G2
:
23203 gas_assert (!fixP
->fx_done
);
23204 if (!seg
->use_rela_p
)
23207 bfd_vma addend_abs
= abs (value
);
23209 /* Check that the absolute value of the addend is a multiple of
23210 four and, when divided by four, fits in 8 bits. */
23211 if (addend_abs
& 0x3)
23212 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23213 _("bad offset 0x%08lX (must be word-aligned)"),
23214 (unsigned long) addend_abs
);
23216 if ((addend_abs
>> 2) > 0xff)
23217 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23218 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
23219 (unsigned long) addend_abs
);
23221 /* Extract the instruction. */
23222 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23224 /* If the addend is negative, clear bit 23 of the instruction.
23225 Otherwise set it. */
23227 insn
&= ~(1 << 23);
23231 /* Place the addend (divided by four) into the first eight
23232 bits of the instruction. */
23233 insn
&= 0xfffffff0;
23234 insn
|= addend_abs
>> 2;
23236 /* Update the instruction. */
23237 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23241 case BFD_RELOC_ARM_V4BX
:
23242 /* This will need to go in the object file. */
23246 case BFD_RELOC_UNUSED
:
23248 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23249 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
23253 /* Translate internal representation of relocation info to BFD target
23257 tc_gen_reloc (asection
*section
, fixS
*fixp
)
23260 bfd_reloc_code_real_type code
;
23262 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
23264 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
23265 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
23266 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
23268 if (fixp
->fx_pcrel
)
23270 if (section
->use_rela_p
)
23271 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
23273 fixp
->fx_offset
= reloc
->address
;
23275 reloc
->addend
= fixp
->fx_offset
;
23277 switch (fixp
->fx_r_type
)
23280 if (fixp
->fx_pcrel
)
23282 code
= BFD_RELOC_8_PCREL
;
23287 if (fixp
->fx_pcrel
)
23289 code
= BFD_RELOC_16_PCREL
;
23294 if (fixp
->fx_pcrel
)
23296 code
= BFD_RELOC_32_PCREL
;
23300 case BFD_RELOC_ARM_MOVW
:
23301 if (fixp
->fx_pcrel
)
23303 code
= BFD_RELOC_ARM_MOVW_PCREL
;
23307 case BFD_RELOC_ARM_MOVT
:
23308 if (fixp
->fx_pcrel
)
23310 code
= BFD_RELOC_ARM_MOVT_PCREL
;
23314 case BFD_RELOC_ARM_THUMB_MOVW
:
23315 if (fixp
->fx_pcrel
)
23317 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
23321 case BFD_RELOC_ARM_THUMB_MOVT
:
23322 if (fixp
->fx_pcrel
)
23324 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
23328 case BFD_RELOC_NONE
:
23329 case BFD_RELOC_ARM_PCREL_BRANCH
:
23330 case BFD_RELOC_ARM_PCREL_BLX
:
23331 case BFD_RELOC_RVA
:
23332 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
23333 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
23334 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
23335 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23336 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23337 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23338 case BFD_RELOC_VTABLE_ENTRY
:
23339 case BFD_RELOC_VTABLE_INHERIT
:
23341 case BFD_RELOC_32_SECREL
:
23343 code
= fixp
->fx_r_type
;
23346 case BFD_RELOC_THUMB_PCREL_BLX
:
23348 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23349 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23352 code
= BFD_RELOC_THUMB_PCREL_BLX
;
23355 case BFD_RELOC_ARM_LITERAL
:
23356 case BFD_RELOC_ARM_HWLITERAL
:
23357 /* If this is called then the a literal has
23358 been referenced across a section boundary. */
23359 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23360 _("literal referenced across section boundary"));
23364 case BFD_RELOC_ARM_TLS_CALL
:
23365 case BFD_RELOC_ARM_THM_TLS_CALL
:
23366 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23367 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23368 case BFD_RELOC_ARM_GOT32
:
23369 case BFD_RELOC_ARM_GOTOFF
:
23370 case BFD_RELOC_ARM_GOT_PREL
:
23371 case BFD_RELOC_ARM_PLT32
:
23372 case BFD_RELOC_ARM_TARGET1
:
23373 case BFD_RELOC_ARM_ROSEGREL32
:
23374 case BFD_RELOC_ARM_SBREL32
:
23375 case BFD_RELOC_ARM_PREL31
:
23376 case BFD_RELOC_ARM_TARGET2
:
23377 case BFD_RELOC_ARM_TLS_LE32
:
23378 case BFD_RELOC_ARM_TLS_LDO32
:
23379 case BFD_RELOC_ARM_PCREL_CALL
:
23380 case BFD_RELOC_ARM_PCREL_JUMP
:
23381 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23382 case BFD_RELOC_ARM_ALU_PC_G0
:
23383 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23384 case BFD_RELOC_ARM_ALU_PC_G1
:
23385 case BFD_RELOC_ARM_ALU_PC_G2
:
23386 case BFD_RELOC_ARM_LDR_PC_G0
:
23387 case BFD_RELOC_ARM_LDR_PC_G1
:
23388 case BFD_RELOC_ARM_LDR_PC_G2
:
23389 case BFD_RELOC_ARM_LDRS_PC_G0
:
23390 case BFD_RELOC_ARM_LDRS_PC_G1
:
23391 case BFD_RELOC_ARM_LDRS_PC_G2
:
23392 case BFD_RELOC_ARM_LDC_PC_G0
:
23393 case BFD_RELOC_ARM_LDC_PC_G1
:
23394 case BFD_RELOC_ARM_LDC_PC_G2
:
23395 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23396 case BFD_RELOC_ARM_ALU_SB_G0
:
23397 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23398 case BFD_RELOC_ARM_ALU_SB_G1
:
23399 case BFD_RELOC_ARM_ALU_SB_G2
:
23400 case BFD_RELOC_ARM_LDR_SB_G0
:
23401 case BFD_RELOC_ARM_LDR_SB_G1
:
23402 case BFD_RELOC_ARM_LDR_SB_G2
:
23403 case BFD_RELOC_ARM_LDRS_SB_G0
:
23404 case BFD_RELOC_ARM_LDRS_SB_G1
:
23405 case BFD_RELOC_ARM_LDRS_SB_G2
:
23406 case BFD_RELOC_ARM_LDC_SB_G0
:
23407 case BFD_RELOC_ARM_LDC_SB_G1
:
23408 case BFD_RELOC_ARM_LDC_SB_G2
:
23409 case BFD_RELOC_ARM_V4BX
:
23410 code
= fixp
->fx_r_type
;
23413 case BFD_RELOC_ARM_TLS_GOTDESC
:
23414 case BFD_RELOC_ARM_TLS_GD32
:
23415 case BFD_RELOC_ARM_TLS_IE32
:
23416 case BFD_RELOC_ARM_TLS_LDM32
:
23417 /* BFD will include the symbol's address in the addend.
23418 But we don't want that, so subtract it out again here. */
23419 if (!S_IS_COMMON (fixp
->fx_addsy
))
23420 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
23421 code
= fixp
->fx_r_type
;
23425 case BFD_RELOC_ARM_IMMEDIATE
:
23426 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23427 _("internal relocation (type: IMMEDIATE) not fixed up"));
23430 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23431 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23432 _("ADRL used for a symbol not defined in the same file"));
23435 case BFD_RELOC_ARM_OFFSET_IMM
:
23436 if (section
->use_rela_p
)
23438 code
= fixp
->fx_r_type
;
23442 if (fixp
->fx_addsy
!= NULL
23443 && !S_IS_DEFINED (fixp
->fx_addsy
)
23444 && S_IS_LOCAL (fixp
->fx_addsy
))
23446 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23447 _("undefined local label `%s'"),
23448 S_GET_NAME (fixp
->fx_addsy
));
23452 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23453 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
23460 switch (fixp
->fx_r_type
)
23462 case BFD_RELOC_NONE
: type
= "NONE"; break;
23463 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
23464 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
23465 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
23466 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
23467 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
23468 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
23469 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
23470 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
23471 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
23472 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
23473 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
23474 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
23475 default: type
= _("<unknown>"); break;
23477 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23478 _("cannot represent %s relocation in this object file format"),
23485 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
23487 && fixp
->fx_addsy
== GOT_symbol
)
23489 code
= BFD_RELOC_ARM_GOTPC
;
23490 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
23494 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
23496 if (reloc
->howto
== NULL
)
23498 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23499 _("cannot represent %s relocation in this object file format"),
23500 bfd_get_reloc_code_name (code
));
23504 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
23505 vtable entry to be used in the relocation's section offset. */
23506 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23507 reloc
->address
= fixp
->fx_offset
;
23512 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
23515 cons_fix_new_arm (fragS
* frag
,
23519 bfd_reloc_code_real_type reloc
)
23524 FIXME: @@ Should look at CPU word size. */
23528 reloc
= BFD_RELOC_8
;
23531 reloc
= BFD_RELOC_16
;
23535 reloc
= BFD_RELOC_32
;
23538 reloc
= BFD_RELOC_64
;
23543 if (exp
->X_op
== O_secrel
)
23545 exp
->X_op
= O_symbol
;
23546 reloc
= BFD_RELOC_32_SECREL
;
23550 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
23553 #if defined (OBJ_COFF)
23555 arm_validate_fix (fixS
* fixP
)
23557 /* If the destination of the branch is a defined symbol which does not have
23558 the THUMB_FUNC attribute, then we must be calling a function which has
23559 the (interfacearm) attribute. We look for the Thumb entry point to that
23560 function and change the branch to refer to that function instead. */
23561 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
23562 && fixP
->fx_addsy
!= NULL
23563 && S_IS_DEFINED (fixP
->fx_addsy
)
23564 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
23566 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
23573 arm_force_relocation (struct fix
* fixp
)
23575 #if defined (OBJ_COFF) && defined (TE_PE)
23576 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
23580 /* In case we have a call or a branch to a function in ARM ISA mode from
23581 a thumb function or vice-versa force the relocation. These relocations
23582 are cleared off for some cores that might have blx and simple transformations
23586 switch (fixp
->fx_r_type
)
23588 case BFD_RELOC_ARM_PCREL_JUMP
:
23589 case BFD_RELOC_ARM_PCREL_CALL
:
23590 case BFD_RELOC_THUMB_PCREL_BLX
:
23591 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
23595 case BFD_RELOC_ARM_PCREL_BLX
:
23596 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23597 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23598 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23599 if (ARM_IS_FUNC (fixp
->fx_addsy
))
23608 /* Resolve these relocations even if the symbol is extern or weak.
23609 Technically this is probably wrong due to symbol preemption.
23610 In practice these relocations do not have enough range to be useful
23611 at dynamic link time, and some code (e.g. in the Linux kernel)
23612 expects these references to be resolved. */
23613 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
23614 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
23615 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
23616 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
23617 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23618 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
23619 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
23620 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
23621 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23622 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
23623 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
23624 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
23625 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
23626 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
23629 /* Always leave these relocations for the linker. */
23630 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23631 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23632 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23635 /* Always generate relocations against function symbols. */
23636 if (fixp
->fx_r_type
== BFD_RELOC_32
23638 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
23641 return generic_force_reloc (fixp
);
23644 #if defined (OBJ_ELF) || defined (OBJ_COFF)
23645 /* Relocations against function names must be left unadjusted,
23646 so that the linker can use this information to generate interworking
23647 stubs. The MIPS version of this function
23648 also prevents relocations that are mips-16 specific, but I do not
23649 know why it does this.
23652 There is one other problem that ought to be addressed here, but
23653 which currently is not: Taking the address of a label (rather
23654 than a function) and then later jumping to that address. Such
23655 addresses also ought to have their bottom bit set (assuming that
23656 they reside in Thumb code), but at the moment they will not. */
23659 arm_fix_adjustable (fixS
* fixP
)
23661 if (fixP
->fx_addsy
== NULL
)
23664 /* Preserve relocations against symbols with function type. */
23665 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
23668 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
23669 && fixP
->fx_subsy
== NULL
)
23672 /* We need the symbol name for the VTABLE entries. */
23673 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
23674 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23677 /* Don't allow symbols to be discarded on GOT related relocs. */
23678 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
23679 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
23680 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
23681 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
23682 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
23683 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
23684 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
23685 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
23686 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
23687 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
23688 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
23689 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
23690 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
23691 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
23694 /* Similarly for group relocations. */
23695 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23696 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23697 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23700 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23701 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
23702 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23703 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
23704 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
23705 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23706 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
23707 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
23708 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
23713 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23718 elf32_arm_target_format (void)
23721 return (target_big_endian
23722 ? "elf32-bigarm-symbian"
23723 : "elf32-littlearm-symbian");
23724 #elif defined (TE_VXWORKS)
23725 return (target_big_endian
23726 ? "elf32-bigarm-vxworks"
23727 : "elf32-littlearm-vxworks");
23728 #elif defined (TE_NACL)
23729 return (target_big_endian
23730 ? "elf32-bigarm-nacl"
23731 : "elf32-littlearm-nacl");
23733 if (target_big_endian
)
23734 return "elf32-bigarm";
23736 return "elf32-littlearm";
23741 armelf_frob_symbol (symbolS
* symp
,
23744 elf_frob_symbol (symp
, puntp
);
23748 /* MD interface: Finalization. */
23753 literal_pool
* pool
;
23755 /* Ensure that all the IT blocks are properly closed. */
23756 check_it_blocks_finished ();
23758 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
23760 /* Put it at the end of the relevant section. */
23761 subseg_set (pool
->section
, pool
->sub_section
);
23763 arm_elf_change_section ();
23770 /* Remove any excess mapping symbols generated for alignment frags in
23771 SEC. We may have created a mapping symbol before a zero byte
23772 alignment; remove it if there's a mapping symbol after the
23775 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
23776 void *dummy ATTRIBUTE_UNUSED
)
23778 segment_info_type
*seginfo
= seg_info (sec
);
23781 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
23784 for (fragp
= seginfo
->frchainP
->frch_root
;
23786 fragp
= fragp
->fr_next
)
23788 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
23789 fragS
*next
= fragp
->fr_next
;
23791 /* Variable-sized frags have been converted to fixed size by
23792 this point. But if this was variable-sized to start with,
23793 there will be a fixed-size frag after it. So don't handle
23795 if (sym
== NULL
|| next
== NULL
)
23798 if (S_GET_VALUE (sym
) < next
->fr_address
)
23799 /* Not at the end of this frag. */
23801 know (S_GET_VALUE (sym
) == next
->fr_address
);
23805 if (next
->tc_frag_data
.first_map
!= NULL
)
23807 /* Next frag starts with a mapping symbol. Discard this
23809 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
23813 if (next
->fr_next
== NULL
)
23815 /* This mapping symbol is at the end of the section. Discard
23817 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
23818 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
23822 /* As long as we have empty frags without any mapping symbols,
23824 /* If the next frag is non-empty and does not start with a
23825 mapping symbol, then this mapping symbol is required. */
23826 if (next
->fr_address
!= next
->fr_next
->fr_address
)
23829 next
= next
->fr_next
;
23831 while (next
!= NULL
);
23836 /* Adjust the symbol table. This marks Thumb symbols as distinct from
23840 arm_adjust_symtab (void)
23845 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
23847 if (ARM_IS_THUMB (sym
))
23849 if (THUMB_IS_FUNC (sym
))
23851 /* Mark the symbol as a Thumb function. */
23852 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
23853 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
23854 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
23856 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
23857 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
23859 as_bad (_("%s: unexpected function type: %d"),
23860 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
23862 else switch (S_GET_STORAGE_CLASS (sym
))
23865 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
23868 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
23871 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
23879 if (ARM_IS_INTERWORK (sym
))
23880 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
23887 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
23889 if (ARM_IS_THUMB (sym
))
23891 elf_symbol_type
* elf_sym
;
23893 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
23894 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
23896 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
23897 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
23899 /* If it's a .thumb_func, declare it as so,
23900 otherwise tag label as .code 16. */
23901 if (THUMB_IS_FUNC (sym
))
23902 elf_sym
->internal_elf_sym
.st_target_internal
23903 = ST_BRANCH_TO_THUMB
;
23904 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23905 elf_sym
->internal_elf_sym
.st_info
=
23906 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
23911 /* Remove any overlapping mapping symbols generated by alignment frags. */
23912 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
23913 /* Now do generic ELF adjustments. */
23914 elf_adjust_symtab ();
23918 /* MD interface: Initialization. */
23921 set_constant_flonums (void)
23925 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
23926 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
23930 /* Auto-select Thumb mode if it's the only available instruction set for the
23931 given architecture. */
23934 autoselect_thumb_from_cpu_variant (void)
23936 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
23937 opcode_select (16);
23946 if ( (arm_ops_hsh
= hash_new ()) == NULL
23947 || (arm_cond_hsh
= hash_new ()) == NULL
23948 || (arm_shift_hsh
= hash_new ()) == NULL
23949 || (arm_psr_hsh
= hash_new ()) == NULL
23950 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
23951 || (arm_reg_hsh
= hash_new ()) == NULL
23952 || (arm_reloc_hsh
= hash_new ()) == NULL
23953 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
23954 as_fatal (_("virtual memory exhausted"));
23956 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
23957 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
23958 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
23959 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
23960 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
23961 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
23962 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
23963 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
23964 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
23965 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
23966 (void *) (v7m_psrs
+ i
));
23967 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
23968 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
23970 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
23972 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
23973 (void *) (barrier_opt_names
+ i
));
23975 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
23977 struct reloc_entry
* entry
= reloc_names
+ i
;
23979 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
23980 /* This makes encode_branch() use the EABI versions of this relocation. */
23981 entry
->reloc
= BFD_RELOC_UNUSED
;
23983 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
23987 set_constant_flonums ();
23989 /* Set the cpu variant based on the command-line options. We prefer
23990 -mcpu= over -march= if both are set (as for GCC); and we prefer
23991 -mfpu= over any other way of setting the floating point unit.
23992 Use of legacy options with new options are faulted. */
23995 if (mcpu_cpu_opt
|| march_cpu_opt
)
23996 as_bad (_("use of old and new-style options to set CPU type"));
23998 mcpu_cpu_opt
= legacy_cpu
;
24000 else if (!mcpu_cpu_opt
)
24001 mcpu_cpu_opt
= march_cpu_opt
;
24006 as_bad (_("use of old and new-style options to set FPU type"));
24008 mfpu_opt
= legacy_fpu
;
24010 else if (!mfpu_opt
)
24012 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24013 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24014 /* Some environments specify a default FPU. If they don't, infer it
24015 from the processor. */
24017 mfpu_opt
= mcpu_fpu_opt
;
24019 mfpu_opt
= march_fpu_opt
;
24021 mfpu_opt
= &fpu_default
;
24027 if (mcpu_cpu_opt
!= NULL
)
24028 mfpu_opt
= &fpu_default
;
24029 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
24030 mfpu_opt
= &fpu_arch_vfp_v2
;
24032 mfpu_opt
= &fpu_arch_fpa
;
24038 mcpu_cpu_opt
= &cpu_default
;
24039 selected_cpu
= cpu_default
;
24041 else if (no_cpu_selected ())
24042 selected_cpu
= cpu_default
;
24045 selected_cpu
= *mcpu_cpu_opt
;
24047 mcpu_cpu_opt
= &arm_arch_any
;
24050 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24052 autoselect_thumb_from_cpu_variant ();
24054 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
24056 #if defined OBJ_COFF || defined OBJ_ELF
24058 unsigned int flags
= 0;
24060 #if defined OBJ_ELF
24061 flags
= meabi_flags
;
24063 switch (meabi_flags
)
24065 case EF_ARM_EABI_UNKNOWN
:
24067 /* Set the flags in the private structure. */
24068 if (uses_apcs_26
) flags
|= F_APCS26
;
24069 if (support_interwork
) flags
|= F_INTERWORK
;
24070 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
24071 if (pic_code
) flags
|= F_PIC
;
24072 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
24073 flags
|= F_SOFT_FLOAT
;
24075 switch (mfloat_abi_opt
)
24077 case ARM_FLOAT_ABI_SOFT
:
24078 case ARM_FLOAT_ABI_SOFTFP
:
24079 flags
|= F_SOFT_FLOAT
;
24082 case ARM_FLOAT_ABI_HARD
:
24083 if (flags
& F_SOFT_FLOAT
)
24084 as_bad (_("hard-float conflicts with specified fpu"));
24088 /* Using pure-endian doubles (even if soft-float). */
24089 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
24090 flags
|= F_VFP_FLOAT
;
24092 #if defined OBJ_ELF
24093 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
24094 flags
|= EF_ARM_MAVERICK_FLOAT
;
24097 case EF_ARM_EABI_VER4
:
24098 case EF_ARM_EABI_VER5
:
24099 /* No additional flags to set. */
24106 bfd_set_private_flags (stdoutput
, flags
);
24108 /* We have run out flags in the COFF header to encode the
24109 status of ATPCS support, so instead we create a dummy,
24110 empty, debug section called .arm.atpcs. */
24115 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
24119 bfd_set_section_flags
24120 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
24121 bfd_set_section_size (stdoutput
, sec
, 0);
24122 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
24128 /* Record the CPU type as well. */
24129 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
24130 mach
= bfd_mach_arm_iWMMXt2
;
24131 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
24132 mach
= bfd_mach_arm_iWMMXt
;
24133 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
24134 mach
= bfd_mach_arm_XScale
;
24135 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
24136 mach
= bfd_mach_arm_ep9312
;
24137 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
24138 mach
= bfd_mach_arm_5TE
;
24139 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
24141 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24142 mach
= bfd_mach_arm_5T
;
24144 mach
= bfd_mach_arm_5
;
24146 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
24148 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24149 mach
= bfd_mach_arm_4T
;
24151 mach
= bfd_mach_arm_4
;
24153 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
24154 mach
= bfd_mach_arm_3M
;
24155 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
24156 mach
= bfd_mach_arm_3
;
24157 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
24158 mach
= bfd_mach_arm_2a
;
24159 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
24160 mach
= bfd_mach_arm_2
;
24162 mach
= bfd_mach_arm_unknown
;
24164 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
24167 /* Command line processing. */
24170 Invocation line includes a switch not recognized by the base assembler.
24171 See if it's a processor-specific option.
24173 This routine is somewhat complicated by the need for backwards
24174 compatibility (since older releases of gcc can't be changed).
24175 The new options try to make the interface as compatible as
24178 New options (supported) are:
24180 -mcpu=<cpu name> Assemble for selected processor
24181 -march=<architecture name> Assemble for selected architecture
24182 -mfpu=<fpu architecture> Assemble for selected FPU.
24183 -EB/-mbig-endian Big-endian
24184 -EL/-mlittle-endian Little-endian
24185 -k Generate PIC code
24186 -mthumb Start in Thumb mode
24187 -mthumb-interwork Code supports ARM/Thumb interworking
24189 -m[no-]warn-deprecated Warn about deprecated features
24190 -m[no-]warn-syms Warn when symbols match instructions
24192 For now we will also provide support for:
24194 -mapcs-32 32-bit Program counter
24195 -mapcs-26 26-bit Program counter
24196 -macps-float Floats passed in FP registers
24197 -mapcs-reentrant Reentrant code
24199 (sometime these will probably be replaced with -mapcs=<list of options>
24200 and -matpcs=<list of options>)
24202 The remaining options are only supported for back-wards compatibility.
24203 Cpu variants, the arm part is optional:
24204 -m[arm]1 Currently not supported.
24205 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
24206 -m[arm]3 Arm 3 processor
24207 -m[arm]6[xx], Arm 6 processors
24208 -m[arm]7[xx][t][[d]m] Arm 7 processors
24209 -m[arm]8[10] Arm 8 processors
24210 -m[arm]9[20][tdmi] Arm 9 processors
24211 -mstrongarm[110[0]] StrongARM processors
24212 -mxscale XScale processors
24213 -m[arm]v[2345[t[e]]] Arm architectures
24214 -mall All (except the ARM1)
24216 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
24217 -mfpe-old (No float load/store multiples)
24218 -mvfpxd VFP Single precision
24220 -mno-fpu Disable all floating point instructions
24222 The following CPU names are recognized:
24223 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
24224 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
24225 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
24226 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
24227 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
24228 arm10t arm10e, arm1020t, arm1020e, arm10200e,
24229 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
24233 const char * md_shortopts
= "m:k";
24235 #ifdef ARM_BI_ENDIAN
24236 #define OPTION_EB (OPTION_MD_BASE + 0)
24237 #define OPTION_EL (OPTION_MD_BASE + 1)
24239 #if TARGET_BYTES_BIG_ENDIAN
24240 #define OPTION_EB (OPTION_MD_BASE + 0)
24242 #define OPTION_EL (OPTION_MD_BASE + 1)
24245 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
24247 struct option md_longopts
[] =
24250 {"EB", no_argument
, NULL
, OPTION_EB
},
24253 {"EL", no_argument
, NULL
, OPTION_EL
},
24255 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
24256 {NULL
, no_argument
, NULL
, 0}
24260 size_t md_longopts_size
= sizeof (md_longopts
);
24262 struct arm_option_table
24264 char *option
; /* Option name to match. */
24265 char *help
; /* Help information. */
24266 int *var
; /* Variable to change. */
24267 int value
; /* What to change it to. */
24268 char *deprecated
; /* If non-null, print this message. */
24271 struct arm_option_table arm_opts
[] =
24273 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
24274 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
24275 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
24276 &support_interwork
, 1, NULL
},
24277 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
24278 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
24279 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
24281 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
24282 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
24283 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
24284 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
24287 /* These are recognized by the assembler, but have no affect on code. */
24288 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
24289 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
24291 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
24292 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
24293 &warn_on_deprecated
, 0, NULL
},
24294 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
24295 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
24296 {NULL
, NULL
, NULL
, 0, NULL
}
24299 struct arm_legacy_option_table
24301 char *option
; /* Option name to match. */
24302 const arm_feature_set
**var
; /* Variable to change. */
24303 const arm_feature_set value
; /* What to change it to. */
24304 char *deprecated
; /* If non-null, print this message. */
24307 const struct arm_legacy_option_table arm_legacy_opts
[] =
24309 /* DON'T add any new processors to this list -- we want the whole list
24310 to go away... Add them to the processors table instead. */
24311 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24312 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24313 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24314 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24315 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
24316 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
24317 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
24318 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
24319 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
24320 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
24321 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
24322 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
24323 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
24324 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
24325 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
24326 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
24327 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
24328 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
24329 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
24330 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
24331 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
24332 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
24333 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
24334 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
24335 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
24336 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
24337 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
24338 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
24339 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
24340 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
24341 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
24342 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
24343 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
24344 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
24345 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
24346 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
24347 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
24348 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
24349 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
24350 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
24351 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
24352 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
24353 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
24354 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
24355 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
24356 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
24357 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24358 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24359 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24360 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24361 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24362 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24363 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24364 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24365 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24366 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24367 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24368 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24369 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24370 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24371 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24372 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24373 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24374 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24375 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24376 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24377 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24378 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24379 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
24380 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
24381 N_("use -mcpu=strongarm110")},
24382 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
24383 N_("use -mcpu=strongarm1100")},
24384 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
24385 N_("use -mcpu=strongarm1110")},
24386 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
24387 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
24388 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
24390 /* Architecture variants -- don't add any more to this list either. */
24391 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24392 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24393 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24394 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24395 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24396 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24397 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24398 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24399 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24400 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24401 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24402 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24403 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24404 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24405 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24406 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24407 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24408 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24410 /* Floating point variants -- don't add any more to this list either. */
24411 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
24412 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
24413 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
24414 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
24415 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
24417 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
24420 struct arm_cpu_option_table
24424 const arm_feature_set value
;
24425 /* For some CPUs we assume an FPU unless the user explicitly sets
24427 const arm_feature_set default_fpu
;
24428 /* The canonical name of the CPU, or NULL to use NAME converted to upper
24430 const char *canonical_name
;
24433 /* This list should, at a minimum, contain all the cpu names
24434 recognized by GCC. */
24435 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
24436 static const struct arm_cpu_option_table arm_cpus
[] =
24438 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
24439 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
24440 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
24441 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24442 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24443 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24444 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24445 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24446 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24447 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24448 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24449 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24450 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24451 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24452 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24453 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24454 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24455 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24456 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24457 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24458 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24459 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24460 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24461 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24462 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24463 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24464 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24465 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24466 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24467 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24468 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24469 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24470 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24471 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24472 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24473 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24474 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24475 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24476 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24477 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
24478 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24479 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24480 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24481 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24482 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24483 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24484 /* For V5 or later processors we default to using VFP; but the user
24485 should really set the FPU type explicitly. */
24486 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24487 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24488 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24489 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24490 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24491 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24492 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
24493 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24494 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24495 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
24496 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24497 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24498 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24499 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24500 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24501 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
24502 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24503 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24504 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24505 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
24507 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24508 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24509 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24510 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24511 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24512 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24513 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
24514 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
24515 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
24517 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
24518 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
24519 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
24520 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
24521 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
24522 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
),
24523 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
),
24524 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
24525 FPU_NONE
, "Cortex-A5"),
24526 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24528 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
24529 ARM_FEATURE_COPROC (FPU_VFP_V3
24530 | FPU_NEON_EXT_V1
),
24532 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
24533 ARM_FEATURE_COPROC (FPU_VFP_V3
24534 | FPU_NEON_EXT_V1
),
24536 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24538 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24540 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24542 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24544 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24546 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24548 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
24549 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
24551 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
24552 FPU_NONE
, "Cortex-R5"),
24553 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
24554 FPU_ARCH_VFP_V3D16
,
24556 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
24557 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
24558 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
24559 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
24560 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
24561 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
24562 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24565 /* ??? XSCALE is really an architecture. */
24566 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24567 /* ??? iwmmxt is not a processor. */
24568 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
24569 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
24570 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24572 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
24573 FPU_ARCH_MAVERICK
, "ARM920T"),
24574 /* Marvell processors. */
24575 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A
| ARM_EXT_MP
24577 FPU_ARCH_VFP_V3D16
, NULL
),
24578 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A
| ARM_EXT_MP
24580 FPU_ARCH_NEON_VFP_V4
, NULL
),
24581 /* APM X-Gene family. */
24582 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24584 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24587 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
24591 struct arm_arch_option_table
24595 const arm_feature_set value
;
24596 const arm_feature_set default_fpu
;
24599 /* This list should, at a minimum, contain all the architecture names
24600 recognized by GCC. */
24601 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
24602 static const struct arm_arch_option_table arm_archs
[] =
24604 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
24605 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
24606 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
24607 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24608 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24609 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
24610 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
24611 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
24612 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
24613 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
24614 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
24615 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
24616 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
24617 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
24618 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
24619 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
24620 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
24621 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24622 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24623 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
24624 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
24625 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
),
24626 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
24627 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
24628 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
24629 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
),
24630 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
24631 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
24632 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
24633 /* The official spelling of the ARMv7 profile variants is the dashed form.
24634 Accept the non-dashed form for compatibility with old toolchains. */
24635 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24636 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
24637 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24638 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24639 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24640 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24641 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24642 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
24643 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
24644 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
24645 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
24646 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
24647 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24649 #undef ARM_ARCH_OPT
24651 /* ISA extensions in the co-processor and main instruction set space. */
24652 struct arm_option_extension_value_table
24656 const arm_feature_set merge_value
;
24657 const arm_feature_set clear_value
;
24658 const arm_feature_set allowed_archs
;
24661 /* The following table must be in alphabetical order with a NULL last entry.
24663 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA }
24664 static const struct arm_option_extension_value_table arm_extensions
[] =
24666 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
24667 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24668 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24669 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
24670 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24671 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
24672 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24673 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
24674 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
24675 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
24676 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
24677 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ANY
),
24678 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
24679 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ANY
),
24680 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
24681 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ANY
),
24682 ARM_EXT_OPT ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
24683 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
24684 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
24685 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
24686 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
24687 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24688 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
24689 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
24690 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
24691 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
24692 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
24693 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24694 ARM_EXT_OPT ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
24695 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
24696 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V7A
)),
24697 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
24699 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
24700 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
24701 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
24702 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ANY
),
24703 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24707 /* ISA floating-point and Advanced SIMD extensions. */
24708 struct arm_option_fpu_value_table
24711 const arm_feature_set value
;
24714 /* This list should, at a minimum, contain all the fpu names
24715 recognized by GCC. */
24716 static const struct arm_option_fpu_value_table arm_fpus
[] =
24718 {"softfpa", FPU_NONE
},
24719 {"fpe", FPU_ARCH_FPE
},
24720 {"fpe2", FPU_ARCH_FPE
},
24721 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
24722 {"fpa", FPU_ARCH_FPA
},
24723 {"fpa10", FPU_ARCH_FPA
},
24724 {"fpa11", FPU_ARCH_FPA
},
24725 {"arm7500fe", FPU_ARCH_FPA
},
24726 {"softvfp", FPU_ARCH_VFP
},
24727 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
24728 {"vfp", FPU_ARCH_VFP_V2
},
24729 {"vfp9", FPU_ARCH_VFP_V2
},
24730 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
24731 {"vfp10", FPU_ARCH_VFP_V2
},
24732 {"vfp10-r0", FPU_ARCH_VFP_V1
},
24733 {"vfpxd", FPU_ARCH_VFP_V1xD
},
24734 {"vfpv2", FPU_ARCH_VFP_V2
},
24735 {"vfpv3", FPU_ARCH_VFP_V3
},
24736 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
24737 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
24738 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
24739 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
24740 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
24741 {"arm1020t", FPU_ARCH_VFP_V1
},
24742 {"arm1020e", FPU_ARCH_VFP_V2
},
24743 {"arm1136jfs", FPU_ARCH_VFP_V2
},
24744 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
24745 {"maverick", FPU_ARCH_MAVERICK
},
24746 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
24747 {"neon-fp16", FPU_ARCH_NEON_FP16
},
24748 {"vfpv4", FPU_ARCH_VFP_V4
},
24749 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
24750 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
24751 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
24752 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
24753 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
24754 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
24755 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
24756 {"crypto-neon-fp-armv8",
24757 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
24758 {NULL
, ARM_ARCH_NONE
}
24761 struct arm_option_value_table
24767 static const struct arm_option_value_table arm_float_abis
[] =
24769 {"hard", ARM_FLOAT_ABI_HARD
},
24770 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
24771 {"soft", ARM_FLOAT_ABI_SOFT
},
24776 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
24777 static const struct arm_option_value_table arm_eabis
[] =
24779 {"gnu", EF_ARM_EABI_UNKNOWN
},
24780 {"4", EF_ARM_EABI_VER4
},
24781 {"5", EF_ARM_EABI_VER5
},
24786 struct arm_long_option_table
24788 char * option
; /* Substring to match. */
24789 char * help
; /* Help information. */
24790 int (* func
) (char * subopt
); /* Function to decode sub-option. */
24791 char * deprecated
; /* If non-null, print this message. */
24795 arm_parse_extension (char *str
, const arm_feature_set
**opt_p
)
24797 arm_feature_set
*ext_set
= (arm_feature_set
*)
24798 xmalloc (sizeof (arm_feature_set
));
24800 /* We insist on extensions being specified in alphabetical order, and with
24801 extensions being added before being removed. We achieve this by having
24802 the global ARM_EXTENSIONS table in alphabetical order, and using the
24803 ADDING_VALUE variable to indicate whether we are adding an extension (1)
24804 or removing it (0) and only allowing it to change in the order
24806 const struct arm_option_extension_value_table
* opt
= NULL
;
24807 int adding_value
= -1;
24809 /* Copy the feature set, so that we can modify it. */
24810 *ext_set
= **opt_p
;
24813 while (str
!= NULL
&& *str
!= 0)
24820 as_bad (_("invalid architectural extension"));
24825 ext
= strchr (str
, '+');
24830 len
= strlen (str
);
24832 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
24834 if (adding_value
!= 0)
24837 opt
= arm_extensions
;
24845 if (adding_value
== -1)
24848 opt
= arm_extensions
;
24850 else if (adding_value
!= 1)
24852 as_bad (_("must specify extensions to add before specifying "
24853 "those to remove"));
24860 as_bad (_("missing architectural extension"));
24864 gas_assert (adding_value
!= -1);
24865 gas_assert (opt
!= NULL
);
24867 /* Scan over the options table trying to find an exact match. */
24868 for (; opt
->name
!= NULL
; opt
++)
24869 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24871 /* Check we can apply the extension to this architecture. */
24872 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
24874 as_bad (_("extension does not apply to the base architecture"));
24878 /* Add or remove the extension. */
24880 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
24882 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
24887 if (opt
->name
== NULL
)
24889 /* Did we fail to find an extension because it wasn't specified in
24890 alphabetical order, or because it does not exist? */
24892 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
24893 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24896 if (opt
->name
== NULL
)
24897 as_bad (_("unknown architectural extension `%s'"), str
);
24899 as_bad (_("architectural extensions must be specified in "
24900 "alphabetical order"));
24906 /* We should skip the extension we've just matched the next time
24918 arm_parse_cpu (char *str
)
24920 const struct arm_cpu_option_table
*opt
;
24921 char *ext
= strchr (str
, '+');
24927 len
= strlen (str
);
24931 as_bad (_("missing cpu name `%s'"), str
);
24935 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
24936 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24938 mcpu_cpu_opt
= &opt
->value
;
24939 mcpu_fpu_opt
= &opt
->default_fpu
;
24940 if (opt
->canonical_name
)
24941 strcpy (selected_cpu_name
, opt
->canonical_name
);
24946 for (i
= 0; i
< len
; i
++)
24947 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
24948 selected_cpu_name
[i
] = 0;
24952 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
24957 as_bad (_("unknown cpu `%s'"), str
);
24962 arm_parse_arch (char *str
)
24964 const struct arm_arch_option_table
*opt
;
24965 char *ext
= strchr (str
, '+');
24971 len
= strlen (str
);
24975 as_bad (_("missing architecture name `%s'"), str
);
24979 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
24980 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24982 march_cpu_opt
= &opt
->value
;
24983 march_fpu_opt
= &opt
->default_fpu
;
24984 strcpy (selected_cpu_name
, opt
->name
);
24987 return arm_parse_extension (ext
, &march_cpu_opt
);
24992 as_bad (_("unknown architecture `%s'\n"), str
);
24997 arm_parse_fpu (char * str
)
24999 const struct arm_option_fpu_value_table
* opt
;
25001 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25002 if (streq (opt
->name
, str
))
25004 mfpu_opt
= &opt
->value
;
25008 as_bad (_("unknown floating point format `%s'\n"), str
);
25013 arm_parse_float_abi (char * str
)
25015 const struct arm_option_value_table
* opt
;
25017 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
25018 if (streq (opt
->name
, str
))
25020 mfloat_abi_opt
= opt
->value
;
25024 as_bad (_("unknown floating point abi `%s'\n"), str
);
25030 arm_parse_eabi (char * str
)
25032 const struct arm_option_value_table
*opt
;
25034 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
25035 if (streq (opt
->name
, str
))
25037 meabi_flags
= opt
->value
;
25040 as_bad (_("unknown EABI `%s'\n"), str
);
25046 arm_parse_it_mode (char * str
)
25048 bfd_boolean ret
= TRUE
;
25050 if (streq ("arm", str
))
25051 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
25052 else if (streq ("thumb", str
))
25053 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
25054 else if (streq ("always", str
))
25055 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
25056 else if (streq ("never", str
))
25057 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
25060 as_bad (_("unknown implicit IT mode `%s', should be "\
25061 "arm, thumb, always, or never."), str
);
25069 arm_ccs_mode (char * unused ATTRIBUTE_UNUSED
)
25071 codecomposer_syntax
= TRUE
;
25072 arm_comment_chars
[0] = ';';
25073 arm_line_separator_chars
[0] = 0;
25077 struct arm_long_option_table arm_long_opts
[] =
25079 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
25080 arm_parse_cpu
, NULL
},
25081 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
25082 arm_parse_arch
, NULL
},
25083 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
25084 arm_parse_fpu
, NULL
},
25085 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
25086 arm_parse_float_abi
, NULL
},
25088 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
25089 arm_parse_eabi
, NULL
},
25091 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
25092 arm_parse_it_mode
, NULL
},
25093 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
25094 arm_ccs_mode
, NULL
},
25095 {NULL
, NULL
, 0, NULL
}
25099 md_parse_option (int c
, char * arg
)
25101 struct arm_option_table
*opt
;
25102 const struct arm_legacy_option_table
*fopt
;
25103 struct arm_long_option_table
*lopt
;
25109 target_big_endian
= 1;
25115 target_big_endian
= 0;
25119 case OPTION_FIX_V4BX
:
25124 /* Listing option. Just ignore these, we don't support additional
25129 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25131 if (c
== opt
->option
[0]
25132 && ((arg
== NULL
&& opt
->option
[1] == 0)
25133 || streq (arg
, opt
->option
+ 1)))
25135 /* If the option is deprecated, tell the user. */
25136 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
25137 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25138 arg
? arg
: "", _(opt
->deprecated
));
25140 if (opt
->var
!= NULL
)
25141 *opt
->var
= opt
->value
;
25147 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
25149 if (c
== fopt
->option
[0]
25150 && ((arg
== NULL
&& fopt
->option
[1] == 0)
25151 || streq (arg
, fopt
->option
+ 1)))
25153 /* If the option is deprecated, tell the user. */
25154 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
25155 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25156 arg
? arg
: "", _(fopt
->deprecated
));
25158 if (fopt
->var
!= NULL
)
25159 *fopt
->var
= &fopt
->value
;
25165 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25167 /* These options are expected to have an argument. */
25168 if (c
== lopt
->option
[0]
25170 && strncmp (arg
, lopt
->option
+ 1,
25171 strlen (lopt
->option
+ 1)) == 0)
25173 /* If the option is deprecated, tell the user. */
25174 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
25175 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
25176 _(lopt
->deprecated
));
25178 /* Call the sup-option parser. */
25179 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
25190 md_show_usage (FILE * fp
)
25192 struct arm_option_table
*opt
;
25193 struct arm_long_option_table
*lopt
;
25195 fprintf (fp
, _(" ARM-specific assembler options:\n"));
25197 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25198 if (opt
->help
!= NULL
)
25199 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
25201 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25202 if (lopt
->help
!= NULL
)
25203 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
25207 -EB assemble code for a big-endian cpu\n"));
25212 -EL assemble code for a little-endian cpu\n"));
25216 --fix-v4bx Allow BX in ARMv4 code\n"));
25224 arm_feature_set flags
;
25225 } cpu_arch_ver_table
;
25227 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
25228 least features first. */
25229 static const cpu_arch_ver_table cpu_arch_ver
[] =
25235 {4, ARM_ARCH_V5TE
},
25236 {5, ARM_ARCH_V5TEJ
},
25240 {11, ARM_ARCH_V6M
},
25241 {12, ARM_ARCH_V6SM
},
25242 {8, ARM_ARCH_V6T2
},
25243 {10, ARM_ARCH_V7VE
},
25244 {10, ARM_ARCH_V7R
},
25245 {10, ARM_ARCH_V7M
},
25246 {14, ARM_ARCH_V8A
},
25250 /* Set an attribute if it has not already been set by the user. */
25252 aeabi_set_attribute_int (int tag
, int value
)
25255 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25256 || !attributes_set_explicitly
[tag
])
25257 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
25261 aeabi_set_attribute_string (int tag
, const char *value
)
25264 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25265 || !attributes_set_explicitly
[tag
])
25266 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
25269 /* Set the public EABI object attributes. */
25271 aeabi_set_public_attributes (void)
25276 int fp16_optional
= 0;
25277 arm_feature_set flags
;
25278 arm_feature_set tmp
;
25279 const cpu_arch_ver_table
*p
;
25281 /* Choose the architecture based on the capabilities of the requested cpu
25282 (if any) and/or the instructions actually used. */
25283 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
25284 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
25285 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
25287 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
25288 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
25290 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
25291 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
25293 selected_cpu
= flags
;
25295 /* Allow the user to override the reported architecture. */
25298 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
25299 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
25302 /* We need to make sure that the attributes do not identify us as v6S-M
25303 when the only v6S-M feature in use is the Operating System Extensions. */
25304 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
25305 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
25306 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
25310 for (p
= cpu_arch_ver
; p
->val
; p
++)
25312 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
25315 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
25319 /* The table lookup above finds the last architecture to contribute
25320 a new feature. Unfortunately, Tag13 is a subset of the union of
25321 v6T2 and v7-M, so it is never seen as contributing a new feature.
25322 We can not search for the last entry which is entirely used,
25323 because if no CPU is specified we build up only those flags
25324 actually used. Perhaps we should separate out the specified
25325 and implicit cases. Avoid taking this path for -march=all by
25326 checking for contradictory v7-A / v7-M features. */
25328 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
25329 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
25330 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
25333 /* Tag_CPU_name. */
25334 if (selected_cpu_name
[0])
25338 q
= selected_cpu_name
;
25339 if (strncmp (q
, "armv", 4) == 0)
25344 for (i
= 0; q
[i
]; i
++)
25345 q
[i
] = TOUPPER (q
[i
]);
25347 aeabi_set_attribute_string (Tag_CPU_name
, q
);
25350 /* Tag_CPU_arch. */
25351 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
25353 /* Tag_CPU_arch_profile. */
25354 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
25356 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
25358 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
25363 if (profile
!= '\0')
25364 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
25366 /* Tag_ARM_ISA_use. */
25367 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
25369 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
25371 /* Tag_THUMB_ISA_use. */
25372 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
25374 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
25375 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
25377 /* Tag_VFP_arch. */
25378 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
25379 aeabi_set_attribute_int (Tag_VFP_arch
,
25380 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
25382 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
25383 aeabi_set_attribute_int (Tag_VFP_arch
,
25384 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
25386 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
25389 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
25391 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
25393 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
25396 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
25397 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
25398 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
25399 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
25400 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
25402 /* Tag_ABI_HardFP_use. */
25403 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
25404 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
25405 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
25407 /* Tag_WMMX_arch. */
25408 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
25409 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
25410 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
25411 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
25413 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
25414 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
25415 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
25416 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
25418 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
25420 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
25424 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
25429 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
25430 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
25431 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
25435 We set Tag_DIV_use to two when integer divide instructions have been used
25436 in ARM state, or when Thumb integer divide instructions have been used,
25437 but we have no architecture profile set, nor have we any ARM instructions.
25439 For ARMv8 we set the tag to 0 as integer divide is implied by the base
25442 For new architectures we will have to check these tests. */
25443 gas_assert (arch
<= TAG_CPU_ARCH_V8
);
25444 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
))
25445 aeabi_set_attribute_int (Tag_DIV_use
, 0);
25446 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
25447 || (profile
== '\0'
25448 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
25449 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
25450 aeabi_set_attribute_int (Tag_DIV_use
, 2);
25452 /* Tag_MP_extension_use. */
25453 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
25454 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
25456 /* Tag Virtualization_use. */
25457 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
25459 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
25462 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
25465 /* Add the default contents for the .ARM.attributes section. */
25469 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25472 aeabi_set_public_attributes ();
25474 #endif /* OBJ_ELF */
25477 /* Parse a .cpu directive. */
25480 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
25482 const struct arm_cpu_option_table
*opt
;
25486 name
= input_line_pointer
;
25487 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25488 input_line_pointer
++;
25489 saved_char
= *input_line_pointer
;
25490 *input_line_pointer
= 0;
25492 /* Skip the first "all" entry. */
25493 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
25494 if (streq (opt
->name
, name
))
25496 mcpu_cpu_opt
= &opt
->value
;
25497 selected_cpu
= opt
->value
;
25498 if (opt
->canonical_name
)
25499 strcpy (selected_cpu_name
, opt
->canonical_name
);
25503 for (i
= 0; opt
->name
[i
]; i
++)
25504 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25506 selected_cpu_name
[i
] = 0;
25508 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25509 *input_line_pointer
= saved_char
;
25510 demand_empty_rest_of_line ();
25513 as_bad (_("unknown cpu `%s'"), name
);
25514 *input_line_pointer
= saved_char
;
25515 ignore_rest_of_line ();
25519 /* Parse a .arch directive. */
25522 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
25524 const struct arm_arch_option_table
*opt
;
25528 name
= input_line_pointer
;
25529 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25530 input_line_pointer
++;
25531 saved_char
= *input_line_pointer
;
25532 *input_line_pointer
= 0;
25534 /* Skip the first "all" entry. */
25535 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25536 if (streq (opt
->name
, name
))
25538 mcpu_cpu_opt
= &opt
->value
;
25539 selected_cpu
= opt
->value
;
25540 strcpy (selected_cpu_name
, opt
->name
);
25541 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25542 *input_line_pointer
= saved_char
;
25543 demand_empty_rest_of_line ();
25547 as_bad (_("unknown architecture `%s'\n"), name
);
25548 *input_line_pointer
= saved_char
;
25549 ignore_rest_of_line ();
25553 /* Parse a .object_arch directive. */
25556 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
25558 const struct arm_arch_option_table
*opt
;
25562 name
= input_line_pointer
;
25563 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25564 input_line_pointer
++;
25565 saved_char
= *input_line_pointer
;
25566 *input_line_pointer
= 0;
25568 /* Skip the first "all" entry. */
25569 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25570 if (streq (opt
->name
, name
))
25572 object_arch
= &opt
->value
;
25573 *input_line_pointer
= saved_char
;
25574 demand_empty_rest_of_line ();
25578 as_bad (_("unknown architecture `%s'\n"), name
);
25579 *input_line_pointer
= saved_char
;
25580 ignore_rest_of_line ();
25583 /* Parse a .arch_extension directive. */
25586 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
25588 const struct arm_option_extension_value_table
*opt
;
25591 int adding_value
= 1;
25593 name
= input_line_pointer
;
25594 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25595 input_line_pointer
++;
25596 saved_char
= *input_line_pointer
;
25597 *input_line_pointer
= 0;
25599 if (strlen (name
) >= 2
25600 && strncmp (name
, "no", 2) == 0)
25606 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25607 if (streq (opt
->name
, name
))
25609 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
25611 as_bad (_("architectural extension `%s' is not allowed for the "
25612 "current base architecture"), name
);
25617 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
25620 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
25622 mcpu_cpu_opt
= &selected_cpu
;
25623 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25624 *input_line_pointer
= saved_char
;
25625 demand_empty_rest_of_line ();
25629 if (opt
->name
== NULL
)
25630 as_bad (_("unknown architecture extension `%s'\n"), name
);
25632 *input_line_pointer
= saved_char
;
25633 ignore_rest_of_line ();
25636 /* Parse a .fpu directive. */
25639 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
25641 const struct arm_option_fpu_value_table
*opt
;
25645 name
= input_line_pointer
;
25646 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25647 input_line_pointer
++;
25648 saved_char
= *input_line_pointer
;
25649 *input_line_pointer
= 0;
25651 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25652 if (streq (opt
->name
, name
))
25654 mfpu_opt
= &opt
->value
;
25655 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25656 *input_line_pointer
= saved_char
;
25657 demand_empty_rest_of_line ();
25661 as_bad (_("unknown floating point format `%s'\n"), name
);
25662 *input_line_pointer
= saved_char
;
25663 ignore_rest_of_line ();
25666 /* Copy symbol information. */
25669 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
25671 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
25675 /* Given a symbolic attribute NAME, return the proper integer value.
25676 Returns -1 if the attribute is not known. */
25679 arm_convert_symbolic_attribute (const char *name
)
25681 static const struct
25686 attribute_table
[] =
25688 /* When you modify this table you should
25689 also modify the list in doc/c-arm.texi. */
25690 #define T(tag) {#tag, tag}
25691 T (Tag_CPU_raw_name
),
25694 T (Tag_CPU_arch_profile
),
25695 T (Tag_ARM_ISA_use
),
25696 T (Tag_THUMB_ISA_use
),
25700 T (Tag_Advanced_SIMD_arch
),
25701 T (Tag_PCS_config
),
25702 T (Tag_ABI_PCS_R9_use
),
25703 T (Tag_ABI_PCS_RW_data
),
25704 T (Tag_ABI_PCS_RO_data
),
25705 T (Tag_ABI_PCS_GOT_use
),
25706 T (Tag_ABI_PCS_wchar_t
),
25707 T (Tag_ABI_FP_rounding
),
25708 T (Tag_ABI_FP_denormal
),
25709 T (Tag_ABI_FP_exceptions
),
25710 T (Tag_ABI_FP_user_exceptions
),
25711 T (Tag_ABI_FP_number_model
),
25712 T (Tag_ABI_align_needed
),
25713 T (Tag_ABI_align8_needed
),
25714 T (Tag_ABI_align_preserved
),
25715 T (Tag_ABI_align8_preserved
),
25716 T (Tag_ABI_enum_size
),
25717 T (Tag_ABI_HardFP_use
),
25718 T (Tag_ABI_VFP_args
),
25719 T (Tag_ABI_WMMX_args
),
25720 T (Tag_ABI_optimization_goals
),
25721 T (Tag_ABI_FP_optimization_goals
),
25722 T (Tag_compatibility
),
25723 T (Tag_CPU_unaligned_access
),
25724 T (Tag_FP_HP_extension
),
25725 T (Tag_VFP_HP_extension
),
25726 T (Tag_ABI_FP_16bit_format
),
25727 T (Tag_MPextension_use
),
25729 T (Tag_nodefaults
),
25730 T (Tag_also_compatible_with
),
25731 T (Tag_conformance
),
25733 T (Tag_Virtualization_use
),
25734 /* We deliberately do not include Tag_MPextension_use_legacy. */
25742 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
25743 if (streq (name
, attribute_table
[i
].name
))
25744 return attribute_table
[i
].tag
;
25750 /* Apply sym value for relocations only in the case that they are for
25751 local symbols in the same segment as the fixup and you have the
25752 respective architectural feature for blx and simple switches. */
25754 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
25757 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
25758 /* PR 17444: If the local symbol is in a different section then a reloc
25759 will always be generated for it, so applying the symbol value now
25760 will result in a double offset being stored in the relocation. */
25761 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
25762 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
25764 switch (fixP
->fx_r_type
)
25766 case BFD_RELOC_ARM_PCREL_BLX
:
25767 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25768 if (ARM_IS_FUNC (fixP
->fx_addsy
))
25772 case BFD_RELOC_ARM_PCREL_CALL
:
25773 case BFD_RELOC_THUMB_PCREL_BLX
:
25774 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
25785 #endif /* OBJ_ELF */