1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
45 #define WARN_DEPRECATED 1
48 /* Must be at least the size of the largest unwind opcode (currently two). */
49 #define ARM_OPCODE_CHUNK_SIZE 8
51 /* This structure holds the unwinding state. */
56 symbolS
* table_entry
;
57 symbolS
* personality_routine
;
58 int personality_index
;
59 /* The segment containing the function. */
62 /* Opcodes generated from this function. */
63 unsigned char * opcodes
;
66 /* The number of bytes pushed to the stack. */
68 /* We don't add stack adjustment opcodes immediately so that we can merge
69 multiple adjustments. We can also omit the final adjustment
70 when using a frame pointer. */
71 offsetT pending_offset
;
72 /* These two fields are set by both unwind_movsp and unwind_setfp. They
73 hold the reg+offset to use when restoring sp from a frame pointer. */
76 /* Nonzero if an unwind_setfp directive has been seen. */
78 /* Nonzero if the last opcode restores sp from fp_reg. */
79 unsigned sp_restored
:1;
82 /* Bit N indicates that an R_ARM_NONE relocation has been output for
83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84 emitted only once per section, to save unnecessary bloat. */
85 static unsigned int marked_pr_dependency
= 0;
89 /* Results from operand parsing worker functions. */
93 PARSE_OPERAND_SUCCESS
,
95 PARSE_OPERAND_FAIL_NO_BACKTRACK
96 } parse_operand_result
;
101 ARM_FLOAT_ABI_SOFTFP
,
105 /* Types of processor to assemble for. */
107 #if defined __XSCALE__
108 #define CPU_DEFAULT ARM_ARCH_XSCALE
110 #if defined __thumb__
111 #define CPU_DEFAULT ARM_ARCH_V5T
118 # define FPU_DEFAULT FPU_ARCH_FPA
119 # elif defined (TE_NetBSD)
121 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
123 /* Legacy a.out format. */
124 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
126 # elif defined (TE_VXWORKS)
127 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
129 /* For backwards compatibility, default to FPA. */
130 # define FPU_DEFAULT FPU_ARCH_FPA
132 #endif /* ifndef FPU_DEFAULT */
134 #define streq(a, b) (strcmp (a, b) == 0)
136 static arm_feature_set cpu_variant
;
137 static arm_feature_set arm_arch_used
;
138 static arm_feature_set thumb_arch_used
;
140 /* Flags stored in private area of BFD structure. */
141 static int uses_apcs_26
= FALSE
;
142 static int atpcs
= FALSE
;
143 static int support_interwork
= FALSE
;
144 static int uses_apcs_float
= FALSE
;
145 static int pic_code
= FALSE
;
147 /* Variables that we set while parsing command-line options. Once all
148 options have been read we re-process these values to set the real
150 static const arm_feature_set
*legacy_cpu
= NULL
;
151 static const arm_feature_set
*legacy_fpu
= NULL
;
153 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
154 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
155 static const arm_feature_set
*march_cpu_opt
= NULL
;
156 static const arm_feature_set
*march_fpu_opt
= NULL
;
157 static const arm_feature_set
*mfpu_opt
= NULL
;
159 /* Constants for known architecture features. */
160 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
161 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
162 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
163 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
164 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
165 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
166 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
167 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
168 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
171 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
174 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
175 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
176 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
177 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
178 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
179 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
180 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
181 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
182 static const arm_feature_set arm_ext_v4t_5
=
183 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
184 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
185 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
186 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
187 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
188 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
189 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
190 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
191 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
192 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
199 static const arm_feature_set arm_arch_any
= ARM_ANY
;
200 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
201 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
202 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
204 static const arm_feature_set arm_cext_iwmmxt
=
205 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
206 static const arm_feature_set arm_cext_xscale
=
207 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
208 static const arm_feature_set arm_cext_maverick
=
209 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
210 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
211 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
212 static const arm_feature_set fpu_vfp_ext_v1xd
=
213 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
214 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
215 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
216 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
217 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
218 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
219 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
221 static int mfloat_abi_opt
= -1;
222 /* Record user cpu selection for object attributes. */
223 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
224 /* Must be long enough to hold any of the names in arm_cpus. */
225 static char selected_cpu_name
[16];
228 static int meabi_flags
= EABI_DEFAULT
;
230 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
235 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
236 symbolS
* GOT_symbol
;
239 /* 0: assemble for ARM,
240 1: assemble for Thumb,
241 2: assemble for Thumb even though target CPU does not support thumb
243 static int thumb_mode
= 0;
245 /* If unified_syntax is true, we are processing the new unified
246 ARM/Thumb syntax. Important differences from the old ARM mode:
248 - Immediate operands do not require a # prefix.
249 - Conditional affixes always appear at the end of the
250 instruction. (For backward compatibility, those instructions
251 that formerly had them in the middle, continue to accept them
253 - The IT instruction may appear, and if it does is validated
254 against subsequent conditional affixes. It does not generate
257 Important differences from the old Thumb mode:
259 - Immediate operands do not require a # prefix.
260 - Most of the V6T2 instructions are only available in unified mode.
261 - The .N and .W suffixes are recognized and honored (it is an error
262 if they cannot be honored).
263 - All instructions set the flags if and only if they have an 's' affix.
264 - Conditional affixes may be used. They are validated against
265 preceding IT instructions. Unlike ARM mode, you cannot use a
266 conditional affix except in the scope of an IT instruction. */
268 static bfd_boolean unified_syntax
= FALSE
;
283 enum neon_el_type type
;
287 #define NEON_MAX_TYPE_ELS 4
291 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
298 unsigned long instruction
;
302 /* "uncond_value" is set to the value in place of the conditional field in
303 unconditional versions of the instruction, or -1 if nothing is
306 struct neon_type vectype
;
307 /* Set to the opcode if the instruction needs relaxation.
308 Zero if the instruction is not relaxed. */
312 bfd_reloc_code_real_type type
;
321 struct neon_type_el vectype
;
322 unsigned present
: 1; /* Operand present. */
323 unsigned isreg
: 1; /* Operand was a register. */
324 unsigned immisreg
: 1; /* .imm field is a second register. */
325 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
326 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
327 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
328 instructions. This allows us to disambiguate ARM <-> vector insns. */
329 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
330 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
331 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
332 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
333 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
334 unsigned writeback
: 1; /* Operand has trailing ! */
335 unsigned preind
: 1; /* Preindexed address. */
336 unsigned postind
: 1; /* Postindexed address. */
337 unsigned negative
: 1; /* Index register was negated. */
338 unsigned shifted
: 1; /* Shift applied to operation. */
339 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
343 static struct arm_it inst
;
345 #define NUM_FLOAT_VALS 8
347 const char * fp_const
[] =
349 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
352 /* Number of littlenums required to hold an extended precision number. */
353 #define MAX_LITTLENUMS 6
355 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
365 #define CP_T_X 0x00008000
366 #define CP_T_Y 0x00400000
368 #define CONDS_BIT 0x00100000
369 #define LOAD_BIT 0x00100000
371 #define DOUBLE_LOAD_FLAG 0x00000001
375 const char * template;
379 #define COND_ALWAYS 0xE
383 const char *template;
387 struct asm_barrier_opt
389 const char *template;
393 /* The bit that distinguishes CPSR and SPSR. */
394 #define SPSR_BIT (1 << 22)
396 /* The individual PSR flag bits. */
397 #define PSR_c (1 << 16)
398 #define PSR_x (1 << 17)
399 #define PSR_s (1 << 18)
400 #define PSR_f (1 << 19)
405 bfd_reloc_code_real_type reloc
;
410 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
411 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
416 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
419 /* Bits for DEFINED field in neon_typed_alias. */
420 #define NTA_HASTYPE 1
421 #define NTA_HASINDEX 2
423 struct neon_typed_alias
425 unsigned char defined
;
427 struct neon_type_el eltype
;
430 /* ARM register categories. This includes coprocessor numbers and various
431 architecture extensions' registers. */
457 /* Structure for a hash table entry for a register.
458 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
459 information which states whether a vector type or index is specified (for a
460 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
464 unsigned char number
;
466 unsigned char builtin
;
467 struct neon_typed_alias
*neon
;
470 /* Diagnostics used when we don't get a register of the expected type. */
471 const char *const reg_expected_msgs
[] =
473 N_("ARM register expected"),
474 N_("bad or missing co-processor number"),
475 N_("co-processor register expected"),
476 N_("FPA register expected"),
477 N_("VFP single precision register expected"),
478 N_("VFP/Neon double precision register expected"),
479 N_("Neon quad precision register expected"),
480 N_("VFP single or double precision register expected"),
481 N_("Neon double or quad precision register expected"),
482 N_("VFP single, double or Neon quad precision register expected"),
483 N_("VFP system register expected"),
484 N_("Maverick MVF register expected"),
485 N_("Maverick MVD register expected"),
486 N_("Maverick MVFX register expected"),
487 N_("Maverick MVDX register expected"),
488 N_("Maverick MVAX register expected"),
489 N_("Maverick DSPSC register expected"),
490 N_("iWMMXt data register expected"),
491 N_("iWMMXt control register expected"),
492 N_("iWMMXt scalar register expected"),
493 N_("XScale accumulator register expected"),
496 /* Some well known registers that we refer to directly elsewhere. */
501 /* ARM instructions take 4bytes in the object file, Thumb instructions
507 /* Basic string to match. */
508 const char *template;
510 /* Parameters to instruction. */
511 unsigned char operands
[8];
513 /* Conditional tag - see opcode_lookup. */
514 unsigned int tag
: 4;
516 /* Basic instruction code. */
517 unsigned int avalue
: 28;
519 /* Thumb-format instruction code. */
522 /* Which architecture variant provides this instruction. */
523 const arm_feature_set
*avariant
;
524 const arm_feature_set
*tvariant
;
526 /* Function to call to encode instruction in ARM format. */
527 void (* aencode
) (void);
529 /* Function to call to encode instruction in Thumb format. */
530 void (* tencode
) (void);
533 /* Defines for various bits that we will want to toggle. */
534 #define INST_IMMEDIATE 0x02000000
535 #define OFFSET_REG 0x02000000
536 #define HWOFFSET_IMM 0x00400000
537 #define SHIFT_BY_REG 0x00000010
538 #define PRE_INDEX 0x01000000
539 #define INDEX_UP 0x00800000
540 #define WRITE_BACK 0x00200000
541 #define LDM_TYPE_2_OR_3 0x00400000
543 #define LITERAL_MASK 0xf000f000
544 #define OPCODE_MASK 0xfe1fffff
545 #define V4_STR_BIT 0x00000020
547 #define DATA_OP_SHIFT 21
549 #define T2_OPCODE_MASK 0xfe1fffff
550 #define T2_DATA_OP_SHIFT 21
552 /* Codes to distinguish the arithmetic instructions. */
563 #define OPCODE_CMP 10
564 #define OPCODE_CMN 11
565 #define OPCODE_ORR 12
566 #define OPCODE_MOV 13
567 #define OPCODE_BIC 14
568 #define OPCODE_MVN 15
570 #define T2_OPCODE_AND 0
571 #define T2_OPCODE_BIC 1
572 #define T2_OPCODE_ORR 2
573 #define T2_OPCODE_ORN 3
574 #define T2_OPCODE_EOR 4
575 #define T2_OPCODE_ADD 8
576 #define T2_OPCODE_ADC 10
577 #define T2_OPCODE_SBC 11
578 #define T2_OPCODE_SUB 13
579 #define T2_OPCODE_RSB 14
581 #define T_OPCODE_MUL 0x4340
582 #define T_OPCODE_TST 0x4200
583 #define T_OPCODE_CMN 0x42c0
584 #define T_OPCODE_NEG 0x4240
585 #define T_OPCODE_MVN 0x43c0
587 #define T_OPCODE_ADD_R3 0x1800
588 #define T_OPCODE_SUB_R3 0x1a00
589 #define T_OPCODE_ADD_HI 0x4400
590 #define T_OPCODE_ADD_ST 0xb000
591 #define T_OPCODE_SUB_ST 0xb080
592 #define T_OPCODE_ADD_SP 0xa800
593 #define T_OPCODE_ADD_PC 0xa000
594 #define T_OPCODE_ADD_I8 0x3000
595 #define T_OPCODE_SUB_I8 0x3800
596 #define T_OPCODE_ADD_I3 0x1c00
597 #define T_OPCODE_SUB_I3 0x1e00
599 #define T_OPCODE_ASR_R 0x4100
600 #define T_OPCODE_LSL_R 0x4080
601 #define T_OPCODE_LSR_R 0x40c0
602 #define T_OPCODE_ROR_R 0x41c0
603 #define T_OPCODE_ASR_I 0x1000
604 #define T_OPCODE_LSL_I 0x0000
605 #define T_OPCODE_LSR_I 0x0800
607 #define T_OPCODE_MOV_I8 0x2000
608 #define T_OPCODE_CMP_I8 0x2800
609 #define T_OPCODE_CMP_LR 0x4280
610 #define T_OPCODE_MOV_HR 0x4600
611 #define T_OPCODE_CMP_HR 0x4500
613 #define T_OPCODE_LDR_PC 0x4800
614 #define T_OPCODE_LDR_SP 0x9800
615 #define T_OPCODE_STR_SP 0x9000
616 #define T_OPCODE_LDR_IW 0x6800
617 #define T_OPCODE_STR_IW 0x6000
618 #define T_OPCODE_LDR_IH 0x8800
619 #define T_OPCODE_STR_IH 0x8000
620 #define T_OPCODE_LDR_IB 0x7800
621 #define T_OPCODE_STR_IB 0x7000
622 #define T_OPCODE_LDR_RW 0x5800
623 #define T_OPCODE_STR_RW 0x5000
624 #define T_OPCODE_LDR_RH 0x5a00
625 #define T_OPCODE_STR_RH 0x5200
626 #define T_OPCODE_LDR_RB 0x5c00
627 #define T_OPCODE_STR_RB 0x5400
629 #define T_OPCODE_PUSH 0xb400
630 #define T_OPCODE_POP 0xbc00
632 #define T_OPCODE_BRANCH 0xe000
634 #define THUMB_SIZE 2 /* Size of thumb instruction. */
635 #define THUMB_PP_PC_LR 0x0100
636 #define THUMB_LOAD_BIT 0x0800
637 #define THUMB2_LOAD_BIT 0x00100000
639 #define BAD_ARGS _("bad arguments to instruction")
640 #define BAD_PC _("r15 not allowed here")
641 #define BAD_COND _("instruction cannot be conditional")
642 #define BAD_OVERLAP _("registers may not be the same")
643 #define BAD_HIREG _("lo register required")
644 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
645 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
646 #define BAD_BRANCH _("branch must be last instruction in IT block")
647 #define BAD_NOT_IT _("instruction not allowed in IT block")
648 #define BAD_FPU _("selected FPU does not support instruction")
650 static struct hash_control
*arm_ops_hsh
;
651 static struct hash_control
*arm_cond_hsh
;
652 static struct hash_control
*arm_shift_hsh
;
653 static struct hash_control
*arm_psr_hsh
;
654 static struct hash_control
*arm_v7m_psr_hsh
;
655 static struct hash_control
*arm_reg_hsh
;
656 static struct hash_control
*arm_reloc_hsh
;
657 static struct hash_control
*arm_barrier_opt_hsh
;
659 /* Stuff needed to resolve the label ambiguity
669 symbolS
* last_label_seen
;
670 static int label_is_thumb_function_name
= FALSE
;
672 /* Literal pool structure. Held on a per-section
673 and per-sub-section basis. */
675 #define MAX_LITERAL_POOL_SIZE 1024
676 typedef struct literal_pool
678 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
679 unsigned int next_free_entry
;
684 struct literal_pool
* next
;
687 /* Pointer to a linked list of literal pools. */
688 literal_pool
* list_of_pools
= NULL
;
690 /* State variables for IT block handling. */
691 static bfd_boolean current_it_mask
= 0;
692 static int current_cc
;
697 /* This array holds the chars that always start a comment. If the
698 pre-processor is disabled, these aren't very useful. */
699 const char comment_chars
[] = "@";
701 /* This array holds the chars that only start a comment at the beginning of
702 a line. If the line seems to have the form '# 123 filename'
703 .line and .file directives will appear in the pre-processed output. */
704 /* Note that input_file.c hand checks for '#' at the beginning of the
705 first line of the input file. This is because the compiler outputs
706 #NO_APP at the beginning of its output. */
707 /* Also note that comments like this one will always work. */
708 const char line_comment_chars
[] = "#";
710 const char line_separator_chars
[] = ";";
712 /* Chars that can be used to separate mant
713 from exp in floating point numbers. */
714 const char EXP_CHARS
[] = "eE";
716 /* Chars that mean this number is a floating point constant. */
720 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
722 /* Prefix characters that indicate the start of an immediate
724 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
726 /* Separator character handling. */
728 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
731 skip_past_char (char ** str
, char c
)
741 #define skip_past_comma(str) skip_past_char (str, ',')
743 /* Arithmetic expressions (possibly involving symbols). */
745 /* Return TRUE if anything in the expression is a bignum. */
748 walk_no_bignums (symbolS
* sp
)
750 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
753 if (symbol_get_value_expression (sp
)->X_add_symbol
)
755 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
756 || (symbol_get_value_expression (sp
)->X_op_symbol
757 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
763 static int in_my_get_expression
= 0;
765 /* Third argument to my_get_expression. */
766 #define GE_NO_PREFIX 0
767 #define GE_IMM_PREFIX 1
768 #define GE_OPT_PREFIX 2
769 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
770 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
771 #define GE_OPT_PREFIX_BIG 3
774 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
779 /* In unified syntax, all prefixes are optional. */
781 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
786 case GE_NO_PREFIX
: break;
788 if (!is_immediate_prefix (**str
))
790 inst
.error
= _("immediate expression requires a # prefix");
796 case GE_OPT_PREFIX_BIG
:
797 if (is_immediate_prefix (**str
))
803 memset (ep
, 0, sizeof (expressionS
));
805 save_in
= input_line_pointer
;
806 input_line_pointer
= *str
;
807 in_my_get_expression
= 1;
808 seg
= expression (ep
);
809 in_my_get_expression
= 0;
811 if (ep
->X_op
== O_illegal
)
813 /* We found a bad expression in md_operand(). */
814 *str
= input_line_pointer
;
815 input_line_pointer
= save_in
;
816 if (inst
.error
== NULL
)
817 inst
.error
= _("bad expression");
822 if (seg
!= absolute_section
823 && seg
!= text_section
824 && seg
!= data_section
825 && seg
!= bss_section
826 && seg
!= undefined_section
)
828 inst
.error
= _("bad segment");
829 *str
= input_line_pointer
;
830 input_line_pointer
= save_in
;
835 /* Get rid of any bignums now, so that we don't generate an error for which
836 we can't establish a line number later on. Big numbers are never valid
837 in instructions, which is where this routine is always called. */
838 if (prefix_mode
!= GE_OPT_PREFIX_BIG
839 && (ep
->X_op
== O_big
841 && (walk_no_bignums (ep
->X_add_symbol
)
843 && walk_no_bignums (ep
->X_op_symbol
))))))
845 inst
.error
= _("invalid constant");
846 *str
= input_line_pointer
;
847 input_line_pointer
= save_in
;
851 *str
= input_line_pointer
;
852 input_line_pointer
= save_in
;
856 /* Turn a string in input_line_pointer into a floating point constant
857 of type TYPE, and store the appropriate bytes in *LITP. The number
858 of LITTLENUMS emitted is stored in *SIZEP. An error message is
859 returned, or NULL on OK.
861 Note that fp constants aren't represent in the normal way on the ARM.
862 In big endian mode, things are as expected. However, in little endian
863 mode fp constants are big-endian word-wise, and little-endian byte-wise
864 within the words. For example, (double) 1.1 in big endian mode is
865 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
866 the byte sequence 99 99 f1 3f 9a 99 99 99.
868 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
871 md_atof (int type
, char * litP
, int * sizeP
)
874 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
906 return _("bad call to MD_ATOF()");
909 t
= atof_ieee (input_line_pointer
, type
, words
);
911 input_line_pointer
= t
;
914 if (target_big_endian
)
916 for (i
= 0; i
< prec
; i
++)
918 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
924 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
925 for (i
= prec
- 1; i
>= 0; i
--)
927 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
931 /* For a 4 byte float the order of elements in `words' is 1 0.
932 For an 8 byte float the order is 1 0 3 2. */
933 for (i
= 0; i
< prec
; i
+= 2)
935 md_number_to_chars (litP
, (valueT
) words
[i
+ 1], 2);
936 md_number_to_chars (litP
+ 2, (valueT
) words
[i
], 2);
944 /* We handle all bad expressions here, so that we can report the faulty
945 instruction in the error message. */
947 md_operand (expressionS
* expr
)
949 if (in_my_get_expression
)
950 expr
->X_op
= O_illegal
;
953 /* Immediate values. */
955 /* Generic immediate-value read function for use in directives.
956 Accepts anything that 'expression' can fold to a constant.
957 *val receives the number. */
960 immediate_for_directive (int *val
)
963 exp
.X_op
= O_illegal
;
965 if (is_immediate_prefix (*input_line_pointer
))
967 input_line_pointer
++;
971 if (exp
.X_op
!= O_constant
)
973 as_bad (_("expected #constant"));
974 ignore_rest_of_line ();
977 *val
= exp
.X_add_number
;
982 /* Register parsing. */
984 /* Generic register parser. CCP points to what should be the
985 beginning of a register name. If it is indeed a valid register
986 name, advance CCP over it and return the reg_entry structure;
987 otherwise return NULL. Does not issue diagnostics. */
989 static struct reg_entry
*
990 arm_reg_parse_multi (char **ccp
)
994 struct reg_entry
*reg
;
996 #ifdef REGISTER_PREFIX
997 if (*start
!= REGISTER_PREFIX
)
1001 #ifdef OPTIONAL_REGISTER_PREFIX
1002 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1007 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1012 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1014 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1024 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1025 enum arm_reg_type type
)
1027 /* Alternative syntaxes are accepted for a few register classes. */
1034 /* Generic coprocessor register names are allowed for these. */
1035 if (reg
&& reg
->type
== REG_TYPE_CN
)
1040 /* For backward compatibility, a bare number is valid here. */
1042 unsigned long processor
= strtoul (start
, ccp
, 10);
1043 if (*ccp
!= start
&& processor
<= 15)
1047 case REG_TYPE_MMXWC
:
1048 /* WC includes WCG. ??? I'm not sure this is true for all
1049 instructions that take WC registers. */
1050 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1061 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1062 return value is the register number or FAIL. */
1065 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1068 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1071 /* Do not allow a scalar (reg+index) to parse as a register. */
1072 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1075 if (reg
&& reg
->type
== type
)
1078 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1085 /* Parse a Neon type specifier. *STR should point at the leading '.'
1086 character. Does no verification at this stage that the type fits the opcode
1093 Can all be legally parsed by this function.
1095 Fills in neon_type struct pointer with parsed information, and updates STR
1096 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1097 type, FAIL if not. */
1100 parse_neon_type (struct neon_type
*type
, char **str
)
1107 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1109 enum neon_el_type thistype
= NT_untyped
;
1110 unsigned thissize
= -1u;
1117 /* Just a size without an explicit type. */
1121 switch (TOLOWER (*ptr
))
1123 case 'i': thistype
= NT_integer
; break;
1124 case 'f': thistype
= NT_float
; break;
1125 case 'p': thistype
= NT_poly
; break;
1126 case 's': thistype
= NT_signed
; break;
1127 case 'u': thistype
= NT_unsigned
; break;
1129 thistype
= NT_float
;
1134 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1140 /* .f is an abbreviation for .f32. */
1141 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1146 thissize
= strtoul (ptr
, &ptr
, 10);
1148 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1151 as_bad (_("bad size %d in type specifier"), thissize
);
1159 type
->el
[type
->elems
].type
= thistype
;
1160 type
->el
[type
->elems
].size
= thissize
;
1165 /* Empty/missing type is not a successful parse. */
1166 if (type
->elems
== 0)
1174 /* Errors may be set multiple times during parsing or bit encoding
1175 (particularly in the Neon bits), but usually the earliest error which is set
1176 will be the most meaningful. Avoid overwriting it with later (cascading)
1177 errors by calling this function. */
1180 first_error (const char *err
)
1186 /* Parse a single type, e.g. ".s32", leading period included. */
1188 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1191 struct neon_type optype
;
1195 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1197 if (optype
.elems
== 1)
1198 *vectype
= optype
.el
[0];
1201 first_error (_("only one type should be specified for operand"));
1207 first_error (_("vector type expected"));
1219 /* Special meanings for indices (which have a range of 0-7), which will fit into
1222 #define NEON_ALL_LANES 15
1223 #define NEON_INTERLEAVE_LANES 14
1225 /* Parse either a register or a scalar, with an optional type. Return the
1226 register number, and optionally fill in the actual type of the register
1227 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1228 type/index information in *TYPEINFO. */
1231 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1232 enum arm_reg_type
*rtype
,
1233 struct neon_typed_alias
*typeinfo
)
1236 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1237 struct neon_typed_alias atype
;
1238 struct neon_type_el parsetype
;
1242 atype
.eltype
.type
= NT_invtype
;
1243 atype
.eltype
.size
= -1;
1245 /* Try alternate syntax for some types of register. Note these are mutually
1246 exclusive with the Neon syntax extensions. */
1249 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1257 /* Undo polymorphism when a set of register types may be accepted. */
1258 if ((type
== REG_TYPE_NDQ
1259 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1260 || (type
== REG_TYPE_VFSD
1261 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1262 || (type
== REG_TYPE_NSDQ
1263 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1264 || reg
->type
== REG_TYPE_NQ
))
1265 || (type
== REG_TYPE_MMXWC
1266 && (reg
->type
== REG_TYPE_MMXWCG
)))
1269 if (type
!= reg
->type
)
1275 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1277 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1279 first_error (_("can't redefine type for operand"));
1282 atype
.defined
|= NTA_HASTYPE
;
1283 atype
.eltype
= parsetype
;
1286 if (skip_past_char (&str
, '[') == SUCCESS
)
1288 if (type
!= REG_TYPE_VFD
)
1290 first_error (_("only D registers may be indexed"));
1294 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1296 first_error (_("can't change index for operand"));
1300 atype
.defined
|= NTA_HASINDEX
;
1302 if (skip_past_char (&str
, ']') == SUCCESS
)
1303 atype
.index
= NEON_ALL_LANES
;
1308 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1310 if (exp
.X_op
!= O_constant
)
1312 first_error (_("constant expression required"));
1316 if (skip_past_char (&str
, ']') == FAIL
)
1319 atype
.index
= exp
.X_add_number
;
1334 /* Like arm_reg_parse, but allow allow the following extra features:
1335 - If RTYPE is non-zero, return the (possibly restricted) type of the
1336 register (e.g. Neon double or quad reg when either has been requested).
1337 - If this is a Neon vector type with additional type information, fill
1338 in the struct pointed to by VECTYPE (if non-NULL).
1339 This function will fault on encountering a scalar.
1343 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1344 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1346 struct neon_typed_alias atype
;
1348 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1353 /* Do not allow a scalar (reg+index) to parse as a register. */
1354 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1356 first_error (_("register operand expected, but got scalar"));
1361 *vectype
= atype
.eltype
;
1368 #define NEON_SCALAR_REG(X) ((X) >> 4)
1369 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1371 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1372 have enough information to be able to do a good job bounds-checking. So, we
1373 just do easy checks here, and do further checks later. */
1376 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1380 struct neon_typed_alias atype
;
1382 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1384 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1387 if (atype
.index
== NEON_ALL_LANES
)
1389 first_error (_("scalar must have an index"));
1392 else if (atype
.index
>= 64 / elsize
)
1394 first_error (_("scalar index out of range"));
1399 *type
= atype
.eltype
;
1403 return reg
* 16 + atype
.index
;
1406 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1408 parse_reg_list (char ** strp
)
1410 char * str
= * strp
;
1414 /* We come back here if we get ranges concatenated by '+' or '|'. */
1429 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1431 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1441 first_error (_("bad range in register list"));
1445 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1447 if (range
& (1 << i
))
1449 (_("Warning: duplicated register (r%d) in register list"),
1457 if (range
& (1 << reg
))
1458 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1460 else if (reg
<= cur_reg
)
1461 as_tsktsk (_("Warning: register range not in ascending order"));
1466 while (skip_past_comma (&str
) != FAIL
1467 || (in_range
= 1, *str
++ == '-'));
1472 first_error (_("missing `}'"));
1480 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1483 if (expr
.X_op
== O_constant
)
1485 if (expr
.X_add_number
1486 != (expr
.X_add_number
& 0x0000ffff))
1488 inst
.error
= _("invalid register mask");
1492 if ((range
& expr
.X_add_number
) != 0)
1494 int regno
= range
& expr
.X_add_number
;
1497 regno
= (1 << regno
) - 1;
1499 (_("Warning: duplicated register (r%d) in register list"),
1503 range
|= expr
.X_add_number
;
1507 if (inst
.reloc
.type
!= 0)
1509 inst
.error
= _("expression too complex");
1513 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1514 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1515 inst
.reloc
.pc_rel
= 0;
1519 if (*str
== '|' || *str
== '+')
1525 while (another_range
);
1531 /* Types of registers in a list. */
1540 /* Parse a VFP register list. If the string is invalid return FAIL.
1541 Otherwise return the number of registers, and set PBASE to the first
1542 register. Parses registers of type ETYPE.
1543 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1544 - Q registers can be used to specify pairs of D registers
1545 - { } can be omitted from around a singleton register list
1546 FIXME: This is not implemented, as it would require backtracking in
1549 This could be done (the meaning isn't really ambiguous), but doesn't
1550 fit in well with the current parsing framework.
1551 - 32 D registers may be used (also true for VFPv3).
1552 FIXME: Types are ignored in these register lists, which is probably a
1556 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1561 enum arm_reg_type regtype
= 0;
1565 unsigned long mask
= 0;
1570 inst
.error
= _("expecting {");
1579 regtype
= REG_TYPE_VFS
;
1584 regtype
= REG_TYPE_VFD
;
1587 case REGLIST_NEON_D
:
1588 regtype
= REG_TYPE_NDQ
;
1592 if (etype
!= REGLIST_VFP_S
)
1594 /* VFPv3 allows 32 D registers. */
1595 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
1599 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1602 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1609 base_reg
= max_regs
;
1613 int setmask
= 1, addregs
= 1;
1615 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1617 if (new_base
== FAIL
)
1619 first_error (_(reg_expected_msgs
[regtype
]));
1623 if (new_base
>= max_regs
)
1625 first_error (_("register out of range in list"));
1629 /* Note: a value of 2 * n is returned for the register Q<n>. */
1630 if (regtype
== REG_TYPE_NQ
)
1636 if (new_base
< base_reg
)
1637 base_reg
= new_base
;
1639 if (mask
& (setmask
<< new_base
))
1641 first_error (_("invalid register list"));
1645 if ((mask
>> new_base
) != 0 && ! warned
)
1647 as_tsktsk (_("register list not in ascending order"));
1651 mask
|= setmask
<< new_base
;
1654 if (*str
== '-') /* We have the start of a range expression */
1660 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1663 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1667 if (high_range
>= max_regs
)
1669 first_error (_("register out of range in list"));
1673 if (regtype
== REG_TYPE_NQ
)
1674 high_range
= high_range
+ 1;
1676 if (high_range
<= new_base
)
1678 inst
.error
= _("register range not in ascending order");
1682 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1684 if (mask
& (setmask
<< new_base
))
1686 inst
.error
= _("invalid register list");
1690 mask
|= setmask
<< new_base
;
1695 while (skip_past_comma (&str
) != FAIL
);
1699 /* Sanity check -- should have raised a parse error above. */
1700 if (count
== 0 || count
> max_regs
)
1705 /* Final test -- the registers must be consecutive. */
1707 for (i
= 0; i
< count
; i
++)
1709 if ((mask
& (1u << i
)) == 0)
1711 inst
.error
= _("non-contiguous register range");
1721 /* True if two alias types are the same. */
1724 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1732 if (a
->defined
!= b
->defined
)
1735 if ((a
->defined
& NTA_HASTYPE
) != 0
1736 && (a
->eltype
.type
!= b
->eltype
.type
1737 || a
->eltype
.size
!= b
->eltype
.size
))
1740 if ((a
->defined
& NTA_HASINDEX
) != 0
1741 && (a
->index
!= b
->index
))
1747 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1748 The base register is put in *PBASE.
1749 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1751 The register stride (minus one) is put in bit 4 of the return value.
1752 Bits [6:5] encode the list length (minus one).
1753 The type of the list elements is put in *ELTYPE, if non-NULL. */
1755 #define NEON_LANE(X) ((X) & 0xf)
1756 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1757 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1760 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1761 struct neon_type_el
*eltype
)
1768 int leading_brace
= 0;
1769 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1771 const char *const incr_error
= "register stride must be 1 or 2";
1772 const char *const type_error
= "mismatched element/structure types in list";
1773 struct neon_typed_alias firsttype
;
1775 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1780 struct neon_typed_alias atype
;
1781 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1785 first_error (_(reg_expected_msgs
[rtype
]));
1792 if (rtype
== REG_TYPE_NQ
)
1799 else if (reg_incr
== -1)
1801 reg_incr
= getreg
- base_reg
;
1802 if (reg_incr
< 1 || reg_incr
> 2)
1804 first_error (_(incr_error
));
1808 else if (getreg
!= base_reg
+ reg_incr
* count
)
1810 first_error (_(incr_error
));
1814 if (!neon_alias_types_same (&atype
, &firsttype
))
1816 first_error (_(type_error
));
1820 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1824 struct neon_typed_alias htype
;
1825 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1827 lane
= NEON_INTERLEAVE_LANES
;
1828 else if (lane
!= NEON_INTERLEAVE_LANES
)
1830 first_error (_(type_error
));
1835 else if (reg_incr
!= 1)
1837 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1841 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1844 first_error (_(reg_expected_msgs
[rtype
]));
1847 if (!neon_alias_types_same (&htype
, &firsttype
))
1849 first_error (_(type_error
));
1852 count
+= hireg
+ dregs
- getreg
;
1856 /* If we're using Q registers, we can't use [] or [n] syntax. */
1857 if (rtype
== REG_TYPE_NQ
)
1863 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1867 else if (lane
!= atype
.index
)
1869 first_error (_(type_error
));
1873 else if (lane
== -1)
1874 lane
= NEON_INTERLEAVE_LANES
;
1875 else if (lane
!= NEON_INTERLEAVE_LANES
)
1877 first_error (_(type_error
));
1882 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1884 /* No lane set by [x]. We must be interleaving structures. */
1886 lane
= NEON_INTERLEAVE_LANES
;
1889 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1890 || (count
> 1 && reg_incr
== -1))
1892 first_error (_("error parsing element/structure list"));
1896 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
1898 first_error (_("expected }"));
1906 *eltype
= firsttype
.eltype
;
1911 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
1914 /* Parse an explicit relocation suffix on an expression. This is
1915 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1916 arm_reloc_hsh contains no entries, so this function can only
1917 succeed if there is no () after the word. Returns -1 on error,
1918 BFD_RELOC_UNUSED if there wasn't any suffix. */
1920 parse_reloc (char **str
)
1922 struct reloc_entry
*r
;
1926 return BFD_RELOC_UNUSED
;
1931 while (*q
&& *q
!= ')' && *q
!= ',')
1936 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1943 /* Directives: register aliases. */
1945 static struct reg_entry
*
1946 insert_reg_alias (char *str
, int number
, int type
)
1948 struct reg_entry
*new;
1951 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1954 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1956 /* Only warn about a redefinition if it's not defined as the
1958 else if (new->number
!= number
|| new->type
!= type
)
1959 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1964 name
= xstrdup (str
);
1965 new = xmalloc (sizeof (struct reg_entry
));
1968 new->number
= number
;
1970 new->builtin
= FALSE
;
1973 if (hash_insert (arm_reg_hsh
, name
, (PTR
) new))
1980 insert_neon_reg_alias (char *str
, int number
, int type
,
1981 struct neon_typed_alias
*atype
)
1983 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
1987 first_error (_("attempt to redefine typed alias"));
1993 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
1994 *reg
->neon
= *atype
;
1998 /* Look for the .req directive. This is of the form:
2000 new_register_name .req existing_register_name
2002 If we find one, or if it looks sufficiently like one that we want to
2003 handle any error here, return non-zero. Otherwise return zero. */
2006 create_register_alias (char * newname
, char *p
)
2008 struct reg_entry
*old
;
2009 char *oldname
, *nbuf
;
2012 /* The input scrubber ensures that whitespace after the mnemonic is
2013 collapsed to single spaces. */
2015 if (strncmp (oldname
, " .req ", 6) != 0)
2019 if (*oldname
== '\0')
2022 old
= hash_find (arm_reg_hsh
, oldname
);
2025 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2029 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2030 the desired alias name, and p points to its end. If not, then
2031 the desired alias name is in the global original_case_string. */
2032 #ifdef TC_CASE_SENSITIVE
2035 newname
= original_case_string
;
2036 nlen
= strlen (newname
);
2039 nbuf
= alloca (nlen
+ 1);
2040 memcpy (nbuf
, newname
, nlen
);
2043 /* Create aliases under the new name as stated; an all-lowercase
2044 version of the new name; and an all-uppercase version of the new
2046 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2048 for (p
= nbuf
; *p
; p
++)
2051 if (strncmp (nbuf
, newname
, nlen
))
2052 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2054 for (p
= nbuf
; *p
; p
++)
2057 if (strncmp (nbuf
, newname
, nlen
))
2058 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2063 /* Create a Neon typed/indexed register alias using directives, e.g.:
2068 These typed registers can be used instead of the types specified after the
2069 Neon mnemonic, so long as all operands given have types. Types can also be
2070 specified directly, e.g.:
2071 vadd d0.s32, d1.s32, d2.s32
2075 create_neon_reg_alias (char *newname
, char *p
)
2077 enum arm_reg_type basetype
;
2078 struct reg_entry
*basereg
;
2079 struct reg_entry mybasereg
;
2080 struct neon_type ntype
;
2081 struct neon_typed_alias typeinfo
;
2082 char *namebuf
, *nameend
;
2085 typeinfo
.defined
= 0;
2086 typeinfo
.eltype
.type
= NT_invtype
;
2087 typeinfo
.eltype
.size
= -1;
2088 typeinfo
.index
= -1;
2092 if (strncmp (p
, " .dn ", 5) == 0)
2093 basetype
= REG_TYPE_VFD
;
2094 else if (strncmp (p
, " .qn ", 5) == 0)
2095 basetype
= REG_TYPE_NQ
;
2104 basereg
= arm_reg_parse_multi (&p
);
2106 if (basereg
&& basereg
->type
!= basetype
)
2108 as_bad (_("bad type for register"));
2112 if (basereg
== NULL
)
2115 /* Try parsing as an integer. */
2116 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2117 if (exp
.X_op
!= O_constant
)
2119 as_bad (_("expression must be constant"));
2122 basereg
= &mybasereg
;
2123 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2129 typeinfo
= *basereg
->neon
;
2131 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2133 /* We got a type. */
2134 if (typeinfo
.defined
& NTA_HASTYPE
)
2136 as_bad (_("can't redefine the type of a register alias"));
2140 typeinfo
.defined
|= NTA_HASTYPE
;
2141 if (ntype
.elems
!= 1)
2143 as_bad (_("you must specify a single type only"));
2146 typeinfo
.eltype
= ntype
.el
[0];
2149 if (skip_past_char (&p
, '[') == SUCCESS
)
2152 /* We got a scalar index. */
2154 if (typeinfo
.defined
& NTA_HASINDEX
)
2156 as_bad (_("can't redefine the index of a scalar alias"));
2160 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2162 if (exp
.X_op
!= O_constant
)
2164 as_bad (_("scalar index must be constant"));
2168 typeinfo
.defined
|= NTA_HASINDEX
;
2169 typeinfo
.index
= exp
.X_add_number
;
2171 if (skip_past_char (&p
, ']') == FAIL
)
2173 as_bad (_("expecting ]"));
2178 namelen
= nameend
- newname
;
2179 namebuf
= alloca (namelen
+ 1);
2180 strncpy (namebuf
, newname
, namelen
);
2181 namebuf
[namelen
] = '\0';
2183 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2184 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2186 /* Insert name in all uppercase. */
2187 for (p
= namebuf
; *p
; p
++)
2190 if (strncmp (namebuf
, newname
, namelen
))
2191 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2192 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2194 /* Insert name in all lowercase. */
2195 for (p
= namebuf
; *p
; p
++)
2198 if (strncmp (namebuf
, newname
, namelen
))
2199 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2200 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2205 /* Should never be called, as .req goes between the alias and the
2206 register name, not at the beginning of the line. */
2208 s_req (int a ATTRIBUTE_UNUSED
)
2210 as_bad (_("invalid syntax for .req directive"));
2214 s_dn (int a ATTRIBUTE_UNUSED
)
2216 as_bad (_("invalid syntax for .dn directive"));
2220 s_qn (int a ATTRIBUTE_UNUSED
)
2222 as_bad (_("invalid syntax for .qn directive"));
2225 /* The .unreq directive deletes an alias which was previously defined
2226 by .req. For example:
2232 s_unreq (int a ATTRIBUTE_UNUSED
)
2237 name
= input_line_pointer
;
2239 while (*input_line_pointer
!= 0
2240 && *input_line_pointer
!= ' '
2241 && *input_line_pointer
!= '\n')
2242 ++input_line_pointer
;
2244 saved_char
= *input_line_pointer
;
2245 *input_line_pointer
= 0;
2248 as_bad (_("invalid syntax for .unreq directive"));
2251 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2254 as_bad (_("unknown register alias '%s'"), name
);
2255 else if (reg
->builtin
)
2256 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2260 hash_delete (arm_reg_hsh
, name
);
2261 free ((char *) reg
->name
);
2268 *input_line_pointer
= saved_char
;
2269 demand_empty_rest_of_line ();
2272 /* Directives: Instruction set selection. */
2275 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2276 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2277 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2278 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2280 static enum mstate mapstate
= MAP_UNDEFINED
;
2283 mapping_state (enum mstate state
)
2286 const char * symname
;
2289 if (mapstate
== state
)
2290 /* The mapping symbol has already been emitted.
2291 There is nothing else to do. */
2300 type
= BSF_NO_FLAGS
;
2304 type
= BSF_NO_FLAGS
;
2308 type
= BSF_NO_FLAGS
;
2316 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2318 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
2319 symbol_table_insert (symbolP
);
2320 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2325 THUMB_SET_FUNC (symbolP
, 0);
2326 ARM_SET_THUMB (symbolP
, 0);
2327 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2331 THUMB_SET_FUNC (symbolP
, 1);
2332 ARM_SET_THUMB (symbolP
, 1);
2333 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2342 #define mapping_state(x) /* nothing */
2345 /* Find the real, Thumb encoded start of a Thumb function. */
2348 find_real_start (symbolS
* symbolP
)
2351 const char * name
= S_GET_NAME (symbolP
);
2352 symbolS
* new_target
;
2354 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2355 #define STUB_NAME ".real_start_of"
2360 /* The compiler may generate BL instructions to local labels because
2361 it needs to perform a branch to a far away location. These labels
2362 do not have a corresponding ".real_start_of" label. We check
2363 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2364 the ".real_start_of" convention for nonlocal branches. */
2365 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2368 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2369 new_target
= symbol_find (real_start
);
2371 if (new_target
== NULL
)
2373 as_warn ("Failed to find real start of function: %s\n", name
);
2374 new_target
= symbolP
;
2381 opcode_select (int width
)
2388 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2389 as_bad (_("selected processor does not support THUMB opcodes"));
2392 /* No need to force the alignment, since we will have been
2393 coming from ARM mode, which is word-aligned. */
2394 record_alignment (now_seg
, 1);
2396 mapping_state (MAP_THUMB
);
2402 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2403 as_bad (_("selected processor does not support ARM opcodes"));
2408 frag_align (2, 0, 0);
2410 record_alignment (now_seg
, 1);
2412 mapping_state (MAP_ARM
);
2416 as_bad (_("invalid instruction size selected (%d)"), width
);
2421 s_arm (int ignore ATTRIBUTE_UNUSED
)
2424 demand_empty_rest_of_line ();
2428 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2431 demand_empty_rest_of_line ();
2435 s_code (int unused ATTRIBUTE_UNUSED
)
2439 temp
= get_absolute_expression ();
2444 opcode_select (temp
);
2448 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2453 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2455 /* If we are not already in thumb mode go into it, EVEN if
2456 the target processor does not support thumb instructions.
2457 This is used by gcc/config/arm/lib1funcs.asm for example
2458 to compile interworking support functions even if the
2459 target processor should not support interworking. */
2463 record_alignment (now_seg
, 1);
2466 demand_empty_rest_of_line ();
2470 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2474 /* The following label is the name/address of the start of a Thumb function.
2475 We need to know this for the interworking support. */
2476 label_is_thumb_function_name
= TRUE
;
2479 /* Perform a .set directive, but also mark the alias as
2480 being a thumb function. */
2483 s_thumb_set (int equiv
)
2485 /* XXX the following is a duplicate of the code for s_set() in read.c
2486 We cannot just call that code as we need to get at the symbol that
2493 /* Especial apologies for the random logic:
2494 This just grew, and could be parsed much more simply!
2496 name
= input_line_pointer
;
2497 delim
= get_symbol_end ();
2498 end_name
= input_line_pointer
;
2501 if (*input_line_pointer
!= ',')
2504 as_bad (_("expected comma after name \"%s\""), name
);
2506 ignore_rest_of_line ();
2510 input_line_pointer
++;
2513 if (name
[0] == '.' && name
[1] == '\0')
2515 /* XXX - this should not happen to .thumb_set. */
2519 if ((symbolP
= symbol_find (name
)) == NULL
2520 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2523 /* When doing symbol listings, play games with dummy fragments living
2524 outside the normal fragment chain to record the file and line info
2526 if (listing
& LISTING_SYMBOLS
)
2528 extern struct list_info_struct
* listing_tail
;
2529 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2531 memset (dummy_frag
, 0, sizeof (fragS
));
2532 dummy_frag
->fr_type
= rs_fill
;
2533 dummy_frag
->line
= listing_tail
;
2534 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2535 dummy_frag
->fr_symbol
= symbolP
;
2539 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2542 /* "set" symbols are local unless otherwise specified. */
2543 SF_SET_LOCAL (symbolP
);
2544 #endif /* OBJ_COFF */
2545 } /* Make a new symbol. */
2547 symbol_table_insert (symbolP
);
2552 && S_IS_DEFINED (symbolP
)
2553 && S_GET_SEGMENT (symbolP
) != reg_section
)
2554 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2556 pseudo_set (symbolP
);
2558 demand_empty_rest_of_line ();
2560 /* XXX Now we come to the Thumb specific bit of code. */
2562 THUMB_SET_FUNC (symbolP
, 1);
2563 ARM_SET_THUMB (symbolP
, 1);
2564 #if defined OBJ_ELF || defined OBJ_COFF
2565 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2569 /* Directives: Mode selection. */
2571 /* .syntax [unified|divided] - choose the new unified syntax
2572 (same for Arm and Thumb encoding, modulo slight differences in what
2573 can be represented) or the old divergent syntax for each mode. */
2575 s_syntax (int unused ATTRIBUTE_UNUSED
)
2579 name
= input_line_pointer
;
2580 delim
= get_symbol_end ();
2582 if (!strcasecmp (name
, "unified"))
2583 unified_syntax
= TRUE
;
2584 else if (!strcasecmp (name
, "divided"))
2585 unified_syntax
= FALSE
;
2588 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2591 *input_line_pointer
= delim
;
2592 demand_empty_rest_of_line ();
2595 /* Directives: sectioning and alignment. */
2597 /* Same as s_align_ptwo but align 0 => align 2. */
2600 s_align (int unused ATTRIBUTE_UNUSED
)
2604 long max_alignment
= 15;
2606 temp
= get_absolute_expression ();
2607 if (temp
> max_alignment
)
2608 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2611 as_bad (_("alignment negative. 0 assumed."));
2615 if (*input_line_pointer
== ',')
2617 input_line_pointer
++;
2618 temp_fill
= get_absolute_expression ();
2626 /* Only make a frag if we HAVE to. */
2627 if (temp
&& !need_pass_2
)
2628 frag_align (temp
, (int) temp_fill
, 0);
2629 demand_empty_rest_of_line ();
2631 record_alignment (now_seg
, temp
);
2635 s_bss (int ignore ATTRIBUTE_UNUSED
)
2637 /* We don't support putting frags in the BSS segment, we fake it by
2638 marking in_bss, then looking at s_skip for clues. */
2639 subseg_set (bss_section
, 0);
2640 demand_empty_rest_of_line ();
2641 mapping_state (MAP_DATA
);
2645 s_even (int ignore ATTRIBUTE_UNUSED
)
2647 /* Never make frag if expect extra pass. */
2649 frag_align (1, 0, 0);
2651 record_alignment (now_seg
, 1);
2653 demand_empty_rest_of_line ();
2656 /* Directives: Literal pools. */
2658 static literal_pool
*
2659 find_literal_pool (void)
2661 literal_pool
* pool
;
2663 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2665 if (pool
->section
== now_seg
2666 && pool
->sub_section
== now_subseg
)
2673 static literal_pool
*
2674 find_or_make_literal_pool (void)
2676 /* Next literal pool ID number. */
2677 static unsigned int latest_pool_num
= 1;
2678 literal_pool
* pool
;
2680 pool
= find_literal_pool ();
2684 /* Create a new pool. */
2685 pool
= xmalloc (sizeof (* pool
));
2689 pool
->next_free_entry
= 0;
2690 pool
->section
= now_seg
;
2691 pool
->sub_section
= now_subseg
;
2692 pool
->next
= list_of_pools
;
2693 pool
->symbol
= NULL
;
2695 /* Add it to the list. */
2696 list_of_pools
= pool
;
2699 /* New pools, and emptied pools, will have a NULL symbol. */
2700 if (pool
->symbol
== NULL
)
2702 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2703 (valueT
) 0, &zero_address_frag
);
2704 pool
->id
= latest_pool_num
++;
2711 /* Add the literal in the global 'inst'
2712 structure to the relevent literal pool. */
2715 add_to_lit_pool (void)
2717 literal_pool
* pool
;
2720 pool
= find_or_make_literal_pool ();
2722 /* Check if this literal value is already in the pool. */
2723 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2725 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2726 && (inst
.reloc
.exp
.X_op
== O_constant
)
2727 && (pool
->literals
[entry
].X_add_number
2728 == inst
.reloc
.exp
.X_add_number
)
2729 && (pool
->literals
[entry
].X_unsigned
2730 == inst
.reloc
.exp
.X_unsigned
))
2733 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2734 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2735 && (pool
->literals
[entry
].X_add_number
2736 == inst
.reloc
.exp
.X_add_number
)
2737 && (pool
->literals
[entry
].X_add_symbol
2738 == inst
.reloc
.exp
.X_add_symbol
)
2739 && (pool
->literals
[entry
].X_op_symbol
2740 == inst
.reloc
.exp
.X_op_symbol
))
2744 /* Do we need to create a new entry? */
2745 if (entry
== pool
->next_free_entry
)
2747 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2749 inst
.error
= _("literal pool overflow");
2753 pool
->literals
[entry
] = inst
.reloc
.exp
;
2754 pool
->next_free_entry
+= 1;
2757 inst
.reloc
.exp
.X_op
= O_symbol
;
2758 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
2759 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
2764 /* Can't use symbol_new here, so have to create a symbol and then at
2765 a later date assign it a value. Thats what these functions do. */
2768 symbol_locate (symbolS
* symbolP
,
2769 const char * name
, /* It is copied, the caller can modify. */
2770 segT segment
, /* Segment identifier (SEG_<something>). */
2771 valueT valu
, /* Symbol value. */
2772 fragS
* frag
) /* Associated fragment. */
2774 unsigned int name_length
;
2775 char * preserved_copy_of_name
;
2777 name_length
= strlen (name
) + 1; /* +1 for \0. */
2778 obstack_grow (¬es
, name
, name_length
);
2779 preserved_copy_of_name
= obstack_finish (¬es
);
2781 #ifdef tc_canonicalize_symbol_name
2782 preserved_copy_of_name
=
2783 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2786 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2788 S_SET_SEGMENT (symbolP
, segment
);
2789 S_SET_VALUE (symbolP
, valu
);
2790 symbol_clear_list_pointers (symbolP
);
2792 symbol_set_frag (symbolP
, frag
);
2794 /* Link to end of symbol chain. */
2796 extern int symbol_table_frozen
;
2798 if (symbol_table_frozen
)
2802 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
2804 obj_symbol_new_hook (symbolP
);
2806 #ifdef tc_symbol_new_hook
2807 tc_symbol_new_hook (symbolP
);
2811 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2812 #endif /* DEBUG_SYMS */
2817 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2820 literal_pool
* pool
;
2823 pool
= find_literal_pool ();
2825 || pool
->symbol
== NULL
2826 || pool
->next_free_entry
== 0)
2829 mapping_state (MAP_DATA
);
2831 /* Align pool as you have word accesses.
2832 Only make a frag if we have to. */
2834 frag_align (2, 0, 0);
2836 record_alignment (now_seg
, 2);
2838 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2840 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2841 (valueT
) frag_now_fix (), frag_now
);
2842 symbol_table_insert (pool
->symbol
);
2844 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
2846 #if defined OBJ_COFF || defined OBJ_ELF
2847 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
2850 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2851 /* First output the expression in the instruction to the pool. */
2852 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
2854 /* Mark the pool as empty. */
2855 pool
->next_free_entry
= 0;
2856 pool
->symbol
= NULL
;
2860 /* Forward declarations for functions below, in the MD interface
2862 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
2863 static valueT
create_unwind_entry (int);
2864 static void start_unwind_section (const segT
, int);
2865 static void add_unwind_opcode (valueT
, int);
2866 static void flush_pending_unwind (void);
2868 /* Directives: Data. */
2871 s_arm_elf_cons (int nbytes
)
2875 #ifdef md_flush_pending_output
2876 md_flush_pending_output ();
2879 if (is_it_end_of_statement ())
2881 demand_empty_rest_of_line ();
2885 #ifdef md_cons_align
2886 md_cons_align (nbytes
);
2889 mapping_state (MAP_DATA
);
2893 char *base
= input_line_pointer
;
2897 if (exp
.X_op
!= O_symbol
)
2898 emit_expr (&exp
, (unsigned int) nbytes
);
2901 char *before_reloc
= input_line_pointer
;
2902 reloc
= parse_reloc (&input_line_pointer
);
2905 as_bad (_("unrecognized relocation suffix"));
2906 ignore_rest_of_line ();
2909 else if (reloc
== BFD_RELOC_UNUSED
)
2910 emit_expr (&exp
, (unsigned int) nbytes
);
2913 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2914 int size
= bfd_get_reloc_size (howto
);
2916 if (reloc
== BFD_RELOC_ARM_PLT32
)
2918 as_bad (_("(plt) is only valid on branch targets"));
2919 reloc
= BFD_RELOC_UNUSED
;
2924 as_bad (_("%s relocations do not fit in %d bytes"),
2925 howto
->name
, nbytes
);
2928 /* We've parsed an expression stopping at O_symbol.
2929 But there may be more expression left now that we
2930 have parsed the relocation marker. Parse it again.
2931 XXX Surely there is a cleaner way to do this. */
2932 char *p
= input_line_pointer
;
2934 char *save_buf
= alloca (input_line_pointer
- base
);
2935 memcpy (save_buf
, base
, input_line_pointer
- base
);
2936 memmove (base
+ (input_line_pointer
- before_reloc
),
2937 base
, before_reloc
- base
);
2939 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
2941 memcpy (base
, save_buf
, p
- base
);
2943 offset
= nbytes
- size
;
2944 p
= frag_more ((int) nbytes
);
2945 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
2946 size
, &exp
, 0, reloc
);
2951 while (*input_line_pointer
++ == ',');
2953 /* Put terminator back into stream. */
2954 input_line_pointer
--;
2955 demand_empty_rest_of_line ();
2959 /* Parse a .rel31 directive. */
2962 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
2969 if (*input_line_pointer
== '1')
2970 highbit
= 0x80000000;
2971 else if (*input_line_pointer
!= '0')
2972 as_bad (_("expected 0 or 1"));
2974 input_line_pointer
++;
2975 if (*input_line_pointer
!= ',')
2976 as_bad (_("missing comma"));
2977 input_line_pointer
++;
2979 #ifdef md_flush_pending_output
2980 md_flush_pending_output ();
2983 #ifdef md_cons_align
2987 mapping_state (MAP_DATA
);
2992 md_number_to_chars (p
, highbit
, 4);
2993 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
2994 BFD_RELOC_ARM_PREL31
);
2996 demand_empty_rest_of_line ();
2999 /* Directives: AEABI stack-unwind tables. */
3001 /* Parse an unwind_fnstart directive. Simply records the current location. */
3004 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3006 demand_empty_rest_of_line ();
3007 /* Mark the start of the function. */
3008 unwind
.proc_start
= expr_build_dot ();
3010 /* Reset the rest of the unwind info. */
3011 unwind
.opcode_count
= 0;
3012 unwind
.table_entry
= NULL
;
3013 unwind
.personality_routine
= NULL
;
3014 unwind
.personality_index
= -1;
3015 unwind
.frame_size
= 0;
3016 unwind
.fp_offset
= 0;
3019 unwind
.sp_restored
= 0;
3023 /* Parse a handlerdata directive. Creates the exception handling table entry
3024 for the function. */
3027 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3029 demand_empty_rest_of_line ();
3030 if (unwind
.table_entry
)
3031 as_bad (_("dupicate .handlerdata directive"));
3033 create_unwind_entry (1);
3036 /* Parse an unwind_fnend directive. Generates the index table entry. */
3039 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3045 demand_empty_rest_of_line ();
3047 /* Add eh table entry. */
3048 if (unwind
.table_entry
== NULL
)
3049 val
= create_unwind_entry (0);
3053 /* Add index table entry. This is two words. */
3054 start_unwind_section (unwind
.saved_seg
, 1);
3055 frag_align (2, 0, 0);
3056 record_alignment (now_seg
, 2);
3058 ptr
= frag_more (8);
3059 where
= frag_now_fix () - 8;
3061 /* Self relative offset of the function start. */
3062 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3063 BFD_RELOC_ARM_PREL31
);
3065 /* Indicate dependency on EHABI-defined personality routines to the
3066 linker, if it hasn't been done already. */
3067 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3068 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3070 static const char *const name
[] = {
3071 "__aeabi_unwind_cpp_pr0",
3072 "__aeabi_unwind_cpp_pr1",
3073 "__aeabi_unwind_cpp_pr2"
3075 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3076 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3077 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3078 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3079 = marked_pr_dependency
;
3083 /* Inline exception table entry. */
3084 md_number_to_chars (ptr
+ 4, val
, 4);
3086 /* Self relative offset of the table entry. */
3087 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3088 BFD_RELOC_ARM_PREL31
);
3090 /* Restore the original section. */
3091 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3095 /* Parse an unwind_cantunwind directive. */
3098 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3100 demand_empty_rest_of_line ();
3101 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3102 as_bad (_("personality routine specified for cantunwind frame"));
3104 unwind
.personality_index
= -2;
3108 /* Parse a personalityindex directive. */
3111 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3115 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3116 as_bad (_("duplicate .personalityindex directive"));
3120 if (exp
.X_op
!= O_constant
3121 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3123 as_bad (_("bad personality routine number"));
3124 ignore_rest_of_line ();
3128 unwind
.personality_index
= exp
.X_add_number
;
3130 demand_empty_rest_of_line ();
3134 /* Parse a personality directive. */
3137 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3141 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3142 as_bad (_("duplicate .personality directive"));
3144 name
= input_line_pointer
;
3145 c
= get_symbol_end ();
3146 p
= input_line_pointer
;
3147 unwind
.personality_routine
= symbol_find_or_make (name
);
3149 demand_empty_rest_of_line ();
3153 /* Parse a directive saving core registers. */
3156 s_arm_unwind_save_core (void)
3162 range
= parse_reg_list (&input_line_pointer
);
3165 as_bad (_("expected register list"));
3166 ignore_rest_of_line ();
3170 demand_empty_rest_of_line ();
3172 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3173 into .unwind_save {..., sp...}. We aren't bothered about the value of
3174 ip because it is clobbered by calls. */
3175 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3176 && (range
& 0x3000) == 0x1000)
3178 unwind
.opcode_count
--;
3179 unwind
.sp_restored
= 0;
3180 range
= (range
| 0x2000) & ~0x1000;
3181 unwind
.pending_offset
= 0;
3187 /* See if we can use the short opcodes. These pop a block of up to 8
3188 registers starting with r4, plus maybe r14. */
3189 for (n
= 0; n
< 8; n
++)
3191 /* Break at the first non-saved register. */
3192 if ((range
& (1 << (n
+ 4))) == 0)
3195 /* See if there are any other bits set. */
3196 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3198 /* Use the long form. */
3199 op
= 0x8000 | ((range
>> 4) & 0xfff);
3200 add_unwind_opcode (op
, 2);
3204 /* Use the short form. */
3206 op
= 0xa8; /* Pop r14. */
3208 op
= 0xa0; /* Do not pop r14. */
3210 add_unwind_opcode (op
, 1);
3217 op
= 0xb100 | (range
& 0xf);
3218 add_unwind_opcode (op
, 2);
3221 /* Record the number of bytes pushed. */
3222 for (n
= 0; n
< 16; n
++)
3224 if (range
& (1 << n
))
3225 unwind
.frame_size
+= 4;
3230 /* Parse a directive saving FPA registers. */
3233 s_arm_unwind_save_fpa (int reg
)
3239 /* Get Number of registers to transfer. */
3240 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3243 exp
.X_op
= O_illegal
;
3245 if (exp
.X_op
!= O_constant
)
3247 as_bad (_("expected , <constant>"));
3248 ignore_rest_of_line ();
3252 num_regs
= exp
.X_add_number
;
3254 if (num_regs
< 1 || num_regs
> 4)
3256 as_bad (_("number of registers must be in the range [1:4]"));
3257 ignore_rest_of_line ();
3261 demand_empty_rest_of_line ();
3266 op
= 0xb4 | (num_regs
- 1);
3267 add_unwind_opcode (op
, 1);
3272 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3273 add_unwind_opcode (op
, 2);
3275 unwind
.frame_size
+= num_regs
* 12;
3279 /* Parse a directive saving VFP registers for ARMv6 and above. */
3282 s_arm_unwind_save_vfp_armv6 (void)
3287 int num_vfpv3_regs
= 0;
3288 int num_regs_below_16
;
3290 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3293 as_bad (_("expected register list"));
3294 ignore_rest_of_line ();
3298 demand_empty_rest_of_line ();
3300 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3301 than FSTMX/FLDMX-style ones). */
3303 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3305 num_vfpv3_regs
= count
;
3306 else if (start
+ count
> 16)
3307 num_vfpv3_regs
= start
+ count
- 16;
3309 if (num_vfpv3_regs
> 0)
3311 int start_offset
= start
> 16 ? start
- 16 : 0;
3312 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3313 add_unwind_opcode (op
, 2);
3316 /* Generate opcode for registers numbered in the range 0 .. 15. */
3317 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3318 assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3319 if (num_regs_below_16
> 0)
3321 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3322 add_unwind_opcode (op
, 2);
3325 unwind
.frame_size
+= count
* 8;
3329 /* Parse a directive saving VFP registers for pre-ARMv6. */
3332 s_arm_unwind_save_vfp (void)
3338 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3341 as_bad (_("expected register list"));
3342 ignore_rest_of_line ();
3346 demand_empty_rest_of_line ();
3351 op
= 0xb8 | (count
- 1);
3352 add_unwind_opcode (op
, 1);
3357 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3358 add_unwind_opcode (op
, 2);
3360 unwind
.frame_size
+= count
* 8 + 4;
3364 /* Parse a directive saving iWMMXt data registers. */
3367 s_arm_unwind_save_mmxwr (void)
3375 if (*input_line_pointer
== '{')
3376 input_line_pointer
++;
3380 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3384 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3389 as_tsktsk (_("register list not in ascending order"));
3392 if (*input_line_pointer
== '-')
3394 input_line_pointer
++;
3395 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3398 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3401 else if (reg
>= hi_reg
)
3403 as_bad (_("bad register range"));
3406 for (; reg
< hi_reg
; reg
++)
3410 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3412 if (*input_line_pointer
== '}')
3413 input_line_pointer
++;
3415 demand_empty_rest_of_line ();
3417 /* Generate any deferred opcodes because we're going to be looking at
3419 flush_pending_unwind ();
3421 for (i
= 0; i
< 16; i
++)
3423 if (mask
& (1 << i
))
3424 unwind
.frame_size
+= 8;
3427 /* Attempt to combine with a previous opcode. We do this because gcc
3428 likes to output separate unwind directives for a single block of
3430 if (unwind
.opcode_count
> 0)
3432 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3433 if ((i
& 0xf8) == 0xc0)
3436 /* Only merge if the blocks are contiguous. */
3439 if ((mask
& 0xfe00) == (1 << 9))
3441 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3442 unwind
.opcode_count
--;
3445 else if (i
== 6 && unwind
.opcode_count
>= 2)
3447 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3451 op
= 0xffff << (reg
- 1);
3453 && ((mask
& op
) == (1u << (reg
- 1))))
3455 op
= (1 << (reg
+ i
+ 1)) - 1;
3456 op
&= ~((1 << reg
) - 1);
3458 unwind
.opcode_count
-= 2;
3465 /* We want to generate opcodes in the order the registers have been
3466 saved, ie. descending order. */
3467 for (reg
= 15; reg
>= -1; reg
--)
3469 /* Save registers in blocks. */
3471 || !(mask
& (1 << reg
)))
3473 /* We found an unsaved reg. Generate opcodes to save the
3474 preceeding block. */
3480 op
= 0xc0 | (hi_reg
- 10);
3481 add_unwind_opcode (op
, 1);
3486 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3487 add_unwind_opcode (op
, 2);
3496 ignore_rest_of_line ();
3500 s_arm_unwind_save_mmxwcg (void)
3507 if (*input_line_pointer
== '{')
3508 input_line_pointer
++;
3512 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3516 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3522 as_tsktsk (_("register list not in ascending order"));
3525 if (*input_line_pointer
== '-')
3527 input_line_pointer
++;
3528 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3531 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3534 else if (reg
>= hi_reg
)
3536 as_bad (_("bad register range"));
3539 for (; reg
< hi_reg
; reg
++)
3543 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3545 if (*input_line_pointer
== '}')
3546 input_line_pointer
++;
3548 demand_empty_rest_of_line ();
3550 /* Generate any deferred opcodes because we're going to be looking at
3552 flush_pending_unwind ();
3554 for (reg
= 0; reg
< 16; reg
++)
3556 if (mask
& (1 << reg
))
3557 unwind
.frame_size
+= 4;
3560 add_unwind_opcode (op
, 2);
3563 ignore_rest_of_line ();
3567 /* Parse an unwind_save directive.
3568 If the argument is non-zero, this is a .vsave directive. */
3571 s_arm_unwind_save (int arch_v6
)
3574 struct reg_entry
*reg
;
3575 bfd_boolean had_brace
= FALSE
;
3577 /* Figure out what sort of save we have. */
3578 peek
= input_line_pointer
;
3586 reg
= arm_reg_parse_multi (&peek
);
3590 as_bad (_("register expected"));
3591 ignore_rest_of_line ();
3600 as_bad (_("FPA .unwind_save does not take a register list"));
3601 ignore_rest_of_line ();
3604 s_arm_unwind_save_fpa (reg
->number
);
3607 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
3610 s_arm_unwind_save_vfp_armv6 ();
3612 s_arm_unwind_save_vfp ();
3614 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
3615 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
3618 as_bad (_(".unwind_save does not support this kind of register"));
3619 ignore_rest_of_line ();
3624 /* Parse an unwind_movsp directive. */
3627 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
3632 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3635 as_bad (_(reg_expected_msgs
[REG_TYPE_RN
]));
3636 ignore_rest_of_line ();
3639 demand_empty_rest_of_line ();
3641 if (reg
== REG_SP
|| reg
== REG_PC
)
3643 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3647 if (unwind
.fp_reg
!= REG_SP
)
3648 as_bad (_("unexpected .unwind_movsp directive"));
3650 /* Generate opcode to restore the value. */
3652 add_unwind_opcode (op
, 1);
3654 /* Record the information for later. */
3655 unwind
.fp_reg
= reg
;
3656 unwind
.fp_offset
= unwind
.frame_size
;
3657 unwind
.sp_restored
= 1;
3660 /* Parse an unwind_pad directive. */
3663 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
3667 if (immediate_for_directive (&offset
) == FAIL
)
3672 as_bad (_("stack increment must be multiple of 4"));
3673 ignore_rest_of_line ();
3677 /* Don't generate any opcodes, just record the details for later. */
3678 unwind
.frame_size
+= offset
;
3679 unwind
.pending_offset
+= offset
;
3681 demand_empty_rest_of_line ();
3684 /* Parse an unwind_setfp directive. */
3687 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
3693 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3694 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3697 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3699 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
3701 as_bad (_("expected <reg>, <reg>"));
3702 ignore_rest_of_line ();
3706 /* Optional constant. */
3707 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3709 if (immediate_for_directive (&offset
) == FAIL
)
3715 demand_empty_rest_of_line ();
3717 if (sp_reg
!= 13 && sp_reg
!= unwind
.fp_reg
)
3719 as_bad (_("register must be either sp or set by a previous"
3720 "unwind_movsp directive"));
3724 /* Don't generate any opcodes, just record the information for later. */
3725 unwind
.fp_reg
= fp_reg
;
3728 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3730 unwind
.fp_offset
-= offset
;
3733 /* Parse an unwind_raw directive. */
3736 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
3739 /* This is an arbitrary limit. */
3740 unsigned char op
[16];
3744 if (exp
.X_op
== O_constant
3745 && skip_past_comma (&input_line_pointer
) != FAIL
)
3747 unwind
.frame_size
+= exp
.X_add_number
;
3751 exp
.X_op
= O_illegal
;
3753 if (exp
.X_op
!= O_constant
)
3755 as_bad (_("expected <offset>, <opcode>"));
3756 ignore_rest_of_line ();
3762 /* Parse the opcode. */
3767 as_bad (_("unwind opcode too long"));
3768 ignore_rest_of_line ();
3770 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
3772 as_bad (_("invalid unwind opcode"));
3773 ignore_rest_of_line ();
3776 op
[count
++] = exp
.X_add_number
;
3778 /* Parse the next byte. */
3779 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3785 /* Add the opcode bytes in reverse order. */
3787 add_unwind_opcode (op
[count
], 1);
3789 demand_empty_rest_of_line ();
3793 /* Parse a .eabi_attribute directive. */
3796 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
3799 bfd_boolean is_string
;
3806 if (exp
.X_op
!= O_constant
)
3809 tag
= exp
.X_add_number
;
3810 if (tag
== 4 || tag
== 5 || tag
== 32 || (tag
> 32 && (tag
& 1) != 0))
3815 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3817 if (tag
== 32 || !is_string
)
3820 if (exp
.X_op
!= O_constant
)
3822 as_bad (_("expected numeric constant"));
3823 ignore_rest_of_line ();
3826 i
= exp
.X_add_number
;
3828 if (tag
== Tag_compatibility
3829 && skip_past_comma (&input_line_pointer
) == FAIL
)
3831 as_bad (_("expected comma"));
3832 ignore_rest_of_line ();
3837 skip_whitespace(input_line_pointer
);
3838 if (*input_line_pointer
!= '"')
3840 input_line_pointer
++;
3841 s
= input_line_pointer
;
3842 while (*input_line_pointer
&& *input_line_pointer
!= '"')
3843 input_line_pointer
++;
3844 if (*input_line_pointer
!= '"')
3846 saved_char
= *input_line_pointer
;
3847 *input_line_pointer
= 0;
3855 if (tag
== Tag_compatibility
)
3856 elf32_arm_add_eabi_attr_compat (stdoutput
, i
, s
);
3858 elf32_arm_add_eabi_attr_string (stdoutput
, tag
, s
);
3860 elf32_arm_add_eabi_attr_int (stdoutput
, tag
, i
);
3864 *input_line_pointer
= saved_char
;
3865 input_line_pointer
++;
3867 demand_empty_rest_of_line ();
3870 as_bad (_("bad string constant"));
3871 ignore_rest_of_line ();
3874 as_bad (_("expected <tag> , <value>"));
3875 ignore_rest_of_line ();
3877 #endif /* OBJ_ELF */
3879 static void s_arm_arch (int);
3880 static void s_arm_cpu (int);
3881 static void s_arm_fpu (int);
3886 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
3893 if (exp
.X_op
== O_symbol
)
3894 exp
.X_op
= O_secrel
;
3896 emit_expr (&exp
, 4);
3898 while (*input_line_pointer
++ == ',');
3900 input_line_pointer
--;
3901 demand_empty_rest_of_line ();
3905 /* This table describes all the machine specific pseudo-ops the assembler
3906 has to support. The fields are:
3907 pseudo-op name without dot
3908 function to call to execute this pseudo-op
3909 Integer arg to pass to the function. */
3911 const pseudo_typeS md_pseudo_table
[] =
3913 /* Never called because '.req' does not start a line. */
3914 { "req", s_req
, 0 },
3915 /* Following two are likewise never called. */
3918 { "unreq", s_unreq
, 0 },
3919 { "bss", s_bss
, 0 },
3920 { "align", s_align
, 0 },
3921 { "arm", s_arm
, 0 },
3922 { "thumb", s_thumb
, 0 },
3923 { "code", s_code
, 0 },
3924 { "force_thumb", s_force_thumb
, 0 },
3925 { "thumb_func", s_thumb_func
, 0 },
3926 { "thumb_set", s_thumb_set
, 0 },
3927 { "even", s_even
, 0 },
3928 { "ltorg", s_ltorg
, 0 },
3929 { "pool", s_ltorg
, 0 },
3930 { "syntax", s_syntax
, 0 },
3931 { "cpu", s_arm_cpu
, 0 },
3932 { "arch", s_arm_arch
, 0 },
3933 { "fpu", s_arm_fpu
, 0 },
3935 { "word", s_arm_elf_cons
, 4 },
3936 { "long", s_arm_elf_cons
, 4 },
3937 { "rel31", s_arm_rel31
, 0 },
3938 { "fnstart", s_arm_unwind_fnstart
, 0 },
3939 { "fnend", s_arm_unwind_fnend
, 0 },
3940 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
3941 { "personality", s_arm_unwind_personality
, 0 },
3942 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
3943 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
3944 { "save", s_arm_unwind_save
, 0 },
3945 { "vsave", s_arm_unwind_save
, 1 },
3946 { "movsp", s_arm_unwind_movsp
, 0 },
3947 { "pad", s_arm_unwind_pad
, 0 },
3948 { "setfp", s_arm_unwind_setfp
, 0 },
3949 { "unwind_raw", s_arm_unwind_raw
, 0 },
3950 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
3954 /* These are used for dwarf. */
3958 /* These are used for dwarf2. */
3959 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
3960 { "loc", dwarf2_directive_loc
, 0 },
3961 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
3963 { "extend", float_cons
, 'x' },
3964 { "ldouble", float_cons
, 'x' },
3965 { "packed", float_cons
, 'p' },
3967 {"secrel32", pe_directive_secrel
, 0},
3972 /* Parser functions used exclusively in instruction operands. */
3974 /* Generic immediate-value read function for use in insn parsing.
3975 STR points to the beginning of the immediate (the leading #);
3976 VAL receives the value; if the value is outside [MIN, MAX]
3977 issue an error. PREFIX_OPT is true if the immediate prefix is
3981 parse_immediate (char **str
, int *val
, int min
, int max
,
3982 bfd_boolean prefix_opt
)
3985 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
3986 if (exp
.X_op
!= O_constant
)
3988 inst
.error
= _("constant expression required");
3992 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
3994 inst
.error
= _("immediate value out of range");
3998 *val
= exp
.X_add_number
;
4002 /* Less-generic immediate-value read function with the possibility of loading a
4003 big (64-bit) immediate, as required by Neon VMOV and VMVN immediate
4004 instructions. Puts the result directly in inst.operands[i]. */
4007 parse_big_immediate (char **str
, int i
)
4012 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4014 if (exp
.X_op
== O_constant
)
4015 inst
.operands
[i
].imm
= exp
.X_add_number
;
4016 else if (exp
.X_op
== O_big
4017 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4018 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4020 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4021 /* Bignums have their least significant bits in
4022 generic_bignum[0]. Make sure we put 32 bits in imm and
4023 32 bits in reg, in a (hopefully) portable way. */
4024 assert (parts
!= 0);
4025 inst
.operands
[i
].imm
= 0;
4026 for (j
= 0; j
< parts
; j
++, idx
++)
4027 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4028 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4029 inst
.operands
[i
].reg
= 0;
4030 for (j
= 0; j
< parts
; j
++, idx
++)
4031 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4032 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4033 inst
.operands
[i
].regisimm
= 1;
4043 /* Returns the pseudo-register number of an FPA immediate constant,
4044 or FAIL if there isn't a valid constant here. */
4047 parse_fpa_immediate (char ** str
)
4049 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4055 /* First try and match exact strings, this is to guarantee
4056 that some formats will work even for cross assembly. */
4058 for (i
= 0; fp_const
[i
]; i
++)
4060 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4064 *str
+= strlen (fp_const
[i
]);
4065 if (is_end_of_line
[(unsigned char) **str
])
4071 /* Just because we didn't get a match doesn't mean that the constant
4072 isn't valid, just that it is in a format that we don't
4073 automatically recognize. Try parsing it with the standard
4074 expression routines. */
4076 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4078 /* Look for a raw floating point number. */
4079 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4080 && is_end_of_line
[(unsigned char) *save_in
])
4082 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4084 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4086 if (words
[j
] != fp_values
[i
][j
])
4090 if (j
== MAX_LITTLENUMS
)
4098 /* Try and parse a more complex expression, this will probably fail
4099 unless the code uses a floating point prefix (eg "0f"). */
4100 save_in
= input_line_pointer
;
4101 input_line_pointer
= *str
;
4102 if (expression (&exp
) == absolute_section
4103 && exp
.X_op
== O_big
4104 && exp
.X_add_number
< 0)
4106 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4108 if (gen_to_words (words
, 5, (long) 15) == 0)
4110 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4112 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4114 if (words
[j
] != fp_values
[i
][j
])
4118 if (j
== MAX_LITTLENUMS
)
4120 *str
= input_line_pointer
;
4121 input_line_pointer
= save_in
;
4128 *str
= input_line_pointer
;
4129 input_line_pointer
= save_in
;
4130 inst
.error
= _("invalid FPA immediate expression");
4134 /* Returns 1 if a number has "quarter-precision" float format
4135 0baBbbbbbc defgh000 00000000 00000000. */
4138 is_quarter_float (unsigned imm
)
4140 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4141 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4144 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4145 0baBbbbbbc defgh000 00000000 00000000.
4146 The minus-zero case needs special handling, since it can't be encoded in the
4147 "quarter-precision" float format, but can nonetheless be loaded as an integer
4151 parse_qfloat_immediate (char **ccp
, int *immed
)
4154 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4156 skip_past_char (&str
, '#');
4158 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4160 unsigned fpword
= 0;
4163 /* Our FP word must be 32 bits (single-precision FP). */
4164 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4166 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4170 if (is_quarter_float (fpword
) || fpword
== 0x80000000)
4183 /* Shift operands. */
4186 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4189 struct asm_shift_name
4192 enum shift_kind kind
;
4195 /* Third argument to parse_shift. */
4196 enum parse_shift_mode
4198 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4199 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4200 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4201 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4202 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4205 /* Parse a <shift> specifier on an ARM data processing instruction.
4206 This has three forms:
4208 (LSL|LSR|ASL|ASR|ROR) Rs
4209 (LSL|LSR|ASL|ASR|ROR) #imm
4212 Note that ASL is assimilated to LSL in the instruction encoding, and
4213 RRX to ROR #0 (which cannot be written as such). */
4216 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4218 const struct asm_shift_name
*shift_name
;
4219 enum shift_kind shift
;
4224 for (p
= *str
; ISALPHA (*p
); p
++)
4229 inst
.error
= _("shift expression expected");
4233 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4235 if (shift_name
== NULL
)
4237 inst
.error
= _("shift expression expected");
4241 shift
= shift_name
->kind
;
4245 case NO_SHIFT_RESTRICT
:
4246 case SHIFT_IMMEDIATE
: break;
4248 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4249 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4251 inst
.error
= _("'LSL' or 'ASR' required");
4256 case SHIFT_LSL_IMMEDIATE
:
4257 if (shift
!= SHIFT_LSL
)
4259 inst
.error
= _("'LSL' required");
4264 case SHIFT_ASR_IMMEDIATE
:
4265 if (shift
!= SHIFT_ASR
)
4267 inst
.error
= _("'ASR' required");
4275 if (shift
!= SHIFT_RRX
)
4277 /* Whitespace can appear here if the next thing is a bare digit. */
4278 skip_whitespace (p
);
4280 if (mode
== NO_SHIFT_RESTRICT
4281 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4283 inst
.operands
[i
].imm
= reg
;
4284 inst
.operands
[i
].immisreg
= 1;
4286 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4289 inst
.operands
[i
].shift_kind
= shift
;
4290 inst
.operands
[i
].shifted
= 1;
4295 /* Parse a <shifter_operand> for an ARM data processing instruction:
4298 #<immediate>, <rotate>
4302 where <shift> is defined by parse_shift above, and <rotate> is a
4303 multiple of 2 between 0 and 30. Validation of immediate operands
4304 is deferred to md_apply_fix. */
4307 parse_shifter_operand (char **str
, int i
)
4312 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4314 inst
.operands
[i
].reg
= value
;
4315 inst
.operands
[i
].isreg
= 1;
4317 /* parse_shift will override this if appropriate */
4318 inst
.reloc
.exp
.X_op
= O_constant
;
4319 inst
.reloc
.exp
.X_add_number
= 0;
4321 if (skip_past_comma (str
) == FAIL
)
4324 /* Shift operation on register. */
4325 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4328 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4331 if (skip_past_comma (str
) == SUCCESS
)
4333 /* #x, y -- ie explicit rotation by Y. */
4334 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4337 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4339 inst
.error
= _("constant expression expected");
4343 value
= expr
.X_add_number
;
4344 if (value
< 0 || value
> 30 || value
% 2 != 0)
4346 inst
.error
= _("invalid rotation");
4349 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4351 inst
.error
= _("invalid constant");
4355 /* Convert to decoded value. md_apply_fix will put it back. */
4356 inst
.reloc
.exp
.X_add_number
4357 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4358 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4361 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4362 inst
.reloc
.pc_rel
= 0;
4366 /* Group relocation information. Each entry in the table contains the
4367 textual name of the relocation as may appear in assembler source
4368 and must end with a colon.
4369 Along with this textual name are the relocation codes to be used if
4370 the corresponding instruction is an ALU instruction (ADD or SUB only),
4371 an LDR, an LDRS, or an LDC. */
4373 struct group_reloc_table_entry
4384 /* Varieties of non-ALU group relocation. */
4391 static struct group_reloc_table_entry group_reloc_table
[] =
4392 { /* Program counter relative: */
4394 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4399 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4400 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4401 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4402 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4404 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4409 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4410 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4411 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4412 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4414 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4415 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4416 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4417 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4418 /* Section base relative */
4420 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4425 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4426 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4427 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4428 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4430 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4435 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4436 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4437 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4438 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4440 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4441 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4442 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4443 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4445 /* Given the address of a pointer pointing to the textual name of a group
4446 relocation as may appear in assembler source, attempt to find its details
4447 in group_reloc_table. The pointer will be updated to the character after
4448 the trailing colon. On failure, FAIL will be returned; SUCCESS
4449 otherwise. On success, *entry will be updated to point at the relevant
4450 group_reloc_table entry. */
4453 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4456 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4458 int length
= strlen (group_reloc_table
[i
].name
);
4460 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0 &&
4461 (*str
)[length
] == ':')
4463 *out
= &group_reloc_table
[i
];
4464 *str
+= (length
+ 1);
4472 /* Parse a <shifter_operand> for an ARM data processing instruction
4473 (as for parse_shifter_operand) where group relocations are allowed:
4476 #<immediate>, <rotate>
4477 #:<group_reloc>:<expression>
4481 where <group_reloc> is one of the strings defined in group_reloc_table.
4482 The hashes are optional.
4484 Everything else is as for parse_shifter_operand. */
4486 static parse_operand_result
4487 parse_shifter_operand_group_reloc (char **str
, int i
)
4489 /* Determine if we have the sequence of characters #: or just :
4490 coming next. If we do, then we check for a group relocation.
4491 If we don't, punt the whole lot to parse_shifter_operand. */
4493 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4494 || (*str
)[0] == ':')
4496 struct group_reloc_table_entry
*entry
;
4498 if ((*str
)[0] == '#')
4503 /* Try to parse a group relocation. Anything else is an error. */
4504 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4506 inst
.error
= _("unknown group relocation");
4507 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4510 /* We now have the group relocation table entry corresponding to
4511 the name in the assembler source. Next, we parse the expression. */
4512 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4513 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4515 /* Record the relocation type (always the ALU variant here). */
4516 inst
.reloc
.type
= entry
->alu_code
;
4517 assert (inst
.reloc
.type
!= 0);
4519 return PARSE_OPERAND_SUCCESS
;
4522 return parse_shifter_operand (str
, i
) == SUCCESS
4523 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4525 /* Never reached. */
4528 /* Parse all forms of an ARM address expression. Information is written
4529 to inst.operands[i] and/or inst.reloc.
4531 Preindexed addressing (.preind=1):
4533 [Rn, #offset] .reg=Rn .reloc.exp=offset
4534 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4535 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4536 .shift_kind=shift .reloc.exp=shift_imm
4538 These three may have a trailing ! which causes .writeback to be set also.
4540 Postindexed addressing (.postind=1, .writeback=1):
4542 [Rn], #offset .reg=Rn .reloc.exp=offset
4543 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4544 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4545 .shift_kind=shift .reloc.exp=shift_imm
4547 Unindexed addressing (.preind=0, .postind=0):
4549 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4553 [Rn]{!} shorthand for [Rn,#0]{!}
4554 =immediate .isreg=0 .reloc.exp=immediate
4555 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4557 It is the caller's responsibility to check for addressing modes not
4558 supported by the instruction, and to set inst.reloc.type. */
4560 static parse_operand_result
4561 parse_address_main (char **str
, int i
, int group_relocations
,
4562 group_reloc_type group_type
)
4567 if (skip_past_char (&p
, '[') == FAIL
)
4569 if (skip_past_char (&p
, '=') == FAIL
)
4571 /* bare address - translate to PC-relative offset */
4572 inst
.reloc
.pc_rel
= 1;
4573 inst
.operands
[i
].reg
= REG_PC
;
4574 inst
.operands
[i
].isreg
= 1;
4575 inst
.operands
[i
].preind
= 1;
4577 /* else a load-constant pseudo op, no special treatment needed here */
4579 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4580 return PARSE_OPERAND_FAIL
;
4583 return PARSE_OPERAND_SUCCESS
;
4586 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4588 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4589 return PARSE_OPERAND_FAIL
;
4591 inst
.operands
[i
].reg
= reg
;
4592 inst
.operands
[i
].isreg
= 1;
4594 if (skip_past_comma (&p
) == SUCCESS
)
4596 inst
.operands
[i
].preind
= 1;
4599 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4601 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4603 inst
.operands
[i
].imm
= reg
;
4604 inst
.operands
[i
].immisreg
= 1;
4606 if (skip_past_comma (&p
) == SUCCESS
)
4607 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4608 return PARSE_OPERAND_FAIL
;
4610 else if (skip_past_char (&p
, ':') == SUCCESS
)
4612 /* FIXME: '@' should be used here, but it's filtered out by generic
4613 code before we get to see it here. This may be subject to
4616 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4617 if (exp
.X_op
!= O_constant
)
4619 inst
.error
= _("alignment must be constant");
4620 return PARSE_OPERAND_FAIL
;
4622 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4623 inst
.operands
[i
].immisalign
= 1;
4624 /* Alignments are not pre-indexes. */
4625 inst
.operands
[i
].preind
= 0;
4629 if (inst
.operands
[i
].negative
)
4631 inst
.operands
[i
].negative
= 0;
4635 if (group_relocations
&&
4636 ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
4639 struct group_reloc_table_entry
*entry
;
4641 /* Skip over the #: or : sequence. */
4647 /* Try to parse a group relocation. Anything else is an
4649 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
4651 inst
.error
= _("unknown group relocation");
4652 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4655 /* We now have the group relocation table entry corresponding to
4656 the name in the assembler source. Next, we parse the
4658 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4659 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4661 /* Record the relocation type. */
4665 inst
.reloc
.type
= entry
->ldr_code
;
4669 inst
.reloc
.type
= entry
->ldrs_code
;
4673 inst
.reloc
.type
= entry
->ldc_code
;
4680 if (inst
.reloc
.type
== 0)
4682 inst
.error
= _("this group relocation is not allowed on this instruction");
4683 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4687 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4688 return PARSE_OPERAND_FAIL
;
4692 if (skip_past_char (&p
, ']') == FAIL
)
4694 inst
.error
= _("']' expected");
4695 return PARSE_OPERAND_FAIL
;
4698 if (skip_past_char (&p
, '!') == SUCCESS
)
4699 inst
.operands
[i
].writeback
= 1;
4701 else if (skip_past_comma (&p
) == SUCCESS
)
4703 if (skip_past_char (&p
, '{') == SUCCESS
)
4705 /* [Rn], {expr} - unindexed, with option */
4706 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
4707 0, 255, TRUE
) == FAIL
)
4708 return PARSE_OPERAND_FAIL
;
4710 if (skip_past_char (&p
, '}') == FAIL
)
4712 inst
.error
= _("'}' expected at end of 'option' field");
4713 return PARSE_OPERAND_FAIL
;
4715 if (inst
.operands
[i
].preind
)
4717 inst
.error
= _("cannot combine index with option");
4718 return PARSE_OPERAND_FAIL
;
4721 return PARSE_OPERAND_SUCCESS
;
4725 inst
.operands
[i
].postind
= 1;
4726 inst
.operands
[i
].writeback
= 1;
4728 if (inst
.operands
[i
].preind
)
4730 inst
.error
= _("cannot combine pre- and post-indexing");
4731 return PARSE_OPERAND_FAIL
;
4735 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4737 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4739 /* We might be using the immediate for alignment already. If we
4740 are, OR the register number into the low-order bits. */
4741 if (inst
.operands
[i
].immisalign
)
4742 inst
.operands
[i
].imm
|= reg
;
4744 inst
.operands
[i
].imm
= reg
;
4745 inst
.operands
[i
].immisreg
= 1;
4747 if (skip_past_comma (&p
) == SUCCESS
)
4748 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4749 return PARSE_OPERAND_FAIL
;
4753 if (inst
.operands
[i
].negative
)
4755 inst
.operands
[i
].negative
= 0;
4758 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4759 return PARSE_OPERAND_FAIL
;
4764 /* If at this point neither .preind nor .postind is set, we have a
4765 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4766 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
4768 inst
.operands
[i
].preind
= 1;
4769 inst
.reloc
.exp
.X_op
= O_constant
;
4770 inst
.reloc
.exp
.X_add_number
= 0;
4773 return PARSE_OPERAND_SUCCESS
;
4777 parse_address (char **str
, int i
)
4779 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
4783 static parse_operand_result
4784 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
4786 return parse_address_main (str
, i
, 1, type
);
4789 /* Parse an operand for a MOVW or MOVT instruction. */
4791 parse_half (char **str
)
4796 skip_past_char (&p
, '#');
4797 if (strncasecmp (p
, ":lower16:", 9) == 0)
4798 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
4799 else if (strncasecmp (p
, ":upper16:", 9) == 0)
4800 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
4802 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4808 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4811 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4813 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4815 inst
.error
= _("constant expression expected");
4818 if (inst
.reloc
.exp
.X_add_number
< 0
4819 || inst
.reloc
.exp
.X_add_number
> 0xffff)
4821 inst
.error
= _("immediate value out of range");
4829 /* Miscellaneous. */
4831 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4832 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4834 parse_psr (char **str
)
4837 unsigned long psr_field
;
4838 const struct asm_psr
*psr
;
4841 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4842 feature for ease of use and backwards compatibility. */
4844 if (strncasecmp (p
, "SPSR", 4) == 0)
4845 psr_field
= SPSR_BIT
;
4846 else if (strncasecmp (p
, "CPSR", 4) == 0)
4853 while (ISALNUM (*p
) || *p
== '_');
4855 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
4866 /* A suffix follows. */
4872 while (ISALNUM (*p
) || *p
== '_');
4874 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
4878 psr_field
|= psr
->field
;
4883 goto error
; /* Garbage after "[CS]PSR". */
4885 psr_field
|= (PSR_c
| PSR_f
);
4891 inst
.error
= _("flag for {c}psr instruction expected");
4895 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4896 value suitable for splatting into the AIF field of the instruction. */
4899 parse_cps_flags (char **str
)
4908 case '\0': case ',':
4911 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
4912 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
4913 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
4916 inst
.error
= _("unrecognized CPS flag");
4921 if (saw_a_flag
== 0)
4923 inst
.error
= _("missing CPS flags");
4931 /* Parse an endian specifier ("BE" or "LE", case insensitive);
4932 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4935 parse_endian_specifier (char **str
)
4940 if (strncasecmp (s
, "BE", 2))
4942 else if (strncasecmp (s
, "LE", 2))
4946 inst
.error
= _("valid endian specifiers are be or le");
4950 if (ISALNUM (s
[2]) || s
[2] == '_')
4952 inst
.error
= _("valid endian specifiers are be or le");
4957 return little_endian
;
4960 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
4961 value suitable for poking into the rotate field of an sxt or sxta
4962 instruction, or FAIL on error. */
4965 parse_ror (char **str
)
4970 if (strncasecmp (s
, "ROR", 3) == 0)
4974 inst
.error
= _("missing rotation field after comma");
4978 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
4983 case 0: *str
= s
; return 0x0;
4984 case 8: *str
= s
; return 0x1;
4985 case 16: *str
= s
; return 0x2;
4986 case 24: *str
= s
; return 0x3;
4989 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
4994 /* Parse a conditional code (from conds[] below). The value returned is in the
4995 range 0 .. 14, or FAIL. */
4997 parse_cond (char **str
)
5000 const struct asm_cond
*c
;
5003 while (ISALPHA (*q
))
5006 c
= hash_find_n (arm_cond_hsh
, p
, q
- p
);
5009 inst
.error
= _("condition required");
5017 /* Parse an option for a barrier instruction. Returns the encoding for the
5020 parse_barrier (char **str
)
5023 const struct asm_barrier_opt
*o
;
5026 while (ISALPHA (*q
))
5029 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
5037 /* Parse the operands of a table branch instruction. Similar to a memory
5040 parse_tb (char **str
)
5045 if (skip_past_char (&p
, '[') == FAIL
)
5047 inst
.error
= _("'[' expected");
5051 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5053 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5056 inst
.operands
[0].reg
= reg
;
5058 if (skip_past_comma (&p
) == FAIL
)
5060 inst
.error
= _("',' expected");
5064 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5066 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5069 inst
.operands
[0].imm
= reg
;
5071 if (skip_past_comma (&p
) == SUCCESS
)
5073 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5075 if (inst
.reloc
.exp
.X_add_number
!= 1)
5077 inst
.error
= _("invalid shift");
5080 inst
.operands
[0].shifted
= 1;
5083 if (skip_past_char (&p
, ']') == FAIL
)
5085 inst
.error
= _("']' expected");
5092 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5093 information on the types the operands can take and how they are encoded.
5094 Up to four operands may be read; this function handles setting the
5095 ".present" field for each read operand itself.
5096 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5097 else returns FAIL. */
5100 parse_neon_mov (char **str
, int *which_operand
)
5102 int i
= *which_operand
, val
;
5103 enum arm_reg_type rtype
;
5105 struct neon_type_el optype
;
5107 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5109 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5110 inst
.operands
[i
].reg
= val
;
5111 inst
.operands
[i
].isscalar
= 1;
5112 inst
.operands
[i
].vectype
= optype
;
5113 inst
.operands
[i
++].present
= 1;
5115 if (skip_past_comma (&ptr
) == FAIL
)
5118 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5121 inst
.operands
[i
].reg
= val
;
5122 inst
.operands
[i
].isreg
= 1;
5123 inst
.operands
[i
].present
= 1;
5125 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5128 /* Cases 0, 1, 2, 3, 5 (D only). */
5129 if (skip_past_comma (&ptr
) == FAIL
)
5132 inst
.operands
[i
].reg
= val
;
5133 inst
.operands
[i
].isreg
= 1;
5134 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5135 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5136 inst
.operands
[i
].isvec
= 1;
5137 inst
.operands
[i
].vectype
= optype
;
5138 inst
.operands
[i
++].present
= 1;
5140 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5142 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5143 Case 13: VMOV <Sd>, <Rm> */
5144 inst
.operands
[i
].reg
= val
;
5145 inst
.operands
[i
].isreg
= 1;
5146 inst
.operands
[i
].present
= 1;
5148 if (rtype
== REG_TYPE_NQ
)
5150 first_error (_("can't use Neon quad register here"));
5153 else if (rtype
!= REG_TYPE_VFS
)
5156 if (skip_past_comma (&ptr
) == FAIL
)
5158 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5160 inst
.operands
[i
].reg
= val
;
5161 inst
.operands
[i
].isreg
= 1;
5162 inst
.operands
[i
].present
= 1;
5165 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5166 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5167 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5168 Case 10: VMOV.F32 <Sd>, #<imm>
5169 Case 11: VMOV.F64 <Dd>, #<imm> */
5171 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5172 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5173 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5175 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5178 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5179 Case 1: VMOV<c><q> <Dd>, <Dm>
5180 Case 8: VMOV.F32 <Sd>, <Sm>
5181 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5183 inst
.operands
[i
].reg
= val
;
5184 inst
.operands
[i
].isreg
= 1;
5185 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5186 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5187 inst
.operands
[i
].isvec
= 1;
5188 inst
.operands
[i
].vectype
= optype
;
5189 inst
.operands
[i
].present
= 1;
5191 if (skip_past_comma (&ptr
) == SUCCESS
)
5196 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5199 inst
.operands
[i
].reg
= val
;
5200 inst
.operands
[i
].isreg
= 1;
5201 inst
.operands
[i
++].present
= 1;
5203 if (skip_past_comma (&ptr
) == FAIL
)
5206 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5209 inst
.operands
[i
].reg
= val
;
5210 inst
.operands
[i
].isreg
= 1;
5211 inst
.operands
[i
++].present
= 1;
5216 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5220 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5223 inst
.operands
[i
].reg
= val
;
5224 inst
.operands
[i
].isreg
= 1;
5225 inst
.operands
[i
++].present
= 1;
5227 if (skip_past_comma (&ptr
) == FAIL
)
5230 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5232 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5233 inst
.operands
[i
].reg
= val
;
5234 inst
.operands
[i
].isscalar
= 1;
5235 inst
.operands
[i
].present
= 1;
5236 inst
.operands
[i
].vectype
= optype
;
5238 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5240 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5241 inst
.operands
[i
].reg
= val
;
5242 inst
.operands
[i
].isreg
= 1;
5243 inst
.operands
[i
++].present
= 1;
5245 if (skip_past_comma (&ptr
) == FAIL
)
5248 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5251 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5255 inst
.operands
[i
].reg
= val
;
5256 inst
.operands
[i
].isreg
= 1;
5257 inst
.operands
[i
].isvec
= 1;
5258 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5259 inst
.operands
[i
].vectype
= optype
;
5260 inst
.operands
[i
].present
= 1;
5262 if (rtype
== REG_TYPE_VFS
)
5266 if (skip_past_comma (&ptr
) == FAIL
)
5268 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5271 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5274 inst
.operands
[i
].reg
= val
;
5275 inst
.operands
[i
].isreg
= 1;
5276 inst
.operands
[i
].isvec
= 1;
5277 inst
.operands
[i
].issingle
= 1;
5278 inst
.operands
[i
].vectype
= optype
;
5279 inst
.operands
[i
].present
= 1;
5282 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5286 inst
.operands
[i
].reg
= val
;
5287 inst
.operands
[i
].isreg
= 1;
5288 inst
.operands
[i
].isvec
= 1;
5289 inst
.operands
[i
].issingle
= 1;
5290 inst
.operands
[i
].vectype
= optype
;
5291 inst
.operands
[i
++].present
= 1;
5296 first_error (_("parse error"));
5300 /* Successfully parsed the operands. Update args. */
5306 first_error (_("expected comma"));
5310 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5314 /* Matcher codes for parse_operands. */
5315 enum operand_parse_code
5317 OP_stop
, /* end of line */
5319 OP_RR
, /* ARM register */
5320 OP_RRnpc
, /* ARM register, not r15 */
5321 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5322 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5323 OP_RCP
, /* Coprocessor number */
5324 OP_RCN
, /* Coprocessor register */
5325 OP_RF
, /* FPA register */
5326 OP_RVS
, /* VFP single precision register */
5327 OP_RVD
, /* VFP double precision register (0..15) */
5328 OP_RND
, /* Neon double precision register (0..31) */
5329 OP_RNQ
, /* Neon quad precision register */
5330 OP_RVSD
, /* VFP single or double precision register */
5331 OP_RNDQ
, /* Neon double or quad precision register */
5332 OP_RNSDQ
, /* Neon single, double or quad precision register */
5333 OP_RNSC
, /* Neon scalar D[X] */
5334 OP_RVC
, /* VFP control register */
5335 OP_RMF
, /* Maverick F register */
5336 OP_RMD
, /* Maverick D register */
5337 OP_RMFX
, /* Maverick FX register */
5338 OP_RMDX
, /* Maverick DX register */
5339 OP_RMAX
, /* Maverick AX register */
5340 OP_RMDS
, /* Maverick DSPSC register */
5341 OP_RIWR
, /* iWMMXt wR register */
5342 OP_RIWC
, /* iWMMXt wC register */
5343 OP_RIWG
, /* iWMMXt wCG register */
5344 OP_RXA
, /* XScale accumulator register */
5346 OP_REGLST
, /* ARM register list */
5347 OP_VRSLST
, /* VFP single-precision register list */
5348 OP_VRDLST
, /* VFP double-precision register list */
5349 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5350 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5351 OP_NSTRLST
, /* Neon element/structure list */
5353 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5354 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5355 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5356 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5357 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5358 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5359 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5360 OP_VMOV
, /* Neon VMOV operands. */
5361 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5362 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5364 OP_I0
, /* immediate zero */
5365 OP_I7
, /* immediate value 0 .. 7 */
5366 OP_I15
, /* 0 .. 15 */
5367 OP_I16
, /* 1 .. 16 */
5368 OP_I16z
, /* 0 .. 16 */
5369 OP_I31
, /* 0 .. 31 */
5370 OP_I31w
, /* 0 .. 31, optional trailing ! */
5371 OP_I32
, /* 1 .. 32 */
5372 OP_I32z
, /* 0 .. 32 */
5373 OP_I63
, /* 0 .. 63 */
5374 OP_I63s
, /* -64 .. 63 */
5375 OP_I64
, /* 1 .. 64 */
5376 OP_I64z
, /* 0 .. 64 */
5377 OP_I255
, /* 0 .. 255 */
5379 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5380 OP_I7b
, /* 0 .. 7 */
5381 OP_I15b
, /* 0 .. 15 */
5382 OP_I31b
, /* 0 .. 31 */
5384 OP_SH
, /* shifter operand */
5385 OP_SHG
, /* shifter operand with possible group relocation */
5386 OP_ADDR
, /* Memory address expression (any mode) */
5387 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5388 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5389 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5390 OP_EXP
, /* arbitrary expression */
5391 OP_EXPi
, /* same, with optional immediate prefix */
5392 OP_EXPr
, /* same, with optional relocation suffix */
5393 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5395 OP_CPSF
, /* CPS flags */
5396 OP_ENDI
, /* Endianness specifier */
5397 OP_PSR
, /* CPSR/SPSR mask for msr */
5398 OP_COND
, /* conditional code */
5399 OP_TB
, /* Table branch. */
5401 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5402 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5404 OP_RRnpc_I0
, /* ARM register or literal 0 */
5405 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5406 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5407 OP_RF_IF
, /* FPA register or immediate */
5408 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5409 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5411 /* Optional operands. */
5412 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5413 OP_oI31b
, /* 0 .. 31 */
5414 OP_oI32b
, /* 1 .. 32 */
5415 OP_oIffffb
, /* 0 .. 65535 */
5416 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5418 OP_oRR
, /* ARM register */
5419 OP_oRRnpc
, /* ARM register, not the PC */
5420 OP_oRND
, /* Optional Neon double precision register */
5421 OP_oRNQ
, /* Optional Neon quad precision register */
5422 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5423 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5424 OP_oSHll
, /* LSL immediate */
5425 OP_oSHar
, /* ASR immediate */
5426 OP_oSHllar
, /* LSL or ASR immediate */
5427 OP_oROR
, /* ROR 0/8/16/24 */
5428 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5430 OP_FIRST_OPTIONAL
= OP_oI7b
5433 /* Generic instruction operand parser. This does no encoding and no
5434 semantic validation; it merely squirrels values away in the inst
5435 structure. Returns SUCCESS or FAIL depending on whether the
5436 specified grammar matched. */
5438 parse_operands (char *str
, const unsigned char *pattern
)
5440 unsigned const char *upat
= pattern
;
5441 char *backtrack_pos
= 0;
5442 const char *backtrack_error
= 0;
5443 int i
, val
, backtrack_index
= 0;
5444 enum arm_reg_type rtype
;
5445 parse_operand_result result
;
5447 #define po_char_or_fail(chr) do { \
5448 if (skip_past_char (&str, chr) == FAIL) \
5452 #define po_reg_or_fail(regtype) do { \
5453 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5454 &inst.operands[i].vectype); \
5457 first_error (_(reg_expected_msgs[regtype])); \
5460 inst.operands[i].reg = val; \
5461 inst.operands[i].isreg = 1; \
5462 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5463 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5464 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5465 || rtype == REG_TYPE_VFD \
5466 || rtype == REG_TYPE_NQ); \
5469 #define po_reg_or_goto(regtype, label) do { \
5470 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5471 &inst.operands[i].vectype); \
5475 inst.operands[i].reg = val; \
5476 inst.operands[i].isreg = 1; \
5477 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5478 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5479 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5480 || rtype == REG_TYPE_VFD \
5481 || rtype == REG_TYPE_NQ); \
5484 #define po_imm_or_fail(min, max, popt) do { \
5485 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5487 inst.operands[i].imm = val; \
5490 #define po_scalar_or_goto(elsz, label) do { \
5491 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5494 inst.operands[i].reg = val; \
5495 inst.operands[i].isscalar = 1; \
5498 #define po_misc_or_fail(expr) do { \
5503 #define po_misc_or_fail_no_backtrack(expr) do { \
5505 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5506 backtrack_pos = 0; \
5507 if (result != PARSE_OPERAND_SUCCESS) \
5511 skip_whitespace (str
);
5513 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5515 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5517 /* Remember where we are in case we need to backtrack. */
5518 assert (!backtrack_pos
);
5519 backtrack_pos
= str
;
5520 backtrack_error
= inst
.error
;
5521 backtrack_index
= i
;
5525 po_char_or_fail (',');
5533 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5534 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5535 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5536 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5537 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5538 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5540 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5541 case OP_RVC
: po_reg_or_fail (REG_TYPE_VFC
); break;
5542 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5543 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5544 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5545 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5546 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5547 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5548 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5549 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5550 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5551 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5553 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5555 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5556 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5558 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5560 /* Neon scalar. Using an element size of 8 means that some invalid
5561 scalars are accepted here, so deal with those in later code. */
5562 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5564 /* WARNING: We can expand to two operands here. This has the potential
5565 to totally confuse the backtracking mechanism! It will be OK at
5566 least as long as we don't try to use optional args as well,
5570 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
5571 inst
.operands
[i
].present
= 1;
5573 skip_past_comma (&str
);
5574 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
5577 /* Optional register operand was omitted. Unfortunately, it's in
5578 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5579 here (this is a bit grotty). */
5580 inst
.operands
[i
] = inst
.operands
[i
-1];
5581 inst
.operands
[i
-1].present
= 0;
5584 /* Immediate gets verified properly later, so accept any now. */
5585 po_imm_or_fail (INT_MIN
, INT_MAX
, TRUE
);
5591 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
5594 po_imm_or_fail (0, 0, TRUE
);
5599 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
5604 po_scalar_or_goto (8, try_rr
);
5607 po_reg_or_fail (REG_TYPE_RN
);
5613 po_scalar_or_goto (8, try_nsdq
);
5616 po_reg_or_fail (REG_TYPE_NSDQ
);
5622 po_scalar_or_goto (8, try_ndq
);
5625 po_reg_or_fail (REG_TYPE_NDQ
);
5631 po_scalar_or_goto (8, try_vfd
);
5634 po_reg_or_fail (REG_TYPE_VFD
);
5639 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5640 not careful then bad things might happen. */
5641 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
5646 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
5649 /* There's a possibility of getting a 64-bit immediate here, so
5650 we need special handling. */
5651 if (parse_big_immediate (&str
, i
) == FAIL
)
5653 inst
.error
= _("immediate value is out of range");
5661 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
5664 po_imm_or_fail (0, 63, TRUE
);
5669 po_char_or_fail ('[');
5670 po_reg_or_fail (REG_TYPE_RN
);
5671 po_char_or_fail (']');
5675 po_reg_or_fail (REG_TYPE_RN
);
5676 if (skip_past_char (&str
, '!') == SUCCESS
)
5677 inst
.operands
[i
].writeback
= 1;
5681 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
5682 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
5683 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
5684 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
5685 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
5686 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
5687 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
5688 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
5689 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
5690 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
5691 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
5692 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
5694 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
5696 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
5697 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
5699 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
5700 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
5701 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
5703 /* Immediate variants */
5705 po_char_or_fail ('{');
5706 po_imm_or_fail (0, 255, TRUE
);
5707 po_char_or_fail ('}');
5711 /* The expression parser chokes on a trailing !, so we have
5712 to find it first and zap it. */
5715 while (*s
&& *s
!= ',')
5720 inst
.operands
[i
].writeback
= 1;
5722 po_imm_or_fail (0, 31, TRUE
);
5730 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5735 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5740 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5742 if (inst
.reloc
.exp
.X_op
== O_symbol
)
5744 val
= parse_reloc (&str
);
5747 inst
.error
= _("unrecognized relocation suffix");
5750 else if (val
!= BFD_RELOC_UNUSED
)
5752 inst
.operands
[i
].imm
= val
;
5753 inst
.operands
[i
].hasreloc
= 1;
5758 /* Operand for MOVW or MOVT. */
5760 po_misc_or_fail (parse_half (&str
));
5763 /* Register or expression */
5764 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
5765 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
5767 /* Register or immediate */
5768 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
5769 I0
: po_imm_or_fail (0, 0, FALSE
); break;
5771 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
5773 if (!is_immediate_prefix (*str
))
5776 val
= parse_fpa_immediate (&str
);
5779 /* FPA immediates are encoded as registers 8-15.
5780 parse_fpa_immediate has already applied the offset. */
5781 inst
.operands
[i
].reg
= val
;
5782 inst
.operands
[i
].isreg
= 1;
5785 /* Two kinds of register */
5788 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5790 || (rege
->type
!= REG_TYPE_MMXWR
5791 && rege
->type
!= REG_TYPE_MMXWC
5792 && rege
->type
!= REG_TYPE_MMXWCG
))
5794 inst
.error
= _("iWMMXt data or control register expected");
5797 inst
.operands
[i
].reg
= rege
->number
;
5798 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
5804 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5806 || (rege
->type
!= REG_TYPE_MMXWC
5807 && rege
->type
!= REG_TYPE_MMXWCG
))
5809 inst
.error
= _("iWMMXt control register expected");
5812 inst
.operands
[i
].reg
= rege
->number
;
5813 inst
.operands
[i
].isreg
= 1;
5818 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
5819 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
5820 case OP_oROR
: val
= parse_ror (&str
); break;
5821 case OP_PSR
: val
= parse_psr (&str
); break;
5822 case OP_COND
: val
= parse_cond (&str
); break;
5823 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
5826 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
5827 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
5830 val
= parse_psr (&str
);
5834 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
5837 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5839 if (strncasecmp (str
, "APSR_", 5) == 0)
5846 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
5847 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
5848 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
5849 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
5850 default: found
= 16;
5854 inst
.operands
[i
].isvec
= 1;
5861 po_misc_or_fail (parse_tb (&str
));
5864 /* Register lists */
5866 val
= parse_reg_list (&str
);
5869 inst
.operands
[1].writeback
= 1;
5875 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
5879 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
5883 /* Allow Q registers too. */
5884 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5889 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5891 inst
.operands
[i
].issingle
= 1;
5896 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5901 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
5902 &inst
.operands
[i
].vectype
);
5905 /* Addressing modes */
5907 po_misc_or_fail (parse_address (&str
, i
));
5911 po_misc_or_fail_no_backtrack (
5912 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
5916 po_misc_or_fail_no_backtrack (
5917 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
5921 po_misc_or_fail_no_backtrack (
5922 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
5926 po_misc_or_fail (parse_shifter_operand (&str
, i
));
5930 po_misc_or_fail_no_backtrack (
5931 parse_shifter_operand_group_reloc (&str
, i
));
5935 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
5939 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
5943 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
5947 as_fatal ("unhandled operand code %d", upat
[i
]);
5950 /* Various value-based sanity checks and shared operations. We
5951 do not signal immediate failures for the register constraints;
5952 this allows a syntax error to take precedence. */
5960 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
5961 inst
.error
= BAD_PC
;
5979 inst
.operands
[i
].imm
= val
;
5986 /* If we get here, this operand was successfully parsed. */
5987 inst
.operands
[i
].present
= 1;
5991 inst
.error
= BAD_ARGS
;
5996 /* The parse routine should already have set inst.error, but set a
5997 defaut here just in case. */
5999 inst
.error
= _("syntax error");
6003 /* Do not backtrack over a trailing optional argument that
6004 absorbed some text. We will only fail again, with the
6005 'garbage following instruction' error message, which is
6006 probably less helpful than the current one. */
6007 if (backtrack_index
== i
&& backtrack_pos
!= str
6008 && upat
[i
+1] == OP_stop
)
6011 inst
.error
= _("syntax error");
6015 /* Try again, skipping the optional argument at backtrack_pos. */
6016 str
= backtrack_pos
;
6017 inst
.error
= backtrack_error
;
6018 inst
.operands
[backtrack_index
].present
= 0;
6019 i
= backtrack_index
;
6023 /* Check that we have parsed all the arguments. */
6024 if (*str
!= '\0' && !inst
.error
)
6025 inst
.error
= _("garbage following instruction");
6027 return inst
.error
? FAIL
: SUCCESS
;
6030 #undef po_char_or_fail
6031 #undef po_reg_or_fail
6032 #undef po_reg_or_goto
6033 #undef po_imm_or_fail
6034 #undef po_scalar_or_fail
6036 /* Shorthand macro for instruction encoding functions issuing errors. */
6037 #define constraint(expr, err) do { \
6045 /* Functions for operand encoding. ARM, then Thumb. */
6047 #define rotate_left(v, n) (v << n | v >> (32 - n))
6049 /* If VAL can be encoded in the immediate field of an ARM instruction,
6050 return the encoded form. Otherwise, return FAIL. */
6053 encode_arm_immediate (unsigned int val
)
6057 for (i
= 0; i
< 32; i
+= 2)
6058 if ((a
= rotate_left (val
, i
)) <= 0xff)
6059 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6064 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6065 return the encoded form. Otherwise, return FAIL. */
6067 encode_thumb32_immediate (unsigned int val
)
6074 for (i
= 1; i
<= 24; i
++)
6077 if ((val
& ~(0xff << i
)) == 0)
6078 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6082 if (val
== ((a
<< 16) | a
))
6084 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6088 if (val
== ((a
<< 16) | a
))
6089 return 0x200 | (a
>> 8);
6093 /* Encode a VFP SP or DP register number into inst.instruction. */
6096 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6098 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6101 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
6104 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6107 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6112 first_error (_("D register out of range for selected VFP version"));
6120 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6124 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6128 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6132 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6136 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6140 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6148 /* Encode a <shift> in an ARM-format instruction. The immediate,
6149 if any, is handled by md_apply_fix. */
6151 encode_arm_shift (int i
)
6153 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6154 inst
.instruction
|= SHIFT_ROR
<< 5;
6157 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6158 if (inst
.operands
[i
].immisreg
)
6160 inst
.instruction
|= SHIFT_BY_REG
;
6161 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6164 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6169 encode_arm_shifter_operand (int i
)
6171 if (inst
.operands
[i
].isreg
)
6173 inst
.instruction
|= inst
.operands
[i
].reg
;
6174 encode_arm_shift (i
);
6177 inst
.instruction
|= INST_IMMEDIATE
;
6180 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6182 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6184 assert (inst
.operands
[i
].isreg
);
6185 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6187 if (inst
.operands
[i
].preind
)
6191 inst
.error
= _("instruction does not accept preindexed addressing");
6194 inst
.instruction
|= PRE_INDEX
;
6195 if (inst
.operands
[i
].writeback
)
6196 inst
.instruction
|= WRITE_BACK
;
6199 else if (inst
.operands
[i
].postind
)
6201 assert (inst
.operands
[i
].writeback
);
6203 inst
.instruction
|= WRITE_BACK
;
6205 else /* unindexed - only for coprocessor */
6207 inst
.error
= _("instruction does not accept unindexed addressing");
6211 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6212 && (((inst
.instruction
& 0x000f0000) >> 16)
6213 == ((inst
.instruction
& 0x0000f000) >> 12)))
6214 as_warn ((inst
.instruction
& LOAD_BIT
)
6215 ? _("destination register same as write-back base")
6216 : _("source register same as write-back base"));
6219 /* inst.operands[i] was set up by parse_address. Encode it into an
6220 ARM-format mode 2 load or store instruction. If is_t is true,
6221 reject forms that cannot be used with a T instruction (i.e. not
6224 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6226 encode_arm_addr_mode_common (i
, is_t
);
6228 if (inst
.operands
[i
].immisreg
)
6230 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6231 inst
.instruction
|= inst
.operands
[i
].imm
;
6232 if (!inst
.operands
[i
].negative
)
6233 inst
.instruction
|= INDEX_UP
;
6234 if (inst
.operands
[i
].shifted
)
6236 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6237 inst
.instruction
|= SHIFT_ROR
<< 5;
6240 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6241 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6245 else /* immediate offset in inst.reloc */
6247 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6248 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6252 /* inst.operands[i] was set up by parse_address. Encode it into an
6253 ARM-format mode 3 load or store instruction. Reject forms that
6254 cannot be used with such instructions. If is_t is true, reject
6255 forms that cannot be used with a T instruction (i.e. not
6258 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6260 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6262 inst
.error
= _("instruction does not accept scaled register index");
6266 encode_arm_addr_mode_common (i
, is_t
);
6268 if (inst
.operands
[i
].immisreg
)
6270 inst
.instruction
|= inst
.operands
[i
].imm
;
6271 if (!inst
.operands
[i
].negative
)
6272 inst
.instruction
|= INDEX_UP
;
6274 else /* immediate offset in inst.reloc */
6276 inst
.instruction
|= HWOFFSET_IMM
;
6277 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6278 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6282 /* inst.operands[i] was set up by parse_address. Encode it into an
6283 ARM-format instruction. Reject all forms which cannot be encoded
6284 into a coprocessor load/store instruction. If wb_ok is false,
6285 reject use of writeback; if unind_ok is false, reject use of
6286 unindexed addressing. If reloc_override is not 0, use it instead
6287 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6288 (in which case it is preserved). */
6291 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6293 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6295 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6297 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6299 assert (!inst
.operands
[i
].writeback
);
6302 inst
.error
= _("instruction does not support unindexed addressing");
6305 inst
.instruction
|= inst
.operands
[i
].imm
;
6306 inst
.instruction
|= INDEX_UP
;
6310 if (inst
.operands
[i
].preind
)
6311 inst
.instruction
|= PRE_INDEX
;
6313 if (inst
.operands
[i
].writeback
)
6315 if (inst
.operands
[i
].reg
== REG_PC
)
6317 inst
.error
= _("pc may not be used with write-back");
6322 inst
.error
= _("instruction does not support writeback");
6325 inst
.instruction
|= WRITE_BACK
;
6329 inst
.reloc
.type
= reloc_override
;
6330 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6331 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6332 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6335 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6337 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6343 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6344 Determine whether it can be performed with a move instruction; if
6345 it can, convert inst.instruction to that move instruction and
6346 return 1; if it can't, convert inst.instruction to a literal-pool
6347 load and return 0. If this is not a valid thing to do in the
6348 current context, set inst.error and return 1.
6350 inst.operands[i] describes the destination register. */
6353 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6358 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6362 if ((inst
.instruction
& tbit
) == 0)
6364 inst
.error
= _("invalid pseudo operation");
6367 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6369 inst
.error
= _("constant expression expected");
6372 if (inst
.reloc
.exp
.X_op
== O_constant
)
6376 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6378 /* This can be done with a mov(1) instruction. */
6379 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6380 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6386 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6389 /* This can be done with a mov instruction. */
6390 inst
.instruction
&= LITERAL_MASK
;
6391 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6392 inst
.instruction
|= value
& 0xfff;
6396 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6399 /* This can be done with a mvn instruction. */
6400 inst
.instruction
&= LITERAL_MASK
;
6401 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6402 inst
.instruction
|= value
& 0xfff;
6408 if (add_to_lit_pool () == FAIL
)
6410 inst
.error
= _("literal pool insertion failed");
6413 inst
.operands
[1].reg
= REG_PC
;
6414 inst
.operands
[1].isreg
= 1;
6415 inst
.operands
[1].preind
= 1;
6416 inst
.reloc
.pc_rel
= 1;
6417 inst
.reloc
.type
= (thumb_p
6418 ? BFD_RELOC_ARM_THUMB_OFFSET
6420 ? BFD_RELOC_ARM_HWLITERAL
6421 : BFD_RELOC_ARM_LITERAL
));
6425 /* Functions for instruction encoding, sorted by subarchitecture.
6426 First some generics; their names are taken from the conventional
6427 bit positions for register arguments in ARM format instructions. */
6437 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6443 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6444 inst
.instruction
|= inst
.operands
[1].reg
;
6450 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6451 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6457 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6458 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6464 unsigned Rn
= inst
.operands
[2].reg
;
6465 /* Enforce restrictions on SWP instruction. */
6466 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6467 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6468 _("Rn must not overlap other operands"));
6469 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6470 inst
.instruction
|= inst
.operands
[1].reg
;
6471 inst
.instruction
|= Rn
<< 16;
6477 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6478 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6479 inst
.instruction
|= inst
.operands
[2].reg
;
6485 inst
.instruction
|= inst
.operands
[0].reg
;
6486 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6487 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6493 inst
.instruction
|= inst
.operands
[0].imm
;
6499 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6500 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6503 /* ARM instructions, in alphabetical order by function name (except
6504 that wrapper functions appear immediately after the function they
6507 /* This is a pseudo-op of the form "adr rd, label" to be converted
6508 into a relative address of the form "add rd, pc, #label-.-8". */
6513 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6515 /* Frag hacking will turn this into a sub instruction if the offset turns
6516 out to be negative. */
6517 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6518 inst
.reloc
.pc_rel
= 1;
6519 inst
.reloc
.exp
.X_add_number
-= 8;
6522 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6523 into a relative address of the form:
6524 add rd, pc, #low(label-.-8)"
6525 add rd, rd, #high(label-.-8)" */
6530 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6532 /* Frag hacking will turn this into a sub instruction if the offset turns
6533 out to be negative. */
6534 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6535 inst
.reloc
.pc_rel
= 1;
6536 inst
.size
= INSN_SIZE
* 2;
6537 inst
.reloc
.exp
.X_add_number
-= 8;
6543 if (!inst
.operands
[1].present
)
6544 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6545 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6546 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6547 encode_arm_shifter_operand (2);
6553 if (inst
.operands
[0].present
)
6555 constraint ((inst
.instruction
& 0xf0) != 0x40
6556 && inst
.operands
[0].imm
!= 0xf,
6557 "bad barrier type");
6558 inst
.instruction
|= inst
.operands
[0].imm
;
6561 inst
.instruction
|= 0xf;
6567 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6568 constraint (msb
> 32, _("bit-field extends past end of register"));
6569 /* The instruction encoding stores the LSB and MSB,
6570 not the LSB and width. */
6571 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6572 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
6573 inst
.instruction
|= (msb
- 1) << 16;
6581 /* #0 in second position is alternative syntax for bfc, which is
6582 the same instruction but with REG_PC in the Rm field. */
6583 if (!inst
.operands
[1].isreg
)
6584 inst
.operands
[1].reg
= REG_PC
;
6586 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6587 constraint (msb
> 32, _("bit-field extends past end of register"));
6588 /* The instruction encoding stores the LSB and MSB,
6589 not the LSB and width. */
6590 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6591 inst
.instruction
|= inst
.operands
[1].reg
;
6592 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6593 inst
.instruction
|= (msb
- 1) << 16;
6599 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6600 _("bit-field extends past end of register"));
6601 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6602 inst
.instruction
|= inst
.operands
[1].reg
;
6603 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6604 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
6607 /* ARM V5 breakpoint instruction (argument parse)
6608 BKPT <16 bit unsigned immediate>
6609 Instruction is not conditional.
6610 The bit pattern given in insns[] has the COND_ALWAYS condition,
6611 and it is an error if the caller tried to override that. */
6616 /* Top 12 of 16 bits to bits 19:8. */
6617 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
6619 /* Bottom 4 of 16 bits to bits 3:0. */
6620 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
6624 encode_branch (int default_reloc
)
6626 if (inst
.operands
[0].hasreloc
)
6628 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
6629 _("the only suffix valid here is '(plt)'"));
6630 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
6634 inst
.reloc
.type
= default_reloc
;
6636 inst
.reloc
.pc_rel
= 1;
6643 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6644 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6647 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6654 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6656 if (inst
.cond
== COND_ALWAYS
)
6657 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6659 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6663 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6666 /* ARM V5 branch-link-exchange instruction (argument parse)
6667 BLX <target_addr> ie BLX(1)
6668 BLX{<condition>} <Rm> ie BLX(2)
6669 Unfortunately, there are two different opcodes for this mnemonic.
6670 So, the insns[].value is not used, and the code here zaps values
6671 into inst.instruction.
6672 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6677 if (inst
.operands
[0].isreg
)
6679 /* Arg is a register; the opcode provided by insns[] is correct.
6680 It is not illegal to do "blx pc", just useless. */
6681 if (inst
.operands
[0].reg
== REG_PC
)
6682 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6684 inst
.instruction
|= inst
.operands
[0].reg
;
6688 /* Arg is an address; this instruction cannot be executed
6689 conditionally, and the opcode must be adjusted. */
6690 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
6691 inst
.instruction
= 0xfa000000;
6693 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6694 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6697 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
6704 if (inst
.operands
[0].reg
== REG_PC
)
6705 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6707 inst
.instruction
|= inst
.operands
[0].reg
;
6711 /* ARM v5TEJ. Jump to Jazelle code. */
6716 if (inst
.operands
[0].reg
== REG_PC
)
6717 as_tsktsk (_("use of r15 in bxj is not really useful"));
6719 inst
.instruction
|= inst
.operands
[0].reg
;
6722 /* Co-processor data operation:
6723 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6724 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6728 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6729 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
6730 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6731 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6732 inst
.instruction
|= inst
.operands
[4].reg
;
6733 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6739 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6740 encode_arm_shifter_operand (1);
6743 /* Transfer between coprocessor and ARM registers.
6744 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6749 No special properties. */
6754 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6755 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
6756 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6757 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6758 inst
.instruction
|= inst
.operands
[4].reg
;
6759 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6762 /* Transfer between coprocessor register and pair of ARM registers.
6763 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6768 Two XScale instructions are special cases of these:
6770 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6771 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6773 Result unpredicatable if Rd or Rn is R15. */
6778 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6779 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
6780 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6781 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6782 inst
.instruction
|= inst
.operands
[4].reg
;
6788 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
6789 inst
.instruction
|= inst
.operands
[1].imm
;
6795 inst
.instruction
|= inst
.operands
[0].imm
;
6801 /* There is no IT instruction in ARM mode. We
6802 process it but do not generate code for it. */
6809 int base_reg
= inst
.operands
[0].reg
;
6810 int range
= inst
.operands
[1].imm
;
6812 inst
.instruction
|= base_reg
<< 16;
6813 inst
.instruction
|= range
;
6815 if (inst
.operands
[1].writeback
)
6816 inst
.instruction
|= LDM_TYPE_2_OR_3
;
6818 if (inst
.operands
[0].writeback
)
6820 inst
.instruction
|= WRITE_BACK
;
6821 /* Check for unpredictable uses of writeback. */
6822 if (inst
.instruction
& LOAD_BIT
)
6824 /* Not allowed in LDM type 2. */
6825 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
6826 && ((range
& (1 << REG_PC
)) == 0))
6827 as_warn (_("writeback of base register is UNPREDICTABLE"));
6828 /* Only allowed if base reg not in list for other types. */
6829 else if (range
& (1 << base_reg
))
6830 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6834 /* Not allowed for type 2. */
6835 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
6836 as_warn (_("writeback of base register is UNPREDICTABLE"));
6837 /* Only allowed if base reg not in list, or first in list. */
6838 else if ((range
& (1 << base_reg
))
6839 && (range
& ((1 << base_reg
) - 1)))
6840 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6845 /* ARMv5TE load-consecutive (argument parse)
6854 constraint (inst
.operands
[0].reg
% 2 != 0,
6855 _("first destination register must be even"));
6856 constraint (inst
.operands
[1].present
6857 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6858 _("can only load two consecutive registers"));
6859 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6860 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
6862 if (!inst
.operands
[1].present
)
6863 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6865 if (inst
.instruction
& LOAD_BIT
)
6867 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6868 register and the first register written; we have to diagnose
6869 overlap between the base and the second register written here. */
6871 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
6872 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
6873 as_warn (_("base register written back, and overlaps "
6874 "second destination register"));
6876 /* For an index-register load, the index register must not overlap the
6877 destination (even if not write-back). */
6878 else if (inst
.operands
[2].immisreg
6879 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
6880 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
6881 as_warn (_("index register overlaps destination register"));
6884 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6885 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
6891 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
6892 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
6893 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
6894 || inst
.operands
[1].negative
6895 /* This can arise if the programmer has written
6897 or if they have mistakenly used a register name as the last
6900 It is very difficult to distinguish between these two cases
6901 because "rX" might actually be a label. ie the register
6902 name has been occluded by a symbol of the same name. So we
6903 just generate a general 'bad addressing mode' type error
6904 message and leave it up to the programmer to discover the
6905 true cause and fix their mistake. */
6906 || (inst
.operands
[1].reg
== REG_PC
),
6909 constraint (inst
.reloc
.exp
.X_op
!= O_constant
6910 || inst
.reloc
.exp
.X_add_number
!= 0,
6911 _("offset must be zero in ARM encoding"));
6913 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6914 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6915 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6921 constraint (inst
.operands
[0].reg
% 2 != 0,
6922 _("even register required"));
6923 constraint (inst
.operands
[1].present
6924 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6925 _("can only load two consecutive registers"));
6926 /* If op 1 were present and equal to PC, this function wouldn't
6927 have been called in the first place. */
6928 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6930 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6931 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6937 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6938 if (!inst
.operands
[1].isreg
)
6939 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
6941 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
6947 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
6949 if (inst
.operands
[1].preind
)
6951 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
6952 inst
.reloc
.exp
.X_add_number
!= 0,
6953 _("this instruction requires a post-indexed address"));
6955 inst
.operands
[1].preind
= 0;
6956 inst
.operands
[1].postind
= 1;
6957 inst
.operands
[1].writeback
= 1;
6959 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6960 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
6963 /* Halfword and signed-byte load/store operations. */
6968 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6969 if (!inst
.operands
[1].isreg
)
6970 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
6972 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
6978 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
6980 if (inst
.operands
[1].preind
)
6982 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
6983 inst
.reloc
.exp
.X_add_number
!= 0,
6984 _("this instruction requires a post-indexed address"));
6986 inst
.operands
[1].preind
= 0;
6987 inst
.operands
[1].postind
= 1;
6988 inst
.operands
[1].writeback
= 1;
6990 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6991 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
6994 /* Co-processor register load/store.
6995 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
6999 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7000 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7001 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7007 /* This restriction does not apply to mls (nor to mla in v6, but
7008 that's hard to detect at present). */
7009 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7010 && !(inst
.instruction
& 0x00400000))
7011 as_tsktsk (_("rd and rm should be different in mla"));
7013 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7014 inst
.instruction
|= inst
.operands
[1].reg
;
7015 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7016 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7023 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7024 encode_arm_shifter_operand (1);
7027 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7034 top
= (inst
.instruction
& 0x00400000) != 0;
7035 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7036 _(":lower16: not allowed this instruction"));
7037 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7038 _(":upper16: not allowed instruction"));
7039 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7040 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7042 imm
= inst
.reloc
.exp
.X_add_number
;
7043 /* The value is in two pieces: 0:11, 16:19. */
7044 inst
.instruction
|= (imm
& 0x00000fff);
7045 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7049 static void do_vfp_nsyn_opcode (const char *);
7052 do_vfp_nsyn_mrs (void)
7054 if (inst
.operands
[0].isvec
)
7056 if (inst
.operands
[1].reg
!= 1)
7057 first_error (_("operand 1 must be FPSCR"));
7058 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7059 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7060 do_vfp_nsyn_opcode ("fmstat");
7062 else if (inst
.operands
[1].isvec
)
7063 do_vfp_nsyn_opcode ("fmrx");
7071 do_vfp_nsyn_msr (void)
7073 if (inst
.operands
[0].isvec
)
7074 do_vfp_nsyn_opcode ("fmxr");
7084 if (do_vfp_nsyn_mrs () == SUCCESS
)
7087 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7088 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7090 _("'CPSR' or 'SPSR' expected"));
7091 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7092 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7095 /* Two possible forms:
7096 "{C|S}PSR_<field>, Rm",
7097 "{C|S}PSR_f, #expression". */
7102 if (do_vfp_nsyn_msr () == SUCCESS
)
7105 inst
.instruction
|= inst
.operands
[0].imm
;
7106 if (inst
.operands
[1].isreg
)
7107 inst
.instruction
|= inst
.operands
[1].reg
;
7110 inst
.instruction
|= INST_IMMEDIATE
;
7111 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7112 inst
.reloc
.pc_rel
= 0;
7119 if (!inst
.operands
[2].present
)
7120 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7121 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7122 inst
.instruction
|= inst
.operands
[1].reg
;
7123 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7125 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7126 as_tsktsk (_("rd and rm should be different in mul"));
7129 /* Long Multiply Parser
7130 UMULL RdLo, RdHi, Rm, Rs
7131 SMULL RdLo, RdHi, Rm, Rs
7132 UMLAL RdLo, RdHi, Rm, Rs
7133 SMLAL RdLo, RdHi, Rm, Rs. */
7138 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7139 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7140 inst
.instruction
|= inst
.operands
[2].reg
;
7141 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7143 /* rdhi, rdlo and rm must all be different. */
7144 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7145 || inst
.operands
[0].reg
== inst
.operands
[2].reg
7146 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7147 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7153 if (inst
.operands
[0].present
)
7155 /* Architectural NOP hints are CPSR sets with no bits selected. */
7156 inst
.instruction
&= 0xf0000000;
7157 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
7161 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7162 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7163 Condition defaults to COND_ALWAYS.
7164 Error if Rd, Rn or Rm are R15. */
7169 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7170 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7171 inst
.instruction
|= inst
.operands
[2].reg
;
7172 if (inst
.operands
[3].present
)
7173 encode_arm_shift (3);
7176 /* ARM V6 PKHTB (Argument Parse). */
7181 if (!inst
.operands
[3].present
)
7183 /* If the shift specifier is omitted, turn the instruction
7184 into pkhbt rd, rm, rn. */
7185 inst
.instruction
&= 0xfff00010;
7186 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7187 inst
.instruction
|= inst
.operands
[1].reg
;
7188 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7192 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7193 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7194 inst
.instruction
|= inst
.operands
[2].reg
;
7195 encode_arm_shift (3);
7199 /* ARMv5TE: Preload-Cache
7203 Syntactically, like LDR with B=1, W=0, L=1. */
7208 constraint (!inst
.operands
[0].isreg
,
7209 _("'[' expected after PLD mnemonic"));
7210 constraint (inst
.operands
[0].postind
,
7211 _("post-indexed expression used in preload instruction"));
7212 constraint (inst
.operands
[0].writeback
,
7213 _("writeback used in preload instruction"));
7214 constraint (!inst
.operands
[0].preind
,
7215 _("unindexed addressing used in preload instruction"));
7216 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7219 /* ARMv7: PLI <addr_mode> */
7223 constraint (!inst
.operands
[0].isreg
,
7224 _("'[' expected after PLI mnemonic"));
7225 constraint (inst
.operands
[0].postind
,
7226 _("post-indexed expression used in preload instruction"));
7227 constraint (inst
.operands
[0].writeback
,
7228 _("writeback used in preload instruction"));
7229 constraint (!inst
.operands
[0].preind
,
7230 _("unindexed addressing used in preload instruction"));
7231 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7232 inst
.instruction
&= ~PRE_INDEX
;
7238 inst
.operands
[1] = inst
.operands
[0];
7239 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7240 inst
.operands
[0].isreg
= 1;
7241 inst
.operands
[0].writeback
= 1;
7242 inst
.operands
[0].reg
= REG_SP
;
7246 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7247 word at the specified address and the following word
7249 Unconditionally executed.
7250 Error if Rn is R15. */
7255 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7256 if (inst
.operands
[0].writeback
)
7257 inst
.instruction
|= WRITE_BACK
;
7260 /* ARM V6 ssat (argument parse). */
7265 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7266 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7267 inst
.instruction
|= inst
.operands
[2].reg
;
7269 if (inst
.operands
[3].present
)
7270 encode_arm_shift (3);
7273 /* ARM V6 usat (argument parse). */
7278 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7279 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7280 inst
.instruction
|= inst
.operands
[2].reg
;
7282 if (inst
.operands
[3].present
)
7283 encode_arm_shift (3);
7286 /* ARM V6 ssat16 (argument parse). */
7291 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7292 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7293 inst
.instruction
|= inst
.operands
[2].reg
;
7299 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7300 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7301 inst
.instruction
|= inst
.operands
[2].reg
;
7304 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7305 preserving the other bits.
7307 setend <endian_specifier>, where <endian_specifier> is either
7313 if (inst
.operands
[0].imm
)
7314 inst
.instruction
|= 0x200;
7320 unsigned int Rm
= (inst
.operands
[1].present
7321 ? inst
.operands
[1].reg
7322 : inst
.operands
[0].reg
);
7324 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7325 inst
.instruction
|= Rm
;
7326 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7328 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7329 inst
.instruction
|= SHIFT_BY_REG
;
7332 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7338 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7339 inst
.reloc
.pc_rel
= 0;
7345 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7346 inst
.reloc
.pc_rel
= 0;
7349 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7350 SMLAxy{cond} Rd,Rm,Rs,Rn
7351 SMLAWy{cond} Rd,Rm,Rs,Rn
7352 Error if any register is R15. */
7357 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7358 inst
.instruction
|= inst
.operands
[1].reg
;
7359 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7360 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7363 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7364 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7365 Error if any register is R15.
7366 Warning if Rdlo == Rdhi. */
7371 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7372 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7373 inst
.instruction
|= inst
.operands
[2].reg
;
7374 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7376 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7377 as_tsktsk (_("rdhi and rdlo must be different"));
7380 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7381 SMULxy{cond} Rd,Rm,Rs
7382 Error if any register is R15. */
7387 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7388 inst
.instruction
|= inst
.operands
[1].reg
;
7389 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7392 /* ARM V6 srs (argument parse). */
7397 inst
.instruction
|= inst
.operands
[0].imm
;
7398 if (inst
.operands
[0].writeback
)
7399 inst
.instruction
|= WRITE_BACK
;
7402 /* ARM V6 strex (argument parse). */
7407 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7408 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7409 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7410 || inst
.operands
[2].negative
7411 /* See comment in do_ldrex(). */
7412 || (inst
.operands
[2].reg
== REG_PC
),
7415 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7416 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7418 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7419 || inst
.reloc
.exp
.X_add_number
!= 0,
7420 _("offset must be zero in ARM encoding"));
7422 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7423 inst
.instruction
|= inst
.operands
[1].reg
;
7424 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7425 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7431 constraint (inst
.operands
[1].reg
% 2 != 0,
7432 _("even register required"));
7433 constraint (inst
.operands
[2].present
7434 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7435 _("can only store two consecutive registers"));
7436 /* If op 2 were present and equal to PC, this function wouldn't
7437 have been called in the first place. */
7438 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7440 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7441 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7442 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7445 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7446 inst
.instruction
|= inst
.operands
[1].reg
;
7447 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7450 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7451 extends it to 32-bits, and adds the result to a value in another
7452 register. You can specify a rotation by 0, 8, 16, or 24 bits
7453 before extracting the 16-bit value.
7454 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7455 Condition defaults to COND_ALWAYS.
7456 Error if any register uses R15. */
7461 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7462 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7463 inst
.instruction
|= inst
.operands
[2].reg
;
7464 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
7469 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7470 Condition defaults to COND_ALWAYS.
7471 Error if any register uses R15. */
7476 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7477 inst
.instruction
|= inst
.operands
[1].reg
;
7478 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
7481 /* VFP instructions. In a logical order: SP variant first, monad
7482 before dyad, arithmetic then move then load/store. */
7485 do_vfp_sp_monadic (void)
7487 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7488 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7492 do_vfp_sp_dyadic (void)
7494 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7495 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7496 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7500 do_vfp_sp_compare_z (void)
7502 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7506 do_vfp_dp_sp_cvt (void)
7508 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7509 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7513 do_vfp_sp_dp_cvt (void)
7515 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7516 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7520 do_vfp_reg_from_sp (void)
7522 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7523 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7527 do_vfp_reg2_from_sp2 (void)
7529 constraint (inst
.operands
[2].imm
!= 2,
7530 _("only two consecutive VFP SP registers allowed here"));
7531 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7532 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7533 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7537 do_vfp_sp_from_reg (void)
7539 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
7540 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7544 do_vfp_sp2_from_reg2 (void)
7546 constraint (inst
.operands
[0].imm
!= 2,
7547 _("only two consecutive VFP SP registers allowed here"));
7548 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
7549 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7550 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7554 do_vfp_sp_ldst (void)
7556 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7557 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7561 do_vfp_dp_ldst (void)
7563 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7564 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7569 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
7571 if (inst
.operands
[0].writeback
)
7572 inst
.instruction
|= WRITE_BACK
;
7574 constraint (ldstm_type
!= VFP_LDSTMIA
,
7575 _("this addressing mode requires base-register writeback"));
7576 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7577 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
7578 inst
.instruction
|= inst
.operands
[1].imm
;
7582 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
7586 if (inst
.operands
[0].writeback
)
7587 inst
.instruction
|= WRITE_BACK
;
7589 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
7590 _("this addressing mode requires base-register writeback"));
7592 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7593 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7595 count
= inst
.operands
[1].imm
<< 1;
7596 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
7599 inst
.instruction
|= count
;
7603 do_vfp_sp_ldstmia (void)
7605 vfp_sp_ldstm (VFP_LDSTMIA
);
7609 do_vfp_sp_ldstmdb (void)
7611 vfp_sp_ldstm (VFP_LDSTMDB
);
7615 do_vfp_dp_ldstmia (void)
7617 vfp_dp_ldstm (VFP_LDSTMIA
);
7621 do_vfp_dp_ldstmdb (void)
7623 vfp_dp_ldstm (VFP_LDSTMDB
);
7627 do_vfp_xp_ldstmia (void)
7629 vfp_dp_ldstm (VFP_LDSTMIAX
);
7633 do_vfp_xp_ldstmdb (void)
7635 vfp_dp_ldstm (VFP_LDSTMDBX
);
7639 do_vfp_dp_rd_rm (void)
7641 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7642 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7646 do_vfp_dp_rn_rd (void)
7648 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
7649 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7653 do_vfp_dp_rd_rn (void)
7655 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7656 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7660 do_vfp_dp_rd_rn_rm (void)
7662 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7663 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7664 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
7670 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7674 do_vfp_dp_rm_rd_rn (void)
7676 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
7677 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7678 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
7681 /* VFPv3 instructions. */
7683 do_vfp_sp_const (void)
7685 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7686 inst
.instruction
|= (inst
.operands
[1].imm
& 15) << 16;
7687 inst
.instruction
|= (inst
.operands
[1].imm
>> 4);
7691 do_vfp_dp_const (void)
7693 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7694 inst
.instruction
|= (inst
.operands
[1].imm
& 15) << 16;
7695 inst
.instruction
|= (inst
.operands
[1].imm
>> 4);
7699 vfp_conv (int srcsize
)
7701 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
7702 inst
.instruction
|= (immbits
& 1) << 5;
7703 inst
.instruction
|= (immbits
>> 1);
7707 do_vfp_sp_conv_16 (void)
7709 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7714 do_vfp_dp_conv_16 (void)
7716 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7721 do_vfp_sp_conv_32 (void)
7723 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7728 do_vfp_dp_conv_32 (void)
7730 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7735 /* FPA instructions. Also in a logical order. */
7740 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7741 inst
.instruction
|= inst
.operands
[1].reg
;
7745 do_fpa_ldmstm (void)
7747 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7748 switch (inst
.operands
[1].imm
)
7750 case 1: inst
.instruction
|= CP_T_X
; break;
7751 case 2: inst
.instruction
|= CP_T_Y
; break;
7752 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
7757 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
7759 /* The instruction specified "ea" or "fd", so we can only accept
7760 [Rn]{!}. The instruction does not really support stacking or
7761 unstacking, so we have to emulate these by setting appropriate
7762 bits and offsets. */
7763 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7764 || inst
.reloc
.exp
.X_add_number
!= 0,
7765 _("this instruction does not support indexing"));
7767 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
7768 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
7770 if (!(inst
.instruction
& INDEX_UP
))
7771 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
7773 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
7775 inst
.operands
[2].preind
= 0;
7776 inst
.operands
[2].postind
= 1;
7780 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7784 /* iWMMXt instructions: strictly in alphabetical order. */
7787 do_iwmmxt_tandorc (void)
7789 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
7793 do_iwmmxt_textrc (void)
7795 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7796 inst
.instruction
|= inst
.operands
[1].imm
;
7800 do_iwmmxt_textrm (void)
7802 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7803 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7804 inst
.instruction
|= inst
.operands
[2].imm
;
7808 do_iwmmxt_tinsr (void)
7810 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7811 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7812 inst
.instruction
|= inst
.operands
[2].imm
;
7816 do_iwmmxt_tmia (void)
7818 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7819 inst
.instruction
|= inst
.operands
[1].reg
;
7820 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7824 do_iwmmxt_waligni (void)
7826 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7827 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7828 inst
.instruction
|= inst
.operands
[2].reg
;
7829 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
7833 do_iwmmxt_wmov (void)
7835 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7836 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7837 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7838 inst
.instruction
|= inst
.operands
[1].reg
;
7842 do_iwmmxt_wldstbh (void)
7845 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7847 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
7849 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
7850 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
7854 do_iwmmxt_wldstw (void)
7856 /* RIWR_RIWC clears .isreg for a control register. */
7857 if (!inst
.operands
[0].isreg
)
7859 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7860 inst
.instruction
|= 0xf0000000;
7863 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7864 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7868 do_iwmmxt_wldstd (void)
7870 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7871 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
7875 do_iwmmxt_wshufh (void)
7877 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7878 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7879 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
7880 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
7884 do_iwmmxt_wzero (void)
7886 /* WZERO reg is an alias for WANDN reg, reg, reg. */
7887 inst
.instruction
|= inst
.operands
[0].reg
;
7888 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7889 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7892 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
7893 operations first, then control, shift, and load/store. */
7895 /* Insns like "foo X,Y,Z". */
7898 do_mav_triple (void)
7900 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7901 inst
.instruction
|= inst
.operands
[1].reg
;
7902 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7905 /* Insns like "foo W,X,Y,Z".
7906 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
7911 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7912 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7913 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7914 inst
.instruction
|= inst
.operands
[3].reg
;
7917 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
7921 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7924 /* Maverick shift immediate instructions.
7925 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
7926 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
7931 int imm
= inst
.operands
[2].imm
;
7933 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7934 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7936 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
7937 Bits 5-7 of the insn should have bits 4-6 of the immediate.
7938 Bit 4 should be 0. */
7939 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
7941 inst
.instruction
|= imm
;
7944 /* XScale instructions. Also sorted arithmetic before move. */
7946 /* Xscale multiply-accumulate (argument parse)
7949 MIAxycc acc0,Rm,Rs. */
7954 inst
.instruction
|= inst
.operands
[1].reg
;
7955 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7958 /* Xscale move-accumulator-register (argument parse)
7960 MARcc acc0,RdLo,RdHi. */
7965 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7966 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7969 /* Xscale move-register-accumulator (argument parse)
7971 MRAcc RdLo,RdHi,acc0. */
7976 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
7977 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7978 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7981 /* Encoding functions relevant only to Thumb. */
7983 /* inst.operands[i] is a shifted-register operand; encode
7984 it into inst.instruction in the format used by Thumb32. */
7987 encode_thumb32_shifted_operand (int i
)
7989 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
7990 unsigned int shift
= inst
.operands
[i
].shift_kind
;
7992 constraint (inst
.operands
[i
].immisreg
,
7993 _("shift by register not allowed in thumb mode"));
7994 inst
.instruction
|= inst
.operands
[i
].reg
;
7995 if (shift
== SHIFT_RRX
)
7996 inst
.instruction
|= SHIFT_ROR
<< 4;
7999 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8000 _("expression too complex"));
8002 constraint (value
> 32
8003 || (value
== 32 && (shift
== SHIFT_LSL
8004 || shift
== SHIFT_ROR
)),
8005 _("shift expression is too large"));
8009 else if (value
== 32)
8012 inst
.instruction
|= shift
<< 4;
8013 inst
.instruction
|= (value
& 0x1c) << 10;
8014 inst
.instruction
|= (value
& 0x03) << 6;
8019 /* inst.operands[i] was set up by parse_address. Encode it into a
8020 Thumb32 format load or store instruction. Reject forms that cannot
8021 be used with such instructions. If is_t is true, reject forms that
8022 cannot be used with a T instruction; if is_d is true, reject forms
8023 that cannot be used with a D instruction. */
8026 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8028 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8030 constraint (!inst
.operands
[i
].isreg
,
8031 _("Instruction does not support =N addresses"));
8033 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8034 if (inst
.operands
[i
].immisreg
)
8036 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8037 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8038 constraint (inst
.operands
[i
].negative
,
8039 _("Thumb does not support negative register indexing"));
8040 constraint (inst
.operands
[i
].postind
,
8041 _("Thumb does not support register post-indexing"));
8042 constraint (inst
.operands
[i
].writeback
,
8043 _("Thumb does not support register indexing with writeback"));
8044 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8045 _("Thumb supports only LSL in shifted register indexing"));
8047 inst
.instruction
|= inst
.operands
[i
].imm
;
8048 if (inst
.operands
[i
].shifted
)
8050 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8051 _("expression too complex"));
8052 constraint (inst
.reloc
.exp
.X_add_number
< 0
8053 || inst
.reloc
.exp
.X_add_number
> 3,
8054 _("shift out of range"));
8055 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8057 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8059 else if (inst
.operands
[i
].preind
)
8061 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8062 _("cannot use writeback with PC-relative addressing"));
8063 constraint (is_t
&& inst
.operands
[i
].writeback
,
8064 _("cannot use writeback with this instruction"));
8068 inst
.instruction
|= 0x01000000;
8069 if (inst
.operands
[i
].writeback
)
8070 inst
.instruction
|= 0x00200000;
8074 inst
.instruction
|= 0x00000c00;
8075 if (inst
.operands
[i
].writeback
)
8076 inst
.instruction
|= 0x00000100;
8078 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8080 else if (inst
.operands
[i
].postind
)
8082 assert (inst
.operands
[i
].writeback
);
8083 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8084 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8087 inst
.instruction
|= 0x00200000;
8089 inst
.instruction
|= 0x00000900;
8090 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8092 else /* unindexed - only for coprocessor */
8093 inst
.error
= _("instruction does not accept unindexed addressing");
8096 /* Table of Thumb instructions which exist in both 16- and 32-bit
8097 encodings (the latter only in post-V6T2 cores). The index is the
8098 value used in the insns table below. When there is more than one
8099 possible 16-bit encoding for the instruction, this table always
8101 Also contains several pseudo-instructions used during relaxation. */
8102 #define T16_32_TAB \
8103 X(adc, 4140, eb400000), \
8104 X(adcs, 4140, eb500000), \
8105 X(add, 1c00, eb000000), \
8106 X(adds, 1c00, eb100000), \
8107 X(addi, 0000, f1000000), \
8108 X(addis, 0000, f1100000), \
8109 X(add_pc,000f, f20f0000), \
8110 X(add_sp,000d, f10d0000), \
8111 X(adr, 000f, f20f0000), \
8112 X(and, 4000, ea000000), \
8113 X(ands, 4000, ea100000), \
8114 X(asr, 1000, fa40f000), \
8115 X(asrs, 1000, fa50f000), \
8116 X(b, e000, f000b000), \
8117 X(bcond, d000, f0008000), \
8118 X(bic, 4380, ea200000), \
8119 X(bics, 4380, ea300000), \
8120 X(cmn, 42c0, eb100f00), \
8121 X(cmp, 2800, ebb00f00), \
8122 X(cpsie, b660, f3af8400), \
8123 X(cpsid, b670, f3af8600), \
8124 X(cpy, 4600, ea4f0000), \
8125 X(dec_sp,80dd, f1bd0d00), \
8126 X(eor, 4040, ea800000), \
8127 X(eors, 4040, ea900000), \
8128 X(inc_sp,00dd, f10d0d00), \
8129 X(ldmia, c800, e8900000), \
8130 X(ldr, 6800, f8500000), \
8131 X(ldrb, 7800, f8100000), \
8132 X(ldrh, 8800, f8300000), \
8133 X(ldrsb, 5600, f9100000), \
8134 X(ldrsh, 5e00, f9300000), \
8135 X(ldr_pc,4800, f85f0000), \
8136 X(ldr_pc2,4800, f85f0000), \
8137 X(ldr_sp,9800, f85d0000), \
8138 X(lsl, 0000, fa00f000), \
8139 X(lsls, 0000, fa10f000), \
8140 X(lsr, 0800, fa20f000), \
8141 X(lsrs, 0800, fa30f000), \
8142 X(mov, 2000, ea4f0000), \
8143 X(movs, 2000, ea5f0000), \
8144 X(mul, 4340, fb00f000), \
8145 X(muls, 4340, ffffffff), /* no 32b muls */ \
8146 X(mvn, 43c0, ea6f0000), \
8147 X(mvns, 43c0, ea7f0000), \
8148 X(neg, 4240, f1c00000), /* rsb #0 */ \
8149 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8150 X(orr, 4300, ea400000), \
8151 X(orrs, 4300, ea500000), \
8152 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8153 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8154 X(rev, ba00, fa90f080), \
8155 X(rev16, ba40, fa90f090), \
8156 X(revsh, bac0, fa90f0b0), \
8157 X(ror, 41c0, fa60f000), \
8158 X(rors, 41c0, fa70f000), \
8159 X(sbc, 4180, eb600000), \
8160 X(sbcs, 4180, eb700000), \
8161 X(stmia, c000, e8800000), \
8162 X(str, 6000, f8400000), \
8163 X(strb, 7000, f8000000), \
8164 X(strh, 8000, f8200000), \
8165 X(str_sp,9000, f84d0000), \
8166 X(sub, 1e00, eba00000), \
8167 X(subs, 1e00, ebb00000), \
8168 X(subi, 8000, f1a00000), \
8169 X(subis, 8000, f1b00000), \
8170 X(sxtb, b240, fa4ff080), \
8171 X(sxth, b200, fa0ff080), \
8172 X(tst, 4200, ea100f00), \
8173 X(uxtb, b2c0, fa5ff080), \
8174 X(uxth, b280, fa1ff080), \
8175 X(nop, bf00, f3af8000), \
8176 X(yield, bf10, f3af8001), \
8177 X(wfe, bf20, f3af8002), \
8178 X(wfi, bf30, f3af8003), \
8179 X(sev, bf40, f3af9004), /* typo, 8004? */
8181 /* To catch errors in encoding functions, the codes are all offset by
8182 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8183 as 16-bit instructions. */
8184 #define X(a,b,c) T_MNEM_##a
8185 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8188 #define X(a,b,c) 0x##b
8189 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8190 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8193 #define X(a,b,c) 0x##c
8194 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8195 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8196 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8200 /* Thumb instruction encoders, in alphabetical order. */
8204 do_t_add_sub_w (void)
8208 Rd
= inst
.operands
[0].reg
;
8209 Rn
= inst
.operands
[1].reg
;
8211 constraint (Rd
== 15, _("PC not allowed as destination"));
8212 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8213 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8216 /* Parse an add or subtract instruction. We get here with inst.instruction
8217 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8224 Rd
= inst
.operands
[0].reg
;
8225 Rs
= (inst
.operands
[1].present
8226 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8227 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8235 flags
= (inst
.instruction
== T_MNEM_adds
8236 || inst
.instruction
== T_MNEM_subs
);
8238 narrow
= (current_it_mask
== 0);
8240 narrow
= (current_it_mask
!= 0);
8241 if (!inst
.operands
[2].isreg
)
8245 add
= (inst
.instruction
== T_MNEM_add
8246 || inst
.instruction
== T_MNEM_adds
);
8248 if (inst
.size_req
!= 4)
8250 /* Attempt to use a narrow opcode, with relaxation if
8252 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8253 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8254 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8255 opcode
= T_MNEM_add_sp
;
8256 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8257 opcode
= T_MNEM_add_pc
;
8258 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8261 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8263 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8267 inst
.instruction
= THUMB_OP16(opcode
);
8268 inst
.instruction
|= (Rd
<< 4) | Rs
;
8269 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8270 if (inst
.size_req
!= 2)
8271 inst
.relax
= opcode
;
8274 constraint (inst
.size_req
== 2, BAD_HIREG
);
8276 if (inst
.size_req
== 4
8277 || (inst
.size_req
!= 2 && !opcode
))
8281 /* Always use addw/subw. */
8282 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8283 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8287 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8288 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8291 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8293 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8295 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8296 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8301 Rn
= inst
.operands
[2].reg
;
8302 /* See if we can do this with a 16-bit instruction. */
8303 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8305 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8310 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8311 || inst
.instruction
== T_MNEM_add
)
8314 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8318 if (inst
.instruction
== T_MNEM_add
)
8322 inst
.instruction
= T_OPCODE_ADD_HI
;
8323 inst
.instruction
|= (Rd
& 8) << 4;
8324 inst
.instruction
|= (Rd
& 7);
8325 inst
.instruction
|= Rn
<< 3;
8328 /* ... because addition is commutative! */
8331 inst
.instruction
= T_OPCODE_ADD_HI
;
8332 inst
.instruction
|= (Rd
& 8) << 4;
8333 inst
.instruction
|= (Rd
& 7);
8334 inst
.instruction
|= Rs
<< 3;
8339 /* If we get here, it can't be done in 16 bits. */
8340 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8341 _("shift must be constant"));
8342 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8343 inst
.instruction
|= Rd
<< 8;
8344 inst
.instruction
|= Rs
<< 16;
8345 encode_thumb32_shifted_operand (2);
8350 constraint (inst
.instruction
== T_MNEM_adds
8351 || inst
.instruction
== T_MNEM_subs
,
8354 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
8356 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
8357 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
8360 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8362 inst
.instruction
|= (Rd
<< 4) | Rs
;
8363 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8367 Rn
= inst
.operands
[2].reg
;
8368 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
8370 /* We now have Rd, Rs, and Rn set to registers. */
8371 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8373 /* Can't do this for SUB. */
8374 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
8375 inst
.instruction
= T_OPCODE_ADD_HI
;
8376 inst
.instruction
|= (Rd
& 8) << 4;
8377 inst
.instruction
|= (Rd
& 7);
8379 inst
.instruction
|= Rn
<< 3;
8381 inst
.instruction
|= Rs
<< 3;
8383 constraint (1, _("dest must overlap one source register"));
8387 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8388 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
8389 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8397 if (unified_syntax
&& inst
.size_req
== 0 && inst
.operands
[0].reg
<= 7)
8399 /* Defer to section relaxation. */
8400 inst
.relax
= inst
.instruction
;
8401 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8402 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8404 else if (unified_syntax
&& inst
.size_req
!= 2)
8406 /* Generate a 32-bit opcode. */
8407 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8408 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8409 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
8410 inst
.reloc
.pc_rel
= 1;
8414 /* Generate a 16-bit opcode. */
8415 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8416 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8417 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
8418 inst
.reloc
.pc_rel
= 1;
8420 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8424 /* Arithmetic instructions for which there is just one 16-bit
8425 instruction encoding, and it allows only two low registers.
8426 For maximal compatibility with ARM syntax, we allow three register
8427 operands even when Thumb-32 instructions are not available, as long
8428 as the first two are identical. For instance, both "sbc r0,r1" and
8429 "sbc r0,r0,r1" are allowed. */
8435 Rd
= inst
.operands
[0].reg
;
8436 Rs
= (inst
.operands
[1].present
8437 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8438 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8439 Rn
= inst
.operands
[2].reg
;
8443 if (!inst
.operands
[2].isreg
)
8445 /* For an immediate, we always generate a 32-bit opcode;
8446 section relaxation will shrink it later if possible. */
8447 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8448 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8449 inst
.instruction
|= Rd
<< 8;
8450 inst
.instruction
|= Rs
<< 16;
8451 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8457 /* See if we can do this with a 16-bit instruction. */
8458 if (THUMB_SETS_FLAGS (inst
.instruction
))
8459 narrow
= current_it_mask
== 0;
8461 narrow
= current_it_mask
!= 0;
8463 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8465 if (inst
.operands
[2].shifted
)
8467 if (inst
.size_req
== 4)
8473 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8474 inst
.instruction
|= Rd
;
8475 inst
.instruction
|= Rn
<< 3;
8479 /* If we get here, it can't be done in 16 bits. */
8480 constraint (inst
.operands
[2].shifted
8481 && inst
.operands
[2].immisreg
,
8482 _("shift must be constant"));
8483 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8484 inst
.instruction
|= Rd
<< 8;
8485 inst
.instruction
|= Rs
<< 16;
8486 encode_thumb32_shifted_operand (2);
8491 /* On its face this is a lie - the instruction does set the
8492 flags. However, the only supported mnemonic in this mode
8494 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8496 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8497 _("unshifted register required"));
8498 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8499 constraint (Rd
!= Rs
,
8500 _("dest and source1 must be the same register"));
8502 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8503 inst
.instruction
|= Rd
;
8504 inst
.instruction
|= Rn
<< 3;
8508 /* Similarly, but for instructions where the arithmetic operation is
8509 commutative, so we can allow either of them to be different from
8510 the destination operand in a 16-bit instruction. For instance, all
8511 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8518 Rd
= inst
.operands
[0].reg
;
8519 Rs
= (inst
.operands
[1].present
8520 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8521 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8522 Rn
= inst
.operands
[2].reg
;
8526 if (!inst
.operands
[2].isreg
)
8528 /* For an immediate, we always generate a 32-bit opcode;
8529 section relaxation will shrink it later if possible. */
8530 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8531 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8532 inst
.instruction
|= Rd
<< 8;
8533 inst
.instruction
|= Rs
<< 16;
8534 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8540 /* See if we can do this with a 16-bit instruction. */
8541 if (THUMB_SETS_FLAGS (inst
.instruction
))
8542 narrow
= current_it_mask
== 0;
8544 narrow
= current_it_mask
!= 0;
8546 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8548 if (inst
.operands
[2].shifted
)
8550 if (inst
.size_req
== 4)
8557 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8558 inst
.instruction
|= Rd
;
8559 inst
.instruction
|= Rn
<< 3;
8564 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8565 inst
.instruction
|= Rd
;
8566 inst
.instruction
|= Rs
<< 3;
8571 /* If we get here, it can't be done in 16 bits. */
8572 constraint (inst
.operands
[2].shifted
8573 && inst
.operands
[2].immisreg
,
8574 _("shift must be constant"));
8575 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8576 inst
.instruction
|= Rd
<< 8;
8577 inst
.instruction
|= Rs
<< 16;
8578 encode_thumb32_shifted_operand (2);
8583 /* On its face this is a lie - the instruction does set the
8584 flags. However, the only supported mnemonic in this mode
8586 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8588 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8589 _("unshifted register required"));
8590 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8592 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8593 inst
.instruction
|= Rd
;
8596 inst
.instruction
|= Rn
<< 3;
8598 inst
.instruction
|= Rs
<< 3;
8600 constraint (1, _("dest must overlap one source register"));
8607 if (inst
.operands
[0].present
)
8609 constraint ((inst
.instruction
& 0xf0) != 0x40
8610 && inst
.operands
[0].imm
!= 0xf,
8611 "bad barrier type");
8612 inst
.instruction
|= inst
.operands
[0].imm
;
8615 inst
.instruction
|= 0xf;
8621 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8622 constraint (msb
> 32, _("bit-field extends past end of register"));
8623 /* The instruction encoding stores the LSB and MSB,
8624 not the LSB and width. */
8625 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8626 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
8627 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
8628 inst
.instruction
|= msb
- 1;
8636 /* #0 in second position is alternative syntax for bfc, which is
8637 the same instruction but with REG_PC in the Rm field. */
8638 if (!inst
.operands
[1].isreg
)
8639 inst
.operands
[1].reg
= REG_PC
;
8641 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8642 constraint (msb
> 32, _("bit-field extends past end of register"));
8643 /* The instruction encoding stores the LSB and MSB,
8644 not the LSB and width. */
8645 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8646 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8647 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8648 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8649 inst
.instruction
|= msb
- 1;
8655 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8656 _("bit-field extends past end of register"));
8657 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8658 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8659 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8660 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8661 inst
.instruction
|= inst
.operands
[3].imm
- 1;
8664 /* ARM V5 Thumb BLX (argument parse)
8665 BLX <target_addr> which is BLX(1)
8666 BLX <Rm> which is BLX(2)
8667 Unfortunately, there are two different opcodes for this mnemonic.
8668 So, the insns[].value is not used, and the code here zaps values
8669 into inst.instruction.
8671 ??? How to take advantage of the additional two bits of displacement
8672 available in Thumb32 mode? Need new relocation? */
8677 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8678 if (inst
.operands
[0].isreg
)
8679 /* We have a register, so this is BLX(2). */
8680 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8683 /* No register. This must be BLX(1). */
8684 inst
.instruction
= 0xf000e800;
8686 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8687 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8690 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
8691 inst
.reloc
.pc_rel
= 1;
8701 if (current_it_mask
)
8703 /* Conditional branches inside IT blocks are encoded as unconditional
8706 /* A branch must be the last instruction in an IT block. */
8707 constraint (current_it_mask
!= 0x10, BAD_BRANCH
);
8712 if (cond
!= COND_ALWAYS
)
8713 opcode
= T_MNEM_bcond
;
8715 opcode
= inst
.instruction
;
8717 if (unified_syntax
&& inst
.size_req
== 4)
8719 inst
.instruction
= THUMB_OP32(opcode
);
8720 if (cond
== COND_ALWAYS
)
8721 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
8724 assert (cond
!= 0xF);
8725 inst
.instruction
|= cond
<< 22;
8726 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
8731 inst
.instruction
= THUMB_OP16(opcode
);
8732 if (cond
== COND_ALWAYS
)
8733 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
8736 inst
.instruction
|= cond
<< 8;
8737 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
8739 /* Allow section relaxation. */
8740 if (unified_syntax
&& inst
.size_req
!= 2)
8741 inst
.relax
= opcode
;
8744 inst
.reloc
.pc_rel
= 1;
8750 constraint (inst
.cond
!= COND_ALWAYS
,
8751 _("instruction is always unconditional"));
8752 if (inst
.operands
[0].present
)
8754 constraint (inst
.operands
[0].imm
> 255,
8755 _("immediate value out of range"));
8756 inst
.instruction
|= inst
.operands
[0].imm
;
8761 do_t_branch23 (void)
8763 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8764 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8765 inst
.reloc
.pc_rel
= 1;
8767 /* If the destination of the branch is a defined symbol which does not have
8768 the THUMB_FUNC attribute, then we must be calling a function which has
8769 the (interfacearm) attribute. We look for the Thumb entry point to that
8770 function and change the branch to refer to that function instead. */
8771 if ( inst
.reloc
.exp
.X_op
== O_symbol
8772 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8773 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8774 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8775 inst
.reloc
.exp
.X_add_symbol
=
8776 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
8782 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8783 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8784 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8785 should cause the alignment to be checked once it is known. This is
8786 because BX PC only works if the instruction is word aligned. */
8792 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8793 if (inst
.operands
[0].reg
== REG_PC
)
8794 as_tsktsk (_("use of r15 in bxj is not really useful"));
8796 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8802 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8803 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8804 inst
.instruction
|= inst
.operands
[1].reg
;
8810 constraint (current_it_mask
, BAD_NOT_IT
);
8811 inst
.instruction
|= inst
.operands
[0].imm
;
8817 constraint (current_it_mask
, BAD_NOT_IT
);
8819 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
8820 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
8822 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
8823 inst
.instruction
= 0xf3af8000;
8824 inst
.instruction
|= imod
<< 9;
8825 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
8826 if (inst
.operands
[1].present
)
8827 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
8831 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
8832 && (inst
.operands
[0].imm
& 4),
8833 _("selected processor does not support 'A' form "
8834 "of this instruction"));
8835 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
8836 _("Thumb does not support the 2-argument "
8837 "form of this instruction"));
8838 inst
.instruction
|= inst
.operands
[0].imm
;
8842 /* THUMB CPY instruction (argument parse). */
8847 if (inst
.size_req
== 4)
8849 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
8850 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8851 inst
.instruction
|= inst
.operands
[1].reg
;
8855 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
8856 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
8857 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
8864 constraint (current_it_mask
, BAD_NOT_IT
);
8865 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
8866 inst
.instruction
|= inst
.operands
[0].reg
;
8867 inst
.reloc
.pc_rel
= 1;
8868 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
8874 inst
.instruction
|= inst
.operands
[0].imm
;
8880 if (!inst
.operands
[1].present
)
8881 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8882 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8883 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8884 inst
.instruction
|= inst
.operands
[2].reg
;
8890 if (unified_syntax
&& inst
.size_req
== 4)
8891 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8893 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8899 unsigned int cond
= inst
.operands
[0].imm
;
8901 constraint (current_it_mask
, BAD_NOT_IT
);
8902 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
8905 /* If the condition is a negative condition, invert the mask. */
8906 if ((cond
& 0x1) == 0x0)
8908 unsigned int mask
= inst
.instruction
& 0x000f;
8910 if ((mask
& 0x7) == 0)
8911 /* no conversion needed */;
8912 else if ((mask
& 0x3) == 0)
8914 else if ((mask
& 0x1) == 0)
8919 inst
.instruction
&= 0xfff0;
8920 inst
.instruction
|= mask
;
8923 inst
.instruction
|= cond
<< 4;
8929 /* This really doesn't seem worth it. */
8930 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
8931 _("expression too complex"));
8932 constraint (inst
.operands
[1].writeback
,
8933 _("Thumb load/store multiple does not support {reglist}^"));
8937 /* See if we can use a 16-bit instruction. */
8938 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
8939 && inst
.size_req
!= 4
8940 && inst
.operands
[0].reg
<= 7
8941 && !(inst
.operands
[1].imm
& ~0xff)
8942 && (inst
.instruction
== T_MNEM_stmia
8943 ? inst
.operands
[0].writeback
8944 : (inst
.operands
[0].writeback
8945 == !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))))
8947 if (inst
.instruction
== T_MNEM_stmia
8948 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8949 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
8950 as_warn (_("value stored for r%d is UNPREDICTABLE"),
8951 inst
.operands
[0].reg
);
8953 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8954 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8955 inst
.instruction
|= inst
.operands
[1].imm
;
8959 if (inst
.operands
[1].imm
& (1 << 13))
8960 as_warn (_("SP should not be in register list"));
8961 if (inst
.instruction
== T_MNEM_stmia
)
8963 if (inst
.operands
[1].imm
& (1 << 15))
8964 as_warn (_("PC should not be in register list"));
8965 if (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8966 as_warn (_("value stored for r%d is UNPREDICTABLE"),
8967 inst
.operands
[0].reg
);
8971 if (inst
.operands
[1].imm
& (1 << 14)
8972 && inst
.operands
[1].imm
& (1 << 15))
8973 as_warn (_("LR and PC should not both be in register list"));
8974 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8975 && inst
.operands
[0].writeback
)
8976 as_warn (_("base register should not be in register list "
8977 "when written back"));
8979 if (inst
.instruction
< 0xffff)
8980 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8981 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8982 inst
.instruction
|= inst
.operands
[1].imm
;
8983 if (inst
.operands
[0].writeback
)
8984 inst
.instruction
|= WRITE_BACK
;
8989 constraint (inst
.operands
[0].reg
> 7
8990 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
8991 if (inst
.instruction
== T_MNEM_stmia
)
8993 if (!inst
.operands
[0].writeback
)
8994 as_warn (_("this instruction will write back the base register"));
8995 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8996 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
8997 as_warn (_("value stored for r%d is UNPREDICTABLE"),
8998 inst
.operands
[0].reg
);
9002 if (!inst
.operands
[0].writeback
9003 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9004 as_warn (_("this instruction will write back the base register"));
9005 else if (inst
.operands
[0].writeback
9006 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9007 as_warn (_("this instruction will not write back the base register"));
9010 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9011 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9012 inst
.instruction
|= inst
.operands
[1].imm
;
9019 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9020 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9021 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9022 || inst
.operands
[1].negative
,
9025 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9026 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9027 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9033 if (!inst
.operands
[1].present
)
9035 constraint (inst
.operands
[0].reg
== REG_LR
,
9036 _("r14 not allowed as first register "
9037 "when second register is omitted"));
9038 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9040 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9043 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9044 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9045 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9051 unsigned long opcode
;
9054 opcode
= inst
.instruction
;
9057 if (!inst
.operands
[1].isreg
)
9059 if (opcode
<= 0xffff)
9060 inst
.instruction
= THUMB_OP32 (opcode
);
9061 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9064 if (inst
.operands
[1].isreg
9065 && !inst
.operands
[1].writeback
9066 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9067 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9069 && inst
.size_req
!= 4)
9071 /* Insn may have a 16-bit form. */
9072 Rn
= inst
.operands
[1].reg
;
9073 if (inst
.operands
[1].immisreg
)
9075 inst
.instruction
= THUMB_OP16 (opcode
);
9077 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9080 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9081 && opcode
!= T_MNEM_ldrsb
)
9082 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9083 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9090 if (inst
.reloc
.pc_rel
)
9091 opcode
= T_MNEM_ldr_pc2
;
9093 opcode
= T_MNEM_ldr_pc
;
9097 if (opcode
== T_MNEM_ldr
)
9098 opcode
= T_MNEM_ldr_sp
;
9100 opcode
= T_MNEM_str_sp
;
9102 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9106 inst
.instruction
= inst
.operands
[0].reg
;
9107 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9109 inst
.instruction
|= THUMB_OP16 (opcode
);
9110 if (inst
.size_req
== 2)
9111 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9113 inst
.relax
= opcode
;
9117 /* Definitely a 32-bit variant. */
9118 inst
.instruction
= THUMB_OP32 (opcode
);
9119 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9120 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9124 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9126 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9128 /* Only [Rn,Rm] is acceptable. */
9129 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9130 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9131 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9132 || inst
.operands
[1].negative
,
9133 _("Thumb does not support this addressing mode"));
9134 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9138 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9139 if (!inst
.operands
[1].isreg
)
9140 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9143 constraint (!inst
.operands
[1].preind
9144 || inst
.operands
[1].shifted
9145 || inst
.operands
[1].writeback
,
9146 _("Thumb does not support this addressing mode"));
9147 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9149 constraint (inst
.instruction
& 0x0600,
9150 _("byte or halfword not valid for base register"));
9151 constraint (inst
.operands
[1].reg
== REG_PC
9152 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9153 _("r15 based store not allowed"));
9154 constraint (inst
.operands
[1].immisreg
,
9155 _("invalid base register for register offset"));
9157 if (inst
.operands
[1].reg
== REG_PC
)
9158 inst
.instruction
= T_OPCODE_LDR_PC
;
9159 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9160 inst
.instruction
= T_OPCODE_LDR_SP
;
9162 inst
.instruction
= T_OPCODE_STR_SP
;
9164 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9165 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9169 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9170 if (!inst
.operands
[1].immisreg
)
9172 /* Immediate offset. */
9173 inst
.instruction
|= inst
.operands
[0].reg
;
9174 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9175 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9179 /* Register offset. */
9180 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9181 constraint (inst
.operands
[1].negative
,
9182 _("Thumb does not support this addressing mode"));
9185 switch (inst
.instruction
)
9187 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9188 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9189 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9190 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9191 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9192 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9193 case 0x5600 /* ldrsb */:
9194 case 0x5e00 /* ldrsh */: break;
9198 inst
.instruction
|= inst
.operands
[0].reg
;
9199 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9200 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9206 if (!inst
.operands
[1].present
)
9208 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9209 constraint (inst
.operands
[0].reg
== REG_LR
,
9210 _("r14 not allowed here"));
9212 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9213 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9214 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9221 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9222 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
9228 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9229 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9230 inst
.instruction
|= inst
.operands
[2].reg
;
9231 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9237 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9238 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9239 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9240 inst
.instruction
|= inst
.operands
[3].reg
;
9248 int r0off
= (inst
.instruction
== T_MNEM_mov
9249 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
9250 unsigned long opcode
;
9252 bfd_boolean low_regs
;
9254 low_regs
= (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7);
9255 opcode
= inst
.instruction
;
9256 if (current_it_mask
)
9257 narrow
= opcode
!= T_MNEM_movs
;
9259 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
9260 if (inst
.size_req
== 4
9261 || inst
.operands
[1].shifted
)
9264 if (!inst
.operands
[1].isreg
)
9266 /* Immediate operand. */
9267 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
9269 if (low_regs
&& narrow
)
9271 inst
.instruction
= THUMB_OP16 (opcode
);
9272 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9273 if (inst
.size_req
== 2)
9274 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9276 inst
.relax
= opcode
;
9280 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9281 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9282 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9283 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9288 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9289 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9290 encode_thumb32_shifted_operand (1);
9293 switch (inst
.instruction
)
9296 inst
.instruction
= T_OPCODE_MOV_HR
;
9297 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9298 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9299 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9303 /* We know we have low registers at this point.
9304 Generate ADD Rd, Rs, #0. */
9305 inst
.instruction
= T_OPCODE_ADD_I3
;
9306 inst
.instruction
|= inst
.operands
[0].reg
;
9307 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9313 inst
.instruction
= T_OPCODE_CMP_LR
;
9314 inst
.instruction
|= inst
.operands
[0].reg
;
9315 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9319 inst
.instruction
= T_OPCODE_CMP_HR
;
9320 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9321 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9322 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9329 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9330 if (inst
.operands
[1].isreg
)
9332 if (inst
.operands
[0].reg
< 8 && inst
.operands
[1].reg
< 8)
9334 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9335 since a MOV instruction produces unpredictable results. */
9336 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9337 inst
.instruction
= T_OPCODE_ADD_I3
;
9339 inst
.instruction
= T_OPCODE_CMP_LR
;
9341 inst
.instruction
|= inst
.operands
[0].reg
;
9342 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9346 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9347 inst
.instruction
= T_OPCODE_MOV_HR
;
9349 inst
.instruction
= T_OPCODE_CMP_HR
;
9355 constraint (inst
.operands
[0].reg
> 7,
9356 _("only lo regs allowed with immediate"));
9357 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9358 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9368 top
= (inst
.instruction
& 0x00800000) != 0;
9369 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
9371 constraint (top
, _(":lower16: not allowed this instruction"));
9372 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
9374 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
9376 constraint (!top
, _(":upper16: not allowed this instruction"));
9377 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
9380 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9381 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9383 imm
= inst
.reloc
.exp
.X_add_number
;
9384 inst
.instruction
|= (imm
& 0xf000) << 4;
9385 inst
.instruction
|= (imm
& 0x0800) << 15;
9386 inst
.instruction
|= (imm
& 0x0700) << 4;
9387 inst
.instruction
|= (imm
& 0x00ff);
9396 int r0off
= (inst
.instruction
== T_MNEM_mvn
9397 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
9400 if (inst
.size_req
== 4
9401 || inst
.instruction
> 0xffff
9402 || inst
.operands
[1].shifted
9403 || inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9405 else if (inst
.instruction
== T_MNEM_cmn
)
9407 else if (THUMB_SETS_FLAGS (inst
.instruction
))
9408 narrow
= (current_it_mask
== 0);
9410 narrow
= (current_it_mask
!= 0);
9412 if (!inst
.operands
[1].isreg
)
9414 /* For an immediate, we always generate a 32-bit opcode;
9415 section relaxation will shrink it later if possible. */
9416 if (inst
.instruction
< 0xffff)
9417 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9418 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9419 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9420 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9424 /* See if we can do this with a 16-bit instruction. */
9427 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9428 inst
.instruction
|= inst
.operands
[0].reg
;
9429 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9433 constraint (inst
.operands
[1].shifted
9434 && inst
.operands
[1].immisreg
,
9435 _("shift must be constant"));
9436 if (inst
.instruction
< 0xffff)
9437 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9438 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9439 encode_thumb32_shifted_operand (1);
9445 constraint (inst
.instruction
> 0xffff
9446 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
9447 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
9448 _("unshifted register required"));
9449 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9452 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9453 inst
.instruction
|= inst
.operands
[0].reg
;
9454 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9463 if (do_vfp_nsyn_mrs () == SUCCESS
)
9466 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
9469 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9470 _("selected processor does not support "
9471 "requested special purpose register"));
9475 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9476 _("selected processor does not support "
9477 "requested special purpose register %x"));
9478 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9479 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
9480 _("'CPSR' or 'SPSR' expected"));
9483 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9484 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9485 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
9493 if (do_vfp_nsyn_msr () == SUCCESS
)
9496 constraint (!inst
.operands
[1].isreg
,
9497 _("Thumb encoding does not support an immediate here"));
9498 flags
= inst
.operands
[0].imm
;
9501 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9502 _("selected processor does not support "
9503 "requested special purpose register"));
9507 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9508 _("selected processor does not support "
9509 "requested special purpose register"));
9512 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9513 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
9514 inst
.instruction
|= (flags
& 0xff);
9515 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9521 if (!inst
.operands
[2].present
)
9522 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9524 /* There is no 32-bit MULS and no 16-bit MUL. */
9525 if (unified_syntax
&& inst
.instruction
== T_MNEM_mul
)
9527 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9528 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9529 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9530 inst
.instruction
|= inst
.operands
[2].reg
<< 0;
9534 constraint (!unified_syntax
9535 && inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
9536 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9539 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9540 inst
.instruction
|= inst
.operands
[0].reg
;
9542 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9543 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9544 else if (inst
.operands
[0].reg
== inst
.operands
[2].reg
)
9545 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9547 constraint (1, _("dest must overlap one source register"));
9554 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9555 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9556 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9557 inst
.instruction
|= inst
.operands
[3].reg
;
9559 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9560 as_tsktsk (_("rdhi and rdlo must be different"));
9568 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
9570 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9571 inst
.instruction
|= inst
.operands
[0].imm
;
9575 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9576 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
9581 constraint (inst
.operands
[0].present
,
9582 _("Thumb does not support NOP with hints"));
9583 inst
.instruction
= 0x46c0;
9594 if (THUMB_SETS_FLAGS (inst
.instruction
))
9595 narrow
= (current_it_mask
== 0);
9597 narrow
= (current_it_mask
!= 0);
9598 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9600 if (inst
.size_req
== 4)
9605 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9606 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9607 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9611 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9612 inst
.instruction
|= inst
.operands
[0].reg
;
9613 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9618 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9620 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9622 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9623 inst
.instruction
|= inst
.operands
[0].reg
;
9624 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9631 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9632 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9633 inst
.instruction
|= inst
.operands
[2].reg
;
9634 if (inst
.operands
[3].present
)
9636 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
9637 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9638 _("expression too complex"));
9639 inst
.instruction
|= (val
& 0x1c) << 10;
9640 inst
.instruction
|= (val
& 0x03) << 6;
9647 if (!inst
.operands
[3].present
)
9648 inst
.instruction
&= ~0x00000020;
9655 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9659 do_t_push_pop (void)
9663 constraint (inst
.operands
[0].writeback
,
9664 _("push/pop do not support {reglist}^"));
9665 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9666 _("expression too complex"));
9668 mask
= inst
.operands
[0].imm
;
9669 if ((mask
& ~0xff) == 0)
9670 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9671 else if ((inst
.instruction
== T_MNEM_push
9672 && (mask
& ~0xff) == 1 << REG_LR
)
9673 || (inst
.instruction
== T_MNEM_pop
9674 && (mask
& ~0xff) == 1 << REG_PC
))
9676 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9677 inst
.instruction
|= THUMB_PP_PC_LR
;
9680 else if (unified_syntax
)
9682 if (mask
& (1 << 13))
9683 inst
.error
= _("SP not allowed in register list");
9684 if (inst
.instruction
== T_MNEM_push
)
9686 if (mask
& (1 << 15))
9687 inst
.error
= _("PC not allowed in register list");
9691 if (mask
& (1 << 14)
9692 && mask
& (1 << 15))
9693 inst
.error
= _("LR and PC should not both be in register list");
9695 if ((mask
& (mask
- 1)) == 0)
9697 /* Single register push/pop implemented as str/ldr. */
9698 if (inst
.instruction
== T_MNEM_push
)
9699 inst
.instruction
= 0xf84d0d04; /* str reg, [sp, #-4]! */
9701 inst
.instruction
= 0xf85d0b04; /* ldr reg, [sp], #4 */
9702 mask
= ffs(mask
) - 1;
9706 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9710 inst
.error
= _("invalid register list to push/pop instruction");
9714 inst
.instruction
|= mask
;
9720 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9721 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9727 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
9728 && inst
.size_req
!= 4)
9730 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9731 inst
.instruction
|= inst
.operands
[0].reg
;
9732 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9734 else if (unified_syntax
)
9736 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9737 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9738 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9739 inst
.instruction
|= inst
.operands
[1].reg
;
9742 inst
.error
= BAD_HIREG
;
9750 Rd
= inst
.operands
[0].reg
;
9751 Rs
= (inst
.operands
[1].present
9752 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9753 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9755 inst
.instruction
|= Rd
<< 8;
9756 inst
.instruction
|= Rs
<< 16;
9757 if (!inst
.operands
[2].isreg
)
9759 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9760 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9763 encode_thumb32_shifted_operand (2);
9769 constraint (current_it_mask
, BAD_NOT_IT
);
9770 if (inst
.operands
[0].imm
)
9771 inst
.instruction
|= 0x8;
9777 if (!inst
.operands
[1].present
)
9778 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9785 switch (inst
.instruction
)
9788 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
9790 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
9792 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
9794 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
9798 if (THUMB_SETS_FLAGS (inst
.instruction
))
9799 narrow
= (current_it_mask
== 0);
9801 narrow
= (current_it_mask
!= 0);
9802 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9804 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
9806 if (inst
.operands
[2].isreg
9807 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
9808 || inst
.operands
[2].reg
> 7))
9810 if (inst
.size_req
== 4)
9815 if (inst
.operands
[2].isreg
)
9817 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9818 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9819 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9820 inst
.instruction
|= inst
.operands
[2].reg
;
9824 inst
.operands
[1].shifted
= 1;
9825 inst
.operands
[1].shift_kind
= shift_kind
;
9826 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
9827 ? T_MNEM_movs
: T_MNEM_mov
);
9828 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9829 encode_thumb32_shifted_operand (1);
9830 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
9831 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9836 if (inst
.operands
[2].isreg
)
9840 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
9841 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
9842 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
9843 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
9847 inst
.instruction
|= inst
.operands
[0].reg
;
9848 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9854 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9855 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9856 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9859 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9860 inst
.instruction
|= inst
.operands
[0].reg
;
9861 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9867 constraint (inst
.operands
[0].reg
> 7
9868 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
9869 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9871 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
9873 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
9874 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
9875 _("source1 and dest must be same register"));
9877 switch (inst
.instruction
)
9879 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
9880 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
9881 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
9882 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
9886 inst
.instruction
|= inst
.operands
[0].reg
;
9887 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9891 switch (inst
.instruction
)
9893 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9894 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9895 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9896 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
9899 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9900 inst
.instruction
|= inst
.operands
[0].reg
;
9901 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9909 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9910 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9911 inst
.instruction
|= inst
.operands
[2].reg
;
9917 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9918 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9919 _("expression too complex"));
9920 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9921 inst
.instruction
|= (value
& 0xf000) >> 12;
9922 inst
.instruction
|= (value
& 0x0ff0);
9923 inst
.instruction
|= (value
& 0x000f) << 16;
9929 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9930 inst
.instruction
|= inst
.operands
[1].imm
- 1;
9931 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9933 if (inst
.operands
[3].present
)
9935 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9936 _("expression too complex"));
9938 if (inst
.reloc
.exp
.X_add_number
!= 0)
9940 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
9941 inst
.instruction
|= 0x00200000; /* sh bit */
9942 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
9943 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
9945 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9952 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9953 inst
.instruction
|= inst
.operands
[1].imm
- 1;
9954 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9960 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9961 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9962 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9963 || inst
.operands
[2].negative
,
9966 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9967 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9968 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9969 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9975 if (!inst
.operands
[2].present
)
9976 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
9978 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9979 || inst
.operands
[0].reg
== inst
.operands
[2].reg
9980 || inst
.operands
[0].reg
== inst
.operands
[3].reg
9981 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
9984 inst
.instruction
|= inst
.operands
[0].reg
;
9985 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9986 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9987 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9993 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9994 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9995 inst
.instruction
|= inst
.operands
[2].reg
;
9996 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
10002 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
10003 && inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10004 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
10006 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10007 inst
.instruction
|= inst
.operands
[0].reg
;
10008 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10010 else if (unified_syntax
)
10012 if (inst
.instruction
<= 0xffff)
10013 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10014 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10015 inst
.instruction
|= inst
.operands
[1].reg
;
10016 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
10020 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
10021 _("Thumb encoding does not support rotation"));
10022 constraint (1, BAD_HIREG
);
10029 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
10037 half
= (inst
.instruction
& 0x10) != 0;
10038 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
10039 constraint (inst
.operands
[0].immisreg
,
10040 _("instruction requires register index"));
10041 constraint (inst
.operands
[0].imm
== 15,
10042 _("PC is not a valid index register"));
10043 constraint (!half
&& inst
.operands
[0].shifted
,
10044 _("instruction does not allow shifted index"));
10045 inst
.instruction
|= (inst
.operands
[0].reg
<< 16) | inst
.operands
[0].imm
;
10051 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10052 inst
.instruction
|= inst
.operands
[1].imm
;
10053 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10055 if (inst
.operands
[3].present
)
10057 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10058 _("expression too complex"));
10059 if (inst
.reloc
.exp
.X_add_number
!= 0)
10061 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10062 inst
.instruction
|= 0x00200000; /* sh bit */
10064 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10065 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10067 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10074 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10075 inst
.instruction
|= inst
.operands
[1].imm
;
10076 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10079 /* Neon instruction encoder helpers. */
10081 /* Encodings for the different types for various Neon opcodes. */
10083 /* An "invalid" code for the following tables. */
10086 struct neon_tab_entry
10089 unsigned float_or_poly
;
10090 unsigned scalar_or_imm
;
10093 /* Map overloaded Neon opcodes to their respective encodings. */
10094 #define NEON_ENC_TAB \
10095 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10096 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10097 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10098 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10099 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10100 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10101 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10102 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10103 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10104 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10105 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10106 /* Register variants of the following two instructions are encoded as
10107 vcge / vcgt with the operands reversed. */ \
10108 X(vclt, 0x0000310, 0x1000e00, 0x1b10200), \
10109 X(vcle, 0x0000300, 0x1200e00, 0x1b10180), \
10110 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10111 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10112 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10113 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10114 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10115 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10116 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10117 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10118 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10119 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10120 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10121 X(vshl, 0x0000400, N_INV, 0x0800510), \
10122 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10123 X(vand, 0x0000110, N_INV, 0x0800030), \
10124 X(vbic, 0x0100110, N_INV, 0x0800030), \
10125 X(veor, 0x1000110, N_INV, N_INV), \
10126 X(vorn, 0x0300110, N_INV, 0x0800010), \
10127 X(vorr, 0x0200110, N_INV, 0x0800010), \
10128 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10129 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10130 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10131 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10132 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10133 X(vst1, 0x0000000, 0x0800000, N_INV), \
10134 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10135 X(vst2, 0x0000100, 0x0800100, N_INV), \
10136 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10137 X(vst3, 0x0000200, 0x0800200, N_INV), \
10138 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10139 X(vst4, 0x0000300, 0x0800300, N_INV), \
10140 X(vmovn, 0x1b20200, N_INV, N_INV), \
10141 X(vtrn, 0x1b20080, N_INV, N_INV), \
10142 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10143 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10144 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10145 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10146 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10147 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10148 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10149 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10150 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10154 #define X(OPC,I,F,S) N_MNEM_##OPC
10159 static const struct neon_tab_entry neon_enc_tab
[] =
10161 #define X(OPC,I,F,S) { (I), (F), (S) }
10166 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10167 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10168 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10169 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10170 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10171 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10172 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10173 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10174 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10175 #define NEON_ENC_SINGLE(X) \
10176 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10177 #define NEON_ENC_DOUBLE(X) \
10178 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10180 /* Define shapes for instruction operands. The following mnemonic characters
10181 are used in this table:
10183 F - VFP S<n> register
10184 D - Neon D<n> register
10185 Q - Neon Q<n> register
10189 L - D<n> register list
10191 This table is used to generate various data:
10192 - enumerations of the form NS_DDR to be used as arguments to
10194 - a table classifying shapes into single, double, quad, mixed.
10195 - a table used to drive neon_select_shape.
10198 #define NEON_SHAPE_DEF \
10199 X(3, (D, D, D), DOUBLE), \
10200 X(3, (Q, Q, Q), QUAD), \
10201 X(3, (D, D, I), DOUBLE), \
10202 X(3, (Q, Q, I), QUAD), \
10203 X(3, (D, D, S), DOUBLE), \
10204 X(3, (Q, Q, S), QUAD), \
10205 X(2, (D, D), DOUBLE), \
10206 X(2, (Q, Q), QUAD), \
10207 X(2, (D, S), DOUBLE), \
10208 X(2, (Q, S), QUAD), \
10209 X(2, (D, R), DOUBLE), \
10210 X(2, (Q, R), QUAD), \
10211 X(2, (D, I), DOUBLE), \
10212 X(2, (Q, I), QUAD), \
10213 X(3, (D, L, D), DOUBLE), \
10214 X(2, (D, Q), MIXED), \
10215 X(2, (Q, D), MIXED), \
10216 X(3, (D, Q, I), MIXED), \
10217 X(3, (Q, D, I), MIXED), \
10218 X(3, (Q, D, D), MIXED), \
10219 X(3, (D, Q, Q), MIXED), \
10220 X(3, (Q, Q, D), MIXED), \
10221 X(3, (Q, D, S), MIXED), \
10222 X(3, (D, Q, S), MIXED), \
10223 X(4, (D, D, D, I), DOUBLE), \
10224 X(4, (Q, Q, Q, I), QUAD), \
10225 X(2, (F, F), SINGLE), \
10226 X(3, (F, F, F), SINGLE), \
10227 X(2, (F, I), SINGLE), \
10228 X(2, (F, D), MIXED), \
10229 X(2, (D, F), MIXED), \
10230 X(3, (F, F, I), MIXED), \
10231 X(4, (R, R, F, F), SINGLE), \
10232 X(4, (F, F, R, R), SINGLE), \
10233 X(3, (D, R, R), DOUBLE), \
10234 X(3, (R, R, D), DOUBLE), \
10235 X(2, (S, R), SINGLE), \
10236 X(2, (R, S), SINGLE), \
10237 X(2, (F, R), SINGLE), \
10238 X(2, (R, F), SINGLE)
10240 #define S2(A,B) NS_##A##B
10241 #define S3(A,B,C) NS_##A##B##C
10242 #define S4(A,B,C,D) NS_##A##B##C##D
10244 #define X(N, L, C) S##N L
10257 enum neon_shape_class
10265 #define X(N, L, C) SC_##C
10267 static enum neon_shape_class neon_shape_class
[] =
10285 /* Register widths of above. */
10286 static unsigned neon_shape_el_size
[] =
10297 struct neon_shape_info
10300 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
10303 #define S2(A,B) { SE_##A, SE_##B }
10304 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10305 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10307 #define X(N, L, C) { N, S##N L }
10309 static struct neon_shape_info neon_shape_tab
[] =
10319 /* Bit masks used in type checking given instructions.
10320 'N_EQK' means the type must be the same as (or based on in some way) the key
10321 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10322 set, various other bits can be set as well in order to modify the meaning of
10323 the type constraint. */
10325 enum neon_type_mask
10347 N_KEY
= 0x100000, /* key element (main type specifier). */
10348 N_EQK
= 0x200000, /* given operand has the same type & size as the key. */
10349 N_VFP
= 0x400000, /* VFP mode: operand size must match register width. */
10350 N_DBL
= 0x000001, /* if N_EQK, this operand is twice the size. */
10351 N_HLF
= 0x000002, /* if N_EQK, this operand is half the size. */
10352 N_SGN
= 0x000004, /* if N_EQK, this operand is forced to be signed. */
10353 N_UNS
= 0x000008, /* if N_EQK, this operand is forced to be unsigned. */
10354 N_INT
= 0x000010, /* if N_EQK, this operand is forced to be integer. */
10355 N_FLT
= 0x000020, /* if N_EQK, this operand is forced to be float. */
10356 N_SIZ
= 0x000040, /* if N_EQK, this operand is forced to be size-only. */
10358 N_MAX_NONSPECIAL
= N_F64
10361 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10363 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10364 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10365 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10366 #define N_SUF_32 (N_SU_32 | N_F32)
10367 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10368 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10370 /* Pass this as the first type argument to neon_check_type to ignore types
10372 #define N_IGNORE_TYPE (N_KEY | N_EQK)
10374 /* Select a "shape" for the current instruction (describing register types or
10375 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10376 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10377 function of operand parsing, so this function doesn't need to be called.
10378 Shapes should be listed in order of decreasing length. */
10380 static enum neon_shape
10381 neon_select_shape (enum neon_shape shape
, ...)
10384 enum neon_shape first_shape
= shape
;
10386 /* Fix missing optional operands. FIXME: we don't know at this point how
10387 many arguments we should have, so this makes the assumption that we have
10388 > 1. This is true of all current Neon opcodes, I think, but may not be
10389 true in the future. */
10390 if (!inst
.operands
[1].present
)
10391 inst
.operands
[1] = inst
.operands
[0];
10393 va_start (ap
, shape
);
10395 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
10400 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
10402 if (!inst
.operands
[j
].present
)
10408 switch (neon_shape_tab
[shape
].el
[j
])
10411 if (!(inst
.operands
[j
].isreg
10412 && inst
.operands
[j
].isvec
10413 && inst
.operands
[j
].issingle
10414 && !inst
.operands
[j
].isquad
))
10419 if (!(inst
.operands
[j
].isreg
10420 && inst
.operands
[j
].isvec
10421 && !inst
.operands
[j
].isquad
10422 && !inst
.operands
[j
].issingle
))
10427 if (!(inst
.operands
[j
].isreg
10428 && !inst
.operands
[j
].isvec
))
10433 if (!(inst
.operands
[j
].isreg
10434 && inst
.operands
[j
].isvec
10435 && inst
.operands
[j
].isquad
10436 && !inst
.operands
[j
].issingle
))
10441 if (!(!inst
.operands
[j
].isreg
10442 && !inst
.operands
[j
].isscalar
))
10447 if (!(!inst
.operands
[j
].isreg
10448 && inst
.operands
[j
].isscalar
))
10462 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
10463 first_error (_("invalid instruction shape"));
10468 /* True if SHAPE is predominantly a quadword operation (most of the time, this
10469 means the Q bit should be set). */
10472 neon_quad (enum neon_shape shape
)
10474 return neon_shape_class
[shape
] == SC_QUAD
;
10478 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
10481 /* Allow modification to be made to types which are constrained to be
10482 based on the key element, based on bits set alongside N_EQK. */
10483 if ((typebits
& N_EQK
) != 0)
10485 if ((typebits
& N_HLF
) != 0)
10487 else if ((typebits
& N_DBL
) != 0)
10489 if ((typebits
& N_SGN
) != 0)
10490 *g_type
= NT_signed
;
10491 else if ((typebits
& N_UNS
) != 0)
10492 *g_type
= NT_unsigned
;
10493 else if ((typebits
& N_INT
) != 0)
10494 *g_type
= NT_integer
;
10495 else if ((typebits
& N_FLT
) != 0)
10496 *g_type
= NT_float
;
10497 else if ((typebits
& N_SIZ
) != 0)
10498 *g_type
= NT_untyped
;
10502 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10503 operand type, i.e. the single type specified in a Neon instruction when it
10504 is the only one given. */
10506 static struct neon_type_el
10507 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
10509 struct neon_type_el dest
= *key
;
10511 assert ((thisarg
& N_EQK
) != 0);
10513 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
10518 /* Convert Neon type and size into compact bitmask representation. */
10520 static enum neon_type_mask
10521 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
10528 case 8: return N_8
;
10529 case 16: return N_16
;
10530 case 32: return N_32
;
10531 case 64: return N_64
;
10539 case 8: return N_I8
;
10540 case 16: return N_I16
;
10541 case 32: return N_I32
;
10542 case 64: return N_I64
;
10550 case 32: return N_F32
;
10551 case 64: return N_F64
;
10559 case 8: return N_P8
;
10560 case 16: return N_P16
;
10568 case 8: return N_S8
;
10569 case 16: return N_S16
;
10570 case 32: return N_S32
;
10571 case 64: return N_S64
;
10579 case 8: return N_U8
;
10580 case 16: return N_U16
;
10581 case 32: return N_U32
;
10582 case 64: return N_U64
;
10593 /* Convert compact Neon bitmask type representation to a type and size. Only
10594 handles the case where a single bit is set in the mask. */
10597 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
10598 enum neon_type_mask mask
)
10600 if ((mask
& N_EQK
) != 0)
10603 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
10605 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
10607 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
10609 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
10614 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
10616 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
10617 *type
= NT_unsigned
;
10618 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
10619 *type
= NT_integer
;
10620 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
10621 *type
= NT_untyped
;
10622 else if ((mask
& (N_P8
| N_P16
)) != 0)
10624 else if ((mask
& (N_F32
| N_F64
)) != 0)
10632 /* Modify a bitmask of allowed types. This is only needed for type
10636 modify_types_allowed (unsigned allowed
, unsigned mods
)
10639 enum neon_el_type type
;
10645 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
10647 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
10649 neon_modify_type_size (mods
, &type
, &size
);
10650 destmask
|= type_chk_of_el_type (type
, size
);
10657 /* Check type and return type classification.
10658 The manual states (paraphrase): If one datatype is given, it indicates the
10660 - the second operand, if there is one
10661 - the operand, if there is no second operand
10662 - the result, if there are no operands.
10663 This isn't quite good enough though, so we use a concept of a "key" datatype
10664 which is set on a per-instruction basis, which is the one which matters when
10665 only one data type is written.
10666 Note: this function has side-effects (e.g. filling in missing operands). All
10667 Neon instructions should call it before performing bit encoding. */
10669 static struct neon_type_el
10670 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
10673 unsigned i
, pass
, key_el
= 0;
10674 unsigned types
[NEON_MAX_TYPE_ELS
];
10675 enum neon_el_type k_type
= NT_invtype
;
10676 unsigned k_size
= -1u;
10677 struct neon_type_el badtype
= {NT_invtype
, -1};
10678 unsigned key_allowed
= 0;
10680 /* Optional registers in Neon instructions are always (not) in operand 1.
10681 Fill in the missing operand here, if it was omitted. */
10682 if (els
> 1 && !inst
.operands
[1].present
)
10683 inst
.operands
[1] = inst
.operands
[0];
10685 /* Suck up all the varargs. */
10687 for (i
= 0; i
< els
; i
++)
10689 unsigned thisarg
= va_arg (ap
, unsigned);
10690 if (thisarg
== N_IGNORE_TYPE
)
10695 types
[i
] = thisarg
;
10696 if ((thisarg
& N_KEY
) != 0)
10701 if (inst
.vectype
.elems
> 0)
10702 for (i
= 0; i
< els
; i
++)
10703 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
10705 first_error (_("types specified in both the mnemonic and operands"));
10709 /* Duplicate inst.vectype elements here as necessary.
10710 FIXME: No idea if this is exactly the same as the ARM assembler,
10711 particularly when an insn takes one register and one non-register
10713 if (inst
.vectype
.elems
== 1 && els
> 1)
10716 inst
.vectype
.elems
= els
;
10717 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
10718 for (j
= 0; j
< els
; j
++)
10720 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
10723 else if (inst
.vectype
.elems
== 0 && els
> 0)
10726 /* No types were given after the mnemonic, so look for types specified
10727 after each operand. We allow some flexibility here; as long as the
10728 "key" operand has a type, we can infer the others. */
10729 for (j
= 0; j
< els
; j
++)
10730 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
10731 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
10733 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
10735 for (j
= 0; j
< els
; j
++)
10736 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
10737 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
10742 first_error (_("operand types can't be inferred"));
10746 else if (inst
.vectype
.elems
!= els
)
10748 first_error (_("type specifier has the wrong number of parts"));
10752 for (pass
= 0; pass
< 2; pass
++)
10754 for (i
= 0; i
< els
; i
++)
10756 unsigned thisarg
= types
[i
];
10757 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
10758 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
10759 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
10760 unsigned g_size
= inst
.vectype
.el
[i
].size
;
10762 /* Decay more-specific signed & unsigned types to sign-insensitive
10763 integer types if sign-specific variants are unavailable. */
10764 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
10765 && (types_allowed
& N_SU_ALL
) == 0)
10766 g_type
= NT_integer
;
10768 /* If only untyped args are allowed, decay any more specific types to
10769 them. Some instructions only care about signs for some element
10770 sizes, so handle that properly. */
10771 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
10772 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
10773 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
10774 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
10775 g_type
= NT_untyped
;
10779 if ((thisarg
& N_KEY
) != 0)
10783 key_allowed
= thisarg
& ~N_KEY
;
10788 if ((thisarg
& N_VFP
) != 0)
10790 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
10791 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
10793 /* In VFP mode, operands must match register widths. If we
10794 have a key operand, use its width, else use the width of
10795 the current operand. */
10801 if (regwidth
!= match
)
10803 first_error (_("operand size must match register width"));
10808 if ((thisarg
& N_EQK
) == 0)
10810 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
10812 if ((given_type
& types_allowed
) == 0)
10814 first_error (_("bad type in Neon instruction"));
10820 enum neon_el_type mod_k_type
= k_type
;
10821 unsigned mod_k_size
= k_size
;
10822 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
10823 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
10825 first_error (_("inconsistent types in Neon instruction"));
10833 return inst
.vectype
.el
[key_el
];
10836 /* Neon-style VFP instruction forwarding. */
10838 /* Thumb VFP instructions have 0xE in the condition field. */
10841 do_vfp_cond_or_thumb (void)
10844 inst
.instruction
|= 0xe0000000;
10846 inst
.instruction
|= inst
.cond
<< 28;
10849 /* Look up and encode a simple mnemonic, for use as a helper function for the
10850 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
10851 etc. It is assumed that operand parsing has already been done, and that the
10852 operands are in the form expected by the given opcode (this isn't necessarily
10853 the same as the form in which they were parsed, hence some massaging must
10854 take place before this function is called).
10855 Checks current arch version against that in the looked-up opcode. */
10858 do_vfp_nsyn_opcode (const char *opname
)
10860 const struct asm_opcode
*opcode
;
10862 opcode
= hash_find (arm_ops_hsh
, opname
);
10867 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
10868 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
10873 inst
.instruction
= opcode
->tvalue
;
10874 opcode
->tencode ();
10878 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
10879 opcode
->aencode ();
10884 do_vfp_nsyn_add_sub (enum neon_shape rs
)
10886 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
10891 do_vfp_nsyn_opcode ("fadds");
10893 do_vfp_nsyn_opcode ("fsubs");
10898 do_vfp_nsyn_opcode ("faddd");
10900 do_vfp_nsyn_opcode ("fsubd");
10904 /* Check operand types to see if this is a VFP instruction, and if so call
10908 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
10910 enum neon_shape rs
;
10911 struct neon_type_el et
;
10916 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
10917 et
= neon_check_type (2, rs
,
10918 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
10922 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
10923 et
= neon_check_type (3, rs
,
10924 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
10931 if (et
.type
!= NT_invtype
)
10943 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
10945 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
10950 do_vfp_nsyn_opcode ("fmacs");
10952 do_vfp_nsyn_opcode ("fmscs");
10957 do_vfp_nsyn_opcode ("fmacd");
10959 do_vfp_nsyn_opcode ("fmscd");
10964 do_vfp_nsyn_mul (enum neon_shape rs
)
10967 do_vfp_nsyn_opcode ("fmuls");
10969 do_vfp_nsyn_opcode ("fmuld");
10973 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
10975 int is_neg
= (inst
.instruction
& 0x80) != 0;
10976 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
10981 do_vfp_nsyn_opcode ("fnegs");
10983 do_vfp_nsyn_opcode ("fabss");
10988 do_vfp_nsyn_opcode ("fnegd");
10990 do_vfp_nsyn_opcode ("fabsd");
10994 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
10995 insns belong to Neon, and are handled elsewhere. */
10998 do_vfp_nsyn_ldm_stm (int is_dbmode
)
11000 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
11004 do_vfp_nsyn_opcode ("fldmdbs");
11006 do_vfp_nsyn_opcode ("fldmias");
11011 do_vfp_nsyn_opcode ("fstmdbs");
11013 do_vfp_nsyn_opcode ("fstmias");
11018 do_vfp_nsyn_sqrt (void)
11020 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11021 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11024 do_vfp_nsyn_opcode ("fsqrts");
11026 do_vfp_nsyn_opcode ("fsqrtd");
11030 do_vfp_nsyn_div (void)
11032 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11033 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11034 N_F32
| N_F64
| N_KEY
| N_VFP
);
11037 do_vfp_nsyn_opcode ("fdivs");
11039 do_vfp_nsyn_opcode ("fdivd");
11043 do_vfp_nsyn_nmul (void)
11045 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11046 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11047 N_F32
| N_F64
| N_KEY
| N_VFP
);
11051 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11052 do_vfp_sp_dyadic ();
11056 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11057 do_vfp_dp_rd_rn_rm ();
11059 do_vfp_cond_or_thumb ();
11063 do_vfp_nsyn_cmp (void)
11065 if (inst
.operands
[1].isreg
)
11067 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11068 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11072 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11073 do_vfp_sp_monadic ();
11077 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11078 do_vfp_dp_rd_rm ();
11083 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
11084 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
11086 switch (inst
.instruction
& 0x0fffffff)
11089 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
11092 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
11100 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11101 do_vfp_sp_compare_z ();
11105 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11109 do_vfp_cond_or_thumb ();
11113 nsyn_insert_sp (void)
11115 inst
.operands
[1] = inst
.operands
[0];
11116 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
11117 inst
.operands
[0].reg
= 13;
11118 inst
.operands
[0].isreg
= 1;
11119 inst
.operands
[0].writeback
= 1;
11120 inst
.operands
[0].present
= 1;
11124 do_vfp_nsyn_push (void)
11127 if (inst
.operands
[1].issingle
)
11128 do_vfp_nsyn_opcode ("fstmdbs");
11130 do_vfp_nsyn_opcode ("fstmdbd");
11134 do_vfp_nsyn_pop (void)
11137 if (inst
.operands
[1].issingle
)
11138 do_vfp_nsyn_opcode ("fldmdbs");
11140 do_vfp_nsyn_opcode ("fldmdbd");
11143 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11144 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11147 neon_dp_fixup (unsigned i
)
11151 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11165 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11169 neon_logbits (unsigned x
)
11171 return ffs (x
) - 4;
11174 #define LOW4(R) ((R) & 0xf)
11175 #define HI1(R) (((R) >> 4) & 1)
11177 /* Encode insns with bit pattern:
11179 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11180 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11182 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11183 different meaning for some instruction. */
11186 neon_three_same (int isquad
, int ubit
, int size
)
11188 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11189 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11190 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11191 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11192 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
11193 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
11194 inst
.instruction
|= (isquad
!= 0) << 6;
11195 inst
.instruction
|= (ubit
!= 0) << 24;
11197 inst
.instruction
|= neon_logbits (size
) << 20;
11199 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11202 /* Encode instructions of the form:
11204 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11205 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11207 Don't write size if SIZE == -1. */
11210 neon_two_same (int qbit
, int ubit
, int size
)
11212 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11213 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11214 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11215 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11216 inst
.instruction
|= (qbit
!= 0) << 6;
11217 inst
.instruction
|= (ubit
!= 0) << 24;
11220 inst
.instruction
|= neon_logbits (size
) << 18;
11222 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11225 /* Neon instruction encoders, in approximate order of appearance. */
11228 do_neon_dyadic_i_su (void)
11230 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11231 struct neon_type_el et
= neon_check_type (3, rs
,
11232 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
11233 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11237 do_neon_dyadic_i64_su (void)
11239 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11240 struct neon_type_el et
= neon_check_type (3, rs
,
11241 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11242 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11246 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
11249 unsigned size
= et
.size
>> 3;
11250 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11251 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11252 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11253 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11254 inst
.instruction
|= (isquad
!= 0) << 6;
11255 inst
.instruction
|= immbits
<< 16;
11256 inst
.instruction
|= (size
>> 3) << 7;
11257 inst
.instruction
|= (size
& 0x7) << 19;
11259 inst
.instruction
|= (uval
!= 0) << 24;
11261 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11265 do_neon_shl_imm (void)
11267 if (!inst
.operands
[2].isreg
)
11269 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11270 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
11271 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11272 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
11276 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11277 struct neon_type_el et
= neon_check_type (3, rs
,
11278 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11279 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11280 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11285 do_neon_qshl_imm (void)
11287 if (!inst
.operands
[2].isreg
)
11289 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11290 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
11291 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11292 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
11293 inst
.operands
[2].imm
);
11297 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11298 struct neon_type_el et
= neon_check_type (3, rs
,
11299 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11300 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11301 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11306 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
11308 /* Handle .I8 and .I64 as pseudo-instructions. */
11312 /* Unfortunately, this will make everything apart from zero out-of-range.
11313 FIXME is this the intended semantics? There doesn't seem much point in
11314 accepting .I8 if so. */
11315 immediate
|= immediate
<< 8;
11319 /* Similarly, anything other than zero will be replicated in bits [63:32],
11320 which probably isn't want we want if we specified .I64. */
11321 if (immediate
!= 0)
11322 goto bad_immediate
;
11328 if (immediate
== (immediate
& 0x000000ff))
11330 *immbits
= immediate
;
11331 return (size
== 16) ? 0x9 : 0x1;
11333 else if (immediate
== (immediate
& 0x0000ff00))
11335 *immbits
= immediate
>> 8;
11336 return (size
== 16) ? 0xb : 0x3;
11338 else if (immediate
== (immediate
& 0x00ff0000))
11340 *immbits
= immediate
>> 16;
11343 else if (immediate
== (immediate
& 0xff000000))
11345 *immbits
= immediate
>> 24;
11350 first_error (_("immediate value out of range"));
11354 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11358 neon_bits_same_in_bytes (unsigned imm
)
11360 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
11361 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
11362 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
11363 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
11366 /* For immediate of above form, return 0bABCD. */
11369 neon_squash_bits (unsigned imm
)
11371 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
11372 | ((imm
& 0x01000000) >> 21);
11375 /* Compress quarter-float representation to 0b...000 abcdefgh. */
11378 neon_qfloat_bits (unsigned imm
)
11380 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
11383 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11384 the instruction. *OP is passed as the initial value of the op field, and
11385 may be set to a different value depending on the constant (i.e.
11386 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11390 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, unsigned *immbits
,
11391 int *op
, int size
, enum neon_el_type type
)
11393 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
11395 if (size
!= 32 || *op
== 1)
11397 *immbits
= neon_qfloat_bits (immlo
);
11400 else if (size
== 64 && neon_bits_same_in_bytes (immhi
)
11401 && neon_bits_same_in_bytes (immlo
))
11403 /* Check this one first so we don't have to bother with immhi in later
11407 *immbits
= (neon_squash_bits (immhi
) << 4) | neon_squash_bits (immlo
);
11411 else if (immhi
!= 0)
11413 else if (immlo
== (immlo
& 0x000000ff))
11415 /* 64-bit case was already handled. Don't allow MVN with 8-bit
11417 if ((size
!= 8 && size
!= 16 && size
!= 32)
11418 || (size
== 8 && *op
== 1))
11421 return (size
== 8) ? 0xe : (size
== 16) ? 0x8 : 0x0;
11423 else if (immlo
== (immlo
& 0x0000ff00))
11425 if (size
!= 16 && size
!= 32)
11427 *immbits
= immlo
>> 8;
11428 return (size
== 16) ? 0xa : 0x2;
11430 else if (immlo
== (immlo
& 0x00ff0000))
11434 *immbits
= immlo
>> 16;
11437 else if (immlo
== (immlo
& 0xff000000))
11441 *immbits
= immlo
>> 24;
11444 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
11448 *immbits
= (immlo
>> 8) & 0xff;
11451 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
11455 *immbits
= (immlo
>> 16) & 0xff;
11462 /* Write immediate bits [7:0] to the following locations:
11464 |28/24|23 19|18 16|15 4|3 0|
11465 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11467 This function is used by VMOV/VMVN/VORR/VBIC. */
11470 neon_write_immbits (unsigned immbits
)
11472 inst
.instruction
|= immbits
& 0xf;
11473 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
11474 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
11477 /* Invert low-order SIZE bits of XHI:XLO. */
11480 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
11482 unsigned immlo
= xlo
? *xlo
: 0;
11483 unsigned immhi
= xhi
? *xhi
: 0;
11488 immlo
= (~immlo
) & 0xff;
11492 immlo
= (~immlo
) & 0xffff;
11496 immhi
= (~immhi
) & 0xffffffff;
11497 /* fall through. */
11500 immlo
= (~immlo
) & 0xffffffff;
11515 do_neon_logic (void)
11517 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
11519 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11520 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11521 /* U bit and size field were set as part of the bitmask. */
11522 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11523 neon_three_same (neon_quad (rs
), 0, -1);
11527 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
11528 struct neon_type_el et
= neon_check_type (2, rs
,
11529 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
11530 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
11534 if (et
.type
== NT_invtype
)
11537 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11542 cmode
= neon_cmode_for_logic_imm (inst
.operands
[1].imm
, &immbits
,
11547 cmode
= neon_cmode_for_logic_imm (inst
.operands
[1].imm
, &immbits
,
11552 /* Pseudo-instruction for VBIC. */
11553 immbits
= inst
.operands
[1].imm
;
11554 neon_invert_size (&immbits
, 0, et
.size
);
11555 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11559 /* Pseudo-instruction for VORR. */
11560 immbits
= inst
.operands
[1].imm
;
11561 neon_invert_size (&immbits
, 0, et
.size
);
11562 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11572 inst
.instruction
|= neon_quad (rs
) << 6;
11573 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11574 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11575 inst
.instruction
|= cmode
<< 8;
11576 neon_write_immbits (immbits
);
11578 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11583 do_neon_bitfield (void)
11585 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11586 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11587 neon_three_same (neon_quad (rs
), 0, -1);
11591 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
11594 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11595 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
11597 if (et
.type
== NT_float
)
11599 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
11600 neon_three_same (neon_quad (rs
), 0, -1);
11604 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11605 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
11610 do_neon_dyadic_if_su (void)
11612 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
11616 do_neon_dyadic_if_su_d (void)
11618 /* This version only allow D registers, but that constraint is enforced during
11619 operand parsing so we don't need to do anything extra here. */
11620 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
11624 do_neon_dyadic_if_i_d (void)
11626 /* The "untyped" case can't happen. Do this to stop the "U" bit being
11627 affected if we specify unsigned args. */
11628 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
11631 enum vfp_or_neon_is_neon_bits
11634 NEON_CHECK_ARCH
= 2
11637 /* Call this function if an instruction which may have belonged to the VFP or
11638 Neon instruction sets, but turned out to be a Neon instruction (due to the
11639 operand types involved, etc.). We have to check and/or fix-up a couple of
11642 - Make sure the user hasn't attempted to make a Neon instruction
11644 - Alter the value in the condition code field if necessary.
11645 - Make sure that the arch supports Neon instructions.
11647 Which of these operations take place depends on bits from enum
11648 vfp_or_neon_is_neon_bits.
11650 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
11651 current instruction's condition is COND_ALWAYS, the condition field is
11652 changed to inst.uncond_value. This is necessary because instructions shared
11653 between VFP and Neon may be conditional for the VFP variants only, and the
11654 unconditional Neon version must have, e.g., 0xF in the condition field. */
11657 vfp_or_neon_is_neon (unsigned check
)
11659 /* Conditions are always legal in Thumb mode (IT blocks). */
11660 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
11662 if (inst
.cond
!= COND_ALWAYS
)
11664 first_error (_(BAD_COND
));
11667 if (inst
.uncond_value
!= -1)
11668 inst
.instruction
|= inst
.uncond_value
<< 28;
11671 if ((check
& NEON_CHECK_ARCH
)
11672 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
11674 first_error (_(BAD_FPU
));
11682 do_neon_addsub_if_i (void)
11684 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
11687 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11690 /* The "untyped" case can't happen. Do this to stop the "U" bit being
11691 affected if we specify unsigned args. */
11692 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
11695 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
11697 V<op> A,B (A is operand 0, B is operand 2)
11702 so handle that case specially. */
11705 neon_exchange_operands (void)
11707 void *scratch
= alloca (sizeof (inst
.operands
[0]));
11708 if (inst
.operands
[1].present
)
11710 /* Swap operands[1] and operands[2]. */
11711 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
11712 inst
.operands
[1] = inst
.operands
[2];
11713 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
11717 inst
.operands
[1] = inst
.operands
[2];
11718 inst
.operands
[2] = inst
.operands
[0];
11723 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
11725 if (inst
.operands
[2].isreg
)
11728 neon_exchange_operands ();
11729 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
11733 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11734 struct neon_type_el et
= neon_check_type (2, rs
,
11735 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
11737 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11738 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11739 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11740 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11741 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11742 inst
.instruction
|= neon_quad (rs
) << 6;
11743 inst
.instruction
|= (et
.type
== NT_float
) << 10;
11744 inst
.instruction
|= neon_logbits (et
.size
) << 18;
11746 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11753 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
11757 do_neon_cmp_inv (void)
11759 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
11765 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
11768 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
11769 scalars, which are encoded in 5 bits, M : Rm.
11770 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
11771 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
11775 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
11777 unsigned regno
= NEON_SCALAR_REG (scalar
);
11778 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
11783 if (regno
> 7 || elno
> 3)
11785 return regno
| (elno
<< 3);
11788 if (regno
> 15 || elno
> 1)
11790 return regno
| (elno
<< 4);
11794 first_error (_("scalar out of range for multiply instruction"));
11800 /* Encode multiply / multiply-accumulate scalar instructions. */
11803 neon_mul_mac (struct neon_type_el et
, int ubit
)
11807 /* Give a more helpful error message if we have an invalid type. */
11808 if (et
.type
== NT_invtype
)
11811 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
11812 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11813 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11814 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11815 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11816 inst
.instruction
|= LOW4 (scalar
);
11817 inst
.instruction
|= HI1 (scalar
) << 5;
11818 inst
.instruction
|= (et
.type
== NT_float
) << 8;
11819 inst
.instruction
|= neon_logbits (et
.size
) << 20;
11820 inst
.instruction
|= (ubit
!= 0) << 24;
11822 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11826 do_neon_mac_maybe_scalar (void)
11828 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
11831 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11834 if (inst
.operands
[2].isscalar
)
11836 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
11837 struct neon_type_el et
= neon_check_type (3, rs
,
11838 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
11839 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
11840 neon_mul_mac (et
, neon_quad (rs
));
11844 /* The "untyped" case can't happen. Do this to stop the "U" bit being
11845 affected if we specify unsigned args. */
11846 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
11853 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11854 struct neon_type_el et
= neon_check_type (3, rs
,
11855 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
11856 neon_three_same (neon_quad (rs
), 0, et
.size
);
11859 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
11860 same types as the MAC equivalents. The polynomial type for this instruction
11861 is encoded the same as the integer type. */
11866 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
11869 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11872 if (inst
.operands
[2].isscalar
)
11873 do_neon_mac_maybe_scalar ();
11875 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
11879 do_neon_qdmulh (void)
11881 if (inst
.operands
[2].isscalar
)
11883 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
11884 struct neon_type_el et
= neon_check_type (3, rs
,
11885 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
11886 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
11887 neon_mul_mac (et
, neon_quad (rs
));
11891 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11892 struct neon_type_el et
= neon_check_type (3, rs
,
11893 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
11894 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11895 /* The U bit (rounding) comes from bit mask. */
11896 neon_three_same (neon_quad (rs
), 0, et
.size
);
11901 do_neon_fcmp_absolute (void)
11903 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11904 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
11905 /* Size field comes from bit mask. */
11906 neon_three_same (neon_quad (rs
), 1, -1);
11910 do_neon_fcmp_absolute_inv (void)
11912 neon_exchange_operands ();
11913 do_neon_fcmp_absolute ();
11917 do_neon_step (void)
11919 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11920 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
11921 neon_three_same (neon_quad (rs
), 0, -1);
11925 do_neon_abs_neg (void)
11927 enum neon_shape rs
;
11928 struct neon_type_el et
;
11930 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
11933 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11936 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
11937 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
11939 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11940 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11941 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11942 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11943 inst
.instruction
|= neon_quad (rs
) << 6;
11944 inst
.instruction
|= (et
.type
== NT_float
) << 10;
11945 inst
.instruction
|= neon_logbits (et
.size
) << 18;
11947 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11953 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11954 struct neon_type_el et
= neon_check_type (2, rs
,
11955 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
11956 int imm
= inst
.operands
[2].imm
;
11957 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
11958 _("immediate out of range for insert"));
11959 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
11965 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11966 struct neon_type_el et
= neon_check_type (2, rs
,
11967 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
11968 int imm
= inst
.operands
[2].imm
;
11969 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
11970 _("immediate out of range for insert"));
11971 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
11975 do_neon_qshlu_imm (void)
11977 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11978 struct neon_type_el et
= neon_check_type (2, rs
,
11979 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
11980 int imm
= inst
.operands
[2].imm
;
11981 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
11982 _("immediate out of range for shift"));
11983 /* Only encodes the 'U present' variant of the instruction.
11984 In this case, signed types have OP (bit 8) set to 0.
11985 Unsigned types have OP set to 1. */
11986 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
11987 /* The rest of the bits are the same as other immediate shifts. */
11988 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
11992 do_neon_qmovn (void)
11994 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
11995 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
11996 /* Saturating move where operands can be signed or unsigned, and the
11997 destination has the same signedness. */
11998 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11999 if (et
.type
== NT_unsigned
)
12000 inst
.instruction
|= 0xc0;
12002 inst
.instruction
|= 0x80;
12003 neon_two_same (0, 1, et
.size
/ 2);
12007 do_neon_qmovun (void)
12009 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12010 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12011 /* Saturating move with unsigned results. Operands must be signed. */
12012 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12013 neon_two_same (0, 1, et
.size
/ 2);
12017 do_neon_rshift_sat_narrow (void)
12019 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12020 or unsigned. If operands are unsigned, results must also be unsigned. */
12021 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12022 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12023 int imm
= inst
.operands
[2].imm
;
12024 /* This gets the bounds check, size encoding and immediate bits calculation
12028 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12029 VQMOVN.I<size> <Dd>, <Qm>. */
12032 inst
.operands
[2].present
= 0;
12033 inst
.instruction
= N_MNEM_vqmovn
;
12038 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12039 _("immediate out of range"));
12040 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
12044 do_neon_rshift_sat_narrow_u (void)
12046 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12047 or unsigned. If operands are unsigned, results must also be unsigned. */
12048 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12049 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12050 int imm
= inst
.operands
[2].imm
;
12051 /* This gets the bounds check, size encoding and immediate bits calculation
12055 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12056 VQMOVUN.I<size> <Dd>, <Qm>. */
12059 inst
.operands
[2].present
= 0;
12060 inst
.instruction
= N_MNEM_vqmovun
;
12065 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12066 _("immediate out of range"));
12067 /* FIXME: The manual is kind of unclear about what value U should have in
12068 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12070 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
12074 do_neon_movn (void)
12076 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12077 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12078 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12079 neon_two_same (0, 1, et
.size
/ 2);
12083 do_neon_rshift_narrow (void)
12085 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12086 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12087 int imm
= inst
.operands
[2].imm
;
12088 /* This gets the bounds check, size encoding and immediate bits calculation
12092 /* If immediate is zero then we are a pseudo-instruction for
12093 VMOVN.I<size> <Dd>, <Qm> */
12096 inst
.operands
[2].present
= 0;
12097 inst
.instruction
= N_MNEM_vmovn
;
12102 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12103 _("immediate out of range for narrowing operation"));
12104 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
12108 do_neon_shll (void)
12110 /* FIXME: Type checking when lengthening. */
12111 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
12112 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
12113 unsigned imm
= inst
.operands
[2].imm
;
12115 if (imm
== et
.size
)
12117 /* Maximum shift variant. */
12118 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12119 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12120 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12121 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12122 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12123 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12125 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12129 /* A more-specific type check for non-max versions. */
12130 et
= neon_check_type (2, NS_QDI
,
12131 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12132 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12133 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
12137 /* Check the various types for the VCVT instruction, and return which version
12138 the current instruction is. */
12141 neon_cvt_flavour (enum neon_shape rs
)
12143 #define CVT_VAR(C,X,Y) \
12144 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12145 if (et.type != NT_invtype) \
12147 inst.error = NULL; \
12150 struct neon_type_el et
;
12151 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
12152 || rs
== NS_FF
) ? N_VFP
: 0;
12153 /* The instruction versions which take an immediate take one register
12154 argument, which is extended to the width of the full register. Thus the
12155 "source" and "destination" registers must have the same width. Hack that
12156 here by making the size equal to the key (wider, in this case) operand. */
12157 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
12159 CVT_VAR (0, N_S32
, N_F32
);
12160 CVT_VAR (1, N_U32
, N_F32
);
12161 CVT_VAR (2, N_F32
, N_S32
);
12162 CVT_VAR (3, N_F32
, N_U32
);
12166 /* VFP instructions. */
12167 CVT_VAR (4, N_F32
, N_F64
);
12168 CVT_VAR (5, N_F64
, N_F32
);
12169 CVT_VAR (6, N_S32
, N_F64
| key
);
12170 CVT_VAR (7, N_U32
, N_F64
| key
);
12171 CVT_VAR (8, N_F64
| key
, N_S32
);
12172 CVT_VAR (9, N_F64
| key
, N_U32
);
12173 /* VFP instructions with bitshift. */
12174 CVT_VAR (10, N_F32
| key
, N_S16
);
12175 CVT_VAR (11, N_F32
| key
, N_U16
);
12176 CVT_VAR (12, N_F64
| key
, N_S16
);
12177 CVT_VAR (13, N_F64
| key
, N_U16
);
12178 CVT_VAR (14, N_S16
, N_F32
| key
);
12179 CVT_VAR (15, N_U16
, N_F32
| key
);
12180 CVT_VAR (16, N_S16
, N_F64
| key
);
12181 CVT_VAR (17, N_U16
, N_F64
| key
);
12187 /* Neon-syntax VFP conversions. */
12190 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
12192 const char *opname
= 0;
12194 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
12196 /* Conversions with immediate bitshift. */
12197 const char *enc
[] =
12219 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12221 opname
= enc
[flavour
];
12222 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12223 _("operands 0 and 1 must be the same register"));
12224 inst
.operands
[1] = inst
.operands
[2];
12225 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
12230 /* Conversions without bitshift. */
12231 const char *enc
[] =
12245 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12246 opname
= enc
[flavour
];
12250 do_vfp_nsyn_opcode (opname
);
12254 do_vfp_nsyn_cvtz (void)
12256 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
12257 int flavour
= neon_cvt_flavour (rs
);
12258 const char *enc
[] =
12270 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
12271 do_vfp_nsyn_opcode (enc
[flavour
]);
12277 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
12278 NS_FD
, NS_DF
, NS_FF
, NS_NULL
);
12279 int flavour
= neon_cvt_flavour (rs
);
12281 /* VFP rather than Neon conversions. */
12284 do_vfp_nsyn_cvt (rs
, flavour
);
12293 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12296 /* Fixed-point conversion with #0 immediate is encoded as an
12297 integer conversion. */
12298 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
12300 unsigned immbits
= 32 - inst
.operands
[2].imm
;
12301 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12302 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12304 inst
.instruction
|= enctab
[flavour
];
12305 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12306 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12307 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12308 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12309 inst
.instruction
|= neon_quad (rs
) << 6;
12310 inst
.instruction
|= 1 << 21;
12311 inst
.instruction
|= immbits
<< 16;
12313 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12321 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
12323 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12325 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12329 inst
.instruction
|= enctab
[flavour
];
12331 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12332 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12333 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12334 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12335 inst
.instruction
|= neon_quad (rs
) << 6;
12336 inst
.instruction
|= 2 << 18;
12338 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12343 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12344 do_vfp_nsyn_cvt (rs
, flavour
);
12349 neon_move_immediate (void)
12351 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12352 struct neon_type_el et
= neon_check_type (2, rs
,
12353 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12354 unsigned immlo
, immhi
= 0, immbits
;
12357 constraint (et
.type
== NT_invtype
,
12358 _("operand size must be specified for immediate VMOV"));
12360 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12361 op
= (inst
.instruction
& (1 << 5)) != 0;
12363 immlo
= inst
.operands
[1].imm
;
12364 if (inst
.operands
[1].regisimm
)
12365 immhi
= inst
.operands
[1].reg
;
12367 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
12368 _("immediate has bits set outside the operand size"));
12370 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, &immbits
, &op
,
12371 et
.size
, et
.type
)) == FAIL
)
12373 /* Invert relevant bits only. */
12374 neon_invert_size (&immlo
, &immhi
, et
.size
);
12375 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12376 with one or the other; those cases are caught by
12377 neon_cmode_for_move_imm. */
12379 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, &immbits
, &op
,
12380 et
.size
, et
.type
)) == FAIL
)
12382 first_error (_("immediate out of range"));
12387 inst
.instruction
&= ~(1 << 5);
12388 inst
.instruction
|= op
<< 5;
12390 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12391 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12392 inst
.instruction
|= neon_quad (rs
) << 6;
12393 inst
.instruction
|= cmode
<< 8;
12395 neon_write_immbits (immbits
);
12401 if (inst
.operands
[1].isreg
)
12403 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12405 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12406 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12407 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12408 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12409 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12410 inst
.instruction
|= neon_quad (rs
) << 6;
12414 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12415 neon_move_immediate ();
12418 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12421 /* Encode instructions of form:
12423 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12424 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm |
12429 neon_mixed_length (struct neon_type_el et
, unsigned size
)
12431 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12432 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12433 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12434 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12435 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12436 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12437 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
12438 inst
.instruction
|= neon_logbits (size
) << 20;
12440 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12444 do_neon_dyadic_long (void)
12446 /* FIXME: Type checking for lengthening op. */
12447 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12448 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12449 neon_mixed_length (et
, et
.size
);
12453 do_neon_abal (void)
12455 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12456 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12457 neon_mixed_length (et
, et
.size
);
12461 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
12463 if (inst
.operands
[2].isscalar
)
12465 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
12466 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
12467 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12468 neon_mul_mac (et
, et
.type
== NT_unsigned
);
12472 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12473 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
12474 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12475 neon_mixed_length (et
, et
.size
);
12480 do_neon_mac_maybe_scalar_long (void)
12482 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
12486 do_neon_dyadic_wide (void)
12488 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
12489 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12490 neon_mixed_length (et
, et
.size
);
12494 do_neon_dyadic_narrow (void)
12496 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12497 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
12498 /* Operand sign is unimportant, and the U bit is part of the opcode,
12499 so force the operand type to integer. */
12500 et
.type
= NT_integer
;
12501 neon_mixed_length (et
, et
.size
/ 2);
12505 do_neon_mul_sat_scalar_long (void)
12507 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
12511 do_neon_vmull (void)
12513 if (inst
.operands
[2].isscalar
)
12514 do_neon_mac_maybe_scalar_long ();
12517 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12518 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
12519 if (et
.type
== NT_poly
)
12520 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
12522 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12523 /* For polynomial encoding, size field must be 0b00 and the U bit must be
12524 zero. Should be OK as-is. */
12525 neon_mixed_length (et
, et
.size
);
12532 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
12533 struct neon_type_el et
= neon_check_type (3, rs
,
12534 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12535 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
12536 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12537 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12538 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12539 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12540 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12541 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12542 inst
.instruction
|= neon_quad (rs
) << 6;
12543 inst
.instruction
|= imm
<< 8;
12545 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12551 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12552 struct neon_type_el et
= neon_check_type (2, rs
,
12553 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12554 unsigned op
= (inst
.instruction
>> 7) & 3;
12555 /* N (width of reversed regions) is encoded as part of the bitmask. We
12556 extract it here to check the elements to be reversed are smaller.
12557 Otherwise we'd get a reserved instruction. */
12558 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
12559 assert (elsize
!= 0);
12560 constraint (et
.size
>= elsize
,
12561 _("elements must be smaller than reversal region"));
12562 neon_two_same (neon_quad (rs
), 1, et
.size
);
12568 if (inst
.operands
[1].isscalar
)
12570 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
12571 struct neon_type_el et
= neon_check_type (2, rs
,
12572 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12573 unsigned sizebits
= et
.size
>> 3;
12574 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
12575 int logsize
= neon_logbits (et
.size
);
12576 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
12578 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
12581 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12582 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12583 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12584 inst
.instruction
|= LOW4 (dm
);
12585 inst
.instruction
|= HI1 (dm
) << 5;
12586 inst
.instruction
|= neon_quad (rs
) << 6;
12587 inst
.instruction
|= x
<< 17;
12588 inst
.instruction
|= sizebits
<< 16;
12590 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12594 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
12595 struct neon_type_el et
= neon_check_type (2, rs
,
12596 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
12597 /* Duplicate ARM register to lanes of vector. */
12598 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
12601 case 8: inst
.instruction
|= 0x400000; break;
12602 case 16: inst
.instruction
|= 0x000020; break;
12603 case 32: inst
.instruction
|= 0x000000; break;
12606 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
12607 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
12608 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
12609 inst
.instruction
|= neon_quad (rs
) << 21;
12610 /* The encoding for this instruction is identical for the ARM and Thumb
12611 variants, except for the condition field. */
12612 do_vfp_cond_or_thumb ();
12616 /* VMOV has particularly many variations. It can be one of:
12617 0. VMOV<c><q> <Qd>, <Qm>
12618 1. VMOV<c><q> <Dd>, <Dm>
12619 (Register operations, which are VORR with Rm = Rn.)
12620 2. VMOV<c><q>.<dt> <Qd>, #<imm>
12621 3. VMOV<c><q>.<dt> <Dd>, #<imm>
12623 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
12624 (ARM register to scalar.)
12625 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
12626 (Two ARM registers to vector.)
12627 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
12628 (Scalar to ARM register.)
12629 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
12630 (Vector to two ARM registers.)
12631 8. VMOV.F32 <Sd>, <Sm>
12632 9. VMOV.F64 <Dd>, <Dm>
12633 (VFP register moves.)
12634 10. VMOV.F32 <Sd>, #imm
12635 11. VMOV.F64 <Dd>, #imm
12636 (VFP float immediate load.)
12637 12. VMOV <Rd>, <Sm>
12638 (VFP single to ARM reg.)
12639 13. VMOV <Sd>, <Rm>
12640 (ARM reg to VFP single.)
12641 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
12642 (Two ARM regs to two VFP singles.)
12643 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
12644 (Two VFP singles to two ARM regs.)
12646 These cases can be disambiguated using neon_select_shape, except cases 1/9
12647 and 3/11 which depend on the operand type too.
12649 All the encoded bits are hardcoded by this function.
12651 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
12652 Cases 5, 7 may be used with VFPv2 and above.
12654 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
12655 can specify a type where it doesn't make sense to, and is ignored).
12661 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
12662 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
12664 struct neon_type_el et
;
12665 const char *ldconst
= 0;
12669 case NS_DD
: /* case 1/9. */
12670 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
12671 /* It is not an error here if no type is given. */
12673 if (et
.type
== NT_float
&& et
.size
== 64)
12675 do_vfp_nsyn_opcode ("fcpyd");
12678 /* fall through. */
12680 case NS_QQ
: /* case 0/1. */
12682 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12684 /* The architecture manual I have doesn't explicitly state which
12685 value the U bit should have for register->register moves, but
12686 the equivalent VORR instruction has U = 0, so do that. */
12687 inst
.instruction
= 0x0200110;
12688 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12689 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12690 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12691 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12692 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12693 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12694 inst
.instruction
|= neon_quad (rs
) << 6;
12696 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12700 case NS_DI
: /* case 3/11. */
12701 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
12703 if (et
.type
== NT_float
&& et
.size
== 64)
12705 /* case 11 (fconstd). */
12706 ldconst
= "fconstd";
12707 goto encode_fconstd
;
12709 /* fall through. */
12711 case NS_QI
: /* case 2/3. */
12712 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12714 inst
.instruction
= 0x0800010;
12715 neon_move_immediate ();
12716 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12719 case NS_SR
: /* case 4. */
12721 unsigned bcdebits
= 0;
12722 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
12723 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
12724 int logsize
= neon_logbits (et
.size
);
12725 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
12726 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
12728 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
12730 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
12731 && et
.size
!= 32, _(BAD_FPU
));
12732 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
12733 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
12737 case 8: bcdebits
= 0x8; break;
12738 case 16: bcdebits
= 0x1; break;
12739 case 32: bcdebits
= 0x0; break;
12743 bcdebits
|= x
<< logsize
;
12745 inst
.instruction
= 0xe000b10;
12746 do_vfp_cond_or_thumb ();
12747 inst
.instruction
|= LOW4 (dn
) << 16;
12748 inst
.instruction
|= HI1 (dn
) << 7;
12749 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12750 inst
.instruction
|= (bcdebits
& 3) << 5;
12751 inst
.instruction
|= (bcdebits
>> 2) << 21;
12755 case NS_DRR
: /* case 5 (fmdrr). */
12756 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
12759 inst
.instruction
= 0xc400b10;
12760 do_vfp_cond_or_thumb ();
12761 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
12762 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
12763 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12764 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12767 case NS_RS
: /* case 6. */
12769 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
12770 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
12771 unsigned logsize
= neon_logbits (et
.size
);
12772 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
12773 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
12774 unsigned abcdebits
= 0;
12776 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
12778 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
12779 && et
.size
!= 32, _(BAD_FPU
));
12780 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
12781 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
12785 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
12786 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
12787 case 32: abcdebits
= 0x00; break;
12791 abcdebits
|= x
<< logsize
;
12792 inst
.instruction
= 0xe100b10;
12793 do_vfp_cond_or_thumb ();
12794 inst
.instruction
|= LOW4 (dn
) << 16;
12795 inst
.instruction
|= HI1 (dn
) << 7;
12796 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12797 inst
.instruction
|= (abcdebits
& 3) << 5;
12798 inst
.instruction
|= (abcdebits
>> 2) << 21;
12802 case NS_RRD
: /* case 7 (fmrrd). */
12803 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
12806 inst
.instruction
= 0xc500b10;
12807 do_vfp_cond_or_thumb ();
12808 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12809 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12810 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12811 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12814 case NS_FF
: /* case 8 (fcpys). */
12815 do_vfp_nsyn_opcode ("fcpys");
12818 case NS_FI
: /* case 10 (fconsts). */
12819 ldconst
= "fconsts";
12821 if (is_quarter_float (inst
.operands
[1].imm
))
12823 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
12824 do_vfp_nsyn_opcode (ldconst
);
12827 first_error (_("immediate out of range"));
12830 case NS_RF
: /* case 12 (fmrs). */
12831 do_vfp_nsyn_opcode ("fmrs");
12834 case NS_FR
: /* case 13 (fmsr). */
12835 do_vfp_nsyn_opcode ("fmsr");
12838 /* The encoders for the fmrrs and fmsrr instructions expect three operands
12839 (one of which is a list), but we have parsed four. Do some fiddling to
12840 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
12842 case NS_RRFF
: /* case 14 (fmrrs). */
12843 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
12844 _("VFP registers must be adjacent"));
12845 inst
.operands
[2].imm
= 2;
12846 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
12847 do_vfp_nsyn_opcode ("fmrrs");
12850 case NS_FFRR
: /* case 15 (fmsrr). */
12851 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
12852 _("VFP registers must be adjacent"));
12853 inst
.operands
[1] = inst
.operands
[2];
12854 inst
.operands
[2] = inst
.operands
[3];
12855 inst
.operands
[0].imm
= 2;
12856 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
12857 do_vfp_nsyn_opcode ("fmsrr");
12866 do_neon_rshift_round_imm (void)
12868 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12869 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12870 int imm
= inst
.operands
[2].imm
;
12872 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
12875 inst
.operands
[2].present
= 0;
12880 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12881 _("immediate out of range for shift"));
12882 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12887 do_neon_movl (void)
12889 struct neon_type_el et
= neon_check_type (2, NS_QD
,
12890 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12891 unsigned sizebits
= et
.size
>> 3;
12892 inst
.instruction
|= sizebits
<< 19;
12893 neon_two_same (0, et
.type
== NT_unsigned
, -1);
12899 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12900 struct neon_type_el et
= neon_check_type (2, rs
,
12901 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12902 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12903 neon_two_same (neon_quad (rs
), 1, et
.size
);
12907 do_neon_zip_uzp (void)
12909 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12910 struct neon_type_el et
= neon_check_type (2, rs
,
12911 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12912 if (rs
== NS_DD
&& et
.size
== 32)
12914 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
12915 inst
.instruction
= N_MNEM_vtrn
;
12919 neon_two_same (neon_quad (rs
), 1, et
.size
);
12923 do_neon_sat_abs_neg (void)
12925 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12926 struct neon_type_el et
= neon_check_type (2, rs
,
12927 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
12928 neon_two_same (neon_quad (rs
), 1, et
.size
);
12932 do_neon_pair_long (void)
12934 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12935 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
12936 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
12937 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
12938 neon_two_same (neon_quad (rs
), 1, et
.size
);
12942 do_neon_recip_est (void)
12944 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12945 struct neon_type_el et
= neon_check_type (2, rs
,
12946 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
12947 inst
.instruction
|= (et
.type
== NT_float
) << 8;
12948 neon_two_same (neon_quad (rs
), 1, et
.size
);
12954 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12955 struct neon_type_el et
= neon_check_type (2, rs
,
12956 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
12957 neon_two_same (neon_quad (rs
), 1, et
.size
);
12963 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12964 struct neon_type_el et
= neon_check_type (2, rs
,
12965 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
12966 neon_two_same (neon_quad (rs
), 1, et
.size
);
12972 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12973 struct neon_type_el et
= neon_check_type (2, rs
,
12974 N_EQK
| N_INT
, N_8
| N_KEY
);
12975 neon_two_same (neon_quad (rs
), 1, et
.size
);
12981 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12982 neon_two_same (neon_quad (rs
), 1, -1);
12986 do_neon_tbl_tbx (void)
12988 unsigned listlenbits
;
12989 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
12991 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
12993 first_error (_("bad list length for table lookup"));
12997 listlenbits
= inst
.operands
[1].imm
- 1;
12998 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12999 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13000 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13001 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13002 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13003 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13004 inst
.instruction
|= listlenbits
<< 8;
13006 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13010 do_neon_ldm_stm (void)
13012 /* P, U and L bits are part of bitmask. */
13013 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
13014 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
13016 if (inst
.operands
[1].issingle
)
13018 do_vfp_nsyn_ldm_stm (is_dbmode
);
13022 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
13023 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13025 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
13026 _("register list must contain at least 1 and at most 16 "
13029 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
13030 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
13031 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13032 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
13034 inst
.instruction
|= offsetbits
;
13036 do_vfp_cond_or_thumb ();
13040 do_neon_ldr_str (void)
13042 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
13044 if (inst
.operands
[0].issingle
)
13047 do_vfp_nsyn_opcode ("flds");
13049 do_vfp_nsyn_opcode ("fsts");
13054 do_vfp_nsyn_opcode ("fldd");
13056 do_vfp_nsyn_opcode ("fstd");
13060 /* "interleave" version also handles non-interleaving register VLD1/VST1
13064 do_neon_ld_st_interleave (void)
13066 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
13067 N_8
| N_16
| N_32
| N_64
);
13068 unsigned alignbits
= 0;
13070 /* The bits in this table go:
13071 0: register stride of one (0) or two (1)
13072 1,2: register list length, minus one (1, 2, 3, 4).
13073 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13074 We use -1 for invalid entries. */
13075 const int typetable
[] =
13077 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
13078 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
13079 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
13080 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
13084 if (et
.type
== NT_invtype
)
13087 if (inst
.operands
[1].immisalign
)
13088 switch (inst
.operands
[1].imm
>> 8)
13090 case 64: alignbits
= 1; break;
13092 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13093 goto bad_alignment
;
13097 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13098 goto bad_alignment
;
13103 first_error (_("bad alignment"));
13107 inst
.instruction
|= alignbits
<< 4;
13108 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13110 /* Bits [4:6] of the immediate in a list specifier encode register stride
13111 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13112 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13113 up the right value for "type" in a table based on this value and the given
13114 list style, then stick it back. */
13115 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
13116 | (((inst
.instruction
>> 8) & 3) << 3);
13118 typebits
= typetable
[idx
];
13120 constraint (typebits
== -1, _("bad list type for instruction"));
13122 inst
.instruction
&= ~0xf00;
13123 inst
.instruction
|= typebits
<< 8;
13126 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13127 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13128 otherwise. The variable arguments are a list of pairs of legal (size, align)
13129 values, terminated with -1. */
13132 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
13135 int result
= FAIL
, thissize
, thisalign
;
13137 if (!inst
.operands
[1].immisalign
)
13143 va_start (ap
, do_align
);
13147 thissize
= va_arg (ap
, int);
13148 if (thissize
== -1)
13150 thisalign
= va_arg (ap
, int);
13152 if (size
== thissize
&& align
== thisalign
)
13155 while (result
!= SUCCESS
);
13159 if (result
== SUCCESS
)
13162 first_error (_("unsupported alignment for instruction"));
13168 do_neon_ld_st_lane (void)
13170 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13171 int align_good
, do_align
= 0;
13172 int logsize
= neon_logbits (et
.size
);
13173 int align
= inst
.operands
[1].imm
>> 8;
13174 int n
= (inst
.instruction
>> 8) & 3;
13175 int max_el
= 64 / et
.size
;
13177 if (et
.type
== NT_invtype
)
13180 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
13181 _("bad list length"));
13182 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
13183 _("scalar index out of range"));
13184 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
13186 _("stride of 2 unavailable when element size is 8"));
13190 case 0: /* VLD1 / VST1. */
13191 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
13193 if (align_good
== FAIL
)
13197 unsigned alignbits
= 0;
13200 case 16: alignbits
= 0x1; break;
13201 case 32: alignbits
= 0x3; break;
13204 inst
.instruction
|= alignbits
<< 4;
13208 case 1: /* VLD2 / VST2. */
13209 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
13211 if (align_good
== FAIL
)
13214 inst
.instruction
|= 1 << 4;
13217 case 2: /* VLD3 / VST3. */
13218 constraint (inst
.operands
[1].immisalign
,
13219 _("can't use alignment with this instruction"));
13222 case 3: /* VLD4 / VST4. */
13223 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13224 16, 64, 32, 64, 32, 128, -1);
13225 if (align_good
== FAIL
)
13229 unsigned alignbits
= 0;
13232 case 8: alignbits
= 0x1; break;
13233 case 16: alignbits
= 0x1; break;
13234 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
13237 inst
.instruction
|= alignbits
<< 4;
13244 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13245 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13246 inst
.instruction
|= 1 << (4 + logsize
);
13248 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
13249 inst
.instruction
|= logsize
<< 10;
13252 /* Encode single n-element structure to all lanes VLD<n> instructions. */
13255 do_neon_ld_dup (void)
13257 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13258 int align_good
, do_align
= 0;
13260 if (et
.type
== NT_invtype
)
13263 switch ((inst
.instruction
>> 8) & 3)
13265 case 0: /* VLD1. */
13266 assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
13267 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13268 &do_align
, 16, 16, 32, 32, -1);
13269 if (align_good
== FAIL
)
13271 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
13274 case 2: inst
.instruction
|= 1 << 5; break;
13275 default: first_error (_("bad list length")); return;
13277 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13280 case 1: /* VLD2. */
13281 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13282 &do_align
, 8, 16, 16, 32, 32, 64, -1);
13283 if (align_good
== FAIL
)
13285 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
13286 _("bad list length"));
13287 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13288 inst
.instruction
|= 1 << 5;
13289 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13292 case 2: /* VLD3. */
13293 constraint (inst
.operands
[1].immisalign
,
13294 _("can't use alignment with this instruction"));
13295 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
13296 _("bad list length"));
13297 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13298 inst
.instruction
|= 1 << 5;
13299 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13302 case 3: /* VLD4. */
13304 int align
= inst
.operands
[1].imm
>> 8;
13305 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13306 16, 64, 32, 64, 32, 128, -1);
13307 if (align_good
== FAIL
)
13309 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
13310 _("bad list length"));
13311 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13312 inst
.instruction
|= 1 << 5;
13313 if (et
.size
== 32 && align
== 128)
13314 inst
.instruction
|= 0x3 << 6;
13316 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13323 inst
.instruction
|= do_align
<< 4;
13326 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13327 apart from bits [11:4]. */
13330 do_neon_ldx_stx (void)
13332 switch (NEON_LANE (inst
.operands
[0].imm
))
13334 case NEON_INTERLEAVE_LANES
:
13335 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
13336 do_neon_ld_st_interleave ();
13339 case NEON_ALL_LANES
:
13340 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
13345 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
13346 do_neon_ld_st_lane ();
13349 /* L bit comes from bit mask. */
13350 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13351 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13352 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13354 if (inst
.operands
[1].postind
)
13356 int postreg
= inst
.operands
[1].imm
& 0xf;
13357 constraint (!inst
.operands
[1].immisreg
,
13358 _("post-index must be a register"));
13359 constraint (postreg
== 0xd || postreg
== 0xf,
13360 _("bad register for post-index"));
13361 inst
.instruction
|= postreg
;
13363 else if (inst
.operands
[1].writeback
)
13365 inst
.instruction
|= 0xd;
13368 inst
.instruction
|= 0xf;
13371 inst
.instruction
|= 0xf9000000;
13373 inst
.instruction
|= 0xf4000000;
13377 /* Overall per-instruction processing. */
13379 /* We need to be able to fix up arbitrary expressions in some statements.
13380 This is so that we can handle symbols that are an arbitrary distance from
13381 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13382 which returns part of an address in a form which will be valid for
13383 a data instruction. We do this by pushing the expression into a symbol
13384 in the expr_section, and creating a fix for that. */
13387 fix_new_arm (fragS
* frag
,
13402 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
13406 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
13411 /* Mark whether the fix is to a THUMB instruction, or an ARM
13413 new_fix
->tc_fix_data
= thumb_mode
;
13416 /* Create a frg for an instruction requiring relaxation. */
13418 output_relax_insn (void)
13424 /* The size of the instruction is unknown, so tie the debug info to the
13425 start of the instruction. */
13426 dwarf2_emit_insn (0);
13428 switch (inst
.reloc
.exp
.X_op
)
13431 sym
= inst
.reloc
.exp
.X_add_symbol
;
13432 offset
= inst
.reloc
.exp
.X_add_number
;
13436 offset
= inst
.reloc
.exp
.X_add_number
;
13439 sym
= make_expr_symbol (&inst
.reloc
.exp
);
13443 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
13444 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
13445 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
13448 /* Write a 32-bit thumb instruction to buf. */
13450 put_thumb32_insn (char * buf
, unsigned long insn
)
13452 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
13453 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
13457 output_inst (const char * str
)
13463 as_bad ("%s -- `%s'", inst
.error
, str
);
13467 output_relax_insn();
13470 if (inst
.size
== 0)
13473 to
= frag_more (inst
.size
);
13475 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
13477 assert (inst
.size
== (2 * THUMB_SIZE
));
13478 put_thumb32_insn (to
, inst
.instruction
);
13480 else if (inst
.size
> INSN_SIZE
)
13482 assert (inst
.size
== (2 * INSN_SIZE
));
13483 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
13484 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
13487 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
13489 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
13490 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
13491 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
13494 dwarf2_emit_insn (inst
.size
);
13497 /* Tag values used in struct asm_opcode's tag field. */
13500 OT_unconditional
, /* Instruction cannot be conditionalized.
13501 The ARM condition field is still 0xE. */
13502 OT_unconditionalF
, /* Instruction cannot be conditionalized
13503 and carries 0xF in its ARM condition field. */
13504 OT_csuffix
, /* Instruction takes a conditional suffix. */
13505 OT_csuffixF
, /* Some forms of the instruction take a conditional
13506 suffix, others place 0xF where the condition field
13508 OT_cinfix3
, /* Instruction takes a conditional infix,
13509 beginning at character index 3. (In
13510 unified mode, it becomes a suffix.) */
13511 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
13512 tsts, cmps, cmns, and teqs. */
13513 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
13514 character index 3, even in unified mode. Used for
13515 legacy instructions where suffix and infix forms
13516 may be ambiguous. */
13517 OT_csuf_or_in3
, /* Instruction takes either a conditional
13518 suffix or an infix at character index 3. */
13519 OT_odd_infix_unc
, /* This is the unconditional variant of an
13520 instruction that takes a conditional infix
13521 at an unusual position. In unified mode,
13522 this variant will accept a suffix. */
13523 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
13524 are the conditional variants of instructions that
13525 take conditional infixes in unusual positions.
13526 The infix appears at character index
13527 (tag - OT_odd_infix_0). These are not accepted
13528 in unified mode. */
13531 /* Subroutine of md_assemble, responsible for looking up the primary
13532 opcode from the mnemonic the user wrote. STR points to the
13533 beginning of the mnemonic.
13535 This is not simply a hash table lookup, because of conditional
13536 variants. Most instructions have conditional variants, which are
13537 expressed with a _conditional affix_ to the mnemonic. If we were
13538 to encode each conditional variant as a literal string in the opcode
13539 table, it would have approximately 20,000 entries.
13541 Most mnemonics take this affix as a suffix, and in unified syntax,
13542 'most' is upgraded to 'all'. However, in the divided syntax, some
13543 instructions take the affix as an infix, notably the s-variants of
13544 the arithmetic instructions. Of those instructions, all but six
13545 have the infix appear after the third character of the mnemonic.
13547 Accordingly, the algorithm for looking up primary opcodes given
13550 1. Look up the identifier in the opcode table.
13551 If we find a match, go to step U.
13553 2. Look up the last two characters of the identifier in the
13554 conditions table. If we find a match, look up the first N-2
13555 characters of the identifier in the opcode table. If we
13556 find a match, go to step CE.
13558 3. Look up the fourth and fifth characters of the identifier in
13559 the conditions table. If we find a match, extract those
13560 characters from the identifier, and look up the remaining
13561 characters in the opcode table. If we find a match, go
13566 U. Examine the tag field of the opcode structure, in case this is
13567 one of the six instructions with its conditional infix in an
13568 unusual place. If it is, the tag tells us where to find the
13569 infix; look it up in the conditions table and set inst.cond
13570 accordingly. Otherwise, this is an unconditional instruction.
13571 Again set inst.cond accordingly. Return the opcode structure.
13573 CE. Examine the tag field to make sure this is an instruction that
13574 should receive a conditional suffix. If it is not, fail.
13575 Otherwise, set inst.cond from the suffix we already looked up,
13576 and return the opcode structure.
13578 CM. Examine the tag field to make sure this is an instruction that
13579 should receive a conditional infix after the third character.
13580 If it is not, fail. Otherwise, undo the edits to the current
13581 line of input and proceed as for case CE. */
13583 static const struct asm_opcode
*
13584 opcode_lookup (char **str
)
13588 const struct asm_opcode
*opcode
;
13589 const struct asm_cond
*cond
;
13591 bfd_boolean neon_supported
;
13593 neon_supported
= ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
);
13595 /* Scan up to the end of the mnemonic, which must end in white space,
13596 '.' (in unified mode, or for Neon instructions), or end of string. */
13597 for (base
= end
= *str
; *end
!= '\0'; end
++)
13598 if (*end
== ' ' || ((unified_syntax
|| neon_supported
) && *end
== '.'))
13604 /* Handle a possible width suffix and/or Neon type suffix. */
13609 /* The .w and .n suffixes are only valid if the unified syntax is in
13611 if (unified_syntax
&& end
[1] == 'w')
13613 else if (unified_syntax
&& end
[1] == 'n')
13618 inst
.vectype
.elems
= 0;
13620 *str
= end
+ offset
;
13622 if (end
[offset
] == '.')
13624 /* See if we have a Neon type suffix (possible in either unified or
13625 non-unified ARM syntax mode). */
13626 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
13629 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
13635 /* Look for unaffixed or special-case affixed mnemonic. */
13636 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
13640 if (opcode
->tag
< OT_odd_infix_0
)
13642 inst
.cond
= COND_ALWAYS
;
13646 if (unified_syntax
)
13647 as_warn (_("conditional infixes are deprecated in unified syntax"));
13648 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
13649 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13652 inst
.cond
= cond
->value
;
13656 /* Cannot have a conditional suffix on a mnemonic of less than two
13658 if (end
- base
< 3)
13661 /* Look for suffixed mnemonic. */
13663 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13664 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
13665 if (opcode
&& cond
)
13668 switch (opcode
->tag
)
13670 case OT_cinfix3_legacy
:
13671 /* Ignore conditional suffixes matched on infix only mnemonics. */
13675 case OT_cinfix3_deprecated
:
13676 case OT_odd_infix_unc
:
13677 if (!unified_syntax
)
13679 /* else fall through */
13683 case OT_csuf_or_in3
:
13684 inst
.cond
= cond
->value
;
13687 case OT_unconditional
:
13688 case OT_unconditionalF
:
13691 inst
.cond
= cond
->value
;
13695 /* delayed diagnostic */
13696 inst
.error
= BAD_COND
;
13697 inst
.cond
= COND_ALWAYS
;
13706 /* Cannot have a usual-position infix on a mnemonic of less than
13707 six characters (five would be a suffix). */
13708 if (end
- base
< 6)
13711 /* Look for infixed mnemonic in the usual position. */
13713 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13717 memcpy (save
, affix
, 2);
13718 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
13719 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
13720 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
13721 memcpy (affix
, save
, 2);
13724 && (opcode
->tag
== OT_cinfix3
13725 || opcode
->tag
== OT_cinfix3_deprecated
13726 || opcode
->tag
== OT_csuf_or_in3
13727 || opcode
->tag
== OT_cinfix3_legacy
))
13731 && (opcode
->tag
== OT_cinfix3
13732 || opcode
->tag
== OT_cinfix3_deprecated
))
13733 as_warn (_("conditional infixes are deprecated in unified syntax"));
13735 inst
.cond
= cond
->value
;
13743 md_assemble (char *str
)
13746 const struct asm_opcode
* opcode
;
13748 /* Align the previous label if needed. */
13749 if (last_label_seen
!= NULL
)
13751 symbol_set_frag (last_label_seen
, frag_now
);
13752 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
13753 S_SET_SEGMENT (last_label_seen
, now_seg
);
13756 memset (&inst
, '\0', sizeof (inst
));
13757 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13759 opcode
= opcode_lookup (&p
);
13762 /* It wasn't an instruction, but it might be a register alias of
13763 the form alias .req reg, or a Neon .dn/.qn directive. */
13764 if (!create_register_alias (str
, p
)
13765 && !create_neon_reg_alias (str
, p
))
13766 as_bad (_("bad instruction `%s'"), str
);
13771 if (opcode
->tag
== OT_cinfix3_deprecated
)
13772 as_warn (_("s suffix on comparison instruction is deprecated"));
13774 /* The value which unconditional instructions should have in place of the
13775 condition field. */
13776 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
13780 arm_feature_set variant
;
13782 variant
= cpu_variant
;
13783 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
13784 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
13785 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
13786 /* Check that this instruction is supported for this CPU. */
13787 if (!opcode
->tvariant
13788 || (thumb_mode
== 1
13789 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
13791 as_bad (_("selected processor does not support `%s'"), str
);
13794 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
13795 && opcode
->tencode
!= do_t_branch
)
13797 as_bad (_("Thumb does not support conditional execution"));
13801 /* Check conditional suffixes. */
13802 if (current_it_mask
)
13805 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
13806 current_it_mask
<<= 1;
13807 current_it_mask
&= 0x1f;
13808 /* The BKPT instruction is unconditional even in an IT block. */
13810 && cond
!= inst
.cond
&& opcode
->tencode
!= do_t_bkpt
)
13812 as_bad (_("incorrect condition in IT block"));
13816 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
13818 as_bad (_("thumb conditional instrunction not in IT block"));
13822 mapping_state (MAP_THUMB
);
13823 inst
.instruction
= opcode
->tvalue
;
13825 if (!parse_operands (p
, opcode
->operands
))
13826 opcode
->tencode ();
13828 /* Clear current_it_mask at the end of an IT block. */
13829 if (current_it_mask
== 0x10)
13830 current_it_mask
= 0;
13832 if (!(inst
.error
|| inst
.relax
))
13834 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
13835 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
13836 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
13838 as_bad (_("cannot honor width suffix -- `%s'"), str
);
13842 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13843 *opcode
->tvariant
);
13844 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
13845 set those bits when Thumb-2 32-bit instructions are seen. ie.
13846 anything other than bl/blx.
13847 This is overly pessimistic for relaxable instructions. */
13848 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
13850 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13853 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
13855 /* Check that this instruction is supported for this CPU. */
13856 if (!opcode
->avariant
||
13857 !ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
13859 as_bad (_("selected processor does not support `%s'"), str
);
13864 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
13868 mapping_state (MAP_ARM
);
13869 inst
.instruction
= opcode
->avalue
;
13870 if (opcode
->tag
== OT_unconditionalF
)
13871 inst
.instruction
|= 0xF << 28;
13873 inst
.instruction
|= inst
.cond
<< 28;
13874 inst
.size
= INSN_SIZE
;
13875 if (!parse_operands (p
, opcode
->operands
))
13876 opcode
->aencode ();
13877 /* Arm mode bx is marked as both v4T and v5 because it's still required
13878 on a hypothetical non-thumb v5 core. */
13879 if (ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v4t
)
13880 || ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v5
))
13881 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
13883 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
13884 *opcode
->avariant
);
13888 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
13895 /* Various frobbings of labels and their addresses. */
13898 arm_start_line_hook (void)
13900 last_label_seen
= NULL
;
13904 arm_frob_label (symbolS
* sym
)
13906 last_label_seen
= sym
;
13908 ARM_SET_THUMB (sym
, thumb_mode
);
13910 #if defined OBJ_COFF || defined OBJ_ELF
13911 ARM_SET_INTERWORK (sym
, support_interwork
);
13914 /* Note - do not allow local symbols (.Lxxx) to be labeled
13915 as Thumb functions. This is because these labels, whilst
13916 they exist inside Thumb code, are not the entry points for
13917 possible ARM->Thumb calls. Also, these labels can be used
13918 as part of a computed goto or switch statement. eg gcc
13919 can generate code that looks like this:
13921 ldr r2, [pc, .Laaa]
13931 The first instruction loads the address of the jump table.
13932 The second instruction converts a table index into a byte offset.
13933 The third instruction gets the jump address out of the table.
13934 The fourth instruction performs the jump.
13936 If the address stored at .Laaa is that of a symbol which has the
13937 Thumb_Func bit set, then the linker will arrange for this address
13938 to have the bottom bit set, which in turn would mean that the
13939 address computation performed by the third instruction would end
13940 up with the bottom bit set. Since the ARM is capable of unaligned
13941 word loads, the instruction would then load the incorrect address
13942 out of the jump table, and chaos would ensue. */
13943 if (label_is_thumb_function_name
13944 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
13945 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
13947 /* When the address of a Thumb function is taken the bottom
13948 bit of that address should be set. This will allow
13949 interworking between Arm and Thumb functions to work
13952 THUMB_SET_FUNC (sym
, 1);
13954 label_is_thumb_function_name
= FALSE
;
13957 dwarf2_emit_label (sym
);
13961 arm_data_in_code (void)
13963 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
13965 *input_line_pointer
= '/';
13966 input_line_pointer
+= 5;
13967 *input_line_pointer
= 0;
13975 arm_canonicalize_symbol_name (char * name
)
13979 if (thumb_mode
&& (len
= strlen (name
)) > 5
13980 && streq (name
+ len
- 5, "/data"))
13981 *(name
+ len
- 5) = 0;
13986 /* Table of all register names defined by default. The user can
13987 define additional names with .req. Note that all register names
13988 should appear in both upper and lowercase variants. Some registers
13989 also have mixed-case names. */
13991 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
13992 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
13993 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
13994 #define REGSET(p,t) \
13995 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
13996 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
13997 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
13998 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
13999 #define REGSETH(p,t) \
14000 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
14001 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14002 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14003 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14004 #define REGSET2(p,t) \
14005 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14006 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14007 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14008 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14010 static const struct reg_entry reg_names
[] =
14012 /* ARM integer registers. */
14013 REGSET(r
, RN
), REGSET(R
, RN
),
14015 /* ATPCS synonyms. */
14016 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
14017 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
14018 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
14020 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
14021 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
14022 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
14024 /* Well-known aliases. */
14025 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
14026 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
14028 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
14029 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
14031 /* Coprocessor numbers. */
14032 REGSET(p
, CP
), REGSET(P
, CP
),
14034 /* Coprocessor register numbers. The "cr" variants are for backward
14036 REGSET(c
, CN
), REGSET(C
, CN
),
14037 REGSET(cr
, CN
), REGSET(CR
, CN
),
14039 /* FPA registers. */
14040 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
14041 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
14043 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
14044 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
14046 /* VFP SP registers. */
14047 REGSET(s
,VFS
), REGSET(S
,VFS
),
14048 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
14050 /* VFP DP Registers. */
14051 REGSET(d
,VFD
), REGSET(D
,VFD
),
14052 /* Extra Neon DP registers. */
14053 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
14055 /* Neon QP registers. */
14056 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
14058 /* VFP control registers. */
14059 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
14060 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
14062 /* Maverick DSP coprocessor registers. */
14063 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
14064 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
14066 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
14067 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
14068 REGDEF(dspsc
,0,DSPSC
),
14070 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
14071 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
14072 REGDEF(DSPSC
,0,DSPSC
),
14074 /* iWMMXt data registers - p0, c0-15. */
14075 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
14077 /* iWMMXt control registers - p1, c0-3. */
14078 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
14079 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
14080 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
14081 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
14083 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
14084 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
14085 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
14086 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
14087 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
14089 /* XScale accumulator registers. */
14090 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
14096 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
14097 within psr_required_here. */
14098 static const struct asm_psr psrs
[] =
14100 /* Backward compatibility notation. Note that "all" is no longer
14101 truly all possible PSR bits. */
14102 {"all", PSR_c
| PSR_f
},
14106 /* Individual flags. */
14111 /* Combinations of flags. */
14112 {"fs", PSR_f
| PSR_s
},
14113 {"fx", PSR_f
| PSR_x
},
14114 {"fc", PSR_f
| PSR_c
},
14115 {"sf", PSR_s
| PSR_f
},
14116 {"sx", PSR_s
| PSR_x
},
14117 {"sc", PSR_s
| PSR_c
},
14118 {"xf", PSR_x
| PSR_f
},
14119 {"xs", PSR_x
| PSR_s
},
14120 {"xc", PSR_x
| PSR_c
},
14121 {"cf", PSR_c
| PSR_f
},
14122 {"cs", PSR_c
| PSR_s
},
14123 {"cx", PSR_c
| PSR_x
},
14124 {"fsx", PSR_f
| PSR_s
| PSR_x
},
14125 {"fsc", PSR_f
| PSR_s
| PSR_c
},
14126 {"fxs", PSR_f
| PSR_x
| PSR_s
},
14127 {"fxc", PSR_f
| PSR_x
| PSR_c
},
14128 {"fcs", PSR_f
| PSR_c
| PSR_s
},
14129 {"fcx", PSR_f
| PSR_c
| PSR_x
},
14130 {"sfx", PSR_s
| PSR_f
| PSR_x
},
14131 {"sfc", PSR_s
| PSR_f
| PSR_c
},
14132 {"sxf", PSR_s
| PSR_x
| PSR_f
},
14133 {"sxc", PSR_s
| PSR_x
| PSR_c
},
14134 {"scf", PSR_s
| PSR_c
| PSR_f
},
14135 {"scx", PSR_s
| PSR_c
| PSR_x
},
14136 {"xfs", PSR_x
| PSR_f
| PSR_s
},
14137 {"xfc", PSR_x
| PSR_f
| PSR_c
},
14138 {"xsf", PSR_x
| PSR_s
| PSR_f
},
14139 {"xsc", PSR_x
| PSR_s
| PSR_c
},
14140 {"xcf", PSR_x
| PSR_c
| PSR_f
},
14141 {"xcs", PSR_x
| PSR_c
| PSR_s
},
14142 {"cfs", PSR_c
| PSR_f
| PSR_s
},
14143 {"cfx", PSR_c
| PSR_f
| PSR_x
},
14144 {"csf", PSR_c
| PSR_s
| PSR_f
},
14145 {"csx", PSR_c
| PSR_s
| PSR_x
},
14146 {"cxf", PSR_c
| PSR_x
| PSR_f
},
14147 {"cxs", PSR_c
| PSR_x
| PSR_s
},
14148 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
14149 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
14150 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
14151 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
14152 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
14153 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
14154 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
14155 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
14156 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
14157 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
14158 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
14159 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
14160 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
14161 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
14162 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
14163 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
14164 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
14165 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
14166 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
14167 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
14168 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
14169 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
14170 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
14171 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
14174 /* Table of V7M psr names. */
14175 static const struct asm_psr v7m_psrs
[] =
14188 {"basepri_max", 18},
14193 /* Table of all shift-in-operand names. */
14194 static const struct asm_shift_name shift_names
[] =
14196 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
14197 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
14198 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
14199 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
14200 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
14201 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
14204 /* Table of all explicit relocation names. */
14206 static struct reloc_entry reloc_names
[] =
14208 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
14209 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
14210 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
14211 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
14212 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
14213 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
14214 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
14215 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
14216 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
14217 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
14218 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
14222 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
14223 static const struct asm_cond conds
[] =
14227 {"cs", 0x2}, {"hs", 0x2},
14228 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14242 static struct asm_barrier_opt barrier_opt_names
[] =
14250 /* Table of ARM-format instructions. */
14252 /* Macros for gluing together operand strings. N.B. In all cases
14253 other than OPS0, the trailing OP_stop comes from default
14254 zero-initialization of the unspecified elements of the array. */
14255 #define OPS0() { OP_stop, }
14256 #define OPS1(a) { OP_##a, }
14257 #define OPS2(a,b) { OP_##a,OP_##b, }
14258 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14259 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14260 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14261 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14263 /* These macros abstract out the exact format of the mnemonic table and
14264 save some repeated characters. */
14266 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14267 #define TxCE(mnem, op, top, nops, ops, ae, te) \
14268 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14269 THUMB_VARIANT, do_##ae, do_##te }
14271 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14272 a T_MNEM_xyz enumerator. */
14273 #define TCE(mnem, aop, top, nops, ops, ae, te) \
14274 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14275 #define tCE(mnem, aop, top, nops, ops, ae, te) \
14276 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14278 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14279 infix after the third character. */
14280 #define TxC3(mnem, op, top, nops, ops, ae, te) \
14281 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14282 THUMB_VARIANT, do_##ae, do_##te }
14283 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
14284 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14285 THUMB_VARIANT, do_##ae, do_##te }
14286 #define TC3(mnem, aop, top, nops, ops, ae, te) \
14287 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14288 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
14289 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14290 #define tC3(mnem, aop, top, nops, ops, ae, te) \
14291 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14292 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
14293 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14295 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14296 appear in the condition table. */
14297 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14298 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14299 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14301 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14302 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14303 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14304 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14305 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14306 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14307 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14308 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14309 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14310 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14311 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14312 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14313 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14314 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14315 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14316 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14317 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14318 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14319 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14320 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14322 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14323 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14324 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14325 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14327 /* Mnemonic that cannot be conditionalized. The ARM condition-code
14328 field is still 0xE. Many of the Thumb variants can be executed
14329 conditionally, so this is checked separately. */
14330 #define TUE(mnem, op, top, nops, ops, ae, te) \
14331 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14332 THUMB_VARIANT, do_##ae, do_##te }
14334 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14335 condition code field. */
14336 #define TUF(mnem, op, top, nops, ops, ae, te) \
14337 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14338 THUMB_VARIANT, do_##ae, do_##te }
14340 /* ARM-only variants of all the above. */
14341 #define CE(mnem, op, nops, ops, ae) \
14342 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14344 #define C3(mnem, op, nops, ops, ae) \
14345 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14347 /* Legacy mnemonics that always have conditional infix after the third
14349 #define CL(mnem, op, nops, ops, ae) \
14350 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14351 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14353 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14354 #define cCE(mnem, op, nops, ops, ae) \
14355 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14357 /* Legacy coprocessor instructions where conditional infix and conditional
14358 suffix are ambiguous. For consistency this includes all FPA instructions,
14359 not just the potentially ambiguous ones. */
14360 #define cCL(mnem, op, nops, ops, ae) \
14361 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14362 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14364 /* Coprocessor, takes either a suffix or a position-3 infix
14365 (for an FPA corner case). */
14366 #define C3E(mnem, op, nops, ops, ae) \
14367 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14368 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14370 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
14371 { #m1 #m2 #m3, OPS##nops ops, \
14372 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14373 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14375 #define CM(m1, m2, op, nops, ops, ae) \
14376 xCM_(m1, , m2, op, nops, ops, ae), \
14377 xCM_(m1, eq, m2, op, nops, ops, ae), \
14378 xCM_(m1, ne, m2, op, nops, ops, ae), \
14379 xCM_(m1, cs, m2, op, nops, ops, ae), \
14380 xCM_(m1, hs, m2, op, nops, ops, ae), \
14381 xCM_(m1, cc, m2, op, nops, ops, ae), \
14382 xCM_(m1, ul, m2, op, nops, ops, ae), \
14383 xCM_(m1, lo, m2, op, nops, ops, ae), \
14384 xCM_(m1, mi, m2, op, nops, ops, ae), \
14385 xCM_(m1, pl, m2, op, nops, ops, ae), \
14386 xCM_(m1, vs, m2, op, nops, ops, ae), \
14387 xCM_(m1, vc, m2, op, nops, ops, ae), \
14388 xCM_(m1, hi, m2, op, nops, ops, ae), \
14389 xCM_(m1, ls, m2, op, nops, ops, ae), \
14390 xCM_(m1, ge, m2, op, nops, ops, ae), \
14391 xCM_(m1, lt, m2, op, nops, ops, ae), \
14392 xCM_(m1, gt, m2, op, nops, ops, ae), \
14393 xCM_(m1, le, m2, op, nops, ops, ae), \
14394 xCM_(m1, al, m2, op, nops, ops, ae)
14396 #define UE(mnem, op, nops, ops, ae) \
14397 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14399 #define UF(mnem, op, nops, ops, ae) \
14400 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14402 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
14403 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14404 use the same encoding function for each. */
14405 #define NUF(mnem, op, nops, ops, enc) \
14406 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
14407 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14409 /* Neon data processing, version which indirects through neon_enc_tab for
14410 the various overloaded versions of opcodes. */
14411 #define nUF(mnem, op, nops, ops, enc) \
14412 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
14413 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14415 /* Neon insn with conditional suffix for the ARM version, non-overloaded
14417 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
14418 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
14419 THUMB_VARIANT, do_##enc, do_##enc }
14421 #define NCE(mnem, op, nops, ops, enc) \
14422 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14424 #define NCEF(mnem, op, nops, ops, enc) \
14425 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14427 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
14428 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
14429 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
14430 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14432 #define nCE(mnem, op, nops, ops, enc) \
14433 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14435 #define nCEF(mnem, op, nops, ops, enc) \
14436 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14440 /* Thumb-only, unconditional. */
14441 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
14443 static const struct asm_opcode insns
[] =
14445 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
14446 #define THUMB_VARIANT &arm_ext_v4t
14447 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14448 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14449 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14450 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14451 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14452 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14453 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14454 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14455 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14456 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14457 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14458 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14459 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14460 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14461 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14462 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14464 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
14465 for setting PSR flag bits. They are obsolete in V6 and do not
14466 have Thumb equivalents. */
14467 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14468 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14469 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
14470 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14471 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14472 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
14473 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14474 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14475 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
14477 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14478 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14479 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14480 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14482 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14483 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14484 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14485 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14487 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14488 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14489 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14490 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14491 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14492 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14494 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14495 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14496 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
14497 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
14500 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
14501 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
14502 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
14504 /* Thumb-compatibility pseudo ops. */
14505 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14506 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14507 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14508 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14509 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14510 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14511 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14512 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14513 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
14514 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
14515 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
14516 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
14518 #undef THUMB_VARIANT
14519 #define THUMB_VARIANT &arm_ext_v6
14520 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
14522 /* V1 instructions with no Thumb analogue prior to V6T2. */
14523 #undef THUMB_VARIANT
14524 #define THUMB_VARIANT &arm_ext_v6t2
14525 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14526 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14527 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14528 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14529 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
14531 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14532 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14533 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14534 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14536 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14537 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14539 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14540 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14542 /* V1 instructions with no Thumb analogue at all. */
14543 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
14544 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
14546 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14547 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14548 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14549 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14550 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14551 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14552 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14553 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14556 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
14557 #undef THUMB_VARIANT
14558 #define THUMB_VARIANT &arm_ext_v4t
14559 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
14560 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
14562 #undef THUMB_VARIANT
14563 #define THUMB_VARIANT &arm_ext_v6t2
14564 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
14565 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
14567 /* Generic coprocessor instructions. */
14568 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
14569 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14570 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14571 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14572 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14573 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14574 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14577 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
14578 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
14579 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
14582 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
14583 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
14584 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
14587 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
14588 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14589 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14590 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14591 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14592 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14593 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14594 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14595 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14598 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
14599 #undef THUMB_VARIANT
14600 #define THUMB_VARIANT &arm_ext_v4t
14601 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14602 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14603 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14604 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14605 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14606 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14609 #define ARM_VARIANT &arm_ext_v4t_5
14610 /* ARM Architecture 4T. */
14611 /* Note: bx (and blx) are required on V5, even if the processor does
14612 not support Thumb. */
14613 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
14616 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
14617 #undef THUMB_VARIANT
14618 #define THUMB_VARIANT &arm_ext_v5t
14619 /* Note: blx has 2 variants; the .value coded here is for
14620 BLX(2). Only this variant has conditional execution. */
14621 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
14622 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
14624 #undef THUMB_VARIANT
14625 #define THUMB_VARIANT &arm_ext_v6t2
14626 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
14627 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14628 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14629 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14630 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14631 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
14632 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14633 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14636 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
14637 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14638 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14639 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14640 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14642 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14643 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14645 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14646 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14647 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14648 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14650 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14651 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14652 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14653 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14655 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14656 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14658 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14659 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14660 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14661 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14664 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
14665 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
14666 TC3(ldrd
, 00000d0
, e9500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
14667 TC3(strd
, 00000f0
, e9400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
14669 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14670 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14673 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
14674 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
14677 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
14678 #undef THUMB_VARIANT
14679 #define THUMB_VARIANT &arm_ext_v6
14680 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
14681 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
14682 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14683 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14684 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14685 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14686 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14687 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14688 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14689 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
14691 #undef THUMB_VARIANT
14692 #define THUMB_VARIANT &arm_ext_v6t2
14693 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
14694 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14695 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14697 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
14698 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
14700 /* ARM V6 not included in V7M (eg. integer SIMD). */
14701 #undef THUMB_VARIANT
14702 #define THUMB_VARIANT &arm_ext_v6_notm
14703 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
14704 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
14705 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
14706 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14707 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14708 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14709 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14710 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14711 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14712 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14713 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14714 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14715 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14716 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14717 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14718 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14719 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14720 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14721 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14722 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14723 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14724 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14725 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14726 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14727 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14728 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14729 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14730 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14731 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14732 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14733 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14734 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14735 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14736 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14737 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14738 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14739 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14740 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14741 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14742 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
14743 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
14744 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
14745 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
14746 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
14747 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
14748 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
14749 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
14750 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14751 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14752 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14753 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14754 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14755 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14756 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14757 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14758 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14759 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14760 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14761 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14762 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14763 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14764 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14765 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14766 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14767 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14768 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14769 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14770 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14771 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14772 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14773 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14774 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14775 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14776 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14777 TUF(srsia
, 8cd0500
, e980c000
, 1, (I31w
), srs
, srs
),
14778 UF(srsib
, 9cd0500
, 1, (I31w
), srs
),
14779 UF(srsda
, 84d0500
, 1, (I31w
), srs
),
14780 TUF(srsdb
, 94d0500
, e800c000
, 1, (I31w
), srs
, srs
),
14781 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
14782 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
14783 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
14784 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14785 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14786 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
14789 #define ARM_VARIANT &arm_ext_v6k
14790 #undef THUMB_VARIANT
14791 #define THUMB_VARIANT &arm_ext_v6k
14792 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
14793 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
14794 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
14795 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
14797 #undef THUMB_VARIANT
14798 #define THUMB_VARIANT &arm_ext_v6_notm
14799 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
14800 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
14802 #undef THUMB_VARIANT
14803 #define THUMB_VARIANT &arm_ext_v6t2
14804 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
14805 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
14806 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
14807 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
14808 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
14811 #define ARM_VARIANT &arm_ext_v6z
14812 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
14815 #define ARM_VARIANT &arm_ext_v6t2
14816 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
14817 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
14818 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
14819 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
14821 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
14822 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
14823 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
14824 TCE(rbit
, 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
14826 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14827 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14828 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14829 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14831 UT(cbnz
, b900
, 2, (RR
, EXP
), t_czb
),
14832 UT(cbz
, b100
, 2, (RR
, EXP
), t_czb
),
14833 /* ARM does not really have an IT instruction, so always allow it. */
14835 #define ARM_VARIANT &arm_ext_v1
14836 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
14837 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
14838 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
14839 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
14840 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
14841 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
14842 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
14843 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
14844 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
14845 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
14846 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
14847 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
14848 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
14849 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
14850 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
14852 /* Thumb2 only instructions. */
14854 #define ARM_VARIANT NULL
14856 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
14857 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
14858 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
14859 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
14861 /* Thumb-2 hardware division instructions (R and M profiles only). */
14862 #undef THUMB_VARIANT
14863 #define THUMB_VARIANT &arm_ext_div
14864 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
14865 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
14867 /* ARM V7 instructions. */
14869 #define ARM_VARIANT &arm_ext_v7
14870 #undef THUMB_VARIANT
14871 #define THUMB_VARIANT &arm_ext_v7
14872 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
14873 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
14874 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
14875 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
14876 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
14879 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
14880 cCE(wfs
, e200110
, 1, (RR
), rd
),
14881 cCE(rfs
, e300110
, 1, (RR
), rd
),
14882 cCE(wfc
, e400110
, 1, (RR
), rd
),
14883 cCE(rfc
, e500110
, 1, (RR
), rd
),
14885 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14886 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14887 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14888 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14890 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14891 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14892 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14893 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14895 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
14896 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
14897 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
14898 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
14899 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
14900 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
14901 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
14902 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
14903 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
14904 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
14905 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
14906 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
14908 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
14909 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
14910 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
14911 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
14912 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
14913 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
14914 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
14915 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
14916 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
14917 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
14918 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
14919 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
14921 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
14922 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
14923 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
14924 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
14925 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
14926 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
14927 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
14928 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
14929 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
14930 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
14931 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
14932 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
14934 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
14935 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
14936 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
14937 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
14938 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
14939 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
14940 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
14941 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
14942 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
14943 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
14944 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
14945 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
14947 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
14948 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
14949 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
14950 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
14951 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
14952 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
14953 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
14954 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
14955 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
14956 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
14957 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
14958 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
14960 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
14961 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
14962 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
14963 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
14964 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
14965 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
14966 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
14967 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
14968 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
14969 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
14970 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
14971 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
14973 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
14974 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
14975 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
14976 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
14977 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
14978 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
14979 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
14980 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
14981 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
14982 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
14983 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
14984 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
14986 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
14987 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
14988 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
14989 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
14990 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
14991 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
14992 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
14993 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
14994 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
14995 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
14996 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
14997 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
14999 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
15000 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
15001 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
15002 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
15003 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
15004 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
15005 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
15006 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
15007 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
15008 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
15009 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
15010 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
15012 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
15013 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
15014 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
15015 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
15016 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
15017 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
15018 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
15019 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
15020 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
15021 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
15022 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
15023 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
15025 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
15026 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
15027 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
15028 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
15029 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
15030 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
15031 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
15032 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
15033 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
15034 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
15035 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
15036 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
15038 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
15039 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
15040 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
15041 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
15042 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
15043 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
15044 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
15045 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
15046 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
15047 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
15048 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
15049 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
15051 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
15052 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
15053 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
15054 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
15055 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
15056 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
15057 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
15058 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
15059 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
15060 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
15061 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
15062 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
15064 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
15065 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
15066 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
15067 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
15068 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
15069 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
15070 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
15071 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
15072 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
15073 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
15074 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
15075 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
15077 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
15078 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
15079 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
15080 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
15081 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
15082 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
15083 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
15084 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
15085 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
15086 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
15087 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
15088 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
15090 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
15091 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
15092 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
15093 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
15094 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
15095 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
15096 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
15097 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
15098 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
15099 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
15100 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
15101 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
15103 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15104 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15105 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15106 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15107 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15108 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15109 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15110 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15111 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15112 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15113 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15114 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15116 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15117 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15118 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15119 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15120 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15121 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15122 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15123 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15124 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15125 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15126 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15127 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15129 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15130 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15131 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15132 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15133 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15134 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15135 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15136 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15137 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15138 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15139 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15140 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15142 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15143 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15144 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15145 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15146 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15147 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15148 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15149 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15150 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15151 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15152 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15153 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15155 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15156 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15157 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15158 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15159 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15160 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15161 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15162 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15163 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15164 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15165 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15166 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15168 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15169 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15170 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15171 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15172 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15173 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15174 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15175 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15176 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15177 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15178 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15179 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15181 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15182 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15183 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15184 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15185 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15186 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15187 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15188 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15189 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15190 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15191 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15192 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15194 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15195 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15196 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15197 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15198 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15199 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15200 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15201 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15202 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15203 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15204 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15205 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15207 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15208 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15209 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15210 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15211 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15212 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15213 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15214 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15215 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15216 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15217 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15218 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15220 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15221 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15222 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15223 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15224 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15225 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15226 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15227 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15228 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15229 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15230 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15231 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15233 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15234 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15235 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15236 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15237 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15238 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15239 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15240 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15241 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15242 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15243 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15244 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15246 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15247 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15248 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15249 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15250 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15251 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15252 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15253 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15254 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15255 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15256 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15257 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15259 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15260 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15261 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15262 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15263 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15264 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15265 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15266 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15267 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15268 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15269 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15270 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15272 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15273 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15274 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15275 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15277 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
15278 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
15279 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
15280 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
15281 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
15282 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
15283 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
15284 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
15285 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
15286 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
15287 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
15288 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
15290 /* The implementation of the FIX instruction is broken on some
15291 assemblers, in that it accepts a precision specifier as well as a
15292 rounding specifier, despite the fact that this is meaningless.
15293 To be more compatible, we accept it as well, though of course it
15294 does not set any bits. */
15295 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
15296 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
15297 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
15298 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
15299 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
15300 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
15301 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
15302 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
15303 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
15304 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
15305 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
15306 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
15307 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
15309 /* Instructions that were new with the real FPA, call them V2. */
15311 #define ARM_VARIANT &fpu_fpa_ext_v2
15312 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15313 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15314 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15315 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15316 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15317 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15320 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
15321 /* Moves and type conversions. */
15322 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15323 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
15324 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
15325 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
15326 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15327 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15328 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15329 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15330 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15331 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15332 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
15333 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
15335 /* Memory operations. */
15336 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15337 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15338 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15339 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15340 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15341 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15342 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15343 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15344 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15345 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15346 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15347 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15348 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15349 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15350 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15351 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15352 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15353 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15355 /* Monadic operations. */
15356 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15357 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15358 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15360 /* Dyadic operations. */
15361 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15362 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15363 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15364 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15365 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15366 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15367 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15368 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15369 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15372 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15373 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
15374 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15375 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
15378 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
15379 /* Moves and type conversions. */
15380 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15381 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15382 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15383 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15384 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15385 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15386 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15387 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15388 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15389 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15390 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15391 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15392 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15394 /* Memory operations. */
15395 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15396 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15397 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15398 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15399 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15400 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15401 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15402 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15403 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15404 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15406 /* Monadic operations. */
15407 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15408 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15409 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15411 /* Dyadic operations. */
15412 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15413 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15414 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15415 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15416 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15417 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15418 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15419 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15420 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15423 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15424 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
15425 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15426 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
15429 #define ARM_VARIANT &fpu_vfp_ext_v2
15430 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
15431 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
15432 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
15433 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
15435 /* Instructions which may belong to either the Neon or VFP instruction sets.
15436 Individual encoder functions perform additional architecture checks. */
15438 #define ARM_VARIANT &fpu_vfp_ext_v1xd
15439 #undef THUMB_VARIANT
15440 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
15441 /* These mnemonics are unique to VFP. */
15442 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
15443 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
15444 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15445 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15446 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15447 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15448 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15449 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
15450 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
15451 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
15453 /* Mnemonics shared by Neon and VFP. */
15454 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
15455 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15456 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15458 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15459 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15461 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15462 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15464 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15465 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15466 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15467 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15468 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15469 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15470 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15471 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15473 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
15475 /* NOTE: All VMOV encoding is special-cased! */
15476 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
15477 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
15479 #undef THUMB_VARIANT
15480 #define THUMB_VARIANT &fpu_neon_ext_v1
15482 #define ARM_VARIANT &fpu_neon_ext_v1
15483 /* Data processing with three registers of the same length. */
15484 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
15485 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
15486 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
15487 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15488 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15489 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15490 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15491 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15492 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15493 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
15494 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15495 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15496 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15497 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15498 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15499 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15500 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15501 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15502 /* If not immediate, fall back to neon_dyadic_i64_su.
15503 shl_imm should accept I8 I16 I32 I64,
15504 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
15505 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
15506 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
15507 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
15508 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
15509 /* Logic ops, types optional & ignored. */
15510 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
15511 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
15512 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
15513 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
15514 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
15515 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
15516 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
15517 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
15518 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
15519 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
15520 /* Bitfield ops, untyped. */
15521 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15522 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15523 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15524 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15525 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15526 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15527 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
15528 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15529 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15530 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15531 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15532 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15533 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15534 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
15535 back to neon_dyadic_if_su. */
15536 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15537 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15538 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15539 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15540 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15541 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15542 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15543 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15544 /* Comparison. Type I8 I16 I32 F32. */
15545 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
15546 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
15547 /* As above, D registers only. */
15548 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15549 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15550 /* Int and float variants, signedness unimportant. */
15551 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15552 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15553 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
15554 /* Add/sub take types I8 I16 I32 I64 F32. */
15555 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
15556 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
15557 /* vtst takes sizes 8, 16, 32. */
15558 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
15559 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
15560 /* VMUL takes I8 I16 I32 F32 P8. */
15561 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
15562 /* VQD{R}MULH takes S16 S32. */
15563 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
15564 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
15565 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
15566 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
15567 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
15568 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
15569 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
15570 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
15571 NUF(vaclt
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
15572 NUF(vacltq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
15573 NUF(vacle
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
15574 NUF(vacleq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
15575 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
15576 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
15577 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
15578 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
15580 /* Two address, int/float. Types S8 S16 S32 F32. */
15581 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
15582 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
15584 /* Data processing with two registers and a shift amount. */
15585 /* Right shifts, and variants with rounding.
15586 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
15587 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
15588 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
15589 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
15590 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
15591 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
15592 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
15593 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
15594 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
15595 /* Shift and insert. Sizes accepted 8 16 32 64. */
15596 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
15597 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
15598 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
15599 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
15600 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
15601 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
15602 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
15603 /* Right shift immediate, saturating & narrowing, with rounding variants.
15604 Types accepted S16 S32 S64 U16 U32 U64. */
15605 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
15606 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
15607 /* As above, unsigned. Types accepted S16 S32 S64. */
15608 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
15609 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
15610 /* Right shift narrowing. Types accepted I16 I32 I64. */
15611 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
15612 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
15613 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
15614 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
15615 /* CVT with optional immediate for fixed-point variant. */
15616 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
15618 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
15619 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
15621 /* Data processing, three registers of different lengths. */
15622 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
15623 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
15624 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15625 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15626 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15627 /* If not scalar, fall back to neon_dyadic_long.
15628 Vector types as above, scalar types S16 S32 U16 U32. */
15629 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
15630 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
15631 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
15632 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
15633 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
15634 /* Dyadic, narrowing insns. Types I16 I32 I64. */
15635 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15636 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15637 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15638 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15639 /* Saturating doubling multiplies. Types S16 S32. */
15640 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15641 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15642 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15643 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
15644 S16 S32 U16 U32. */
15645 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
15647 /* Extract. Size 8. */
15648 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I7
), neon_ext
),
15649 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I7
), neon_ext
),
15651 /* Two registers, miscellaneous. */
15652 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
15653 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
15654 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
15655 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
15656 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
15657 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
15658 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
15659 /* Vector replicate. Sizes 8 16 32. */
15660 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
15661 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
15662 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
15663 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
15664 /* VMOVN. Types I16 I32 I64. */
15665 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
15666 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
15667 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
15668 /* VQMOVUN. Types S16 S32 S64. */
15669 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
15670 /* VZIP / VUZP. Sizes 8 16 32. */
15671 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
15672 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
15673 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
15674 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
15675 /* VQABS / VQNEG. Types S8 S16 S32. */
15676 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
15677 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
15678 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
15679 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
15680 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
15681 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
15682 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
15683 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
15684 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
15685 /* Reciprocal estimates. Types U32 F32. */
15686 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
15687 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
15688 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
15689 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
15690 /* VCLS. Types S8 S16 S32. */
15691 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
15692 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
15693 /* VCLZ. Types I8 I16 I32. */
15694 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
15695 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
15696 /* VCNT. Size 8. */
15697 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
15698 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
15699 /* Two address, untyped. */
15700 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
15701 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
15702 /* VTRN. Sizes 8 16 32. */
15703 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
15704 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
15706 /* Table lookup. Size 8. */
15707 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
15708 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
15710 #undef THUMB_VARIANT
15711 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
15713 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
15714 /* Neon element/structure load/store. */
15715 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15716 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15717 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15718 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15719 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15720 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15721 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15722 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15724 #undef THUMB_VARIANT
15725 #define THUMB_VARIANT &fpu_vfp_ext_v3
15727 #define ARM_VARIANT &fpu_vfp_ext_v3
15728 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
15729 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
15730 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15731 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15732 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15733 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15734 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15735 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15736 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15737 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15738 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15739 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15740 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15741 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15742 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15743 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15744 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15745 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15747 #undef THUMB_VARIANT
15749 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
15750 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15751 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15752 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15753 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15754 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15755 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15756 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
15757 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
15760 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
15761 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
15762 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
15763 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
15764 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
15765 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
15766 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
15767 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
15768 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
15769 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
15770 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15771 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15772 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15773 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15774 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15775 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15776 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15777 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15778 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15779 cCE(tmcr
, e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
15780 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
15781 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15782 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15783 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15784 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15785 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15786 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15787 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
15788 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
15789 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
15790 cCE(tmrc
, e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
15791 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
15792 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
15793 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
15794 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
15795 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
15796 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
15797 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
15798 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15799 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15800 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15801 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15802 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15803 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15804 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15805 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15806 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15807 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
15808 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15809 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15810 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15811 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15812 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15813 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15814 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15815 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15816 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15817 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15818 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15819 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15820 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15821 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15822 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15823 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15824 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15825 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15826 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15827 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15828 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15829 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
15830 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
15831 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15832 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15833 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15834 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15835 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15836 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15837 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15838 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15839 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15840 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15841 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15842 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15843 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15844 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15845 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15846 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15847 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15848 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15849 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
15850 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15851 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15852 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15853 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15854 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15855 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15856 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15857 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15858 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15859 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15860 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15861 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15862 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15863 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15864 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15865 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15866 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15867 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15868 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15869 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15870 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15871 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
15872 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15873 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15874 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15875 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15876 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15877 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15878 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15879 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15880 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15881 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15882 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15883 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15884 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15885 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15886 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15887 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15888 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15889 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15890 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15891 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15892 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
15893 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
15894 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15895 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15896 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15897 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15898 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15899 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15900 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15901 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15902 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15903 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15904 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15905 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15906 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15907 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15908 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15909 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15910 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15911 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15912 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15913 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15914 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15915 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15916 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15917 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15918 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15919 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15920 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15921 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15922 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
15925 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
15926 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
15927 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
15928 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
15929 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
15930 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
15931 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
15932 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
15933 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
15934 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
15935 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
15936 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
15937 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
15938 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
15939 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
15940 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
15941 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
15942 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
15943 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
15944 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
15945 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
15946 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
15947 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
15948 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
15949 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
15950 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
15951 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
15952 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
15953 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
15954 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
15955 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
15956 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
15957 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
15958 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
15959 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
15960 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
15961 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
15962 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
15963 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
15964 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
15965 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
15966 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
15967 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
15968 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
15969 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
15970 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
15971 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
15972 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
15973 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
15974 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
15975 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
15976 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
15977 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
15978 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
15979 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
15980 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
15981 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
15982 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
15983 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
15984 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
15985 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
15986 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
15987 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
15988 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
15989 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
15990 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15991 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
15992 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15993 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
15994 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15995 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
15996 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15997 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15998 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
15999 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16000 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16001 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16004 #undef THUMB_VARIANT
16031 /* MD interface: bits in the object file. */
16033 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
16034 for use in the a.out file, and stores them in the array pointed to by buf.
16035 This knows about the endian-ness of the target machine and does
16036 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
16037 2 (short) and 4 (long) Floating numbers are put out as a series of
16038 LITTLENUMS (shorts, here at least). */
16041 md_number_to_chars (char * buf
, valueT val
, int n
)
16043 if (target_big_endian
)
16044 number_to_chars_bigendian (buf
, val
, n
);
16046 number_to_chars_littleendian (buf
, val
, n
);
16050 md_chars_to_number (char * buf
, int n
)
16053 unsigned char * where
= (unsigned char *) buf
;
16055 if (target_big_endian
)
16060 result
|= (*where
++ & 255);
16068 result
|= (where
[n
] & 255);
16075 /* MD interface: Sections. */
16077 /* Estimate the size of a frag before relaxing. Assume everything fits in
16081 md_estimate_size_before_relax (fragS
* fragp
,
16082 segT segtype ATTRIBUTE_UNUSED
)
16088 /* Convert a machine dependent frag. */
16091 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
16093 unsigned long insn
;
16094 unsigned long old_op
;
16102 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16104 old_op
= bfd_get_16(abfd
, buf
);
16105 if (fragp
->fr_symbol
) {
16106 exp
.X_op
= O_symbol
;
16107 exp
.X_add_symbol
= fragp
->fr_symbol
;
16109 exp
.X_op
= O_constant
;
16111 exp
.X_add_number
= fragp
->fr_offset
;
16112 opcode
= fragp
->fr_subtype
;
16115 case T_MNEM_ldr_pc
:
16116 case T_MNEM_ldr_pc2
:
16117 case T_MNEM_ldr_sp
:
16118 case T_MNEM_str_sp
:
16125 if (fragp
->fr_var
== 4)
16127 insn
= THUMB_OP32(opcode
);
16128 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
16130 insn
|= (old_op
& 0x700) << 4;
16134 insn
|= (old_op
& 7) << 12;
16135 insn
|= (old_op
& 0x38) << 13;
16137 insn
|= 0x00000c00;
16138 put_thumb32_insn (buf
, insn
);
16139 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
16143 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
16145 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
16148 if (fragp
->fr_var
== 4)
16150 insn
= THUMB_OP32 (opcode
);
16151 insn
|= (old_op
& 0xf0) << 4;
16152 put_thumb32_insn (buf
, insn
);
16153 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
16157 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16158 exp
.X_add_number
-= 4;
16166 if (fragp
->fr_var
== 4)
16168 int r0off
= (opcode
== T_MNEM_mov
16169 || opcode
== T_MNEM_movs
) ? 0 : 8;
16170 insn
= THUMB_OP32 (opcode
);
16171 insn
= (insn
& 0xe1ffffff) | 0x10000000;
16172 insn
|= (old_op
& 0x700) << r0off
;
16173 put_thumb32_insn (buf
, insn
);
16174 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16178 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
16183 if (fragp
->fr_var
== 4)
16185 insn
= THUMB_OP32(opcode
);
16186 put_thumb32_insn (buf
, insn
);
16187 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
16190 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
16194 if (fragp
->fr_var
== 4)
16196 insn
= THUMB_OP32(opcode
);
16197 insn
|= (old_op
& 0xf00) << 14;
16198 put_thumb32_insn (buf
, insn
);
16199 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
16202 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
16205 case T_MNEM_add_sp
:
16206 case T_MNEM_add_pc
:
16207 case T_MNEM_inc_sp
:
16208 case T_MNEM_dec_sp
:
16209 if (fragp
->fr_var
== 4)
16211 /* ??? Choose between add and addw. */
16212 insn
= THUMB_OP32 (opcode
);
16213 insn
|= (old_op
& 0xf0) << 4;
16214 put_thumb32_insn (buf
, insn
);
16215 if (opcode
== T_MNEM_add_pc
)
16216 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
16218 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16221 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16229 if (fragp
->fr_var
== 4)
16231 insn
= THUMB_OP32 (opcode
);
16232 insn
|= (old_op
& 0xf0) << 4;
16233 insn
|= (old_op
& 0xf) << 16;
16234 put_thumb32_insn (buf
, insn
);
16235 if (insn
& (1 << 20))
16236 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16238 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16241 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16247 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
16249 fixp
->fx_file
= fragp
->fr_file
;
16250 fixp
->fx_line
= fragp
->fr_line
;
16251 fragp
->fr_fix
+= fragp
->fr_var
;
16254 /* Return the size of a relaxable immediate operand instruction.
16255 SHIFT and SIZE specify the form of the allowable immediate. */
16257 relax_immediate (fragS
*fragp
, int size
, int shift
)
16263 /* ??? Should be able to do better than this. */
16264 if (fragp
->fr_symbol
)
16267 low
= (1 << shift
) - 1;
16268 mask
= (1 << (shift
+ size
)) - (1 << shift
);
16269 offset
= fragp
->fr_offset
;
16270 /* Force misaligned offsets to 32-bit variant. */
16273 if (offset
& ~mask
)
16278 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
16281 relax_adr (fragS
*fragp
, asection
*sec
)
16286 /* Assume worst case for symbols not known to be in the same section. */
16287 if (!S_IS_DEFINED(fragp
->fr_symbol
)
16288 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16291 val
= S_GET_VALUE(fragp
->fr_symbol
) + fragp
->fr_offset
;
16292 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16293 addr
= (addr
+ 4) & ~3;
16294 /* Fix the insn as the 4-byte version if the target address is not
16295 sufficiently aligned. This is prevents an infinite loop when two
16296 instructions have contradictory range/alignment requirements. */
16300 if (val
< 0 || val
> 1020)
16305 /* Return the size of a relaxable add/sub immediate instruction. */
16307 relax_addsub (fragS
*fragp
, asection
*sec
)
16312 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16313 op
= bfd_get_16(sec
->owner
, buf
);
16314 if ((op
& 0xf) == ((op
>> 4) & 0xf))
16315 return relax_immediate (fragp
, 8, 0);
16317 return relax_immediate (fragp
, 3, 0);
16321 /* Return the size of a relaxable branch instruction. BITS is the
16322 size of the offset field in the narrow instruction. */
16325 relax_branch (fragS
*fragp
, asection
*sec
, int bits
)
16331 /* Assume worst case for symbols not known to be in the same section. */
16332 if (!S_IS_DEFINED(fragp
->fr_symbol
)
16333 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16336 val
= S_GET_VALUE(fragp
->fr_symbol
) + fragp
->fr_offset
;
16337 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16340 /* Offset is a signed value *2 */
16342 if (val
>= limit
|| val
< -limit
)
16348 /* Relax a machine dependent frag. This returns the amount by which
16349 the current size of the frag should change. */
16352 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
16357 oldsize
= fragp
->fr_var
;
16358 switch (fragp
->fr_subtype
)
16360 case T_MNEM_ldr_pc2
:
16361 newsize
= relax_adr(fragp
, sec
);
16363 case T_MNEM_ldr_pc
:
16364 case T_MNEM_ldr_sp
:
16365 case T_MNEM_str_sp
:
16366 newsize
= relax_immediate(fragp
, 8, 2);
16370 newsize
= relax_immediate(fragp
, 5, 2);
16374 newsize
= relax_immediate(fragp
, 5, 1);
16378 newsize
= relax_immediate(fragp
, 5, 0);
16381 newsize
= relax_adr(fragp
, sec
);
16387 newsize
= relax_immediate(fragp
, 8, 0);
16390 newsize
= relax_branch(fragp
, sec
, 11);
16393 newsize
= relax_branch(fragp
, sec
, 8);
16395 case T_MNEM_add_sp
:
16396 case T_MNEM_add_pc
:
16397 newsize
= relax_immediate (fragp
, 8, 2);
16399 case T_MNEM_inc_sp
:
16400 case T_MNEM_dec_sp
:
16401 newsize
= relax_immediate (fragp
, 7, 2);
16407 newsize
= relax_addsub (fragp
, sec
);
16414 fragp
->fr_var
= -newsize
;
16415 md_convert_frag (sec
->owner
, sec
, fragp
);
16417 return -(newsize
+ oldsize
);
16419 fragp
->fr_var
= newsize
;
16420 return newsize
- oldsize
;
16423 /* Round up a section size to the appropriate boundary. */
16426 md_section_align (segT segment ATTRIBUTE_UNUSED
,
16429 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
16430 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
16432 /* For a.out, force the section size to be aligned. If we don't do
16433 this, BFD will align it for us, but it will not write out the
16434 final bytes of the section. This may be a bug in BFD, but it is
16435 easier to fix it here since that is how the other a.out targets
16439 align
= bfd_get_section_alignment (stdoutput
, segment
);
16440 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
16447 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
16448 of an rs_align_code fragment. */
16451 arm_handle_align (fragS
* fragP
)
16453 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
16454 static char const thumb_noop
[2] = { 0xc0, 0x46 };
16455 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
16456 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
16458 int bytes
, fix
, noop_size
;
16462 if (fragP
->fr_type
!= rs_align_code
)
16465 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
16466 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
16469 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
16470 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
16472 if (fragP
->tc_frag_data
)
16474 if (target_big_endian
)
16475 noop
= thumb_bigend_noop
;
16478 noop_size
= sizeof (thumb_noop
);
16482 if (target_big_endian
)
16483 noop
= arm_bigend_noop
;
16486 noop_size
= sizeof (arm_noop
);
16489 if (bytes
& (noop_size
- 1))
16491 fix
= bytes
& (noop_size
- 1);
16492 memset (p
, 0, fix
);
16497 while (bytes
>= noop_size
)
16499 memcpy (p
, noop
, noop_size
);
16501 bytes
-= noop_size
;
16505 fragP
->fr_fix
+= fix
;
16506 fragP
->fr_var
= noop_size
;
16509 /* Called from md_do_align. Used to create an alignment
16510 frag in a code section. */
16513 arm_frag_align_code (int n
, int max
)
16517 /* We assume that there will never be a requirement
16518 to support alignments greater than 32 bytes. */
16519 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
16520 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
16522 p
= frag_var (rs_align_code
,
16523 MAX_MEM_FOR_RS_ALIGN_CODE
,
16525 (relax_substateT
) max
,
16532 /* Perform target specific initialisation of a frag. */
16535 arm_init_frag (fragS
* fragP
)
16537 /* Record whether this frag is in an ARM or a THUMB area. */
16538 fragP
->tc_frag_data
= thumb_mode
;
16542 /* When we change sections we need to issue a new mapping symbol. */
16545 arm_elf_change_section (void)
16548 segment_info_type
*seginfo
;
16550 /* Link an unlinked unwind index table section to the .text section. */
16551 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
16552 && elf_linked_to_section (now_seg
) == NULL
)
16553 elf_linked_to_section (now_seg
) = text_section
;
16555 if (!SEG_NORMAL (now_seg
))
16558 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
16560 /* We can ignore sections that only contain debug info. */
16561 if ((flags
& SEC_ALLOC
) == 0)
16564 seginfo
= seg_info (now_seg
);
16565 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
16566 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
16570 arm_elf_section_type (const char * str
, size_t len
)
16572 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
16573 return SHT_ARM_EXIDX
;
16578 /* Code to deal with unwinding tables. */
16580 static void add_unwind_adjustsp (offsetT
);
16582 /* Cenerate and deferred unwind frame offset. */
16585 flush_pending_unwind (void)
16589 offset
= unwind
.pending_offset
;
16590 unwind
.pending_offset
= 0;
16592 add_unwind_adjustsp (offset
);
16595 /* Add an opcode to this list for this function. Two-byte opcodes should
16596 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
16600 add_unwind_opcode (valueT op
, int length
)
16602 /* Add any deferred stack adjustment. */
16603 if (unwind
.pending_offset
)
16604 flush_pending_unwind ();
16606 unwind
.sp_restored
= 0;
16608 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
16610 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
16611 if (unwind
.opcodes
)
16612 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
16613 unwind
.opcode_alloc
);
16615 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
16620 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
16622 unwind
.opcode_count
++;
16626 /* Add unwind opcodes to adjust the stack pointer. */
16629 add_unwind_adjustsp (offsetT offset
)
16633 if (offset
> 0x200)
16635 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
16640 /* Long form: 0xb2, uleb128. */
16641 /* This might not fit in a word so add the individual bytes,
16642 remembering the list is built in reverse order. */
16643 o
= (valueT
) ((offset
- 0x204) >> 2);
16645 add_unwind_opcode (0, 1);
16647 /* Calculate the uleb128 encoding of the offset. */
16651 bytes
[n
] = o
& 0x7f;
16657 /* Add the insn. */
16659 add_unwind_opcode (bytes
[n
- 1], 1);
16660 add_unwind_opcode (0xb2, 1);
16662 else if (offset
> 0x100)
16664 /* Two short opcodes. */
16665 add_unwind_opcode (0x3f, 1);
16666 op
= (offset
- 0x104) >> 2;
16667 add_unwind_opcode (op
, 1);
16669 else if (offset
> 0)
16671 /* Short opcode. */
16672 op
= (offset
- 4) >> 2;
16673 add_unwind_opcode (op
, 1);
16675 else if (offset
< 0)
16678 while (offset
> 0x100)
16680 add_unwind_opcode (0x7f, 1);
16683 op
= ((offset
- 4) >> 2) | 0x40;
16684 add_unwind_opcode (op
, 1);
16688 /* Finish the list of unwind opcodes for this function. */
16690 finish_unwind_opcodes (void)
16694 if (unwind
.fp_used
)
16696 /* Adjust sp as necessary. */
16697 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
16698 flush_pending_unwind ();
16700 /* After restoring sp from the frame pointer. */
16701 op
= 0x90 | unwind
.fp_reg
;
16702 add_unwind_opcode (op
, 1);
16705 flush_pending_unwind ();
16709 /* Start an exception table entry. If idx is nonzero this is an index table
16713 start_unwind_section (const segT text_seg
, int idx
)
16715 const char * text_name
;
16716 const char * prefix
;
16717 const char * prefix_once
;
16718 const char * group_name
;
16722 size_t sec_name_len
;
16729 prefix
= ELF_STRING_ARM_unwind
;
16730 prefix_once
= ELF_STRING_ARM_unwind_once
;
16731 type
= SHT_ARM_EXIDX
;
16735 prefix
= ELF_STRING_ARM_unwind_info
;
16736 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
16737 type
= SHT_PROGBITS
;
16740 text_name
= segment_name (text_seg
);
16741 if (streq (text_name
, ".text"))
16744 if (strncmp (text_name
, ".gnu.linkonce.t.",
16745 strlen (".gnu.linkonce.t.")) == 0)
16747 prefix
= prefix_once
;
16748 text_name
+= strlen (".gnu.linkonce.t.");
16751 prefix_len
= strlen (prefix
);
16752 text_len
= strlen (text_name
);
16753 sec_name_len
= prefix_len
+ text_len
;
16754 sec_name
= xmalloc (sec_name_len
+ 1);
16755 memcpy (sec_name
, prefix
, prefix_len
);
16756 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
16757 sec_name
[prefix_len
+ text_len
] = '\0';
16763 /* Handle COMDAT group. */
16764 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
16766 group_name
= elf_group_name (text_seg
);
16767 if (group_name
== NULL
)
16769 as_bad ("Group section `%s' has no group signature",
16770 segment_name (text_seg
));
16771 ignore_rest_of_line ();
16774 flags
|= SHF_GROUP
;
16778 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
16780 /* Set the setion link for index tables. */
16782 elf_linked_to_section (now_seg
) = text_seg
;
16786 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
16787 personality routine data. Returns zero, or the index table value for
16788 and inline entry. */
16791 create_unwind_entry (int have_data
)
16796 /* The current word of data. */
16798 /* The number of bytes left in this word. */
16801 finish_unwind_opcodes ();
16803 /* Remember the current text section. */
16804 unwind
.saved_seg
= now_seg
;
16805 unwind
.saved_subseg
= now_subseg
;
16807 start_unwind_section (now_seg
, 0);
16809 if (unwind
.personality_routine
== NULL
)
16811 if (unwind
.personality_index
== -2)
16814 as_bad (_("handerdata in cantunwind frame"));
16815 return 1; /* EXIDX_CANTUNWIND. */
16818 /* Use a default personality routine if none is specified. */
16819 if (unwind
.personality_index
== -1)
16821 if (unwind
.opcode_count
> 3)
16822 unwind
.personality_index
= 1;
16824 unwind
.personality_index
= 0;
16827 /* Space for the personality routine entry. */
16828 if (unwind
.personality_index
== 0)
16830 if (unwind
.opcode_count
> 3)
16831 as_bad (_("too many unwind opcodes for personality routine 0"));
16835 /* All the data is inline in the index table. */
16838 while (unwind
.opcode_count
> 0)
16840 unwind
.opcode_count
--;
16841 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
16845 /* Pad with "finish" opcodes. */
16847 data
= (data
<< 8) | 0xb0;
16854 /* We get two opcodes "free" in the first word. */
16855 size
= unwind
.opcode_count
- 2;
16858 /* An extra byte is required for the opcode count. */
16859 size
= unwind
.opcode_count
+ 1;
16861 size
= (size
+ 3) >> 2;
16863 as_bad (_("too many unwind opcodes"));
16865 frag_align (2, 0, 0);
16866 record_alignment (now_seg
, 2);
16867 unwind
.table_entry
= expr_build_dot ();
16869 /* Allocate the table entry. */
16870 ptr
= frag_more ((size
<< 2) + 4);
16871 where
= frag_now_fix () - ((size
<< 2) + 4);
16873 switch (unwind
.personality_index
)
16876 /* ??? Should this be a PLT generating relocation? */
16877 /* Custom personality routine. */
16878 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
16879 BFD_RELOC_ARM_PREL31
);
16884 /* Set the first byte to the number of additional words. */
16889 /* ABI defined personality routines. */
16891 /* Three opcodes bytes are packed into the first word. */
16898 /* The size and first two opcode bytes go in the first word. */
16899 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
16904 /* Should never happen. */
16908 /* Pack the opcodes into words (MSB first), reversing the list at the same
16910 while (unwind
.opcode_count
> 0)
16914 md_number_to_chars (ptr
, data
, 4);
16919 unwind
.opcode_count
--;
16921 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
16924 /* Finish off the last word. */
16927 /* Pad with "finish" opcodes. */
16929 data
= (data
<< 8) | 0xb0;
16931 md_number_to_chars (ptr
, data
, 4);
16936 /* Add an empty descriptor if there is no user-specified data. */
16937 ptr
= frag_more (4);
16938 md_number_to_chars (ptr
, 0, 4);
16945 /* Initialize the DWARF-2 unwind information for this procedure. */
16948 tc_arm_frame_initial_instructions (void)
16950 cfi_add_CFA_def_cfa (REG_SP
, 0);
16952 #endif /* OBJ_ELF */
16954 /* Convert REGNAME to a DWARF-2 register number. */
16957 tc_arm_regname_to_dw2regnum (char *regname
)
16959 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
16969 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
16973 expr
.X_op
= O_secrel
;
16974 expr
.X_add_symbol
= symbol
;
16975 expr
.X_add_number
= 0;
16976 emit_expr (&expr
, size
);
16980 /* MD interface: Symbol and relocation handling. */
16982 /* Return the address within the segment that a PC-relative fixup is
16983 relative to. For ARM, PC-relative fixups applied to instructions
16984 are generally relative to the location of the fixup plus 8 bytes.
16985 Thumb branches are offset by 4, and Thumb loads relative to PC
16986 require special handling. */
16989 md_pcrel_from_section (fixS
* fixP
, segT seg
)
16991 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
16993 /* If this is pc-relative and we are going to emit a relocation
16994 then we just want to put out any pipeline compensation that the linker
16995 will need. Otherwise we want to use the calculated base.
16996 For WinCE we skip the bias for externals as well, since this
16997 is how the MS ARM-CE assembler behaves and we want to be compatible. */
16999 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
17000 || (arm_force_relocation (fixP
)
17002 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
17007 switch (fixP
->fx_r_type
)
17009 /* PC relative addressing on the Thumb is slightly odd as the
17010 bottom two bits of the PC are forced to zero for the
17011 calculation. This happens *after* application of the
17012 pipeline offset. However, Thumb adrl already adjusts for
17013 this, so we need not do it again. */
17014 case BFD_RELOC_ARM_THUMB_ADD
:
17017 case BFD_RELOC_ARM_THUMB_OFFSET
:
17018 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17019 case BFD_RELOC_ARM_T32_ADD_PC12
:
17020 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
17021 return (base
+ 4) & ~3;
17023 /* Thumb branches are simply offset by +4. */
17024 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
17025 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
17026 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
17027 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
17028 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
17029 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
17030 case BFD_RELOC_THUMB_PCREL_BLX
:
17033 /* ARM mode branches are offset by +8. However, the Windows CE
17034 loader expects the relocation not to take this into account. */
17035 case BFD_RELOC_ARM_PCREL_BRANCH
:
17036 case BFD_RELOC_ARM_PCREL_CALL
:
17037 case BFD_RELOC_ARM_PCREL_JUMP
:
17038 case BFD_RELOC_ARM_PCREL_BLX
:
17039 case BFD_RELOC_ARM_PLT32
:
17041 /* When handling fixups immediately, because we have already
17042 discovered the value of a symbol, or the address of the frag involved
17043 we must account for the offset by +8, as the OS loader will never see the reloc.
17044 see fixup_segment() in write.c
17045 The S_IS_EXTERNAL test handles the case of global symbols.
17046 Those need the calculated base, not just the pipe compensation the linker will need. */
17048 && fixP
->fx_addsy
!= NULL
17049 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
17050 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
17057 /* ARM mode loads relative to PC are also offset by +8. Unlike
17058 branches, the Windows CE loader *does* expect the relocation
17059 to take this into account. */
17060 case BFD_RELOC_ARM_OFFSET_IMM
:
17061 case BFD_RELOC_ARM_OFFSET_IMM8
:
17062 case BFD_RELOC_ARM_HWLITERAL
:
17063 case BFD_RELOC_ARM_LITERAL
:
17064 case BFD_RELOC_ARM_CP_OFF_IMM
:
17068 /* Other PC-relative relocations are un-offset. */
17074 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17075 Otherwise we have no need to default values of symbols. */
17078 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
17081 if (name
[0] == '_' && name
[1] == 'G'
17082 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
17086 if (symbol_find (name
))
17087 as_bad ("GOT already in the symbol table");
17089 GOT_symbol
= symbol_new (name
, undefined_section
,
17090 (valueT
) 0, & zero_address_frag
);
17100 /* Subroutine of md_apply_fix. Check to see if an immediate can be
17101 computed as two separate immediate values, added together. We
17102 already know that this value cannot be computed by just one ARM
17105 static unsigned int
17106 validate_immediate_twopart (unsigned int val
,
17107 unsigned int * highpart
)
17112 for (i
= 0; i
< 32; i
+= 2)
17113 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
17119 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
17121 else if (a
& 0xff0000)
17123 if (a
& 0xff000000)
17125 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
17129 assert (a
& 0xff000000);
17130 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
17133 return (a
& 0xff) | (i
<< 7);
17140 validate_offset_imm (unsigned int val
, int hwse
)
17142 if ((hwse
&& val
> 255) || val
> 4095)
17147 /* Subroutine of md_apply_fix. Do those data_ops which can take a
17148 negative immediate constant by altering the instruction. A bit of
17153 by inverting the second operand, and
17156 by negating the second operand. */
17159 negate_data_op (unsigned long * instruction
,
17160 unsigned long value
)
17163 unsigned long negated
, inverted
;
17165 negated
= encode_arm_immediate (-value
);
17166 inverted
= encode_arm_immediate (~value
);
17168 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
17171 /* First negates. */
17172 case OPCODE_SUB
: /* ADD <-> SUB */
17173 new_inst
= OPCODE_ADD
;
17178 new_inst
= OPCODE_SUB
;
17182 case OPCODE_CMP
: /* CMP <-> CMN */
17183 new_inst
= OPCODE_CMN
;
17188 new_inst
= OPCODE_CMP
;
17192 /* Now Inverted ops. */
17193 case OPCODE_MOV
: /* MOV <-> MVN */
17194 new_inst
= OPCODE_MVN
;
17199 new_inst
= OPCODE_MOV
;
17203 case OPCODE_AND
: /* AND <-> BIC */
17204 new_inst
= OPCODE_BIC
;
17209 new_inst
= OPCODE_AND
;
17213 case OPCODE_ADC
: /* ADC <-> SBC */
17214 new_inst
= OPCODE_SBC
;
17219 new_inst
= OPCODE_ADC
;
17223 /* We cannot do anything. */
17228 if (value
== (unsigned) FAIL
)
17231 *instruction
&= OPCODE_MASK
;
17232 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
17236 /* Like negate_data_op, but for Thumb-2. */
17238 static unsigned int
17239 thumb32_negate_data_op (offsetT
*instruction
, offsetT value
)
17243 offsetT negated
, inverted
;
17245 negated
= encode_thumb32_immediate (-value
);
17246 inverted
= encode_thumb32_immediate (~value
);
17248 rd
= (*instruction
>> 8) & 0xf;
17249 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
17252 /* ADD <-> SUB. Includes CMP <-> CMN. */
17253 case T2_OPCODE_SUB
:
17254 new_inst
= T2_OPCODE_ADD
;
17258 case T2_OPCODE_ADD
:
17259 new_inst
= T2_OPCODE_SUB
;
17263 /* ORR <-> ORN. Includes MOV <-> MVN. */
17264 case T2_OPCODE_ORR
:
17265 new_inst
= T2_OPCODE_ORN
;
17269 case T2_OPCODE_ORN
:
17270 new_inst
= T2_OPCODE_ORR
;
17274 /* AND <-> BIC. TST has no inverted equivalent. */
17275 case T2_OPCODE_AND
:
17276 new_inst
= T2_OPCODE_BIC
;
17283 case T2_OPCODE_BIC
:
17284 new_inst
= T2_OPCODE_AND
;
17289 case T2_OPCODE_ADC
:
17290 new_inst
= T2_OPCODE_SBC
;
17294 case T2_OPCODE_SBC
:
17295 new_inst
= T2_OPCODE_ADC
;
17299 /* We cannot do anything. */
17307 *instruction
&= T2_OPCODE_MASK
;
17308 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
17312 /* Read a 32-bit thumb instruction from buf. */
17313 static unsigned long
17314 get_thumb32_insn (char * buf
)
17316 unsigned long insn
;
17317 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
17318 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17324 /* We usually want to set the low bit on the address of thumb function
17325 symbols. In particular .word foo - . should have the low bit set.
17326 Generic code tries to fold the difference of two symbols to
17327 a constant. Prevent this and force a relocation when the first symbols
17328 is a thumb function. */
17330 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
17332 if (op
== O_subtract
17333 && l
->X_op
== O_symbol
17334 && r
->X_op
== O_symbol
17335 && THUMB_IS_FUNC (l
->X_add_symbol
))
17337 l
->X_op
= O_subtract
;
17338 l
->X_op_symbol
= r
->X_add_symbol
;
17339 l
->X_add_number
-= r
->X_add_number
;
17342 /* Process as normal. */
17347 md_apply_fix (fixS
* fixP
,
17351 offsetT value
= * valP
;
17353 unsigned int newimm
;
17354 unsigned long temp
;
17356 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
17358 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
17360 /* Note whether this will delete the relocation. */
17362 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
17365 /* On a 64-bit host, silently truncate 'value' to 32 bits for
17366 consistency with the behavior on 32-bit hosts. Remember value
17368 value
&= 0xffffffff;
17369 value
^= 0x80000000;
17370 value
-= 0x80000000;
17373 fixP
->fx_addnumber
= value
;
17375 /* Same treatment for fixP->fx_offset. */
17376 fixP
->fx_offset
&= 0xffffffff;
17377 fixP
->fx_offset
^= 0x80000000;
17378 fixP
->fx_offset
-= 0x80000000;
17380 switch (fixP
->fx_r_type
)
17382 case BFD_RELOC_NONE
:
17383 /* This will need to go in the object file. */
17387 case BFD_RELOC_ARM_IMMEDIATE
:
17388 /* We claim that this fixup has been processed here,
17389 even if in fact we generate an error because we do
17390 not have a reloc for it, so tc_gen_reloc will reject it. */
17394 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17396 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17397 _("undefined symbol %s used as an immediate value"),
17398 S_GET_NAME (fixP
->fx_addsy
));
17402 newimm
= encode_arm_immediate (value
);
17403 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17405 /* If the instruction will fail, see if we can fix things up by
17406 changing the opcode. */
17407 if (newimm
== (unsigned int) FAIL
17408 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
17410 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17411 _("invalid constant (%lx) after fixup"),
17412 (unsigned long) value
);
17416 newimm
|= (temp
& 0xfffff000);
17417 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17420 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
17422 unsigned int highpart
= 0;
17423 unsigned int newinsn
= 0xe1a00000; /* nop. */
17425 newimm
= encode_arm_immediate (value
);
17426 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17428 /* If the instruction will fail, see if we can fix things up by
17429 changing the opcode. */
17430 if (newimm
== (unsigned int) FAIL
17431 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
17433 /* No ? OK - try using two ADD instructions to generate
17435 newimm
= validate_immediate_twopart (value
, & highpart
);
17437 /* Yes - then make sure that the second instruction is
17439 if (newimm
!= (unsigned int) FAIL
)
17441 /* Still No ? Try using a negated value. */
17442 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
17443 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
17444 /* Otherwise - give up. */
17447 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17448 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
17453 /* Replace the first operand in the 2nd instruction (which
17454 is the PC) with the destination register. We have
17455 already added in the PC in the first instruction and we
17456 do not want to do it again. */
17457 newinsn
&= ~ 0xf0000;
17458 newinsn
|= ((newinsn
& 0x0f000) << 4);
17461 newimm
|= (temp
& 0xfffff000);
17462 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17464 highpart
|= (newinsn
& 0xfffff000);
17465 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
17469 case BFD_RELOC_ARM_OFFSET_IMM
:
17470 if (!fixP
->fx_done
&& seg
->use_rela_p
)
17473 case BFD_RELOC_ARM_LITERAL
:
17479 if (validate_offset_imm (value
, 0) == FAIL
)
17481 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
17482 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17483 _("invalid literal constant: pool needs to be closer"));
17485 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17486 _("bad immediate value for offset (%ld)"),
17491 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17492 newval
&= 0xff7ff000;
17493 newval
|= value
| (sign
? INDEX_UP
: 0);
17494 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17497 case BFD_RELOC_ARM_OFFSET_IMM8
:
17498 case BFD_RELOC_ARM_HWLITERAL
:
17504 if (validate_offset_imm (value
, 1) == FAIL
)
17506 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
17507 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17508 _("invalid literal constant: pool needs to be closer"));
17510 as_bad (_("bad immediate value for half-word offset (%ld)"),
17515 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17516 newval
&= 0xff7ff0f0;
17517 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
17518 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17521 case BFD_RELOC_ARM_T32_OFFSET_U8
:
17522 if (value
< 0 || value
> 1020 || value
% 4 != 0)
17523 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17524 _("bad immediate value for offset (%ld)"), (long) value
);
17527 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
17529 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
17532 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17533 /* This is a complicated relocation used for all varieties of Thumb32
17534 load/store instruction with immediate offset:
17536 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
17537 *4, optional writeback(W)
17538 (doubleword load/store)
17540 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
17541 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
17542 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
17543 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
17544 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
17546 Uppercase letters indicate bits that are already encoded at
17547 this point. Lowercase letters are our problem. For the
17548 second block of instructions, the secondary opcode nybble
17549 (bits 8..11) is present, and bit 23 is zero, even if this is
17550 a PC-relative operation. */
17551 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17553 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
17555 if ((newval
& 0xf0000000) == 0xe0000000)
17557 /* Doubleword load/store: 8-bit offset, scaled by 4. */
17559 newval
|= (1 << 23);
17562 if (value
% 4 != 0)
17564 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17565 _("offset not a multiple of 4"));
17571 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17572 _("offset out of range"));
17577 else if ((newval
& 0x000f0000) == 0x000f0000)
17579 /* PC-relative, 12-bit offset. */
17581 newval
|= (1 << 23);
17586 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17587 _("offset out of range"));
17592 else if ((newval
& 0x00000100) == 0x00000100)
17594 /* Writeback: 8-bit, +/- offset. */
17596 newval
|= (1 << 9);
17601 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17602 _("offset out of range"));
17607 else if ((newval
& 0x00000f00) == 0x00000e00)
17609 /* T-instruction: positive 8-bit offset. */
17610 if (value
< 0 || value
> 0xff)
17612 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17613 _("offset out of range"));
17621 /* Positive 12-bit or negative 8-bit offset. */
17625 newval
|= (1 << 23);
17635 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17636 _("offset out of range"));
17643 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
17644 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
17647 case BFD_RELOC_ARM_SHIFT_IMM
:
17648 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17649 if (((unsigned long) value
) > 32
17651 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
17653 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17654 _("shift expression is too large"));
17659 /* Shifts of zero must be done as lsl. */
17661 else if (value
== 32)
17663 newval
&= 0xfffff07f;
17664 newval
|= (value
& 0x1f) << 7;
17665 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17668 case BFD_RELOC_ARM_T32_IMMEDIATE
:
17669 case BFD_RELOC_ARM_T32_ADD_IMM
:
17670 case BFD_RELOC_ARM_T32_IMM12
:
17671 case BFD_RELOC_ARM_T32_ADD_PC12
:
17672 /* We claim that this fixup has been processed here,
17673 even if in fact we generate an error because we do
17674 not have a reloc for it, so tc_gen_reloc will reject it. */
17678 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17680 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17681 _("undefined symbol %s used as an immediate value"),
17682 S_GET_NAME (fixP
->fx_addsy
));
17686 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17688 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
17691 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
17692 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
17694 newimm
= encode_thumb32_immediate (value
);
17695 if (newimm
== (unsigned int) FAIL
)
17696 newimm
= thumb32_negate_data_op (&newval
, value
);
17698 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
17699 && newimm
== (unsigned int) FAIL
)
17701 /* Turn add/sum into addw/subw. */
17702 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
17703 newval
= (newval
& 0xfeffffff) | 0x02000000;
17705 /* 12 bit immediate for addw/subw. */
17709 newval
^= 0x00a00000;
17712 newimm
= (unsigned int) FAIL
;
17717 if (newimm
== (unsigned int)FAIL
)
17719 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17720 _("invalid constant (%lx) after fixup"),
17721 (unsigned long) value
);
17725 newval
|= (newimm
& 0x800) << 15;
17726 newval
|= (newimm
& 0x700) << 4;
17727 newval
|= (newimm
& 0x0ff);
17729 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
17730 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
17733 case BFD_RELOC_ARM_SMC
:
17734 if (((unsigned long) value
) > 0xffff)
17735 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17736 _("invalid smc expression"));
17737 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17738 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
17739 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17742 case BFD_RELOC_ARM_SWI
:
17743 if (fixP
->tc_fix_data
!= 0)
17745 if (((unsigned long) value
) > 0xff)
17746 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17747 _("invalid swi expression"));
17748 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17750 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17754 if (((unsigned long) value
) > 0x00ffffff)
17755 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17756 _("invalid swi expression"));
17757 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17759 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17763 case BFD_RELOC_ARM_MULTI
:
17764 if (((unsigned long) value
) > 0xffff)
17765 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17766 _("invalid expression in load/store multiple"));
17767 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
17768 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17772 case BFD_RELOC_ARM_PCREL_CALL
:
17773 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17774 if ((newval
& 0xf0000000) == 0xf0000000)
17778 goto arm_branch_common
;
17780 case BFD_RELOC_ARM_PCREL_JUMP
:
17781 case BFD_RELOC_ARM_PLT32
:
17783 case BFD_RELOC_ARM_PCREL_BRANCH
:
17785 goto arm_branch_common
;
17787 case BFD_RELOC_ARM_PCREL_BLX
:
17790 /* We are going to store value (shifted right by two) in the
17791 instruction, in a 24 bit, signed field. Bits 26 through 32 either
17792 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
17793 also be be clear. */
17795 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17796 _("misaligned branch destination"));
17797 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
17798 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
17799 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17800 _("branch out of range"));
17802 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17804 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17805 newval
|= (value
>> 2) & 0x00ffffff;
17806 /* Set the H bit on BLX instructions. */
17810 newval
|= 0x01000000;
17812 newval
&= ~0x01000000;
17814 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17818 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CZB */
17819 /* CZB can only branch forward. */
17821 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17822 _("branch out of range"));
17824 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17826 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17827 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
17828 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17832 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
17833 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
17834 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17835 _("branch out of range"));
17837 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17839 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17840 newval
|= (value
& 0x1ff) >> 1;
17841 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17845 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
17846 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
17847 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17848 _("branch out of range"));
17850 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17852 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17853 newval
|= (value
& 0xfff) >> 1;
17854 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17858 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
17859 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
17860 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17861 _("conditional branch out of range"));
17863 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17866 addressT S
, J1
, J2
, lo
, hi
;
17868 S
= (value
& 0x00100000) >> 20;
17869 J2
= (value
& 0x00080000) >> 19;
17870 J1
= (value
& 0x00040000) >> 18;
17871 hi
= (value
& 0x0003f000) >> 12;
17872 lo
= (value
& 0x00000ffe) >> 1;
17874 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17875 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17876 newval
|= (S
<< 10) | hi
;
17877 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
17878 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17879 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
17883 case BFD_RELOC_THUMB_PCREL_BLX
:
17884 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
17885 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
17886 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17887 _("branch out of range"));
17889 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
17890 /* For a BLX instruction, make sure that the relocation is rounded up
17891 to a word boundary. This follows the semantics of the instruction
17892 which specifies that bit 1 of the target address will come from bit
17893 1 of the base address. */
17894 value
= (value
+ 1) & ~ 1;
17896 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17900 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17901 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17902 newval
|= (value
& 0x7fffff) >> 12;
17903 newval2
|= (value
& 0xfff) >> 1;
17904 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17905 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
17909 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
17910 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
17911 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17912 _("branch out of range"));
17914 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17917 addressT S
, I1
, I2
, lo
, hi
;
17919 S
= (value
& 0x01000000) >> 24;
17920 I1
= (value
& 0x00800000) >> 23;
17921 I2
= (value
& 0x00400000) >> 22;
17922 hi
= (value
& 0x003ff000) >> 12;
17923 lo
= (value
& 0x00000ffe) >> 1;
17928 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17929 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17930 newval
|= (S
<< 10) | hi
;
17931 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
17932 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17933 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
17938 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17939 md_number_to_chars (buf
, value
, 1);
17943 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17944 md_number_to_chars (buf
, value
, 2);
17948 case BFD_RELOC_ARM_TLS_GD32
:
17949 case BFD_RELOC_ARM_TLS_LE32
:
17950 case BFD_RELOC_ARM_TLS_IE32
:
17951 case BFD_RELOC_ARM_TLS_LDM32
:
17952 case BFD_RELOC_ARM_TLS_LDO32
:
17953 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
17956 case BFD_RELOC_ARM_GOT32
:
17957 case BFD_RELOC_ARM_GOTOFF
:
17958 case BFD_RELOC_ARM_TARGET2
:
17959 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17960 md_number_to_chars (buf
, 0, 4);
17964 case BFD_RELOC_RVA
:
17966 case BFD_RELOC_ARM_TARGET1
:
17967 case BFD_RELOC_ARM_ROSEGREL32
:
17968 case BFD_RELOC_ARM_SBREL32
:
17969 case BFD_RELOC_32_PCREL
:
17971 case BFD_RELOC_32_SECREL
:
17973 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17975 /* For WinCE we only do this for pcrel fixups. */
17976 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
17978 md_number_to_chars (buf
, value
, 4);
17982 case BFD_RELOC_ARM_PREL31
:
17983 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17985 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
17986 if ((value
^ (value
>> 1)) & 0x40000000)
17988 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17989 _("rel31 relocation overflow"));
17991 newval
|= value
& 0x7fffffff;
17992 md_number_to_chars (buf
, newval
, 4);
17997 case BFD_RELOC_ARM_CP_OFF_IMM
:
17998 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
17999 if (value
< -1023 || value
> 1023 || (value
& 3))
18000 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18001 _("co-processor offset out of range"));
18006 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18007 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18008 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18010 newval
= get_thumb32_insn (buf
);
18011 newval
&= 0xff7fff00;
18012 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
18014 newval
&= ~WRITE_BACK
;
18015 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18016 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18017 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18019 put_thumb32_insn (buf
, newval
);
18022 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
18023 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
18024 if (value
< -255 || value
> 255)
18025 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18026 _("co-processor offset out of range"));
18028 goto cp_off_common
;
18030 case BFD_RELOC_ARM_THUMB_OFFSET
:
18031 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18032 /* Exactly what ranges, and where the offset is inserted depends
18033 on the type of instruction, we can establish this from the
18035 switch (newval
>> 12)
18037 case 4: /* PC load. */
18038 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
18039 forced to zero for these loads; md_pcrel_from has already
18040 compensated for this. */
18042 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18043 _("invalid offset, target not word aligned (0x%08lX)"),
18044 (((unsigned long) fixP
->fx_frag
->fr_address
18045 + (unsigned long) fixP
->fx_where
) & ~3)
18046 + (unsigned long) value
);
18048 if (value
& ~0x3fc)
18049 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18050 _("invalid offset, value too big (0x%08lX)"),
18053 newval
|= value
>> 2;
18056 case 9: /* SP load/store. */
18057 if (value
& ~0x3fc)
18058 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18059 _("invalid offset, value too big (0x%08lX)"),
18061 newval
|= value
>> 2;
18064 case 6: /* Word load/store. */
18066 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18067 _("invalid offset, value too big (0x%08lX)"),
18069 newval
|= value
<< 4; /* 6 - 2. */
18072 case 7: /* Byte load/store. */
18074 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18075 _("invalid offset, value too big (0x%08lX)"),
18077 newval
|= value
<< 6;
18080 case 8: /* Halfword load/store. */
18082 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18083 _("invalid offset, value too big (0x%08lX)"),
18085 newval
|= value
<< 5; /* 6 - 1. */
18089 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18090 "Unable to process relocation for thumb opcode: %lx",
18091 (unsigned long) newval
);
18094 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18097 case BFD_RELOC_ARM_THUMB_ADD
:
18098 /* This is a complicated relocation, since we use it for all of
18099 the following immediate relocations:
18103 9bit ADD/SUB SP word-aligned
18104 10bit ADD PC/SP word-aligned
18106 The type of instruction being processed is encoded in the
18113 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18115 int rd
= (newval
>> 4) & 0xf;
18116 int rs
= newval
& 0xf;
18117 int subtract
= !!(newval
& 0x8000);
18119 /* Check for HI regs, only very restricted cases allowed:
18120 Adjusting SP, and using PC or SP to get an address. */
18121 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
18122 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
18123 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18124 _("invalid Hi register with immediate"));
18126 /* If value is negative, choose the opposite instruction. */
18130 subtract
= !subtract
;
18132 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18133 _("immediate value out of range"));
18138 if (value
& ~0x1fc)
18139 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18140 _("invalid immediate for stack address calculation"));
18141 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
18142 newval
|= value
>> 2;
18144 else if (rs
== REG_PC
|| rs
== REG_SP
)
18146 if (subtract
|| value
& ~0x3fc)
18147 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18148 _("invalid immediate for address calculation (value = 0x%08lX)"),
18149 (unsigned long) value
);
18150 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
18152 newval
|= value
>> 2;
18157 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18158 _("immediate value out of range"));
18159 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
18160 newval
|= (rd
<< 8) | value
;
18165 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18166 _("immediate value out of range"));
18167 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
18168 newval
|= rd
| (rs
<< 3) | (value
<< 6);
18171 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18174 case BFD_RELOC_ARM_THUMB_IMM
:
18175 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18176 if (value
< 0 || value
> 255)
18177 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18178 _("invalid immediate: %ld is too large"),
18181 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18184 case BFD_RELOC_ARM_THUMB_SHIFT
:
18185 /* 5bit shift value (0..32). LSL cannot take 32. */
18186 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
18187 temp
= newval
& 0xf800;
18188 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
18189 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18190 _("invalid shift value: %ld"), (long) value
);
18191 /* Shifts of zero must be encoded as LSL. */
18193 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
18194 /* Shifts of 32 are encoded as zero. */
18195 else if (value
== 32)
18197 newval
|= value
<< 6;
18198 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18201 case BFD_RELOC_VTABLE_INHERIT
:
18202 case BFD_RELOC_VTABLE_ENTRY
:
18206 case BFD_RELOC_ARM_MOVW
:
18207 case BFD_RELOC_ARM_MOVT
:
18208 case BFD_RELOC_ARM_THUMB_MOVW
:
18209 case BFD_RELOC_ARM_THUMB_MOVT
:
18210 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18212 /* REL format relocations are limited to a 16-bit addend. */
18213 if (!fixP
->fx_done
)
18215 if (value
< -0x1000 || value
> 0xffff)
18216 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18217 _("offset too big"));
18219 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
18220 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18225 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
18226 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18228 newval
= get_thumb32_insn (buf
);
18229 newval
&= 0xfbf08f00;
18230 newval
|= (value
& 0xf000) << 4;
18231 newval
|= (value
& 0x0800) << 15;
18232 newval
|= (value
& 0x0700) << 4;
18233 newval
|= (value
& 0x00ff);
18234 put_thumb32_insn (buf
, newval
);
18238 newval
= md_chars_to_number (buf
, 4);
18239 newval
&= 0xfff0f000;
18240 newval
|= value
& 0x0fff;
18241 newval
|= (value
& 0xf000) << 4;
18242 md_number_to_chars (buf
, newval
, 4);
18247 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18248 case BFD_RELOC_ARM_ALU_PC_G0
:
18249 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18250 case BFD_RELOC_ARM_ALU_PC_G1
:
18251 case BFD_RELOC_ARM_ALU_PC_G2
:
18252 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18253 case BFD_RELOC_ARM_ALU_SB_G0
:
18254 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18255 case BFD_RELOC_ARM_ALU_SB_G1
:
18256 case BFD_RELOC_ARM_ALU_SB_G2
:
18257 assert (!fixP
->fx_done
);
18258 if (!seg
->use_rela_p
)
18261 bfd_vma encoded_addend
;
18262 bfd_vma addend_abs
= abs (value
);
18264 /* Check that the absolute value of the addend can be
18265 expressed as an 8-bit constant plus a rotation. */
18266 encoded_addend
= encode_arm_immediate (addend_abs
);
18267 if (encoded_addend
== (unsigned int) FAIL
)
18268 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18269 _("the offset 0x%08lX is not representable"),
18272 /* Extract the instruction. */
18273 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18275 /* If the addend is positive, use an ADD instruction.
18276 Otherwise use a SUB. Take care not to destroy the S bit. */
18277 insn
&= 0xff1fffff;
18283 /* Place the encoded addend into the first 12 bits of the
18285 insn
&= 0xfffff000;
18286 insn
|= encoded_addend
;
18288 /* Update the instruction. */
18289 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18293 case BFD_RELOC_ARM_LDR_PC_G0
:
18294 case BFD_RELOC_ARM_LDR_PC_G1
:
18295 case BFD_RELOC_ARM_LDR_PC_G2
:
18296 case BFD_RELOC_ARM_LDR_SB_G0
:
18297 case BFD_RELOC_ARM_LDR_SB_G1
:
18298 case BFD_RELOC_ARM_LDR_SB_G2
:
18299 assert (!fixP
->fx_done
);
18300 if (!seg
->use_rela_p
)
18303 bfd_vma addend_abs
= abs (value
);
18305 /* Check that the absolute value of the addend can be
18306 encoded in 12 bits. */
18307 if (addend_abs
>= 0x1000)
18308 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18309 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18312 /* Extract the instruction. */
18313 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18315 /* If the addend is negative, clear bit 23 of the instruction.
18316 Otherwise set it. */
18318 insn
&= ~(1 << 23);
18322 /* Place the absolute value of the addend into the first 12 bits
18323 of the instruction. */
18324 insn
&= 0xfffff000;
18325 insn
|= addend_abs
;
18327 /* Update the instruction. */
18328 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18332 case BFD_RELOC_ARM_LDRS_PC_G0
:
18333 case BFD_RELOC_ARM_LDRS_PC_G1
:
18334 case BFD_RELOC_ARM_LDRS_PC_G2
:
18335 case BFD_RELOC_ARM_LDRS_SB_G0
:
18336 case BFD_RELOC_ARM_LDRS_SB_G1
:
18337 case BFD_RELOC_ARM_LDRS_SB_G2
:
18338 assert (!fixP
->fx_done
);
18339 if (!seg
->use_rela_p
)
18342 bfd_vma addend_abs
= abs (value
);
18344 /* Check that the absolute value of the addend can be
18345 encoded in 8 bits. */
18346 if (addend_abs
>= 0x100)
18347 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18348 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
18351 /* Extract the instruction. */
18352 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18354 /* If the addend is negative, clear bit 23 of the instruction.
18355 Otherwise set it. */
18357 insn
&= ~(1 << 23);
18361 /* Place the first four bits of the absolute value of the addend
18362 into the first 4 bits of the instruction, and the remaining
18363 four into bits 8 .. 11. */
18364 insn
&= 0xfffff0f0;
18365 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
18367 /* Update the instruction. */
18368 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18372 case BFD_RELOC_ARM_LDC_PC_G0
:
18373 case BFD_RELOC_ARM_LDC_PC_G1
:
18374 case BFD_RELOC_ARM_LDC_PC_G2
:
18375 case BFD_RELOC_ARM_LDC_SB_G0
:
18376 case BFD_RELOC_ARM_LDC_SB_G1
:
18377 case BFD_RELOC_ARM_LDC_SB_G2
:
18378 assert (!fixP
->fx_done
);
18379 if (!seg
->use_rela_p
)
18382 bfd_vma addend_abs
= abs (value
);
18384 /* Check that the absolute value of the addend is a multiple of
18385 four and, when divided by four, fits in 8 bits. */
18386 if (addend_abs
& 0x3)
18387 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18388 _("bad offset 0x%08lX (must be word-aligned)"),
18391 if ((addend_abs
>> 2) > 0xff)
18392 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18393 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
18396 /* Extract the instruction. */
18397 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18399 /* If the addend is negative, clear bit 23 of the instruction.
18400 Otherwise set it. */
18402 insn
&= ~(1 << 23);
18406 /* Place the addend (divided by four) into the first eight
18407 bits of the instruction. */
18408 insn
&= 0xfffffff0;
18409 insn
|= addend_abs
>> 2;
18411 /* Update the instruction. */
18412 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18416 case BFD_RELOC_UNUSED
:
18418 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18419 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
18423 /* Translate internal representation of relocation info to BFD target
18427 tc_gen_reloc (asection
*section
, fixS
*fixp
)
18430 bfd_reloc_code_real_type code
;
18432 reloc
= xmalloc (sizeof (arelent
));
18434 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
18435 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18436 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18438 if (fixp
->fx_pcrel
)
18440 if (section
->use_rela_p
)
18441 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
18443 fixp
->fx_offset
= reloc
->address
;
18445 reloc
->addend
= fixp
->fx_offset
;
18447 switch (fixp
->fx_r_type
)
18450 if (fixp
->fx_pcrel
)
18452 code
= BFD_RELOC_8_PCREL
;
18457 if (fixp
->fx_pcrel
)
18459 code
= BFD_RELOC_16_PCREL
;
18464 if (fixp
->fx_pcrel
)
18466 code
= BFD_RELOC_32_PCREL
;
18470 case BFD_RELOC_ARM_MOVW
:
18471 if (fixp
->fx_pcrel
)
18473 code
= BFD_RELOC_ARM_MOVW_PCREL
;
18477 case BFD_RELOC_ARM_MOVT
:
18478 if (fixp
->fx_pcrel
)
18480 code
= BFD_RELOC_ARM_MOVT_PCREL
;
18484 case BFD_RELOC_ARM_THUMB_MOVW
:
18485 if (fixp
->fx_pcrel
)
18487 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
18491 case BFD_RELOC_ARM_THUMB_MOVT
:
18492 if (fixp
->fx_pcrel
)
18494 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
18498 case BFD_RELOC_NONE
:
18499 case BFD_RELOC_ARM_PCREL_BRANCH
:
18500 case BFD_RELOC_ARM_PCREL_BLX
:
18501 case BFD_RELOC_RVA
:
18502 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
18503 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
18504 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
18505 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18506 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18507 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18508 case BFD_RELOC_THUMB_PCREL_BLX
:
18509 case BFD_RELOC_VTABLE_ENTRY
:
18510 case BFD_RELOC_VTABLE_INHERIT
:
18512 case BFD_RELOC_32_SECREL
:
18514 code
= fixp
->fx_r_type
;
18517 case BFD_RELOC_ARM_LITERAL
:
18518 case BFD_RELOC_ARM_HWLITERAL
:
18519 /* If this is called then the a literal has
18520 been referenced across a section boundary. */
18521 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18522 _("literal referenced across section boundary"));
18526 case BFD_RELOC_ARM_GOT32
:
18527 case BFD_RELOC_ARM_GOTOFF
:
18528 case BFD_RELOC_ARM_PLT32
:
18529 case BFD_RELOC_ARM_TARGET1
:
18530 case BFD_RELOC_ARM_ROSEGREL32
:
18531 case BFD_RELOC_ARM_SBREL32
:
18532 case BFD_RELOC_ARM_PREL31
:
18533 case BFD_RELOC_ARM_TARGET2
:
18534 case BFD_RELOC_ARM_TLS_LE32
:
18535 case BFD_RELOC_ARM_TLS_LDO32
:
18536 case BFD_RELOC_ARM_PCREL_CALL
:
18537 case BFD_RELOC_ARM_PCREL_JUMP
:
18538 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18539 case BFD_RELOC_ARM_ALU_PC_G0
:
18540 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18541 case BFD_RELOC_ARM_ALU_PC_G1
:
18542 case BFD_RELOC_ARM_ALU_PC_G2
:
18543 case BFD_RELOC_ARM_LDR_PC_G0
:
18544 case BFD_RELOC_ARM_LDR_PC_G1
:
18545 case BFD_RELOC_ARM_LDR_PC_G2
:
18546 case BFD_RELOC_ARM_LDRS_PC_G0
:
18547 case BFD_RELOC_ARM_LDRS_PC_G1
:
18548 case BFD_RELOC_ARM_LDRS_PC_G2
:
18549 case BFD_RELOC_ARM_LDC_PC_G0
:
18550 case BFD_RELOC_ARM_LDC_PC_G1
:
18551 case BFD_RELOC_ARM_LDC_PC_G2
:
18552 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18553 case BFD_RELOC_ARM_ALU_SB_G0
:
18554 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18555 case BFD_RELOC_ARM_ALU_SB_G1
:
18556 case BFD_RELOC_ARM_ALU_SB_G2
:
18557 case BFD_RELOC_ARM_LDR_SB_G0
:
18558 case BFD_RELOC_ARM_LDR_SB_G1
:
18559 case BFD_RELOC_ARM_LDR_SB_G2
:
18560 case BFD_RELOC_ARM_LDRS_SB_G0
:
18561 case BFD_RELOC_ARM_LDRS_SB_G1
:
18562 case BFD_RELOC_ARM_LDRS_SB_G2
:
18563 case BFD_RELOC_ARM_LDC_SB_G0
:
18564 case BFD_RELOC_ARM_LDC_SB_G1
:
18565 case BFD_RELOC_ARM_LDC_SB_G2
:
18566 code
= fixp
->fx_r_type
;
18569 case BFD_RELOC_ARM_TLS_GD32
:
18570 case BFD_RELOC_ARM_TLS_IE32
:
18571 case BFD_RELOC_ARM_TLS_LDM32
:
18572 /* BFD will include the symbol's address in the addend.
18573 But we don't want that, so subtract it out again here. */
18574 if (!S_IS_COMMON (fixp
->fx_addsy
))
18575 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
18576 code
= fixp
->fx_r_type
;
18580 case BFD_RELOC_ARM_IMMEDIATE
:
18581 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18582 _("internal relocation (type: IMMEDIATE) not fixed up"));
18585 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
18586 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18587 _("ADRL used for a symbol not defined in the same file"));
18590 case BFD_RELOC_ARM_OFFSET_IMM
:
18591 if (section
->use_rela_p
)
18593 code
= fixp
->fx_r_type
;
18597 if (fixp
->fx_addsy
!= NULL
18598 && !S_IS_DEFINED (fixp
->fx_addsy
)
18599 && S_IS_LOCAL (fixp
->fx_addsy
))
18601 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18602 _("undefined local label `%s'"),
18603 S_GET_NAME (fixp
->fx_addsy
));
18607 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18608 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
18615 switch (fixp
->fx_r_type
)
18617 case BFD_RELOC_NONE
: type
= "NONE"; break;
18618 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
18619 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
18620 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
18621 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
18622 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
18623 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
18624 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
18625 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
18626 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
18627 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
18628 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
18629 default: type
= _("<unknown>"); break;
18631 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18632 _("cannot represent %s relocation in this object file format"),
18639 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
18641 && fixp
->fx_addsy
== GOT_symbol
)
18643 code
= BFD_RELOC_ARM_GOTPC
;
18644 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
18648 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18650 if (reloc
->howto
== NULL
)
18652 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18653 _("cannot represent %s relocation in this object file format"),
18654 bfd_get_reloc_code_name (code
));
18658 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
18659 vtable entry to be used in the relocation's section offset. */
18660 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18661 reloc
->address
= fixp
->fx_offset
;
18666 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
18669 cons_fix_new_arm (fragS
* frag
,
18674 bfd_reloc_code_real_type type
;
18678 FIXME: @@ Should look at CPU word size. */
18682 type
= BFD_RELOC_8
;
18685 type
= BFD_RELOC_16
;
18689 type
= BFD_RELOC_32
;
18692 type
= BFD_RELOC_64
;
18697 if (exp
->X_op
== O_secrel
)
18699 exp
->X_op
= O_symbol
;
18700 type
= BFD_RELOC_32_SECREL
;
18704 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
18707 #if defined OBJ_COFF || defined OBJ_ELF
18709 arm_validate_fix (fixS
* fixP
)
18711 /* If the destination of the branch is a defined symbol which does not have
18712 the THUMB_FUNC attribute, then we must be calling a function which has
18713 the (interfacearm) attribute. We look for the Thumb entry point to that
18714 function and change the branch to refer to that function instead. */
18715 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
18716 && fixP
->fx_addsy
!= NULL
18717 && S_IS_DEFINED (fixP
->fx_addsy
)
18718 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
18720 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
18726 arm_force_relocation (struct fix
* fixp
)
18728 #if defined (OBJ_COFF) && defined (TE_PE)
18729 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
18733 /* Resolve these relocations even if the symbol is extern or weak. */
18734 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
18735 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
18736 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
18737 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
18738 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
18739 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
18740 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
18743 /* Always leave these relocations for the linker. */
18744 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
18745 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
18746 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
18749 return generic_force_reloc (fixp
);
18754 arm_fix_adjustable (fixS
* fixP
)
18756 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
18757 local labels from being added to the output symbol table when they
18758 are used with the ADRL pseudo op. The ADRL relocation should always
18759 be resolved before the binbary is emitted, so it is safe to say that
18760 it is adjustable. */
18761 if (fixP
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
)
18764 /* This is a hack for the gas/all/redef2.s test. This test causes symbols
18765 to be cloned, and without this test relocs would still be generated
18766 against the original, pre-cloned symbol. Such symbols would not appear
18767 in the symbol table however, and so a valid reloc could not be
18768 generated. So check to see if the fixup is against a symbol which has
18769 been removed from the symbol chain, and if it is, then allow it to be
18770 adjusted into a reloc against a section symbol. */
18771 if (fixP
->fx_addsy
!= NULL
18772 && ! S_IS_LOCAL (fixP
->fx_addsy
)
18773 && symbol_next (fixP
->fx_addsy
) == NULL
18774 && symbol_next (fixP
->fx_addsy
) == symbol_previous (fixP
->fx_addsy
))
18782 /* Relocations against function names must be left unadjusted,
18783 so that the linker can use this information to generate interworking
18784 stubs. The MIPS version of this function
18785 also prevents relocations that are mips-16 specific, but I do not
18786 know why it does this.
18789 There is one other problem that ought to be addressed here, but
18790 which currently is not: Taking the address of a label (rather
18791 than a function) and then later jumping to that address. Such
18792 addresses also ought to have their bottom bit set (assuming that
18793 they reside in Thumb code), but at the moment they will not. */
18796 arm_fix_adjustable (fixS
* fixP
)
18798 if (fixP
->fx_addsy
== NULL
)
18801 /* Preserve relocations against symbols with function type. */
18802 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
18805 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
18806 && fixP
->fx_subsy
== NULL
)
18809 /* We need the symbol name for the VTABLE entries. */
18810 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
18811 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18814 /* Don't allow symbols to be discarded on GOT related relocs. */
18815 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
18816 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
18817 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
18818 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
18819 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
18820 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
18821 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
18822 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
18823 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
18826 /* Similarly for group relocations. */
18827 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
18828 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
18829 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
18836 elf32_arm_target_format (void)
18839 return (target_big_endian
18840 ? "elf32-bigarm-symbian"
18841 : "elf32-littlearm-symbian");
18842 #elif defined (TE_VXWORKS)
18843 return (target_big_endian
18844 ? "elf32-bigarm-vxworks"
18845 : "elf32-littlearm-vxworks");
18847 if (target_big_endian
)
18848 return "elf32-bigarm";
18850 return "elf32-littlearm";
18855 armelf_frob_symbol (symbolS
* symp
,
18858 elf_frob_symbol (symp
, puntp
);
18862 /* MD interface: Finalization. */
18864 /* A good place to do this, although this was probably not intended
18865 for this kind of use. We need to dump the literal pool before
18866 references are made to a null symbol pointer. */
18871 literal_pool
* pool
;
18873 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
18875 /* Put it at the end of the relevent section. */
18876 subseg_set (pool
->section
, pool
->sub_section
);
18878 arm_elf_change_section ();
18884 /* Adjust the symbol table. This marks Thumb symbols as distinct from
18888 arm_adjust_symtab (void)
18893 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
18895 if (ARM_IS_THUMB (sym
))
18897 if (THUMB_IS_FUNC (sym
))
18899 /* Mark the symbol as a Thumb function. */
18900 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
18901 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
18902 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
18904 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
18905 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
18907 as_bad (_("%s: unexpected function type: %d"),
18908 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
18910 else switch (S_GET_STORAGE_CLASS (sym
))
18913 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
18916 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
18919 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
18927 if (ARM_IS_INTERWORK (sym
))
18928 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
18935 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
18937 if (ARM_IS_THUMB (sym
))
18939 elf_symbol_type
* elf_sym
;
18941 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
18942 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
18944 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
18945 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
18947 /* If it's a .thumb_func, declare it as so,
18948 otherwise tag label as .code 16. */
18949 if (THUMB_IS_FUNC (sym
))
18950 elf_sym
->internal_elf_sym
.st_info
=
18951 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
18953 elf_sym
->internal_elf_sym
.st_info
=
18954 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
18961 /* MD interface: Initialization. */
18964 set_constant_flonums (void)
18968 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
18969 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
18973 /* Auto-select Thumb mode if it's the only available instruction set for the
18974 given architecture. */
18977 autoselect_thumb_from_cpu_variant (void)
18979 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18980 opcode_select (16);
18989 if ( (arm_ops_hsh
= hash_new ()) == NULL
18990 || (arm_cond_hsh
= hash_new ()) == NULL
18991 || (arm_shift_hsh
= hash_new ()) == NULL
18992 || (arm_psr_hsh
= hash_new ()) == NULL
18993 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
18994 || (arm_reg_hsh
= hash_new ()) == NULL
18995 || (arm_reloc_hsh
= hash_new ()) == NULL
18996 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
18997 as_fatal (_("virtual memory exhausted"));
18999 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
19000 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
19001 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
19002 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
19003 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
19004 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (PTR
) (shift_names
+ i
));
19005 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
19006 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
19007 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
19008 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (PTR
) (v7m_psrs
+ i
));
19009 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
19010 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (PTR
) (reg_names
+ i
));
19012 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
19014 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
19015 (PTR
) (barrier_opt_names
+ i
));
19017 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
19018 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (PTR
) (reloc_names
+ i
));
19021 set_constant_flonums ();
19023 /* Set the cpu variant based on the command-line options. We prefer
19024 -mcpu= over -march= if both are set (as for GCC); and we prefer
19025 -mfpu= over any other way of setting the floating point unit.
19026 Use of legacy options with new options are faulted. */
19029 if (mcpu_cpu_opt
|| march_cpu_opt
)
19030 as_bad (_("use of old and new-style options to set CPU type"));
19032 mcpu_cpu_opt
= legacy_cpu
;
19034 else if (!mcpu_cpu_opt
)
19035 mcpu_cpu_opt
= march_cpu_opt
;
19040 as_bad (_("use of old and new-style options to set FPU type"));
19042 mfpu_opt
= legacy_fpu
;
19044 else if (!mfpu_opt
)
19046 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
19047 /* Some environments specify a default FPU. If they don't, infer it
19048 from the processor. */
19050 mfpu_opt
= mcpu_fpu_opt
;
19052 mfpu_opt
= march_fpu_opt
;
19054 mfpu_opt
= &fpu_default
;
19061 mfpu_opt
= &fpu_default
;
19062 else if (ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
19063 mfpu_opt
= &fpu_arch_vfp_v2
;
19065 mfpu_opt
= &fpu_arch_fpa
;
19071 mcpu_cpu_opt
= &cpu_default
;
19072 selected_cpu
= cpu_default
;
19076 selected_cpu
= *mcpu_cpu_opt
;
19078 mcpu_cpu_opt
= &arm_arch_any
;
19081 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
19083 autoselect_thumb_from_cpu_variant ();
19085 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
19087 #if defined OBJ_COFF || defined OBJ_ELF
19089 unsigned int flags
= 0;
19091 #if defined OBJ_ELF
19092 flags
= meabi_flags
;
19094 switch (meabi_flags
)
19096 case EF_ARM_EABI_UNKNOWN
:
19098 /* Set the flags in the private structure. */
19099 if (uses_apcs_26
) flags
|= F_APCS26
;
19100 if (support_interwork
) flags
|= F_INTERWORK
;
19101 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
19102 if (pic_code
) flags
|= F_PIC
;
19103 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
19104 flags
|= F_SOFT_FLOAT
;
19106 switch (mfloat_abi_opt
)
19108 case ARM_FLOAT_ABI_SOFT
:
19109 case ARM_FLOAT_ABI_SOFTFP
:
19110 flags
|= F_SOFT_FLOAT
;
19113 case ARM_FLOAT_ABI_HARD
:
19114 if (flags
& F_SOFT_FLOAT
)
19115 as_bad (_("hard-float conflicts with specified fpu"));
19119 /* Using pure-endian doubles (even if soft-float). */
19120 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
19121 flags
|= F_VFP_FLOAT
;
19123 #if defined OBJ_ELF
19124 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
19125 flags
|= EF_ARM_MAVERICK_FLOAT
;
19128 case EF_ARM_EABI_VER4
:
19129 case EF_ARM_EABI_VER5
:
19130 /* No additional flags to set. */
19137 bfd_set_private_flags (stdoutput
, flags
);
19139 /* We have run out flags in the COFF header to encode the
19140 status of ATPCS support, so instead we create a dummy,
19141 empty, debug section called .arm.atpcs. */
19146 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
19150 bfd_set_section_flags
19151 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
19152 bfd_set_section_size (stdoutput
, sec
, 0);
19153 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
19159 /* Record the CPU type as well. */
19160 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
19161 mach
= bfd_mach_arm_iWMMXt
;
19162 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
19163 mach
= bfd_mach_arm_XScale
;
19164 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
19165 mach
= bfd_mach_arm_ep9312
;
19166 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
19167 mach
= bfd_mach_arm_5TE
;
19168 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
19170 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19171 mach
= bfd_mach_arm_5T
;
19173 mach
= bfd_mach_arm_5
;
19175 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
19177 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19178 mach
= bfd_mach_arm_4T
;
19180 mach
= bfd_mach_arm_4
;
19182 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
19183 mach
= bfd_mach_arm_3M
;
19184 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
19185 mach
= bfd_mach_arm_3
;
19186 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
19187 mach
= bfd_mach_arm_2a
;
19188 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
19189 mach
= bfd_mach_arm_2
;
19191 mach
= bfd_mach_arm_unknown
;
19193 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
19196 /* Command line processing. */
19199 Invocation line includes a switch not recognized by the base assembler.
19200 See if it's a processor-specific option.
19202 This routine is somewhat complicated by the need for backwards
19203 compatibility (since older releases of gcc can't be changed).
19204 The new options try to make the interface as compatible as
19207 New options (supported) are:
19209 -mcpu=<cpu name> Assemble for selected processor
19210 -march=<architecture name> Assemble for selected architecture
19211 -mfpu=<fpu architecture> Assemble for selected FPU.
19212 -EB/-mbig-endian Big-endian
19213 -EL/-mlittle-endian Little-endian
19214 -k Generate PIC code
19215 -mthumb Start in Thumb mode
19216 -mthumb-interwork Code supports ARM/Thumb interworking
19218 For now we will also provide support for:
19220 -mapcs-32 32-bit Program counter
19221 -mapcs-26 26-bit Program counter
19222 -macps-float Floats passed in FP registers
19223 -mapcs-reentrant Reentrant code
19225 (sometime these will probably be replaced with -mapcs=<list of options>
19226 and -matpcs=<list of options>)
19228 The remaining options are only supported for back-wards compatibility.
19229 Cpu variants, the arm part is optional:
19230 -m[arm]1 Currently not supported.
19231 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
19232 -m[arm]3 Arm 3 processor
19233 -m[arm]6[xx], Arm 6 processors
19234 -m[arm]7[xx][t][[d]m] Arm 7 processors
19235 -m[arm]8[10] Arm 8 processors
19236 -m[arm]9[20][tdmi] Arm 9 processors
19237 -mstrongarm[110[0]] StrongARM processors
19238 -mxscale XScale processors
19239 -m[arm]v[2345[t[e]]] Arm architectures
19240 -mall All (except the ARM1)
19242 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
19243 -mfpe-old (No float load/store multiples)
19244 -mvfpxd VFP Single precision
19246 -mno-fpu Disable all floating point instructions
19248 The following CPU names are recognized:
19249 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19250 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19251 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19252 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19253 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19254 arm10t arm10e, arm1020t, arm1020e, arm10200e,
19255 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
19259 const char * md_shortopts
= "m:k";
19261 #ifdef ARM_BI_ENDIAN
19262 #define OPTION_EB (OPTION_MD_BASE + 0)
19263 #define OPTION_EL (OPTION_MD_BASE + 1)
19265 #if TARGET_BYTES_BIG_ENDIAN
19266 #define OPTION_EB (OPTION_MD_BASE + 0)
19268 #define OPTION_EL (OPTION_MD_BASE + 1)
19272 struct option md_longopts
[] =
19275 {"EB", no_argument
, NULL
, OPTION_EB
},
19278 {"EL", no_argument
, NULL
, OPTION_EL
},
19280 {NULL
, no_argument
, NULL
, 0}
19283 size_t md_longopts_size
= sizeof (md_longopts
);
19285 struct arm_option_table
19287 char *option
; /* Option name to match. */
19288 char *help
; /* Help information. */
19289 int *var
; /* Variable to change. */
19290 int value
; /* What to change it to. */
19291 char *deprecated
; /* If non-null, print this message. */
19294 struct arm_option_table arm_opts
[] =
19296 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
19297 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
19298 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19299 &support_interwork
, 1, NULL
},
19300 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
19301 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
19302 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
19304 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
19305 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
19306 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
19307 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
19310 /* These are recognized by the assembler, but have no affect on code. */
19311 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
19312 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
19313 {NULL
, NULL
, NULL
, 0, NULL
}
19316 struct arm_legacy_option_table
19318 char *option
; /* Option name to match. */
19319 const arm_feature_set
**var
; /* Variable to change. */
19320 const arm_feature_set value
; /* What to change it to. */
19321 char *deprecated
; /* If non-null, print this message. */
19324 const struct arm_legacy_option_table arm_legacy_opts
[] =
19326 /* DON'T add any new processors to this list -- we want the whole list
19327 to go away... Add them to the processors table instead. */
19328 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19329 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19330 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19331 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19332 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19333 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19334 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19335 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19336 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19337 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19338 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19339 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19340 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19341 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19342 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19343 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19344 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19345 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19346 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19347 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19348 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19349 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19350 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19351 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19352 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19353 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19354 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19355 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19356 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19357 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19358 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19359 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19360 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19361 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19362 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19363 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19364 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19365 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19366 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19367 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19368 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19369 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19370 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19371 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19372 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19373 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19374 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19375 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19376 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19377 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19378 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19379 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19380 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19381 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19382 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19383 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19384 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19385 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19386 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19387 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19388 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19389 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19390 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19391 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19392 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19393 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19394 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19395 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19396 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
19397 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
19398 N_("use -mcpu=strongarm110")},
19399 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
19400 N_("use -mcpu=strongarm1100")},
19401 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
19402 N_("use -mcpu=strongarm1110")},
19403 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
19404 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
19405 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
19407 /* Architecture variants -- don't add any more to this list either. */
19408 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19409 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19410 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19411 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19412 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19413 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19414 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19415 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19416 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19417 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19418 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19419 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19420 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19421 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19422 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19423 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19424 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19425 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19427 /* Floating point variants -- don't add any more to this list either. */
19428 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
19429 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
19430 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
19431 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
19432 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
19434 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
19437 struct arm_cpu_option_table
19440 const arm_feature_set value
;
19441 /* For some CPUs we assume an FPU unless the user explicitly sets
19443 const arm_feature_set default_fpu
;
19444 /* The canonical name of the CPU, or NULL to use NAME converted to upper
19446 const char *canonical_name
;
19449 /* This list should, at a minimum, contain all the cpu names
19450 recognized by GCC. */
19451 static const struct arm_cpu_option_table arm_cpus
[] =
19453 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
19454 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
19455 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
19456 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19457 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19458 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19459 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19460 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19461 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19462 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19463 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19464 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19465 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19466 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19467 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19468 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19469 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19470 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19471 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19472 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19473 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19474 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19475 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19476 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19477 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19478 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19479 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19480 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19481 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19482 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19483 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19484 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19485 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19486 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19487 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19488 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19489 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19490 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19491 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19492 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
19493 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19494 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19495 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19496 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19497 /* For V5 or later processors we default to using VFP; but the user
19498 should really set the FPU type explicitly. */
19499 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19500 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19501 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
19502 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
19503 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
19504 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19505 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
19506 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19507 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19508 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
19509 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19510 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19511 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19512 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19513 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19514 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
19515 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19516 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19517 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19518 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
19519 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
19520 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
19521 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
19522 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
19523 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
19524 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
19525 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
19526 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
19527 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
19528 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
19529 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
19530 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
19531 | FPU_NEON_EXT_V1
),
19533 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
19534 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
19535 /* ??? XSCALE is really an architecture. */
19536 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
19537 /* ??? iwmmxt is not a processor. */
19538 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
19539 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
19541 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
19542 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
19545 struct arm_arch_option_table
19548 const arm_feature_set value
;
19549 const arm_feature_set default_fpu
;
19552 /* This list should, at a minimum, contain all the architecture names
19553 recognized by GCC. */
19554 static const struct arm_arch_option_table arm_archs
[] =
19556 {"all", ARM_ANY
, FPU_ARCH_FPA
},
19557 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
19558 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
19559 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
19560 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
19561 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
19562 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
19563 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
19564 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
19565 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
19566 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
19567 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
19568 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
19569 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
19570 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
19571 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
19572 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
19573 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
19574 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
19575 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
19576 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
19577 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
19578 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
19579 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
19580 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
19581 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
19582 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
19583 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
19584 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
19585 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
19586 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
19587 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
19588 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
19591 /* ISA extensions in the co-processor space. */
19592 struct arm_option_cpu_value_table
19595 const arm_feature_set value
;
19598 static const struct arm_option_cpu_value_table arm_extensions
[] =
19600 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
19601 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
19602 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
19603 {NULL
, ARM_ARCH_NONE
}
19606 /* This list should, at a minimum, contain all the fpu names
19607 recognized by GCC. */
19608 static const struct arm_option_cpu_value_table arm_fpus
[] =
19610 {"softfpa", FPU_NONE
},
19611 {"fpe", FPU_ARCH_FPE
},
19612 {"fpe2", FPU_ARCH_FPE
},
19613 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
19614 {"fpa", FPU_ARCH_FPA
},
19615 {"fpa10", FPU_ARCH_FPA
},
19616 {"fpa11", FPU_ARCH_FPA
},
19617 {"arm7500fe", FPU_ARCH_FPA
},
19618 {"softvfp", FPU_ARCH_VFP
},
19619 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
19620 {"vfp", FPU_ARCH_VFP_V2
},
19621 {"vfp9", FPU_ARCH_VFP_V2
},
19622 {"vfp3", FPU_ARCH_VFP_V3
},
19623 {"vfp10", FPU_ARCH_VFP_V2
},
19624 {"vfp10-r0", FPU_ARCH_VFP_V1
},
19625 {"vfpxd", FPU_ARCH_VFP_V1xD
},
19626 {"arm1020t", FPU_ARCH_VFP_V1
},
19627 {"arm1020e", FPU_ARCH_VFP_V2
},
19628 {"arm1136jfs", FPU_ARCH_VFP_V2
},
19629 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
19630 {"maverick", FPU_ARCH_MAVERICK
},
19631 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
19632 {NULL
, ARM_ARCH_NONE
}
19635 struct arm_option_value_table
19641 static const struct arm_option_value_table arm_float_abis
[] =
19643 {"hard", ARM_FLOAT_ABI_HARD
},
19644 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
19645 {"soft", ARM_FLOAT_ABI_SOFT
},
19650 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
19651 static const struct arm_option_value_table arm_eabis
[] =
19653 {"gnu", EF_ARM_EABI_UNKNOWN
},
19654 {"4", EF_ARM_EABI_VER4
},
19655 {"5", EF_ARM_EABI_VER5
},
19660 struct arm_long_option_table
19662 char * option
; /* Substring to match. */
19663 char * help
; /* Help information. */
19664 int (* func
) (char * subopt
); /* Function to decode sub-option. */
19665 char * deprecated
; /* If non-null, print this message. */
19669 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
19671 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
19673 /* Copy the feature set, so that we can modify it. */
19674 *ext_set
= **opt_p
;
19677 while (str
!= NULL
&& *str
!= 0)
19679 const struct arm_option_cpu_value_table
* opt
;
19685 as_bad (_("invalid architectural extension"));
19690 ext
= strchr (str
, '+');
19693 optlen
= ext
- str
;
19695 optlen
= strlen (str
);
19699 as_bad (_("missing architectural extension"));
19703 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
19704 if (strncmp (opt
->name
, str
, optlen
) == 0)
19706 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
19710 if (opt
->name
== NULL
)
19712 as_bad (_("unknown architectural extnsion `%s'"), str
);
19723 arm_parse_cpu (char * str
)
19725 const struct arm_cpu_option_table
* opt
;
19726 char * ext
= strchr (str
, '+');
19730 optlen
= ext
- str
;
19732 optlen
= strlen (str
);
19736 as_bad (_("missing cpu name `%s'"), str
);
19740 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
19741 if (strncmp (opt
->name
, str
, optlen
) == 0)
19743 mcpu_cpu_opt
= &opt
->value
;
19744 mcpu_fpu_opt
= &opt
->default_fpu
;
19745 if (opt
->canonical_name
)
19746 strcpy(selected_cpu_name
, opt
->canonical_name
);
19750 for (i
= 0; i
< optlen
; i
++)
19751 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
19752 selected_cpu_name
[i
] = 0;
19756 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
19761 as_bad (_("unknown cpu `%s'"), str
);
19766 arm_parse_arch (char * str
)
19768 const struct arm_arch_option_table
*opt
;
19769 char *ext
= strchr (str
, '+');
19773 optlen
= ext
- str
;
19775 optlen
= strlen (str
);
19779 as_bad (_("missing architecture name `%s'"), str
);
19783 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
19784 if (streq (opt
->name
, str
))
19786 march_cpu_opt
= &opt
->value
;
19787 march_fpu_opt
= &opt
->default_fpu
;
19788 strcpy(selected_cpu_name
, opt
->name
);
19791 return arm_parse_extension (ext
, &march_cpu_opt
);
19796 as_bad (_("unknown architecture `%s'\n"), str
);
19801 arm_parse_fpu (char * str
)
19803 const struct arm_option_cpu_value_table
* opt
;
19805 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
19806 if (streq (opt
->name
, str
))
19808 mfpu_opt
= &opt
->value
;
19812 as_bad (_("unknown floating point format `%s'\n"), str
);
19817 arm_parse_float_abi (char * str
)
19819 const struct arm_option_value_table
* opt
;
19821 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
19822 if (streq (opt
->name
, str
))
19824 mfloat_abi_opt
= opt
->value
;
19828 as_bad (_("unknown floating point abi `%s'\n"), str
);
19834 arm_parse_eabi (char * str
)
19836 const struct arm_option_value_table
*opt
;
19838 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
19839 if (streq (opt
->name
, str
))
19841 meabi_flags
= opt
->value
;
19844 as_bad (_("unknown EABI `%s'\n"), str
);
19849 struct arm_long_option_table arm_long_opts
[] =
19851 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
19852 arm_parse_cpu
, NULL
},
19853 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
19854 arm_parse_arch
, NULL
},
19855 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
19856 arm_parse_fpu
, NULL
},
19857 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
19858 arm_parse_float_abi
, NULL
},
19860 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
19861 arm_parse_eabi
, NULL
},
19863 {NULL
, NULL
, 0, NULL
}
19867 md_parse_option (int c
, char * arg
)
19869 struct arm_option_table
*opt
;
19870 const struct arm_legacy_option_table
*fopt
;
19871 struct arm_long_option_table
*lopt
;
19877 target_big_endian
= 1;
19883 target_big_endian
= 0;
19888 /* Listing option. Just ignore these, we don't support additional
19893 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
19895 if (c
== opt
->option
[0]
19896 && ((arg
== NULL
&& opt
->option
[1] == 0)
19897 || streq (arg
, opt
->option
+ 1)))
19899 #if WARN_DEPRECATED
19900 /* If the option is deprecated, tell the user. */
19901 if (opt
->deprecated
!= NULL
)
19902 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
19903 arg
? arg
: "", _(opt
->deprecated
));
19906 if (opt
->var
!= NULL
)
19907 *opt
->var
= opt
->value
;
19913 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
19915 if (c
== fopt
->option
[0]
19916 && ((arg
== NULL
&& fopt
->option
[1] == 0)
19917 || streq (arg
, fopt
->option
+ 1)))
19919 #if WARN_DEPRECATED
19920 /* If the option is deprecated, tell the user. */
19921 if (fopt
->deprecated
!= NULL
)
19922 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
19923 arg
? arg
: "", _(fopt
->deprecated
));
19926 if (fopt
->var
!= NULL
)
19927 *fopt
->var
= &fopt
->value
;
19933 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
19935 /* These options are expected to have an argument. */
19936 if (c
== lopt
->option
[0]
19938 && strncmp (arg
, lopt
->option
+ 1,
19939 strlen (lopt
->option
+ 1)) == 0)
19941 #if WARN_DEPRECATED
19942 /* If the option is deprecated, tell the user. */
19943 if (lopt
->deprecated
!= NULL
)
19944 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
19945 _(lopt
->deprecated
));
19948 /* Call the sup-option parser. */
19949 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
19960 md_show_usage (FILE * fp
)
19962 struct arm_option_table
*opt
;
19963 struct arm_long_option_table
*lopt
;
19965 fprintf (fp
, _(" ARM-specific assembler options:\n"));
19967 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
19968 if (opt
->help
!= NULL
)
19969 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
19971 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
19972 if (lopt
->help
!= NULL
)
19973 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
19977 -EB assemble code for a big-endian cpu\n"));
19982 -EL assemble code for a little-endian cpu\n"));
19991 arm_feature_set flags
;
19992 } cpu_arch_ver_table
;
19994 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
19995 least features first. */
19996 static const cpu_arch_ver_table cpu_arch_ver
[] =
20001 {4, ARM_ARCH_V5TE
},
20002 {5, ARM_ARCH_V5TEJ
},
20006 {9, ARM_ARCH_V6T2
},
20007 {10, ARM_ARCH_V7A
},
20008 {10, ARM_ARCH_V7R
},
20009 {10, ARM_ARCH_V7M
},
20013 /* Set the public EABI object attributes. */
20015 aeabi_set_public_attributes (void)
20018 arm_feature_set flags
;
20019 arm_feature_set tmp
;
20020 const cpu_arch_ver_table
*p
;
20022 /* Choose the architecture based on the capabilities of the requested cpu
20023 (if any) and/or the instructions actually used. */
20024 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
20025 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
20026 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
20030 for (p
= cpu_arch_ver
; p
->val
; p
++)
20032 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
20035 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
20039 /* Tag_CPU_name. */
20040 if (selected_cpu_name
[0])
20044 p
= selected_cpu_name
;
20045 if (strncmp(p
, "armv", 4) == 0)
20050 for (i
= 0; p
[i
]; i
++)
20051 p
[i
] = TOUPPER (p
[i
]);
20053 elf32_arm_add_eabi_attr_string (stdoutput
, 5, p
);
20055 /* Tag_CPU_arch. */
20056 elf32_arm_add_eabi_attr_int (stdoutput
, 6, arch
);
20057 /* Tag_CPU_arch_profile. */
20058 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
20059 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'A');
20060 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
20061 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'R');
20062 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
))
20063 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'M');
20064 /* Tag_ARM_ISA_use. */
20065 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_full
))
20066 elf32_arm_add_eabi_attr_int (stdoutput
, 8, 1);
20067 /* Tag_THUMB_ISA_use. */
20068 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_full
))
20069 elf32_arm_add_eabi_attr_int (stdoutput
, 9,
20070 ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
) ? 2 : 1);
20071 /* Tag_VFP_arch. */
20072 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v3
)
20073 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v3
))
20074 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 3);
20075 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v2
)
20076 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v2
))
20077 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 2);
20078 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1
)
20079 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1
)
20080 || ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1xd
)
20081 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1xd
))
20082 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 1);
20083 /* Tag_WMMX_arch. */
20084 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_cext_iwmmxt
)
20085 || ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_cext_iwmmxt
))
20086 elf32_arm_add_eabi_attr_int (stdoutput
, 11, 1);
20087 /* Tag_NEON_arch. */
20088 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_neon_ext_v1
)
20089 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_neon_ext_v1
))
20090 elf32_arm_add_eabi_attr_int (stdoutput
, 12, 1);
20093 /* Add the .ARM.attributes section. */
20102 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
20105 aeabi_set_public_attributes ();
20106 size
= elf32_arm_eabi_attr_size (stdoutput
);
20107 s
= subseg_new (".ARM.attributes", 0);
20108 bfd_set_section_flags (stdoutput
, s
, SEC_READONLY
| SEC_DATA
);
20109 addr
= frag_now_fix ();
20110 p
= frag_more (size
);
20111 elf32_arm_set_eabi_attr_contents (stdoutput
, (bfd_byte
*)p
, size
);
20113 #endif /* OBJ_ELF */
20116 /* Parse a .cpu directive. */
20119 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
20121 const struct arm_cpu_option_table
*opt
;
20125 name
= input_line_pointer
;
20126 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20127 input_line_pointer
++;
20128 saved_char
= *input_line_pointer
;
20129 *input_line_pointer
= 0;
20131 /* Skip the first "all" entry. */
20132 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
20133 if (streq (opt
->name
, name
))
20135 mcpu_cpu_opt
= &opt
->value
;
20136 selected_cpu
= opt
->value
;
20137 if (opt
->canonical_name
)
20138 strcpy(selected_cpu_name
, opt
->canonical_name
);
20142 for (i
= 0; opt
->name
[i
]; i
++)
20143 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20144 selected_cpu_name
[i
] = 0;
20146 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20147 *input_line_pointer
= saved_char
;
20148 demand_empty_rest_of_line ();
20151 as_bad (_("unknown cpu `%s'"), name
);
20152 *input_line_pointer
= saved_char
;
20153 ignore_rest_of_line ();
20157 /* Parse a .arch directive. */
20160 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
20162 const struct arm_arch_option_table
*opt
;
20166 name
= input_line_pointer
;
20167 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20168 input_line_pointer
++;
20169 saved_char
= *input_line_pointer
;
20170 *input_line_pointer
= 0;
20172 /* Skip the first "all" entry. */
20173 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20174 if (streq (opt
->name
, name
))
20176 mcpu_cpu_opt
= &opt
->value
;
20177 selected_cpu
= opt
->value
;
20178 strcpy(selected_cpu_name
, opt
->name
);
20179 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20180 *input_line_pointer
= saved_char
;
20181 demand_empty_rest_of_line ();
20185 as_bad (_("unknown architecture `%s'\n"), name
);
20186 *input_line_pointer
= saved_char
;
20187 ignore_rest_of_line ();
20191 /* Parse a .fpu directive. */
20194 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
20196 const struct arm_option_cpu_value_table
*opt
;
20200 name
= input_line_pointer
;
20201 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20202 input_line_pointer
++;
20203 saved_char
= *input_line_pointer
;
20204 *input_line_pointer
= 0;
20206 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20207 if (streq (opt
->name
, name
))
20209 mfpu_opt
= &opt
->value
;
20210 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20211 *input_line_pointer
= saved_char
;
20212 demand_empty_rest_of_line ();
20216 as_bad (_("unknown floating point format `%s'\n"), name
);
20217 *input_line_pointer
= saved_char
;
20218 ignore_rest_of_line ();