1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
80 /* Bit N indicates that an R_ARM_NONE relocation has been output for
81 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
82 emitted only once per section, to save unnecessary bloat. */
83 static unsigned int marked_pr_dependency
= 0;
87 /* Results from operand parsing worker functions. */
91 PARSE_OPERAND_SUCCESS
,
93 PARSE_OPERAND_FAIL_NO_BACKTRACK
94 } parse_operand_result
;
103 /* Types of processor to assemble for. */
105 #if defined __XSCALE__
106 #define CPU_DEFAULT ARM_ARCH_XSCALE
108 #if defined __thumb__
109 #define CPU_DEFAULT ARM_ARCH_V5T
116 # define FPU_DEFAULT FPU_ARCH_FPA
117 # elif defined (TE_NetBSD)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
121 /* Legacy a.out format. */
122 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
124 # elif defined (TE_VXWORKS)
125 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
127 /* For backwards compatibility, default to FPA. */
128 # define FPU_DEFAULT FPU_ARCH_FPA
130 #endif /* ifndef FPU_DEFAULT */
132 #define streq(a, b) (strcmp (a, b) == 0)
134 static arm_feature_set cpu_variant
;
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
149 /* Variables that we set while parsing command-line options. Once all
150 options have been read we re-process these values to set the real
152 static const arm_feature_set
*legacy_cpu
= NULL
;
153 static const arm_feature_set
*legacy_fpu
= NULL
;
155 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
156 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
157 static const arm_feature_set
*march_cpu_opt
= NULL
;
158 static const arm_feature_set
*march_fpu_opt
= NULL
;
159 static const arm_feature_set
*mfpu_opt
= NULL
;
160 static const arm_feature_set
*object_arch
= NULL
;
162 /* Constants for known architecture features. */
163 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
164 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
165 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
166 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
167 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
168 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
169 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
170 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
171 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
174 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
177 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
178 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
179 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
180 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
181 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
182 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
183 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
184 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
185 static const arm_feature_set arm_ext_v4t_5
=
186 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
187 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
188 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
189 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
190 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
191 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
192 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
193 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
194 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
195 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
196 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
197 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
198 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
199 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
200 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
201 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
202 static const arm_feature_set arm_ext_m
=
203 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
205 static const arm_feature_set arm_arch_any
= ARM_ANY
;
206 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
207 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
208 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
210 static const arm_feature_set arm_cext_iwmmxt2
=
211 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
212 static const arm_feature_set arm_cext_iwmmxt
=
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
214 static const arm_feature_set arm_cext_xscale
=
215 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
216 static const arm_feature_set arm_cext_maverick
=
217 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
218 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
219 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
220 static const arm_feature_set fpu_vfp_ext_v1xd
=
221 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
222 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
223 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
224 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
225 static const arm_feature_set fpu_vfp_ext_d32
=
226 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
227 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
228 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
229 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
230 static const arm_feature_set fpu_neon_fp16
= ARM_FEATURE (0, FPU_NEON_FP16
);
232 static int mfloat_abi_opt
= -1;
233 /* Record user cpu selection for object attributes. */
234 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
235 /* Must be long enough to hold any of the names in arm_cpus. */
236 static char selected_cpu_name
[16];
239 static int meabi_flags
= EABI_DEFAULT
;
241 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
244 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
249 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
254 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
255 symbolS
* GOT_symbol
;
258 /* 0: assemble for ARM,
259 1: assemble for Thumb,
260 2: assemble for Thumb even though target CPU does not support thumb
262 static int thumb_mode
= 0;
263 /* A value distinct from the possible values for thumb_mode that we
264 can use to record whether thumb_mode has been copied into the
265 tc_frag_data field of a frag. */
266 #define MODE_RECORDED (1 << 4)
268 /* Specifies the intrinsic IT insn behavior mode. */
269 enum implicit_it_mode
271 IMPLICIT_IT_MODE_NEVER
= 0x00,
272 IMPLICIT_IT_MODE_ARM
= 0x01,
273 IMPLICIT_IT_MODE_THUMB
= 0x02,
274 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
276 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
278 /* If unified_syntax is true, we are processing the new unified
279 ARM/Thumb syntax. Important differences from the old ARM mode:
281 - Immediate operands do not require a # prefix.
282 - Conditional affixes always appear at the end of the
283 instruction. (For backward compatibility, those instructions
284 that formerly had them in the middle, continue to accept them
286 - The IT instruction may appear, and if it does is validated
287 against subsequent conditional affixes. It does not generate
290 Important differences from the old Thumb mode:
292 - Immediate operands do not require a # prefix.
293 - Most of the V6T2 instructions are only available in unified mode.
294 - The .N and .W suffixes are recognized and honored (it is an error
295 if they cannot be honored).
296 - All instructions set the flags if and only if they have an 's' affix.
297 - Conditional affixes may be used. They are validated against
298 preceding IT instructions. Unlike ARM mode, you cannot use a
299 conditional affix except in the scope of an IT instruction. */
301 static bfd_boolean unified_syntax
= FALSE
;
316 enum neon_el_type type
;
320 #define NEON_MAX_TYPE_ELS 4
324 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
328 enum it_instruction_type
333 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
334 if inside, should be the last one. */
335 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
336 i.e. BKPT and NOP. */
337 IT_INSN
/* The IT insn has been parsed. */
343 unsigned long instruction
;
347 /* "uncond_value" is set to the value in place of the conditional field in
348 unconditional versions of the instruction, or -1 if nothing is
351 struct neon_type vectype
;
352 /* Set to the opcode if the instruction needs relaxation.
353 Zero if the instruction is not relaxed. */
357 bfd_reloc_code_real_type type
;
362 enum it_instruction_type it_insn_type
;
368 struct neon_type_el vectype
;
369 unsigned present
: 1; /* Operand present. */
370 unsigned isreg
: 1; /* Operand was a register. */
371 unsigned immisreg
: 1; /* .imm field is a second register. */
372 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
373 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
374 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
375 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
376 instructions. This allows us to disambiguate ARM <-> vector insns. */
377 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
378 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
379 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
380 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
381 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
382 unsigned writeback
: 1; /* Operand has trailing ! */
383 unsigned preind
: 1; /* Preindexed address. */
384 unsigned postind
: 1; /* Postindexed address. */
385 unsigned negative
: 1; /* Index register was negated. */
386 unsigned shifted
: 1; /* Shift applied to operation. */
387 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
391 static struct arm_it inst
;
393 #define NUM_FLOAT_VALS 8
395 const char * fp_const
[] =
397 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
400 /* Number of littlenums required to hold an extended precision number. */
401 #define MAX_LITTLENUMS 6
403 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
413 #define CP_T_X 0x00008000
414 #define CP_T_Y 0x00400000
416 #define CONDS_BIT 0x00100000
417 #define LOAD_BIT 0x00100000
419 #define DOUBLE_LOAD_FLAG 0x00000001
423 const char * template;
427 #define COND_ALWAYS 0xE
431 const char * template;
435 struct asm_barrier_opt
437 const char * template;
441 /* The bit that distinguishes CPSR and SPSR. */
442 #define SPSR_BIT (1 << 22)
444 /* The individual PSR flag bits. */
445 #define PSR_c (1 << 16)
446 #define PSR_x (1 << 17)
447 #define PSR_s (1 << 18)
448 #define PSR_f (1 << 19)
453 bfd_reloc_code_real_type reloc
;
458 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
459 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
464 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
467 /* Bits for DEFINED field in neon_typed_alias. */
468 #define NTA_HASTYPE 1
469 #define NTA_HASINDEX 2
471 struct neon_typed_alias
473 unsigned char defined
;
475 struct neon_type_el eltype
;
478 /* ARM register categories. This includes coprocessor numbers and various
479 architecture extensions' registers. */
505 /* Structure for a hash table entry for a register.
506 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
507 information which states whether a vector type or index is specified (for a
508 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
512 unsigned char number
;
514 unsigned char builtin
;
515 struct neon_typed_alias
* neon
;
518 /* Diagnostics used when we don't get a register of the expected type. */
519 const char * const reg_expected_msgs
[] =
521 N_("ARM register expected"),
522 N_("bad or missing co-processor number"),
523 N_("co-processor register expected"),
524 N_("FPA register expected"),
525 N_("VFP single precision register expected"),
526 N_("VFP/Neon double precision register expected"),
527 N_("Neon quad precision register expected"),
528 N_("VFP single or double precision register expected"),
529 N_("Neon double or quad precision register expected"),
530 N_("VFP single, double or Neon quad precision register expected"),
531 N_("VFP system register expected"),
532 N_("Maverick MVF register expected"),
533 N_("Maverick MVD register expected"),
534 N_("Maverick MVFX register expected"),
535 N_("Maverick MVDX register expected"),
536 N_("Maverick MVAX register expected"),
537 N_("Maverick DSPSC register expected"),
538 N_("iWMMXt data register expected"),
539 N_("iWMMXt control register expected"),
540 N_("iWMMXt scalar register expected"),
541 N_("XScale accumulator register expected"),
544 /* Some well known registers that we refer to directly elsewhere. */
549 /* ARM instructions take 4bytes in the object file, Thumb instructions
555 /* Basic string to match. */
556 const char * template;
558 /* Parameters to instruction. */
559 unsigned char operands
[8];
561 /* Conditional tag - see opcode_lookup. */
562 unsigned int tag
: 4;
564 /* Basic instruction code. */
565 unsigned int avalue
: 28;
567 /* Thumb-format instruction code. */
570 /* Which architecture variant provides this instruction. */
571 const arm_feature_set
* avariant
;
572 const arm_feature_set
* tvariant
;
574 /* Function to call to encode instruction in ARM format. */
575 void (* aencode
) (void);
577 /* Function to call to encode instruction in Thumb format. */
578 void (* tencode
) (void);
581 /* Defines for various bits that we will want to toggle. */
582 #define INST_IMMEDIATE 0x02000000
583 #define OFFSET_REG 0x02000000
584 #define HWOFFSET_IMM 0x00400000
585 #define SHIFT_BY_REG 0x00000010
586 #define PRE_INDEX 0x01000000
587 #define INDEX_UP 0x00800000
588 #define WRITE_BACK 0x00200000
589 #define LDM_TYPE_2_OR_3 0x00400000
590 #define CPSI_MMOD 0x00020000
592 #define LITERAL_MASK 0xf000f000
593 #define OPCODE_MASK 0xfe1fffff
594 #define V4_STR_BIT 0x00000020
596 #define T2_SUBS_PC_LR 0xf3de8f00
598 #define DATA_OP_SHIFT 21
600 #define T2_OPCODE_MASK 0xfe1fffff
601 #define T2_DATA_OP_SHIFT 21
603 /* Codes to distinguish the arithmetic instructions. */
614 #define OPCODE_CMP 10
615 #define OPCODE_CMN 11
616 #define OPCODE_ORR 12
617 #define OPCODE_MOV 13
618 #define OPCODE_BIC 14
619 #define OPCODE_MVN 15
621 #define T2_OPCODE_AND 0
622 #define T2_OPCODE_BIC 1
623 #define T2_OPCODE_ORR 2
624 #define T2_OPCODE_ORN 3
625 #define T2_OPCODE_EOR 4
626 #define T2_OPCODE_ADD 8
627 #define T2_OPCODE_ADC 10
628 #define T2_OPCODE_SBC 11
629 #define T2_OPCODE_SUB 13
630 #define T2_OPCODE_RSB 14
632 #define T_OPCODE_MUL 0x4340
633 #define T_OPCODE_TST 0x4200
634 #define T_OPCODE_CMN 0x42c0
635 #define T_OPCODE_NEG 0x4240
636 #define T_OPCODE_MVN 0x43c0
638 #define T_OPCODE_ADD_R3 0x1800
639 #define T_OPCODE_SUB_R3 0x1a00
640 #define T_OPCODE_ADD_HI 0x4400
641 #define T_OPCODE_ADD_ST 0xb000
642 #define T_OPCODE_SUB_ST 0xb080
643 #define T_OPCODE_ADD_SP 0xa800
644 #define T_OPCODE_ADD_PC 0xa000
645 #define T_OPCODE_ADD_I8 0x3000
646 #define T_OPCODE_SUB_I8 0x3800
647 #define T_OPCODE_ADD_I3 0x1c00
648 #define T_OPCODE_SUB_I3 0x1e00
650 #define T_OPCODE_ASR_R 0x4100
651 #define T_OPCODE_LSL_R 0x4080
652 #define T_OPCODE_LSR_R 0x40c0
653 #define T_OPCODE_ROR_R 0x41c0
654 #define T_OPCODE_ASR_I 0x1000
655 #define T_OPCODE_LSL_I 0x0000
656 #define T_OPCODE_LSR_I 0x0800
658 #define T_OPCODE_MOV_I8 0x2000
659 #define T_OPCODE_CMP_I8 0x2800
660 #define T_OPCODE_CMP_LR 0x4280
661 #define T_OPCODE_MOV_HR 0x4600
662 #define T_OPCODE_CMP_HR 0x4500
664 #define T_OPCODE_LDR_PC 0x4800
665 #define T_OPCODE_LDR_SP 0x9800
666 #define T_OPCODE_STR_SP 0x9000
667 #define T_OPCODE_LDR_IW 0x6800
668 #define T_OPCODE_STR_IW 0x6000
669 #define T_OPCODE_LDR_IH 0x8800
670 #define T_OPCODE_STR_IH 0x8000
671 #define T_OPCODE_LDR_IB 0x7800
672 #define T_OPCODE_STR_IB 0x7000
673 #define T_OPCODE_LDR_RW 0x5800
674 #define T_OPCODE_STR_RW 0x5000
675 #define T_OPCODE_LDR_RH 0x5a00
676 #define T_OPCODE_STR_RH 0x5200
677 #define T_OPCODE_LDR_RB 0x5c00
678 #define T_OPCODE_STR_RB 0x5400
680 #define T_OPCODE_PUSH 0xb400
681 #define T_OPCODE_POP 0xbc00
683 #define T_OPCODE_BRANCH 0xe000
685 #define THUMB_SIZE 2 /* Size of thumb instruction. */
686 #define THUMB_PP_PC_LR 0x0100
687 #define THUMB_LOAD_BIT 0x0800
688 #define THUMB2_LOAD_BIT 0x00100000
690 #define BAD_ARGS _("bad arguments to instruction")
691 #define BAD_SP _("r13 not allowed here")
692 #define BAD_PC _("r15 not allowed here")
693 #define BAD_COND _("instruction cannot be conditional")
694 #define BAD_OVERLAP _("registers may not be the same")
695 #define BAD_HIREG _("lo register required")
696 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
697 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
698 #define BAD_BRANCH _("branch must be last instruction in IT block")
699 #define BAD_NOT_IT _("instruction not allowed in IT block")
700 #define BAD_FPU _("selected FPU does not support instruction")
701 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
702 #define BAD_IT_COND _("incorrect condition in IT block")
703 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
704 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
706 static struct hash_control
* arm_ops_hsh
;
707 static struct hash_control
* arm_cond_hsh
;
708 static struct hash_control
* arm_shift_hsh
;
709 static struct hash_control
* arm_psr_hsh
;
710 static struct hash_control
* arm_v7m_psr_hsh
;
711 static struct hash_control
* arm_reg_hsh
;
712 static struct hash_control
* arm_reloc_hsh
;
713 static struct hash_control
* arm_barrier_opt_hsh
;
715 /* Stuff needed to resolve the label ambiguity
724 symbolS
* last_label_seen
;
725 static int label_is_thumb_function_name
= FALSE
;
727 /* Literal pool structure. Held on a per-section
728 and per-sub-section basis. */
730 #define MAX_LITERAL_POOL_SIZE 1024
731 typedef struct literal_pool
733 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
734 unsigned int next_free_entry
;
739 struct literal_pool
* next
;
742 /* Pointer to a linked list of literal pools. */
743 literal_pool
* list_of_pools
= NULL
;
746 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
748 static struct current_it now_it
;
752 now_it_compatible (int cond
)
754 return (cond
& ~1) == (now_it
.cc
& ~1);
758 conditional_insn (void)
760 return inst
.cond
!= COND_ALWAYS
;
763 static int in_it_block (void);
765 static int handle_it_state (void);
767 static void force_automatic_it_block_close (void);
769 static void it_fsm_post_encode (void);
771 #define set_it_insn_type(type) \
774 inst.it_insn_type = type; \
775 if (handle_it_state () == FAIL) \
780 #define set_it_insn_type_nonvoid(type, failret) \
783 inst.it_insn_type = type; \
784 if (handle_it_state () == FAIL) \
789 #define set_it_insn_type_last() \
792 if (inst.cond == COND_ALWAYS) \
793 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
795 set_it_insn_type (INSIDE_IT_LAST_INSN); \
801 /* This array holds the chars that always start a comment. If the
802 pre-processor is disabled, these aren't very useful. */
803 const char comment_chars
[] = "@";
805 /* This array holds the chars that only start a comment at the beginning of
806 a line. If the line seems to have the form '# 123 filename'
807 .line and .file directives will appear in the pre-processed output. */
808 /* Note that input_file.c hand checks for '#' at the beginning of the
809 first line of the input file. This is because the compiler outputs
810 #NO_APP at the beginning of its output. */
811 /* Also note that comments like this one will always work. */
812 const char line_comment_chars
[] = "#";
814 const char line_separator_chars
[] = ";";
816 /* Chars that can be used to separate mant
817 from exp in floating point numbers. */
818 const char EXP_CHARS
[] = "eE";
820 /* Chars that mean this number is a floating point constant. */
824 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
826 /* Prefix characters that indicate the start of an immediate
828 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
830 /* Separator character handling. */
832 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
835 skip_past_char (char ** str
, char c
)
846 #define skip_past_comma(str) skip_past_char (str, ',')
848 /* Arithmetic expressions (possibly involving symbols). */
850 /* Return TRUE if anything in the expression is a bignum. */
853 walk_no_bignums (symbolS
* sp
)
855 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
858 if (symbol_get_value_expression (sp
)->X_add_symbol
)
860 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
861 || (symbol_get_value_expression (sp
)->X_op_symbol
862 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
868 static int in_my_get_expression
= 0;
870 /* Third argument to my_get_expression. */
871 #define GE_NO_PREFIX 0
872 #define GE_IMM_PREFIX 1
873 #define GE_OPT_PREFIX 2
874 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
875 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
876 #define GE_OPT_PREFIX_BIG 3
879 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
884 /* In unified syntax, all prefixes are optional. */
886 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
891 case GE_NO_PREFIX
: break;
893 if (!is_immediate_prefix (**str
))
895 inst
.error
= _("immediate expression requires a # prefix");
901 case GE_OPT_PREFIX_BIG
:
902 if (is_immediate_prefix (**str
))
908 memset (ep
, 0, sizeof (expressionS
));
910 save_in
= input_line_pointer
;
911 input_line_pointer
= *str
;
912 in_my_get_expression
= 1;
913 seg
= expression (ep
);
914 in_my_get_expression
= 0;
916 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
918 /* We found a bad or missing expression in md_operand(). */
919 *str
= input_line_pointer
;
920 input_line_pointer
= save_in
;
921 if (inst
.error
== NULL
)
922 inst
.error
= (ep
->X_op
== O_absent
923 ? _("missing expression") :_("bad expression"));
928 if (seg
!= absolute_section
929 && seg
!= text_section
930 && seg
!= data_section
931 && seg
!= bss_section
932 && seg
!= undefined_section
)
934 inst
.error
= _("bad segment");
935 *str
= input_line_pointer
;
936 input_line_pointer
= save_in
;
941 /* Get rid of any bignums now, so that we don't generate an error for which
942 we can't establish a line number later on. Big numbers are never valid
943 in instructions, which is where this routine is always called. */
944 if (prefix_mode
!= GE_OPT_PREFIX_BIG
945 && (ep
->X_op
== O_big
947 && (walk_no_bignums (ep
->X_add_symbol
)
949 && walk_no_bignums (ep
->X_op_symbol
))))))
951 inst
.error
= _("invalid constant");
952 *str
= input_line_pointer
;
953 input_line_pointer
= save_in
;
957 *str
= input_line_pointer
;
958 input_line_pointer
= save_in
;
962 /* Turn a string in input_line_pointer into a floating point constant
963 of type TYPE, and store the appropriate bytes in *LITP. The number
964 of LITTLENUMS emitted is stored in *SIZEP. An error message is
965 returned, or NULL on OK.
967 Note that fp constants aren't represent in the normal way on the ARM.
968 In big endian mode, things are as expected. However, in little endian
969 mode fp constants are big-endian word-wise, and little-endian byte-wise
970 within the words. For example, (double) 1.1 in big endian mode is
971 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
972 the byte sequence 99 99 f1 3f 9a 99 99 99.
974 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
977 md_atof (int type
, char * litP
, int * sizeP
)
980 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1012 return _("Unrecognized or unsupported floating point constant");
1015 t
= atof_ieee (input_line_pointer
, type
, words
);
1017 input_line_pointer
= t
;
1018 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1020 if (target_big_endian
)
1022 for (i
= 0; i
< prec
; i
++)
1024 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1025 litP
+= sizeof (LITTLENUM_TYPE
);
1030 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1031 for (i
= prec
- 1; i
>= 0; i
--)
1033 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1034 litP
+= sizeof (LITTLENUM_TYPE
);
1037 /* For a 4 byte float the order of elements in `words' is 1 0.
1038 For an 8 byte float the order is 1 0 3 2. */
1039 for (i
= 0; i
< prec
; i
+= 2)
1041 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1042 sizeof (LITTLENUM_TYPE
));
1043 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1044 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1045 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1052 /* We handle all bad expressions here, so that we can report the faulty
1053 instruction in the error message. */
1055 md_operand (expressionS
* expr
)
1057 if (in_my_get_expression
)
1058 expr
->X_op
= O_illegal
;
1061 /* Immediate values. */
1063 /* Generic immediate-value read function for use in directives.
1064 Accepts anything that 'expression' can fold to a constant.
1065 *val receives the number. */
1068 immediate_for_directive (int *val
)
1071 exp
.X_op
= O_illegal
;
1073 if (is_immediate_prefix (*input_line_pointer
))
1075 input_line_pointer
++;
1079 if (exp
.X_op
!= O_constant
)
1081 as_bad (_("expected #constant"));
1082 ignore_rest_of_line ();
1085 *val
= exp
.X_add_number
;
1090 /* Register parsing. */
1092 /* Generic register parser. CCP points to what should be the
1093 beginning of a register name. If it is indeed a valid register
1094 name, advance CCP over it and return the reg_entry structure;
1095 otherwise return NULL. Does not issue diagnostics. */
1097 static struct reg_entry
*
1098 arm_reg_parse_multi (char **ccp
)
1102 struct reg_entry
*reg
;
1104 #ifdef REGISTER_PREFIX
1105 if (*start
!= REGISTER_PREFIX
)
1109 #ifdef OPTIONAL_REGISTER_PREFIX
1110 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1115 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1120 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1122 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1132 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1133 enum arm_reg_type type
)
1135 /* Alternative syntaxes are accepted for a few register classes. */
1142 /* Generic coprocessor register names are allowed for these. */
1143 if (reg
&& reg
->type
== REG_TYPE_CN
)
1148 /* For backward compatibility, a bare number is valid here. */
1150 unsigned long processor
= strtoul (start
, ccp
, 10);
1151 if (*ccp
!= start
&& processor
<= 15)
1155 case REG_TYPE_MMXWC
:
1156 /* WC includes WCG. ??? I'm not sure this is true for all
1157 instructions that take WC registers. */
1158 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1169 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1170 return value is the register number or FAIL. */
1173 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1176 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1179 /* Do not allow a scalar (reg+index) to parse as a register. */
1180 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1183 if (reg
&& reg
->type
== type
)
1186 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1193 /* Parse a Neon type specifier. *STR should point at the leading '.'
1194 character. Does no verification at this stage that the type fits the opcode
1201 Can all be legally parsed by this function.
1203 Fills in neon_type struct pointer with parsed information, and updates STR
1204 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1205 type, FAIL if not. */
1208 parse_neon_type (struct neon_type
*type
, char **str
)
1215 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1217 enum neon_el_type thistype
= NT_untyped
;
1218 unsigned thissize
= -1u;
1225 /* Just a size without an explicit type. */
1229 switch (TOLOWER (*ptr
))
1231 case 'i': thistype
= NT_integer
; break;
1232 case 'f': thistype
= NT_float
; break;
1233 case 'p': thistype
= NT_poly
; break;
1234 case 's': thistype
= NT_signed
; break;
1235 case 'u': thistype
= NT_unsigned
; break;
1237 thistype
= NT_float
;
1242 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1248 /* .f is an abbreviation for .f32. */
1249 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1254 thissize
= strtoul (ptr
, &ptr
, 10);
1256 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1259 as_bad (_("bad size %d in type specifier"), thissize
);
1267 type
->el
[type
->elems
].type
= thistype
;
1268 type
->el
[type
->elems
].size
= thissize
;
1273 /* Empty/missing type is not a successful parse. */
1274 if (type
->elems
== 0)
1282 /* Errors may be set multiple times during parsing or bit encoding
1283 (particularly in the Neon bits), but usually the earliest error which is set
1284 will be the most meaningful. Avoid overwriting it with later (cascading)
1285 errors by calling this function. */
1288 first_error (const char *err
)
1294 /* Parse a single type, e.g. ".s32", leading period included. */
1296 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1299 struct neon_type optype
;
1303 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1305 if (optype
.elems
== 1)
1306 *vectype
= optype
.el
[0];
1309 first_error (_("only one type should be specified for operand"));
1315 first_error (_("vector type expected"));
1327 /* Special meanings for indices (which have a range of 0-7), which will fit into
1330 #define NEON_ALL_LANES 15
1331 #define NEON_INTERLEAVE_LANES 14
1333 /* Parse either a register or a scalar, with an optional type. Return the
1334 register number, and optionally fill in the actual type of the register
1335 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1336 type/index information in *TYPEINFO. */
1339 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1340 enum arm_reg_type
*rtype
,
1341 struct neon_typed_alias
*typeinfo
)
1344 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1345 struct neon_typed_alias atype
;
1346 struct neon_type_el parsetype
;
1350 atype
.eltype
.type
= NT_invtype
;
1351 atype
.eltype
.size
= -1;
1353 /* Try alternate syntax for some types of register. Note these are mutually
1354 exclusive with the Neon syntax extensions. */
1357 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1365 /* Undo polymorphism when a set of register types may be accepted. */
1366 if ((type
== REG_TYPE_NDQ
1367 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1368 || (type
== REG_TYPE_VFSD
1369 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1370 || (type
== REG_TYPE_NSDQ
1371 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1372 || reg
->type
== REG_TYPE_NQ
))
1373 || (type
== REG_TYPE_MMXWC
1374 && (reg
->type
== REG_TYPE_MMXWCG
)))
1377 if (type
!= reg
->type
)
1383 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1385 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1387 first_error (_("can't redefine type for operand"));
1390 atype
.defined
|= NTA_HASTYPE
;
1391 atype
.eltype
= parsetype
;
1394 if (skip_past_char (&str
, '[') == SUCCESS
)
1396 if (type
!= REG_TYPE_VFD
)
1398 first_error (_("only D registers may be indexed"));
1402 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1404 first_error (_("can't change index for operand"));
1408 atype
.defined
|= NTA_HASINDEX
;
1410 if (skip_past_char (&str
, ']') == SUCCESS
)
1411 atype
.index
= NEON_ALL_LANES
;
1416 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1418 if (exp
.X_op
!= O_constant
)
1420 first_error (_("constant expression required"));
1424 if (skip_past_char (&str
, ']') == FAIL
)
1427 atype
.index
= exp
.X_add_number
;
1442 /* Like arm_reg_parse, but allow allow the following extra features:
1443 - If RTYPE is non-zero, return the (possibly restricted) type of the
1444 register (e.g. Neon double or quad reg when either has been requested).
1445 - If this is a Neon vector type with additional type information, fill
1446 in the struct pointed to by VECTYPE (if non-NULL).
1447 This function will fault on encountering a scalar. */
1450 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1451 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1453 struct neon_typed_alias atype
;
1455 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1460 /* Do not allow a scalar (reg+index) to parse as a register. */
1461 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1463 first_error (_("register operand expected, but got scalar"));
1468 *vectype
= atype
.eltype
;
1475 #define NEON_SCALAR_REG(X) ((X) >> 4)
1476 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1478 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1479 have enough information to be able to do a good job bounds-checking. So, we
1480 just do easy checks here, and do further checks later. */
1483 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1487 struct neon_typed_alias atype
;
1489 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1491 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1494 if (atype
.index
== NEON_ALL_LANES
)
1496 first_error (_("scalar must have an index"));
1499 else if (atype
.index
>= 64 / elsize
)
1501 first_error (_("scalar index out of range"));
1506 *type
= atype
.eltype
;
1510 return reg
* 16 + atype
.index
;
1513 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1516 parse_reg_list (char ** strp
)
1518 char * str
= * strp
;
1522 /* We come back here if we get ranges concatenated by '+' or '|'. */
1537 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1539 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1549 first_error (_("bad range in register list"));
1553 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1555 if (range
& (1 << i
))
1557 (_("Warning: duplicated register (r%d) in register list"),
1565 if (range
& (1 << reg
))
1566 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1568 else if (reg
<= cur_reg
)
1569 as_tsktsk (_("Warning: register range not in ascending order"));
1574 while (skip_past_comma (&str
) != FAIL
1575 || (in_range
= 1, *str
++ == '-'));
1580 first_error (_("missing `}'"));
1588 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1591 if (expr
.X_op
== O_constant
)
1593 if (expr
.X_add_number
1594 != (expr
.X_add_number
& 0x0000ffff))
1596 inst
.error
= _("invalid register mask");
1600 if ((range
& expr
.X_add_number
) != 0)
1602 int regno
= range
& expr
.X_add_number
;
1605 regno
= (1 << regno
) - 1;
1607 (_("Warning: duplicated register (r%d) in register list"),
1611 range
|= expr
.X_add_number
;
1615 if (inst
.reloc
.type
!= 0)
1617 inst
.error
= _("expression too complex");
1621 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1622 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1623 inst
.reloc
.pc_rel
= 0;
1627 if (*str
== '|' || *str
== '+')
1633 while (another_range
);
1639 /* Types of registers in a list. */
1648 /* Parse a VFP register list. If the string is invalid return FAIL.
1649 Otherwise return the number of registers, and set PBASE to the first
1650 register. Parses registers of type ETYPE.
1651 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1652 - Q registers can be used to specify pairs of D registers
1653 - { } can be omitted from around a singleton register list
1654 FIXME: This is not implemented, as it would require backtracking in
1657 This could be done (the meaning isn't really ambiguous), but doesn't
1658 fit in well with the current parsing framework.
1659 - 32 D registers may be used (also true for VFPv3).
1660 FIXME: Types are ignored in these register lists, which is probably a
1664 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1669 enum arm_reg_type regtype
= 0;
1673 unsigned long mask
= 0;
1678 inst
.error
= _("expecting {");
1687 regtype
= REG_TYPE_VFS
;
1692 regtype
= REG_TYPE_VFD
;
1695 case REGLIST_NEON_D
:
1696 regtype
= REG_TYPE_NDQ
;
1700 if (etype
!= REGLIST_VFP_S
)
1702 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1703 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1707 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1710 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1717 base_reg
= max_regs
;
1721 int setmask
= 1, addregs
= 1;
1723 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1725 if (new_base
== FAIL
)
1727 first_error (_(reg_expected_msgs
[regtype
]));
1731 if (new_base
>= max_regs
)
1733 first_error (_("register out of range in list"));
1737 /* Note: a value of 2 * n is returned for the register Q<n>. */
1738 if (regtype
== REG_TYPE_NQ
)
1744 if (new_base
< base_reg
)
1745 base_reg
= new_base
;
1747 if (mask
& (setmask
<< new_base
))
1749 first_error (_("invalid register list"));
1753 if ((mask
>> new_base
) != 0 && ! warned
)
1755 as_tsktsk (_("register list not in ascending order"));
1759 mask
|= setmask
<< new_base
;
1762 if (*str
== '-') /* We have the start of a range expression */
1768 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1771 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1775 if (high_range
>= max_regs
)
1777 first_error (_("register out of range in list"));
1781 if (regtype
== REG_TYPE_NQ
)
1782 high_range
= high_range
+ 1;
1784 if (high_range
<= new_base
)
1786 inst
.error
= _("register range not in ascending order");
1790 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1792 if (mask
& (setmask
<< new_base
))
1794 inst
.error
= _("invalid register list");
1798 mask
|= setmask
<< new_base
;
1803 while (skip_past_comma (&str
) != FAIL
);
1807 /* Sanity check -- should have raised a parse error above. */
1808 if (count
== 0 || count
> max_regs
)
1813 /* Final test -- the registers must be consecutive. */
1815 for (i
= 0; i
< count
; i
++)
1817 if ((mask
& (1u << i
)) == 0)
1819 inst
.error
= _("non-contiguous register range");
1829 /* True if two alias types are the same. */
1832 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1840 if (a
->defined
!= b
->defined
)
1843 if ((a
->defined
& NTA_HASTYPE
) != 0
1844 && (a
->eltype
.type
!= b
->eltype
.type
1845 || a
->eltype
.size
!= b
->eltype
.size
))
1848 if ((a
->defined
& NTA_HASINDEX
) != 0
1849 && (a
->index
!= b
->index
))
1855 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1856 The base register is put in *PBASE.
1857 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1859 The register stride (minus one) is put in bit 4 of the return value.
1860 Bits [6:5] encode the list length (minus one).
1861 The type of the list elements is put in *ELTYPE, if non-NULL. */
1863 #define NEON_LANE(X) ((X) & 0xf)
1864 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1865 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1868 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1869 struct neon_type_el
*eltype
)
1876 int leading_brace
= 0;
1877 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1879 const char *const incr_error
= _("register stride must be 1 or 2");
1880 const char *const type_error
= _("mismatched element/structure types in list");
1881 struct neon_typed_alias firsttype
;
1883 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1888 struct neon_typed_alias atype
;
1889 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1893 first_error (_(reg_expected_msgs
[rtype
]));
1900 if (rtype
== REG_TYPE_NQ
)
1907 else if (reg_incr
== -1)
1909 reg_incr
= getreg
- base_reg
;
1910 if (reg_incr
< 1 || reg_incr
> 2)
1912 first_error (_(incr_error
));
1916 else if (getreg
!= base_reg
+ reg_incr
* count
)
1918 first_error (_(incr_error
));
1922 if (! neon_alias_types_same (&atype
, &firsttype
))
1924 first_error (_(type_error
));
1928 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1932 struct neon_typed_alias htype
;
1933 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1935 lane
= NEON_INTERLEAVE_LANES
;
1936 else if (lane
!= NEON_INTERLEAVE_LANES
)
1938 first_error (_(type_error
));
1943 else if (reg_incr
!= 1)
1945 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1949 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1952 first_error (_(reg_expected_msgs
[rtype
]));
1955 if (! neon_alias_types_same (&htype
, &firsttype
))
1957 first_error (_(type_error
));
1960 count
+= hireg
+ dregs
- getreg
;
1964 /* If we're using Q registers, we can't use [] or [n] syntax. */
1965 if (rtype
== REG_TYPE_NQ
)
1971 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1975 else if (lane
!= atype
.index
)
1977 first_error (_(type_error
));
1981 else if (lane
== -1)
1982 lane
= NEON_INTERLEAVE_LANES
;
1983 else if (lane
!= NEON_INTERLEAVE_LANES
)
1985 first_error (_(type_error
));
1990 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1992 /* No lane set by [x]. We must be interleaving structures. */
1994 lane
= NEON_INTERLEAVE_LANES
;
1997 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1998 || (count
> 1 && reg_incr
== -1))
2000 first_error (_("error parsing element/structure list"));
2004 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2006 first_error (_("expected }"));
2014 *eltype
= firsttype
.eltype
;
2019 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2022 /* Parse an explicit relocation suffix on an expression. This is
2023 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2024 arm_reloc_hsh contains no entries, so this function can only
2025 succeed if there is no () after the word. Returns -1 on error,
2026 BFD_RELOC_UNUSED if there wasn't any suffix. */
2028 parse_reloc (char **str
)
2030 struct reloc_entry
*r
;
2034 return BFD_RELOC_UNUSED
;
2039 while (*q
&& *q
!= ')' && *q
!= ',')
2044 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2051 /* Directives: register aliases. */
2053 static struct reg_entry
*
2054 insert_reg_alias (char *str
, int number
, int type
)
2056 struct reg_entry
*new;
2059 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
2062 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2064 /* Only warn about a redefinition if it's not defined as the
2066 else if (new->number
!= number
|| new->type
!= type
)
2067 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2072 name
= xstrdup (str
);
2073 new = xmalloc (sizeof (struct reg_entry
));
2076 new->number
= number
;
2078 new->builtin
= FALSE
;
2081 if (hash_insert (arm_reg_hsh
, name
, (void *) new))
2088 insert_neon_reg_alias (char *str
, int number
, int type
,
2089 struct neon_typed_alias
*atype
)
2091 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2095 first_error (_("attempt to redefine typed alias"));
2101 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
2102 *reg
->neon
= *atype
;
2106 /* Look for the .req directive. This is of the form:
2108 new_register_name .req existing_register_name
2110 If we find one, or if it looks sufficiently like one that we want to
2111 handle any error here, return TRUE. Otherwise return FALSE. */
2114 create_register_alias (char * newname
, char *p
)
2116 struct reg_entry
*old
;
2117 char *oldname
, *nbuf
;
2120 /* The input scrubber ensures that whitespace after the mnemonic is
2121 collapsed to single spaces. */
2123 if (strncmp (oldname
, " .req ", 6) != 0)
2127 if (*oldname
== '\0')
2130 old
= hash_find (arm_reg_hsh
, oldname
);
2133 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2137 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2138 the desired alias name, and p points to its end. If not, then
2139 the desired alias name is in the global original_case_string. */
2140 #ifdef TC_CASE_SENSITIVE
2143 newname
= original_case_string
;
2144 nlen
= strlen (newname
);
2147 nbuf
= alloca (nlen
+ 1);
2148 memcpy (nbuf
, newname
, nlen
);
2151 /* Create aliases under the new name as stated; an all-lowercase
2152 version of the new name; and an all-uppercase version of the new
2154 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2156 for (p
= nbuf
; *p
; p
++)
2159 if (strncmp (nbuf
, newname
, nlen
))
2161 /* If this attempt to create an additional alias fails, do not bother
2162 trying to create the all-lower case alias. We will fail and issue
2163 a second, duplicate error message. This situation arises when the
2164 programmer does something like:
2167 The second .req creates the "Foo" alias but then fails to create
2168 the artificial FOO alias because it has already been created by the
2170 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2174 for (p
= nbuf
; *p
; p
++)
2177 if (strncmp (nbuf
, newname
, nlen
))
2178 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2184 /* Create a Neon typed/indexed register alias using directives, e.g.:
2189 These typed registers can be used instead of the types specified after the
2190 Neon mnemonic, so long as all operands given have types. Types can also be
2191 specified directly, e.g.:
2192 vadd d0.s32, d1.s32, d2.s32 */
2195 create_neon_reg_alias (char *newname
, char *p
)
2197 enum arm_reg_type basetype
;
2198 struct reg_entry
*basereg
;
2199 struct reg_entry mybasereg
;
2200 struct neon_type ntype
;
2201 struct neon_typed_alias typeinfo
;
2202 char *namebuf
, *nameend
;
2205 typeinfo
.defined
= 0;
2206 typeinfo
.eltype
.type
= NT_invtype
;
2207 typeinfo
.eltype
.size
= -1;
2208 typeinfo
.index
= -1;
2212 if (strncmp (p
, " .dn ", 5) == 0)
2213 basetype
= REG_TYPE_VFD
;
2214 else if (strncmp (p
, " .qn ", 5) == 0)
2215 basetype
= REG_TYPE_NQ
;
2224 basereg
= arm_reg_parse_multi (&p
);
2226 if (basereg
&& basereg
->type
!= basetype
)
2228 as_bad (_("bad type for register"));
2232 if (basereg
== NULL
)
2235 /* Try parsing as an integer. */
2236 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2237 if (exp
.X_op
!= O_constant
)
2239 as_bad (_("expression must be constant"));
2242 basereg
= &mybasereg
;
2243 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2249 typeinfo
= *basereg
->neon
;
2251 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2253 /* We got a type. */
2254 if (typeinfo
.defined
& NTA_HASTYPE
)
2256 as_bad (_("can't redefine the type of a register alias"));
2260 typeinfo
.defined
|= NTA_HASTYPE
;
2261 if (ntype
.elems
!= 1)
2263 as_bad (_("you must specify a single type only"));
2266 typeinfo
.eltype
= ntype
.el
[0];
2269 if (skip_past_char (&p
, '[') == SUCCESS
)
2272 /* We got a scalar index. */
2274 if (typeinfo
.defined
& NTA_HASINDEX
)
2276 as_bad (_("can't redefine the index of a scalar alias"));
2280 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2282 if (exp
.X_op
!= O_constant
)
2284 as_bad (_("scalar index must be constant"));
2288 typeinfo
.defined
|= NTA_HASINDEX
;
2289 typeinfo
.index
= exp
.X_add_number
;
2291 if (skip_past_char (&p
, ']') == FAIL
)
2293 as_bad (_("expecting ]"));
2298 namelen
= nameend
- newname
;
2299 namebuf
= alloca (namelen
+ 1);
2300 strncpy (namebuf
, newname
, namelen
);
2301 namebuf
[namelen
] = '\0';
2303 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2304 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2306 /* Insert name in all uppercase. */
2307 for (p
= namebuf
; *p
; p
++)
2310 if (strncmp (namebuf
, newname
, namelen
))
2311 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2312 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2314 /* Insert name in all lowercase. */
2315 for (p
= namebuf
; *p
; p
++)
2318 if (strncmp (namebuf
, newname
, namelen
))
2319 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2320 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2325 /* Should never be called, as .req goes between the alias and the
2326 register name, not at the beginning of the line. */
2329 s_req (int a ATTRIBUTE_UNUSED
)
2331 as_bad (_("invalid syntax for .req directive"));
2335 s_dn (int a ATTRIBUTE_UNUSED
)
2337 as_bad (_("invalid syntax for .dn directive"));
2341 s_qn (int a ATTRIBUTE_UNUSED
)
2343 as_bad (_("invalid syntax for .qn directive"));
2346 /* The .unreq directive deletes an alias which was previously defined
2347 by .req. For example:
2353 s_unreq (int a ATTRIBUTE_UNUSED
)
2358 name
= input_line_pointer
;
2360 while (*input_line_pointer
!= 0
2361 && *input_line_pointer
!= ' '
2362 && *input_line_pointer
!= '\n')
2363 ++input_line_pointer
;
2365 saved_char
= *input_line_pointer
;
2366 *input_line_pointer
= 0;
2369 as_bad (_("invalid syntax for .unreq directive"));
2372 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2375 as_bad (_("unknown register alias '%s'"), name
);
2376 else if (reg
->builtin
)
2377 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2384 hash_delete (arm_reg_hsh
, name
, FALSE
);
2385 free ((char *) reg
->name
);
2390 /* Also locate the all upper case and all lower case versions.
2391 Do not complain if we cannot find one or the other as it
2392 was probably deleted above. */
2394 nbuf
= strdup (name
);
2395 for (p
= nbuf
; *p
; p
++)
2397 reg
= hash_find (arm_reg_hsh
, nbuf
);
2400 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2401 free ((char *) reg
->name
);
2407 for (p
= nbuf
; *p
; p
++)
2409 reg
= hash_find (arm_reg_hsh
, nbuf
);
2412 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2413 free ((char *) reg
->name
);
2423 *input_line_pointer
= saved_char
;
2424 demand_empty_rest_of_line ();
2427 /* Directives: Instruction set selection. */
2430 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2431 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2432 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2433 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2435 static enum mstate mapstate
= MAP_UNDEFINED
;
2437 /* Create a new mapping symbol for the transition to STATE. */
2440 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2443 const char * symname
;
2450 type
= BSF_NO_FLAGS
;
2454 type
= BSF_NO_FLAGS
;
2458 type
= BSF_NO_FLAGS
;
2464 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2465 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2470 THUMB_SET_FUNC (symbolP
, 0);
2471 ARM_SET_THUMB (symbolP
, 0);
2472 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2476 THUMB_SET_FUNC (symbolP
, 1);
2477 ARM_SET_THUMB (symbolP
, 1);
2478 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2486 /* Save the mapping symbols for future reference. Also check that
2487 we do not place two mapping symbols at the same offset within a
2488 frag. We'll handle overlap between frags in
2489 check_mapping_symbols. */
2492 know (frag
->tc_frag_data
.first_map
== NULL
);
2493 frag
->tc_frag_data
.first_map
= symbolP
;
2495 if (frag
->tc_frag_data
.last_map
!= NULL
)
2496 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) < S_GET_VALUE (symbolP
));
2497 frag
->tc_frag_data
.last_map
= symbolP
;
2500 /* We must sometimes convert a region marked as code to data during
2501 code alignment, if an odd number of bytes have to be padded. The
2502 code mapping symbol is pushed to an aligned address. */
2505 insert_data_mapping_symbol (enum mstate state
,
2506 valueT value
, fragS
*frag
, offsetT bytes
)
2508 /* If there was already a mapping symbol, remove it. */
2509 if (frag
->tc_frag_data
.last_map
!= NULL
2510 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2512 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2516 know (frag
->tc_frag_data
.first_map
== symp
);
2517 frag
->tc_frag_data
.first_map
= NULL
;
2519 frag
->tc_frag_data
.last_map
= NULL
;
2520 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2523 make_mapping_symbol (MAP_DATA
, value
, frag
);
2524 make_mapping_symbol (state
, value
+ bytes
, frag
);
2527 static void mapping_state_2 (enum mstate state
, int max_chars
);
2529 /* Set the mapping state to STATE. Only call this when about to
2530 emit some STATE bytes to the file. */
2533 mapping_state (enum mstate state
)
2535 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2537 if (mapstate
== state
)
2538 /* The mapping symbol has already been emitted.
2539 There is nothing else to do. */
2541 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2542 /* This case will be evaluated later in the next else. */
2544 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2545 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2547 /* Only add the symbol if the offset is > 0:
2548 if we're at the first frag, check it's size > 0;
2549 if we're not at the first frag, then for sure
2550 the offset is > 0. */
2551 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2552 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2555 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2558 mapping_state_2 (state
, 0);
2562 /* Same as mapping_state, but MAX_CHARS bytes have already been
2563 allocated. Put the mapping symbol that far back. */
2566 mapping_state_2 (enum mstate state
, int max_chars
)
2568 if (mapstate
== state
)
2569 /* The mapping symbol has already been emitted.
2570 There is nothing else to do. */
2574 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2575 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2578 #define mapping_state(x) /* nothing */
2579 #define mapping_state_2(x, y) /* nothing */
2582 /* Find the real, Thumb encoded start of a Thumb function. */
2586 find_real_start (symbolS
* symbolP
)
2589 const char * name
= S_GET_NAME (symbolP
);
2590 symbolS
* new_target
;
2592 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2593 #define STUB_NAME ".real_start_of"
2598 /* The compiler may generate BL instructions to local labels because
2599 it needs to perform a branch to a far away location. These labels
2600 do not have a corresponding ".real_start_of" label. We check
2601 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2602 the ".real_start_of" convention for nonlocal branches. */
2603 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2606 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2607 new_target
= symbol_find (real_start
);
2609 if (new_target
== NULL
)
2611 as_warn (_("Failed to find real start of function: %s\n"), name
);
2612 new_target
= symbolP
;
2620 opcode_select (int width
)
2627 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2628 as_bad (_("selected processor does not support THUMB opcodes"));
2631 /* No need to force the alignment, since we will have been
2632 coming from ARM mode, which is word-aligned. */
2633 record_alignment (now_seg
, 1);
2640 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2641 as_bad (_("selected processor does not support ARM opcodes"));
2646 frag_align (2, 0, 0);
2648 record_alignment (now_seg
, 1);
2653 as_bad (_("invalid instruction size selected (%d)"), width
);
2658 s_arm (int ignore ATTRIBUTE_UNUSED
)
2661 demand_empty_rest_of_line ();
2665 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2668 demand_empty_rest_of_line ();
2672 s_code (int unused ATTRIBUTE_UNUSED
)
2676 temp
= get_absolute_expression ();
2681 opcode_select (temp
);
2685 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2690 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2692 /* If we are not already in thumb mode go into it, EVEN if
2693 the target processor does not support thumb instructions.
2694 This is used by gcc/config/arm/lib1funcs.asm for example
2695 to compile interworking support functions even if the
2696 target processor should not support interworking. */
2700 record_alignment (now_seg
, 1);
2703 demand_empty_rest_of_line ();
2707 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2711 /* The following label is the name/address of the start of a Thumb function.
2712 We need to know this for the interworking support. */
2713 label_is_thumb_function_name
= TRUE
;
2716 /* Perform a .set directive, but also mark the alias as
2717 being a thumb function. */
2720 s_thumb_set (int equiv
)
2722 /* XXX the following is a duplicate of the code for s_set() in read.c
2723 We cannot just call that code as we need to get at the symbol that
2730 /* Especial apologies for the random logic:
2731 This just grew, and could be parsed much more simply!
2733 name
= input_line_pointer
;
2734 delim
= get_symbol_end ();
2735 end_name
= input_line_pointer
;
2738 if (*input_line_pointer
!= ',')
2741 as_bad (_("expected comma after name \"%s\""), name
);
2743 ignore_rest_of_line ();
2747 input_line_pointer
++;
2750 if (name
[0] == '.' && name
[1] == '\0')
2752 /* XXX - this should not happen to .thumb_set. */
2756 if ((symbolP
= symbol_find (name
)) == NULL
2757 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2760 /* When doing symbol listings, play games with dummy fragments living
2761 outside the normal fragment chain to record the file and line info
2763 if (listing
& LISTING_SYMBOLS
)
2765 extern struct list_info_struct
* listing_tail
;
2766 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2768 memset (dummy_frag
, 0, sizeof (fragS
));
2769 dummy_frag
->fr_type
= rs_fill
;
2770 dummy_frag
->line
= listing_tail
;
2771 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2772 dummy_frag
->fr_symbol
= symbolP
;
2776 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2779 /* "set" symbols are local unless otherwise specified. */
2780 SF_SET_LOCAL (symbolP
);
2781 #endif /* OBJ_COFF */
2782 } /* Make a new symbol. */
2784 symbol_table_insert (symbolP
);
2789 && S_IS_DEFINED (symbolP
)
2790 && S_GET_SEGMENT (symbolP
) != reg_section
)
2791 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2793 pseudo_set (symbolP
);
2795 demand_empty_rest_of_line ();
2797 /* XXX Now we come to the Thumb specific bit of code. */
2799 THUMB_SET_FUNC (symbolP
, 1);
2800 ARM_SET_THUMB (symbolP
, 1);
2801 #if defined OBJ_ELF || defined OBJ_COFF
2802 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2806 /* Directives: Mode selection. */
2808 /* .syntax [unified|divided] - choose the new unified syntax
2809 (same for Arm and Thumb encoding, modulo slight differences in what
2810 can be represented) or the old divergent syntax for each mode. */
2812 s_syntax (int unused ATTRIBUTE_UNUSED
)
2816 name
= input_line_pointer
;
2817 delim
= get_symbol_end ();
2819 if (!strcasecmp (name
, "unified"))
2820 unified_syntax
= TRUE
;
2821 else if (!strcasecmp (name
, "divided"))
2822 unified_syntax
= FALSE
;
2825 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2828 *input_line_pointer
= delim
;
2829 demand_empty_rest_of_line ();
2832 /* Directives: sectioning and alignment. */
2834 /* Same as s_align_ptwo but align 0 => align 2. */
2837 s_align (int unused ATTRIBUTE_UNUSED
)
2842 long max_alignment
= 15;
2844 temp
= get_absolute_expression ();
2845 if (temp
> max_alignment
)
2846 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2849 as_bad (_("alignment negative. 0 assumed."));
2853 if (*input_line_pointer
== ',')
2855 input_line_pointer
++;
2856 temp_fill
= get_absolute_expression ();
2868 /* Only make a frag if we HAVE to. */
2869 if (temp
&& !need_pass_2
)
2871 if (!fill_p
&& subseg_text_p (now_seg
))
2872 frag_align_code (temp
, 0);
2874 frag_align (temp
, (int) temp_fill
, 0);
2876 demand_empty_rest_of_line ();
2878 record_alignment (now_seg
, temp
);
2882 s_bss (int ignore ATTRIBUTE_UNUSED
)
2884 /* We don't support putting frags in the BSS segment, we fake it by
2885 marking in_bss, then looking at s_skip for clues. */
2886 subseg_set (bss_section
, 0);
2887 demand_empty_rest_of_line ();
2889 #ifdef md_elf_section_change_hook
2890 md_elf_section_change_hook ();
2895 s_even (int ignore ATTRIBUTE_UNUSED
)
2897 /* Never make frag if expect extra pass. */
2899 frag_align (1, 0, 0);
2901 record_alignment (now_seg
, 1);
2903 demand_empty_rest_of_line ();
2906 /* Directives: Literal pools. */
2908 static literal_pool
*
2909 find_literal_pool (void)
2911 literal_pool
* pool
;
2913 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2915 if (pool
->section
== now_seg
2916 && pool
->sub_section
== now_subseg
)
2923 static literal_pool
*
2924 find_or_make_literal_pool (void)
2926 /* Next literal pool ID number. */
2927 static unsigned int latest_pool_num
= 1;
2928 literal_pool
* pool
;
2930 pool
= find_literal_pool ();
2934 /* Create a new pool. */
2935 pool
= xmalloc (sizeof (* pool
));
2939 pool
->next_free_entry
= 0;
2940 pool
->section
= now_seg
;
2941 pool
->sub_section
= now_subseg
;
2942 pool
->next
= list_of_pools
;
2943 pool
->symbol
= NULL
;
2945 /* Add it to the list. */
2946 list_of_pools
= pool
;
2949 /* New pools, and emptied pools, will have a NULL symbol. */
2950 if (pool
->symbol
== NULL
)
2952 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2953 (valueT
) 0, &zero_address_frag
);
2954 pool
->id
= latest_pool_num
++;
2961 /* Add the literal in the global 'inst'
2962 structure to the relevant literal pool. */
2965 add_to_lit_pool (void)
2967 literal_pool
* pool
;
2970 pool
= find_or_make_literal_pool ();
2972 /* Check if this literal value is already in the pool. */
2973 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2975 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2976 && (inst
.reloc
.exp
.X_op
== O_constant
)
2977 && (pool
->literals
[entry
].X_add_number
2978 == inst
.reloc
.exp
.X_add_number
)
2979 && (pool
->literals
[entry
].X_unsigned
2980 == inst
.reloc
.exp
.X_unsigned
))
2983 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2984 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2985 && (pool
->literals
[entry
].X_add_number
2986 == inst
.reloc
.exp
.X_add_number
)
2987 && (pool
->literals
[entry
].X_add_symbol
2988 == inst
.reloc
.exp
.X_add_symbol
)
2989 && (pool
->literals
[entry
].X_op_symbol
2990 == inst
.reloc
.exp
.X_op_symbol
))
2994 /* Do we need to create a new entry? */
2995 if (entry
== pool
->next_free_entry
)
2997 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2999 inst
.error
= _("literal pool overflow");
3003 pool
->literals
[entry
] = inst
.reloc
.exp
;
3004 pool
->next_free_entry
+= 1;
3007 inst
.reloc
.exp
.X_op
= O_symbol
;
3008 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3009 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3014 /* Can't use symbol_new here, so have to create a symbol and then at
3015 a later date assign it a value. Thats what these functions do. */
3018 symbol_locate (symbolS
* symbolP
,
3019 const char * name
, /* It is copied, the caller can modify. */
3020 segT segment
, /* Segment identifier (SEG_<something>). */
3021 valueT valu
, /* Symbol value. */
3022 fragS
* frag
) /* Associated fragment. */
3024 unsigned int name_length
;
3025 char * preserved_copy_of_name
;
3027 name_length
= strlen (name
) + 1; /* +1 for \0. */
3028 obstack_grow (¬es
, name
, name_length
);
3029 preserved_copy_of_name
= obstack_finish (¬es
);
3031 #ifdef tc_canonicalize_symbol_name
3032 preserved_copy_of_name
=
3033 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3036 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3038 S_SET_SEGMENT (symbolP
, segment
);
3039 S_SET_VALUE (symbolP
, valu
);
3040 symbol_clear_list_pointers (symbolP
);
3042 symbol_set_frag (symbolP
, frag
);
3044 /* Link to end of symbol chain. */
3046 extern int symbol_table_frozen
;
3048 if (symbol_table_frozen
)
3052 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3054 obj_symbol_new_hook (symbolP
);
3056 #ifdef tc_symbol_new_hook
3057 tc_symbol_new_hook (symbolP
);
3061 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3062 #endif /* DEBUG_SYMS */
3067 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3070 literal_pool
* pool
;
3073 pool
= find_literal_pool ();
3075 || pool
->symbol
== NULL
3076 || pool
->next_free_entry
== 0)
3079 mapping_state (MAP_DATA
);
3081 /* Align pool as you have word accesses.
3082 Only make a frag if we have to. */
3084 frag_align (2, 0, 0);
3086 record_alignment (now_seg
, 2);
3088 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3090 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3091 (valueT
) frag_now_fix (), frag_now
);
3092 symbol_table_insert (pool
->symbol
);
3094 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3096 #if defined OBJ_COFF || defined OBJ_ELF
3097 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3100 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3101 /* First output the expression in the instruction to the pool. */
3102 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3104 /* Mark the pool as empty. */
3105 pool
->next_free_entry
= 0;
3106 pool
->symbol
= NULL
;
3110 /* Forward declarations for functions below, in the MD interface
3112 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3113 static valueT
create_unwind_entry (int);
3114 static void start_unwind_section (const segT
, int);
3115 static void add_unwind_opcode (valueT
, int);
3116 static void flush_pending_unwind (void);
3118 /* Directives: Data. */
3121 s_arm_elf_cons (int nbytes
)
3125 #ifdef md_flush_pending_output
3126 md_flush_pending_output ();
3129 if (is_it_end_of_statement ())
3131 demand_empty_rest_of_line ();
3135 #ifdef md_cons_align
3136 md_cons_align (nbytes
);
3139 mapping_state (MAP_DATA
);
3143 char *base
= input_line_pointer
;
3147 if (exp
.X_op
!= O_symbol
)
3148 emit_expr (&exp
, (unsigned int) nbytes
);
3151 char *before_reloc
= input_line_pointer
;
3152 reloc
= parse_reloc (&input_line_pointer
);
3155 as_bad (_("unrecognized relocation suffix"));
3156 ignore_rest_of_line ();
3159 else if (reloc
== BFD_RELOC_UNUSED
)
3160 emit_expr (&exp
, (unsigned int) nbytes
);
3163 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
3164 int size
= bfd_get_reloc_size (howto
);
3166 if (reloc
== BFD_RELOC_ARM_PLT32
)
3168 as_bad (_("(plt) is only valid on branch targets"));
3169 reloc
= BFD_RELOC_UNUSED
;
3174 as_bad (_("%s relocations do not fit in %d bytes"),
3175 howto
->name
, nbytes
);
3178 /* We've parsed an expression stopping at O_symbol.
3179 But there may be more expression left now that we
3180 have parsed the relocation marker. Parse it again.
3181 XXX Surely there is a cleaner way to do this. */
3182 char *p
= input_line_pointer
;
3184 char *save_buf
= alloca (input_line_pointer
- base
);
3185 memcpy (save_buf
, base
, input_line_pointer
- base
);
3186 memmove (base
+ (input_line_pointer
- before_reloc
),
3187 base
, before_reloc
- base
);
3189 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3191 memcpy (base
, save_buf
, p
- base
);
3193 offset
= nbytes
- size
;
3194 p
= frag_more ((int) nbytes
);
3195 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3196 size
, &exp
, 0, reloc
);
3201 while (*input_line_pointer
++ == ',');
3203 /* Put terminator back into stream. */
3204 input_line_pointer
--;
3205 demand_empty_rest_of_line ();
3208 /* Emit an expression containing a 32-bit thumb instruction.
3209 Implementation based on put_thumb32_insn. */
3212 emit_thumb32_expr (expressionS
* exp
)
3214 expressionS exp_high
= *exp
;
3216 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3217 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3218 exp
->X_add_number
&= 0xffff;
3219 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3222 /* Guess the instruction size based on the opcode. */
3225 thumb_insn_size (int opcode
)
3227 if ((unsigned int) opcode
< 0xe800u
)
3229 else if ((unsigned int) opcode
>= 0xe8000000u
)
3236 emit_insn (expressionS
*exp
, int nbytes
)
3240 if (exp
->X_op
== O_constant
)
3245 size
= thumb_insn_size (exp
->X_add_number
);
3249 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3251 as_bad (_(".inst.n operand too big. "\
3252 "Use .inst.w instead"));
3257 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3258 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3260 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3262 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3263 emit_thumb32_expr (exp
);
3265 emit_expr (exp
, (unsigned int) size
);
3267 it_fsm_post_encode ();
3271 as_bad (_("cannot determine Thumb instruction size. " \
3272 "Use .inst.n/.inst.w instead"));
3275 as_bad (_("constant expression required"));
3280 /* Like s_arm_elf_cons but do not use md_cons_align and
3281 set the mapping state to MAP_ARM/MAP_THUMB. */
3284 s_arm_elf_inst (int nbytes
)
3286 if (is_it_end_of_statement ())
3288 demand_empty_rest_of_line ();
3292 /* Calling mapping_state () here will not change ARM/THUMB,
3293 but will ensure not to be in DATA state. */
3296 mapping_state (MAP_THUMB
);
3301 as_bad (_("width suffixes are invalid in ARM mode"));
3302 ignore_rest_of_line ();
3308 mapping_state (MAP_ARM
);
3317 if (! emit_insn (& exp
, nbytes
))
3319 ignore_rest_of_line ();
3323 while (*input_line_pointer
++ == ',');
3325 /* Put terminator back into stream. */
3326 input_line_pointer
--;
3327 demand_empty_rest_of_line ();
3330 /* Parse a .rel31 directive. */
3333 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3340 if (*input_line_pointer
== '1')
3341 highbit
= 0x80000000;
3342 else if (*input_line_pointer
!= '0')
3343 as_bad (_("expected 0 or 1"));
3345 input_line_pointer
++;
3346 if (*input_line_pointer
!= ',')
3347 as_bad (_("missing comma"));
3348 input_line_pointer
++;
3350 #ifdef md_flush_pending_output
3351 md_flush_pending_output ();
3354 #ifdef md_cons_align
3358 mapping_state (MAP_DATA
);
3363 md_number_to_chars (p
, highbit
, 4);
3364 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3365 BFD_RELOC_ARM_PREL31
);
3367 demand_empty_rest_of_line ();
3370 /* Directives: AEABI stack-unwind tables. */
3372 /* Parse an unwind_fnstart directive. Simply records the current location. */
3375 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3377 demand_empty_rest_of_line ();
3378 if (unwind
.proc_start
)
3380 as_bad (_("duplicate .fnstart directive"));
3384 /* Mark the start of the function. */
3385 unwind
.proc_start
= expr_build_dot ();
3387 /* Reset the rest of the unwind info. */
3388 unwind
.opcode_count
= 0;
3389 unwind
.table_entry
= NULL
;
3390 unwind
.personality_routine
= NULL
;
3391 unwind
.personality_index
= -1;
3392 unwind
.frame_size
= 0;
3393 unwind
.fp_offset
= 0;
3394 unwind
.fp_reg
= REG_SP
;
3396 unwind
.sp_restored
= 0;
3400 /* Parse a handlerdata directive. Creates the exception handling table entry
3401 for the function. */
3404 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3406 demand_empty_rest_of_line ();
3407 if (!unwind
.proc_start
)
3408 as_bad (MISSING_FNSTART
);
3410 if (unwind
.table_entry
)
3411 as_bad (_("duplicate .handlerdata directive"));
3413 create_unwind_entry (1);
3416 /* Parse an unwind_fnend directive. Generates the index table entry. */
3419 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3425 demand_empty_rest_of_line ();
3427 if (!unwind
.proc_start
)
3429 as_bad (_(".fnend directive without .fnstart"));
3433 /* Add eh table entry. */
3434 if (unwind
.table_entry
== NULL
)
3435 val
= create_unwind_entry (0);
3439 /* Add index table entry. This is two words. */
3440 start_unwind_section (unwind
.saved_seg
, 1);
3441 frag_align (2, 0, 0);
3442 record_alignment (now_seg
, 2);
3444 ptr
= frag_more (8);
3445 where
= frag_now_fix () - 8;
3447 /* Self relative offset of the function start. */
3448 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3449 BFD_RELOC_ARM_PREL31
);
3451 /* Indicate dependency on EHABI-defined personality routines to the
3452 linker, if it hasn't been done already. */
3453 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3454 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3456 static const char *const name
[] =
3458 "__aeabi_unwind_cpp_pr0",
3459 "__aeabi_unwind_cpp_pr1",
3460 "__aeabi_unwind_cpp_pr2"
3462 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3463 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3464 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3465 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3466 = marked_pr_dependency
;
3470 /* Inline exception table entry. */
3471 md_number_to_chars (ptr
+ 4, val
, 4);
3473 /* Self relative offset of the table entry. */
3474 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3475 BFD_RELOC_ARM_PREL31
);
3477 /* Restore the original section. */
3478 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3480 unwind
.proc_start
= NULL
;
3484 /* Parse an unwind_cantunwind directive. */
3487 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3489 demand_empty_rest_of_line ();
3490 if (!unwind
.proc_start
)
3491 as_bad (MISSING_FNSTART
);
3493 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3494 as_bad (_("personality routine specified for cantunwind frame"));
3496 unwind
.personality_index
= -2;
3500 /* Parse a personalityindex directive. */
3503 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3507 if (!unwind
.proc_start
)
3508 as_bad (MISSING_FNSTART
);
3510 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3511 as_bad (_("duplicate .personalityindex directive"));
3515 if (exp
.X_op
!= O_constant
3516 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3518 as_bad (_("bad personality routine number"));
3519 ignore_rest_of_line ();
3523 unwind
.personality_index
= exp
.X_add_number
;
3525 demand_empty_rest_of_line ();
3529 /* Parse a personality directive. */
3532 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3536 if (!unwind
.proc_start
)
3537 as_bad (MISSING_FNSTART
);
3539 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3540 as_bad (_("duplicate .personality directive"));
3542 name
= input_line_pointer
;
3543 c
= get_symbol_end ();
3544 p
= input_line_pointer
;
3545 unwind
.personality_routine
= symbol_find_or_make (name
);
3547 demand_empty_rest_of_line ();
3551 /* Parse a directive saving core registers. */
3554 s_arm_unwind_save_core (void)
3560 range
= parse_reg_list (&input_line_pointer
);
3563 as_bad (_("expected register list"));
3564 ignore_rest_of_line ();
3568 demand_empty_rest_of_line ();
3570 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3571 into .unwind_save {..., sp...}. We aren't bothered about the value of
3572 ip because it is clobbered by calls. */
3573 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3574 && (range
& 0x3000) == 0x1000)
3576 unwind
.opcode_count
--;
3577 unwind
.sp_restored
= 0;
3578 range
= (range
| 0x2000) & ~0x1000;
3579 unwind
.pending_offset
= 0;
3585 /* See if we can use the short opcodes. These pop a block of up to 8
3586 registers starting with r4, plus maybe r14. */
3587 for (n
= 0; n
< 8; n
++)
3589 /* Break at the first non-saved register. */
3590 if ((range
& (1 << (n
+ 4))) == 0)
3593 /* See if there are any other bits set. */
3594 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3596 /* Use the long form. */
3597 op
= 0x8000 | ((range
>> 4) & 0xfff);
3598 add_unwind_opcode (op
, 2);
3602 /* Use the short form. */
3604 op
= 0xa8; /* Pop r14. */
3606 op
= 0xa0; /* Do not pop r14. */
3608 add_unwind_opcode (op
, 1);
3615 op
= 0xb100 | (range
& 0xf);
3616 add_unwind_opcode (op
, 2);
3619 /* Record the number of bytes pushed. */
3620 for (n
= 0; n
< 16; n
++)
3622 if (range
& (1 << n
))
3623 unwind
.frame_size
+= 4;
3628 /* Parse a directive saving FPA registers. */
3631 s_arm_unwind_save_fpa (int reg
)
3637 /* Get Number of registers to transfer. */
3638 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3641 exp
.X_op
= O_illegal
;
3643 if (exp
.X_op
!= O_constant
)
3645 as_bad (_("expected , <constant>"));
3646 ignore_rest_of_line ();
3650 num_regs
= exp
.X_add_number
;
3652 if (num_regs
< 1 || num_regs
> 4)
3654 as_bad (_("number of registers must be in the range [1:4]"));
3655 ignore_rest_of_line ();
3659 demand_empty_rest_of_line ();
3664 op
= 0xb4 | (num_regs
- 1);
3665 add_unwind_opcode (op
, 1);
3670 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3671 add_unwind_opcode (op
, 2);
3673 unwind
.frame_size
+= num_regs
* 12;
3677 /* Parse a directive saving VFP registers for ARMv6 and above. */
3680 s_arm_unwind_save_vfp_armv6 (void)
3685 int num_vfpv3_regs
= 0;
3686 int num_regs_below_16
;
3688 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3691 as_bad (_("expected register list"));
3692 ignore_rest_of_line ();
3696 demand_empty_rest_of_line ();
3698 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3699 than FSTMX/FLDMX-style ones). */
3701 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3703 num_vfpv3_regs
= count
;
3704 else if (start
+ count
> 16)
3705 num_vfpv3_regs
= start
+ count
- 16;
3707 if (num_vfpv3_regs
> 0)
3709 int start_offset
= start
> 16 ? start
- 16 : 0;
3710 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3711 add_unwind_opcode (op
, 2);
3714 /* Generate opcode for registers numbered in the range 0 .. 15. */
3715 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3716 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3717 if (num_regs_below_16
> 0)
3719 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3720 add_unwind_opcode (op
, 2);
3723 unwind
.frame_size
+= count
* 8;
3727 /* Parse a directive saving VFP registers for pre-ARMv6. */
3730 s_arm_unwind_save_vfp (void)
3736 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3739 as_bad (_("expected register list"));
3740 ignore_rest_of_line ();
3744 demand_empty_rest_of_line ();
3749 op
= 0xb8 | (count
- 1);
3750 add_unwind_opcode (op
, 1);
3755 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3756 add_unwind_opcode (op
, 2);
3758 unwind
.frame_size
+= count
* 8 + 4;
3762 /* Parse a directive saving iWMMXt data registers. */
3765 s_arm_unwind_save_mmxwr (void)
3773 if (*input_line_pointer
== '{')
3774 input_line_pointer
++;
3778 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3782 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3787 as_tsktsk (_("register list not in ascending order"));
3790 if (*input_line_pointer
== '-')
3792 input_line_pointer
++;
3793 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3796 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3799 else if (reg
>= hi_reg
)
3801 as_bad (_("bad register range"));
3804 for (; reg
< hi_reg
; reg
++)
3808 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3810 if (*input_line_pointer
== '}')
3811 input_line_pointer
++;
3813 demand_empty_rest_of_line ();
3815 /* Generate any deferred opcodes because we're going to be looking at
3817 flush_pending_unwind ();
3819 for (i
= 0; i
< 16; i
++)
3821 if (mask
& (1 << i
))
3822 unwind
.frame_size
+= 8;
3825 /* Attempt to combine with a previous opcode. We do this because gcc
3826 likes to output separate unwind directives for a single block of
3828 if (unwind
.opcode_count
> 0)
3830 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3831 if ((i
& 0xf8) == 0xc0)
3834 /* Only merge if the blocks are contiguous. */
3837 if ((mask
& 0xfe00) == (1 << 9))
3839 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3840 unwind
.opcode_count
--;
3843 else if (i
== 6 && unwind
.opcode_count
>= 2)
3845 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3849 op
= 0xffff << (reg
- 1);
3851 && ((mask
& op
) == (1u << (reg
- 1))))
3853 op
= (1 << (reg
+ i
+ 1)) - 1;
3854 op
&= ~((1 << reg
) - 1);
3856 unwind
.opcode_count
-= 2;
3863 /* We want to generate opcodes in the order the registers have been
3864 saved, ie. descending order. */
3865 for (reg
= 15; reg
>= -1; reg
--)
3867 /* Save registers in blocks. */
3869 || !(mask
& (1 << reg
)))
3871 /* We found an unsaved reg. Generate opcodes to save the
3878 op
= 0xc0 | (hi_reg
- 10);
3879 add_unwind_opcode (op
, 1);
3884 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3885 add_unwind_opcode (op
, 2);
3894 ignore_rest_of_line ();
3898 s_arm_unwind_save_mmxwcg (void)
3905 if (*input_line_pointer
== '{')
3906 input_line_pointer
++;
3910 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3914 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3920 as_tsktsk (_("register list not in ascending order"));
3923 if (*input_line_pointer
== '-')
3925 input_line_pointer
++;
3926 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3929 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3932 else if (reg
>= hi_reg
)
3934 as_bad (_("bad register range"));
3937 for (; reg
< hi_reg
; reg
++)
3941 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3943 if (*input_line_pointer
== '}')
3944 input_line_pointer
++;
3946 demand_empty_rest_of_line ();
3948 /* Generate any deferred opcodes because we're going to be looking at
3950 flush_pending_unwind ();
3952 for (reg
= 0; reg
< 16; reg
++)
3954 if (mask
& (1 << reg
))
3955 unwind
.frame_size
+= 4;
3958 add_unwind_opcode (op
, 2);
3961 ignore_rest_of_line ();
3965 /* Parse an unwind_save directive.
3966 If the argument is non-zero, this is a .vsave directive. */
3969 s_arm_unwind_save (int arch_v6
)
3972 struct reg_entry
*reg
;
3973 bfd_boolean had_brace
= FALSE
;
3975 if (!unwind
.proc_start
)
3976 as_bad (MISSING_FNSTART
);
3978 /* Figure out what sort of save we have. */
3979 peek
= input_line_pointer
;
3987 reg
= arm_reg_parse_multi (&peek
);
3991 as_bad (_("register expected"));
3992 ignore_rest_of_line ();
4001 as_bad (_("FPA .unwind_save does not take a register list"));
4002 ignore_rest_of_line ();
4005 input_line_pointer
= peek
;
4006 s_arm_unwind_save_fpa (reg
->number
);
4009 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4012 s_arm_unwind_save_vfp_armv6 ();
4014 s_arm_unwind_save_vfp ();
4016 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4017 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4020 as_bad (_(".unwind_save does not support this kind of register"));
4021 ignore_rest_of_line ();
4026 /* Parse an unwind_movsp directive. */
4029 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4035 if (!unwind
.proc_start
)
4036 as_bad (MISSING_FNSTART
);
4038 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4041 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4042 ignore_rest_of_line ();
4046 /* Optional constant. */
4047 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4049 if (immediate_for_directive (&offset
) == FAIL
)
4055 demand_empty_rest_of_line ();
4057 if (reg
== REG_SP
|| reg
== REG_PC
)
4059 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4063 if (unwind
.fp_reg
!= REG_SP
)
4064 as_bad (_("unexpected .unwind_movsp directive"));
4066 /* Generate opcode to restore the value. */
4068 add_unwind_opcode (op
, 1);
4070 /* Record the information for later. */
4071 unwind
.fp_reg
= reg
;
4072 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4073 unwind
.sp_restored
= 1;
4076 /* Parse an unwind_pad directive. */
4079 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4083 if (!unwind
.proc_start
)
4084 as_bad (MISSING_FNSTART
);
4086 if (immediate_for_directive (&offset
) == FAIL
)
4091 as_bad (_("stack increment must be multiple of 4"));
4092 ignore_rest_of_line ();
4096 /* Don't generate any opcodes, just record the details for later. */
4097 unwind
.frame_size
+= offset
;
4098 unwind
.pending_offset
+= offset
;
4100 demand_empty_rest_of_line ();
4103 /* Parse an unwind_setfp directive. */
4106 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4112 if (!unwind
.proc_start
)
4113 as_bad (MISSING_FNSTART
);
4115 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4116 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4119 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4121 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4123 as_bad (_("expected <reg>, <reg>"));
4124 ignore_rest_of_line ();
4128 /* Optional constant. */
4129 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4131 if (immediate_for_directive (&offset
) == FAIL
)
4137 demand_empty_rest_of_line ();
4139 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4141 as_bad (_("register must be either sp or set by a previous"
4142 "unwind_movsp directive"));
4146 /* Don't generate any opcodes, just record the information for later. */
4147 unwind
.fp_reg
= fp_reg
;
4149 if (sp_reg
== REG_SP
)
4150 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4152 unwind
.fp_offset
-= offset
;
4155 /* Parse an unwind_raw directive. */
4158 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4161 /* This is an arbitrary limit. */
4162 unsigned char op
[16];
4165 if (!unwind
.proc_start
)
4166 as_bad (MISSING_FNSTART
);
4169 if (exp
.X_op
== O_constant
4170 && skip_past_comma (&input_line_pointer
) != FAIL
)
4172 unwind
.frame_size
+= exp
.X_add_number
;
4176 exp
.X_op
= O_illegal
;
4178 if (exp
.X_op
!= O_constant
)
4180 as_bad (_("expected <offset>, <opcode>"));
4181 ignore_rest_of_line ();
4187 /* Parse the opcode. */
4192 as_bad (_("unwind opcode too long"));
4193 ignore_rest_of_line ();
4195 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4197 as_bad (_("invalid unwind opcode"));
4198 ignore_rest_of_line ();
4201 op
[count
++] = exp
.X_add_number
;
4203 /* Parse the next byte. */
4204 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4210 /* Add the opcode bytes in reverse order. */
4212 add_unwind_opcode (op
[count
], 1);
4214 demand_empty_rest_of_line ();
4218 /* Parse a .eabi_attribute directive. */
4221 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4223 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4225 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4226 attributes_set_explicitly
[tag
] = 1;
4228 #endif /* OBJ_ELF */
4230 static void s_arm_arch (int);
4231 static void s_arm_object_arch (int);
4232 static void s_arm_cpu (int);
4233 static void s_arm_fpu (int);
4238 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4245 if (exp
.X_op
== O_symbol
)
4246 exp
.X_op
= O_secrel
;
4248 emit_expr (&exp
, 4);
4250 while (*input_line_pointer
++ == ',');
4252 input_line_pointer
--;
4253 demand_empty_rest_of_line ();
4257 /* This table describes all the machine specific pseudo-ops the assembler
4258 has to support. The fields are:
4259 pseudo-op name without dot
4260 function to call to execute this pseudo-op
4261 Integer arg to pass to the function. */
4263 const pseudo_typeS md_pseudo_table
[] =
4265 /* Never called because '.req' does not start a line. */
4266 { "req", s_req
, 0 },
4267 /* Following two are likewise never called. */
4270 { "unreq", s_unreq
, 0 },
4271 { "bss", s_bss
, 0 },
4272 { "align", s_align
, 0 },
4273 { "arm", s_arm
, 0 },
4274 { "thumb", s_thumb
, 0 },
4275 { "code", s_code
, 0 },
4276 { "force_thumb", s_force_thumb
, 0 },
4277 { "thumb_func", s_thumb_func
, 0 },
4278 { "thumb_set", s_thumb_set
, 0 },
4279 { "even", s_even
, 0 },
4280 { "ltorg", s_ltorg
, 0 },
4281 { "pool", s_ltorg
, 0 },
4282 { "syntax", s_syntax
, 0 },
4283 { "cpu", s_arm_cpu
, 0 },
4284 { "arch", s_arm_arch
, 0 },
4285 { "object_arch", s_arm_object_arch
, 0 },
4286 { "fpu", s_arm_fpu
, 0 },
4288 { "word", s_arm_elf_cons
, 4 },
4289 { "long", s_arm_elf_cons
, 4 },
4290 { "inst.n", s_arm_elf_inst
, 2 },
4291 { "inst.w", s_arm_elf_inst
, 4 },
4292 { "inst", s_arm_elf_inst
, 0 },
4293 { "rel31", s_arm_rel31
, 0 },
4294 { "fnstart", s_arm_unwind_fnstart
, 0 },
4295 { "fnend", s_arm_unwind_fnend
, 0 },
4296 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4297 { "personality", s_arm_unwind_personality
, 0 },
4298 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4299 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4300 { "save", s_arm_unwind_save
, 0 },
4301 { "vsave", s_arm_unwind_save
, 1 },
4302 { "movsp", s_arm_unwind_movsp
, 0 },
4303 { "pad", s_arm_unwind_pad
, 0 },
4304 { "setfp", s_arm_unwind_setfp
, 0 },
4305 { "unwind_raw", s_arm_unwind_raw
, 0 },
4306 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4310 /* These are used for dwarf. */
4314 /* These are used for dwarf2. */
4315 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4316 { "loc", dwarf2_directive_loc
, 0 },
4317 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4319 { "extend", float_cons
, 'x' },
4320 { "ldouble", float_cons
, 'x' },
4321 { "packed", float_cons
, 'p' },
4323 {"secrel32", pe_directive_secrel
, 0},
4328 /* Parser functions used exclusively in instruction operands. */
4330 /* Generic immediate-value read function for use in insn parsing.
4331 STR points to the beginning of the immediate (the leading #);
4332 VAL receives the value; if the value is outside [MIN, MAX]
4333 issue an error. PREFIX_OPT is true if the immediate prefix is
4337 parse_immediate (char **str
, int *val
, int min
, int max
,
4338 bfd_boolean prefix_opt
)
4341 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4342 if (exp
.X_op
!= O_constant
)
4344 inst
.error
= _("constant expression required");
4348 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4350 inst
.error
= _("immediate value out of range");
4354 *val
= exp
.X_add_number
;
4358 /* Less-generic immediate-value read function with the possibility of loading a
4359 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4360 instructions. Puts the result directly in inst.operands[i]. */
4363 parse_big_immediate (char **str
, int i
)
4368 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4370 if (exp
.X_op
== O_constant
)
4372 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4373 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4374 O_constant. We have to be careful not to break compilation for
4375 32-bit X_add_number, though. */
4376 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4378 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4379 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4380 inst
.operands
[i
].regisimm
= 1;
4383 else if (exp
.X_op
== O_big
4384 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4385 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4387 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4388 /* Bignums have their least significant bits in
4389 generic_bignum[0]. Make sure we put 32 bits in imm and
4390 32 bits in reg, in a (hopefully) portable way. */
4391 gas_assert (parts
!= 0);
4392 inst
.operands
[i
].imm
= 0;
4393 for (j
= 0; j
< parts
; j
++, idx
++)
4394 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4395 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4396 inst
.operands
[i
].reg
= 0;
4397 for (j
= 0; j
< parts
; j
++, idx
++)
4398 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4399 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4400 inst
.operands
[i
].regisimm
= 1;
4410 /* Returns the pseudo-register number of an FPA immediate constant,
4411 or FAIL if there isn't a valid constant here. */
4414 parse_fpa_immediate (char ** str
)
4416 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4422 /* First try and match exact strings, this is to guarantee
4423 that some formats will work even for cross assembly. */
4425 for (i
= 0; fp_const
[i
]; i
++)
4427 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4431 *str
+= strlen (fp_const
[i
]);
4432 if (is_end_of_line
[(unsigned char) **str
])
4438 /* Just because we didn't get a match doesn't mean that the constant
4439 isn't valid, just that it is in a format that we don't
4440 automatically recognize. Try parsing it with the standard
4441 expression routines. */
4443 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4445 /* Look for a raw floating point number. */
4446 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4447 && is_end_of_line
[(unsigned char) *save_in
])
4449 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4451 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4453 if (words
[j
] != fp_values
[i
][j
])
4457 if (j
== MAX_LITTLENUMS
)
4465 /* Try and parse a more complex expression, this will probably fail
4466 unless the code uses a floating point prefix (eg "0f"). */
4467 save_in
= input_line_pointer
;
4468 input_line_pointer
= *str
;
4469 if (expression (&exp
) == absolute_section
4470 && exp
.X_op
== O_big
4471 && exp
.X_add_number
< 0)
4473 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4475 if (gen_to_words (words
, 5, (long) 15) == 0)
4477 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4479 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4481 if (words
[j
] != fp_values
[i
][j
])
4485 if (j
== MAX_LITTLENUMS
)
4487 *str
= input_line_pointer
;
4488 input_line_pointer
= save_in
;
4495 *str
= input_line_pointer
;
4496 input_line_pointer
= save_in
;
4497 inst
.error
= _("invalid FPA immediate expression");
4501 /* Returns 1 if a number has "quarter-precision" float format
4502 0baBbbbbbc defgh000 00000000 00000000. */
4505 is_quarter_float (unsigned imm
)
4507 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4508 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4511 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4512 0baBbbbbbc defgh000 00000000 00000000.
4513 The zero and minus-zero cases need special handling, since they can't be
4514 encoded in the "quarter-precision" float format, but can nonetheless be
4515 loaded as integer constants. */
4518 parse_qfloat_immediate (char **ccp
, int *immed
)
4522 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4523 int found_fpchar
= 0;
4525 skip_past_char (&str
, '#');
4527 /* We must not accidentally parse an integer as a floating-point number. Make
4528 sure that the value we parse is not an integer by checking for special
4529 characters '.' or 'e'.
4530 FIXME: This is a horrible hack, but doing better is tricky because type
4531 information isn't in a very usable state at parse time. */
4533 skip_whitespace (fpnum
);
4535 if (strncmp (fpnum
, "0x", 2) == 0)
4539 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4540 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4550 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4552 unsigned fpword
= 0;
4555 /* Our FP word must be 32 bits (single-precision FP). */
4556 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4558 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4562 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4575 /* Shift operands. */
4578 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4581 struct asm_shift_name
4584 enum shift_kind kind
;
4587 /* Third argument to parse_shift. */
4588 enum parse_shift_mode
4590 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4591 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4592 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4593 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4594 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4597 /* Parse a <shift> specifier on an ARM data processing instruction.
4598 This has three forms:
4600 (LSL|LSR|ASL|ASR|ROR) Rs
4601 (LSL|LSR|ASL|ASR|ROR) #imm
4604 Note that ASL is assimilated to LSL in the instruction encoding, and
4605 RRX to ROR #0 (which cannot be written as such). */
4608 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4610 const struct asm_shift_name
*shift_name
;
4611 enum shift_kind shift
;
4616 for (p
= *str
; ISALPHA (*p
); p
++)
4621 inst
.error
= _("shift expression expected");
4625 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4627 if (shift_name
== NULL
)
4629 inst
.error
= _("shift expression expected");
4633 shift
= shift_name
->kind
;
4637 case NO_SHIFT_RESTRICT
:
4638 case SHIFT_IMMEDIATE
: break;
4640 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4641 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4643 inst
.error
= _("'LSL' or 'ASR' required");
4648 case SHIFT_LSL_IMMEDIATE
:
4649 if (shift
!= SHIFT_LSL
)
4651 inst
.error
= _("'LSL' required");
4656 case SHIFT_ASR_IMMEDIATE
:
4657 if (shift
!= SHIFT_ASR
)
4659 inst
.error
= _("'ASR' required");
4667 if (shift
!= SHIFT_RRX
)
4669 /* Whitespace can appear here if the next thing is a bare digit. */
4670 skip_whitespace (p
);
4672 if (mode
== NO_SHIFT_RESTRICT
4673 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4675 inst
.operands
[i
].imm
= reg
;
4676 inst
.operands
[i
].immisreg
= 1;
4678 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4681 inst
.operands
[i
].shift_kind
= shift
;
4682 inst
.operands
[i
].shifted
= 1;
4687 /* Parse a <shifter_operand> for an ARM data processing instruction:
4690 #<immediate>, <rotate>
4694 where <shift> is defined by parse_shift above, and <rotate> is a
4695 multiple of 2 between 0 and 30. Validation of immediate operands
4696 is deferred to md_apply_fix. */
4699 parse_shifter_operand (char **str
, int i
)
4704 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4706 inst
.operands
[i
].reg
= value
;
4707 inst
.operands
[i
].isreg
= 1;
4709 /* parse_shift will override this if appropriate */
4710 inst
.reloc
.exp
.X_op
= O_constant
;
4711 inst
.reloc
.exp
.X_add_number
= 0;
4713 if (skip_past_comma (str
) == FAIL
)
4716 /* Shift operation on register. */
4717 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4720 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4723 if (skip_past_comma (str
) == SUCCESS
)
4725 /* #x, y -- ie explicit rotation by Y. */
4726 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4729 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4731 inst
.error
= _("constant expression expected");
4735 value
= expr
.X_add_number
;
4736 if (value
< 0 || value
> 30 || value
% 2 != 0)
4738 inst
.error
= _("invalid rotation");
4741 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4743 inst
.error
= _("invalid constant");
4747 /* Convert to decoded value. md_apply_fix will put it back. */
4748 inst
.reloc
.exp
.X_add_number
4749 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4750 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4753 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4754 inst
.reloc
.pc_rel
= 0;
4758 /* Group relocation information. Each entry in the table contains the
4759 textual name of the relocation as may appear in assembler source
4760 and must end with a colon.
4761 Along with this textual name are the relocation codes to be used if
4762 the corresponding instruction is an ALU instruction (ADD or SUB only),
4763 an LDR, an LDRS, or an LDC. */
4765 struct group_reloc_table_entry
4776 /* Varieties of non-ALU group relocation. */
4783 static struct group_reloc_table_entry group_reloc_table
[] =
4784 { /* Program counter relative: */
4786 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4791 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4792 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4793 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4794 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4796 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4801 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4802 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4803 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4804 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4806 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4807 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4808 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4809 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4810 /* Section base relative */
4812 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4817 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4818 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4819 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4820 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4822 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4827 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4828 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4829 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4830 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4832 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4833 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4834 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4835 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4837 /* Given the address of a pointer pointing to the textual name of a group
4838 relocation as may appear in assembler source, attempt to find its details
4839 in group_reloc_table. The pointer will be updated to the character after
4840 the trailing colon. On failure, FAIL will be returned; SUCCESS
4841 otherwise. On success, *entry will be updated to point at the relevant
4842 group_reloc_table entry. */
4845 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4848 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4850 int length
= strlen (group_reloc_table
[i
].name
);
4852 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4853 && (*str
)[length
] == ':')
4855 *out
= &group_reloc_table
[i
];
4856 *str
+= (length
+ 1);
4864 /* Parse a <shifter_operand> for an ARM data processing instruction
4865 (as for parse_shifter_operand) where group relocations are allowed:
4868 #<immediate>, <rotate>
4869 #:<group_reloc>:<expression>
4873 where <group_reloc> is one of the strings defined in group_reloc_table.
4874 The hashes are optional.
4876 Everything else is as for parse_shifter_operand. */
4878 static parse_operand_result
4879 parse_shifter_operand_group_reloc (char **str
, int i
)
4881 /* Determine if we have the sequence of characters #: or just :
4882 coming next. If we do, then we check for a group relocation.
4883 If we don't, punt the whole lot to parse_shifter_operand. */
4885 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4886 || (*str
)[0] == ':')
4888 struct group_reloc_table_entry
*entry
;
4890 if ((*str
)[0] == '#')
4895 /* Try to parse a group relocation. Anything else is an error. */
4896 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4898 inst
.error
= _("unknown group relocation");
4899 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4902 /* We now have the group relocation table entry corresponding to
4903 the name in the assembler source. Next, we parse the expression. */
4904 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4905 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4907 /* Record the relocation type (always the ALU variant here). */
4908 inst
.reloc
.type
= entry
->alu_code
;
4909 gas_assert (inst
.reloc
.type
!= 0);
4911 return PARSE_OPERAND_SUCCESS
;
4914 return parse_shifter_operand (str
, i
) == SUCCESS
4915 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4917 /* Never reached. */
4920 /* Parse all forms of an ARM address expression. Information is written
4921 to inst.operands[i] and/or inst.reloc.
4923 Preindexed addressing (.preind=1):
4925 [Rn, #offset] .reg=Rn .reloc.exp=offset
4926 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4927 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4928 .shift_kind=shift .reloc.exp=shift_imm
4930 These three may have a trailing ! which causes .writeback to be set also.
4932 Postindexed addressing (.postind=1, .writeback=1):
4934 [Rn], #offset .reg=Rn .reloc.exp=offset
4935 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4936 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4937 .shift_kind=shift .reloc.exp=shift_imm
4939 Unindexed addressing (.preind=0, .postind=0):
4941 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4945 [Rn]{!} shorthand for [Rn,#0]{!}
4946 =immediate .isreg=0 .reloc.exp=immediate
4947 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4949 It is the caller's responsibility to check for addressing modes not
4950 supported by the instruction, and to set inst.reloc.type. */
4952 static parse_operand_result
4953 parse_address_main (char **str
, int i
, int group_relocations
,
4954 group_reloc_type group_type
)
4959 if (skip_past_char (&p
, '[') == FAIL
)
4961 if (skip_past_char (&p
, '=') == FAIL
)
4963 /* bare address - translate to PC-relative offset */
4964 inst
.reloc
.pc_rel
= 1;
4965 inst
.operands
[i
].reg
= REG_PC
;
4966 inst
.operands
[i
].isreg
= 1;
4967 inst
.operands
[i
].preind
= 1;
4969 /* else a load-constant pseudo op, no special treatment needed here */
4971 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4972 return PARSE_OPERAND_FAIL
;
4975 return PARSE_OPERAND_SUCCESS
;
4978 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4980 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4981 return PARSE_OPERAND_FAIL
;
4983 inst
.operands
[i
].reg
= reg
;
4984 inst
.operands
[i
].isreg
= 1;
4986 if (skip_past_comma (&p
) == SUCCESS
)
4988 inst
.operands
[i
].preind
= 1;
4991 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4993 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4995 inst
.operands
[i
].imm
= reg
;
4996 inst
.operands
[i
].immisreg
= 1;
4998 if (skip_past_comma (&p
) == SUCCESS
)
4999 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5000 return PARSE_OPERAND_FAIL
;
5002 else if (skip_past_char (&p
, ':') == SUCCESS
)
5004 /* FIXME: '@' should be used here, but it's filtered out by generic
5005 code before we get to see it here. This may be subject to
5008 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5009 if (exp
.X_op
!= O_constant
)
5011 inst
.error
= _("alignment must be constant");
5012 return PARSE_OPERAND_FAIL
;
5014 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5015 inst
.operands
[i
].immisalign
= 1;
5016 /* Alignments are not pre-indexes. */
5017 inst
.operands
[i
].preind
= 0;
5021 if (inst
.operands
[i
].negative
)
5023 inst
.operands
[i
].negative
= 0;
5027 if (group_relocations
5028 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5030 struct group_reloc_table_entry
*entry
;
5032 /* Skip over the #: or : sequence. */
5038 /* Try to parse a group relocation. Anything else is an
5040 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5042 inst
.error
= _("unknown group relocation");
5043 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5046 /* We now have the group relocation table entry corresponding to
5047 the name in the assembler source. Next, we parse the
5049 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5050 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5052 /* Record the relocation type. */
5056 inst
.reloc
.type
= entry
->ldr_code
;
5060 inst
.reloc
.type
= entry
->ldrs_code
;
5064 inst
.reloc
.type
= entry
->ldc_code
;
5071 if (inst
.reloc
.type
== 0)
5073 inst
.error
= _("this group relocation is not allowed on this instruction");
5074 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5078 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5079 return PARSE_OPERAND_FAIL
;
5083 if (skip_past_char (&p
, ']') == FAIL
)
5085 inst
.error
= _("']' expected");
5086 return PARSE_OPERAND_FAIL
;
5089 if (skip_past_char (&p
, '!') == SUCCESS
)
5090 inst
.operands
[i
].writeback
= 1;
5092 else if (skip_past_comma (&p
) == SUCCESS
)
5094 if (skip_past_char (&p
, '{') == SUCCESS
)
5096 /* [Rn], {expr} - unindexed, with option */
5097 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5098 0, 255, TRUE
) == FAIL
)
5099 return PARSE_OPERAND_FAIL
;
5101 if (skip_past_char (&p
, '}') == FAIL
)
5103 inst
.error
= _("'}' expected at end of 'option' field");
5104 return PARSE_OPERAND_FAIL
;
5106 if (inst
.operands
[i
].preind
)
5108 inst
.error
= _("cannot combine index with option");
5109 return PARSE_OPERAND_FAIL
;
5112 return PARSE_OPERAND_SUCCESS
;
5116 inst
.operands
[i
].postind
= 1;
5117 inst
.operands
[i
].writeback
= 1;
5119 if (inst
.operands
[i
].preind
)
5121 inst
.error
= _("cannot combine pre- and post-indexing");
5122 return PARSE_OPERAND_FAIL
;
5126 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5128 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5130 /* We might be using the immediate for alignment already. If we
5131 are, OR the register number into the low-order bits. */
5132 if (inst
.operands
[i
].immisalign
)
5133 inst
.operands
[i
].imm
|= reg
;
5135 inst
.operands
[i
].imm
= reg
;
5136 inst
.operands
[i
].immisreg
= 1;
5138 if (skip_past_comma (&p
) == SUCCESS
)
5139 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5140 return PARSE_OPERAND_FAIL
;
5144 if (inst
.operands
[i
].negative
)
5146 inst
.operands
[i
].negative
= 0;
5149 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5150 return PARSE_OPERAND_FAIL
;
5155 /* If at this point neither .preind nor .postind is set, we have a
5156 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5157 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5159 inst
.operands
[i
].preind
= 1;
5160 inst
.reloc
.exp
.X_op
= O_constant
;
5161 inst
.reloc
.exp
.X_add_number
= 0;
5164 return PARSE_OPERAND_SUCCESS
;
5168 parse_address (char **str
, int i
)
5170 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
5174 static parse_operand_result
5175 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5177 return parse_address_main (str
, i
, 1, type
);
5180 /* Parse an operand for a MOVW or MOVT instruction. */
5182 parse_half (char **str
)
5187 skip_past_char (&p
, '#');
5188 if (strncasecmp (p
, ":lower16:", 9) == 0)
5189 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5190 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5191 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5193 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5196 skip_whitespace (p
);
5199 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5202 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5204 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5206 inst
.error
= _("constant expression expected");
5209 if (inst
.reloc
.exp
.X_add_number
< 0
5210 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5212 inst
.error
= _("immediate value out of range");
5220 /* Miscellaneous. */
5222 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5223 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5225 parse_psr (char **str
)
5228 unsigned long psr_field
;
5229 const struct asm_psr
*psr
;
5232 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5233 feature for ease of use and backwards compatibility. */
5235 if (strncasecmp (p
, "SPSR", 4) == 0)
5236 psr_field
= SPSR_BIT
;
5237 else if (strncasecmp (p
, "CPSR", 4) == 0)
5244 while (ISALNUM (*p
) || *p
== '_');
5246 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
5257 /* A suffix follows. */
5263 while (ISALNUM (*p
) || *p
== '_');
5265 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
5269 psr_field
|= psr
->field
;
5274 goto error
; /* Garbage after "[CS]PSR". */
5276 psr_field
|= (PSR_c
| PSR_f
);
5282 inst
.error
= _("flag for {c}psr instruction expected");
5286 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5287 value suitable for splatting into the AIF field of the instruction. */
5290 parse_cps_flags (char **str
)
5299 case '\0': case ',':
5302 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5303 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5304 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5307 inst
.error
= _("unrecognized CPS flag");
5312 if (saw_a_flag
== 0)
5314 inst
.error
= _("missing CPS flags");
5322 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5323 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5326 parse_endian_specifier (char **str
)
5331 if (strncasecmp (s
, "BE", 2))
5333 else if (strncasecmp (s
, "LE", 2))
5337 inst
.error
= _("valid endian specifiers are be or le");
5341 if (ISALNUM (s
[2]) || s
[2] == '_')
5343 inst
.error
= _("valid endian specifiers are be or le");
5348 return little_endian
;
5351 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5352 value suitable for poking into the rotate field of an sxt or sxta
5353 instruction, or FAIL on error. */
5356 parse_ror (char **str
)
5361 if (strncasecmp (s
, "ROR", 3) == 0)
5365 inst
.error
= _("missing rotation field after comma");
5369 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5374 case 0: *str
= s
; return 0x0;
5375 case 8: *str
= s
; return 0x1;
5376 case 16: *str
= s
; return 0x2;
5377 case 24: *str
= s
; return 0x3;
5380 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5385 /* Parse a conditional code (from conds[] below). The value returned is in the
5386 range 0 .. 14, or FAIL. */
5388 parse_cond (char **str
)
5391 const struct asm_cond
*c
;
5393 /* Condition codes are always 2 characters, so matching up to
5394 3 characters is sufficient. */
5399 while (ISALPHA (*q
) && n
< 3)
5401 cond
[n
] = TOLOWER (*q
);
5406 c
= hash_find_n (arm_cond_hsh
, cond
, n
);
5409 inst
.error
= _("condition required");
5417 /* Parse an option for a barrier instruction. Returns the encoding for the
5420 parse_barrier (char **str
)
5423 const struct asm_barrier_opt
*o
;
5426 while (ISALPHA (*q
))
5429 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
5437 /* Parse the operands of a table branch instruction. Similar to a memory
5440 parse_tb (char **str
)
5445 if (skip_past_char (&p
, '[') == FAIL
)
5447 inst
.error
= _("'[' expected");
5451 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5453 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5456 inst
.operands
[0].reg
= reg
;
5458 if (skip_past_comma (&p
) == FAIL
)
5460 inst
.error
= _("',' expected");
5464 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5466 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5469 inst
.operands
[0].imm
= reg
;
5471 if (skip_past_comma (&p
) == SUCCESS
)
5473 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5475 if (inst
.reloc
.exp
.X_add_number
!= 1)
5477 inst
.error
= _("invalid shift");
5480 inst
.operands
[0].shifted
= 1;
5483 if (skip_past_char (&p
, ']') == FAIL
)
5485 inst
.error
= _("']' expected");
5492 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5493 information on the types the operands can take and how they are encoded.
5494 Up to four operands may be read; this function handles setting the
5495 ".present" field for each read operand itself.
5496 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5497 else returns FAIL. */
5500 parse_neon_mov (char **str
, int *which_operand
)
5502 int i
= *which_operand
, val
;
5503 enum arm_reg_type rtype
;
5505 struct neon_type_el optype
;
5507 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5509 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5510 inst
.operands
[i
].reg
= val
;
5511 inst
.operands
[i
].isscalar
= 1;
5512 inst
.operands
[i
].vectype
= optype
;
5513 inst
.operands
[i
++].present
= 1;
5515 if (skip_past_comma (&ptr
) == FAIL
)
5518 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5521 inst
.operands
[i
].reg
= val
;
5522 inst
.operands
[i
].isreg
= 1;
5523 inst
.operands
[i
].present
= 1;
5525 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5528 /* Cases 0, 1, 2, 3, 5 (D only). */
5529 if (skip_past_comma (&ptr
) == FAIL
)
5532 inst
.operands
[i
].reg
= val
;
5533 inst
.operands
[i
].isreg
= 1;
5534 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5535 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5536 inst
.operands
[i
].isvec
= 1;
5537 inst
.operands
[i
].vectype
= optype
;
5538 inst
.operands
[i
++].present
= 1;
5540 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5542 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5543 Case 13: VMOV <Sd>, <Rm> */
5544 inst
.operands
[i
].reg
= val
;
5545 inst
.operands
[i
].isreg
= 1;
5546 inst
.operands
[i
].present
= 1;
5548 if (rtype
== REG_TYPE_NQ
)
5550 first_error (_("can't use Neon quad register here"));
5553 else if (rtype
!= REG_TYPE_VFS
)
5556 if (skip_past_comma (&ptr
) == FAIL
)
5558 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5560 inst
.operands
[i
].reg
= val
;
5561 inst
.operands
[i
].isreg
= 1;
5562 inst
.operands
[i
].present
= 1;
5565 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5568 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5569 Case 1: VMOV<c><q> <Dd>, <Dm>
5570 Case 8: VMOV.F32 <Sd>, <Sm>
5571 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5573 inst
.operands
[i
].reg
= val
;
5574 inst
.operands
[i
].isreg
= 1;
5575 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5576 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5577 inst
.operands
[i
].isvec
= 1;
5578 inst
.operands
[i
].vectype
= optype
;
5579 inst
.operands
[i
].present
= 1;
5581 if (skip_past_comma (&ptr
) == SUCCESS
)
5586 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5589 inst
.operands
[i
].reg
= val
;
5590 inst
.operands
[i
].isreg
= 1;
5591 inst
.operands
[i
++].present
= 1;
5593 if (skip_past_comma (&ptr
) == FAIL
)
5596 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5599 inst
.operands
[i
].reg
= val
;
5600 inst
.operands
[i
].isreg
= 1;
5601 inst
.operands
[i
++].present
= 1;
5604 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5605 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5606 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5607 Case 10: VMOV.F32 <Sd>, #<imm>
5608 Case 11: VMOV.F64 <Dd>, #<imm> */
5609 inst
.operands
[i
].immisfloat
= 1;
5610 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5611 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5612 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5616 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5620 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5623 inst
.operands
[i
].reg
= val
;
5624 inst
.operands
[i
].isreg
= 1;
5625 inst
.operands
[i
++].present
= 1;
5627 if (skip_past_comma (&ptr
) == FAIL
)
5630 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5632 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5633 inst
.operands
[i
].reg
= val
;
5634 inst
.operands
[i
].isscalar
= 1;
5635 inst
.operands
[i
].present
= 1;
5636 inst
.operands
[i
].vectype
= optype
;
5638 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5640 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5641 inst
.operands
[i
].reg
= val
;
5642 inst
.operands
[i
].isreg
= 1;
5643 inst
.operands
[i
++].present
= 1;
5645 if (skip_past_comma (&ptr
) == FAIL
)
5648 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5651 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5655 inst
.operands
[i
].reg
= val
;
5656 inst
.operands
[i
].isreg
= 1;
5657 inst
.operands
[i
].isvec
= 1;
5658 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5659 inst
.operands
[i
].vectype
= optype
;
5660 inst
.operands
[i
].present
= 1;
5662 if (rtype
== REG_TYPE_VFS
)
5666 if (skip_past_comma (&ptr
) == FAIL
)
5668 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5671 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5674 inst
.operands
[i
].reg
= val
;
5675 inst
.operands
[i
].isreg
= 1;
5676 inst
.operands
[i
].isvec
= 1;
5677 inst
.operands
[i
].issingle
= 1;
5678 inst
.operands
[i
].vectype
= optype
;
5679 inst
.operands
[i
].present
= 1;
5682 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5686 inst
.operands
[i
].reg
= val
;
5687 inst
.operands
[i
].isreg
= 1;
5688 inst
.operands
[i
].isvec
= 1;
5689 inst
.operands
[i
].issingle
= 1;
5690 inst
.operands
[i
].vectype
= optype
;
5691 inst
.operands
[i
++].present
= 1;
5696 first_error (_("parse error"));
5700 /* Successfully parsed the operands. Update args. */
5706 first_error (_("expected comma"));
5710 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5714 /* Matcher codes for parse_operands. */
5715 enum operand_parse_code
5717 OP_stop
, /* end of line */
5719 OP_RR
, /* ARM register */
5720 OP_RRnpc
, /* ARM register, not r15 */
5721 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5722 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5723 OP_RCP
, /* Coprocessor number */
5724 OP_RCN
, /* Coprocessor register */
5725 OP_RF
, /* FPA register */
5726 OP_RVS
, /* VFP single precision register */
5727 OP_RVD
, /* VFP double precision register (0..15) */
5728 OP_RND
, /* Neon double precision register (0..31) */
5729 OP_RNQ
, /* Neon quad precision register */
5730 OP_RVSD
, /* VFP single or double precision register */
5731 OP_RNDQ
, /* Neon double or quad precision register */
5732 OP_RNSDQ
, /* Neon single, double or quad precision register */
5733 OP_RNSC
, /* Neon scalar D[X] */
5734 OP_RVC
, /* VFP control register */
5735 OP_RMF
, /* Maverick F register */
5736 OP_RMD
, /* Maverick D register */
5737 OP_RMFX
, /* Maverick FX register */
5738 OP_RMDX
, /* Maverick DX register */
5739 OP_RMAX
, /* Maverick AX register */
5740 OP_RMDS
, /* Maverick DSPSC register */
5741 OP_RIWR
, /* iWMMXt wR register */
5742 OP_RIWC
, /* iWMMXt wC register */
5743 OP_RIWG
, /* iWMMXt wCG register */
5744 OP_RXA
, /* XScale accumulator register */
5746 OP_REGLST
, /* ARM register list */
5747 OP_VRSLST
, /* VFP single-precision register list */
5748 OP_VRDLST
, /* VFP double-precision register list */
5749 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5750 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5751 OP_NSTRLST
, /* Neon element/structure list */
5753 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5754 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5755 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5756 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5757 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5758 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5759 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5760 OP_VMOV
, /* Neon VMOV operands. */
5761 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5762 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5763 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5765 OP_I0
, /* immediate zero */
5766 OP_I7
, /* immediate value 0 .. 7 */
5767 OP_I15
, /* 0 .. 15 */
5768 OP_I16
, /* 1 .. 16 */
5769 OP_I16z
, /* 0 .. 16 */
5770 OP_I31
, /* 0 .. 31 */
5771 OP_I31w
, /* 0 .. 31, optional trailing ! */
5772 OP_I32
, /* 1 .. 32 */
5773 OP_I32z
, /* 0 .. 32 */
5774 OP_I63
, /* 0 .. 63 */
5775 OP_I63s
, /* -64 .. 63 */
5776 OP_I64
, /* 1 .. 64 */
5777 OP_I64z
, /* 0 .. 64 */
5778 OP_I255
, /* 0 .. 255 */
5780 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5781 OP_I7b
, /* 0 .. 7 */
5782 OP_I15b
, /* 0 .. 15 */
5783 OP_I31b
, /* 0 .. 31 */
5785 OP_SH
, /* shifter operand */
5786 OP_SHG
, /* shifter operand with possible group relocation */
5787 OP_ADDR
, /* Memory address expression (any mode) */
5788 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5789 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5790 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5791 OP_EXP
, /* arbitrary expression */
5792 OP_EXPi
, /* same, with optional immediate prefix */
5793 OP_EXPr
, /* same, with optional relocation suffix */
5794 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5796 OP_CPSF
, /* CPS flags */
5797 OP_ENDI
, /* Endianness specifier */
5798 OP_PSR
, /* CPSR/SPSR mask for msr */
5799 OP_COND
, /* conditional code */
5800 OP_TB
, /* Table branch. */
5802 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5803 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5805 OP_RRnpc_I0
, /* ARM register or literal 0 */
5806 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5807 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5808 OP_RF_IF
, /* FPA register or immediate */
5809 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5810 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5812 /* Optional operands. */
5813 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5814 OP_oI31b
, /* 0 .. 31 */
5815 OP_oI32b
, /* 1 .. 32 */
5816 OP_oIffffb
, /* 0 .. 65535 */
5817 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5819 OP_oRR
, /* ARM register */
5820 OP_oRRnpc
, /* ARM register, not the PC */
5821 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5822 OP_oRND
, /* Optional Neon double precision register */
5823 OP_oRNQ
, /* Optional Neon quad precision register */
5824 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5825 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5826 OP_oSHll
, /* LSL immediate */
5827 OP_oSHar
, /* ASR immediate */
5828 OP_oSHllar
, /* LSL or ASR immediate */
5829 OP_oROR
, /* ROR 0/8/16/24 */
5830 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5832 OP_FIRST_OPTIONAL
= OP_oI7b
5835 /* Generic instruction operand parser. This does no encoding and no
5836 semantic validation; it merely squirrels values away in the inst
5837 structure. Returns SUCCESS or FAIL depending on whether the
5838 specified grammar matched. */
5840 parse_operands (char *str
, const unsigned char *pattern
)
5842 unsigned const char *upat
= pattern
;
5843 char *backtrack_pos
= 0;
5844 const char *backtrack_error
= 0;
5845 int i
, val
, backtrack_index
= 0;
5846 enum arm_reg_type rtype
;
5847 parse_operand_result result
;
5849 #define po_char_or_fail(chr) \
5852 if (skip_past_char (&str, chr) == FAIL) \
5857 #define po_reg_or_fail(regtype) \
5860 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5861 & inst.operands[i].vectype); \
5864 first_error (_(reg_expected_msgs[regtype])); \
5867 inst.operands[i].reg = val; \
5868 inst.operands[i].isreg = 1; \
5869 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5870 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5871 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5872 || rtype == REG_TYPE_VFD \
5873 || rtype == REG_TYPE_NQ); \
5877 #define po_reg_or_goto(regtype, label) \
5880 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5881 & inst.operands[i].vectype); \
5885 inst.operands[i].reg = val; \
5886 inst.operands[i].isreg = 1; \
5887 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5888 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5889 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5890 || rtype == REG_TYPE_VFD \
5891 || rtype == REG_TYPE_NQ); \
5895 #define po_imm_or_fail(min, max, popt) \
5898 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5900 inst.operands[i].imm = val; \
5904 #define po_scalar_or_goto(elsz, label) \
5907 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
5910 inst.operands[i].reg = val; \
5911 inst.operands[i].isscalar = 1; \
5915 #define po_misc_or_fail(expr) \
5923 #define po_misc_or_fail_no_backtrack(expr) \
5927 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
5928 backtrack_pos = 0; \
5929 if (result != PARSE_OPERAND_SUCCESS) \
5934 skip_whitespace (str
);
5936 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5938 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5940 /* Remember where we are in case we need to backtrack. */
5941 gas_assert (!backtrack_pos
);
5942 backtrack_pos
= str
;
5943 backtrack_error
= inst
.error
;
5944 backtrack_index
= i
;
5947 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5948 po_char_or_fail (',');
5956 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5957 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5958 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5959 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5960 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5961 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5963 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5965 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
5967 /* Also accept generic coprocessor regs for unknown registers. */
5969 po_reg_or_fail (REG_TYPE_CN
);
5971 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5972 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5973 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5974 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5975 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5976 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5977 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5978 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5979 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5980 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5982 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5984 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5985 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5987 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5989 /* Neon scalar. Using an element size of 8 means that some invalid
5990 scalars are accepted here, so deal with those in later code. */
5991 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5993 /* WARNING: We can expand to two operands here. This has the potential
5994 to totally confuse the backtracking mechanism! It will be OK at
5995 least as long as we don't try to use optional args as well,
5999 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
6000 inst
.operands
[i
].present
= 1;
6002 skip_past_comma (&str
);
6003 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
6006 /* Optional register operand was omitted. Unfortunately, it's in
6007 operands[i-1] and we need it to be in inst.operands[i]. Fix that
6008 here (this is a bit grotty). */
6009 inst
.operands
[i
] = inst
.operands
[i
-1];
6010 inst
.operands
[i
-1].present
= 0;
6013 /* There's a possibility of getting a 64-bit immediate here, so
6014 we need special handling. */
6015 if (parse_big_immediate (&str
, i
) == FAIL
)
6017 inst
.error
= _("immediate value is out of range");
6025 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6028 po_imm_or_fail (0, 0, TRUE
);
6033 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6038 po_scalar_or_goto (8, try_rr
);
6041 po_reg_or_fail (REG_TYPE_RN
);
6047 po_scalar_or_goto (8, try_nsdq
);
6050 po_reg_or_fail (REG_TYPE_NSDQ
);
6056 po_scalar_or_goto (8, try_ndq
);
6059 po_reg_or_fail (REG_TYPE_NDQ
);
6065 po_scalar_or_goto (8, try_vfd
);
6068 po_reg_or_fail (REG_TYPE_VFD
);
6073 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6074 not careful then bad things might happen. */
6075 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6080 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
6083 /* There's a possibility of getting a 64-bit immediate here, so
6084 we need special handling. */
6085 if (parse_big_immediate (&str
, i
) == FAIL
)
6087 inst
.error
= _("immediate value is out of range");
6095 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6098 po_imm_or_fail (0, 63, TRUE
);
6103 po_char_or_fail ('[');
6104 po_reg_or_fail (REG_TYPE_RN
);
6105 po_char_or_fail (']');
6110 po_reg_or_fail (REG_TYPE_RN
);
6111 if (skip_past_char (&str
, '!') == SUCCESS
)
6112 inst
.operands
[i
].writeback
= 1;
6116 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6117 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6118 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6119 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6120 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6121 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6122 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6123 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6124 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6125 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6126 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6127 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6129 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6131 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6132 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6134 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6135 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6136 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6138 /* Immediate variants */
6140 po_char_or_fail ('{');
6141 po_imm_or_fail (0, 255, TRUE
);
6142 po_char_or_fail ('}');
6146 /* The expression parser chokes on a trailing !, so we have
6147 to find it first and zap it. */
6150 while (*s
&& *s
!= ',')
6155 inst
.operands
[i
].writeback
= 1;
6157 po_imm_or_fail (0, 31, TRUE
);
6165 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6170 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6175 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6177 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6179 val
= parse_reloc (&str
);
6182 inst
.error
= _("unrecognized relocation suffix");
6185 else if (val
!= BFD_RELOC_UNUSED
)
6187 inst
.operands
[i
].imm
= val
;
6188 inst
.operands
[i
].hasreloc
= 1;
6193 /* Operand for MOVW or MOVT. */
6195 po_misc_or_fail (parse_half (&str
));
6198 /* Register or expression. */
6199 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6200 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6202 /* Register or immediate. */
6203 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6204 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6206 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6208 if (!is_immediate_prefix (*str
))
6211 val
= parse_fpa_immediate (&str
);
6214 /* FPA immediates are encoded as registers 8-15.
6215 parse_fpa_immediate has already applied the offset. */
6216 inst
.operands
[i
].reg
= val
;
6217 inst
.operands
[i
].isreg
= 1;
6220 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6221 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6223 /* Two kinds of register. */
6226 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6228 || (rege
->type
!= REG_TYPE_MMXWR
6229 && rege
->type
!= REG_TYPE_MMXWC
6230 && rege
->type
!= REG_TYPE_MMXWCG
))
6232 inst
.error
= _("iWMMXt data or control register expected");
6235 inst
.operands
[i
].reg
= rege
->number
;
6236 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6242 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6244 || (rege
->type
!= REG_TYPE_MMXWC
6245 && rege
->type
!= REG_TYPE_MMXWCG
))
6247 inst
.error
= _("iWMMXt control register expected");
6250 inst
.operands
[i
].reg
= rege
->number
;
6251 inst
.operands
[i
].isreg
= 1;
6256 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6257 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6258 case OP_oROR
: val
= parse_ror (&str
); break;
6259 case OP_PSR
: val
= parse_psr (&str
); break;
6260 case OP_COND
: val
= parse_cond (&str
); break;
6261 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
6264 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
6265 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
6268 val
= parse_psr (&str
);
6272 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6275 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6277 if (strncasecmp (str
, "APSR_", 5) == 0)
6284 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6285 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6286 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6287 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6288 default: found
= 16;
6292 inst
.operands
[i
].isvec
= 1;
6299 po_misc_or_fail (parse_tb (&str
));
6302 /* Register lists. */
6304 val
= parse_reg_list (&str
);
6307 inst
.operands
[1].writeback
= 1;
6313 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6317 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6321 /* Allow Q registers too. */
6322 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6327 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6329 inst
.operands
[i
].issingle
= 1;
6334 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6339 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6340 &inst
.operands
[i
].vectype
);
6343 /* Addressing modes */
6345 po_misc_or_fail (parse_address (&str
, i
));
6349 po_misc_or_fail_no_backtrack (
6350 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6354 po_misc_or_fail_no_backtrack (
6355 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6359 po_misc_or_fail_no_backtrack (
6360 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6364 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6368 po_misc_or_fail_no_backtrack (
6369 parse_shifter_operand_group_reloc (&str
, i
));
6373 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6377 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6381 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6385 as_fatal (_("unhandled operand code %d"), upat
[i
]);
6388 /* Various value-based sanity checks and shared operations. We
6389 do not signal immediate failures for the register constraints;
6390 this allows a syntax error to take precedence. */
6399 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6400 inst
.error
= BAD_PC
;
6418 inst
.operands
[i
].imm
= val
;
6425 /* If we get here, this operand was successfully parsed. */
6426 inst
.operands
[i
].present
= 1;
6430 inst
.error
= BAD_ARGS
;
6435 /* The parse routine should already have set inst.error, but set a
6436 default here just in case. */
6438 inst
.error
= _("syntax error");
6442 /* Do not backtrack over a trailing optional argument that
6443 absorbed some text. We will only fail again, with the
6444 'garbage following instruction' error message, which is
6445 probably less helpful than the current one. */
6446 if (backtrack_index
== i
&& backtrack_pos
!= str
6447 && upat
[i
+1] == OP_stop
)
6450 inst
.error
= _("syntax error");
6454 /* Try again, skipping the optional argument at backtrack_pos. */
6455 str
= backtrack_pos
;
6456 inst
.error
= backtrack_error
;
6457 inst
.operands
[backtrack_index
].present
= 0;
6458 i
= backtrack_index
;
6462 /* Check that we have parsed all the arguments. */
6463 if (*str
!= '\0' && !inst
.error
)
6464 inst
.error
= _("garbage following instruction");
6466 return inst
.error
? FAIL
: SUCCESS
;
6469 #undef po_char_or_fail
6470 #undef po_reg_or_fail
6471 #undef po_reg_or_goto
6472 #undef po_imm_or_fail
6473 #undef po_scalar_or_fail
6475 /* Shorthand macro for instruction encoding functions issuing errors. */
6476 #define constraint(expr, err) \
6487 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6488 instructions are unpredictable if these registers are used. This
6489 is the BadReg predicate in ARM's Thumb-2 documentation. */
6490 #define reject_bad_reg(reg) \
6492 if (reg == REG_SP || reg == REG_PC) \
6494 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6499 /* If REG is R13 (the stack pointer), warn that its use is
6501 #define warn_deprecated_sp(reg) \
6503 if (warn_on_deprecated && reg == REG_SP) \
6504 as_warn (_("use of r13 is deprecated")); \
6507 /* Functions for operand encoding. ARM, then Thumb. */
6509 #define rotate_left(v, n) (v << n | v >> (32 - n))
6511 /* If VAL can be encoded in the immediate field of an ARM instruction,
6512 return the encoded form. Otherwise, return FAIL. */
6515 encode_arm_immediate (unsigned int val
)
6519 for (i
= 0; i
< 32; i
+= 2)
6520 if ((a
= rotate_left (val
, i
)) <= 0xff)
6521 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6526 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6527 return the encoded form. Otherwise, return FAIL. */
6529 encode_thumb32_immediate (unsigned int val
)
6536 for (i
= 1; i
<= 24; i
++)
6539 if ((val
& ~(0xff << i
)) == 0)
6540 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6544 if (val
== ((a
<< 16) | a
))
6546 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6550 if (val
== ((a
<< 16) | a
))
6551 return 0x200 | (a
>> 8);
6555 /* Encode a VFP SP or DP register number into inst.instruction. */
6558 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6560 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6563 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6566 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6569 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6574 first_error (_("D register out of range for selected VFP version"));
6582 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6586 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6590 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6594 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6598 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6602 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6610 /* Encode a <shift> in an ARM-format instruction. The immediate,
6611 if any, is handled by md_apply_fix. */
6613 encode_arm_shift (int i
)
6615 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6616 inst
.instruction
|= SHIFT_ROR
<< 5;
6619 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6620 if (inst
.operands
[i
].immisreg
)
6622 inst
.instruction
|= SHIFT_BY_REG
;
6623 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6626 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6631 encode_arm_shifter_operand (int i
)
6633 if (inst
.operands
[i
].isreg
)
6635 inst
.instruction
|= inst
.operands
[i
].reg
;
6636 encode_arm_shift (i
);
6639 inst
.instruction
|= INST_IMMEDIATE
;
6642 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6644 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6646 gas_assert (inst
.operands
[i
].isreg
);
6647 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6649 if (inst
.operands
[i
].preind
)
6653 inst
.error
= _("instruction does not accept preindexed addressing");
6656 inst
.instruction
|= PRE_INDEX
;
6657 if (inst
.operands
[i
].writeback
)
6658 inst
.instruction
|= WRITE_BACK
;
6661 else if (inst
.operands
[i
].postind
)
6663 gas_assert (inst
.operands
[i
].writeback
);
6665 inst
.instruction
|= WRITE_BACK
;
6667 else /* unindexed - only for coprocessor */
6669 inst
.error
= _("instruction does not accept unindexed addressing");
6673 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6674 && (((inst
.instruction
& 0x000f0000) >> 16)
6675 == ((inst
.instruction
& 0x0000f000) >> 12)))
6676 as_warn ((inst
.instruction
& LOAD_BIT
)
6677 ? _("destination register same as write-back base")
6678 : _("source register same as write-back base"));
6681 /* inst.operands[i] was set up by parse_address. Encode it into an
6682 ARM-format mode 2 load or store instruction. If is_t is true,
6683 reject forms that cannot be used with a T instruction (i.e. not
6686 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6688 encode_arm_addr_mode_common (i
, is_t
);
6690 if (inst
.operands
[i
].immisreg
)
6692 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6693 inst
.instruction
|= inst
.operands
[i
].imm
;
6694 if (!inst
.operands
[i
].negative
)
6695 inst
.instruction
|= INDEX_UP
;
6696 if (inst
.operands
[i
].shifted
)
6698 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6699 inst
.instruction
|= SHIFT_ROR
<< 5;
6702 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6703 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6707 else /* immediate offset in inst.reloc */
6709 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6710 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6714 /* inst.operands[i] was set up by parse_address. Encode it into an
6715 ARM-format mode 3 load or store instruction. Reject forms that
6716 cannot be used with such instructions. If is_t is true, reject
6717 forms that cannot be used with a T instruction (i.e. not
6720 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6722 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6724 inst
.error
= _("instruction does not accept scaled register index");
6728 encode_arm_addr_mode_common (i
, is_t
);
6730 if (inst
.operands
[i
].immisreg
)
6732 inst
.instruction
|= inst
.operands
[i
].imm
;
6733 if (!inst
.operands
[i
].negative
)
6734 inst
.instruction
|= INDEX_UP
;
6736 else /* immediate offset in inst.reloc */
6738 inst
.instruction
|= HWOFFSET_IMM
;
6739 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6740 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6744 /* inst.operands[i] was set up by parse_address. Encode it into an
6745 ARM-format instruction. Reject all forms which cannot be encoded
6746 into a coprocessor load/store instruction. If wb_ok is false,
6747 reject use of writeback; if unind_ok is false, reject use of
6748 unindexed addressing. If reloc_override is not 0, use it instead
6749 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6750 (in which case it is preserved). */
6753 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6755 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6757 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6759 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6761 gas_assert (!inst
.operands
[i
].writeback
);
6764 inst
.error
= _("instruction does not support unindexed addressing");
6767 inst
.instruction
|= inst
.operands
[i
].imm
;
6768 inst
.instruction
|= INDEX_UP
;
6772 if (inst
.operands
[i
].preind
)
6773 inst
.instruction
|= PRE_INDEX
;
6775 if (inst
.operands
[i
].writeback
)
6777 if (inst
.operands
[i
].reg
== REG_PC
)
6779 inst
.error
= _("pc may not be used with write-back");
6784 inst
.error
= _("instruction does not support writeback");
6787 inst
.instruction
|= WRITE_BACK
;
6791 inst
.reloc
.type
= reloc_override
;
6792 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6793 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6794 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6797 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6799 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6805 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6806 Determine whether it can be performed with a move instruction; if
6807 it can, convert inst.instruction to that move instruction and
6808 return TRUE; if it can't, convert inst.instruction to a literal-pool
6809 load and return FALSE. If this is not a valid thing to do in the
6810 current context, set inst.error and return TRUE.
6812 inst.operands[i] describes the destination register. */
6815 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6820 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6824 if ((inst
.instruction
& tbit
) == 0)
6826 inst
.error
= _("invalid pseudo operation");
6829 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6831 inst
.error
= _("constant expression expected");
6834 if (inst
.reloc
.exp
.X_op
== O_constant
)
6838 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6840 /* This can be done with a mov(1) instruction. */
6841 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6842 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6848 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6851 /* This can be done with a mov instruction. */
6852 inst
.instruction
&= LITERAL_MASK
;
6853 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6854 inst
.instruction
|= value
& 0xfff;
6858 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6861 /* This can be done with a mvn instruction. */
6862 inst
.instruction
&= LITERAL_MASK
;
6863 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6864 inst
.instruction
|= value
& 0xfff;
6870 if (add_to_lit_pool () == FAIL
)
6872 inst
.error
= _("literal pool insertion failed");
6875 inst
.operands
[1].reg
= REG_PC
;
6876 inst
.operands
[1].isreg
= 1;
6877 inst
.operands
[1].preind
= 1;
6878 inst
.reloc
.pc_rel
= 1;
6879 inst
.reloc
.type
= (thumb_p
6880 ? BFD_RELOC_ARM_THUMB_OFFSET
6882 ? BFD_RELOC_ARM_HWLITERAL
6883 : BFD_RELOC_ARM_LITERAL
));
6887 /* Functions for instruction encoding, sorted by sub-architecture.
6888 First some generics; their names are taken from the conventional
6889 bit positions for register arguments in ARM format instructions. */
6899 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6905 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6906 inst
.instruction
|= inst
.operands
[1].reg
;
6912 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6913 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6919 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6920 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6926 unsigned Rn
= inst
.operands
[2].reg
;
6927 /* Enforce restrictions on SWP instruction. */
6928 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6929 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6930 _("Rn must not overlap other operands"));
6931 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6932 inst
.instruction
|= inst
.operands
[1].reg
;
6933 inst
.instruction
|= Rn
<< 16;
6939 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6940 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6941 inst
.instruction
|= inst
.operands
[2].reg
;
6947 inst
.instruction
|= inst
.operands
[0].reg
;
6948 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6949 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6955 inst
.instruction
|= inst
.operands
[0].imm
;
6961 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6962 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6965 /* ARM instructions, in alphabetical order by function name (except
6966 that wrapper functions appear immediately after the function they
6969 /* This is a pseudo-op of the form "adr rd, label" to be converted
6970 into a relative address of the form "add rd, pc, #label-.-8". */
6975 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6977 /* Frag hacking will turn this into a sub instruction if the offset turns
6978 out to be negative. */
6979 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6980 inst
.reloc
.pc_rel
= 1;
6981 inst
.reloc
.exp
.X_add_number
-= 8;
6984 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6985 into a relative address of the form:
6986 add rd, pc, #low(label-.-8)"
6987 add rd, rd, #high(label-.-8)" */
6992 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6994 /* Frag hacking will turn this into a sub instruction if the offset turns
6995 out to be negative. */
6996 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6997 inst
.reloc
.pc_rel
= 1;
6998 inst
.size
= INSN_SIZE
* 2;
6999 inst
.reloc
.exp
.X_add_number
-= 8;
7005 if (!inst
.operands
[1].present
)
7006 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7007 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7008 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7009 encode_arm_shifter_operand (2);
7015 if (inst
.operands
[0].present
)
7017 constraint ((inst
.instruction
& 0xf0) != 0x40
7018 && inst
.operands
[0].imm
!= 0xf,
7019 _("bad barrier type"));
7020 inst
.instruction
|= inst
.operands
[0].imm
;
7023 inst
.instruction
|= 0xf;
7029 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7030 constraint (msb
> 32, _("bit-field extends past end of register"));
7031 /* The instruction encoding stores the LSB and MSB,
7032 not the LSB and width. */
7033 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7034 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7035 inst
.instruction
|= (msb
- 1) << 16;
7043 /* #0 in second position is alternative syntax for bfc, which is
7044 the same instruction but with REG_PC in the Rm field. */
7045 if (!inst
.operands
[1].isreg
)
7046 inst
.operands
[1].reg
= REG_PC
;
7048 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7049 constraint (msb
> 32, _("bit-field extends past end of register"));
7050 /* The instruction encoding stores the LSB and MSB,
7051 not the LSB and width. */
7052 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7053 inst
.instruction
|= inst
.operands
[1].reg
;
7054 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7055 inst
.instruction
|= (msb
- 1) << 16;
7061 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7062 _("bit-field extends past end of register"));
7063 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7064 inst
.instruction
|= inst
.operands
[1].reg
;
7065 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7066 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7069 /* ARM V5 breakpoint instruction (argument parse)
7070 BKPT <16 bit unsigned immediate>
7071 Instruction is not conditional.
7072 The bit pattern given in insns[] has the COND_ALWAYS condition,
7073 and it is an error if the caller tried to override that. */
7078 /* Top 12 of 16 bits to bits 19:8. */
7079 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7081 /* Bottom 4 of 16 bits to bits 3:0. */
7082 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7086 encode_branch (int default_reloc
)
7088 if (inst
.operands
[0].hasreloc
)
7090 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
7091 _("the only suffix valid here is '(plt)'"));
7092 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
7096 inst
.reloc
.type
= default_reloc
;
7098 inst
.reloc
.pc_rel
= 1;
7105 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7106 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7109 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7116 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7118 if (inst
.cond
== COND_ALWAYS
)
7119 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7121 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7125 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7128 /* ARM V5 branch-link-exchange instruction (argument parse)
7129 BLX <target_addr> ie BLX(1)
7130 BLX{<condition>} <Rm> ie BLX(2)
7131 Unfortunately, there are two different opcodes for this mnemonic.
7132 So, the insns[].value is not used, and the code here zaps values
7133 into inst.instruction.
7134 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7139 if (inst
.operands
[0].isreg
)
7141 /* Arg is a register; the opcode provided by insns[] is correct.
7142 It is not illegal to do "blx pc", just useless. */
7143 if (inst
.operands
[0].reg
== REG_PC
)
7144 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7146 inst
.instruction
|= inst
.operands
[0].reg
;
7150 /* Arg is an address; this instruction cannot be executed
7151 conditionally, and the opcode must be adjusted.
7152 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7153 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7154 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7155 inst
.instruction
= 0xfa000000;
7156 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7163 bfd_boolean want_reloc
;
7165 if (inst
.operands
[0].reg
== REG_PC
)
7166 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7168 inst
.instruction
|= inst
.operands
[0].reg
;
7169 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7170 it is for ARMv4t or earlier. */
7171 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7172 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7176 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7181 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7185 /* ARM v5TEJ. Jump to Jazelle code. */
7190 if (inst
.operands
[0].reg
== REG_PC
)
7191 as_tsktsk (_("use of r15 in bxj is not really useful"));
7193 inst
.instruction
|= inst
.operands
[0].reg
;
7196 /* Co-processor data operation:
7197 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7198 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7202 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7203 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7204 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7205 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7206 inst
.instruction
|= inst
.operands
[4].reg
;
7207 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7213 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7214 encode_arm_shifter_operand (1);
7217 /* Transfer between coprocessor and ARM registers.
7218 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7223 No special properties. */
7230 Rd
= inst
.operands
[2].reg
;
7233 if (inst
.instruction
== 0xee000010
7234 || inst
.instruction
== 0xfe000010)
7236 reject_bad_reg (Rd
);
7239 constraint (Rd
== REG_SP
, BAD_SP
);
7244 if (inst
.instruction
== 0xe000010)
7245 constraint (Rd
== REG_PC
, BAD_PC
);
7249 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7250 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7251 inst
.instruction
|= Rd
<< 12;
7252 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7253 inst
.instruction
|= inst
.operands
[4].reg
;
7254 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7257 /* Transfer between coprocessor register and pair of ARM registers.
7258 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7263 Two XScale instructions are special cases of these:
7265 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7266 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7268 Result unpredictable if Rd or Rn is R15. */
7275 Rd
= inst
.operands
[2].reg
;
7276 Rn
= inst
.operands
[3].reg
;
7280 reject_bad_reg (Rd
);
7281 reject_bad_reg (Rn
);
7285 constraint (Rd
== REG_PC
, BAD_PC
);
7286 constraint (Rn
== REG_PC
, BAD_PC
);
7289 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7290 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7291 inst
.instruction
|= Rd
<< 12;
7292 inst
.instruction
|= Rn
<< 16;
7293 inst
.instruction
|= inst
.operands
[4].reg
;
7299 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7300 if (inst
.operands
[1].present
)
7302 inst
.instruction
|= CPSI_MMOD
;
7303 inst
.instruction
|= inst
.operands
[1].imm
;
7310 inst
.instruction
|= inst
.operands
[0].imm
;
7316 /* There is no IT instruction in ARM mode. We
7317 process it to do the validation as if in
7318 thumb mode, just in case the code gets
7319 assembled for thumb using the unified syntax. */
7324 set_it_insn_type (IT_INSN
);
7325 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7326 now_it
.cc
= inst
.operands
[0].imm
;
7333 int base_reg
= inst
.operands
[0].reg
;
7334 int range
= inst
.operands
[1].imm
;
7336 inst
.instruction
|= base_reg
<< 16;
7337 inst
.instruction
|= range
;
7339 if (inst
.operands
[1].writeback
)
7340 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7342 if (inst
.operands
[0].writeback
)
7344 inst
.instruction
|= WRITE_BACK
;
7345 /* Check for unpredictable uses of writeback. */
7346 if (inst
.instruction
& LOAD_BIT
)
7348 /* Not allowed in LDM type 2. */
7349 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7350 && ((range
& (1 << REG_PC
)) == 0))
7351 as_warn (_("writeback of base register is UNPREDICTABLE"));
7352 /* Only allowed if base reg not in list for other types. */
7353 else if (range
& (1 << base_reg
))
7354 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7358 /* Not allowed for type 2. */
7359 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7360 as_warn (_("writeback of base register is UNPREDICTABLE"));
7361 /* Only allowed if base reg not in list, or first in list. */
7362 else if ((range
& (1 << base_reg
))
7363 && (range
& ((1 << base_reg
) - 1)))
7364 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7369 /* ARMv5TE load-consecutive (argument parse)
7378 constraint (inst
.operands
[0].reg
% 2 != 0,
7379 _("first destination register must be even"));
7380 constraint (inst
.operands
[1].present
7381 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7382 _("can only load two consecutive registers"));
7383 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7384 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7386 if (!inst
.operands
[1].present
)
7387 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7389 if (inst
.instruction
& LOAD_BIT
)
7391 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7392 register and the first register written; we have to diagnose
7393 overlap between the base and the second register written here. */
7395 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7396 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7397 as_warn (_("base register written back, and overlaps "
7398 "second destination register"));
7400 /* For an index-register load, the index register must not overlap the
7401 destination (even if not write-back). */
7402 else if (inst
.operands
[2].immisreg
7403 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7404 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7405 as_warn (_("index register overlaps destination register"));
7408 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7409 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7415 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7416 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7417 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7418 || inst
.operands
[1].negative
7419 /* This can arise if the programmer has written
7421 or if they have mistakenly used a register name as the last
7424 It is very difficult to distinguish between these two cases
7425 because "rX" might actually be a label. ie the register
7426 name has been occluded by a symbol of the same name. So we
7427 just generate a general 'bad addressing mode' type error
7428 message and leave it up to the programmer to discover the
7429 true cause and fix their mistake. */
7430 || (inst
.operands
[1].reg
== REG_PC
),
7433 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7434 || inst
.reloc
.exp
.X_add_number
!= 0,
7435 _("offset must be zero in ARM encoding"));
7437 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7438 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7439 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7445 constraint (inst
.operands
[0].reg
% 2 != 0,
7446 _("even register required"));
7447 constraint (inst
.operands
[1].present
7448 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7449 _("can only load two consecutive registers"));
7450 /* If op 1 were present and equal to PC, this function wouldn't
7451 have been called in the first place. */
7452 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7454 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7455 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7461 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7462 if (!inst
.operands
[1].isreg
)
7463 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7465 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7471 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7473 if (inst
.operands
[1].preind
)
7475 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7476 || inst
.reloc
.exp
.X_add_number
!= 0,
7477 _("this instruction requires a post-indexed address"));
7479 inst
.operands
[1].preind
= 0;
7480 inst
.operands
[1].postind
= 1;
7481 inst
.operands
[1].writeback
= 1;
7483 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7484 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7487 /* Halfword and signed-byte load/store operations. */
7492 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7493 if (!inst
.operands
[1].isreg
)
7494 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7496 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7502 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7504 if (inst
.operands
[1].preind
)
7506 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7507 || inst
.reloc
.exp
.X_add_number
!= 0,
7508 _("this instruction requires a post-indexed address"));
7510 inst
.operands
[1].preind
= 0;
7511 inst
.operands
[1].postind
= 1;
7512 inst
.operands
[1].writeback
= 1;
7514 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7515 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7518 /* Co-processor register load/store.
7519 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7523 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7524 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7525 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7531 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7532 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7533 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7534 && !(inst
.instruction
& 0x00400000))
7535 as_tsktsk (_("Rd and Rm should be different in mla"));
7537 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7538 inst
.instruction
|= inst
.operands
[1].reg
;
7539 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7540 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7546 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7547 encode_arm_shifter_operand (1);
7550 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7557 top
= (inst
.instruction
& 0x00400000) != 0;
7558 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7559 _(":lower16: not allowed this instruction"));
7560 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7561 _(":upper16: not allowed instruction"));
7562 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7563 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7565 imm
= inst
.reloc
.exp
.X_add_number
;
7566 /* The value is in two pieces: 0:11, 16:19. */
7567 inst
.instruction
|= (imm
& 0x00000fff);
7568 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7572 static void do_vfp_nsyn_opcode (const char *);
7575 do_vfp_nsyn_mrs (void)
7577 if (inst
.operands
[0].isvec
)
7579 if (inst
.operands
[1].reg
!= 1)
7580 first_error (_("operand 1 must be FPSCR"));
7581 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7582 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7583 do_vfp_nsyn_opcode ("fmstat");
7585 else if (inst
.operands
[1].isvec
)
7586 do_vfp_nsyn_opcode ("fmrx");
7594 do_vfp_nsyn_msr (void)
7596 if (inst
.operands
[0].isvec
)
7597 do_vfp_nsyn_opcode ("fmxr");
7607 if (do_vfp_nsyn_mrs () == SUCCESS
)
7610 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7611 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7613 _("'CPSR' or 'SPSR' expected"));
7614 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7615 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7618 /* Two possible forms:
7619 "{C|S}PSR_<field>, Rm",
7620 "{C|S}PSR_f, #expression". */
7625 if (do_vfp_nsyn_msr () == SUCCESS
)
7628 inst
.instruction
|= inst
.operands
[0].imm
;
7629 if (inst
.operands
[1].isreg
)
7630 inst
.instruction
|= inst
.operands
[1].reg
;
7633 inst
.instruction
|= INST_IMMEDIATE
;
7634 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7635 inst
.reloc
.pc_rel
= 0;
7642 if (!inst
.operands
[2].present
)
7643 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7644 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7645 inst
.instruction
|= inst
.operands
[1].reg
;
7646 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7648 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7649 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7650 as_tsktsk (_("Rd and Rm should be different in mul"));
7653 /* Long Multiply Parser
7654 UMULL RdLo, RdHi, Rm, Rs
7655 SMULL RdLo, RdHi, Rm, Rs
7656 UMLAL RdLo, RdHi, Rm, Rs
7657 SMLAL RdLo, RdHi, Rm, Rs. */
7662 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7663 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7664 inst
.instruction
|= inst
.operands
[2].reg
;
7665 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7667 /* rdhi and rdlo must be different. */
7668 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7669 as_tsktsk (_("rdhi and rdlo must be different"));
7671 /* rdhi, rdlo and rm must all be different before armv6. */
7672 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7673 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7674 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7675 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7681 if (inst
.operands
[0].present
7682 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7684 /* Architectural NOP hints are CPSR sets with no bits selected. */
7685 inst
.instruction
&= 0xf0000000;
7686 inst
.instruction
|= 0x0320f000;
7687 if (inst
.operands
[0].present
)
7688 inst
.instruction
|= inst
.operands
[0].imm
;
7692 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7693 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7694 Condition defaults to COND_ALWAYS.
7695 Error if Rd, Rn or Rm are R15. */
7700 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7701 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7702 inst
.instruction
|= inst
.operands
[2].reg
;
7703 if (inst
.operands
[3].present
)
7704 encode_arm_shift (3);
7707 /* ARM V6 PKHTB (Argument Parse). */
7712 if (!inst
.operands
[3].present
)
7714 /* If the shift specifier is omitted, turn the instruction
7715 into pkhbt rd, rm, rn. */
7716 inst
.instruction
&= 0xfff00010;
7717 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7718 inst
.instruction
|= inst
.operands
[1].reg
;
7719 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7723 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7724 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7725 inst
.instruction
|= inst
.operands
[2].reg
;
7726 encode_arm_shift (3);
7730 /* ARMv5TE: Preload-Cache
7734 Syntactically, like LDR with B=1, W=0, L=1. */
7739 constraint (!inst
.operands
[0].isreg
,
7740 _("'[' expected after PLD mnemonic"));
7741 constraint (inst
.operands
[0].postind
,
7742 _("post-indexed expression used in preload instruction"));
7743 constraint (inst
.operands
[0].writeback
,
7744 _("writeback used in preload instruction"));
7745 constraint (!inst
.operands
[0].preind
,
7746 _("unindexed addressing used in preload instruction"));
7747 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7750 /* ARMv7: PLI <addr_mode> */
7754 constraint (!inst
.operands
[0].isreg
,
7755 _("'[' expected after PLI mnemonic"));
7756 constraint (inst
.operands
[0].postind
,
7757 _("post-indexed expression used in preload instruction"));
7758 constraint (inst
.operands
[0].writeback
,
7759 _("writeback used in preload instruction"));
7760 constraint (!inst
.operands
[0].preind
,
7761 _("unindexed addressing used in preload instruction"));
7762 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7763 inst
.instruction
&= ~PRE_INDEX
;
7769 inst
.operands
[1] = inst
.operands
[0];
7770 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7771 inst
.operands
[0].isreg
= 1;
7772 inst
.operands
[0].writeback
= 1;
7773 inst
.operands
[0].reg
= REG_SP
;
7777 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7778 word at the specified address and the following word
7780 Unconditionally executed.
7781 Error if Rn is R15. */
7786 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7787 if (inst
.operands
[0].writeback
)
7788 inst
.instruction
|= WRITE_BACK
;
7791 /* ARM V6 ssat (argument parse). */
7796 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7797 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7798 inst
.instruction
|= inst
.operands
[2].reg
;
7800 if (inst
.operands
[3].present
)
7801 encode_arm_shift (3);
7804 /* ARM V6 usat (argument parse). */
7809 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7810 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7811 inst
.instruction
|= inst
.operands
[2].reg
;
7813 if (inst
.operands
[3].present
)
7814 encode_arm_shift (3);
7817 /* ARM V6 ssat16 (argument parse). */
7822 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7823 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7824 inst
.instruction
|= inst
.operands
[2].reg
;
7830 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7831 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7832 inst
.instruction
|= inst
.operands
[2].reg
;
7835 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7836 preserving the other bits.
7838 setend <endian_specifier>, where <endian_specifier> is either
7844 if (inst
.operands
[0].imm
)
7845 inst
.instruction
|= 0x200;
7851 unsigned int Rm
= (inst
.operands
[1].present
7852 ? inst
.operands
[1].reg
7853 : inst
.operands
[0].reg
);
7855 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7856 inst
.instruction
|= Rm
;
7857 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7859 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7860 inst
.instruction
|= SHIFT_BY_REG
;
7863 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7869 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7870 inst
.reloc
.pc_rel
= 0;
7876 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7877 inst
.reloc
.pc_rel
= 0;
7880 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7881 SMLAxy{cond} Rd,Rm,Rs,Rn
7882 SMLAWy{cond} Rd,Rm,Rs,Rn
7883 Error if any register is R15. */
7888 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7889 inst
.instruction
|= inst
.operands
[1].reg
;
7890 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7891 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7894 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7895 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7896 Error if any register is R15.
7897 Warning if Rdlo == Rdhi. */
7902 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7903 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7904 inst
.instruction
|= inst
.operands
[2].reg
;
7905 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7907 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7908 as_tsktsk (_("rdhi and rdlo must be different"));
7911 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7912 SMULxy{cond} Rd,Rm,Rs
7913 Error if any register is R15. */
7918 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7919 inst
.instruction
|= inst
.operands
[1].reg
;
7920 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7923 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7924 the same for both ARM and Thumb-2. */
7931 if (inst
.operands
[0].present
)
7933 reg
= inst
.operands
[0].reg
;
7934 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
7939 inst
.instruction
|= reg
<< 16;
7940 inst
.instruction
|= inst
.operands
[1].imm
;
7941 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
7942 inst
.instruction
|= WRITE_BACK
;
7945 /* ARM V6 strex (argument parse). */
7950 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7951 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7952 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7953 || inst
.operands
[2].negative
7954 /* See comment in do_ldrex(). */
7955 || (inst
.operands
[2].reg
== REG_PC
),
7958 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7959 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7961 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7962 || inst
.reloc
.exp
.X_add_number
!= 0,
7963 _("offset must be zero in ARM encoding"));
7965 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7966 inst
.instruction
|= inst
.operands
[1].reg
;
7967 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7968 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7974 constraint (inst
.operands
[1].reg
% 2 != 0,
7975 _("even register required"));
7976 constraint (inst
.operands
[2].present
7977 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7978 _("can only store two consecutive registers"));
7979 /* If op 2 were present and equal to PC, this function wouldn't
7980 have been called in the first place. */
7981 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7983 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7984 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7985 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7988 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7989 inst
.instruction
|= inst
.operands
[1].reg
;
7990 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7993 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7994 extends it to 32-bits, and adds the result to a value in another
7995 register. You can specify a rotation by 0, 8, 16, or 24 bits
7996 before extracting the 16-bit value.
7997 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7998 Condition defaults to COND_ALWAYS.
7999 Error if any register uses R15. */
8004 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8005 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8006 inst
.instruction
|= inst
.operands
[2].reg
;
8007 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8012 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8013 Condition defaults to COND_ALWAYS.
8014 Error if any register uses R15. */
8019 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8020 inst
.instruction
|= inst
.operands
[1].reg
;
8021 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8024 /* VFP instructions. In a logical order: SP variant first, monad
8025 before dyad, arithmetic then move then load/store. */
8028 do_vfp_sp_monadic (void)
8030 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8031 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8035 do_vfp_sp_dyadic (void)
8037 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8038 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8039 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8043 do_vfp_sp_compare_z (void)
8045 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8049 do_vfp_dp_sp_cvt (void)
8051 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8052 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8056 do_vfp_sp_dp_cvt (void)
8058 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8059 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8063 do_vfp_reg_from_sp (void)
8065 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8066 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8070 do_vfp_reg2_from_sp2 (void)
8072 constraint (inst
.operands
[2].imm
!= 2,
8073 _("only two consecutive VFP SP registers allowed here"));
8074 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8075 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8076 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8080 do_vfp_sp_from_reg (void)
8082 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8083 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8087 do_vfp_sp2_from_reg2 (void)
8089 constraint (inst
.operands
[0].imm
!= 2,
8090 _("only two consecutive VFP SP registers allowed here"));
8091 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8092 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8093 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8097 do_vfp_sp_ldst (void)
8099 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8100 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8104 do_vfp_dp_ldst (void)
8106 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8107 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8112 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8114 if (inst
.operands
[0].writeback
)
8115 inst
.instruction
|= WRITE_BACK
;
8117 constraint (ldstm_type
!= VFP_LDSTMIA
,
8118 _("this addressing mode requires base-register writeback"));
8119 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8120 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8121 inst
.instruction
|= inst
.operands
[1].imm
;
8125 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8129 if (inst
.operands
[0].writeback
)
8130 inst
.instruction
|= WRITE_BACK
;
8132 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8133 _("this addressing mode requires base-register writeback"));
8135 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8136 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8138 count
= inst
.operands
[1].imm
<< 1;
8139 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8142 inst
.instruction
|= count
;
8146 do_vfp_sp_ldstmia (void)
8148 vfp_sp_ldstm (VFP_LDSTMIA
);
8152 do_vfp_sp_ldstmdb (void)
8154 vfp_sp_ldstm (VFP_LDSTMDB
);
8158 do_vfp_dp_ldstmia (void)
8160 vfp_dp_ldstm (VFP_LDSTMIA
);
8164 do_vfp_dp_ldstmdb (void)
8166 vfp_dp_ldstm (VFP_LDSTMDB
);
8170 do_vfp_xp_ldstmia (void)
8172 vfp_dp_ldstm (VFP_LDSTMIAX
);
8176 do_vfp_xp_ldstmdb (void)
8178 vfp_dp_ldstm (VFP_LDSTMDBX
);
8182 do_vfp_dp_rd_rm (void)
8184 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8185 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8189 do_vfp_dp_rn_rd (void)
8191 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8192 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8196 do_vfp_dp_rd_rn (void)
8198 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8199 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8203 do_vfp_dp_rd_rn_rm (void)
8205 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8206 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8207 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8213 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8217 do_vfp_dp_rm_rd_rn (void)
8219 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8220 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8221 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8224 /* VFPv3 instructions. */
8226 do_vfp_sp_const (void)
8228 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8229 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8230 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8234 do_vfp_dp_const (void)
8236 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8237 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8238 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8242 vfp_conv (int srcsize
)
8244 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8245 inst
.instruction
|= (immbits
& 1) << 5;
8246 inst
.instruction
|= (immbits
>> 1);
8250 do_vfp_sp_conv_16 (void)
8252 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8257 do_vfp_dp_conv_16 (void)
8259 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8264 do_vfp_sp_conv_32 (void)
8266 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8271 do_vfp_dp_conv_32 (void)
8273 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8277 /* FPA instructions. Also in a logical order. */
8282 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8283 inst
.instruction
|= inst
.operands
[1].reg
;
8287 do_fpa_ldmstm (void)
8289 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8290 switch (inst
.operands
[1].imm
)
8292 case 1: inst
.instruction
|= CP_T_X
; break;
8293 case 2: inst
.instruction
|= CP_T_Y
; break;
8294 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8299 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8301 /* The instruction specified "ea" or "fd", so we can only accept
8302 [Rn]{!}. The instruction does not really support stacking or
8303 unstacking, so we have to emulate these by setting appropriate
8304 bits and offsets. */
8305 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8306 || inst
.reloc
.exp
.X_add_number
!= 0,
8307 _("this instruction does not support indexing"));
8309 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8310 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8312 if (!(inst
.instruction
& INDEX_UP
))
8313 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8315 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8317 inst
.operands
[2].preind
= 0;
8318 inst
.operands
[2].postind
= 1;
8322 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8325 /* iWMMXt instructions: strictly in alphabetical order. */
8328 do_iwmmxt_tandorc (void)
8330 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8334 do_iwmmxt_textrc (void)
8336 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8337 inst
.instruction
|= inst
.operands
[1].imm
;
8341 do_iwmmxt_textrm (void)
8343 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8344 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8345 inst
.instruction
|= inst
.operands
[2].imm
;
8349 do_iwmmxt_tinsr (void)
8351 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8352 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8353 inst
.instruction
|= inst
.operands
[2].imm
;
8357 do_iwmmxt_tmia (void)
8359 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8360 inst
.instruction
|= inst
.operands
[1].reg
;
8361 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8365 do_iwmmxt_waligni (void)
8367 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8368 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8369 inst
.instruction
|= inst
.operands
[2].reg
;
8370 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8374 do_iwmmxt_wmerge (void)
8376 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8377 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8378 inst
.instruction
|= inst
.operands
[2].reg
;
8379 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8383 do_iwmmxt_wmov (void)
8385 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8386 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8387 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8388 inst
.instruction
|= inst
.operands
[1].reg
;
8392 do_iwmmxt_wldstbh (void)
8395 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8397 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8399 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8400 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8404 do_iwmmxt_wldstw (void)
8406 /* RIWR_RIWC clears .isreg for a control register. */
8407 if (!inst
.operands
[0].isreg
)
8409 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8410 inst
.instruction
|= 0xf0000000;
8413 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8414 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8418 do_iwmmxt_wldstd (void)
8420 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8421 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8422 && inst
.operands
[1].immisreg
)
8424 inst
.instruction
&= ~0x1a000ff;
8425 inst
.instruction
|= (0xf << 28);
8426 if (inst
.operands
[1].preind
)
8427 inst
.instruction
|= PRE_INDEX
;
8428 if (!inst
.operands
[1].negative
)
8429 inst
.instruction
|= INDEX_UP
;
8430 if (inst
.operands
[1].writeback
)
8431 inst
.instruction
|= WRITE_BACK
;
8432 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8433 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8434 inst
.instruction
|= inst
.operands
[1].imm
;
8437 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8441 do_iwmmxt_wshufh (void)
8443 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8444 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8445 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8446 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8450 do_iwmmxt_wzero (void)
8452 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8453 inst
.instruction
|= inst
.operands
[0].reg
;
8454 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8455 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8459 do_iwmmxt_wrwrwr_or_imm5 (void)
8461 if (inst
.operands
[2].isreg
)
8464 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8465 _("immediate operand requires iWMMXt2"));
8467 if (inst
.operands
[2].imm
== 0)
8469 switch ((inst
.instruction
>> 20) & 0xf)
8475 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8476 inst
.operands
[2].imm
= 16;
8477 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8483 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8484 inst
.operands
[2].imm
= 32;
8485 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8492 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8494 wrn
= (inst
.instruction
>> 16) & 0xf;
8495 inst
.instruction
&= 0xff0fff0f;
8496 inst
.instruction
|= wrn
;
8497 /* Bail out here; the instruction is now assembled. */
8502 /* Map 32 -> 0, etc. */
8503 inst
.operands
[2].imm
&= 0x1f;
8504 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8508 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8509 operations first, then control, shift, and load/store. */
8511 /* Insns like "foo X,Y,Z". */
8514 do_mav_triple (void)
8516 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8517 inst
.instruction
|= inst
.operands
[1].reg
;
8518 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8521 /* Insns like "foo W,X,Y,Z".
8522 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8527 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8528 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8529 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8530 inst
.instruction
|= inst
.operands
[3].reg
;
8533 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8537 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8540 /* Maverick shift immediate instructions.
8541 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8542 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8547 int imm
= inst
.operands
[2].imm
;
8549 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8550 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8552 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8553 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8554 Bit 4 should be 0. */
8555 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8557 inst
.instruction
|= imm
;
8560 /* XScale instructions. Also sorted arithmetic before move. */
8562 /* Xscale multiply-accumulate (argument parse)
8565 MIAxycc acc0,Rm,Rs. */
8570 inst
.instruction
|= inst
.operands
[1].reg
;
8571 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8574 /* Xscale move-accumulator-register (argument parse)
8576 MARcc acc0,RdLo,RdHi. */
8581 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8582 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8585 /* Xscale move-register-accumulator (argument parse)
8587 MRAcc RdLo,RdHi,acc0. */
8592 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8593 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8594 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8597 /* Encoding functions relevant only to Thumb. */
8599 /* inst.operands[i] is a shifted-register operand; encode
8600 it into inst.instruction in the format used by Thumb32. */
8603 encode_thumb32_shifted_operand (int i
)
8605 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8606 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8608 constraint (inst
.operands
[i
].immisreg
,
8609 _("shift by register not allowed in thumb mode"));
8610 inst
.instruction
|= inst
.operands
[i
].reg
;
8611 if (shift
== SHIFT_RRX
)
8612 inst
.instruction
|= SHIFT_ROR
<< 4;
8615 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8616 _("expression too complex"));
8618 constraint (value
> 32
8619 || (value
== 32 && (shift
== SHIFT_LSL
8620 || shift
== SHIFT_ROR
)),
8621 _("shift expression is too large"));
8625 else if (value
== 32)
8628 inst
.instruction
|= shift
<< 4;
8629 inst
.instruction
|= (value
& 0x1c) << 10;
8630 inst
.instruction
|= (value
& 0x03) << 6;
8635 /* inst.operands[i] was set up by parse_address. Encode it into a
8636 Thumb32 format load or store instruction. Reject forms that cannot
8637 be used with such instructions. If is_t is true, reject forms that
8638 cannot be used with a T instruction; if is_d is true, reject forms
8639 that cannot be used with a D instruction. */
8642 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8644 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8646 constraint (!inst
.operands
[i
].isreg
,
8647 _("Instruction does not support =N addresses"));
8649 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8650 if (inst
.operands
[i
].immisreg
)
8652 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8653 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8654 constraint (inst
.operands
[i
].negative
,
8655 _("Thumb does not support negative register indexing"));
8656 constraint (inst
.operands
[i
].postind
,
8657 _("Thumb does not support register post-indexing"));
8658 constraint (inst
.operands
[i
].writeback
,
8659 _("Thumb does not support register indexing with writeback"));
8660 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8661 _("Thumb supports only LSL in shifted register indexing"));
8663 inst
.instruction
|= inst
.operands
[i
].imm
;
8664 if (inst
.operands
[i
].shifted
)
8666 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8667 _("expression too complex"));
8668 constraint (inst
.reloc
.exp
.X_add_number
< 0
8669 || inst
.reloc
.exp
.X_add_number
> 3,
8670 _("shift out of range"));
8671 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8673 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8675 else if (inst
.operands
[i
].preind
)
8677 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8678 _("cannot use writeback with PC-relative addressing"));
8679 constraint (is_t
&& inst
.operands
[i
].writeback
,
8680 _("cannot use writeback with this instruction"));
8684 inst
.instruction
|= 0x01000000;
8685 if (inst
.operands
[i
].writeback
)
8686 inst
.instruction
|= 0x00200000;
8690 inst
.instruction
|= 0x00000c00;
8691 if (inst
.operands
[i
].writeback
)
8692 inst
.instruction
|= 0x00000100;
8694 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8696 else if (inst
.operands
[i
].postind
)
8698 gas_assert (inst
.operands
[i
].writeback
);
8699 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8700 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8703 inst
.instruction
|= 0x00200000;
8705 inst
.instruction
|= 0x00000900;
8706 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8708 else /* unindexed - only for coprocessor */
8709 inst
.error
= _("instruction does not accept unindexed addressing");
8712 /* Table of Thumb instructions which exist in both 16- and 32-bit
8713 encodings (the latter only in post-V6T2 cores). The index is the
8714 value used in the insns table below. When there is more than one
8715 possible 16-bit encoding for the instruction, this table always
8717 Also contains several pseudo-instructions used during relaxation. */
8718 #define T16_32_TAB \
8719 X(adc, 4140, eb400000), \
8720 X(adcs, 4140, eb500000), \
8721 X(add, 1c00, eb000000), \
8722 X(adds, 1c00, eb100000), \
8723 X(addi, 0000, f1000000), \
8724 X(addis, 0000, f1100000), \
8725 X(add_pc,000f, f20f0000), \
8726 X(add_sp,000d, f10d0000), \
8727 X(adr, 000f, f20f0000), \
8728 X(and, 4000, ea000000), \
8729 X(ands, 4000, ea100000), \
8730 X(asr, 1000, fa40f000), \
8731 X(asrs, 1000, fa50f000), \
8732 X(b, e000, f000b000), \
8733 X(bcond, d000, f0008000), \
8734 X(bic, 4380, ea200000), \
8735 X(bics, 4380, ea300000), \
8736 X(cmn, 42c0, eb100f00), \
8737 X(cmp, 2800, ebb00f00), \
8738 X(cpsie, b660, f3af8400), \
8739 X(cpsid, b670, f3af8600), \
8740 X(cpy, 4600, ea4f0000), \
8741 X(dec_sp,80dd, f1ad0d00), \
8742 X(eor, 4040, ea800000), \
8743 X(eors, 4040, ea900000), \
8744 X(inc_sp,00dd, f10d0d00), \
8745 X(ldmia, c800, e8900000), \
8746 X(ldr, 6800, f8500000), \
8747 X(ldrb, 7800, f8100000), \
8748 X(ldrh, 8800, f8300000), \
8749 X(ldrsb, 5600, f9100000), \
8750 X(ldrsh, 5e00, f9300000), \
8751 X(ldr_pc,4800, f85f0000), \
8752 X(ldr_pc2,4800, f85f0000), \
8753 X(ldr_sp,9800, f85d0000), \
8754 X(lsl, 0000, fa00f000), \
8755 X(lsls, 0000, fa10f000), \
8756 X(lsr, 0800, fa20f000), \
8757 X(lsrs, 0800, fa30f000), \
8758 X(mov, 2000, ea4f0000), \
8759 X(movs, 2000, ea5f0000), \
8760 X(mul, 4340, fb00f000), \
8761 X(muls, 4340, ffffffff), /* no 32b muls */ \
8762 X(mvn, 43c0, ea6f0000), \
8763 X(mvns, 43c0, ea7f0000), \
8764 X(neg, 4240, f1c00000), /* rsb #0 */ \
8765 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8766 X(orr, 4300, ea400000), \
8767 X(orrs, 4300, ea500000), \
8768 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8769 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8770 X(rev, ba00, fa90f080), \
8771 X(rev16, ba40, fa90f090), \
8772 X(revsh, bac0, fa90f0b0), \
8773 X(ror, 41c0, fa60f000), \
8774 X(rors, 41c0, fa70f000), \
8775 X(sbc, 4180, eb600000), \
8776 X(sbcs, 4180, eb700000), \
8777 X(stmia, c000, e8800000), \
8778 X(str, 6000, f8400000), \
8779 X(strb, 7000, f8000000), \
8780 X(strh, 8000, f8200000), \
8781 X(str_sp,9000, f84d0000), \
8782 X(sub, 1e00, eba00000), \
8783 X(subs, 1e00, ebb00000), \
8784 X(subi, 8000, f1a00000), \
8785 X(subis, 8000, f1b00000), \
8786 X(sxtb, b240, fa4ff080), \
8787 X(sxth, b200, fa0ff080), \
8788 X(tst, 4200, ea100f00), \
8789 X(uxtb, b2c0, fa5ff080), \
8790 X(uxth, b280, fa1ff080), \
8791 X(nop, bf00, f3af8000), \
8792 X(yield, bf10, f3af8001), \
8793 X(wfe, bf20, f3af8002), \
8794 X(wfi, bf30, f3af8003), \
8795 X(sev, bf40, f3af8004),
8797 /* To catch errors in encoding functions, the codes are all offset by
8798 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8799 as 16-bit instructions. */
8800 #define X(a,b,c) T_MNEM_##a
8801 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8804 #define X(a,b,c) 0x##b
8805 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8806 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8809 #define X(a,b,c) 0x##c
8810 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8811 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8812 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8816 /* Thumb instruction encoders, in alphabetical order. */
8821 do_t_add_sub_w (void)
8825 Rd
= inst
.operands
[0].reg
;
8826 Rn
= inst
.operands
[1].reg
;
8828 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this is the
8829 SP-{plus,minute}-immediate form of the instruction. */
8830 reject_bad_reg (Rd
);
8832 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8833 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8836 /* Parse an add or subtract instruction. We get here with inst.instruction
8837 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8844 Rd
= inst
.operands
[0].reg
;
8845 Rs
= (inst
.operands
[1].present
8846 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8847 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8850 set_it_insn_type_last ();
8858 flags
= (inst
.instruction
== T_MNEM_adds
8859 || inst
.instruction
== T_MNEM_subs
);
8861 narrow
= !in_it_block ();
8863 narrow
= in_it_block ();
8864 if (!inst
.operands
[2].isreg
)
8868 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
8870 add
= (inst
.instruction
== T_MNEM_add
8871 || inst
.instruction
== T_MNEM_adds
);
8873 if (inst
.size_req
!= 4)
8875 /* Attempt to use a narrow opcode, with relaxation if
8877 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8878 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8879 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8880 opcode
= T_MNEM_add_sp
;
8881 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8882 opcode
= T_MNEM_add_pc
;
8883 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8886 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8888 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8892 inst
.instruction
= THUMB_OP16(opcode
);
8893 inst
.instruction
|= (Rd
<< 4) | Rs
;
8894 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8895 if (inst
.size_req
!= 2)
8896 inst
.relax
= opcode
;
8899 constraint (inst
.size_req
== 2, BAD_HIREG
);
8901 if (inst
.size_req
== 4
8902 || (inst
.size_req
!= 2 && !opcode
))
8906 constraint (add
, BAD_PC
);
8907 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
8908 _("only SUBS PC, LR, #const allowed"));
8909 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8910 _("expression too complex"));
8911 constraint (inst
.reloc
.exp
.X_add_number
< 0
8912 || inst
.reloc
.exp
.X_add_number
> 0xff,
8913 _("immediate value out of range"));
8914 inst
.instruction
= T2_SUBS_PC_LR
8915 | inst
.reloc
.exp
.X_add_number
;
8916 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8919 else if (Rs
== REG_PC
)
8921 /* Always use addw/subw. */
8922 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8923 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8927 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8928 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8931 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8933 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8935 inst
.instruction
|= Rd
<< 8;
8936 inst
.instruction
|= Rs
<< 16;
8941 Rn
= inst
.operands
[2].reg
;
8942 /* See if we can do this with a 16-bit instruction. */
8943 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8945 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8950 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8951 || inst
.instruction
== T_MNEM_add
)
8954 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8958 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
8960 /* Thumb-1 cores (except v6-M) require at least one high
8961 register in a narrow non flag setting add. */
8962 if (Rd
> 7 || Rn
> 7
8963 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
8964 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
8971 inst
.instruction
= T_OPCODE_ADD_HI
;
8972 inst
.instruction
|= (Rd
& 8) << 4;
8973 inst
.instruction
|= (Rd
& 7);
8974 inst
.instruction
|= Rn
<< 3;
8980 constraint (Rd
== REG_PC
, BAD_PC
);
8981 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
8982 constraint (Rs
== REG_PC
, BAD_PC
);
8983 reject_bad_reg (Rn
);
8985 /* If we get here, it can't be done in 16 bits. */
8986 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8987 _("shift must be constant"));
8988 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8989 inst
.instruction
|= Rd
<< 8;
8990 inst
.instruction
|= Rs
<< 16;
8991 encode_thumb32_shifted_operand (2);
8996 constraint (inst
.instruction
== T_MNEM_adds
8997 || inst
.instruction
== T_MNEM_subs
,
9000 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9002 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9003 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9006 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9008 inst
.instruction
|= (Rd
<< 4) | Rs
;
9009 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9013 Rn
= inst
.operands
[2].reg
;
9014 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9016 /* We now have Rd, Rs, and Rn set to registers. */
9017 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9019 /* Can't do this for SUB. */
9020 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9021 inst
.instruction
= T_OPCODE_ADD_HI
;
9022 inst
.instruction
|= (Rd
& 8) << 4;
9023 inst
.instruction
|= (Rd
& 7);
9025 inst
.instruction
|= Rn
<< 3;
9027 inst
.instruction
|= Rs
<< 3;
9029 constraint (1, _("dest must overlap one source register"));
9033 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9034 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9035 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9045 Rd
= inst
.operands
[0].reg
;
9046 reject_bad_reg (Rd
);
9048 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9050 /* Defer to section relaxation. */
9051 inst
.relax
= inst
.instruction
;
9052 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9053 inst
.instruction
|= Rd
<< 4;
9055 else if (unified_syntax
&& inst
.size_req
!= 2)
9057 /* Generate a 32-bit opcode. */
9058 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9059 inst
.instruction
|= Rd
<< 8;
9060 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9061 inst
.reloc
.pc_rel
= 1;
9065 /* Generate a 16-bit opcode. */
9066 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9067 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9068 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9069 inst
.reloc
.pc_rel
= 1;
9071 inst
.instruction
|= Rd
<< 4;
9075 /* Arithmetic instructions for which there is just one 16-bit
9076 instruction encoding, and it allows only two low registers.
9077 For maximal compatibility with ARM syntax, we allow three register
9078 operands even when Thumb-32 instructions are not available, as long
9079 as the first two are identical. For instance, both "sbc r0,r1" and
9080 "sbc r0,r0,r1" are allowed. */
9086 Rd
= inst
.operands
[0].reg
;
9087 Rs
= (inst
.operands
[1].present
9088 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9089 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9090 Rn
= inst
.operands
[2].reg
;
9092 reject_bad_reg (Rd
);
9093 reject_bad_reg (Rs
);
9094 if (inst
.operands
[2].isreg
)
9095 reject_bad_reg (Rn
);
9099 if (!inst
.operands
[2].isreg
)
9101 /* For an immediate, we always generate a 32-bit opcode;
9102 section relaxation will shrink it later if possible. */
9103 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9104 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9105 inst
.instruction
|= Rd
<< 8;
9106 inst
.instruction
|= Rs
<< 16;
9107 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9113 /* See if we can do this with a 16-bit instruction. */
9114 if (THUMB_SETS_FLAGS (inst
.instruction
))
9115 narrow
= !in_it_block ();
9117 narrow
= in_it_block ();
9119 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9121 if (inst
.operands
[2].shifted
)
9123 if (inst
.size_req
== 4)
9129 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9130 inst
.instruction
|= Rd
;
9131 inst
.instruction
|= Rn
<< 3;
9135 /* If we get here, it can't be done in 16 bits. */
9136 constraint (inst
.operands
[2].shifted
9137 && inst
.operands
[2].immisreg
,
9138 _("shift must be constant"));
9139 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9140 inst
.instruction
|= Rd
<< 8;
9141 inst
.instruction
|= Rs
<< 16;
9142 encode_thumb32_shifted_operand (2);
9147 /* On its face this is a lie - the instruction does set the
9148 flags. However, the only supported mnemonic in this mode
9150 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9152 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9153 _("unshifted register required"));
9154 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9155 constraint (Rd
!= Rs
,
9156 _("dest and source1 must be the same register"));
9158 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9159 inst
.instruction
|= Rd
;
9160 inst
.instruction
|= Rn
<< 3;
9164 /* Similarly, but for instructions where the arithmetic operation is
9165 commutative, so we can allow either of them to be different from
9166 the destination operand in a 16-bit instruction. For instance, all
9167 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9174 Rd
= inst
.operands
[0].reg
;
9175 Rs
= (inst
.operands
[1].present
9176 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9177 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9178 Rn
= inst
.operands
[2].reg
;
9180 reject_bad_reg (Rd
);
9181 reject_bad_reg (Rs
);
9182 if (inst
.operands
[2].isreg
)
9183 reject_bad_reg (Rn
);
9187 if (!inst
.operands
[2].isreg
)
9189 /* For an immediate, we always generate a 32-bit opcode;
9190 section relaxation will shrink it later if possible. */
9191 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9192 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9193 inst
.instruction
|= Rd
<< 8;
9194 inst
.instruction
|= Rs
<< 16;
9195 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9201 /* See if we can do this with a 16-bit instruction. */
9202 if (THUMB_SETS_FLAGS (inst
.instruction
))
9203 narrow
= !in_it_block ();
9205 narrow
= in_it_block ();
9207 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9209 if (inst
.operands
[2].shifted
)
9211 if (inst
.size_req
== 4)
9218 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9219 inst
.instruction
|= Rd
;
9220 inst
.instruction
|= Rn
<< 3;
9225 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9226 inst
.instruction
|= Rd
;
9227 inst
.instruction
|= Rs
<< 3;
9232 /* If we get here, it can't be done in 16 bits. */
9233 constraint (inst
.operands
[2].shifted
9234 && inst
.operands
[2].immisreg
,
9235 _("shift must be constant"));
9236 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9237 inst
.instruction
|= Rd
<< 8;
9238 inst
.instruction
|= Rs
<< 16;
9239 encode_thumb32_shifted_operand (2);
9244 /* On its face this is a lie - the instruction does set the
9245 flags. However, the only supported mnemonic in this mode
9247 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9249 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9250 _("unshifted register required"));
9251 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9253 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9254 inst
.instruction
|= Rd
;
9257 inst
.instruction
|= Rn
<< 3;
9259 inst
.instruction
|= Rs
<< 3;
9261 constraint (1, _("dest must overlap one source register"));
9268 if (inst
.operands
[0].present
)
9270 constraint ((inst
.instruction
& 0xf0) != 0x40
9271 && inst
.operands
[0].imm
!= 0xf,
9272 _("bad barrier type"));
9273 inst
.instruction
|= inst
.operands
[0].imm
;
9276 inst
.instruction
|= 0xf;
9283 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9284 constraint (msb
> 32, _("bit-field extends past end of register"));
9285 /* The instruction encoding stores the LSB and MSB,
9286 not the LSB and width. */
9287 Rd
= inst
.operands
[0].reg
;
9288 reject_bad_reg (Rd
);
9289 inst
.instruction
|= Rd
<< 8;
9290 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9291 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9292 inst
.instruction
|= msb
- 1;
9301 Rd
= inst
.operands
[0].reg
;
9302 reject_bad_reg (Rd
);
9304 /* #0 in second position is alternative syntax for bfc, which is
9305 the same instruction but with REG_PC in the Rm field. */
9306 if (!inst
.operands
[1].isreg
)
9310 Rn
= inst
.operands
[1].reg
;
9311 reject_bad_reg (Rn
);
9314 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9315 constraint (msb
> 32, _("bit-field extends past end of register"));
9316 /* The instruction encoding stores the LSB and MSB,
9317 not the LSB and width. */
9318 inst
.instruction
|= Rd
<< 8;
9319 inst
.instruction
|= Rn
<< 16;
9320 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9321 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9322 inst
.instruction
|= msb
- 1;
9330 Rd
= inst
.operands
[0].reg
;
9331 Rn
= inst
.operands
[1].reg
;
9333 reject_bad_reg (Rd
);
9334 reject_bad_reg (Rn
);
9336 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9337 _("bit-field extends past end of register"));
9338 inst
.instruction
|= Rd
<< 8;
9339 inst
.instruction
|= Rn
<< 16;
9340 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9341 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9342 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9345 /* ARM V5 Thumb BLX (argument parse)
9346 BLX <target_addr> which is BLX(1)
9347 BLX <Rm> which is BLX(2)
9348 Unfortunately, there are two different opcodes for this mnemonic.
9349 So, the insns[].value is not used, and the code here zaps values
9350 into inst.instruction.
9352 ??? How to take advantage of the additional two bits of displacement
9353 available in Thumb32 mode? Need new relocation? */
9358 set_it_insn_type_last ();
9360 if (inst
.operands
[0].isreg
)
9362 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9363 /* We have a register, so this is BLX(2). */
9364 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9368 /* No register. This must be BLX(1). */
9369 inst
.instruction
= 0xf000e800;
9370 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9371 inst
.reloc
.pc_rel
= 1;
9382 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9386 /* Conditional branches inside IT blocks are encoded as unconditional
9393 if (cond
!= COND_ALWAYS
)
9394 opcode
= T_MNEM_bcond
;
9396 opcode
= inst
.instruction
;
9398 if (unified_syntax
&& inst
.size_req
== 4)
9400 inst
.instruction
= THUMB_OP32(opcode
);
9401 if (cond
== COND_ALWAYS
)
9402 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9405 gas_assert (cond
!= 0xF);
9406 inst
.instruction
|= cond
<< 22;
9407 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9412 inst
.instruction
= THUMB_OP16(opcode
);
9413 if (cond
== COND_ALWAYS
)
9414 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9417 inst
.instruction
|= cond
<< 8;
9418 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9420 /* Allow section relaxation. */
9421 if (unified_syntax
&& inst
.size_req
!= 2)
9422 inst
.relax
= opcode
;
9425 inst
.reloc
.pc_rel
= 1;
9431 constraint (inst
.cond
!= COND_ALWAYS
,
9432 _("instruction is always unconditional"));
9433 if (inst
.operands
[0].present
)
9435 constraint (inst
.operands
[0].imm
> 255,
9436 _("immediate value out of range"));
9437 inst
.instruction
|= inst
.operands
[0].imm
;
9438 set_it_insn_type (NEUTRAL_IT_INSN
);
9443 do_t_branch23 (void)
9445 set_it_insn_type_last ();
9446 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9447 inst
.reloc
.pc_rel
= 1;
9449 #if defined(OBJ_COFF)
9450 /* If the destination of the branch is a defined symbol which does not have
9451 the THUMB_FUNC attribute, then we must be calling a function which has
9452 the (interfacearm) attribute. We look for the Thumb entry point to that
9453 function and change the branch to refer to that function instead. */
9454 if ( inst
.reloc
.exp
.X_op
== O_symbol
9455 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9456 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9457 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9458 inst
.reloc
.exp
.X_add_symbol
=
9459 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9466 set_it_insn_type_last ();
9467 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9468 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9469 should cause the alignment to be checked once it is known. This is
9470 because BX PC only works if the instruction is word aligned. */
9478 set_it_insn_type_last ();
9479 Rm
= inst
.operands
[0].reg
;
9480 reject_bad_reg (Rm
);
9481 inst
.instruction
|= Rm
<< 16;
9490 Rd
= inst
.operands
[0].reg
;
9491 Rm
= inst
.operands
[1].reg
;
9493 reject_bad_reg (Rd
);
9494 reject_bad_reg (Rm
);
9496 inst
.instruction
|= Rd
<< 8;
9497 inst
.instruction
|= Rm
<< 16;
9498 inst
.instruction
|= Rm
;
9504 set_it_insn_type (OUTSIDE_IT_INSN
);
9505 inst
.instruction
|= inst
.operands
[0].imm
;
9511 set_it_insn_type (OUTSIDE_IT_INSN
);
9513 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9514 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9516 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9517 inst
.instruction
= 0xf3af8000;
9518 inst
.instruction
|= imod
<< 9;
9519 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9520 if (inst
.operands
[1].present
)
9521 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9525 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9526 && (inst
.operands
[0].imm
& 4),
9527 _("selected processor does not support 'A' form "
9528 "of this instruction"));
9529 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9530 _("Thumb does not support the 2-argument "
9531 "form of this instruction"));
9532 inst
.instruction
|= inst
.operands
[0].imm
;
9536 /* THUMB CPY instruction (argument parse). */
9541 if (inst
.size_req
== 4)
9543 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9544 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9545 inst
.instruction
|= inst
.operands
[1].reg
;
9549 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9550 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9551 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9558 set_it_insn_type (OUTSIDE_IT_INSN
);
9559 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9560 inst
.instruction
|= inst
.operands
[0].reg
;
9561 inst
.reloc
.pc_rel
= 1;
9562 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9568 inst
.instruction
|= inst
.operands
[0].imm
;
9574 unsigned Rd
, Rn
, Rm
;
9576 Rd
= inst
.operands
[0].reg
;
9577 Rn
= (inst
.operands
[1].present
9578 ? inst
.operands
[1].reg
: Rd
);
9579 Rm
= inst
.operands
[2].reg
;
9581 reject_bad_reg (Rd
);
9582 reject_bad_reg (Rn
);
9583 reject_bad_reg (Rm
);
9585 inst
.instruction
|= Rd
<< 8;
9586 inst
.instruction
|= Rn
<< 16;
9587 inst
.instruction
|= Rm
;
9593 if (unified_syntax
&& inst
.size_req
== 4)
9594 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9596 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9602 unsigned int cond
= inst
.operands
[0].imm
;
9604 set_it_insn_type (IT_INSN
);
9605 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
9608 /* If the condition is a negative condition, invert the mask. */
9609 if ((cond
& 0x1) == 0x0)
9611 unsigned int mask
= inst
.instruction
& 0x000f;
9613 if ((mask
& 0x7) == 0)
9614 /* no conversion needed */;
9615 else if ((mask
& 0x3) == 0)
9617 else if ((mask
& 0x1) == 0)
9622 inst
.instruction
&= 0xfff0;
9623 inst
.instruction
|= mask
;
9626 inst
.instruction
|= cond
<< 4;
9629 /* Helper function used for both push/pop and ldm/stm. */
9631 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9635 load
= (inst
.instruction
& (1 << 20)) != 0;
9637 if (mask
& (1 << 13))
9638 inst
.error
= _("SP not allowed in register list");
9641 if (mask
& (1 << 15))
9643 if (mask
& (1 << 14))
9644 inst
.error
= _("LR and PC should not both be in register list");
9646 set_it_insn_type_last ();
9649 if ((mask
& (1 << base
)) != 0
9651 as_warn (_("base register should not be in register list "
9652 "when written back"));
9656 if (mask
& (1 << 15))
9657 inst
.error
= _("PC not allowed in register list");
9659 if (mask
& (1 << base
))
9660 as_warn (_("value stored for r%d is UNPREDICTABLE"), base
);
9663 if ((mask
& (mask
- 1)) == 0)
9665 /* Single register transfers implemented as str/ldr. */
9668 if (inst
.instruction
& (1 << 23))
9669 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9671 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9675 if (inst
.instruction
& (1 << 23))
9676 inst
.instruction
= 0x00800000; /* ia -> [base] */
9678 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9681 inst
.instruction
|= 0xf8400000;
9683 inst
.instruction
|= 0x00100000;
9685 mask
= ffs (mask
) - 1;
9689 inst
.instruction
|= WRITE_BACK
;
9691 inst
.instruction
|= mask
;
9692 inst
.instruction
|= base
<< 16;
9698 /* This really doesn't seem worth it. */
9699 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9700 _("expression too complex"));
9701 constraint (inst
.operands
[1].writeback
,
9702 _("Thumb load/store multiple does not support {reglist}^"));
9710 /* See if we can use a 16-bit instruction. */
9711 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9712 && inst
.size_req
!= 4
9713 && !(inst
.operands
[1].imm
& ~0xff))
9715 mask
= 1 << inst
.operands
[0].reg
;
9717 if (inst
.operands
[0].reg
<= 7
9718 && (inst
.instruction
== T_MNEM_stmia
9719 ? inst
.operands
[0].writeback
9720 : (inst
.operands
[0].writeback
9721 == !(inst
.operands
[1].imm
& mask
))))
9723 if (inst
.instruction
== T_MNEM_stmia
9724 && (inst
.operands
[1].imm
& mask
)
9725 && (inst
.operands
[1].imm
& (mask
- 1)))
9726 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9727 inst
.operands
[0].reg
);
9729 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9730 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9731 inst
.instruction
|= inst
.operands
[1].imm
;
9734 else if (inst
.operands
[0] .reg
== REG_SP
9735 && inst
.operands
[0].writeback
)
9737 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9738 ? T_MNEM_push
: T_MNEM_pop
);
9739 inst
.instruction
|= inst
.operands
[1].imm
;
9746 if (inst
.instruction
< 0xffff)
9747 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9749 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9750 inst
.operands
[0].writeback
);
9755 constraint (inst
.operands
[0].reg
> 7
9756 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9757 constraint (inst
.instruction
!= T_MNEM_ldmia
9758 && inst
.instruction
!= T_MNEM_stmia
,
9759 _("Thumb-2 instruction only valid in unified syntax"));
9760 if (inst
.instruction
== T_MNEM_stmia
)
9762 if (!inst
.operands
[0].writeback
)
9763 as_warn (_("this instruction will write back the base register"));
9764 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9765 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9766 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9767 inst
.operands
[0].reg
);
9771 if (!inst
.operands
[0].writeback
9772 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9773 as_warn (_("this instruction will write back the base register"));
9774 else if (inst
.operands
[0].writeback
9775 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9776 as_warn (_("this instruction will not write back the base register"));
9779 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9780 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9781 inst
.instruction
|= inst
.operands
[1].imm
;
9788 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9789 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9790 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9791 || inst
.operands
[1].negative
,
9794 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9795 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9796 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9802 if (!inst
.operands
[1].present
)
9804 constraint (inst
.operands
[0].reg
== REG_LR
,
9805 _("r14 not allowed as first register "
9806 "when second register is omitted"));
9807 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9809 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9812 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9813 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9814 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9820 unsigned long opcode
;
9823 if (inst
.operands
[0].isreg
9824 && !inst
.operands
[0].preind
9825 && inst
.operands
[0].reg
== REG_PC
)
9826 set_it_insn_type_last ();
9828 opcode
= inst
.instruction
;
9831 if (!inst
.operands
[1].isreg
)
9833 if (opcode
<= 0xffff)
9834 inst
.instruction
= THUMB_OP32 (opcode
);
9835 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9838 if (inst
.operands
[1].isreg
9839 && !inst
.operands
[1].writeback
9840 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9841 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9843 && inst
.size_req
!= 4)
9845 /* Insn may have a 16-bit form. */
9846 Rn
= inst
.operands
[1].reg
;
9847 if (inst
.operands
[1].immisreg
)
9849 inst
.instruction
= THUMB_OP16 (opcode
);
9851 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9854 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9855 && opcode
!= T_MNEM_ldrsb
)
9856 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9857 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9864 if (inst
.reloc
.pc_rel
)
9865 opcode
= T_MNEM_ldr_pc2
;
9867 opcode
= T_MNEM_ldr_pc
;
9871 if (opcode
== T_MNEM_ldr
)
9872 opcode
= T_MNEM_ldr_sp
;
9874 opcode
= T_MNEM_str_sp
;
9876 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9880 inst
.instruction
= inst
.operands
[0].reg
;
9881 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9883 inst
.instruction
|= THUMB_OP16 (opcode
);
9884 if (inst
.size_req
== 2)
9885 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9887 inst
.relax
= opcode
;
9891 /* Definitely a 32-bit variant. */
9892 inst
.instruction
= THUMB_OP32 (opcode
);
9893 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9894 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9898 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9900 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9902 /* Only [Rn,Rm] is acceptable. */
9903 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9904 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9905 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9906 || inst
.operands
[1].negative
,
9907 _("Thumb does not support this addressing mode"));
9908 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9912 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9913 if (!inst
.operands
[1].isreg
)
9914 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9917 constraint (!inst
.operands
[1].preind
9918 || inst
.operands
[1].shifted
9919 || inst
.operands
[1].writeback
,
9920 _("Thumb does not support this addressing mode"));
9921 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9923 constraint (inst
.instruction
& 0x0600,
9924 _("byte or halfword not valid for base register"));
9925 constraint (inst
.operands
[1].reg
== REG_PC
9926 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9927 _("r15 based store not allowed"));
9928 constraint (inst
.operands
[1].immisreg
,
9929 _("invalid base register for register offset"));
9931 if (inst
.operands
[1].reg
== REG_PC
)
9932 inst
.instruction
= T_OPCODE_LDR_PC
;
9933 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9934 inst
.instruction
= T_OPCODE_LDR_SP
;
9936 inst
.instruction
= T_OPCODE_STR_SP
;
9938 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9939 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9943 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9944 if (!inst
.operands
[1].immisreg
)
9946 /* Immediate offset. */
9947 inst
.instruction
|= inst
.operands
[0].reg
;
9948 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9949 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9953 /* Register offset. */
9954 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9955 constraint (inst
.operands
[1].negative
,
9956 _("Thumb does not support this addressing mode"));
9959 switch (inst
.instruction
)
9961 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9962 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9963 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9964 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9965 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9966 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9967 case 0x5600 /* ldrsb */:
9968 case 0x5e00 /* ldrsh */: break;
9972 inst
.instruction
|= inst
.operands
[0].reg
;
9973 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9974 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9980 if (!inst
.operands
[1].present
)
9982 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9983 constraint (inst
.operands
[0].reg
== REG_LR
,
9984 _("r14 not allowed here"));
9986 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9987 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9988 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9994 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9995 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10001 unsigned Rd
, Rn
, Rm
, Ra
;
10003 Rd
= inst
.operands
[0].reg
;
10004 Rn
= inst
.operands
[1].reg
;
10005 Rm
= inst
.operands
[2].reg
;
10006 Ra
= inst
.operands
[3].reg
;
10008 reject_bad_reg (Rd
);
10009 reject_bad_reg (Rn
);
10010 reject_bad_reg (Rm
);
10011 reject_bad_reg (Ra
);
10013 inst
.instruction
|= Rd
<< 8;
10014 inst
.instruction
|= Rn
<< 16;
10015 inst
.instruction
|= Rm
;
10016 inst
.instruction
|= Ra
<< 12;
10022 unsigned RdLo
, RdHi
, Rn
, Rm
;
10024 RdLo
= inst
.operands
[0].reg
;
10025 RdHi
= inst
.operands
[1].reg
;
10026 Rn
= inst
.operands
[2].reg
;
10027 Rm
= inst
.operands
[3].reg
;
10029 reject_bad_reg (RdLo
);
10030 reject_bad_reg (RdHi
);
10031 reject_bad_reg (Rn
);
10032 reject_bad_reg (Rm
);
10034 inst
.instruction
|= RdLo
<< 12;
10035 inst
.instruction
|= RdHi
<< 8;
10036 inst
.instruction
|= Rn
<< 16;
10037 inst
.instruction
|= Rm
;
10041 do_t_mov_cmp (void)
10045 Rn
= inst
.operands
[0].reg
;
10046 Rm
= inst
.operands
[1].reg
;
10049 set_it_insn_type_last ();
10051 if (unified_syntax
)
10053 int r0off
= (inst
.instruction
== T_MNEM_mov
10054 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10055 unsigned long opcode
;
10056 bfd_boolean narrow
;
10057 bfd_boolean low_regs
;
10059 low_regs
= (Rn
<= 7 && Rm
<= 7);
10060 opcode
= inst
.instruction
;
10061 if (in_it_block ())
10062 narrow
= opcode
!= T_MNEM_movs
;
10064 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10065 if (inst
.size_req
== 4
10066 || inst
.operands
[1].shifted
)
10069 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10070 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10071 && !inst
.operands
[1].shifted
10075 inst
.instruction
= T2_SUBS_PC_LR
;
10079 if (opcode
== T_MNEM_cmp
)
10081 constraint (Rn
== REG_PC
, BAD_PC
);
10084 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10086 warn_deprecated_sp (Rm
);
10087 /* R15 was documented as a valid choice for Rm in ARMv6,
10088 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10089 tools reject R15, so we do too. */
10090 constraint (Rm
== REG_PC
, BAD_PC
);
10093 reject_bad_reg (Rm
);
10095 else if (opcode
== T_MNEM_mov
10096 || opcode
== T_MNEM_movs
)
10098 if (inst
.operands
[1].isreg
)
10100 if (opcode
== T_MNEM_movs
)
10102 reject_bad_reg (Rn
);
10103 reject_bad_reg (Rm
);
10105 else if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10106 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10107 reject_bad_reg (Rm
);
10110 reject_bad_reg (Rn
);
10113 if (!inst
.operands
[1].isreg
)
10115 /* Immediate operand. */
10116 if (!in_it_block () && opcode
== T_MNEM_mov
)
10118 if (low_regs
&& narrow
)
10120 inst
.instruction
= THUMB_OP16 (opcode
);
10121 inst
.instruction
|= Rn
<< 8;
10122 if (inst
.size_req
== 2)
10123 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10125 inst
.relax
= opcode
;
10129 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10130 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10131 inst
.instruction
|= Rn
<< r0off
;
10132 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10135 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10136 && (inst
.instruction
== T_MNEM_mov
10137 || inst
.instruction
== T_MNEM_movs
))
10139 /* Register shifts are encoded as separate shift instructions. */
10140 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10142 if (in_it_block ())
10147 if (inst
.size_req
== 4)
10150 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10156 switch (inst
.operands
[1].shift_kind
)
10159 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10162 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10165 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10168 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10174 inst
.instruction
= opcode
;
10177 inst
.instruction
|= Rn
;
10178 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10183 inst
.instruction
|= CONDS_BIT
;
10185 inst
.instruction
|= Rn
<< 8;
10186 inst
.instruction
|= Rm
<< 16;
10187 inst
.instruction
|= inst
.operands
[1].imm
;
10192 /* Some mov with immediate shift have narrow variants.
10193 Register shifts are handled above. */
10194 if (low_regs
&& inst
.operands
[1].shifted
10195 && (inst
.instruction
== T_MNEM_mov
10196 || inst
.instruction
== T_MNEM_movs
))
10198 if (in_it_block ())
10199 narrow
= (inst
.instruction
== T_MNEM_mov
);
10201 narrow
= (inst
.instruction
== T_MNEM_movs
);
10206 switch (inst
.operands
[1].shift_kind
)
10208 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10209 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10210 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10211 default: narrow
= FALSE
; break;
10217 inst
.instruction
|= Rn
;
10218 inst
.instruction
|= Rm
<< 3;
10219 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10223 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10224 inst
.instruction
|= Rn
<< r0off
;
10225 encode_thumb32_shifted_operand (1);
10229 switch (inst
.instruction
)
10232 inst
.instruction
= T_OPCODE_MOV_HR
;
10233 inst
.instruction
|= (Rn
& 0x8) << 4;
10234 inst
.instruction
|= (Rn
& 0x7);
10235 inst
.instruction
|= Rm
<< 3;
10239 /* We know we have low registers at this point.
10240 Generate ADD Rd, Rs, #0. */
10241 inst
.instruction
= T_OPCODE_ADD_I3
;
10242 inst
.instruction
|= Rn
;
10243 inst
.instruction
|= Rm
<< 3;
10249 inst
.instruction
= T_OPCODE_CMP_LR
;
10250 inst
.instruction
|= Rn
;
10251 inst
.instruction
|= Rm
<< 3;
10255 inst
.instruction
= T_OPCODE_CMP_HR
;
10256 inst
.instruction
|= (Rn
& 0x8) << 4;
10257 inst
.instruction
|= (Rn
& 0x7);
10258 inst
.instruction
|= Rm
<< 3;
10265 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10266 if (inst
.operands
[1].isreg
)
10268 if (Rn
< 8 && Rm
< 8)
10270 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10271 since a MOV instruction produces unpredictable results. */
10272 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10273 inst
.instruction
= T_OPCODE_ADD_I3
;
10275 inst
.instruction
= T_OPCODE_CMP_LR
;
10277 inst
.instruction
|= Rn
;
10278 inst
.instruction
|= Rm
<< 3;
10282 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10283 inst
.instruction
= T_OPCODE_MOV_HR
;
10285 inst
.instruction
= T_OPCODE_CMP_HR
;
10291 constraint (Rn
> 7,
10292 _("only lo regs allowed with immediate"));
10293 inst
.instruction
|= Rn
<< 8;
10294 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10305 top
= (inst
.instruction
& 0x00800000) != 0;
10306 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10308 constraint (top
, _(":lower16: not allowed this instruction"));
10309 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10311 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10313 constraint (!top
, _(":upper16: not allowed this instruction"));
10314 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10317 Rd
= inst
.operands
[0].reg
;
10318 reject_bad_reg (Rd
);
10320 inst
.instruction
|= Rd
<< 8;
10321 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10323 imm
= inst
.reloc
.exp
.X_add_number
;
10324 inst
.instruction
|= (imm
& 0xf000) << 4;
10325 inst
.instruction
|= (imm
& 0x0800) << 15;
10326 inst
.instruction
|= (imm
& 0x0700) << 4;
10327 inst
.instruction
|= (imm
& 0x00ff);
10332 do_t_mvn_tst (void)
10336 Rn
= inst
.operands
[0].reg
;
10337 Rm
= inst
.operands
[1].reg
;
10339 if (inst
.instruction
== T_MNEM_cmp
10340 || inst
.instruction
== T_MNEM_cmn
)
10341 constraint (Rn
== REG_PC
, BAD_PC
);
10343 reject_bad_reg (Rn
);
10344 reject_bad_reg (Rm
);
10346 if (unified_syntax
)
10348 int r0off
= (inst
.instruction
== T_MNEM_mvn
10349 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10350 bfd_boolean narrow
;
10352 if (inst
.size_req
== 4
10353 || inst
.instruction
> 0xffff
10354 || inst
.operands
[1].shifted
10355 || Rn
> 7 || Rm
> 7)
10357 else if (inst
.instruction
== T_MNEM_cmn
)
10359 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10360 narrow
= !in_it_block ();
10362 narrow
= in_it_block ();
10364 if (!inst
.operands
[1].isreg
)
10366 /* For an immediate, we always generate a 32-bit opcode;
10367 section relaxation will shrink it later if possible. */
10368 if (inst
.instruction
< 0xffff)
10369 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10370 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10371 inst
.instruction
|= Rn
<< r0off
;
10372 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10376 /* See if we can do this with a 16-bit instruction. */
10379 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10380 inst
.instruction
|= Rn
;
10381 inst
.instruction
|= Rm
<< 3;
10385 constraint (inst
.operands
[1].shifted
10386 && inst
.operands
[1].immisreg
,
10387 _("shift must be constant"));
10388 if (inst
.instruction
< 0xffff)
10389 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10390 inst
.instruction
|= Rn
<< r0off
;
10391 encode_thumb32_shifted_operand (1);
10397 constraint (inst
.instruction
> 0xffff
10398 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10399 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10400 _("unshifted register required"));
10401 constraint (Rn
> 7 || Rm
> 7,
10404 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10405 inst
.instruction
|= Rn
;
10406 inst
.instruction
|= Rm
<< 3;
10416 if (do_vfp_nsyn_mrs () == SUCCESS
)
10419 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10422 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10423 _("selected processor does not support "
10424 "requested special purpose register"));
10428 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10429 _("selected processor does not support "
10430 "requested special purpose register"));
10431 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10432 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10433 _("'CPSR' or 'SPSR' expected"));
10436 Rd
= inst
.operands
[0].reg
;
10437 reject_bad_reg (Rd
);
10439 inst
.instruction
|= Rd
<< 8;
10440 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10441 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10450 if (do_vfp_nsyn_msr () == SUCCESS
)
10453 constraint (!inst
.operands
[1].isreg
,
10454 _("Thumb encoding does not support an immediate here"));
10455 flags
= inst
.operands
[0].imm
;
10458 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10459 _("selected processor does not support "
10460 "requested special purpose register"));
10464 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10465 _("selected processor does not support "
10466 "requested special purpose register"));
10470 Rn
= inst
.operands
[1].reg
;
10471 reject_bad_reg (Rn
);
10473 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10474 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
10475 inst
.instruction
|= (flags
& 0xff);
10476 inst
.instruction
|= Rn
<< 16;
10482 bfd_boolean narrow
;
10483 unsigned Rd
, Rn
, Rm
;
10485 if (!inst
.operands
[2].present
)
10486 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10488 Rd
= inst
.operands
[0].reg
;
10489 Rn
= inst
.operands
[1].reg
;
10490 Rm
= inst
.operands
[2].reg
;
10492 if (unified_syntax
)
10494 if (inst
.size_req
== 4
10500 else if (inst
.instruction
== T_MNEM_muls
)
10501 narrow
= !in_it_block ();
10503 narrow
= in_it_block ();
10507 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10508 constraint (Rn
> 7 || Rm
> 7,
10515 /* 16-bit MULS/Conditional MUL. */
10516 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10517 inst
.instruction
|= Rd
;
10520 inst
.instruction
|= Rm
<< 3;
10522 inst
.instruction
|= Rn
<< 3;
10524 constraint (1, _("dest must overlap one source register"));
10528 constraint (inst
.instruction
!= T_MNEM_mul
,
10529 _("Thumb-2 MUL must not set flags"));
10531 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10532 inst
.instruction
|= Rd
<< 8;
10533 inst
.instruction
|= Rn
<< 16;
10534 inst
.instruction
|= Rm
<< 0;
10536 reject_bad_reg (Rd
);
10537 reject_bad_reg (Rn
);
10538 reject_bad_reg (Rm
);
10545 unsigned RdLo
, RdHi
, Rn
, Rm
;
10547 RdLo
= inst
.operands
[0].reg
;
10548 RdHi
= inst
.operands
[1].reg
;
10549 Rn
= inst
.operands
[2].reg
;
10550 Rm
= inst
.operands
[3].reg
;
10552 reject_bad_reg (RdLo
);
10553 reject_bad_reg (RdHi
);
10554 reject_bad_reg (Rn
);
10555 reject_bad_reg (Rm
);
10557 inst
.instruction
|= RdLo
<< 12;
10558 inst
.instruction
|= RdHi
<< 8;
10559 inst
.instruction
|= Rn
<< 16;
10560 inst
.instruction
|= Rm
;
10563 as_tsktsk (_("rdhi and rdlo must be different"));
10569 set_it_insn_type (NEUTRAL_IT_INSN
);
10571 if (unified_syntax
)
10573 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10575 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10576 inst
.instruction
|= inst
.operands
[0].imm
;
10580 /* PR9722: Check for Thumb2 availability before
10581 generating a thumb2 nop instruction. */
10582 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
10584 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10585 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10588 inst
.instruction
= 0x46c0;
10593 constraint (inst
.operands
[0].present
,
10594 _("Thumb does not support NOP with hints"));
10595 inst
.instruction
= 0x46c0;
10602 if (unified_syntax
)
10604 bfd_boolean narrow
;
10606 if (THUMB_SETS_FLAGS (inst
.instruction
))
10607 narrow
= !in_it_block ();
10609 narrow
= in_it_block ();
10610 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10612 if (inst
.size_req
== 4)
10617 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10618 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10619 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10623 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10624 inst
.instruction
|= inst
.operands
[0].reg
;
10625 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10630 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10632 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10634 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10635 inst
.instruction
|= inst
.operands
[0].reg
;
10636 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10645 Rd
= inst
.operands
[0].reg
;
10646 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10648 reject_bad_reg (Rd
);
10649 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10650 reject_bad_reg (Rn
);
10652 inst
.instruction
|= Rd
<< 8;
10653 inst
.instruction
|= Rn
<< 16;
10655 if (!inst
.operands
[2].isreg
)
10657 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10658 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10664 Rm
= inst
.operands
[2].reg
;
10665 reject_bad_reg (Rm
);
10667 constraint (inst
.operands
[2].shifted
10668 && inst
.operands
[2].immisreg
,
10669 _("shift must be constant"));
10670 encode_thumb32_shifted_operand (2);
10677 unsigned Rd
, Rn
, Rm
;
10679 Rd
= inst
.operands
[0].reg
;
10680 Rn
= inst
.operands
[1].reg
;
10681 Rm
= inst
.operands
[2].reg
;
10683 reject_bad_reg (Rd
);
10684 reject_bad_reg (Rn
);
10685 reject_bad_reg (Rm
);
10687 inst
.instruction
|= Rd
<< 8;
10688 inst
.instruction
|= Rn
<< 16;
10689 inst
.instruction
|= Rm
;
10690 if (inst
.operands
[3].present
)
10692 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10693 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10694 _("expression too complex"));
10695 inst
.instruction
|= (val
& 0x1c) << 10;
10696 inst
.instruction
|= (val
& 0x03) << 6;
10703 if (!inst
.operands
[3].present
)
10707 inst
.instruction
&= ~0x00000020;
10709 /* PR 10168. Swap the Rm and Rn registers. */
10710 Rtmp
= inst
.operands
[1].reg
;
10711 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
10712 inst
.operands
[2].reg
= Rtmp
;
10720 if (inst
.operands
[0].immisreg
)
10721 reject_bad_reg (inst
.operands
[0].imm
);
10723 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10727 do_t_push_pop (void)
10731 constraint (inst
.operands
[0].writeback
,
10732 _("push/pop do not support {reglist}^"));
10733 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10734 _("expression too complex"));
10736 mask
= inst
.operands
[0].imm
;
10737 if ((mask
& ~0xff) == 0)
10738 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10739 else if ((inst
.instruction
== T_MNEM_push
10740 && (mask
& ~0xff) == 1 << REG_LR
)
10741 || (inst
.instruction
== T_MNEM_pop
10742 && (mask
& ~0xff) == 1 << REG_PC
))
10744 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10745 inst
.instruction
|= THUMB_PP_PC_LR
;
10746 inst
.instruction
|= mask
& 0xff;
10748 else if (unified_syntax
)
10750 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10751 encode_thumb2_ldmstm (13, mask
, TRUE
);
10755 inst
.error
= _("invalid register list to push/pop instruction");
10765 Rd
= inst
.operands
[0].reg
;
10766 Rm
= inst
.operands
[1].reg
;
10768 reject_bad_reg (Rd
);
10769 reject_bad_reg (Rm
);
10771 inst
.instruction
|= Rd
<< 8;
10772 inst
.instruction
|= Rm
<< 16;
10773 inst
.instruction
|= Rm
;
10781 Rd
= inst
.operands
[0].reg
;
10782 Rm
= inst
.operands
[1].reg
;
10784 reject_bad_reg (Rd
);
10785 reject_bad_reg (Rm
);
10787 if (Rd
<= 7 && Rm
<= 7
10788 && inst
.size_req
!= 4)
10790 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10791 inst
.instruction
|= Rd
;
10792 inst
.instruction
|= Rm
<< 3;
10794 else if (unified_syntax
)
10796 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10797 inst
.instruction
|= Rd
<< 8;
10798 inst
.instruction
|= Rm
<< 16;
10799 inst
.instruction
|= Rm
;
10802 inst
.error
= BAD_HIREG
;
10810 Rd
= inst
.operands
[0].reg
;
10811 Rm
= inst
.operands
[1].reg
;
10813 reject_bad_reg (Rd
);
10814 reject_bad_reg (Rm
);
10816 inst
.instruction
|= Rd
<< 8;
10817 inst
.instruction
|= Rm
;
10825 Rd
= inst
.operands
[0].reg
;
10826 Rs
= (inst
.operands
[1].present
10827 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10828 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10830 reject_bad_reg (Rd
);
10831 reject_bad_reg (Rs
);
10832 if (inst
.operands
[2].isreg
)
10833 reject_bad_reg (inst
.operands
[2].reg
);
10835 inst
.instruction
|= Rd
<< 8;
10836 inst
.instruction
|= Rs
<< 16;
10837 if (!inst
.operands
[2].isreg
)
10839 bfd_boolean narrow
;
10841 if ((inst
.instruction
& 0x00100000) != 0)
10842 narrow
= !in_it_block ();
10844 narrow
= in_it_block ();
10846 if (Rd
> 7 || Rs
> 7)
10849 if (inst
.size_req
== 4 || !unified_syntax
)
10852 if (inst
.reloc
.exp
.X_op
!= O_constant
10853 || inst
.reloc
.exp
.X_add_number
!= 0)
10856 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10857 relaxation, but it doesn't seem worth the hassle. */
10860 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10861 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
10862 inst
.instruction
|= Rs
<< 3;
10863 inst
.instruction
|= Rd
;
10867 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10868 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10872 encode_thumb32_shifted_operand (2);
10878 set_it_insn_type (OUTSIDE_IT_INSN
);
10879 if (inst
.operands
[0].imm
)
10880 inst
.instruction
|= 0x8;
10886 if (!inst
.operands
[1].present
)
10887 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
10889 if (unified_syntax
)
10891 bfd_boolean narrow
;
10894 switch (inst
.instruction
)
10897 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
10899 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
10901 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
10903 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
10907 if (THUMB_SETS_FLAGS (inst
.instruction
))
10908 narrow
= !in_it_block ();
10910 narrow
= in_it_block ();
10911 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10913 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
10915 if (inst
.operands
[2].isreg
10916 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
10917 || inst
.operands
[2].reg
> 7))
10919 if (inst
.size_req
== 4)
10922 reject_bad_reg (inst
.operands
[0].reg
);
10923 reject_bad_reg (inst
.operands
[1].reg
);
10927 if (inst
.operands
[2].isreg
)
10929 reject_bad_reg (inst
.operands
[2].reg
);
10930 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10931 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10932 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10933 inst
.instruction
|= inst
.operands
[2].reg
;
10937 inst
.operands
[1].shifted
= 1;
10938 inst
.operands
[1].shift_kind
= shift_kind
;
10939 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
10940 ? T_MNEM_movs
: T_MNEM_mov
);
10941 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10942 encode_thumb32_shifted_operand (1);
10943 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10944 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10949 if (inst
.operands
[2].isreg
)
10951 switch (shift_kind
)
10953 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10954 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10955 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10956 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10960 inst
.instruction
|= inst
.operands
[0].reg
;
10961 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10965 switch (shift_kind
)
10967 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10968 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10969 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10972 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10973 inst
.instruction
|= inst
.operands
[0].reg
;
10974 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10980 constraint (inst
.operands
[0].reg
> 7
10981 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
10982 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10984 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
10986 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
10987 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
10988 _("source1 and dest must be same register"));
10990 switch (inst
.instruction
)
10992 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10993 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10994 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10995 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10999 inst
.instruction
|= inst
.operands
[0].reg
;
11000 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11004 switch (inst
.instruction
)
11006 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11007 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11008 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11009 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11012 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11013 inst
.instruction
|= inst
.operands
[0].reg
;
11014 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11022 unsigned Rd
, Rn
, Rm
;
11024 Rd
= inst
.operands
[0].reg
;
11025 Rn
= inst
.operands
[1].reg
;
11026 Rm
= inst
.operands
[2].reg
;
11028 reject_bad_reg (Rd
);
11029 reject_bad_reg (Rn
);
11030 reject_bad_reg (Rm
);
11032 inst
.instruction
|= Rd
<< 8;
11033 inst
.instruction
|= Rn
<< 16;
11034 inst
.instruction
|= Rm
;
11040 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11041 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11042 _("expression too complex"));
11043 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11044 inst
.instruction
|= (value
& 0xf000) >> 12;
11045 inst
.instruction
|= (value
& 0x0ff0);
11046 inst
.instruction
|= (value
& 0x000f) << 16;
11050 do_t_ssat_usat (int bias
)
11054 Rd
= inst
.operands
[0].reg
;
11055 Rn
= inst
.operands
[2].reg
;
11057 reject_bad_reg (Rd
);
11058 reject_bad_reg (Rn
);
11060 inst
.instruction
|= Rd
<< 8;
11061 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11062 inst
.instruction
|= Rn
<< 16;
11064 if (inst
.operands
[3].present
)
11066 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11068 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11070 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11071 _("expression too complex"));
11073 if (shift_amount
!= 0)
11075 constraint (shift_amount
> 31,
11076 _("shift expression is too large"));
11078 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11079 inst
.instruction
|= 0x00200000; /* sh bit. */
11081 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11082 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11090 do_t_ssat_usat (1);
11098 Rd
= inst
.operands
[0].reg
;
11099 Rn
= inst
.operands
[2].reg
;
11101 reject_bad_reg (Rd
);
11102 reject_bad_reg (Rn
);
11104 inst
.instruction
|= Rd
<< 8;
11105 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11106 inst
.instruction
|= Rn
<< 16;
11112 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11113 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11114 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11115 || inst
.operands
[2].negative
,
11118 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11119 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11120 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11121 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11127 if (!inst
.operands
[2].present
)
11128 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11130 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11131 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11132 || inst
.operands
[0].reg
== inst
.operands
[3].reg
11133 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
11136 inst
.instruction
|= inst
.operands
[0].reg
;
11137 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11138 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11139 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11145 unsigned Rd
, Rn
, Rm
;
11147 Rd
= inst
.operands
[0].reg
;
11148 Rn
= inst
.operands
[1].reg
;
11149 Rm
= inst
.operands
[2].reg
;
11151 reject_bad_reg (Rd
);
11152 reject_bad_reg (Rn
);
11153 reject_bad_reg (Rm
);
11155 inst
.instruction
|= Rd
<< 8;
11156 inst
.instruction
|= Rn
<< 16;
11157 inst
.instruction
|= Rm
;
11158 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11166 Rd
= inst
.operands
[0].reg
;
11167 Rm
= inst
.operands
[1].reg
;
11169 reject_bad_reg (Rd
);
11170 reject_bad_reg (Rm
);
11172 if (inst
.instruction
<= 0xffff
11173 && inst
.size_req
!= 4
11174 && Rd
<= 7 && Rm
<= 7
11175 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11177 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11178 inst
.instruction
|= Rd
;
11179 inst
.instruction
|= Rm
<< 3;
11181 else if (unified_syntax
)
11183 if (inst
.instruction
<= 0xffff)
11184 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11185 inst
.instruction
|= Rd
<< 8;
11186 inst
.instruction
|= Rm
;
11187 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11191 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11192 _("Thumb encoding does not support rotation"));
11193 constraint (1, BAD_HIREG
);
11200 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11209 half
= (inst
.instruction
& 0x10) != 0;
11210 set_it_insn_type_last ();
11211 constraint (inst
.operands
[0].immisreg
,
11212 _("instruction requires register index"));
11214 Rn
= inst
.operands
[0].reg
;
11215 Rm
= inst
.operands
[0].imm
;
11217 constraint (Rn
== REG_SP
, BAD_SP
);
11218 reject_bad_reg (Rm
);
11220 constraint (!half
&& inst
.operands
[0].shifted
,
11221 _("instruction does not allow shifted index"));
11222 inst
.instruction
|= (Rn
<< 16) | Rm
;
11228 do_t_ssat_usat (0);
11236 Rd
= inst
.operands
[0].reg
;
11237 Rn
= inst
.operands
[2].reg
;
11239 reject_bad_reg (Rd
);
11240 reject_bad_reg (Rn
);
11242 inst
.instruction
|= Rd
<< 8;
11243 inst
.instruction
|= inst
.operands
[1].imm
;
11244 inst
.instruction
|= Rn
<< 16;
11247 /* Neon instruction encoder helpers. */
11249 /* Encodings for the different types for various Neon opcodes. */
11251 /* An "invalid" code for the following tables. */
11254 struct neon_tab_entry
11257 unsigned float_or_poly
;
11258 unsigned scalar_or_imm
;
11261 /* Map overloaded Neon opcodes to their respective encodings. */
11262 #define NEON_ENC_TAB \
11263 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11264 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11265 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11266 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11267 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11268 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11269 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11270 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11271 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11272 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11273 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11274 /* Register variants of the following two instructions are encoded as
11275 vcge / vcgt with the operands reversed. */ \
11276 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11277 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11278 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11279 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11280 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11281 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11282 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11283 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11284 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11285 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11286 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11287 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11288 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11289 X(vshl, 0x0000400, N_INV, 0x0800510), \
11290 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11291 X(vand, 0x0000110, N_INV, 0x0800030), \
11292 X(vbic, 0x0100110, N_INV, 0x0800030), \
11293 X(veor, 0x1000110, N_INV, N_INV), \
11294 X(vorn, 0x0300110, N_INV, 0x0800010), \
11295 X(vorr, 0x0200110, N_INV, 0x0800010), \
11296 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11297 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11298 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11299 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11300 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11301 X(vst1, 0x0000000, 0x0800000, N_INV), \
11302 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11303 X(vst2, 0x0000100, 0x0800100, N_INV), \
11304 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11305 X(vst3, 0x0000200, 0x0800200, N_INV), \
11306 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11307 X(vst4, 0x0000300, 0x0800300, N_INV), \
11308 X(vmovn, 0x1b20200, N_INV, N_INV), \
11309 X(vtrn, 0x1b20080, N_INV, N_INV), \
11310 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11311 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11312 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11313 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
11314 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
11315 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11316 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11317 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11318 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11322 #define X(OPC,I,F,S) N_MNEM_##OPC
11327 static const struct neon_tab_entry neon_enc_tab
[] =
11329 #define X(OPC,I,F,S) { (I), (F), (S) }
11334 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11335 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11336 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11337 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11338 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11339 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11340 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11341 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11342 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11343 #define NEON_ENC_SINGLE(X) \
11344 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11345 #define NEON_ENC_DOUBLE(X) \
11346 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11348 /* Define shapes for instruction operands. The following mnemonic characters
11349 are used in this table:
11351 F - VFP S<n> register
11352 D - Neon D<n> register
11353 Q - Neon Q<n> register
11357 L - D<n> register list
11359 This table is used to generate various data:
11360 - enumerations of the form NS_DDR to be used as arguments to
11362 - a table classifying shapes into single, double, quad, mixed.
11363 - a table used to drive neon_select_shape. */
11365 #define NEON_SHAPE_DEF \
11366 X(3, (D, D, D), DOUBLE), \
11367 X(3, (Q, Q, Q), QUAD), \
11368 X(3, (D, D, I), DOUBLE), \
11369 X(3, (Q, Q, I), QUAD), \
11370 X(3, (D, D, S), DOUBLE), \
11371 X(3, (Q, Q, S), QUAD), \
11372 X(2, (D, D), DOUBLE), \
11373 X(2, (Q, Q), QUAD), \
11374 X(2, (D, S), DOUBLE), \
11375 X(2, (Q, S), QUAD), \
11376 X(2, (D, R), DOUBLE), \
11377 X(2, (Q, R), QUAD), \
11378 X(2, (D, I), DOUBLE), \
11379 X(2, (Q, I), QUAD), \
11380 X(3, (D, L, D), DOUBLE), \
11381 X(2, (D, Q), MIXED), \
11382 X(2, (Q, D), MIXED), \
11383 X(3, (D, Q, I), MIXED), \
11384 X(3, (Q, D, I), MIXED), \
11385 X(3, (Q, D, D), MIXED), \
11386 X(3, (D, Q, Q), MIXED), \
11387 X(3, (Q, Q, D), MIXED), \
11388 X(3, (Q, D, S), MIXED), \
11389 X(3, (D, Q, S), MIXED), \
11390 X(4, (D, D, D, I), DOUBLE), \
11391 X(4, (Q, Q, Q, I), QUAD), \
11392 X(2, (F, F), SINGLE), \
11393 X(3, (F, F, F), SINGLE), \
11394 X(2, (F, I), SINGLE), \
11395 X(2, (F, D), MIXED), \
11396 X(2, (D, F), MIXED), \
11397 X(3, (F, F, I), MIXED), \
11398 X(4, (R, R, F, F), SINGLE), \
11399 X(4, (F, F, R, R), SINGLE), \
11400 X(3, (D, R, R), DOUBLE), \
11401 X(3, (R, R, D), DOUBLE), \
11402 X(2, (S, R), SINGLE), \
11403 X(2, (R, S), SINGLE), \
11404 X(2, (F, R), SINGLE), \
11405 X(2, (R, F), SINGLE)
11407 #define S2(A,B) NS_##A##B
11408 #define S3(A,B,C) NS_##A##B##C
11409 #define S4(A,B,C,D) NS_##A##B##C##D
11411 #define X(N, L, C) S##N L
11424 enum neon_shape_class
11432 #define X(N, L, C) SC_##C
11434 static enum neon_shape_class neon_shape_class
[] =
11452 /* Register widths of above. */
11453 static unsigned neon_shape_el_size
[] =
11464 struct neon_shape_info
11467 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11470 #define S2(A,B) { SE_##A, SE_##B }
11471 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11472 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11474 #define X(N, L, C) { N, S##N L }
11476 static struct neon_shape_info neon_shape_tab
[] =
11486 /* Bit masks used in type checking given instructions.
11487 'N_EQK' means the type must be the same as (or based on in some way) the key
11488 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11489 set, various other bits can be set as well in order to modify the meaning of
11490 the type constraint. */
11492 enum neon_type_mask
11515 N_KEY
= 0x1000000, /* Key element (main type specifier). */
11516 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
11517 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11518 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
11519 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
11520 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
11521 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
11522 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
11523 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
11524 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
11526 N_MAX_NONSPECIAL
= N_F64
11529 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11531 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11532 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11533 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11534 #define N_SUF_32 (N_SU_32 | N_F32)
11535 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11536 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11538 /* Pass this as the first type argument to neon_check_type to ignore types
11540 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11542 /* Select a "shape" for the current instruction (describing register types or
11543 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11544 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11545 function of operand parsing, so this function doesn't need to be called.
11546 Shapes should be listed in order of decreasing length. */
11548 static enum neon_shape
11549 neon_select_shape (enum neon_shape shape
, ...)
11552 enum neon_shape first_shape
= shape
;
11554 /* Fix missing optional operands. FIXME: we don't know at this point how
11555 many arguments we should have, so this makes the assumption that we have
11556 > 1. This is true of all current Neon opcodes, I think, but may not be
11557 true in the future. */
11558 if (!inst
.operands
[1].present
)
11559 inst
.operands
[1] = inst
.operands
[0];
11561 va_start (ap
, shape
);
11563 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
11568 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
11570 if (!inst
.operands
[j
].present
)
11576 switch (neon_shape_tab
[shape
].el
[j
])
11579 if (!(inst
.operands
[j
].isreg
11580 && inst
.operands
[j
].isvec
11581 && inst
.operands
[j
].issingle
11582 && !inst
.operands
[j
].isquad
))
11587 if (!(inst
.operands
[j
].isreg
11588 && inst
.operands
[j
].isvec
11589 && !inst
.operands
[j
].isquad
11590 && !inst
.operands
[j
].issingle
))
11595 if (!(inst
.operands
[j
].isreg
11596 && !inst
.operands
[j
].isvec
))
11601 if (!(inst
.operands
[j
].isreg
11602 && inst
.operands
[j
].isvec
11603 && inst
.operands
[j
].isquad
11604 && !inst
.operands
[j
].issingle
))
11609 if (!(!inst
.operands
[j
].isreg
11610 && !inst
.operands
[j
].isscalar
))
11615 if (!(!inst
.operands
[j
].isreg
11616 && inst
.operands
[j
].isscalar
))
11630 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
11631 first_error (_("invalid instruction shape"));
11636 /* True if SHAPE is predominantly a quadword operation (most of the time, this
11637 means the Q bit should be set). */
11640 neon_quad (enum neon_shape shape
)
11642 return neon_shape_class
[shape
] == SC_QUAD
;
11646 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
11649 /* Allow modification to be made to types which are constrained to be
11650 based on the key element, based on bits set alongside N_EQK. */
11651 if ((typebits
& N_EQK
) != 0)
11653 if ((typebits
& N_HLF
) != 0)
11655 else if ((typebits
& N_DBL
) != 0)
11657 if ((typebits
& N_SGN
) != 0)
11658 *g_type
= NT_signed
;
11659 else if ((typebits
& N_UNS
) != 0)
11660 *g_type
= NT_unsigned
;
11661 else if ((typebits
& N_INT
) != 0)
11662 *g_type
= NT_integer
;
11663 else if ((typebits
& N_FLT
) != 0)
11664 *g_type
= NT_float
;
11665 else if ((typebits
& N_SIZ
) != 0)
11666 *g_type
= NT_untyped
;
11670 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
11671 operand type, i.e. the single type specified in a Neon instruction when it
11672 is the only one given. */
11674 static struct neon_type_el
11675 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
11677 struct neon_type_el dest
= *key
;
11679 gas_assert ((thisarg
& N_EQK
) != 0);
11681 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
11686 /* Convert Neon type and size into compact bitmask representation. */
11688 static enum neon_type_mask
11689 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
11696 case 8: return N_8
;
11697 case 16: return N_16
;
11698 case 32: return N_32
;
11699 case 64: return N_64
;
11707 case 8: return N_I8
;
11708 case 16: return N_I16
;
11709 case 32: return N_I32
;
11710 case 64: return N_I64
;
11718 case 16: return N_F16
;
11719 case 32: return N_F32
;
11720 case 64: return N_F64
;
11728 case 8: return N_P8
;
11729 case 16: return N_P16
;
11737 case 8: return N_S8
;
11738 case 16: return N_S16
;
11739 case 32: return N_S32
;
11740 case 64: return N_S64
;
11748 case 8: return N_U8
;
11749 case 16: return N_U16
;
11750 case 32: return N_U32
;
11751 case 64: return N_U64
;
11762 /* Convert compact Neon bitmask type representation to a type and size. Only
11763 handles the case where a single bit is set in the mask. */
11766 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
11767 enum neon_type_mask mask
)
11769 if ((mask
& N_EQK
) != 0)
11772 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
11774 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
11776 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
11778 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
11783 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
11785 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
11786 *type
= NT_unsigned
;
11787 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
11788 *type
= NT_integer
;
11789 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
11790 *type
= NT_untyped
;
11791 else if ((mask
& (N_P8
| N_P16
)) != 0)
11793 else if ((mask
& (N_F32
| N_F64
)) != 0)
11801 /* Modify a bitmask of allowed types. This is only needed for type
11805 modify_types_allowed (unsigned allowed
, unsigned mods
)
11808 enum neon_el_type type
;
11814 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
11816 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
11818 neon_modify_type_size (mods
, &type
, &size
);
11819 destmask
|= type_chk_of_el_type (type
, size
);
11826 /* Check type and return type classification.
11827 The manual states (paraphrase): If one datatype is given, it indicates the
11829 - the second operand, if there is one
11830 - the operand, if there is no second operand
11831 - the result, if there are no operands.
11832 This isn't quite good enough though, so we use a concept of a "key" datatype
11833 which is set on a per-instruction basis, which is the one which matters when
11834 only one data type is written.
11835 Note: this function has side-effects (e.g. filling in missing operands). All
11836 Neon instructions should call it before performing bit encoding. */
11838 static struct neon_type_el
11839 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
11842 unsigned i
, pass
, key_el
= 0;
11843 unsigned types
[NEON_MAX_TYPE_ELS
];
11844 enum neon_el_type k_type
= NT_invtype
;
11845 unsigned k_size
= -1u;
11846 struct neon_type_el badtype
= {NT_invtype
, -1};
11847 unsigned key_allowed
= 0;
11849 /* Optional registers in Neon instructions are always (not) in operand 1.
11850 Fill in the missing operand here, if it was omitted. */
11851 if (els
> 1 && !inst
.operands
[1].present
)
11852 inst
.operands
[1] = inst
.operands
[0];
11854 /* Suck up all the varargs. */
11856 for (i
= 0; i
< els
; i
++)
11858 unsigned thisarg
= va_arg (ap
, unsigned);
11859 if (thisarg
== N_IGNORE_TYPE
)
11864 types
[i
] = thisarg
;
11865 if ((thisarg
& N_KEY
) != 0)
11870 if (inst
.vectype
.elems
> 0)
11871 for (i
= 0; i
< els
; i
++)
11872 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
11874 first_error (_("types specified in both the mnemonic and operands"));
11878 /* Duplicate inst.vectype elements here as necessary.
11879 FIXME: No idea if this is exactly the same as the ARM assembler,
11880 particularly when an insn takes one register and one non-register
11882 if (inst
.vectype
.elems
== 1 && els
> 1)
11885 inst
.vectype
.elems
= els
;
11886 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
11887 for (j
= 0; j
< els
; j
++)
11889 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11892 else if (inst
.vectype
.elems
== 0 && els
> 0)
11895 /* No types were given after the mnemonic, so look for types specified
11896 after each operand. We allow some flexibility here; as long as the
11897 "key" operand has a type, we can infer the others. */
11898 for (j
= 0; j
< els
; j
++)
11899 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
11900 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
11902 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
11904 for (j
= 0; j
< els
; j
++)
11905 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
11906 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11911 first_error (_("operand types can't be inferred"));
11915 else if (inst
.vectype
.elems
!= els
)
11917 first_error (_("type specifier has the wrong number of parts"));
11921 for (pass
= 0; pass
< 2; pass
++)
11923 for (i
= 0; i
< els
; i
++)
11925 unsigned thisarg
= types
[i
];
11926 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
11927 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
11928 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
11929 unsigned g_size
= inst
.vectype
.el
[i
].size
;
11931 /* Decay more-specific signed & unsigned types to sign-insensitive
11932 integer types if sign-specific variants are unavailable. */
11933 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
11934 && (types_allowed
& N_SU_ALL
) == 0)
11935 g_type
= NT_integer
;
11937 /* If only untyped args are allowed, decay any more specific types to
11938 them. Some instructions only care about signs for some element
11939 sizes, so handle that properly. */
11940 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
11941 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
11942 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
11943 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
11944 g_type
= NT_untyped
;
11948 if ((thisarg
& N_KEY
) != 0)
11952 key_allowed
= thisarg
& ~N_KEY
;
11957 if ((thisarg
& N_VFP
) != 0)
11959 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
11960 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
11962 /* In VFP mode, operands must match register widths. If we
11963 have a key operand, use its width, else use the width of
11964 the current operand. */
11970 if (regwidth
!= match
)
11972 first_error (_("operand size must match register width"));
11977 if ((thisarg
& N_EQK
) == 0)
11979 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
11981 if ((given_type
& types_allowed
) == 0)
11983 first_error (_("bad type in Neon instruction"));
11989 enum neon_el_type mod_k_type
= k_type
;
11990 unsigned mod_k_size
= k_size
;
11991 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
11992 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
11994 first_error (_("inconsistent types in Neon instruction"));
12002 return inst
.vectype
.el
[key_el
];
12005 /* Neon-style VFP instruction forwarding. */
12007 /* Thumb VFP instructions have 0xE in the condition field. */
12010 do_vfp_cond_or_thumb (void)
12013 inst
.instruction
|= 0xe0000000;
12015 inst
.instruction
|= inst
.cond
<< 28;
12018 /* Look up and encode a simple mnemonic, for use as a helper function for the
12019 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12020 etc. It is assumed that operand parsing has already been done, and that the
12021 operands are in the form expected by the given opcode (this isn't necessarily
12022 the same as the form in which they were parsed, hence some massaging must
12023 take place before this function is called).
12024 Checks current arch version against that in the looked-up opcode. */
12027 do_vfp_nsyn_opcode (const char *opname
)
12029 const struct asm_opcode
*opcode
;
12031 opcode
= hash_find (arm_ops_hsh
, opname
);
12036 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12037 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12042 inst
.instruction
= opcode
->tvalue
;
12043 opcode
->tencode ();
12047 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12048 opcode
->aencode ();
12053 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12055 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12060 do_vfp_nsyn_opcode ("fadds");
12062 do_vfp_nsyn_opcode ("fsubs");
12067 do_vfp_nsyn_opcode ("faddd");
12069 do_vfp_nsyn_opcode ("fsubd");
12073 /* Check operand types to see if this is a VFP instruction, and if so call
12077 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12079 enum neon_shape rs
;
12080 struct neon_type_el et
;
12085 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12086 et
= neon_check_type (2, rs
,
12087 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12091 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12092 et
= neon_check_type (3, rs
,
12093 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12100 if (et
.type
!= NT_invtype
)
12112 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12114 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12119 do_vfp_nsyn_opcode ("fmacs");
12121 do_vfp_nsyn_opcode ("fmscs");
12126 do_vfp_nsyn_opcode ("fmacd");
12128 do_vfp_nsyn_opcode ("fmscd");
12133 do_vfp_nsyn_mul (enum neon_shape rs
)
12136 do_vfp_nsyn_opcode ("fmuls");
12138 do_vfp_nsyn_opcode ("fmuld");
12142 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12144 int is_neg
= (inst
.instruction
& 0x80) != 0;
12145 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12150 do_vfp_nsyn_opcode ("fnegs");
12152 do_vfp_nsyn_opcode ("fabss");
12157 do_vfp_nsyn_opcode ("fnegd");
12159 do_vfp_nsyn_opcode ("fabsd");
12163 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12164 insns belong to Neon, and are handled elsewhere. */
12167 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12169 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12173 do_vfp_nsyn_opcode ("fldmdbs");
12175 do_vfp_nsyn_opcode ("fldmias");
12180 do_vfp_nsyn_opcode ("fstmdbs");
12182 do_vfp_nsyn_opcode ("fstmias");
12187 do_vfp_nsyn_sqrt (void)
12189 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12190 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12193 do_vfp_nsyn_opcode ("fsqrts");
12195 do_vfp_nsyn_opcode ("fsqrtd");
12199 do_vfp_nsyn_div (void)
12201 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12202 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12203 N_F32
| N_F64
| N_KEY
| N_VFP
);
12206 do_vfp_nsyn_opcode ("fdivs");
12208 do_vfp_nsyn_opcode ("fdivd");
12212 do_vfp_nsyn_nmul (void)
12214 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12215 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12216 N_F32
| N_F64
| N_KEY
| N_VFP
);
12220 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
12221 do_vfp_sp_dyadic ();
12225 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
12226 do_vfp_dp_rd_rn_rm ();
12228 do_vfp_cond_or_thumb ();
12232 do_vfp_nsyn_cmp (void)
12234 if (inst
.operands
[1].isreg
)
12236 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12237 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12241 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
12242 do_vfp_sp_monadic ();
12246 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
12247 do_vfp_dp_rd_rm ();
12252 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12253 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12255 switch (inst
.instruction
& 0x0fffffff)
12258 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12261 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12269 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
12270 do_vfp_sp_compare_z ();
12274 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
12278 do_vfp_cond_or_thumb ();
12282 nsyn_insert_sp (void)
12284 inst
.operands
[1] = inst
.operands
[0];
12285 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12286 inst
.operands
[0].reg
= REG_SP
;
12287 inst
.operands
[0].isreg
= 1;
12288 inst
.operands
[0].writeback
= 1;
12289 inst
.operands
[0].present
= 1;
12293 do_vfp_nsyn_push (void)
12296 if (inst
.operands
[1].issingle
)
12297 do_vfp_nsyn_opcode ("fstmdbs");
12299 do_vfp_nsyn_opcode ("fstmdbd");
12303 do_vfp_nsyn_pop (void)
12306 if (inst
.operands
[1].issingle
)
12307 do_vfp_nsyn_opcode ("fldmias");
12309 do_vfp_nsyn_opcode ("fldmiad");
12312 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12313 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12316 neon_dp_fixup (unsigned i
)
12320 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12334 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12338 neon_logbits (unsigned x
)
12340 return ffs (x
) - 4;
12343 #define LOW4(R) ((R) & 0xf)
12344 #define HI1(R) (((R) >> 4) & 1)
12346 /* Encode insns with bit pattern:
12348 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12349 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
12351 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12352 different meaning for some instruction. */
12355 neon_three_same (int isquad
, int ubit
, int size
)
12357 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12358 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12359 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12360 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12361 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12362 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12363 inst
.instruction
|= (isquad
!= 0) << 6;
12364 inst
.instruction
|= (ubit
!= 0) << 24;
12366 inst
.instruction
|= neon_logbits (size
) << 20;
12368 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12371 /* Encode instructions of the form:
12373 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
12374 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
12376 Don't write size if SIZE == -1. */
12379 neon_two_same (int qbit
, int ubit
, int size
)
12381 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12382 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12383 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12384 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12385 inst
.instruction
|= (qbit
!= 0) << 6;
12386 inst
.instruction
|= (ubit
!= 0) << 24;
12389 inst
.instruction
|= neon_logbits (size
) << 18;
12391 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12394 /* Neon instruction encoders, in approximate order of appearance. */
12397 do_neon_dyadic_i_su (void)
12399 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12400 struct neon_type_el et
= neon_check_type (3, rs
,
12401 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12402 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12406 do_neon_dyadic_i64_su (void)
12408 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12409 struct neon_type_el et
= neon_check_type (3, rs
,
12410 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12411 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12415 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12418 unsigned size
= et
.size
>> 3;
12419 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12420 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12421 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12422 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12423 inst
.instruction
|= (isquad
!= 0) << 6;
12424 inst
.instruction
|= immbits
<< 16;
12425 inst
.instruction
|= (size
>> 3) << 7;
12426 inst
.instruction
|= (size
& 0x7) << 19;
12428 inst
.instruction
|= (uval
!= 0) << 24;
12430 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12434 do_neon_shl_imm (void)
12436 if (!inst
.operands
[2].isreg
)
12438 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12439 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12440 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12441 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12445 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12446 struct neon_type_el et
= neon_check_type (3, rs
,
12447 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12450 /* VSHL/VQSHL 3-register variants have syntax such as:
12452 whereas other 3-register operations encoded by neon_three_same have
12455 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12457 tmp
= inst
.operands
[2].reg
;
12458 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12459 inst
.operands
[1].reg
= tmp
;
12460 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12461 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12466 do_neon_qshl_imm (void)
12468 if (!inst
.operands
[2].isreg
)
12470 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12471 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12473 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12474 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12475 inst
.operands
[2].imm
);
12479 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12480 struct neon_type_el et
= neon_check_type (3, rs
,
12481 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12484 /* See note in do_neon_shl_imm. */
12485 tmp
= inst
.operands
[2].reg
;
12486 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12487 inst
.operands
[1].reg
= tmp
;
12488 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12489 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12494 do_neon_rshl (void)
12496 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12497 struct neon_type_el et
= neon_check_type (3, rs
,
12498 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12501 tmp
= inst
.operands
[2].reg
;
12502 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12503 inst
.operands
[1].reg
= tmp
;
12504 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12508 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12510 /* Handle .I8 pseudo-instructions. */
12513 /* Unfortunately, this will make everything apart from zero out-of-range.
12514 FIXME is this the intended semantics? There doesn't seem much point in
12515 accepting .I8 if so. */
12516 immediate
|= immediate
<< 8;
12522 if (immediate
== (immediate
& 0x000000ff))
12524 *immbits
= immediate
;
12527 else if (immediate
== (immediate
& 0x0000ff00))
12529 *immbits
= immediate
>> 8;
12532 else if (immediate
== (immediate
& 0x00ff0000))
12534 *immbits
= immediate
>> 16;
12537 else if (immediate
== (immediate
& 0xff000000))
12539 *immbits
= immediate
>> 24;
12542 if ((immediate
& 0xffff) != (immediate
>> 16))
12543 goto bad_immediate
;
12544 immediate
&= 0xffff;
12547 if (immediate
== (immediate
& 0x000000ff))
12549 *immbits
= immediate
;
12552 else if (immediate
== (immediate
& 0x0000ff00))
12554 *immbits
= immediate
>> 8;
12559 first_error (_("immediate value out of range"));
12563 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12567 neon_bits_same_in_bytes (unsigned imm
)
12569 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
12570 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
12571 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
12572 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
12575 /* For immediate of above form, return 0bABCD. */
12578 neon_squash_bits (unsigned imm
)
12580 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
12581 | ((imm
& 0x01000000) >> 21);
12584 /* Compress quarter-float representation to 0b...000 abcdefgh. */
12587 neon_qfloat_bits (unsigned imm
)
12589 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
12592 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12593 the instruction. *OP is passed as the initial value of the op field, and
12594 may be set to a different value depending on the constant (i.e.
12595 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
12596 MVN). If the immediate looks like a repeated pattern then also
12597 try smaller element sizes. */
12600 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
12601 unsigned *immbits
, int *op
, int size
,
12602 enum neon_el_type type
)
12604 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
12606 if (type
== NT_float
&& !float_p
)
12609 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
12611 if (size
!= 32 || *op
== 1)
12613 *immbits
= neon_qfloat_bits (immlo
);
12619 if (neon_bits_same_in_bytes (immhi
)
12620 && neon_bits_same_in_bytes (immlo
))
12624 *immbits
= (neon_squash_bits (immhi
) << 4)
12625 | neon_squash_bits (immlo
);
12630 if (immhi
!= immlo
)
12636 if (immlo
== (immlo
& 0x000000ff))
12641 else if (immlo
== (immlo
& 0x0000ff00))
12643 *immbits
= immlo
>> 8;
12646 else if (immlo
== (immlo
& 0x00ff0000))
12648 *immbits
= immlo
>> 16;
12651 else if (immlo
== (immlo
& 0xff000000))
12653 *immbits
= immlo
>> 24;
12656 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
12658 *immbits
= (immlo
>> 8) & 0xff;
12661 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
12663 *immbits
= (immlo
>> 16) & 0xff;
12667 if ((immlo
& 0xffff) != (immlo
>> 16))
12674 if (immlo
== (immlo
& 0x000000ff))
12679 else if (immlo
== (immlo
& 0x0000ff00))
12681 *immbits
= immlo
>> 8;
12685 if ((immlo
& 0xff) != (immlo
>> 8))
12690 if (immlo
== (immlo
& 0x000000ff))
12692 /* Don't allow MVN with 8-bit immediate. */
12702 /* Write immediate bits [7:0] to the following locations:
12704 |28/24|23 19|18 16|15 4|3 0|
12705 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
12707 This function is used by VMOV/VMVN/VORR/VBIC. */
12710 neon_write_immbits (unsigned immbits
)
12712 inst
.instruction
|= immbits
& 0xf;
12713 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
12714 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
12717 /* Invert low-order SIZE bits of XHI:XLO. */
12720 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
12722 unsigned immlo
= xlo
? *xlo
: 0;
12723 unsigned immhi
= xhi
? *xhi
: 0;
12728 immlo
= (~immlo
) & 0xff;
12732 immlo
= (~immlo
) & 0xffff;
12736 immhi
= (~immhi
) & 0xffffffff;
12737 /* fall through. */
12740 immlo
= (~immlo
) & 0xffffffff;
12755 do_neon_logic (void)
12757 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
12759 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12760 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12761 /* U bit and size field were set as part of the bitmask. */
12762 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12763 neon_three_same (neon_quad (rs
), 0, -1);
12767 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12768 struct neon_type_el et
= neon_check_type (2, rs
,
12769 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12770 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
12774 if (et
.type
== NT_invtype
)
12777 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12779 immbits
= inst
.operands
[1].imm
;
12782 /* .i64 is a pseudo-op, so the immediate must be a repeating
12784 if (immbits
!= (inst
.operands
[1].regisimm
?
12785 inst
.operands
[1].reg
: 0))
12787 /* Set immbits to an invalid constant. */
12788 immbits
= 0xdeadbeef;
12795 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12799 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12803 /* Pseudo-instruction for VBIC. */
12804 neon_invert_size (&immbits
, 0, et
.size
);
12805 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12809 /* Pseudo-instruction for VORR. */
12810 neon_invert_size (&immbits
, 0, et
.size
);
12811 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12821 inst
.instruction
|= neon_quad (rs
) << 6;
12822 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12823 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12824 inst
.instruction
|= cmode
<< 8;
12825 neon_write_immbits (immbits
);
12827 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12832 do_neon_bitfield (void)
12834 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12835 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12836 neon_three_same (neon_quad (rs
), 0, -1);
12840 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
12843 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12844 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
12846 if (et
.type
== NT_float
)
12848 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
12849 neon_three_same (neon_quad (rs
), 0, -1);
12853 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12854 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
12859 do_neon_dyadic_if_su (void)
12861 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12865 do_neon_dyadic_if_su_d (void)
12867 /* This version only allow D registers, but that constraint is enforced during
12868 operand parsing so we don't need to do anything extra here. */
12869 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12873 do_neon_dyadic_if_i_d (void)
12875 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12876 affected if we specify unsigned args. */
12877 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12880 enum vfp_or_neon_is_neon_bits
12883 NEON_CHECK_ARCH
= 2
12886 /* Call this function if an instruction which may have belonged to the VFP or
12887 Neon instruction sets, but turned out to be a Neon instruction (due to the
12888 operand types involved, etc.). We have to check and/or fix-up a couple of
12891 - Make sure the user hasn't attempted to make a Neon instruction
12893 - Alter the value in the condition code field if necessary.
12894 - Make sure that the arch supports Neon instructions.
12896 Which of these operations take place depends on bits from enum
12897 vfp_or_neon_is_neon_bits.
12899 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12900 current instruction's condition is COND_ALWAYS, the condition field is
12901 changed to inst.uncond_value. This is necessary because instructions shared
12902 between VFP and Neon may be conditional for the VFP variants only, and the
12903 unconditional Neon version must have, e.g., 0xF in the condition field. */
12906 vfp_or_neon_is_neon (unsigned check
)
12908 /* Conditions are always legal in Thumb mode (IT blocks). */
12909 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
12911 if (inst
.cond
!= COND_ALWAYS
)
12913 first_error (_(BAD_COND
));
12916 if (inst
.uncond_value
!= -1)
12917 inst
.instruction
|= inst
.uncond_value
<< 28;
12920 if ((check
& NEON_CHECK_ARCH
)
12921 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
12923 first_error (_(BAD_FPU
));
12931 do_neon_addsub_if_i (void)
12933 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
12936 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12939 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12940 affected if we specify unsigned args. */
12941 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
12944 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
12946 V<op> A,B (A is operand 0, B is operand 2)
12951 so handle that case specially. */
12954 neon_exchange_operands (void)
12956 void *scratch
= alloca (sizeof (inst
.operands
[0]));
12957 if (inst
.operands
[1].present
)
12959 /* Swap operands[1] and operands[2]. */
12960 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
12961 inst
.operands
[1] = inst
.operands
[2];
12962 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
12966 inst
.operands
[1] = inst
.operands
[2];
12967 inst
.operands
[2] = inst
.operands
[0];
12972 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
12974 if (inst
.operands
[2].isreg
)
12977 neon_exchange_operands ();
12978 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
12982 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12983 struct neon_type_el et
= neon_check_type (2, rs
,
12984 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
12986 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12987 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12988 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12989 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12990 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12991 inst
.instruction
|= neon_quad (rs
) << 6;
12992 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12993 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12995 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13002 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13006 do_neon_cmp_inv (void)
13008 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13014 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13017 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13018 scalars, which are encoded in 5 bits, M : Rm.
13019 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13020 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13024 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13026 unsigned regno
= NEON_SCALAR_REG (scalar
);
13027 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13032 if (regno
> 7 || elno
> 3)
13034 return regno
| (elno
<< 3);
13037 if (regno
> 15 || elno
> 1)
13039 return regno
| (elno
<< 4);
13043 first_error (_("scalar out of range for multiply instruction"));
13049 /* Encode multiply / multiply-accumulate scalar instructions. */
13052 neon_mul_mac (struct neon_type_el et
, int ubit
)
13056 /* Give a more helpful error message if we have an invalid type. */
13057 if (et
.type
== NT_invtype
)
13060 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13061 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13062 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13063 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13064 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13065 inst
.instruction
|= LOW4 (scalar
);
13066 inst
.instruction
|= HI1 (scalar
) << 5;
13067 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13068 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13069 inst
.instruction
|= (ubit
!= 0) << 24;
13071 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13075 do_neon_mac_maybe_scalar (void)
13077 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13080 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13083 if (inst
.operands
[2].isscalar
)
13085 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13086 struct neon_type_el et
= neon_check_type (3, rs
,
13087 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13088 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13089 neon_mul_mac (et
, neon_quad (rs
));
13093 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13094 affected if we specify unsigned args. */
13095 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13102 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13103 struct neon_type_el et
= neon_check_type (3, rs
,
13104 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13105 neon_three_same (neon_quad (rs
), 0, et
.size
);
13108 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13109 same types as the MAC equivalents. The polynomial type for this instruction
13110 is encoded the same as the integer type. */
13115 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13118 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13121 if (inst
.operands
[2].isscalar
)
13122 do_neon_mac_maybe_scalar ();
13124 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13128 do_neon_qdmulh (void)
13130 if (inst
.operands
[2].isscalar
)
13132 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13133 struct neon_type_el et
= neon_check_type (3, rs
,
13134 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13135 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13136 neon_mul_mac (et
, neon_quad (rs
));
13140 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13141 struct neon_type_el et
= neon_check_type (3, rs
,
13142 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13143 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13144 /* The U bit (rounding) comes from bit mask. */
13145 neon_three_same (neon_quad (rs
), 0, et
.size
);
13150 do_neon_fcmp_absolute (void)
13152 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13153 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13154 /* Size field comes from bit mask. */
13155 neon_three_same (neon_quad (rs
), 1, -1);
13159 do_neon_fcmp_absolute_inv (void)
13161 neon_exchange_operands ();
13162 do_neon_fcmp_absolute ();
13166 do_neon_step (void)
13168 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13169 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13170 neon_three_same (neon_quad (rs
), 0, -1);
13174 do_neon_abs_neg (void)
13176 enum neon_shape rs
;
13177 struct neon_type_el et
;
13179 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13182 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13185 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13186 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13188 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13189 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13190 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13191 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13192 inst
.instruction
|= neon_quad (rs
) << 6;
13193 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13194 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13196 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13202 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13203 struct neon_type_el et
= neon_check_type (2, rs
,
13204 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13205 int imm
= inst
.operands
[2].imm
;
13206 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13207 _("immediate out of range for insert"));
13208 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13214 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13215 struct neon_type_el et
= neon_check_type (2, rs
,
13216 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13217 int imm
= inst
.operands
[2].imm
;
13218 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13219 _("immediate out of range for insert"));
13220 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13224 do_neon_qshlu_imm (void)
13226 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13227 struct neon_type_el et
= neon_check_type (2, rs
,
13228 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13229 int imm
= inst
.operands
[2].imm
;
13230 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13231 _("immediate out of range for shift"));
13232 /* Only encodes the 'U present' variant of the instruction.
13233 In this case, signed types have OP (bit 8) set to 0.
13234 Unsigned types have OP set to 1. */
13235 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13236 /* The rest of the bits are the same as other immediate shifts. */
13237 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13241 do_neon_qmovn (void)
13243 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13244 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13245 /* Saturating move where operands can be signed or unsigned, and the
13246 destination has the same signedness. */
13247 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13248 if (et
.type
== NT_unsigned
)
13249 inst
.instruction
|= 0xc0;
13251 inst
.instruction
|= 0x80;
13252 neon_two_same (0, 1, et
.size
/ 2);
13256 do_neon_qmovun (void)
13258 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13259 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13260 /* Saturating move with unsigned results. Operands must be signed. */
13261 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13262 neon_two_same (0, 1, et
.size
/ 2);
13266 do_neon_rshift_sat_narrow (void)
13268 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13269 or unsigned. If operands are unsigned, results must also be unsigned. */
13270 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13271 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13272 int imm
= inst
.operands
[2].imm
;
13273 /* This gets the bounds check, size encoding and immediate bits calculation
13277 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13278 VQMOVN.I<size> <Dd>, <Qm>. */
13281 inst
.operands
[2].present
= 0;
13282 inst
.instruction
= N_MNEM_vqmovn
;
13287 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13288 _("immediate out of range"));
13289 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13293 do_neon_rshift_sat_narrow_u (void)
13295 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13296 or unsigned. If operands are unsigned, results must also be unsigned. */
13297 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13298 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13299 int imm
= inst
.operands
[2].imm
;
13300 /* This gets the bounds check, size encoding and immediate bits calculation
13304 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13305 VQMOVUN.I<size> <Dd>, <Qm>. */
13308 inst
.operands
[2].present
= 0;
13309 inst
.instruction
= N_MNEM_vqmovun
;
13314 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13315 _("immediate out of range"));
13316 /* FIXME: The manual is kind of unclear about what value U should have in
13317 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13319 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
13323 do_neon_movn (void)
13325 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13326 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13327 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13328 neon_two_same (0, 1, et
.size
/ 2);
13332 do_neon_rshift_narrow (void)
13334 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13335 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13336 int imm
= inst
.operands
[2].imm
;
13337 /* This gets the bounds check, size encoding and immediate bits calculation
13341 /* If immediate is zero then we are a pseudo-instruction for
13342 VMOVN.I<size> <Dd>, <Qm> */
13345 inst
.operands
[2].present
= 0;
13346 inst
.instruction
= N_MNEM_vmovn
;
13351 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13352 _("immediate out of range for narrowing operation"));
13353 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
13357 do_neon_shll (void)
13359 /* FIXME: Type checking when lengthening. */
13360 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
13361 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
13362 unsigned imm
= inst
.operands
[2].imm
;
13364 if (imm
== et
.size
)
13366 /* Maximum shift variant. */
13367 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13368 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13369 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13370 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13371 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13372 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13374 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13378 /* A more-specific type check for non-max versions. */
13379 et
= neon_check_type (2, NS_QDI
,
13380 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13381 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13382 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13386 /* Check the various types for the VCVT instruction, and return which version
13387 the current instruction is. */
13390 neon_cvt_flavour (enum neon_shape rs
)
13392 #define CVT_VAR(C,X,Y) \
13393 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13394 if (et.type != NT_invtype) \
13396 inst.error = NULL; \
13399 struct neon_type_el et
;
13400 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13401 || rs
== NS_FF
) ? N_VFP
: 0;
13402 /* The instruction versions which take an immediate take one register
13403 argument, which is extended to the width of the full register. Thus the
13404 "source" and "destination" registers must have the same width. Hack that
13405 here by making the size equal to the key (wider, in this case) operand. */
13406 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13408 CVT_VAR (0, N_S32
, N_F32
);
13409 CVT_VAR (1, N_U32
, N_F32
);
13410 CVT_VAR (2, N_F32
, N_S32
);
13411 CVT_VAR (3, N_F32
, N_U32
);
13412 /* Half-precision conversions. */
13413 CVT_VAR (4, N_F32
, N_F16
);
13414 CVT_VAR (5, N_F16
, N_F32
);
13418 /* VFP instructions. */
13419 CVT_VAR (6, N_F32
, N_F64
);
13420 CVT_VAR (7, N_F64
, N_F32
);
13421 CVT_VAR (8, N_S32
, N_F64
| key
);
13422 CVT_VAR (9, N_U32
, N_F64
| key
);
13423 CVT_VAR (10, N_F64
| key
, N_S32
);
13424 CVT_VAR (11, N_F64
| key
, N_U32
);
13425 /* VFP instructions with bitshift. */
13426 CVT_VAR (12, N_F32
| key
, N_S16
);
13427 CVT_VAR (13, N_F32
| key
, N_U16
);
13428 CVT_VAR (14, N_F64
| key
, N_S16
);
13429 CVT_VAR (15, N_F64
| key
, N_U16
);
13430 CVT_VAR (16, N_S16
, N_F32
| key
);
13431 CVT_VAR (17, N_U16
, N_F32
| key
);
13432 CVT_VAR (18, N_S16
, N_F64
| key
);
13433 CVT_VAR (19, N_U16
, N_F64
| key
);
13439 /* Neon-syntax VFP conversions. */
13442 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13444 const char *opname
= 0;
13446 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13448 /* Conversions with immediate bitshift. */
13449 const char *enc
[] =
13473 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13475 opname
= enc
[flavour
];
13476 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13477 _("operands 0 and 1 must be the same register"));
13478 inst
.operands
[1] = inst
.operands
[2];
13479 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13484 /* Conversions without bitshift. */
13485 const char *enc
[] =
13501 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13502 opname
= enc
[flavour
];
13506 do_vfp_nsyn_opcode (opname
);
13510 do_vfp_nsyn_cvtz (void)
13512 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
13513 int flavour
= neon_cvt_flavour (rs
);
13514 const char *enc
[] =
13528 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
13529 do_vfp_nsyn_opcode (enc
[flavour
]);
13535 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
13536 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
13537 int flavour
= neon_cvt_flavour (rs
);
13539 /* VFP rather than Neon conversions. */
13542 do_vfp_nsyn_cvt (rs
, flavour
);
13552 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13554 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13557 /* Fixed-point conversion with #0 immediate is encoded as an
13558 integer conversion. */
13559 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
13561 immbits
= 32 - inst
.operands
[2].imm
;
13562 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13564 inst
.instruction
|= enctab
[flavour
];
13565 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13566 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13567 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13568 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13569 inst
.instruction
|= neon_quad (rs
) << 6;
13570 inst
.instruction
|= 1 << 21;
13571 inst
.instruction
|= immbits
<< 16;
13573 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13581 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
13583 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13585 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13589 inst
.instruction
|= enctab
[flavour
];
13591 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13592 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13593 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13594 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13595 inst
.instruction
|= neon_quad (rs
) << 6;
13596 inst
.instruction
|= 2 << 18;
13598 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13602 /* Half-precision conversions for Advanced SIMD -- neon. */
13607 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
13609 as_bad (_("operand size must match register width"));
13614 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
13616 as_bad (_("operand size must match register width"));
13621 inst
.instruction
= 0x3b60600;
13623 inst
.instruction
= 0x3b60700;
13625 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13626 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13627 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13628 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13629 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13633 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
13634 do_vfp_nsyn_cvt (rs
, flavour
);
13639 do_neon_cvtb (void)
13641 inst
.instruction
= 0xeb20a40;
13643 /* The sizes are attached to the mnemonic. */
13644 if (inst
.vectype
.el
[0].type
!= NT_invtype
13645 && inst
.vectype
.el
[0].size
== 16)
13646 inst
.instruction
|= 0x00010000;
13648 /* Programmer's syntax: the sizes are attached to the operands. */
13649 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
13650 && inst
.operands
[0].vectype
.size
== 16)
13651 inst
.instruction
|= 0x00010000;
13653 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
13654 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
13655 do_vfp_cond_or_thumb ();
13660 do_neon_cvtt (void)
13663 inst
.instruction
|= 0x80;
13667 neon_move_immediate (void)
13669 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
13670 struct neon_type_el et
= neon_check_type (2, rs
,
13671 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13672 unsigned immlo
, immhi
= 0, immbits
;
13673 int op
, cmode
, float_p
;
13675 constraint (et
.type
== NT_invtype
,
13676 _("operand size must be specified for immediate VMOV"));
13678 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
13679 op
= (inst
.instruction
& (1 << 5)) != 0;
13681 immlo
= inst
.operands
[1].imm
;
13682 if (inst
.operands
[1].regisimm
)
13683 immhi
= inst
.operands
[1].reg
;
13685 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
13686 _("immediate has bits set outside the operand size"));
13688 float_p
= inst
.operands
[1].immisfloat
;
13690 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
13691 et
.size
, et
.type
)) == FAIL
)
13693 /* Invert relevant bits only. */
13694 neon_invert_size (&immlo
, &immhi
, et
.size
);
13695 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
13696 with one or the other; those cases are caught by
13697 neon_cmode_for_move_imm. */
13699 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
13700 &op
, et
.size
, et
.type
)) == FAIL
)
13702 first_error (_("immediate out of range"));
13707 inst
.instruction
&= ~(1 << 5);
13708 inst
.instruction
|= op
<< 5;
13710 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13711 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13712 inst
.instruction
|= neon_quad (rs
) << 6;
13713 inst
.instruction
|= cmode
<< 8;
13715 neon_write_immbits (immbits
);
13721 if (inst
.operands
[1].isreg
)
13723 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13725 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13726 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13727 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13728 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13729 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13730 inst
.instruction
|= neon_quad (rs
) << 6;
13734 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13735 neon_move_immediate ();
13738 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13741 /* Encode instructions of form:
13743 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13744 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
13747 neon_mixed_length (struct neon_type_el et
, unsigned size
)
13749 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13750 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13751 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13752 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13753 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13754 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13755 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
13756 inst
.instruction
|= neon_logbits (size
) << 20;
13758 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13762 do_neon_dyadic_long (void)
13764 /* FIXME: Type checking for lengthening op. */
13765 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13766 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13767 neon_mixed_length (et
, et
.size
);
13771 do_neon_abal (void)
13773 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13774 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13775 neon_mixed_length (et
, et
.size
);
13779 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
13781 if (inst
.operands
[2].isscalar
)
13783 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
13784 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
13785 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13786 neon_mul_mac (et
, et
.type
== NT_unsigned
);
13790 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13791 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
13792 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13793 neon_mixed_length (et
, et
.size
);
13798 do_neon_mac_maybe_scalar_long (void)
13800 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
13804 do_neon_dyadic_wide (void)
13806 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
13807 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13808 neon_mixed_length (et
, et
.size
);
13812 do_neon_dyadic_narrow (void)
13814 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13815 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
13816 /* Operand sign is unimportant, and the U bit is part of the opcode,
13817 so force the operand type to integer. */
13818 et
.type
= NT_integer
;
13819 neon_mixed_length (et
, et
.size
/ 2);
13823 do_neon_mul_sat_scalar_long (void)
13825 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
13829 do_neon_vmull (void)
13831 if (inst
.operands
[2].isscalar
)
13832 do_neon_mac_maybe_scalar_long ();
13835 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13836 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
13837 if (et
.type
== NT_poly
)
13838 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
13840 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13841 /* For polynomial encoding, size field must be 0b00 and the U bit must be
13842 zero. Should be OK as-is. */
13843 neon_mixed_length (et
, et
.size
);
13850 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
13851 struct neon_type_el et
= neon_check_type (3, rs
,
13852 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13853 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
13855 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
13856 _("shift out of range"));
13857 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13858 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13859 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13860 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13861 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13862 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13863 inst
.instruction
|= neon_quad (rs
) << 6;
13864 inst
.instruction
|= imm
<< 8;
13866 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13872 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13873 struct neon_type_el et
= neon_check_type (2, rs
,
13874 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13875 unsigned op
= (inst
.instruction
>> 7) & 3;
13876 /* N (width of reversed regions) is encoded as part of the bitmask. We
13877 extract it here to check the elements to be reversed are smaller.
13878 Otherwise we'd get a reserved instruction. */
13879 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
13880 gas_assert (elsize
!= 0);
13881 constraint (et
.size
>= elsize
,
13882 _("elements must be smaller than reversal region"));
13883 neon_two_same (neon_quad (rs
), 1, et
.size
);
13889 if (inst
.operands
[1].isscalar
)
13891 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
13892 struct neon_type_el et
= neon_check_type (2, rs
,
13893 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13894 unsigned sizebits
= et
.size
>> 3;
13895 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13896 int logsize
= neon_logbits (et
.size
);
13897 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
13899 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
13902 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13903 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13904 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13905 inst
.instruction
|= LOW4 (dm
);
13906 inst
.instruction
|= HI1 (dm
) << 5;
13907 inst
.instruction
|= neon_quad (rs
) << 6;
13908 inst
.instruction
|= x
<< 17;
13909 inst
.instruction
|= sizebits
<< 16;
13911 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13915 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
13916 struct neon_type_el et
= neon_check_type (2, rs
,
13917 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13918 /* Duplicate ARM register to lanes of vector. */
13919 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
13922 case 8: inst
.instruction
|= 0x400000; break;
13923 case 16: inst
.instruction
|= 0x000020; break;
13924 case 32: inst
.instruction
|= 0x000000; break;
13927 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13928 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
13929 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
13930 inst
.instruction
|= neon_quad (rs
) << 21;
13931 /* The encoding for this instruction is identical for the ARM and Thumb
13932 variants, except for the condition field. */
13933 do_vfp_cond_or_thumb ();
13937 /* VMOV has particularly many variations. It can be one of:
13938 0. VMOV<c><q> <Qd>, <Qm>
13939 1. VMOV<c><q> <Dd>, <Dm>
13940 (Register operations, which are VORR with Rm = Rn.)
13941 2. VMOV<c><q>.<dt> <Qd>, #<imm>
13942 3. VMOV<c><q>.<dt> <Dd>, #<imm>
13944 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
13945 (ARM register to scalar.)
13946 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
13947 (Two ARM registers to vector.)
13948 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
13949 (Scalar to ARM register.)
13950 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
13951 (Vector to two ARM registers.)
13952 8. VMOV.F32 <Sd>, <Sm>
13953 9. VMOV.F64 <Dd>, <Dm>
13954 (VFP register moves.)
13955 10. VMOV.F32 <Sd>, #imm
13956 11. VMOV.F64 <Dd>, #imm
13957 (VFP float immediate load.)
13958 12. VMOV <Rd>, <Sm>
13959 (VFP single to ARM reg.)
13960 13. VMOV <Sd>, <Rm>
13961 (ARM reg to VFP single.)
13962 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
13963 (Two ARM regs to two VFP singles.)
13964 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
13965 (Two VFP singles to two ARM regs.)
13967 These cases can be disambiguated using neon_select_shape, except cases 1/9
13968 and 3/11 which depend on the operand type too.
13970 All the encoded bits are hardcoded by this function.
13972 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
13973 Cases 5, 7 may be used with VFPv2 and above.
13975 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
13976 can specify a type where it doesn't make sense to, and is ignored). */
13981 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
13982 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
13984 struct neon_type_el et
;
13985 const char *ldconst
= 0;
13989 case NS_DD
: /* case 1/9. */
13990 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13991 /* It is not an error here if no type is given. */
13993 if (et
.type
== NT_float
&& et
.size
== 64)
13995 do_vfp_nsyn_opcode ("fcpyd");
13998 /* fall through. */
14000 case NS_QQ
: /* case 0/1. */
14002 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14004 /* The architecture manual I have doesn't explicitly state which
14005 value the U bit should have for register->register moves, but
14006 the equivalent VORR instruction has U = 0, so do that. */
14007 inst
.instruction
= 0x0200110;
14008 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14009 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14010 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14011 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14012 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14013 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14014 inst
.instruction
|= neon_quad (rs
) << 6;
14016 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14020 case NS_DI
: /* case 3/11. */
14021 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14023 if (et
.type
== NT_float
&& et
.size
== 64)
14025 /* case 11 (fconstd). */
14026 ldconst
= "fconstd";
14027 goto encode_fconstd
;
14029 /* fall through. */
14031 case NS_QI
: /* case 2/3. */
14032 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14034 inst
.instruction
= 0x0800010;
14035 neon_move_immediate ();
14036 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14039 case NS_SR
: /* case 4. */
14041 unsigned bcdebits
= 0;
14042 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
14043 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14044 int logsize
= neon_logbits (et
.size
);
14045 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14046 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14048 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14050 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14051 && et
.size
!= 32, _(BAD_FPU
));
14052 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14053 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14057 case 8: bcdebits
= 0x8; break;
14058 case 16: bcdebits
= 0x1; break;
14059 case 32: bcdebits
= 0x0; break;
14063 bcdebits
|= x
<< logsize
;
14065 inst
.instruction
= 0xe000b10;
14066 do_vfp_cond_or_thumb ();
14067 inst
.instruction
|= LOW4 (dn
) << 16;
14068 inst
.instruction
|= HI1 (dn
) << 7;
14069 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14070 inst
.instruction
|= (bcdebits
& 3) << 5;
14071 inst
.instruction
|= (bcdebits
>> 2) << 21;
14075 case NS_DRR
: /* case 5 (fmdrr). */
14076 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14079 inst
.instruction
= 0xc400b10;
14080 do_vfp_cond_or_thumb ();
14081 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14082 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14083 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14084 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14087 case NS_RS
: /* case 6. */
14089 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
14090 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14091 unsigned logsize
= neon_logbits (et
.size
);
14092 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14093 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14094 unsigned abcdebits
= 0;
14096 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14098 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14099 && et
.size
!= 32, _(BAD_FPU
));
14100 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14101 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14105 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14106 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14107 case 32: abcdebits
= 0x00; break;
14111 abcdebits
|= x
<< logsize
;
14112 inst
.instruction
= 0xe100b10;
14113 do_vfp_cond_or_thumb ();
14114 inst
.instruction
|= LOW4 (dn
) << 16;
14115 inst
.instruction
|= HI1 (dn
) << 7;
14116 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14117 inst
.instruction
|= (abcdebits
& 3) << 5;
14118 inst
.instruction
|= (abcdebits
>> 2) << 21;
14122 case NS_RRD
: /* case 7 (fmrrd). */
14123 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14126 inst
.instruction
= 0xc500b10;
14127 do_vfp_cond_or_thumb ();
14128 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14129 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14130 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14131 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14134 case NS_FF
: /* case 8 (fcpys). */
14135 do_vfp_nsyn_opcode ("fcpys");
14138 case NS_FI
: /* case 10 (fconsts). */
14139 ldconst
= "fconsts";
14141 if (is_quarter_float (inst
.operands
[1].imm
))
14143 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14144 do_vfp_nsyn_opcode (ldconst
);
14147 first_error (_("immediate out of range"));
14150 case NS_RF
: /* case 12 (fmrs). */
14151 do_vfp_nsyn_opcode ("fmrs");
14154 case NS_FR
: /* case 13 (fmsr). */
14155 do_vfp_nsyn_opcode ("fmsr");
14158 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14159 (one of which is a list), but we have parsed four. Do some fiddling to
14160 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14162 case NS_RRFF
: /* case 14 (fmrrs). */
14163 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14164 _("VFP registers must be adjacent"));
14165 inst
.operands
[2].imm
= 2;
14166 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14167 do_vfp_nsyn_opcode ("fmrrs");
14170 case NS_FFRR
: /* case 15 (fmsrr). */
14171 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14172 _("VFP registers must be adjacent"));
14173 inst
.operands
[1] = inst
.operands
[2];
14174 inst
.operands
[2] = inst
.operands
[3];
14175 inst
.operands
[0].imm
= 2;
14176 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14177 do_vfp_nsyn_opcode ("fmsrr");
14186 do_neon_rshift_round_imm (void)
14188 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14189 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14190 int imm
= inst
.operands
[2].imm
;
14192 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14195 inst
.operands
[2].present
= 0;
14200 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14201 _("immediate out of range for shift"));
14202 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14207 do_neon_movl (void)
14209 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14210 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14211 unsigned sizebits
= et
.size
>> 3;
14212 inst
.instruction
|= sizebits
<< 19;
14213 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14219 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14220 struct neon_type_el et
= neon_check_type (2, rs
,
14221 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14222 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
14223 neon_two_same (neon_quad (rs
), 1, et
.size
);
14227 do_neon_zip_uzp (void)
14229 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14230 struct neon_type_el et
= neon_check_type (2, rs
,
14231 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14232 if (rs
== NS_DD
&& et
.size
== 32)
14234 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14235 inst
.instruction
= N_MNEM_vtrn
;
14239 neon_two_same (neon_quad (rs
), 1, et
.size
);
14243 do_neon_sat_abs_neg (void)
14245 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14246 struct neon_type_el et
= neon_check_type (2, rs
,
14247 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14248 neon_two_same (neon_quad (rs
), 1, et
.size
);
14252 do_neon_pair_long (void)
14254 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14255 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14256 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14257 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14258 neon_two_same (neon_quad (rs
), 1, et
.size
);
14262 do_neon_recip_est (void)
14264 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14265 struct neon_type_el et
= neon_check_type (2, rs
,
14266 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14267 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14268 neon_two_same (neon_quad (rs
), 1, et
.size
);
14274 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14275 struct neon_type_el et
= neon_check_type (2, rs
,
14276 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14277 neon_two_same (neon_quad (rs
), 1, et
.size
);
14283 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14284 struct neon_type_el et
= neon_check_type (2, rs
,
14285 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14286 neon_two_same (neon_quad (rs
), 1, et
.size
);
14292 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14293 struct neon_type_el et
= neon_check_type (2, rs
,
14294 N_EQK
| N_INT
, N_8
| N_KEY
);
14295 neon_two_same (neon_quad (rs
), 1, et
.size
);
14301 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14302 neon_two_same (neon_quad (rs
), 1, -1);
14306 do_neon_tbl_tbx (void)
14308 unsigned listlenbits
;
14309 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
14311 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
14313 first_error (_("bad list length for table lookup"));
14317 listlenbits
= inst
.operands
[1].imm
- 1;
14318 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14319 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14320 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14321 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14322 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14323 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14324 inst
.instruction
|= listlenbits
<< 8;
14326 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
14330 do_neon_ldm_stm (void)
14332 /* P, U and L bits are part of bitmask. */
14333 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
14334 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
14336 if (inst
.operands
[1].issingle
)
14338 do_vfp_nsyn_ldm_stm (is_dbmode
);
14342 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
14343 _("writeback (!) must be used for VLDMDB and VSTMDB"));
14345 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14346 _("register list must contain at least 1 and at most 16 "
14349 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14350 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
14351 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14352 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
14354 inst
.instruction
|= offsetbits
;
14356 do_vfp_cond_or_thumb ();
14360 do_neon_ldr_str (void)
14362 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
14364 if (inst
.operands
[0].issingle
)
14367 do_vfp_nsyn_opcode ("flds");
14369 do_vfp_nsyn_opcode ("fsts");
14374 do_vfp_nsyn_opcode ("fldd");
14376 do_vfp_nsyn_opcode ("fstd");
14380 /* "interleave" version also handles non-interleaving register VLD1/VST1
14384 do_neon_ld_st_interleave (void)
14386 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14387 N_8
| N_16
| N_32
| N_64
);
14388 unsigned alignbits
= 0;
14390 /* The bits in this table go:
14391 0: register stride of one (0) or two (1)
14392 1,2: register list length, minus one (1, 2, 3, 4).
14393 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14394 We use -1 for invalid entries. */
14395 const int typetable
[] =
14397 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14398 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14399 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14400 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14404 if (et
.type
== NT_invtype
)
14407 if (inst
.operands
[1].immisalign
)
14408 switch (inst
.operands
[1].imm
>> 8)
14410 case 64: alignbits
= 1; break;
14412 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14413 goto bad_alignment
;
14417 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14418 goto bad_alignment
;
14423 first_error (_("bad alignment"));
14427 inst
.instruction
|= alignbits
<< 4;
14428 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14430 /* Bits [4:6] of the immediate in a list specifier encode register stride
14431 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14432 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14433 up the right value for "type" in a table based on this value and the given
14434 list style, then stick it back. */
14435 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14436 | (((inst
.instruction
>> 8) & 3) << 3);
14438 typebits
= typetable
[idx
];
14440 constraint (typebits
== -1, _("bad list type for instruction"));
14442 inst
.instruction
&= ~0xf00;
14443 inst
.instruction
|= typebits
<< 8;
14446 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14447 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14448 otherwise. The variable arguments are a list of pairs of legal (size, align)
14449 values, terminated with -1. */
14452 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14455 int result
= FAIL
, thissize
, thisalign
;
14457 if (!inst
.operands
[1].immisalign
)
14463 va_start (ap
, do_align
);
14467 thissize
= va_arg (ap
, int);
14468 if (thissize
== -1)
14470 thisalign
= va_arg (ap
, int);
14472 if (size
== thissize
&& align
== thisalign
)
14475 while (result
!= SUCCESS
);
14479 if (result
== SUCCESS
)
14482 first_error (_("unsupported alignment for instruction"));
14488 do_neon_ld_st_lane (void)
14490 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14491 int align_good
, do_align
= 0;
14492 int logsize
= neon_logbits (et
.size
);
14493 int align
= inst
.operands
[1].imm
>> 8;
14494 int n
= (inst
.instruction
>> 8) & 3;
14495 int max_el
= 64 / et
.size
;
14497 if (et
.type
== NT_invtype
)
14500 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
14501 _("bad list length"));
14502 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
14503 _("scalar index out of range"));
14504 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
14506 _("stride of 2 unavailable when element size is 8"));
14510 case 0: /* VLD1 / VST1. */
14511 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
14513 if (align_good
== FAIL
)
14517 unsigned alignbits
= 0;
14520 case 16: alignbits
= 0x1; break;
14521 case 32: alignbits
= 0x3; break;
14524 inst
.instruction
|= alignbits
<< 4;
14528 case 1: /* VLD2 / VST2. */
14529 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
14531 if (align_good
== FAIL
)
14534 inst
.instruction
|= 1 << 4;
14537 case 2: /* VLD3 / VST3. */
14538 constraint (inst
.operands
[1].immisalign
,
14539 _("can't use alignment with this instruction"));
14542 case 3: /* VLD4 / VST4. */
14543 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14544 16, 64, 32, 64, 32, 128, -1);
14545 if (align_good
== FAIL
)
14549 unsigned alignbits
= 0;
14552 case 8: alignbits
= 0x1; break;
14553 case 16: alignbits
= 0x1; break;
14554 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
14557 inst
.instruction
|= alignbits
<< 4;
14564 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
14565 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14566 inst
.instruction
|= 1 << (4 + logsize
);
14568 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
14569 inst
.instruction
|= logsize
<< 10;
14572 /* Encode single n-element structure to all lanes VLD<n> instructions. */
14575 do_neon_ld_dup (void)
14577 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14578 int align_good
, do_align
= 0;
14580 if (et
.type
== NT_invtype
)
14583 switch ((inst
.instruction
>> 8) & 3)
14585 case 0: /* VLD1. */
14586 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
14587 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14588 &do_align
, 16, 16, 32, 32, -1);
14589 if (align_good
== FAIL
)
14591 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
14594 case 2: inst
.instruction
|= 1 << 5; break;
14595 default: first_error (_("bad list length")); return;
14597 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14600 case 1: /* VLD2. */
14601 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14602 &do_align
, 8, 16, 16, 32, 32, 64, -1);
14603 if (align_good
== FAIL
)
14605 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
14606 _("bad list length"));
14607 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14608 inst
.instruction
|= 1 << 5;
14609 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14612 case 2: /* VLD3. */
14613 constraint (inst
.operands
[1].immisalign
,
14614 _("can't use alignment with this instruction"));
14615 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
14616 _("bad list length"));
14617 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14618 inst
.instruction
|= 1 << 5;
14619 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14622 case 3: /* VLD4. */
14624 int align
= inst
.operands
[1].imm
>> 8;
14625 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14626 16, 64, 32, 64, 32, 128, -1);
14627 if (align_good
== FAIL
)
14629 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
14630 _("bad list length"));
14631 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14632 inst
.instruction
|= 1 << 5;
14633 if (et
.size
== 32 && align
== 128)
14634 inst
.instruction
|= 0x3 << 6;
14636 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14643 inst
.instruction
|= do_align
<< 4;
14646 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
14647 apart from bits [11:4]. */
14650 do_neon_ldx_stx (void)
14652 switch (NEON_LANE (inst
.operands
[0].imm
))
14654 case NEON_INTERLEAVE_LANES
:
14655 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
14656 do_neon_ld_st_interleave ();
14659 case NEON_ALL_LANES
:
14660 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
14665 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
14666 do_neon_ld_st_lane ();
14669 /* L bit comes from bit mask. */
14670 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14671 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14672 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14674 if (inst
.operands
[1].postind
)
14676 int postreg
= inst
.operands
[1].imm
& 0xf;
14677 constraint (!inst
.operands
[1].immisreg
,
14678 _("post-index must be a register"));
14679 constraint (postreg
== 0xd || postreg
== 0xf,
14680 _("bad register for post-index"));
14681 inst
.instruction
|= postreg
;
14683 else if (inst
.operands
[1].writeback
)
14685 inst
.instruction
|= 0xd;
14688 inst
.instruction
|= 0xf;
14691 inst
.instruction
|= 0xf9000000;
14693 inst
.instruction
|= 0xf4000000;
14696 /* Overall per-instruction processing. */
14698 /* We need to be able to fix up arbitrary expressions in some statements.
14699 This is so that we can handle symbols that are an arbitrary distance from
14700 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
14701 which returns part of an address in a form which will be valid for
14702 a data instruction. We do this by pushing the expression into a symbol
14703 in the expr_section, and creating a fix for that. */
14706 fix_new_arm (fragS
* frag
,
14721 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
14725 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
14730 /* Mark whether the fix is to a THUMB instruction, or an ARM
14732 new_fix
->tc_fix_data
= thumb_mode
;
14735 /* Create a frg for an instruction requiring relaxation. */
14737 output_relax_insn (void)
14743 /* The size of the instruction is unknown, so tie the debug info to the
14744 start of the instruction. */
14745 dwarf2_emit_insn (0);
14747 switch (inst
.reloc
.exp
.X_op
)
14750 sym
= inst
.reloc
.exp
.X_add_symbol
;
14751 offset
= inst
.reloc
.exp
.X_add_number
;
14755 offset
= inst
.reloc
.exp
.X_add_number
;
14758 sym
= make_expr_symbol (&inst
.reloc
.exp
);
14762 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
14763 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
14764 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
14767 /* Write a 32-bit thumb instruction to buf. */
14769 put_thumb32_insn (char * buf
, unsigned long insn
)
14771 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
14772 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
14776 output_inst (const char * str
)
14782 as_bad ("%s -- `%s'", inst
.error
, str
);
14787 output_relax_insn ();
14790 if (inst
.size
== 0)
14793 to
= frag_more (inst
.size
);
14794 /* PR 9814: Record the thumb mode into the current frag so that we know
14795 what type of NOP padding to use, if necessary. We override any previous
14796 setting so that if the mode has changed then the NOPS that we use will
14797 match the encoding of the last instruction in the frag. */
14798 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
14800 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
14802 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
14803 put_thumb32_insn (to
, inst
.instruction
);
14805 else if (inst
.size
> INSN_SIZE
)
14807 gas_assert (inst
.size
== (2 * INSN_SIZE
));
14808 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
14809 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
14812 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
14814 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
14815 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
14816 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
14819 dwarf2_emit_insn (inst
.size
);
14823 output_it_inst (int cond
, int mask
, char * to
)
14825 unsigned long instruction
= 0xbf00;
14828 instruction
|= mask
;
14829 instruction
|= cond
<< 4;
14833 to
= frag_more (2);
14835 dwarf2_emit_insn (2);
14839 md_number_to_chars (to
, instruction
, 2);
14844 /* Tag values used in struct asm_opcode's tag field. */
14847 OT_unconditional
, /* Instruction cannot be conditionalized.
14848 The ARM condition field is still 0xE. */
14849 OT_unconditionalF
, /* Instruction cannot be conditionalized
14850 and carries 0xF in its ARM condition field. */
14851 OT_csuffix
, /* Instruction takes a conditional suffix. */
14852 OT_csuffixF
, /* Some forms of the instruction take a conditional
14853 suffix, others place 0xF where the condition field
14855 OT_cinfix3
, /* Instruction takes a conditional infix,
14856 beginning at character index 3. (In
14857 unified mode, it becomes a suffix.) */
14858 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
14859 tsts, cmps, cmns, and teqs. */
14860 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
14861 character index 3, even in unified mode. Used for
14862 legacy instructions where suffix and infix forms
14863 may be ambiguous. */
14864 OT_csuf_or_in3
, /* Instruction takes either a conditional
14865 suffix or an infix at character index 3. */
14866 OT_odd_infix_unc
, /* This is the unconditional variant of an
14867 instruction that takes a conditional infix
14868 at an unusual position. In unified mode,
14869 this variant will accept a suffix. */
14870 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
14871 are the conditional variants of instructions that
14872 take conditional infixes in unusual positions.
14873 The infix appears at character index
14874 (tag - OT_odd_infix_0). These are not accepted
14875 in unified mode. */
14878 /* Subroutine of md_assemble, responsible for looking up the primary
14879 opcode from the mnemonic the user wrote. STR points to the
14880 beginning of the mnemonic.
14882 This is not simply a hash table lookup, because of conditional
14883 variants. Most instructions have conditional variants, which are
14884 expressed with a _conditional affix_ to the mnemonic. If we were
14885 to encode each conditional variant as a literal string in the opcode
14886 table, it would have approximately 20,000 entries.
14888 Most mnemonics take this affix as a suffix, and in unified syntax,
14889 'most' is upgraded to 'all'. However, in the divided syntax, some
14890 instructions take the affix as an infix, notably the s-variants of
14891 the arithmetic instructions. Of those instructions, all but six
14892 have the infix appear after the third character of the mnemonic.
14894 Accordingly, the algorithm for looking up primary opcodes given
14897 1. Look up the identifier in the opcode table.
14898 If we find a match, go to step U.
14900 2. Look up the last two characters of the identifier in the
14901 conditions table. If we find a match, look up the first N-2
14902 characters of the identifier in the opcode table. If we
14903 find a match, go to step CE.
14905 3. Look up the fourth and fifth characters of the identifier in
14906 the conditions table. If we find a match, extract those
14907 characters from the identifier, and look up the remaining
14908 characters in the opcode table. If we find a match, go
14913 U. Examine the tag field of the opcode structure, in case this is
14914 one of the six instructions with its conditional infix in an
14915 unusual place. If it is, the tag tells us where to find the
14916 infix; look it up in the conditions table and set inst.cond
14917 accordingly. Otherwise, this is an unconditional instruction.
14918 Again set inst.cond accordingly. Return the opcode structure.
14920 CE. Examine the tag field to make sure this is an instruction that
14921 should receive a conditional suffix. If it is not, fail.
14922 Otherwise, set inst.cond from the suffix we already looked up,
14923 and return the opcode structure.
14925 CM. Examine the tag field to make sure this is an instruction that
14926 should receive a conditional infix after the third character.
14927 If it is not, fail. Otherwise, undo the edits to the current
14928 line of input and proceed as for case CE. */
14930 static const struct asm_opcode
*
14931 opcode_lookup (char **str
)
14935 const struct asm_opcode
*opcode
;
14936 const struct asm_cond
*cond
;
14938 bfd_boolean neon_supported
;
14940 neon_supported
= ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
);
14942 /* Scan up to the end of the mnemonic, which must end in white space,
14943 '.' (in unified mode, or for Neon instructions), or end of string. */
14944 for (base
= end
= *str
; *end
!= '\0'; end
++)
14945 if (*end
== ' ' || ((unified_syntax
|| neon_supported
) && *end
== '.'))
14951 /* Handle a possible width suffix and/or Neon type suffix. */
14956 /* The .w and .n suffixes are only valid if the unified syntax is in
14958 if (unified_syntax
&& end
[1] == 'w')
14960 else if (unified_syntax
&& end
[1] == 'n')
14965 inst
.vectype
.elems
= 0;
14967 *str
= end
+ offset
;
14969 if (end
[offset
] == '.')
14971 /* See if we have a Neon type suffix (possible in either unified or
14972 non-unified ARM syntax mode). */
14973 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
14976 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
14982 /* Look for unaffixed or special-case affixed mnemonic. */
14983 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
14987 if (opcode
->tag
< OT_odd_infix_0
)
14989 inst
.cond
= COND_ALWAYS
;
14993 if (warn_on_deprecated
&& unified_syntax
)
14994 as_warn (_("conditional infixes are deprecated in unified syntax"));
14995 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
14996 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14999 inst
.cond
= cond
->value
;
15003 /* Cannot have a conditional suffix on a mnemonic of less than two
15005 if (end
- base
< 3)
15008 /* Look for suffixed mnemonic. */
15010 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
15011 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
15012 if (opcode
&& cond
)
15015 switch (opcode
->tag
)
15017 case OT_cinfix3_legacy
:
15018 /* Ignore conditional suffixes matched on infix only mnemonics. */
15022 case OT_cinfix3_deprecated
:
15023 case OT_odd_infix_unc
:
15024 if (!unified_syntax
)
15026 /* else fall through */
15030 case OT_csuf_or_in3
:
15031 inst
.cond
= cond
->value
;
15034 case OT_unconditional
:
15035 case OT_unconditionalF
:
15037 inst
.cond
= cond
->value
;
15040 /* Delayed diagnostic. */
15041 inst
.error
= BAD_COND
;
15042 inst
.cond
= COND_ALWAYS
;
15051 /* Cannot have a usual-position infix on a mnemonic of less than
15052 six characters (five would be a suffix). */
15053 if (end
- base
< 6)
15056 /* Look for infixed mnemonic in the usual position. */
15058 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
15062 memcpy (save
, affix
, 2);
15063 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15064 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
15065 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15066 memcpy (affix
, save
, 2);
15069 && (opcode
->tag
== OT_cinfix3
15070 || opcode
->tag
== OT_cinfix3_deprecated
15071 || opcode
->tag
== OT_csuf_or_in3
15072 || opcode
->tag
== OT_cinfix3_legacy
))
15075 if (warn_on_deprecated
&& unified_syntax
15076 && (opcode
->tag
== OT_cinfix3
15077 || opcode
->tag
== OT_cinfix3_deprecated
))
15078 as_warn (_("conditional infixes are deprecated in unified syntax"));
15080 inst
.cond
= cond
->value
;
15087 /* This function generates an initial IT instruction, leaving its block
15088 virtually open for the new instructions. Eventually,
15089 the mask will be updated by now_it_add_mask () each time
15090 a new instruction needs to be included in the IT block.
15091 Finally, the block is closed with close_automatic_it_block ().
15092 The block closure can be requested either from md_assemble (),
15093 a tencode (), or due to a label hook. */
15096 new_automatic_it_block (int cond
)
15098 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15099 now_it
.mask
= 0x18;
15101 now_it
.block_length
= 1;
15102 mapping_state (MAP_THUMB
);
15103 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15106 /* Close an automatic IT block.
15107 See comments in new_automatic_it_block (). */
15110 close_automatic_it_block (void)
15112 now_it
.mask
= 0x10;
15113 now_it
.block_length
= 0;
15116 /* Update the mask of the current automatically-generated IT
15117 instruction. See comments in new_automatic_it_block (). */
15120 now_it_add_mask (int cond
)
15122 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15123 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15124 | ((bitvalue) << (nbit)))
15125 const int resulting_bit
= (cond
& 1);
15127 now_it
.mask
&= 0xf;
15128 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15130 (5 - now_it
.block_length
));
15131 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15133 ((5 - now_it
.block_length
) - 1) );
15134 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15137 #undef SET_BIT_VALUE
15140 /* The IT blocks handling machinery is accessed through the these functions:
15141 it_fsm_pre_encode () from md_assemble ()
15142 set_it_insn_type () optional, from the tencode functions
15143 set_it_insn_type_last () ditto
15144 in_it_block () ditto
15145 it_fsm_post_encode () from md_assemble ()
15146 force_automatic_it_block_close () from label habdling functions
15149 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15150 initializing the IT insn type with a generic initial value depending
15151 on the inst.condition.
15152 2) During the tencode function, two things may happen:
15153 a) The tencode function overrides the IT insn type by
15154 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15155 b) The tencode function queries the IT block state by
15156 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15158 Both set_it_insn_type and in_it_block run the internal FSM state
15159 handling function (handle_it_state), because: a) setting the IT insn
15160 type may incur in an invalid state (exiting the function),
15161 and b) querying the state requires the FSM to be updated.
15162 Specifically we want to avoid creating an IT block for conditional
15163 branches, so it_fsm_pre_encode is actually a guess and we can't
15164 determine whether an IT block is required until the tencode () routine
15165 has decided what type of instruction this actually it.
15166 Because of this, if set_it_insn_type and in_it_block have to be used,
15167 set_it_insn_type has to be called first.
15169 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15170 determines the insn IT type depending on the inst.cond code.
15171 When a tencode () routine encodes an instruction that can be
15172 either outside an IT block, or, in the case of being inside, has to be
15173 the last one, set_it_insn_type_last () will determine the proper
15174 IT instruction type based on the inst.cond code. Otherwise,
15175 set_it_insn_type can be called for overriding that logic or
15176 for covering other cases.
15178 Calling handle_it_state () may not transition the IT block state to
15179 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15180 still queried. Instead, if the FSM determines that the state should
15181 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15182 after the tencode () function: that's what it_fsm_post_encode () does.
15184 Since in_it_block () calls the state handling function to get an
15185 updated state, an error may occur (due to invalid insns combination).
15186 In that case, inst.error is set.
15187 Therefore, inst.error has to be checked after the execution of
15188 the tencode () routine.
15190 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15191 any pending state change (if any) that didn't take place in
15192 handle_it_state () as explained above. */
15195 it_fsm_pre_encode (void)
15197 if (inst
.cond
!= COND_ALWAYS
)
15198 inst
.it_insn_type
= INSIDE_IT_INSN
;
15200 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15202 now_it
.state_handled
= 0;
15205 /* IT state FSM handling function. */
15208 handle_it_state (void)
15210 now_it
.state_handled
= 1;
15212 switch (now_it
.state
)
15214 case OUTSIDE_IT_BLOCK
:
15215 switch (inst
.it_insn_type
)
15217 case OUTSIDE_IT_INSN
:
15220 case INSIDE_IT_INSN
:
15221 case INSIDE_IT_LAST_INSN
:
15222 if (thumb_mode
== 0)
15225 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15226 as_tsktsk (_("Warning: conditional outside an IT block"\
15231 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15232 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15234 /* Automatically generate the IT instruction. */
15235 new_automatic_it_block (inst
.cond
);
15236 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15237 close_automatic_it_block ();
15241 inst
.error
= BAD_OUT_IT
;
15247 case IF_INSIDE_IT_LAST_INSN
:
15248 case NEUTRAL_IT_INSN
:
15252 now_it
.state
= MANUAL_IT_BLOCK
;
15253 now_it
.block_length
= 0;
15258 case AUTOMATIC_IT_BLOCK
:
15259 /* Three things may happen now:
15260 a) We should increment current it block size;
15261 b) We should close current it block (closing insn or 4 insns);
15262 c) We should close current it block and start a new one (due
15263 to incompatible conditions or
15264 4 insns-length block reached). */
15266 switch (inst
.it_insn_type
)
15268 case OUTSIDE_IT_INSN
:
15269 /* The closure of the block shall happen immediatelly,
15270 so any in_it_block () call reports the block as closed. */
15271 force_automatic_it_block_close ();
15274 case INSIDE_IT_INSN
:
15275 case INSIDE_IT_LAST_INSN
:
15276 case IF_INSIDE_IT_LAST_INSN
:
15277 now_it
.block_length
++;
15279 if (now_it
.block_length
> 4
15280 || !now_it_compatible (inst
.cond
))
15282 force_automatic_it_block_close ();
15283 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
15284 new_automatic_it_block (inst
.cond
);
15288 now_it_add_mask (inst
.cond
);
15291 if (now_it
.state
== AUTOMATIC_IT_BLOCK
15292 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
15293 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
15294 close_automatic_it_block ();
15297 case NEUTRAL_IT_INSN
:
15298 now_it
.block_length
++;
15300 if (now_it
.block_length
> 4)
15301 force_automatic_it_block_close ();
15303 now_it_add_mask (now_it
.cc
& 1);
15307 close_automatic_it_block ();
15308 now_it
.state
= MANUAL_IT_BLOCK
;
15313 case MANUAL_IT_BLOCK
:
15315 /* Check conditional suffixes. */
15316 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
15319 now_it
.mask
&= 0x1f;
15320 is_last
= (now_it
.mask
== 0x10);
15322 switch (inst
.it_insn_type
)
15324 case OUTSIDE_IT_INSN
:
15325 inst
.error
= BAD_NOT_IT
;
15328 case INSIDE_IT_INSN
:
15329 if (cond
!= inst
.cond
)
15331 inst
.error
= BAD_IT_COND
;
15336 case INSIDE_IT_LAST_INSN
:
15337 case IF_INSIDE_IT_LAST_INSN
:
15338 if (cond
!= inst
.cond
)
15340 inst
.error
= BAD_IT_COND
;
15345 inst
.error
= BAD_BRANCH
;
15350 case NEUTRAL_IT_INSN
:
15351 /* The BKPT instruction is unconditional even in an IT block. */
15355 inst
.error
= BAD_IT_IT
;
15366 it_fsm_post_encode (void)
15370 if (!now_it
.state_handled
)
15371 handle_it_state ();
15373 is_last
= (now_it
.mask
== 0x10);
15376 now_it
.state
= OUTSIDE_IT_BLOCK
;
15382 force_automatic_it_block_close (void)
15384 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
15386 close_automatic_it_block ();
15387 now_it
.state
= OUTSIDE_IT_BLOCK
;
15395 if (!now_it
.state_handled
)
15396 handle_it_state ();
15398 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
15402 md_assemble (char *str
)
15405 const struct asm_opcode
* opcode
;
15407 /* Align the previous label if needed. */
15408 if (last_label_seen
!= NULL
)
15410 symbol_set_frag (last_label_seen
, frag_now
);
15411 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
15412 S_SET_SEGMENT (last_label_seen
, now_seg
);
15415 memset (&inst
, '\0', sizeof (inst
));
15416 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
15418 opcode
= opcode_lookup (&p
);
15421 /* It wasn't an instruction, but it might be a register alias of
15422 the form alias .req reg, or a Neon .dn/.qn directive. */
15423 if (! create_register_alias (str
, p
)
15424 && ! create_neon_reg_alias (str
, p
))
15425 as_bad (_("bad instruction `%s'"), str
);
15430 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
15431 as_warn (_("s suffix on comparison instruction is deprecated"));
15433 /* The value which unconditional instructions should have in place of the
15434 condition field. */
15435 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
15439 arm_feature_set variant
;
15441 variant
= cpu_variant
;
15442 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
15443 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
15444 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
15445 /* Check that this instruction is supported for this CPU. */
15446 if (!opcode
->tvariant
15447 || (thumb_mode
== 1
15448 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
15450 as_bad (_("selected processor does not support `%s'"), str
);
15453 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
15454 && opcode
->tencode
!= do_t_branch
)
15456 as_bad (_("Thumb does not support conditional execution"));
15460 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
15462 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
15463 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
15464 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
15466 /* Two things are addressed here.
15467 1) Implicit require narrow instructions on Thumb-1.
15468 This avoids relaxation accidentally introducing Thumb-2
15470 2) Reject wide instructions in non Thumb-2 cores. */
15471 if (inst
.size_req
== 0)
15473 else if (inst
.size_req
== 4)
15475 as_bad (_("selected processor does not support `%s'"), str
);
15481 inst
.instruction
= opcode
->tvalue
;
15483 if (!parse_operands (p
, opcode
->operands
))
15485 /* Prepare the it_insn_type for those encodings that don't set
15487 it_fsm_pre_encode ();
15489 opcode
->tencode ();
15491 it_fsm_post_encode ();
15494 if (!(inst
.error
|| inst
.relax
))
15496 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
15497 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
15498 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
15500 as_bad (_("cannot honor width suffix -- `%s'"), str
);
15505 /* Something has gone badly wrong if we try to relax a fixed size
15507 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
15509 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15510 *opcode
->tvariant
);
15511 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
15512 set those bits when Thumb-2 32-bit instructions are seen. ie.
15513 anything other than bl/blx and v6-M instructions.
15514 This is overly pessimistic for relaxable instructions. */
15515 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
15517 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
15518 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
15519 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15523 mapping_state (MAP_THUMB
);
15525 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
15529 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
15530 is_bx
= (opcode
->aencode
== do_bx
);
15532 /* Check that this instruction is supported for this CPU. */
15533 if (!(is_bx
&& fix_v4bx
)
15534 && !(opcode
->avariant
&&
15535 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
15537 as_bad (_("selected processor does not support `%s'"), str
);
15542 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
15546 inst
.instruction
= opcode
->avalue
;
15547 if (opcode
->tag
== OT_unconditionalF
)
15548 inst
.instruction
|= 0xF << 28;
15550 inst
.instruction
|= inst
.cond
<< 28;
15551 inst
.size
= INSN_SIZE
;
15552 if (!parse_operands (p
, opcode
->operands
))
15554 it_fsm_pre_encode ();
15555 opcode
->aencode ();
15556 it_fsm_post_encode ();
15558 /* Arm mode bx is marked as both v4T and v5 because it's still required
15559 on a hypothetical non-thumb v5 core. */
15561 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
15563 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
15564 *opcode
->avariant
);
15566 mapping_state (MAP_ARM
);
15570 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
15578 check_it_blocks_finished (void)
15583 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
15584 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
15585 == MANUAL_IT_BLOCK
)
15587 as_warn (_("section '%s' finished with an open IT block."),
15591 if (now_it
.state
== MANUAL_IT_BLOCK
)
15592 as_warn (_("file finished with an open IT block."));
15596 /* Various frobbings of labels and their addresses. */
15599 arm_start_line_hook (void)
15601 last_label_seen
= NULL
;
15605 arm_frob_label (symbolS
* sym
)
15607 last_label_seen
= sym
;
15609 ARM_SET_THUMB (sym
, thumb_mode
);
15611 #if defined OBJ_COFF || defined OBJ_ELF
15612 ARM_SET_INTERWORK (sym
, support_interwork
);
15615 force_automatic_it_block_close ();
15617 /* Note - do not allow local symbols (.Lxxx) to be labelled
15618 as Thumb functions. This is because these labels, whilst
15619 they exist inside Thumb code, are not the entry points for
15620 possible ARM->Thumb calls. Also, these labels can be used
15621 as part of a computed goto or switch statement. eg gcc
15622 can generate code that looks like this:
15624 ldr r2, [pc, .Laaa]
15634 The first instruction loads the address of the jump table.
15635 The second instruction converts a table index into a byte offset.
15636 The third instruction gets the jump address out of the table.
15637 The fourth instruction performs the jump.
15639 If the address stored at .Laaa is that of a symbol which has the
15640 Thumb_Func bit set, then the linker will arrange for this address
15641 to have the bottom bit set, which in turn would mean that the
15642 address computation performed by the third instruction would end
15643 up with the bottom bit set. Since the ARM is capable of unaligned
15644 word loads, the instruction would then load the incorrect address
15645 out of the jump table, and chaos would ensue. */
15646 if (label_is_thumb_function_name
15647 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
15648 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
15650 /* When the address of a Thumb function is taken the bottom
15651 bit of that address should be set. This will allow
15652 interworking between Arm and Thumb functions to work
15655 THUMB_SET_FUNC (sym
, 1);
15657 label_is_thumb_function_name
= FALSE
;
15660 dwarf2_emit_label (sym
);
15664 arm_data_in_code (void)
15666 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
15668 *input_line_pointer
= '/';
15669 input_line_pointer
+= 5;
15670 *input_line_pointer
= 0;
15678 arm_canonicalize_symbol_name (char * name
)
15682 if (thumb_mode
&& (len
= strlen (name
)) > 5
15683 && streq (name
+ len
- 5, "/data"))
15684 *(name
+ len
- 5) = 0;
15689 /* Table of all register names defined by default. The user can
15690 define additional names with .req. Note that all register names
15691 should appear in both upper and lowercase variants. Some registers
15692 also have mixed-case names. */
15694 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
15695 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
15696 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
15697 #define REGSET(p,t) \
15698 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
15699 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
15700 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
15701 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
15702 #define REGSETH(p,t) \
15703 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
15704 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
15705 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
15706 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
15707 #define REGSET2(p,t) \
15708 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
15709 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
15710 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
15711 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
15713 static const struct reg_entry reg_names
[] =
15715 /* ARM integer registers. */
15716 REGSET(r
, RN
), REGSET(R
, RN
),
15718 /* ATPCS synonyms. */
15719 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
15720 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
15721 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
15723 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
15724 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
15725 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
15727 /* Well-known aliases. */
15728 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
15729 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
15731 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
15732 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
15734 /* Coprocessor numbers. */
15735 REGSET(p
, CP
), REGSET(P
, CP
),
15737 /* Coprocessor register numbers. The "cr" variants are for backward
15739 REGSET(c
, CN
), REGSET(C
, CN
),
15740 REGSET(cr
, CN
), REGSET(CR
, CN
),
15742 /* FPA registers. */
15743 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
15744 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
15746 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
15747 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
15749 /* VFP SP registers. */
15750 REGSET(s
,VFS
), REGSET(S
,VFS
),
15751 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
15753 /* VFP DP Registers. */
15754 REGSET(d
,VFD
), REGSET(D
,VFD
),
15755 /* Extra Neon DP registers. */
15756 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
15758 /* Neon QP registers. */
15759 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
15761 /* VFP control registers. */
15762 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
15763 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
15764 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
15765 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
15766 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
15767 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
15769 /* Maverick DSP coprocessor registers. */
15770 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
15771 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
15773 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
15774 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
15775 REGDEF(dspsc
,0,DSPSC
),
15777 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
15778 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
15779 REGDEF(DSPSC
,0,DSPSC
),
15781 /* iWMMXt data registers - p0, c0-15. */
15782 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
15784 /* iWMMXt control registers - p1, c0-3. */
15785 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
15786 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
15787 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
15788 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
15790 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
15791 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
15792 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
15793 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
15794 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
15796 /* XScale accumulator registers. */
15797 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
15803 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
15804 within psr_required_here. */
15805 static const struct asm_psr psrs
[] =
15807 /* Backward compatibility notation. Note that "all" is no longer
15808 truly all possible PSR bits. */
15809 {"all", PSR_c
| PSR_f
},
15813 /* Individual flags. */
15818 /* Combinations of flags. */
15819 {"fs", PSR_f
| PSR_s
},
15820 {"fx", PSR_f
| PSR_x
},
15821 {"fc", PSR_f
| PSR_c
},
15822 {"sf", PSR_s
| PSR_f
},
15823 {"sx", PSR_s
| PSR_x
},
15824 {"sc", PSR_s
| PSR_c
},
15825 {"xf", PSR_x
| PSR_f
},
15826 {"xs", PSR_x
| PSR_s
},
15827 {"xc", PSR_x
| PSR_c
},
15828 {"cf", PSR_c
| PSR_f
},
15829 {"cs", PSR_c
| PSR_s
},
15830 {"cx", PSR_c
| PSR_x
},
15831 {"fsx", PSR_f
| PSR_s
| PSR_x
},
15832 {"fsc", PSR_f
| PSR_s
| PSR_c
},
15833 {"fxs", PSR_f
| PSR_x
| PSR_s
},
15834 {"fxc", PSR_f
| PSR_x
| PSR_c
},
15835 {"fcs", PSR_f
| PSR_c
| PSR_s
},
15836 {"fcx", PSR_f
| PSR_c
| PSR_x
},
15837 {"sfx", PSR_s
| PSR_f
| PSR_x
},
15838 {"sfc", PSR_s
| PSR_f
| PSR_c
},
15839 {"sxf", PSR_s
| PSR_x
| PSR_f
},
15840 {"sxc", PSR_s
| PSR_x
| PSR_c
},
15841 {"scf", PSR_s
| PSR_c
| PSR_f
},
15842 {"scx", PSR_s
| PSR_c
| PSR_x
},
15843 {"xfs", PSR_x
| PSR_f
| PSR_s
},
15844 {"xfc", PSR_x
| PSR_f
| PSR_c
},
15845 {"xsf", PSR_x
| PSR_s
| PSR_f
},
15846 {"xsc", PSR_x
| PSR_s
| PSR_c
},
15847 {"xcf", PSR_x
| PSR_c
| PSR_f
},
15848 {"xcs", PSR_x
| PSR_c
| PSR_s
},
15849 {"cfs", PSR_c
| PSR_f
| PSR_s
},
15850 {"cfx", PSR_c
| PSR_f
| PSR_x
},
15851 {"csf", PSR_c
| PSR_s
| PSR_f
},
15852 {"csx", PSR_c
| PSR_s
| PSR_x
},
15853 {"cxf", PSR_c
| PSR_x
| PSR_f
},
15854 {"cxs", PSR_c
| PSR_x
| PSR_s
},
15855 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
15856 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
15857 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
15858 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
15859 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
15860 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
15861 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
15862 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
15863 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
15864 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
15865 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
15866 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
15867 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
15868 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
15869 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
15870 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
15871 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
15872 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
15873 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
15874 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
15875 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
15876 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
15877 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
15878 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
15881 /* Table of V7M psr names. */
15882 static const struct asm_psr v7m_psrs
[] =
15884 {"apsr", 0 }, {"APSR", 0 },
15885 {"iapsr", 1 }, {"IAPSR", 1 },
15886 {"eapsr", 2 }, {"EAPSR", 2 },
15887 {"psr", 3 }, {"PSR", 3 },
15888 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
15889 {"ipsr", 5 }, {"IPSR", 5 },
15890 {"epsr", 6 }, {"EPSR", 6 },
15891 {"iepsr", 7 }, {"IEPSR", 7 },
15892 {"msp", 8 }, {"MSP", 8 },
15893 {"psp", 9 }, {"PSP", 9 },
15894 {"primask", 16}, {"PRIMASK", 16},
15895 {"basepri", 17}, {"BASEPRI", 17},
15896 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
15897 {"faultmask", 19}, {"FAULTMASK", 19},
15898 {"control", 20}, {"CONTROL", 20}
15901 /* Table of all shift-in-operand names. */
15902 static const struct asm_shift_name shift_names
[] =
15904 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
15905 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
15906 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
15907 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
15908 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
15909 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
15912 /* Table of all explicit relocation names. */
15914 static struct reloc_entry reloc_names
[] =
15916 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
15917 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
15918 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
15919 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
15920 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
15921 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
15922 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
15923 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
15924 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
15925 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
15926 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
15930 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
15931 static const struct asm_cond conds
[] =
15935 {"cs", 0x2}, {"hs", 0x2},
15936 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
15950 static struct asm_barrier_opt barrier_opt_names
[] =
15958 /* Table of ARM-format instructions. */
15960 /* Macros for gluing together operand strings. N.B. In all cases
15961 other than OPS0, the trailing OP_stop comes from default
15962 zero-initialization of the unspecified elements of the array. */
15963 #define OPS0() { OP_stop, }
15964 #define OPS1(a) { OP_##a, }
15965 #define OPS2(a,b) { OP_##a,OP_##b, }
15966 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
15967 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
15968 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
15969 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
15971 /* These macros abstract out the exact format of the mnemonic table and
15972 save some repeated characters. */
15974 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
15975 #define TxCE(mnem, op, top, nops, ops, ae, te) \
15976 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
15977 THUMB_VARIANT, do_##ae, do_##te }
15979 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
15980 a T_MNEM_xyz enumerator. */
15981 #define TCE(mnem, aop, top, nops, ops, ae, te) \
15982 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
15983 #define tCE(mnem, aop, top, nops, ops, ae, te) \
15984 TxCE (mnem, aop, T_MNEM_##top, nops, ops, ae, te)
15986 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
15987 infix after the third character. */
15988 #define TxC3(mnem, op, top, nops, ops, ae, te) \
15989 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
15990 THUMB_VARIANT, do_##ae, do_##te }
15991 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
15992 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
15993 THUMB_VARIANT, do_##ae, do_##te }
15994 #define TC3(mnem, aop, top, nops, ops, ae, te) \
15995 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
15996 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
15997 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
15998 #define tC3(mnem, aop, top, nops, ops, ae, te) \
15999 TxC3 (mnem, aop, T_MNEM_##top, nops, ops, ae, te)
16000 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16001 TxC3w (mnem, aop, T_MNEM_##top, nops, ops, ae, te)
16003 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16004 appear in the condition table. */
16005 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16006 { #m1 #m2 #m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (#m1) - 1, \
16007 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16009 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16010 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16011 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16012 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16013 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16014 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16015 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16016 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16017 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16018 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16019 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16020 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16021 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16022 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16023 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16024 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16025 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16026 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16027 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16028 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16030 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16031 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16032 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16033 TxCM (m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
16035 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16036 field is still 0xE. Many of the Thumb variants can be executed
16037 conditionally, so this is checked separately. */
16038 #define TUE(mnem, op, top, nops, ops, ae, te) \
16039 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16040 THUMB_VARIANT, do_##ae, do_##te }
16042 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16043 condition code field. */
16044 #define TUF(mnem, op, top, nops, ops, ae, te) \
16045 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16046 THUMB_VARIANT, do_##ae, do_##te }
16048 /* ARM-only variants of all the above. */
16049 #define CE(mnem, op, nops, ops, ae) \
16050 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16052 #define C3(mnem, op, nops, ops, ae) \
16053 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16055 /* Legacy mnemonics that always have conditional infix after the third
16057 #define CL(mnem, op, nops, ops, ae) \
16058 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
16059 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16061 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16062 #define cCE(mnem, op, nops, ops, ae) \
16063 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16065 /* Legacy coprocessor instructions where conditional infix and conditional
16066 suffix are ambiguous. For consistency this includes all FPA instructions,
16067 not just the potentially ambiguous ones. */
16068 #define cCL(mnem, op, nops, ops, ae) \
16069 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
16070 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16072 /* Coprocessor, takes either a suffix or a position-3 infix
16073 (for an FPA corner case). */
16074 #define C3E(mnem, op, nops, ops, ae) \
16075 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
16076 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16078 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16079 { #m1 #m2 #m3, OPS##nops ops, \
16080 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (#m1) - 1, \
16081 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16083 #define CM(m1, m2, op, nops, ops, ae) \
16084 xCM_ (m1, , m2, op, nops, ops, ae), \
16085 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16086 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16087 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16088 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16089 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16090 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16091 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16092 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16093 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16094 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16095 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16096 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16097 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16098 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16099 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16100 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16101 xCM_ (m1, le, m2, op, nops, ops, ae), \
16102 xCM_ (m1, al, m2, op, nops, ops, ae)
16104 #define UE(mnem, op, nops, ops, ae) \
16105 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16107 #define UF(mnem, op, nops, ops, ae) \
16108 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16110 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16111 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16112 use the same encoding function for each. */
16113 #define NUF(mnem, op, nops, ops, enc) \
16114 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16115 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16117 /* Neon data processing, version which indirects through neon_enc_tab for
16118 the various overloaded versions of opcodes. */
16119 #define nUF(mnem, op, nops, ops, enc) \
16120 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
16121 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16123 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16125 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16126 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16127 THUMB_VARIANT, do_##enc, do_##enc }
16129 #define NCE(mnem, op, nops, ops, enc) \
16130 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16132 #define NCEF(mnem, op, nops, ops, enc) \
16133 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16135 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16136 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16137 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
16138 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16140 #define nCE(mnem, op, nops, ops, enc) \
16141 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16143 #define nCEF(mnem, op, nops, ops, enc) \
16144 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16148 /* Thumb-only, unconditional. */
16149 #define UT(mnem, op, nops, ops, te) TUE (mnem, 0, op, nops, ops, 0, te)
16151 static const struct asm_opcode insns
[] =
16153 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16154 #define THUMB_VARIANT &arm_ext_v4t
16155 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16156 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16157 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16158 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16159 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16160 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16161 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16162 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16163 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16164 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16165 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16166 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16167 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16168 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16169 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16170 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16172 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16173 for setting PSR flag bits. They are obsolete in V6 and do not
16174 have Thumb equivalents. */
16175 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16176 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16177 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
16178 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16179 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16180 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
16181 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16182 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16183 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
16185 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16186 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16187 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16188 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16190 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16191 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16192 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16193 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16195 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16196 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16197 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16198 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16199 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16200 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16202 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16203 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16204 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
16205 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
16208 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
16209 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
16210 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
16212 /* Thumb-compatibility pseudo ops. */
16213 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16214 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16215 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16216 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16217 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16218 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16219 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16220 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16221 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
16222 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
16223 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
16224 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
16226 /* These may simplify to neg. */
16227 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16228 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16230 #undef THUMB_VARIANT
16231 #define THUMB_VARIANT & arm_ext_v6
16233 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
16235 /* V1 instructions with no Thumb analogue prior to V6T2. */
16236 #undef THUMB_VARIANT
16237 #define THUMB_VARIANT & arm_ext_v6t2
16239 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16240 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16241 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
16243 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16244 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16245 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16246 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
16248 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16249 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16251 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16252 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16254 /* V1 instructions with no Thumb analogue at all. */
16255 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
16256 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
16258 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16259 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16260 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16261 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16262 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16263 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16264 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16265 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16268 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
16269 #undef THUMB_VARIANT
16270 #define THUMB_VARIANT & arm_ext_v4t
16272 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16273 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16275 #undef THUMB_VARIANT
16276 #define THUMB_VARIANT & arm_ext_v6t2
16278 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16279 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
16281 /* Generic coprocessor instructions. */
16282 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16283 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16284 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16285 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16286 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16287 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16288 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16291 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
16293 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16294 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16297 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
16298 #undef THUMB_VARIANT
16299 #define THUMB_VARIANT & arm_ext_msr
16301 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
16302 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
16305 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
16306 #undef THUMB_VARIANT
16307 #define THUMB_VARIANT & arm_ext_v6t2
16309 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16310 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16311 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16312 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16313 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16314 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16315 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16316 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16319 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
16320 #undef THUMB_VARIANT
16321 #define THUMB_VARIANT & arm_ext_v4t
16323 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16324 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16325 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16326 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16327 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16328 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
16331 #define ARM_VARIANT & arm_ext_v4t_5
16333 /* ARM Architecture 4T. */
16334 /* Note: bx (and blx) are required on V5, even if the processor does
16335 not support Thumb. */
16336 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
16339 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
16340 #undef THUMB_VARIANT
16341 #define THUMB_VARIANT & arm_ext_v5t
16343 /* Note: blx has 2 variants; the .value coded here is for
16344 BLX(2). Only this variant has conditional execution. */
16345 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
16346 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
16348 #undef THUMB_VARIANT
16349 #define THUMB_VARIANT & arm_ext_v6t2
16351 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
16352 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16353 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16354 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16355 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16356 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16357 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16358 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16361 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
16363 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16364 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16365 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16366 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16368 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16369 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16371 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16372 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16373 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16374 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16376 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16377 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16378 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16379 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16381 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16382 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16384 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
16385 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
16386 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
16387 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
16390 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
16392 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
16393 TC3(ldrd
, 00000d0
, e8500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
16394 TC3(strd
, 00000f0
, e8400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
16396 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16397 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16400 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
16402 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
16405 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
16406 #undef THUMB_VARIANT
16407 #define THUMB_VARIANT & arm_ext_v6
16409 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16410 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16411 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16412 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16413 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16414 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16415 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16416 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16417 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16418 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
16420 #undef THUMB_VARIANT
16421 #define THUMB_VARIANT & arm_ext_v6t2
16423 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
16424 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
16425 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16426 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16428 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
16429 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
16431 /* ARM V6 not included in V7M (eg. integer SIMD). */
16432 #undef THUMB_VARIANT
16433 #define THUMB_VARIANT & arm_ext_v6_notm
16435 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
16436 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
16437 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
16438 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16439 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16440 TCE(qasx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16441 /* Old name for QASX. */
16442 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16443 TCE(qsax
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16444 /* Old name for QSAX. */
16445 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16446 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16447 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16448 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16449 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16450 TCE(sasx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16451 /* Old name for SASX. */
16452 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16453 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16454 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16455 TCE(shasx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16456 /* Old name for SHASX. */
16457 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16458 TCE(shsax
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16459 /* Old name for SHSAX. */
16460 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16461 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16462 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16463 TCE(ssax
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16464 /* Old name for SSAX. */
16465 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16466 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16467 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16468 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16469 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16470 TCE(uasx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16471 /* Old name for UASX. */
16472 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16473 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16474 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16475 TCE(uhasx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16476 /* Old name for UHASX. */
16477 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16478 TCE(uhsax
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16479 /* Old name for UHSAX. */
16480 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16481 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16482 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16483 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16484 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16485 TCE(uqasx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16486 /* Old name for UQASX. */
16487 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16488 TCE(uqsax
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16489 /* Old name for UQSAX. */
16490 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16491 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16492 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16493 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16494 TCE(usax
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16495 /* Old name for USAX. */
16496 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16497 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16498 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16499 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
16500 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
16501 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16502 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16503 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
16504 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
16505 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16506 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16507 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16508 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16509 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16510 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16511 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16512 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16513 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16514 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16515 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16516 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16517 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16518 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16519 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16520 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16521 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16522 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16523 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16524 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16525 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16526 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16527 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16528 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16529 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16530 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16531 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16532 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16533 TUF(srsia
, 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
16534 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
16535 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
16536 TUF(srsdb
, 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
16537 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
16538 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
16539 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16540 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16541 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
16544 #define ARM_VARIANT & arm_ext_v6k
16545 #undef THUMB_VARIANT
16546 #define THUMB_VARIANT & arm_ext_v6k
16548 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
16549 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
16550 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
16551 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
16553 #undef THUMB_VARIANT
16554 #define THUMB_VARIANT & arm_ext_v6_notm
16556 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
16557 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
16559 #undef THUMB_VARIANT
16560 #define THUMB_VARIANT & arm_ext_v6t2
16562 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
16563 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
16564 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
16565 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
16566 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
16569 #define ARM_VARIANT & arm_ext_v6z
16571 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
16574 #define ARM_VARIANT & arm_ext_v6t2
16576 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
16577 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
16578 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16579 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16581 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16582 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16583 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16584 TCE(rbit
, 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
16586 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16587 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16588 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16589 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
16591 UT(cbnz
, b900
, 2, (RR
, EXP
), t_cbz
),
16592 UT(cbz
, b100
, 2, (RR
, EXP
), t_cbz
),
16594 /* ARM does not really have an IT instruction, so always allow it.
16595 The opcode is copied from Thumb in order to allow warnings in
16596 -mimplicit-it=[never | arm] modes. */
16598 #define ARM_VARIANT & arm_ext_v1
16600 TUE(it
, bf08
, bf08
, 1, (COND
), it
, t_it
),
16601 TUE(itt
, bf0c
, bf0c
, 1, (COND
), it
, t_it
),
16602 TUE(ite
, bf04
, bf04
, 1, (COND
), it
, t_it
),
16603 TUE(ittt
, bf0e
, bf0e
, 1, (COND
), it
, t_it
),
16604 TUE(itet
, bf06
, bf06
, 1, (COND
), it
, t_it
),
16605 TUE(itte
, bf0a
, bf0a
, 1, (COND
), it
, t_it
),
16606 TUE(itee
, bf02
, bf02
, 1, (COND
), it
, t_it
),
16607 TUE(itttt
, bf0f
, bf0f
, 1, (COND
), it
, t_it
),
16608 TUE(itett
, bf07
, bf07
, 1, (COND
), it
, t_it
),
16609 TUE(ittet
, bf0b
, bf0b
, 1, (COND
), it
, t_it
),
16610 TUE(iteet
, bf03
, bf03
, 1, (COND
), it
, t_it
),
16611 TUE(ittte
, bf0d
, bf0d
, 1, (COND
), it
, t_it
),
16612 TUE(itete
, bf05
, bf05
, 1, (COND
), it
, t_it
),
16613 TUE(ittee
, bf09
, bf09
, 1, (COND
), it
, t_it
),
16614 TUE(iteee
, bf01
, bf01
, 1, (COND
), it
, t_it
),
16615 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
16616 TC3(rrx
, 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16617 TC3(rrxs
, 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16619 /* Thumb2 only instructions. */
16621 #define ARM_VARIANT NULL
16623 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16624 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16625 TCE(orn
, 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16626 TCE(orns
, 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16627 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
16628 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
16630 /* Thumb-2 hardware division instructions (R and M profiles only). */
16631 #undef THUMB_VARIANT
16632 #define THUMB_VARIANT & arm_ext_div
16634 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16635 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16637 /* ARM V6M/V7 instructions. */
16639 #define ARM_VARIANT & arm_ext_barrier
16640 #undef THUMB_VARIANT
16641 #define THUMB_VARIANT & arm_ext_barrier
16643 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
16644 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
16645 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
16647 /* ARM V7 instructions. */
16649 #define ARM_VARIANT & arm_ext_v7
16650 #undef THUMB_VARIANT
16651 #define THUMB_VARIANT & arm_ext_v7
16653 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
16654 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
16657 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
16659 cCE(wfs
, e200110
, 1, (RR
), rd
),
16660 cCE(rfs
, e300110
, 1, (RR
), rd
),
16661 cCE(wfc
, e400110
, 1, (RR
), rd
),
16662 cCE(rfc
, e500110
, 1, (RR
), rd
),
16664 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16665 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16666 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16667 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16669 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16670 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16671 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16672 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16674 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
16675 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
16676 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
16677 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
16678 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
16679 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
16680 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
16681 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
16682 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
16683 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
16684 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
16685 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
16687 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
16688 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
16689 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
16690 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
16691 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
16692 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
16693 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
16694 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
16695 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
16696 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
16697 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
16698 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
16700 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
16701 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
16702 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
16703 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
16704 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
16705 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
16706 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
16707 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
16708 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
16709 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
16710 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
16711 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
16713 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
16714 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
16715 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
16716 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
16717 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
16718 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
16719 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
16720 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
16721 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
16722 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
16723 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
16724 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
16726 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
16727 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
16728 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
16729 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
16730 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
16731 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
16732 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
16733 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
16734 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
16735 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
16736 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
16737 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
16739 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
16740 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
16741 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
16742 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
16743 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
16744 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
16745 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
16746 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
16747 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
16748 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
16749 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
16750 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
16752 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
16753 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
16754 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
16755 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
16756 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
16757 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
16758 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
16759 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
16760 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
16761 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
16762 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
16763 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
16765 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
16766 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
16767 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
16768 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
16769 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
16770 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
16771 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
16772 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
16773 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
16774 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
16775 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
16776 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
16778 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
16779 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
16780 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
16781 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
16782 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
16783 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
16784 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
16785 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
16786 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
16787 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
16788 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
16789 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
16791 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
16792 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
16793 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
16794 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
16795 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
16796 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
16797 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
16798 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
16799 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
16800 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
16801 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
16802 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
16804 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
16805 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
16806 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
16807 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
16808 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
16809 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
16810 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
16811 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
16812 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
16813 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
16814 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
16815 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
16817 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
16818 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
16819 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
16820 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
16821 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
16822 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
16823 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
16824 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
16825 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
16826 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
16827 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
16828 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
16830 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
16831 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
16832 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
16833 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
16834 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
16835 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
16836 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
16837 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
16838 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
16839 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
16840 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
16841 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
16843 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
16844 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
16845 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
16846 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
16847 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
16848 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
16849 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
16850 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
16851 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
16852 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
16853 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
16854 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
16856 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
16857 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
16858 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
16859 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
16860 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
16861 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
16862 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
16863 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
16864 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
16865 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
16866 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
16867 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
16869 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
16870 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
16871 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
16872 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
16873 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
16874 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
16875 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
16876 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
16877 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
16878 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
16879 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
16880 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
16882 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16883 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16884 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16885 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16886 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16887 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16888 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16889 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16890 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16891 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16892 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16893 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16895 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16896 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16897 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16898 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16899 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16900 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16901 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16902 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16903 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16904 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16905 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16906 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16908 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16909 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16910 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16911 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16912 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16913 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16914 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16915 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16916 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16917 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16918 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16919 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16921 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16922 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16923 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16924 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16925 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16926 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16927 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16928 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16929 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16930 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16931 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16932 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16934 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16935 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16936 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16937 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16938 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16939 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16940 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16941 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16942 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16943 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16944 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16945 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16947 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16948 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16949 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16950 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16951 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16952 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16953 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16954 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16955 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16956 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16957 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16958 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16960 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16961 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16962 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16963 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16964 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16965 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16966 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16967 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16968 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16969 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16970 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16971 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16973 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16974 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16975 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16976 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16977 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16978 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16979 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16980 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16981 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16982 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16983 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16984 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16986 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16987 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16988 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16989 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16990 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16991 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16992 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16993 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16994 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16995 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16996 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16997 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16999 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17000 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17001 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17002 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17003 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17004 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17005 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17006 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17007 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17008 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17009 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17010 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17012 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17013 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17014 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17015 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17016 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17017 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17018 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17019 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17020 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17021 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17022 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17023 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17025 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17026 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17027 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17028 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17029 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17030 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17031 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17032 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17033 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17034 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17035 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17036 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17038 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17039 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17040 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17041 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17042 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17043 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17044 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17045 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17046 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17047 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17048 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17049 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17051 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17052 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17053 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17054 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17056 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
17057 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
17058 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
17059 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
17060 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
17061 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
17062 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
17063 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
17064 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
17065 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
17066 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
17067 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
17069 /* The implementation of the FIX instruction is broken on some
17070 assemblers, in that it accepts a precision specifier as well as a
17071 rounding specifier, despite the fact that this is meaningless.
17072 To be more compatible, we accept it as well, though of course it
17073 does not set any bits. */
17074 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
17075 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
17076 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
17077 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
17078 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
17079 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
17080 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
17081 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
17082 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
17083 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
17084 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
17085 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
17086 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
17088 /* Instructions that were new with the real FPA, call them V2. */
17090 #define ARM_VARIANT & fpu_fpa_ext_v2
17092 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17093 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17094 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17095 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17096 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17097 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17100 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17102 /* Moves and type conversions. */
17103 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17104 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17105 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17106 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
17107 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17108 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17109 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17110 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17111 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17112 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17113 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
17114 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
17116 /* Memory operations. */
17117 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17118 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17119 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17120 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17121 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17122 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17123 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17124 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17125 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17126 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17127 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17128 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17129 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17130 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17131 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17132 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17133 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17134 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17136 /* Monadic operations. */
17137 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17138 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17139 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17141 /* Dyadic operations. */
17142 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17143 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17144 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17145 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17146 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17147 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17148 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17149 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17150 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17153 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17154 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17155 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17156 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17159 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17161 /* Moves and type conversions. */
17162 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17163 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17164 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17165 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17166 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17167 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17168 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17169 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17170 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17171 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17172 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17173 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17174 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17176 /* Memory operations. */
17177 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17178 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17179 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17180 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17181 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17182 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17183 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17184 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17185 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17186 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17188 /* Monadic operations. */
17189 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17190 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17191 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17193 /* Dyadic operations. */
17194 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17195 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17196 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17197 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17198 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17199 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17200 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17201 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17202 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17205 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17206 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
17207 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17208 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
17211 #define ARM_VARIANT & fpu_vfp_ext_v2
17213 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
17214 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
17215 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
17216 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
17218 /* Instructions which may belong to either the Neon or VFP instruction sets.
17219 Individual encoder functions perform additional architecture checks. */
17221 #define ARM_VARIANT & fpu_vfp_ext_v1xd
17222 #undef THUMB_VARIANT
17223 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
17225 /* These mnemonics are unique to VFP. */
17226 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
17227 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
17228 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17229 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17230 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17231 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17232 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17233 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
17234 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
17235 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
17237 /* Mnemonics shared by Neon and VFP. */
17238 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
17239 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17240 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17242 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17243 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17245 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17246 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17248 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17249 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17250 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17251 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17252 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17253 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17254 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17255 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17257 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
17258 nCEF(vcvtb
, vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
17259 nCEF(vcvtt
, vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
17262 /* NOTE: All VMOV encoding is special-cased! */
17263 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
17264 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
17266 #undef THUMB_VARIANT
17267 #define THUMB_VARIANT & fpu_neon_ext_v1
17269 #define ARM_VARIANT & fpu_neon_ext_v1
17271 /* Data processing with three registers of the same length. */
17272 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
17273 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
17274 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
17275 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17276 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17277 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17278 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17279 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17280 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17281 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
17282 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17283 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17284 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17285 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17286 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17287 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17288 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17289 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17290 /* If not immediate, fall back to neon_dyadic_i64_su.
17291 shl_imm should accept I8 I16 I32 I64,
17292 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
17293 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
17294 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
17295 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
17296 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
17297 /* Logic ops, types optional & ignored. */
17298 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
17299 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
17300 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
17301 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
17302 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
17303 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
17304 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
17305 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
17306 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
17307 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
17308 /* Bitfield ops, untyped. */
17309 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17310 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17311 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17312 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17313 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17314 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17315 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
17316 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17317 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17318 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17319 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17320 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17321 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17322 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
17323 back to neon_dyadic_if_su. */
17324 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17325 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17326 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17327 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17328 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17329 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17330 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17331 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17332 /* Comparison. Type I8 I16 I32 F32. */
17333 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
17334 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
17335 /* As above, D registers only. */
17336 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17337 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17338 /* Int and float variants, signedness unimportant. */
17339 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17340 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17341 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
17342 /* Add/sub take types I8 I16 I32 I64 F32. */
17343 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17344 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17345 /* vtst takes sizes 8, 16, 32. */
17346 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
17347 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
17348 /* VMUL takes I8 I16 I32 F32 P8. */
17349 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
17350 /* VQD{R}MULH takes S16 S32. */
17351 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17352 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17353 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17354 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17355 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17356 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17357 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17358 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17359 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17360 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17361 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17362 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17363 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17364 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17365 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17366 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17368 /* Two address, int/float. Types S8 S16 S32 F32. */
17369 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17370 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17372 /* Data processing with two registers and a shift amount. */
17373 /* Right shifts, and variants with rounding.
17374 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
17375 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17376 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17377 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17378 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17379 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17380 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17381 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17382 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17383 /* Shift and insert. Sizes accepted 8 16 32 64. */
17384 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
17385 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
17386 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
17387 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
17388 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
17389 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
17390 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
17391 /* Right shift immediate, saturating & narrowing, with rounding variants.
17392 Types accepted S16 S32 S64 U16 U32 U64. */
17393 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17394 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17395 /* As above, unsigned. Types accepted S16 S32 S64. */
17396 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17397 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17398 /* Right shift narrowing. Types accepted I16 I32 I64. */
17399 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17400 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17401 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
17402 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
17403 /* CVT with optional immediate for fixed-point variant. */
17404 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
17406 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
17407 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
17409 /* Data processing, three registers of different lengths. */
17410 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
17411 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
17412 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17413 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17414 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17415 /* If not scalar, fall back to neon_dyadic_long.
17416 Vector types as above, scalar types S16 S32 U16 U32. */
17417 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17418 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17419 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
17420 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17421 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17422 /* Dyadic, narrowing insns. Types I16 I32 I64. */
17423 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17424 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17425 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17426 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17427 /* Saturating doubling multiplies. Types S16 S32. */
17428 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17429 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17430 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17431 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
17432 S16 S32 U16 U32. */
17433 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
17435 /* Extract. Size 8. */
17436 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
17437 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
17439 /* Two registers, miscellaneous. */
17440 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
17441 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
17442 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
17443 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
17444 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
17445 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
17446 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
17447 /* Vector replicate. Sizes 8 16 32. */
17448 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
17449 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
17450 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
17451 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
17452 /* VMOVN. Types I16 I32 I64. */
17453 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
17454 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
17455 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
17456 /* VQMOVUN. Types S16 S32 S64. */
17457 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
17458 /* VZIP / VUZP. Sizes 8 16 32. */
17459 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17460 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17461 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17462 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17463 /* VQABS / VQNEG. Types S8 S16 S32. */
17464 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17465 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17466 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17467 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17468 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
17469 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17470 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
17471 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17472 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
17473 /* Reciprocal estimates. Types U32 F32. */
17474 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17475 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
17476 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17477 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
17478 /* VCLS. Types S8 S16 S32. */
17479 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
17480 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
17481 /* VCLZ. Types I8 I16 I32. */
17482 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
17483 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
17484 /* VCNT. Size 8. */
17485 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
17486 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
17487 /* Two address, untyped. */
17488 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
17489 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
17490 /* VTRN. Sizes 8 16 32. */
17491 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
17492 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
17494 /* Table lookup. Size 8. */
17495 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17496 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17498 #undef THUMB_VARIANT
17499 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
17501 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
17503 /* Neon element/structure load/store. */
17504 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17505 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17506 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17507 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17508 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17509 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17510 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17511 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17513 #undef THUMB_VARIANT
17514 #define THUMB_VARIANT & fpu_vfp_ext_v3
17516 #define ARM_VARIANT & fpu_vfp_ext_v3
17518 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
17519 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
17520 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17521 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17522 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17523 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17524 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17525 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17526 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17527 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17528 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17529 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17530 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17531 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17532 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17533 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17534 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17535 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17537 #undef THUMB_VARIANT
17539 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
17541 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17542 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17543 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17544 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17545 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17546 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17547 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
17548 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
17551 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
17553 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
17554 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
17555 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
17556 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
17557 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
17558 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
17559 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
17560 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
17561 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
17562 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17563 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17564 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17565 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17566 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17567 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17568 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17569 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17570 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17571 cCE(tmcr
, e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
17572 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
17573 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17574 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17575 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17576 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17577 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17578 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17579 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
17580 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
17581 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
17582 cCE(tmrc
, e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
17583 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
17584 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
17585 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
17586 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
17587 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17588 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17589 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17590 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17591 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17592 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17593 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17594 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17595 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17596 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17597 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17598 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17599 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
17600 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17601 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17602 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17603 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17604 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17605 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17606 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17607 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17608 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17609 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17610 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17611 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17612 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17613 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17614 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17615 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17616 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17617 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17618 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17619 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17620 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17621 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
17622 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
17623 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17624 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17625 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17626 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17627 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17628 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17629 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17630 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17631 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17632 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17633 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17634 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17635 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17636 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17637 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17638 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17639 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17640 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17641 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
17642 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17643 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17644 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17645 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17646 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17647 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17648 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17649 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17650 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17651 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17652 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17653 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17654 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17655 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17656 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17657 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17658 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17659 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17660 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17661 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17662 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17663 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
17664 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17665 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17666 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17667 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17668 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17669 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17670 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17671 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17672 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17673 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17674 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17675 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17676 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17677 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17678 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17679 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17680 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17681 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17682 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17683 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17684 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
17685 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
17686 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17687 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17688 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17689 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17690 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17691 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17692 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17693 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17694 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17695 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17696 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17697 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17698 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17699 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17700 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
17701 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17702 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17703 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17704 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17705 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17706 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17707 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17708 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17709 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
17710 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17711 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17712 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17713 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17714 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
17717 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
17719 cCE(torvscb
, e12f190
, 1, (RR
), iwmmxt_tandorc
),
17720 cCE(torvsch
, e52f190
, 1, (RR
), iwmmxt_tandorc
),
17721 cCE(torvscw
, e92f190
, 1, (RR
), iwmmxt_tandorc
),
17722 cCE(wabsb
, e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17723 cCE(wabsh
, e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17724 cCE(wabsw
, ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17725 cCE(wabsdiffb
, e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17726 cCE(wabsdiffh
, e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17727 cCE(wabsdiffw
, e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17728 cCE(waddbhusl
, e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17729 cCE(waddbhusm
, e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17730 cCE(waddhc
, e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17731 cCE(waddwc
, ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17732 cCE(waddsubhx
, ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17733 cCE(wavg4
, e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17734 cCE(wavg4r
, e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17735 cCE(wmaddsn
, ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17736 cCE(wmaddsx
, eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17737 cCE(wmaddun
, ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17738 cCE(wmaddux
, e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17739 cCE(wmerge
, e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
17740 cCE(wmiabb
, e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17741 cCE(wmiabt
, e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17742 cCE(wmiatb
, e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17743 cCE(wmiatt
, e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17744 cCE(wmiabbn
, e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17745 cCE(wmiabtn
, e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17746 cCE(wmiatbn
, e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17747 cCE(wmiattn
, e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17748 cCE(wmiawbb
, e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17749 cCE(wmiawbt
, e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17750 cCE(wmiawtb
, ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17751 cCE(wmiawtt
, eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17752 cCE(wmiawbbn
, ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17753 cCE(wmiawbtn
, ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17754 cCE(wmiawtbn
, ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17755 cCE(wmiawttn
, ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17756 cCE(wmulsmr
, ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17757 cCE(wmulumr
, ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17758 cCE(wmulwumr
, ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17759 cCE(wmulwsmr
, ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17760 cCE(wmulwum
, ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17761 cCE(wmulwsm
, ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17762 cCE(wmulwl
, eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17763 cCE(wqmiabb
, e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17764 cCE(wqmiabt
, e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17765 cCE(wqmiatb
, ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17766 cCE(wqmiatt
, eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17767 cCE(wqmiabbn
, ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17768 cCE(wqmiabtn
, ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17769 cCE(wqmiatbn
, ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17770 cCE(wqmiattn
, ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17771 cCE(wqmulm
, e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17772 cCE(wqmulmr
, e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17773 cCE(wqmulwm
, ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17774 cCE(wqmulwmr
, ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17775 cCE(wsubaddhx
, ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17778 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
17780 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
17781 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
17782 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
17783 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
17784 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
17785 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
17786 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
17787 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
17788 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
17789 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
17790 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
17791 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
17792 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
17793 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
17794 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
17795 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
17796 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
17797 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
17798 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
17799 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
17800 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
17801 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
17802 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
17803 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
17804 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
17805 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
17806 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
17807 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
17808 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
17809 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
17810 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
17811 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
17812 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
17813 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
17814 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
17815 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
17816 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
17817 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
17818 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
17819 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
17820 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
17821 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
17822 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
17823 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
17824 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
17825 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
17826 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
17827 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
17828 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
17829 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
17830 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
17831 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
17832 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
17833 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
17834 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17835 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17836 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17837 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17838 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17839 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17840 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
17841 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
17842 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
17843 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
17844 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17845 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17846 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17847 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17848 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17849 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17850 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17851 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17852 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
17853 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
17854 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
17855 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
17858 #undef THUMB_VARIANT
17885 /* MD interface: bits in the object file. */
17887 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
17888 for use in the a.out file, and stores them in the array pointed to by buf.
17889 This knows about the endian-ness of the target machine and does
17890 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
17891 2 (short) and 4 (long) Floating numbers are put out as a series of
17892 LITTLENUMS (shorts, here at least). */
17895 md_number_to_chars (char * buf
, valueT val
, int n
)
17897 if (target_big_endian
)
17898 number_to_chars_bigendian (buf
, val
, n
);
17900 number_to_chars_littleendian (buf
, val
, n
);
17904 md_chars_to_number (char * buf
, int n
)
17907 unsigned char * where
= (unsigned char *) buf
;
17909 if (target_big_endian
)
17914 result
|= (*where
++ & 255);
17922 result
|= (where
[n
] & 255);
17929 /* MD interface: Sections. */
17931 /* Estimate the size of a frag before relaxing. Assume everything fits in
17935 md_estimate_size_before_relax (fragS
* fragp
,
17936 segT segtype ATTRIBUTE_UNUSED
)
17942 /* Convert a machine dependent frag. */
17945 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
17947 unsigned long insn
;
17948 unsigned long old_op
;
17956 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17958 old_op
= bfd_get_16(abfd
, buf
);
17959 if (fragp
->fr_symbol
)
17961 exp
.X_op
= O_symbol
;
17962 exp
.X_add_symbol
= fragp
->fr_symbol
;
17966 exp
.X_op
= O_constant
;
17968 exp
.X_add_number
= fragp
->fr_offset
;
17969 opcode
= fragp
->fr_subtype
;
17972 case T_MNEM_ldr_pc
:
17973 case T_MNEM_ldr_pc2
:
17974 case T_MNEM_ldr_sp
:
17975 case T_MNEM_str_sp
:
17982 if (fragp
->fr_var
== 4)
17984 insn
= THUMB_OP32 (opcode
);
17985 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
17987 insn
|= (old_op
& 0x700) << 4;
17991 insn
|= (old_op
& 7) << 12;
17992 insn
|= (old_op
& 0x38) << 13;
17994 insn
|= 0x00000c00;
17995 put_thumb32_insn (buf
, insn
);
17996 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18000 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18002 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18005 if (fragp
->fr_var
== 4)
18007 insn
= THUMB_OP32 (opcode
);
18008 insn
|= (old_op
& 0xf0) << 4;
18009 put_thumb32_insn (buf
, insn
);
18010 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18014 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18015 exp
.X_add_number
-= 4;
18023 if (fragp
->fr_var
== 4)
18025 int r0off
= (opcode
== T_MNEM_mov
18026 || opcode
== T_MNEM_movs
) ? 0 : 8;
18027 insn
= THUMB_OP32 (opcode
);
18028 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18029 insn
|= (old_op
& 0x700) << r0off
;
18030 put_thumb32_insn (buf
, insn
);
18031 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18035 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18040 if (fragp
->fr_var
== 4)
18042 insn
= THUMB_OP32(opcode
);
18043 put_thumb32_insn (buf
, insn
);
18044 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18047 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18051 if (fragp
->fr_var
== 4)
18053 insn
= THUMB_OP32(opcode
);
18054 insn
|= (old_op
& 0xf00) << 14;
18055 put_thumb32_insn (buf
, insn
);
18056 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18059 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18062 case T_MNEM_add_sp
:
18063 case T_MNEM_add_pc
:
18064 case T_MNEM_inc_sp
:
18065 case T_MNEM_dec_sp
:
18066 if (fragp
->fr_var
== 4)
18068 /* ??? Choose between add and addw. */
18069 insn
= THUMB_OP32 (opcode
);
18070 insn
|= (old_op
& 0xf0) << 4;
18071 put_thumb32_insn (buf
, insn
);
18072 if (opcode
== T_MNEM_add_pc
)
18073 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18075 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18078 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18086 if (fragp
->fr_var
== 4)
18088 insn
= THUMB_OP32 (opcode
);
18089 insn
|= (old_op
& 0xf0) << 4;
18090 insn
|= (old_op
& 0xf) << 16;
18091 put_thumb32_insn (buf
, insn
);
18092 if (insn
& (1 << 20))
18093 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18095 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18098 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18104 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18106 fixp
->fx_file
= fragp
->fr_file
;
18107 fixp
->fx_line
= fragp
->fr_line
;
18108 fragp
->fr_fix
+= fragp
->fr_var
;
18111 /* Return the size of a relaxable immediate operand instruction.
18112 SHIFT and SIZE specify the form of the allowable immediate. */
18114 relax_immediate (fragS
*fragp
, int size
, int shift
)
18120 /* ??? Should be able to do better than this. */
18121 if (fragp
->fr_symbol
)
18124 low
= (1 << shift
) - 1;
18125 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18126 offset
= fragp
->fr_offset
;
18127 /* Force misaligned offsets to 32-bit variant. */
18130 if (offset
& ~mask
)
18135 /* Get the address of a symbol during relaxation. */
18137 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
18143 sym
= fragp
->fr_symbol
;
18144 sym_frag
= symbol_get_frag (sym
);
18145 know (S_GET_SEGMENT (sym
) != absolute_section
18146 || sym_frag
== &zero_address_frag
);
18147 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
18149 /* If frag has yet to be reached on this pass, assume it will
18150 move by STRETCH just as we did. If this is not so, it will
18151 be because some frag between grows, and that will force
18155 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
18159 /* Adjust stretch for any alignment frag. Note that if have
18160 been expanding the earlier code, the symbol may be
18161 defined in what appears to be an earlier frag. FIXME:
18162 This doesn't handle the fr_subtype field, which specifies
18163 a maximum number of bytes to skip when doing an
18165 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
18167 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
18170 stretch
= - ((- stretch
)
18171 & ~ ((1 << (int) f
->fr_offset
) - 1));
18173 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
18185 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
18188 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
18193 /* Assume worst case for symbols not known to be in the same section. */
18194 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18195 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
18198 val
= relaxed_symbol_addr (fragp
, stretch
);
18199 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18200 addr
= (addr
+ 4) & ~3;
18201 /* Force misaligned targets to 32-bit variant. */
18205 if (val
< 0 || val
> 1020)
18210 /* Return the size of a relaxable add/sub immediate instruction. */
18212 relax_addsub (fragS
*fragp
, asection
*sec
)
18217 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18218 op
= bfd_get_16(sec
->owner
, buf
);
18219 if ((op
& 0xf) == ((op
>> 4) & 0xf))
18220 return relax_immediate (fragp
, 8, 0);
18222 return relax_immediate (fragp
, 3, 0);
18226 /* Return the size of a relaxable branch instruction. BITS is the
18227 size of the offset field in the narrow instruction. */
18230 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
18236 /* Assume worst case for symbols not known to be in the same section. */
18237 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18238 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
18242 if (S_IS_DEFINED (fragp
->fr_symbol
)
18243 && ARM_IS_FUNC (fragp
->fr_symbol
))
18247 val
= relaxed_symbol_addr (fragp
, stretch
);
18248 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18251 /* Offset is a signed value *2 */
18253 if (val
>= limit
|| val
< -limit
)
18259 /* Relax a machine dependent frag. This returns the amount by which
18260 the current size of the frag should change. */
18263 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18268 oldsize
= fragp
->fr_var
;
18269 switch (fragp
->fr_subtype
)
18271 case T_MNEM_ldr_pc2
:
18272 newsize
= relax_adr (fragp
, sec
, stretch
);
18274 case T_MNEM_ldr_pc
:
18275 case T_MNEM_ldr_sp
:
18276 case T_MNEM_str_sp
:
18277 newsize
= relax_immediate (fragp
, 8, 2);
18281 newsize
= relax_immediate (fragp
, 5, 2);
18285 newsize
= relax_immediate (fragp
, 5, 1);
18289 newsize
= relax_immediate (fragp
, 5, 0);
18292 newsize
= relax_adr (fragp
, sec
, stretch
);
18298 newsize
= relax_immediate (fragp
, 8, 0);
18301 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
18304 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
18306 case T_MNEM_add_sp
:
18307 case T_MNEM_add_pc
:
18308 newsize
= relax_immediate (fragp
, 8, 2);
18310 case T_MNEM_inc_sp
:
18311 case T_MNEM_dec_sp
:
18312 newsize
= relax_immediate (fragp
, 7, 2);
18318 newsize
= relax_addsub (fragp
, sec
);
18324 fragp
->fr_var
= newsize
;
18325 /* Freeze wide instructions that are at or before the same location as
18326 in the previous pass. This avoids infinite loops.
18327 Don't freeze them unconditionally because targets may be artificially
18328 misaligned by the expansion of preceding frags. */
18329 if (stretch
<= 0 && newsize
> 2)
18331 md_convert_frag (sec
->owner
, sec
, fragp
);
18335 return newsize
- oldsize
;
18338 /* Round up a section size to the appropriate boundary. */
18341 md_section_align (segT segment ATTRIBUTE_UNUSED
,
18344 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
18345 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
18347 /* For a.out, force the section size to be aligned. If we don't do
18348 this, BFD will align it for us, but it will not write out the
18349 final bytes of the section. This may be a bug in BFD, but it is
18350 easier to fix it here since that is how the other a.out targets
18354 align
= bfd_get_section_alignment (stdoutput
, segment
);
18355 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
18362 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
18363 of an rs_align_code fragment. */
18366 arm_handle_align (fragS
* fragP
)
18368 static char const arm_noop
[2][2][4] =
18371 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
18372 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
18375 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
18376 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
18379 static char const thumb_noop
[2][2][2] =
18382 {0xc0, 0x46}, /* LE */
18383 {0x46, 0xc0}, /* BE */
18386 {0x00, 0xbf}, /* LE */
18387 {0xbf, 0x00} /* BE */
18390 static char const wide_thumb_noop
[2][4] =
18391 { /* Wide Thumb-2 */
18392 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
18393 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
18396 unsigned bytes
, fix
, noop_size
;
18399 const char *narrow_noop
= NULL
;
18404 if (fragP
->fr_type
!= rs_align_code
)
18407 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
18408 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
18411 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18412 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
18414 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
18416 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
18418 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
18420 narrow_noop
= thumb_noop
[1][target_big_endian
];
18421 noop
= wide_thumb_noop
[target_big_endian
];
18424 noop
= thumb_noop
[0][target_big_endian
];
18432 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
18433 [target_big_endian
];
18440 fragP
->fr_var
= noop_size
;
18442 if (bytes
& (noop_size
- 1))
18444 fix
= bytes
& (noop_size
- 1);
18446 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
18448 memset (p
, 0, fix
);
18455 if (bytes
& noop_size
)
18457 /* Insert a narrow noop. */
18458 memcpy (p
, narrow_noop
, noop_size
);
18460 bytes
-= noop_size
;
18464 /* Use wide noops for the remainder */
18468 while (bytes
>= noop_size
)
18470 memcpy (p
, noop
, noop_size
);
18472 bytes
-= noop_size
;
18476 fragP
->fr_fix
+= fix
;
18479 /* Called from md_do_align. Used to create an alignment
18480 frag in a code section. */
18483 arm_frag_align_code (int n
, int max
)
18487 /* We assume that there will never be a requirement
18488 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
18489 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18494 _("alignments greater than %d bytes not supported in .text sections."),
18495 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
18496 as_fatal ("%s", err_msg
);
18499 p
= frag_var (rs_align_code
,
18500 MAX_MEM_FOR_RS_ALIGN_CODE
,
18502 (relax_substateT
) max
,
18509 /* Perform target specific initialisation of a frag.
18510 Note - despite the name this initialisation is not done when the frag
18511 is created, but only when its type is assigned. A frag can be created
18512 and used a long time before its type is set, so beware of assuming that
18513 this initialisationis performed first. */
18517 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
18519 /* Record whether this frag is in an ARM or a THUMB area. */
18520 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
;
18523 #else /* OBJ_ELF is defined. */
18525 arm_init_frag (fragS
* fragP
, int max_chars
)
18527 /* If the current ARM vs THUMB mode has not already
18528 been recorded into this frag then do so now. */
18529 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
18531 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18533 /* Record a mapping symbol for alignment frags. We will delete this
18534 later if the alignment ends up empty. */
18535 switch (fragP
->fr_type
)
18538 case rs_align_test
:
18540 mapping_state_2 (MAP_DATA
, max_chars
);
18542 case rs_align_code
:
18543 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
18551 /* When we change sections we need to issue a new mapping symbol. */
18554 arm_elf_change_section (void)
18556 segment_info_type
*seginfo
;
18558 /* Link an unlinked unwind index table section to the .text section. */
18559 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
18560 && elf_linked_to_section (now_seg
) == NULL
)
18561 elf_linked_to_section (now_seg
) = text_section
;
18563 if (!SEG_NORMAL (now_seg
))
18566 seginfo
= seg_info (now_seg
);
18567 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
18568 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
18572 arm_elf_section_type (const char * str
, size_t len
)
18574 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
18575 return SHT_ARM_EXIDX
;
18580 /* Code to deal with unwinding tables. */
18582 static void add_unwind_adjustsp (offsetT
);
18584 /* Generate any deferred unwind frame offset. */
18587 flush_pending_unwind (void)
18591 offset
= unwind
.pending_offset
;
18592 unwind
.pending_offset
= 0;
18594 add_unwind_adjustsp (offset
);
18597 /* Add an opcode to this list for this function. Two-byte opcodes should
18598 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
18602 add_unwind_opcode (valueT op
, int length
)
18604 /* Add any deferred stack adjustment. */
18605 if (unwind
.pending_offset
)
18606 flush_pending_unwind ();
18608 unwind
.sp_restored
= 0;
18610 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
18612 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
18613 if (unwind
.opcodes
)
18614 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
18615 unwind
.opcode_alloc
);
18617 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
18622 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
18624 unwind
.opcode_count
++;
18628 /* Add unwind opcodes to adjust the stack pointer. */
18631 add_unwind_adjustsp (offsetT offset
)
18635 if (offset
> 0x200)
18637 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
18642 /* Long form: 0xb2, uleb128. */
18643 /* This might not fit in a word so add the individual bytes,
18644 remembering the list is built in reverse order. */
18645 o
= (valueT
) ((offset
- 0x204) >> 2);
18647 add_unwind_opcode (0, 1);
18649 /* Calculate the uleb128 encoding of the offset. */
18653 bytes
[n
] = o
& 0x7f;
18659 /* Add the insn. */
18661 add_unwind_opcode (bytes
[n
- 1], 1);
18662 add_unwind_opcode (0xb2, 1);
18664 else if (offset
> 0x100)
18666 /* Two short opcodes. */
18667 add_unwind_opcode (0x3f, 1);
18668 op
= (offset
- 0x104) >> 2;
18669 add_unwind_opcode (op
, 1);
18671 else if (offset
> 0)
18673 /* Short opcode. */
18674 op
= (offset
- 4) >> 2;
18675 add_unwind_opcode (op
, 1);
18677 else if (offset
< 0)
18680 while (offset
> 0x100)
18682 add_unwind_opcode (0x7f, 1);
18685 op
= ((offset
- 4) >> 2) | 0x40;
18686 add_unwind_opcode (op
, 1);
18690 /* Finish the list of unwind opcodes for this function. */
18692 finish_unwind_opcodes (void)
18696 if (unwind
.fp_used
)
18698 /* Adjust sp as necessary. */
18699 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
18700 flush_pending_unwind ();
18702 /* After restoring sp from the frame pointer. */
18703 op
= 0x90 | unwind
.fp_reg
;
18704 add_unwind_opcode (op
, 1);
18707 flush_pending_unwind ();
18711 /* Start an exception table entry. If idx is nonzero this is an index table
18715 start_unwind_section (const segT text_seg
, int idx
)
18717 const char * text_name
;
18718 const char * prefix
;
18719 const char * prefix_once
;
18720 const char * group_name
;
18724 size_t sec_name_len
;
18731 prefix
= ELF_STRING_ARM_unwind
;
18732 prefix_once
= ELF_STRING_ARM_unwind_once
;
18733 type
= SHT_ARM_EXIDX
;
18737 prefix
= ELF_STRING_ARM_unwind_info
;
18738 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
18739 type
= SHT_PROGBITS
;
18742 text_name
= segment_name (text_seg
);
18743 if (streq (text_name
, ".text"))
18746 if (strncmp (text_name
, ".gnu.linkonce.t.",
18747 strlen (".gnu.linkonce.t.")) == 0)
18749 prefix
= prefix_once
;
18750 text_name
+= strlen (".gnu.linkonce.t.");
18753 prefix_len
= strlen (prefix
);
18754 text_len
= strlen (text_name
);
18755 sec_name_len
= prefix_len
+ text_len
;
18756 sec_name
= xmalloc (sec_name_len
+ 1);
18757 memcpy (sec_name
, prefix
, prefix_len
);
18758 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
18759 sec_name
[prefix_len
+ text_len
] = '\0';
18765 /* Handle COMDAT group. */
18766 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
18768 group_name
= elf_group_name (text_seg
);
18769 if (group_name
== NULL
)
18771 as_bad (_("Group section `%s' has no group signature"),
18772 segment_name (text_seg
));
18773 ignore_rest_of_line ();
18776 flags
|= SHF_GROUP
;
18780 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
18782 /* Set the section link for index tables. */
18784 elf_linked_to_section (now_seg
) = text_seg
;
18788 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
18789 personality routine data. Returns zero, or the index table value for
18790 and inline entry. */
18793 create_unwind_entry (int have_data
)
18798 /* The current word of data. */
18800 /* The number of bytes left in this word. */
18803 finish_unwind_opcodes ();
18805 /* Remember the current text section. */
18806 unwind
.saved_seg
= now_seg
;
18807 unwind
.saved_subseg
= now_subseg
;
18809 start_unwind_section (now_seg
, 0);
18811 if (unwind
.personality_routine
== NULL
)
18813 if (unwind
.personality_index
== -2)
18816 as_bad (_("handlerdata in cantunwind frame"));
18817 return 1; /* EXIDX_CANTUNWIND. */
18820 /* Use a default personality routine if none is specified. */
18821 if (unwind
.personality_index
== -1)
18823 if (unwind
.opcode_count
> 3)
18824 unwind
.personality_index
= 1;
18826 unwind
.personality_index
= 0;
18829 /* Space for the personality routine entry. */
18830 if (unwind
.personality_index
== 0)
18832 if (unwind
.opcode_count
> 3)
18833 as_bad (_("too many unwind opcodes for personality routine 0"));
18837 /* All the data is inline in the index table. */
18840 while (unwind
.opcode_count
> 0)
18842 unwind
.opcode_count
--;
18843 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
18847 /* Pad with "finish" opcodes. */
18849 data
= (data
<< 8) | 0xb0;
18856 /* We get two opcodes "free" in the first word. */
18857 size
= unwind
.opcode_count
- 2;
18860 /* An extra byte is required for the opcode count. */
18861 size
= unwind
.opcode_count
+ 1;
18863 size
= (size
+ 3) >> 2;
18865 as_bad (_("too many unwind opcodes"));
18867 frag_align (2, 0, 0);
18868 record_alignment (now_seg
, 2);
18869 unwind
.table_entry
= expr_build_dot ();
18871 /* Allocate the table entry. */
18872 ptr
= frag_more ((size
<< 2) + 4);
18873 where
= frag_now_fix () - ((size
<< 2) + 4);
18875 switch (unwind
.personality_index
)
18878 /* ??? Should this be a PLT generating relocation? */
18879 /* Custom personality routine. */
18880 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
18881 BFD_RELOC_ARM_PREL31
);
18886 /* Set the first byte to the number of additional words. */
18891 /* ABI defined personality routines. */
18893 /* Three opcodes bytes are packed into the first word. */
18900 /* The size and first two opcode bytes go in the first word. */
18901 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
18906 /* Should never happen. */
18910 /* Pack the opcodes into words (MSB first), reversing the list at the same
18912 while (unwind
.opcode_count
> 0)
18916 md_number_to_chars (ptr
, data
, 4);
18921 unwind
.opcode_count
--;
18923 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
18926 /* Finish off the last word. */
18929 /* Pad with "finish" opcodes. */
18931 data
= (data
<< 8) | 0xb0;
18933 md_number_to_chars (ptr
, data
, 4);
18938 /* Add an empty descriptor if there is no user-specified data. */
18939 ptr
= frag_more (4);
18940 md_number_to_chars (ptr
, 0, 4);
18947 /* Initialize the DWARF-2 unwind information for this procedure. */
18950 tc_arm_frame_initial_instructions (void)
18952 cfi_add_CFA_def_cfa (REG_SP
, 0);
18954 #endif /* OBJ_ELF */
18956 /* Convert REGNAME to a DWARF-2 register number. */
18959 tc_arm_regname_to_dw2regnum (char *regname
)
18961 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
18971 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
18975 expr
.X_op
= O_secrel
;
18976 expr
.X_add_symbol
= symbol
;
18977 expr
.X_add_number
= 0;
18978 emit_expr (&expr
, size
);
18982 /* MD interface: Symbol and relocation handling. */
18984 /* Return the address within the segment that a PC-relative fixup is
18985 relative to. For ARM, PC-relative fixups applied to instructions
18986 are generally relative to the location of the fixup plus 8 bytes.
18987 Thumb branches are offset by 4, and Thumb loads relative to PC
18988 require special handling. */
18991 md_pcrel_from_section (fixS
* fixP
, segT seg
)
18993 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
18995 /* If this is pc-relative and we are going to emit a relocation
18996 then we just want to put out any pipeline compensation that the linker
18997 will need. Otherwise we want to use the calculated base.
18998 For WinCE we skip the bias for externals as well, since this
18999 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19001 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19002 || (arm_force_relocation (fixP
)
19004 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19010 switch (fixP
->fx_r_type
)
19012 /* PC relative addressing on the Thumb is slightly odd as the
19013 bottom two bits of the PC are forced to zero for the
19014 calculation. This happens *after* application of the
19015 pipeline offset. However, Thumb adrl already adjusts for
19016 this, so we need not do it again. */
19017 case BFD_RELOC_ARM_THUMB_ADD
:
19020 case BFD_RELOC_ARM_THUMB_OFFSET
:
19021 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19022 case BFD_RELOC_ARM_T32_ADD_PC12
:
19023 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19024 return (base
+ 4) & ~3;
19026 /* Thumb branches are simply offset by +4. */
19027 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19028 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19029 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19030 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19031 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19034 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19036 && ARM_IS_FUNC (fixP
->fx_addsy
)
19037 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19038 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19041 /* BLX is like branches above, but forces the low two bits of PC to
19043 case BFD_RELOC_THUMB_PCREL_BLX
:
19045 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19046 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19047 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19048 return (base
+ 4) & ~3;
19050 /* ARM mode branches are offset by +8. However, the Windows CE
19051 loader expects the relocation not to take this into account. */
19052 case BFD_RELOC_ARM_PCREL_BLX
:
19054 && ARM_IS_FUNC (fixP
->fx_addsy
)
19055 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19056 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19059 case BFD_RELOC_ARM_PCREL_CALL
:
19061 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19062 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19063 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19066 case BFD_RELOC_ARM_PCREL_BRANCH
:
19067 case BFD_RELOC_ARM_PCREL_JUMP
:
19068 case BFD_RELOC_ARM_PLT32
:
19070 /* When handling fixups immediately, because we have already
19071 discovered the value of a symbol, or the address of the frag involved
19072 we must account for the offset by +8, as the OS loader will never see the reloc.
19073 see fixup_segment() in write.c
19074 The S_IS_EXTERNAL test handles the case of global symbols.
19075 Those need the calculated base, not just the pipe compensation the linker will need. */
19077 && fixP
->fx_addsy
!= NULL
19078 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19079 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19087 /* ARM mode loads relative to PC are also offset by +8. Unlike
19088 branches, the Windows CE loader *does* expect the relocation
19089 to take this into account. */
19090 case BFD_RELOC_ARM_OFFSET_IMM
:
19091 case BFD_RELOC_ARM_OFFSET_IMM8
:
19092 case BFD_RELOC_ARM_HWLITERAL
:
19093 case BFD_RELOC_ARM_LITERAL
:
19094 case BFD_RELOC_ARM_CP_OFF_IMM
:
19098 /* Other PC-relative relocations are un-offset. */
19104 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19105 Otherwise we have no need to default values of symbols. */
19108 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
19111 if (name
[0] == '_' && name
[1] == 'G'
19112 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
19116 if (symbol_find (name
))
19117 as_bad (_("GOT already in the symbol table"));
19119 GOT_symbol
= symbol_new (name
, undefined_section
,
19120 (valueT
) 0, & zero_address_frag
);
19130 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19131 computed as two separate immediate values, added together. We
19132 already know that this value cannot be computed by just one ARM
19135 static unsigned int
19136 validate_immediate_twopart (unsigned int val
,
19137 unsigned int * highpart
)
19142 for (i
= 0; i
< 32; i
+= 2)
19143 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
19149 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
19151 else if (a
& 0xff0000)
19153 if (a
& 0xff000000)
19155 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
19159 gas_assert (a
& 0xff000000);
19160 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
19163 return (a
& 0xff) | (i
<< 7);
19170 validate_offset_imm (unsigned int val
, int hwse
)
19172 if ((hwse
&& val
> 255) || val
> 4095)
19177 /* Subroutine of md_apply_fix. Do those data_ops which can take a
19178 negative immediate constant by altering the instruction. A bit of
19183 by inverting the second operand, and
19186 by negating the second operand. */
19189 negate_data_op (unsigned long * instruction
,
19190 unsigned long value
)
19193 unsigned long negated
, inverted
;
19195 negated
= encode_arm_immediate (-value
);
19196 inverted
= encode_arm_immediate (~value
);
19198 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
19201 /* First negates. */
19202 case OPCODE_SUB
: /* ADD <-> SUB */
19203 new_inst
= OPCODE_ADD
;
19208 new_inst
= OPCODE_SUB
;
19212 case OPCODE_CMP
: /* CMP <-> CMN */
19213 new_inst
= OPCODE_CMN
;
19218 new_inst
= OPCODE_CMP
;
19222 /* Now Inverted ops. */
19223 case OPCODE_MOV
: /* MOV <-> MVN */
19224 new_inst
= OPCODE_MVN
;
19229 new_inst
= OPCODE_MOV
;
19233 case OPCODE_AND
: /* AND <-> BIC */
19234 new_inst
= OPCODE_BIC
;
19239 new_inst
= OPCODE_AND
;
19243 case OPCODE_ADC
: /* ADC <-> SBC */
19244 new_inst
= OPCODE_SBC
;
19249 new_inst
= OPCODE_ADC
;
19253 /* We cannot do anything. */
19258 if (value
== (unsigned) FAIL
)
19261 *instruction
&= OPCODE_MASK
;
19262 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
19266 /* Like negate_data_op, but for Thumb-2. */
19268 static unsigned int
19269 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
19273 unsigned int negated
, inverted
;
19275 negated
= encode_thumb32_immediate (-value
);
19276 inverted
= encode_thumb32_immediate (~value
);
19278 rd
= (*instruction
>> 8) & 0xf;
19279 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
19282 /* ADD <-> SUB. Includes CMP <-> CMN. */
19283 case T2_OPCODE_SUB
:
19284 new_inst
= T2_OPCODE_ADD
;
19288 case T2_OPCODE_ADD
:
19289 new_inst
= T2_OPCODE_SUB
;
19293 /* ORR <-> ORN. Includes MOV <-> MVN. */
19294 case T2_OPCODE_ORR
:
19295 new_inst
= T2_OPCODE_ORN
;
19299 case T2_OPCODE_ORN
:
19300 new_inst
= T2_OPCODE_ORR
;
19304 /* AND <-> BIC. TST has no inverted equivalent. */
19305 case T2_OPCODE_AND
:
19306 new_inst
= T2_OPCODE_BIC
;
19313 case T2_OPCODE_BIC
:
19314 new_inst
= T2_OPCODE_AND
;
19319 case T2_OPCODE_ADC
:
19320 new_inst
= T2_OPCODE_SBC
;
19324 case T2_OPCODE_SBC
:
19325 new_inst
= T2_OPCODE_ADC
;
19329 /* We cannot do anything. */
19334 if (value
== (unsigned int)FAIL
)
19337 *instruction
&= T2_OPCODE_MASK
;
19338 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
19342 /* Read a 32-bit thumb instruction from buf. */
19343 static unsigned long
19344 get_thumb32_insn (char * buf
)
19346 unsigned long insn
;
19347 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
19348 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19354 /* We usually want to set the low bit on the address of thumb function
19355 symbols. In particular .word foo - . should have the low bit set.
19356 Generic code tries to fold the difference of two symbols to
19357 a constant. Prevent this and force a relocation when the first symbols
19358 is a thumb function. */
19361 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
19363 if (op
== O_subtract
19364 && l
->X_op
== O_symbol
19365 && r
->X_op
== O_symbol
19366 && THUMB_IS_FUNC (l
->X_add_symbol
))
19368 l
->X_op
= O_subtract
;
19369 l
->X_op_symbol
= r
->X_add_symbol
;
19370 l
->X_add_number
-= r
->X_add_number
;
19374 /* Process as normal. */
19379 md_apply_fix (fixS
* fixP
,
19383 offsetT value
= * valP
;
19385 unsigned int newimm
;
19386 unsigned long temp
;
19388 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
19390 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
19392 /* Note whether this will delete the relocation. */
19394 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
19397 /* On a 64-bit host, silently truncate 'value' to 32 bits for
19398 consistency with the behaviour on 32-bit hosts. Remember value
19400 value
&= 0xffffffff;
19401 value
^= 0x80000000;
19402 value
-= 0x80000000;
19405 fixP
->fx_addnumber
= value
;
19407 /* Same treatment for fixP->fx_offset. */
19408 fixP
->fx_offset
&= 0xffffffff;
19409 fixP
->fx_offset
^= 0x80000000;
19410 fixP
->fx_offset
-= 0x80000000;
19412 switch (fixP
->fx_r_type
)
19414 case BFD_RELOC_NONE
:
19415 /* This will need to go in the object file. */
19419 case BFD_RELOC_ARM_IMMEDIATE
:
19420 /* We claim that this fixup has been processed here,
19421 even if in fact we generate an error because we do
19422 not have a reloc for it, so tc_gen_reloc will reject it. */
19426 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19428 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19429 _("undefined symbol %s used as an immediate value"),
19430 S_GET_NAME (fixP
->fx_addsy
));
19435 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19437 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19438 _("symbol %s is in a different section"),
19439 S_GET_NAME (fixP
->fx_addsy
));
19443 newimm
= encode_arm_immediate (value
);
19444 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19446 /* If the instruction will fail, see if we can fix things up by
19447 changing the opcode. */
19448 if (newimm
== (unsigned int) FAIL
19449 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
19451 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19452 _("invalid constant (%lx) after fixup"),
19453 (unsigned long) value
);
19457 newimm
|= (temp
& 0xfffff000);
19458 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19461 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19463 unsigned int highpart
= 0;
19464 unsigned int newinsn
= 0xe1a00000; /* nop. */
19467 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19469 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19470 _("undefined symbol %s used as an immediate value"),
19471 S_GET_NAME (fixP
->fx_addsy
));
19476 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19478 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19479 _("symbol %s is in a different section"),
19480 S_GET_NAME (fixP
->fx_addsy
));
19484 newimm
= encode_arm_immediate (value
);
19485 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19487 /* If the instruction will fail, see if we can fix things up by
19488 changing the opcode. */
19489 if (newimm
== (unsigned int) FAIL
19490 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
19492 /* No ? OK - try using two ADD instructions to generate
19494 newimm
= validate_immediate_twopart (value
, & highpart
);
19496 /* Yes - then make sure that the second instruction is
19498 if (newimm
!= (unsigned int) FAIL
)
19500 /* Still No ? Try using a negated value. */
19501 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
19502 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
19503 /* Otherwise - give up. */
19506 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19507 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
19512 /* Replace the first operand in the 2nd instruction (which
19513 is the PC) with the destination register. We have
19514 already added in the PC in the first instruction and we
19515 do not want to do it again. */
19516 newinsn
&= ~ 0xf0000;
19517 newinsn
|= ((newinsn
& 0x0f000) << 4);
19520 newimm
|= (temp
& 0xfffff000);
19521 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19523 highpart
|= (newinsn
& 0xfffff000);
19524 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
19528 case BFD_RELOC_ARM_OFFSET_IMM
:
19529 if (!fixP
->fx_done
&& seg
->use_rela_p
)
19532 case BFD_RELOC_ARM_LITERAL
:
19538 if (validate_offset_imm (value
, 0) == FAIL
)
19540 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
19541 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19542 _("invalid literal constant: pool needs to be closer"));
19544 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19545 _("bad immediate value for offset (%ld)"),
19550 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19551 newval
&= 0xff7ff000;
19552 newval
|= value
| (sign
? INDEX_UP
: 0);
19553 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19556 case BFD_RELOC_ARM_OFFSET_IMM8
:
19557 case BFD_RELOC_ARM_HWLITERAL
:
19563 if (validate_offset_imm (value
, 1) == FAIL
)
19565 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
19566 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19567 _("invalid literal constant: pool needs to be closer"));
19569 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
19574 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19575 newval
&= 0xff7ff0f0;
19576 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
19577 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19580 case BFD_RELOC_ARM_T32_OFFSET_U8
:
19581 if (value
< 0 || value
> 1020 || value
% 4 != 0)
19582 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19583 _("bad immediate value for offset (%ld)"), (long) value
);
19586 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
19588 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
19591 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19592 /* This is a complicated relocation used for all varieties of Thumb32
19593 load/store instruction with immediate offset:
19595 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
19596 *4, optional writeback(W)
19597 (doubleword load/store)
19599 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
19600 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
19601 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
19602 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
19603 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
19605 Uppercase letters indicate bits that are already encoded at
19606 this point. Lowercase letters are our problem. For the
19607 second block of instructions, the secondary opcode nybble
19608 (bits 8..11) is present, and bit 23 is zero, even if this is
19609 a PC-relative operation. */
19610 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19612 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
19614 if ((newval
& 0xf0000000) == 0xe0000000)
19616 /* Doubleword load/store: 8-bit offset, scaled by 4. */
19618 newval
|= (1 << 23);
19621 if (value
% 4 != 0)
19623 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19624 _("offset not a multiple of 4"));
19630 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19631 _("offset out of range"));
19636 else if ((newval
& 0x000f0000) == 0x000f0000)
19638 /* PC-relative, 12-bit offset. */
19640 newval
|= (1 << 23);
19645 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19646 _("offset out of range"));
19651 else if ((newval
& 0x00000100) == 0x00000100)
19653 /* Writeback: 8-bit, +/- offset. */
19655 newval
|= (1 << 9);
19660 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19661 _("offset out of range"));
19666 else if ((newval
& 0x00000f00) == 0x00000e00)
19668 /* T-instruction: positive 8-bit offset. */
19669 if (value
< 0 || value
> 0xff)
19671 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19672 _("offset out of range"));
19680 /* Positive 12-bit or negative 8-bit offset. */
19684 newval
|= (1 << 23);
19694 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19695 _("offset out of range"));
19702 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
19703 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
19706 case BFD_RELOC_ARM_SHIFT_IMM
:
19707 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19708 if (((unsigned long) value
) > 32
19710 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
19712 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19713 _("shift expression is too large"));
19718 /* Shifts of zero must be done as lsl. */
19720 else if (value
== 32)
19722 newval
&= 0xfffff07f;
19723 newval
|= (value
& 0x1f) << 7;
19724 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19727 case BFD_RELOC_ARM_T32_IMMEDIATE
:
19728 case BFD_RELOC_ARM_T32_ADD_IMM
:
19729 case BFD_RELOC_ARM_T32_IMM12
:
19730 case BFD_RELOC_ARM_T32_ADD_PC12
:
19731 /* We claim that this fixup has been processed here,
19732 even if in fact we generate an error because we do
19733 not have a reloc for it, so tc_gen_reloc will reject it. */
19737 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19739 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19740 _("undefined symbol %s used as an immediate value"),
19741 S_GET_NAME (fixP
->fx_addsy
));
19745 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19747 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
19750 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
19751 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
19753 newimm
= encode_thumb32_immediate (value
);
19754 if (newimm
== (unsigned int) FAIL
)
19755 newimm
= thumb32_negate_data_op (&newval
, value
);
19757 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
19758 && newimm
== (unsigned int) FAIL
)
19760 /* Turn add/sum into addw/subw. */
19761 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
19762 newval
= (newval
& 0xfeffffff) | 0x02000000;
19764 /* 12 bit immediate for addw/subw. */
19768 newval
^= 0x00a00000;
19771 newimm
= (unsigned int) FAIL
;
19776 if (newimm
== (unsigned int)FAIL
)
19778 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19779 _("invalid constant (%lx) after fixup"),
19780 (unsigned long) value
);
19784 newval
|= (newimm
& 0x800) << 15;
19785 newval
|= (newimm
& 0x700) << 4;
19786 newval
|= (newimm
& 0x0ff);
19788 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
19789 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
19792 case BFD_RELOC_ARM_SMC
:
19793 if (((unsigned long) value
) > 0xffff)
19794 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19795 _("invalid smc expression"));
19796 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19797 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
19798 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19801 case BFD_RELOC_ARM_SWI
:
19802 if (fixP
->tc_fix_data
!= 0)
19804 if (((unsigned long) value
) > 0xff)
19805 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19806 _("invalid swi expression"));
19807 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19809 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19813 if (((unsigned long) value
) > 0x00ffffff)
19814 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19815 _("invalid swi expression"));
19816 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19818 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19822 case BFD_RELOC_ARM_MULTI
:
19823 if (((unsigned long) value
) > 0xffff)
19824 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19825 _("invalid expression in load/store multiple"));
19826 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
19827 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19831 case BFD_RELOC_ARM_PCREL_CALL
:
19833 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
19835 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19836 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19837 && THUMB_IS_FUNC (fixP
->fx_addsy
))
19838 /* Flip the bl to blx. This is a simple flip
19839 bit here because we generate PCREL_CALL for
19840 unconditional bls. */
19842 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19843 newval
= newval
| 0x10000000;
19844 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19850 goto arm_branch_common
;
19852 case BFD_RELOC_ARM_PCREL_JUMP
:
19853 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
19855 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19856 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19857 && THUMB_IS_FUNC (fixP
->fx_addsy
))
19859 /* This would map to a bl<cond>, b<cond>,
19860 b<always> to a Thumb function. We
19861 need to force a relocation for this particular
19863 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19867 case BFD_RELOC_ARM_PLT32
:
19869 case BFD_RELOC_ARM_PCREL_BRANCH
:
19871 goto arm_branch_common
;
19873 case BFD_RELOC_ARM_PCREL_BLX
:
19876 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
19878 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19879 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19880 && ARM_IS_FUNC (fixP
->fx_addsy
))
19882 /* Flip the blx to a bl and warn. */
19883 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
19884 newval
= 0xeb000000;
19885 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
19886 _("blx to '%s' an ARM ISA state function changed to bl"),
19888 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19894 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
19895 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
19899 /* We are going to store value (shifted right by two) in the
19900 instruction, in a 24 bit, signed field. Bits 26 through 32 either
19901 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
19902 also be be clear. */
19904 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19905 _("misaligned branch destination"));
19906 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
19907 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
19908 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19909 _("branch out of range"));
19911 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19913 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19914 newval
|= (value
>> 2) & 0x00ffffff;
19915 /* Set the H bit on BLX instructions. */
19919 newval
|= 0x01000000;
19921 newval
&= ~0x01000000;
19923 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19927 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
19928 /* CBZ can only branch forward. */
19930 /* Attempts to use CBZ to branch to the next instruction
19931 (which, strictly speaking, are prohibited) will be turned into
19934 FIXME: It may be better to remove the instruction completely and
19935 perform relaxation. */
19938 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19939 newval
= 0xbf00; /* NOP encoding T1 */
19940 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19945 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19946 _("branch out of range"));
19948 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19950 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19951 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
19952 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19957 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
19958 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
19959 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19960 _("branch out of range"));
19962 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19964 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19965 newval
|= (value
& 0x1ff) >> 1;
19966 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19970 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
19971 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
19972 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19973 _("branch out of range"));
19975 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19977 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19978 newval
|= (value
& 0xfff) >> 1;
19979 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19983 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19985 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19986 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19987 && S_IS_DEFINED (fixP
->fx_addsy
)
19988 && ARM_IS_FUNC (fixP
->fx_addsy
)
19989 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19991 /* Force a relocation for a branch 20 bits wide. */
19994 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
19995 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19996 _("conditional branch out of range"));
19998 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20001 addressT S
, J1
, J2
, lo
, hi
;
20003 S
= (value
& 0x00100000) >> 20;
20004 J2
= (value
& 0x00080000) >> 19;
20005 J1
= (value
& 0x00040000) >> 18;
20006 hi
= (value
& 0x0003f000) >> 12;
20007 lo
= (value
& 0x00000ffe) >> 1;
20009 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20010 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20011 newval
|= (S
<< 10) | hi
;
20012 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20013 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20014 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20018 case BFD_RELOC_THUMB_PCREL_BLX
:
20020 /* If there is a blx from a thumb state function to
20021 another thumb function flip this to a bl and warn
20025 && S_IS_DEFINED (fixP
->fx_addsy
)
20026 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20027 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20028 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20030 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20031 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20032 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20034 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20035 newval
= newval
| 0x1000;
20036 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20037 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20042 goto thumb_bl_common
;
20044 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20046 /* A bl from Thumb state ISA to an internal ARM state function
20047 is converted to a blx. */
20049 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20050 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20051 && S_IS_DEFINED (fixP
->fx_addsy
)
20052 && ARM_IS_FUNC (fixP
->fx_addsy
)
20053 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20055 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20056 newval
= newval
& ~0x1000;
20057 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20058 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20065 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20066 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20067 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20070 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
20071 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20072 _("branch out of range"));
20074 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20075 /* For a BLX instruction, make sure that the relocation is rounded up
20076 to a word boundary. This follows the semantics of the instruction
20077 which specifies that bit 1 of the target address will come from bit
20078 1 of the base address. */
20079 value
= (value
+ 1) & ~ 1;
20081 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20085 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20086 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20087 newval
|= (value
& 0x7fffff) >> 12;
20088 newval2
|= (value
& 0xfff) >> 1;
20089 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20090 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20094 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20095 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
20096 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20097 _("branch out of range"));
20099 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20102 addressT S
, I1
, I2
, lo
, hi
;
20104 S
= (value
& 0x01000000) >> 24;
20105 I1
= (value
& 0x00800000) >> 23;
20106 I2
= (value
& 0x00400000) >> 22;
20107 hi
= (value
& 0x003ff000) >> 12;
20108 lo
= (value
& 0x00000ffe) >> 1;
20113 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20114 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20115 newval
|= (S
<< 10) | hi
;
20116 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
20117 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20118 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20123 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20124 md_number_to_chars (buf
, value
, 1);
20128 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20129 md_number_to_chars (buf
, value
, 2);
20133 case BFD_RELOC_ARM_TLS_GD32
:
20134 case BFD_RELOC_ARM_TLS_LE32
:
20135 case BFD_RELOC_ARM_TLS_IE32
:
20136 case BFD_RELOC_ARM_TLS_LDM32
:
20137 case BFD_RELOC_ARM_TLS_LDO32
:
20138 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
20141 case BFD_RELOC_ARM_GOT32
:
20142 case BFD_RELOC_ARM_GOTOFF
:
20143 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20144 md_number_to_chars (buf
, 0, 4);
20147 case BFD_RELOC_ARM_TARGET2
:
20148 /* TARGET2 is not partial-inplace, so we need to write the
20149 addend here for REL targets, because it won't be written out
20150 during reloc processing later. */
20151 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20152 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
20156 case BFD_RELOC_RVA
:
20158 case BFD_RELOC_ARM_TARGET1
:
20159 case BFD_RELOC_ARM_ROSEGREL32
:
20160 case BFD_RELOC_ARM_SBREL32
:
20161 case BFD_RELOC_32_PCREL
:
20163 case BFD_RELOC_32_SECREL
:
20165 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20167 /* For WinCE we only do this for pcrel fixups. */
20168 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
20170 md_number_to_chars (buf
, value
, 4);
20174 case BFD_RELOC_ARM_PREL31
:
20175 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20177 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
20178 if ((value
^ (value
>> 1)) & 0x40000000)
20180 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20181 _("rel31 relocation overflow"));
20183 newval
|= value
& 0x7fffffff;
20184 md_number_to_chars (buf
, newval
, 4);
20189 case BFD_RELOC_ARM_CP_OFF_IMM
:
20190 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20191 if (value
< -1023 || value
> 1023 || (value
& 3))
20192 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20193 _("co-processor offset out of range"));
20198 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20199 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20200 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20202 newval
= get_thumb32_insn (buf
);
20203 newval
&= 0xff7fff00;
20204 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
20205 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20206 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20207 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20209 put_thumb32_insn (buf
, newval
);
20212 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
20213 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
20214 if (value
< -255 || value
> 255)
20215 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20216 _("co-processor offset out of range"));
20218 goto cp_off_common
;
20220 case BFD_RELOC_ARM_THUMB_OFFSET
:
20221 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20222 /* Exactly what ranges, and where the offset is inserted depends
20223 on the type of instruction, we can establish this from the
20225 switch (newval
>> 12)
20227 case 4: /* PC load. */
20228 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
20229 forced to zero for these loads; md_pcrel_from has already
20230 compensated for this. */
20232 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20233 _("invalid offset, target not word aligned (0x%08lX)"),
20234 (((unsigned long) fixP
->fx_frag
->fr_address
20235 + (unsigned long) fixP
->fx_where
) & ~3)
20236 + (unsigned long) value
);
20238 if (value
& ~0x3fc)
20239 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20240 _("invalid offset, value too big (0x%08lX)"),
20243 newval
|= value
>> 2;
20246 case 9: /* SP load/store. */
20247 if (value
& ~0x3fc)
20248 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20249 _("invalid offset, value too big (0x%08lX)"),
20251 newval
|= value
>> 2;
20254 case 6: /* Word load/store. */
20256 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20257 _("invalid offset, value too big (0x%08lX)"),
20259 newval
|= value
<< 4; /* 6 - 2. */
20262 case 7: /* Byte load/store. */
20264 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20265 _("invalid offset, value too big (0x%08lX)"),
20267 newval
|= value
<< 6;
20270 case 8: /* Halfword load/store. */
20272 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20273 _("invalid offset, value too big (0x%08lX)"),
20275 newval
|= value
<< 5; /* 6 - 1. */
20279 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20280 "Unable to process relocation for thumb opcode: %lx",
20281 (unsigned long) newval
);
20284 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20287 case BFD_RELOC_ARM_THUMB_ADD
:
20288 /* This is a complicated relocation, since we use it for all of
20289 the following immediate relocations:
20293 9bit ADD/SUB SP word-aligned
20294 10bit ADD PC/SP word-aligned
20296 The type of instruction being processed is encoded in the
20303 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20305 int rd
= (newval
>> 4) & 0xf;
20306 int rs
= newval
& 0xf;
20307 int subtract
= !!(newval
& 0x8000);
20309 /* Check for HI regs, only very restricted cases allowed:
20310 Adjusting SP, and using PC or SP to get an address. */
20311 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
20312 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
20313 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20314 _("invalid Hi register with immediate"));
20316 /* If value is negative, choose the opposite instruction. */
20320 subtract
= !subtract
;
20322 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20323 _("immediate value out of range"));
20328 if (value
& ~0x1fc)
20329 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20330 _("invalid immediate for stack address calculation"));
20331 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
20332 newval
|= value
>> 2;
20334 else if (rs
== REG_PC
|| rs
== REG_SP
)
20336 if (subtract
|| value
& ~0x3fc)
20337 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20338 _("invalid immediate for address calculation (value = 0x%08lX)"),
20339 (unsigned long) value
);
20340 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
20342 newval
|= value
>> 2;
20347 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20348 _("immediate value out of range"));
20349 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
20350 newval
|= (rd
<< 8) | value
;
20355 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20356 _("immediate value out of range"));
20357 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
20358 newval
|= rd
| (rs
<< 3) | (value
<< 6);
20361 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20364 case BFD_RELOC_ARM_THUMB_IMM
:
20365 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20366 if (value
< 0 || value
> 255)
20367 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20368 _("invalid immediate: %ld is out of range"),
20371 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20374 case BFD_RELOC_ARM_THUMB_SHIFT
:
20375 /* 5bit shift value (0..32). LSL cannot take 32. */
20376 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
20377 temp
= newval
& 0xf800;
20378 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
20379 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20380 _("invalid shift value: %ld"), (long) value
);
20381 /* Shifts of zero must be encoded as LSL. */
20383 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
20384 /* Shifts of 32 are encoded as zero. */
20385 else if (value
== 32)
20387 newval
|= value
<< 6;
20388 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20391 case BFD_RELOC_VTABLE_INHERIT
:
20392 case BFD_RELOC_VTABLE_ENTRY
:
20396 case BFD_RELOC_ARM_MOVW
:
20397 case BFD_RELOC_ARM_MOVT
:
20398 case BFD_RELOC_ARM_THUMB_MOVW
:
20399 case BFD_RELOC_ARM_THUMB_MOVT
:
20400 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20402 /* REL format relocations are limited to a 16-bit addend. */
20403 if (!fixP
->fx_done
)
20405 if (value
< -0x8000 || value
> 0x7fff)
20406 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20407 _("offset out of range"));
20409 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
20410 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20415 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20416 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20418 newval
= get_thumb32_insn (buf
);
20419 newval
&= 0xfbf08f00;
20420 newval
|= (value
& 0xf000) << 4;
20421 newval
|= (value
& 0x0800) << 15;
20422 newval
|= (value
& 0x0700) << 4;
20423 newval
|= (value
& 0x00ff);
20424 put_thumb32_insn (buf
, newval
);
20428 newval
= md_chars_to_number (buf
, 4);
20429 newval
&= 0xfff0f000;
20430 newval
|= value
& 0x0fff;
20431 newval
|= (value
& 0xf000) << 4;
20432 md_number_to_chars (buf
, newval
, 4);
20437 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20438 case BFD_RELOC_ARM_ALU_PC_G0
:
20439 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20440 case BFD_RELOC_ARM_ALU_PC_G1
:
20441 case BFD_RELOC_ARM_ALU_PC_G2
:
20442 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20443 case BFD_RELOC_ARM_ALU_SB_G0
:
20444 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20445 case BFD_RELOC_ARM_ALU_SB_G1
:
20446 case BFD_RELOC_ARM_ALU_SB_G2
:
20447 gas_assert (!fixP
->fx_done
);
20448 if (!seg
->use_rela_p
)
20451 bfd_vma encoded_addend
;
20452 bfd_vma addend_abs
= abs (value
);
20454 /* Check that the absolute value of the addend can be
20455 expressed as an 8-bit constant plus a rotation. */
20456 encoded_addend
= encode_arm_immediate (addend_abs
);
20457 if (encoded_addend
== (unsigned int) FAIL
)
20458 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20459 _("the offset 0x%08lX is not representable"),
20460 (unsigned long) addend_abs
);
20462 /* Extract the instruction. */
20463 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20465 /* If the addend is positive, use an ADD instruction.
20466 Otherwise use a SUB. Take care not to destroy the S bit. */
20467 insn
&= 0xff1fffff;
20473 /* Place the encoded addend into the first 12 bits of the
20475 insn
&= 0xfffff000;
20476 insn
|= encoded_addend
;
20478 /* Update the instruction. */
20479 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20483 case BFD_RELOC_ARM_LDR_PC_G0
:
20484 case BFD_RELOC_ARM_LDR_PC_G1
:
20485 case BFD_RELOC_ARM_LDR_PC_G2
:
20486 case BFD_RELOC_ARM_LDR_SB_G0
:
20487 case BFD_RELOC_ARM_LDR_SB_G1
:
20488 case BFD_RELOC_ARM_LDR_SB_G2
:
20489 gas_assert (!fixP
->fx_done
);
20490 if (!seg
->use_rela_p
)
20493 bfd_vma addend_abs
= abs (value
);
20495 /* Check that the absolute value of the addend can be
20496 encoded in 12 bits. */
20497 if (addend_abs
>= 0x1000)
20498 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20499 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
20500 (unsigned long) addend_abs
);
20502 /* Extract the instruction. */
20503 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20505 /* If the addend is negative, clear bit 23 of the instruction.
20506 Otherwise set it. */
20508 insn
&= ~(1 << 23);
20512 /* Place the absolute value of the addend into the first 12 bits
20513 of the instruction. */
20514 insn
&= 0xfffff000;
20515 insn
|= addend_abs
;
20517 /* Update the instruction. */
20518 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20522 case BFD_RELOC_ARM_LDRS_PC_G0
:
20523 case BFD_RELOC_ARM_LDRS_PC_G1
:
20524 case BFD_RELOC_ARM_LDRS_PC_G2
:
20525 case BFD_RELOC_ARM_LDRS_SB_G0
:
20526 case BFD_RELOC_ARM_LDRS_SB_G1
:
20527 case BFD_RELOC_ARM_LDRS_SB_G2
:
20528 gas_assert (!fixP
->fx_done
);
20529 if (!seg
->use_rela_p
)
20532 bfd_vma addend_abs
= abs (value
);
20534 /* Check that the absolute value of the addend can be
20535 encoded in 8 bits. */
20536 if (addend_abs
>= 0x100)
20537 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20538 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
20539 (unsigned long) addend_abs
);
20541 /* Extract the instruction. */
20542 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20544 /* If the addend is negative, clear bit 23 of the instruction.
20545 Otherwise set it. */
20547 insn
&= ~(1 << 23);
20551 /* Place the first four bits of the absolute value of the addend
20552 into the first 4 bits of the instruction, and the remaining
20553 four into bits 8 .. 11. */
20554 insn
&= 0xfffff0f0;
20555 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
20557 /* Update the instruction. */
20558 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20562 case BFD_RELOC_ARM_LDC_PC_G0
:
20563 case BFD_RELOC_ARM_LDC_PC_G1
:
20564 case BFD_RELOC_ARM_LDC_PC_G2
:
20565 case BFD_RELOC_ARM_LDC_SB_G0
:
20566 case BFD_RELOC_ARM_LDC_SB_G1
:
20567 case BFD_RELOC_ARM_LDC_SB_G2
:
20568 gas_assert (!fixP
->fx_done
);
20569 if (!seg
->use_rela_p
)
20572 bfd_vma addend_abs
= abs (value
);
20574 /* Check that the absolute value of the addend is a multiple of
20575 four and, when divided by four, fits in 8 bits. */
20576 if (addend_abs
& 0x3)
20577 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20578 _("bad offset 0x%08lX (must be word-aligned)"),
20579 (unsigned long) addend_abs
);
20581 if ((addend_abs
>> 2) > 0xff)
20582 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20583 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
20584 (unsigned long) addend_abs
);
20586 /* Extract the instruction. */
20587 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20589 /* If the addend is negative, clear bit 23 of the instruction.
20590 Otherwise set it. */
20592 insn
&= ~(1 << 23);
20596 /* Place the addend (divided by four) into the first eight
20597 bits of the instruction. */
20598 insn
&= 0xfffffff0;
20599 insn
|= addend_abs
>> 2;
20601 /* Update the instruction. */
20602 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20606 case BFD_RELOC_ARM_V4BX
:
20607 /* This will need to go in the object file. */
20611 case BFD_RELOC_UNUSED
:
20613 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20614 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
20618 /* Translate internal representation of relocation info to BFD target
20622 tc_gen_reloc (asection
*section
, fixS
*fixp
)
20625 bfd_reloc_code_real_type code
;
20627 reloc
= xmalloc (sizeof (arelent
));
20629 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
20630 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
20631 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
20633 if (fixp
->fx_pcrel
)
20635 if (section
->use_rela_p
)
20636 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
20638 fixp
->fx_offset
= reloc
->address
;
20640 reloc
->addend
= fixp
->fx_offset
;
20642 switch (fixp
->fx_r_type
)
20645 if (fixp
->fx_pcrel
)
20647 code
= BFD_RELOC_8_PCREL
;
20652 if (fixp
->fx_pcrel
)
20654 code
= BFD_RELOC_16_PCREL
;
20659 if (fixp
->fx_pcrel
)
20661 code
= BFD_RELOC_32_PCREL
;
20665 case BFD_RELOC_ARM_MOVW
:
20666 if (fixp
->fx_pcrel
)
20668 code
= BFD_RELOC_ARM_MOVW_PCREL
;
20672 case BFD_RELOC_ARM_MOVT
:
20673 if (fixp
->fx_pcrel
)
20675 code
= BFD_RELOC_ARM_MOVT_PCREL
;
20679 case BFD_RELOC_ARM_THUMB_MOVW
:
20680 if (fixp
->fx_pcrel
)
20682 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
20686 case BFD_RELOC_ARM_THUMB_MOVT
:
20687 if (fixp
->fx_pcrel
)
20689 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
20693 case BFD_RELOC_NONE
:
20694 case BFD_RELOC_ARM_PCREL_BRANCH
:
20695 case BFD_RELOC_ARM_PCREL_BLX
:
20696 case BFD_RELOC_RVA
:
20697 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
20698 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
20699 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
20700 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20701 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20702 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20703 case BFD_RELOC_VTABLE_ENTRY
:
20704 case BFD_RELOC_VTABLE_INHERIT
:
20706 case BFD_RELOC_32_SECREL
:
20708 code
= fixp
->fx_r_type
;
20711 case BFD_RELOC_THUMB_PCREL_BLX
:
20713 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20714 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20717 code
= BFD_RELOC_THUMB_PCREL_BLX
;
20720 case BFD_RELOC_ARM_LITERAL
:
20721 case BFD_RELOC_ARM_HWLITERAL
:
20722 /* If this is called then the a literal has
20723 been referenced across a section boundary. */
20724 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20725 _("literal referenced across section boundary"));
20729 case BFD_RELOC_ARM_GOT32
:
20730 case BFD_RELOC_ARM_GOTOFF
:
20731 case BFD_RELOC_ARM_PLT32
:
20732 case BFD_RELOC_ARM_TARGET1
:
20733 case BFD_RELOC_ARM_ROSEGREL32
:
20734 case BFD_RELOC_ARM_SBREL32
:
20735 case BFD_RELOC_ARM_PREL31
:
20736 case BFD_RELOC_ARM_TARGET2
:
20737 case BFD_RELOC_ARM_TLS_LE32
:
20738 case BFD_RELOC_ARM_TLS_LDO32
:
20739 case BFD_RELOC_ARM_PCREL_CALL
:
20740 case BFD_RELOC_ARM_PCREL_JUMP
:
20741 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20742 case BFD_RELOC_ARM_ALU_PC_G0
:
20743 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20744 case BFD_RELOC_ARM_ALU_PC_G1
:
20745 case BFD_RELOC_ARM_ALU_PC_G2
:
20746 case BFD_RELOC_ARM_LDR_PC_G0
:
20747 case BFD_RELOC_ARM_LDR_PC_G1
:
20748 case BFD_RELOC_ARM_LDR_PC_G2
:
20749 case BFD_RELOC_ARM_LDRS_PC_G0
:
20750 case BFD_RELOC_ARM_LDRS_PC_G1
:
20751 case BFD_RELOC_ARM_LDRS_PC_G2
:
20752 case BFD_RELOC_ARM_LDC_PC_G0
:
20753 case BFD_RELOC_ARM_LDC_PC_G1
:
20754 case BFD_RELOC_ARM_LDC_PC_G2
:
20755 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20756 case BFD_RELOC_ARM_ALU_SB_G0
:
20757 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20758 case BFD_RELOC_ARM_ALU_SB_G1
:
20759 case BFD_RELOC_ARM_ALU_SB_G2
:
20760 case BFD_RELOC_ARM_LDR_SB_G0
:
20761 case BFD_RELOC_ARM_LDR_SB_G1
:
20762 case BFD_RELOC_ARM_LDR_SB_G2
:
20763 case BFD_RELOC_ARM_LDRS_SB_G0
:
20764 case BFD_RELOC_ARM_LDRS_SB_G1
:
20765 case BFD_RELOC_ARM_LDRS_SB_G2
:
20766 case BFD_RELOC_ARM_LDC_SB_G0
:
20767 case BFD_RELOC_ARM_LDC_SB_G1
:
20768 case BFD_RELOC_ARM_LDC_SB_G2
:
20769 case BFD_RELOC_ARM_V4BX
:
20770 code
= fixp
->fx_r_type
;
20773 case BFD_RELOC_ARM_TLS_GD32
:
20774 case BFD_RELOC_ARM_TLS_IE32
:
20775 case BFD_RELOC_ARM_TLS_LDM32
:
20776 /* BFD will include the symbol's address in the addend.
20777 But we don't want that, so subtract it out again here. */
20778 if (!S_IS_COMMON (fixp
->fx_addsy
))
20779 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
20780 code
= fixp
->fx_r_type
;
20784 case BFD_RELOC_ARM_IMMEDIATE
:
20785 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20786 _("internal relocation (type: IMMEDIATE) not fixed up"));
20789 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
20790 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20791 _("ADRL used for a symbol not defined in the same file"));
20794 case BFD_RELOC_ARM_OFFSET_IMM
:
20795 if (section
->use_rela_p
)
20797 code
= fixp
->fx_r_type
;
20801 if (fixp
->fx_addsy
!= NULL
20802 && !S_IS_DEFINED (fixp
->fx_addsy
)
20803 && S_IS_LOCAL (fixp
->fx_addsy
))
20805 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20806 _("undefined local label `%s'"),
20807 S_GET_NAME (fixp
->fx_addsy
));
20811 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20812 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
20819 switch (fixp
->fx_r_type
)
20821 case BFD_RELOC_NONE
: type
= "NONE"; break;
20822 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
20823 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
20824 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
20825 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
20826 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
20827 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
20828 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
20829 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
20830 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
20831 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
20832 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
20833 default: type
= _("<unknown>"); break;
20835 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20836 _("cannot represent %s relocation in this object file format"),
20843 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
20845 && fixp
->fx_addsy
== GOT_symbol
)
20847 code
= BFD_RELOC_ARM_GOTPC
;
20848 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
20852 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
20854 if (reloc
->howto
== NULL
)
20856 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
20857 _("cannot represent %s relocation in this object file format"),
20858 bfd_get_reloc_code_name (code
));
20862 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
20863 vtable entry to be used in the relocation's section offset. */
20864 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
20865 reloc
->address
= fixp
->fx_offset
;
20870 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
20873 cons_fix_new_arm (fragS
* frag
,
20878 bfd_reloc_code_real_type type
;
20882 FIXME: @@ Should look at CPU word size. */
20886 type
= BFD_RELOC_8
;
20889 type
= BFD_RELOC_16
;
20893 type
= BFD_RELOC_32
;
20896 type
= BFD_RELOC_64
;
20901 if (exp
->X_op
== O_secrel
)
20903 exp
->X_op
= O_symbol
;
20904 type
= BFD_RELOC_32_SECREL
;
20908 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
20911 #if defined (OBJ_COFF)
20913 arm_validate_fix (fixS
* fixP
)
20915 /* If the destination of the branch is a defined symbol which does not have
20916 the THUMB_FUNC attribute, then we must be calling a function which has
20917 the (interfacearm) attribute. We look for the Thumb entry point to that
20918 function and change the branch to refer to that function instead. */
20919 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
20920 && fixP
->fx_addsy
!= NULL
20921 && S_IS_DEFINED (fixP
->fx_addsy
)
20922 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
20924 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
20931 arm_force_relocation (struct fix
* fixp
)
20933 #if defined (OBJ_COFF) && defined (TE_PE)
20934 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
20938 /* In case we have a call or a branch to a function in ARM ISA mode from
20939 a thumb function or vice-versa force the relocation. These relocations
20940 are cleared off for some cores that might have blx and simple transformations
20944 switch (fixp
->fx_r_type
)
20946 case BFD_RELOC_ARM_PCREL_JUMP
:
20947 case BFD_RELOC_ARM_PCREL_CALL
:
20948 case BFD_RELOC_THUMB_PCREL_BLX
:
20949 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
20953 case BFD_RELOC_ARM_PCREL_BLX
:
20954 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20955 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20956 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20957 if (ARM_IS_FUNC (fixp
->fx_addsy
))
20966 /* Resolve these relocations even if the symbol is extern or weak. */
20967 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
20968 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
20969 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
20970 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
20971 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20972 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
20973 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
20976 /* Always leave these relocations for the linker. */
20977 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
20978 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
20979 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
20982 /* Always generate relocations against function symbols. */
20983 if (fixp
->fx_r_type
== BFD_RELOC_32
20985 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
20988 return generic_force_reloc (fixp
);
20991 #if defined (OBJ_ELF) || defined (OBJ_COFF)
20992 /* Relocations against function names must be left unadjusted,
20993 so that the linker can use this information to generate interworking
20994 stubs. The MIPS version of this function
20995 also prevents relocations that are mips-16 specific, but I do not
20996 know why it does this.
20999 There is one other problem that ought to be addressed here, but
21000 which currently is not: Taking the address of a label (rather
21001 than a function) and then later jumping to that address. Such
21002 addresses also ought to have their bottom bit set (assuming that
21003 they reside in Thumb code), but at the moment they will not. */
21006 arm_fix_adjustable (fixS
* fixP
)
21008 if (fixP
->fx_addsy
== NULL
)
21011 /* Preserve relocations against symbols with function type. */
21012 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21015 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21016 && fixP
->fx_subsy
== NULL
)
21019 /* We need the symbol name for the VTABLE entries. */
21020 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21021 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21024 /* Don't allow symbols to be discarded on GOT related relocs. */
21025 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21026 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21027 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21028 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21029 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21030 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21031 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21032 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21033 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21036 /* Similarly for group relocations. */
21037 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21038 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21039 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21042 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21043 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21044 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21045 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21046 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21047 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21048 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21049 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21050 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
21055 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21060 elf32_arm_target_format (void)
21063 return (target_big_endian
21064 ? "elf32-bigarm-symbian"
21065 : "elf32-littlearm-symbian");
21066 #elif defined (TE_VXWORKS)
21067 return (target_big_endian
21068 ? "elf32-bigarm-vxworks"
21069 : "elf32-littlearm-vxworks");
21071 if (target_big_endian
)
21072 return "elf32-bigarm";
21074 return "elf32-littlearm";
21079 armelf_frob_symbol (symbolS
* symp
,
21082 elf_frob_symbol (symp
, puntp
);
21086 /* MD interface: Finalization. */
21091 literal_pool
* pool
;
21093 /* Ensure that all the IT blocks are properly closed. */
21094 check_it_blocks_finished ();
21096 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
21098 /* Put it at the end of the relevant section. */
21099 subseg_set (pool
->section
, pool
->sub_section
);
21101 arm_elf_change_section ();
21108 /* Remove any excess mapping symbols generated for alignment frags in
21109 SEC. We may have created a mapping symbol before a zero byte
21110 alignment; remove it if there's a mapping symbol after the
21113 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
21114 void *dummy ATTRIBUTE_UNUSED
)
21116 segment_info_type
*seginfo
= seg_info (sec
);
21119 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
21122 for (fragp
= seginfo
->frchainP
->frch_root
;
21124 fragp
= fragp
->fr_next
)
21126 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
21127 fragS
*next
= fragp
->fr_next
;
21129 /* Variable-sized frags have been converted to fixed size by
21130 this point. But if this was variable-sized to start with,
21131 there will be a fixed-size frag after it. So don't handle
21133 if (sym
== NULL
|| next
== NULL
)
21136 if (S_GET_VALUE (sym
) < next
->fr_address
)
21137 /* Not at the end of this frag. */
21139 know (S_GET_VALUE (sym
) == next
->fr_address
);
21143 if (next
->tc_frag_data
.first_map
!= NULL
)
21145 /* Next frag starts with a mapping symbol. Discard this
21147 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21151 if (next
->fr_next
== NULL
)
21153 /* This mapping symbol is at the end of the section. Discard
21155 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
21156 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21160 /* As long as we have empty frags without any mapping symbols,
21162 /* If the next frag is non-empty and does not start with a
21163 mapping symbol, then this mapping symbol is required. */
21164 if (next
->fr_address
!= next
->fr_next
->fr_address
)
21167 next
= next
->fr_next
;
21169 while (next
!= NULL
);
21174 /* Adjust the symbol table. This marks Thumb symbols as distinct from
21178 arm_adjust_symtab (void)
21183 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21185 if (ARM_IS_THUMB (sym
))
21187 if (THUMB_IS_FUNC (sym
))
21189 /* Mark the symbol as a Thumb function. */
21190 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
21191 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
21192 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
21194 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
21195 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
21197 as_bad (_("%s: unexpected function type: %d"),
21198 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
21200 else switch (S_GET_STORAGE_CLASS (sym
))
21203 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
21206 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
21209 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
21217 if (ARM_IS_INTERWORK (sym
))
21218 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
21225 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21227 if (ARM_IS_THUMB (sym
))
21229 elf_symbol_type
* elf_sym
;
21231 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
21232 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
21234 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
21235 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
21237 /* If it's a .thumb_func, declare it as so,
21238 otherwise tag label as .code 16. */
21239 if (THUMB_IS_FUNC (sym
))
21240 elf_sym
->internal_elf_sym
.st_info
=
21241 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
21242 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21243 elf_sym
->internal_elf_sym
.st_info
=
21244 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
21249 /* Remove any overlapping mapping symbols generated by alignment frags. */
21250 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
21254 /* MD interface: Initialization. */
21257 set_constant_flonums (void)
21261 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
21262 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
21266 /* Auto-select Thumb mode if it's the only available instruction set for the
21267 given architecture. */
21270 autoselect_thumb_from_cpu_variant (void)
21272 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21273 opcode_select (16);
21282 if ( (arm_ops_hsh
= hash_new ()) == NULL
21283 || (arm_cond_hsh
= hash_new ()) == NULL
21284 || (arm_shift_hsh
= hash_new ()) == NULL
21285 || (arm_psr_hsh
= hash_new ()) == NULL
21286 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
21287 || (arm_reg_hsh
= hash_new ()) == NULL
21288 || (arm_reloc_hsh
= hash_new ()) == NULL
21289 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
21290 as_fatal (_("virtual memory exhausted"));
21292 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
21293 hash_insert (arm_ops_hsh
, insns
[i
].template, (void *) (insns
+ i
));
21294 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
21295 hash_insert (arm_cond_hsh
, conds
[i
].template, (void *) (conds
+ i
));
21296 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
21297 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
21298 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
21299 hash_insert (arm_psr_hsh
, psrs
[i
].template, (void *) (psrs
+ i
));
21300 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
21301 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (void *) (v7m_psrs
+ i
));
21302 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
21303 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
21305 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
21307 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
21308 (void *) (barrier_opt_names
+ i
));
21310 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
21311 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
21314 set_constant_flonums ();
21316 /* Set the cpu variant based on the command-line options. We prefer
21317 -mcpu= over -march= if both are set (as for GCC); and we prefer
21318 -mfpu= over any other way of setting the floating point unit.
21319 Use of legacy options with new options are faulted. */
21322 if (mcpu_cpu_opt
|| march_cpu_opt
)
21323 as_bad (_("use of old and new-style options to set CPU type"));
21325 mcpu_cpu_opt
= legacy_cpu
;
21327 else if (!mcpu_cpu_opt
)
21328 mcpu_cpu_opt
= march_cpu_opt
;
21333 as_bad (_("use of old and new-style options to set FPU type"));
21335 mfpu_opt
= legacy_fpu
;
21337 else if (!mfpu_opt
)
21339 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
21340 || defined (TE_NetBSD) || defined (TE_VXWORKS))
21341 /* Some environments specify a default FPU. If they don't, infer it
21342 from the processor. */
21344 mfpu_opt
= mcpu_fpu_opt
;
21346 mfpu_opt
= march_fpu_opt
;
21348 mfpu_opt
= &fpu_default
;
21354 if (mcpu_cpu_opt
!= NULL
)
21355 mfpu_opt
= &fpu_default
;
21356 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
21357 mfpu_opt
= &fpu_arch_vfp_v2
;
21359 mfpu_opt
= &fpu_arch_fpa
;
21365 mcpu_cpu_opt
= &cpu_default
;
21366 selected_cpu
= cpu_default
;
21370 selected_cpu
= *mcpu_cpu_opt
;
21372 mcpu_cpu_opt
= &arm_arch_any
;
21375 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21377 autoselect_thumb_from_cpu_variant ();
21379 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
21381 #if defined OBJ_COFF || defined OBJ_ELF
21383 unsigned int flags
= 0;
21385 #if defined OBJ_ELF
21386 flags
= meabi_flags
;
21388 switch (meabi_flags
)
21390 case EF_ARM_EABI_UNKNOWN
:
21392 /* Set the flags in the private structure. */
21393 if (uses_apcs_26
) flags
|= F_APCS26
;
21394 if (support_interwork
) flags
|= F_INTERWORK
;
21395 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
21396 if (pic_code
) flags
|= F_PIC
;
21397 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
21398 flags
|= F_SOFT_FLOAT
;
21400 switch (mfloat_abi_opt
)
21402 case ARM_FLOAT_ABI_SOFT
:
21403 case ARM_FLOAT_ABI_SOFTFP
:
21404 flags
|= F_SOFT_FLOAT
;
21407 case ARM_FLOAT_ABI_HARD
:
21408 if (flags
& F_SOFT_FLOAT
)
21409 as_bad (_("hard-float conflicts with specified fpu"));
21413 /* Using pure-endian doubles (even if soft-float). */
21414 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
21415 flags
|= F_VFP_FLOAT
;
21417 #if defined OBJ_ELF
21418 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
21419 flags
|= EF_ARM_MAVERICK_FLOAT
;
21422 case EF_ARM_EABI_VER4
:
21423 case EF_ARM_EABI_VER5
:
21424 /* No additional flags to set. */
21431 bfd_set_private_flags (stdoutput
, flags
);
21433 /* We have run out flags in the COFF header to encode the
21434 status of ATPCS support, so instead we create a dummy,
21435 empty, debug section called .arm.atpcs. */
21440 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
21444 bfd_set_section_flags
21445 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
21446 bfd_set_section_size (stdoutput
, sec
, 0);
21447 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
21453 /* Record the CPU type as well. */
21454 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
21455 mach
= bfd_mach_arm_iWMMXt2
;
21456 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
21457 mach
= bfd_mach_arm_iWMMXt
;
21458 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
21459 mach
= bfd_mach_arm_XScale
;
21460 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
21461 mach
= bfd_mach_arm_ep9312
;
21462 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
21463 mach
= bfd_mach_arm_5TE
;
21464 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
21466 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21467 mach
= bfd_mach_arm_5T
;
21469 mach
= bfd_mach_arm_5
;
21471 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
21473 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21474 mach
= bfd_mach_arm_4T
;
21476 mach
= bfd_mach_arm_4
;
21478 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
21479 mach
= bfd_mach_arm_3M
;
21480 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
21481 mach
= bfd_mach_arm_3
;
21482 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
21483 mach
= bfd_mach_arm_2a
;
21484 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
21485 mach
= bfd_mach_arm_2
;
21487 mach
= bfd_mach_arm_unknown
;
21489 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
21492 /* Command line processing. */
21495 Invocation line includes a switch not recognized by the base assembler.
21496 See if it's a processor-specific option.
21498 This routine is somewhat complicated by the need for backwards
21499 compatibility (since older releases of gcc can't be changed).
21500 The new options try to make the interface as compatible as
21503 New options (supported) are:
21505 -mcpu=<cpu name> Assemble for selected processor
21506 -march=<architecture name> Assemble for selected architecture
21507 -mfpu=<fpu architecture> Assemble for selected FPU.
21508 -EB/-mbig-endian Big-endian
21509 -EL/-mlittle-endian Little-endian
21510 -k Generate PIC code
21511 -mthumb Start in Thumb mode
21512 -mthumb-interwork Code supports ARM/Thumb interworking
21514 -m[no-]warn-deprecated Warn about deprecated features
21516 For now we will also provide support for:
21518 -mapcs-32 32-bit Program counter
21519 -mapcs-26 26-bit Program counter
21520 -macps-float Floats passed in FP registers
21521 -mapcs-reentrant Reentrant code
21523 (sometime these will probably be replaced with -mapcs=<list of options>
21524 and -matpcs=<list of options>)
21526 The remaining options are only supported for back-wards compatibility.
21527 Cpu variants, the arm part is optional:
21528 -m[arm]1 Currently not supported.
21529 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
21530 -m[arm]3 Arm 3 processor
21531 -m[arm]6[xx], Arm 6 processors
21532 -m[arm]7[xx][t][[d]m] Arm 7 processors
21533 -m[arm]8[10] Arm 8 processors
21534 -m[arm]9[20][tdmi] Arm 9 processors
21535 -mstrongarm[110[0]] StrongARM processors
21536 -mxscale XScale processors
21537 -m[arm]v[2345[t[e]]] Arm architectures
21538 -mall All (except the ARM1)
21540 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
21541 -mfpe-old (No float load/store multiples)
21542 -mvfpxd VFP Single precision
21544 -mno-fpu Disable all floating point instructions
21546 The following CPU names are recognized:
21547 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
21548 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
21549 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
21550 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
21551 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
21552 arm10t arm10e, arm1020t, arm1020e, arm10200e,
21553 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
21557 const char * md_shortopts
= "m:k";
21559 #ifdef ARM_BI_ENDIAN
21560 #define OPTION_EB (OPTION_MD_BASE + 0)
21561 #define OPTION_EL (OPTION_MD_BASE + 1)
21563 #if TARGET_BYTES_BIG_ENDIAN
21564 #define OPTION_EB (OPTION_MD_BASE + 0)
21566 #define OPTION_EL (OPTION_MD_BASE + 1)
21569 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
21571 struct option md_longopts
[] =
21574 {"EB", no_argument
, NULL
, OPTION_EB
},
21577 {"EL", no_argument
, NULL
, OPTION_EL
},
21579 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
21580 {NULL
, no_argument
, NULL
, 0}
21583 size_t md_longopts_size
= sizeof (md_longopts
);
21585 struct arm_option_table
21587 char *option
; /* Option name to match. */
21588 char *help
; /* Help information. */
21589 int *var
; /* Variable to change. */
21590 int value
; /* What to change it to. */
21591 char *deprecated
; /* If non-null, print this message. */
21594 struct arm_option_table arm_opts
[] =
21596 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
21597 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
21598 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
21599 &support_interwork
, 1, NULL
},
21600 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
21601 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
21602 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
21604 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
21605 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
21606 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
21607 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
21610 /* These are recognized by the assembler, but have no affect on code. */
21611 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
21612 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
21614 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
21615 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
21616 &warn_on_deprecated
, 0, NULL
},
21617 {NULL
, NULL
, NULL
, 0, NULL
}
21620 struct arm_legacy_option_table
21622 char *option
; /* Option name to match. */
21623 const arm_feature_set
**var
; /* Variable to change. */
21624 const arm_feature_set value
; /* What to change it to. */
21625 char *deprecated
; /* If non-null, print this message. */
21628 const struct arm_legacy_option_table arm_legacy_opts
[] =
21630 /* DON'T add any new processors to this list -- we want the whole list
21631 to go away... Add them to the processors table instead. */
21632 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
21633 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
21634 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
21635 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
21636 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
21637 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
21638 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
21639 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
21640 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
21641 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
21642 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
21643 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
21644 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
21645 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
21646 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
21647 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
21648 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
21649 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
21650 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
21651 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
21652 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
21653 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
21654 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
21655 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
21656 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
21657 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
21658 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
21659 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
21660 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
21661 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
21662 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
21663 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
21664 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
21665 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
21666 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
21667 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
21668 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
21669 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
21670 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
21671 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
21672 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
21673 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
21674 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
21675 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
21676 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
21677 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
21678 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21679 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21680 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21681 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
21682 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
21683 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
21684 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
21685 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
21686 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
21687 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
21688 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
21689 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
21690 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
21691 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
21692 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
21693 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
21694 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
21695 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
21696 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
21697 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
21698 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
21699 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
21700 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
21701 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
21702 N_("use -mcpu=strongarm110")},
21703 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
21704 N_("use -mcpu=strongarm1100")},
21705 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
21706 N_("use -mcpu=strongarm1110")},
21707 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
21708 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
21709 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
21711 /* Architecture variants -- don't add any more to this list either. */
21712 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
21713 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
21714 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
21715 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
21716 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
21717 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
21718 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
21719 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
21720 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
21721 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
21722 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
21723 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
21724 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
21725 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
21726 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
21727 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
21728 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
21729 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
21731 /* Floating point variants -- don't add any more to this list either. */
21732 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
21733 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
21734 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
21735 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
21736 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
21738 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
21741 struct arm_cpu_option_table
21744 const arm_feature_set value
;
21745 /* For some CPUs we assume an FPU unless the user explicitly sets
21747 const arm_feature_set default_fpu
;
21748 /* The canonical name of the CPU, or NULL to use NAME converted to upper
21750 const char *canonical_name
;
21753 /* This list should, at a minimum, contain all the cpu names
21754 recognized by GCC. */
21755 static const struct arm_cpu_option_table arm_cpus
[] =
21757 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
21758 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
21759 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
21760 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
21761 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
21762 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21763 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21764 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21765 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21766 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21767 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21768 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21769 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21770 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21771 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21772 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
21773 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21774 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21775 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21776 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21777 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21778 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21779 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21780 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21781 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21782 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21783 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21784 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
21785 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21786 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21787 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21788 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21789 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21790 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21791 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21792 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21793 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21794 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21795 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21796 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
21797 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21798 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21799 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21800 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
21801 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21802 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
21803 /* For V5 or later processors we default to using VFP; but the user
21804 should really set the FPU type explicitly. */
21805 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
21806 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21807 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
21808 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
21809 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
21810 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
21811 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
21812 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21813 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
21814 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
21815 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21816 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21817 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
21818 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
21819 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21820 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
21821 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
21822 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21823 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21824 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
21825 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
21826 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
21827 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
21828 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
21829 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
21830 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
21831 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
21832 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
21833 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
21834 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
21835 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
21836 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
21837 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
21838 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
21839 | FPU_NEON_EXT_V1
),
21841 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
21842 | FPU_NEON_EXT_V1
),
21844 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
21845 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
21846 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
21847 {"cortex-m0", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
21848 /* ??? XSCALE is really an architecture. */
21849 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
21850 /* ??? iwmmxt is not a processor. */
21851 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
21852 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
21853 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
21855 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
21856 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
21859 struct arm_arch_option_table
21862 const arm_feature_set value
;
21863 const arm_feature_set default_fpu
;
21866 /* This list should, at a minimum, contain all the architecture names
21867 recognized by GCC. */
21868 static const struct arm_arch_option_table arm_archs
[] =
21870 {"all", ARM_ANY
, FPU_ARCH_FPA
},
21871 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
21872 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
21873 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
21874 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
21875 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
21876 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
21877 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
21878 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
21879 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
21880 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
21881 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
21882 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
21883 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
21884 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
21885 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
21886 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
21887 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
21888 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
21889 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
21890 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
21891 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
21892 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
21893 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
21894 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
21895 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
21896 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
21897 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
21898 /* The official spelling of the ARMv7 profile variants is the dashed form.
21899 Accept the non-dashed form for compatibility with old toolchains. */
21900 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
21901 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
21902 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
21903 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
21904 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
21905 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
21906 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
21907 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
21908 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
21909 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
21912 /* ISA extensions in the co-processor space. */
21913 struct arm_option_cpu_value_table
21916 const arm_feature_set value
;
21919 static const struct arm_option_cpu_value_table arm_extensions
[] =
21921 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
21922 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
21923 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
21924 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
21925 {NULL
, ARM_ARCH_NONE
}
21928 /* This list should, at a minimum, contain all the fpu names
21929 recognized by GCC. */
21930 static const struct arm_option_cpu_value_table arm_fpus
[] =
21932 {"softfpa", FPU_NONE
},
21933 {"fpe", FPU_ARCH_FPE
},
21934 {"fpe2", FPU_ARCH_FPE
},
21935 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
21936 {"fpa", FPU_ARCH_FPA
},
21937 {"fpa10", FPU_ARCH_FPA
},
21938 {"fpa11", FPU_ARCH_FPA
},
21939 {"arm7500fe", FPU_ARCH_FPA
},
21940 {"softvfp", FPU_ARCH_VFP
},
21941 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
21942 {"vfp", FPU_ARCH_VFP_V2
},
21943 {"vfp9", FPU_ARCH_VFP_V2
},
21944 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
21945 {"vfp10", FPU_ARCH_VFP_V2
},
21946 {"vfp10-r0", FPU_ARCH_VFP_V1
},
21947 {"vfpxd", FPU_ARCH_VFP_V1xD
},
21948 {"vfpv2", FPU_ARCH_VFP_V2
},
21949 {"vfpv3", FPU_ARCH_VFP_V3
},
21950 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
21951 {"arm1020t", FPU_ARCH_VFP_V1
},
21952 {"arm1020e", FPU_ARCH_VFP_V2
},
21953 {"arm1136jfs", FPU_ARCH_VFP_V2
},
21954 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
21955 {"maverick", FPU_ARCH_MAVERICK
},
21956 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
21957 {"neon-fp16", FPU_ARCH_NEON_FP16
},
21958 {NULL
, ARM_ARCH_NONE
}
21961 struct arm_option_value_table
21967 static const struct arm_option_value_table arm_float_abis
[] =
21969 {"hard", ARM_FLOAT_ABI_HARD
},
21970 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
21971 {"soft", ARM_FLOAT_ABI_SOFT
},
21976 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
21977 static const struct arm_option_value_table arm_eabis
[] =
21979 {"gnu", EF_ARM_EABI_UNKNOWN
},
21980 {"4", EF_ARM_EABI_VER4
},
21981 {"5", EF_ARM_EABI_VER5
},
21986 struct arm_long_option_table
21988 char * option
; /* Substring to match. */
21989 char * help
; /* Help information. */
21990 int (* func
) (char * subopt
); /* Function to decode sub-option. */
21991 char * deprecated
; /* If non-null, print this message. */
21995 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
21997 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
21999 /* Copy the feature set, so that we can modify it. */
22000 *ext_set
= **opt_p
;
22003 while (str
!= NULL
&& *str
!= 0)
22005 const struct arm_option_cpu_value_table
* opt
;
22011 as_bad (_("invalid architectural extension"));
22016 ext
= strchr (str
, '+');
22019 optlen
= ext
- str
;
22021 optlen
= strlen (str
);
22025 as_bad (_("missing architectural extension"));
22029 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
22030 if (strncmp (opt
->name
, str
, optlen
) == 0)
22032 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
22036 if (opt
->name
== NULL
)
22038 as_bad (_("unknown architectural extension `%s'"), str
);
22049 arm_parse_cpu (char * str
)
22051 const struct arm_cpu_option_table
* opt
;
22052 char * ext
= strchr (str
, '+');
22056 optlen
= ext
- str
;
22058 optlen
= strlen (str
);
22062 as_bad (_("missing cpu name `%s'"), str
);
22066 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
22067 if (strncmp (opt
->name
, str
, optlen
) == 0)
22069 mcpu_cpu_opt
= &opt
->value
;
22070 mcpu_fpu_opt
= &opt
->default_fpu
;
22071 if (opt
->canonical_name
)
22072 strcpy (selected_cpu_name
, opt
->canonical_name
);
22077 for (i
= 0; i
< optlen
; i
++)
22078 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22079 selected_cpu_name
[i
] = 0;
22083 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
22088 as_bad (_("unknown cpu `%s'"), str
);
22093 arm_parse_arch (char * str
)
22095 const struct arm_arch_option_table
*opt
;
22096 char *ext
= strchr (str
, '+');
22100 optlen
= ext
- str
;
22102 optlen
= strlen (str
);
22106 as_bad (_("missing architecture name `%s'"), str
);
22110 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
22111 if (streq (opt
->name
, str
))
22113 march_cpu_opt
= &opt
->value
;
22114 march_fpu_opt
= &opt
->default_fpu
;
22115 strcpy (selected_cpu_name
, opt
->name
);
22118 return arm_parse_extension (ext
, &march_cpu_opt
);
22123 as_bad (_("unknown architecture `%s'\n"), str
);
22128 arm_parse_fpu (char * str
)
22130 const struct arm_option_cpu_value_table
* opt
;
22132 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22133 if (streq (opt
->name
, str
))
22135 mfpu_opt
= &opt
->value
;
22139 as_bad (_("unknown floating point format `%s'\n"), str
);
22144 arm_parse_float_abi (char * str
)
22146 const struct arm_option_value_table
* opt
;
22148 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
22149 if (streq (opt
->name
, str
))
22151 mfloat_abi_opt
= opt
->value
;
22155 as_bad (_("unknown floating point abi `%s'\n"), str
);
22161 arm_parse_eabi (char * str
)
22163 const struct arm_option_value_table
*opt
;
22165 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
22166 if (streq (opt
->name
, str
))
22168 meabi_flags
= opt
->value
;
22171 as_bad (_("unknown EABI `%s'\n"), str
);
22177 arm_parse_it_mode (char * str
)
22179 bfd_boolean ret
= TRUE
;
22181 if (streq ("arm", str
))
22182 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
22183 else if (streq ("thumb", str
))
22184 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
22185 else if (streq ("always", str
))
22186 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
22187 else if (streq ("never", str
))
22188 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
22191 as_bad (_("unknown implicit IT mode `%s', should be "\
22192 "arm, thumb, always, or never."), str
);
22199 struct arm_long_option_table arm_long_opts
[] =
22201 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
22202 arm_parse_cpu
, NULL
},
22203 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
22204 arm_parse_arch
, NULL
},
22205 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
22206 arm_parse_fpu
, NULL
},
22207 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
22208 arm_parse_float_abi
, NULL
},
22210 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
22211 arm_parse_eabi
, NULL
},
22213 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
22214 arm_parse_it_mode
, NULL
},
22215 {NULL
, NULL
, 0, NULL
}
22219 md_parse_option (int c
, char * arg
)
22221 struct arm_option_table
*opt
;
22222 const struct arm_legacy_option_table
*fopt
;
22223 struct arm_long_option_table
*lopt
;
22229 target_big_endian
= 1;
22235 target_big_endian
= 0;
22239 case OPTION_FIX_V4BX
:
22244 /* Listing option. Just ignore these, we don't support additional
22249 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22251 if (c
== opt
->option
[0]
22252 && ((arg
== NULL
&& opt
->option
[1] == 0)
22253 || streq (arg
, opt
->option
+ 1)))
22255 /* If the option is deprecated, tell the user. */
22256 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
22257 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22258 arg
? arg
: "", _(opt
->deprecated
));
22260 if (opt
->var
!= NULL
)
22261 *opt
->var
= opt
->value
;
22267 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
22269 if (c
== fopt
->option
[0]
22270 && ((arg
== NULL
&& fopt
->option
[1] == 0)
22271 || streq (arg
, fopt
->option
+ 1)))
22273 /* If the option is deprecated, tell the user. */
22274 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
22275 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22276 arg
? arg
: "", _(fopt
->deprecated
));
22278 if (fopt
->var
!= NULL
)
22279 *fopt
->var
= &fopt
->value
;
22285 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22287 /* These options are expected to have an argument. */
22288 if (c
== lopt
->option
[0]
22290 && strncmp (arg
, lopt
->option
+ 1,
22291 strlen (lopt
->option
+ 1)) == 0)
22293 /* If the option is deprecated, tell the user. */
22294 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
22295 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
22296 _(lopt
->deprecated
));
22298 /* Call the sup-option parser. */
22299 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
22310 md_show_usage (FILE * fp
)
22312 struct arm_option_table
*opt
;
22313 struct arm_long_option_table
*lopt
;
22315 fprintf (fp
, _(" ARM-specific assembler options:\n"));
22317 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22318 if (opt
->help
!= NULL
)
22319 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
22321 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22322 if (lopt
->help
!= NULL
)
22323 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
22327 -EB assemble code for a big-endian cpu\n"));
22332 -EL assemble code for a little-endian cpu\n"));
22336 --fix-v4bx Allow BX in ARMv4 code\n"));
22344 arm_feature_set flags
;
22345 } cpu_arch_ver_table
;
22347 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
22348 least features first. */
22349 static const cpu_arch_ver_table cpu_arch_ver
[] =
22355 {4, ARM_ARCH_V5TE
},
22356 {5, ARM_ARCH_V5TEJ
},
22360 {11, ARM_ARCH_V6M
},
22361 {8, ARM_ARCH_V6T2
},
22362 {10, ARM_ARCH_V7A
},
22363 {10, ARM_ARCH_V7R
},
22364 {10, ARM_ARCH_V7M
},
22368 /* Set an attribute if it has not already been set by the user. */
22370 aeabi_set_attribute_int (int tag
, int value
)
22373 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22374 || !attributes_set_explicitly
[tag
])
22375 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
22379 aeabi_set_attribute_string (int tag
, const char *value
)
22382 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22383 || !attributes_set_explicitly
[tag
])
22384 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
22387 /* Set the public EABI object attributes. */
22389 aeabi_set_public_attributes (void)
22392 arm_feature_set flags
;
22393 arm_feature_set tmp
;
22394 const cpu_arch_ver_table
*p
;
22396 /* Choose the architecture based on the capabilities of the requested cpu
22397 (if any) and/or the instructions actually used. */
22398 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
22399 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
22400 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
22401 /*Allow the user to override the reported architecture. */
22404 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
22405 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
22410 for (p
= cpu_arch_ver
; p
->val
; p
++)
22412 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
22415 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
22419 /* Tag_CPU_name. */
22420 if (selected_cpu_name
[0])
22424 p
= selected_cpu_name
;
22425 if (strncmp (p
, "armv", 4) == 0)
22430 for (i
= 0; p
[i
]; i
++)
22431 p
[i
] = TOUPPER (p
[i
]);
22433 aeabi_set_attribute_string (Tag_CPU_name
, p
);
22435 /* Tag_CPU_arch. */
22436 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
22437 /* Tag_CPU_arch_profile. */
22438 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
22439 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
22440 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
22441 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
22442 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
22443 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
22444 /* Tag_ARM_ISA_use. */
22445 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
22447 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
22448 /* Tag_THUMB_ISA_use. */
22449 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
22451 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
22452 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
22453 /* Tag_VFP_arch. */
22454 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
22455 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
22456 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3
))
22457 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
22458 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
22459 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
22460 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
22461 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
22462 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
22463 /* Tag_WMMX_arch. */
22464 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
22465 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
22466 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
22467 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
22468 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
22469 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
22470 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
22471 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
22472 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_fp16
))
22473 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
22476 /* Add the default contents for the .ARM.attributes section. */
22480 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
22483 aeabi_set_public_attributes ();
22485 #endif /* OBJ_ELF */
22488 /* Parse a .cpu directive. */
22491 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
22493 const struct arm_cpu_option_table
*opt
;
22497 name
= input_line_pointer
;
22498 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22499 input_line_pointer
++;
22500 saved_char
= *input_line_pointer
;
22501 *input_line_pointer
= 0;
22503 /* Skip the first "all" entry. */
22504 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
22505 if (streq (opt
->name
, name
))
22507 mcpu_cpu_opt
= &opt
->value
;
22508 selected_cpu
= opt
->value
;
22509 if (opt
->canonical_name
)
22510 strcpy (selected_cpu_name
, opt
->canonical_name
);
22514 for (i
= 0; opt
->name
[i
]; i
++)
22515 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22516 selected_cpu_name
[i
] = 0;
22518 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22519 *input_line_pointer
= saved_char
;
22520 demand_empty_rest_of_line ();
22523 as_bad (_("unknown cpu `%s'"), name
);
22524 *input_line_pointer
= saved_char
;
22525 ignore_rest_of_line ();
22529 /* Parse a .arch directive. */
22532 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
22534 const struct arm_arch_option_table
*opt
;
22538 name
= input_line_pointer
;
22539 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22540 input_line_pointer
++;
22541 saved_char
= *input_line_pointer
;
22542 *input_line_pointer
= 0;
22544 /* Skip the first "all" entry. */
22545 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
22546 if (streq (opt
->name
, name
))
22548 mcpu_cpu_opt
= &opt
->value
;
22549 selected_cpu
= opt
->value
;
22550 strcpy (selected_cpu_name
, opt
->name
);
22551 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22552 *input_line_pointer
= saved_char
;
22553 demand_empty_rest_of_line ();
22557 as_bad (_("unknown architecture `%s'\n"), name
);
22558 *input_line_pointer
= saved_char
;
22559 ignore_rest_of_line ();
22563 /* Parse a .object_arch directive. */
22566 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
22568 const struct arm_arch_option_table
*opt
;
22572 name
= input_line_pointer
;
22573 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22574 input_line_pointer
++;
22575 saved_char
= *input_line_pointer
;
22576 *input_line_pointer
= 0;
22578 /* Skip the first "all" entry. */
22579 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
22580 if (streq (opt
->name
, name
))
22582 object_arch
= &opt
->value
;
22583 *input_line_pointer
= saved_char
;
22584 demand_empty_rest_of_line ();
22588 as_bad (_("unknown architecture `%s'\n"), name
);
22589 *input_line_pointer
= saved_char
;
22590 ignore_rest_of_line ();
22593 /* Parse a .fpu directive. */
22596 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
22598 const struct arm_option_cpu_value_table
*opt
;
22602 name
= input_line_pointer
;
22603 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22604 input_line_pointer
++;
22605 saved_char
= *input_line_pointer
;
22606 *input_line_pointer
= 0;
22608 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22609 if (streq (opt
->name
, name
))
22611 mfpu_opt
= &opt
->value
;
22612 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22613 *input_line_pointer
= saved_char
;
22614 demand_empty_rest_of_line ();
22618 as_bad (_("unknown floating point format `%s'\n"), name
);
22619 *input_line_pointer
= saved_char
;
22620 ignore_rest_of_line ();
22623 /* Copy symbol information. */
22626 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
22628 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
22632 /* Given a symbolic attribute NAME, return the proper integer value.
22633 Returns -1 if the attribute is not known. */
22636 arm_convert_symbolic_attribute (const char *name
)
22638 static const struct
22643 attribute_table
[] =
22645 /* When you modify this table you should
22646 also modify the list in doc/c-arm.texi. */
22647 #define T(tag) {#tag, tag}
22648 T (Tag_CPU_raw_name
),
22651 T (Tag_CPU_arch_profile
),
22652 T (Tag_ARM_ISA_use
),
22653 T (Tag_THUMB_ISA_use
),
22656 T (Tag_Advanced_SIMD_arch
),
22657 T (Tag_PCS_config
),
22658 T (Tag_ABI_PCS_R9_use
),
22659 T (Tag_ABI_PCS_RW_data
),
22660 T (Tag_ABI_PCS_RO_data
),
22661 T (Tag_ABI_PCS_GOT_use
),
22662 T (Tag_ABI_PCS_wchar_t
),
22663 T (Tag_ABI_FP_rounding
),
22664 T (Tag_ABI_FP_denormal
),
22665 T (Tag_ABI_FP_exceptions
),
22666 T (Tag_ABI_FP_user_exceptions
),
22667 T (Tag_ABI_FP_number_model
),
22668 T (Tag_ABI_align8_needed
),
22669 T (Tag_ABI_align8_preserved
),
22670 T (Tag_ABI_enum_size
),
22671 T (Tag_ABI_HardFP_use
),
22672 T (Tag_ABI_VFP_args
),
22673 T (Tag_ABI_WMMX_args
),
22674 T (Tag_ABI_optimization_goals
),
22675 T (Tag_ABI_FP_optimization_goals
),
22676 T (Tag_compatibility
),
22677 T (Tag_CPU_unaligned_access
),
22678 T (Tag_VFP_HP_extension
),
22679 T (Tag_ABI_FP_16bit_format
),
22680 T (Tag_nodefaults
),
22681 T (Tag_also_compatible_with
),
22682 T (Tag_conformance
),
22684 T (Tag_Virtualization_use
),
22685 T (Tag_MPextension_use
)
22693 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
22694 if (streq (name
, attribute_table
[i
].name
))
22695 return attribute_table
[i
].tag
;
22701 /* Apply sym value for relocations only in the case that
22702 they are for local symbols and you have the respective
22703 architectural feature for blx and simple switches. */
22705 arm_apply_sym_value (struct fix
* fixP
)
22708 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22709 && !S_IS_EXTERNAL (fixP
->fx_addsy
))
22711 switch (fixP
->fx_r_type
)
22713 case BFD_RELOC_ARM_PCREL_BLX
:
22714 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22715 if (ARM_IS_FUNC (fixP
->fx_addsy
))
22719 case BFD_RELOC_ARM_PCREL_CALL
:
22720 case BFD_RELOC_THUMB_PCREL_BLX
:
22721 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
22732 #endif /* OBJ_ELF */