1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dwarf2dbg.h"
41 #include "dw2gencfi.h"
44 /* XXX Set this to 1 after the next binutils release. */
45 #define WARN_DEPRECATED 0
48 /* Must be at least the size of the largest unwind opcode (currently two). */
49 #define ARM_OPCODE_CHUNK_SIZE 8
51 /* This structure holds the unwinding state. */
56 symbolS
* table_entry
;
57 symbolS
* personality_routine
;
58 int personality_index
;
59 /* The segment containing the function. */
62 /* Opcodes generated from this function. */
63 unsigned char * opcodes
;
66 /* The number of bytes pushed to the stack. */
68 /* We don't add stack adjustment opcodes immediately so that we can merge
69 multiple adjustments. We can also omit the final adjustment
70 when using a frame pointer. */
71 offsetT pending_offset
;
72 /* These two fields are set by both unwind_movsp and unwind_setfp. They
73 hold the reg+offset to use when restoring sp from a frame pointer. */
76 /* Nonzero if an unwind_setfp directive has been seen. */
78 /* Nonzero if the last opcode restores sp from fp_reg. */
79 unsigned sp_restored
:1;
82 /* Bit N indicates that an R_ARM_NONE relocation has been output for
83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84 emitted only once per section, to save unnecessary bloat. */
85 static unsigned int marked_pr_dependency
= 0;
89 /* Results from operand parsing worker functions. */
93 PARSE_OPERAND_SUCCESS
,
95 PARSE_OPERAND_FAIL_NO_BACKTRACK
96 } parse_operand_result
;
101 ARM_FLOAT_ABI_SOFTFP
,
105 /* Types of processor to assemble for. */
107 #if defined __XSCALE__
108 #define CPU_DEFAULT ARM_ARCH_XSCALE
110 #if defined __thumb__
111 #define CPU_DEFAULT ARM_ARCH_V5T
118 # define FPU_DEFAULT FPU_ARCH_FPA
119 # elif defined (TE_NetBSD)
121 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
123 /* Legacy a.out format. */
124 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
126 # elif defined (TE_VXWORKS)
127 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
129 /* For backwards compatibility, default to FPA. */
130 # define FPU_DEFAULT FPU_ARCH_FPA
132 #endif /* ifndef FPU_DEFAULT */
134 #define streq(a, b) (strcmp (a, b) == 0)
136 static arm_feature_set cpu_variant
;
137 static arm_feature_set arm_arch_used
;
138 static arm_feature_set thumb_arch_used
;
140 /* Flags stored in private area of BFD structure. */
141 static int uses_apcs_26
= FALSE
;
142 static int atpcs
= FALSE
;
143 static int support_interwork
= FALSE
;
144 static int uses_apcs_float
= FALSE
;
145 static int pic_code
= FALSE
;
147 /* Variables that we set while parsing command-line options. Once all
148 options have been read we re-process these values to set the real
150 static const arm_feature_set
*legacy_cpu
= NULL
;
151 static const arm_feature_set
*legacy_fpu
= NULL
;
153 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
154 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
155 static const arm_feature_set
*march_cpu_opt
= NULL
;
156 static const arm_feature_set
*march_fpu_opt
= NULL
;
157 static const arm_feature_set
*mfpu_opt
= NULL
;
159 /* Constants for known architecture features. */
160 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
161 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
162 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
163 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
164 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
165 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
166 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
167 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
168 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
171 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
174 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
175 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
176 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
177 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
178 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
179 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
180 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
181 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
182 static const arm_feature_set arm_ext_v4t_5
=
183 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
184 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
185 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
186 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
187 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
188 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
189 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
190 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
191 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
192 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
199 static const arm_feature_set arm_arch_any
= ARM_ANY
;
200 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
201 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
202 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
204 static const arm_feature_set arm_cext_iwmmxt
=
205 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
206 static const arm_feature_set arm_cext_xscale
=
207 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
208 static const arm_feature_set arm_cext_maverick
=
209 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
210 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
211 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
212 static const arm_feature_set fpu_vfp_ext_v1xd
=
213 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
214 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
215 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
216 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
217 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
218 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
219 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
221 static int mfloat_abi_opt
= -1;
222 /* Record user cpu selection for object attributes. */
223 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
224 /* Must be long enough to hold any of the names in arm_cpus. */
225 static char selected_cpu_name
[16];
228 static int meabi_flags
= EABI_DEFAULT
;
230 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
235 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
236 symbolS
* GOT_symbol
;
239 /* 0: assemble for ARM,
240 1: assemble for Thumb,
241 2: assemble for Thumb even though target CPU does not support thumb
243 static int thumb_mode
= 0;
245 /* If unified_syntax is true, we are processing the new unified
246 ARM/Thumb syntax. Important differences from the old ARM mode:
248 - Immediate operands do not require a # prefix.
249 - Conditional affixes always appear at the end of the
250 instruction. (For backward compatibility, those instructions
251 that formerly had them in the middle, continue to accept them
253 - The IT instruction may appear, and if it does is validated
254 against subsequent conditional affixes. It does not generate
257 Important differences from the old Thumb mode:
259 - Immediate operands do not require a # prefix.
260 - Most of the V6T2 instructions are only available in unified mode.
261 - The .N and .W suffixes are recognized and honored (it is an error
262 if they cannot be honored).
263 - All instructions set the flags if and only if they have an 's' affix.
264 - Conditional affixes may be used. They are validated against
265 preceding IT instructions. Unlike ARM mode, you cannot use a
266 conditional affix except in the scope of an IT instruction. */
268 static bfd_boolean unified_syntax
= FALSE
;
283 enum neon_el_type type
;
287 #define NEON_MAX_TYPE_ELS 4
291 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
298 unsigned long instruction
;
302 /* "uncond_value" is set to the value in place of the conditional field in
303 unconditional versions of the instruction, or -1 if nothing is
306 struct neon_type vectype
;
307 /* Set to the opcode if the instruction needs relaxation.
308 Zero if the instruction is not relaxed. */
312 bfd_reloc_code_real_type type
;
321 struct neon_type_el vectype
;
322 unsigned present
: 1; /* Operand present. */
323 unsigned isreg
: 1; /* Operand was a register. */
324 unsigned immisreg
: 1; /* .imm field is a second register. */
325 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
326 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
327 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
328 instructions. This allows us to disambiguate ARM <-> vector insns. */
329 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
330 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
331 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
332 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
333 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
334 unsigned writeback
: 1; /* Operand has trailing ! */
335 unsigned preind
: 1; /* Preindexed address. */
336 unsigned postind
: 1; /* Postindexed address. */
337 unsigned negative
: 1; /* Index register was negated. */
338 unsigned shifted
: 1; /* Shift applied to operation. */
339 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
343 static struct arm_it inst
;
345 #define NUM_FLOAT_VALS 8
347 const char * fp_const
[] =
349 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
352 /* Number of littlenums required to hold an extended precision number. */
353 #define MAX_LITTLENUMS 6
355 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
365 #define CP_T_X 0x00008000
366 #define CP_T_Y 0x00400000
368 #define CONDS_BIT 0x00100000
369 #define LOAD_BIT 0x00100000
371 #define DOUBLE_LOAD_FLAG 0x00000001
375 const char * template;
379 #define COND_ALWAYS 0xE
383 const char *template;
387 struct asm_barrier_opt
389 const char *template;
393 /* The bit that distinguishes CPSR and SPSR. */
394 #define SPSR_BIT (1 << 22)
396 /* The individual PSR flag bits. */
397 #define PSR_c (1 << 16)
398 #define PSR_x (1 << 17)
399 #define PSR_s (1 << 18)
400 #define PSR_f (1 << 19)
405 bfd_reloc_code_real_type reloc
;
410 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
411 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
416 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
419 /* Bits for DEFINED field in neon_typed_alias. */
420 #define NTA_HASTYPE 1
421 #define NTA_HASINDEX 2
423 struct neon_typed_alias
425 unsigned char defined
;
427 struct neon_type_el eltype
;
430 /* ARM register categories. This includes coprocessor numbers and various
431 architecture extensions' registers. */
457 /* Structure for a hash table entry for a register.
458 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
459 information which states whether a vector type or index is specified (for a
460 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
464 unsigned char number
;
466 unsigned char builtin
;
467 struct neon_typed_alias
*neon
;
470 /* Diagnostics used when we don't get a register of the expected type. */
471 const char *const reg_expected_msgs
[] =
473 N_("ARM register expected"),
474 N_("bad or missing co-processor number"),
475 N_("co-processor register expected"),
476 N_("FPA register expected"),
477 N_("VFP single precision register expected"),
478 N_("VFP/Neon double precision register expected"),
479 N_("Neon quad precision register expected"),
480 N_("VFP single or double precision register expected"),
481 N_("Neon double or quad precision register expected"),
482 N_("VFP single, double or Neon quad precision register expected"),
483 N_("VFP system register expected"),
484 N_("Maverick MVF register expected"),
485 N_("Maverick MVD register expected"),
486 N_("Maverick MVFX register expected"),
487 N_("Maverick MVDX register expected"),
488 N_("Maverick MVAX register expected"),
489 N_("Maverick DSPSC register expected"),
490 N_("iWMMXt data register expected"),
491 N_("iWMMXt control register expected"),
492 N_("iWMMXt scalar register expected"),
493 N_("XScale accumulator register expected"),
496 /* Some well known registers that we refer to directly elsewhere. */
501 /* ARM instructions take 4bytes in the object file, Thumb instructions
507 /* Basic string to match. */
508 const char *template;
510 /* Parameters to instruction. */
511 unsigned char operands
[8];
513 /* Conditional tag - see opcode_lookup. */
514 unsigned int tag
: 4;
516 /* Basic instruction code. */
517 unsigned int avalue
: 28;
519 /* Thumb-format instruction code. */
522 /* Which architecture variant provides this instruction. */
523 const arm_feature_set
*avariant
;
524 const arm_feature_set
*tvariant
;
526 /* Function to call to encode instruction in ARM format. */
527 void (* aencode
) (void);
529 /* Function to call to encode instruction in Thumb format. */
530 void (* tencode
) (void);
533 /* Defines for various bits that we will want to toggle. */
534 #define INST_IMMEDIATE 0x02000000
535 #define OFFSET_REG 0x02000000
536 #define HWOFFSET_IMM 0x00400000
537 #define SHIFT_BY_REG 0x00000010
538 #define PRE_INDEX 0x01000000
539 #define INDEX_UP 0x00800000
540 #define WRITE_BACK 0x00200000
541 #define LDM_TYPE_2_OR_3 0x00400000
543 #define LITERAL_MASK 0xf000f000
544 #define OPCODE_MASK 0xfe1fffff
545 #define V4_STR_BIT 0x00000020
547 #define DATA_OP_SHIFT 21
549 #define T2_OPCODE_MASK 0xfe1fffff
550 #define T2_DATA_OP_SHIFT 21
552 /* Codes to distinguish the arithmetic instructions. */
563 #define OPCODE_CMP 10
564 #define OPCODE_CMN 11
565 #define OPCODE_ORR 12
566 #define OPCODE_MOV 13
567 #define OPCODE_BIC 14
568 #define OPCODE_MVN 15
570 #define T2_OPCODE_AND 0
571 #define T2_OPCODE_BIC 1
572 #define T2_OPCODE_ORR 2
573 #define T2_OPCODE_ORN 3
574 #define T2_OPCODE_EOR 4
575 #define T2_OPCODE_ADD 8
576 #define T2_OPCODE_ADC 10
577 #define T2_OPCODE_SBC 11
578 #define T2_OPCODE_SUB 13
579 #define T2_OPCODE_RSB 14
581 #define T_OPCODE_MUL 0x4340
582 #define T_OPCODE_TST 0x4200
583 #define T_OPCODE_CMN 0x42c0
584 #define T_OPCODE_NEG 0x4240
585 #define T_OPCODE_MVN 0x43c0
587 #define T_OPCODE_ADD_R3 0x1800
588 #define T_OPCODE_SUB_R3 0x1a00
589 #define T_OPCODE_ADD_HI 0x4400
590 #define T_OPCODE_ADD_ST 0xb000
591 #define T_OPCODE_SUB_ST 0xb080
592 #define T_OPCODE_ADD_SP 0xa800
593 #define T_OPCODE_ADD_PC 0xa000
594 #define T_OPCODE_ADD_I8 0x3000
595 #define T_OPCODE_SUB_I8 0x3800
596 #define T_OPCODE_ADD_I3 0x1c00
597 #define T_OPCODE_SUB_I3 0x1e00
599 #define T_OPCODE_ASR_R 0x4100
600 #define T_OPCODE_LSL_R 0x4080
601 #define T_OPCODE_LSR_R 0x40c0
602 #define T_OPCODE_ROR_R 0x41c0
603 #define T_OPCODE_ASR_I 0x1000
604 #define T_OPCODE_LSL_I 0x0000
605 #define T_OPCODE_LSR_I 0x0800
607 #define T_OPCODE_MOV_I8 0x2000
608 #define T_OPCODE_CMP_I8 0x2800
609 #define T_OPCODE_CMP_LR 0x4280
610 #define T_OPCODE_MOV_HR 0x4600
611 #define T_OPCODE_CMP_HR 0x4500
613 #define T_OPCODE_LDR_PC 0x4800
614 #define T_OPCODE_LDR_SP 0x9800
615 #define T_OPCODE_STR_SP 0x9000
616 #define T_OPCODE_LDR_IW 0x6800
617 #define T_OPCODE_STR_IW 0x6000
618 #define T_OPCODE_LDR_IH 0x8800
619 #define T_OPCODE_STR_IH 0x8000
620 #define T_OPCODE_LDR_IB 0x7800
621 #define T_OPCODE_STR_IB 0x7000
622 #define T_OPCODE_LDR_RW 0x5800
623 #define T_OPCODE_STR_RW 0x5000
624 #define T_OPCODE_LDR_RH 0x5a00
625 #define T_OPCODE_STR_RH 0x5200
626 #define T_OPCODE_LDR_RB 0x5c00
627 #define T_OPCODE_STR_RB 0x5400
629 #define T_OPCODE_PUSH 0xb400
630 #define T_OPCODE_POP 0xbc00
632 #define T_OPCODE_BRANCH 0xe000
634 #define THUMB_SIZE 2 /* Size of thumb instruction. */
635 #define THUMB_PP_PC_LR 0x0100
636 #define THUMB_LOAD_BIT 0x0800
637 #define THUMB2_LOAD_BIT 0x00100000
639 #define BAD_ARGS _("bad arguments to instruction")
640 #define BAD_PC _("r15 not allowed here")
641 #define BAD_COND _("instruction cannot be conditional")
642 #define BAD_OVERLAP _("registers may not be the same")
643 #define BAD_HIREG _("lo register required")
644 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
645 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
646 #define BAD_BRANCH _("branch must be last instruction in IT block")
647 #define BAD_NOT_IT _("instruction not allowed in IT block")
648 #define BAD_FPU _("selected FPU does not support instruction")
650 static struct hash_control
*arm_ops_hsh
;
651 static struct hash_control
*arm_cond_hsh
;
652 static struct hash_control
*arm_shift_hsh
;
653 static struct hash_control
*arm_psr_hsh
;
654 static struct hash_control
*arm_v7m_psr_hsh
;
655 static struct hash_control
*arm_reg_hsh
;
656 static struct hash_control
*arm_reloc_hsh
;
657 static struct hash_control
*arm_barrier_opt_hsh
;
659 /* Stuff needed to resolve the label ambiguity
669 symbolS
* last_label_seen
;
670 static int label_is_thumb_function_name
= FALSE
;
672 /* Literal pool structure. Held on a per-section
673 and per-sub-section basis. */
675 #define MAX_LITERAL_POOL_SIZE 1024
676 typedef struct literal_pool
678 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
679 unsigned int next_free_entry
;
684 struct literal_pool
* next
;
687 /* Pointer to a linked list of literal pools. */
688 literal_pool
* list_of_pools
= NULL
;
690 /* State variables for IT block handling. */
691 static bfd_boolean current_it_mask
= 0;
692 static int current_cc
;
697 /* This array holds the chars that always start a comment. If the
698 pre-processor is disabled, these aren't very useful. */
699 const char comment_chars
[] = "@";
701 /* This array holds the chars that only start a comment at the beginning of
702 a line. If the line seems to have the form '# 123 filename'
703 .line and .file directives will appear in the pre-processed output. */
704 /* Note that input_file.c hand checks for '#' at the beginning of the
705 first line of the input file. This is because the compiler outputs
706 #NO_APP at the beginning of its output. */
707 /* Also note that comments like this one will always work. */
708 const char line_comment_chars
[] = "#";
710 const char line_separator_chars
[] = ";";
712 /* Chars that can be used to separate mant
713 from exp in floating point numbers. */
714 const char EXP_CHARS
[] = "eE";
716 /* Chars that mean this number is a floating point constant. */
720 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
722 /* Prefix characters that indicate the start of an immediate
724 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
726 /* Separator character handling. */
728 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
731 skip_past_char (char ** str
, char c
)
741 #define skip_past_comma(str) skip_past_char (str, ',')
743 /* Arithmetic expressions (possibly involving symbols). */
745 /* Return TRUE if anything in the expression is a bignum. */
748 walk_no_bignums (symbolS
* sp
)
750 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
753 if (symbol_get_value_expression (sp
)->X_add_symbol
)
755 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
756 || (symbol_get_value_expression (sp
)->X_op_symbol
757 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
763 static int in_my_get_expression
= 0;
765 /* Third argument to my_get_expression. */
766 #define GE_NO_PREFIX 0
767 #define GE_IMM_PREFIX 1
768 #define GE_OPT_PREFIX 2
769 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
770 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
771 #define GE_OPT_PREFIX_BIG 3
774 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
779 /* In unified syntax, all prefixes are optional. */
781 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
786 case GE_NO_PREFIX
: break;
788 if (!is_immediate_prefix (**str
))
790 inst
.error
= _("immediate expression requires a # prefix");
796 case GE_OPT_PREFIX_BIG
:
797 if (is_immediate_prefix (**str
))
803 memset (ep
, 0, sizeof (expressionS
));
805 save_in
= input_line_pointer
;
806 input_line_pointer
= *str
;
807 in_my_get_expression
= 1;
808 seg
= expression (ep
);
809 in_my_get_expression
= 0;
811 if (ep
->X_op
== O_illegal
)
813 /* We found a bad expression in md_operand(). */
814 *str
= input_line_pointer
;
815 input_line_pointer
= save_in
;
816 if (inst
.error
== NULL
)
817 inst
.error
= _("bad expression");
822 if (seg
!= absolute_section
823 && seg
!= text_section
824 && seg
!= data_section
825 && seg
!= bss_section
826 && seg
!= undefined_section
)
828 inst
.error
= _("bad segment");
829 *str
= input_line_pointer
;
830 input_line_pointer
= save_in
;
835 /* Get rid of any bignums now, so that we don't generate an error for which
836 we can't establish a line number later on. Big numbers are never valid
837 in instructions, which is where this routine is always called. */
838 if (prefix_mode
!= GE_OPT_PREFIX_BIG
839 && (ep
->X_op
== O_big
841 && (walk_no_bignums (ep
->X_add_symbol
)
843 && walk_no_bignums (ep
->X_op_symbol
))))))
845 inst
.error
= _("invalid constant");
846 *str
= input_line_pointer
;
847 input_line_pointer
= save_in
;
851 *str
= input_line_pointer
;
852 input_line_pointer
= save_in
;
856 /* Turn a string in input_line_pointer into a floating point constant
857 of type TYPE, and store the appropriate bytes in *LITP. The number
858 of LITTLENUMS emitted is stored in *SIZEP. An error message is
859 returned, or NULL on OK.
861 Note that fp constants aren't represent in the normal way on the ARM.
862 In big endian mode, things are as expected. However, in little endian
863 mode fp constants are big-endian word-wise, and little-endian byte-wise
864 within the words. For example, (double) 1.1 in big endian mode is
865 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
866 the byte sequence 99 99 f1 3f 9a 99 99 99.
868 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
871 md_atof (int type
, char * litP
, int * sizeP
)
874 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
906 return _("bad call to MD_ATOF()");
909 t
= atof_ieee (input_line_pointer
, type
, words
);
911 input_line_pointer
= t
;
914 if (target_big_endian
)
916 for (i
= 0; i
< prec
; i
++)
918 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
924 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
925 for (i
= prec
- 1; i
>= 0; i
--)
927 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
931 /* For a 4 byte float the order of elements in `words' is 1 0.
932 For an 8 byte float the order is 1 0 3 2. */
933 for (i
= 0; i
< prec
; i
+= 2)
935 md_number_to_chars (litP
, (valueT
) words
[i
+ 1], 2);
936 md_number_to_chars (litP
+ 2, (valueT
) words
[i
], 2);
944 /* We handle all bad expressions here, so that we can report the faulty
945 instruction in the error message. */
947 md_operand (expressionS
* expr
)
949 if (in_my_get_expression
)
950 expr
->X_op
= O_illegal
;
953 /* Immediate values. */
955 /* Generic immediate-value read function for use in directives.
956 Accepts anything that 'expression' can fold to a constant.
957 *val receives the number. */
960 immediate_for_directive (int *val
)
963 exp
.X_op
= O_illegal
;
965 if (is_immediate_prefix (*input_line_pointer
))
967 input_line_pointer
++;
971 if (exp
.X_op
!= O_constant
)
973 as_bad (_("expected #constant"));
974 ignore_rest_of_line ();
977 *val
= exp
.X_add_number
;
982 /* Register parsing. */
984 /* Generic register parser. CCP points to what should be the
985 beginning of a register name. If it is indeed a valid register
986 name, advance CCP over it and return the reg_entry structure;
987 otherwise return NULL. Does not issue diagnostics. */
989 static struct reg_entry
*
990 arm_reg_parse_multi (char **ccp
)
994 struct reg_entry
*reg
;
996 #ifdef REGISTER_PREFIX
997 if (*start
!= REGISTER_PREFIX
)
1001 #ifdef OPTIONAL_REGISTER_PREFIX
1002 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1007 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1012 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1014 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1024 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1025 enum arm_reg_type type
)
1027 /* Alternative syntaxes are accepted for a few register classes. */
1034 /* Generic coprocessor register names are allowed for these. */
1035 if (reg
&& reg
->type
== REG_TYPE_CN
)
1040 /* For backward compatibility, a bare number is valid here. */
1042 unsigned long processor
= strtoul (start
, ccp
, 10);
1043 if (*ccp
!= start
&& processor
<= 15)
1047 case REG_TYPE_MMXWC
:
1048 /* WC includes WCG. ??? I'm not sure this is true for all
1049 instructions that take WC registers. */
1050 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1061 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1062 return value is the register number or FAIL. */
1065 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1068 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1071 /* Do not allow a scalar (reg+index) to parse as a register. */
1072 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1075 if (reg
&& reg
->type
== type
)
1078 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1085 /* Parse a Neon type specifier. *STR should point at the leading '.'
1086 character. Does no verification at this stage that the type fits the opcode
1093 Can all be legally parsed by this function.
1095 Fills in neon_type struct pointer with parsed information, and updates STR
1096 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1097 type, FAIL if not. */
1100 parse_neon_type (struct neon_type
*type
, char **str
)
1107 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1109 enum neon_el_type thistype
= NT_untyped
;
1110 unsigned thissize
= -1u;
1117 /* Just a size without an explicit type. */
1121 switch (TOLOWER (*ptr
))
1123 case 'i': thistype
= NT_integer
; break;
1124 case 'f': thistype
= NT_float
; break;
1125 case 'p': thistype
= NT_poly
; break;
1126 case 's': thistype
= NT_signed
; break;
1127 case 'u': thistype
= NT_unsigned
; break;
1129 thistype
= NT_float
;
1134 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1140 /* .f is an abbreviation for .f32. */
1141 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1146 thissize
= strtoul (ptr
, &ptr
, 10);
1148 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1151 as_bad (_("bad size %d in type specifier"), thissize
);
1159 type
->el
[type
->elems
].type
= thistype
;
1160 type
->el
[type
->elems
].size
= thissize
;
1165 /* Empty/missing type is not a successful parse. */
1166 if (type
->elems
== 0)
1174 /* Errors may be set multiple times during parsing or bit encoding
1175 (particularly in the Neon bits), but usually the earliest error which is set
1176 will be the most meaningful. Avoid overwriting it with later (cascading)
1177 errors by calling this function. */
1180 first_error (const char *err
)
1186 /* Parse a single type, e.g. ".s32", leading period included. */
1188 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1191 struct neon_type optype
;
1195 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1197 if (optype
.elems
== 1)
1198 *vectype
= optype
.el
[0];
1201 first_error (_("only one type should be specified for operand"));
1207 first_error (_("vector type expected"));
1219 /* Special meanings for indices (which have a range of 0-7), which will fit into
1222 #define NEON_ALL_LANES 15
1223 #define NEON_INTERLEAVE_LANES 14
1225 /* Parse either a register or a scalar, with an optional type. Return the
1226 register number, and optionally fill in the actual type of the register
1227 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1228 type/index information in *TYPEINFO. */
1231 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1232 enum arm_reg_type
*rtype
,
1233 struct neon_typed_alias
*typeinfo
)
1236 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1237 struct neon_typed_alias atype
;
1238 struct neon_type_el parsetype
;
1242 atype
.eltype
.type
= NT_invtype
;
1243 atype
.eltype
.size
= -1;
1245 /* Try alternate syntax for some types of register. Note these are mutually
1246 exclusive with the Neon syntax extensions. */
1249 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1257 /* Undo polymorphism when a set of register types may be accepted. */
1258 if ((type
== REG_TYPE_NDQ
1259 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1260 || (type
== REG_TYPE_VFSD
1261 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1262 || (type
== REG_TYPE_NSDQ
1263 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1264 || reg
->type
== REG_TYPE_NQ
)))
1267 if (type
!= reg
->type
)
1273 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1275 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1277 first_error (_("can't redefine type for operand"));
1280 atype
.defined
|= NTA_HASTYPE
;
1281 atype
.eltype
= parsetype
;
1284 if (skip_past_char (&str
, '[') == SUCCESS
)
1286 if (type
!= REG_TYPE_VFD
)
1288 first_error (_("only D registers may be indexed"));
1292 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1294 first_error (_("can't change index for operand"));
1298 atype
.defined
|= NTA_HASINDEX
;
1300 if (skip_past_char (&str
, ']') == SUCCESS
)
1301 atype
.index
= NEON_ALL_LANES
;
1306 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1308 if (exp
.X_op
!= O_constant
)
1310 first_error (_("constant expression required"));
1314 if (skip_past_char (&str
, ']') == FAIL
)
1317 atype
.index
= exp
.X_add_number
;
1332 /* Like arm_reg_parse, but allow allow the following extra features:
1333 - If RTYPE is non-zero, return the (possibly restricted) type of the
1334 register (e.g. Neon double or quad reg when either has been requested).
1335 - If this is a Neon vector type with additional type information, fill
1336 in the struct pointed to by VECTYPE (if non-NULL).
1337 This function will fault on encountering a scalar.
1341 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1342 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1344 struct neon_typed_alias atype
;
1346 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1351 /* Do not allow a scalar (reg+index) to parse as a register. */
1352 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1354 first_error (_("register operand expected, but got scalar"));
1359 *vectype
= atype
.eltype
;
1366 #define NEON_SCALAR_REG(X) ((X) >> 4)
1367 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1369 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1370 have enough information to be able to do a good job bounds-checking. So, we
1371 just do easy checks here, and do further checks later. */
1374 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1378 struct neon_typed_alias atype
;
1380 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1382 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1385 if (atype
.index
== NEON_ALL_LANES
)
1387 first_error (_("scalar must have an index"));
1390 else if (atype
.index
>= 64 / elsize
)
1392 first_error (_("scalar index out of range"));
1397 *type
= atype
.eltype
;
1401 return reg
* 16 + atype
.index
;
1404 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1406 parse_reg_list (char ** strp
)
1408 char * str
= * strp
;
1412 /* We come back here if we get ranges concatenated by '+' or '|'. */
1427 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1429 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1439 first_error (_("bad range in register list"));
1443 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1445 if (range
& (1 << i
))
1447 (_("Warning: duplicated register (r%d) in register list"),
1455 if (range
& (1 << reg
))
1456 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1458 else if (reg
<= cur_reg
)
1459 as_tsktsk (_("Warning: register range not in ascending order"));
1464 while (skip_past_comma (&str
) != FAIL
1465 || (in_range
= 1, *str
++ == '-'));
1470 first_error (_("missing `}'"));
1478 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1481 if (expr
.X_op
== O_constant
)
1483 if (expr
.X_add_number
1484 != (expr
.X_add_number
& 0x0000ffff))
1486 inst
.error
= _("invalid register mask");
1490 if ((range
& expr
.X_add_number
) != 0)
1492 int regno
= range
& expr
.X_add_number
;
1495 regno
= (1 << regno
) - 1;
1497 (_("Warning: duplicated register (r%d) in register list"),
1501 range
|= expr
.X_add_number
;
1505 if (inst
.reloc
.type
!= 0)
1507 inst
.error
= _("expression too complex");
1511 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1512 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1513 inst
.reloc
.pc_rel
= 0;
1517 if (*str
== '|' || *str
== '+')
1523 while (another_range
);
1529 /* Types of registers in a list. */
1538 /* Parse a VFP register list. If the string is invalid return FAIL.
1539 Otherwise return the number of registers, and set PBASE to the first
1540 register. Parses registers of type ETYPE.
1541 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1542 - Q registers can be used to specify pairs of D registers
1543 - { } can be omitted from around a singleton register list
1544 FIXME: This is not implemented, as it would require backtracking in
1547 This could be done (the meaning isn't really ambiguous), but doesn't
1548 fit in well with the current parsing framework.
1549 - 32 D registers may be used (also true for VFPv3).
1550 FIXME: Types are ignored in these register lists, which is probably a
1554 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1559 enum arm_reg_type regtype
= 0;
1563 unsigned long mask
= 0;
1568 inst
.error
= _("expecting {");
1577 regtype
= REG_TYPE_VFS
;
1582 regtype
= REG_TYPE_VFD
;
1585 case REGLIST_NEON_D
:
1586 regtype
= REG_TYPE_NDQ
;
1590 if (etype
!= REGLIST_VFP_S
)
1592 /* VFPv3 allows 32 D registers. */
1593 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
1597 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1600 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1607 base_reg
= max_regs
;
1611 int setmask
= 1, addregs
= 1;
1613 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1615 if (new_base
== FAIL
)
1617 first_error (_(reg_expected_msgs
[regtype
]));
1621 if (new_base
>= max_regs
)
1623 first_error (_("register out of range in list"));
1627 /* Note: a value of 2 * n is returned for the register Q<n>. */
1628 if (regtype
== REG_TYPE_NQ
)
1634 if (new_base
< base_reg
)
1635 base_reg
= new_base
;
1637 if (mask
& (setmask
<< new_base
))
1639 first_error (_("invalid register list"));
1643 if ((mask
>> new_base
) != 0 && ! warned
)
1645 as_tsktsk (_("register list not in ascending order"));
1649 mask
|= setmask
<< new_base
;
1652 if (*str
== '-') /* We have the start of a range expression */
1658 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1661 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1665 if (high_range
>= max_regs
)
1667 first_error (_("register out of range in list"));
1671 if (regtype
== REG_TYPE_NQ
)
1672 high_range
= high_range
+ 1;
1674 if (high_range
<= new_base
)
1676 inst
.error
= _("register range not in ascending order");
1680 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1682 if (mask
& (setmask
<< new_base
))
1684 inst
.error
= _("invalid register list");
1688 mask
|= setmask
<< new_base
;
1693 while (skip_past_comma (&str
) != FAIL
);
1697 /* Sanity check -- should have raised a parse error above. */
1698 if (count
== 0 || count
> max_regs
)
1703 /* Final test -- the registers must be consecutive. */
1705 for (i
= 0; i
< count
; i
++)
1707 if ((mask
& (1u << i
)) == 0)
1709 inst
.error
= _("non-contiguous register range");
1719 /* True if two alias types are the same. */
1722 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1730 if (a
->defined
!= b
->defined
)
1733 if ((a
->defined
& NTA_HASTYPE
) != 0
1734 && (a
->eltype
.type
!= b
->eltype
.type
1735 || a
->eltype
.size
!= b
->eltype
.size
))
1738 if ((a
->defined
& NTA_HASINDEX
) != 0
1739 && (a
->index
!= b
->index
))
1745 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1746 The base register is put in *PBASE.
1747 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1749 The register stride (minus one) is put in bit 4 of the return value.
1750 Bits [6:5] encode the list length (minus one).
1751 The type of the list elements is put in *ELTYPE, if non-NULL. */
1753 #define NEON_LANE(X) ((X) & 0xf)
1754 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1755 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1758 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1759 struct neon_type_el
*eltype
)
1766 int leading_brace
= 0;
1767 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1769 const char *const incr_error
= "register stride must be 1 or 2";
1770 const char *const type_error
= "mismatched element/structure types in list";
1771 struct neon_typed_alias firsttype
;
1773 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1778 struct neon_typed_alias atype
;
1779 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1783 first_error (_(reg_expected_msgs
[rtype
]));
1790 if (rtype
== REG_TYPE_NQ
)
1797 else if (reg_incr
== -1)
1799 reg_incr
= getreg
- base_reg
;
1800 if (reg_incr
< 1 || reg_incr
> 2)
1802 first_error (_(incr_error
));
1806 else if (getreg
!= base_reg
+ reg_incr
* count
)
1808 first_error (_(incr_error
));
1812 if (!neon_alias_types_same (&atype
, &firsttype
))
1814 first_error (_(type_error
));
1818 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1822 struct neon_typed_alias htype
;
1823 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1825 lane
= NEON_INTERLEAVE_LANES
;
1826 else if (lane
!= NEON_INTERLEAVE_LANES
)
1828 first_error (_(type_error
));
1833 else if (reg_incr
!= 1)
1835 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1839 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1842 first_error (_(reg_expected_msgs
[rtype
]));
1845 if (!neon_alias_types_same (&htype
, &firsttype
))
1847 first_error (_(type_error
));
1850 count
+= hireg
+ dregs
- getreg
;
1854 /* If we're using Q registers, we can't use [] or [n] syntax. */
1855 if (rtype
== REG_TYPE_NQ
)
1861 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1865 else if (lane
!= atype
.index
)
1867 first_error (_(type_error
));
1871 else if (lane
== -1)
1872 lane
= NEON_INTERLEAVE_LANES
;
1873 else if (lane
!= NEON_INTERLEAVE_LANES
)
1875 first_error (_(type_error
));
1880 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1882 /* No lane set by [x]. We must be interleaving structures. */
1884 lane
= NEON_INTERLEAVE_LANES
;
1887 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1888 || (count
> 1 && reg_incr
== -1))
1890 first_error (_("error parsing element/structure list"));
1894 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
1896 first_error (_("expected }"));
1904 *eltype
= firsttype
.eltype
;
1909 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
1912 /* Parse an explicit relocation suffix on an expression. This is
1913 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1914 arm_reloc_hsh contains no entries, so this function can only
1915 succeed if there is no () after the word. Returns -1 on error,
1916 BFD_RELOC_UNUSED if there wasn't any suffix. */
1918 parse_reloc (char **str
)
1920 struct reloc_entry
*r
;
1924 return BFD_RELOC_UNUSED
;
1929 while (*q
&& *q
!= ')' && *q
!= ',')
1934 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1941 /* Directives: register aliases. */
1943 static struct reg_entry
*
1944 insert_reg_alias (char *str
, int number
, int type
)
1946 struct reg_entry
*new;
1949 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1952 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1954 /* Only warn about a redefinition if it's not defined as the
1956 else if (new->number
!= number
|| new->type
!= type
)
1957 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1962 name
= xstrdup (str
);
1963 new = xmalloc (sizeof (struct reg_entry
));
1966 new->number
= number
;
1968 new->builtin
= FALSE
;
1971 if (hash_insert (arm_reg_hsh
, name
, (PTR
) new))
1978 insert_neon_reg_alias (char *str
, int number
, int type
,
1979 struct neon_typed_alias
*atype
)
1981 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
1985 first_error (_("attempt to redefine typed alias"));
1991 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
1992 *reg
->neon
= *atype
;
1996 /* Look for the .req directive. This is of the form:
1998 new_register_name .req existing_register_name
2000 If we find one, or if it looks sufficiently like one that we want to
2001 handle any error here, return non-zero. Otherwise return zero. */
2004 create_register_alias (char * newname
, char *p
)
2006 struct reg_entry
*old
;
2007 char *oldname
, *nbuf
;
2010 /* The input scrubber ensures that whitespace after the mnemonic is
2011 collapsed to single spaces. */
2013 if (strncmp (oldname
, " .req ", 6) != 0)
2017 if (*oldname
== '\0')
2020 old
= hash_find (arm_reg_hsh
, oldname
);
2023 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2027 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2028 the desired alias name, and p points to its end. If not, then
2029 the desired alias name is in the global original_case_string. */
2030 #ifdef TC_CASE_SENSITIVE
2033 newname
= original_case_string
;
2034 nlen
= strlen (newname
);
2037 nbuf
= alloca (nlen
+ 1);
2038 memcpy (nbuf
, newname
, nlen
);
2041 /* Create aliases under the new name as stated; an all-lowercase
2042 version of the new name; and an all-uppercase version of the new
2044 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2046 for (p
= nbuf
; *p
; p
++)
2049 if (strncmp (nbuf
, newname
, nlen
))
2050 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2052 for (p
= nbuf
; *p
; p
++)
2055 if (strncmp (nbuf
, newname
, nlen
))
2056 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2061 /* Create a Neon typed/indexed register alias using directives, e.g.:
2066 These typed registers can be used instead of the types specified after the
2067 Neon mnemonic, so long as all operands given have types. Types can also be
2068 specified directly, e.g.:
2069 vadd d0.s32, d1.s32, d2.s32
2073 create_neon_reg_alias (char *newname
, char *p
)
2075 enum arm_reg_type basetype
;
2076 struct reg_entry
*basereg
;
2077 struct reg_entry mybasereg
;
2078 struct neon_type ntype
;
2079 struct neon_typed_alias typeinfo
;
2080 char *namebuf
, *nameend
;
2083 typeinfo
.defined
= 0;
2084 typeinfo
.eltype
.type
= NT_invtype
;
2085 typeinfo
.eltype
.size
= -1;
2086 typeinfo
.index
= -1;
2090 if (strncmp (p
, " .dn ", 5) == 0)
2091 basetype
= REG_TYPE_VFD
;
2092 else if (strncmp (p
, " .qn ", 5) == 0)
2093 basetype
= REG_TYPE_NQ
;
2102 basereg
= arm_reg_parse_multi (&p
);
2104 if (basereg
&& basereg
->type
!= basetype
)
2106 as_bad (_("bad type for register"));
2110 if (basereg
== NULL
)
2113 /* Try parsing as an integer. */
2114 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2115 if (exp
.X_op
!= O_constant
)
2117 as_bad (_("expression must be constant"));
2120 basereg
= &mybasereg
;
2121 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2127 typeinfo
= *basereg
->neon
;
2129 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2131 /* We got a type. */
2132 if (typeinfo
.defined
& NTA_HASTYPE
)
2134 as_bad (_("can't redefine the type of a register alias"));
2138 typeinfo
.defined
|= NTA_HASTYPE
;
2139 if (ntype
.elems
!= 1)
2141 as_bad (_("you must specify a single type only"));
2144 typeinfo
.eltype
= ntype
.el
[0];
2147 if (skip_past_char (&p
, '[') == SUCCESS
)
2150 /* We got a scalar index. */
2152 if (typeinfo
.defined
& NTA_HASINDEX
)
2154 as_bad (_("can't redefine the index of a scalar alias"));
2158 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2160 if (exp
.X_op
!= O_constant
)
2162 as_bad (_("scalar index must be constant"));
2166 typeinfo
.defined
|= NTA_HASINDEX
;
2167 typeinfo
.index
= exp
.X_add_number
;
2169 if (skip_past_char (&p
, ']') == FAIL
)
2171 as_bad (_("expecting ]"));
2176 namelen
= nameend
- newname
;
2177 namebuf
= alloca (namelen
+ 1);
2178 strncpy (namebuf
, newname
, namelen
);
2179 namebuf
[namelen
] = '\0';
2181 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2182 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2184 /* Insert name in all uppercase. */
2185 for (p
= namebuf
; *p
; p
++)
2188 if (strncmp (namebuf
, newname
, namelen
))
2189 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2190 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2192 /* Insert name in all lowercase. */
2193 for (p
= namebuf
; *p
; p
++)
2196 if (strncmp (namebuf
, newname
, namelen
))
2197 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2198 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2203 /* Should never be called, as .req goes between the alias and the
2204 register name, not at the beginning of the line. */
2206 s_req (int a ATTRIBUTE_UNUSED
)
2208 as_bad (_("invalid syntax for .req directive"));
2212 s_dn (int a ATTRIBUTE_UNUSED
)
2214 as_bad (_("invalid syntax for .dn directive"));
2218 s_qn (int a ATTRIBUTE_UNUSED
)
2220 as_bad (_("invalid syntax for .qn directive"));
2223 /* The .unreq directive deletes an alias which was previously defined
2224 by .req. For example:
2230 s_unreq (int a ATTRIBUTE_UNUSED
)
2235 name
= input_line_pointer
;
2237 while (*input_line_pointer
!= 0
2238 && *input_line_pointer
!= ' '
2239 && *input_line_pointer
!= '\n')
2240 ++input_line_pointer
;
2242 saved_char
= *input_line_pointer
;
2243 *input_line_pointer
= 0;
2246 as_bad (_("invalid syntax for .unreq directive"));
2249 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2252 as_bad (_("unknown register alias '%s'"), name
);
2253 else if (reg
->builtin
)
2254 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2258 hash_delete (arm_reg_hsh
, name
);
2259 free ((char *) reg
->name
);
2266 *input_line_pointer
= saved_char
;
2267 demand_empty_rest_of_line ();
2270 /* Directives: Instruction set selection. */
2273 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2274 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2275 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2276 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2278 static enum mstate mapstate
= MAP_UNDEFINED
;
2281 mapping_state (enum mstate state
)
2284 const char * symname
;
2287 if (mapstate
== state
)
2288 /* The mapping symbol has already been emitted.
2289 There is nothing else to do. */
2298 type
= BSF_NO_FLAGS
;
2302 type
= BSF_NO_FLAGS
;
2306 type
= BSF_NO_FLAGS
;
2314 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2316 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
2317 symbol_table_insert (symbolP
);
2318 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2323 THUMB_SET_FUNC (symbolP
, 0);
2324 ARM_SET_THUMB (symbolP
, 0);
2325 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2329 THUMB_SET_FUNC (symbolP
, 1);
2330 ARM_SET_THUMB (symbolP
, 1);
2331 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2340 #define mapping_state(x) /* nothing */
2343 /* Find the real, Thumb encoded start of a Thumb function. */
2346 find_real_start (symbolS
* symbolP
)
2349 const char * name
= S_GET_NAME (symbolP
);
2350 symbolS
* new_target
;
2352 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2353 #define STUB_NAME ".real_start_of"
2358 /* The compiler may generate BL instructions to local labels because
2359 it needs to perform a branch to a far away location. These labels
2360 do not have a corresponding ".real_start_of" label. We check
2361 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2362 the ".real_start_of" convention for nonlocal branches. */
2363 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2366 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2367 new_target
= symbol_find (real_start
);
2369 if (new_target
== NULL
)
2371 as_warn ("Failed to find real start of function: %s\n", name
);
2372 new_target
= symbolP
;
2379 opcode_select (int width
)
2386 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2387 as_bad (_("selected processor does not support THUMB opcodes"));
2390 /* No need to force the alignment, since we will have been
2391 coming from ARM mode, which is word-aligned. */
2392 record_alignment (now_seg
, 1);
2394 mapping_state (MAP_THUMB
);
2400 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2401 as_bad (_("selected processor does not support ARM opcodes"));
2406 frag_align (2, 0, 0);
2408 record_alignment (now_seg
, 1);
2410 mapping_state (MAP_ARM
);
2414 as_bad (_("invalid instruction size selected (%d)"), width
);
2419 s_arm (int ignore ATTRIBUTE_UNUSED
)
2422 demand_empty_rest_of_line ();
2426 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2429 demand_empty_rest_of_line ();
2433 s_code (int unused ATTRIBUTE_UNUSED
)
2437 temp
= get_absolute_expression ();
2442 opcode_select (temp
);
2446 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2451 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2453 /* If we are not already in thumb mode go into it, EVEN if
2454 the target processor does not support thumb instructions.
2455 This is used by gcc/config/arm/lib1funcs.asm for example
2456 to compile interworking support functions even if the
2457 target processor should not support interworking. */
2461 record_alignment (now_seg
, 1);
2464 demand_empty_rest_of_line ();
2468 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2472 /* The following label is the name/address of the start of a Thumb function.
2473 We need to know this for the interworking support. */
2474 label_is_thumb_function_name
= TRUE
;
2477 /* Perform a .set directive, but also mark the alias as
2478 being a thumb function. */
2481 s_thumb_set (int equiv
)
2483 /* XXX the following is a duplicate of the code for s_set() in read.c
2484 We cannot just call that code as we need to get at the symbol that
2491 /* Especial apologies for the random logic:
2492 This just grew, and could be parsed much more simply!
2494 name
= input_line_pointer
;
2495 delim
= get_symbol_end ();
2496 end_name
= input_line_pointer
;
2499 if (*input_line_pointer
!= ',')
2502 as_bad (_("expected comma after name \"%s\""), name
);
2504 ignore_rest_of_line ();
2508 input_line_pointer
++;
2511 if (name
[0] == '.' && name
[1] == '\0')
2513 /* XXX - this should not happen to .thumb_set. */
2517 if ((symbolP
= symbol_find (name
)) == NULL
2518 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2521 /* When doing symbol listings, play games with dummy fragments living
2522 outside the normal fragment chain to record the file and line info
2524 if (listing
& LISTING_SYMBOLS
)
2526 extern struct list_info_struct
* listing_tail
;
2527 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2529 memset (dummy_frag
, 0, sizeof (fragS
));
2530 dummy_frag
->fr_type
= rs_fill
;
2531 dummy_frag
->line
= listing_tail
;
2532 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2533 dummy_frag
->fr_symbol
= symbolP
;
2537 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2540 /* "set" symbols are local unless otherwise specified. */
2541 SF_SET_LOCAL (symbolP
);
2542 #endif /* OBJ_COFF */
2543 } /* Make a new symbol. */
2545 symbol_table_insert (symbolP
);
2550 && S_IS_DEFINED (symbolP
)
2551 && S_GET_SEGMENT (symbolP
) != reg_section
)
2552 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2554 pseudo_set (symbolP
);
2556 demand_empty_rest_of_line ();
2558 /* XXX Now we come to the Thumb specific bit of code. */
2560 THUMB_SET_FUNC (symbolP
, 1);
2561 ARM_SET_THUMB (symbolP
, 1);
2562 #if defined OBJ_ELF || defined OBJ_COFF
2563 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2567 /* Directives: Mode selection. */
2569 /* .syntax [unified|divided] - choose the new unified syntax
2570 (same for Arm and Thumb encoding, modulo slight differences in what
2571 can be represented) or the old divergent syntax for each mode. */
2573 s_syntax (int unused ATTRIBUTE_UNUSED
)
2577 name
= input_line_pointer
;
2578 delim
= get_symbol_end ();
2580 if (!strcasecmp (name
, "unified"))
2581 unified_syntax
= TRUE
;
2582 else if (!strcasecmp (name
, "divided"))
2583 unified_syntax
= FALSE
;
2586 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2589 *input_line_pointer
= delim
;
2590 demand_empty_rest_of_line ();
2593 /* Directives: sectioning and alignment. */
2595 /* Same as s_align_ptwo but align 0 => align 2. */
2598 s_align (int unused ATTRIBUTE_UNUSED
)
2602 long max_alignment
= 15;
2604 temp
= get_absolute_expression ();
2605 if (temp
> max_alignment
)
2606 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2609 as_bad (_("alignment negative. 0 assumed."));
2613 if (*input_line_pointer
== ',')
2615 input_line_pointer
++;
2616 temp_fill
= get_absolute_expression ();
2624 /* Only make a frag if we HAVE to. */
2625 if (temp
&& !need_pass_2
)
2626 frag_align (temp
, (int) temp_fill
, 0);
2627 demand_empty_rest_of_line ();
2629 record_alignment (now_seg
, temp
);
2633 s_bss (int ignore ATTRIBUTE_UNUSED
)
2635 /* We don't support putting frags in the BSS segment, we fake it by
2636 marking in_bss, then looking at s_skip for clues. */
2637 subseg_set (bss_section
, 0);
2638 demand_empty_rest_of_line ();
2639 mapping_state (MAP_DATA
);
2643 s_even (int ignore ATTRIBUTE_UNUSED
)
2645 /* Never make frag if expect extra pass. */
2647 frag_align (1, 0, 0);
2649 record_alignment (now_seg
, 1);
2651 demand_empty_rest_of_line ();
2654 /* Directives: Literal pools. */
2656 static literal_pool
*
2657 find_literal_pool (void)
2659 literal_pool
* pool
;
2661 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2663 if (pool
->section
== now_seg
2664 && pool
->sub_section
== now_subseg
)
2671 static literal_pool
*
2672 find_or_make_literal_pool (void)
2674 /* Next literal pool ID number. */
2675 static unsigned int latest_pool_num
= 1;
2676 literal_pool
* pool
;
2678 pool
= find_literal_pool ();
2682 /* Create a new pool. */
2683 pool
= xmalloc (sizeof (* pool
));
2687 pool
->next_free_entry
= 0;
2688 pool
->section
= now_seg
;
2689 pool
->sub_section
= now_subseg
;
2690 pool
->next
= list_of_pools
;
2691 pool
->symbol
= NULL
;
2693 /* Add it to the list. */
2694 list_of_pools
= pool
;
2697 /* New pools, and emptied pools, will have a NULL symbol. */
2698 if (pool
->symbol
== NULL
)
2700 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2701 (valueT
) 0, &zero_address_frag
);
2702 pool
->id
= latest_pool_num
++;
2709 /* Add the literal in the global 'inst'
2710 structure to the relevent literal pool. */
2713 add_to_lit_pool (void)
2715 literal_pool
* pool
;
2718 pool
= find_or_make_literal_pool ();
2720 /* Check if this literal value is already in the pool. */
2721 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2723 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2724 && (inst
.reloc
.exp
.X_op
== O_constant
)
2725 && (pool
->literals
[entry
].X_add_number
2726 == inst
.reloc
.exp
.X_add_number
)
2727 && (pool
->literals
[entry
].X_unsigned
2728 == inst
.reloc
.exp
.X_unsigned
))
2731 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2732 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2733 && (pool
->literals
[entry
].X_add_number
2734 == inst
.reloc
.exp
.X_add_number
)
2735 && (pool
->literals
[entry
].X_add_symbol
2736 == inst
.reloc
.exp
.X_add_symbol
)
2737 && (pool
->literals
[entry
].X_op_symbol
2738 == inst
.reloc
.exp
.X_op_symbol
))
2742 /* Do we need to create a new entry? */
2743 if (entry
== pool
->next_free_entry
)
2745 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2747 inst
.error
= _("literal pool overflow");
2751 pool
->literals
[entry
] = inst
.reloc
.exp
;
2752 pool
->next_free_entry
+= 1;
2755 inst
.reloc
.exp
.X_op
= O_symbol
;
2756 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
2757 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
2762 /* Can't use symbol_new here, so have to create a symbol and then at
2763 a later date assign it a value. Thats what these functions do. */
2766 symbol_locate (symbolS
* symbolP
,
2767 const char * name
, /* It is copied, the caller can modify. */
2768 segT segment
, /* Segment identifier (SEG_<something>). */
2769 valueT valu
, /* Symbol value. */
2770 fragS
* frag
) /* Associated fragment. */
2772 unsigned int name_length
;
2773 char * preserved_copy_of_name
;
2775 name_length
= strlen (name
) + 1; /* +1 for \0. */
2776 obstack_grow (¬es
, name
, name_length
);
2777 preserved_copy_of_name
= obstack_finish (¬es
);
2779 #ifdef tc_canonicalize_symbol_name
2780 preserved_copy_of_name
=
2781 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2784 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2786 S_SET_SEGMENT (symbolP
, segment
);
2787 S_SET_VALUE (symbolP
, valu
);
2788 symbol_clear_list_pointers (symbolP
);
2790 symbol_set_frag (symbolP
, frag
);
2792 /* Link to end of symbol chain. */
2794 extern int symbol_table_frozen
;
2796 if (symbol_table_frozen
)
2800 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
2802 obj_symbol_new_hook (symbolP
);
2804 #ifdef tc_symbol_new_hook
2805 tc_symbol_new_hook (symbolP
);
2809 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2810 #endif /* DEBUG_SYMS */
2815 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2818 literal_pool
* pool
;
2821 pool
= find_literal_pool ();
2823 || pool
->symbol
== NULL
2824 || pool
->next_free_entry
== 0)
2827 mapping_state (MAP_DATA
);
2829 /* Align pool as you have word accesses.
2830 Only make a frag if we have to. */
2832 frag_align (2, 0, 0);
2834 record_alignment (now_seg
, 2);
2836 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2838 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2839 (valueT
) frag_now_fix (), frag_now
);
2840 symbol_table_insert (pool
->symbol
);
2842 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
2844 #if defined OBJ_COFF || defined OBJ_ELF
2845 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
2848 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2849 /* First output the expression in the instruction to the pool. */
2850 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
2852 /* Mark the pool as empty. */
2853 pool
->next_free_entry
= 0;
2854 pool
->symbol
= NULL
;
2858 /* Forward declarations for functions below, in the MD interface
2860 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
2861 static valueT
create_unwind_entry (int);
2862 static void start_unwind_section (const segT
, int);
2863 static void add_unwind_opcode (valueT
, int);
2864 static void flush_pending_unwind (void);
2866 /* Directives: Data. */
2869 s_arm_elf_cons (int nbytes
)
2873 #ifdef md_flush_pending_output
2874 md_flush_pending_output ();
2877 if (is_it_end_of_statement ())
2879 demand_empty_rest_of_line ();
2883 #ifdef md_cons_align
2884 md_cons_align (nbytes
);
2887 mapping_state (MAP_DATA
);
2891 char *base
= input_line_pointer
;
2895 if (exp
.X_op
!= O_symbol
)
2896 emit_expr (&exp
, (unsigned int) nbytes
);
2899 char *before_reloc
= input_line_pointer
;
2900 reloc
= parse_reloc (&input_line_pointer
);
2903 as_bad (_("unrecognized relocation suffix"));
2904 ignore_rest_of_line ();
2907 else if (reloc
== BFD_RELOC_UNUSED
)
2908 emit_expr (&exp
, (unsigned int) nbytes
);
2911 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2912 int size
= bfd_get_reloc_size (howto
);
2914 if (reloc
== BFD_RELOC_ARM_PLT32
)
2916 as_bad (_("(plt) is only valid on branch targets"));
2917 reloc
= BFD_RELOC_UNUSED
;
2922 as_bad (_("%s relocations do not fit in %d bytes"),
2923 howto
->name
, nbytes
);
2926 /* We've parsed an expression stopping at O_symbol.
2927 But there may be more expression left now that we
2928 have parsed the relocation marker. Parse it again.
2929 XXX Surely there is a cleaner way to do this. */
2930 char *p
= input_line_pointer
;
2932 char *save_buf
= alloca (input_line_pointer
- base
);
2933 memcpy (save_buf
, base
, input_line_pointer
- base
);
2934 memmove (base
+ (input_line_pointer
- before_reloc
),
2935 base
, before_reloc
- base
);
2937 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
2939 memcpy (base
, save_buf
, p
- base
);
2941 offset
= nbytes
- size
;
2942 p
= frag_more ((int) nbytes
);
2943 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
2944 size
, &exp
, 0, reloc
);
2949 while (*input_line_pointer
++ == ',');
2951 /* Put terminator back into stream. */
2952 input_line_pointer
--;
2953 demand_empty_rest_of_line ();
2957 /* Parse a .rel31 directive. */
2960 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
2967 if (*input_line_pointer
== '1')
2968 highbit
= 0x80000000;
2969 else if (*input_line_pointer
!= '0')
2970 as_bad (_("expected 0 or 1"));
2972 input_line_pointer
++;
2973 if (*input_line_pointer
!= ',')
2974 as_bad (_("missing comma"));
2975 input_line_pointer
++;
2977 #ifdef md_flush_pending_output
2978 md_flush_pending_output ();
2981 #ifdef md_cons_align
2985 mapping_state (MAP_DATA
);
2990 md_number_to_chars (p
, highbit
, 4);
2991 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
2992 BFD_RELOC_ARM_PREL31
);
2994 demand_empty_rest_of_line ();
2997 /* Directives: AEABI stack-unwind tables. */
2999 /* Parse an unwind_fnstart directive. Simply records the current location. */
3002 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3004 demand_empty_rest_of_line ();
3005 /* Mark the start of the function. */
3006 unwind
.proc_start
= expr_build_dot ();
3008 /* Reset the rest of the unwind info. */
3009 unwind
.opcode_count
= 0;
3010 unwind
.table_entry
= NULL
;
3011 unwind
.personality_routine
= NULL
;
3012 unwind
.personality_index
= -1;
3013 unwind
.frame_size
= 0;
3014 unwind
.fp_offset
= 0;
3017 unwind
.sp_restored
= 0;
3021 /* Parse a handlerdata directive. Creates the exception handling table entry
3022 for the function. */
3025 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3027 demand_empty_rest_of_line ();
3028 if (unwind
.table_entry
)
3029 as_bad (_("dupicate .handlerdata directive"));
3031 create_unwind_entry (1);
3034 /* Parse an unwind_fnend directive. Generates the index table entry. */
3037 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3043 demand_empty_rest_of_line ();
3045 /* Add eh table entry. */
3046 if (unwind
.table_entry
== NULL
)
3047 val
= create_unwind_entry (0);
3051 /* Add index table entry. This is two words. */
3052 start_unwind_section (unwind
.saved_seg
, 1);
3053 frag_align (2, 0, 0);
3054 record_alignment (now_seg
, 2);
3056 ptr
= frag_more (8);
3057 where
= frag_now_fix () - 8;
3059 /* Self relative offset of the function start. */
3060 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3061 BFD_RELOC_ARM_PREL31
);
3063 /* Indicate dependency on EHABI-defined personality routines to the
3064 linker, if it hasn't been done already. */
3065 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3066 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3068 static const char *const name
[] = {
3069 "__aeabi_unwind_cpp_pr0",
3070 "__aeabi_unwind_cpp_pr1",
3071 "__aeabi_unwind_cpp_pr2"
3073 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3074 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3075 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3076 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3077 = marked_pr_dependency
;
3081 /* Inline exception table entry. */
3082 md_number_to_chars (ptr
+ 4, val
, 4);
3084 /* Self relative offset of the table entry. */
3085 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3086 BFD_RELOC_ARM_PREL31
);
3088 /* Restore the original section. */
3089 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3093 /* Parse an unwind_cantunwind directive. */
3096 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3098 demand_empty_rest_of_line ();
3099 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3100 as_bad (_("personality routine specified for cantunwind frame"));
3102 unwind
.personality_index
= -2;
3106 /* Parse a personalityindex directive. */
3109 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3113 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3114 as_bad (_("duplicate .personalityindex directive"));
3118 if (exp
.X_op
!= O_constant
3119 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3121 as_bad (_("bad personality routine number"));
3122 ignore_rest_of_line ();
3126 unwind
.personality_index
= exp
.X_add_number
;
3128 demand_empty_rest_of_line ();
3132 /* Parse a personality directive. */
3135 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3139 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3140 as_bad (_("duplicate .personality directive"));
3142 name
= input_line_pointer
;
3143 c
= get_symbol_end ();
3144 p
= input_line_pointer
;
3145 unwind
.personality_routine
= symbol_find_or_make (name
);
3147 demand_empty_rest_of_line ();
3151 /* Parse a directive saving core registers. */
3154 s_arm_unwind_save_core (void)
3160 range
= parse_reg_list (&input_line_pointer
);
3163 as_bad (_("expected register list"));
3164 ignore_rest_of_line ();
3168 demand_empty_rest_of_line ();
3170 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3171 into .unwind_save {..., sp...}. We aren't bothered about the value of
3172 ip because it is clobbered by calls. */
3173 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3174 && (range
& 0x3000) == 0x1000)
3176 unwind
.opcode_count
--;
3177 unwind
.sp_restored
= 0;
3178 range
= (range
| 0x2000) & ~0x1000;
3179 unwind
.pending_offset
= 0;
3185 /* See if we can use the short opcodes. These pop a block of up to 8
3186 registers starting with r4, plus maybe r14. */
3187 for (n
= 0; n
< 8; n
++)
3189 /* Break at the first non-saved register. */
3190 if ((range
& (1 << (n
+ 4))) == 0)
3193 /* See if there are any other bits set. */
3194 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3196 /* Use the long form. */
3197 op
= 0x8000 | ((range
>> 4) & 0xfff);
3198 add_unwind_opcode (op
, 2);
3202 /* Use the short form. */
3204 op
= 0xa8; /* Pop r14. */
3206 op
= 0xa0; /* Do not pop r14. */
3208 add_unwind_opcode (op
, 1);
3215 op
= 0xb100 | (range
& 0xf);
3216 add_unwind_opcode (op
, 2);
3219 /* Record the number of bytes pushed. */
3220 for (n
= 0; n
< 16; n
++)
3222 if (range
& (1 << n
))
3223 unwind
.frame_size
+= 4;
3228 /* Parse a directive saving FPA registers. */
3231 s_arm_unwind_save_fpa (int reg
)
3237 /* Get Number of registers to transfer. */
3238 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3241 exp
.X_op
= O_illegal
;
3243 if (exp
.X_op
!= O_constant
)
3245 as_bad (_("expected , <constant>"));
3246 ignore_rest_of_line ();
3250 num_regs
= exp
.X_add_number
;
3252 if (num_regs
< 1 || num_regs
> 4)
3254 as_bad (_("number of registers must be in the range [1:4]"));
3255 ignore_rest_of_line ();
3259 demand_empty_rest_of_line ();
3264 op
= 0xb4 | (num_regs
- 1);
3265 add_unwind_opcode (op
, 1);
3270 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3271 add_unwind_opcode (op
, 2);
3273 unwind
.frame_size
+= num_regs
* 12;
3277 /* Parse a directive saving VFP registers for ARMv6 and above. */
3280 s_arm_unwind_save_vfp_armv6 (void)
3285 int num_vfpv3_regs
= 0;
3286 int num_regs_below_16
;
3288 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3291 as_bad (_("expected register list"));
3292 ignore_rest_of_line ();
3296 demand_empty_rest_of_line ();
3298 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3299 than FSTMX/FLDMX-style ones). */
3301 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3303 num_vfpv3_regs
= count
;
3304 else if (start
+ count
> 16)
3305 num_vfpv3_regs
= start
+ count
- 16;
3307 if (num_vfpv3_regs
> 0)
3309 int start_offset
= start
> 16 ? start
- 16 : 0;
3310 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3311 add_unwind_opcode (op
, 2);
3314 /* Generate opcode for registers numbered in the range 0 .. 15. */
3315 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3316 assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3317 if (num_regs_below_16
> 0)
3319 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3320 add_unwind_opcode (op
, 2);
3323 unwind
.frame_size
+= count
* 8;
3327 /* Parse a directive saving VFP registers for pre-ARMv6. */
3330 s_arm_unwind_save_vfp (void)
3336 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3339 as_bad (_("expected register list"));
3340 ignore_rest_of_line ();
3344 demand_empty_rest_of_line ();
3349 op
= 0xb8 | (count
- 1);
3350 add_unwind_opcode (op
, 1);
3355 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3356 add_unwind_opcode (op
, 2);
3358 unwind
.frame_size
+= count
* 8 + 4;
3362 /* Parse a directive saving iWMMXt data registers. */
3365 s_arm_unwind_save_mmxwr (void)
3373 if (*input_line_pointer
== '{')
3374 input_line_pointer
++;
3378 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3382 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3387 as_tsktsk (_("register list not in ascending order"));
3390 if (*input_line_pointer
== '-')
3392 input_line_pointer
++;
3393 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3396 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3399 else if (reg
>= hi_reg
)
3401 as_bad (_("bad register range"));
3404 for (; reg
< hi_reg
; reg
++)
3408 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3410 if (*input_line_pointer
== '}')
3411 input_line_pointer
++;
3413 demand_empty_rest_of_line ();
3415 /* Generate any deferred opcodes because we're going to be looking at
3417 flush_pending_unwind ();
3419 for (i
= 0; i
< 16; i
++)
3421 if (mask
& (1 << i
))
3422 unwind
.frame_size
+= 8;
3425 /* Attempt to combine with a previous opcode. We do this because gcc
3426 likes to output separate unwind directives for a single block of
3428 if (unwind
.opcode_count
> 0)
3430 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3431 if ((i
& 0xf8) == 0xc0)
3434 /* Only merge if the blocks are contiguous. */
3437 if ((mask
& 0xfe00) == (1 << 9))
3439 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3440 unwind
.opcode_count
--;
3443 else if (i
== 6 && unwind
.opcode_count
>= 2)
3445 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3449 op
= 0xffff << (reg
- 1);
3451 || ((mask
& op
) == (1u << (reg
- 1))))
3453 op
= (1 << (reg
+ i
+ 1)) - 1;
3454 op
&= ~((1 << reg
) - 1);
3456 unwind
.opcode_count
-= 2;
3463 /* We want to generate opcodes in the order the registers have been
3464 saved, ie. descending order. */
3465 for (reg
= 15; reg
>= -1; reg
--)
3467 /* Save registers in blocks. */
3469 || !(mask
& (1 << reg
)))
3471 /* We found an unsaved reg. Generate opcodes to save the
3472 preceeding block. */
3478 op
= 0xc0 | (hi_reg
- 10);
3479 add_unwind_opcode (op
, 1);
3484 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3485 add_unwind_opcode (op
, 2);
3494 ignore_rest_of_line ();
3498 s_arm_unwind_save_mmxwcg (void)
3505 if (*input_line_pointer
== '{')
3506 input_line_pointer
++;
3510 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3514 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3520 as_tsktsk (_("register list not in ascending order"));
3523 if (*input_line_pointer
== '-')
3525 input_line_pointer
++;
3526 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3529 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3532 else if (reg
>= hi_reg
)
3534 as_bad (_("bad register range"));
3537 for (; reg
< hi_reg
; reg
++)
3541 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3543 if (*input_line_pointer
== '}')
3544 input_line_pointer
++;
3546 demand_empty_rest_of_line ();
3548 /* Generate any deferred opcodes because we're going to be looking at
3550 flush_pending_unwind ();
3552 for (reg
= 0; reg
< 16; reg
++)
3554 if (mask
& (1 << reg
))
3555 unwind
.frame_size
+= 4;
3558 add_unwind_opcode (op
, 2);
3561 ignore_rest_of_line ();
3565 /* Parse an unwind_save directive.
3566 If the argument is non-zero, this is a .vsave directive. */
3569 s_arm_unwind_save (int arch_v6
)
3572 struct reg_entry
*reg
;
3573 bfd_boolean had_brace
= FALSE
;
3575 /* Figure out what sort of save we have. */
3576 peek
= input_line_pointer
;
3584 reg
= arm_reg_parse_multi (&peek
);
3588 as_bad (_("register expected"));
3589 ignore_rest_of_line ();
3598 as_bad (_("FPA .unwind_save does not take a register list"));
3599 ignore_rest_of_line ();
3602 s_arm_unwind_save_fpa (reg
->number
);
3605 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
3608 s_arm_unwind_save_vfp_armv6 ();
3610 s_arm_unwind_save_vfp ();
3612 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
3613 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
3616 as_bad (_(".unwind_save does not support this kind of register"));
3617 ignore_rest_of_line ();
3622 /* Parse an unwind_movsp directive. */
3625 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
3630 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3633 as_bad (_(reg_expected_msgs
[REG_TYPE_RN
]));
3634 ignore_rest_of_line ();
3637 demand_empty_rest_of_line ();
3639 if (reg
== REG_SP
|| reg
== REG_PC
)
3641 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3645 if (unwind
.fp_reg
!= REG_SP
)
3646 as_bad (_("unexpected .unwind_movsp directive"));
3648 /* Generate opcode to restore the value. */
3650 add_unwind_opcode (op
, 1);
3652 /* Record the information for later. */
3653 unwind
.fp_reg
= reg
;
3654 unwind
.fp_offset
= unwind
.frame_size
;
3655 unwind
.sp_restored
= 1;
3658 /* Parse an unwind_pad directive. */
3661 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
3665 if (immediate_for_directive (&offset
) == FAIL
)
3670 as_bad (_("stack increment must be multiple of 4"));
3671 ignore_rest_of_line ();
3675 /* Don't generate any opcodes, just record the details for later. */
3676 unwind
.frame_size
+= offset
;
3677 unwind
.pending_offset
+= offset
;
3679 demand_empty_rest_of_line ();
3682 /* Parse an unwind_setfp directive. */
3685 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
3691 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3692 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3695 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3697 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
3699 as_bad (_("expected <reg>, <reg>"));
3700 ignore_rest_of_line ();
3704 /* Optional constant. */
3705 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3707 if (immediate_for_directive (&offset
) == FAIL
)
3713 demand_empty_rest_of_line ();
3715 if (sp_reg
!= 13 && sp_reg
!= unwind
.fp_reg
)
3717 as_bad (_("register must be either sp or set by a previous"
3718 "unwind_movsp directive"));
3722 /* Don't generate any opcodes, just record the information for later. */
3723 unwind
.fp_reg
= fp_reg
;
3726 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3728 unwind
.fp_offset
-= offset
;
3731 /* Parse an unwind_raw directive. */
3734 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
3737 /* This is an arbitrary limit. */
3738 unsigned char op
[16];
3742 if (exp
.X_op
== O_constant
3743 && skip_past_comma (&input_line_pointer
) != FAIL
)
3745 unwind
.frame_size
+= exp
.X_add_number
;
3749 exp
.X_op
= O_illegal
;
3751 if (exp
.X_op
!= O_constant
)
3753 as_bad (_("expected <offset>, <opcode>"));
3754 ignore_rest_of_line ();
3760 /* Parse the opcode. */
3765 as_bad (_("unwind opcode too long"));
3766 ignore_rest_of_line ();
3768 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
3770 as_bad (_("invalid unwind opcode"));
3771 ignore_rest_of_line ();
3774 op
[count
++] = exp
.X_add_number
;
3776 /* Parse the next byte. */
3777 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3783 /* Add the opcode bytes in reverse order. */
3785 add_unwind_opcode (op
[count
], 1);
3787 demand_empty_rest_of_line ();
3791 /* Parse a .eabi_attribute directive. */
3794 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
3797 bfd_boolean is_string
;
3804 if (exp
.X_op
!= O_constant
)
3807 tag
= exp
.X_add_number
;
3808 if (tag
== 4 || tag
== 5 || tag
== 32 || (tag
> 32 && (tag
& 1) != 0))
3813 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3815 if (tag
== 32 || !is_string
)
3818 if (exp
.X_op
!= O_constant
)
3820 as_bad (_("expected numeric constant"));
3821 ignore_rest_of_line ();
3824 i
= exp
.X_add_number
;
3826 if (tag
== Tag_compatibility
3827 && skip_past_comma (&input_line_pointer
) == FAIL
)
3829 as_bad (_("expected comma"));
3830 ignore_rest_of_line ();
3835 skip_whitespace(input_line_pointer
);
3836 if (*input_line_pointer
!= '"')
3838 input_line_pointer
++;
3839 s
= input_line_pointer
;
3840 while (*input_line_pointer
&& *input_line_pointer
!= '"')
3841 input_line_pointer
++;
3842 if (*input_line_pointer
!= '"')
3844 saved_char
= *input_line_pointer
;
3845 *input_line_pointer
= 0;
3853 if (tag
== Tag_compatibility
)
3854 elf32_arm_add_eabi_attr_compat (stdoutput
, i
, s
);
3856 elf32_arm_add_eabi_attr_string (stdoutput
, tag
, s
);
3858 elf32_arm_add_eabi_attr_int (stdoutput
, tag
, i
);
3862 *input_line_pointer
= saved_char
;
3863 input_line_pointer
++;
3865 demand_empty_rest_of_line ();
3868 as_bad (_("bad string constant"));
3869 ignore_rest_of_line ();
3872 as_bad (_("expected <tag> , <value>"));
3873 ignore_rest_of_line ();
3875 #endif /* OBJ_ELF */
3877 static void s_arm_arch (int);
3878 static void s_arm_cpu (int);
3879 static void s_arm_fpu (int);
3881 /* This table describes all the machine specific pseudo-ops the assembler
3882 has to support. The fields are:
3883 pseudo-op name without dot
3884 function to call to execute this pseudo-op
3885 Integer arg to pass to the function. */
3887 const pseudo_typeS md_pseudo_table
[] =
3889 /* Never called because '.req' does not start a line. */
3890 { "req", s_req
, 0 },
3891 /* Following two are likewise never called. */
3894 { "unreq", s_unreq
, 0 },
3895 { "bss", s_bss
, 0 },
3896 { "align", s_align
, 0 },
3897 { "arm", s_arm
, 0 },
3898 { "thumb", s_thumb
, 0 },
3899 { "code", s_code
, 0 },
3900 { "force_thumb", s_force_thumb
, 0 },
3901 { "thumb_func", s_thumb_func
, 0 },
3902 { "thumb_set", s_thumb_set
, 0 },
3903 { "even", s_even
, 0 },
3904 { "ltorg", s_ltorg
, 0 },
3905 { "pool", s_ltorg
, 0 },
3906 { "syntax", s_syntax
, 0 },
3907 { "cpu", s_arm_cpu
, 0 },
3908 { "arch", s_arm_arch
, 0 },
3909 { "fpu", s_arm_fpu
, 0 },
3911 { "word", s_arm_elf_cons
, 4 },
3912 { "long", s_arm_elf_cons
, 4 },
3913 { "rel31", s_arm_rel31
, 0 },
3914 { "fnstart", s_arm_unwind_fnstart
, 0 },
3915 { "fnend", s_arm_unwind_fnend
, 0 },
3916 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
3917 { "personality", s_arm_unwind_personality
, 0 },
3918 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
3919 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
3920 { "save", s_arm_unwind_save
, 0 },
3921 { "vsave", s_arm_unwind_save
, 1 },
3922 { "movsp", s_arm_unwind_movsp
, 0 },
3923 { "pad", s_arm_unwind_pad
, 0 },
3924 { "setfp", s_arm_unwind_setfp
, 0 },
3925 { "unwind_raw", s_arm_unwind_raw
, 0 },
3926 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
3930 { "extend", float_cons
, 'x' },
3931 { "ldouble", float_cons
, 'x' },
3932 { "packed", float_cons
, 'p' },
3936 /* Parser functions used exclusively in instruction operands. */
3938 /* Generic immediate-value read function for use in insn parsing.
3939 STR points to the beginning of the immediate (the leading #);
3940 VAL receives the value; if the value is outside [MIN, MAX]
3941 issue an error. PREFIX_OPT is true if the immediate prefix is
3945 parse_immediate (char **str
, int *val
, int min
, int max
,
3946 bfd_boolean prefix_opt
)
3949 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
3950 if (exp
.X_op
!= O_constant
)
3952 inst
.error
= _("constant expression required");
3956 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
3958 inst
.error
= _("immediate value out of range");
3962 *val
= exp
.X_add_number
;
3966 /* Less-generic immediate-value read function with the possibility of loading a
3967 big (64-bit) immediate, as required by Neon VMOV and VMVN immediate
3968 instructions. Puts the result directly in inst.operands[i]. */
3971 parse_big_immediate (char **str
, int i
)
3976 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
3978 if (exp
.X_op
== O_constant
)
3979 inst
.operands
[i
].imm
= exp
.X_add_number
;
3980 else if (exp
.X_op
== O_big
3981 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
3982 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
3984 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
3985 /* Bignums have their least significant bits in
3986 generic_bignum[0]. Make sure we put 32 bits in imm and
3987 32 bits in reg, in a (hopefully) portable way. */
3988 assert (parts
!= 0);
3989 inst
.operands
[i
].imm
= 0;
3990 for (j
= 0; j
< parts
; j
++, idx
++)
3991 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
3992 << (LITTLENUM_NUMBER_OF_BITS
* j
);
3993 inst
.operands
[i
].reg
= 0;
3994 for (j
= 0; j
< parts
; j
++, idx
++)
3995 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
3996 << (LITTLENUM_NUMBER_OF_BITS
* j
);
3997 inst
.operands
[i
].regisimm
= 1;
4007 /* Returns the pseudo-register number of an FPA immediate constant,
4008 or FAIL if there isn't a valid constant here. */
4011 parse_fpa_immediate (char ** str
)
4013 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4019 /* First try and match exact strings, this is to guarantee
4020 that some formats will work even for cross assembly. */
4022 for (i
= 0; fp_const
[i
]; i
++)
4024 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4028 *str
+= strlen (fp_const
[i
]);
4029 if (is_end_of_line
[(unsigned char) **str
])
4035 /* Just because we didn't get a match doesn't mean that the constant
4036 isn't valid, just that it is in a format that we don't
4037 automatically recognize. Try parsing it with the standard
4038 expression routines. */
4040 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4042 /* Look for a raw floating point number. */
4043 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4044 && is_end_of_line
[(unsigned char) *save_in
])
4046 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4048 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4050 if (words
[j
] != fp_values
[i
][j
])
4054 if (j
== MAX_LITTLENUMS
)
4062 /* Try and parse a more complex expression, this will probably fail
4063 unless the code uses a floating point prefix (eg "0f"). */
4064 save_in
= input_line_pointer
;
4065 input_line_pointer
= *str
;
4066 if (expression (&exp
) == absolute_section
4067 && exp
.X_op
== O_big
4068 && exp
.X_add_number
< 0)
4070 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4072 if (gen_to_words (words
, 5, (long) 15) == 0)
4074 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4076 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4078 if (words
[j
] != fp_values
[i
][j
])
4082 if (j
== MAX_LITTLENUMS
)
4084 *str
= input_line_pointer
;
4085 input_line_pointer
= save_in
;
4092 *str
= input_line_pointer
;
4093 input_line_pointer
= save_in
;
4094 inst
.error
= _("invalid FPA immediate expression");
4098 /* Returns 1 if a number has "quarter-precision" float format
4099 0baBbbbbbc defgh000 00000000 00000000. */
4102 is_quarter_float (unsigned imm
)
4104 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4105 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4108 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4109 0baBbbbbbc defgh000 00000000 00000000.
4110 The minus-zero case needs special handling, since it can't be encoded in the
4111 "quarter-precision" float format, but can nonetheless be loaded as an integer
4115 parse_qfloat_immediate (char **ccp
, int *immed
)
4118 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4120 skip_past_char (&str
, '#');
4122 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4124 unsigned fpword
= 0;
4127 /* Our FP word must be 32 bits (single-precision FP). */
4128 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4130 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4134 if (is_quarter_float (fpword
) || fpword
== 0x80000000)
4147 /* Shift operands. */
4150 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4153 struct asm_shift_name
4156 enum shift_kind kind
;
4159 /* Third argument to parse_shift. */
4160 enum parse_shift_mode
4162 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4163 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4164 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4165 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4166 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4169 /* Parse a <shift> specifier on an ARM data processing instruction.
4170 This has three forms:
4172 (LSL|LSR|ASL|ASR|ROR) Rs
4173 (LSL|LSR|ASL|ASR|ROR) #imm
4176 Note that ASL is assimilated to LSL in the instruction encoding, and
4177 RRX to ROR #0 (which cannot be written as such). */
4180 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4182 const struct asm_shift_name
*shift_name
;
4183 enum shift_kind shift
;
4188 for (p
= *str
; ISALPHA (*p
); p
++)
4193 inst
.error
= _("shift expression expected");
4197 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4199 if (shift_name
== NULL
)
4201 inst
.error
= _("shift expression expected");
4205 shift
= shift_name
->kind
;
4209 case NO_SHIFT_RESTRICT
:
4210 case SHIFT_IMMEDIATE
: break;
4212 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4213 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4215 inst
.error
= _("'LSL' or 'ASR' required");
4220 case SHIFT_LSL_IMMEDIATE
:
4221 if (shift
!= SHIFT_LSL
)
4223 inst
.error
= _("'LSL' required");
4228 case SHIFT_ASR_IMMEDIATE
:
4229 if (shift
!= SHIFT_ASR
)
4231 inst
.error
= _("'ASR' required");
4239 if (shift
!= SHIFT_RRX
)
4241 /* Whitespace can appear here if the next thing is a bare digit. */
4242 skip_whitespace (p
);
4244 if (mode
== NO_SHIFT_RESTRICT
4245 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4247 inst
.operands
[i
].imm
= reg
;
4248 inst
.operands
[i
].immisreg
= 1;
4250 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4253 inst
.operands
[i
].shift_kind
= shift
;
4254 inst
.operands
[i
].shifted
= 1;
4259 /* Parse a <shifter_operand> for an ARM data processing instruction:
4262 #<immediate>, <rotate>
4266 where <shift> is defined by parse_shift above, and <rotate> is a
4267 multiple of 2 between 0 and 30. Validation of immediate operands
4268 is deferred to md_apply_fix. */
4271 parse_shifter_operand (char **str
, int i
)
4276 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4278 inst
.operands
[i
].reg
= value
;
4279 inst
.operands
[i
].isreg
= 1;
4281 /* parse_shift will override this if appropriate */
4282 inst
.reloc
.exp
.X_op
= O_constant
;
4283 inst
.reloc
.exp
.X_add_number
= 0;
4285 if (skip_past_comma (str
) == FAIL
)
4288 /* Shift operation on register. */
4289 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4292 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4295 if (skip_past_comma (str
) == SUCCESS
)
4297 /* #x, y -- ie explicit rotation by Y. */
4298 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4301 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4303 inst
.error
= _("constant expression expected");
4307 value
= expr
.X_add_number
;
4308 if (value
< 0 || value
> 30 || value
% 2 != 0)
4310 inst
.error
= _("invalid rotation");
4313 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4315 inst
.error
= _("invalid constant");
4319 /* Convert to decoded value. md_apply_fix will put it back. */
4320 inst
.reloc
.exp
.X_add_number
4321 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4322 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4325 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4326 inst
.reloc
.pc_rel
= 0;
4330 /* Group relocation information. Each entry in the table contains the
4331 textual name of the relocation as may appear in assembler source
4332 and must end with a colon.
4333 Along with this textual name are the relocation codes to be used if
4334 the corresponding instruction is an ALU instruction (ADD or SUB only),
4335 an LDR, an LDRS, or an LDC. */
4337 struct group_reloc_table_entry
4348 /* Varieties of non-ALU group relocation. */
4355 static struct group_reloc_table_entry group_reloc_table
[] =
4356 { /* Program counter relative: */
4358 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4363 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4364 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4365 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4366 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4368 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4373 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4374 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4375 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4376 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4378 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4379 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4380 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4381 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4382 /* Section base relative */
4384 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4389 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4390 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4391 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4392 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4394 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4399 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4400 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4401 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4402 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4404 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4405 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4406 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4407 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4409 /* Given the address of a pointer pointing to the textual name of a group
4410 relocation as may appear in assembler source, attempt to find its details
4411 in group_reloc_table. The pointer will be updated to the character after
4412 the trailing colon. On failure, FAIL will be returned; SUCCESS
4413 otherwise. On success, *entry will be updated to point at the relevant
4414 group_reloc_table entry. */
4417 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4420 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4422 int length
= strlen (group_reloc_table
[i
].name
);
4424 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0 &&
4425 (*str
)[length
] == ':')
4427 *out
= &group_reloc_table
[i
];
4428 *str
+= (length
+ 1);
4436 /* Parse a <shifter_operand> for an ARM data processing instruction
4437 (as for parse_shifter_operand) where group relocations are allowed:
4440 #<immediate>, <rotate>
4441 #:<group_reloc>:<expression>
4445 where <group_reloc> is one of the strings defined in group_reloc_table.
4446 The hashes are optional.
4448 Everything else is as for parse_shifter_operand. */
4450 static parse_operand_result
4451 parse_shifter_operand_group_reloc (char **str
, int i
)
4453 /* Determine if we have the sequence of characters #: or just :
4454 coming next. If we do, then we check for a group relocation.
4455 If we don't, punt the whole lot to parse_shifter_operand. */
4457 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4458 || (*str
)[0] == ':')
4460 struct group_reloc_table_entry
*entry
;
4462 if ((*str
)[0] == '#')
4467 /* Try to parse a group relocation. Anything else is an error. */
4468 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4470 inst
.error
= _("unknown group relocation");
4471 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4474 /* We now have the group relocation table entry corresponding to
4475 the name in the assembler source. Next, we parse the expression. */
4476 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4477 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4479 /* Record the relocation type (always the ALU variant here). */
4480 inst
.reloc
.type
= entry
->alu_code
;
4481 assert (inst
.reloc
.type
!= 0);
4483 return PARSE_OPERAND_SUCCESS
;
4486 return parse_shifter_operand (str
, i
) == SUCCESS
4487 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4489 /* Never reached. */
4492 /* Parse all forms of an ARM address expression. Information is written
4493 to inst.operands[i] and/or inst.reloc.
4495 Preindexed addressing (.preind=1):
4497 [Rn, #offset] .reg=Rn .reloc.exp=offset
4498 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4499 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4500 .shift_kind=shift .reloc.exp=shift_imm
4502 These three may have a trailing ! which causes .writeback to be set also.
4504 Postindexed addressing (.postind=1, .writeback=1):
4506 [Rn], #offset .reg=Rn .reloc.exp=offset
4507 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4508 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4509 .shift_kind=shift .reloc.exp=shift_imm
4511 Unindexed addressing (.preind=0, .postind=0):
4513 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4517 [Rn]{!} shorthand for [Rn,#0]{!}
4518 =immediate .isreg=0 .reloc.exp=immediate
4519 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4521 It is the caller's responsibility to check for addressing modes not
4522 supported by the instruction, and to set inst.reloc.type. */
4524 static parse_operand_result
4525 parse_address_main (char **str
, int i
, int group_relocations
,
4526 group_reloc_type group_type
)
4531 if (skip_past_char (&p
, '[') == FAIL
)
4533 if (skip_past_char (&p
, '=') == FAIL
)
4535 /* bare address - translate to PC-relative offset */
4536 inst
.reloc
.pc_rel
= 1;
4537 inst
.operands
[i
].reg
= REG_PC
;
4538 inst
.operands
[i
].isreg
= 1;
4539 inst
.operands
[i
].preind
= 1;
4541 /* else a load-constant pseudo op, no special treatment needed here */
4543 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4544 return PARSE_OPERAND_FAIL
;
4547 return PARSE_OPERAND_SUCCESS
;
4550 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4552 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4553 return PARSE_OPERAND_FAIL
;
4555 inst
.operands
[i
].reg
= reg
;
4556 inst
.operands
[i
].isreg
= 1;
4558 if (skip_past_comma (&p
) == SUCCESS
)
4560 inst
.operands
[i
].preind
= 1;
4563 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4565 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4567 inst
.operands
[i
].imm
= reg
;
4568 inst
.operands
[i
].immisreg
= 1;
4570 if (skip_past_comma (&p
) == SUCCESS
)
4571 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4572 return PARSE_OPERAND_FAIL
;
4574 else if (skip_past_char (&p
, ':') == SUCCESS
)
4576 /* FIXME: '@' should be used here, but it's filtered out by generic
4577 code before we get to see it here. This may be subject to
4580 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4581 if (exp
.X_op
!= O_constant
)
4583 inst
.error
= _("alignment must be constant");
4584 return PARSE_OPERAND_FAIL
;
4586 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4587 inst
.operands
[i
].immisalign
= 1;
4588 /* Alignments are not pre-indexes. */
4589 inst
.operands
[i
].preind
= 0;
4593 if (inst
.operands
[i
].negative
)
4595 inst
.operands
[i
].negative
= 0;
4599 if (group_relocations
&&
4600 ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
4603 struct group_reloc_table_entry
*entry
;
4605 /* Skip over the #: or : sequence. */
4611 /* Try to parse a group relocation. Anything else is an
4613 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
4615 inst
.error
= _("unknown group relocation");
4616 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4619 /* We now have the group relocation table entry corresponding to
4620 the name in the assembler source. Next, we parse the
4622 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4623 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4625 /* Record the relocation type. */
4629 inst
.reloc
.type
= entry
->ldr_code
;
4633 inst
.reloc
.type
= entry
->ldrs_code
;
4637 inst
.reloc
.type
= entry
->ldc_code
;
4644 if (inst
.reloc
.type
== 0)
4646 inst
.error
= _("this group relocation is not allowed on this instruction");
4647 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4651 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4652 return PARSE_OPERAND_FAIL
;
4656 if (skip_past_char (&p
, ']') == FAIL
)
4658 inst
.error
= _("']' expected");
4659 return PARSE_OPERAND_FAIL
;
4662 if (skip_past_char (&p
, '!') == SUCCESS
)
4663 inst
.operands
[i
].writeback
= 1;
4665 else if (skip_past_comma (&p
) == SUCCESS
)
4667 if (skip_past_char (&p
, '{') == SUCCESS
)
4669 /* [Rn], {expr} - unindexed, with option */
4670 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
4671 0, 255, TRUE
) == FAIL
)
4672 return PARSE_OPERAND_FAIL
;
4674 if (skip_past_char (&p
, '}') == FAIL
)
4676 inst
.error
= _("'}' expected at end of 'option' field");
4677 return PARSE_OPERAND_FAIL
;
4679 if (inst
.operands
[i
].preind
)
4681 inst
.error
= _("cannot combine index with option");
4682 return PARSE_OPERAND_FAIL
;
4685 return PARSE_OPERAND_SUCCESS
;
4689 inst
.operands
[i
].postind
= 1;
4690 inst
.operands
[i
].writeback
= 1;
4692 if (inst
.operands
[i
].preind
)
4694 inst
.error
= _("cannot combine pre- and post-indexing");
4695 return PARSE_OPERAND_FAIL
;
4699 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4701 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4703 /* We might be using the immediate for alignment already. If we
4704 are, OR the register number into the low-order bits. */
4705 if (inst
.operands
[i
].immisalign
)
4706 inst
.operands
[i
].imm
|= reg
;
4708 inst
.operands
[i
].imm
= reg
;
4709 inst
.operands
[i
].immisreg
= 1;
4711 if (skip_past_comma (&p
) == SUCCESS
)
4712 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4713 return PARSE_OPERAND_FAIL
;
4717 if (inst
.operands
[i
].negative
)
4719 inst
.operands
[i
].negative
= 0;
4722 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4723 return PARSE_OPERAND_FAIL
;
4728 /* If at this point neither .preind nor .postind is set, we have a
4729 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4730 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
4732 inst
.operands
[i
].preind
= 1;
4733 inst
.reloc
.exp
.X_op
= O_constant
;
4734 inst
.reloc
.exp
.X_add_number
= 0;
4737 return PARSE_OPERAND_SUCCESS
;
4741 parse_address (char **str
, int i
)
4743 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
4747 static parse_operand_result
4748 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
4750 return parse_address_main (str
, i
, 1, type
);
4753 /* Parse an operand for a MOVW or MOVT instruction. */
4755 parse_half (char **str
)
4760 skip_past_char (&p
, '#');
4761 if (strncasecmp (p
, ":lower16:", 9) == 0)
4762 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
4763 else if (strncasecmp (p
, ":upper16:", 9) == 0)
4764 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
4766 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4772 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4775 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4777 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4779 inst
.error
= _("constant expression expected");
4782 if (inst
.reloc
.exp
.X_add_number
< 0
4783 || inst
.reloc
.exp
.X_add_number
> 0xffff)
4785 inst
.error
= _("immediate value out of range");
4793 /* Miscellaneous. */
4795 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4796 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4798 parse_psr (char **str
)
4801 unsigned long psr_field
;
4802 const struct asm_psr
*psr
;
4805 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4806 feature for ease of use and backwards compatibility. */
4808 if (strncasecmp (p
, "SPSR", 4) == 0)
4809 psr_field
= SPSR_BIT
;
4810 else if (strncasecmp (p
, "CPSR", 4) == 0)
4817 while (ISALNUM (*p
) || *p
== '_');
4819 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
4830 /* A suffix follows. */
4836 while (ISALNUM (*p
) || *p
== '_');
4838 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
4842 psr_field
|= psr
->field
;
4847 goto error
; /* Garbage after "[CS]PSR". */
4849 psr_field
|= (PSR_c
| PSR_f
);
4855 inst
.error
= _("flag for {c}psr instruction expected");
4859 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4860 value suitable for splatting into the AIF field of the instruction. */
4863 parse_cps_flags (char **str
)
4872 case '\0': case ',':
4875 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
4876 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
4877 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
4880 inst
.error
= _("unrecognized CPS flag");
4885 if (saw_a_flag
== 0)
4887 inst
.error
= _("missing CPS flags");
4895 /* Parse an endian specifier ("BE" or "LE", case insensitive);
4896 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4899 parse_endian_specifier (char **str
)
4904 if (strncasecmp (s
, "BE", 2))
4906 else if (strncasecmp (s
, "LE", 2))
4910 inst
.error
= _("valid endian specifiers are be or le");
4914 if (ISALNUM (s
[2]) || s
[2] == '_')
4916 inst
.error
= _("valid endian specifiers are be or le");
4921 return little_endian
;
4924 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
4925 value suitable for poking into the rotate field of an sxt or sxta
4926 instruction, or FAIL on error. */
4929 parse_ror (char **str
)
4934 if (strncasecmp (s
, "ROR", 3) == 0)
4938 inst
.error
= _("missing rotation field after comma");
4942 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
4947 case 0: *str
= s
; return 0x0;
4948 case 8: *str
= s
; return 0x1;
4949 case 16: *str
= s
; return 0x2;
4950 case 24: *str
= s
; return 0x3;
4953 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
4958 /* Parse a conditional code (from conds[] below). The value returned is in the
4959 range 0 .. 14, or FAIL. */
4961 parse_cond (char **str
)
4964 const struct asm_cond
*c
;
4967 while (ISALPHA (*q
))
4970 c
= hash_find_n (arm_cond_hsh
, p
, q
- p
);
4973 inst
.error
= _("condition required");
4981 /* Parse an option for a barrier instruction. Returns the encoding for the
4984 parse_barrier (char **str
)
4987 const struct asm_barrier_opt
*o
;
4990 while (ISALPHA (*q
))
4993 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
5001 /* Parse the operands of a table branch instruction. Similar to a memory
5004 parse_tb (char **str
)
5009 if (skip_past_char (&p
, '[') == FAIL
)
5011 inst
.error
= _("'[' expected");
5015 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5017 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5020 inst
.operands
[0].reg
= reg
;
5022 if (skip_past_comma (&p
) == FAIL
)
5024 inst
.error
= _("',' expected");
5028 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5030 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5033 inst
.operands
[0].imm
= reg
;
5035 if (skip_past_comma (&p
) == SUCCESS
)
5037 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5039 if (inst
.reloc
.exp
.X_add_number
!= 1)
5041 inst
.error
= _("invalid shift");
5044 inst
.operands
[0].shifted
= 1;
5047 if (skip_past_char (&p
, ']') == FAIL
)
5049 inst
.error
= _("']' expected");
5056 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5057 information on the types the operands can take and how they are encoded.
5058 Up to four operands may be read; this function handles setting the
5059 ".present" field for each read operand itself.
5060 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5061 else returns FAIL. */
5064 parse_neon_mov (char **str
, int *which_operand
)
5066 int i
= *which_operand
, val
;
5067 enum arm_reg_type rtype
;
5069 struct neon_type_el optype
;
5071 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5073 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5074 inst
.operands
[i
].reg
= val
;
5075 inst
.operands
[i
].isscalar
= 1;
5076 inst
.operands
[i
].vectype
= optype
;
5077 inst
.operands
[i
++].present
= 1;
5079 if (skip_past_comma (&ptr
) == FAIL
)
5082 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5085 inst
.operands
[i
].reg
= val
;
5086 inst
.operands
[i
].isreg
= 1;
5087 inst
.operands
[i
].present
= 1;
5089 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5092 /* Cases 0, 1, 2, 3, 5 (D only). */
5093 if (skip_past_comma (&ptr
) == FAIL
)
5096 inst
.operands
[i
].reg
= val
;
5097 inst
.operands
[i
].isreg
= 1;
5098 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5099 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5100 inst
.operands
[i
].isvec
= 1;
5101 inst
.operands
[i
].vectype
= optype
;
5102 inst
.operands
[i
++].present
= 1;
5104 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5106 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5107 Case 13: VMOV <Sd>, <Rm> */
5108 inst
.operands
[i
].reg
= val
;
5109 inst
.operands
[i
].isreg
= 1;
5110 inst
.operands
[i
].present
= 1;
5112 if (rtype
== REG_TYPE_NQ
)
5114 first_error (_("can't use Neon quad register here"));
5117 else if (rtype
!= REG_TYPE_VFS
)
5120 if (skip_past_comma (&ptr
) == FAIL
)
5122 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5124 inst
.operands
[i
].reg
= val
;
5125 inst
.operands
[i
].isreg
= 1;
5126 inst
.operands
[i
].present
= 1;
5129 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5130 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5131 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5132 Case 10: VMOV.F32 <Sd>, #<imm>
5133 Case 11: VMOV.F64 <Dd>, #<imm> */
5135 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5136 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5137 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5139 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5142 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5143 Case 1: VMOV<c><q> <Dd>, <Dm>
5144 Case 8: VMOV.F32 <Sd>, <Sm>
5145 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5147 inst
.operands
[i
].reg
= val
;
5148 inst
.operands
[i
].isreg
= 1;
5149 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5150 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5151 inst
.operands
[i
].isvec
= 1;
5152 inst
.operands
[i
].vectype
= optype
;
5153 inst
.operands
[i
].present
= 1;
5155 if (skip_past_comma (&ptr
) == SUCCESS
)
5160 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5163 inst
.operands
[i
].reg
= val
;
5164 inst
.operands
[i
].isreg
= 1;
5165 inst
.operands
[i
++].present
= 1;
5167 if (skip_past_comma (&ptr
) == FAIL
)
5170 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5173 inst
.operands
[i
].reg
= val
;
5174 inst
.operands
[i
].isreg
= 1;
5175 inst
.operands
[i
++].present
= 1;
5180 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5184 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5187 inst
.operands
[i
].reg
= val
;
5188 inst
.operands
[i
].isreg
= 1;
5189 inst
.operands
[i
++].present
= 1;
5191 if (skip_past_comma (&ptr
) == FAIL
)
5194 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5196 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5197 inst
.operands
[i
].reg
= val
;
5198 inst
.operands
[i
].isscalar
= 1;
5199 inst
.operands
[i
].present
= 1;
5200 inst
.operands
[i
].vectype
= optype
;
5202 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5204 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5205 inst
.operands
[i
].reg
= val
;
5206 inst
.operands
[i
].isreg
= 1;
5207 inst
.operands
[i
++].present
= 1;
5209 if (skip_past_comma (&ptr
) == FAIL
)
5212 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5215 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5219 inst
.operands
[i
].reg
= val
;
5220 inst
.operands
[i
].isreg
= 1;
5221 inst
.operands
[i
].isvec
= 1;
5222 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5223 inst
.operands
[i
].vectype
= optype
;
5224 inst
.operands
[i
].present
= 1;
5226 if (rtype
== REG_TYPE_VFS
)
5230 if (skip_past_comma (&ptr
) == FAIL
)
5232 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5235 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5238 inst
.operands
[i
].reg
= val
;
5239 inst
.operands
[i
].isreg
= 1;
5240 inst
.operands
[i
].isvec
= 1;
5241 inst
.operands
[i
].issingle
= 1;
5242 inst
.operands
[i
].vectype
= optype
;
5243 inst
.operands
[i
].present
= 1;
5246 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5250 inst
.operands
[i
].reg
= val
;
5251 inst
.operands
[i
].isreg
= 1;
5252 inst
.operands
[i
].isvec
= 1;
5253 inst
.operands
[i
].issingle
= 1;
5254 inst
.operands
[i
].vectype
= optype
;
5255 inst
.operands
[i
++].present
= 1;
5260 first_error (_("parse error"));
5264 /* Successfully parsed the operands. Update args. */
5270 first_error (_("expected comma"));
5274 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5278 /* Matcher codes for parse_operands. */
5279 enum operand_parse_code
5281 OP_stop
, /* end of line */
5283 OP_RR
, /* ARM register */
5284 OP_RRnpc
, /* ARM register, not r15 */
5285 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5286 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5287 OP_RCP
, /* Coprocessor number */
5288 OP_RCN
, /* Coprocessor register */
5289 OP_RF
, /* FPA register */
5290 OP_RVS
, /* VFP single precision register */
5291 OP_RVD
, /* VFP double precision register (0..15) */
5292 OP_RND
, /* Neon double precision register (0..31) */
5293 OP_RNQ
, /* Neon quad precision register */
5294 OP_RVSD
, /* VFP single or double precision register */
5295 OP_RNDQ
, /* Neon double or quad precision register */
5296 OP_RNSDQ
, /* Neon single, double or quad precision register */
5297 OP_RNSC
, /* Neon scalar D[X] */
5298 OP_RVC
, /* VFP control register */
5299 OP_RMF
, /* Maverick F register */
5300 OP_RMD
, /* Maverick D register */
5301 OP_RMFX
, /* Maverick FX register */
5302 OP_RMDX
, /* Maverick DX register */
5303 OP_RMAX
, /* Maverick AX register */
5304 OP_RMDS
, /* Maverick DSPSC register */
5305 OP_RIWR
, /* iWMMXt wR register */
5306 OP_RIWC
, /* iWMMXt wC register */
5307 OP_RIWG
, /* iWMMXt wCG register */
5308 OP_RXA
, /* XScale accumulator register */
5310 OP_REGLST
, /* ARM register list */
5311 OP_VRSLST
, /* VFP single-precision register list */
5312 OP_VRDLST
, /* VFP double-precision register list */
5313 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5314 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5315 OP_NSTRLST
, /* Neon element/structure list */
5317 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5318 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5319 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5320 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5321 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5322 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5323 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5324 OP_VMOV
, /* Neon VMOV operands. */
5325 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5326 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5328 OP_I0
, /* immediate zero */
5329 OP_I7
, /* immediate value 0 .. 7 */
5330 OP_I15
, /* 0 .. 15 */
5331 OP_I16
, /* 1 .. 16 */
5332 OP_I16z
, /* 0 .. 16 */
5333 OP_I31
, /* 0 .. 31 */
5334 OP_I31w
, /* 0 .. 31, optional trailing ! */
5335 OP_I32
, /* 1 .. 32 */
5336 OP_I32z
, /* 0 .. 32 */
5337 OP_I63
, /* 0 .. 63 */
5338 OP_I63s
, /* -64 .. 63 */
5339 OP_I64
, /* 1 .. 64 */
5340 OP_I64z
, /* 0 .. 64 */
5341 OP_I255
, /* 0 .. 255 */
5343 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5344 OP_I7b
, /* 0 .. 7 */
5345 OP_I15b
, /* 0 .. 15 */
5346 OP_I31b
, /* 0 .. 31 */
5348 OP_SH
, /* shifter operand */
5349 OP_SHG
, /* shifter operand with possible group relocation */
5350 OP_ADDR
, /* Memory address expression (any mode) */
5351 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5352 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5353 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5354 OP_EXP
, /* arbitrary expression */
5355 OP_EXPi
, /* same, with optional immediate prefix */
5356 OP_EXPr
, /* same, with optional relocation suffix */
5357 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5359 OP_CPSF
, /* CPS flags */
5360 OP_ENDI
, /* Endianness specifier */
5361 OP_PSR
, /* CPSR/SPSR mask for msr */
5362 OP_COND
, /* conditional code */
5363 OP_TB
, /* Table branch. */
5365 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5366 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5368 OP_RRnpc_I0
, /* ARM register or literal 0 */
5369 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5370 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5371 OP_RF_IF
, /* FPA register or immediate */
5372 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5374 /* Optional operands. */
5375 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5376 OP_oI31b
, /* 0 .. 31 */
5377 OP_oI32b
, /* 1 .. 32 */
5378 OP_oIffffb
, /* 0 .. 65535 */
5379 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5381 OP_oRR
, /* ARM register */
5382 OP_oRRnpc
, /* ARM register, not the PC */
5383 OP_oRND
, /* Optional Neon double precision register */
5384 OP_oRNQ
, /* Optional Neon quad precision register */
5385 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5386 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5387 OP_oSHll
, /* LSL immediate */
5388 OP_oSHar
, /* ASR immediate */
5389 OP_oSHllar
, /* LSL or ASR immediate */
5390 OP_oROR
, /* ROR 0/8/16/24 */
5391 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5393 OP_FIRST_OPTIONAL
= OP_oI7b
5396 /* Generic instruction operand parser. This does no encoding and no
5397 semantic validation; it merely squirrels values away in the inst
5398 structure. Returns SUCCESS or FAIL depending on whether the
5399 specified grammar matched. */
5401 parse_operands (char *str
, const unsigned char *pattern
)
5403 unsigned const char *upat
= pattern
;
5404 char *backtrack_pos
= 0;
5405 const char *backtrack_error
= 0;
5406 int i
, val
, backtrack_index
= 0;
5407 enum arm_reg_type rtype
;
5408 parse_operand_result result
;
5410 #define po_char_or_fail(chr) do { \
5411 if (skip_past_char (&str, chr) == FAIL) \
5415 #define po_reg_or_fail(regtype) do { \
5416 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5417 &inst.operands[i].vectype); \
5420 first_error (_(reg_expected_msgs[regtype])); \
5423 inst.operands[i].reg = val; \
5424 inst.operands[i].isreg = 1; \
5425 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5426 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5427 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5428 || rtype == REG_TYPE_VFD \
5429 || rtype == REG_TYPE_NQ); \
5432 #define po_reg_or_goto(regtype, label) do { \
5433 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5434 &inst.operands[i].vectype); \
5438 inst.operands[i].reg = val; \
5439 inst.operands[i].isreg = 1; \
5440 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5441 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5442 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5443 || rtype == REG_TYPE_VFD \
5444 || rtype == REG_TYPE_NQ); \
5447 #define po_imm_or_fail(min, max, popt) do { \
5448 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5450 inst.operands[i].imm = val; \
5453 #define po_scalar_or_goto(elsz, label) do { \
5454 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5457 inst.operands[i].reg = val; \
5458 inst.operands[i].isscalar = 1; \
5461 #define po_misc_or_fail(expr) do { \
5466 #define po_misc_or_fail_no_backtrack(expr) do { \
5468 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5469 backtrack_pos = 0; \
5470 if (result != PARSE_OPERAND_SUCCESS) \
5474 skip_whitespace (str
);
5476 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5478 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5480 /* Remember where we are in case we need to backtrack. */
5481 assert (!backtrack_pos
);
5482 backtrack_pos
= str
;
5483 backtrack_error
= inst
.error
;
5484 backtrack_index
= i
;
5488 po_char_or_fail (',');
5496 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5497 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5498 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5499 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5500 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5501 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5503 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5504 case OP_RVC
: po_reg_or_fail (REG_TYPE_VFC
); break;
5505 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5506 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5507 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5508 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5509 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5510 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5511 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5512 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5513 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5514 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5516 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5518 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5519 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5521 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5523 /* Neon scalar. Using an element size of 8 means that some invalid
5524 scalars are accepted here, so deal with those in later code. */
5525 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5527 /* WARNING: We can expand to two operands here. This has the potential
5528 to totally confuse the backtracking mechanism! It will be OK at
5529 least as long as we don't try to use optional args as well,
5533 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
5535 skip_past_comma (&str
);
5536 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
5539 /* Optional register operand was omitted. Unfortunately, it's in
5540 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5541 here (this is a bit grotty). */
5542 inst
.operands
[i
] = inst
.operands
[i
-1];
5543 inst
.operands
[i
-1].present
= 0;
5546 /* Immediate gets verified properly later, so accept any now. */
5547 po_imm_or_fail (INT_MIN
, INT_MAX
, TRUE
);
5553 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
5556 po_imm_or_fail (0, 0, TRUE
);
5561 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
5566 po_scalar_or_goto (8, try_rr
);
5569 po_reg_or_fail (REG_TYPE_RN
);
5575 po_scalar_or_goto (8, try_nsdq
);
5578 po_reg_or_fail (REG_TYPE_NSDQ
);
5584 po_scalar_or_goto (8, try_ndq
);
5587 po_reg_or_fail (REG_TYPE_NDQ
);
5593 po_scalar_or_goto (8, try_vfd
);
5596 po_reg_or_fail (REG_TYPE_VFD
);
5601 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5602 not careful then bad things might happen. */
5603 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
5608 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
5611 /* There's a possibility of getting a 64-bit immediate here, so
5612 we need special handling. */
5613 if (parse_big_immediate (&str
, i
) == FAIL
)
5615 inst
.error
= _("immediate value is out of range");
5623 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
5626 po_imm_or_fail (0, 63, TRUE
);
5631 po_char_or_fail ('[');
5632 po_reg_or_fail (REG_TYPE_RN
);
5633 po_char_or_fail (']');
5637 po_reg_or_fail (REG_TYPE_RN
);
5638 if (skip_past_char (&str
, '!') == SUCCESS
)
5639 inst
.operands
[i
].writeback
= 1;
5643 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
5644 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
5645 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
5646 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
5647 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
5648 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
5649 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
5650 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
5651 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
5652 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
5653 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
5654 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
5656 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
5658 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
5659 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
5661 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
5662 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
5663 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
5665 /* Immediate variants */
5667 po_char_or_fail ('{');
5668 po_imm_or_fail (0, 255, TRUE
);
5669 po_char_or_fail ('}');
5673 /* The expression parser chokes on a trailing !, so we have
5674 to find it first and zap it. */
5677 while (*s
&& *s
!= ',')
5682 inst
.operands
[i
].writeback
= 1;
5684 po_imm_or_fail (0, 31, TRUE
);
5692 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5697 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5702 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5704 if (inst
.reloc
.exp
.X_op
== O_symbol
)
5706 val
= parse_reloc (&str
);
5709 inst
.error
= _("unrecognized relocation suffix");
5712 else if (val
!= BFD_RELOC_UNUSED
)
5714 inst
.operands
[i
].imm
= val
;
5715 inst
.operands
[i
].hasreloc
= 1;
5720 /* Operand for MOVW or MOVT. */
5722 po_misc_or_fail (parse_half (&str
));
5725 /* Register or expression */
5726 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
5727 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
5729 /* Register or immediate */
5730 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
5731 I0
: po_imm_or_fail (0, 0, FALSE
); break;
5733 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
5735 if (!is_immediate_prefix (*str
))
5738 val
= parse_fpa_immediate (&str
);
5741 /* FPA immediates are encoded as registers 8-15.
5742 parse_fpa_immediate has already applied the offset. */
5743 inst
.operands
[i
].reg
= val
;
5744 inst
.operands
[i
].isreg
= 1;
5747 /* Two kinds of register */
5750 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5751 if (rege
->type
!= REG_TYPE_MMXWR
5752 && rege
->type
!= REG_TYPE_MMXWC
5753 && rege
->type
!= REG_TYPE_MMXWCG
)
5755 inst
.error
= _("iWMMXt data or control register expected");
5758 inst
.operands
[i
].reg
= rege
->number
;
5759 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
5764 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
5765 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
5766 case OP_oROR
: val
= parse_ror (&str
); break;
5767 case OP_PSR
: val
= parse_psr (&str
); break;
5768 case OP_COND
: val
= parse_cond (&str
); break;
5769 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
5772 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
5773 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
5776 val
= parse_psr (&str
);
5780 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
5783 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5785 if (strncasecmp (str
, "APSR_", 5) == 0)
5792 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
5793 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
5794 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
5795 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
5796 default: found
= 16;
5800 inst
.operands
[i
].isvec
= 1;
5807 po_misc_or_fail (parse_tb (&str
));
5810 /* Register lists */
5812 val
= parse_reg_list (&str
);
5815 inst
.operands
[1].writeback
= 1;
5821 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
5825 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
5829 /* Allow Q registers too. */
5830 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5835 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5837 inst
.operands
[i
].issingle
= 1;
5842 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5847 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
5848 &inst
.operands
[i
].vectype
);
5851 /* Addressing modes */
5853 po_misc_or_fail (parse_address (&str
, i
));
5857 po_misc_or_fail_no_backtrack (
5858 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
5862 po_misc_or_fail_no_backtrack (
5863 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
5867 po_misc_or_fail_no_backtrack (
5868 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
5872 po_misc_or_fail (parse_shifter_operand (&str
, i
));
5876 po_misc_or_fail_no_backtrack (
5877 parse_shifter_operand_group_reloc (&str
, i
));
5881 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
5885 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
5889 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
5893 as_fatal ("unhandled operand code %d", upat
[i
]);
5896 /* Various value-based sanity checks and shared operations. We
5897 do not signal immediate failures for the register constraints;
5898 this allows a syntax error to take precedence. */
5906 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
5907 inst
.error
= BAD_PC
;
5925 inst
.operands
[i
].imm
= val
;
5932 /* If we get here, this operand was successfully parsed. */
5933 inst
.operands
[i
].present
= 1;
5937 inst
.error
= BAD_ARGS
;
5942 /* The parse routine should already have set inst.error, but set a
5943 defaut here just in case. */
5945 inst
.error
= _("syntax error");
5949 /* Do not backtrack over a trailing optional argument that
5950 absorbed some text. We will only fail again, with the
5951 'garbage following instruction' error message, which is
5952 probably less helpful than the current one. */
5953 if (backtrack_index
== i
&& backtrack_pos
!= str
5954 && upat
[i
+1] == OP_stop
)
5957 inst
.error
= _("syntax error");
5961 /* Try again, skipping the optional argument at backtrack_pos. */
5962 str
= backtrack_pos
;
5963 inst
.error
= backtrack_error
;
5964 inst
.operands
[backtrack_index
].present
= 0;
5965 i
= backtrack_index
;
5969 /* Check that we have parsed all the arguments. */
5970 if (*str
!= '\0' && !inst
.error
)
5971 inst
.error
= _("garbage following instruction");
5973 return inst
.error
? FAIL
: SUCCESS
;
5976 #undef po_char_or_fail
5977 #undef po_reg_or_fail
5978 #undef po_reg_or_goto
5979 #undef po_imm_or_fail
5980 #undef po_scalar_or_fail
5982 /* Shorthand macro for instruction encoding functions issuing errors. */
5983 #define constraint(expr, err) do { \
5991 /* Functions for operand encoding. ARM, then Thumb. */
5993 #define rotate_left(v, n) (v << n | v >> (32 - n))
5995 /* If VAL can be encoded in the immediate field of an ARM instruction,
5996 return the encoded form. Otherwise, return FAIL. */
5999 encode_arm_immediate (unsigned int val
)
6003 for (i
= 0; i
< 32; i
+= 2)
6004 if ((a
= rotate_left (val
, i
)) <= 0xff)
6005 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6010 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6011 return the encoded form. Otherwise, return FAIL. */
6013 encode_thumb32_immediate (unsigned int val
)
6020 for (i
= 1; i
<= 24; i
++)
6023 if ((val
& ~(0xff << i
)) == 0)
6024 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6028 if (val
== ((a
<< 16) | a
))
6030 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6034 if (val
== ((a
<< 16) | a
))
6035 return 0x200 | (a
>> 8);
6039 /* Encode a VFP SP or DP register number into inst.instruction. */
6042 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6044 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6047 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
6050 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6053 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6058 first_error (_("D register out of range for selected VFP version"));
6066 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6070 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6074 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6078 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6082 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6086 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6094 /* Encode a <shift> in an ARM-format instruction. The immediate,
6095 if any, is handled by md_apply_fix. */
6097 encode_arm_shift (int i
)
6099 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6100 inst
.instruction
|= SHIFT_ROR
<< 5;
6103 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6104 if (inst
.operands
[i
].immisreg
)
6106 inst
.instruction
|= SHIFT_BY_REG
;
6107 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6110 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6115 encode_arm_shifter_operand (int i
)
6117 if (inst
.operands
[i
].isreg
)
6119 inst
.instruction
|= inst
.operands
[i
].reg
;
6120 encode_arm_shift (i
);
6123 inst
.instruction
|= INST_IMMEDIATE
;
6126 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6128 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6130 assert (inst
.operands
[i
].isreg
);
6131 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6133 if (inst
.operands
[i
].preind
)
6137 inst
.error
= _("instruction does not accept preindexed addressing");
6140 inst
.instruction
|= PRE_INDEX
;
6141 if (inst
.operands
[i
].writeback
)
6142 inst
.instruction
|= WRITE_BACK
;
6145 else if (inst
.operands
[i
].postind
)
6147 assert (inst
.operands
[i
].writeback
);
6149 inst
.instruction
|= WRITE_BACK
;
6151 else /* unindexed - only for coprocessor */
6153 inst
.error
= _("instruction does not accept unindexed addressing");
6157 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6158 && (((inst
.instruction
& 0x000f0000) >> 16)
6159 == ((inst
.instruction
& 0x0000f000) >> 12)))
6160 as_warn ((inst
.instruction
& LOAD_BIT
)
6161 ? _("destination register same as write-back base")
6162 : _("source register same as write-back base"));
6165 /* inst.operands[i] was set up by parse_address. Encode it into an
6166 ARM-format mode 2 load or store instruction. If is_t is true,
6167 reject forms that cannot be used with a T instruction (i.e. not
6170 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6172 encode_arm_addr_mode_common (i
, is_t
);
6174 if (inst
.operands
[i
].immisreg
)
6176 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6177 inst
.instruction
|= inst
.operands
[i
].imm
;
6178 if (!inst
.operands
[i
].negative
)
6179 inst
.instruction
|= INDEX_UP
;
6180 if (inst
.operands
[i
].shifted
)
6182 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6183 inst
.instruction
|= SHIFT_ROR
<< 5;
6186 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6187 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6191 else /* immediate offset in inst.reloc */
6193 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6194 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6198 /* inst.operands[i] was set up by parse_address. Encode it into an
6199 ARM-format mode 3 load or store instruction. Reject forms that
6200 cannot be used with such instructions. If is_t is true, reject
6201 forms that cannot be used with a T instruction (i.e. not
6204 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6206 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6208 inst
.error
= _("instruction does not accept scaled register index");
6212 encode_arm_addr_mode_common (i
, is_t
);
6214 if (inst
.operands
[i
].immisreg
)
6216 inst
.instruction
|= inst
.operands
[i
].imm
;
6217 if (!inst
.operands
[i
].negative
)
6218 inst
.instruction
|= INDEX_UP
;
6220 else /* immediate offset in inst.reloc */
6222 inst
.instruction
|= HWOFFSET_IMM
;
6223 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6224 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6228 /* inst.operands[i] was set up by parse_address. Encode it into an
6229 ARM-format instruction. Reject all forms which cannot be encoded
6230 into a coprocessor load/store instruction. If wb_ok is false,
6231 reject use of writeback; if unind_ok is false, reject use of
6232 unindexed addressing. If reloc_override is not 0, use it instead
6233 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6234 (in which case it is preserved). */
6237 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6239 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6241 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6243 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6245 assert (!inst
.operands
[i
].writeback
);
6248 inst
.error
= _("instruction does not support unindexed addressing");
6251 inst
.instruction
|= inst
.operands
[i
].imm
;
6252 inst
.instruction
|= INDEX_UP
;
6256 if (inst
.operands
[i
].preind
)
6257 inst
.instruction
|= PRE_INDEX
;
6259 if (inst
.operands
[i
].writeback
)
6261 if (inst
.operands
[i
].reg
== REG_PC
)
6263 inst
.error
= _("pc may not be used with write-back");
6268 inst
.error
= _("instruction does not support writeback");
6271 inst
.instruction
|= WRITE_BACK
;
6275 inst
.reloc
.type
= reloc_override
;
6276 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6277 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6278 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6281 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6283 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6289 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6290 Determine whether it can be performed with a move instruction; if
6291 it can, convert inst.instruction to that move instruction and
6292 return 1; if it can't, convert inst.instruction to a literal-pool
6293 load and return 0. If this is not a valid thing to do in the
6294 current context, set inst.error and return 1.
6296 inst.operands[i] describes the destination register. */
6299 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6304 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6308 if ((inst
.instruction
& tbit
) == 0)
6310 inst
.error
= _("invalid pseudo operation");
6313 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6315 inst
.error
= _("constant expression expected");
6318 if (inst
.reloc
.exp
.X_op
== O_constant
)
6322 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6324 /* This can be done with a mov(1) instruction. */
6325 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6326 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6332 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6335 /* This can be done with a mov instruction. */
6336 inst
.instruction
&= LITERAL_MASK
;
6337 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6338 inst
.instruction
|= value
& 0xfff;
6342 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6345 /* This can be done with a mvn instruction. */
6346 inst
.instruction
&= LITERAL_MASK
;
6347 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6348 inst
.instruction
|= value
& 0xfff;
6354 if (add_to_lit_pool () == FAIL
)
6356 inst
.error
= _("literal pool insertion failed");
6359 inst
.operands
[1].reg
= REG_PC
;
6360 inst
.operands
[1].isreg
= 1;
6361 inst
.operands
[1].preind
= 1;
6362 inst
.reloc
.pc_rel
= 1;
6363 inst
.reloc
.type
= (thumb_p
6364 ? BFD_RELOC_ARM_THUMB_OFFSET
6366 ? BFD_RELOC_ARM_HWLITERAL
6367 : BFD_RELOC_ARM_LITERAL
));
6371 /* Functions for instruction encoding, sorted by subarchitecture.
6372 First some generics; their names are taken from the conventional
6373 bit positions for register arguments in ARM format instructions. */
6383 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6389 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6390 inst
.instruction
|= inst
.operands
[1].reg
;
6396 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6397 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6403 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6404 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6410 unsigned Rn
= inst
.operands
[2].reg
;
6411 /* Enforce restrictions on SWP instruction. */
6412 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6413 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6414 _("Rn must not overlap other operands"));
6415 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6416 inst
.instruction
|= inst
.operands
[1].reg
;
6417 inst
.instruction
|= Rn
<< 16;
6423 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6424 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6425 inst
.instruction
|= inst
.operands
[2].reg
;
6431 inst
.instruction
|= inst
.operands
[0].reg
;
6432 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6433 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6439 inst
.instruction
|= inst
.operands
[0].imm
;
6445 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6446 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6449 /* ARM instructions, in alphabetical order by function name (except
6450 that wrapper functions appear immediately after the function they
6453 /* This is a pseudo-op of the form "adr rd, label" to be converted
6454 into a relative address of the form "add rd, pc, #label-.-8". */
6459 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6461 /* Frag hacking will turn this into a sub instruction if the offset turns
6462 out to be negative. */
6463 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6464 inst
.reloc
.pc_rel
= 1;
6465 inst
.reloc
.exp
.X_add_number
-= 8;
6468 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6469 into a relative address of the form:
6470 add rd, pc, #low(label-.-8)"
6471 add rd, rd, #high(label-.-8)" */
6476 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6478 /* Frag hacking will turn this into a sub instruction if the offset turns
6479 out to be negative. */
6480 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6481 inst
.reloc
.pc_rel
= 1;
6482 inst
.size
= INSN_SIZE
* 2;
6483 inst
.reloc
.exp
.X_add_number
-= 8;
6489 if (!inst
.operands
[1].present
)
6490 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6491 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6492 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6493 encode_arm_shifter_operand (2);
6499 if (inst
.operands
[0].present
)
6501 constraint ((inst
.instruction
& 0xf0) != 0x40
6502 && inst
.operands
[0].imm
!= 0xf,
6503 "bad barrier type");
6504 inst
.instruction
|= inst
.operands
[0].imm
;
6507 inst
.instruction
|= 0xf;
6513 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6514 constraint (msb
> 32, _("bit-field extends past end of register"));
6515 /* The instruction encoding stores the LSB and MSB,
6516 not the LSB and width. */
6517 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6518 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
6519 inst
.instruction
|= (msb
- 1) << 16;
6527 /* #0 in second position is alternative syntax for bfc, which is
6528 the same instruction but with REG_PC in the Rm field. */
6529 if (!inst
.operands
[1].isreg
)
6530 inst
.operands
[1].reg
= REG_PC
;
6532 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6533 constraint (msb
> 32, _("bit-field extends past end of register"));
6534 /* The instruction encoding stores the LSB and MSB,
6535 not the LSB and width. */
6536 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6537 inst
.instruction
|= inst
.operands
[1].reg
;
6538 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6539 inst
.instruction
|= (msb
- 1) << 16;
6545 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6546 _("bit-field extends past end of register"));
6547 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6548 inst
.instruction
|= inst
.operands
[1].reg
;
6549 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6550 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
6553 /* ARM V5 breakpoint instruction (argument parse)
6554 BKPT <16 bit unsigned immediate>
6555 Instruction is not conditional.
6556 The bit pattern given in insns[] has the COND_ALWAYS condition,
6557 and it is an error if the caller tried to override that. */
6562 /* Top 12 of 16 bits to bits 19:8. */
6563 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
6565 /* Bottom 4 of 16 bits to bits 3:0. */
6566 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
6570 encode_branch (int default_reloc
)
6572 if (inst
.operands
[0].hasreloc
)
6574 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
6575 _("the only suffix valid here is '(plt)'"));
6576 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
6580 inst
.reloc
.type
= default_reloc
;
6582 inst
.reloc
.pc_rel
= 1;
6589 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6590 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6593 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6600 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6602 if (inst
.cond
== COND_ALWAYS
)
6603 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6605 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6609 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6612 /* ARM V5 branch-link-exchange instruction (argument parse)
6613 BLX <target_addr> ie BLX(1)
6614 BLX{<condition>} <Rm> ie BLX(2)
6615 Unfortunately, there are two different opcodes for this mnemonic.
6616 So, the insns[].value is not used, and the code here zaps values
6617 into inst.instruction.
6618 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6623 if (inst
.operands
[0].isreg
)
6625 /* Arg is a register; the opcode provided by insns[] is correct.
6626 It is not illegal to do "blx pc", just useless. */
6627 if (inst
.operands
[0].reg
== REG_PC
)
6628 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6630 inst
.instruction
|= inst
.operands
[0].reg
;
6634 /* Arg is an address; this instruction cannot be executed
6635 conditionally, and the opcode must be adjusted. */
6636 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
6637 inst
.instruction
= 0xfa000000;
6639 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6640 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6643 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
6650 if (inst
.operands
[0].reg
== REG_PC
)
6651 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6653 inst
.instruction
|= inst
.operands
[0].reg
;
6657 /* ARM v5TEJ. Jump to Jazelle code. */
6662 if (inst
.operands
[0].reg
== REG_PC
)
6663 as_tsktsk (_("use of r15 in bxj is not really useful"));
6665 inst
.instruction
|= inst
.operands
[0].reg
;
6668 /* Co-processor data operation:
6669 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6670 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6674 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6675 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
6676 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6677 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6678 inst
.instruction
|= inst
.operands
[4].reg
;
6679 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6685 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6686 encode_arm_shifter_operand (1);
6689 /* Transfer between coprocessor and ARM registers.
6690 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6695 No special properties. */
6700 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6701 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
6702 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6703 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6704 inst
.instruction
|= inst
.operands
[4].reg
;
6705 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6708 /* Transfer between coprocessor register and pair of ARM registers.
6709 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6714 Two XScale instructions are special cases of these:
6716 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6717 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6719 Result unpredicatable if Rd or Rn is R15. */
6724 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6725 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
6726 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6727 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6728 inst
.instruction
|= inst
.operands
[4].reg
;
6734 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
6735 inst
.instruction
|= inst
.operands
[1].imm
;
6741 inst
.instruction
|= inst
.operands
[0].imm
;
6747 /* There is no IT instruction in ARM mode. We
6748 process it but do not generate code for it. */
6755 int base_reg
= inst
.operands
[0].reg
;
6756 int range
= inst
.operands
[1].imm
;
6758 inst
.instruction
|= base_reg
<< 16;
6759 inst
.instruction
|= range
;
6761 if (inst
.operands
[1].writeback
)
6762 inst
.instruction
|= LDM_TYPE_2_OR_3
;
6764 if (inst
.operands
[0].writeback
)
6766 inst
.instruction
|= WRITE_BACK
;
6767 /* Check for unpredictable uses of writeback. */
6768 if (inst
.instruction
& LOAD_BIT
)
6770 /* Not allowed in LDM type 2. */
6771 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
6772 && ((range
& (1 << REG_PC
)) == 0))
6773 as_warn (_("writeback of base register is UNPREDICTABLE"));
6774 /* Only allowed if base reg not in list for other types. */
6775 else if (range
& (1 << base_reg
))
6776 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6780 /* Not allowed for type 2. */
6781 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
6782 as_warn (_("writeback of base register is UNPREDICTABLE"));
6783 /* Only allowed if base reg not in list, or first in list. */
6784 else if ((range
& (1 << base_reg
))
6785 && (range
& ((1 << base_reg
) - 1)))
6786 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6791 /* ARMv5TE load-consecutive (argument parse)
6800 constraint (inst
.operands
[0].reg
% 2 != 0,
6801 _("first destination register must be even"));
6802 constraint (inst
.operands
[1].present
6803 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6804 _("can only load two consecutive registers"));
6805 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6806 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
6808 if (!inst
.operands
[1].present
)
6809 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6811 if (inst
.instruction
& LOAD_BIT
)
6813 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6814 register and the first register written; we have to diagnose
6815 overlap between the base and the second register written here. */
6817 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
6818 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
6819 as_warn (_("base register written back, and overlaps "
6820 "second destination register"));
6822 /* For an index-register load, the index register must not overlap the
6823 destination (even if not write-back). */
6824 else if (inst
.operands
[2].immisreg
6825 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
6826 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
6827 as_warn (_("index register overlaps destination register"));
6830 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6831 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
6837 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
6838 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
6839 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
6840 || inst
.operands
[1].negative
6841 /* This can arise if the programmer has written
6843 or if they have mistakenly used a register name as the last
6846 It is very difficult to distinguish between these two cases
6847 because "rX" might actually be a label. ie the register
6848 name has been occluded by a symbol of the same name. So we
6849 just generate a general 'bad addressing mode' type error
6850 message and leave it up to the programmer to discover the
6851 true cause and fix their mistake. */
6852 || (inst
.operands
[1].reg
== REG_PC
),
6855 constraint (inst
.reloc
.exp
.X_op
!= O_constant
6856 || inst
.reloc
.exp
.X_add_number
!= 0,
6857 _("offset must be zero in ARM encoding"));
6859 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6860 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6861 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6867 constraint (inst
.operands
[0].reg
% 2 != 0,
6868 _("even register required"));
6869 constraint (inst
.operands
[1].present
6870 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6871 _("can only load two consecutive registers"));
6872 /* If op 1 were present and equal to PC, this function wouldn't
6873 have been called in the first place. */
6874 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6876 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6877 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6883 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6884 if (!inst
.operands
[1].isreg
)
6885 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
6887 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
6893 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
6895 if (inst
.operands
[1].preind
)
6897 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
6898 inst
.reloc
.exp
.X_add_number
!= 0,
6899 _("this instruction requires a post-indexed address"));
6901 inst
.operands
[1].preind
= 0;
6902 inst
.operands
[1].postind
= 1;
6903 inst
.operands
[1].writeback
= 1;
6905 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6906 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
6909 /* Halfword and signed-byte load/store operations. */
6914 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6915 if (!inst
.operands
[1].isreg
)
6916 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
6918 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
6924 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
6926 if (inst
.operands
[1].preind
)
6928 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
6929 inst
.reloc
.exp
.X_add_number
!= 0,
6930 _("this instruction requires a post-indexed address"));
6932 inst
.operands
[1].preind
= 0;
6933 inst
.operands
[1].postind
= 1;
6934 inst
.operands
[1].writeback
= 1;
6936 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6937 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
6940 /* Co-processor register load/store.
6941 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
6945 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6946 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6947 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
6953 /* This restriction does not apply to mls (nor to mla in v6, but
6954 that's hard to detect at present). */
6955 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
6956 && !(inst
.instruction
& 0x00400000))
6957 as_tsktsk (_("rd and rm should be different in mla"));
6959 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6960 inst
.instruction
|= inst
.operands
[1].reg
;
6961 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
6962 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
6969 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6970 encode_arm_shifter_operand (1);
6973 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
6980 top
= (inst
.instruction
& 0x00400000) != 0;
6981 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
6982 _(":lower16: not allowed this instruction"));
6983 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
6984 _(":upper16: not allowed instruction"));
6985 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6986 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6988 imm
= inst
.reloc
.exp
.X_add_number
;
6989 /* The value is in two pieces: 0:11, 16:19. */
6990 inst
.instruction
|= (imm
& 0x00000fff);
6991 inst
.instruction
|= (imm
& 0x0000f000) << 4;
6995 static void do_vfp_nsyn_opcode (const char *);
6998 do_vfp_nsyn_mrs (void)
7000 if (inst
.operands
[0].isvec
)
7002 if (inst
.operands
[1].reg
!= 1)
7003 first_error (_("operand 1 must be FPSCR"));
7004 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7005 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7006 do_vfp_nsyn_opcode ("fmstat");
7008 else if (inst
.operands
[1].isvec
)
7009 do_vfp_nsyn_opcode ("fmrx");
7017 do_vfp_nsyn_msr (void)
7019 if (inst
.operands
[0].isvec
)
7020 do_vfp_nsyn_opcode ("fmxr");
7030 if (do_vfp_nsyn_mrs () == SUCCESS
)
7033 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7034 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7036 _("'CPSR' or 'SPSR' expected"));
7037 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7038 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7041 /* Two possible forms:
7042 "{C|S}PSR_<field>, Rm",
7043 "{C|S}PSR_f, #expression". */
7048 if (do_vfp_nsyn_msr () == SUCCESS
)
7051 inst
.instruction
|= inst
.operands
[0].imm
;
7052 if (inst
.operands
[1].isreg
)
7053 inst
.instruction
|= inst
.operands
[1].reg
;
7056 inst
.instruction
|= INST_IMMEDIATE
;
7057 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7058 inst
.reloc
.pc_rel
= 0;
7065 if (!inst
.operands
[2].present
)
7066 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7067 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7068 inst
.instruction
|= inst
.operands
[1].reg
;
7069 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7071 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7072 as_tsktsk (_("rd and rm should be different in mul"));
7075 /* Long Multiply Parser
7076 UMULL RdLo, RdHi, Rm, Rs
7077 SMULL RdLo, RdHi, Rm, Rs
7078 UMLAL RdLo, RdHi, Rm, Rs
7079 SMLAL RdLo, RdHi, Rm, Rs. */
7084 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7085 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7086 inst
.instruction
|= inst
.operands
[2].reg
;
7087 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7089 /* rdhi, rdlo and rm must all be different. */
7090 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7091 || inst
.operands
[0].reg
== inst
.operands
[2].reg
7092 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7093 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7099 if (inst
.operands
[0].present
)
7101 /* Architectural NOP hints are CPSR sets with no bits selected. */
7102 inst
.instruction
&= 0xf0000000;
7103 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
7107 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7108 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7109 Condition defaults to COND_ALWAYS.
7110 Error if Rd, Rn or Rm are R15. */
7115 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7116 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7117 inst
.instruction
|= inst
.operands
[2].reg
;
7118 if (inst
.operands
[3].present
)
7119 encode_arm_shift (3);
7122 /* ARM V6 PKHTB (Argument Parse). */
7127 if (!inst
.operands
[3].present
)
7129 /* If the shift specifier is omitted, turn the instruction
7130 into pkhbt rd, rm, rn. */
7131 inst
.instruction
&= 0xfff00010;
7132 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7133 inst
.instruction
|= inst
.operands
[1].reg
;
7134 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7138 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7139 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7140 inst
.instruction
|= inst
.operands
[2].reg
;
7141 encode_arm_shift (3);
7145 /* ARMv5TE: Preload-Cache
7149 Syntactically, like LDR with B=1, W=0, L=1. */
7154 constraint (!inst
.operands
[0].isreg
,
7155 _("'[' expected after PLD mnemonic"));
7156 constraint (inst
.operands
[0].postind
,
7157 _("post-indexed expression used in preload instruction"));
7158 constraint (inst
.operands
[0].writeback
,
7159 _("writeback used in preload instruction"));
7160 constraint (!inst
.operands
[0].preind
,
7161 _("unindexed addressing used in preload instruction"));
7162 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7165 /* ARMv7: PLI <addr_mode> */
7169 constraint (!inst
.operands
[0].isreg
,
7170 _("'[' expected after PLI mnemonic"));
7171 constraint (inst
.operands
[0].postind
,
7172 _("post-indexed expression used in preload instruction"));
7173 constraint (inst
.operands
[0].writeback
,
7174 _("writeback used in preload instruction"));
7175 constraint (!inst
.operands
[0].preind
,
7176 _("unindexed addressing used in preload instruction"));
7177 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7178 inst
.instruction
&= ~PRE_INDEX
;
7184 inst
.operands
[1] = inst
.operands
[0];
7185 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7186 inst
.operands
[0].isreg
= 1;
7187 inst
.operands
[0].writeback
= 1;
7188 inst
.operands
[0].reg
= REG_SP
;
7192 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7193 word at the specified address and the following word
7195 Unconditionally executed.
7196 Error if Rn is R15. */
7201 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7202 if (inst
.operands
[0].writeback
)
7203 inst
.instruction
|= WRITE_BACK
;
7206 /* ARM V6 ssat (argument parse). */
7211 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7212 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7213 inst
.instruction
|= inst
.operands
[2].reg
;
7215 if (inst
.operands
[3].present
)
7216 encode_arm_shift (3);
7219 /* ARM V6 usat (argument parse). */
7224 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7225 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7226 inst
.instruction
|= inst
.operands
[2].reg
;
7228 if (inst
.operands
[3].present
)
7229 encode_arm_shift (3);
7232 /* ARM V6 ssat16 (argument parse). */
7237 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7238 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7239 inst
.instruction
|= inst
.operands
[2].reg
;
7245 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7246 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7247 inst
.instruction
|= inst
.operands
[2].reg
;
7250 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7251 preserving the other bits.
7253 setend <endian_specifier>, where <endian_specifier> is either
7259 if (inst
.operands
[0].imm
)
7260 inst
.instruction
|= 0x200;
7266 unsigned int Rm
= (inst
.operands
[1].present
7267 ? inst
.operands
[1].reg
7268 : inst
.operands
[0].reg
);
7270 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7271 inst
.instruction
|= Rm
;
7272 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7274 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7275 inst
.instruction
|= SHIFT_BY_REG
;
7278 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7284 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7285 inst
.reloc
.pc_rel
= 0;
7291 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7292 inst
.reloc
.pc_rel
= 0;
7295 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7296 SMLAxy{cond} Rd,Rm,Rs,Rn
7297 SMLAWy{cond} Rd,Rm,Rs,Rn
7298 Error if any register is R15. */
7303 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7304 inst
.instruction
|= inst
.operands
[1].reg
;
7305 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7306 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7309 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7310 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7311 Error if any register is R15.
7312 Warning if Rdlo == Rdhi. */
7317 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7318 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7319 inst
.instruction
|= inst
.operands
[2].reg
;
7320 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7322 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7323 as_tsktsk (_("rdhi and rdlo must be different"));
7326 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7327 SMULxy{cond} Rd,Rm,Rs
7328 Error if any register is R15. */
7333 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7334 inst
.instruction
|= inst
.operands
[1].reg
;
7335 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7338 /* ARM V6 srs (argument parse). */
7343 inst
.instruction
|= inst
.operands
[0].imm
;
7344 if (inst
.operands
[0].writeback
)
7345 inst
.instruction
|= WRITE_BACK
;
7348 /* ARM V6 strex (argument parse). */
7353 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7354 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7355 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7356 || inst
.operands
[2].negative
7357 /* See comment in do_ldrex(). */
7358 || (inst
.operands
[2].reg
== REG_PC
),
7361 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7362 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7364 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7365 || inst
.reloc
.exp
.X_add_number
!= 0,
7366 _("offset must be zero in ARM encoding"));
7368 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7369 inst
.instruction
|= inst
.operands
[1].reg
;
7370 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7371 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7377 constraint (inst
.operands
[1].reg
% 2 != 0,
7378 _("even register required"));
7379 constraint (inst
.operands
[2].present
7380 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7381 _("can only store two consecutive registers"));
7382 /* If op 2 were present and equal to PC, this function wouldn't
7383 have been called in the first place. */
7384 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7386 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7387 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7388 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7391 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7392 inst
.instruction
|= inst
.operands
[1].reg
;
7393 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7396 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7397 extends it to 32-bits, and adds the result to a value in another
7398 register. You can specify a rotation by 0, 8, 16, or 24 bits
7399 before extracting the 16-bit value.
7400 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7401 Condition defaults to COND_ALWAYS.
7402 Error if any register uses R15. */
7407 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7408 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7409 inst
.instruction
|= inst
.operands
[2].reg
;
7410 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
7415 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7416 Condition defaults to COND_ALWAYS.
7417 Error if any register uses R15. */
7422 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7423 inst
.instruction
|= inst
.operands
[1].reg
;
7424 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
7427 /* VFP instructions. In a logical order: SP variant first, monad
7428 before dyad, arithmetic then move then load/store. */
7431 do_vfp_sp_monadic (void)
7433 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7434 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7438 do_vfp_sp_dyadic (void)
7440 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7441 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7442 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7446 do_vfp_sp_compare_z (void)
7448 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7452 do_vfp_dp_sp_cvt (void)
7454 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7455 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7459 do_vfp_sp_dp_cvt (void)
7461 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7462 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7466 do_vfp_reg_from_sp (void)
7468 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7469 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7473 do_vfp_reg2_from_sp2 (void)
7475 constraint (inst
.operands
[2].imm
!= 2,
7476 _("only two consecutive VFP SP registers allowed here"));
7477 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7478 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7479 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7483 do_vfp_sp_from_reg (void)
7485 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
7486 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7490 do_vfp_sp2_from_reg2 (void)
7492 constraint (inst
.operands
[0].imm
!= 2,
7493 _("only two consecutive VFP SP registers allowed here"));
7494 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
7495 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7496 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7500 do_vfp_sp_ldst (void)
7502 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7503 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7507 do_vfp_dp_ldst (void)
7509 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7510 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7515 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
7517 if (inst
.operands
[0].writeback
)
7518 inst
.instruction
|= WRITE_BACK
;
7520 constraint (ldstm_type
!= VFP_LDSTMIA
,
7521 _("this addressing mode requires base-register writeback"));
7522 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7523 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
7524 inst
.instruction
|= inst
.operands
[1].imm
;
7528 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
7532 if (inst
.operands
[0].writeback
)
7533 inst
.instruction
|= WRITE_BACK
;
7535 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
7536 _("this addressing mode requires base-register writeback"));
7538 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7539 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7541 count
= inst
.operands
[1].imm
<< 1;
7542 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
7545 inst
.instruction
|= count
;
7549 do_vfp_sp_ldstmia (void)
7551 vfp_sp_ldstm (VFP_LDSTMIA
);
7555 do_vfp_sp_ldstmdb (void)
7557 vfp_sp_ldstm (VFP_LDSTMDB
);
7561 do_vfp_dp_ldstmia (void)
7563 vfp_dp_ldstm (VFP_LDSTMIA
);
7567 do_vfp_dp_ldstmdb (void)
7569 vfp_dp_ldstm (VFP_LDSTMDB
);
7573 do_vfp_xp_ldstmia (void)
7575 vfp_dp_ldstm (VFP_LDSTMIAX
);
7579 do_vfp_xp_ldstmdb (void)
7581 vfp_dp_ldstm (VFP_LDSTMDBX
);
7585 do_vfp_dp_rd_rm (void)
7587 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7588 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7592 do_vfp_dp_rn_rd (void)
7594 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
7595 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7599 do_vfp_dp_rd_rn (void)
7601 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7602 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7606 do_vfp_dp_rd_rn_rm (void)
7608 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7609 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7610 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
7616 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7620 do_vfp_dp_rm_rd_rn (void)
7622 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
7623 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7624 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
7627 /* VFPv3 instructions. */
7629 do_vfp_sp_const (void)
7631 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7632 inst
.instruction
|= (inst
.operands
[1].imm
& 15) << 16;
7633 inst
.instruction
|= (inst
.operands
[1].imm
>> 4);
7637 do_vfp_dp_const (void)
7639 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7640 inst
.instruction
|= (inst
.operands
[1].imm
& 15) << 16;
7641 inst
.instruction
|= (inst
.operands
[1].imm
>> 4);
7645 vfp_conv (int srcsize
)
7647 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
7648 inst
.instruction
|= (immbits
& 1) << 5;
7649 inst
.instruction
|= (immbits
>> 1);
7653 do_vfp_sp_conv_16 (void)
7655 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7660 do_vfp_dp_conv_16 (void)
7662 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7667 do_vfp_sp_conv_32 (void)
7669 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7674 do_vfp_dp_conv_32 (void)
7676 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7681 /* FPA instructions. Also in a logical order. */
7686 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7687 inst
.instruction
|= inst
.operands
[1].reg
;
7691 do_fpa_ldmstm (void)
7693 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7694 switch (inst
.operands
[1].imm
)
7696 case 1: inst
.instruction
|= CP_T_X
; break;
7697 case 2: inst
.instruction
|= CP_T_Y
; break;
7698 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
7703 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
7705 /* The instruction specified "ea" or "fd", so we can only accept
7706 [Rn]{!}. The instruction does not really support stacking or
7707 unstacking, so we have to emulate these by setting appropriate
7708 bits and offsets. */
7709 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7710 || inst
.reloc
.exp
.X_add_number
!= 0,
7711 _("this instruction does not support indexing"));
7713 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
7714 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
7716 if (!(inst
.instruction
& INDEX_UP
))
7717 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
7719 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
7721 inst
.operands
[2].preind
= 0;
7722 inst
.operands
[2].postind
= 1;
7726 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7730 /* iWMMXt instructions: strictly in alphabetical order. */
7733 do_iwmmxt_tandorc (void)
7735 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
7739 do_iwmmxt_textrc (void)
7741 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7742 inst
.instruction
|= inst
.operands
[1].imm
;
7746 do_iwmmxt_textrm (void)
7748 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7749 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7750 inst
.instruction
|= inst
.operands
[2].imm
;
7754 do_iwmmxt_tinsr (void)
7756 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7757 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7758 inst
.instruction
|= inst
.operands
[2].imm
;
7762 do_iwmmxt_tmia (void)
7764 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7765 inst
.instruction
|= inst
.operands
[1].reg
;
7766 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7770 do_iwmmxt_waligni (void)
7772 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7773 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7774 inst
.instruction
|= inst
.operands
[2].reg
;
7775 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
7779 do_iwmmxt_wmov (void)
7781 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7782 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7783 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7784 inst
.instruction
|= inst
.operands
[1].reg
;
7788 do_iwmmxt_wldstbh (void)
7791 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7793 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
7795 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
7796 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
7800 do_iwmmxt_wldstw (void)
7802 /* RIWR_RIWC clears .isreg for a control register. */
7803 if (!inst
.operands
[0].isreg
)
7805 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7806 inst
.instruction
|= 0xf0000000;
7809 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7810 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7814 do_iwmmxt_wldstd (void)
7816 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7817 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
7821 do_iwmmxt_wshufh (void)
7823 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7824 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7825 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
7826 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
7830 do_iwmmxt_wzero (void)
7832 /* WZERO reg is an alias for WANDN reg, reg, reg. */
7833 inst
.instruction
|= inst
.operands
[0].reg
;
7834 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7835 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7838 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
7839 operations first, then control, shift, and load/store. */
7841 /* Insns like "foo X,Y,Z". */
7844 do_mav_triple (void)
7846 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7847 inst
.instruction
|= inst
.operands
[1].reg
;
7848 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7851 /* Insns like "foo W,X,Y,Z".
7852 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
7857 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7858 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7859 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7860 inst
.instruction
|= inst
.operands
[3].reg
;
7863 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
7867 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7870 /* Maverick shift immediate instructions.
7871 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
7872 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
7877 int imm
= inst
.operands
[2].imm
;
7879 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7880 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7882 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
7883 Bits 5-7 of the insn should have bits 4-6 of the immediate.
7884 Bit 4 should be 0. */
7885 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
7887 inst
.instruction
|= imm
;
7890 /* XScale instructions. Also sorted arithmetic before move. */
7892 /* Xscale multiply-accumulate (argument parse)
7895 MIAxycc acc0,Rm,Rs. */
7900 inst
.instruction
|= inst
.operands
[1].reg
;
7901 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7904 /* Xscale move-accumulator-register (argument parse)
7906 MARcc acc0,RdLo,RdHi. */
7911 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7912 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7915 /* Xscale move-register-accumulator (argument parse)
7917 MRAcc RdLo,RdHi,acc0. */
7922 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
7923 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7924 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7927 /* Encoding functions relevant only to Thumb. */
7929 /* inst.operands[i] is a shifted-register operand; encode
7930 it into inst.instruction in the format used by Thumb32. */
7933 encode_thumb32_shifted_operand (int i
)
7935 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
7936 unsigned int shift
= inst
.operands
[i
].shift_kind
;
7938 constraint (inst
.operands
[i
].immisreg
,
7939 _("shift by register not allowed in thumb mode"));
7940 inst
.instruction
|= inst
.operands
[i
].reg
;
7941 if (shift
== SHIFT_RRX
)
7942 inst
.instruction
|= SHIFT_ROR
<< 4;
7945 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
7946 _("expression too complex"));
7948 constraint (value
> 32
7949 || (value
== 32 && (shift
== SHIFT_LSL
7950 || shift
== SHIFT_ROR
)),
7951 _("shift expression is too large"));
7955 else if (value
== 32)
7958 inst
.instruction
|= shift
<< 4;
7959 inst
.instruction
|= (value
& 0x1c) << 10;
7960 inst
.instruction
|= (value
& 0x03) << 6;
7965 /* inst.operands[i] was set up by parse_address. Encode it into a
7966 Thumb32 format load or store instruction. Reject forms that cannot
7967 be used with such instructions. If is_t is true, reject forms that
7968 cannot be used with a T instruction; if is_d is true, reject forms
7969 that cannot be used with a D instruction. */
7972 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
7974 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7976 constraint (!inst
.operands
[i
].isreg
,
7977 _("Instruction does not support =N addresses"));
7979 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7980 if (inst
.operands
[i
].immisreg
)
7982 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
7983 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
7984 constraint (inst
.operands
[i
].negative
,
7985 _("Thumb does not support negative register indexing"));
7986 constraint (inst
.operands
[i
].postind
,
7987 _("Thumb does not support register post-indexing"));
7988 constraint (inst
.operands
[i
].writeback
,
7989 _("Thumb does not support register indexing with writeback"));
7990 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
7991 _("Thumb supports only LSL in shifted register indexing"));
7993 inst
.instruction
|= inst
.operands
[i
].imm
;
7994 if (inst
.operands
[i
].shifted
)
7996 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
7997 _("expression too complex"));
7998 constraint (inst
.reloc
.exp
.X_add_number
< 0
7999 || inst
.reloc
.exp
.X_add_number
> 3,
8000 _("shift out of range"));
8001 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8003 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8005 else if (inst
.operands
[i
].preind
)
8007 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8008 _("cannot use writeback with PC-relative addressing"));
8009 constraint (is_t
&& inst
.operands
[i
].writeback
,
8010 _("cannot use writeback with this instruction"));
8014 inst
.instruction
|= 0x01000000;
8015 if (inst
.operands
[i
].writeback
)
8016 inst
.instruction
|= 0x00200000;
8020 inst
.instruction
|= 0x00000c00;
8021 if (inst
.operands
[i
].writeback
)
8022 inst
.instruction
|= 0x00000100;
8024 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8026 else if (inst
.operands
[i
].postind
)
8028 assert (inst
.operands
[i
].writeback
);
8029 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8030 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8033 inst
.instruction
|= 0x00200000;
8035 inst
.instruction
|= 0x00000900;
8036 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8038 else /* unindexed - only for coprocessor */
8039 inst
.error
= _("instruction does not accept unindexed addressing");
8042 /* Table of Thumb instructions which exist in both 16- and 32-bit
8043 encodings (the latter only in post-V6T2 cores). The index is the
8044 value used in the insns table below. When there is more than one
8045 possible 16-bit encoding for the instruction, this table always
8047 Also contains several pseudo-instructions used during relaxation. */
8048 #define T16_32_TAB \
8049 X(adc, 4140, eb400000), \
8050 X(adcs, 4140, eb500000), \
8051 X(add, 1c00, eb000000), \
8052 X(adds, 1c00, eb100000), \
8053 X(addi, 0000, f1000000), \
8054 X(addis, 0000, f1100000), \
8055 X(add_pc,000f, f20f0000), \
8056 X(add_sp,000d, f10d0000), \
8057 X(adr, 000f, f20f0000), \
8058 X(and, 4000, ea000000), \
8059 X(ands, 4000, ea100000), \
8060 X(asr, 1000, fa40f000), \
8061 X(asrs, 1000, fa50f000), \
8062 X(b, e000, f000b000), \
8063 X(bcond, d000, f0008000), \
8064 X(bic, 4380, ea200000), \
8065 X(bics, 4380, ea300000), \
8066 X(cmn, 42c0, eb100f00), \
8067 X(cmp, 2800, ebb00f00), \
8068 X(cpsie, b660, f3af8400), \
8069 X(cpsid, b670, f3af8600), \
8070 X(cpy, 4600, ea4f0000), \
8071 X(dec_sp,80dd, f1bd0d00), \
8072 X(eor, 4040, ea800000), \
8073 X(eors, 4040, ea900000), \
8074 X(inc_sp,00dd, f10d0d00), \
8075 X(ldmia, c800, e8900000), \
8076 X(ldr, 6800, f8500000), \
8077 X(ldrb, 7800, f8100000), \
8078 X(ldrh, 8800, f8300000), \
8079 X(ldrsb, 5600, f9100000), \
8080 X(ldrsh, 5e00, f9300000), \
8081 X(ldr_pc,4800, f85f0000), \
8082 X(ldr_pc2,4800, f85f0000), \
8083 X(ldr_sp,9800, f85d0000), \
8084 X(lsl, 0000, fa00f000), \
8085 X(lsls, 0000, fa10f000), \
8086 X(lsr, 0800, fa20f000), \
8087 X(lsrs, 0800, fa30f000), \
8088 X(mov, 2000, ea4f0000), \
8089 X(movs, 2000, ea5f0000), \
8090 X(mul, 4340, fb00f000), \
8091 X(muls, 4340, ffffffff), /* no 32b muls */ \
8092 X(mvn, 43c0, ea6f0000), \
8093 X(mvns, 43c0, ea7f0000), \
8094 X(neg, 4240, f1c00000), /* rsb #0 */ \
8095 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8096 X(orr, 4300, ea400000), \
8097 X(orrs, 4300, ea500000), \
8098 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8099 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8100 X(rev, ba00, fa90f080), \
8101 X(rev16, ba40, fa90f090), \
8102 X(revsh, bac0, fa90f0b0), \
8103 X(ror, 41c0, fa60f000), \
8104 X(rors, 41c0, fa70f000), \
8105 X(sbc, 4180, eb600000), \
8106 X(sbcs, 4180, eb700000), \
8107 X(stmia, c000, e8800000), \
8108 X(str, 6000, f8400000), \
8109 X(strb, 7000, f8000000), \
8110 X(strh, 8000, f8200000), \
8111 X(str_sp,9000, f84d0000), \
8112 X(sub, 1e00, eba00000), \
8113 X(subs, 1e00, ebb00000), \
8114 X(subi, 8000, f1a00000), \
8115 X(subis, 8000, f1b00000), \
8116 X(sxtb, b240, fa4ff080), \
8117 X(sxth, b200, fa0ff080), \
8118 X(tst, 4200, ea100f00), \
8119 X(uxtb, b2c0, fa5ff080), \
8120 X(uxth, b280, fa1ff080), \
8121 X(nop, bf00, f3af8000), \
8122 X(yield, bf10, f3af8001), \
8123 X(wfe, bf20, f3af8002), \
8124 X(wfi, bf30, f3af8003), \
8125 X(sev, bf40, f3af9004), /* typo, 8004? */
8127 /* To catch errors in encoding functions, the codes are all offset by
8128 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8129 as 16-bit instructions. */
8130 #define X(a,b,c) T_MNEM_##a
8131 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8134 #define X(a,b,c) 0x##b
8135 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8136 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8139 #define X(a,b,c) 0x##c
8140 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8141 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8142 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8146 /* Thumb instruction encoders, in alphabetical order. */
8150 do_t_add_sub_w (void)
8154 Rd
= inst
.operands
[0].reg
;
8155 Rn
= inst
.operands
[1].reg
;
8157 constraint (Rd
== 15, _("PC not allowed as destination"));
8158 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8159 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8162 /* Parse an add or subtract instruction. We get here with inst.instruction
8163 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8170 Rd
= inst
.operands
[0].reg
;
8171 Rs
= (inst
.operands
[1].present
8172 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8173 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8181 flags
= (inst
.instruction
== T_MNEM_adds
8182 || inst
.instruction
== T_MNEM_subs
);
8184 narrow
= (current_it_mask
== 0);
8186 narrow
= (current_it_mask
!= 0);
8187 if (!inst
.operands
[2].isreg
)
8190 if (inst
.size_req
!= 4)
8194 add
= (inst
.instruction
== T_MNEM_add
8195 || inst
.instruction
== T_MNEM_adds
);
8196 /* Attempt to use a narrow opcode, with relaxation if
8198 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8199 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8200 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8201 opcode
= T_MNEM_add_sp
;
8202 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8203 opcode
= T_MNEM_add_pc
;
8204 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8207 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8209 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8213 inst
.instruction
= THUMB_OP16(opcode
);
8214 inst
.instruction
|= (Rd
<< 4) | Rs
;
8215 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8216 if (inst
.size_req
!= 2)
8217 inst
.relax
= opcode
;
8220 constraint (inst
.size_req
== 2, BAD_HIREG
);
8222 if (inst
.size_req
== 4
8223 || (inst
.size_req
!= 2 && !opcode
))
8225 /* ??? Convert large immediates to addw/subw. */
8226 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8227 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8228 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8229 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8230 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8235 Rn
= inst
.operands
[2].reg
;
8236 /* See if we can do this with a 16-bit instruction. */
8237 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8239 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8244 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8245 || inst
.instruction
== T_MNEM_add
)
8248 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8252 if (inst
.instruction
== T_MNEM_add
)
8256 inst
.instruction
= T_OPCODE_ADD_HI
;
8257 inst
.instruction
|= (Rd
& 8) << 4;
8258 inst
.instruction
|= (Rd
& 7);
8259 inst
.instruction
|= Rn
<< 3;
8262 /* ... because addition is commutative! */
8265 inst
.instruction
= T_OPCODE_ADD_HI
;
8266 inst
.instruction
|= (Rd
& 8) << 4;
8267 inst
.instruction
|= (Rd
& 7);
8268 inst
.instruction
|= Rs
<< 3;
8273 /* If we get here, it can't be done in 16 bits. */
8274 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8275 _("shift must be constant"));
8276 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8277 inst
.instruction
|= Rd
<< 8;
8278 inst
.instruction
|= Rs
<< 16;
8279 encode_thumb32_shifted_operand (2);
8284 constraint (inst
.instruction
== T_MNEM_adds
8285 || inst
.instruction
== T_MNEM_subs
,
8288 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
8290 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
8291 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
8294 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8296 inst
.instruction
|= (Rd
<< 4) | Rs
;
8297 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8301 Rn
= inst
.operands
[2].reg
;
8302 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
8304 /* We now have Rd, Rs, and Rn set to registers. */
8305 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8307 /* Can't do this for SUB. */
8308 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
8309 inst
.instruction
= T_OPCODE_ADD_HI
;
8310 inst
.instruction
|= (Rd
& 8) << 4;
8311 inst
.instruction
|= (Rd
& 7);
8313 inst
.instruction
|= Rn
<< 3;
8315 inst
.instruction
|= Rs
<< 3;
8317 constraint (1, _("dest must overlap one source register"));
8321 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8322 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
8323 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8331 if (unified_syntax
&& inst
.size_req
== 0 && inst
.operands
[0].reg
<= 7)
8333 /* Defer to section relaxation. */
8334 inst
.relax
= inst
.instruction
;
8335 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8336 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8338 else if (unified_syntax
&& inst
.size_req
!= 2)
8340 /* Generate a 32-bit opcode. */
8341 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8342 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8343 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
8344 inst
.reloc
.pc_rel
= 1;
8348 /* Generate a 16-bit opcode. */
8349 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8350 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8351 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
8352 inst
.reloc
.pc_rel
= 1;
8354 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8358 /* Arithmetic instructions for which there is just one 16-bit
8359 instruction encoding, and it allows only two low registers.
8360 For maximal compatibility with ARM syntax, we allow three register
8361 operands even when Thumb-32 instructions are not available, as long
8362 as the first two are identical. For instance, both "sbc r0,r1" and
8363 "sbc r0,r0,r1" are allowed. */
8369 Rd
= inst
.operands
[0].reg
;
8370 Rs
= (inst
.operands
[1].present
8371 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8372 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8373 Rn
= inst
.operands
[2].reg
;
8377 if (!inst
.operands
[2].isreg
)
8379 /* For an immediate, we always generate a 32-bit opcode;
8380 section relaxation will shrink it later if possible. */
8381 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8382 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8383 inst
.instruction
|= Rd
<< 8;
8384 inst
.instruction
|= Rs
<< 16;
8385 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8391 /* See if we can do this with a 16-bit instruction. */
8392 if (THUMB_SETS_FLAGS (inst
.instruction
))
8393 narrow
= current_it_mask
== 0;
8395 narrow
= current_it_mask
!= 0;
8397 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8399 if (inst
.operands
[2].shifted
)
8401 if (inst
.size_req
== 4)
8407 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8408 inst
.instruction
|= Rd
;
8409 inst
.instruction
|= Rn
<< 3;
8413 /* If we get here, it can't be done in 16 bits. */
8414 constraint (inst
.operands
[2].shifted
8415 && inst
.operands
[2].immisreg
,
8416 _("shift must be constant"));
8417 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8418 inst
.instruction
|= Rd
<< 8;
8419 inst
.instruction
|= Rs
<< 16;
8420 encode_thumb32_shifted_operand (2);
8425 /* On its face this is a lie - the instruction does set the
8426 flags. However, the only supported mnemonic in this mode
8428 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8430 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8431 _("unshifted register required"));
8432 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8433 constraint (Rd
!= Rs
,
8434 _("dest and source1 must be the same register"));
8436 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8437 inst
.instruction
|= Rd
;
8438 inst
.instruction
|= Rn
<< 3;
8442 /* Similarly, but for instructions where the arithmetic operation is
8443 commutative, so we can allow either of them to be different from
8444 the destination operand in a 16-bit instruction. For instance, all
8445 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8452 Rd
= inst
.operands
[0].reg
;
8453 Rs
= (inst
.operands
[1].present
8454 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8455 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8456 Rn
= inst
.operands
[2].reg
;
8460 if (!inst
.operands
[2].isreg
)
8462 /* For an immediate, we always generate a 32-bit opcode;
8463 section relaxation will shrink it later if possible. */
8464 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8465 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8466 inst
.instruction
|= Rd
<< 8;
8467 inst
.instruction
|= Rs
<< 16;
8468 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8474 /* See if we can do this with a 16-bit instruction. */
8475 if (THUMB_SETS_FLAGS (inst
.instruction
))
8476 narrow
= current_it_mask
== 0;
8478 narrow
= current_it_mask
!= 0;
8480 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8482 if (inst
.operands
[2].shifted
)
8484 if (inst
.size_req
== 4)
8491 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8492 inst
.instruction
|= Rd
;
8493 inst
.instruction
|= Rn
<< 3;
8498 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8499 inst
.instruction
|= Rd
;
8500 inst
.instruction
|= Rs
<< 3;
8505 /* If we get here, it can't be done in 16 bits. */
8506 constraint (inst
.operands
[2].shifted
8507 && inst
.operands
[2].immisreg
,
8508 _("shift must be constant"));
8509 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8510 inst
.instruction
|= Rd
<< 8;
8511 inst
.instruction
|= Rs
<< 16;
8512 encode_thumb32_shifted_operand (2);
8517 /* On its face this is a lie - the instruction does set the
8518 flags. However, the only supported mnemonic in this mode
8520 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8522 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8523 _("unshifted register required"));
8524 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8526 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8527 inst
.instruction
|= Rd
;
8530 inst
.instruction
|= Rn
<< 3;
8532 inst
.instruction
|= Rs
<< 3;
8534 constraint (1, _("dest must overlap one source register"));
8541 if (inst
.operands
[0].present
)
8543 constraint ((inst
.instruction
& 0xf0) != 0x40
8544 && inst
.operands
[0].imm
!= 0xf,
8545 "bad barrier type");
8546 inst
.instruction
|= inst
.operands
[0].imm
;
8549 inst
.instruction
|= 0xf;
8555 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8556 constraint (msb
> 32, _("bit-field extends past end of register"));
8557 /* The instruction encoding stores the LSB and MSB,
8558 not the LSB and width. */
8559 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8560 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
8561 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
8562 inst
.instruction
|= msb
- 1;
8570 /* #0 in second position is alternative syntax for bfc, which is
8571 the same instruction but with REG_PC in the Rm field. */
8572 if (!inst
.operands
[1].isreg
)
8573 inst
.operands
[1].reg
= REG_PC
;
8575 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8576 constraint (msb
> 32, _("bit-field extends past end of register"));
8577 /* The instruction encoding stores the LSB and MSB,
8578 not the LSB and width. */
8579 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8580 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8581 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8582 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8583 inst
.instruction
|= msb
- 1;
8589 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8590 _("bit-field extends past end of register"));
8591 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8592 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8593 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8594 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8595 inst
.instruction
|= inst
.operands
[3].imm
- 1;
8598 /* ARM V5 Thumb BLX (argument parse)
8599 BLX <target_addr> which is BLX(1)
8600 BLX <Rm> which is BLX(2)
8601 Unfortunately, there are two different opcodes for this mnemonic.
8602 So, the insns[].value is not used, and the code here zaps values
8603 into inst.instruction.
8605 ??? How to take advantage of the additional two bits of displacement
8606 available in Thumb32 mode? Need new relocation? */
8611 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8612 if (inst
.operands
[0].isreg
)
8613 /* We have a register, so this is BLX(2). */
8614 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8617 /* No register. This must be BLX(1). */
8618 inst
.instruction
= 0xf000e800;
8620 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8621 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8624 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
8625 inst
.reloc
.pc_rel
= 1;
8635 if (current_it_mask
)
8637 /* Conditional branches inside IT blocks are encoded as unconditional
8640 /* A branch must be the last instruction in an IT block. */
8641 constraint (current_it_mask
!= 0x10, BAD_BRANCH
);
8646 if (cond
!= COND_ALWAYS
)
8647 opcode
= T_MNEM_bcond
;
8649 opcode
= inst
.instruction
;
8651 if (unified_syntax
&& inst
.size_req
== 4)
8653 inst
.instruction
= THUMB_OP32(opcode
);
8654 if (cond
== COND_ALWAYS
)
8655 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
8658 assert (cond
!= 0xF);
8659 inst
.instruction
|= cond
<< 22;
8660 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
8665 inst
.instruction
= THUMB_OP16(opcode
);
8666 if (cond
== COND_ALWAYS
)
8667 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
8670 inst
.instruction
|= cond
<< 8;
8671 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
8673 /* Allow section relaxation. */
8674 if (unified_syntax
&& inst
.size_req
!= 2)
8675 inst
.relax
= opcode
;
8678 inst
.reloc
.pc_rel
= 1;
8684 constraint (inst
.cond
!= COND_ALWAYS
,
8685 _("instruction is always unconditional"));
8686 if (inst
.operands
[0].present
)
8688 constraint (inst
.operands
[0].imm
> 255,
8689 _("immediate value out of range"));
8690 inst
.instruction
|= inst
.operands
[0].imm
;
8695 do_t_branch23 (void)
8697 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8698 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8699 inst
.reloc
.pc_rel
= 1;
8701 /* If the destination of the branch is a defined symbol which does not have
8702 the THUMB_FUNC attribute, then we must be calling a function which has
8703 the (interfacearm) attribute. We look for the Thumb entry point to that
8704 function and change the branch to refer to that function instead. */
8705 if ( inst
.reloc
.exp
.X_op
== O_symbol
8706 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8707 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8708 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8709 inst
.reloc
.exp
.X_add_symbol
=
8710 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
8716 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8717 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8718 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8719 should cause the alignment to be checked once it is known. This is
8720 because BX PC only works if the instruction is word aligned. */
8726 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8727 if (inst
.operands
[0].reg
== REG_PC
)
8728 as_tsktsk (_("use of r15 in bxj is not really useful"));
8730 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8736 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8737 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8738 inst
.instruction
|= inst
.operands
[1].reg
;
8744 constraint (current_it_mask
, BAD_NOT_IT
);
8745 inst
.instruction
|= inst
.operands
[0].imm
;
8751 constraint (current_it_mask
, BAD_NOT_IT
);
8753 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
8754 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
8756 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
8757 inst
.instruction
= 0xf3af8000;
8758 inst
.instruction
|= imod
<< 9;
8759 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
8760 if (inst
.operands
[1].present
)
8761 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
8765 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
8766 && (inst
.operands
[0].imm
& 4),
8767 _("selected processor does not support 'A' form "
8768 "of this instruction"));
8769 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
8770 _("Thumb does not support the 2-argument "
8771 "form of this instruction"));
8772 inst
.instruction
|= inst
.operands
[0].imm
;
8776 /* THUMB CPY instruction (argument parse). */
8781 if (inst
.size_req
== 4)
8783 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
8784 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8785 inst
.instruction
|= inst
.operands
[1].reg
;
8789 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
8790 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
8791 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
8798 constraint (current_it_mask
, BAD_NOT_IT
);
8799 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
8800 inst
.instruction
|= inst
.operands
[0].reg
;
8801 inst
.reloc
.pc_rel
= 1;
8802 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
8808 inst
.instruction
|= inst
.operands
[0].imm
;
8814 if (!inst
.operands
[1].present
)
8815 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8816 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8817 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8818 inst
.instruction
|= inst
.operands
[2].reg
;
8824 if (unified_syntax
&& inst
.size_req
== 4)
8825 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8827 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8833 unsigned int cond
= inst
.operands
[0].imm
;
8835 constraint (current_it_mask
, BAD_NOT_IT
);
8836 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
8839 /* If the condition is a negative condition, invert the mask. */
8840 if ((cond
& 0x1) == 0x0)
8842 unsigned int mask
= inst
.instruction
& 0x000f;
8844 if ((mask
& 0x7) == 0)
8845 /* no conversion needed */;
8846 else if ((mask
& 0x3) == 0)
8848 else if ((mask
& 0x1) == 0)
8853 inst
.instruction
&= 0xfff0;
8854 inst
.instruction
|= mask
;
8857 inst
.instruction
|= cond
<< 4;
8863 /* This really doesn't seem worth it. */
8864 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
8865 _("expression too complex"));
8866 constraint (inst
.operands
[1].writeback
,
8867 _("Thumb load/store multiple does not support {reglist}^"));
8871 /* See if we can use a 16-bit instruction. */
8872 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
8873 && inst
.size_req
!= 4
8874 && inst
.operands
[0].reg
<= 7
8875 && !(inst
.operands
[1].imm
& ~0xff)
8876 && (inst
.instruction
== T_MNEM_stmia
8877 ? inst
.operands
[0].writeback
8878 : (inst
.operands
[0].writeback
8879 == !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))))
8881 if (inst
.instruction
== T_MNEM_stmia
8882 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8883 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
8884 as_warn (_("value stored for r%d is UNPREDICTABLE"),
8885 inst
.operands
[0].reg
);
8887 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8888 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8889 inst
.instruction
|= inst
.operands
[1].imm
;
8893 if (inst
.operands
[1].imm
& (1 << 13))
8894 as_warn (_("SP should not be in register list"));
8895 if (inst
.instruction
== T_MNEM_stmia
)
8897 if (inst
.operands
[1].imm
& (1 << 15))
8898 as_warn (_("PC should not be in register list"));
8899 if (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8900 as_warn (_("value stored for r%d is UNPREDICTABLE"),
8901 inst
.operands
[0].reg
);
8905 if (inst
.operands
[1].imm
& (1 << 14)
8906 && inst
.operands
[1].imm
& (1 << 15))
8907 as_warn (_("LR and PC should not both be in register list"));
8908 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8909 && inst
.operands
[0].writeback
)
8910 as_warn (_("base register should not be in register list "
8911 "when written back"));
8913 if (inst
.instruction
< 0xffff)
8914 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8915 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8916 inst
.instruction
|= inst
.operands
[1].imm
;
8917 if (inst
.operands
[0].writeback
)
8918 inst
.instruction
|= WRITE_BACK
;
8923 constraint (inst
.operands
[0].reg
> 7
8924 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
8925 if (inst
.instruction
== T_MNEM_stmia
)
8927 if (!inst
.operands
[0].writeback
)
8928 as_warn (_("this instruction will write back the base register"));
8929 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8930 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
8931 as_warn (_("value stored for r%d is UNPREDICTABLE"),
8932 inst
.operands
[0].reg
);
8936 if (!inst
.operands
[0].writeback
8937 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
8938 as_warn (_("this instruction will write back the base register"));
8939 else if (inst
.operands
[0].writeback
8940 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
8941 as_warn (_("this instruction will not write back the base register"));
8944 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8945 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8946 inst
.instruction
|= inst
.operands
[1].imm
;
8953 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8954 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8955 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8956 || inst
.operands
[1].negative
,
8959 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8960 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8961 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
8967 if (!inst
.operands
[1].present
)
8969 constraint (inst
.operands
[0].reg
== REG_LR
,
8970 _("r14 not allowed as first register "
8971 "when second register is omitted"));
8972 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8974 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
8977 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8978 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
8979 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8985 unsigned long opcode
;
8988 opcode
= inst
.instruction
;
8991 if (!inst
.operands
[1].isreg
)
8993 if (opcode
<= 0xffff)
8994 inst
.instruction
= THUMB_OP32 (opcode
);
8995 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
8998 if (inst
.operands
[1].isreg
8999 && !inst
.operands
[1].writeback
9000 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9001 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9003 && inst
.size_req
!= 4)
9005 /* Insn may have a 16-bit form. */
9006 Rn
= inst
.operands
[1].reg
;
9007 if (inst
.operands
[1].immisreg
)
9009 inst
.instruction
= THUMB_OP16 (opcode
);
9011 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9014 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9015 && opcode
!= T_MNEM_ldrsb
)
9016 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9017 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9024 if (inst
.reloc
.pc_rel
)
9025 opcode
= T_MNEM_ldr_pc2
;
9027 opcode
= T_MNEM_ldr_pc
;
9031 if (opcode
== T_MNEM_ldr
)
9032 opcode
= T_MNEM_ldr_sp
;
9034 opcode
= T_MNEM_str_sp
;
9036 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9040 inst
.instruction
= inst
.operands
[0].reg
;
9041 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9043 inst
.instruction
|= THUMB_OP16 (opcode
);
9044 if (inst
.size_req
== 2)
9045 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9047 inst
.relax
= opcode
;
9051 /* Definitely a 32-bit variant. */
9052 inst
.instruction
= THUMB_OP32 (opcode
);
9053 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9054 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9058 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9060 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9062 /* Only [Rn,Rm] is acceptable. */
9063 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9064 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9065 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9066 || inst
.operands
[1].negative
,
9067 _("Thumb does not support this addressing mode"));
9068 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9072 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9073 if (!inst
.operands
[1].isreg
)
9074 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9077 constraint (!inst
.operands
[1].preind
9078 || inst
.operands
[1].shifted
9079 || inst
.operands
[1].writeback
,
9080 _("Thumb does not support this addressing mode"));
9081 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9083 constraint (inst
.instruction
& 0x0600,
9084 _("byte or halfword not valid for base register"));
9085 constraint (inst
.operands
[1].reg
== REG_PC
9086 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9087 _("r15 based store not allowed"));
9088 constraint (inst
.operands
[1].immisreg
,
9089 _("invalid base register for register offset"));
9091 if (inst
.operands
[1].reg
== REG_PC
)
9092 inst
.instruction
= T_OPCODE_LDR_PC
;
9093 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9094 inst
.instruction
= T_OPCODE_LDR_SP
;
9096 inst
.instruction
= T_OPCODE_STR_SP
;
9098 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9099 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9103 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9104 if (!inst
.operands
[1].immisreg
)
9106 /* Immediate offset. */
9107 inst
.instruction
|= inst
.operands
[0].reg
;
9108 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9109 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9113 /* Register offset. */
9114 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9115 constraint (inst
.operands
[1].negative
,
9116 _("Thumb does not support this addressing mode"));
9119 switch (inst
.instruction
)
9121 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9122 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9123 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9124 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9125 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9126 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9127 case 0x5600 /* ldrsb */:
9128 case 0x5e00 /* ldrsh */: break;
9132 inst
.instruction
|= inst
.operands
[0].reg
;
9133 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9134 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9140 if (!inst
.operands
[1].present
)
9142 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9143 constraint (inst
.operands
[0].reg
== REG_LR
,
9144 _("r14 not allowed here"));
9146 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9147 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9148 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9155 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9156 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
9162 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9163 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9164 inst
.instruction
|= inst
.operands
[2].reg
;
9165 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9171 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9172 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9173 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9174 inst
.instruction
|= inst
.operands
[3].reg
;
9182 int r0off
= (inst
.instruction
== T_MNEM_mov
9183 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
9184 unsigned long opcode
;
9186 bfd_boolean low_regs
;
9188 low_regs
= (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7);
9189 opcode
= inst
.instruction
;
9190 if (current_it_mask
)
9191 narrow
= opcode
!= T_MNEM_movs
;
9193 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
9194 if (inst
.size_req
== 4
9195 || inst
.operands
[1].shifted
)
9198 if (!inst
.operands
[1].isreg
)
9200 /* Immediate operand. */
9201 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
9203 if (low_regs
&& narrow
)
9205 inst
.instruction
= THUMB_OP16 (opcode
);
9206 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9207 if (inst
.size_req
== 2)
9208 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9210 inst
.relax
= opcode
;
9214 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9215 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9216 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9217 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9222 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9223 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9224 encode_thumb32_shifted_operand (1);
9227 switch (inst
.instruction
)
9230 inst
.instruction
= T_OPCODE_MOV_HR
;
9231 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9232 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9233 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9237 /* We know we have low registers at this point.
9238 Generate ADD Rd, Rs, #0. */
9239 inst
.instruction
= T_OPCODE_ADD_I3
;
9240 inst
.instruction
|= inst
.operands
[0].reg
;
9241 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9247 inst
.instruction
= T_OPCODE_CMP_LR
;
9248 inst
.instruction
|= inst
.operands
[0].reg
;
9249 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9253 inst
.instruction
= T_OPCODE_CMP_HR
;
9254 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9255 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9256 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9263 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9264 if (inst
.operands
[1].isreg
)
9266 if (inst
.operands
[0].reg
< 8 && inst
.operands
[1].reg
< 8)
9268 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9269 since a MOV instruction produces unpredictable results. */
9270 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9271 inst
.instruction
= T_OPCODE_ADD_I3
;
9273 inst
.instruction
= T_OPCODE_CMP_LR
;
9275 inst
.instruction
|= inst
.operands
[0].reg
;
9276 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9280 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9281 inst
.instruction
= T_OPCODE_MOV_HR
;
9283 inst
.instruction
= T_OPCODE_CMP_HR
;
9289 constraint (inst
.operands
[0].reg
> 7,
9290 _("only lo regs allowed with immediate"));
9291 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9292 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9302 top
= (inst
.instruction
& 0x00800000) != 0;
9303 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
9305 constraint (top
, _(":lower16: not allowed this instruction"));
9306 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
9308 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
9310 constraint (!top
, _(":upper16: not allowed this instruction"));
9311 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
9314 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9315 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9317 imm
= inst
.reloc
.exp
.X_add_number
;
9318 inst
.instruction
|= (imm
& 0xf000) << 4;
9319 inst
.instruction
|= (imm
& 0x0800) << 15;
9320 inst
.instruction
|= (imm
& 0x0700) << 4;
9321 inst
.instruction
|= (imm
& 0x00ff);
9330 int r0off
= (inst
.instruction
== T_MNEM_mvn
9331 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
9334 if (inst
.size_req
== 4
9335 || inst
.instruction
> 0xffff
9336 || inst
.operands
[1].shifted
9337 || inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9339 else if (inst
.instruction
== T_MNEM_cmn
)
9341 else if (THUMB_SETS_FLAGS (inst
.instruction
))
9342 narrow
= (current_it_mask
== 0);
9344 narrow
= (current_it_mask
!= 0);
9346 if (!inst
.operands
[1].isreg
)
9348 /* For an immediate, we always generate a 32-bit opcode;
9349 section relaxation will shrink it later if possible. */
9350 if (inst
.instruction
< 0xffff)
9351 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9352 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9353 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9354 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9358 /* See if we can do this with a 16-bit instruction. */
9361 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9362 inst
.instruction
|= inst
.operands
[0].reg
;
9363 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9367 constraint (inst
.operands
[1].shifted
9368 && inst
.operands
[1].immisreg
,
9369 _("shift must be constant"));
9370 if (inst
.instruction
< 0xffff)
9371 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9372 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9373 encode_thumb32_shifted_operand (1);
9379 constraint (inst
.instruction
> 0xffff
9380 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
9381 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
9382 _("unshifted register required"));
9383 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9386 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9387 inst
.instruction
|= inst
.operands
[0].reg
;
9388 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9397 if (do_vfp_nsyn_mrs () == SUCCESS
)
9400 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
9403 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9404 _("selected processor does not support "
9405 "requested special purpose register"));
9409 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9410 _("selected processor does not support "
9411 "requested special purpose register %x"));
9412 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9413 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
9414 _("'CPSR' or 'SPSR' expected"));
9417 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9418 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9419 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
9427 if (do_vfp_nsyn_msr () == SUCCESS
)
9430 constraint (!inst
.operands
[1].isreg
,
9431 _("Thumb encoding does not support an immediate here"));
9432 flags
= inst
.operands
[0].imm
;
9435 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9436 _("selected processor does not support "
9437 "requested special purpose register"));
9441 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9442 _("selected processor does not support "
9443 "requested special purpose register"));
9446 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9447 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
9448 inst
.instruction
|= (flags
& 0xff);
9449 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9455 if (!inst
.operands
[2].present
)
9456 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9458 /* There is no 32-bit MULS and no 16-bit MUL. */
9459 if (unified_syntax
&& inst
.instruction
== T_MNEM_mul
)
9461 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9462 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9463 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9464 inst
.instruction
|= inst
.operands
[2].reg
<< 0;
9468 constraint (!unified_syntax
9469 && inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
9470 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9473 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9474 inst
.instruction
|= inst
.operands
[0].reg
;
9476 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9477 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9478 else if (inst
.operands
[0].reg
== inst
.operands
[2].reg
)
9479 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9481 constraint (1, _("dest must overlap one source register"));
9488 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9489 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9490 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9491 inst
.instruction
|= inst
.operands
[3].reg
;
9493 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9494 as_tsktsk (_("rdhi and rdlo must be different"));
9502 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
9504 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9505 inst
.instruction
|= inst
.operands
[0].imm
;
9509 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9510 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
9515 constraint (inst
.operands
[0].present
,
9516 _("Thumb does not support NOP with hints"));
9517 inst
.instruction
= 0x46c0;
9528 if (THUMB_SETS_FLAGS (inst
.instruction
))
9529 narrow
= (current_it_mask
== 0);
9531 narrow
= (current_it_mask
!= 0);
9532 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9534 if (inst
.size_req
== 4)
9539 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9540 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9541 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9545 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9546 inst
.instruction
|= inst
.operands
[0].reg
;
9547 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9552 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9554 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9556 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9557 inst
.instruction
|= inst
.operands
[0].reg
;
9558 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9565 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9566 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9567 inst
.instruction
|= inst
.operands
[2].reg
;
9568 if (inst
.operands
[3].present
)
9570 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
9571 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9572 _("expression too complex"));
9573 inst
.instruction
|= (val
& 0x1c) << 10;
9574 inst
.instruction
|= (val
& 0x03) << 6;
9581 if (!inst
.operands
[3].present
)
9582 inst
.instruction
&= ~0x00000020;
9589 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9593 do_t_push_pop (void)
9597 constraint (inst
.operands
[0].writeback
,
9598 _("push/pop do not support {reglist}^"));
9599 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9600 _("expression too complex"));
9602 mask
= inst
.operands
[0].imm
;
9603 if ((mask
& ~0xff) == 0)
9604 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9605 else if ((inst
.instruction
== T_MNEM_push
9606 && (mask
& ~0xff) == 1 << REG_LR
)
9607 || (inst
.instruction
== T_MNEM_pop
9608 && (mask
& ~0xff) == 1 << REG_PC
))
9610 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9611 inst
.instruction
|= THUMB_PP_PC_LR
;
9614 else if (unified_syntax
)
9616 if (mask
& (1 << 13))
9617 inst
.error
= _("SP not allowed in register list");
9618 if (inst
.instruction
== T_MNEM_push
)
9620 if (mask
& (1 << 15))
9621 inst
.error
= _("PC not allowed in register list");
9625 if (mask
& (1 << 14)
9626 && mask
& (1 << 15))
9627 inst
.error
= _("LR and PC should not both be in register list");
9629 if ((mask
& (mask
- 1)) == 0)
9631 /* Single register push/pop implemented as str/ldr. */
9632 if (inst
.instruction
== T_MNEM_push
)
9633 inst
.instruction
= 0xf84d0d04; /* str reg, [sp, #-4]! */
9635 inst
.instruction
= 0xf85d0b04; /* ldr reg, [sp], #4 */
9636 mask
= ffs(mask
) - 1;
9640 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9644 inst
.error
= _("invalid register list to push/pop instruction");
9648 inst
.instruction
|= mask
;
9654 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9655 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9661 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
9662 && inst
.size_req
!= 4)
9664 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9665 inst
.instruction
|= inst
.operands
[0].reg
;
9666 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9668 else if (unified_syntax
)
9670 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9671 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9672 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9673 inst
.instruction
|= inst
.operands
[1].reg
;
9676 inst
.error
= BAD_HIREG
;
9684 Rd
= inst
.operands
[0].reg
;
9685 Rs
= (inst
.operands
[1].present
9686 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9687 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9689 inst
.instruction
|= Rd
<< 8;
9690 inst
.instruction
|= Rs
<< 16;
9691 if (!inst
.operands
[2].isreg
)
9693 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9694 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9697 encode_thumb32_shifted_operand (2);
9703 constraint (current_it_mask
, BAD_NOT_IT
);
9704 if (inst
.operands
[0].imm
)
9705 inst
.instruction
|= 0x8;
9711 if (!inst
.operands
[1].present
)
9712 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9719 switch (inst
.instruction
)
9722 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
9724 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
9726 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
9728 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
9732 if (THUMB_SETS_FLAGS (inst
.instruction
))
9733 narrow
= (current_it_mask
== 0);
9735 narrow
= (current_it_mask
!= 0);
9736 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9738 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
9740 if (inst
.operands
[2].isreg
9741 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
9742 || inst
.operands
[2].reg
> 7))
9744 if (inst
.size_req
== 4)
9749 if (inst
.operands
[2].isreg
)
9751 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9752 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9753 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9754 inst
.instruction
|= inst
.operands
[2].reg
;
9758 inst
.operands
[1].shifted
= 1;
9759 inst
.operands
[1].shift_kind
= shift_kind
;
9760 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
9761 ? T_MNEM_movs
: T_MNEM_mov
);
9762 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9763 encode_thumb32_shifted_operand (1);
9764 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
9765 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9770 if (inst
.operands
[2].isreg
)
9774 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
9775 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
9776 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
9777 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
9781 inst
.instruction
|= inst
.operands
[0].reg
;
9782 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9788 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9789 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9790 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9793 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9794 inst
.instruction
|= inst
.operands
[0].reg
;
9795 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9801 constraint (inst
.operands
[0].reg
> 7
9802 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
9803 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9805 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
9807 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
9808 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
9809 _("source1 and dest must be same register"));
9811 switch (inst
.instruction
)
9813 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
9814 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
9815 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
9816 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
9820 inst
.instruction
|= inst
.operands
[0].reg
;
9821 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9825 switch (inst
.instruction
)
9827 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9828 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9829 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9830 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
9833 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9834 inst
.instruction
|= inst
.operands
[0].reg
;
9835 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9843 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9844 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9845 inst
.instruction
|= inst
.operands
[2].reg
;
9851 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9852 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9853 _("expression too complex"));
9854 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9855 inst
.instruction
|= (value
& 0xf000) >> 12;
9856 inst
.instruction
|= (value
& 0x0ff0);
9857 inst
.instruction
|= (value
& 0x000f) << 16;
9863 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9864 inst
.instruction
|= inst
.operands
[1].imm
- 1;
9865 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9867 if (inst
.operands
[3].present
)
9869 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9870 _("expression too complex"));
9872 if (inst
.reloc
.exp
.X_add_number
!= 0)
9874 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
9875 inst
.instruction
|= 0x00200000; /* sh bit */
9876 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
9877 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
9879 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9886 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9887 inst
.instruction
|= inst
.operands
[1].imm
- 1;
9888 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9894 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9895 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9896 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9897 || inst
.operands
[2].negative
,
9900 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9901 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9902 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9903 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9909 if (!inst
.operands
[2].present
)
9910 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
9912 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9913 || inst
.operands
[0].reg
== inst
.operands
[2].reg
9914 || inst
.operands
[0].reg
== inst
.operands
[3].reg
9915 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
9918 inst
.instruction
|= inst
.operands
[0].reg
;
9919 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9920 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9921 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9927 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9928 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9929 inst
.instruction
|= inst
.operands
[2].reg
;
9930 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
9936 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
9937 && inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
9938 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
9940 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9941 inst
.instruction
|= inst
.operands
[0].reg
;
9942 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9944 else if (unified_syntax
)
9946 if (inst
.instruction
<= 0xffff)
9947 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9948 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9949 inst
.instruction
|= inst
.operands
[1].reg
;
9950 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
9954 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
9955 _("Thumb encoding does not support rotation"));
9956 constraint (1, BAD_HIREG
);
9963 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9971 half
= (inst
.instruction
& 0x10) != 0;
9972 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
9973 constraint (inst
.operands
[0].immisreg
,
9974 _("instruction requires register index"));
9975 constraint (inst
.operands
[0].imm
== 15,
9976 _("PC is not a valid index register"));
9977 constraint (!half
&& inst
.operands
[0].shifted
,
9978 _("instruction does not allow shifted index"));
9979 inst
.instruction
|= (inst
.operands
[0].reg
<< 16) | inst
.operands
[0].imm
;
9985 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9986 inst
.instruction
|= inst
.operands
[1].imm
;
9987 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9989 if (inst
.operands
[3].present
)
9991 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9992 _("expression too complex"));
9993 if (inst
.reloc
.exp
.X_add_number
!= 0)
9995 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
9996 inst
.instruction
|= 0x00200000; /* sh bit */
9998 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
9999 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10001 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10008 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10009 inst
.instruction
|= inst
.operands
[1].imm
;
10010 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10013 /* Neon instruction encoder helpers. */
10015 /* Encodings for the different types for various Neon opcodes. */
10017 /* An "invalid" code for the following tables. */
10020 struct neon_tab_entry
10023 unsigned float_or_poly
;
10024 unsigned scalar_or_imm
;
10027 /* Map overloaded Neon opcodes to their respective encodings. */
10028 #define NEON_ENC_TAB \
10029 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10030 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10031 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10032 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10033 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10034 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10035 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10036 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10037 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10038 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10039 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10040 /* Register variants of the following two instructions are encoded as
10041 vcge / vcgt with the operands reversed. */ \
10042 X(vclt, 0x0000310, 0x1000e00, 0x1b10200), \
10043 X(vcle, 0x0000300, 0x1200e00, 0x1b10180), \
10044 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10045 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10046 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10047 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10048 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10049 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10050 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10051 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10052 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10053 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10054 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10055 X(vshl, 0x0000400, N_INV, 0x0800510), \
10056 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10057 X(vand, 0x0000110, N_INV, 0x0800030), \
10058 X(vbic, 0x0100110, N_INV, 0x0800030), \
10059 X(veor, 0x1000110, N_INV, N_INV), \
10060 X(vorn, 0x0300110, N_INV, 0x0800010), \
10061 X(vorr, 0x0200110, N_INV, 0x0800010), \
10062 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10063 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10064 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10065 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10066 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10067 X(vst1, 0x0000000, 0x0800000, N_INV), \
10068 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10069 X(vst2, 0x0000100, 0x0800100, N_INV), \
10070 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10071 X(vst3, 0x0000200, 0x0800200, N_INV), \
10072 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10073 X(vst4, 0x0000300, 0x0800300, N_INV), \
10074 X(vmovn, 0x1b20200, N_INV, N_INV), \
10075 X(vtrn, 0x1b20080, N_INV, N_INV), \
10076 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10077 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10078 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10079 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10080 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10081 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10082 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10083 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10084 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10088 #define X(OPC,I,F,S) N_MNEM_##OPC
10093 static const struct neon_tab_entry neon_enc_tab
[] =
10095 #define X(OPC,I,F,S) { (I), (F), (S) }
10100 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10101 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10102 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10103 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10104 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10105 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10106 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10107 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10108 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10109 #define NEON_ENC_SINGLE(X) \
10110 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10111 #define NEON_ENC_DOUBLE(X) \
10112 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10114 /* Define shapes for instruction operands. The following mnemonic characters
10115 are used in this table:
10117 F - VFP S<n> register
10118 D - Neon D<n> register
10119 Q - Neon Q<n> register
10123 L - D<n> register list
10125 This table is used to generate various data:
10126 - enumerations of the form NS_DDR to be used as arguments to
10128 - a table classifying shapes into single, double, quad, mixed.
10129 - a table used to drive neon_select_shape.
10132 #define NEON_SHAPE_DEF \
10133 X(3, (D, D, D), DOUBLE), \
10134 X(3, (Q, Q, Q), QUAD), \
10135 X(3, (D, D, I), DOUBLE), \
10136 X(3, (Q, Q, I), QUAD), \
10137 X(3, (D, D, S), DOUBLE), \
10138 X(3, (Q, Q, S), QUAD), \
10139 X(2, (D, D), DOUBLE), \
10140 X(2, (Q, Q), QUAD), \
10141 X(2, (D, S), DOUBLE), \
10142 X(2, (Q, S), QUAD), \
10143 X(2, (D, R), DOUBLE), \
10144 X(2, (Q, R), QUAD), \
10145 X(2, (D, I), DOUBLE), \
10146 X(2, (Q, I), QUAD), \
10147 X(3, (D, L, D), DOUBLE), \
10148 X(2, (D, Q), MIXED), \
10149 X(2, (Q, D), MIXED), \
10150 X(3, (D, Q, I), MIXED), \
10151 X(3, (Q, D, I), MIXED), \
10152 X(3, (Q, D, D), MIXED), \
10153 X(3, (D, Q, Q), MIXED), \
10154 X(3, (Q, Q, D), MIXED), \
10155 X(3, (Q, D, S), MIXED), \
10156 X(3, (D, Q, S), MIXED), \
10157 X(4, (D, D, D, I), DOUBLE), \
10158 X(4, (Q, Q, Q, I), QUAD), \
10159 X(2, (F, F), SINGLE), \
10160 X(3, (F, F, F), SINGLE), \
10161 X(2, (F, I), SINGLE), \
10162 X(2, (F, D), MIXED), \
10163 X(2, (D, F), MIXED), \
10164 X(3, (F, F, I), MIXED), \
10165 X(4, (R, R, F, F), SINGLE), \
10166 X(4, (F, F, R, R), SINGLE), \
10167 X(3, (D, R, R), DOUBLE), \
10168 X(3, (R, R, D), DOUBLE), \
10169 X(2, (S, R), SINGLE), \
10170 X(2, (R, S), SINGLE), \
10171 X(2, (F, R), SINGLE), \
10172 X(2, (R, F), SINGLE)
10174 #define S2(A,B) NS_##A##B
10175 #define S3(A,B,C) NS_##A##B##C
10176 #define S4(A,B,C,D) NS_##A##B##C##D
10178 #define X(N, L, C) S##N L
10191 enum neon_shape_class
10199 #define X(N, L, C) SC_##C
10201 static enum neon_shape_class neon_shape_class
[] =
10219 /* Register widths of above. */
10220 static unsigned neon_shape_el_size
[] =
10231 struct neon_shape_info
10234 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
10237 #define S2(A,B) { SE_##A, SE_##B }
10238 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10239 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10241 #define X(N, L, C) { N, S##N L }
10243 static struct neon_shape_info neon_shape_tab
[] =
10253 /* Bit masks used in type checking given instructions.
10254 'N_EQK' means the type must be the same as (or based on in some way) the key
10255 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10256 set, various other bits can be set as well in order to modify the meaning of
10257 the type constraint. */
10259 enum neon_type_mask
10281 N_KEY
= 0x100000, /* key element (main type specifier). */
10282 N_EQK
= 0x200000, /* given operand has the same type & size as the key. */
10283 N_VFP
= 0x400000, /* VFP mode: operand size must match register width. */
10284 N_DBL
= 0x000001, /* if N_EQK, this operand is twice the size. */
10285 N_HLF
= 0x000002, /* if N_EQK, this operand is half the size. */
10286 N_SGN
= 0x000004, /* if N_EQK, this operand is forced to be signed. */
10287 N_UNS
= 0x000008, /* if N_EQK, this operand is forced to be unsigned. */
10288 N_INT
= 0x000010, /* if N_EQK, this operand is forced to be integer. */
10289 N_FLT
= 0x000020, /* if N_EQK, this operand is forced to be float. */
10290 N_SIZ
= 0x000040, /* if N_EQK, this operand is forced to be size-only. */
10292 N_MAX_NONSPECIAL
= N_F64
10295 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10297 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10298 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10299 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10300 #define N_SUF_32 (N_SU_32 | N_F32)
10301 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10302 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10304 /* Pass this as the first type argument to neon_check_type to ignore types
10306 #define N_IGNORE_TYPE (N_KEY | N_EQK)
10308 /* Select a "shape" for the current instruction (describing register types or
10309 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10310 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10311 function of operand parsing, so this function doesn't need to be called.
10312 Shapes should be listed in order of decreasing length. */
10314 static enum neon_shape
10315 neon_select_shape (enum neon_shape shape
, ...)
10318 enum neon_shape first_shape
= shape
;
10320 /* Fix missing optional operands. FIXME: we don't know at this point how
10321 many arguments we should have, so this makes the assumption that we have
10322 > 1. This is true of all current Neon opcodes, I think, but may not be
10323 true in the future. */
10324 if (!inst
.operands
[1].present
)
10325 inst
.operands
[1] = inst
.operands
[0];
10327 va_start (ap
, shape
);
10329 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
10334 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
10336 if (!inst
.operands
[j
].present
)
10342 switch (neon_shape_tab
[shape
].el
[j
])
10345 if (!(inst
.operands
[j
].isreg
10346 && inst
.operands
[j
].isvec
10347 && inst
.operands
[j
].issingle
10348 && !inst
.operands
[j
].isquad
))
10353 if (!(inst
.operands
[j
].isreg
10354 && inst
.operands
[j
].isvec
10355 && !inst
.operands
[j
].isquad
10356 && !inst
.operands
[j
].issingle
))
10361 if (!(inst
.operands
[j
].isreg
10362 && !inst
.operands
[j
].isvec
))
10367 if (!(inst
.operands
[j
].isreg
10368 && inst
.operands
[j
].isvec
10369 && inst
.operands
[j
].isquad
10370 && !inst
.operands
[j
].issingle
))
10375 if (!(!inst
.operands
[j
].isreg
10376 && !inst
.operands
[j
].isscalar
))
10381 if (!(!inst
.operands
[j
].isreg
10382 && inst
.operands
[j
].isscalar
))
10396 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
10397 first_error (_("invalid instruction shape"));
10402 /* True if SHAPE is predominantly a quadword operation (most of the time, this
10403 means the Q bit should be set). */
10406 neon_quad (enum neon_shape shape
)
10408 return neon_shape_class
[shape
] == SC_QUAD
;
10412 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
10415 /* Allow modification to be made to types which are constrained to be
10416 based on the key element, based on bits set alongside N_EQK. */
10417 if ((typebits
& N_EQK
) != 0)
10419 if ((typebits
& N_HLF
) != 0)
10421 else if ((typebits
& N_DBL
) != 0)
10423 if ((typebits
& N_SGN
) != 0)
10424 *g_type
= NT_signed
;
10425 else if ((typebits
& N_UNS
) != 0)
10426 *g_type
= NT_unsigned
;
10427 else if ((typebits
& N_INT
) != 0)
10428 *g_type
= NT_integer
;
10429 else if ((typebits
& N_FLT
) != 0)
10430 *g_type
= NT_float
;
10431 else if ((typebits
& N_SIZ
) != 0)
10432 *g_type
= NT_untyped
;
10436 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10437 operand type, i.e. the single type specified in a Neon instruction when it
10438 is the only one given. */
10440 static struct neon_type_el
10441 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
10443 struct neon_type_el dest
= *key
;
10445 assert ((thisarg
& N_EQK
) != 0);
10447 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
10452 /* Convert Neon type and size into compact bitmask representation. */
10454 static enum neon_type_mask
10455 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
10462 case 8: return N_8
;
10463 case 16: return N_16
;
10464 case 32: return N_32
;
10465 case 64: return N_64
;
10473 case 8: return N_I8
;
10474 case 16: return N_I16
;
10475 case 32: return N_I32
;
10476 case 64: return N_I64
;
10484 case 32: return N_F32
;
10485 case 64: return N_F64
;
10493 case 8: return N_P8
;
10494 case 16: return N_P16
;
10502 case 8: return N_S8
;
10503 case 16: return N_S16
;
10504 case 32: return N_S32
;
10505 case 64: return N_S64
;
10513 case 8: return N_U8
;
10514 case 16: return N_U16
;
10515 case 32: return N_U32
;
10516 case 64: return N_U64
;
10527 /* Convert compact Neon bitmask type representation to a type and size. Only
10528 handles the case where a single bit is set in the mask. */
10531 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
10532 enum neon_type_mask mask
)
10534 if ((mask
& N_EQK
) != 0)
10537 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
10539 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
10541 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
10543 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
10548 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
10550 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
10551 *type
= NT_unsigned
;
10552 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
10553 *type
= NT_integer
;
10554 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
10555 *type
= NT_untyped
;
10556 else if ((mask
& (N_P8
| N_P16
)) != 0)
10558 else if ((mask
& (N_F32
| N_F64
)) != 0)
10566 /* Modify a bitmask of allowed types. This is only needed for type
10570 modify_types_allowed (unsigned allowed
, unsigned mods
)
10573 enum neon_el_type type
;
10579 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
10581 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
10583 neon_modify_type_size (mods
, &type
, &size
);
10584 destmask
|= type_chk_of_el_type (type
, size
);
10591 /* Check type and return type classification.
10592 The manual states (paraphrase): If one datatype is given, it indicates the
10594 - the second operand, if there is one
10595 - the operand, if there is no second operand
10596 - the result, if there are no operands.
10597 This isn't quite good enough though, so we use a concept of a "key" datatype
10598 which is set on a per-instruction basis, which is the one which matters when
10599 only one data type is written.
10600 Note: this function has side-effects (e.g. filling in missing operands). All
10601 Neon instructions should call it before performing bit encoding. */
10603 static struct neon_type_el
10604 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
10607 unsigned i
, pass
, key_el
= 0;
10608 unsigned types
[NEON_MAX_TYPE_ELS
];
10609 enum neon_el_type k_type
= NT_invtype
;
10610 unsigned k_size
= -1u;
10611 struct neon_type_el badtype
= {NT_invtype
, -1};
10612 unsigned key_allowed
= 0;
10614 /* Optional registers in Neon instructions are always (not) in operand 1.
10615 Fill in the missing operand here, if it was omitted. */
10616 if (els
> 1 && !inst
.operands
[1].present
)
10617 inst
.operands
[1] = inst
.operands
[0];
10619 /* Suck up all the varargs. */
10621 for (i
= 0; i
< els
; i
++)
10623 unsigned thisarg
= va_arg (ap
, unsigned);
10624 if (thisarg
== N_IGNORE_TYPE
)
10629 types
[i
] = thisarg
;
10630 if ((thisarg
& N_KEY
) != 0)
10635 if (inst
.vectype
.elems
> 0)
10636 for (i
= 0; i
< els
; i
++)
10637 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
10639 first_error (_("types specified in both the mnemonic and operands"));
10643 /* Duplicate inst.vectype elements here as necessary.
10644 FIXME: No idea if this is exactly the same as the ARM assembler,
10645 particularly when an insn takes one register and one non-register
10647 if (inst
.vectype
.elems
== 1 && els
> 1)
10650 inst
.vectype
.elems
= els
;
10651 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
10652 for (j
= 0; j
< els
; j
++)
10654 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
10657 else if (inst
.vectype
.elems
== 0 && els
> 0)
10660 /* No types were given after the mnemonic, so look for types specified
10661 after each operand. We allow some flexibility here; as long as the
10662 "key" operand has a type, we can infer the others. */
10663 for (j
= 0; j
< els
; j
++)
10664 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
10665 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
10667 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
10669 for (j
= 0; j
< els
; j
++)
10670 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
10671 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
10676 first_error (_("operand types can't be inferred"));
10680 else if (inst
.vectype
.elems
!= els
)
10682 first_error (_("type specifier has the wrong number of parts"));
10686 for (pass
= 0; pass
< 2; pass
++)
10688 for (i
= 0; i
< els
; i
++)
10690 unsigned thisarg
= types
[i
];
10691 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
10692 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
10693 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
10694 unsigned g_size
= inst
.vectype
.el
[i
].size
;
10696 /* Decay more-specific signed & unsigned types to sign-insensitive
10697 integer types if sign-specific variants are unavailable. */
10698 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
10699 && (types_allowed
& N_SU_ALL
) == 0)
10700 g_type
= NT_integer
;
10702 /* If only untyped args are allowed, decay any more specific types to
10703 them. Some instructions only care about signs for some element
10704 sizes, so handle that properly. */
10705 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
10706 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
10707 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
10708 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
10709 g_type
= NT_untyped
;
10713 if ((thisarg
& N_KEY
) != 0)
10717 key_allowed
= thisarg
& ~N_KEY
;
10722 if ((thisarg
& N_VFP
) != 0)
10724 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
10725 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
10727 /* In VFP mode, operands must match register widths. If we
10728 have a key operand, use its width, else use the width of
10729 the current operand. */
10735 if (regwidth
!= match
)
10737 first_error (_("operand size must match register width"));
10742 if ((thisarg
& N_EQK
) == 0)
10744 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
10746 if ((given_type
& types_allowed
) == 0)
10748 first_error (_("bad type in Neon instruction"));
10754 enum neon_el_type mod_k_type
= k_type
;
10755 unsigned mod_k_size
= k_size
;
10756 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
10757 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
10759 first_error (_("inconsistent types in Neon instruction"));
10767 return inst
.vectype
.el
[key_el
];
10770 /* Neon-style VFP instruction forwarding. */
10772 /* Thumb VFP instructions have 0xE in the condition field. */
10775 do_vfp_cond_or_thumb (void)
10778 inst
.instruction
|= 0xe0000000;
10780 inst
.instruction
|= inst
.cond
<< 28;
10783 /* Look up and encode a simple mnemonic, for use as a helper function for the
10784 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
10785 etc. It is assumed that operand parsing has already been done, and that the
10786 operands are in the form expected by the given opcode (this isn't necessarily
10787 the same as the form in which they were parsed, hence some massaging must
10788 take place before this function is called).
10789 Checks current arch version against that in the looked-up opcode. */
10792 do_vfp_nsyn_opcode (const char *opname
)
10794 const struct asm_opcode
*opcode
;
10796 opcode
= hash_find (arm_ops_hsh
, opname
);
10801 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
10802 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
10807 inst
.instruction
= opcode
->tvalue
;
10808 opcode
->tencode ();
10812 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
10813 opcode
->aencode ();
10818 do_vfp_nsyn_add_sub (enum neon_shape rs
)
10820 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
10825 do_vfp_nsyn_opcode ("fadds");
10827 do_vfp_nsyn_opcode ("fsubs");
10832 do_vfp_nsyn_opcode ("faddd");
10834 do_vfp_nsyn_opcode ("fsubd");
10838 /* Check operand types to see if this is a VFP instruction, and if so call
10842 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
10844 enum neon_shape rs
;
10845 struct neon_type_el et
;
10850 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
10851 et
= neon_check_type (2, rs
,
10852 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
10856 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
10857 et
= neon_check_type (3, rs
,
10858 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
10865 if (et
.type
!= NT_invtype
)
10877 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
10879 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
10884 do_vfp_nsyn_opcode ("fmacs");
10886 do_vfp_nsyn_opcode ("fmscs");
10891 do_vfp_nsyn_opcode ("fmacd");
10893 do_vfp_nsyn_opcode ("fmscd");
10898 do_vfp_nsyn_mul (enum neon_shape rs
)
10901 do_vfp_nsyn_opcode ("fmuls");
10903 do_vfp_nsyn_opcode ("fmuld");
10907 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
10909 int is_neg
= (inst
.instruction
& 0x80) != 0;
10910 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
10915 do_vfp_nsyn_opcode ("fnegs");
10917 do_vfp_nsyn_opcode ("fabss");
10922 do_vfp_nsyn_opcode ("fnegd");
10924 do_vfp_nsyn_opcode ("fabsd");
10928 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
10929 insns belong to Neon, and are handled elsewhere. */
10932 do_vfp_nsyn_ldm_stm (int is_dbmode
)
10934 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
10938 do_vfp_nsyn_opcode ("fldmdbs");
10940 do_vfp_nsyn_opcode ("fldmias");
10945 do_vfp_nsyn_opcode ("fstmdbs");
10947 do_vfp_nsyn_opcode ("fstmias");
10952 do_vfp_nsyn_sqrt (void)
10954 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
10955 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
10958 do_vfp_nsyn_opcode ("fsqrts");
10960 do_vfp_nsyn_opcode ("fsqrtd");
10964 do_vfp_nsyn_div (void)
10966 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
10967 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
10968 N_F32
| N_F64
| N_KEY
| N_VFP
);
10971 do_vfp_nsyn_opcode ("fdivs");
10973 do_vfp_nsyn_opcode ("fdivd");
10977 do_vfp_nsyn_nmul (void)
10979 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
10980 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
10981 N_F32
| N_F64
| N_KEY
| N_VFP
);
10985 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
10986 do_vfp_sp_dyadic ();
10990 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
10991 do_vfp_dp_rd_rn_rm ();
10993 do_vfp_cond_or_thumb ();
10997 do_vfp_nsyn_cmp (void)
10999 if (inst
.operands
[1].isreg
)
11001 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11002 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11006 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11007 do_vfp_sp_monadic ();
11011 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11012 do_vfp_dp_rd_rm ();
11017 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
11018 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
11020 switch (inst
.instruction
& 0x0fffffff)
11023 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
11026 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
11034 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11035 do_vfp_sp_compare_z ();
11039 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11043 do_vfp_cond_or_thumb ();
11047 nsyn_insert_sp (void)
11049 inst
.operands
[1] = inst
.operands
[0];
11050 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
11051 inst
.operands
[0].reg
= 13;
11052 inst
.operands
[0].isreg
= 1;
11053 inst
.operands
[0].writeback
= 1;
11054 inst
.operands
[0].present
= 1;
11058 do_vfp_nsyn_push (void)
11061 if (inst
.operands
[1].issingle
)
11062 do_vfp_nsyn_opcode ("fstmdbs");
11064 do_vfp_nsyn_opcode ("fstmdbd");
11068 do_vfp_nsyn_pop (void)
11071 if (inst
.operands
[1].issingle
)
11072 do_vfp_nsyn_opcode ("fldmdbs");
11074 do_vfp_nsyn_opcode ("fldmdbd");
11077 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11078 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11081 neon_dp_fixup (unsigned i
)
11085 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11099 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11103 neon_logbits (unsigned x
)
11105 return ffs (x
) - 4;
11108 #define LOW4(R) ((R) & 0xf)
11109 #define HI1(R) (((R) >> 4) & 1)
11111 /* Encode insns with bit pattern:
11113 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11114 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11116 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11117 different meaning for some instruction. */
11120 neon_three_same (int isquad
, int ubit
, int size
)
11122 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11123 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11124 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11125 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11126 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
11127 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
11128 inst
.instruction
|= (isquad
!= 0) << 6;
11129 inst
.instruction
|= (ubit
!= 0) << 24;
11131 inst
.instruction
|= neon_logbits (size
) << 20;
11133 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11136 /* Encode instructions of the form:
11138 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11139 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11141 Don't write size if SIZE == -1. */
11144 neon_two_same (int qbit
, int ubit
, int size
)
11146 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11147 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11148 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11149 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11150 inst
.instruction
|= (qbit
!= 0) << 6;
11151 inst
.instruction
|= (ubit
!= 0) << 24;
11154 inst
.instruction
|= neon_logbits (size
) << 18;
11156 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11159 /* Neon instruction encoders, in approximate order of appearance. */
11162 do_neon_dyadic_i_su (void)
11164 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11165 struct neon_type_el et
= neon_check_type (3, rs
,
11166 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
11167 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11171 do_neon_dyadic_i64_su (void)
11173 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11174 struct neon_type_el et
= neon_check_type (3, rs
,
11175 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11176 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11180 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
11183 unsigned size
= et
.size
>> 3;
11184 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11185 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11186 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11187 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11188 inst
.instruction
|= (isquad
!= 0) << 6;
11189 inst
.instruction
|= immbits
<< 16;
11190 inst
.instruction
|= (size
>> 3) << 7;
11191 inst
.instruction
|= (size
& 0x7) << 19;
11193 inst
.instruction
|= (uval
!= 0) << 24;
11195 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11199 do_neon_shl_imm (void)
11201 if (!inst
.operands
[2].isreg
)
11203 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11204 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
11205 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11206 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
11210 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11211 struct neon_type_el et
= neon_check_type (3, rs
,
11212 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11213 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11214 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11219 do_neon_qshl_imm (void)
11221 if (!inst
.operands
[2].isreg
)
11223 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11224 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
11225 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11226 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
11227 inst
.operands
[2].imm
);
11231 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11232 struct neon_type_el et
= neon_check_type (3, rs
,
11233 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11234 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11235 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11240 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
11242 /* Handle .I8 and .I64 as pseudo-instructions. */
11246 /* Unfortunately, this will make everything apart from zero out-of-range.
11247 FIXME is this the intended semantics? There doesn't seem much point in
11248 accepting .I8 if so. */
11249 immediate
|= immediate
<< 8;
11253 /* Similarly, anything other than zero will be replicated in bits [63:32],
11254 which probably isn't want we want if we specified .I64. */
11255 if (immediate
!= 0)
11256 goto bad_immediate
;
11262 if (immediate
== (immediate
& 0x000000ff))
11264 *immbits
= immediate
;
11265 return (size
== 16) ? 0x9 : 0x1;
11267 else if (immediate
== (immediate
& 0x0000ff00))
11269 *immbits
= immediate
>> 8;
11270 return (size
== 16) ? 0xb : 0x3;
11272 else if (immediate
== (immediate
& 0x00ff0000))
11274 *immbits
= immediate
>> 16;
11277 else if (immediate
== (immediate
& 0xff000000))
11279 *immbits
= immediate
>> 24;
11284 first_error (_("immediate value out of range"));
11288 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11292 neon_bits_same_in_bytes (unsigned imm
)
11294 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
11295 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
11296 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
11297 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
11300 /* For immediate of above form, return 0bABCD. */
11303 neon_squash_bits (unsigned imm
)
11305 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
11306 | ((imm
& 0x01000000) >> 21);
11309 /* Compress quarter-float representation to 0b...000 abcdefgh. */
11312 neon_qfloat_bits (unsigned imm
)
11314 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
11317 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11318 the instruction. *OP is passed as the initial value of the op field, and
11319 may be set to a different value depending on the constant (i.e.
11320 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11324 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, unsigned *immbits
,
11325 int *op
, int size
, enum neon_el_type type
)
11327 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
11329 if (size
!= 32 || *op
== 1)
11331 *immbits
= neon_qfloat_bits (immlo
);
11334 else if (size
== 64 && neon_bits_same_in_bytes (immhi
)
11335 && neon_bits_same_in_bytes (immlo
))
11337 /* Check this one first so we don't have to bother with immhi in later
11341 *immbits
= (neon_squash_bits (immhi
) << 4) | neon_squash_bits (immlo
);
11345 else if (immhi
!= 0)
11347 else if (immlo
== (immlo
& 0x000000ff))
11349 /* 64-bit case was already handled. Don't allow MVN with 8-bit
11351 if ((size
!= 8 && size
!= 16 && size
!= 32)
11352 || (size
== 8 && *op
== 1))
11355 return (size
== 8) ? 0xe : (size
== 16) ? 0x8 : 0x0;
11357 else if (immlo
== (immlo
& 0x0000ff00))
11359 if (size
!= 16 && size
!= 32)
11361 *immbits
= immlo
>> 8;
11362 return (size
== 16) ? 0xa : 0x2;
11364 else if (immlo
== (immlo
& 0x00ff0000))
11368 *immbits
= immlo
>> 16;
11371 else if (immlo
== (immlo
& 0xff000000))
11375 *immbits
= immlo
>> 24;
11378 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
11382 *immbits
= (immlo
>> 8) & 0xff;
11385 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
11389 *immbits
= (immlo
>> 16) & 0xff;
11396 /* Write immediate bits [7:0] to the following locations:
11398 |28/24|23 19|18 16|15 4|3 0|
11399 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11401 This function is used by VMOV/VMVN/VORR/VBIC. */
11404 neon_write_immbits (unsigned immbits
)
11406 inst
.instruction
|= immbits
& 0xf;
11407 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
11408 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
11411 /* Invert low-order SIZE bits of XHI:XLO. */
11414 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
11416 unsigned immlo
= xlo
? *xlo
: 0;
11417 unsigned immhi
= xhi
? *xhi
: 0;
11422 immlo
= (~immlo
) & 0xff;
11426 immlo
= (~immlo
) & 0xffff;
11430 immhi
= (~immhi
) & 0xffffffff;
11431 /* fall through. */
11434 immlo
= (~immlo
) & 0xffffffff;
11449 do_neon_logic (void)
11451 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
11453 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11454 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11455 /* U bit and size field were set as part of the bitmask. */
11456 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11457 neon_three_same (neon_quad (rs
), 0, -1);
11461 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
11462 struct neon_type_el et
= neon_check_type (2, rs
,
11463 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
11464 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
11468 if (et
.type
== NT_invtype
)
11471 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11476 cmode
= neon_cmode_for_logic_imm (inst
.operands
[1].imm
, &immbits
,
11481 cmode
= neon_cmode_for_logic_imm (inst
.operands
[1].imm
, &immbits
,
11486 /* Pseudo-instruction for VBIC. */
11487 immbits
= inst
.operands
[1].imm
;
11488 neon_invert_size (&immbits
, 0, et
.size
);
11489 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11493 /* Pseudo-instruction for VORR. */
11494 immbits
= inst
.operands
[1].imm
;
11495 neon_invert_size (&immbits
, 0, et
.size
);
11496 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11506 inst
.instruction
|= neon_quad (rs
) << 6;
11507 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11508 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11509 inst
.instruction
|= cmode
<< 8;
11510 neon_write_immbits (immbits
);
11512 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11517 do_neon_bitfield (void)
11519 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11520 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11521 neon_three_same (neon_quad (rs
), 0, -1);
11525 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
11528 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11529 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
11531 if (et
.type
== NT_float
)
11533 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
11534 neon_three_same (neon_quad (rs
), 0, -1);
11538 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11539 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
11544 do_neon_dyadic_if_su (void)
11546 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
11550 do_neon_dyadic_if_su_d (void)
11552 /* This version only allow D registers, but that constraint is enforced during
11553 operand parsing so we don't need to do anything extra here. */
11554 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
11558 do_neon_dyadic_if_i (void)
11560 neon_dyadic_misc (NT_unsigned
, N_IF_32
, 0);
11564 do_neon_dyadic_if_i_d (void)
11566 neon_dyadic_misc (NT_unsigned
, N_IF_32
, 0);
11569 enum vfp_or_neon_is_neon_bits
11572 NEON_CHECK_ARCH
= 2
11575 /* Call this function if an instruction which may have belonged to the VFP or
11576 Neon instruction sets, but turned out to be a Neon instruction (due to the
11577 operand types involved, etc.). We have to check and/or fix-up a couple of
11580 - Make sure the user hasn't attempted to make a Neon instruction
11582 - Alter the value in the condition code field if necessary.
11583 - Make sure that the arch supports Neon instructions.
11585 Which of these operations take place depends on bits from enum
11586 vfp_or_neon_is_neon_bits.
11588 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
11589 current instruction's condition is COND_ALWAYS, the condition field is
11590 changed to inst.uncond_value. This is necessary because instructions shared
11591 between VFP and Neon may be conditional for the VFP variants only, and the
11592 unconditional Neon version must have, e.g., 0xF in the condition field. */
11595 vfp_or_neon_is_neon (unsigned check
)
11597 /* Conditions are always legal in Thumb mode (IT blocks). */
11598 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
11600 if (inst
.cond
!= COND_ALWAYS
)
11602 first_error (_(BAD_COND
));
11605 if (inst
.uncond_value
!= -1)
11606 inst
.instruction
|= inst
.uncond_value
<< 28;
11609 if ((check
& NEON_CHECK_ARCH
)
11610 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
11612 first_error (_(BAD_FPU
));
11620 do_neon_addsub_if_i (void)
11622 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
11625 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11628 /* The "untyped" case can't happen. Do this to stop the "U" bit being
11629 affected if we specify unsigned args. */
11630 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
11633 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
11635 V<op> A,B (A is operand 0, B is operand 2)
11640 so handle that case specially. */
11643 neon_exchange_operands (void)
11645 void *scratch
= alloca (sizeof (inst
.operands
[0]));
11646 if (inst
.operands
[1].present
)
11648 /* Swap operands[1] and operands[2]. */
11649 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
11650 inst
.operands
[1] = inst
.operands
[2];
11651 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
11655 inst
.operands
[1] = inst
.operands
[2];
11656 inst
.operands
[2] = inst
.operands
[0];
11661 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
11663 if (inst
.operands
[2].isreg
)
11666 neon_exchange_operands ();
11667 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
11671 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11672 struct neon_type_el et
= neon_check_type (2, rs
,
11673 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
11675 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11676 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11677 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11678 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11679 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11680 inst
.instruction
|= neon_quad (rs
) << 6;
11681 inst
.instruction
|= (et
.type
== NT_float
) << 10;
11682 inst
.instruction
|= neon_logbits (et
.size
) << 18;
11684 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11691 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
11695 do_neon_cmp_inv (void)
11697 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
11703 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
11706 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
11707 scalars, which are encoded in 5 bits, M : Rm.
11708 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
11709 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
11713 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
11715 unsigned regno
= NEON_SCALAR_REG (scalar
);
11716 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
11721 if (regno
> 7 || elno
> 3)
11723 return regno
| (elno
<< 3);
11726 if (regno
> 15 || elno
> 1)
11728 return regno
| (elno
<< 4);
11732 first_error (_("scalar out of range for multiply instruction"));
11738 /* Encode multiply / multiply-accumulate scalar instructions. */
11741 neon_mul_mac (struct neon_type_el et
, int ubit
)
11745 /* Give a more helpful error message if we have an invalid type. */
11746 if (et
.type
== NT_invtype
)
11749 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
11750 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11751 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11752 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11753 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11754 inst
.instruction
|= LOW4 (scalar
);
11755 inst
.instruction
|= HI1 (scalar
) << 5;
11756 inst
.instruction
|= (et
.type
== NT_float
) << 8;
11757 inst
.instruction
|= neon_logbits (et
.size
) << 20;
11758 inst
.instruction
|= (ubit
!= 0) << 24;
11760 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11764 do_neon_mac_maybe_scalar (void)
11766 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
11769 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11772 if (inst
.operands
[2].isscalar
)
11774 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
11775 struct neon_type_el et
= neon_check_type (3, rs
,
11776 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
11777 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
11778 neon_mul_mac (et
, neon_quad (rs
));
11781 do_neon_dyadic_if_i ();
11787 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11788 struct neon_type_el et
= neon_check_type (3, rs
,
11789 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
11790 neon_three_same (neon_quad (rs
), 0, et
.size
);
11793 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
11794 same types as the MAC equivalents. The polynomial type for this instruction
11795 is encoded the same as the integer type. */
11800 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
11803 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11806 if (inst
.operands
[2].isscalar
)
11807 do_neon_mac_maybe_scalar ();
11809 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
11813 do_neon_qdmulh (void)
11815 if (inst
.operands
[2].isscalar
)
11817 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
11818 struct neon_type_el et
= neon_check_type (3, rs
,
11819 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
11820 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
11821 neon_mul_mac (et
, neon_quad (rs
));
11825 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11826 struct neon_type_el et
= neon_check_type (3, rs
,
11827 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
11828 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11829 /* The U bit (rounding) comes from bit mask. */
11830 neon_three_same (neon_quad (rs
), 0, et
.size
);
11835 do_neon_fcmp_absolute (void)
11837 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11838 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
11839 /* Size field comes from bit mask. */
11840 neon_three_same (neon_quad (rs
), 1, -1);
11844 do_neon_fcmp_absolute_inv (void)
11846 neon_exchange_operands ();
11847 do_neon_fcmp_absolute ();
11851 do_neon_step (void)
11853 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11854 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
11855 neon_three_same (neon_quad (rs
), 0, -1);
11859 do_neon_abs_neg (void)
11861 enum neon_shape rs
;
11862 struct neon_type_el et
;
11864 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
11867 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11870 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
11871 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
11873 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11874 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11875 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11876 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11877 inst
.instruction
|= neon_quad (rs
) << 6;
11878 inst
.instruction
|= (et
.type
== NT_float
) << 10;
11879 inst
.instruction
|= neon_logbits (et
.size
) << 18;
11881 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11887 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11888 struct neon_type_el et
= neon_check_type (2, rs
,
11889 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
11890 int imm
= inst
.operands
[2].imm
;
11891 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
11892 _("immediate out of range for insert"));
11893 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
11899 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11900 struct neon_type_el et
= neon_check_type (2, rs
,
11901 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
11902 int imm
= inst
.operands
[2].imm
;
11903 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
11904 _("immediate out of range for insert"));
11905 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
11909 do_neon_qshlu_imm (void)
11911 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11912 struct neon_type_el et
= neon_check_type (2, rs
,
11913 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
11914 int imm
= inst
.operands
[2].imm
;
11915 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
11916 _("immediate out of range for shift"));
11917 /* Only encodes the 'U present' variant of the instruction.
11918 In this case, signed types have OP (bit 8) set to 0.
11919 Unsigned types have OP set to 1. */
11920 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
11921 /* The rest of the bits are the same as other immediate shifts. */
11922 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
11926 do_neon_qmovn (void)
11928 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
11929 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
11930 /* Saturating move where operands can be signed or unsigned, and the
11931 destination has the same signedness. */
11932 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11933 if (et
.type
== NT_unsigned
)
11934 inst
.instruction
|= 0xc0;
11936 inst
.instruction
|= 0x80;
11937 neon_two_same (0, 1, et
.size
/ 2);
11941 do_neon_qmovun (void)
11943 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
11944 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
11945 /* Saturating move with unsigned results. Operands must be signed. */
11946 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11947 neon_two_same (0, 1, et
.size
/ 2);
11951 do_neon_rshift_sat_narrow (void)
11953 /* FIXME: Types for narrowing. If operands are signed, results can be signed
11954 or unsigned. If operands are unsigned, results must also be unsigned. */
11955 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
11956 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
11957 int imm
= inst
.operands
[2].imm
;
11958 /* This gets the bounds check, size encoding and immediate bits calculation
11962 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
11963 VQMOVN.I<size> <Dd>, <Qm>. */
11966 inst
.operands
[2].present
= 0;
11967 inst
.instruction
= N_MNEM_vqmovn
;
11972 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
11973 _("immediate out of range"));
11974 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
11978 do_neon_rshift_sat_narrow_u (void)
11980 /* FIXME: Types for narrowing. If operands are signed, results can be signed
11981 or unsigned. If operands are unsigned, results must also be unsigned. */
11982 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
11983 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
11984 int imm
= inst
.operands
[2].imm
;
11985 /* This gets the bounds check, size encoding and immediate bits calculation
11989 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
11990 VQMOVUN.I<size> <Dd>, <Qm>. */
11993 inst
.operands
[2].present
= 0;
11994 inst
.instruction
= N_MNEM_vqmovun
;
11999 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12000 _("immediate out of range"));
12001 /* FIXME: The manual is kind of unclear about what value U should have in
12002 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12004 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
12008 do_neon_movn (void)
12010 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12011 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12012 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12013 neon_two_same (0, 1, et
.size
/ 2);
12017 do_neon_rshift_narrow (void)
12019 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12020 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12021 int imm
= inst
.operands
[2].imm
;
12022 /* This gets the bounds check, size encoding and immediate bits calculation
12026 /* If immediate is zero then we are a pseudo-instruction for
12027 VMOVN.I<size> <Dd>, <Qm> */
12030 inst
.operands
[2].present
= 0;
12031 inst
.instruction
= N_MNEM_vmovn
;
12036 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12037 _("immediate out of range for narrowing operation"));
12038 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
12042 do_neon_shll (void)
12044 /* FIXME: Type checking when lengthening. */
12045 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
12046 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
12047 unsigned imm
= inst
.operands
[2].imm
;
12049 if (imm
== et
.size
)
12051 /* Maximum shift variant. */
12052 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12053 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12054 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12055 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12056 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12057 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12059 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12063 /* A more-specific type check for non-max versions. */
12064 et
= neon_check_type (2, NS_QDI
,
12065 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12066 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12067 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
12071 /* Check the various types for the VCVT instruction, and return which version
12072 the current instruction is. */
12075 neon_cvt_flavour (enum neon_shape rs
)
12077 #define CVT_VAR(C,X,Y) \
12078 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12079 if (et.type != NT_invtype) \
12081 inst.error = NULL; \
12084 struct neon_type_el et
;
12085 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
12086 || rs
== NS_FF
) ? N_VFP
: 0;
12087 /* The instruction versions which take an immediate take one register
12088 argument, which is extended to the width of the full register. Thus the
12089 "source" and "destination" registers must have the same width. Hack that
12090 here by making the size equal to the key (wider, in this case) operand. */
12091 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
12093 CVT_VAR (0, N_S32
, N_F32
);
12094 CVT_VAR (1, N_U32
, N_F32
);
12095 CVT_VAR (2, N_F32
, N_S32
);
12096 CVT_VAR (3, N_F32
, N_U32
);
12100 /* VFP instructions. */
12101 CVT_VAR (4, N_F32
, N_F64
);
12102 CVT_VAR (5, N_F64
, N_F32
);
12103 CVT_VAR (6, N_S32
, N_F64
| key
);
12104 CVT_VAR (7, N_U32
, N_F64
| key
);
12105 CVT_VAR (8, N_F64
| key
, N_S32
);
12106 CVT_VAR (9, N_F64
| key
, N_U32
);
12107 /* VFP instructions with bitshift. */
12108 CVT_VAR (10, N_F32
| key
, N_S16
);
12109 CVT_VAR (11, N_F32
| key
, N_U16
);
12110 CVT_VAR (12, N_F64
| key
, N_S16
);
12111 CVT_VAR (13, N_F64
| key
, N_U16
);
12112 CVT_VAR (14, N_S16
, N_F32
| key
);
12113 CVT_VAR (15, N_U16
, N_F32
| key
);
12114 CVT_VAR (16, N_S16
, N_F64
| key
);
12115 CVT_VAR (17, N_U16
, N_F64
| key
);
12121 /* Neon-syntax VFP conversions. */
12124 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
12126 const char *opname
= 0;
12128 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
12130 /* Conversions with immediate bitshift. */
12131 const char *enc
[] =
12153 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12155 opname
= enc
[flavour
];
12156 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12157 _("operands 0 and 1 must be the same register"));
12158 inst
.operands
[1] = inst
.operands
[2];
12159 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
12164 /* Conversions without bitshift. */
12165 const char *enc
[] =
12179 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12180 opname
= enc
[flavour
];
12184 do_vfp_nsyn_opcode (opname
);
12188 do_vfp_nsyn_cvtz (void)
12190 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
12191 int flavour
= neon_cvt_flavour (rs
);
12192 const char *enc
[] =
12204 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
12205 do_vfp_nsyn_opcode (enc
[flavour
]);
12211 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
12212 NS_FD
, NS_DF
, NS_FF
, NS_NULL
);
12213 int flavour
= neon_cvt_flavour (rs
);
12215 /* VFP rather than Neon conversions. */
12218 do_vfp_nsyn_cvt (rs
, flavour
);
12227 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12230 /* Fixed-point conversion with #0 immediate is encoded as an
12231 integer conversion. */
12232 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
12234 unsigned immbits
= 32 - inst
.operands
[2].imm
;
12235 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12236 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12238 inst
.instruction
|= enctab
[flavour
];
12239 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12240 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12241 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12242 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12243 inst
.instruction
|= neon_quad (rs
) << 6;
12244 inst
.instruction
|= 1 << 21;
12245 inst
.instruction
|= immbits
<< 16;
12247 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12255 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
12257 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12259 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12263 inst
.instruction
|= enctab
[flavour
];
12265 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12266 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12267 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12268 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12269 inst
.instruction
|= neon_quad (rs
) << 6;
12270 inst
.instruction
|= 2 << 18;
12272 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12277 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12278 do_vfp_nsyn_cvt (rs
, flavour
);
12283 neon_move_immediate (void)
12285 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12286 struct neon_type_el et
= neon_check_type (2, rs
,
12287 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12288 unsigned immlo
, immhi
= 0, immbits
;
12291 constraint (et
.type
== NT_invtype
,
12292 _("operand size must be specified for immediate VMOV"));
12294 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12295 op
= (inst
.instruction
& (1 << 5)) != 0;
12297 immlo
= inst
.operands
[1].imm
;
12298 if (inst
.operands
[1].regisimm
)
12299 immhi
= inst
.operands
[1].reg
;
12301 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
12302 _("immediate has bits set outside the operand size"));
12304 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, &immbits
, &op
,
12305 et
.size
, et
.type
)) == FAIL
)
12307 /* Invert relevant bits only. */
12308 neon_invert_size (&immlo
, &immhi
, et
.size
);
12309 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12310 with one or the other; those cases are caught by
12311 neon_cmode_for_move_imm. */
12313 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, &immbits
, &op
,
12314 et
.size
, et
.type
)) == FAIL
)
12316 first_error (_("immediate out of range"));
12321 inst
.instruction
&= ~(1 << 5);
12322 inst
.instruction
|= op
<< 5;
12324 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12325 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12326 inst
.instruction
|= neon_quad (rs
) << 6;
12327 inst
.instruction
|= cmode
<< 8;
12329 neon_write_immbits (immbits
);
12335 if (inst
.operands
[1].isreg
)
12337 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12339 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12340 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12341 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12342 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12343 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12344 inst
.instruction
|= neon_quad (rs
) << 6;
12348 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12349 neon_move_immediate ();
12352 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12355 /* Encode instructions of form:
12357 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12358 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm |
12363 neon_mixed_length (struct neon_type_el et
, unsigned size
)
12365 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12366 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12367 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12368 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12369 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12370 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12371 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
12372 inst
.instruction
|= neon_logbits (size
) << 20;
12374 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12378 do_neon_dyadic_long (void)
12380 /* FIXME: Type checking for lengthening op. */
12381 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12382 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12383 neon_mixed_length (et
, et
.size
);
12387 do_neon_abal (void)
12389 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12390 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12391 neon_mixed_length (et
, et
.size
);
12395 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
12397 if (inst
.operands
[2].isscalar
)
12399 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
12400 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
12401 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12402 neon_mul_mac (et
, et
.type
== NT_unsigned
);
12406 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12407 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
12408 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12409 neon_mixed_length (et
, et
.size
);
12414 do_neon_mac_maybe_scalar_long (void)
12416 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
12420 do_neon_dyadic_wide (void)
12422 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
12423 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12424 neon_mixed_length (et
, et
.size
);
12428 do_neon_dyadic_narrow (void)
12430 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12431 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
12432 neon_mixed_length (et
, et
.size
/ 2);
12436 do_neon_mul_sat_scalar_long (void)
12438 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
12442 do_neon_vmull (void)
12444 if (inst
.operands
[2].isscalar
)
12445 do_neon_mac_maybe_scalar_long ();
12448 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12449 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
12450 if (et
.type
== NT_poly
)
12451 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
12453 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12454 /* For polynomial encoding, size field must be 0b00 and the U bit must be
12455 zero. Should be OK as-is. */
12456 neon_mixed_length (et
, et
.size
);
12463 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
12464 struct neon_type_el et
= neon_check_type (3, rs
,
12465 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12466 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
12467 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12468 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12469 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12470 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12471 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12472 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12473 inst
.instruction
|= neon_quad (rs
) << 6;
12474 inst
.instruction
|= imm
<< 8;
12476 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12482 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12483 struct neon_type_el et
= neon_check_type (2, rs
,
12484 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12485 unsigned op
= (inst
.instruction
>> 7) & 3;
12486 /* N (width of reversed regions) is encoded as part of the bitmask. We
12487 extract it here to check the elements to be reversed are smaller.
12488 Otherwise we'd get a reserved instruction. */
12489 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
12490 assert (elsize
!= 0);
12491 constraint (et
.size
>= elsize
,
12492 _("elements must be smaller than reversal region"));
12493 neon_two_same (neon_quad (rs
), 1, et
.size
);
12499 if (inst
.operands
[1].isscalar
)
12501 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
12502 struct neon_type_el et
= neon_check_type (2, rs
,
12503 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12504 unsigned sizebits
= et
.size
>> 3;
12505 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
12506 int logsize
= neon_logbits (et
.size
);
12507 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
12509 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
12512 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12513 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12514 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12515 inst
.instruction
|= LOW4 (dm
);
12516 inst
.instruction
|= HI1 (dm
) << 5;
12517 inst
.instruction
|= neon_quad (rs
) << 6;
12518 inst
.instruction
|= x
<< 17;
12519 inst
.instruction
|= sizebits
<< 16;
12521 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12525 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
12526 struct neon_type_el et
= neon_check_type (2, rs
,
12527 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
12528 /* Duplicate ARM register to lanes of vector. */
12529 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
12532 case 8: inst
.instruction
|= 0x400000; break;
12533 case 16: inst
.instruction
|= 0x000020; break;
12534 case 32: inst
.instruction
|= 0x000000; break;
12537 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
12538 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
12539 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
12540 inst
.instruction
|= neon_quad (rs
) << 21;
12541 /* The encoding for this instruction is identical for the ARM and Thumb
12542 variants, except for the condition field. */
12543 do_vfp_cond_or_thumb ();
12547 /* VMOV has particularly many variations. It can be one of:
12548 0. VMOV<c><q> <Qd>, <Qm>
12549 1. VMOV<c><q> <Dd>, <Dm>
12550 (Register operations, which are VORR with Rm = Rn.)
12551 2. VMOV<c><q>.<dt> <Qd>, #<imm>
12552 3. VMOV<c><q>.<dt> <Dd>, #<imm>
12554 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
12555 (ARM register to scalar.)
12556 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
12557 (Two ARM registers to vector.)
12558 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
12559 (Scalar to ARM register.)
12560 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
12561 (Vector to two ARM registers.)
12562 8. VMOV.F32 <Sd>, <Sm>
12563 9. VMOV.F64 <Dd>, <Dm>
12564 (VFP register moves.)
12565 10. VMOV.F32 <Sd>, #imm
12566 11. VMOV.F64 <Dd>, #imm
12567 (VFP float immediate load.)
12568 12. VMOV <Rd>, <Sm>
12569 (VFP single to ARM reg.)
12570 13. VMOV <Sd>, <Rm>
12571 (ARM reg to VFP single.)
12572 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
12573 (Two ARM regs to two VFP singles.)
12574 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
12575 (Two VFP singles to two ARM regs.)
12577 These cases can be disambiguated using neon_select_shape, except cases 1/9
12578 and 3/11 which depend on the operand type too.
12580 All the encoded bits are hardcoded by this function.
12582 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
12583 Cases 5, 7 may be used with VFPv2 and above.
12585 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
12586 can specify a type where it doesn't make sense to, and is ignored).
12592 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
12593 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
12595 struct neon_type_el et
;
12596 const char *ldconst
= 0;
12600 case NS_DD
: /* case 1/9. */
12601 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
12602 /* It is not an error here if no type is given. */
12604 if (et
.type
== NT_float
&& et
.size
== 64)
12606 do_vfp_nsyn_opcode ("fcpyd");
12609 /* fall through. */
12611 case NS_QQ
: /* case 0/1. */
12613 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12615 /* The architecture manual I have doesn't explicitly state which
12616 value the U bit should have for register->register moves, but
12617 the equivalent VORR instruction has U = 0, so do that. */
12618 inst
.instruction
= 0x0200110;
12619 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12620 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12621 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12622 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12623 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12624 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12625 inst
.instruction
|= neon_quad (rs
) << 6;
12627 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12631 case NS_DI
: /* case 3/11. */
12632 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
12634 if (et
.type
== NT_float
&& et
.size
== 64)
12636 /* case 11 (fconstd). */
12637 ldconst
= "fconstd";
12638 goto encode_fconstd
;
12640 /* fall through. */
12642 case NS_QI
: /* case 2/3. */
12643 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12645 inst
.instruction
= 0x0800010;
12646 neon_move_immediate ();
12647 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12650 case NS_SR
: /* case 4. */
12652 unsigned bcdebits
= 0;
12653 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
12654 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
12655 int logsize
= neon_logbits (et
.size
);
12656 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
12657 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
12659 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
12661 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
12662 && et
.size
!= 32, _(BAD_FPU
));
12663 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
12664 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
12668 case 8: bcdebits
= 0x8; break;
12669 case 16: bcdebits
= 0x1; break;
12670 case 32: bcdebits
= 0x0; break;
12674 bcdebits
|= x
<< logsize
;
12676 inst
.instruction
= 0xe000b10;
12677 do_vfp_cond_or_thumb ();
12678 inst
.instruction
|= LOW4 (dn
) << 16;
12679 inst
.instruction
|= HI1 (dn
) << 7;
12680 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12681 inst
.instruction
|= (bcdebits
& 3) << 5;
12682 inst
.instruction
|= (bcdebits
>> 2) << 21;
12686 case NS_DRR
: /* case 5 (fmdrr). */
12687 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
12690 inst
.instruction
= 0xc400b10;
12691 do_vfp_cond_or_thumb ();
12692 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
12693 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
12694 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12695 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12698 case NS_RS
: /* case 6. */
12700 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
12701 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
12702 unsigned logsize
= neon_logbits (et
.size
);
12703 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
12704 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
12705 unsigned abcdebits
= 0;
12707 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
12709 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
12710 && et
.size
!= 32, _(BAD_FPU
));
12711 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
12712 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
12716 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
12717 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
12718 case 32: abcdebits
= 0x00; break;
12722 abcdebits
|= x
<< logsize
;
12723 inst
.instruction
= 0xe100b10;
12724 do_vfp_cond_or_thumb ();
12725 inst
.instruction
|= LOW4 (dn
) << 16;
12726 inst
.instruction
|= HI1 (dn
) << 7;
12727 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12728 inst
.instruction
|= (abcdebits
& 3) << 5;
12729 inst
.instruction
|= (abcdebits
>> 2) << 21;
12733 case NS_RRD
: /* case 7 (fmrrd). */
12734 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
12737 inst
.instruction
= 0xc500b10;
12738 do_vfp_cond_or_thumb ();
12739 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12740 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12741 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12742 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12745 case NS_FF
: /* case 8 (fcpys). */
12746 do_vfp_nsyn_opcode ("fcpys");
12749 case NS_FI
: /* case 10 (fconsts). */
12750 ldconst
= "fconsts";
12752 if (is_quarter_float (inst
.operands
[1].imm
))
12754 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
12755 do_vfp_nsyn_opcode (ldconst
);
12758 first_error (_("immediate out of range"));
12761 case NS_RF
: /* case 12 (fmrs). */
12762 do_vfp_nsyn_opcode ("fmrs");
12765 case NS_FR
: /* case 13 (fmsr). */
12766 do_vfp_nsyn_opcode ("fmsr");
12769 /* The encoders for the fmrrs and fmsrr instructions expect three operands
12770 (one of which is a list), but we have parsed four. Do some fiddling to
12771 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
12773 case NS_RRFF
: /* case 14 (fmrrs). */
12774 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
12775 _("VFP registers must be adjacent"));
12776 inst
.operands
[2].imm
= 2;
12777 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
12778 do_vfp_nsyn_opcode ("fmrrs");
12781 case NS_FFRR
: /* case 15 (fmsrr). */
12782 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
12783 _("VFP registers must be adjacent"));
12784 inst
.operands
[1] = inst
.operands
[2];
12785 inst
.operands
[2] = inst
.operands
[3];
12786 inst
.operands
[0].imm
= 2;
12787 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
12788 do_vfp_nsyn_opcode ("fmsrr");
12797 do_neon_rshift_round_imm (void)
12799 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12800 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12801 int imm
= inst
.operands
[2].imm
;
12803 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
12806 inst
.operands
[2].present
= 0;
12811 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12812 _("immediate out of range for shift"));
12813 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12818 do_neon_movl (void)
12820 struct neon_type_el et
= neon_check_type (2, NS_QD
,
12821 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12822 unsigned sizebits
= et
.size
>> 3;
12823 inst
.instruction
|= sizebits
<< 19;
12824 neon_two_same (0, et
.type
== NT_unsigned
, -1);
12830 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12831 struct neon_type_el et
= neon_check_type (2, rs
,
12832 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12833 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12834 neon_two_same (neon_quad (rs
), 1, et
.size
);
12838 do_neon_zip_uzp (void)
12840 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12841 struct neon_type_el et
= neon_check_type (2, rs
,
12842 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12843 if (rs
== NS_DD
&& et
.size
== 32)
12845 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
12846 inst
.instruction
= N_MNEM_vtrn
;
12850 neon_two_same (neon_quad (rs
), 1, et
.size
);
12854 do_neon_sat_abs_neg (void)
12856 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12857 struct neon_type_el et
= neon_check_type (2, rs
,
12858 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
12859 neon_two_same (neon_quad (rs
), 1, et
.size
);
12863 do_neon_pair_long (void)
12865 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12866 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
12867 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
12868 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
12869 neon_two_same (neon_quad (rs
), 1, et
.size
);
12873 do_neon_recip_est (void)
12875 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12876 struct neon_type_el et
= neon_check_type (2, rs
,
12877 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
12878 inst
.instruction
|= (et
.type
== NT_float
) << 8;
12879 neon_two_same (neon_quad (rs
), 1, et
.size
);
12885 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12886 struct neon_type_el et
= neon_check_type (2, rs
,
12887 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
12888 neon_two_same (neon_quad (rs
), 1, et
.size
);
12894 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12895 struct neon_type_el et
= neon_check_type (2, rs
,
12896 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
12897 neon_two_same (neon_quad (rs
), 1, et
.size
);
12903 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12904 struct neon_type_el et
= neon_check_type (2, rs
,
12905 N_EQK
| N_INT
, N_8
| N_KEY
);
12906 neon_two_same (neon_quad (rs
), 1, et
.size
);
12912 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12913 neon_two_same (neon_quad (rs
), 1, -1);
12917 do_neon_tbl_tbx (void)
12919 unsigned listlenbits
;
12920 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
12922 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
12924 first_error (_("bad list length for table lookup"));
12928 listlenbits
= inst
.operands
[1].imm
- 1;
12929 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12930 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12931 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12932 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12933 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12934 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12935 inst
.instruction
|= listlenbits
<< 8;
12937 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12941 do_neon_ldm_stm (void)
12943 /* P, U and L bits are part of bitmask. */
12944 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
12945 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
12947 if (inst
.operands
[1].issingle
)
12949 do_vfp_nsyn_ldm_stm (is_dbmode
);
12953 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
12954 _("writeback (!) must be used for VLDMDB and VSTMDB"));
12956 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
12957 _("register list must contain at least 1 and at most 16 "
12960 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
12961 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
12962 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
12963 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
12965 inst
.instruction
|= offsetbits
;
12967 do_vfp_cond_or_thumb ();
12971 do_neon_ldr_str (void)
12973 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
12975 if (inst
.operands
[0].issingle
)
12978 do_vfp_nsyn_opcode ("flds");
12980 do_vfp_nsyn_opcode ("fsts");
12985 do_vfp_nsyn_opcode ("fldd");
12987 do_vfp_nsyn_opcode ("fstd");
12991 /* "interleave" version also handles non-interleaving register VLD1/VST1
12995 do_neon_ld_st_interleave (void)
12997 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
12998 N_8
| N_16
| N_32
| N_64
);
12999 unsigned alignbits
= 0;
13001 /* The bits in this table go:
13002 0: register stride of one (0) or two (1)
13003 1,2: register list length, minus one (1, 2, 3, 4).
13004 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13005 We use -1 for invalid entries. */
13006 const int typetable
[] =
13008 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
13009 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
13010 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
13011 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
13015 if (et
.type
== NT_invtype
)
13018 if (inst
.operands
[1].immisalign
)
13019 switch (inst
.operands
[1].imm
>> 8)
13021 case 64: alignbits
= 1; break;
13023 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13024 goto bad_alignment
;
13028 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13029 goto bad_alignment
;
13034 first_error (_("bad alignment"));
13038 inst
.instruction
|= alignbits
<< 4;
13039 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13041 /* Bits [4:6] of the immediate in a list specifier encode register stride
13042 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13043 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13044 up the right value for "type" in a table based on this value and the given
13045 list style, then stick it back. */
13046 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
13047 | (((inst
.instruction
>> 8) & 3) << 3);
13049 typebits
= typetable
[idx
];
13051 constraint (typebits
== -1, _("bad list type for instruction"));
13053 inst
.instruction
&= ~0xf00;
13054 inst
.instruction
|= typebits
<< 8;
13057 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13058 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13059 otherwise. The variable arguments are a list of pairs of legal (size, align)
13060 values, terminated with -1. */
13063 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
13066 int result
= FAIL
, thissize
, thisalign
;
13068 if (!inst
.operands
[1].immisalign
)
13074 va_start (ap
, do_align
);
13078 thissize
= va_arg (ap
, int);
13079 if (thissize
== -1)
13081 thisalign
= va_arg (ap
, int);
13083 if (size
== thissize
&& align
== thisalign
)
13086 while (result
!= SUCCESS
);
13090 if (result
== SUCCESS
)
13093 first_error (_("unsupported alignment for instruction"));
13099 do_neon_ld_st_lane (void)
13101 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13102 int align_good
, do_align
= 0;
13103 int logsize
= neon_logbits (et
.size
);
13104 int align
= inst
.operands
[1].imm
>> 8;
13105 int n
= (inst
.instruction
>> 8) & 3;
13106 int max_el
= 64 / et
.size
;
13108 if (et
.type
== NT_invtype
)
13111 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
13112 _("bad list length"));
13113 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
13114 _("scalar index out of range"));
13115 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
13117 _("stride of 2 unavailable when element size is 8"));
13121 case 0: /* VLD1 / VST1. */
13122 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
13124 if (align_good
== FAIL
)
13128 unsigned alignbits
= 0;
13131 case 16: alignbits
= 0x1; break;
13132 case 32: alignbits
= 0x3; break;
13135 inst
.instruction
|= alignbits
<< 4;
13139 case 1: /* VLD2 / VST2. */
13140 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
13142 if (align_good
== FAIL
)
13145 inst
.instruction
|= 1 << 4;
13148 case 2: /* VLD3 / VST3. */
13149 constraint (inst
.operands
[1].immisalign
,
13150 _("can't use alignment with this instruction"));
13153 case 3: /* VLD4 / VST4. */
13154 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13155 16, 64, 32, 64, 32, 128, -1);
13156 if (align_good
== FAIL
)
13160 unsigned alignbits
= 0;
13163 case 8: alignbits
= 0x1; break;
13164 case 16: alignbits
= 0x1; break;
13165 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
13168 inst
.instruction
|= alignbits
<< 4;
13175 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13176 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13177 inst
.instruction
|= 1 << (4 + logsize
);
13179 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
13180 inst
.instruction
|= logsize
<< 10;
13183 /* Encode single n-element structure to all lanes VLD<n> instructions. */
13186 do_neon_ld_dup (void)
13188 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13189 int align_good
, do_align
= 0;
13191 if (et
.type
== NT_invtype
)
13194 switch ((inst
.instruction
>> 8) & 3)
13196 case 0: /* VLD1. */
13197 assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
13198 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13199 &do_align
, 16, 16, 32, 32, -1);
13200 if (align_good
== FAIL
)
13202 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
13205 case 2: inst
.instruction
|= 1 << 5; break;
13206 default: first_error (_("bad list length")); return;
13208 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13211 case 1: /* VLD2. */
13212 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13213 &do_align
, 8, 16, 16, 32, 32, 64, -1);
13214 if (align_good
== FAIL
)
13216 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
13217 _("bad list length"));
13218 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13219 inst
.instruction
|= 1 << 5;
13220 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13223 case 2: /* VLD3. */
13224 constraint (inst
.operands
[1].immisalign
,
13225 _("can't use alignment with this instruction"));
13226 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
13227 _("bad list length"));
13228 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13229 inst
.instruction
|= 1 << 5;
13230 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13233 case 3: /* VLD4. */
13235 int align
= inst
.operands
[1].imm
>> 8;
13236 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13237 16, 64, 32, 64, 32, 128, -1);
13238 if (align_good
== FAIL
)
13240 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
13241 _("bad list length"));
13242 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13243 inst
.instruction
|= 1 << 5;
13244 if (et
.size
== 32 && align
== 128)
13245 inst
.instruction
|= 0x3 << 6;
13247 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13254 inst
.instruction
|= do_align
<< 4;
13257 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13258 apart from bits [11:4]. */
13261 do_neon_ldx_stx (void)
13263 switch (NEON_LANE (inst
.operands
[0].imm
))
13265 case NEON_INTERLEAVE_LANES
:
13266 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
13267 do_neon_ld_st_interleave ();
13270 case NEON_ALL_LANES
:
13271 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
13276 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
13277 do_neon_ld_st_lane ();
13280 /* L bit comes from bit mask. */
13281 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13282 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13283 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13285 if (inst
.operands
[1].postind
)
13287 int postreg
= inst
.operands
[1].imm
& 0xf;
13288 constraint (!inst
.operands
[1].immisreg
,
13289 _("post-index must be a register"));
13290 constraint (postreg
== 0xd || postreg
== 0xf,
13291 _("bad register for post-index"));
13292 inst
.instruction
|= postreg
;
13294 else if (inst
.operands
[1].writeback
)
13296 inst
.instruction
|= 0xd;
13299 inst
.instruction
|= 0xf;
13302 inst
.instruction
|= 0xf9000000;
13304 inst
.instruction
|= 0xf4000000;
13308 /* Overall per-instruction processing. */
13310 /* We need to be able to fix up arbitrary expressions in some statements.
13311 This is so that we can handle symbols that are an arbitrary distance from
13312 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13313 which returns part of an address in a form which will be valid for
13314 a data instruction. We do this by pushing the expression into a symbol
13315 in the expr_section, and creating a fix for that. */
13318 fix_new_arm (fragS
* frag
,
13333 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
13337 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
13342 /* Mark whether the fix is to a THUMB instruction, or an ARM
13344 new_fix
->tc_fix_data
= thumb_mode
;
13347 /* Create a frg for an instruction requiring relaxation. */
13349 output_relax_insn (void)
13356 /* The size of the instruction is unknown, so tie the debug info to the
13357 start of the instruction. */
13358 dwarf2_emit_insn (0);
13361 switch (inst
.reloc
.exp
.X_op
)
13364 sym
= inst
.reloc
.exp
.X_add_symbol
;
13365 offset
= inst
.reloc
.exp
.X_add_number
;
13369 offset
= inst
.reloc
.exp
.X_add_number
;
13372 sym
= make_expr_symbol (&inst
.reloc
.exp
);
13376 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
13377 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
13378 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
13381 /* Write a 32-bit thumb instruction to buf. */
13383 put_thumb32_insn (char * buf
, unsigned long insn
)
13385 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
13386 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
13390 output_inst (const char * str
)
13396 as_bad ("%s -- `%s'", inst
.error
, str
);
13400 output_relax_insn();
13403 if (inst
.size
== 0)
13406 to
= frag_more (inst
.size
);
13408 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
13410 assert (inst
.size
== (2 * THUMB_SIZE
));
13411 put_thumb32_insn (to
, inst
.instruction
);
13413 else if (inst
.size
> INSN_SIZE
)
13415 assert (inst
.size
== (2 * INSN_SIZE
));
13416 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
13417 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
13420 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
13422 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
13423 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
13424 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
13428 dwarf2_emit_insn (inst
.size
);
13432 /* Tag values used in struct asm_opcode's tag field. */
13435 OT_unconditional
, /* Instruction cannot be conditionalized.
13436 The ARM condition field is still 0xE. */
13437 OT_unconditionalF
, /* Instruction cannot be conditionalized
13438 and carries 0xF in its ARM condition field. */
13439 OT_csuffix
, /* Instruction takes a conditional suffix. */
13440 OT_csuffixF
, /* Some forms of the instruction take a conditional
13441 suffix, others place 0xF where the condition field
13443 OT_cinfix3
, /* Instruction takes a conditional infix,
13444 beginning at character index 3. (In
13445 unified mode, it becomes a suffix.) */
13446 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
13447 tsts, cmps, cmns, and teqs. */
13448 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
13449 character index 3, even in unified mode. Used for
13450 legacy instructions where suffix and infix forms
13451 may be ambiguous. */
13452 OT_csuf_or_in3
, /* Instruction takes either a conditional
13453 suffix or an infix at character index 3. */
13454 OT_odd_infix_unc
, /* This is the unconditional variant of an
13455 instruction that takes a conditional infix
13456 at an unusual position. In unified mode,
13457 this variant will accept a suffix. */
13458 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
13459 are the conditional variants of instructions that
13460 take conditional infixes in unusual positions.
13461 The infix appears at character index
13462 (tag - OT_odd_infix_0). These are not accepted
13463 in unified mode. */
13466 /* Subroutine of md_assemble, responsible for looking up the primary
13467 opcode from the mnemonic the user wrote. STR points to the
13468 beginning of the mnemonic.
13470 This is not simply a hash table lookup, because of conditional
13471 variants. Most instructions have conditional variants, which are
13472 expressed with a _conditional affix_ to the mnemonic. If we were
13473 to encode each conditional variant as a literal string in the opcode
13474 table, it would have approximately 20,000 entries.
13476 Most mnemonics take this affix as a suffix, and in unified syntax,
13477 'most' is upgraded to 'all'. However, in the divided syntax, some
13478 instructions take the affix as an infix, notably the s-variants of
13479 the arithmetic instructions. Of those instructions, all but six
13480 have the infix appear after the third character of the mnemonic.
13482 Accordingly, the algorithm for looking up primary opcodes given
13485 1. Look up the identifier in the opcode table.
13486 If we find a match, go to step U.
13488 2. Look up the last two characters of the identifier in the
13489 conditions table. If we find a match, look up the first N-2
13490 characters of the identifier in the opcode table. If we
13491 find a match, go to step CE.
13493 3. Look up the fourth and fifth characters of the identifier in
13494 the conditions table. If we find a match, extract those
13495 characters from the identifier, and look up the remaining
13496 characters in the opcode table. If we find a match, go
13501 U. Examine the tag field of the opcode structure, in case this is
13502 one of the six instructions with its conditional infix in an
13503 unusual place. If it is, the tag tells us where to find the
13504 infix; look it up in the conditions table and set inst.cond
13505 accordingly. Otherwise, this is an unconditional instruction.
13506 Again set inst.cond accordingly. Return the opcode structure.
13508 CE. Examine the tag field to make sure this is an instruction that
13509 should receive a conditional suffix. If it is not, fail.
13510 Otherwise, set inst.cond from the suffix we already looked up,
13511 and return the opcode structure.
13513 CM. Examine the tag field to make sure this is an instruction that
13514 should receive a conditional infix after the third character.
13515 If it is not, fail. Otherwise, undo the edits to the current
13516 line of input and proceed as for case CE. */
13518 static const struct asm_opcode
*
13519 opcode_lookup (char **str
)
13523 const struct asm_opcode
*opcode
;
13524 const struct asm_cond
*cond
;
13527 /* Scan up to the end of the mnemonic, which must end in white space,
13528 '.' (in unified mode only), or end of string. */
13529 for (base
= end
= *str
; *end
!= '\0'; end
++)
13530 if (*end
== ' ' || (unified_syntax
&& *end
== '.'))
13536 /* Handle a possible width suffix and/or Neon type suffix. */
13543 else if (end
[1] == 'n')
13548 inst
.vectype
.elems
= 0;
13550 *str
= end
+ offset
;
13552 if (end
[offset
] == '.')
13554 /* See if we have a Neon type suffix. */
13555 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
13558 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
13564 /* Look for unaffixed or special-case affixed mnemonic. */
13565 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
13569 if (opcode
->tag
< OT_odd_infix_0
)
13571 inst
.cond
= COND_ALWAYS
;
13575 if (unified_syntax
)
13576 as_warn (_("conditional infixes are deprecated in unified syntax"));
13577 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
13578 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13581 inst
.cond
= cond
->value
;
13585 /* Cannot have a conditional suffix on a mnemonic of less than two
13587 if (end
- base
< 3)
13590 /* Look for suffixed mnemonic. */
13592 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13593 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
13594 if (opcode
&& cond
)
13597 switch (opcode
->tag
)
13599 case OT_cinfix3_legacy
:
13600 /* Ignore conditional suffixes matched on infix only mnemonics. */
13604 case OT_cinfix3_deprecated
:
13605 case OT_odd_infix_unc
:
13606 if (!unified_syntax
)
13608 /* else fall through */
13612 case OT_csuf_or_in3
:
13613 inst
.cond
= cond
->value
;
13616 case OT_unconditional
:
13617 case OT_unconditionalF
:
13620 inst
.cond
= cond
->value
;
13624 /* delayed diagnostic */
13625 inst
.error
= BAD_COND
;
13626 inst
.cond
= COND_ALWAYS
;
13635 /* Cannot have a usual-position infix on a mnemonic of less than
13636 six characters (five would be a suffix). */
13637 if (end
- base
< 6)
13640 /* Look for infixed mnemonic in the usual position. */
13642 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13646 memcpy (save
, affix
, 2);
13647 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
13648 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
13649 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
13650 memcpy (affix
, save
, 2);
13653 && (opcode
->tag
== OT_cinfix3
13654 || opcode
->tag
== OT_cinfix3_deprecated
13655 || opcode
->tag
== OT_csuf_or_in3
13656 || opcode
->tag
== OT_cinfix3_legacy
))
13660 && (opcode
->tag
== OT_cinfix3
13661 || opcode
->tag
== OT_cinfix3_deprecated
))
13662 as_warn (_("conditional infixes are deprecated in unified syntax"));
13664 inst
.cond
= cond
->value
;
13672 md_assemble (char *str
)
13675 const struct asm_opcode
* opcode
;
13677 /* Align the previous label if needed. */
13678 if (last_label_seen
!= NULL
)
13680 symbol_set_frag (last_label_seen
, frag_now
);
13681 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
13682 S_SET_SEGMENT (last_label_seen
, now_seg
);
13685 memset (&inst
, '\0', sizeof (inst
));
13686 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13688 opcode
= opcode_lookup (&p
);
13691 /* It wasn't an instruction, but it might be a register alias of
13692 the form alias .req reg, or a Neon .dn/.qn directive. */
13693 if (!create_register_alias (str
, p
)
13694 && !create_neon_reg_alias (str
, p
))
13695 as_bad (_("bad instruction `%s'"), str
);
13700 if (opcode
->tag
== OT_cinfix3_deprecated
)
13701 as_warn (_("s suffix on comparison instruction is deprecated"));
13703 /* The value which unconditional instructions should have in place of the
13704 condition field. */
13705 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
13709 arm_feature_set variant
;
13711 variant
= cpu_variant
;
13712 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
13713 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
13714 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
13715 /* Check that this instruction is supported for this CPU. */
13716 if (!opcode
->tvariant
13717 || (thumb_mode
== 1
13718 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
13720 as_bad (_("selected processor does not support `%s'"), str
);
13723 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
13724 && opcode
->tencode
!= do_t_branch
)
13726 as_bad (_("Thumb does not support conditional execution"));
13730 /* Check conditional suffixes. */
13731 if (current_it_mask
)
13734 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
13735 current_it_mask
<<= 1;
13736 current_it_mask
&= 0x1f;
13737 /* The BKPT instruction is unconditional even in an IT block. */
13739 && cond
!= inst
.cond
&& opcode
->tencode
!= do_t_bkpt
)
13741 as_bad (_("incorrect condition in IT block"));
13745 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
13747 as_bad (_("thumb conditional instrunction not in IT block"));
13751 mapping_state (MAP_THUMB
);
13752 inst
.instruction
= opcode
->tvalue
;
13754 if (!parse_operands (p
, opcode
->operands
))
13755 opcode
->tencode ();
13757 /* Clear current_it_mask at the end of an IT block. */
13758 if (current_it_mask
== 0x10)
13759 current_it_mask
= 0;
13761 if (!(inst
.error
|| inst
.relax
))
13763 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
13764 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
13765 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
13767 as_bad (_("cannot honor width suffix -- `%s'"), str
);
13771 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13772 *opcode
->tvariant
);
13773 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
13774 set those bits when Thumb-2 32-bit instructions are seen. ie.
13775 anything other than bl/blx.
13776 This is overly pessimistic for relaxable instructions. */
13777 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
13779 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13784 /* Check that this instruction is supported for this CPU. */
13785 if (!opcode
->avariant
||
13786 !ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
13788 as_bad (_("selected processor does not support `%s'"), str
);
13793 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
13797 mapping_state (MAP_ARM
);
13798 inst
.instruction
= opcode
->avalue
;
13799 if (opcode
->tag
== OT_unconditionalF
)
13800 inst
.instruction
|= 0xF << 28;
13802 inst
.instruction
|= inst
.cond
<< 28;
13803 inst
.size
= INSN_SIZE
;
13804 if (!parse_operands (p
, opcode
->operands
))
13805 opcode
->aencode ();
13806 /* Arm mode bx is marked as both v4T and v5 because it's still required
13807 on a hypothetical non-thumb v5 core. */
13808 if (ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v4t
)
13809 || ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v5
))
13810 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
13812 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
13813 *opcode
->avariant
);
13818 /* Various frobbings of labels and their addresses. */
13821 arm_start_line_hook (void)
13823 last_label_seen
= NULL
;
13827 arm_frob_label (symbolS
* sym
)
13829 last_label_seen
= sym
;
13831 ARM_SET_THUMB (sym
, thumb_mode
);
13833 #if defined OBJ_COFF || defined OBJ_ELF
13834 ARM_SET_INTERWORK (sym
, support_interwork
);
13837 /* Note - do not allow local symbols (.Lxxx) to be labeled
13838 as Thumb functions. This is because these labels, whilst
13839 they exist inside Thumb code, are not the entry points for
13840 possible ARM->Thumb calls. Also, these labels can be used
13841 as part of a computed goto or switch statement. eg gcc
13842 can generate code that looks like this:
13844 ldr r2, [pc, .Laaa]
13854 The first instruction loads the address of the jump table.
13855 The second instruction converts a table index into a byte offset.
13856 The third instruction gets the jump address out of the table.
13857 The fourth instruction performs the jump.
13859 If the address stored at .Laaa is that of a symbol which has the
13860 Thumb_Func bit set, then the linker will arrange for this address
13861 to have the bottom bit set, which in turn would mean that the
13862 address computation performed by the third instruction would end
13863 up with the bottom bit set. Since the ARM is capable of unaligned
13864 word loads, the instruction would then load the incorrect address
13865 out of the jump table, and chaos would ensue. */
13866 if (label_is_thumb_function_name
13867 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
13868 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
13870 /* When the address of a Thumb function is taken the bottom
13871 bit of that address should be set. This will allow
13872 interworking between Arm and Thumb functions to work
13875 THUMB_SET_FUNC (sym
, 1);
13877 label_is_thumb_function_name
= FALSE
;
13881 dwarf2_emit_label (sym
);
13886 arm_data_in_code (void)
13888 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
13890 *input_line_pointer
= '/';
13891 input_line_pointer
+= 5;
13892 *input_line_pointer
= 0;
13900 arm_canonicalize_symbol_name (char * name
)
13904 if (thumb_mode
&& (len
= strlen (name
)) > 5
13905 && streq (name
+ len
- 5, "/data"))
13906 *(name
+ len
- 5) = 0;
13911 /* Table of all register names defined by default. The user can
13912 define additional names with .req. Note that all register names
13913 should appear in both upper and lowercase variants. Some registers
13914 also have mixed-case names. */
13916 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
13917 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
13918 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
13919 #define REGSET(p,t) \
13920 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
13921 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
13922 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
13923 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
13924 #define REGSETH(p,t) \
13925 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
13926 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
13927 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
13928 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
13929 #define REGSET2(p,t) \
13930 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
13931 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
13932 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
13933 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
13935 static const struct reg_entry reg_names
[] =
13937 /* ARM integer registers. */
13938 REGSET(r
, RN
), REGSET(R
, RN
),
13940 /* ATPCS synonyms. */
13941 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
13942 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
13943 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
13945 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
13946 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
13947 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
13949 /* Well-known aliases. */
13950 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
13951 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
13953 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
13954 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
13956 /* Coprocessor numbers. */
13957 REGSET(p
, CP
), REGSET(P
, CP
),
13959 /* Coprocessor register numbers. The "cr" variants are for backward
13961 REGSET(c
, CN
), REGSET(C
, CN
),
13962 REGSET(cr
, CN
), REGSET(CR
, CN
),
13964 /* FPA registers. */
13965 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
13966 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
13968 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
13969 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
13971 /* VFP SP registers. */
13972 REGSET(s
,VFS
), REGSET(S
,VFS
),
13973 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
13975 /* VFP DP Registers. */
13976 REGSET(d
,VFD
), REGSET(D
,VFD
),
13977 /* Extra Neon DP registers. */
13978 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
13980 /* Neon QP registers. */
13981 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
13983 /* VFP control registers. */
13984 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
13985 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
13987 /* Maverick DSP coprocessor registers. */
13988 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
13989 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
13991 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
13992 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
13993 REGDEF(dspsc
,0,DSPSC
),
13995 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
13996 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
13997 REGDEF(DSPSC
,0,DSPSC
),
13999 /* iWMMXt data registers - p0, c0-15. */
14000 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
14002 /* iWMMXt control registers - p1, c0-3. */
14003 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
14004 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
14005 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
14006 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
14008 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
14009 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
14010 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
14011 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
14012 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
14014 /* XScale accumulator registers. */
14015 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
14021 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
14022 within psr_required_here. */
14023 static const struct asm_psr psrs
[] =
14025 /* Backward compatibility notation. Note that "all" is no longer
14026 truly all possible PSR bits. */
14027 {"all", PSR_c
| PSR_f
},
14031 /* Individual flags. */
14036 /* Combinations of flags. */
14037 {"fs", PSR_f
| PSR_s
},
14038 {"fx", PSR_f
| PSR_x
},
14039 {"fc", PSR_f
| PSR_c
},
14040 {"sf", PSR_s
| PSR_f
},
14041 {"sx", PSR_s
| PSR_x
},
14042 {"sc", PSR_s
| PSR_c
},
14043 {"xf", PSR_x
| PSR_f
},
14044 {"xs", PSR_x
| PSR_s
},
14045 {"xc", PSR_x
| PSR_c
},
14046 {"cf", PSR_c
| PSR_f
},
14047 {"cs", PSR_c
| PSR_s
},
14048 {"cx", PSR_c
| PSR_x
},
14049 {"fsx", PSR_f
| PSR_s
| PSR_x
},
14050 {"fsc", PSR_f
| PSR_s
| PSR_c
},
14051 {"fxs", PSR_f
| PSR_x
| PSR_s
},
14052 {"fxc", PSR_f
| PSR_x
| PSR_c
},
14053 {"fcs", PSR_f
| PSR_c
| PSR_s
},
14054 {"fcx", PSR_f
| PSR_c
| PSR_x
},
14055 {"sfx", PSR_s
| PSR_f
| PSR_x
},
14056 {"sfc", PSR_s
| PSR_f
| PSR_c
},
14057 {"sxf", PSR_s
| PSR_x
| PSR_f
},
14058 {"sxc", PSR_s
| PSR_x
| PSR_c
},
14059 {"scf", PSR_s
| PSR_c
| PSR_f
},
14060 {"scx", PSR_s
| PSR_c
| PSR_x
},
14061 {"xfs", PSR_x
| PSR_f
| PSR_s
},
14062 {"xfc", PSR_x
| PSR_f
| PSR_c
},
14063 {"xsf", PSR_x
| PSR_s
| PSR_f
},
14064 {"xsc", PSR_x
| PSR_s
| PSR_c
},
14065 {"xcf", PSR_x
| PSR_c
| PSR_f
},
14066 {"xcs", PSR_x
| PSR_c
| PSR_s
},
14067 {"cfs", PSR_c
| PSR_f
| PSR_s
},
14068 {"cfx", PSR_c
| PSR_f
| PSR_x
},
14069 {"csf", PSR_c
| PSR_s
| PSR_f
},
14070 {"csx", PSR_c
| PSR_s
| PSR_x
},
14071 {"cxf", PSR_c
| PSR_x
| PSR_f
},
14072 {"cxs", PSR_c
| PSR_x
| PSR_s
},
14073 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
14074 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
14075 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
14076 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
14077 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
14078 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
14079 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
14080 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
14081 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
14082 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
14083 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
14084 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
14085 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
14086 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
14087 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
14088 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
14089 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
14090 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
14091 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
14092 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
14093 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
14094 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
14095 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
14096 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
14099 /* Table of V7M psr names. */
14100 static const struct asm_psr v7m_psrs
[] =
14113 {"basepri_max", 18},
14118 /* Table of all shift-in-operand names. */
14119 static const struct asm_shift_name shift_names
[] =
14121 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
14122 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
14123 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
14124 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
14125 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
14126 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
14129 /* Table of all explicit relocation names. */
14131 static struct reloc_entry reloc_names
[] =
14133 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
14134 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
14135 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
14136 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
14137 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
14138 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
14139 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
14140 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
14141 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
14142 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
14143 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
14147 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
14148 static const struct asm_cond conds
[] =
14152 {"cs", 0x2}, {"hs", 0x2},
14153 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14167 static struct asm_barrier_opt barrier_opt_names
[] =
14175 /* Table of ARM-format instructions. */
14177 /* Macros for gluing together operand strings. N.B. In all cases
14178 other than OPS0, the trailing OP_stop comes from default
14179 zero-initialization of the unspecified elements of the array. */
14180 #define OPS0() { OP_stop, }
14181 #define OPS1(a) { OP_##a, }
14182 #define OPS2(a,b) { OP_##a,OP_##b, }
14183 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14184 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14185 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14186 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14188 /* These macros abstract out the exact format of the mnemonic table and
14189 save some repeated characters. */
14191 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14192 #define TxCE(mnem, op, top, nops, ops, ae, te) \
14193 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14194 THUMB_VARIANT, do_##ae, do_##te }
14196 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14197 a T_MNEM_xyz enumerator. */
14198 #define TCE(mnem, aop, top, nops, ops, ae, te) \
14199 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14200 #define tCE(mnem, aop, top, nops, ops, ae, te) \
14201 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14203 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14204 infix after the third character. */
14205 #define TxC3(mnem, op, top, nops, ops, ae, te) \
14206 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14207 THUMB_VARIANT, do_##ae, do_##te }
14208 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
14209 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14210 THUMB_VARIANT, do_##ae, do_##te }
14211 #define TC3(mnem, aop, top, nops, ops, ae, te) \
14212 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14213 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
14214 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14215 #define tC3(mnem, aop, top, nops, ops, ae, te) \
14216 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14217 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
14218 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14220 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14221 appear in the condition table. */
14222 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14223 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14224 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14226 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14227 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14228 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14229 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14230 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14231 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14232 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14233 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14234 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14235 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14236 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14237 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14238 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14239 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14240 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14241 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14242 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14243 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14244 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14245 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14247 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14248 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14249 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14250 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14252 /* Mnemonic that cannot be conditionalized. The ARM condition-code
14253 field is still 0xE. Many of the Thumb variants can be executed
14254 conditionally, so this is checked separately. */
14255 #define TUE(mnem, op, top, nops, ops, ae, te) \
14256 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14257 THUMB_VARIANT, do_##ae, do_##te }
14259 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14260 condition code field. */
14261 #define TUF(mnem, op, top, nops, ops, ae, te) \
14262 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14263 THUMB_VARIANT, do_##ae, do_##te }
14265 /* ARM-only variants of all the above. */
14266 #define CE(mnem, op, nops, ops, ae) \
14267 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14269 #define C3(mnem, op, nops, ops, ae) \
14270 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14272 /* Legacy mnemonics that always have conditional infix after the third
14274 #define CL(mnem, op, nops, ops, ae) \
14275 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14276 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14278 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14279 #define cCE(mnem, op, nops, ops, ae) \
14280 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14282 /* Legacy coprocessor instructions where conditional infix and conditional
14283 suffix are ambiguous. For consistency this includes all FPA instructions,
14284 not just the potentially ambiguous ones. */
14285 #define cCL(mnem, op, nops, ops, ae) \
14286 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14287 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14289 /* Coprocessor, takes either a suffix or a position-3 infix
14290 (for an FPA corner case). */
14291 #define C3E(mnem, op, nops, ops, ae) \
14292 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14293 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14295 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
14296 { #m1 #m2 #m3, OPS##nops ops, \
14297 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14298 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14300 #define CM(m1, m2, op, nops, ops, ae) \
14301 xCM_(m1, , m2, op, nops, ops, ae), \
14302 xCM_(m1, eq, m2, op, nops, ops, ae), \
14303 xCM_(m1, ne, m2, op, nops, ops, ae), \
14304 xCM_(m1, cs, m2, op, nops, ops, ae), \
14305 xCM_(m1, hs, m2, op, nops, ops, ae), \
14306 xCM_(m1, cc, m2, op, nops, ops, ae), \
14307 xCM_(m1, ul, m2, op, nops, ops, ae), \
14308 xCM_(m1, lo, m2, op, nops, ops, ae), \
14309 xCM_(m1, mi, m2, op, nops, ops, ae), \
14310 xCM_(m1, pl, m2, op, nops, ops, ae), \
14311 xCM_(m1, vs, m2, op, nops, ops, ae), \
14312 xCM_(m1, vc, m2, op, nops, ops, ae), \
14313 xCM_(m1, hi, m2, op, nops, ops, ae), \
14314 xCM_(m1, ls, m2, op, nops, ops, ae), \
14315 xCM_(m1, ge, m2, op, nops, ops, ae), \
14316 xCM_(m1, lt, m2, op, nops, ops, ae), \
14317 xCM_(m1, gt, m2, op, nops, ops, ae), \
14318 xCM_(m1, le, m2, op, nops, ops, ae), \
14319 xCM_(m1, al, m2, op, nops, ops, ae)
14321 #define UE(mnem, op, nops, ops, ae) \
14322 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14324 #define UF(mnem, op, nops, ops, ae) \
14325 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14327 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
14328 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14329 use the same encoding function for each. */
14330 #define NUF(mnem, op, nops, ops, enc) \
14331 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
14332 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14334 /* Neon data processing, version which indirects through neon_enc_tab for
14335 the various overloaded versions of opcodes. */
14336 #define nUF(mnem, op, nops, ops, enc) \
14337 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
14338 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14340 /* Neon insn with conditional suffix for the ARM version, non-overloaded
14342 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
14343 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
14344 THUMB_VARIANT, do_##enc, do_##enc }
14346 #define NCE(mnem, op, nops, ops, enc) \
14347 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14349 #define NCEF(mnem, op, nops, ops, enc) \
14350 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14352 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
14353 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
14354 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
14355 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14357 #define nCE(mnem, op, nops, ops, enc) \
14358 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14360 #define nCEF(mnem, op, nops, ops, enc) \
14361 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14365 /* Thumb-only, unconditional. */
14366 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
14368 static const struct asm_opcode insns
[] =
14370 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
14371 #define THUMB_VARIANT &arm_ext_v4t
14372 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14373 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14374 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14375 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14376 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14377 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14378 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14379 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14380 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14381 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14382 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14383 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14384 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14385 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14386 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14387 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14389 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
14390 for setting PSR flag bits. They are obsolete in V6 and do not
14391 have Thumb equivalents. */
14392 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14393 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14394 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
14395 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14396 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14397 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
14398 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14399 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14400 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
14402 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14403 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14404 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14405 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14407 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14408 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14409 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14410 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14412 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14413 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14414 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14415 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14416 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14417 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14419 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14420 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14421 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
14422 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
14425 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
14426 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
14427 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
14429 /* Thumb-compatibility pseudo ops. */
14430 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14431 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14432 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14433 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14434 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14435 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14436 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14437 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14438 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
14439 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
14440 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
14441 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
14443 #undef THUMB_VARIANT
14444 #define THUMB_VARIANT &arm_ext_v6
14445 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
14447 /* V1 instructions with no Thumb analogue prior to V6T2. */
14448 #undef THUMB_VARIANT
14449 #define THUMB_VARIANT &arm_ext_v6t2
14450 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14451 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14452 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14453 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14454 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
14456 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14457 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14458 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14459 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14461 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14462 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14464 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14465 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14467 /* V1 instructions with no Thumb analogue at all. */
14468 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
14469 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
14471 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14472 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14473 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14474 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14475 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14476 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14477 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14478 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14481 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
14482 #undef THUMB_VARIANT
14483 #define THUMB_VARIANT &arm_ext_v4t
14484 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
14485 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
14487 #undef THUMB_VARIANT
14488 #define THUMB_VARIANT &arm_ext_v6t2
14489 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
14490 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
14492 /* Generic coprocessor instructions. */
14493 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
14494 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14495 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14496 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14497 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14498 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14499 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14502 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
14503 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
14504 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
14507 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
14508 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
14509 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
14512 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
14513 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14514 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14515 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14516 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14517 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14518 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14519 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14520 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14523 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
14524 #undef THUMB_VARIANT
14525 #define THUMB_VARIANT &arm_ext_v4t
14526 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14527 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14528 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14529 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14530 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14531 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14534 #define ARM_VARIANT &arm_ext_v4t_5
14535 /* ARM Architecture 4T. */
14536 /* Note: bx (and blx) are required on V5, even if the processor does
14537 not support Thumb. */
14538 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
14541 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
14542 #undef THUMB_VARIANT
14543 #define THUMB_VARIANT &arm_ext_v5t
14544 /* Note: blx has 2 variants; the .value coded here is for
14545 BLX(2). Only this variant has conditional execution. */
14546 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
14547 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
14549 #undef THUMB_VARIANT
14550 #define THUMB_VARIANT &arm_ext_v6t2
14551 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
14552 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14553 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14554 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14555 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14556 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
14557 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14558 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14561 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
14562 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14563 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14564 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14565 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14567 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14568 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14570 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14571 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14572 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14573 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14575 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14576 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14577 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14578 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14580 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14581 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14583 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14584 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14585 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14586 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14589 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
14590 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
14591 TC3(ldrd
, 00000d0
, e9500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
14592 TC3(strd
, 00000f0
, e9400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
14594 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14595 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14598 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
14599 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
14602 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
14603 #undef THUMB_VARIANT
14604 #define THUMB_VARIANT &arm_ext_v6
14605 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
14606 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
14607 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14608 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14609 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14610 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14611 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14612 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14613 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14614 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
14616 #undef THUMB_VARIANT
14617 #define THUMB_VARIANT &arm_ext_v6t2
14618 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
14619 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14620 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14622 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
14623 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
14625 /* ARM V6 not included in V7M (eg. integer SIMD). */
14626 #undef THUMB_VARIANT
14627 #define THUMB_VARIANT &arm_ext_v6_notm
14628 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
14629 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
14630 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
14631 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14632 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14633 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14634 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14635 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14636 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14637 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14638 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14639 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14640 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14641 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14642 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14643 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14644 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14645 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14646 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14647 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14648 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14649 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14650 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14651 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14652 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14653 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14654 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14655 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14656 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14657 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14658 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14659 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14660 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14661 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14662 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14663 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14664 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14665 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14666 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14667 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
14668 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
14669 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
14670 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
14671 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
14672 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
14673 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
14674 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
14675 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14676 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14677 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14678 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14679 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14680 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14681 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14682 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14683 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14684 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14685 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14686 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14687 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14688 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14689 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14690 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14691 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14692 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14693 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14694 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14695 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14696 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14697 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14698 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14699 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14700 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14701 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14702 TUF(srsia
, 8cd0500
, e980c000
, 1, (I31w
), srs
, srs
),
14703 UF(srsib
, 9cd0500
, 1, (I31w
), srs
),
14704 UF(srsda
, 84d0500
, 1, (I31w
), srs
),
14705 TUF(srsdb
, 94d0500
, e800c000
, 1, (I31w
), srs
, srs
),
14706 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
14707 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
14708 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
14709 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14710 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14711 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
14714 #define ARM_VARIANT &arm_ext_v6k
14715 #undef THUMB_VARIANT
14716 #define THUMB_VARIANT &arm_ext_v6k
14717 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
14718 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
14719 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
14720 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
14722 #undef THUMB_VARIANT
14723 #define THUMB_VARIANT &arm_ext_v6_notm
14724 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
14725 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
14727 #undef THUMB_VARIANT
14728 #define THUMB_VARIANT &arm_ext_v6t2
14729 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
14730 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
14731 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
14732 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
14733 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
14736 #define ARM_VARIANT &arm_ext_v6z
14737 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
14740 #define ARM_VARIANT &arm_ext_v6t2
14741 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
14742 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
14743 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
14744 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
14746 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
14747 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
14748 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
14749 TCE(rbit
, 3ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
14751 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14752 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14753 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14754 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14756 UT(cbnz
, b900
, 2, (RR
, EXP
), t_czb
),
14757 UT(cbz
, b100
, 2, (RR
, EXP
), t_czb
),
14758 /* ARM does not really have an IT instruction. */
14759 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
14760 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
14761 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
14762 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
14763 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
14764 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
14765 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
14766 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
14767 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
14768 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
14769 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
14770 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
14771 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
14772 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
14773 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
14775 /* Thumb2 only instructions. */
14777 #define ARM_VARIANT NULL
14779 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
14780 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
14781 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
14782 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
14784 /* Thumb-2 hardware division instructions (R and M profiles only). */
14785 #undef THUMB_VARIANT
14786 #define THUMB_VARIANT &arm_ext_div
14787 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
14788 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
14790 /* ARM V7 instructions. */
14792 #define ARM_VARIANT &arm_ext_v7
14793 #undef THUMB_VARIANT
14794 #define THUMB_VARIANT &arm_ext_v7
14795 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
14796 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
14797 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
14798 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
14799 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
14802 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
14803 cCE(wfs
, e200110
, 1, (RR
), rd
),
14804 cCE(rfs
, e300110
, 1, (RR
), rd
),
14805 cCE(wfc
, e400110
, 1, (RR
), rd
),
14806 cCE(rfc
, e500110
, 1, (RR
), rd
),
14808 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14809 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14810 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14811 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14813 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14814 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14815 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14816 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14818 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
14819 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
14820 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
14821 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
14822 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
14823 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
14824 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
14825 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
14826 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
14827 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
14828 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
14829 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
14831 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
14832 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
14833 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
14834 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
14835 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
14836 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
14837 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
14838 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
14839 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
14840 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
14841 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
14842 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
14844 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
14845 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
14846 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
14847 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
14848 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
14849 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
14850 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
14851 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
14852 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
14853 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
14854 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
14855 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
14857 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
14858 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
14859 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
14860 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
14861 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
14862 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
14863 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
14864 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
14865 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
14866 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
14867 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
14868 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
14870 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
14871 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
14872 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
14873 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
14874 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
14875 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
14876 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
14877 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
14878 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
14879 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
14880 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
14881 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
14883 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
14884 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
14885 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
14886 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
14887 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
14888 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
14889 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
14890 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
14891 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
14892 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
14893 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
14894 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
14896 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
14897 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
14898 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
14899 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
14900 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
14901 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
14902 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
14903 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
14904 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
14905 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
14906 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
14907 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
14909 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
14910 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
14911 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
14912 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
14913 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
14914 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
14915 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
14916 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
14917 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
14918 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
14919 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
14920 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
14922 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
14923 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
14924 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
14925 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
14926 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
14927 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
14928 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
14929 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
14930 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
14931 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
14932 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
14933 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
14935 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
14936 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
14937 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
14938 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
14939 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
14940 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
14941 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
14942 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
14943 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
14944 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
14945 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
14946 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
14948 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
14949 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
14950 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
14951 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
14952 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
14953 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
14954 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
14955 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
14956 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
14957 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
14958 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
14959 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
14961 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
14962 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
14963 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
14964 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
14965 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
14966 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
14967 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
14968 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
14969 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
14970 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
14971 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
14972 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
14974 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
14975 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
14976 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
14977 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
14978 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
14979 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
14980 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
14981 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
14982 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
14983 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
14984 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
14985 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
14987 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
14988 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
14989 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
14990 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
14991 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
14992 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
14993 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
14994 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
14995 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
14996 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
14997 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
14998 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
15000 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
15001 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
15002 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
15003 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
15004 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
15005 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
15006 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
15007 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
15008 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
15009 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
15010 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
15011 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
15013 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
15014 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
15015 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
15016 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
15017 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
15018 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
15019 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
15020 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
15021 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
15022 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
15023 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
15024 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
15026 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15027 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15028 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15029 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15030 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15031 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15032 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15033 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15034 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15035 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15036 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15037 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15039 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15040 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15041 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15042 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15043 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15044 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15045 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15046 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15047 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15048 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15049 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15050 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15052 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15053 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15054 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15055 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15056 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15057 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15058 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15059 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15060 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15061 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15062 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15063 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15065 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15066 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15067 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15068 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15069 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15070 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15071 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15072 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15073 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15074 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15075 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15076 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15078 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15079 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15080 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15081 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15082 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15083 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15084 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15085 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15086 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15087 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15088 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15089 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15091 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15092 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15093 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15094 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15095 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15096 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15097 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15098 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15099 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15100 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15101 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15102 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15104 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15105 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15106 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15107 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15108 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15109 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15110 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15111 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15112 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15113 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15114 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15115 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15117 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15118 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15119 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15120 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15121 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15122 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15123 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15124 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15125 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15126 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15127 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15128 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15130 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15131 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15132 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15133 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15134 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15135 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15136 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15137 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15138 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15139 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15140 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15141 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15143 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15144 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15145 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15146 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15147 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15148 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15149 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15150 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15151 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15152 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15153 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15154 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15156 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15157 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15158 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15159 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15160 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15161 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15162 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15163 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15164 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15165 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15166 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15167 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15169 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15170 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15171 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15172 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15173 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15174 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15175 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15176 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15177 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15178 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15179 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15180 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15182 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15183 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15184 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15185 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15186 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15187 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15188 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15189 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15190 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15191 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15192 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15193 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15195 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15196 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15197 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15198 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15200 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
15201 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
15202 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
15203 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
15204 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
15205 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
15206 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
15207 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
15208 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
15209 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
15210 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
15211 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
15213 /* The implementation of the FIX instruction is broken on some
15214 assemblers, in that it accepts a precision specifier as well as a
15215 rounding specifier, despite the fact that this is meaningless.
15216 To be more compatible, we accept it as well, though of course it
15217 does not set any bits. */
15218 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
15219 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
15220 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
15221 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
15222 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
15223 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
15224 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
15225 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
15226 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
15227 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
15228 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
15229 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
15230 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
15232 /* Instructions that were new with the real FPA, call them V2. */
15234 #define ARM_VARIANT &fpu_fpa_ext_v2
15235 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15236 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15237 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15238 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15239 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15240 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15243 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
15244 /* Moves and type conversions. */
15245 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15246 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
15247 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
15248 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
15249 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15250 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15251 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15252 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15253 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15254 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15255 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
15256 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
15258 /* Memory operations. */
15259 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15260 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15261 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15262 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15263 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15264 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15265 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15266 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15267 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15268 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15269 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15270 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15271 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15272 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15273 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15274 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15275 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15276 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15278 /* Monadic operations. */
15279 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15280 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15281 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15283 /* Dyadic operations. */
15284 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15285 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15286 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15287 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15288 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15289 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15290 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15291 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15292 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15295 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15296 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
15297 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15298 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
15301 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
15302 /* Moves and type conversions. */
15303 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15304 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15305 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15306 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15307 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15308 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15309 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15310 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15311 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15312 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15313 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15314 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15315 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15317 /* Memory operations. */
15318 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15319 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15320 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15321 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15322 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15323 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15324 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15325 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15326 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15327 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15329 /* Monadic operations. */
15330 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15331 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15332 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15334 /* Dyadic operations. */
15335 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15336 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15337 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15338 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15339 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15340 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15341 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15342 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15343 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15346 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15347 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
15348 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15349 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
15352 #define ARM_VARIANT &fpu_vfp_ext_v2
15353 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
15354 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
15355 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
15356 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
15358 /* Instructions which may belong to either the Neon or VFP instruction sets.
15359 Individual encoder functions perform additional architecture checks. */
15361 #define ARM_VARIANT &fpu_vfp_ext_v1xd
15362 #undef THUMB_VARIANT
15363 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
15364 /* These mnemonics are unique to VFP. */
15365 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
15366 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
15367 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15368 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15369 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15370 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15371 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15372 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
15373 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
15374 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
15376 /* Mnemonics shared by Neon and VFP. */
15377 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
15378 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15379 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15381 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15382 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15384 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15385 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15387 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15388 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15389 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15390 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15391 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15392 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15393 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15394 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15396 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
15398 /* NOTE: All VMOV encoding is special-cased! */
15399 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
15400 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
15402 #undef THUMB_VARIANT
15403 #define THUMB_VARIANT &fpu_neon_ext_v1
15405 #define ARM_VARIANT &fpu_neon_ext_v1
15406 /* Data processing with three registers of the same length. */
15407 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
15408 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
15409 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
15410 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15411 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15412 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15413 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15414 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15415 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15416 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
15417 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15418 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15419 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15420 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15421 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15422 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15423 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15424 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15425 /* If not immediate, fall back to neon_dyadic_i64_su.
15426 shl_imm should accept I8 I16 I32 I64,
15427 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
15428 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
15429 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
15430 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
15431 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
15432 /* Logic ops, types optional & ignored. */
15433 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
15434 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
15435 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
15436 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
15437 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
15438 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
15439 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
15440 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
15441 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
15442 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
15443 /* Bitfield ops, untyped. */
15444 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15445 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15446 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15447 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15448 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15449 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15450 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
15451 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15452 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15453 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15454 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15455 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15456 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15457 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
15458 back to neon_dyadic_if_su. */
15459 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15460 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15461 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15462 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15463 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15464 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15465 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15466 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15467 /* Comparison. Type I8 I16 I32 F32. Non-immediate -> neon_dyadic_if_i. */
15468 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
15469 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
15470 /* As above, D registers only. */
15471 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15472 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15473 /* Int and float variants, signedness unimportant. */
15474 /* If not scalar, fall back to neon_dyadic_if_i. */
15475 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15476 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15477 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
15478 /* Add/sub take types I8 I16 I32 I64 F32. */
15479 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
15480 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
15481 /* vtst takes sizes 8, 16, 32. */
15482 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
15483 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
15484 /* VMUL takes I8 I16 I32 F32 P8. */
15485 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
15486 /* VQD{R}MULH takes S16 S32. */
15487 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
15488 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
15489 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
15490 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
15491 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
15492 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
15493 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
15494 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
15495 NUF(vaclt
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
15496 NUF(vacltq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
15497 NUF(vacle
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
15498 NUF(vacleq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
15499 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
15500 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
15501 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
15502 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
15504 /* Two address, int/float. Types S8 S16 S32 F32. */
15505 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
15506 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
15508 /* Data processing with two registers and a shift amount. */
15509 /* Right shifts, and variants with rounding.
15510 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
15511 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
15512 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
15513 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
15514 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
15515 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
15516 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
15517 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
15518 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
15519 /* Shift and insert. Sizes accepted 8 16 32 64. */
15520 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
15521 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
15522 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
15523 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
15524 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
15525 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
15526 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
15527 /* Right shift immediate, saturating & narrowing, with rounding variants.
15528 Types accepted S16 S32 S64 U16 U32 U64. */
15529 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
15530 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
15531 /* As above, unsigned. Types accepted S16 S32 S64. */
15532 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
15533 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
15534 /* Right shift narrowing. Types accepted I16 I32 I64. */
15535 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
15536 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
15537 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
15538 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
15539 /* CVT with optional immediate for fixed-point variant. */
15540 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
15542 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
15543 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
15545 /* Data processing, three registers of different lengths. */
15546 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
15547 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
15548 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15549 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15550 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15551 /* If not scalar, fall back to neon_dyadic_long.
15552 Vector types as above, scalar types S16 S32 U16 U32. */
15553 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
15554 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
15555 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
15556 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
15557 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
15558 /* Dyadic, narrowing insns. Types I16 I32 I64. */
15559 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15560 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15561 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15562 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15563 /* Saturating doubling multiplies. Types S16 S32. */
15564 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15565 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15566 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15567 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
15568 S16 S32 U16 U32. */
15569 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
15571 /* Extract. Size 8. */
15572 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I7
), neon_ext
),
15573 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I7
), neon_ext
),
15575 /* Two registers, miscellaneous. */
15576 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
15577 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
15578 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
15579 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
15580 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
15581 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
15582 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
15583 /* Vector replicate. Sizes 8 16 32. */
15584 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
15585 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
15586 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
15587 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
15588 /* VMOVN. Types I16 I32 I64. */
15589 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
15590 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
15591 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
15592 /* VQMOVUN. Types S16 S32 S64. */
15593 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
15594 /* VZIP / VUZP. Sizes 8 16 32. */
15595 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
15596 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
15597 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
15598 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
15599 /* VQABS / VQNEG. Types S8 S16 S32. */
15600 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
15601 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
15602 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
15603 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
15604 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
15605 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
15606 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
15607 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
15608 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
15609 /* Reciprocal estimates. Types U32 F32. */
15610 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
15611 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
15612 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
15613 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
15614 /* VCLS. Types S8 S16 S32. */
15615 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
15616 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
15617 /* VCLZ. Types I8 I16 I32. */
15618 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
15619 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
15620 /* VCNT. Size 8. */
15621 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
15622 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
15623 /* Two address, untyped. */
15624 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
15625 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
15626 /* VTRN. Sizes 8 16 32. */
15627 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
15628 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
15630 /* Table lookup. Size 8. */
15631 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
15632 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
15634 #undef THUMB_VARIANT
15635 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
15637 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
15638 /* Neon element/structure load/store. */
15639 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15640 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15641 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15642 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15643 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15644 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15645 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15646 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15648 #undef THUMB_VARIANT
15649 #define THUMB_VARIANT &fpu_vfp_ext_v3
15651 #define ARM_VARIANT &fpu_vfp_ext_v3
15652 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
15653 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
15654 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15655 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15656 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15657 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15658 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15659 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15660 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15661 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15662 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15663 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15664 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15665 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15666 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15667 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15668 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15669 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15671 #undef THUMB_VARIANT
15673 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
15674 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15675 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15676 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15677 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15678 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15679 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15680 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
15681 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
15684 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
15685 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
15686 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
15687 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
15688 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
15689 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
15690 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
15691 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
15692 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
15693 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
15694 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15695 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15696 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15697 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15698 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15699 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15700 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15701 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15702 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15703 cCE(tmcr
, e000110
, 2, (RIWC
, RR
), rn_rd
),
15704 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
15705 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15706 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15707 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15708 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15709 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15710 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15711 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
15712 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
15713 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
15714 cCE(tmrc
, e100110
, 2, (RR
, RIWC
), rd_rn
),
15715 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
15716 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
15717 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
15718 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
15719 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
15720 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
15721 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
15722 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15723 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15724 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15725 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15726 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15727 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15728 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15729 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15730 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15731 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
15732 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15733 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15734 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15735 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15736 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15737 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15738 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15739 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15740 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15741 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15742 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15743 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15744 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15745 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15746 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15747 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15748 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15749 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15750 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15751 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15752 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15753 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
15754 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
15755 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15756 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15757 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15758 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15759 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15760 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15761 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15762 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15763 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15764 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15765 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15766 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15767 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15768 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15769 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15770 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15771 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15772 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15773 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
15774 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15775 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15776 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15777 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15778 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15779 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15780 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15781 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15782 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15783 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15784 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15785 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15786 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15787 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15788 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15789 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15790 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15791 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15792 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15793 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15794 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15795 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
15796 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15797 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15798 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15799 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15800 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15801 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15802 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15803 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15804 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15805 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15806 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15807 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15808 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15809 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15810 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15811 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15812 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15813 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15814 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15815 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15816 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
15817 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
15818 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15819 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15820 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15821 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15822 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15823 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15824 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15825 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15826 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15827 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15828 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15829 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15830 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15831 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15832 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15833 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15834 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15835 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15836 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15837 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15838 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15839 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15840 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15841 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15842 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15843 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15844 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15845 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15846 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
15849 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
15850 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
15851 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
15852 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
15853 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
15854 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
15855 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
15856 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
15857 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
15858 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
15859 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
15860 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
15861 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
15862 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
15863 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
15864 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
15865 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
15866 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
15867 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
15868 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
15869 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
15870 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
15871 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
15872 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
15873 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
15874 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
15875 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
15876 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
15877 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
15878 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
15879 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
15880 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
15881 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
15882 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
15883 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
15884 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
15885 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
15886 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
15887 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
15888 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
15889 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
15890 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
15891 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
15892 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
15893 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
15894 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
15895 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
15896 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
15897 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
15898 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
15899 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
15900 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
15901 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
15902 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
15903 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
15904 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
15905 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
15906 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
15907 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
15908 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
15909 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
15910 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
15911 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
15912 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
15913 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
15914 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15915 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
15916 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15917 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
15918 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15919 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
15920 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15921 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15922 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
15923 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
15924 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
15925 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
15928 #undef THUMB_VARIANT
15955 /* MD interface: bits in the object file. */
15957 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
15958 for use in the a.out file, and stores them in the array pointed to by buf.
15959 This knows about the endian-ness of the target machine and does
15960 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
15961 2 (short) and 4 (long) Floating numbers are put out as a series of
15962 LITTLENUMS (shorts, here at least). */
15965 md_number_to_chars (char * buf
, valueT val
, int n
)
15967 if (target_big_endian
)
15968 number_to_chars_bigendian (buf
, val
, n
);
15970 number_to_chars_littleendian (buf
, val
, n
);
15974 md_chars_to_number (char * buf
, int n
)
15977 unsigned char * where
= (unsigned char *) buf
;
15979 if (target_big_endian
)
15984 result
|= (*where
++ & 255);
15992 result
|= (where
[n
] & 255);
15999 /* MD interface: Sections. */
16001 /* Estimate the size of a frag before relaxing. Assume everything fits in
16005 md_estimate_size_before_relax (fragS
* fragp
,
16006 segT segtype ATTRIBUTE_UNUSED
)
16012 /* Convert a machine dependent frag. */
16015 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
16017 unsigned long insn
;
16018 unsigned long old_op
;
16026 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16028 old_op
= bfd_get_16(abfd
, buf
);
16029 if (fragp
->fr_symbol
) {
16030 exp
.X_op
= O_symbol
;
16031 exp
.X_add_symbol
= fragp
->fr_symbol
;
16033 exp
.X_op
= O_constant
;
16035 exp
.X_add_number
= fragp
->fr_offset
;
16036 opcode
= fragp
->fr_subtype
;
16039 case T_MNEM_ldr_pc
:
16040 case T_MNEM_ldr_pc2
:
16041 case T_MNEM_ldr_sp
:
16042 case T_MNEM_str_sp
:
16049 if (fragp
->fr_var
== 4)
16051 insn
= THUMB_OP32(opcode
);
16052 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
16054 insn
|= (old_op
& 0x700) << 4;
16058 insn
|= (old_op
& 7) << 12;
16059 insn
|= (old_op
& 0x38) << 13;
16061 insn
|= 0x00000c00;
16062 put_thumb32_insn (buf
, insn
);
16063 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
16067 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
16069 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
16072 if (fragp
->fr_var
== 4)
16074 insn
= THUMB_OP32 (opcode
);
16075 insn
|= (old_op
& 0xf0) << 4;
16076 put_thumb32_insn (buf
, insn
);
16077 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
16081 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16082 exp
.X_add_number
-= 4;
16090 if (fragp
->fr_var
== 4)
16092 int r0off
= (opcode
== T_MNEM_mov
16093 || opcode
== T_MNEM_movs
) ? 0 : 8;
16094 insn
= THUMB_OP32 (opcode
);
16095 insn
= (insn
& 0xe1ffffff) | 0x10000000;
16096 insn
|= (old_op
& 0x700) << r0off
;
16097 put_thumb32_insn (buf
, insn
);
16098 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16102 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
16107 if (fragp
->fr_var
== 4)
16109 insn
= THUMB_OP32(opcode
);
16110 put_thumb32_insn (buf
, insn
);
16111 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
16114 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
16118 if (fragp
->fr_var
== 4)
16120 insn
= THUMB_OP32(opcode
);
16121 insn
|= (old_op
& 0xf00) << 14;
16122 put_thumb32_insn (buf
, insn
);
16123 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
16126 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
16129 case T_MNEM_add_sp
:
16130 case T_MNEM_add_pc
:
16131 case T_MNEM_inc_sp
:
16132 case T_MNEM_dec_sp
:
16133 if (fragp
->fr_var
== 4)
16135 /* ??? Choose between add and addw. */
16136 insn
= THUMB_OP32 (opcode
);
16137 insn
|= (old_op
& 0xf0) << 4;
16138 put_thumb32_insn (buf
, insn
);
16139 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16142 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16150 if (fragp
->fr_var
== 4)
16152 insn
= THUMB_OP32 (opcode
);
16153 insn
|= (old_op
& 0xf0) << 4;
16154 insn
|= (old_op
& 0xf) << 16;
16155 put_thumb32_insn (buf
, insn
);
16156 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16159 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16165 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
16167 fixp
->fx_file
= fragp
->fr_file
;
16168 fixp
->fx_line
= fragp
->fr_line
;
16169 fragp
->fr_fix
+= fragp
->fr_var
;
16172 /* Return the size of a relaxable immediate operand instruction.
16173 SHIFT and SIZE specify the form of the allowable immediate. */
16175 relax_immediate (fragS
*fragp
, int size
, int shift
)
16181 /* ??? Should be able to do better than this. */
16182 if (fragp
->fr_symbol
)
16185 low
= (1 << shift
) - 1;
16186 mask
= (1 << (shift
+ size
)) - (1 << shift
);
16187 offset
= fragp
->fr_offset
;
16188 /* Force misaligned offsets to 32-bit variant. */
16191 if (offset
& ~mask
)
16196 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
16199 relax_adr (fragS
*fragp
, asection
*sec
)
16204 /* Assume worst case for symbols not known to be in the same section. */
16205 if (!S_IS_DEFINED(fragp
->fr_symbol
)
16206 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16209 val
= S_GET_VALUE(fragp
->fr_symbol
) + fragp
->fr_offset
;
16210 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16211 addr
= (addr
+ 4) & ~3;
16212 /* Fix the insn as the 4-byte version if the target address is not
16213 sufficiently aligned. This is prevents an infinite loop when two
16214 instructions have contradictory range/alignment requirements. */
16218 if (val
< 0 || val
> 1020)
16223 /* Return the size of a relaxable add/sub immediate instruction. */
16225 relax_addsub (fragS
*fragp
, asection
*sec
)
16230 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16231 op
= bfd_get_16(sec
->owner
, buf
);
16232 if ((op
& 0xf) == ((op
>> 4) & 0xf))
16233 return relax_immediate (fragp
, 8, 0);
16235 return relax_immediate (fragp
, 3, 0);
16239 /* Return the size of a relaxable branch instruction. BITS is the
16240 size of the offset field in the narrow instruction. */
16243 relax_branch (fragS
*fragp
, asection
*sec
, int bits
)
16249 /* Assume worst case for symbols not known to be in the same section. */
16250 if (!S_IS_DEFINED(fragp
->fr_symbol
)
16251 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16254 val
= S_GET_VALUE(fragp
->fr_symbol
) + fragp
->fr_offset
;
16255 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16258 /* Offset is a signed value *2 */
16260 if (val
>= limit
|| val
< -limit
)
16266 /* Relax a machine dependent frag. This returns the amount by which
16267 the current size of the frag should change. */
16270 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
16275 oldsize
= fragp
->fr_var
;
16276 switch (fragp
->fr_subtype
)
16278 case T_MNEM_ldr_pc2
:
16279 newsize
= relax_adr(fragp
, sec
);
16281 case T_MNEM_ldr_pc
:
16282 case T_MNEM_ldr_sp
:
16283 case T_MNEM_str_sp
:
16284 newsize
= relax_immediate(fragp
, 8, 2);
16288 newsize
= relax_immediate(fragp
, 5, 2);
16292 newsize
= relax_immediate(fragp
, 5, 1);
16296 newsize
= relax_immediate(fragp
, 5, 0);
16299 newsize
= relax_adr(fragp
, sec
);
16305 newsize
= relax_immediate(fragp
, 8, 0);
16308 newsize
= relax_branch(fragp
, sec
, 11);
16311 newsize
= relax_branch(fragp
, sec
, 8);
16313 case T_MNEM_add_sp
:
16314 case T_MNEM_add_pc
:
16315 newsize
= relax_immediate (fragp
, 8, 2);
16317 case T_MNEM_inc_sp
:
16318 case T_MNEM_dec_sp
:
16319 newsize
= relax_immediate (fragp
, 7, 2);
16325 newsize
= relax_addsub (fragp
, sec
);
16332 fragp
->fr_var
= -newsize
;
16333 md_convert_frag (sec
->owner
, sec
, fragp
);
16335 return -(newsize
+ oldsize
);
16337 fragp
->fr_var
= newsize
;
16338 return newsize
- oldsize
;
16341 /* Round up a section size to the appropriate boundary. */
16344 md_section_align (segT segment ATTRIBUTE_UNUSED
,
16350 /* Round all sects to multiple of 4. */
16351 return (size
+ 3) & ~3;
16355 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
16356 of an rs_align_code fragment. */
16359 arm_handle_align (fragS
* fragP
)
16361 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
16362 static char const thumb_noop
[2] = { 0xc0, 0x46 };
16363 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
16364 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
16366 int bytes
, fix
, noop_size
;
16370 if (fragP
->fr_type
!= rs_align_code
)
16373 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
16374 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
16377 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
16378 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
16380 if (fragP
->tc_frag_data
)
16382 if (target_big_endian
)
16383 noop
= thumb_bigend_noop
;
16386 noop_size
= sizeof (thumb_noop
);
16390 if (target_big_endian
)
16391 noop
= arm_bigend_noop
;
16394 noop_size
= sizeof (arm_noop
);
16397 if (bytes
& (noop_size
- 1))
16399 fix
= bytes
& (noop_size
- 1);
16400 memset (p
, 0, fix
);
16405 while (bytes
>= noop_size
)
16407 memcpy (p
, noop
, noop_size
);
16409 bytes
-= noop_size
;
16413 fragP
->fr_fix
+= fix
;
16414 fragP
->fr_var
= noop_size
;
16417 /* Called from md_do_align. Used to create an alignment
16418 frag in a code section. */
16421 arm_frag_align_code (int n
, int max
)
16425 /* We assume that there will never be a requirement
16426 to support alignments greater than 32 bytes. */
16427 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
16428 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
16430 p
= frag_var (rs_align_code
,
16431 MAX_MEM_FOR_RS_ALIGN_CODE
,
16433 (relax_substateT
) max
,
16440 /* Perform target specific initialisation of a frag. */
16443 arm_init_frag (fragS
* fragP
)
16445 /* Record whether this frag is in an ARM or a THUMB area. */
16446 fragP
->tc_frag_data
= thumb_mode
;
16450 /* When we change sections we need to issue a new mapping symbol. */
16453 arm_elf_change_section (void)
16456 segment_info_type
*seginfo
;
16458 /* Link an unlinked unwind index table section to the .text section. */
16459 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
16460 && elf_linked_to_section (now_seg
) == NULL
)
16461 elf_linked_to_section (now_seg
) = text_section
;
16463 if (!SEG_NORMAL (now_seg
))
16466 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
16468 /* We can ignore sections that only contain debug info. */
16469 if ((flags
& SEC_ALLOC
) == 0)
16472 seginfo
= seg_info (now_seg
);
16473 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
16474 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
16478 arm_elf_section_type (const char * str
, size_t len
)
16480 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
16481 return SHT_ARM_EXIDX
;
16486 /* Code to deal with unwinding tables. */
16488 static void add_unwind_adjustsp (offsetT
);
16490 /* Cenerate and deferred unwind frame offset. */
16493 flush_pending_unwind (void)
16497 offset
= unwind
.pending_offset
;
16498 unwind
.pending_offset
= 0;
16500 add_unwind_adjustsp (offset
);
16503 /* Add an opcode to this list for this function. Two-byte opcodes should
16504 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
16508 add_unwind_opcode (valueT op
, int length
)
16510 /* Add any deferred stack adjustment. */
16511 if (unwind
.pending_offset
)
16512 flush_pending_unwind ();
16514 unwind
.sp_restored
= 0;
16516 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
16518 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
16519 if (unwind
.opcodes
)
16520 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
16521 unwind
.opcode_alloc
);
16523 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
16528 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
16530 unwind
.opcode_count
++;
16534 /* Add unwind opcodes to adjust the stack pointer. */
16537 add_unwind_adjustsp (offsetT offset
)
16541 if (offset
> 0x200)
16543 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
16548 /* Long form: 0xb2, uleb128. */
16549 /* This might not fit in a word so add the individual bytes,
16550 remembering the list is built in reverse order. */
16551 o
= (valueT
) ((offset
- 0x204) >> 2);
16553 add_unwind_opcode (0, 1);
16555 /* Calculate the uleb128 encoding of the offset. */
16559 bytes
[n
] = o
& 0x7f;
16565 /* Add the insn. */
16567 add_unwind_opcode (bytes
[n
- 1], 1);
16568 add_unwind_opcode (0xb2, 1);
16570 else if (offset
> 0x100)
16572 /* Two short opcodes. */
16573 add_unwind_opcode (0x3f, 1);
16574 op
= (offset
- 0x104) >> 2;
16575 add_unwind_opcode (op
, 1);
16577 else if (offset
> 0)
16579 /* Short opcode. */
16580 op
= (offset
- 4) >> 2;
16581 add_unwind_opcode (op
, 1);
16583 else if (offset
< 0)
16586 while (offset
> 0x100)
16588 add_unwind_opcode (0x7f, 1);
16591 op
= ((offset
- 4) >> 2) | 0x40;
16592 add_unwind_opcode (op
, 1);
16596 /* Finish the list of unwind opcodes for this function. */
16598 finish_unwind_opcodes (void)
16602 if (unwind
.fp_used
)
16604 /* Adjust sp as necessary. */
16605 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
16606 flush_pending_unwind ();
16608 /* After restoring sp from the frame pointer. */
16609 op
= 0x90 | unwind
.fp_reg
;
16610 add_unwind_opcode (op
, 1);
16613 flush_pending_unwind ();
16617 /* Start an exception table entry. If idx is nonzero this is an index table
16621 start_unwind_section (const segT text_seg
, int idx
)
16623 const char * text_name
;
16624 const char * prefix
;
16625 const char * prefix_once
;
16626 const char * group_name
;
16630 size_t sec_name_len
;
16637 prefix
= ELF_STRING_ARM_unwind
;
16638 prefix_once
= ELF_STRING_ARM_unwind_once
;
16639 type
= SHT_ARM_EXIDX
;
16643 prefix
= ELF_STRING_ARM_unwind_info
;
16644 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
16645 type
= SHT_PROGBITS
;
16648 text_name
= segment_name (text_seg
);
16649 if (streq (text_name
, ".text"))
16652 if (strncmp (text_name
, ".gnu.linkonce.t.",
16653 strlen (".gnu.linkonce.t.")) == 0)
16655 prefix
= prefix_once
;
16656 text_name
+= strlen (".gnu.linkonce.t.");
16659 prefix_len
= strlen (prefix
);
16660 text_len
= strlen (text_name
);
16661 sec_name_len
= prefix_len
+ text_len
;
16662 sec_name
= xmalloc (sec_name_len
+ 1);
16663 memcpy (sec_name
, prefix
, prefix_len
);
16664 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
16665 sec_name
[prefix_len
+ text_len
] = '\0';
16671 /* Handle COMDAT group. */
16672 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
16674 group_name
= elf_group_name (text_seg
);
16675 if (group_name
== NULL
)
16677 as_bad ("Group section `%s' has no group signature",
16678 segment_name (text_seg
));
16679 ignore_rest_of_line ();
16682 flags
|= SHF_GROUP
;
16686 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
16688 /* Set the setion link for index tables. */
16690 elf_linked_to_section (now_seg
) = text_seg
;
16694 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
16695 personality routine data. Returns zero, or the index table value for
16696 and inline entry. */
16699 create_unwind_entry (int have_data
)
16704 /* The current word of data. */
16706 /* The number of bytes left in this word. */
16709 finish_unwind_opcodes ();
16711 /* Remember the current text section. */
16712 unwind
.saved_seg
= now_seg
;
16713 unwind
.saved_subseg
= now_subseg
;
16715 start_unwind_section (now_seg
, 0);
16717 if (unwind
.personality_routine
== NULL
)
16719 if (unwind
.personality_index
== -2)
16722 as_bad (_("handerdata in cantunwind frame"));
16723 return 1; /* EXIDX_CANTUNWIND. */
16726 /* Use a default personality routine if none is specified. */
16727 if (unwind
.personality_index
== -1)
16729 if (unwind
.opcode_count
> 3)
16730 unwind
.personality_index
= 1;
16732 unwind
.personality_index
= 0;
16735 /* Space for the personality routine entry. */
16736 if (unwind
.personality_index
== 0)
16738 if (unwind
.opcode_count
> 3)
16739 as_bad (_("too many unwind opcodes for personality routine 0"));
16743 /* All the data is inline in the index table. */
16746 while (unwind
.opcode_count
> 0)
16748 unwind
.opcode_count
--;
16749 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
16753 /* Pad with "finish" opcodes. */
16755 data
= (data
<< 8) | 0xb0;
16762 /* We get two opcodes "free" in the first word. */
16763 size
= unwind
.opcode_count
- 2;
16766 /* An extra byte is required for the opcode count. */
16767 size
= unwind
.opcode_count
+ 1;
16769 size
= (size
+ 3) >> 2;
16771 as_bad (_("too many unwind opcodes"));
16773 frag_align (2, 0, 0);
16774 record_alignment (now_seg
, 2);
16775 unwind
.table_entry
= expr_build_dot ();
16777 /* Allocate the table entry. */
16778 ptr
= frag_more ((size
<< 2) + 4);
16779 where
= frag_now_fix () - ((size
<< 2) + 4);
16781 switch (unwind
.personality_index
)
16784 /* ??? Should this be a PLT generating relocation? */
16785 /* Custom personality routine. */
16786 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
16787 BFD_RELOC_ARM_PREL31
);
16792 /* Set the first byte to the number of additional words. */
16797 /* ABI defined personality routines. */
16799 /* Three opcodes bytes are packed into the first word. */
16806 /* The size and first two opcode bytes go in the first word. */
16807 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
16812 /* Should never happen. */
16816 /* Pack the opcodes into words (MSB first), reversing the list at the same
16818 while (unwind
.opcode_count
> 0)
16822 md_number_to_chars (ptr
, data
, 4);
16827 unwind
.opcode_count
--;
16829 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
16832 /* Finish off the last word. */
16835 /* Pad with "finish" opcodes. */
16837 data
= (data
<< 8) | 0xb0;
16839 md_number_to_chars (ptr
, data
, 4);
16844 /* Add an empty descriptor if there is no user-specified data. */
16845 ptr
= frag_more (4);
16846 md_number_to_chars (ptr
, 0, 4);
16852 /* Convert REGNAME to a DWARF-2 register number. */
16855 tc_arm_regname_to_dw2regnum (char *regname
)
16857 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
16865 /* Initialize the DWARF-2 unwind information for this procedure. */
16868 tc_arm_frame_initial_instructions (void)
16870 cfi_add_CFA_def_cfa (REG_SP
, 0);
16872 #endif /* OBJ_ELF */
16875 /* MD interface: Symbol and relocation handling. */
16877 /* Return the address within the segment that a PC-relative fixup is
16878 relative to. For ARM, PC-relative fixups applied to instructions
16879 are generally relative to the location of the fixup plus 8 bytes.
16880 Thumb branches are offset by 4, and Thumb loads relative to PC
16881 require special handling. */
16884 md_pcrel_from_section (fixS
* fixP
, segT seg
)
16886 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
16888 /* If this is pc-relative and we are going to emit a relocation
16889 then we just want to put out any pipeline compensation that the linker
16890 will need. Otherwise we want to use the calculated base.
16891 For WinCE we skip the bias for externals as well, since this
16892 is how the MS ARM-CE assembler behaves and we want to be compatible. */
16894 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
16895 || (arm_force_relocation (fixP
)
16897 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
16902 switch (fixP
->fx_r_type
)
16904 /* PC relative addressing on the Thumb is slightly odd as the
16905 bottom two bits of the PC are forced to zero for the
16906 calculation. This happens *after* application of the
16907 pipeline offset. However, Thumb adrl already adjusts for
16908 this, so we need not do it again. */
16909 case BFD_RELOC_ARM_THUMB_ADD
:
16912 case BFD_RELOC_ARM_THUMB_OFFSET
:
16913 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
16914 case BFD_RELOC_ARM_T32_ADD_PC12
:
16915 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
16916 return (base
+ 4) & ~3;
16918 /* Thumb branches are simply offset by +4. */
16919 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
16920 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
16921 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
16922 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
16923 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
16924 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
16925 case BFD_RELOC_THUMB_PCREL_BLX
:
16928 /* ARM mode branches are offset by +8. However, the Windows CE
16929 loader expects the relocation not to take this into account. */
16930 case BFD_RELOC_ARM_PCREL_BRANCH
:
16931 case BFD_RELOC_ARM_PCREL_CALL
:
16932 case BFD_RELOC_ARM_PCREL_JUMP
:
16933 case BFD_RELOC_ARM_PCREL_BLX
:
16934 case BFD_RELOC_ARM_PLT32
:
16936 /* When handling fixups immediately, because we have already
16937 discovered the value of a symbol, or the address of the frag involved
16938 we must account for the offset by +8, as the OS loader will never see the reloc.
16939 see fixup_segment() in write.c
16940 The S_IS_EXTERNAL test handles the case of global symbols.
16941 Those need the calculated base, not just the pipe compensation the linker will need. */
16943 && fixP
->fx_addsy
!= NULL
16944 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
16945 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
16952 /* ARM mode loads relative to PC are also offset by +8. Unlike
16953 branches, the Windows CE loader *does* expect the relocation
16954 to take this into account. */
16955 case BFD_RELOC_ARM_OFFSET_IMM
:
16956 case BFD_RELOC_ARM_OFFSET_IMM8
:
16957 case BFD_RELOC_ARM_HWLITERAL
:
16958 case BFD_RELOC_ARM_LITERAL
:
16959 case BFD_RELOC_ARM_CP_OFF_IMM
:
16963 /* Other PC-relative relocations are un-offset. */
16969 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
16970 Otherwise we have no need to default values of symbols. */
16973 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
16976 if (name
[0] == '_' && name
[1] == 'G'
16977 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
16981 if (symbol_find (name
))
16982 as_bad ("GOT already in the symbol table");
16984 GOT_symbol
= symbol_new (name
, undefined_section
,
16985 (valueT
) 0, & zero_address_frag
);
16995 /* Subroutine of md_apply_fix. Check to see if an immediate can be
16996 computed as two separate immediate values, added together. We
16997 already know that this value cannot be computed by just one ARM
17000 static unsigned int
17001 validate_immediate_twopart (unsigned int val
,
17002 unsigned int * highpart
)
17007 for (i
= 0; i
< 32; i
+= 2)
17008 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
17014 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
17016 else if (a
& 0xff0000)
17018 if (a
& 0xff000000)
17020 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
17024 assert (a
& 0xff000000);
17025 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
17028 return (a
& 0xff) | (i
<< 7);
17035 validate_offset_imm (unsigned int val
, int hwse
)
17037 if ((hwse
&& val
> 255) || val
> 4095)
17042 /* Subroutine of md_apply_fix. Do those data_ops which can take a
17043 negative immediate constant by altering the instruction. A bit of
17048 by inverting the second operand, and
17051 by negating the second operand. */
17054 negate_data_op (unsigned long * instruction
,
17055 unsigned long value
)
17058 unsigned long negated
, inverted
;
17060 negated
= encode_arm_immediate (-value
);
17061 inverted
= encode_arm_immediate (~value
);
17063 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
17066 /* First negates. */
17067 case OPCODE_SUB
: /* ADD <-> SUB */
17068 new_inst
= OPCODE_ADD
;
17073 new_inst
= OPCODE_SUB
;
17077 case OPCODE_CMP
: /* CMP <-> CMN */
17078 new_inst
= OPCODE_CMN
;
17083 new_inst
= OPCODE_CMP
;
17087 /* Now Inverted ops. */
17088 case OPCODE_MOV
: /* MOV <-> MVN */
17089 new_inst
= OPCODE_MVN
;
17094 new_inst
= OPCODE_MOV
;
17098 case OPCODE_AND
: /* AND <-> BIC */
17099 new_inst
= OPCODE_BIC
;
17104 new_inst
= OPCODE_AND
;
17108 case OPCODE_ADC
: /* ADC <-> SBC */
17109 new_inst
= OPCODE_SBC
;
17114 new_inst
= OPCODE_ADC
;
17118 /* We cannot do anything. */
17123 if (value
== (unsigned) FAIL
)
17126 *instruction
&= OPCODE_MASK
;
17127 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
17131 /* Like negate_data_op, but for Thumb-2. */
17133 static unsigned int
17134 thumb32_negate_data_op (offsetT
*instruction
, offsetT value
)
17138 offsetT negated
, inverted
;
17140 negated
= encode_thumb32_immediate (-value
);
17141 inverted
= encode_thumb32_immediate (~value
);
17143 rd
= (*instruction
>> 8) & 0xf;
17144 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
17147 /* ADD <-> SUB. Includes CMP <-> CMN. */
17148 case T2_OPCODE_SUB
:
17149 new_inst
= T2_OPCODE_ADD
;
17153 case T2_OPCODE_ADD
:
17154 new_inst
= T2_OPCODE_SUB
;
17158 /* ORR <-> ORN. Includes MOV <-> MVN. */
17159 case T2_OPCODE_ORR
:
17160 new_inst
= T2_OPCODE_ORN
;
17164 case T2_OPCODE_ORN
:
17165 new_inst
= T2_OPCODE_ORR
;
17169 /* AND <-> BIC. TST has no inverted equivalent. */
17170 case T2_OPCODE_AND
:
17171 new_inst
= T2_OPCODE_BIC
;
17178 case T2_OPCODE_BIC
:
17179 new_inst
= T2_OPCODE_AND
;
17184 case T2_OPCODE_ADC
:
17185 new_inst
= T2_OPCODE_SBC
;
17189 case T2_OPCODE_SBC
:
17190 new_inst
= T2_OPCODE_ADC
;
17194 /* We cannot do anything. */
17202 *instruction
&= T2_OPCODE_MASK
;
17203 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
17207 /* Read a 32-bit thumb instruction from buf. */
17208 static unsigned long
17209 get_thumb32_insn (char * buf
)
17211 unsigned long insn
;
17212 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
17213 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17219 /* We usually want to set the low bit on the address of thumb function
17220 symbols. In particular .word foo - . should have the low bit set.
17221 Generic code tries to fold the difference of two symbols to
17222 a constant. Prevent this and force a relocation when the first symbols
17223 is a thumb function. */
17225 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
17227 if (op
== O_subtract
17228 && l
->X_op
== O_symbol
17229 && r
->X_op
== O_symbol
17230 && THUMB_IS_FUNC (l
->X_add_symbol
))
17232 l
->X_op
= O_subtract
;
17233 l
->X_op_symbol
= r
->X_add_symbol
;
17234 l
->X_add_number
-= r
->X_add_number
;
17237 /* Process as normal. */
17242 md_apply_fix (fixS
* fixP
,
17246 offsetT value
= * valP
;
17248 unsigned int newimm
;
17249 unsigned long temp
;
17251 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
17253 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
17255 /* Note whether this will delete the relocation. */
17257 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
17260 /* On a 64-bit host, silently truncate 'value' to 32 bits for
17261 consistency with the behavior on 32-bit hosts. Remember value
17263 value
&= 0xffffffff;
17264 value
^= 0x80000000;
17265 value
-= 0x80000000;
17268 fixP
->fx_addnumber
= value
;
17270 /* Same treatment for fixP->fx_offset. */
17271 fixP
->fx_offset
&= 0xffffffff;
17272 fixP
->fx_offset
^= 0x80000000;
17273 fixP
->fx_offset
-= 0x80000000;
17275 switch (fixP
->fx_r_type
)
17277 case BFD_RELOC_NONE
:
17278 /* This will need to go in the object file. */
17282 case BFD_RELOC_ARM_IMMEDIATE
:
17283 /* We claim that this fixup has been processed here,
17284 even if in fact we generate an error because we do
17285 not have a reloc for it, so tc_gen_reloc will reject it. */
17289 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17291 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17292 _("undefined symbol %s used as an immediate value"),
17293 S_GET_NAME (fixP
->fx_addsy
));
17297 newimm
= encode_arm_immediate (value
);
17298 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17300 /* If the instruction will fail, see if we can fix things up by
17301 changing the opcode. */
17302 if (newimm
== (unsigned int) FAIL
17303 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
17305 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17306 _("invalid constant (%lx) after fixup"),
17307 (unsigned long) value
);
17311 newimm
|= (temp
& 0xfffff000);
17312 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17315 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
17317 unsigned int highpart
= 0;
17318 unsigned int newinsn
= 0xe1a00000; /* nop. */
17320 newimm
= encode_arm_immediate (value
);
17321 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17323 /* If the instruction will fail, see if we can fix things up by
17324 changing the opcode. */
17325 if (newimm
== (unsigned int) FAIL
17326 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
17328 /* No ? OK - try using two ADD instructions to generate
17330 newimm
= validate_immediate_twopart (value
, & highpart
);
17332 /* Yes - then make sure that the second instruction is
17334 if (newimm
!= (unsigned int) FAIL
)
17336 /* Still No ? Try using a negated value. */
17337 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
17338 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
17339 /* Otherwise - give up. */
17342 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17343 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
17348 /* Replace the first operand in the 2nd instruction (which
17349 is the PC) with the destination register. We have
17350 already added in the PC in the first instruction and we
17351 do not want to do it again. */
17352 newinsn
&= ~ 0xf0000;
17353 newinsn
|= ((newinsn
& 0x0f000) << 4);
17356 newimm
|= (temp
& 0xfffff000);
17357 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17359 highpart
|= (newinsn
& 0xfffff000);
17360 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
17364 case BFD_RELOC_ARM_OFFSET_IMM
:
17365 if (!fixP
->fx_done
&& seg
->use_rela_p
)
17368 case BFD_RELOC_ARM_LITERAL
:
17374 if (validate_offset_imm (value
, 0) == FAIL
)
17376 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
17377 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17378 _("invalid literal constant: pool needs to be closer"));
17380 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17381 _("bad immediate value for offset (%ld)"),
17386 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17387 newval
&= 0xff7ff000;
17388 newval
|= value
| (sign
? INDEX_UP
: 0);
17389 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17392 case BFD_RELOC_ARM_OFFSET_IMM8
:
17393 case BFD_RELOC_ARM_HWLITERAL
:
17399 if (validate_offset_imm (value
, 1) == FAIL
)
17401 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
17402 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17403 _("invalid literal constant: pool needs to be closer"));
17405 as_bad (_("bad immediate value for half-word offset (%ld)"),
17410 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17411 newval
&= 0xff7ff0f0;
17412 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
17413 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17416 case BFD_RELOC_ARM_T32_OFFSET_U8
:
17417 if (value
< 0 || value
> 1020 || value
% 4 != 0)
17418 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17419 _("bad immediate value for offset (%ld)"), (long) value
);
17422 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
17424 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
17427 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17428 /* This is a complicated relocation used for all varieties of Thumb32
17429 load/store instruction with immediate offset:
17431 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
17432 *4, optional writeback(W)
17433 (doubleword load/store)
17435 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
17436 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
17437 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
17438 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
17439 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
17441 Uppercase letters indicate bits that are already encoded at
17442 this point. Lowercase letters are our problem. For the
17443 second block of instructions, the secondary opcode nybble
17444 (bits 8..11) is present, and bit 23 is zero, even if this is
17445 a PC-relative operation. */
17446 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17448 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
17450 if ((newval
& 0xf0000000) == 0xe0000000)
17452 /* Doubleword load/store: 8-bit offset, scaled by 4. */
17454 newval
|= (1 << 23);
17457 if (value
% 4 != 0)
17459 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17460 _("offset not a multiple of 4"));
17466 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17467 _("offset out of range"));
17472 else if ((newval
& 0x000f0000) == 0x000f0000)
17474 /* PC-relative, 12-bit offset. */
17476 newval
|= (1 << 23);
17481 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17482 _("offset out of range"));
17487 else if ((newval
& 0x00000100) == 0x00000100)
17489 /* Writeback: 8-bit, +/- offset. */
17491 newval
|= (1 << 9);
17496 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17497 _("offset out of range"));
17502 else if ((newval
& 0x00000f00) == 0x00000e00)
17504 /* T-instruction: positive 8-bit offset. */
17505 if (value
< 0 || value
> 0xff)
17507 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17508 _("offset out of range"));
17516 /* Positive 12-bit or negative 8-bit offset. */
17520 newval
|= (1 << 23);
17530 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17531 _("offset out of range"));
17538 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
17539 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
17542 case BFD_RELOC_ARM_SHIFT_IMM
:
17543 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17544 if (((unsigned long) value
) > 32
17546 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
17548 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17549 _("shift expression is too large"));
17554 /* Shifts of zero must be done as lsl. */
17556 else if (value
== 32)
17558 newval
&= 0xfffff07f;
17559 newval
|= (value
& 0x1f) << 7;
17560 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17563 case BFD_RELOC_ARM_T32_IMMEDIATE
:
17564 case BFD_RELOC_ARM_T32_IMM12
:
17565 case BFD_RELOC_ARM_T32_ADD_PC12
:
17566 /* We claim that this fixup has been processed here,
17567 even if in fact we generate an error because we do
17568 not have a reloc for it, so tc_gen_reloc will reject it. */
17572 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17574 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17575 _("undefined symbol %s used as an immediate value"),
17576 S_GET_NAME (fixP
->fx_addsy
));
17580 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17582 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
17584 /* FUTURE: Implement analogue of negate_data_op for T32. */
17585 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
)
17587 newimm
= encode_thumb32_immediate (value
);
17588 if (newimm
== (unsigned int) FAIL
)
17589 newimm
= thumb32_negate_data_op (&newval
, value
);
17593 /* 12 bit immediate for addw/subw. */
17597 newval
^= 0x00a00000;
17600 newimm
= (unsigned int) FAIL
;
17605 if (newimm
== (unsigned int)FAIL
)
17607 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17608 _("invalid constant (%lx) after fixup"),
17609 (unsigned long) value
);
17613 newval
|= (newimm
& 0x800) << 15;
17614 newval
|= (newimm
& 0x700) << 4;
17615 newval
|= (newimm
& 0x0ff);
17617 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
17618 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
17621 case BFD_RELOC_ARM_SMC
:
17622 if (((unsigned long) value
) > 0xffff)
17623 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17624 _("invalid smc expression"));
17625 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17626 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
17627 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17630 case BFD_RELOC_ARM_SWI
:
17631 if (fixP
->tc_fix_data
!= 0)
17633 if (((unsigned long) value
) > 0xff)
17634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17635 _("invalid swi expression"));
17636 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17638 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17642 if (((unsigned long) value
) > 0x00ffffff)
17643 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17644 _("invalid swi expression"));
17645 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17647 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17651 case BFD_RELOC_ARM_MULTI
:
17652 if (((unsigned long) value
) > 0xffff)
17653 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17654 _("invalid expression in load/store multiple"));
17655 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
17656 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17660 case BFD_RELOC_ARM_PCREL_CALL
:
17661 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17662 if ((newval
& 0xf0000000) == 0xf0000000)
17666 goto arm_branch_common
;
17668 case BFD_RELOC_ARM_PCREL_JUMP
:
17669 case BFD_RELOC_ARM_PLT32
:
17671 case BFD_RELOC_ARM_PCREL_BRANCH
:
17673 goto arm_branch_common
;
17675 case BFD_RELOC_ARM_PCREL_BLX
:
17678 /* We are going to store value (shifted right by two) in the
17679 instruction, in a 24 bit, signed field. Bits 26 through 32 either
17680 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
17681 also be be clear. */
17683 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17684 _("misaligned branch destination"));
17685 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
17686 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
17687 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17688 _("branch out of range"));
17690 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17692 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17693 newval
|= (value
>> 2) & 0x00ffffff;
17694 /* Set the H bit on BLX instructions. */
17698 newval
|= 0x01000000;
17700 newval
&= ~0x01000000;
17702 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17706 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CZB */
17707 /* CZB can only branch forward. */
17709 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17710 _("branch out of range"));
17712 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17714 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17715 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
17716 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17720 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
17721 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
17722 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17723 _("branch out of range"));
17725 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17727 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17728 newval
|= (value
& 0x1ff) >> 1;
17729 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17733 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
17734 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
17735 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17736 _("branch out of range"));
17738 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17740 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17741 newval
|= (value
& 0xfff) >> 1;
17742 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17746 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
17747 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
17748 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17749 _("conditional branch out of range"));
17751 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17754 addressT S
, J1
, J2
, lo
, hi
;
17756 S
= (value
& 0x00100000) >> 20;
17757 J2
= (value
& 0x00080000) >> 19;
17758 J1
= (value
& 0x00040000) >> 18;
17759 hi
= (value
& 0x0003f000) >> 12;
17760 lo
= (value
& 0x00000ffe) >> 1;
17762 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17763 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17764 newval
|= (S
<< 10) | hi
;
17765 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
17766 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17767 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
17771 case BFD_RELOC_THUMB_PCREL_BLX
:
17772 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
17773 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
17774 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17775 _("branch out of range"));
17777 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
17778 /* For a BLX instruction, make sure that the relocation is rounded up
17779 to a word boundary. This follows the semantics of the instruction
17780 which specifies that bit 1 of the target address will come from bit
17781 1 of the base address. */
17782 value
= (value
+ 1) & ~ 1;
17784 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17788 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17789 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17790 newval
|= (value
& 0x7fffff) >> 12;
17791 newval2
|= (value
& 0xfff) >> 1;
17792 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17793 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
17797 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
17798 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
17799 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17800 _("branch out of range"));
17802 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17805 addressT S
, I1
, I2
, lo
, hi
;
17807 S
= (value
& 0x01000000) >> 24;
17808 I1
= (value
& 0x00800000) >> 23;
17809 I2
= (value
& 0x00400000) >> 22;
17810 hi
= (value
& 0x003ff000) >> 12;
17811 lo
= (value
& 0x00000ffe) >> 1;
17816 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17817 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17818 newval
|= (S
<< 10) | hi
;
17819 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
17820 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17821 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
17826 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17827 md_number_to_chars (buf
, value
, 1);
17831 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17832 md_number_to_chars (buf
, value
, 2);
17836 case BFD_RELOC_ARM_TLS_GD32
:
17837 case BFD_RELOC_ARM_TLS_LE32
:
17838 case BFD_RELOC_ARM_TLS_IE32
:
17839 case BFD_RELOC_ARM_TLS_LDM32
:
17840 case BFD_RELOC_ARM_TLS_LDO32
:
17841 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
17844 case BFD_RELOC_ARM_GOT32
:
17845 case BFD_RELOC_ARM_GOTOFF
:
17846 case BFD_RELOC_ARM_TARGET2
:
17847 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17848 md_number_to_chars (buf
, 0, 4);
17852 case BFD_RELOC_RVA
:
17854 case BFD_RELOC_ARM_TARGET1
:
17855 case BFD_RELOC_ARM_ROSEGREL32
:
17856 case BFD_RELOC_ARM_SBREL32
:
17857 case BFD_RELOC_32_PCREL
:
17858 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17860 /* For WinCE we only do this for pcrel fixups. */
17861 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
17863 md_number_to_chars (buf
, value
, 4);
17867 case BFD_RELOC_ARM_PREL31
:
17868 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17870 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
17871 if ((value
^ (value
>> 1)) & 0x40000000)
17873 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17874 _("rel31 relocation overflow"));
17876 newval
|= value
& 0x7fffffff;
17877 md_number_to_chars (buf
, newval
, 4);
17882 case BFD_RELOC_ARM_CP_OFF_IMM
:
17883 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
17884 if (value
< -1023 || value
> 1023 || (value
& 3))
17885 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17886 _("co-processor offset out of range"));
17891 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
17892 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
17893 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17895 newval
= get_thumb32_insn (buf
);
17896 newval
&= 0xff7fff00;
17897 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
17899 newval
&= ~WRITE_BACK
;
17900 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
17901 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
17902 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17904 put_thumb32_insn (buf
, newval
);
17907 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
17908 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
17909 if (value
< -255 || value
> 255)
17910 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17911 _("co-processor offset out of range"));
17913 goto cp_off_common
;
17915 case BFD_RELOC_ARM_THUMB_OFFSET
:
17916 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17917 /* Exactly what ranges, and where the offset is inserted depends
17918 on the type of instruction, we can establish this from the
17920 switch (newval
>> 12)
17922 case 4: /* PC load. */
17923 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
17924 forced to zero for these loads; md_pcrel_from has already
17925 compensated for this. */
17927 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17928 _("invalid offset, target not word aligned (0x%08lX)"),
17929 (((unsigned long) fixP
->fx_frag
->fr_address
17930 + (unsigned long) fixP
->fx_where
) & ~3)
17931 + (unsigned long) value
);
17933 if (value
& ~0x3fc)
17934 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17935 _("invalid offset, value too big (0x%08lX)"),
17938 newval
|= value
>> 2;
17941 case 9: /* SP load/store. */
17942 if (value
& ~0x3fc)
17943 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17944 _("invalid offset, value too big (0x%08lX)"),
17946 newval
|= value
>> 2;
17949 case 6: /* Word load/store. */
17951 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17952 _("invalid offset, value too big (0x%08lX)"),
17954 newval
|= value
<< 4; /* 6 - 2. */
17957 case 7: /* Byte load/store. */
17959 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17960 _("invalid offset, value too big (0x%08lX)"),
17962 newval
|= value
<< 6;
17965 case 8: /* Halfword load/store. */
17967 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17968 _("invalid offset, value too big (0x%08lX)"),
17970 newval
|= value
<< 5; /* 6 - 1. */
17974 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17975 "Unable to process relocation for thumb opcode: %lx",
17976 (unsigned long) newval
);
17979 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17982 case BFD_RELOC_ARM_THUMB_ADD
:
17983 /* This is a complicated relocation, since we use it for all of
17984 the following immediate relocations:
17988 9bit ADD/SUB SP word-aligned
17989 10bit ADD PC/SP word-aligned
17991 The type of instruction being processed is encoded in the
17998 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18000 int rd
= (newval
>> 4) & 0xf;
18001 int rs
= newval
& 0xf;
18002 int subtract
= !!(newval
& 0x8000);
18004 /* Check for HI regs, only very restricted cases allowed:
18005 Adjusting SP, and using PC or SP to get an address. */
18006 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
18007 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
18008 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18009 _("invalid Hi register with immediate"));
18011 /* If value is negative, choose the opposite instruction. */
18015 subtract
= !subtract
;
18017 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18018 _("immediate value out of range"));
18023 if (value
& ~0x1fc)
18024 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18025 _("invalid immediate for stack address calculation"));
18026 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
18027 newval
|= value
>> 2;
18029 else if (rs
== REG_PC
|| rs
== REG_SP
)
18031 if (subtract
|| value
& ~0x3fc)
18032 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18033 _("invalid immediate for address calculation (value = 0x%08lX)"),
18034 (unsigned long) value
);
18035 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
18037 newval
|= value
>> 2;
18042 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18043 _("immediate value out of range"));
18044 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
18045 newval
|= (rd
<< 8) | value
;
18050 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18051 _("immediate value out of range"));
18052 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
18053 newval
|= rd
| (rs
<< 3) | (value
<< 6);
18056 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18059 case BFD_RELOC_ARM_THUMB_IMM
:
18060 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18061 if (value
< 0 || value
> 255)
18062 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18063 _("invalid immediate: %ld is too large"),
18066 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18069 case BFD_RELOC_ARM_THUMB_SHIFT
:
18070 /* 5bit shift value (0..32). LSL cannot take 32. */
18071 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
18072 temp
= newval
& 0xf800;
18073 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
18074 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18075 _("invalid shift value: %ld"), (long) value
);
18076 /* Shifts of zero must be encoded as LSL. */
18078 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
18079 /* Shifts of 32 are encoded as zero. */
18080 else if (value
== 32)
18082 newval
|= value
<< 6;
18083 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18086 case BFD_RELOC_VTABLE_INHERIT
:
18087 case BFD_RELOC_VTABLE_ENTRY
:
18091 case BFD_RELOC_ARM_MOVW
:
18092 case BFD_RELOC_ARM_MOVT
:
18093 case BFD_RELOC_ARM_THUMB_MOVW
:
18094 case BFD_RELOC_ARM_THUMB_MOVT
:
18095 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18097 /* REL format relocations are limited to a 16-bit addend. */
18098 if (!fixP
->fx_done
)
18100 if (value
< -0x1000 || value
> 0xffff)
18101 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18102 _("offset too big"));
18104 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
18105 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18110 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
18111 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18113 newval
= get_thumb32_insn (buf
);
18114 newval
&= 0xfbf08f00;
18115 newval
|= (value
& 0xf000) << 4;
18116 newval
|= (value
& 0x0800) << 15;
18117 newval
|= (value
& 0x0700) << 4;
18118 newval
|= (value
& 0x00ff);
18119 put_thumb32_insn (buf
, newval
);
18123 newval
= md_chars_to_number (buf
, 4);
18124 newval
&= 0xfff0f000;
18125 newval
|= value
& 0x0fff;
18126 newval
|= (value
& 0xf000) << 4;
18127 md_number_to_chars (buf
, newval
, 4);
18132 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18133 case BFD_RELOC_ARM_ALU_PC_G0
:
18134 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18135 case BFD_RELOC_ARM_ALU_PC_G1
:
18136 case BFD_RELOC_ARM_ALU_PC_G2
:
18137 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18138 case BFD_RELOC_ARM_ALU_SB_G0
:
18139 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18140 case BFD_RELOC_ARM_ALU_SB_G1
:
18141 case BFD_RELOC_ARM_ALU_SB_G2
:
18142 assert (!fixP
->fx_done
);
18143 if (!seg
->use_rela_p
)
18146 bfd_vma encoded_addend
;
18147 bfd_vma addend_abs
= abs (value
);
18149 /* Check that the absolute value of the addend can be
18150 expressed as an 8-bit constant plus a rotation. */
18151 encoded_addend
= encode_arm_immediate (addend_abs
);
18152 if (encoded_addend
== (unsigned int) FAIL
)
18153 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18154 _("the offset 0x%08lX is not representable"),
18157 /* Extract the instruction. */
18158 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18160 /* If the addend is positive, use an ADD instruction.
18161 Otherwise use a SUB. Take care not to destroy the S bit. */
18162 insn
&= 0xff1fffff;
18168 /* Place the encoded addend into the first 12 bits of the
18170 insn
&= 0xfffff000;
18171 insn
|= encoded_addend
;
18173 /* Update the instruction. */
18174 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18178 case BFD_RELOC_ARM_LDR_PC_G0
:
18179 case BFD_RELOC_ARM_LDR_PC_G1
:
18180 case BFD_RELOC_ARM_LDR_PC_G2
:
18181 case BFD_RELOC_ARM_LDR_SB_G0
:
18182 case BFD_RELOC_ARM_LDR_SB_G1
:
18183 case BFD_RELOC_ARM_LDR_SB_G2
:
18184 assert (!fixP
->fx_done
);
18185 if (!seg
->use_rela_p
)
18188 bfd_vma addend_abs
= abs (value
);
18190 /* Check that the absolute value of the addend can be
18191 encoded in 12 bits. */
18192 if (addend_abs
>= 0x1000)
18193 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18194 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18197 /* Extract the instruction. */
18198 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18200 /* If the addend is negative, clear bit 23 of the instruction.
18201 Otherwise set it. */
18203 insn
&= ~(1 << 23);
18207 /* Place the absolute value of the addend into the first 12 bits
18208 of the instruction. */
18209 insn
&= 0xfffff000;
18210 insn
|= addend_abs
;
18212 /* Update the instruction. */
18213 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18217 case BFD_RELOC_ARM_LDRS_PC_G0
:
18218 case BFD_RELOC_ARM_LDRS_PC_G1
:
18219 case BFD_RELOC_ARM_LDRS_PC_G2
:
18220 case BFD_RELOC_ARM_LDRS_SB_G0
:
18221 case BFD_RELOC_ARM_LDRS_SB_G1
:
18222 case BFD_RELOC_ARM_LDRS_SB_G2
:
18223 assert (!fixP
->fx_done
);
18224 if (!seg
->use_rela_p
)
18227 bfd_vma addend_abs
= abs (value
);
18229 /* Check that the absolute value of the addend can be
18230 encoded in 8 bits. */
18231 if (addend_abs
>= 0x100)
18232 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18233 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
18236 /* Extract the instruction. */
18237 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18239 /* If the addend is negative, clear bit 23 of the instruction.
18240 Otherwise set it. */
18242 insn
&= ~(1 << 23);
18246 /* Place the first four bits of the absolute value of the addend
18247 into the first 4 bits of the instruction, and the remaining
18248 four into bits 8 .. 11. */
18249 insn
&= 0xfffff0f0;
18250 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
18252 /* Update the instruction. */
18253 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18257 case BFD_RELOC_ARM_LDC_PC_G0
:
18258 case BFD_RELOC_ARM_LDC_PC_G1
:
18259 case BFD_RELOC_ARM_LDC_PC_G2
:
18260 case BFD_RELOC_ARM_LDC_SB_G0
:
18261 case BFD_RELOC_ARM_LDC_SB_G1
:
18262 case BFD_RELOC_ARM_LDC_SB_G2
:
18263 assert (!fixP
->fx_done
);
18264 if (!seg
->use_rela_p
)
18267 bfd_vma addend_abs
= abs (value
);
18269 /* Check that the absolute value of the addend is a multiple of
18270 four and, when divided by four, fits in 8 bits. */
18271 if (addend_abs
& 0x3)
18272 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18273 _("bad offset 0x%08lX (must be word-aligned)"),
18276 if ((addend_abs
>> 2) > 0xff)
18277 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18278 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
18281 /* Extract the instruction. */
18282 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18284 /* If the addend is negative, clear bit 23 of the instruction.
18285 Otherwise set it. */
18287 insn
&= ~(1 << 23);
18291 /* Place the addend (divided by four) into the first eight
18292 bits of the instruction. */
18293 insn
&= 0xfffffff0;
18294 insn
|= addend_abs
>> 2;
18296 /* Update the instruction. */
18297 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18301 case BFD_RELOC_UNUSED
:
18303 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18304 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
18308 /* Translate internal representation of relocation info to BFD target
18312 tc_gen_reloc (asection
*section
, fixS
*fixp
)
18315 bfd_reloc_code_real_type code
;
18317 reloc
= xmalloc (sizeof (arelent
));
18319 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
18320 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18321 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18323 if (fixp
->fx_pcrel
)
18325 if (section
->use_rela_p
)
18326 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
18328 fixp
->fx_offset
= reloc
->address
;
18330 reloc
->addend
= fixp
->fx_offset
;
18332 switch (fixp
->fx_r_type
)
18335 if (fixp
->fx_pcrel
)
18337 code
= BFD_RELOC_8_PCREL
;
18342 if (fixp
->fx_pcrel
)
18344 code
= BFD_RELOC_16_PCREL
;
18349 if (fixp
->fx_pcrel
)
18351 code
= BFD_RELOC_32_PCREL
;
18355 case BFD_RELOC_ARM_MOVW
:
18356 if (fixp
->fx_pcrel
)
18358 code
= BFD_RELOC_ARM_MOVW_PCREL
;
18362 case BFD_RELOC_ARM_MOVT
:
18363 if (fixp
->fx_pcrel
)
18365 code
= BFD_RELOC_ARM_MOVT_PCREL
;
18369 case BFD_RELOC_ARM_THUMB_MOVW
:
18370 if (fixp
->fx_pcrel
)
18372 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
18376 case BFD_RELOC_ARM_THUMB_MOVT
:
18377 if (fixp
->fx_pcrel
)
18379 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
18383 case BFD_RELOC_NONE
:
18384 case BFD_RELOC_ARM_PCREL_BRANCH
:
18385 case BFD_RELOC_ARM_PCREL_BLX
:
18386 case BFD_RELOC_RVA
:
18387 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
18388 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
18389 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
18390 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18391 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18392 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18393 case BFD_RELOC_THUMB_PCREL_BLX
:
18394 case BFD_RELOC_VTABLE_ENTRY
:
18395 case BFD_RELOC_VTABLE_INHERIT
:
18396 code
= fixp
->fx_r_type
;
18399 case BFD_RELOC_ARM_LITERAL
:
18400 case BFD_RELOC_ARM_HWLITERAL
:
18401 /* If this is called then the a literal has
18402 been referenced across a section boundary. */
18403 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18404 _("literal referenced across section boundary"));
18408 case BFD_RELOC_ARM_GOT32
:
18409 case BFD_RELOC_ARM_GOTOFF
:
18410 case BFD_RELOC_ARM_PLT32
:
18411 case BFD_RELOC_ARM_TARGET1
:
18412 case BFD_RELOC_ARM_ROSEGREL32
:
18413 case BFD_RELOC_ARM_SBREL32
:
18414 case BFD_RELOC_ARM_PREL31
:
18415 case BFD_RELOC_ARM_TARGET2
:
18416 case BFD_RELOC_ARM_TLS_LE32
:
18417 case BFD_RELOC_ARM_TLS_LDO32
:
18418 case BFD_RELOC_ARM_PCREL_CALL
:
18419 case BFD_RELOC_ARM_PCREL_JUMP
:
18420 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18421 case BFD_RELOC_ARM_ALU_PC_G0
:
18422 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18423 case BFD_RELOC_ARM_ALU_PC_G1
:
18424 case BFD_RELOC_ARM_ALU_PC_G2
:
18425 case BFD_RELOC_ARM_LDR_PC_G0
:
18426 case BFD_RELOC_ARM_LDR_PC_G1
:
18427 case BFD_RELOC_ARM_LDR_PC_G2
:
18428 case BFD_RELOC_ARM_LDRS_PC_G0
:
18429 case BFD_RELOC_ARM_LDRS_PC_G1
:
18430 case BFD_RELOC_ARM_LDRS_PC_G2
:
18431 case BFD_RELOC_ARM_LDC_PC_G0
:
18432 case BFD_RELOC_ARM_LDC_PC_G1
:
18433 case BFD_RELOC_ARM_LDC_PC_G2
:
18434 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18435 case BFD_RELOC_ARM_ALU_SB_G0
:
18436 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18437 case BFD_RELOC_ARM_ALU_SB_G1
:
18438 case BFD_RELOC_ARM_ALU_SB_G2
:
18439 case BFD_RELOC_ARM_LDR_SB_G0
:
18440 case BFD_RELOC_ARM_LDR_SB_G1
:
18441 case BFD_RELOC_ARM_LDR_SB_G2
:
18442 case BFD_RELOC_ARM_LDRS_SB_G0
:
18443 case BFD_RELOC_ARM_LDRS_SB_G1
:
18444 case BFD_RELOC_ARM_LDRS_SB_G2
:
18445 case BFD_RELOC_ARM_LDC_SB_G0
:
18446 case BFD_RELOC_ARM_LDC_SB_G1
:
18447 case BFD_RELOC_ARM_LDC_SB_G2
:
18448 code
= fixp
->fx_r_type
;
18451 case BFD_RELOC_ARM_TLS_GD32
:
18452 case BFD_RELOC_ARM_TLS_IE32
:
18453 case BFD_RELOC_ARM_TLS_LDM32
:
18454 /* BFD will include the symbol's address in the addend.
18455 But we don't want that, so subtract it out again here. */
18456 if (!S_IS_COMMON (fixp
->fx_addsy
))
18457 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
18458 code
= fixp
->fx_r_type
;
18462 case BFD_RELOC_ARM_IMMEDIATE
:
18463 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18464 _("internal relocation (type: IMMEDIATE) not fixed up"));
18467 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
18468 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18469 _("ADRL used for a symbol not defined in the same file"));
18472 case BFD_RELOC_ARM_OFFSET_IMM
:
18473 if (section
->use_rela_p
)
18475 code
= fixp
->fx_r_type
;
18479 if (fixp
->fx_addsy
!= NULL
18480 && !S_IS_DEFINED (fixp
->fx_addsy
)
18481 && S_IS_LOCAL (fixp
->fx_addsy
))
18483 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18484 _("undefined local label `%s'"),
18485 S_GET_NAME (fixp
->fx_addsy
));
18489 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18490 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
18497 switch (fixp
->fx_r_type
)
18499 case BFD_RELOC_NONE
: type
= "NONE"; break;
18500 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
18501 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
18502 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
18503 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
18504 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
18505 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
18506 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
18507 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
18508 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
18509 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
18510 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
18511 default: type
= _("<unknown>"); break;
18513 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18514 _("cannot represent %s relocation in this object file format"),
18521 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
18523 && fixp
->fx_addsy
== GOT_symbol
)
18525 code
= BFD_RELOC_ARM_GOTPC
;
18526 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
18530 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18532 if (reloc
->howto
== NULL
)
18534 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18535 _("cannot represent %s relocation in this object file format"),
18536 bfd_get_reloc_code_name (code
));
18540 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
18541 vtable entry to be used in the relocation's section offset. */
18542 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18543 reloc
->address
= fixp
->fx_offset
;
18548 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
18551 cons_fix_new_arm (fragS
* frag
,
18556 bfd_reloc_code_real_type type
;
18560 FIXME: @@ Should look at CPU word size. */
18564 type
= BFD_RELOC_8
;
18567 type
= BFD_RELOC_16
;
18571 type
= BFD_RELOC_32
;
18574 type
= BFD_RELOC_64
;
18578 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
18581 #if defined OBJ_COFF || defined OBJ_ELF
18583 arm_validate_fix (fixS
* fixP
)
18585 /* If the destination of the branch is a defined symbol which does not have
18586 the THUMB_FUNC attribute, then we must be calling a function which has
18587 the (interfacearm) attribute. We look for the Thumb entry point to that
18588 function and change the branch to refer to that function instead. */
18589 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
18590 && fixP
->fx_addsy
!= NULL
18591 && S_IS_DEFINED (fixP
->fx_addsy
)
18592 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
18594 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
18600 arm_force_relocation (struct fix
* fixp
)
18602 #if defined (OBJ_COFF) && defined (TE_PE)
18603 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
18607 /* Resolve these relocations even if the symbol is extern or weak. */
18608 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
18609 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
18610 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
18611 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
18612 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
18613 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
18616 /* Always leave these relocations for the linker. */
18617 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
18618 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
18619 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
18622 return generic_force_reloc (fixp
);
18627 arm_fix_adjustable (fixS
* fixP
)
18629 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
18630 local labels from being added to the output symbol table when they
18631 are used with the ADRL pseudo op. The ADRL relocation should always
18632 be resolved before the binbary is emitted, so it is safe to say that
18633 it is adjustable. */
18634 if (fixP
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
)
18637 /* This is a hack for the gas/all/redef2.s test. This test causes symbols
18638 to be cloned, and without this test relocs would still be generated
18639 against the original, pre-cloned symbol. Such symbols would not appear
18640 in the symbol table however, and so a valid reloc could not be
18641 generated. So check to see if the fixup is against a symbol which has
18642 been removed from the symbol chain, and if it is, then allow it to be
18643 adjusted into a reloc against a section symbol. */
18644 if (fixP
->fx_addsy
!= NULL
18645 && ! S_IS_LOCAL (fixP
->fx_addsy
)
18646 && symbol_next (fixP
->fx_addsy
) == NULL
18647 && symbol_next (fixP
->fx_addsy
) == symbol_previous (fixP
->fx_addsy
))
18655 /* Relocations against function names must be left unadjusted,
18656 so that the linker can use this information to generate interworking
18657 stubs. The MIPS version of this function
18658 also prevents relocations that are mips-16 specific, but I do not
18659 know why it does this.
18662 There is one other problem that ought to be addressed here, but
18663 which currently is not: Taking the address of a label (rather
18664 than a function) and then later jumping to that address. Such
18665 addresses also ought to have their bottom bit set (assuming that
18666 they reside in Thumb code), but at the moment they will not. */
18669 arm_fix_adjustable (fixS
* fixP
)
18671 if (fixP
->fx_addsy
== NULL
)
18674 /* Preserve relocations against symbols with function type. */
18675 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
18678 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
18679 && fixP
->fx_subsy
== NULL
)
18682 /* We need the symbol name for the VTABLE entries. */
18683 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
18684 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18687 /* Don't allow symbols to be discarded on GOT related relocs. */
18688 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
18689 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
18690 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
18691 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
18692 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
18693 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
18694 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
18695 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
18696 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
18699 /* Similarly for group relocations. */
18700 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
18701 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
18702 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
18709 elf32_arm_target_format (void)
18712 return (target_big_endian
18713 ? "elf32-bigarm-symbian"
18714 : "elf32-littlearm-symbian");
18715 #elif defined (TE_VXWORKS)
18716 return (target_big_endian
18717 ? "elf32-bigarm-vxworks"
18718 : "elf32-littlearm-vxworks");
18720 if (target_big_endian
)
18721 return "elf32-bigarm";
18723 return "elf32-littlearm";
18728 armelf_frob_symbol (symbolS
* symp
,
18731 elf_frob_symbol (symp
, puntp
);
18735 /* MD interface: Finalization. */
18737 /* A good place to do this, although this was probably not intended
18738 for this kind of use. We need to dump the literal pool before
18739 references are made to a null symbol pointer. */
18744 literal_pool
* pool
;
18746 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
18748 /* Put it at the end of the relevent section. */
18749 subseg_set (pool
->section
, pool
->sub_section
);
18751 arm_elf_change_section ();
18757 /* Adjust the symbol table. This marks Thumb symbols as distinct from
18761 arm_adjust_symtab (void)
18766 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
18768 if (ARM_IS_THUMB (sym
))
18770 if (THUMB_IS_FUNC (sym
))
18772 /* Mark the symbol as a Thumb function. */
18773 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
18774 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
18775 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
18777 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
18778 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
18780 as_bad (_("%s: unexpected function type: %d"),
18781 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
18783 else switch (S_GET_STORAGE_CLASS (sym
))
18786 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
18789 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
18792 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
18800 if (ARM_IS_INTERWORK (sym
))
18801 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
18808 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
18810 if (ARM_IS_THUMB (sym
))
18812 elf_symbol_type
* elf_sym
;
18814 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
18815 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
18817 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
18818 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
18820 /* If it's a .thumb_func, declare it as so,
18821 otherwise tag label as .code 16. */
18822 if (THUMB_IS_FUNC (sym
))
18823 elf_sym
->internal_elf_sym
.st_info
=
18824 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
18826 elf_sym
->internal_elf_sym
.st_info
=
18827 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
18834 /* MD interface: Initialization. */
18837 set_constant_flonums (void)
18841 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
18842 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
18852 if ( (arm_ops_hsh
= hash_new ()) == NULL
18853 || (arm_cond_hsh
= hash_new ()) == NULL
18854 || (arm_shift_hsh
= hash_new ()) == NULL
18855 || (arm_psr_hsh
= hash_new ()) == NULL
18856 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
18857 || (arm_reg_hsh
= hash_new ()) == NULL
18858 || (arm_reloc_hsh
= hash_new ()) == NULL
18859 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
18860 as_fatal (_("virtual memory exhausted"));
18862 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
18863 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
18864 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
18865 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
18866 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
18867 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (PTR
) (shift_names
+ i
));
18868 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
18869 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
18870 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
18871 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (PTR
) (v7m_psrs
+ i
));
18872 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
18873 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (PTR
) (reg_names
+ i
));
18875 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
18877 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
18878 (PTR
) (barrier_opt_names
+ i
));
18880 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
18881 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (PTR
) (reloc_names
+ i
));
18884 set_constant_flonums ();
18886 /* Set the cpu variant based on the command-line options. We prefer
18887 -mcpu= over -march= if both are set (as for GCC); and we prefer
18888 -mfpu= over any other way of setting the floating point unit.
18889 Use of legacy options with new options are faulted. */
18892 if (mcpu_cpu_opt
|| march_cpu_opt
)
18893 as_bad (_("use of old and new-style options to set CPU type"));
18895 mcpu_cpu_opt
= legacy_cpu
;
18897 else if (!mcpu_cpu_opt
)
18898 mcpu_cpu_opt
= march_cpu_opt
;
18903 as_bad (_("use of old and new-style options to set FPU type"));
18905 mfpu_opt
= legacy_fpu
;
18907 else if (!mfpu_opt
)
18909 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
18910 /* Some environments specify a default FPU. If they don't, infer it
18911 from the processor. */
18913 mfpu_opt
= mcpu_fpu_opt
;
18915 mfpu_opt
= march_fpu_opt
;
18917 mfpu_opt
= &fpu_default
;
18924 mfpu_opt
= &fpu_default
;
18925 else if (ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
18926 mfpu_opt
= &fpu_arch_vfp_v2
;
18928 mfpu_opt
= &fpu_arch_fpa
;
18934 mcpu_cpu_opt
= &cpu_default
;
18935 selected_cpu
= cpu_default
;
18939 selected_cpu
= *mcpu_cpu_opt
;
18941 mcpu_cpu_opt
= &arm_arch_any
;
18944 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
18946 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
18948 #if defined OBJ_COFF || defined OBJ_ELF
18950 unsigned int flags
= 0;
18952 #if defined OBJ_ELF
18953 flags
= meabi_flags
;
18955 switch (meabi_flags
)
18957 case EF_ARM_EABI_UNKNOWN
:
18959 /* Set the flags in the private structure. */
18960 if (uses_apcs_26
) flags
|= F_APCS26
;
18961 if (support_interwork
) flags
|= F_INTERWORK
;
18962 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
18963 if (pic_code
) flags
|= F_PIC
;
18964 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
18965 flags
|= F_SOFT_FLOAT
;
18967 switch (mfloat_abi_opt
)
18969 case ARM_FLOAT_ABI_SOFT
:
18970 case ARM_FLOAT_ABI_SOFTFP
:
18971 flags
|= F_SOFT_FLOAT
;
18974 case ARM_FLOAT_ABI_HARD
:
18975 if (flags
& F_SOFT_FLOAT
)
18976 as_bad (_("hard-float conflicts with specified fpu"));
18980 /* Using pure-endian doubles (even if soft-float). */
18981 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
18982 flags
|= F_VFP_FLOAT
;
18984 #if defined OBJ_ELF
18985 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
18986 flags
|= EF_ARM_MAVERICK_FLOAT
;
18989 case EF_ARM_EABI_VER4
:
18990 case EF_ARM_EABI_VER5
:
18991 /* No additional flags to set. */
18998 bfd_set_private_flags (stdoutput
, flags
);
19000 /* We have run out flags in the COFF header to encode the
19001 status of ATPCS support, so instead we create a dummy,
19002 empty, debug section called .arm.atpcs. */
19007 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
19011 bfd_set_section_flags
19012 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
19013 bfd_set_section_size (stdoutput
, sec
, 0);
19014 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
19020 /* Record the CPU type as well. */
19021 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
19022 mach
= bfd_mach_arm_iWMMXt
;
19023 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
19024 mach
= bfd_mach_arm_XScale
;
19025 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
19026 mach
= bfd_mach_arm_ep9312
;
19027 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
19028 mach
= bfd_mach_arm_5TE
;
19029 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
19031 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19032 mach
= bfd_mach_arm_5T
;
19034 mach
= bfd_mach_arm_5
;
19036 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
19038 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19039 mach
= bfd_mach_arm_4T
;
19041 mach
= bfd_mach_arm_4
;
19043 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
19044 mach
= bfd_mach_arm_3M
;
19045 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
19046 mach
= bfd_mach_arm_3
;
19047 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
19048 mach
= bfd_mach_arm_2a
;
19049 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
19050 mach
= bfd_mach_arm_2
;
19052 mach
= bfd_mach_arm_unknown
;
19054 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
19057 /* Command line processing. */
19060 Invocation line includes a switch not recognized by the base assembler.
19061 See if it's a processor-specific option.
19063 This routine is somewhat complicated by the need for backwards
19064 compatibility (since older releases of gcc can't be changed).
19065 The new options try to make the interface as compatible as
19068 New options (supported) are:
19070 -mcpu=<cpu name> Assemble for selected processor
19071 -march=<architecture name> Assemble for selected architecture
19072 -mfpu=<fpu architecture> Assemble for selected FPU.
19073 -EB/-mbig-endian Big-endian
19074 -EL/-mlittle-endian Little-endian
19075 -k Generate PIC code
19076 -mthumb Start in Thumb mode
19077 -mthumb-interwork Code supports ARM/Thumb interworking
19079 For now we will also provide support for:
19081 -mapcs-32 32-bit Program counter
19082 -mapcs-26 26-bit Program counter
19083 -macps-float Floats passed in FP registers
19084 -mapcs-reentrant Reentrant code
19086 (sometime these will probably be replaced with -mapcs=<list of options>
19087 and -matpcs=<list of options>)
19089 The remaining options are only supported for back-wards compatibility.
19090 Cpu variants, the arm part is optional:
19091 -m[arm]1 Currently not supported.
19092 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
19093 -m[arm]3 Arm 3 processor
19094 -m[arm]6[xx], Arm 6 processors
19095 -m[arm]7[xx][t][[d]m] Arm 7 processors
19096 -m[arm]8[10] Arm 8 processors
19097 -m[arm]9[20][tdmi] Arm 9 processors
19098 -mstrongarm[110[0]] StrongARM processors
19099 -mxscale XScale processors
19100 -m[arm]v[2345[t[e]]] Arm architectures
19101 -mall All (except the ARM1)
19103 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
19104 -mfpe-old (No float load/store multiples)
19105 -mvfpxd VFP Single precision
19107 -mno-fpu Disable all floating point instructions
19109 The following CPU names are recognized:
19110 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19111 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19112 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19113 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19114 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19115 arm10t arm10e, arm1020t, arm1020e, arm10200e,
19116 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
19120 const char * md_shortopts
= "m:k";
19122 #ifdef ARM_BI_ENDIAN
19123 #define OPTION_EB (OPTION_MD_BASE + 0)
19124 #define OPTION_EL (OPTION_MD_BASE + 1)
19126 #if TARGET_BYTES_BIG_ENDIAN
19127 #define OPTION_EB (OPTION_MD_BASE + 0)
19129 #define OPTION_EL (OPTION_MD_BASE + 1)
19133 struct option md_longopts
[] =
19136 {"EB", no_argument
, NULL
, OPTION_EB
},
19139 {"EL", no_argument
, NULL
, OPTION_EL
},
19141 {NULL
, no_argument
, NULL
, 0}
19144 size_t md_longopts_size
= sizeof (md_longopts
);
19146 struct arm_option_table
19148 char *option
; /* Option name to match. */
19149 char *help
; /* Help information. */
19150 int *var
; /* Variable to change. */
19151 int value
; /* What to change it to. */
19152 char *deprecated
; /* If non-null, print this message. */
19155 struct arm_option_table arm_opts
[] =
19157 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
19158 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
19159 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19160 &support_interwork
, 1, NULL
},
19161 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
19162 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
19163 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
19165 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
19166 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
19167 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
19168 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
19171 /* These are recognized by the assembler, but have no affect on code. */
19172 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
19173 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
19174 {NULL
, NULL
, NULL
, 0, NULL
}
19177 struct arm_legacy_option_table
19179 char *option
; /* Option name to match. */
19180 const arm_feature_set
**var
; /* Variable to change. */
19181 const arm_feature_set value
; /* What to change it to. */
19182 char *deprecated
; /* If non-null, print this message. */
19185 const struct arm_legacy_option_table arm_legacy_opts
[] =
19187 /* DON'T add any new processors to this list -- we want the whole list
19188 to go away... Add them to the processors table instead. */
19189 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19190 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19191 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19192 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19193 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19194 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19195 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19196 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19197 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19198 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19199 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19200 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19201 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19202 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19203 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19204 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19205 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19206 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19207 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19208 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19209 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19210 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19211 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19212 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19213 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19214 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19215 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19216 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19217 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19218 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19219 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19220 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19221 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19222 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19223 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19224 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19225 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19226 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19227 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19228 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19229 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19230 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19231 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19232 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19233 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19234 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19235 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19236 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19237 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19238 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19239 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19240 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19241 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19242 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19243 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19244 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19245 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19246 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19247 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19248 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19249 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19250 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19251 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19252 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19253 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19254 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19255 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19256 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19257 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
19258 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
19259 N_("use -mcpu=strongarm110")},
19260 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
19261 N_("use -mcpu=strongarm1100")},
19262 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
19263 N_("use -mcpu=strongarm1110")},
19264 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
19265 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
19266 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
19268 /* Architecture variants -- don't add any more to this list either. */
19269 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19270 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19271 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19272 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19273 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19274 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19275 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19276 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19277 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19278 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19279 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19280 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19281 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19282 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19283 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19284 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19285 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19286 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19288 /* Floating point variants -- don't add any more to this list either. */
19289 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
19290 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
19291 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
19292 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
19293 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
19295 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
19298 struct arm_cpu_option_table
19301 const arm_feature_set value
;
19302 /* For some CPUs we assume an FPU unless the user explicitly sets
19304 const arm_feature_set default_fpu
;
19305 /* The canonical name of the CPU, or NULL to use NAME converted to upper
19307 const char *canonical_name
;
19310 /* This list should, at a minimum, contain all the cpu names
19311 recognized by GCC. */
19312 static const struct arm_cpu_option_table arm_cpus
[] =
19314 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
19315 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
19316 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
19317 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19318 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19319 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19320 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19321 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19322 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19323 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19324 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19325 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19326 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19327 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19328 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19329 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19330 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19331 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19332 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19333 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19334 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19335 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19336 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19337 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19338 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19339 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19340 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19341 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19342 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19343 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19344 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19345 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19346 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19347 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19348 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19349 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19350 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19351 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19352 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19353 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
19354 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19355 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19356 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19357 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19358 /* For V5 or later processors we default to using VFP; but the user
19359 should really set the FPU type explicitly. */
19360 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19361 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19362 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
19363 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
19364 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
19365 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19366 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
19367 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19368 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19369 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
19370 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19371 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19372 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19373 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19374 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19375 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
19376 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19377 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19378 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19379 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
19380 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
19381 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
19382 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
19383 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
19384 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
19385 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
19386 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
19387 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
19388 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
19389 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
19390 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
19391 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
19392 | FPU_NEON_EXT_V1
),
19394 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
19395 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
19396 /* ??? XSCALE is really an architecture. */
19397 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
19398 /* ??? iwmmxt is not a processor. */
19399 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
19400 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
19402 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
19403 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
19406 struct arm_arch_option_table
19409 const arm_feature_set value
;
19410 const arm_feature_set default_fpu
;
19413 /* This list should, at a minimum, contain all the architecture names
19414 recognized by GCC. */
19415 static const struct arm_arch_option_table arm_archs
[] =
19417 {"all", ARM_ANY
, FPU_ARCH_FPA
},
19418 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
19419 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
19420 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
19421 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
19422 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
19423 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
19424 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
19425 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
19426 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
19427 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
19428 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
19429 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
19430 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
19431 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
19432 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
19433 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
19434 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
19435 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
19436 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
19437 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
19438 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
19439 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
19440 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
19441 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
19442 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
19443 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
19444 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
19445 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
19446 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
19447 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
19448 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
19449 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
19452 /* ISA extensions in the co-processor space. */
19453 struct arm_option_cpu_value_table
19456 const arm_feature_set value
;
19459 static const struct arm_option_cpu_value_table arm_extensions
[] =
19461 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
19462 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
19463 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
19464 {NULL
, ARM_ARCH_NONE
}
19467 /* This list should, at a minimum, contain all the fpu names
19468 recognized by GCC. */
19469 static const struct arm_option_cpu_value_table arm_fpus
[] =
19471 {"softfpa", FPU_NONE
},
19472 {"fpe", FPU_ARCH_FPE
},
19473 {"fpe2", FPU_ARCH_FPE
},
19474 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
19475 {"fpa", FPU_ARCH_FPA
},
19476 {"fpa10", FPU_ARCH_FPA
},
19477 {"fpa11", FPU_ARCH_FPA
},
19478 {"arm7500fe", FPU_ARCH_FPA
},
19479 {"softvfp", FPU_ARCH_VFP
},
19480 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
19481 {"vfp", FPU_ARCH_VFP_V2
},
19482 {"vfp9", FPU_ARCH_VFP_V2
},
19483 {"vfp3", FPU_ARCH_VFP_V3
},
19484 {"vfp10", FPU_ARCH_VFP_V2
},
19485 {"vfp10-r0", FPU_ARCH_VFP_V1
},
19486 {"vfpxd", FPU_ARCH_VFP_V1xD
},
19487 {"arm1020t", FPU_ARCH_VFP_V1
},
19488 {"arm1020e", FPU_ARCH_VFP_V2
},
19489 {"arm1136jfs", FPU_ARCH_VFP_V2
},
19490 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
19491 {"maverick", FPU_ARCH_MAVERICK
},
19492 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
19493 {NULL
, ARM_ARCH_NONE
}
19496 struct arm_option_value_table
19502 static const struct arm_option_value_table arm_float_abis
[] =
19504 {"hard", ARM_FLOAT_ABI_HARD
},
19505 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
19506 {"soft", ARM_FLOAT_ABI_SOFT
},
19511 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
19512 static const struct arm_option_value_table arm_eabis
[] =
19514 {"gnu", EF_ARM_EABI_UNKNOWN
},
19515 {"4", EF_ARM_EABI_VER4
},
19516 {"5", EF_ARM_EABI_VER5
},
19521 struct arm_long_option_table
19523 char * option
; /* Substring to match. */
19524 char * help
; /* Help information. */
19525 int (* func
) (char * subopt
); /* Function to decode sub-option. */
19526 char * deprecated
; /* If non-null, print this message. */
19530 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
19532 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
19534 /* Copy the feature set, so that we can modify it. */
19535 *ext_set
= **opt_p
;
19538 while (str
!= NULL
&& *str
!= 0)
19540 const struct arm_option_cpu_value_table
* opt
;
19546 as_bad (_("invalid architectural extension"));
19551 ext
= strchr (str
, '+');
19554 optlen
= ext
- str
;
19556 optlen
= strlen (str
);
19560 as_bad (_("missing architectural extension"));
19564 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
19565 if (strncmp (opt
->name
, str
, optlen
) == 0)
19567 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
19571 if (opt
->name
== NULL
)
19573 as_bad (_("unknown architectural extnsion `%s'"), str
);
19584 arm_parse_cpu (char * str
)
19586 const struct arm_cpu_option_table
* opt
;
19587 char * ext
= strchr (str
, '+');
19591 optlen
= ext
- str
;
19593 optlen
= strlen (str
);
19597 as_bad (_("missing cpu name `%s'"), str
);
19601 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
19602 if (strncmp (opt
->name
, str
, optlen
) == 0)
19604 mcpu_cpu_opt
= &opt
->value
;
19605 mcpu_fpu_opt
= &opt
->default_fpu
;
19606 if (opt
->canonical_name
)
19607 strcpy(selected_cpu_name
, opt
->canonical_name
);
19611 for (i
= 0; i
< optlen
; i
++)
19612 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
19613 selected_cpu_name
[i
] = 0;
19617 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
19622 as_bad (_("unknown cpu `%s'"), str
);
19627 arm_parse_arch (char * str
)
19629 const struct arm_arch_option_table
*opt
;
19630 char *ext
= strchr (str
, '+');
19634 optlen
= ext
- str
;
19636 optlen
= strlen (str
);
19640 as_bad (_("missing architecture name `%s'"), str
);
19644 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
19645 if (streq (opt
->name
, str
))
19647 march_cpu_opt
= &opt
->value
;
19648 march_fpu_opt
= &opt
->default_fpu
;
19649 strcpy(selected_cpu_name
, opt
->name
);
19652 return arm_parse_extension (ext
, &march_cpu_opt
);
19657 as_bad (_("unknown architecture `%s'\n"), str
);
19662 arm_parse_fpu (char * str
)
19664 const struct arm_option_cpu_value_table
* opt
;
19666 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
19667 if (streq (opt
->name
, str
))
19669 mfpu_opt
= &opt
->value
;
19673 as_bad (_("unknown floating point format `%s'\n"), str
);
19678 arm_parse_float_abi (char * str
)
19680 const struct arm_option_value_table
* opt
;
19682 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
19683 if (streq (opt
->name
, str
))
19685 mfloat_abi_opt
= opt
->value
;
19689 as_bad (_("unknown floating point abi `%s'\n"), str
);
19695 arm_parse_eabi (char * str
)
19697 const struct arm_option_value_table
*opt
;
19699 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
19700 if (streq (opt
->name
, str
))
19702 meabi_flags
= opt
->value
;
19705 as_bad (_("unknown EABI `%s'\n"), str
);
19710 struct arm_long_option_table arm_long_opts
[] =
19712 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
19713 arm_parse_cpu
, NULL
},
19714 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
19715 arm_parse_arch
, NULL
},
19716 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
19717 arm_parse_fpu
, NULL
},
19718 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
19719 arm_parse_float_abi
, NULL
},
19721 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
19722 arm_parse_eabi
, NULL
},
19724 {NULL
, NULL
, 0, NULL
}
19728 md_parse_option (int c
, char * arg
)
19730 struct arm_option_table
*opt
;
19731 const struct arm_legacy_option_table
*fopt
;
19732 struct arm_long_option_table
*lopt
;
19738 target_big_endian
= 1;
19744 target_big_endian
= 0;
19749 /* Listing option. Just ignore these, we don't support additional
19754 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
19756 if (c
== opt
->option
[0]
19757 && ((arg
== NULL
&& opt
->option
[1] == 0)
19758 || streq (arg
, opt
->option
+ 1)))
19760 #if WARN_DEPRECATED
19761 /* If the option is deprecated, tell the user. */
19762 if (opt
->deprecated
!= NULL
)
19763 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
19764 arg
? arg
: "", _(opt
->deprecated
));
19767 if (opt
->var
!= NULL
)
19768 *opt
->var
= opt
->value
;
19774 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
19776 if (c
== fopt
->option
[0]
19777 && ((arg
== NULL
&& fopt
->option
[1] == 0)
19778 || streq (arg
, fopt
->option
+ 1)))
19780 #if WARN_DEPRECATED
19781 /* If the option is deprecated, tell the user. */
19782 if (fopt
->deprecated
!= NULL
)
19783 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
19784 arg
? arg
: "", _(fopt
->deprecated
));
19787 if (fopt
->var
!= NULL
)
19788 *fopt
->var
= &fopt
->value
;
19794 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
19796 /* These options are expected to have an argument. */
19797 if (c
== lopt
->option
[0]
19799 && strncmp (arg
, lopt
->option
+ 1,
19800 strlen (lopt
->option
+ 1)) == 0)
19802 #if WARN_DEPRECATED
19803 /* If the option is deprecated, tell the user. */
19804 if (lopt
->deprecated
!= NULL
)
19805 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
19806 _(lopt
->deprecated
));
19809 /* Call the sup-option parser. */
19810 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
19821 md_show_usage (FILE * fp
)
19823 struct arm_option_table
*opt
;
19824 struct arm_long_option_table
*lopt
;
19826 fprintf (fp
, _(" ARM-specific assembler options:\n"));
19828 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
19829 if (opt
->help
!= NULL
)
19830 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
19832 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
19833 if (lopt
->help
!= NULL
)
19834 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
19838 -EB assemble code for a big-endian cpu\n"));
19843 -EL assemble code for a little-endian cpu\n"));
19852 arm_feature_set flags
;
19853 } cpu_arch_ver_table
;
19855 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
19856 least features first. */
19857 static const cpu_arch_ver_table cpu_arch_ver
[] =
19862 {4, ARM_ARCH_V5TE
},
19863 {5, ARM_ARCH_V5TEJ
},
19867 {9, ARM_ARCH_V6T2
},
19868 {10, ARM_ARCH_V7A
},
19869 {10, ARM_ARCH_V7R
},
19870 {10, ARM_ARCH_V7M
},
19874 /* Set the public EABI object attributes. */
19876 aeabi_set_public_attributes (void)
19879 arm_feature_set flags
;
19880 arm_feature_set tmp
;
19881 const cpu_arch_ver_table
*p
;
19883 /* Choose the architecture based on the capabilities of the requested cpu
19884 (if any) and/or the instructions actually used. */
19885 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
19886 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
19887 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
19891 for (p
= cpu_arch_ver
; p
->val
; p
++)
19893 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
19896 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
19900 /* Tag_CPU_name. */
19901 if (selected_cpu_name
[0])
19905 p
= selected_cpu_name
;
19906 if (strncmp(p
, "armv", 4) == 0)
19911 for (i
= 0; p
[i
]; i
++)
19912 p
[i
] = TOUPPER (p
[i
]);
19914 elf32_arm_add_eabi_attr_string (stdoutput
, 5, p
);
19916 /* Tag_CPU_arch. */
19917 elf32_arm_add_eabi_attr_int (stdoutput
, 6, arch
);
19918 /* Tag_CPU_arch_profile. */
19919 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
19920 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'A');
19921 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
19922 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'R');
19923 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
))
19924 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'M');
19925 /* Tag_ARM_ISA_use. */
19926 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_full
))
19927 elf32_arm_add_eabi_attr_int (stdoutput
, 8, 1);
19928 /* Tag_THUMB_ISA_use. */
19929 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_full
))
19930 elf32_arm_add_eabi_attr_int (stdoutput
, 9,
19931 ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
) ? 2 : 1);
19932 /* Tag_VFP_arch. */
19933 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v3
)
19934 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v3
))
19935 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 3);
19936 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v2
)
19937 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v2
))
19938 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 2);
19939 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1
)
19940 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1
)
19941 || ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1xd
)
19942 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1xd
))
19943 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 1);
19944 /* Tag_WMMX_arch. */
19945 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_cext_iwmmxt
)
19946 || ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_cext_iwmmxt
))
19947 elf32_arm_add_eabi_attr_int (stdoutput
, 11, 1);
19948 /* Tag_NEON_arch. */
19949 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_neon_ext_v1
)
19950 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_neon_ext_v1
))
19951 elf32_arm_add_eabi_attr_int (stdoutput
, 12, 1);
19954 /* Add the .ARM.attributes section. */
19963 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
19966 aeabi_set_public_attributes ();
19967 size
= elf32_arm_eabi_attr_size (stdoutput
);
19968 s
= subseg_new (".ARM.attributes", 0);
19969 bfd_set_section_flags (stdoutput
, s
, SEC_READONLY
| SEC_DATA
);
19970 addr
= frag_now_fix ();
19971 p
= frag_more (size
);
19972 elf32_arm_set_eabi_attr_contents (stdoutput
, (bfd_byte
*)p
, size
);
19974 #endif /* OBJ_ELF */
19977 /* Parse a .cpu directive. */
19980 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
19982 const struct arm_cpu_option_table
*opt
;
19986 name
= input_line_pointer
;
19987 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
19988 input_line_pointer
++;
19989 saved_char
= *input_line_pointer
;
19990 *input_line_pointer
= 0;
19992 /* Skip the first "all" entry. */
19993 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
19994 if (streq (opt
->name
, name
))
19996 mcpu_cpu_opt
= &opt
->value
;
19997 selected_cpu
= opt
->value
;
19998 if (opt
->canonical_name
)
19999 strcpy(selected_cpu_name
, opt
->canonical_name
);
20003 for (i
= 0; opt
->name
[i
]; i
++)
20004 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20005 selected_cpu_name
[i
] = 0;
20007 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20008 *input_line_pointer
= saved_char
;
20009 demand_empty_rest_of_line ();
20012 as_bad (_("unknown cpu `%s'"), name
);
20013 *input_line_pointer
= saved_char
;
20014 ignore_rest_of_line ();
20018 /* Parse a .arch directive. */
20021 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
20023 const struct arm_arch_option_table
*opt
;
20027 name
= input_line_pointer
;
20028 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20029 input_line_pointer
++;
20030 saved_char
= *input_line_pointer
;
20031 *input_line_pointer
= 0;
20033 /* Skip the first "all" entry. */
20034 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20035 if (streq (opt
->name
, name
))
20037 mcpu_cpu_opt
= &opt
->value
;
20038 selected_cpu
= opt
->value
;
20039 strcpy(selected_cpu_name
, opt
->name
);
20040 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20041 *input_line_pointer
= saved_char
;
20042 demand_empty_rest_of_line ();
20046 as_bad (_("unknown architecture `%s'\n"), name
);
20047 *input_line_pointer
= saved_char
;
20048 ignore_rest_of_line ();
20052 /* Parse a .fpu directive. */
20055 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
20057 const struct arm_option_cpu_value_table
*opt
;
20061 name
= input_line_pointer
;
20062 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20063 input_line_pointer
++;
20064 saved_char
= *input_line_pointer
;
20065 *input_line_pointer
= 0;
20067 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20068 if (streq (opt
->name
, name
))
20070 mfpu_opt
= &opt
->value
;
20071 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20072 *input_line_pointer
= saved_char
;
20073 demand_empty_rest_of_line ();
20077 as_bad (_("unknown floating point format `%s'\n"), name
);
20078 *input_line_pointer
= saved_char
;
20079 ignore_rest_of_line ();